date:20181017

Re: [PATCH 2/7] drm: add syncobj timeline support v8

2018-10-17 Thread zhoucm1




On 2018年10月17日 18:24, Daniel Vetter wrote:

On Wed, Oct 17, 2018 at 11:29 AM Koenig, Christian
 wrote:

Am 17.10.18 um 11:17 schrieb zhoucm1:

[SNIP]

   +struct drm_syncobj_signal_pt {
+struct dma_fence_array *base;

Out of curiosity, why the pointer and not embedding? base is kinda
misleading for a pointer.

Yeah, Christian doesn't like signal_pt lifecycle same as fence, so
it's a pointer.
If you don't like 'base' name, I can change it.

Well I never said that you can't embed the fence array into the signal_pt.

You just need to make sure that we don't affect the drm_syncobj
lilecycle as well, e.g. that we don't also need to keep that around.

I don't see a problem with that, as long as drm_syncobj keeps a
reference to the fence while it's on the timeline list. Which it
already does. And embedding would avoid that 2nd separate allocation,
aside from making base less confusing.
That's indeed my initial implementation for signal_pt/wait_pt with fence 
based, but after long and many discussions, we get current solution, as 
you see, the version is up to v8 :).


For here  why the pointer and not embedding?
Two reasons:
1. their lifecycles are not same.
2. It is a fence array usage, which always needs separate allocation, 
seems which is mandatory.

So it is a pointer.

But the name is historical from initial, and indeed be kinda misleading 
for a pointer, I will change it to fence_array instead in coming v9.


Thanks,
David Zhou


-Daniel


___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 2/2] drm/amdgpu: replace get_user_pages with HMM address mirror helpers

2018-10-17 Thread Yang, Philip

On 2018-10-17 04:15 AM, Christian König wrote:
> Am 17.10.18 um 04:56 schrieb Yang, Philip:
>> Use HMM helper function hmm_vma_fault() to get physical pages backing
>> userptr and start CPU page table update track of those pages. Then use
>> hmm_vma_range_done() to check if those pages are updated before
>> amdgpu_cs_submit for gfx or before user queues are resumed for kfd.
>>
>> If userptr pages are updated, for gfx, amdgpu_cs_ioctl will restart
>> from scratch, for kfd, restore worker is rescheduled to retry.
>>
>> To avoid circular lock dependency, the locking order is:
>> mmap_sem -> amdgpu_mn_lock(p->mn) -> bo::reserve
>> mmap_sem -> bo::reserve
>
> I'm not sure that this will work, we used to have some dependencies on 
> bo::reserve -> mmap_sem.
>
> See the following patch as well:
>
> commit 2f568dbd6b944c2e8c0c54b53c2211c23995e6a4
> Author: Christian König 
> Date:   Tue Feb 23 12:36:59 2016 +0100
>
>     drm/amdgpu: move get_user_pages out of amdgpu_ttm_tt_pin_userptr v6
>
>     That avoids lock inversion between the BO reservation lock
>     and the anon_vma lock.
>
> A whole bunch of more problems below.
>
Thanks for the review.

I will remove the nested lock between mmap_sem and bo::reserve, and 
change the kfd side locking order
to bo::reserve -> amdgpu_mn_lock(p->mn) as the original gfx side locking 
order.

Will submit patch v2 with other changes.

Philip
>>
>> HMM simplify the CPU page table concurrently update check, so remove
>> guptasklock, mmu_invalidations, last_set_pages fields from
>> amdgpu_ttm_tt struct.
>>
>> HMM doesnot pin the page (increase page ref count), so remove related
>> operations like release_pages(), put_page(), mark_page_dirty().
>>
>> Change-Id: Iffd5f855cc9ce402cdfca167f68f83fe39ac56f9
>> Signed-off-by: Philip Yang 
>> ---
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 101 ++---
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c  |   2 -
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h  |   3 +-
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c   | 171 
>> +--
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c  |  14 +-
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c   |  34 -
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h   |   7 +-
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c  | 164 
>> +-
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h  |   3 +-
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c   |   1 -
>>   10 files changed, 252 insertions(+), 248 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
>> index df0a059..3fd0340 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
>> @@ -615,8 +615,7 @@ static int init_user_pages(struct kgd_mem *mem, 
>> struct mm_struct *mm,
>>   amdgpu_bo_unreserve(bo);
>>     release_out:
>> -    if (ret)
>> -    release_pages(mem->user_pages, bo->tbo.ttm->num_pages);
>> +    amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm);
>>   free_out:
>>   kvfree(mem->user_pages);
>>   mem->user_pages = NULL;
>> @@ -678,7 +677,6 @@ static int reserve_bo_and_vm(struct kgd_mem *mem,
>>   ctx->kfd_bo.priority = 0;
>>   ctx->kfd_bo.tv.bo = >tbo;
>>   ctx->kfd_bo.tv.shared = true;
>> -    ctx->kfd_bo.user_pages = NULL;
>>   list_add(>kfd_bo.tv.head, >list);
>>     amdgpu_vm_get_pd_bo(vm, >list, >vm_pd[0]);
>> @@ -742,7 +740,6 @@ static int reserve_bo_and_cond_vms(struct kgd_mem 
>> *mem,
>>   ctx->kfd_bo.priority = 0;
>>   ctx->kfd_bo.tv.bo = >tbo;
>>   ctx->kfd_bo.tv.shared = true;
>> -    ctx->kfd_bo.user_pages = NULL;
>>   list_add(>kfd_bo.tv.head, >list);
>>     i = 0;
>> @@ -1311,9 +1308,6 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
>>   /* Free user pages if necessary */
>>   if (mem->user_pages) {
>>   pr_debug("%s: Freeing user_pages array\n", __func__);
>> -    if (mem->user_pages[0])
>> -    release_pages(mem->user_pages,
>> -    mem->bo->tbo.ttm->num_pages);
>>   kvfree(mem->user_pages);
>>   }
>>   @@ -1739,8 +1733,6 @@ static int update_invalid_user_pages(struct 
>> amdkfd_process_info *process_info,
>>  __func__);
>>   return -ENOMEM;
>>   }
>> -    } else if (mem->user_pages[0]) {
>> -    release_pages(mem->user_pages, bo->tbo.ttm->num_pages);
>>   }
>>     /* Get updated user pages */
>> @@ -1756,12 +1748,6 @@ static int update_invalid_user_pages(struct 
>> amdkfd_process_info *process_info,
>>    * stalled user mode queues.
>>    */
>>   }
>> -
>> -    /* Mark the BO as valid unless it was invalidated
>> - * again concurrently
>> - */
>> -    if (atomic_cmpxchg(>invalid, invalid, 0) != invalid)
>> -    return -EAGAIN;
>>   }
>>

[pull] amdgpu, radeon, scheduler drm-next-4.20

2018-10-17 Thread Alex Deucher

Hi Dave,

Fixes for 4.20.  Highlights:
- VCN DPG fixes for Picasso
- Add support for the latest vega20 vbios
- Scheduler timeout fix
- License fixes for radeon and amdgpu
- Misc other fixes

The following changes since commit ca4b869240d5810ebac6b1570ad7beffcfbac2f5:

  Merge branch 'drm-next-4.20' of git://people.freedesktop.org/~agd5f/linux 
into drm-next (2018-10-11 14:53:45 +1000)

are available in the git repository at:

  git://people.freedesktop.org/~agd5f/linux drm-next-4.20

for you to fetch changes up to 8e16695b4eb819881774b8c06eb164dc1fb74275:

  drm/amdgpu/vcn:Fix uninitialized symbol error (2018-10-17 16:13:07 -0500)


Christian König (2):
  drm/sched: add drm_sched_start_timeout helper
  drm/sched: fix timeout handling v2

Dan Carpenter (1):
  drm/amd/amdgpu: Fix debugfs error handling

Emily Deng (1):
  drm/amdgpu: Set the default value about gds vmid0 size

Evan Quan (5):
  drm/amd/powerplay: translate power_profile mode to pplib workload type
  drm/amd/powerplay: hint when power profile setting is not supported
  drm/amdgpu: update Vega20 SDMA golden setting
  drm/amd/powerplay: added I2C controller configuration
  drm/amd/powerplay: update PPtable with DC BTC and Tvr SocLimit fields

Feifei Xu (1):
  drm/amdgpu: Update gc_9_0 golden settings.

James Zhu (19):
  drm/amdgpu/vcn:Add new register offset/mask for VCN
  drm/amdgpu/vcn:Update latest UVD_MPC register for VCN
  drm/amdgpu/vcn:Update latest spg mode stop for VCN
  drm/amdgpu/vcn:Add ring W/R PTR check for VCN DPG mode stop
  drm/amdgpu/vcn:Reduce unnecessary local variable
  drm/amdgpu/vcn:Update DPG mode VCN memory control
  drm/amdgpu/vcn:Update DPG mode VCN global tiling registers
  drm/amdgpu/vcn:Add DPG mode Register XX check
  drm/amdgpu/vcn:Remove DPG mode unused steps during vcn start
  drm/amdgpu/vcn:Apply new UMC enable for VNC DPG mode start
  drm/amdgpu/vcn:Update SPG mode VCN memory control
  drm/amdgpu/vcn:Update SPG mode VCN global tiling
  drm/amdgpu/vcn:Move SPG mode mc resume after MPC control
  drm/amdgpu/vcn:Add SPG mode Register XX check
  drm/amdgpu/vcn:Remove SPG mode unused steps during vcn start
  drm/amdgpu/vcn:Apply new UMC enable for VNC DPG mode
  drm/amdgpu/vcn:Set VCPU busy after gate power during vcn SPG start
  drm/amdgpu/vcn:Update SPG mode UVD status clear
  drm/amdgpu/vcn:Fix uninitialized symbol error

Jonathan Gray (2):
  drm/amdgpu: correct SPDX identifier in amdgpu_trace_points.c
  drm/radeon: change SPDX identifier to MIT

Rex Zhu (1):
  drm/amdgpu: Fix typo in amdgpu_vmid_mgr_init

Su Sung Chung (1):
  drm/amd/display: fix bug of accessing invalid memory

hersen wu (1):
  drm/amdgpu/display: dm/amdgpu: make dp phy debugfs for eDP

 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c|  12 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c|   2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_trace_points.c   |   2 +-
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c  |  16 +-
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c |   2 +
 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c  | 290 -
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c  |   3 +-
 .../drm/amd/display/modules/color/color_gamma.c|   8 +-
 .../drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h  |  14 +
 .../drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h |  18 ++
 drivers/gpu/drm/amd/include/atomfirmware.h |  88 +++
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c  |   9 +-
 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c |  42 ++-
 .../amd/powerplay/hwmgr/vega20_processpptables.c   | 102 +---
 .../gpu/drm/amd/powerplay/inc/smu11_driver_if.h| 115 +---
 drivers/gpu/drm/radeon/mkregtable.c|   2 +-
 drivers/gpu/drm/radeon/r100_track.h|   2 +-
 drivers/gpu/drm/radeon/radeon_dp_mst.c |   2 +-
 drivers/gpu/drm/radeon/radeon_legacy_tv.c  |   2 +-
 drivers/gpu/drm/radeon/radeon_trace.h  |   2 +-
 drivers/gpu/drm/radeon/radeon_trace_points.c   |   2 +-
 drivers/gpu/drm/scheduler/sched_main.c |  59 -
 include/drm/drm_pciids.h   |   2 +-
 23 files changed, 567 insertions(+), 229 deletions(-)
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH v2 04/10] drm/amd/display: dc/bios: add support for DCE6

2018-10-17 Thread Wentland, Harry

On 2018-10-17 4:42 p.m., Alex Deucher wrote:
> On Wed, Oct 17, 2018 at 4:16 PM Wentland, Harry  
> wrote:
>>
>> On 2018-10-17 4:10 p.m., Alex Deucher wrote:
>>> On Wed, Oct 17, 2018 at 3:54 PM Wentland, Harry  
>>> wrote:

 On 2018-10-17 4:35 a.m., Mauro Rossi wrote:
> DCE6 targets are added replicating existing DCE8 implementation.
> ---
>  drivers/gpu/drm/amd/display/dc/bios/Makefile  |   9 +
>  .../display/dc/bios/command_table_helper.c|   8 +
>  .../display/dc/bios/command_table_helper.h|   3 +
>  .../display/dc/bios/command_table_helper2.c   |   8 +
>  .../display/dc/bios/command_table_helper2.h   |   3 +
>  .../bios/dce60/command_table_helper_dce60.c   | 354 ++
>  .../bios/dce60/command_table_helper_dce60.h   |  33 ++
>  7 files changed, 418 insertions(+)
>  create mode 100644 
> drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c
>  create mode 100644 
> drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.h
>
> diff --git a/drivers/gpu/drm/amd/display/dc/bios/Makefile 
> b/drivers/gpu/drm/amd/display/dc/bios/Makefile
> index 239e86bbec5a..ed6b5e9763f6 100644
> --- a/drivers/gpu/drm/amd/display/dc/bios/Makefile
> +++ b/drivers/gpu/drm/amd/display/dc/bios/Makefile
> @@ -31,6 +31,15 @@ AMD_DAL_BIOS = $(addprefix 
> $(AMDDALPATH)/dc/bios/,$(BIOS))
>
>  AMD_DISPLAY_FILES += $(AMD_DAL_BIOS)
>
> +###
> +# DCE 6x
> +###
> +# All DCE6.x are derived from DCE6.0, so 6.0 MUST be defined if ANY of
> +# DCE6.x is compiled.
> +ifdef CONFIG_DRM_AMD_DC_SI
> +AMD_DISPLAY_FILES += 
> $(AMDDALPATH)/dc/bios/dce60/command_table_helper_dce60.o
> +endif
> +
>  
> ###
>  # DCE 8x
>  
> ###
> diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c 
> b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c
> index 253bbb1eea60..48b4ef03fc8f 100644
> --- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c
> +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c
> @@ -36,6 +36,14 @@ bool dal_bios_parser_init_cmd_tbl_helper(
>   enum dce_version dce)
>  {
>   switch (dce) {
> +#if defined(CONFIG_DRM_AMD_DC_SI)
> + case DCE_VERSION_6_0:
> + case DCE_VERSION_6_1:
> + case DCE_VERSION_6_4:
> + *h = dal_cmd_tbl_helper_dce60_get_table();

 Can we just point these to the dce80 version since they're exactly the 
 same?
>>>
>>> Some of the dig transmitter and encoder cmd tables had different
>>> versions on DCE6 vs 8.  I'm not sure if we need to do any different
>>> translations for some of these.
>>>
>>
>> Currently it's an exact copy. Since you remember differences it makes sense 
>> to duplicate this for DCE6 so we can update it for any difference if we'll 
>> need that.
>>
>> Mauro, ignore my comments in this case. :)
> 
> I just double checked the vbios DCE8 design documents and the cmd
> tables are compatible (the only major difference was the addition of
> the 7th phy which won't show up on DCE6, so not an issue).  I also
> double check the cmd table versions on a few bioses and they are the
> same.  We should be fine with just sharing the DCE8 code for DCE6 as
> well.  Sorry for the noise.
> 

Thanks for looking into the design docs. Looks like we're good to share this 
code then.

Harry

> Alex
> 
>>
>> Harry
>>
>>> Alex
>>>

> + return true;
> +#endif
> +
>   case DCE_VERSION_8_0:
>   case DCE_VERSION_8_1:
>   case DCE_VERSION_8_3:
> diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h 
> b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h
> index 4c3789df253d..dfd30aaf4032 100644
> --- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h
> +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h
> @@ -26,6 +26,9 @@
>  #ifndef __DAL_COMMAND_TABLE_HELPER_H__
>  #define __DAL_COMMAND_TABLE_HELPER_H__
>
> +#if defined(CONFIG_DRM_AMD_DC_SI)
> +#include "dce60/command_table_helper_dce60.h"
> +#endif
>  #include "dce80/command_table_helper_dce80.h"
>  #include "dce110/command_table_helper_dce110.h"
>  #include "dce112/command_table_helper_dce112.h"
> diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c 
> b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
> index 65b006ad372e..92288c582934 100644
> --- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
> +++

Re: [PATCH v2 07/10] drm/amd/display: dc/irq: add support for DCE6

2018-10-17 Thread Wentland, Harry



On 2018-10-17 4:35 a.m., Mauro Rossi wrote:
> DCE6 targets are added replicating existing DCE8 implementation.
> 
> NOTE: due to missing CRTC_VERTICAL_INTERRUPT0_CONTROL registers/masks,
> dce/dce_8_0_{d,sh_mask}.h headers were used instead of 
> dce/dce_6_0_{d,sh_mask}.h
> but only as exception in dce/irq_service_dce60.c
> 
> IMPORTANT: Coding of dce/irq_service_dce60.c requires review to understand
> if dce_6_0_{d,sh_mask}.h should be updated with macros/registers/masks
> ---
>  drivers/gpu/drm/amd/display/dc/irq/Makefile   |  11 +
>  .../display/dc/irq/dce60/irq_service_dce60.c  | 303 ++
>  .../display/dc/irq/dce60/irq_service_dce60.h  |  35 ++
>  .../gpu/drm/amd/display/dc/irq/irq_service.c  |   3 +
>  4 files changed, 352 insertions(+)
>  create mode 100644 
> drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
>  create mode 100644 
> drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.h
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/irq/Makefile 
> b/drivers/gpu/drm/amd/display/dc/irq/Makefile
> index 498515aad4a5..e38b6d8d614d 100644
> --- a/drivers/gpu/drm/amd/display/dc/irq/Makefile
> +++ b/drivers/gpu/drm/amd/display/dc/irq/Makefile
> @@ -30,6 +30,17 @@ AMD_DAL_IRQ = $(addprefix $(AMDDALPATH)/dc/irq/,$(IRQ))
>  
>  AMD_DISPLAY_FILES += $(AMD_DAL_IRQ)
>  
> +###
> +# DCE 6x
> +###
> +ifdef CONFIG_DRM_AMD_DC_SI
> +IRQ_DCE60 = irq_service_dce60.o
> +
> +AMD_DAL_IRQ_DCE60 = $(addprefix $(AMDDALPATH)/dc/irq/dce60/,$(IRQ_DCE60))
> +
> +AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCE60)
> +endif
> +
>  
> ###
>  # DCE 8x
>  
> ###
> diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c 
> b/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
> new file mode 100644
> index ..107e0dcb5f80
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
> @@ -0,0 +1,303 @@
> +/*
> + * Copyright 2012-15 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> + * Authors: AMD
> + *
> + */
> +
> +#include "dm_services.h"
> +
> +#include "include/logger_interface.h"
> +
> +#include "irq_service_dce60.h"
> +#include "../dce110/irq_service_dce110.h"
> +
> +#include "dce/dce_8_0_d.h"
> +#include "dce/dce_8_0_sh_mask.h"
> +
> +#include "ivsrcid/ivsrcid_vislands30.h"
> +
> +#include "dc_types.h"
> +
> +static bool hpd_ack(
> + struct irq_service *irq_service,
> + const struct irq_source_info *info)
> +{
> + uint32_t addr = info->status_reg;
> + uint32_t value = dm_read_reg(irq_service->ctx, addr);
> + uint32_t current_status =
> + get_reg_field_value(
> + value,
> + DC_HPD1_INT_STATUS,
> + DC_HPD1_SENSE_DELAYED);
> +
> + dal_irq_service_ack_generic(irq_service, info);
> +
> + value = dm_read_reg(irq_service->ctx, info->enable_reg);
> +
> + set_reg_field_value(
> + value,
> + current_status ? 0 : 1,
> + DC_HPD1_INT_CONTROL,
> + DC_HPD1_INT_POLARITY);
> +
> + dm_write_reg(irq_service->ctx, info->enable_reg, value);
> +
> + return true;
> +}
> +
> +static const struct irq_source_info_funcs hpd_irq_info_funcs = {
> + .set = NULL,
> + .ack = hpd_ack
> +};
> +
> +static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
> + .set = NULL,
> + .ack = NULL
> +};
> +
> +static const struct irq_source_info_funcs pflip_irq_info_funcs = {
> + .set = NULL,
> + .ack = NULL
> +};
> +
> +static const struct irq_source_info_funcs vblank_irq_info_funcs = {
> +

Re: [PATCH v2 04/10] drm/amd/display: dc/bios: add support for DCE6

2018-10-17 Thread Alex Deucher

On Wed, Oct 17, 2018 at 3:54 PM Wentland, Harry  wrote:
>
> On 2018-10-17 4:35 a.m., Mauro Rossi wrote:
> > DCE6 targets are added replicating existing DCE8 implementation.
> > ---
> >  drivers/gpu/drm/amd/display/dc/bios/Makefile  |   9 +
> >  .../display/dc/bios/command_table_helper.c|   8 +
> >  .../display/dc/bios/command_table_helper.h|   3 +
> >  .../display/dc/bios/command_table_helper2.c   |   8 +
> >  .../display/dc/bios/command_table_helper2.h   |   3 +
> >  .../bios/dce60/command_table_helper_dce60.c   | 354 ++
> >  .../bios/dce60/command_table_helper_dce60.h   |  33 ++
> >  7 files changed, 418 insertions(+)
> >  create mode 100644 
> > drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c
> >  create mode 100644 
> > drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.h
> >
> > diff --git a/drivers/gpu/drm/amd/display/dc/bios/Makefile 
> > b/drivers/gpu/drm/amd/display/dc/bios/Makefile
> > index 239e86bbec5a..ed6b5e9763f6 100644
> > --- a/drivers/gpu/drm/amd/display/dc/bios/Makefile
> > +++ b/drivers/gpu/drm/amd/display/dc/bios/Makefile
> > @@ -31,6 +31,15 @@ AMD_DAL_BIOS = $(addprefix 
> > $(AMDDALPATH)/dc/bios/,$(BIOS))
> >
> >  AMD_DISPLAY_FILES += $(AMD_DAL_BIOS)
> >
> > +###
> > +# DCE 6x
> > +###
> > +# All DCE6.x are derived from DCE6.0, so 6.0 MUST be defined if ANY of
> > +# DCE6.x is compiled.
> > +ifdef CONFIG_DRM_AMD_DC_SI
> > +AMD_DISPLAY_FILES += 
> > $(AMDDALPATH)/dc/bios/dce60/command_table_helper_dce60.o
> > +endif
> > +
> >  
> > ###
> >  # DCE 8x
> >  
> > ###
> > diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c 
> > b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c
> > index 253bbb1eea60..48b4ef03fc8f 100644
> > --- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c
> > +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c
> > @@ -36,6 +36,14 @@ bool dal_bios_parser_init_cmd_tbl_helper(
> >   enum dce_version dce)
> >  {
> >   switch (dce) {
> > +#if defined(CONFIG_DRM_AMD_DC_SI)
> > + case DCE_VERSION_6_0:
> > + case DCE_VERSION_6_1:
> > + case DCE_VERSION_6_4:
> > + *h = dal_cmd_tbl_helper_dce60_get_table();
>
> Can we just point these to the dce80 version since they're exactly the same?

Some of the dig transmitter and encoder cmd tables had different
versions on DCE6 vs 8.  I'm not sure if we need to do any different
translations for some of these.

Alex

>
> > + return true;
> > +#endif
> > +
> >   case DCE_VERSION_8_0:
> >   case DCE_VERSION_8_1:
> >   case DCE_VERSION_8_3:
> > diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h 
> > b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h
> > index 4c3789df253d..dfd30aaf4032 100644
> > --- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h
> > +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h
> > @@ -26,6 +26,9 @@
> >  #ifndef __DAL_COMMAND_TABLE_HELPER_H__
> >  #define __DAL_COMMAND_TABLE_HELPER_H__
> >
> > +#if defined(CONFIG_DRM_AMD_DC_SI)
> > +#include "dce60/command_table_helper_dce60.h"
> > +#endif
> >  #include "dce80/command_table_helper_dce80.h"
> >  #include "dce110/command_table_helper_dce110.h"
> >  #include "dce112/command_table_helper_dce112.h"
> > diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c 
> > b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
> > index 65b006ad372e..92288c582934 100644
> > --- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
> > +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
> > @@ -37,6 +37,14 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
> >   enum dce_version dce)
> >  {
> >   switch (dce) {
> > +#if defined(CONFIG_DRM_AMD_DC_SI)
> > + case DCE_VERSION_6_0:
> > + case DCE_VERSION_6_1:
> > + case DCE_VERSION_6_4:
> > + *h = dal_cmd_tbl_helper_dce60_get_table();
>
> Same as above.
>
> Harry
>
> > + return true;
> > +#endif
> > +
> >   case DCE_VERSION_8_0:
> >   case DCE_VERSION_8_1:
> >   case DCE_VERSION_8_3:
> > diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h 
> > b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h
> > index 785fcb20a1b9..66e0a3e73768 100644
> > --- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h
> > +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h
> > @@ -26,6 +26,9 @@
> >  #ifndef __DAL_COMMAND_TABLE_HELPER2_H__
> >  #define __DAL_COMMAND_TABLE_HELPER2_H__
> >
> > +#if defined(CONFIG_DRM_AMD_DC_SI)
> > +#include "dce60/command_table_helper_dce60.h"
> >

Re: [PATCH v2 03/10] drm/amd/display: dc/core: add DCE6 support

2018-10-17 Thread Wentland, Harry



On 2018-10-17 3:50 p.m., Wentland, Harry wrote:
> On 2018-10-17 4:35 a.m., Mauro Rossi wrote:
>> DCE6 targets are added as branching of existing DCE8 implementation.
> 
> All your parents require a Signed-off-by. See 
> https://www.kernel.org/doc/html/v4.17/process/submitting-patches.html#developer-s-certificate-of-origin-1-1

s/parents/patches

Harry

> 
> Harry
> 
>> ---
>>  .../gpu/drm/amd/display/dc/core/dc_resource.c | 29 +++
>>  1 file changed, 29 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c 
>> b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
>> index a5eb80aa3dd9..07bd4f72acc5 100644
>> --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
>> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
>> @@ -37,6 +37,9 @@
>>  #include "virtual/virtual_stream_encoder.h"
>>  #include "dpcd_defs.h"
>>  
>> +#if defined(CONFIG_DRM_AMD_DC_SI)
>> +#include "dce60/dce60_resource.h"
>> +#endif
>>  #include "dce80/dce80_resource.h"
>>  #include "dce100/dce100_resource.h"
>>  #include "dce110/dce110_resource.h"
>> @@ -53,6 +56,18 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id 
>> asic_id)
>>  enum dce_version dc_version = DCE_VERSION_UNKNOWN;
>>  switch (asic_id.chip_family) {
>>  
>> +#if defined(CONFIG_DRM_AMD_DC_SI)
>> +case FAMILY_SI:
>> +if (ASIC_REV_IS_TAHITI_P(asic_id.hw_internal_rev) ||
>> +ASIC_REV_IS_PITCAIRN_PM(asic_id.hw_internal_rev) ||
>> +ASIC_REV_IS_CAPEVERDE_M(asic_id.hw_internal_rev))
>> +dc_version = DCE_VERSION_6_0;
>> +else if (ASIC_REV_IS_OLAND_M(asic_id.hw_internal_rev))
>> +dc_version = DCE_VERSION_6_4;
>> +else
>> +dc_version = DCE_VERSION_6_1;
>> +break;
>> +#endif
>>  case FAMILY_CI:
>>  dc_version = DCE_VERSION_8_0;
>>  break;
>> @@ -110,6 +125,20 @@ struct resource_pool *dc_create_resource_pool(
>>  struct resource_pool *res_pool = NULL;
>>  
>>  switch (dc_version) {
>> +#if defined(CONFIG_DRM_AMD_DC_SI)
>> +case DCE_VERSION_6_0:
>> +res_pool = dce60_create_resource_pool(
>> +num_virtual_links, dc);
>> +break;
>> +case DCE_VERSION_6_1:
>> +res_pool = dce61_create_resource_pool(
>> +num_virtual_links, dc);
>> +break;
>> +case DCE_VERSION_6_4:
>> +res_pool = dce64_create_resource_pool(
>> +num_virtual_links, dc);
>> +break;
>> +#endif
>>  case DCE_VERSION_8_0:
>>  res_pool = dce80_create_resource_pool(
>>  num_virtual_links, dc);
>>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> 
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH v2 04/10] drm/amd/display: dc/bios: add support for DCE6

2018-10-17 Thread Wentland, Harry

On 2018-10-17 4:35 a.m., Mauro Rossi wrote:
> DCE6 targets are added replicating existing DCE8 implementation.
> ---
>  drivers/gpu/drm/amd/display/dc/bios/Makefile  |   9 +
>  .../display/dc/bios/command_table_helper.c|   8 +
>  .../display/dc/bios/command_table_helper.h|   3 +
>  .../display/dc/bios/command_table_helper2.c   |   8 +
>  .../display/dc/bios/command_table_helper2.h   |   3 +
>  .../bios/dce60/command_table_helper_dce60.c   | 354 ++
>  .../bios/dce60/command_table_helper_dce60.h   |  33 ++
>  7 files changed, 418 insertions(+)
>  create mode 100644 
> drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c
>  create mode 100644 
> drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.h
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/bios/Makefile 
> b/drivers/gpu/drm/amd/display/dc/bios/Makefile
> index 239e86bbec5a..ed6b5e9763f6 100644
> --- a/drivers/gpu/drm/amd/display/dc/bios/Makefile
> +++ b/drivers/gpu/drm/amd/display/dc/bios/Makefile
> @@ -31,6 +31,15 @@ AMD_DAL_BIOS = $(addprefix $(AMDDALPATH)/dc/bios/,$(BIOS))
>  
>  AMD_DISPLAY_FILES += $(AMD_DAL_BIOS)
>  
> +###
> +# DCE 6x
> +###
> +# All DCE6.x are derived from DCE6.0, so 6.0 MUST be defined if ANY of
> +# DCE6.x is compiled.
> +ifdef CONFIG_DRM_AMD_DC_SI
> +AMD_DISPLAY_FILES += $(AMDDALPATH)/dc/bios/dce60/command_table_helper_dce60.o
> +endif
> +
>  
> ###
>  # DCE 8x
>  
> ###
> diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c 
> b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c
> index 253bbb1eea60..48b4ef03fc8f 100644
> --- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c
> +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c
> @@ -36,6 +36,14 @@ bool dal_bios_parser_init_cmd_tbl_helper(
>   enum dce_version dce)
>  {
>   switch (dce) {
> +#if defined(CONFIG_DRM_AMD_DC_SI)
> + case DCE_VERSION_6_0:
> + case DCE_VERSION_6_1:
> + case DCE_VERSION_6_4:
> + *h = dal_cmd_tbl_helper_dce60_get_table();

Can we just point these to the dce80 version since they're exactly the same?

> + return true;
> +#endif
> +
>   case DCE_VERSION_8_0:
>   case DCE_VERSION_8_1:
>   case DCE_VERSION_8_3:
> diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h 
> b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h
> index 4c3789df253d..dfd30aaf4032 100644
> --- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h
> +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h
> @@ -26,6 +26,9 @@
>  #ifndef __DAL_COMMAND_TABLE_HELPER_H__
>  #define __DAL_COMMAND_TABLE_HELPER_H__
>  
> +#if defined(CONFIG_DRM_AMD_DC_SI)
> +#include "dce60/command_table_helper_dce60.h"
> +#endif
>  #include "dce80/command_table_helper_dce80.h"
>  #include "dce110/command_table_helper_dce110.h"
>  #include "dce112/command_table_helper_dce112.h"
> diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c 
> b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
> index 65b006ad372e..92288c582934 100644
> --- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
> +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
> @@ -37,6 +37,14 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
>   enum dce_version dce)
>  {
>   switch (dce) {
> +#if defined(CONFIG_DRM_AMD_DC_SI)
> + case DCE_VERSION_6_0:
> + case DCE_VERSION_6_1:
> + case DCE_VERSION_6_4:
> + *h = dal_cmd_tbl_helper_dce60_get_table();

Same as above.

Harry

> + return true;
> +#endif
> +
>   case DCE_VERSION_8_0:
>   case DCE_VERSION_8_1:
>   case DCE_VERSION_8_3:
> diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h 
> b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h
> index 785fcb20a1b9..66e0a3e73768 100644
> --- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h
> +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h
> @@ -26,6 +26,9 @@
>  #ifndef __DAL_COMMAND_TABLE_HELPER2_H__
>  #define __DAL_COMMAND_TABLE_HELPER2_H__
>  
> +#if defined(CONFIG_DRM_AMD_DC_SI)
> +#include "dce60/command_table_helper_dce60.h"
> +#endif
>  #include "dce80/command_table_helper_dce80.h"
>  #include "dce110/command_table_helper_dce110.h"
>  #include "dce112/command_table_helper2_dce112.h"
> diff --git 
> a/drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c 
> b/drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c
> new file mode 100644
> index ..552778ce9835
> --- /dev/null
> +++

Re: [PATCH v2 03/10] drm/amd/display: dc/core: add DCE6 support

2018-10-17 Thread Wentland, Harry

On 2018-10-17 4:35 a.m., Mauro Rossi wrote:
> DCE6 targets are added as branching of existing DCE8 implementation.

All your parents require a Signed-off-by. See 
https://www.kernel.org/doc/html/v4.17/process/submitting-patches.html#developer-s-certificate-of-origin-1-1

Harry

> ---
>  .../gpu/drm/amd/display/dc/core/dc_resource.c | 29 +++
>  1 file changed, 29 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c 
> b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> index a5eb80aa3dd9..07bd4f72acc5 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> @@ -37,6 +37,9 @@
>  #include "virtual/virtual_stream_encoder.h"
>  #include "dpcd_defs.h"
>  
> +#if defined(CONFIG_DRM_AMD_DC_SI)
> +#include "dce60/dce60_resource.h"
> +#endif
>  #include "dce80/dce80_resource.h"
>  #include "dce100/dce100_resource.h"
>  #include "dce110/dce110_resource.h"
> @@ -53,6 +56,18 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id 
> asic_id)
>   enum dce_version dc_version = DCE_VERSION_UNKNOWN;
>   switch (asic_id.chip_family) {
>  
> +#if defined(CONFIG_DRM_AMD_DC_SI)
> + case FAMILY_SI:
> + if (ASIC_REV_IS_TAHITI_P(asic_id.hw_internal_rev) ||
> + ASIC_REV_IS_PITCAIRN_PM(asic_id.hw_internal_rev) ||
> + ASIC_REV_IS_CAPEVERDE_M(asic_id.hw_internal_rev))
> + dc_version = DCE_VERSION_6_0;
> + else if (ASIC_REV_IS_OLAND_M(asic_id.hw_internal_rev))
> + dc_version = DCE_VERSION_6_4;
> + else
> + dc_version = DCE_VERSION_6_1;
> + break;
> +#endif
>   case FAMILY_CI:
>   dc_version = DCE_VERSION_8_0;
>   break;
> @@ -110,6 +125,20 @@ struct resource_pool *dc_create_resource_pool(
>   struct resource_pool *res_pool = NULL;
>  
>   switch (dc_version) {
> +#if defined(CONFIG_DRM_AMD_DC_SI)
> + case DCE_VERSION_6_0:
> + res_pool = dce60_create_resource_pool(
> + num_virtual_links, dc);
> + break;
> + case DCE_VERSION_6_1:
> + res_pool = dce61_create_resource_pool(
> + num_virtual_links, dc);
> + break;
> + case DCE_VERSION_6_4:
> + res_pool = dce64_create_resource_pool(
> + num_virtual_links, dc);
> + break;
> +#endif
>   case DCE_VERSION_8_0:
>   res_pool = dce80_create_resource_pool(
>   num_virtual_links, dc);
> 
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH v2 02/10] drm/amd/display: dc/dce: add DCE6 support (v2)

2018-10-17 Thread Wentland, Harry

On 2018-10-17 4:35 a.m., Mauro Rossi wrote:
> DCE6 targets are added replicating existing DCE8 implementation.
> 
> NOTE: dce_8_0_{d,sh_mask}.h headers used instead of dce_6_0_{d,sh_mask}.h
> only to build dce60_resource.c due to missing *_DCE60 macros/registers/masks
> 
> IMPORTANT: Coding of dce60_resource.c requires review to understand
> if dce_6_0_{d,sh_mask}.h should be updated with macros/registers/masks
> 
> (v2) updated dce60_{hw_sequencer,resources}.c as per amd-staging-drm-next
>  removed dce_version cases in dc/dce/dce_clock_source.c
> ---
>  drivers/gpu/drm/amd/display/dc/Makefile   |4 +
>  drivers/gpu/drm/amd/display/dc/dce60/Makefile |   34 +
>  .../amd/display/dc/dce60/dce60_hw_sequencer.c |   82 +
>  .../amd/display/dc/dce60/dce60_hw_sequencer.h |   36 +
>  .../drm/amd/display/dc/dce60/dce60_resource.c | 1458 +
>  .../drm/amd/display/dc/dce60/dce60_resource.h |   47 +
>  .../display/dc/dce60/dce60_timing_generator.c |  242 +++
>  .../display/dc/dce60/dce60_timing_generator.h |   39 +
>  .../include/asic_reg/dce/dce_6_0_sh_mask.h|4 +
>  9 files changed, 1946 insertions(+)
>  create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/Makefile
>  create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.c
>  create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.h
>  create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c
>  create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.h
>  create mode 100644 
> drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.c
>  create mode 100644 
> drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.h
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/Makefile 
> b/drivers/gpu/drm/amd/display/dc/Makefile
> index aed538a4d1ba..d5d5acd57559 100644
> --- a/drivers/gpu/drm/amd/display/dc/Makefile
> +++ b/drivers/gpu/drm/amd/display/dc/Makefile
> @@ -36,6 +36,10 @@ DC_LIBS += dce110
>  DC_LIBS += dce100
>  DC_LIBS += dce80
>  
> +ifdef CONFIG_DRM_AMD_DC_SI
> +DC_LIBS += dce60
> +endif
> +
>  AMD_DC = $(addsuffix /Makefile, $(addprefix 
> $(FULL_AMD_DISPLAY_PATH)/dc/,$(DC_LIBS)))
>  
>  include $(AMD_DC)
> diff --git a/drivers/gpu/drm/amd/display/dc/dce60/Makefile 
> b/drivers/gpu/drm/amd/display/dc/dce60/Makefile
> new file mode 100644
> index ..39afd7c59a7c
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/display/dc/dce60/Makefile
> @@ -0,0 +1,34 @@
> +#
> +# Copyright 2017 Advanced Micro Devices, Inc.
> +#
> +# Permission is hereby granted, free of charge, to any person obtaining a
> +# copy of this software and associated documentation files (the "Software"),
> +# to deal in the Software without restriction, including without limitation
> +# the rights to use, copy, modify, merge, publish, distribute, sublicense,
> +# and/or sell copies of the Software, and to permit persons to whom the
> +# Software is furnished to do so, subject to the following conditions:
> +#
> +# The above copyright notice and this permission notice shall be included in
> +# all copies or substantial portions of the Software.
> +#
> +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> +# OTHER DEALINGS IN THE SOFTWARE.
> +#
> +#
> +# Makefile for the 'controller' sub-component of DAL.
> +# It provides the control and status of HW CRTC block.
> +
> +DCE60 = dce60_timing_generator.o dce60_hw_sequencer.o \
> + dce60_resource.o
> +
> +AMD_DAL_DCE60 = $(addprefix $(AMDDALPATH)/dc/dce60/,$(DCE60))
> +
> +AMD_DISPLAY_FILES += $(AMD_DAL_DCE60)
> +
> +
> +
> diff --git a/drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.c 
> b/drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.c
> new file mode 100644
> index ..502172bf6097
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.c
> @@ -0,0 +1,82 @@
> +/*
> + * Copyright 2015 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT

Re: regression on RV1

2018-10-17 Thread StDenis, Tom

I had sent a patch to the list but yours is prettier.  You can add my 
Tested-By: to your patch.

Tom



On 2018-10-17 12:40 p.m., Deucher, Alexander wrote:
> I think something like this should fix it.
> 
> 
> Alex
> 
> 
> *From:* amd-gfx  on behalf of 
> Deucher, Alexander 
> *Sent:* Wednesday, October 17, 2018 12:15:21 PM
> *To:* StDenis, Tom; Koenig, Christian; amd-gfx mailing list
> *Cc:* Huang, Ray
> *Subject:* Re: regression on RV1
> 
> IIRC, APUs do not have a paging queue.  Only dGPUs have it.
> 
> 
> Alex
> 
> 
> *From:* amd-gfx  on behalf of 
> StDenis, Tom 
> *Sent:* Wednesday, October 17, 2018 11:54:33 AM
> *To:* Koenig, Christian; amd-gfx mailing list
> *Cc:* Huang, Ray
> *Subject:* regression on RV1
> This commit:
> 
> commit 6cbd074831a423e0d30b386fc056d6c2c3559147 (HEAD, refs/bisect/bad)
> Author: Christian König 
> Date:   Mon Oct 8 14:38:22 2018 +0200
> 
>   drm/amdgpu: activate paging queue on SDMA v4
> 
>   Implement all the necessary stuff to get those extra rings working.
> 
>   Signed-off-by: Christian König 
>   Reviewed-by: Huang Rui 
> 
> Breaks my RV1 init.
> 
> Tom

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: regression on RV1

2018-10-17 Thread Koenig, Christian

Sorry for the noise, didn't thought about the issue that this SDMA code is used 
on RV as well.

Feel free to add my rb to the patch,
Christian.

Am 17.10.18 um 18:40 schrieb Deucher, Alexander:

I think something like this should fix it.


Alex


From: amd-gfx 

 on behalf of Deucher, Alexander 

Sent: Wednesday, October 17, 2018 12:15:21 PM
To: StDenis, Tom; Koenig, Christian; amd-gfx mailing list
Cc: Huang, Ray
Subject: Re: regression on RV1


IIRC, APUs do not have a paging queue.  Only dGPUs have it.


Alex


From: amd-gfx 

 on behalf of StDenis, Tom 
Sent: Wednesday, October 17, 2018 11:54:33 AM
To: Koenig, Christian; amd-gfx mailing list
Cc: Huang, Ray
Subject: regression on RV1

This commit:

commit 6cbd074831a423e0d30b386fc056d6c2c3559147 (HEAD, refs/bisect/bad)
Author: Christian König 

Date:   Mon Oct 8 14:38:22 2018 +0200

 drm/amdgpu: activate paging queue on SDMA v4

 Implement all the necessary stuff to get those extra rings working.

 Signed-off-by: Christian König 

 Reviewed-by: Huang Rui 

Breaks my RV1 init.

Tom

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: regression on RV1

2018-10-17 Thread Deucher, Alexander

I think something like this should fix it.


Alex


From: amd-gfx  on behalf of Deucher, 
Alexander 
Sent: Wednesday, October 17, 2018 12:15:21 PM
To: StDenis, Tom; Koenig, Christian; amd-gfx mailing list
Cc: Huang, Ray
Subject: Re: regression on RV1


IIRC, APUs do not have a paging queue.  Only dGPUs have it.


Alex


From: amd-gfx  on behalf of StDenis, Tom 

Sent: Wednesday, October 17, 2018 11:54:33 AM
To: Koenig, Christian; amd-gfx mailing list
Cc: Huang, Ray
Subject: regression on RV1

This commit:

commit 6cbd074831a423e0d30b386fc056d6c2c3559147 (HEAD, refs/bisect/bad)
Author: Christian König 
Date:   Mon Oct 8 14:38:22 2018 +0200

 drm/amdgpu: activate paging queue on SDMA v4

 Implement all the necessary stuff to get those extra rings working.

 Signed-off-by: Christian König 
 Reviewed-by: Huang Rui 

Breaks my RV1 init.

Tom
From 73d0b51c1277dce3b73651cc189dca074c9d3678 Mon Sep 17 00:00:00 2001
From: Alex Deucher 
Date: Wed, 17 Oct 2018 11:39:27 -0500
Subject: [PATCH] drm/amdgpu/sdma4: APUs do not have a page queue

Don't use the paging queue on APUs.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h |  1 +
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c   | 53 
 2 files changed, 34 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
index 556db42edaed..479a2459e558 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
@@ -51,6 +51,7 @@ struct amdgpu_sdma {
 	struct amdgpu_irq_src	illegal_inst_irq;
 	int			num_instances;
 	uint32_tsrbm_soft_reset;
+	bool			has_page_queue;
 };
 
 /*
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index a0a5b2161d78..6ad4fda010f2 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -746,7 +746,8 @@ static void sdma_v4_0_enable(struct amdgpu_device *adev, bool enable)
 	if (enable == false) {
 		sdma_v4_0_gfx_stop(adev);
 		sdma_v4_0_rlc_stop(adev);
-		sdma_v4_0_page_stop(adev);
+		if (adev->sdma.has_page_queue)
+			sdma_v4_0_page_stop(adev);
 	}
 
 	for (i = 0; i < adev->sdma.num_instances; i++) {
@@ -1115,7 +1116,8 @@ static int sdma_v4_0_start(struct amdgpu_device *adev)
 
 		WREG32_SDMA(i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL, 0);
 		sdma_v4_0_gfx_resume(adev, i);
-		sdma_v4_0_page_resume(adev, i);
+		if (adev->sdma.has_page_queue)
+			sdma_v4_0_page_resume(adev, i);
 
 		/* set utc l1 enable flag always to 1 */
 		temp = RREG32_SDMA(i, mmSDMA0_CNTL);
@@ -1457,10 +1459,13 @@ static int sdma_v4_0_early_init(void *handle)
 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-	if (adev->asic_type == CHIP_RAVEN)
+	if (adev->asic_type == CHIP_RAVEN) {
 		adev->sdma.num_instances = 1;
-	else
+		adev->sdma.has_page_queue = false;
+	} else {
 		adev->sdma.num_instances = 2;
+		adev->sdma.has_page_queue = true;
+	}
 
 	sdma_v4_0_set_ring_funcs(adev);
 	sdma_v4_0_set_buffer_funcs(adev);
@@ -1522,18 +1527,20 @@ static int sdma_v4_0_sw_init(void *handle)
 		if (r)
 			return r;
 
-		ring = >sdma.instance[i].page;
-		ring->ring_obj = NULL;
-		ring->use_doorbell = false;
-
-		sprintf(ring->name, "page%d", i);
-		r = amdgpu_ring_init(adev, ring, 1024,
- >sdma.trap_irq,
- (i == 0) ?
- AMDGPU_SDMA_IRQ_TRAP0 :
- AMDGPU_SDMA_IRQ_TRAP1);
-		if (r)
-			return r;
+		if (adev->sdma.has_page_queue) {
+			ring = >sdma.instance[i].page;
+			ring->ring_obj = NULL;
+			ring->use_doorbell = false;
+
+			sprintf(ring->name, "page%d", i);
+			r = amdgpu_ring_init(adev, ring, 1024,
+	 >sdma.trap_irq,
+	 (i == 0) ?
+	 AMDGPU_SDMA_IRQ_TRAP0 :
+	 AMDGPU_SDMA_IRQ_TRAP1);
+			if (r)
+return r;
+		}
 	}
 
 	return r;
@@ -1546,7 +1553,8 @@ static int sdma_v4_0_sw_fini(void *handle)
 
 	for (i = 0; i < adev->sdma.num_instances; i++) {
 		amdgpu_ring_fini(>sdma.instance[i].ring);
-		amdgpu_ring_fini(>sdma.instance[i].page);
+		if (adev->sdma.has_page_queue)
+			amdgpu_ring_fini(>sdma.instance[i].page);
 	}
 
 	for (i = 0; i < adev->sdma.num_instances; i++) {
@@ -1970,8 +1978,10 @@ static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev)
 	for (i = 0; i < adev->sdma.num_instances; i++) {
 		adev->sdma.instance[i].ring.funcs = _v4_0_ring_funcs;
 		adev->sdma.instance[i].ring.me = i;
-		adev->sdma.instance[i].page.funcs = _v4_0_page_ring_funcs;
-		adev->sdma.instance[i].page.me = i;
+		if (adev->sdma.has_page_queue) {
+			adev->sdma.instance[i].page.funcs = _v4_0_page_ring_funcs;
+			adev->sdma.instance[i].page.me = i;
+		}
 	}
 }
 
@@ -2071,7 +2081,10 @@ static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev)
 
 	adev->vm_manager.vm_pte_funcs = _v4_0_vm_pte_funcs;
 	for (i = 0; i < adev->sdma.num_instances; i++) {
-		sched =

[PATCH] drm/amd/amdgpu: Don't use paging functions on APU

2018-10-17 Thread StDenis, Tom

Signed-off-by: Tom St Denis 
---
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 46 --
 1 file changed, 28 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 33a62d5a4949..b7f6db39d357 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -1115,7 +1115,8 @@ static int sdma_v4_0_start(struct amdgpu_device *adev)
 
WREG32_SDMA(i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL, 0);
sdma_v4_0_gfx_resume(adev, i);
-   sdma_v4_0_page_resume(adev, i);
+   if (!(adev->flags & AMD_IS_APU))
+   sdma_v4_0_page_resume(adev, i);
 
/* set utc l1 enable flag always to 1 */
temp = RREG32_SDMA(i, mmSDMA0_CNTL);
@@ -1522,18 +1523,20 @@ static int sdma_v4_0_sw_init(void *handle)
if (r)
return r;
 
-   ring = >sdma.instance[i].page;
-   ring->ring_obj = NULL;
-   ring->use_doorbell = false;
-
-   sprintf(ring->name, "page%d", i);
-   r = amdgpu_ring_init(adev, ring, 1024,
->sdma.trap_irq,
-(i == 0) ?
-AMDGPU_SDMA_IRQ_TRAP0 :
-AMDGPU_SDMA_IRQ_TRAP1);
-   if (r)
-   return r;
+   if (!(adev->flags & AMD_IS_APU)) {
+   ring = >sdma.instance[i].page;
+   ring->ring_obj = NULL;
+   ring->use_doorbell = false;
+
+   sprintf(ring->name, "page%d", i);
+   r = amdgpu_ring_init(adev, ring, 1024,
+>sdma.trap_irq,
+(i == 0) ?
+AMDGPU_SDMA_IRQ_TRAP0 :
+AMDGPU_SDMA_IRQ_TRAP1);
+   if (r)
+   return r;
+   }
}
 
return r;
@@ -1546,7 +1549,8 @@ static int sdma_v4_0_sw_fini(void *handle)
 
for (i = 0; i < adev->sdma.num_instances; i++) {
amdgpu_ring_fini(>sdma.instance[i].ring);
-   amdgpu_ring_fini(>sdma.instance[i].page);
+   if (!(adev->flags & AMD_IS_APU))
+   amdgpu_ring_fini(>sdma.instance[i].page);
}
 
for (i = 0; i < adev->sdma.num_instances; i++) {
@@ -1686,7 +1690,8 @@ static int sdma_v4_0_process_trap_irq(struct 
amdgpu_device *adev,
/* XXX compute */
break;
case 3:
-   amdgpu_fence_process(>sdma.instance[instance].page);
+   if (!(adev->flags & AMD_IS_APU))
+   
amdgpu_fence_process(>sdma.instance[instance].page);
break;
}
return 0;
@@ -1953,8 +1958,10 @@ static void sdma_v4_0_set_ring_funcs(struct 
amdgpu_device *adev)
for (i = 0; i < adev->sdma.num_instances; i++) {
adev->sdma.instance[i].ring.funcs = _v4_0_ring_funcs;
adev->sdma.instance[i].ring.me = i;
-   adev->sdma.instance[i].page.funcs = _v4_0_page_ring_funcs;
-   adev->sdma.instance[i].page.me = i;
+   if (!(adev->flags & AMD_IS_APU)) {
+   adev->sdma.instance[i].page.funcs = 
_v4_0_page_ring_funcs;
+   adev->sdma.instance[i].page.me = i;
+   }
}
 }
 
@@ -2054,7 +2061,10 @@ static void sdma_v4_0_set_vm_pte_funcs(struct 
amdgpu_device *adev)
 
adev->vm_manager.vm_pte_funcs = _v4_0_vm_pte_funcs;
for (i = 0; i < adev->sdma.num_instances; i++) {
-   sched = >sdma.instance[i].page.sched;
+   if (!(adev->flags & AMD_IS_APU))
+   sched = >sdma.instance[i].page.sched;
+   else
+   sched = >sdma.instance[i].ring.sched;
adev->vm_manager.vm_pte_rqs[i] =
>sched_rq[DRM_SCHED_PRIORITY_KERNEL];
}
-- 
2.17.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 1/4] drm/scheduler: make sure timer is restarted

2018-10-17 Thread Nayan Deshmukh

Patch 1 and 2 are Reviewed-by: Nayan Deshmukh 
On Wed, Oct 17, 2018 at 12:30 AM Grodzovsky, Andrey
 wrote:
>
> Patches 1-3 Reviewed-by: Andrey Grodzovsky 
>
> Patch 4 Acked-by: Andrey Grodzovsky 
>
> Andrey
>
>
> On 10/16/2018 07:55 AM, Christian König wrote:
> > Make sure we always restart the timer after a timeout and remove the
> > device specific workarounds.
> >
> > Signed-off-by: Christian König 
> > ---
> >   drivers/gpu/drm/etnaviv/etnaviv_sched.c | 2 --
> >   drivers/gpu/drm/scheduler/sched_main.c  | 1 +
> >   drivers/gpu/drm/v3d/v3d_sched.c | 3 ---
> >   3 files changed, 1 insertion(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/etnaviv/etnaviv_sched.c 
> > b/drivers/gpu/drm/etnaviv/etnaviv_sched.c
> > index e7c3ed6c9a2e..f8c5f1e6c5e2 100644
> > --- a/drivers/gpu/drm/etnaviv/etnaviv_sched.c
> > +++ b/drivers/gpu/drm/etnaviv/etnaviv_sched.c
> > @@ -105,8 +105,6 @@ static void etnaviv_sched_timedout_job(struct 
> > drm_sched_job *sched_job)
> >   change = dma_addr - gpu->hangcheck_dma_addr;
> >   if (change < 0 || change > 16) {
> >   gpu->hangcheck_dma_addr = dma_addr;
> > - schedule_delayed_work(_job->sched->work_tdr,
> > -   sched_job->sched->timeout);
> >   return;
> >   }
> >
> > diff --git a/drivers/gpu/drm/scheduler/sched_main.c 
> > b/drivers/gpu/drm/scheduler/sched_main.c
> > index 44fe587aaef9..73449c653b6e 100644
> > --- a/drivers/gpu/drm/scheduler/sched_main.c
> > +++ b/drivers/gpu/drm/scheduler/sched_main.c
> > @@ -283,6 +283,7 @@ static void drm_sched_job_timedout(struct work_struct 
> > *work)
> >   already_signaled:
> >   ;
> >   }
> > + drm_sched_start_timeout(sched);
> >   spin_unlock(>job_list_lock);
> >   }
> >
> > diff --git a/drivers/gpu/drm/v3d/v3d_sched.c 
> > b/drivers/gpu/drm/v3d/v3d_sched.c
> > index 9243dea6e6ad..80b641ffc3be 100644
> > --- a/drivers/gpu/drm/v3d/v3d_sched.c
> > +++ b/drivers/gpu/drm/v3d/v3d_sched.c
> > @@ -167,9 +167,6 @@ v3d_job_timedout(struct drm_sched_job *sched_job)
> >   if (job->timedout_ctca != ctca || job->timedout_ctra != ctra) {
> >   job->timedout_ctca = ctca;
> >   job->timedout_ctra = ctra;
> > -
> > - schedule_delayed_work(>base.sched->work_tdr,
> > -   job->base.sched->timeout);
> >   return;
> >   }
> >
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: regression on RV1

2018-10-17 Thread Deucher, Alexander

IIRC, APUs do not have a paging queue.  Only dGPUs have it.


Alex


From: amd-gfx  on behalf of StDenis, Tom 

Sent: Wednesday, October 17, 2018 11:54:33 AM
To: Koenig, Christian; amd-gfx mailing list
Cc: Huang, Ray
Subject: regression on RV1

This commit:

commit 6cbd074831a423e0d30b386fc056d6c2c3559147 (HEAD, refs/bisect/bad)
Author: Christian König 
Date:   Mon Oct 8 14:38:22 2018 +0200

 drm/amdgpu: activate paging queue on SDMA v4

 Implement all the necessary stuff to get those extra rings working.

 Signed-off-by: Christian König 
 Reviewed-by: Huang Rui 

Breaks my RV1 init.

Tom
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

regression on RV1

2018-10-17 Thread StDenis, Tom

This commit:

commit 6cbd074831a423e0d30b386fc056d6c2c3559147 (HEAD, refs/bisect/bad)
Author: Christian König 
Date:   Mon Oct 8 14:38:22 2018 +0200

 drm/amdgpu: activate paging queue on SDMA v4

 Implement all the necessary stuff to get those extra rings working.

 Signed-off-by: Christian König 
 Reviewed-by: Huang Rui 

Breaks my RV1 init.

Tom
[0.00] Linux version 4.19.0-rc1+ (root@raven) (gcc version 8.1.1 
20180712 (Red Hat 8.1.1-5) (GCC)) #36 SMP Mon Oct 15 11:34:58 EDT 2018
[0.00] Command line: BOOT_IMAGE=/vmlinuz-4.19.0-rc1+ 
root=UUID=66163c80-0ca1-4beb-aeba-5cc130b813e6 ro rhgb quiet 
modprobe.blacklist=amdgpu,radeon LANG=en_CA.UTF-8
[0.00] x86/fpu: Supporting XSAVE feature 0x001: 'x87 floating point 
registers'
[0.00] x86/fpu: Supporting XSAVE feature 0x002: 'SSE registers'
[0.00] x86/fpu: Supporting XSAVE feature 0x004: 'AVX registers'
[0.00] x86/fpu: xstate_offset[2]:  576, xstate_sizes[2]:  256
[0.00] x86/fpu: Enabled xstate features 0x7, context size is 832 bytes, 
using 'compacted' format.
[0.00] BIOS-provided physical RAM map:
[0.00] BIOS-e820: [mem 0x-0x0009d3ff] usable
[0.00] BIOS-e820: [mem 0x0009d400-0x0009] reserved
[0.00] BIOS-e820: [mem 0x000e-0x000f] reserved
[0.00] BIOS-e820: [mem 0x0010-0x03ff] usable
[0.00] BIOS-e820: [mem 0x0400-0x04009fff] ACPI NVS
[0.00] BIOS-e820: [mem 0x0400a000-0x09bf] usable
[0.00] BIOS-e820: [mem 0x09c0-0x09ff] reserved
[0.00] BIOS-e820: [mem 0x0a00-0x0aff] usable
[0.00] BIOS-e820: [mem 0x0b00-0x0b01] reserved
[0.00] BIOS-e820: [mem 0x0b02-0x73963fff] usable
[0.00] BIOS-e820: [mem 0x73964000-0x7397cfff] ACPI data
[0.00] BIOS-e820: [mem 0x7397d000-0x7a5aafff] usable
[0.00] BIOS-e820: [mem 0x7a5ab000-0x7a6c2fff] reserved
[0.00] BIOS-e820: [mem 0x7a6c3000-0x7a6cefff] ACPI data
[0.00] BIOS-e820: [mem 0x7a6cf000-0x7a7d1fff] usable
[0.00] BIOS-e820: [mem 0x7a7d2000-0x7ab89fff] ACPI NVS
[0.00] BIOS-e820: [mem 0x7ab8a000-0x7b942fff] reserved
[0.00] BIOS-e820: [mem 0x7b943000-0x7dff] usable
[0.00] BIOS-e820: [mem 0x7e00-0xbfff] reserved
[0.00] BIOS-e820: [mem 0xf800-0xfbff] reserved
[0.00] BIOS-e820: [mem 0xfd80-0xfdff] reserved
[0.00] BIOS-e820: [mem 0xfea0-0xfea0] reserved
[0.00] BIOS-e820: [mem 0xfeb8-0xfec01fff] reserved
[0.00] BIOS-e820: [mem 0xfec1-0xfec10fff] reserved
[0.00] BIOS-e820: [mem 0xfec3-0xfec30fff] reserved
[0.00] BIOS-e820: [mem 0xfed0-0xfed00fff] reserved
[0.00] BIOS-e820: [mem 0xfed4-0xfed44fff] reserved
[0.00] BIOS-e820: [mem 0xfed8-0xfed8] reserved
[0.00] BIOS-e820: [mem 0xfedc2000-0xfedc] reserved
[0.00] BIOS-e820: [mem 0xfedd4000-0xfedd5fff] reserved
[0.00] BIOS-e820: [mem 0xfee0-0xfeef] reserved
[0.00] BIOS-e820: [mem 0xff00-0x] reserved
[0.00] BIOS-e820: [mem 0x0001-0x00023f33] usable
[0.00] NX (Execute Disable) protection: active
[0.00] SMBIOS 3.1.1 present.
[0.00] DMI: System manufacturer System Product Name/TUF B350M-PLUS 
GAMING, BIOS 4011 04/19/2018
[0.00] tsc: Fast TSC calibration failed
[0.00] e820: update [mem 0x-0x0fff] usable ==> reserved
[0.00] e820: remove [mem 0x000a-0x000f] usable
[0.00] last_pfn = 0x23f340 max_arch_pfn = 0x4
[0.00] MTRR default type: uncachable
[0.00] MTRR fixed ranges enabled:
[0.00]   0-9 write-back
[0.00]   A-B write-through
[0.00]   C-F write-protect
[0.00] MTRR variable ranges enabled:
[0.00]   0 base  mask 8000 write-back
[0.00]   1 base 8000 mask C000 write-back
[0.00]   2 disabled
[0.00]   3 disabled
[0.00]   4 disabled
[0.00]   5 disabled
[0.00]   6 disabled
[0.00]   7 disabled
[0.00] TOM2: 00024000 aka 9216M
[0.00] x86/PAT: Configuration [0-7]: WB  WC  UC- UC  WB  WP  UC- WT  
[0.00] e820: update [mem 0xc000-0x] usable ==> reserved
[0.00] last_pfn = 0x7e000 max_arch_pfn =

Re: [PATCH] drm/amd/powerplay: error out when force clock level under auto dpm mode V2

2018-10-17 Thread Deucher, Alexander

Reviewed-by: Alex Deucher 


From: Evan Quan 
Sent: Wednesday, October 17, 2018 5:21:54 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhu, Rex; Deucher, Alexander; Quan, Evan
Subject: [PATCH] drm/amd/powerplay: error out when force clock level under auto 
dpm mode V2

Forcing clock level is supported under manual dpm mode only. Error out
when trying to set under manual mode. Instead of doing nothing and
reporting success.

V2: update for mclk/pcie clock level settings also

Change-Id: I2af32be5ebd4323a98cb48da88b22177a68fbdb0
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c| 15 ---
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 11 +++
 2 files changed, 19 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 94055a485e01..59cc678de8c1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -704,7 +704,10 @@ static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
 return ret;

 if (adev->powerplay.pp_funcs->force_clock_level)
-   amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
+   ret = amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
+
+   if (ret)
+   return -EINVAL;

 return count;
 }
@@ -737,7 +740,10 @@ static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
 return ret;

 if (adev->powerplay.pp_funcs->force_clock_level)
-   amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
+   ret = amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
+
+   if (ret)
+   return -EINVAL;

 return count;
 }
@@ -770,7 +776,10 @@ static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
 return ret;

 if (adev->powerplay.pp_funcs->force_clock_level)
-   amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
+   ret = amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
+
+   if (ret)
+   return -EINVAL;

 return count;
 }
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c 
b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index e8964cae6b93..da9ff2cc2777 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -723,11 +723,14 @@ static int pp_dpm_force_clock_level(void *handle,
 pr_info("%s was not implemented.\n", __func__);
 return 0;
 }
+
+   if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
+   pr_info("force clock level is for dpm manual mode only.\n");
+   return -EINVAL;
+   }
+
 mutex_lock(>smu_lock);
-   if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)
-   ret = hwmgr->hwmgr_func->force_clock_level(hwmgr, type, mask);
-   else
-   ret = -EINVAL;
+   ret = hwmgr->hwmgr_func->force_clock_level(hwmgr, type, mask);
 mutex_unlock(>smu_lock);
 return ret;
 }
--
2.19.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm/amd/powerplay: error out when force clock level under auto dpm mode

2018-10-17 Thread Deucher, Alexander

Reviewed-by: Alex Deucher 


From: amd-gfx  on behalf of Evan Quan 

Sent: Wednesday, October 17, 2018 4:41:16 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander; Quan, Evan; Zhu, Rex
Subject: [PATCH] drm/amd/powerplay: error out when force clock level under auto 
dpm mode

Forcing clock level is supported under manual dpm mode only. Error out
when trying to set under manual mode. Instead of doing nothing and
reporting success.

Change-Id: I2af32be5ebd4323a98cb48da88b22177a68fbdb0
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c|  5 -
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 11 +++
 2 files changed, 11 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 94055a485e01..c2efd79d9a39 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -704,7 +704,10 @@ static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
 return ret;

 if (adev->powerplay.pp_funcs->force_clock_level)
-   amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
+   ret = amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
+
+   if (ret)
+   return -EINVAL;

 return count;
 }
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c 
b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index e8964cae6b93..da9ff2cc2777 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -723,11 +723,14 @@ static int pp_dpm_force_clock_level(void *handle,
 pr_info("%s was not implemented.\n", __func__);
 return 0;
 }
+
+   if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
+   pr_info("force clock level is for dpm manual mode only.\n");
+   return -EINVAL;
+   }
+
 mutex_lock(>smu_lock);
-   if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)
-   ret = hwmgr->hwmgr_func->force_clock_level(hwmgr, type, mask);
-   else
-   ret = -EINVAL;
+   ret = hwmgr->hwmgr_func->force_clock_level(hwmgr, type, mask);
 mutex_unlock(>smu_lock);
 return ret;
 }
--
2.19.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 2/7] drm: add syncobj timeline support v8

2018-10-17 Thread zhoucm1


+Jason as well.


On 2018年10月17日 18:22, Daniel Vetter wrote:

On Wed, Oct 17, 2018 at 11:17 AM zhoucm1  wrote:



On 2018年10月17日 16:09, Daniel Vetter wrote:

On Mon, Oct 15, 2018 at 04:55:48PM +0800, Chunming Zhou wrote:

This patch is for VK_KHR_timeline_semaphore extension, semaphore is called 
syncobj in kernel side:
This extension introduces a new type of syncobj that has an integer payload
identifying a point in a timeline. Such timeline syncobjs support the
following operations:
 * CPU query - A host operation that allows querying the payload of the
   timeline syncobj.
 * CPU wait - A host operation that allows a blocking wait for a
   timeline syncobj to reach a specified value.
 * Device wait - A device operation that allows waiting for a
   timeline syncobj to reach a specified value.
 * Device signal - A device operation that allows advancing the
   timeline syncobj to a specified value.

v1:
Since it's a timeline, that means the front time point(PT) always is signaled 
before the late PT.
a. signal PT design:
Signal PT fence N depends on PT[N-1] fence and signal opertion fence, when 
PT[N] fence is signaled,
the timeline will increase to value of PT[N].
b. wait PT design:
Wait PT fence is signaled by reaching timeline point value, when timeline is 
increasing, will compare
wait PTs value with new timeline value, if PT value is lower than timeline 
value, then wait PT will be
signaled, otherwise keep in list. syncobj wait operation can wait on any point 
of timeline,
so need a RB tree to order them. And wait PT could ahead of signal PT, we need 
a sumission fence to
perform that.

v2:
1. remove unused DRM_SYNCOBJ_CREATE_TYPE_NORMAL. (Christian)
2. move unexposed denitions to .c file. (Daniel Vetter)
3. split up the change to drm_syncobj_find_fence() in a separate patch. 
(Christian)
4. split up the change to drm_syncobj_replace_fence() in a separate patch.
5. drop the submission_fence implementation and instead use wait_event() for 
that. (Christian)
6. WARN_ON(point != 0) for NORMAL type syncobj case. (Daniel Vetter)

v3:
1. replace normal syncobj with timeline implemenation. (Vetter and Christian)
  a. normal syncobj signal op will create a signal PT to tail of signal pt 
list.
  b. normal syncobj wait op will create a wait pt with last signal point, 
and this wait PT is only signaled by related signal point PT.
2. many bug fix and clean up
3. stub fence moving is moved to other patch.

v4：
1. fix RB tree loop with while(node=rb_first(...)). (Christian)
2. fix syncobj lifecycle. (Christian)
3. only enable_signaling when there is wait_pt. (Christian)
4. fix timeline path issues.
5. write a timeline test in libdrm

v5: (Christian)
1. semaphore is called syncobj in kernel side.
2. don't need 'timeline' characters in some function name.
3. keep syncobj cb.

v6: (Christian)
1. merge syncobj_timeline to syncobj structure.
2. simplify some check sentences.
3. some misc change.
4. fix CTS failed issue.

v7: (Christian)
1. error handling when creating signal pt.
2. remove timeline naming in func.
3. export flags in find_fence.
4. allow reset timeline.

v8:
1. use wait_event_interruptible without timeout
2. rename _TYPE_INDIVIDUAL to _TYPE_BINARY

individual syncobj is tested by ./deqp-vk -n dEQP-VK*semaphore*
timeline syncobj is tested by ./amdgpu_test -s 9

Can we please have these low-level syncobj tests as part of igt, together
with all the other syncobj tests which are there already?

Good suggestion first, I'm just not familiar with igt( build, run
cmd...), maybe we can add it later.


Really doesn't
make much sense imo to splits things on the test suite front.

Signed-off-by: Chunming Zhou 
Cc: Christian Konig 
Cc: Dave Airlie 
Cc: Daniel Rakos 
Cc: Daniel Vetter 
Reviewed-by: Christian König 
---
   drivers/gpu/drm/drm_syncobj.c  | 287 ++---
   drivers/gpu/drm/i915/i915_gem_execbuffer.c |   2 +-
   include/drm/drm_syncobj.h  |  65 ++---
   include/uapi/drm/drm.h |   1 +
   4 files changed, 281 insertions(+), 74 deletions(-)

diff --git a/drivers/gpu/drm/drm_syncobj.c b/drivers/gpu/drm/drm_syncobj.c
index f796c9fc3858..67472bd77c83 100644
--- a/drivers/gpu/drm/drm_syncobj.c
+++ b/drivers/gpu/drm/drm_syncobj.c
@@ -56,6 +56,9 @@
   #include "drm_internal.h"
   #include 

+/* merge normal syncobj to timeline syncobj, the point interval is 1 */
+#define DRM_SYNCOBJ_BINARY_POINT 1
+
   struct drm_syncobj_stub_fence {
  struct dma_fence base;
  spinlock_t lock;
@@ -82,6 +85,11 @@ static const struct dma_fence_ops drm_syncobj_stub_fence_ops 
= {
  .release = drm_syncobj_stub_fence_release,
   };

+struct drm_syncobj_signal_pt {
+struct dma_fence_array *base;

Out of curiosity, why the pointer and not embedding? base is kinda
misleading for a pointer.

Yeah, Christian doesn't like signal_pt lifecycle same as fence, so it's
a pointer.
If you don't like 'base' name, I can change it.


+

Re: [PATCH 2/7] drm: add syncobj timeline support v8

2018-10-17 Thread Daniel Vetter

On Wed, Oct 17, 2018 at 11:29 AM Koenig, Christian
 wrote:
>
> Am 17.10.18 um 11:17 schrieb zhoucm1:
> > [SNIP]
> >>>   +struct drm_syncobj_signal_pt {
> >>> +struct dma_fence_array *base;
> >> Out of curiosity, why the pointer and not embedding? base is kinda
> >> misleading for a pointer.
> > Yeah, Christian doesn't like signal_pt lifecycle same as fence, so
> > it's a pointer.
> > If you don't like 'base' name, I can change it.
>
> Well I never said that you can't embed the fence array into the signal_pt.
>
> You just need to make sure that we don't affect the drm_syncobj
> lilecycle as well, e.g. that we don't also need to keep that around.

I don't see a problem with that, as long as drm_syncobj keeps a
reference to the fence while it's on the timeline list. Which it
already does. And embedding would avoid that 2nd separate allocation,
aside from making base less confusing.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 2/7] drm: add syncobj timeline support v8

2018-10-17 Thread Daniel Vetter

On Wed, Oct 17, 2018 at 11:17 AM zhoucm1  wrote:
>
>
>
> On 2018年10月17日 16:09, Daniel Vetter wrote:
> > On Mon, Oct 15, 2018 at 04:55:48PM +0800, Chunming Zhou wrote:
> >> This patch is for VK_KHR_timeline_semaphore extension, semaphore is called 
> >> syncobj in kernel side:
> >> This extension introduces a new type of syncobj that has an integer payload
> >> identifying a point in a timeline. Such timeline syncobjs support the
> >> following operations:
> >> * CPU query - A host operation that allows querying the payload of the
> >>   timeline syncobj.
> >> * CPU wait - A host operation that allows a blocking wait for a
> >>   timeline syncobj to reach a specified value.
> >> * Device wait - A device operation that allows waiting for a
> >>   timeline syncobj to reach a specified value.
> >> * Device signal - A device operation that allows advancing the
> >>   timeline syncobj to a specified value.
> >>
> >> v1:
> >> Since it's a timeline, that means the front time point(PT) always is 
> >> signaled before the late PT.
> >> a. signal PT design:
> >> Signal PT fence N depends on PT[N-1] fence and signal opertion fence, when 
> >> PT[N] fence is signaled,
> >> the timeline will increase to value of PT[N].
> >> b. wait PT design:
> >> Wait PT fence is signaled by reaching timeline point value, when timeline 
> >> is increasing, will compare
> >> wait PTs value with new timeline value, if PT value is lower than timeline 
> >> value, then wait PT will be
> >> signaled, otherwise keep in list. syncobj wait operation can wait on any 
> >> point of timeline,
> >> so need a RB tree to order them. And wait PT could ahead of signal PT, we 
> >> need a sumission fence to
> >> perform that.
> >>
> >> v2:
> >> 1. remove unused DRM_SYNCOBJ_CREATE_TYPE_NORMAL. (Christian)
> >> 2. move unexposed denitions to .c file. (Daniel Vetter)
> >> 3. split up the change to drm_syncobj_find_fence() in a separate patch. 
> >> (Christian)
> >> 4. split up the change to drm_syncobj_replace_fence() in a separate patch.
> >> 5. drop the submission_fence implementation and instead use wait_event() 
> >> for that. (Christian)
> >> 6. WARN_ON(point != 0) for NORMAL type syncobj case. (Daniel Vetter)
> >>
> >> v3:
> >> 1. replace normal syncobj with timeline implemenation. (Vetter and 
> >> Christian)
> >>  a. normal syncobj signal op will create a signal PT to tail of signal 
> >> pt list.
> >>  b. normal syncobj wait op will create a wait pt with last signal 
> >> point, and this wait PT is only signaled by related signal point PT.
> >> 2. many bug fix and clean up
> >> 3. stub fence moving is moved to other patch.
> >>
> >> v4：
> >> 1. fix RB tree loop with while(node=rb_first(...)). (Christian)
> >> 2. fix syncobj lifecycle. (Christian)
> >> 3. only enable_signaling when there is wait_pt. (Christian)
> >> 4. fix timeline path issues.
> >> 5. write a timeline test in libdrm
> >>
> >> v5: (Christian)
> >> 1. semaphore is called syncobj in kernel side.
> >> 2. don't need 'timeline' characters in some function name.
> >> 3. keep syncobj cb.
> >>
> >> v6: (Christian)
> >> 1. merge syncobj_timeline to syncobj structure.
> >> 2. simplify some check sentences.
> >> 3. some misc change.
> >> 4. fix CTS failed issue.
> >>
> >> v7: (Christian)
> >> 1. error handling when creating signal pt.
> >> 2. remove timeline naming in func.
> >> 3. export flags in find_fence.
> >> 4. allow reset timeline.
> >>
> >> v8:
> >> 1. use wait_event_interruptible without timeout
> >> 2. rename _TYPE_INDIVIDUAL to _TYPE_BINARY
> >>
> >> individual syncobj is tested by ./deqp-vk -n dEQP-VK*semaphore*
> >> timeline syncobj is tested by ./amdgpu_test -s 9
> > Can we please have these low-level syncobj tests as part of igt, together
> > with all the other syncobj tests which are there already?
> Good suggestion first, I'm just not familiar with igt( build, run
> cmd...), maybe we can add it later.
>
> > Really doesn't
> > make much sense imo to splits things on the test suite front.
> >> Signed-off-by: Chunming Zhou 
> >> Cc: Christian Konig 
> >> Cc: Dave Airlie 
> >> Cc: Daniel Rakos 
> >> Cc: Daniel Vetter 
> >> Reviewed-by: Christian König 
> >> ---
> >>   drivers/gpu/drm/drm_syncobj.c  | 287 ++---
> >>   drivers/gpu/drm/i915/i915_gem_execbuffer.c |   2 +-
> >>   include/drm/drm_syncobj.h  |  65 ++---
> >>   include/uapi/drm/drm.h |   1 +
> >>   4 files changed, 281 insertions(+), 74 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/drm_syncobj.c b/drivers/gpu/drm/drm_syncobj.c
> >> index f796c9fc3858..67472bd77c83 100644
> >> --- a/drivers/gpu/drm/drm_syncobj.c
> >> +++ b/drivers/gpu/drm/drm_syncobj.c
> >> @@ -56,6 +56,9 @@
> >>   #include "drm_internal.h"
> >>   #include 
> >>
> >> +/* merge normal syncobj to timeline syncobj, the point interval is 1 */
> >> +#define DRM_SYNCOBJ_BINARY_POINT 1
> >> +
> >>   struct drm_syncobj_stub_fence {
> >>  struct

Re: [PATCH 2/7] drm: add syncobj timeline support v8

2018-10-17 Thread Koenig, Christian

Am 17.10.18 um 11:17 schrieb zhoucm1:
> [SNIP]
>>>   +struct drm_syncobj_signal_pt {
>>> +    struct dma_fence_array *base;
>> Out of curiosity, why the pointer and not embedding? base is kinda
>> misleading for a pointer.
> Yeah, Christian doesn't like signal_pt lifecycle same as fence, so 
> it's a pointer.
> If you don't like 'base' name, I can change it.

Well I never said that you can't embed the fence array into the signal_pt.

You just need to make sure that we don't affect the drm_syncobj 
lilecycle as well, e.g. that we don't also need to keep that around.

Regards,
Christian.
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH] drm/amd/powerplay: error out when force clock level under auto dpm mode V2

2018-10-17 Thread Evan Quan

Forcing clock level is supported under manual dpm mode only. Error out
when trying to set under manual mode. Instead of doing nothing and
reporting success.

V2: update for mclk/pcie clock level settings also

Change-Id: I2af32be5ebd4323a98cb48da88b22177a68fbdb0
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c| 15 ---
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 11 +++
 2 files changed, 19 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 94055a485e01..59cc678de8c1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -704,7 +704,10 @@ static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
return ret;
 
if (adev->powerplay.pp_funcs->force_clock_level)
-   amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
+   ret = amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
+
+   if (ret)
+   return -EINVAL;
 
return count;
 }
@@ -737,7 +740,10 @@ static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
return ret;
 
if (adev->powerplay.pp_funcs->force_clock_level)
-   amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
+   ret = amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
+
+   if (ret)
+   return -EINVAL;
 
return count;
 }
@@ -770,7 +776,10 @@ static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
return ret;
 
if (adev->powerplay.pp_funcs->force_clock_level)
-   amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
+   ret = amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
+
+   if (ret)
+   return -EINVAL;
 
return count;
 }
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c 
b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index e8964cae6b93..da9ff2cc2777 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -723,11 +723,14 @@ static int pp_dpm_force_clock_level(void *handle,
pr_info("%s was not implemented.\n", __func__);
return 0;
}
+
+   if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
+   pr_info("force clock level is for dpm manual mode only.\n");
+   return -EINVAL;
+   }
+
mutex_lock(>smu_lock);
-   if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)
-   ret = hwmgr->hwmgr_func->force_clock_level(hwmgr, type, mask);
-   else
-   ret = -EINVAL;
+   ret = hwmgr->hwmgr_func->force_clock_level(hwmgr, type, mask);
mutex_unlock(>smu_lock);
return ret;
 }
-- 
2.19.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 2/7] drm: add syncobj timeline support v8

2018-10-17 Thread zhoucm1




On 2018年10月17日 16:09, Daniel Vetter wrote:

On Mon, Oct 15, 2018 at 04:55:48PM +0800, Chunming Zhou wrote:

This patch is for VK_KHR_timeline_semaphore extension, semaphore is called 
syncobj in kernel side:
This extension introduces a new type of syncobj that has an integer payload
identifying a point in a timeline. Such timeline syncobjs support the
following operations:
* CPU query - A host operation that allows querying the payload of the
  timeline syncobj.
* CPU wait - A host operation that allows a blocking wait for a
  timeline syncobj to reach a specified value.
* Device wait - A device operation that allows waiting for a
  timeline syncobj to reach a specified value.
* Device signal - A device operation that allows advancing the
  timeline syncobj to a specified value.

v1:
Since it's a timeline, that means the front time point(PT) always is signaled 
before the late PT.
a. signal PT design:
Signal PT fence N depends on PT[N-1] fence and signal opertion fence, when 
PT[N] fence is signaled,
the timeline will increase to value of PT[N].
b. wait PT design:
Wait PT fence is signaled by reaching timeline point value, when timeline is 
increasing, will compare
wait PTs value with new timeline value, if PT value is lower than timeline 
value, then wait PT will be
signaled, otherwise keep in list. syncobj wait operation can wait on any point 
of timeline,
so need a RB tree to order them. And wait PT could ahead of signal PT, we need 
a sumission fence to
perform that.

v2:
1. remove unused DRM_SYNCOBJ_CREATE_TYPE_NORMAL. (Christian)
2. move unexposed denitions to .c file. (Daniel Vetter)
3. split up the change to drm_syncobj_find_fence() in a separate patch. 
(Christian)
4. split up the change to drm_syncobj_replace_fence() in a separate patch.
5. drop the submission_fence implementation and instead use wait_event() for 
that. (Christian)
6. WARN_ON(point != 0) for NORMAL type syncobj case. (Daniel Vetter)

v3:
1. replace normal syncobj with timeline implemenation. (Vetter and Christian)
 a. normal syncobj signal op will create a signal PT to tail of signal pt 
list.
 b. normal syncobj wait op will create a wait pt with last signal point, 
and this wait PT is only signaled by related signal point PT.
2. many bug fix and clean up
3. stub fence moving is moved to other patch.

v4：
1. fix RB tree loop with while(node=rb_first(...)). (Christian)
2. fix syncobj lifecycle. (Christian)
3. only enable_signaling when there is wait_pt. (Christian)
4. fix timeline path issues.
5. write a timeline test in libdrm

v5: (Christian)
1. semaphore is called syncobj in kernel side.
2. don't need 'timeline' characters in some function name.
3. keep syncobj cb.

v6: (Christian)
1. merge syncobj_timeline to syncobj structure.
2. simplify some check sentences.
3. some misc change.
4. fix CTS failed issue.

v7: (Christian)
1. error handling when creating signal pt.
2. remove timeline naming in func.
3. export flags in find_fence.
4. allow reset timeline.

v8:
1. use wait_event_interruptible without timeout
2. rename _TYPE_INDIVIDUAL to _TYPE_BINARY

individual syncobj is tested by ./deqp-vk -n dEQP-VK*semaphore*
timeline syncobj is tested by ./amdgpu_test -s 9

Can we please have these low-level syncobj tests as part of igt, together
with all the other syncobj tests which are there already?
Good suggestion first, I'm just not familiar with igt( build, run 
cmd...), maybe we can add it later.



Really doesn't
make much sense imo to splits things on the test suite front.

Signed-off-by: Chunming Zhou 
Cc: Christian Konig 
Cc: Dave Airlie 
Cc: Daniel Rakos 
Cc: Daniel Vetter 
Reviewed-by: Christian König 
---
  drivers/gpu/drm/drm_syncobj.c  | 287 ++---
  drivers/gpu/drm/i915/i915_gem_execbuffer.c |   2 +-
  include/drm/drm_syncobj.h  |  65 ++---
  include/uapi/drm/drm.h |   1 +
  4 files changed, 281 insertions(+), 74 deletions(-)

diff --git a/drivers/gpu/drm/drm_syncobj.c b/drivers/gpu/drm/drm_syncobj.c
index f796c9fc3858..67472bd77c83 100644
--- a/drivers/gpu/drm/drm_syncobj.c
+++ b/drivers/gpu/drm/drm_syncobj.c
@@ -56,6 +56,9 @@
  #include "drm_internal.h"
  #include 
  
+/* merge normal syncobj to timeline syncobj, the point interval is 1 */

+#define DRM_SYNCOBJ_BINARY_POINT 1
+
  struct drm_syncobj_stub_fence {
struct dma_fence base;
spinlock_t lock;
@@ -82,6 +85,11 @@ static const struct dma_fence_ops drm_syncobj_stub_fence_ops 
= {
.release = drm_syncobj_stub_fence_release,
  };
  
+struct drm_syncobj_signal_pt {

+   struct dma_fence_array *base;

Out of curiosity, why the pointer and not embedding? base is kinda
misleading for a pointer.
Yeah, Christian doesn't like signal_pt lifecycle same as fence, so it's 
a pointer.

If you don't like 'base' name, I can change it.




+   u64value;
+   struct list_head list;
+};
  
  /**

   * drm_syncobj_find - lookup and reference a

[PATCH] drm/amdgpu: disable VCE after resume on Stoney

2018-10-17 Thread Christian König

VCE on Stoney seems to have problems after the first suspend/resume
cycle. Disable it before we destabilize the whole driver.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 12 +++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c 
b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
index 6dbd39730070..cf2bda5bb2ee 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
@@ -517,13 +517,23 @@ static int vce_v3_0_suspend(void *handle)
 
 static int vce_v3_0_resume(void *handle)
 {
-   int r;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+   int i, r;
 
r = amdgpu_vce_resume(adev);
if (r)
return r;
 
+   /* TODO: VCE has problems resuming on Stoney. Disable the whole block
+* instead of risking to destabilize the driver
+*/
+   if (adev->asic_type == CHIP_STONEY) {
+   for (i = 0; i < AMDGPU_MAX_VCE_RINGS; ++i)
+   adev->vce.ring[i].ready = false;
+
+   return 0;
+   }
+
return vce_v3_0_hw_init(adev);
 }
 
-- 
2.14.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH] drm/amd/powerplay: error out when force clock level under auto dpm mode

2018-10-17 Thread Evan Quan

Forcing clock level is supported under manual dpm mode only. Error out
when trying to set under manual mode. Instead of doing nothing and
reporting success.

Change-Id: I2af32be5ebd4323a98cb48da88b22177a68fbdb0
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c|  5 -
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 11 +++
 2 files changed, 11 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 94055a485e01..c2efd79d9a39 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -704,7 +704,10 @@ static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
return ret;
 
if (adev->powerplay.pp_funcs->force_clock_level)
-   amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
+   ret = amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
+
+   if (ret)
+   return -EINVAL;
 
return count;
 }
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c 
b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index e8964cae6b93..da9ff2cc2777 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -723,11 +723,14 @@ static int pp_dpm_force_clock_level(void *handle,
pr_info("%s was not implemented.\n", __func__);
return 0;
}
+
+   if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
+   pr_info("force clock level is for dpm manual mode only.\n");
+   return -EINVAL;
+   }
+
mutex_lock(>smu_lock);
-   if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)
-   ret = hwmgr->hwmgr_func->force_clock_level(hwmgr, type, mask);
-   else
-   ret = -EINVAL;
+   ret = hwmgr->hwmgr_func->force_clock_level(hwmgr, type, mask);
mutex_unlock(>smu_lock);
return ret;
 }
-- 
2.19.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH v2 04/10] drm/amd/display: dc/bios: add support for DCE6

2018-10-17 Thread Mauro Rossi

DCE6 targets are added replicating existing DCE8 implementation.
---
 drivers/gpu/drm/amd/display/dc/bios/Makefile  |   9 +
 .../display/dc/bios/command_table_helper.c|   8 +
 .../display/dc/bios/command_table_helper.h|   3 +
 .../display/dc/bios/command_table_helper2.c   |   8 +
 .../display/dc/bios/command_table_helper2.h   |   3 +
 .../bios/dce60/command_table_helper_dce60.c   | 354 ++
 .../bios/dce60/command_table_helper_dce60.h   |  33 ++
 7 files changed, 418 insertions(+)
 create mode 100644 
drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c
 create mode 100644 
drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.h

diff --git a/drivers/gpu/drm/amd/display/dc/bios/Makefile 
b/drivers/gpu/drm/amd/display/dc/bios/Makefile
index 239e86bbec5a..ed6b5e9763f6 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/bios/Makefile
@@ -31,6 +31,15 @@ AMD_DAL_BIOS = $(addprefix $(AMDDALPATH)/dc/bios/,$(BIOS))
 
 AMD_DISPLAY_FILES += $(AMD_DAL_BIOS)
 
+###
+# DCE 6x
+###
+# All DCE6.x are derived from DCE6.0, so 6.0 MUST be defined if ANY of
+# DCE6.x is compiled.
+ifdef CONFIG_DRM_AMD_DC_SI
+AMD_DISPLAY_FILES += $(AMDDALPATH)/dc/bios/dce60/command_table_helper_dce60.o
+endif
+
 ###
 # DCE 8x
 ###
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c 
b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c
index 253bbb1eea60..48b4ef03fc8f 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c
@@ -36,6 +36,14 @@ bool dal_bios_parser_init_cmd_tbl_helper(
enum dce_version dce)
 {
switch (dce) {
+#if defined(CONFIG_DRM_AMD_DC_SI)
+   case DCE_VERSION_6_0:
+   case DCE_VERSION_6_1:
+   case DCE_VERSION_6_4:
+   *h = dal_cmd_tbl_helper_dce60_get_table();
+   return true;
+#endif
+
case DCE_VERSION_8_0:
case DCE_VERSION_8_1:
case DCE_VERSION_8_3:
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h 
b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h
index 4c3789df253d..dfd30aaf4032 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h
@@ -26,6 +26,9 @@
 #ifndef __DAL_COMMAND_TABLE_HELPER_H__
 #define __DAL_COMMAND_TABLE_HELPER_H__
 
+#if defined(CONFIG_DRM_AMD_DC_SI)
+#include "dce60/command_table_helper_dce60.h"
+#endif
 #include "dce80/command_table_helper_dce80.h"
 #include "dce110/command_table_helper_dce110.h"
 #include "dce112/command_table_helper_dce112.h"
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c 
b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
index 65b006ad372e..92288c582934 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
@@ -37,6 +37,14 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
enum dce_version dce)
 {
switch (dce) {
+#if defined(CONFIG_DRM_AMD_DC_SI)
+   case DCE_VERSION_6_0:
+   case DCE_VERSION_6_1:
+   case DCE_VERSION_6_4:
+   *h = dal_cmd_tbl_helper_dce60_get_table();
+   return true;
+#endif
+
case DCE_VERSION_8_0:
case DCE_VERSION_8_1:
case DCE_VERSION_8_3:
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h 
b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h
index 785fcb20a1b9..66e0a3e73768 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h
@@ -26,6 +26,9 @@
 #ifndef __DAL_COMMAND_TABLE_HELPER2_H__
 #define __DAL_COMMAND_TABLE_HELPER2_H__
 
+#if defined(CONFIG_DRM_AMD_DC_SI)
+#include "dce60/command_table_helper_dce60.h"
+#endif
 #include "dce80/command_table_helper_dce80.h"
 #include "dce110/command_table_helper_dce110.h"
 #include "dce112/command_table_helper2_dce112.h"
diff --git 
a/drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c 
b/drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c
new file mode 100644
index ..552778ce9835
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c
@@ -0,0 +1,354 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the

[PATCH v2 01/10] drm/amd/display: add asics info for SI parts

2018-10-17 Thread Mauro Rossi

Asics info retrieved from si_id.h in https://github.com/GPUOpen-Tools/CodeXL

Tree path:
./CodeXL/Components/ShaderAnalyzer/AMDTBackEnd/Include/Common/asic_reg/si_id.h
---
 .../gpu/drm/amd/display/include/dal_asic_id.h | 40 +++
 .../gpu/drm/amd/display/include/dal_types.h   |  3 ++
 2 files changed, 43 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h 
b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
index 4f501ddcfb8d..5b600c9445bd 100644
--- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
+++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
@@ -30,6 +30,34 @@
  * ASIC internal revision ID
  */
 
+/* DCE60 (based on si_id.h in GPUOpen-Tools CodeXL) */
+#define SI_TAHITI_P_A00x01
+#define SI_TAHITI_P_B00x05
+#define SI_TAHITI_P_B10x06
+#define SI_PITCAIRN_PM_A0 0x14
+#define SI_PITCAIRN_PM_A1 0x15
+#define SI_CAPEVERDE_M_A0 0x28
+#define SI_CAPEVERDE_M_A1 0x29
+#define SI_OLAND_M_A0 0x3C
+#define SI_HAINAN_V_A00x46
+
+#define SI_UNKNOWN0xFF
+
+#define ASIC_REV_IS_TAHITI_P(rev) \
+   ((rev >= SI_TAHITI_P_A0) && (rev < SI_PITCAIRN_PM_A0))
+
+#define ASIC_REV_IS_PITCAIRN_PM(rev) \
+   ((rev >= SI_PITCAIRN_PM_A0) && (rev < SI_CAPEVERDE_M_A0))
+
+#define ASIC_REV_IS_CAPEVERDE_M(rev) \
+   ((rev >= SI_CAPEVERDE_M_A0) && (rev < SI_OLAND_M_A0))
+
+#define ASIC_REV_IS_OLAND_M(rev) \
+   ((rev >= SI_OLAND_M_A0) && (rev < SI_HAINAN_V_A0))
+
+#define ASIC_REV_IS_HAINAN_V(rev) \
+   ((rev >= SI_HAINAN_V_A0) && (rev < SI_UNKNOWN))
+
 /* DCE80 (based on ci_id.h in Perforce) */
 #defineCI_BONAIRE_M_A0 0x14
 #defineCI_BONAIRE_M_A1 0x15
@@ -150,12 +178,24 @@
 /*
  * ASIC chip ID
  */
+
+/* DCE60 */
+#define DEVICE_ID_SI_TAHITI_P_6780 0x6780
+#define DEVICE_ID_SI_PITCAIRN_PM_6800 0x6800
+#define DEVICE_ID_SI_PITCAIRN_PM_6808 0x6808
+#define DEVICE_ID_SI_CAPEVERDE_M_6820 0x6820
+#define DEVICE_ID_SI_CAPEVERDE_M_6828 0x6828
+#define DEVICE_ID_SI_OLAND_M_6600 0x6600
+#define DEVICE_ID_SI_OLAND_M_6608 0x6608
+#define DEVICE_ID_SI_HAINAN_V_6660 0x6660
+
 /* DCE80 */
 #define DEVICE_ID_KALINDI_9834 0x9834
 #define DEVICE_ID_TEMASH_9839 0x9839
 #define DEVICE_ID_TEMASH_983D 0x983D
 
 /* Asic Family IDs for different asic family. */
+#define FAMILY_SI 110 /* Southern Islands: Tahiti (P), Pitcairn (PM), Cape 
Verde (M), Oland (M), Hainan (V) */
 #define FAMILY_CI 120 /* Sea Islands: Hawaii (P), Bonaire (M) */
 #define FAMILY_KV 125 /* Fusion => Kaveri: Spectre, Spooky; Kabini: Kalindi */
 #define FAMILY_VI 130 /* Volcanic Islands: Iceland (V), Tonga (M) */
diff --git a/drivers/gpu/drm/amd/display/include/dal_types.h 
b/drivers/gpu/drm/amd/display/include/dal_types.h
index 89627133e188..c79f42544aae 100644
--- a/drivers/gpu/drm/amd/display/include/dal_types.h
+++ b/drivers/gpu/drm/amd/display/include/dal_types.h
@@ -34,6 +34,9 @@ struct dc_bios;
 
 enum dce_version {
DCE_VERSION_UNKNOWN = (-1),
+   DCE_VERSION_6_0,
+   DCE_VERSION_6_1,
+   DCE_VERSION_6_4,
DCE_VERSION_8_0,
DCE_VERSION_8_1,
DCE_VERSION_8_3,
-- 
2.17.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH v2 02/10] drm/amd/display: dc/dce: add DCE6 support (v2)

2018-10-17 Thread Mauro Rossi

DCE6 targets are added replicating existing DCE8 implementation.

NOTE: dce_8_0_{d,sh_mask}.h headers used instead of dce_6_0_{d,sh_mask}.h
only to build dce60_resource.c due to missing *_DCE60 macros/registers/masks

IMPORTANT: Coding of dce60_resource.c requires review to understand
if dce_6_0_{d,sh_mask}.h should be updated with macros/registers/masks

(v2) updated dce60_{hw_sequencer,resources}.c as per amd-staging-drm-next
 removed dce_version cases in dc/dce/dce_clock_source.c
---
 drivers/gpu/drm/amd/display/dc/Makefile   |4 +
 drivers/gpu/drm/amd/display/dc/dce60/Makefile |   34 +
 .../amd/display/dc/dce60/dce60_hw_sequencer.c |   82 +
 .../amd/display/dc/dce60/dce60_hw_sequencer.h |   36 +
 .../drm/amd/display/dc/dce60/dce60_resource.c | 1458 +
 .../drm/amd/display/dc/dce60/dce60_resource.h |   47 +
 .../display/dc/dce60/dce60_timing_generator.c |  242 +++
 .../display/dc/dce60/dce60_timing_generator.h |   39 +
 .../include/asic_reg/dce/dce_6_0_sh_mask.h|4 +
 9 files changed, 1946 insertions(+)
 create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/Makefile
 create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.h
 create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.h
 create mode 100644 
drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.c
 create mode 100644 
drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.h

diff --git a/drivers/gpu/drm/amd/display/dc/Makefile 
b/drivers/gpu/drm/amd/display/dc/Makefile
index aed538a4d1ba..d5d5acd57559 100644
--- a/drivers/gpu/drm/amd/display/dc/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/Makefile
@@ -36,6 +36,10 @@ DC_LIBS += dce110
 DC_LIBS += dce100
 DC_LIBS += dce80
 
+ifdef CONFIG_DRM_AMD_DC_SI
+DC_LIBS += dce60
+endif
+
 AMD_DC = $(addsuffix /Makefile, $(addprefix 
$(FULL_AMD_DISPLAY_PATH)/dc/,$(DC_LIBS)))
 
 include $(AMD_DC)
diff --git a/drivers/gpu/drm/amd/display/dc/dce60/Makefile 
b/drivers/gpu/drm/amd/display/dc/dce60/Makefile
new file mode 100644
index ..39afd7c59a7c
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dce60/Makefile
@@ -0,0 +1,34 @@
+#
+# Copyright 2017 Advanced Micro Devices, Inc.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+# OTHER DEALINGS IN THE SOFTWARE.
+#
+#
+# Makefile for the 'controller' sub-component of DAL.
+# It provides the control and status of HW CRTC block.
+
+DCE60 = dce60_timing_generator.o dce60_hw_sequencer.o \
+   dce60_resource.o
+
+AMD_DAL_DCE60 = $(addprefix $(AMDDALPATH)/dc/dce60/,$(DCE60))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_DCE60)
+
+
+
diff --git a/drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.c
new file mode 100644
index ..502172bf6097
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.c
@@ -0,0 +1,82 @@
+/*
+ * Copyright 2015 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ *

[PATCH v2 10/10] drm/amd/display: enable SI support in the Kconfig (v2)

2018-10-17 Thread Mauro Rossi

CONFIG_DRM_AMD_DC_SI configuration option is added, default setting is disabled

(v2) Hainan is not supported, description updated accordingly
---
 drivers/gpu/drm/amd/display/Kconfig | 8 
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/Kconfig 
b/drivers/gpu/drm/amd/display/Kconfig
index 13a6ce9c8e94..32cdb2da603e 100644
--- a/drivers/gpu/drm/amd/display/Kconfig
+++ b/drivers/gpu/drm/amd/display/Kconfig
@@ -21,6 +21,14 @@ config DRM_AMD_DC_DCN1_01
help
  RV2 family for display engine
 
+config DRM_AMD_DC_SI
+   bool "AMD DC support for Southern Islands ASICs"
+   default n
+   help
+ Choose this option to enable new AMD DC support for SI asics
+ by default. This includes Tahiti, Pitcairn, Cape Verde, Oland.
+ Hainan is not supported by AMD DC and it has no physical DCE6.
+
 config DEBUG_KERNEL_DC
bool "Enable kgdb break in DC"
depends on DRM_AMD_DC
-- 
2.17.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH v2 09/10] drm/amdgpu: enable DC support for SI parts (v2)

2018-10-17 Thread Mauro Rossi

This commit enables DC support and Display Manager IP block
conditionally to CONFIG_DRM_AMD_DC_SI kernel configuration

(v1) pre-requisite to have Kaveri and Hawaii is revert of d9fda24804
 ("drm/amdgpu: Don't default to DC support for Kaveri and older")

(v2) fix for bc011f9350 ("drm/amdgpu: Change SI/CI gfx/sdma/smu init sequence")
 remove CHIP_HAINAN support since it does not have physical DCE6 module
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  6 ++
 drivers/gpu/drm/amd/amdgpu/si.c| 10 ++
 2 files changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 27de8442e808..2d17d760af64 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2290,6 +2290,12 @@ bool amdgpu_device_asic_has_dc_support(enum 
amd_asic_type asic_type)
 {
switch (asic_type) {
 #if defined(CONFIG_DRM_AMD_DC)
+#if defined(CONFIG_DRM_AMD_DC_SI)
+   case CHIP_TAHITI:
+   case CHIP_PITCAIRN:
+   case CHIP_VERDE:
+   case CHIP_OLAND:
+#endif
case CHIP_BONAIRE:
case CHIP_HAWAII:
case CHIP_KAVERI:
diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index f8408f88cd37..700d6a914b30 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -48,6 +48,8 @@
 #include "uvd/uvd_4_0_d.h"
 #include "bif/bif_3_0_d.h"
 
+#include "amdgpu_dm.h"
+
 static const u32 tahiti_golden_registers[] =
 {
mmAZALIA_SCLK_CONTROL, 0x0030, 0x0011,
@@ -2062,6 +2064,10 @@ int si_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, _smu_ip_block);
if (adev->enable_virtual_display)
amdgpu_device_ip_block_add(adev, _virtual_ip_block);
+#if defined(CONFIG_DRM_AMD_DC) && defined(CONFIG_DRM_AMD_DC_SI)
+   else if (amdgpu_device_has_dc_support(adev))
+   amdgpu_device_ip_block_add(adev, _ip_block);
+#endif
else
amdgpu_device_ip_block_add(adev, _v6_0_ip_block);
/* amdgpu_device_ip_block_add(adev, _v3_1_ip_block); */
@@ -2076,6 +2082,10 @@ int si_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, _smu_ip_block);
if (adev->enable_virtual_display)
amdgpu_device_ip_block_add(adev, _virtual_ip_block);
+#if defined(CONFIG_DRM_AMD_DC) && defined(CONFIG_DRM_AMD_DC_SI)
+   else if (amdgpu_device_has_dc_support(adev))
+   amdgpu_device_ip_block_add(adev, _ip_block);
+#endif
else
amdgpu_device_ip_block_add(adev, _v6_4_ip_block);
 
-- 
2.17.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH v2 08/10] drm/amd/display: amdgpu_dm: add SI support (v2)

2018-10-17 Thread Mauro Rossi

This commit adds Display Manager early initialization for SI parts
conditionally to CONFIG_DRM_AMD_DC_SI kernel configuration

(v2) remove CHIP_HAINAN support since it does not have physical DCE6 module
 add SI families except CHIP_HAINAN in load_dmcu_fw() new function
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 28 +++
 1 file changed, 28 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 492230c41b4a..7dedb363a476 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -514,6 +514,12 @@ static int load_dmcu_fw(struct amdgpu_device *adev)
const struct dmcu_firmware_header_v1_0 *hdr;
 
switch(adev->asic_type) {
+#if defined(CONFIG_DRM_AMD_DC_SI)
+   case CHIP_TAHITI:
+   case CHIP_PITCAIRN:
+   case CHIP_VERDE:
+   case CHIP_OLAND:
+#endif
case CHIP_BONAIRE:
case CHIP_HAWAII:
case CHIP_KAVERI:
@@ -1728,6 +1734,12 @@ static int amdgpu_dm_initialize_drm_device(struct 
amdgpu_device *adev)
 
/* Software is initialized. Now we can register interrupt handlers. */
switch (adev->asic_type) {
+#if defined(CONFIG_DRM_AMD_DC_SI)
+   case CHIP_TAHITI:
+   case CHIP_PITCAIRN:
+   case CHIP_VERDE:
+   case CHIP_OLAND:
+#endif
case CHIP_BONAIRE:
case CHIP_HAWAII:
case CHIP_KAVERI:
@@ -1918,6 +1930,22 @@ static int dm_early_init(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
switch (adev->asic_type) {
+#if defined(CONFIG_DRM_AMD_DC_SI)
+   case CHIP_TAHITI:
+   case CHIP_PITCAIRN:
+   case CHIP_VERDE:
+   adev->mode_info.num_crtc = 6;
+   adev->mode_info.num_hpd = 6;
+   adev->mode_info.num_dig = 6;
+   adev->mode_info.plane_type = dm_plane_type_default;
+   break;
+   case CHIP_OLAND:
+   adev->mode_info.num_crtc = 2;
+   adev->mode_info.num_hpd = 2;
+   adev->mode_info.num_dig = 2;
+   adev->mode_info.plane_type = dm_plane_type_default;
+   break;
+#endif
case CHIP_BONAIRE:
case CHIP_HAWAII:
adev->mode_info.num_crtc = 6;
-- 
2.17.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH v2 07/10] drm/amd/display: dc/irq: add support for DCE6

2018-10-17 Thread Mauro Rossi

DCE6 targets are added replicating existing DCE8 implementation.

NOTE: due to missing CRTC_VERTICAL_INTERRUPT0_CONTROL registers/masks,
dce/dce_8_0_{d,sh_mask}.h headers were used instead of dce/dce_6_0_{d,sh_mask}.h
but only as exception in dce/irq_service_dce60.c

IMPORTANT: Coding of dce/irq_service_dce60.c requires review to understand
if dce_6_0_{d,sh_mask}.h should be updated with macros/registers/masks
---
 drivers/gpu/drm/amd/display/dc/irq/Makefile   |  11 +
 .../display/dc/irq/dce60/irq_service_dce60.c  | 303 ++
 .../display/dc/irq/dce60/irq_service_dce60.h  |  35 ++
 .../gpu/drm/amd/display/dc/irq/irq_service.c  |   3 +
 4 files changed, 352 insertions(+)
 create mode 100644 drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.h

diff --git a/drivers/gpu/drm/amd/display/dc/irq/Makefile 
b/drivers/gpu/drm/amd/display/dc/irq/Makefile
index 498515aad4a5..e38b6d8d614d 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/irq/Makefile
@@ -30,6 +30,17 @@ AMD_DAL_IRQ = $(addprefix $(AMDDALPATH)/dc/irq/,$(IRQ))
 
 AMD_DISPLAY_FILES += $(AMD_DAL_IRQ)
 
+###
+# DCE 6x
+###
+ifdef CONFIG_DRM_AMD_DC_SI
+IRQ_DCE60 = irq_service_dce60.o
+
+AMD_DAL_IRQ_DCE60 = $(addprefix $(AMDDALPATH)/dc/irq/dce60/,$(IRQ_DCE60))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCE60)
+endif
+
 ###
 # DCE 8x
 ###
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c 
b/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
new file mode 100644
index ..107e0dcb5f80
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
@@ -0,0 +1,303 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+
+#include "include/logger_interface.h"
+
+#include "irq_service_dce60.h"
+#include "../dce110/irq_service_dce110.h"
+
+#include "dce/dce_8_0_d.h"
+#include "dce/dce_8_0_sh_mask.h"
+
+#include "ivsrcid/ivsrcid_vislands30.h"
+
+#include "dc_types.h"
+
+static bool hpd_ack(
+   struct irq_service *irq_service,
+   const struct irq_source_info *info)
+{
+   uint32_t addr = info->status_reg;
+   uint32_t value = dm_read_reg(irq_service->ctx, addr);
+   uint32_t current_status =
+   get_reg_field_value(
+   value,
+   DC_HPD1_INT_STATUS,
+   DC_HPD1_SENSE_DELAYED);
+
+   dal_irq_service_ack_generic(irq_service, info);
+
+   value = dm_read_reg(irq_service->ctx, info->enable_reg);
+
+   set_reg_field_value(
+   value,
+   current_status ? 0 : 1,
+   DC_HPD1_INT_CONTROL,
+   DC_HPD1_INT_POLARITY);
+
+   dm_write_reg(irq_service->ctx, info->enable_reg, value);
+
+   return true;
+}
+
+static const struct irq_source_info_funcs hpd_irq_info_funcs = {
+   .set = NULL,
+   .ack = hpd_ack
+};
+
+static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
+   .set = NULL,
+   .ack = NULL
+};
+
+static const struct irq_source_info_funcs pflip_irq_info_funcs = {
+   .set = NULL,
+   .ack = NULL
+};
+
+static const struct irq_source_info_funcs vblank_irq_info_funcs = {
+   .set = dce110_vblank_set,
+   .ack = NULL
+};
+
+
+#define hpd_int_entry(reg_num)\
+   [DC_IRQ_SOURCE_INVALID + reg_num] = {\
+   .enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
+   .enable_mask =

[PATCH v2 06/10] drm/amd/display: dc/i2caux: add support for DCE6

2018-10-17 Thread Mauro Rossi

DCE6 targets are added replicating existing DCE8 implementation.
---
 .../gpu/drm/amd/display/dc/i2caux/Makefile|  12 +
 .../dc/i2caux/dce60/i2c_hw_engine_dce60.c | 875 ++
 .../dc/i2caux/dce60/i2c_hw_engine_dce60.h |  54 ++
 .../dc/i2caux/dce60/i2c_sw_engine_dce60.c | 173 
 .../dc/i2caux/dce60/i2c_sw_engine_dce60.h |  43 +
 .../display/dc/i2caux/dce60/i2caux_dce60.c| 284 ++
 .../display/dc/i2caux/dce60/i2caux_dce60.h|  38 +
 .../gpu/drm/amd/display/dc/i2caux/i2caux.c|  10 +
 8 files changed, 1489 insertions(+)
 create mode 100644 
drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2c_hw_engine_dce60.c
 create mode 100644 
drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2c_hw_engine_dce60.h
 create mode 100644 
drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2c_sw_engine_dce60.c
 create mode 100644 
drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2c_sw_engine_dce60.h
 create mode 100644 drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2caux_dce60.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2caux_dce60.h

diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/Makefile 
b/drivers/gpu/drm/amd/display/dc/i2caux/Makefile
index 352885cb4d07..80f58a357879 100644
--- a/drivers/gpu/drm/amd/display/dc/i2caux/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/i2caux/Makefile
@@ -30,6 +30,18 @@ AMD_DAL_I2CAUX = $(addprefix 
$(AMDDALPATH)/dc/i2caux/,$(I2CAUX))
 
 AMD_DISPLAY_FILES += $(AMD_DAL_I2CAUX)
 
+###
+# DCE 6x family
+###
+ifdef CONFIG_DRM_AMD_DC_SI
+I2CAUX_DCE60 = i2caux_dce60.o i2c_hw_engine_dce60.o \
+   i2c_sw_engine_dce60.o
+
+AMD_DAL_I2CAUX_DCE60 = $(addprefix 
$(AMDDALPATH)/dc/i2caux/dce60/,$(I2CAUX_DCE60))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_I2CAUX_DCE60)
+endif
+
 ###
 # DCE 8x family
 ###
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2c_hw_engine_dce60.c 
b/drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2c_hw_engine_dce60.c
new file mode 100644
index ..a945e00ce913
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2c_hw_engine_dce60.c
@@ -0,0 +1,875 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+
+/*
+ * Pre-requisites: headers required by header of this unit
+ */
+#include "include/i2caux_interface.h"
+#include "../engine.h"
+#include "../i2c_engine.h"
+#include "../i2c_hw_engine.h"
+#include "../i2c_generic_hw_engine.h"
+/*
+ * Header of this unit
+ */
+
+#include "i2c_hw_engine_dce60.h"
+
+/*
+ * Post-requisites: headers required by this unit
+ */
+
+#include "dce/dce_6_0_d.h"
+#include "dce/dce_6_0_sh_mask.h"
+/*
+ * This unit
+ */
+
+enum dc_i2c_status {
+   DC_I2C_STATUS__DC_I2C_STATUS_IDLE,
+   DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_SW,
+   DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_HW
+};
+
+enum dc_i2c_arbitration {
+   DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_NORMAL,
+   DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_HIGH
+};
+
+enum {
+   /* No timeout in HW
+* (timeout implemented in SW by querying status) */
+   I2C_SETUP_TIME_LIMIT = 255,
+   I2C_HW_BUFFER_SIZE = 144
+};
+
+/*
+ * @brief
+ * Cast 'struct i2c_hw_engine *'
+ * to 'struct i2c_hw_engine_dce60 *'
+ */
+#define FROM_I2C_HW_ENGINE(ptr) \
+   container_of((ptr), struct i2c_hw_engine_dce60, base)
+
+/*
+ * @brief
+ * Cast pointer to 'struct i2c_engine *'
+ * to pointer to 'struct i2c_hw_engine_dce60 *'
+ */
+#define FROM_I2C_ENGINE(ptr) \
+   FROM_I2C_HW_ENGINE(container_of((ptr), struct i2c_hw_engine, base))
+
+/*
+ * @brief
+ * Cast pointer to 'struct engine *'
+ *

[PATCH v2] drm/amd/display: add SI support to AMD DC

2018-10-17 Thread Mauro Rossi

Sending PATCH v2 series rebase on amd-staging-drm-next

dce/dce60/dce60_resources.c and irq/dce60/irq_service_dce60.c
are still using dce_8_0_{d,sh_mask}.h headers

dpm is used for power management, a non fatal message is generated:

[drm:dm_pp_get_static_clocks: [amdgpu]] 
*ERROR* DM_PPLIB: invalid powerlevel state: 0!

VBIOS parsing requires review about severity of generated Warning:

dce110_link_encoder_construct: 
Failed to get encoder_cap_info from VBIOS with error code 4!


[PATCH v2 01/10] drm/amd/display: add asics info for SI parts
[PATCH v2 02/10] drm/amd/display: dc/dce: add DCE6 support (v2)
[PATCH v2 03/10] drm/amd/display: dc/core: add DCE6 support
[PATCH v2 04/10] drm/amd/display: dc/bios: add support for DCE6
[PATCH v2 05/10] drm/amd/display: dc/gpio: add support for DCE6
[PATCH v2 06/10] drm/amd/display: dc/i2caux: add support for DCE6
[PATCH v2 07/10] drm/amd/display: dc/irq: add support for DCE6
[PATCH v2 08/10] drm/amd/display: amdgpu_dm: add SI support (v2)
[PATCH v2 09/10] drm/amdgpu: enable DC support for SI parts (v2)
[PATCH v2 10/10] drm/amd/display: enable SI support in the Kconfig (v2)

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH v2 03/10] drm/amd/display: dc/core: add DCE6 support

2018-10-17 Thread Mauro Rossi

DCE6 targets are added as branching of existing DCE8 implementation.
---
 .../gpu/drm/amd/display/dc/core/dc_resource.c | 29 +++
 1 file changed, 29 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index a5eb80aa3dd9..07bd4f72acc5 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -37,6 +37,9 @@
 #include "virtual/virtual_stream_encoder.h"
 #include "dpcd_defs.h"
 
+#if defined(CONFIG_DRM_AMD_DC_SI)
+#include "dce60/dce60_resource.h"
+#endif
 #include "dce80/dce80_resource.h"
 #include "dce100/dce100_resource.h"
 #include "dce110/dce110_resource.h"
@@ -53,6 +56,18 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id 
asic_id)
enum dce_version dc_version = DCE_VERSION_UNKNOWN;
switch (asic_id.chip_family) {
 
+#if defined(CONFIG_DRM_AMD_DC_SI)
+   case FAMILY_SI:
+   if (ASIC_REV_IS_TAHITI_P(asic_id.hw_internal_rev) ||
+   ASIC_REV_IS_PITCAIRN_PM(asic_id.hw_internal_rev) ||
+   ASIC_REV_IS_CAPEVERDE_M(asic_id.hw_internal_rev))
+   dc_version = DCE_VERSION_6_0;
+   else if (ASIC_REV_IS_OLAND_M(asic_id.hw_internal_rev))
+   dc_version = DCE_VERSION_6_4;
+   else
+   dc_version = DCE_VERSION_6_1;
+   break;
+#endif
case FAMILY_CI:
dc_version = DCE_VERSION_8_0;
break;
@@ -110,6 +125,20 @@ struct resource_pool *dc_create_resource_pool(
struct resource_pool *res_pool = NULL;
 
switch (dc_version) {
+#if defined(CONFIG_DRM_AMD_DC_SI)
+   case DCE_VERSION_6_0:
+   res_pool = dce60_create_resource_pool(
+   num_virtual_links, dc);
+   break;
+   case DCE_VERSION_6_1:
+   res_pool = dce61_create_resource_pool(
+   num_virtual_links, dc);
+   break;
+   case DCE_VERSION_6_4:
+   res_pool = dce64_create_resource_pool(
+   num_virtual_links, dc);
+   break;
+#endif
case DCE_VERSION_8_0:
res_pool = dce80_create_resource_pool(
num_virtual_links, dc);
-- 
2.17.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH v2 05/10] drm/amd/display: dc/gpio: add support for DCE6

2018-10-17 Thread Mauro Rossi

DCE6 targets are added replicating existing DCE8 implementation.
---
 drivers/gpu/drm/amd/display/dc/gpio/Makefile  |  12 +
 .../display/dc/gpio/dce60/hw_factory_dce60.c  | 174 
 .../display/dc/gpio/dce60/hw_factory_dce60.h  |  32 ++
 .../dc/gpio/dce60/hw_translate_dce60.c| 411 ++
 .../dc/gpio/dce60/hw_translate_dce60.h|  32 ++
 .../gpu/drm/amd/display/dc/gpio/hw_factory.c  |  10 +
 .../drm/amd/display/dc/gpio/hw_translate.c|  10 +
 7 files changed, 681 insertions(+)
 create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_factory_dce60.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_factory_dce60.h
 create mode 100644 
drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c
 create mode 100644 
drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.h

diff --git a/drivers/gpu/drm/amd/display/dc/gpio/Makefile 
b/drivers/gpu/drm/amd/display/dc/gpio/Makefile
index 562ee189d780..122ca9991100 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/gpio/Makefile
@@ -30,6 +30,18 @@ AMD_DAL_GPIO = $(addprefix $(AMDDALPATH)/dc/gpio/,$(GPIO))
 
 AMD_DISPLAY_FILES += $(AMD_DAL_GPIO)
 
+###
+# DCE 6x
+###
+# all DCE6.x are derived from DCE6.0
+ifdef CONFIG_DRM_AMD_DC_SI
+GPIO_DCE60 = hw_translate_dce60.o hw_factory_dce60.o
+
+AMD_DAL_GPIO_DCE60 = $(addprefix $(AMDDALPATH)/dc/gpio/dce60/,$(GPIO_DCE60))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCE60)
+endif
+
 ###
 # DCE 8x
 ###
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_factory_dce60.c 
b/drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_factory_dce60.c
new file mode 100644
index ..64afe9b48c5f
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_factory_dce60.c
@@ -0,0 +1,174 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ * Copyright 2018 Mauro Rossi 
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+#include "include/gpio_types.h"
+#include "../hw_factory.h"
+
+#include "hw_factory_dce60.h"
+
+#include "../hw_gpio.h"
+#include "../hw_ddc.h"
+#include "../hw_hpd.h"
+
+#include "dce/dce_6_0_d.h"
+#include "dce/dce_6_0_sh_mask.h"
+
+#define REG(reg_name)\
+   mm ## reg_name
+
+#include "reg_helper.h"
+#include "../hpd_regs.h"
+
+#define HPD_REG_LIST_DCE6(id) \
+   HPD_GPIO_REG_LIST(id), \
+   .int_status = mmDC_HPD ## id ## _INT_STATUS,\
+   .toggle_filt_cntl = mmDC_HPD ## id ## _TOGGLE_FILT_CNTL
+
+#define HPD_MASK_SH_LIST_DCE6(mask_sh) \
+   .DC_HPD_SENSE_DELAYED = 
DC_HPD1_INT_STATUS__DC_HPD1_SENSE_DELAYED ## mask_sh,\
+   .DC_HPD_SENSE = DC_HPD1_INT_STATUS__DC_HPD1_SENSE ## mask_sh,\
+   .DC_HPD_CONNECT_INT_DELAY = 
DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_CONNECT_INT_DELAY ## mask_sh,\
+   .DC_HPD_DISCONNECT_INT_DELAY = 
DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_DISCONNECT_INT_DELAY ## mask_sh
+
+#define hpd_regs(id) \
+{\
+   HPD_REG_LIST_DCE6(id)\
+}
+
+static const struct hpd_registers hpd_regs[] = {
+   hpd_regs(1),
+   hpd_regs(2),
+   hpd_regs(3),
+   hpd_regs(4),
+   hpd_regs(5),
+   hpd_regs(6)
+};
+
+static const struct hpd_sh_mask hpd_shift = {
+   HPD_MASK_SH_LIST_DCE6(__SHIFT)
+};
+
+static const struct hpd_sh_mask hpd_mask = {
+   HPD_MASK_SH_LIST_DCE6(_MASK)
+};
+
+#include "../ddc_regs.h"
+
+ /* set field name */
+#define SF_DDC(reg_name, field_name, post_fix)\
+   .field_name = reg_name ## __ ## field_name ## post_fix
+
+static const struct ddc_registers ddc_data_regs[] = {
+

Re: [PATCH 2/2] drm/amdgpu: replace get_user_pages with HMM address mirror helpers

2018-10-17 Thread Christian König


Am 17.10.18 um 04:56 schrieb Yang, Philip:

Use HMM helper function hmm_vma_fault() to get physical pages backing
userptr and start CPU page table update track of those pages. Then use
hmm_vma_range_done() to check if those pages are updated before
amdgpu_cs_submit for gfx or before user queues are resumed for kfd.

If userptr pages are updated, for gfx, amdgpu_cs_ioctl will restart
from scratch, for kfd, restore worker is rescheduled to retry.

To avoid circular lock dependency, the locking order is:
mmap_sem -> amdgpu_mn_lock(p->mn) -> bo::reserve
mmap_sem -> bo::reserve


I'm not sure that this will work, we used to have some dependencies on 
bo::reserve -> mmap_sem.


See the following patch as well:

commit 2f568dbd6b944c2e8c0c54b53c2211c23995e6a4
Author: Christian König 
Date:   Tue Feb 23 12:36:59 2016 +0100

    drm/amdgpu: move get_user_pages out of amdgpu_ttm_tt_pin_userptr v6

    That avoids lock inversion between the BO reservation lock
    and the anon_vma lock.

A whole bunch of more problems below.



HMM simplify the CPU page table concurrently update check, so remove
guptasklock, mmu_invalidations, last_set_pages fields from
amdgpu_ttm_tt struct.

HMM doesnot pin the page (increase page ref count), so remove related
operations like release_pages(), put_page(), mark_page_dirty().

Change-Id: Iffd5f855cc9ce402cdfca167f68f83fe39ac56f9
Signed-off-by: Philip Yang 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 101 ++---
  drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c  |   2 -
  drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h  |   3 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c   | 171 +--
  drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c  |  14 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c   |  34 -
  drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h   |   7 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c  | 164 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h  |   3 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c   |   1 -
  10 files changed, 252 insertions(+), 248 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index df0a059..3fd0340 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -615,8 +615,7 @@ static int init_user_pages(struct kgd_mem *mem, struct 
mm_struct *mm,
amdgpu_bo_unreserve(bo);
  
  release_out:

-   if (ret)
-   release_pages(mem->user_pages, bo->tbo.ttm->num_pages);
+   amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm);
  free_out:
kvfree(mem->user_pages);
mem->user_pages = NULL;
@@ -678,7 +677,6 @@ static int reserve_bo_and_vm(struct kgd_mem *mem,
ctx->kfd_bo.priority = 0;
ctx->kfd_bo.tv.bo = >tbo;
ctx->kfd_bo.tv.shared = true;
-   ctx->kfd_bo.user_pages = NULL;
list_add(>kfd_bo.tv.head, >list);
  
  	amdgpu_vm_get_pd_bo(vm, >list, >vm_pd[0]);

@@ -742,7 +740,6 @@ static int reserve_bo_and_cond_vms(struct kgd_mem *mem,
ctx->kfd_bo.priority = 0;
ctx->kfd_bo.tv.bo = >tbo;
ctx->kfd_bo.tv.shared = true;
-   ctx->kfd_bo.user_pages = NULL;
list_add(>kfd_bo.tv.head, >list);
  
  	i = 0;

@@ -1311,9 +1308,6 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
/* Free user pages if necessary */
if (mem->user_pages) {
pr_debug("%s: Freeing user_pages array\n", __func__);
-   if (mem->user_pages[0])
-   release_pages(mem->user_pages,
-   mem->bo->tbo.ttm->num_pages);
kvfree(mem->user_pages);
}
  
@@ -1739,8 +1733,6 @@ static int update_invalid_user_pages(struct amdkfd_process_info *process_info,

   __func__);
return -ENOMEM;
}
-   } else if (mem->user_pages[0]) {
-   release_pages(mem->user_pages, bo->tbo.ttm->num_pages);
}
  
  		/* Get updated user pages */

@@ -1756,12 +1748,6 @@ static int update_invalid_user_pages(struct 
amdkfd_process_info *process_info,
 * stalled user mode queues.
 */
}
-
-   /* Mark the BO as valid unless it was invalidated
-* again concurrently
-*/
-   if (atomic_cmpxchg(>invalid, invalid, 0) != invalid)
-   return -EAGAIN;
}
  
  	return 0;

@@ -1854,14 +1840,10 @@ static int validate_invalid_user_pages(struct 
amdkfd_process_info *process_info)
}
  
  		/* Validate succeeded, now the BO owns the pages, free

-* our copy of the pointer array. Put this BO back on
-* the userptr_valid_list. If we need to revalidate
-* it, we need to start from

Re: [PATCH 2/2] drm/amdgpu: replace get_user_pages with HMM address mirror helpers

2018-10-17 Thread Christian König


Am 17.10.18 um 04:56 schrieb Yang, Philip:

Use HMM helper function hmm_vma_fault() to get physical pages backing
userptr and start CPU page table update track of those pages. Then use
hmm_vma_range_done() to check if those pages are updated before
amdgpu_cs_submit for gfx or before user queues are resumed for kfd.

If userptr pages are updated, for gfx, amdgpu_cs_ioctl will restart
from scratch, for kfd, restore worker is rescheduled to retry.

To avoid circular lock dependency, the locking order is:
mmap_sem -> amdgpu_mn_lock(p->mn) -> bo::reserve
mmap_sem -> bo::reserve


I'm not sure that this will work, we used to have some dependencies on 
bo::reserve -> mmap_sem.


See the following patch as well:

commit 2f568dbd6b944c2e8c0c54b53c2211c23995e6a4
Author: Christian König 
Date:   Tue Feb 23 12:36:59 2016 +0100

    drm/amdgpu: move get_user_pages out of amdgpu_ttm_tt_pin_userptr v6

    That avoids lock inversion between the BO reservation lock
    and the anon_vma lock.

A few more comments below.



HMM simplify the CPU page table concurrently update check, so remove
guptasklock, mmu_invalidations, last_set_pages fields from
amdgpu_ttm_tt struct.

HMM doesnot pin the page (increase page ref count), so remove related
operations like release_pages(), put_page(), mark_page_dirty().

Change-Id: Iffd5f855cc9ce402cdfca167f68f83fe39ac56f9
Signed-off-by: Philip Yang 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 101 ++---
  drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c  |   2 -
  drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h  |   3 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c   | 171 +--
  drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c  |  14 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c   |  34 -
  drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h   |   7 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c  | 164 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h  |   3 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c   |   1 -
  10 files changed, 252 insertions(+), 248 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index df0a059..3fd0340 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -615,8 +615,7 @@ static int init_user_pages(struct kgd_mem *mem, struct 
mm_struct *mm,
amdgpu_bo_unreserve(bo);
  
  release_out:

-   if (ret)
-   release_pages(mem->user_pages, bo->tbo.ttm->num_pages);
+   amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm);
  free_out:
kvfree(mem->user_pages);
mem->user_pages = NULL;
@@ -678,7 +677,6 @@ static int reserve_bo_and_vm(struct kgd_mem *mem,
ctx->kfd_bo.priority = 0;
ctx->kfd_bo.tv.bo = >tbo;
ctx->kfd_bo.tv.shared = true;
-   ctx->kfd_bo.user_pages = NULL;
list_add(>kfd_bo.tv.head, >list);
  
  	amdgpu_vm_get_pd_bo(vm, >list, >vm_pd[0]);

@@ -742,7 +740,6 @@ static int reserve_bo_and_cond_vms(struct kgd_mem *mem,
ctx->kfd_bo.priority = 0;
ctx->kfd_bo.tv.bo = >tbo;
ctx->kfd_bo.tv.shared = true;
-   ctx->kfd_bo.user_pages = NULL;
list_add(>kfd_bo.tv.head, >list);
  
  	i = 0;

@@ -1311,9 +1308,6 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
/* Free user pages if necessary */
if (mem->user_pages) {
pr_debug("%s: Freeing user_pages array\n", __func__);
-   if (mem->user_pages[0])
-   release_pages(mem->user_pages,
-   mem->bo->tbo.ttm->num_pages);
kvfree(mem->user_pages);
}
  
@@ -1739,8 +1733,6 @@ static int update_invalid_user_pages(struct amdkfd_process_info *process_info,

   __func__);
return -ENOMEM;
}
-   } else if (mem->user_pages[0]) {
-   release_pages(mem->user_pages, bo->tbo.ttm->num_pages);
}
  
  		/* Get updated user pages */

@@ -1756,12 +1748,6 @@ static int update_invalid_user_pages(struct 
amdkfd_process_info *process_info,
 * stalled user mode queues.
 */
}
-
-   /* Mark the BO as valid unless it was invalidated
-* again concurrently
-*/
-   if (atomic_cmpxchg(>invalid, invalid, 0) != invalid)
-   return -EAGAIN;
}
  
  	return 0;

@@ -1854,14 +1840,10 @@ static int validate_invalid_user_pages(struct 
amdkfd_process_info *process_info)
}
  
  		/* Validate succeeded, now the BO owns the pages, free

-* our copy of the pointer array. Put this BO back on
-* the userptr_valid_list. If we need to revalidate
-* it, we need to start from scratch.
+

Re: [PATCH 2/7] drm: add syncobj timeline support v8

2018-10-17 Thread Daniel Vetter

On Mon, Oct 15, 2018 at 04:55:48PM +0800, Chunming Zhou wrote:
> This patch is for VK_KHR_timeline_semaphore extension, semaphore is called 
> syncobj in kernel side:
> This extension introduces a new type of syncobj that has an integer payload
> identifying a point in a timeline. Such timeline syncobjs support the
> following operations:
>* CPU query - A host operation that allows querying the payload of the
>  timeline syncobj.
>* CPU wait - A host operation that allows a blocking wait for a
>  timeline syncobj to reach a specified value.
>* Device wait - A device operation that allows waiting for a
>  timeline syncobj to reach a specified value.
>* Device signal - A device operation that allows advancing the
>  timeline syncobj to a specified value.
> 
> v1:
> Since it's a timeline, that means the front time point(PT) always is signaled 
> before the late PT.
> a. signal PT design:
> Signal PT fence N depends on PT[N-1] fence and signal opertion fence, when 
> PT[N] fence is signaled,
> the timeline will increase to value of PT[N].
> b. wait PT design:
> Wait PT fence is signaled by reaching timeline point value, when timeline is 
> increasing, will compare
> wait PTs value with new timeline value, if PT value is lower than timeline 
> value, then wait PT will be
> signaled, otherwise keep in list. syncobj wait operation can wait on any 
> point of timeline,
> so need a RB tree to order them. And wait PT could ahead of signal PT, we 
> need a sumission fence to
> perform that.
> 
> v2:
> 1. remove unused DRM_SYNCOBJ_CREATE_TYPE_NORMAL. (Christian)
> 2. move unexposed denitions to .c file. (Daniel Vetter)
> 3. split up the change to drm_syncobj_find_fence() in a separate patch. 
> (Christian)
> 4. split up the change to drm_syncobj_replace_fence() in a separate patch.
> 5. drop the submission_fence implementation and instead use wait_event() for 
> that. (Christian)
> 6. WARN_ON(point != 0) for NORMAL type syncobj case. (Daniel Vetter)
> 
> v3:
> 1. replace normal syncobj with timeline implemenation. (Vetter and Christian)
> a. normal syncobj signal op will create a signal PT to tail of signal pt 
> list.
> b. normal syncobj wait op will create a wait pt with last signal point, 
> and this wait PT is only signaled by related signal point PT.
> 2. many bug fix and clean up
> 3. stub fence moving is moved to other patch.
> 
> v4：
> 1. fix RB tree loop with while(node=rb_first(...)). (Christian)
> 2. fix syncobj lifecycle. (Christian)
> 3. only enable_signaling when there is wait_pt. (Christian)
> 4. fix timeline path issues.
> 5. write a timeline test in libdrm
> 
> v5: (Christian)
> 1. semaphore is called syncobj in kernel side.
> 2. don't need 'timeline' characters in some function name.
> 3. keep syncobj cb.
> 
> v6: (Christian)
> 1. merge syncobj_timeline to syncobj structure.
> 2. simplify some check sentences.
> 3. some misc change.
> 4. fix CTS failed issue.
> 
> v7: (Christian)
> 1. error handling when creating signal pt.
> 2. remove timeline naming in func.
> 3. export flags in find_fence.
> 4. allow reset timeline.
> 
> v8:
> 1. use wait_event_interruptible without timeout
> 2. rename _TYPE_INDIVIDUAL to _TYPE_BINARY
> 
> individual syncobj is tested by ./deqp-vk -n dEQP-VK*semaphore*
> timeline syncobj is tested by ./amdgpu_test -s 9

Can we please have these low-level syncobj tests as part of igt, together
with all the other syncobj tests which are there already? Really doesn't
make much sense imo to splits things on the test suite front.
> 
> Signed-off-by: Chunming Zhou 
> Cc: Christian Konig 
> Cc: Dave Airlie 
> Cc: Daniel Rakos 
> Cc: Daniel Vetter 
> Reviewed-by: Christian König 
> ---
>  drivers/gpu/drm/drm_syncobj.c  | 287 ++---
>  drivers/gpu/drm/i915/i915_gem_execbuffer.c |   2 +-
>  include/drm/drm_syncobj.h  |  65 ++---
>  include/uapi/drm/drm.h |   1 +
>  4 files changed, 281 insertions(+), 74 deletions(-)
> 
> diff --git a/drivers/gpu/drm/drm_syncobj.c b/drivers/gpu/drm/drm_syncobj.c
> index f796c9fc3858..67472bd77c83 100644
> --- a/drivers/gpu/drm/drm_syncobj.c
> +++ b/drivers/gpu/drm/drm_syncobj.c
> @@ -56,6 +56,9 @@
>  #include "drm_internal.h"
>  #include 
>  
> +/* merge normal syncobj to timeline syncobj, the point interval is 1 */
> +#define DRM_SYNCOBJ_BINARY_POINT 1
> +
>  struct drm_syncobj_stub_fence {
>   struct dma_fence base;
>   spinlock_t lock;
> @@ -82,6 +85,11 @@ static const struct dma_fence_ops 
> drm_syncobj_stub_fence_ops = {
>   .release = drm_syncobj_stub_fence_release,
>  };
>  
> +struct drm_syncobj_signal_pt {
> + struct dma_fence_array *base;

Out of curiosity, why the pointer and not embedding? base is kinda
misleading for a pointer.

> + u64value;
> + struct list_head list;
> +};
>  
>  /**
>   * drm_syncobj_find - lookup and reference a sync object.
> @@ -124,8 +132,8 @@ static int

RE: [PATCH] Revised PSP comments

2018-10-17 Thread Huang, Ray

> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of John Clements
> Sent: Wednesday, October 17, 2018 6:48 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: John Clements 
> Subject: [PATCH] Revised PSP comments
> 
> From: John Clements 
> 
> Revised comments in PSP SOS/Sysdriver loading sequence
> 
> Signed-off-by: John Clements 

Thanks, applied it.

Reviewed-by: Huang Rui 

> ---
>  drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/psp_v3_1.c  | 4 ++--
>  2 files changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
> b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
> index b70cfa3fe1b2..3fe30eb46d26 100644
> --- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
> @@ -167,7 +167,7 @@ static int psp_v11_0_bootloader_load_sysdrv(struct
> psp_context *psp)
>   /* Copy PSP System Driver binary to memory */
>   memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size);
> 
> - /* Provide the sys driver to bootrom */
> + /* Provide the sys driver to bootloader */
>   WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
>  (uint32_t)(psp->fw_pri_mc_addr >> 20));
>   psp_gfxdrv_command_reg = 1 << 16;
> @@ -208,7 +208,7 @@ static int psp_v11_0_bootloader_load_sos(struct
> psp_context *psp)
>   /* Copy Secure OS binary to PSP memory */
>   memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size);
> 
> - /* Provide the PSP secure OS to bootrom */
> + /* Provide the PSP secure OS to bootloader */
>   WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
>  (uint32_t)(psp->fw_pri_mc_addr >> 20));
>   psp_gfxdrv_command_reg = 2 << 16;
> diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
> b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
> index e1ebf770c303..9cea0bbe4525 100644
> --- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
> +++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
> @@ -194,7 +194,7 @@ static int psp_v3_1_bootloader_load_sysdrv(struct
> psp_context *psp)
>   /* Copy PSP System Driver binary to memory */
>   memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size);
> 
> - /* Provide the sys driver to bootrom */
> + /* Provide the sys driver to bootloader */
>   WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
>  (uint32_t)(psp->fw_pri_mc_addr >> 20));
>   psp_gfxdrv_command_reg = 1 << 16;
> @@ -254,7 +254,7 @@ static int psp_v3_1_bootloader_load_sos(struct
> psp_context *psp)
>   /* Copy Secure OS binary to PSP memory */
>   memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size);
> 
> - /* Provide the PSP secure OS to bootrom */
> + /* Provide the PSP secure OS to bootloader */
>   WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
>  (uint32_t)(psp->fw_pri_mc_addr >> 20));
>   psp_gfxdrv_command_reg = 2 << 16;
> --
> 2.17.1
> 
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 7/7] drm/amdgpu: update version for timeline syncobj support in amdgpu

2018-10-17 Thread zhoucm1




On 2018年10月16日 20:54, Christian König wrote:

I've added my rb to patch #1 and pushed it to drm-misc-next.

I would really like to get an rb from other people on patch #2 before 
proceeding.


Daniel, Dave and all the other usual suspects on the list what is your 
opinion on this implementation?
Thanks for head up, @Daniel, @Dave, or the others, Could you take a look 
for the series?


Thanks,
David


Christian.

Am 15.10.2018 um 11:04 schrieb Koenig, Christian:

I'm on sick leave today.

But I will see what I can do later in the afternoon,
Christian.

Am 15.10.2018 um 11:01 schrieb Zhou, David(ChunMing):

Ping...
Christian, Could I get your RB on the series? And help me to push to 
drm-misc?

After that I can rebase libdrm header file based on drm-next.

Thanks,
David Zhou


-Original Message-
From: amd-gfx  On Behalf Of
Chunming Zhou
Sent: Monday, October 15, 2018 4:56 PM
To: dri-de...@lists.freedesktop.org
Cc: Zhou, David(ChunMing) ; amd-
g...@lists.freedesktop.org
Subject: [PATCH 7/7] drm/amdgpu: update version for timeline syncobj
support in amdgpu

Signed-off-by: Chunming Zhou 
---
   drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++-
   1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 6870909da926..58cba492ba55 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -70,9 +70,10 @@
    * - 3.25.0 - Add support for sensor query info (stable pstate 
sclk/mclk).

    * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE.
    * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST 
creation.

+ * - 3.28.0 - Add syncobj timeline support to AMDGPU_CS.
    */
   #define KMS_DRIVER_MAJOR    3
-#define KMS_DRIVER_MINOR    27
+#define KMS_DRIVER_MINOR    28
   #define KMS_DRIVER_PATCHLEVEL    0

   int amdgpu_vram_limit = 0;
--
2.17.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

___
dri-devel mailing list
dri-de...@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel




___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH] Revised PSP comments

2018-10-17 Thread John Clements

From: John Clements 

Revised comments in PSP SOS/Sysdriver loading sequence

Signed-off-by: John Clements 
---
 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 4 ++--
 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c  | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c 
b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index b70cfa3fe1b2..3fe30eb46d26 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -167,7 +167,7 @@ static int psp_v11_0_bootloader_load_sysdrv(struct 
psp_context *psp)
/* Copy PSP System Driver binary to memory */
memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size);
 
-   /* Provide the sys driver to bootrom */
+   /* Provide the sys driver to bootloader */
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
   (uint32_t)(psp->fw_pri_mc_addr >> 20));
psp_gfxdrv_command_reg = 1 << 16;
@@ -208,7 +208,7 @@ static int psp_v11_0_bootloader_load_sos(struct psp_context 
*psp)
/* Copy Secure OS binary to PSP memory */
memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size);
 
-   /* Provide the PSP secure OS to bootrom */
+   /* Provide the PSP secure OS to bootloader */
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
   (uint32_t)(psp->fw_pri_mc_addr >> 20));
psp_gfxdrv_command_reg = 2 << 16;
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c 
b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
index e1ebf770c303..9cea0bbe4525 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
@@ -194,7 +194,7 @@ static int psp_v3_1_bootloader_load_sysdrv(struct 
psp_context *psp)
/* Copy PSP System Driver binary to memory */
memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size);
 
-   /* Provide the sys driver to bootrom */
+   /* Provide the sys driver to bootloader */
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
   (uint32_t)(psp->fw_pri_mc_addr >> 20));
psp_gfxdrv_command_reg = 1 << 16;
@@ -254,7 +254,7 @@ static int psp_v3_1_bootloader_load_sos(struct psp_context 
*psp)
/* Copy Secure OS binary to PSP memory */
memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size);
 
-   /* Provide the PSP secure OS to bootrom */
+   /* Provide the PSP secure OS to bootloader */
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
   (uint32_t)(psp->fw_pri_mc_addr >> 20));
psp_gfxdrv_command_reg = 2 << 16;
-- 
2.17.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

44 matches

Mail list logo