[PATCH 3/6] drm/amdpgu: add common functions for BACO feature in PP

[Jim Qu]

Change-Id: I088260c27bc2a84b4e0abd96aca9a981dd52f7b6
Signed-off-by: Jim Qu 
Reviewed-by: Alex Deucher 
Reviewed-by: Hawking Zhang 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/Makefile  |  2 +-
 .../gpu/drm/amd/powerplay/hwmgr/common_baco.c | 98 +++
 .../gpu/drm/amd/powerplay/hwmgr/common_baco.h | 50 ++
 3 files changed, 149 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.c
 create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.h

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile 
b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
index ade8973b6f4d..5afec1a138ac 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
@@ -35,7 +35,7 @@ HARDWARE_MGR = hwmgr.o processpptables.o \
vega12_thermal.o \
pp_overdriver.o smu_helper.o \
vega20_processpptables.o vega20_hwmgr.o vega20_powertune.o \
-   vega20_thermal.o
+   vega20_thermal.o common_baco.o
 
 AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR))
 
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.c
new file mode 100644
index ..002693c421d2
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.c
@@ -0,0 +1,98 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include "common_baco.h"
+
+
+static bool baco_wait_register(struct pp_hwmgr *hwmgr, u32 reg, u32 mask, u32 
value)
+{
+   struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
+   u32 timeout = 5000, data;
+
+   do {
+   msleep(1);
+   data = RREG32(reg);
+   timeout--;
+   } while (value != (data & mask) && (timeout != 0));
+
+   if (timeout == 0)
+   return false;
+
+   return true;
+}
+
+static bool baco_cmd_handler(struct pp_hwmgr *hwmgr, u32 command, u32 reg, u32 
mask,
+   u32 shift, u32 value, u32 timeout)
+{
+   struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
+   u32 data;
+   bool ret = true;
+
+   switch (command) {
+   case CMD_WRITE:
+   WREG32(reg, value << shift);
+   break;
+   case CMD_READMODIFYWRITE:
+   data = RREG32(reg);
+   data = (data & (~mask)) | (value << shift);
+   WREG32(reg, data);
+   break;
+   case CMD_WAITFOR:
+   ret = baco_wait_register(hwmgr, reg, mask, value);
+   break;
+   case CMD_DELAY_MS:
+   if (timeout)
+   /* Delay in milli Seconds */
+   msleep(timeout);
+   break;
+   case CMD_DELAY_US:
+   if (timeout)
+   /* Delay in micro Seconds */
+   udelay(timeout);
+   break;
+
+   default:
+   dev_warn(adev->dev, "Invalid BACO command.\n");
+   ret = false;
+   }
+
+   return ret;
+}
+
+bool soc15_baco_program_registers(struct pp_hwmgr *hwmgr,
+const struct soc15_baco_cmd_entry *entry,
+const u32 array_size)
+{
+   struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
+   u32 i, reg;
+
+   for (i = 0; i < array_size; i++) {
+   reg = 
adev->reg_offset[entry[i].hwip][entry[i].inst][entry[i].seg]
+   + entry[i].reg_offset;
+   if (!baco_cmd_handler(hwmgr, entry[i].cmd, reg, entry[i].mask,
+entry[i].shift, entry[i].val, 
entry[i].timeout))
+   return false;
+   }
+
+   return true;
+}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.h 

[PATCH 6/6] drm/amdgpu: use BACO reset if platform support

[Jim Qu]

It will fall back to use mode1 reset if platform does not support BACO
feature.

Change-Id: If145e0868c37d76091e0782a49b82c5a935d2367
Signed-off-by: Jim Qu 
Reviewed-by: Alex Deucher 
Reviewed-by: Hawking Zhang 
---
 drivers/gpu/drm/amd/amdgpu/soc15.c | 62 --
 1 file changed, 59 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c 
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 483867f49154..ece6fca476d4 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -389,14 +389,13 @@ void soc15_program_register_sequence(struct amdgpu_device 
*adev,
 
 }
 
-
-static int soc15_asic_reset(struct amdgpu_device *adev)
+static int soc15_asic_mode1_reset(struct amdgpu_device *adev)
 {
u32 i;
 
amdgpu_atombios_scratch_regs_engine_hung(adev, true);
 
-   dev_info(adev->dev, "GPU reset\n");
+   dev_info(adev->dev, "GPU mode1 reset\n");
 
/* disable BM */
pci_clear_master(adev->pdev);
@@ -421,6 +420,63 @@ static int soc15_asic_reset(struct amdgpu_device *adev)
return 0;
 }
 
+static int soc15_asic_get_baco_capability(struct amdgpu_device *adev, bool 
*cap)
+{
+   void *pp_handle = adev->powerplay.pp_handle;
+   const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
+
+   if (!pp_funcs || !pp_funcs->get_asic_baco_capability) {
+   *cap = false;
+   return -1;
+   }
+
+   return pp_funcs->get_asic_baco_capability(pp_handle, cap);
+}
+
+static int soc15_asic_baco_reset(struct amdgpu_device *adev)
+{
+   int state;
+   void *pp_handle = adev->powerplay.pp_handle;
+   const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
+
+   if (!pp_funcs ||!pp_funcs->get_asic_baco_state 
||!pp_funcs->set_asic_baco_state)
+   return -1;
+
+   /* enter BACO state */
+   if (pp_funcs->set_asic_baco_state(pp_handle, 1))
+   return -1;
+
+   /* exit BACO state */
+   if (pp_funcs->set_asic_baco_state(pp_handle, 0))
+   return -1;
+
+   dev_info(adev->dev, "GPU BACO reset\n");
+
+   return 0;
+}
+
+static int soc15_asic_reset(struct amdgpu_device *adev)
+{
+   int ret;
+   bool baco_reset;
+
+   switch (adev->asic_type) {
+   case CHIP_VEGA10:
+   soc15_asic_get_baco_capability(adev, _reset);
+   break;
+   default:
+   baco_reset = false;
+   break;
+   }
+
+   if (baco_reset)
+   ret = soc15_asic_baco_reset(adev);
+   else
+   ret = soc15_asic_mode1_reset(adev);
+
+   return ret;
+}
+
 /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
u32 cntl_reg, u32 status_reg)
 {
-- 
2.17.1

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[PATCH 5/6] drm/amdgpu: expose BACO interfaces to upper level from PP

[Jim Qu]

Change-Id: Id9601a47afcd39107c94b6ae62577549e21a45ae
Signed-off-by: Jim Qu 
Reviewed-by: Alex Deucher 
Reviewed-by: Hawking Zhang 
---
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 54 +++
 .../drm/amd/powerplay/hwmgr/vega10_hwmgr.c|  4 ++
 2 files changed, 58 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c 
b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 9bc27f468d5b..5d8b5d3c2453 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -1404,6 +1404,57 @@ static int pp_set_active_display_count(void *handle, 
uint32_t count)
return ret;
 }
 
+static int pp_get_asic_baco_capability(void *handle, bool *cap)
+{
+   struct pp_hwmgr *hwmgr = handle;
+
+   if (!hwmgr)
+   return -EINVAL;
+
+   if (!hwmgr->pm_en || !hwmgr->hwmgr_func->get_asic_baco_capability)
+   return 0;
+
+   mutex_lock(>smu_lock);
+   hwmgr->hwmgr_func->get_asic_baco_capability(hwmgr, cap);
+   mutex_unlock(>smu_lock);
+
+   return 0;
+}
+
+static int pp_get_asic_baco_state(void *handle, int *state)
+{
+   struct pp_hwmgr *hwmgr = handle;
+
+   if (!hwmgr)
+   return -EINVAL;
+
+   if (!hwmgr->pm_en || !hwmgr->hwmgr_func->get_asic_baco_state)
+   return 0;
+
+   mutex_lock(>smu_lock);
+   hwmgr->hwmgr_func->get_asic_baco_state(hwmgr, (enum BACO_STATE *)state);
+   mutex_unlock(>smu_lock);
+
+   return 0;
+}
+
+static int pp_set_asic_baco_state(void *handle, int state)
+{
+   struct pp_hwmgr *hwmgr = handle;
+
+   if (!hwmgr)
+   return -EINVAL;
+
+   if (!hwmgr->pm_en || !hwmgr->hwmgr_func->set_asic_baco_state)
+   return 0;
+
+   mutex_lock(>smu_lock);
+   hwmgr->hwmgr_func->set_asic_baco_state(hwmgr, (enum BACO_STATE)state);
+   mutex_unlock(>smu_lock);
+
+   return 0;
+}
+
 static const struct amd_pm_funcs pp_dpm_funcs = {
.load_firmware = pp_dpm_load_fw,
.wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
@@ -1454,4 +1505,7 @@ static const struct amd_pm_funcs pp_dpm_funcs = {
.set_min_deep_sleep_dcefclk = pp_set_min_deep_sleep_dcefclk,
.set_hard_min_dcefclk_by_freq = pp_set_hard_min_dcefclk_by_freq,
.set_hard_min_fclk_by_freq = pp_set_hard_min_fclk_by_freq,
+   .get_asic_baco_capability = pp_get_asic_baco_capability,
+   .get_asic_baco_state = pp_get_asic_baco_state,
+   .set_asic_baco_state = pp_set_asic_baco_state,
 };
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index 91e3bbe6d61d..d1e262844619 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -48,6 +48,7 @@
 #include "ppinterrupt.h"
 #include "pp_overdriver.h"
 #include "pp_thermal.h"
+#include "vega10_baco.h"
 
 #include "smuio/smuio_9_0_offset.h"
 #include "smuio/smuio_9_0_sh_mask.h"
@@ -4980,6 +4981,9 @@ static const struct pp_hwmgr_func vega10_hwmgr_funcs = {
.set_power_limit = vega10_set_power_limit,
.odn_edit_dpm_table = vega10_odn_edit_dpm_table,
.get_performance_level = vega10_get_performance_level,
+   .get_asic_baco_capability = vega10_baco_get_capability,
+   .get_asic_baco_state = vega10_baco_get_state,
+   .set_asic_baco_state = vega10_baco_set_state,
 };
 
 int vega10_hwmgr_init(struct pp_hwmgr *hwmgr)
-- 
2.17.1

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[PATCH 4/6] drm/amdgpu: add BACO interfaces for vega10

[Jim Qu]

V2: delay 20ms before BACO out.
V3: rename function to vega10_baco_xxx

Change-Id: Ibd2b78a723ba56a90fe78b052b27d0ab0e45f0e5
Signed-off-by: Jim Qu 
Reviewed-by: Alex Deucher 
Reviewed-by: Hawking Zhang 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/Makefile  |   2 +-
 .../gpu/drm/amd/powerplay/hwmgr/vega10_baco.c | 136 ++
 .../gpu/drm/amd/powerplay/hwmgr/vega10_baco.h |  32 +
 3 files changed, 169 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.c
 create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.h

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile 
b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
index 5afec1a138ac..e563811b2ebe 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
@@ -35,7 +35,7 @@ HARDWARE_MGR = hwmgr.o processpptables.o \
vega12_thermal.o \
pp_overdriver.o smu_helper.o \
vega20_processpptables.o vega20_hwmgr.o vega20_powertune.o \
-   vega20_thermal.o common_baco.o
+   vega20_thermal.o common_baco.o vega10_baco.o
 
 AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR))
 
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.c
new file mode 100644
index ..f94dab27f486
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.c
@@ -0,0 +1,136 @@
+#include "amdgpu.h"
+#include "soc15.h"
+#include "soc15_hw_ip.h"
+#include "vega10_ip_offset.h"
+#include "soc15_common.h"
+#include "vega10_inc.h"
+#include "vega10_ppsmc.h"
+#include "vega10_baco.h"
+
+
+
+static const struct soc15_baco_cmd_entry  pre_baco_tbl[] =
+{
+   {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(NBIF, 0, mmBIF_DOORBELL_CNTL), 
BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK, 
BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT, 0, 1},
+   {CMD_WRITE, SOC15_REG_ENTRY(NBIF, 0, mmBIF_FB_EN), 0, 0, 0, 0},
+   {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(NBIF, 0, mmBACO_CNTL), 
BACO_CNTL__BACO_DSTATE_BYPASS_MASK, BACO_CNTL__BACO_DSTATE_BYPASS__SHIFT, 0, 1},
+   {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(NBIF, 0, mmBACO_CNTL), 
BACO_CNTL__BACO_RST_INTR_MASK_MASK, BACO_CNTL__BACO_RST_INTR_MASK__SHIFT, 0, 1}
+};
+
+static const struct soc15_baco_cmd_entry enter_baco_tbl[] =
+{
+   {CMD_WAITFOR, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), 
THM_BACO_CNTL__SOC_DOMAIN_IDLE_MASK, THM_BACO_CNTL__SOC_DOMAIN_IDLE__SHIFT, 
0x, 0x8000},
+   {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(NBIF, 0, mmBACO_CNTL), 
BACO_CNTL__BACO_EN_MASK, BACO_CNTL__BACO_EN__SHIFT, 0, 1},
+   {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(NBIF, 0, mmBACO_CNTL), 
BACO_CNTL__BACO_BIF_LCLK_SWITCH_MASK, BACO_CNTL__BACO_BIF_LCLK_SWITCH__SHIFT, 
0, 1},
+   {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(NBIF, 0, mmBACO_CNTL), 
BACO_CNTL__BACO_DUMMY_EN_MASK, BACO_CNTL__BACO_DUMMY_EN__SHIFT, 0, 1},
+   {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), 
THM_BACO_CNTL__BACO_SOC_VDCI_RESET_MASK, 
THM_BACO_CNTL__BACO_SOC_VDCI_RESET__SHIFT, 0, 1},
+   {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), 
THM_BACO_CNTL__BACO_SMNCLK_MUX_MASK, THM_BACO_CNTL__BACO_SMNCLK_MUX__SHIFT,0, 
1},
+   {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), 
THM_BACO_CNTL__BACO_ISO_EN_MASK, THM_BACO_CNTL__BACO_ISO_EN__SHIFT, 0, 1},
+   {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), 
THM_BACO_CNTL__BACO_AEB_ISO_EN_MASK, THM_BACO_CNTL__BACO_AEB_ISO_EN__SHIFT,0, 
1},
+   {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), 
THM_BACO_CNTL__BACO_ANA_ISO_EN_MASK, THM_BACO_CNTL__BACO_ANA_ISO_EN__SHIFT, 0, 
1},
+   {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), 
THM_BACO_CNTL__BACO_SOC_REFCLK_OFF_MASK, 
THM_BACO_CNTL__BACO_SOC_REFCLK_OFF__SHIFT, 0, 1},
+   {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(NBIF, 0, mmBACO_CNTL), 
BACO_CNTL__BACO_POWER_OFF_MASK, BACO_CNTL__BACO_POWER_OFF__SHIFT, 0, 1},
+   {CMD_DELAY_MS, 0, 0, 0, 0, 0, 0, 5, 0},
+   {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), 
THM_BACO_CNTL__BACO_RESET_EN_MASK, THM_BACO_CNTL__BACO_RESET_EN__SHIFT, 0, 1},
+   {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), 
THM_BACO_CNTL__BACO_PWROKRAW_CNTL_MASK, 
THM_BACO_CNTL__BACO_PWROKRAW_CNTL__SHIFT, 0, 0},
+   {CMD_WAITFOR, SOC15_REG_ENTRY(NBIF, 0, mmBACO_CNTL), 
BACO_CNTL__BACO_MODE_MASK, BACO_CNTL__BACO_MODE__SHIFT, 0x, 0x100}
+};
+
+static const struct soc15_baco_cmd_entry exit_baco_tbl[] =
+{
+   {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(NBIF, 0, mmBACO_CNTL), 
BACO_CNTL__BACO_POWER_OFF_MASK, BACO_CNTL__BACO_POWER_OFF__SHIFT, 0, 0},
+   {CMD_DELAY_MS, 0, 0, 0, 0, 0, 0, 10,0},
+   {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), 
THM_BACO_CNTL__BACO_SOC_REFCLK_OFF_MASK, 
THM_BACO_CNTL__BACO_SOC_REFCLK_OFF__SHIFT, 0,0},
+   

[PATCH 0/6] Enable BACO function for VGf10

[Jim Qu]

Bus Alive Chip Off Power mode(BACO) refers to the case in which
the power consumption in the GPU is at its lowest level while
keeping the PCIe config space alive.

Jim Qu (6):
  drm/amdgpu: update nbio v6.1 register/master to support BACO
  drm/amdgpu: add BACO interfaces in pm and hwmgr function table
  drm/amdpgu: add common functions for BACO feature in PP
  drm/amdgpu: add BACO interfaces for vega10
  drm/amdgpu: expose BACO interfaces to upper level from PP
  drm/amdgpu: use BACO reset if platform support

 drivers/gpu/drm/amd/amdgpu/soc15.c|  62 +++-
 .../include/asic_reg/nbio/nbio_6_1_offset.h   |   2 +
 .../include/asic_reg/nbio/nbio_6_1_sh_mask.h  |   4 +
 .../gpu/drm/amd/include/kgd_pp_interface.h|   3 +
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c |  54 +++
 drivers/gpu/drm/amd/powerplay/hwmgr/Makefile  |   2 +-
 .../gpu/drm/amd/powerplay/hwmgr/common_baco.c |  98 +
 .../gpu/drm/amd/powerplay/hwmgr/common_baco.h |  50 +++
 .../gpu/drm/amd/powerplay/hwmgr/vega10_baco.c | 136 ++
 .../gpu/drm/amd/powerplay/hwmgr/vega10_baco.h |  32 +
 .../drm/amd/powerplay/hwmgr/vega10_hwmgr.c|   4 +
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h |   8 ++
 12 files changed, 451 insertions(+), 4 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.c
 create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.h
 create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.c
 create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.h

-- 
2.17.1

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[PATCH 2/6] drm/amdgpu: add BACO interfaces in pm and hwmgr function table

[Jim Qu]

Change-Id: I55e58b4627e6d5935dbe56657bef65f37b2a39b3
Signed-off-by: Jim Qu 
Reviewed-by: Alex Deucher 
Reviewed-by: Hawking Zhang 
---
 drivers/gpu/drm/amd/include/kgd_pp_interface.h | 3 +++
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h  | 8 
 2 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h 
b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index 789c4f288485..a2ea4c933360 100644
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -281,6 +281,9 @@ struct amd_pm_funcs {
int (*set_hard_min_dcefclk_by_freq)(void *handle, uint32_t clock);
int (*set_hard_min_fclk_by_freq)(void *handle, uint32_t clock);
int (*set_min_deep_sleep_dcefclk)(void *handle, uint32_t clock);
+   int (*get_asic_baco_capability)(void *handle, bool *cap);
+   int (*get_asic_baco_state)(void *handle, int *state);
+   int (*set_asic_baco_state)(void *handle, int state);
 };
 
 #endif
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 
b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index be4f87aed99c..577cec90aef1 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -47,6 +47,11 @@ enum DISPLAY_GAP {
 };
 typedef enum DISPLAY_GAP DISPLAY_GAP;
 
+enum BACO_STATE {
+   BACO_STATE_OUT = 0,
+   BACO_STATE_IN,
+};
+
 struct vi_dpm_level {
bool enabled;
uint32_t value;
@@ -333,6 +338,9 @@ struct pp_hwmgr_func {
int (*enable_mgpu_fan_boost)(struct pp_hwmgr *hwmgr);
int (*set_hard_min_dcefclk_by_freq)(struct pp_hwmgr *hwmgr, uint32_t 
clock);
int (*set_hard_min_fclk_by_freq)(struct pp_hwmgr *hwmgr, uint32_t 
clock);
+   int (*get_asic_baco_capability)(struct pp_hwmgr *hwmgr, bool *cap);
+   int (*get_asic_baco_state)(struct pp_hwmgr *hwmgr, enum BACO_STATE 
*state);
+   int (*set_asic_baco_state)(struct pp_hwmgr *hwmgr, enum BACO_STATE 
state);
 };
 
 struct pp_table_func {
-- 
2.17.1

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[PATCH 1/6] drm/amdgpu: update nbio v6.1 register/master to support BACO

[Jim Qu]

Change-Id: I119c30c8b70911be59d2e42501ad7aa7dffcfe61
Signed-off-by: Jim Qu 
Reviewed-by: Alex Deucher 
Reviewed-by: Hawking Zhang 
---
 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_offset.h  | 2 ++
 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_sh_mask.h | 4 
 2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_offset.h 
b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_offset.h
index 13d4de645190..d8e0dd192fdd 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_offset.h
@@ -2247,6 +2247,8 @@
 
 // addressBlock: nbio_nbif_rcc_strap_BIFDEC1[13440..14975]
 // base address: 0x3480
+#define mmRCC_BIF_STRAP0   
0x
+#define mmRCC_BIF_STRAP0_BASE_IDX  
2
 #define mmRCC_DEV0_EPF0_STRAP0 
0x000f
 #define mmRCC_DEV0_EPF0_STRAP0_BASE_IDX
2
 
diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_sh_mask.h 
b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_sh_mask.h
index a02b67943372..29af5167cd00 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_sh_mask.h
@@ -16838,6 +16838,10 @@
 
 
 // addressBlock: nbio_nbif_rcc_strap_BIFDEC1[13440..14975]
+//RCC_BIF_STRAP0
+#define RCC_BIF_STRAP0__STRAP_PX_CAPABLE__SHIFT
   0x7
+#define RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK  
   0x0080L
+
 //RCC_DEV0_EPF0_STRAP0
 #define RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT   
   0x0
 #define RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT
   0x10
-- 
2.17.1

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Re: After Vega 56/64 GPU hang I unable reboot system

[Mikhail Gavrilov]

On Thu, 10 Jan 2019 at 01:35, Grodzovsky, Andrey
 wrote:
>
> I think the 'verbose' flag causes it do dump so much output, maybe try 
> without it in ALL the commands above.
> Are you are aware of any particular application during which run this happens 
> ?
>

Last logs related to situation when I launch the game "Shadow of the
Tomb Raider" via proton 3.16-16.
Occurs every time when the game menu should appear after game launching.

--
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Mike Gavrilov.
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[PATCH] drm/amdgpu: Add missing power attribute to APU check

[Alex Deucher]

Add missing power_average to visible check for power
attributesi for APUs.  Was missed before.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 51eb2cf42b81..979d96278413 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -1799,7 +1799,8 @@ static umode_t hwmon_attributes_visible(struct kobject 
*kobj,
effective_mode &= ~S_IWUSR;
 
if ((adev->flags & AMD_IS_APU) &&
-   (attr == _dev_attr_power1_cap_max.dev_attr.attr ||
+   (attr == _dev_attr_power1_average.dev_attr.attr ||
+attr == _dev_attr_power1_cap_max.dev_attr.attr ||
 attr == _dev_attr_power1_cap_min.dev_attr.attr||
 attr == _dev_attr_power1_cap.dev_attr.attr))
return 0;
-- 
2.20.1

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Re: [PATCH] WIP: drm/amd/display: dc/irq: use dce_6_0_{d,sh_mask}.h

[Mauro Rossi]

Hi,
just not to keep you engaged on this,
I've got the vblank irq handling working now.

I had exactly to replicate in dce60_irq_service.c the behavior of commit
b10d51f8 ("drm/amd/display: Add interrupt entries for VBLANK isr.")
and behavior of b57de80a ("drm/amd/display: Register on VLBLANK ISR.")
in amdgpu_dm.c

From functional point of view IRQ handling for DCE6 is complete,
I can proceed with other improvements, like Line Buffer/Watermark programming,
and VGA support for Kaveri and older.

Some suggestion those two areas by AMD developers would be very much
appreciated.

Kind regards
Mauro

On Wed, Jan 9, 2019 at 8:07 PM Mauro Rossi  wrote:
>
> Ah-ha! (Meaning self-checking and trying to self-correct myself)
>
> I've seen that commit b10d51f8 ("drm/amd/display: Add interrupt
> entries for VBLANK isr.")
> required to be complemented by b57de80a ("drm/amd/display: Register on
> VLBLANK ISR.")
> which changed vblank irq control in dce110_register_irq_handlers() in file
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
>
> In this WIP I did not applied changes in amdgpu_dm_irq.c accordingly
> and this is the most probable root cause for screen being always blank
>
> I will specialize a dce60_register_irq_handlers()
> within braces #if defined(CONFIG_DRM_AMD_DC_SI)/#endif
> and replicate the behavior of  b57de80a ("drm/amd/display: Register on
> VLBLANK ISR.")
>
> Please let me know if I'm at least going in the right direction
> and confirm that there is no other VBLANK Interrupt Register to be used in 
> DCE6,
> if there is some other VBLANK Interrupt Register better than the one I found
> I'd like to know to implement directly the best solution.
>
> Mauro
>
> On Wed, Jan 2, 2019 at 1:12 AM Mauro Rossi  wrote:
> >
> > Work In Progress for using DCE6 headers
> > vblank registers and masks where identified,
> > but using them gives a glipse with monitor screen active,
> > followed by monitor screen in standby
> >
> > Please review to identify the problem
> > as the DCE6 vblank irq do not map exactlyto DC irq code,
> > it's not clear how to_dal_irq_source_dce60 should be defined and used
> > and it's not clear how to manage the DCE6 registers
> > in the following struct:
> >
> > static const struct irq_source_info_funcs vblank_irq_info_funcs = {
> > .set = dce110_vblank_set,
> > .ack = NULL
> > };
> > ---
> >  .../display/dc/irq/dce60/irq_service_dce60.c  | 116 +++---
> >  .../display/dc/irq/dce60/irq_service_dce60.h  |   5 +
> >  .../drm/amd/include/asic_reg/dce/dce_6_0_d.h  |  14 +++
> >  .../include/asic_reg/dce/dce_6_0_sh_mask.h|  24 
> >  4 files changed, 145 insertions(+), 14 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c 
> > b/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
> > index 107e0dcb5f80..c3befab49374 100644
> > --- a/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
> > +++ b/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
> > @@ -30,10 +30,17 @@
> >  #include "irq_service_dce60.h"
> >  #include "../dce110/irq_service_dce110.h"
> >
> > -#include "dce/dce_8_0_d.h"
> > -#include "dce/dce_8_0_sh_mask.h"
> > -
> > +#include "dce/dce_6_0_d.h"
> > +#include "dce/dce_6_0_sh_mask.h"
> > +/* Q1: Are the DCE8 Interrupt Vector tables applicable to DCE6? */
> >  #include "ivsrcid/ivsrcid_vislands30.h"
> > +/* See b10d51f8 ("drm/amd/display: Add interrupt entries for VBLANK isr.") 
> > */
> > +#define VISLANDS30_IV_SRCID_D1_VBLANK1
> > +#define VISLANDS30_IV_SRCID_D2_VBLANK2
> > +#define VISLANDS30_IV_SRCID_D3_VBLANK3
> > +#define VISLANDS30_IV_SRCID_D4_VBLANK4
> > +#define VISLANDS30_IV_SRCID_D5_VBLANK5
> > +#define VISLANDS30_IV_SRCID_D6_VBLANK6
> >
> >  #include "dc_types.h"
> >
> > @@ -78,7 +85,7 @@ static const struct irq_source_info_funcs 
> > pflip_irq_info_funcs = {
> > .set = NULL,
> > .ack = NULL
> >  };
> > -
> > + /* NOTE: .set = NULL in commit b10d51f8 Q2: Can dce110_vblank_set be used 
> > here? */
> >  static const struct irq_source_info_funcs vblank_irq_info_funcs = {
> > .set = dce110_vblank_set,
> > .ack = NULL
> > @@ -145,21 +152,21 @@ static const struct irq_source_info_funcs 
> > vblank_irq_info_funcs = {
> > .funcs = _irq_info_funcs\
> > }
> >
> > +/* NOTE: vblank_irq_info_funcs.set = dce110_vblank instead of NULL (see 
> > b10d51f8) */
> >  #define vblank_int_entry(reg_num)\
> > [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
> > -   .enable_reg = mmCRTC ## reg_num ## 
> > _CRTC_VERTICAL_INTERRUPT0_CONTROL,\
> > +   .enable_reg = mmLB ## reg_num ## _INT_MASK,\
> > .enable_mask =\
> > -   
> > CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\
> > +   

Re: [PATCH libdrm] amdgpu: add a faster BO list API

[Marek Olšák]

On Wed, Jan 9, 2019 at 1:41 PM Christian König <
ckoenig.leichtzumer...@gmail.com> wrote:

> Am 09.01.19 um 17:14 schrieb Marek Olšák:
>
> On Wed, Jan 9, 2019 at 8:09 AM Christian König <
> ckoenig.leichtzumer...@gmail.com> wrote:
>
>> Am 09.01.19 um 13:36 schrieb Marek Olšák:
>>
>>
>>
>> On Wed, Jan 9, 2019, 5:28 AM Christian König <
>> ckoenig.leichtzumer...@gmail.com wrote:
>>
>>> Looks good, but I'm wondering what's the actual improvement?
>>>
>>
>> No malloc calls and 1 less for loop copying the bo list.
>>
>>
>> Yeah, but didn't we want to get completely rid of the bo list?
>>
>
> If we have multiple IBs (e.g. gfx + compute) that share a BO list, I think
> it's faster to send the BO list to the kernel only once.
>
>
> That's not really faster.
>
> The only thing we safe us is a single loop over all BOs to lockup the
> handle into a pointer and that is only a tiny fraction of the overhead.
>
> The majority of the overhead is locking the BOs and reserving space for
> the submission.
>
> What could really help here is to submit gfx+comput together in just one
> CS IOCTL. This way we would need the locking and space reservation only
> once.
>
> It's a bit of work in the kernel side, but certainly doable.
>

OK. Any objections to this patch?

Thanks,
Marek
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Re: After Vega 56/64 GPU hang I unable reboot system

[Grodzovsky, Andrey]

Can you launch Poton from command line appending GALLIUM_DDEBUG=1000 
before the command ? This should create MESA debug info in ~/ddebug_dumps/

Andrey


On 01/09/2019 04:12 PM, Mikhail Gavrilov wrote:
> On Thu, 10 Jan 2019 at 01:35, Grodzovsky, Andrey
>  wrote:
>> I think the 'verbose' flag causes it do dump so much output, maybe try 
>> without it in ALL the commands above.
>> Are you are aware of any particular application during which run this 
>> happens ?
>>
> Last logs related to situation when I launch the game "Shadow of the
> Tomb Raider" via proton 3.16-16.
> Occurs every time when the game menu should appear after game launching.
>
> --
> Best Regards,
> Mike Gavrilov.

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[pull] amdgpu drm-fixes-5.0

[Alex Deucher]

Hi Dave, Daniel,

Fixes for 5.0.  Highlights:
- Powerplay fixes
- Virtual display pinning fixes
- Golden register updates for vega
- Pitch and gem size validation fixes
- Fix for error case in sr-iov init
- Disable page tables in system memory on RV due to issues with IOMMU
  reported on some platforms

The following changes since commit 74136a3d47f51ae72ee8b9ebc1ec2a29bcf30676:

  Merge branch 'drm-next-4.21' of git://people.freedesktop.org/~agd5f/linux 
into drm-next (2018-12-31 08:29:54 +1000)

are available in the Git repository at:

  git://people.freedesktop.org/~agd5f/linux drm-fixes-5.0

for you to fetch changes up to 1c1eba86339c8517814863bc7dd21e2661a84e77:

  drm/amdgpu: disable system memory page tables for now (2019-01-09 15:01:18 
-0500)


Christian König (1):
  drm/amdgpu: disable system memory page tables for now

Emily Deng (3):
  drm/amdgpu/virtual_dce: No need to pin the fb's bo
  drm/amdgpu/virtual_dce: No need to pin the cursor bo
  drm/amdgpu/sriov:Correct pfvf exchange logic

Evan Quan (5):
  drm/amd/powerplay: support BOOTUP_DEFAULT power profile mode
  drm/amd/powerplay: update OD support flag for SKU with no OD capabilities
  drm/amd/powerplay: create pp_od_clk_voltage device file under OD support
  drm/amd/powerplay: avoid possible buffer overflow
  drm/amd/powerplay: drop the unnecessary uclk hard min setting

Jim Qu (1):
  drm/amdgpu: set WRITE_BURST_LENGTH to 64B to workaround SDMA1 hang

Kent Russell (1):
  drm/amdgpu: Cleanup 2 compiler warnings

Likun Gao (1):
  drm/amdgpu: make gfx9 enter into rlc safe mode when set MGCG

Tao Zhou (1):
  drm/amdgpu: fix CPDMA hang in PRT mode for VEGA20

Tiecheng Zhou (1):
  drm/amdgpu/gfx_v8_0: Reorder the gfx, kiq and kcq rings test sequence

Yu Zhao (2):
  drm/amdgpu: validate user pitch alignment
  drm/amdgpu: validate user GEM object size

 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 12 +++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_display.c| 38 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 22 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c |  3 --
 drivers/gpu/drm/amd/amdgpu/dce_virtual.c   | 17 ++--
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c  | 48 +++---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c  | 14 ---
 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c  |  2 +-
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c |  3 +-
 drivers/gpu/drm/amd/include/kgd_pp_interface.h | 13 +++---
 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c| 24 ++-
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c   |  8 ++--
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 12 +++---
 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 34 ++-
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h  |  2 +-
 15 files changed, 156 insertions(+), 96 deletions(-)
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Re: After Vega 56/64 GPU hang I unable reboot system

[Grodzovsky, Andrey]

On 01/09/2019 02:36 PM, Mikhail Gavrilov wrote:
> On Mon, 7 Jan 2019 at 23:47, Grodzovsky, Andrey
>  wrote:
>> I see 'no active waves' print meaning it's not shader hang.
>>
>> We can try and estimate around which commands the hang occurred - in
>> addition to what you already print please also dump
>>
>> sudo umr -O many,bits  -r *.*.mmGRBM_STATUS* && sudo umr -O many,bits
>> -r *.*.mmCP_EOP_* && sudo umr -O many,bits -r *.*.mmCP_PFP_HEADER_DUMP
>> && sudo umr -O many,bits  -r *.*.mmCP_ME_HEADER_DUMP
>>
>> Andrey
>>
> All new one logs attached here.
>
> Thanks.
>
> P.S. This time I had to terminate command `./umr -O verbose,follow -R
> gfx[.] > gfx.log 2>&1` cause it tried to write log infinitely.
> I also had to terminate command `./umr -O verbose,follow -R gfx[.] >
> gfx.log 2>&1` cause it stuck for a long time.
>
>
> --
> Best Regards,
> Mike Gavrilov.

I think the 'verbose' flag causes it do dump so much output, maybe try without 
it in ALL the commands above.
Are you are aware of any particular application during which run this happens ?

Andrey


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[bug report] drm/amd/dc: Add dc display driver (v2)

[Dan Carpenter]

Hello Harry Wentland,

This is a semi-automatic email about new static checker warnings.

The patch 4562236b3bc0: "drm/amd/dc: Add dc display driver (v2)" from 
Sep 12, 2017, leads to the following Smatch complaint:

drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:754 construct()
error: we previously assumed 'dc->current_state' could be null (see line 
677)

drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c
   676  
   677  if (!dc->current_state) {
^^

   678  dm_error("%s: failed to create validate ctx\n", 
__func__);
   679  goto fail;
^

   680  }
   681  
   682  /* Create logger */
   683  
   684  dc_ctx->dce_environment = init_params->dce_environment;
   685  
   686  dc_version = resource_parse_asic_id(init_params->asic_id);
   687  dc_ctx->dce_version = dc_version;
   688  
   689  /* Resource should construct all asic specific resources.
   690   * This should be the only place where we need to parse the 
asic id
   691   */
   692  if (init_params->vbios_override)
   693  dc_ctx->dc_bios = init_params->vbios_override;
   694  else {
   695  /* Create BIOS parser */
   696  struct bp_init_data bp_init_data;
   697  
   698  bp_init_data.ctx = dc_ctx;
   699  bp_init_data.bios = 
init_params->asic_id.atombios_base_address;
   700  
   701  dc_ctx->dc_bios = dal_bios_parser_create(
   702  _init_data, dc_version);
   703  
   704  if (!dc_ctx->dc_bios) {
   705  ASSERT_CRITICAL(false);
   706  goto fail;
   707  }
   708  
   709  dc_ctx->created_bios = true;
   710  }
   711  
   712  /* Create I2C AUX */
   713  dc_ctx->i2caux = dal_i2caux_create(dc_ctx);
   714  
   715  if (!dc_ctx->i2caux) {
   716  ASSERT_CRITICAL(false);
   717  goto fail;
   718  }
   719  
   720  dc_ctx->perf_trace = dc_perf_trace_create();
   721  if (!dc_ctx->perf_trace) {
   722  ASSERT_CRITICAL(false);
   723  goto fail;
   724  }
   725  
   726  /* Create GPIO service */
   727  dc_ctx->gpio_service = dal_gpio_service_create(
   728  dc_version,
   729  dc_ctx->dce_environment,
   730  dc_ctx);
   731  
   732  if (!dc_ctx->gpio_service) {
   733  ASSERT_CRITICAL(false);
   734  goto fail;
   735  }
   736  
   737  dc->res_pool = dc_create_resource_pool(
   738  dc,
   739  init_params->num_virtual_links,
   740  dc_version,
   741  init_params->asic_id);
   742  if (!dc->res_pool)
   743  goto fail;
   744  
   745  dc_resource_state_construct(dc, dc->current_state);
   746  
   747  if (!create_links(dc, init_params->num_virtual_links))
   748  goto fail;
   749  
   750  return true;
   751  
   752  fail:
   753  
   754  destruct(dc);
 ^^
"dc->current_state" gets dereferenced inside the function.  This style
of one function cleans up everything error handling is always buggy...

:/

https://plus.google.com/u/0/106378716002406849458/posts/1Ud9JbaYnPr

   755  return false;
   756  }

regards,
dan carpenter
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Re: [PATCH] WIP: drm/amd/display: dc/irq: use dce_6_0_{d,sh_mask}.h

[Mauro Rossi]

Ah-ha! (Meaning self-checking and trying to self-correct myself)

I've seen that commit b10d51f8 ("drm/amd/display: Add interrupt
entries for VBLANK isr.")
required to be complemented by b57de80a ("drm/amd/display: Register on
VLBLANK ISR.")
which changed vblank irq control in dce110_register_irq_handlers() in file
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

In this WIP I did not applied changes in amdgpu_dm_irq.c accordingly
and this is the most probable root cause for screen being always blank

I will specialize a dce60_register_irq_handlers()
within braces #if defined(CONFIG_DRM_AMD_DC_SI)/#endif
and replicate the behavior of  b57de80a ("drm/amd/display: Register on
VLBLANK ISR.")

Please let me know if I'm at least going in the right direction
and confirm that there is no other VBLANK Interrupt Register to be used in DCE6,
if there is some other VBLANK Interrupt Register better than the one I found
I'd like to know to implement directly the best solution.

Mauro

On Wed, Jan 2, 2019 at 1:12 AM Mauro Rossi  wrote:
>
> Work In Progress for using DCE6 headers
> vblank registers and masks where identified,
> but using them gives a glipse with monitor screen active,
> followed by monitor screen in standby
>
> Please review to identify the problem
> as the DCE6 vblank irq do not map exactlyto DC irq code,
> it's not clear how to_dal_irq_source_dce60 should be defined and used
> and it's not clear how to manage the DCE6 registers
> in the following struct:
>
> static const struct irq_source_info_funcs vblank_irq_info_funcs = {
> .set = dce110_vblank_set,
> .ack = NULL
> };
> ---
>  .../display/dc/irq/dce60/irq_service_dce60.c  | 116 +++---
>  .../display/dc/irq/dce60/irq_service_dce60.h  |   5 +
>  .../drm/amd/include/asic_reg/dce/dce_6_0_d.h  |  14 +++
>  .../include/asic_reg/dce/dce_6_0_sh_mask.h|  24 
>  4 files changed, 145 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c 
> b/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
> index 107e0dcb5f80..c3befab49374 100644
> --- a/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
> +++ b/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
> @@ -30,10 +30,17 @@
>  #include "irq_service_dce60.h"
>  #include "../dce110/irq_service_dce110.h"
>
> -#include "dce/dce_8_0_d.h"
> -#include "dce/dce_8_0_sh_mask.h"
> -
> +#include "dce/dce_6_0_d.h"
> +#include "dce/dce_6_0_sh_mask.h"
> +/* Q1: Are the DCE8 Interrupt Vector tables applicable to DCE6? */
>  #include "ivsrcid/ivsrcid_vislands30.h"
> +/* See b10d51f8 ("drm/amd/display: Add interrupt entries for VBLANK isr.") */
> +#define VISLANDS30_IV_SRCID_D1_VBLANK1
> +#define VISLANDS30_IV_SRCID_D2_VBLANK2
> +#define VISLANDS30_IV_SRCID_D3_VBLANK3
> +#define VISLANDS30_IV_SRCID_D4_VBLANK4
> +#define VISLANDS30_IV_SRCID_D5_VBLANK5
> +#define VISLANDS30_IV_SRCID_D6_VBLANK6
>
>  #include "dc_types.h"
>
> @@ -78,7 +85,7 @@ static const struct irq_source_info_funcs 
> pflip_irq_info_funcs = {
> .set = NULL,
> .ack = NULL
>  };
> -
> + /* NOTE: .set = NULL in commit b10d51f8 Q2: Can dce110_vblank_set be used 
> here? */
>  static const struct irq_source_info_funcs vblank_irq_info_funcs = {
> .set = dce110_vblank_set,
> .ack = NULL
> @@ -145,21 +152,21 @@ static const struct irq_source_info_funcs 
> vblank_irq_info_funcs = {
> .funcs = _irq_info_funcs\
> }
>
> +/* NOTE: vblank_irq_info_funcs.set = dce110_vblank instead of NULL (see 
> b10d51f8) */
>  #define vblank_int_entry(reg_num)\
> [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
> -   .enable_reg = mmCRTC ## reg_num ## 
> _CRTC_VERTICAL_INTERRUPT0_CONTROL,\
> +   .enable_reg = mmLB ## reg_num ## _INT_MASK,\
> .enable_mask =\
> -   
> CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\
> +   INT_MASK__VBLANK_INT_MASK,\
> .enable_value = {\
> -   
> CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\
> -   
> ~CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK},\
> -   .ack_reg = mmCRTC ## reg_num ## 
> _CRTC_VERTICAL_INTERRUPT0_CONTROL,\
> +   INT_MASK__VBLANK_INT_MASK,\
> +   ~INT_MASK__VBLANK_INT_MASK},\
> +   .ack_reg = mmLB ## reg_num ## _VBLANK_STATUS,\
> .ack_mask =\
> -   
> CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK,\
> +   VBLANK_STATUS__VBLANK_ACK_MASK,\
> .ack_value =\
> -   
> CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK,\
> -   .funcs = 

Re: [PATCH libdrm] amdgpu: add a faster BO list API

[Christian König]

Am 09.01.19 um 17:14 schrieb Marek Olšák:
On Wed, Jan 9, 2019 at 8:09 AM Christian König 
> wrote:


Am 09.01.19 um 13:36 schrieb Marek Olšák:



On Wed, Jan 9, 2019, 5:28 AM Christian König
mailto:ckoenig.leichtzumer...@gmail.com> wrote:

Looks good, but I'm wondering what's the actual improvement?


No malloc calls and 1 less for loop copying the bo list.


Yeah, but didn't we want to get completely rid of the bo list?


If we have multiple IBs (e.g. gfx + compute) that share a BO list, I 
think it's faster to send the BO list to the kernel only once.


That's not really faster.

The only thing we safe us is a single loop over all BOs to lockup the 
handle into a pointer and that is only a tiny fraction of the overhead.


The majority of the overhead is locking the BOs and reserving space for 
the submission.


What could really help here is to submit gfx+comput together in just one 
CS IOCTL. This way we would need the locking and space reservation only 
once.


It's a bit of work in the kernel side, but certainly doable.

Christian.



Marek

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Re: [PATCH v5 1/2] drm/sched: Refactor ring mirror list handling.

[Grodzovsky, Andrey]

On 01/09/2019 05:22 AM, Christian König wrote:
> Am 07.01.19 um 20:47 schrieb Grodzovsky, Andrey:
>>
>> On 01/07/2019 09:13 AM, Christian König wrote:
>>> Am 03.01.19 um 18:42 schrieb Grodzovsky, Andrey:
 On 01/03/2019 11:20 AM, Grodzovsky, Andrey wrote:
> On 01/03/2019 03:54 AM, Koenig, Christian wrote:
>> Am 21.12.18 um 21:36 schrieb Grodzovsky, Andrey:
>>> On 12/21/2018 01:37 PM, Christian König wrote:
 Am 20.12.18 um 20:23 schrieb Andrey Grodzovsky:
> Decauple sched threads stop and start and ring mirror
> list handling from the policy of what to do about the
> guilty jobs.
> When stoppping the sched thread and detaching sched fences
> from non signaled HW fenes wait for all signaled HW fences
> to complete before rerunning the jobs.
>
> v2: Fix resubmission of guilty job into HW after refactoring.
>
> v4:
> Full restart for all the jobs, not only from guilty ring.
> Extract karma increase into standalone function.
>
> v5:
> Rework waiting for signaled jobs without relying on the job
> struct itself as those might already be freed for non 'guilty'
> job's schedulers.
> Expose karma increase to drivers.
>
> Suggested-by: Christian Koenig 
> Signed-off-by: Andrey Grodzovsky 
> ---
>    drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  18 +--
>    drivers/gpu/drm/etnaviv/etnaviv_sched.c |  11 +-
>    drivers/gpu/drm/scheduler/sched_main.c | 188
> +++--
>    drivers/gpu/drm/v3d/v3d_sched.c |  12 +-
>    include/drm/gpu_scheduler.h |  10 +-
>    5 files changed, 151 insertions(+), 88 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 8a078f4..a4bd2d3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -3298,12 +3298,10 @@ static int
> amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
>    if (!ring || !ring->sched.thread)
>    continue;
>    - kthread_park(ring->sched.thread);
> +    drm_sched_stop(>sched, job ? >base : NULL);
>    -    if (job && job->base.sched != >sched)
> -    continue;
> -
> - drm_sched_hw_job_reset(>sched, job ? >base :
> NULL);
> +    if(job)
> + drm_sched_increase_karma(>base);
 Since we dropped the "job && job->base.sched != >sched" 
 check
 above this will now increase the jobs karma multiple times.

 Maybe just move that outside of the loop.

>      /* after all hw jobs are reset, hw fence is
> meaningless,
> so force_completion */
> amdgpu_fence_driver_force_completion(ring);
> @@ -3454,14 +3452,10 @@ static void
> amdgpu_device_post_asic_reset(struct amdgpu_device *adev,
>    if (!ring || !ring->sched.thread)
>    continue;
>    -    /* only need recovery sched of the given job's 
> ring
> - * or all rings (in the case @job is NULL)
> - * after above amdgpu_reset accomplished
> - */
> -    if ((!job || job->base.sched == >sched) &&
> !adev->asic_reset_res)
> - drm_sched_job_recovery(>sched);
> +    if (!adev->asic_reset_res)
> + drm_sched_resubmit_jobs(>sched);
>    - kthread_unpark(ring->sched.thread);
> +    drm_sched_start(>sched, !adev->asic_reset_res);
>    }
>      if (!amdgpu_device_has_dc_support(adev)) {
> diff --git a/drivers/gpu/drm/etnaviv/etnaviv_sched.c
> b/drivers/gpu/drm/etnaviv/etnaviv_sched.c
> index 49a6763..6f1268f 100644
> --- a/drivers/gpu/drm/etnaviv/etnaviv_sched.c
> +++ b/drivers/gpu/drm/etnaviv/etnaviv_sched.c
> @@ -109,16 +109,19 @@ static void 
> etnaviv_sched_timedout_job(struct
> drm_sched_job *sched_job)
>    }
>      /* block scheduler */
> -    kthread_park(gpu->sched.thread);
> -    drm_sched_hw_job_reset(>sched, sched_job);
> +    drm_sched_stop(>sched, sched_job);
> +
> +    if(sched_job)
> +    drm_sched_increase_karma(sched_job);
>      /* get the GPU back into the init state */
>    etnaviv_core_dump(gpu);
>    etnaviv_gpu_recover_hang(gpu);
>    + drm_sched_resubmit_jobs(>sched);
> +
>    /* restart scheduler after GPU is usable again */

RE: [PATCH 1/2] drm/amdgpu: Add NBIO SMN headers v2

[Kuehling, Felix]

The series is reviewed by me too.

Reviewed-by: Felix Kuehling 

From: amd-gfx  On Behalf Of Deucher, 
Alexander
Sent: Wednesday, January 09, 2019 10:06 AM
To: Russell, Kent ; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/2] drm/amdgpu: Add NBIO SMN headers v2


Series is:

Reviewed-by: Alex Deucher 
mailto:alexander.deuc...@amd.com>>


From: amd-gfx 
mailto:amd-gfx-boun...@lists.freedesktop.org>>
 on behalf of Russell, Kent mailto:kent.russ...@amd.com>>
Sent: Wednesday, January 9, 2019 9:43:51 AM
To: amd-gfx@lists.freedesktop.org
Cc: Russell, Kent
Subject: [PATCH 1/2] drm/amdgpu: Add NBIO SMN headers v2

We need these offsets for PCIE perf counters, so include them as well as
the the previously-used defines from the nbio_*.c files

v2: Return NBIF definitions back to previous files

Signed-off-by: Kent Russell mailto:kent.russ...@amd.com>>
---
 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c |  6 +--
 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c |  4 +-
 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c |  5 +-
 .../drm/amd/include/asic_reg/nbio/nbio_6_1_smn.h   | 58 ++
 .../drm/amd/include/asic_reg/nbio/nbio_7_0_smn.h   | 54 
 .../drm/amd/include/asic_reg/nbio/nbio_7_4_0_smn.h | 53 
 6 files changed, 168 insertions(+), 12 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_smn.h
 create mode 100644 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_smn.h
 create mode 100644 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_0_smn.h

diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c 
b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
index accdedd..1965756 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
@@ -27,13 +27,9 @@
 #include "nbio/nbio_6_1_default.h"
 #include "nbio/nbio_6_1_offset.h"
 #include "nbio/nbio_6_1_sh_mask.h"
+#include "nbio/nbio_6_1_smn.h"
 #include "vega10_enum.h"

-#define smnCPM_CONTROL 
 0x11180460
-#define smnPCIE_CNTL2  
 0x11180070
-#define smnPCIE_CONFIG_CNTL
 0x11180044
-#define smnPCIE_CI_CNTL
 0x11180080
-
 static u32 nbio_v6_1_get_rev_id(struct amdgpu_device *adev)
 {
 u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c 
b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
index df34dc7..38291c5 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
@@ -27,13 +27,11 @@
 #include "nbio/nbio_7_0_default.h"
 #include "nbio/nbio_7_0_offset.h"
 #include "nbio/nbio_7_0_sh_mask.h"
+#include "nbio/nbio_7_0_smn.h"
 #include "vega10_enum.h"

 #define smnNBIF_MGCG_CTRL_LCLK  0x1013a05c

-#define smnCPM_CONTROL 
 0x11180460
-#define smnPCIE_CNTL2  
 0x11180070
-
 static u32 nbio_v7_0_get_rev_id(struct amdgpu_device *adev)
 {
 u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c 
b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
index 4cd31a2..0a61309 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
@@ -26,13 +26,10 @@

 #include "nbio/nbio_7_4_offset.h"
 #include "nbio/nbio_7_4_sh_mask.h"
+#include "nbio/nbio_7_4_0_smn.h"

 #define smnNBIF_MGCG_CTRL_LCLK  0x1013a21c

-#define smnCPM_CONTROL 
 0x11180460
-#define smnPCIE_CNTL2  
 0x11180070
-#define smnPCIE_CI_CNTL
 0x11180080
-
 static u32 nbio_v7_4_get_rev_id(struct amdgpu_device *adev)
 {
 u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_smn.h 
b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_smn.h
new file mode 100644
index 000..8c75669
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_smn.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (C) 2019  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to 

Re: [PATCH 1/2] drm/amdgpu: Add NBIO SMN headers v2

[Deucher, Alexander]

Series is:

Reviewed-by: Alex Deucher 


From: amd-gfx  on behalf of Russell, 
Kent 
Sent: Wednesday, January 9, 2019 9:43:51 AM
To: amd-gfx@lists.freedesktop.org
Cc: Russell, Kent
Subject: [PATCH 1/2] drm/amdgpu: Add NBIO SMN headers v2

We need these offsets for PCIE perf counters, so include them as well as
the the previously-used defines from the nbio_*.c files

v2: Return NBIF definitions back to previous files

Signed-off-by: Kent Russell 
---
 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c |  6 +--
 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c |  4 +-
 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c |  5 +-
 .../drm/amd/include/asic_reg/nbio/nbio_6_1_smn.h   | 58 ++
 .../drm/amd/include/asic_reg/nbio/nbio_7_0_smn.h   | 54 
 .../drm/amd/include/asic_reg/nbio/nbio_7_4_0_smn.h | 53 
 6 files changed, 168 insertions(+), 12 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_smn.h
 create mode 100644 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_smn.h
 create mode 100644 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_0_smn.h

diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c 
b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
index accdedd..1965756 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
@@ -27,13 +27,9 @@
 #include "nbio/nbio_6_1_default.h"
 #include "nbio/nbio_6_1_offset.h"
 #include "nbio/nbio_6_1_sh_mask.h"
+#include "nbio/nbio_6_1_smn.h"
 #include "vega10_enum.h"

-#define smnCPM_CONTROL 
 0x11180460
-#define smnPCIE_CNTL2  
 0x11180070
-#define smnPCIE_CONFIG_CNTL
 0x11180044
-#define smnPCIE_CI_CNTL
 0x11180080
-
 static u32 nbio_v6_1_get_rev_id(struct amdgpu_device *adev)
 {
 u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c 
b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
index df34dc7..38291c5 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
@@ -27,13 +27,11 @@
 #include "nbio/nbio_7_0_default.h"
 #include "nbio/nbio_7_0_offset.h"
 #include "nbio/nbio_7_0_sh_mask.h"
+#include "nbio/nbio_7_0_smn.h"
 #include "vega10_enum.h"

 #define smnNBIF_MGCG_CTRL_LCLK  0x1013a05c

-#define smnCPM_CONTROL 
 0x11180460
-#define smnPCIE_CNTL2  
 0x11180070
-
 static u32 nbio_v7_0_get_rev_id(struct amdgpu_device *adev)
 {
 u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c 
b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
index 4cd31a2..0a61309 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
@@ -26,13 +26,10 @@

 #include "nbio/nbio_7_4_offset.h"
 #include "nbio/nbio_7_4_sh_mask.h"
+#include "nbio/nbio_7_4_0_smn.h"

 #define smnNBIF_MGCG_CTRL_LCLK  0x1013a21c

-#define smnCPM_CONTROL 
 0x11180460
-#define smnPCIE_CNTL2  
 0x11180070
-#define smnPCIE_CI_CNTL
 0x11180080
-
 static u32 nbio_v7_4_get_rev_id(struct amdgpu_device *adev)
 {
 u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_smn.h 
b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_smn.h
new file mode 100644
index 000..8c75669
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_smn.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (C) 2019  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND 

[PATCH 2/2] drm/amdgpu: Add sysfs file for PCIe usage v4

[Russell, Kent]

Add a sysfs file that reports the number of bytes transmitted and
received in the last second. This can be used to approximate the PCIe
bandwidth usage over the last second.

v2: Clarify use of mps as estimation of bandwidth
v3: Don't make the file on APUs
v4: Early exit for APUs in the read function, change output to
display "packets-received packets-sent mps"
Signed-off-by: Kent Russell 

Signed-off-by: Kent Russell 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h|  4 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 36 
 drivers/gpu/drm/amd/amdgpu/cik.c   | 47 
 drivers/gpu/drm/amd/amdgpu/si.c| 47 
 drivers/gpu/drm/amd/amdgpu/soc15.c | 50 ++
 drivers/gpu/drm/amd/amdgpu/vi.c| 47 
 6 files changed, 231 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index e1b2c64..512b124 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -542,6 +542,9 @@ struct amdgpu_asic_funcs {
bool (*need_full_reset)(struct amdgpu_device *adev);
/* initialize doorbell layout for specific asic*/
void (*init_doorbell_index)(struct amdgpu_device *adev);
+   /* PCIe bandwidth usage */
+   void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0,
+  uint64_t *count1);
 };
 
 /*
@@ -1045,6 +1048,7 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
 #define amdgpu_asic_invalidate_hdp(adev, r) 
(adev)->asic_funcs->invalidate_hdp((adev), (r))
 #define amdgpu_asic_need_full_reset(adev) 
(adev)->asic_funcs->need_full_reset((adev))
 #define amdgpu_asic_init_doorbell_index(adev) 
(adev)->asic_funcs->init_doorbell_index((adev))
+#define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) 
((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1)))
 
 /* Common functions */
 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 6896dec..b38c06f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -990,6 +990,31 @@ static ssize_t amdgpu_get_busy_percent(struct device *dev,
return snprintf(buf, PAGE_SIZE, "%d\n", value);
 }
 
+/**
+ * DOC: pcie_bw
+ *
+ * The amdgpu driver provides a sysfs API for estimating how much data
+ * has been received and sent by the GPU in the last second through PCIe.
+ * The file pcie_bw is used for this.
+ * The Perf counters count the number of received and sent messages and return
+ * those values, as well as the maximum payload size of a PCIe packet (mps).
+ * Note that it is not possible to easily and quickly obtain the size of each
+ * packet transmitted, so we output the max payload size (mps) to allow for
+ * quick estimation of the PCIe bandwidth usage
+ */
+static ssize_t amdgpu_get_pcie_bw(struct device *dev,
+   struct device_attribute *attr,
+   char *buf)
+{
+   struct drm_device *ddev = dev_get_drvdata(dev);
+   struct amdgpu_device *adev = ddev->dev_private;
+   uint64_t count0, count1;
+
+   amdgpu_asic_get_pcie_usage(adev, , );
+   return snprintf(buf, PAGE_SIZE, "%llu %llu %i\n",
+   count0, count1, pcie_get_mps(adev->pdev));
+}
+
 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, amdgpu_get_dpm_state, 
amdgpu_set_dpm_state);
 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
   amdgpu_get_dpm_forced_performance_level,
@@ -1025,6 +1050,7 @@ static DEVICE_ATTR(pp_od_clk_voltage, S_IRUGO | S_IWUSR,
amdgpu_set_pp_od_clk_voltage);
 static DEVICE_ATTR(gpu_busy_percent, S_IRUGO,
amdgpu_get_busy_percent, NULL);
+static DEVICE_ATTR(pcie_bw, S_IRUGO, amdgpu_get_pcie_bw, NULL);
 
 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
  struct device_attribute *attr,
@@ -2108,6 +2134,14 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
"gpu_busy_level\n");
return ret;
}
+   /* PCIe Perf counters won't work on APU nodes */
+   if (adev->flags & !AMD_IS_APU) {
+   ret = device_create_file(adev->dev, _attr_pcie_bw);
+   if (ret) {
+   DRM_ERROR("failed to create device file pcie_bw\n");
+   return ret;
+   }
+   }
ret = amdgpu_debugfs_pm_init(adev);
if (ret) {
DRM_ERROR("Failed to register debugfs file for dpm!\n");
@@ -2147,6 +2181,8 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
device_remove_file(adev->dev,
_attr_pp_od_clk_voltage);
device_remove_file(adev->dev, _attr_gpu_busy_percent);
+   

[PATCH 1/2] drm/amdgpu: Add NBIO SMN headers v2

[Russell, Kent]

We need these offsets for PCIE perf counters, so include them as well as
the the previously-used defines from the nbio_*.c files

v2: Return NBIF definitions back to previous files

Signed-off-by: Kent Russell 
---
 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c |  6 +--
 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c |  4 +-
 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c |  5 +-
 .../drm/amd/include/asic_reg/nbio/nbio_6_1_smn.h   | 58 ++
 .../drm/amd/include/asic_reg/nbio/nbio_7_0_smn.h   | 54 
 .../drm/amd/include/asic_reg/nbio/nbio_7_4_0_smn.h | 53 
 6 files changed, 168 insertions(+), 12 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_smn.h
 create mode 100644 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_smn.h
 create mode 100644 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_0_smn.h

diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c 
b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
index accdedd..1965756 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
@@ -27,13 +27,9 @@
 #include "nbio/nbio_6_1_default.h"
 #include "nbio/nbio_6_1_offset.h"
 #include "nbio/nbio_6_1_sh_mask.h"
+#include "nbio/nbio_6_1_smn.h"
 #include "vega10_enum.h"
 
-#define smnCPM_CONTROL 
 0x11180460
-#define smnPCIE_CNTL2  
 0x11180070
-#define smnPCIE_CONFIG_CNTL
 0x11180044
-#define smnPCIE_CI_CNTL
 0x11180080
-
 static u32 nbio_v6_1_get_rev_id(struct amdgpu_device *adev)
 {
 u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c 
b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
index df34dc7..38291c5 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
@@ -27,13 +27,11 @@
 #include "nbio/nbio_7_0_default.h"
 #include "nbio/nbio_7_0_offset.h"
 #include "nbio/nbio_7_0_sh_mask.h"
+#include "nbio/nbio_7_0_smn.h"
 #include "vega10_enum.h"
 
 #define smnNBIF_MGCG_CTRL_LCLK 0x1013a05c
 
-#define smnCPM_CONTROL 
 0x11180460
-#define smnPCIE_CNTL2  
 0x11180070
-
 static u32 nbio_v7_0_get_rev_id(struct amdgpu_device *adev)
 {
 u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c 
b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
index 4cd31a2..0a61309 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
@@ -26,13 +26,10 @@
 
 #include "nbio/nbio_7_4_offset.h"
 #include "nbio/nbio_7_4_sh_mask.h"
+#include "nbio/nbio_7_4_0_smn.h"
 
 #define smnNBIF_MGCG_CTRL_LCLK 0x1013a21c
 
-#define smnCPM_CONTROL 
 0x11180460
-#define smnPCIE_CNTL2  
 0x11180070
-#define smnPCIE_CI_CNTL
 0x11180080
-
 static u32 nbio_v7_4_get_rev_id(struct amdgpu_device *adev)
 {
 u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_smn.h 
b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_smn.h
new file mode 100644
index 000..8c75669
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_smn.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (C) 2019  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 
LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 

Re: [PATCH xf86-video-ati 1/2] Only call drmmode_uevent_init if RandR is enabled

[Deucher, Alexander]

Series is:

Reviewed-by: Alex Deucher 


From: amd-gfx  on behalf of Michel 
Dänzer 
Sent: Wednesday, January 9, 2019 5:43:22 AM
To: amd-gfx@lists.freedesktop.org
Subject: [PATCH xf86-video-ati 1/2] Only call drmmode_uevent_init if RandR is 
enabled

From: Michel Dänzer 

There's no point in listening for hotplug events if RandR is disabled,
as there's no other mechanism for them to be propagated. We were already
mostly ignoring them in that case.

Inspired by
https://gitlab.freedesktop.org/xorg/driver/xf86-video-intel/commit/1a489142c8e6a4828348cc9afbd0f430d3b1e2d8
(via https://bugs.freedesktop.org/109230#c11).

Signed-off-by: Michel Dänzer 
---
 src/drmmode_display.c | 2 +-
 src/radeon_kms.c  | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index d433e0611..e04a17d5e 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -3273,7 +3273,7 @@ restart_destroy:
 /* Check to see if a lessee has disappeared */
 drmmode_validate_leases(scrn);

-   if (changed && dixPrivateKeyRegistered(rrPrivKey)) {
+   if (changed) {
 #if XORG_VERSION_CURRENT >= XORG_VERSION_NUMERIC(1,14,99,2,0)
 RRSetChanged(xf86ScrnToScreen(scrn));
 #else
diff --git a/src/radeon_kms.c b/src/radeon_kms.c
index bb6885fb9..67f42e0fe 100644
--- a/src/radeon_kms.c
+++ b/src/radeon_kms.c
@@ -349,13 +349,13 @@ static Bool RADEONCreateScreenResources_KMS(ScreenPtr 
pScreen)
 RROutputChanged(rrScrPriv->primaryOutput, FALSE);
 rrScrPriv->layoutChanged = TRUE;
 }
+
+   drmmode_uevent_init(pScrn, >drmmode);
 }

 if (!drmmode_set_desired_modes(pScrn, >drmmode, pScreen->isGPU))
 return FALSE;

-drmmode_uevent_init(pScrn, >drmmode);
-
 if (info->r600_shadow_fb) {
 pixmap = pScreen->GetScreenPixmap(pScreen);

--
2.20.1

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[PATCH 1/3] drm/amdgpu: enable IH ring 1 and ring 2 v3

[Christian König]

The entries are ignored for now, but it at least stops crashing the
hardware when somebody tries to push something to the other IH rings.

v2: limit ring size, add TODO comment
v3: only program rings if they are actually allocated

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h |   4 +-
 drivers/gpu/drm/amd/amdgpu/vega10_ih.c  | 143 
 2 files changed, 121 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
index f6ce171cb8aa..7e06fa64321a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
@@ -87,8 +87,8 @@ struct amdgpu_irq {
/* status, etc. */
boolmsi_enabled; /* msi enabled */
 
-   /* interrupt ring */
-   struct amdgpu_ih_ring   ih;
+   /* interrupt rings */
+   struct amdgpu_ih_ring   ih, ih1, ih2;
const struct amdgpu_ih_funcs*ih_funcs;
 
/* gen irq stuff */
diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c 
b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
index 562701939d3e..eea5530d2961 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
@@ -50,6 +50,22 @@ static void vega10_ih_enable_interrupts(struct amdgpu_device 
*adev)
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1);
WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
adev->irq.ih.enabled = true;
+
+   if (adev->irq.ih1.ring_size) {
+   ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);
+   ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
+  RB_ENABLE, 1);
+   WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
+   adev->irq.ih1.enabled = true;
+   }
+
+   if (adev->irq.ih2.ring_size) {
+   ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
+   ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,
+  RB_ENABLE, 1);
+   WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
+   adev->irq.ih2.enabled = true;
+   }
 }
 
 /**
@@ -71,6 +87,53 @@ static void vega10_ih_disable_interrupts(struct 
amdgpu_device *adev)
WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0);
adev->irq.ih.enabled = false;
adev->irq.ih.rptr = 0;
+
+   if (adev->irq.ih1.ring_size) {
+   ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);
+   ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
+  RB_ENABLE, 0);
+   WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
+   /* set rptr, wptr to 0 */
+   WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0);
+   WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0);
+   adev->irq.ih1.enabled = false;
+   adev->irq.ih1.rptr = 0;
+   }
+
+   if (adev->irq.ih2.ring_size) {
+   ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
+   ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,
+  RB_ENABLE, 0);
+   WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
+   /* set rptr, wptr to 0 */
+   WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0);
+   WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0);
+   adev->irq.ih2.enabled = false;
+   adev->irq.ih2.rptr = 0;
+   }
+}
+
+static uint32_t vega10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t 
ih_rb_cntl)
+{
+   int rb_bufsz = order_base_2(ih->ring_size / 4);
+
+   ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
+  MC_SPACE, ih->use_bus_addr ? 1 : 4);
+   ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
+  WPTR_OVERFLOW_CLEAR, 1);
+   ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
+  WPTR_OVERFLOW_ENABLE, 1);
+   ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
+   /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register
+* value is written to memory
+*/
+   ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
+  WPTR_WRITEBACK_ENABLE, 1);
+   ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1);
+   ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0);
+   ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);
+
+   return ih_rb_cntl;
 }
 
 /**
@@ -86,9 +149,8 @@ static void vega10_ih_disable_interrupts(struct 
amdgpu_device *adev)
  */
 static int vega10_ih_irq_init(struct amdgpu_device *adev)
 {
-   struct amdgpu_ih_ring *ih = >irq.ih;
+   struct 

[PATCH 2/3] drm/amdgpu: add support for processing IH ring 1 & 2

[Christian König]

Previously we only added the ring buffer memory, now add the handling as
well.

Signed-off-by: Christian König 
Acked-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 33 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h |  4 ++-
 2 files changed, 36 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
index b8e543e23166..8bfb3dab46f7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
@@ -176,6 +176,36 @@ irqreturn_t amdgpu_irq_handler(int irq, void *arg)
return ret;
 }
 
+/**
+ * amdgpu_irq_handle_ih1 - kick of processing for IH1
+ *
+ * @work: work structure in struct amdgpu_irq
+ *
+ * Kick of processing IH ring 1.
+ */
+static void amdgpu_irq_handle_ih1(struct work_struct *work)
+{
+   struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
+ irq.ih1_work);
+
+   amdgpu_ih_process(adev, >irq.ih1, amdgpu_irq_callback);
+}
+
+/**
+ * amdgpu_irq_handle_ih2 - kick of processing for IH2
+ *
+ * @work: work structure in struct amdgpu_irq
+ *
+ * Kick of processing IH ring 2.
+ */
+static void amdgpu_irq_handle_ih2(struct work_struct *work)
+{
+   struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
+ irq.ih2_work);
+
+   amdgpu_ih_process(adev, >irq.ih2, amdgpu_irq_callback);
+}
+
 /**
  * amdgpu_msi_ok - check whether MSI functionality is enabled
  *
@@ -240,6 +270,9 @@ int amdgpu_irq_init(struct amdgpu_device *adev)
amdgpu_hotplug_work_func);
}
 
+   INIT_WORK(>irq.ih1_work, amdgpu_irq_handle_ih1);
+   INIT_WORK(>irq.ih2_work, amdgpu_irq_handle_ih2);
+
adev->irq.installed = true;
r = drm_irq_install(adev->ddev, adev->ddev->pdev->irq);
if (r) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
index 7e06fa64321a..c27decfda494 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
@@ -89,7 +89,9 @@ struct amdgpu_irq {
 
/* interrupt rings */
struct amdgpu_ih_ring   ih, ih1, ih2;
-   const struct amdgpu_ih_funcs*ih_funcs;
+   const struct amdgpu_ih_funcs*ih_funcs;
+   struct work_struct  ih1_work, ih2_work;
+   struct amdgpu_irq_src   self_irq;
 
/* gen irq stuff */
struct irq_domain   *domain; /* GPU irq controller domain */
-- 
2.17.1

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[PATCH 3/3] drm/amdgpu: add support for self irq on Vega10 v2

[Christian König]

This finally enables processing of ring 1 & 2.

v2: fix copy error

Signed-off-by: Christian König 
Reviewed-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 80 --
 1 file changed, 74 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c 
b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
index eea5530d2961..030617624b8a 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
@@ -272,7 +272,7 @@ static void vega10_ih_irq_disable(struct amdgpu_device 
*adev)
 static u32 vega10_ih_get_wptr(struct amdgpu_device *adev,
  struct amdgpu_ih_ring *ih)
 {
-   u32 wptr, tmp;
+   u32 wptr, reg, tmp;
 
wptr = le32_to_cpu(*ih->wptr_cpu);
 
@@ -280,7 +280,17 @@ static u32 vega10_ih_get_wptr(struct amdgpu_device *adev,
goto out;
 
/* Double check that the overflow wasn't already cleared. */
-   wptr = RREG32_NO_KIQ(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR));
+
+   if (ih == >irq.ih)
+   reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR);
+   else if (ih == >irq.ih1)
+   reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1);
+   else if (ih == >irq.ih2)
+   reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2);
+   else
+   BUG();
+
+   wptr = RREG32_NO_KIQ(reg);
if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
goto out;
 
@@ -296,9 +306,18 @@ static u32 vega10_ih_get_wptr(struct amdgpu_device *adev,
 wptr, ih->rptr, tmp);
ih->rptr = tmp;
 
-   tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL));
+   if (ih == >irq.ih)
+   reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL);
+   else if (ih == >irq.ih1)
+   reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1);
+   else if (ih == >irq.ih2)
+   reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2);
+   else
+   BUG();
+
+   tmp = RREG32_NO_KIQ(reg);
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
-   WREG32_NO_KIQ(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL), tmp);
+   WREG32_NO_KIQ(reg, tmp);
 
 out:
return (wptr & ih->ptr_mask);
@@ -361,9 +380,52 @@ static void vega10_ih_set_rptr(struct amdgpu_device *adev,
/* XXX check if swapping is necessary on BE */
*ih->rptr_cpu = ih->rptr;
WDOORBELL32(ih->doorbell_index, ih->rptr);
-   } else {
+   } else if (ih == >irq.ih) {
WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, ih->rptr);
+   } else if (ih == >irq.ih1) {
+   WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, ih->rptr);
+   } else if (ih == >irq.ih2) {
+   WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, ih->rptr);
+   }
+}
+
+/**
+ * vega10_ih_self_irq - dispatch work for ring 1 and 2
+ *
+ * @adev: amdgpu_device pointer
+ * @source: irq source
+ * @entry: IV with WPTR update
+ *
+ * Update the WPTR from the IV and schedule work to handle the entries.
+ */
+static int vega10_ih_self_irq(struct amdgpu_device *adev,
+ struct amdgpu_irq_src *source,
+ struct amdgpu_iv_entry *entry)
+{
+   uint32_t wptr = cpu_to_le32(entry->src_data[0]);
+
+   switch (entry->ring_id) {
+   case 1:
+   *adev->irq.ih1.wptr_cpu = wptr;
+   schedule_work(>irq.ih1_work);
+   break;
+   case 2:
+   *adev->irq.ih2.wptr_cpu = wptr;
+   schedule_work(>irq.ih2_work);
+   break;
+   default: break;
}
+   return 0;
+}
+
+static const struct amdgpu_irq_src_funcs vega10_ih_self_irq_funcs = {
+   .process = vega10_ih_self_irq,
+};
+
+static void vega10_ih_set_self_irq_funcs(struct amdgpu_device *adev)
+{
+   adev->irq.self_irq.num_types = 0;
+   adev->irq.self_irq.funcs = _ih_self_irq_funcs;
 }
 
 static int vega10_ih_early_init(void *handle)
@@ -371,13 +433,19 @@ static int vega10_ih_early_init(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
vega10_ih_set_interrupt_funcs(adev);
+   vega10_ih_set_self_irq_funcs(adev);
return 0;
 }
 
 static int vega10_ih_sw_init(void *handle)
 {
-   int r;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+   int r;
+
+   r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0,
+ >irq.self_irq);
+   if (r)
+   return r;
 
r = amdgpu_ih_ring_init(adev, >irq.ih, 256 * 1024, true);
if (r)
-- 
2.17.1

___
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Re: [PATCH libdrm] amdgpu: add a faster BO list API

[Christian König]

Am 09.01.19 um 13:36 schrieb Marek Olšák:



On Wed, Jan 9, 2019, 5:28 AM Christian König 
 wrote:


Looks good, but I'm wondering what's the actual improvement?


No malloc calls and 1 less for loop copying the bo list.


Yeah, but didn't we want to get completely rid of the bo list?

Christian.



Marek


Christian.

Am 07.01.19 um 20:31 schrieb Marek Olšák:
> From: Marek Olšák mailto:marek.ol...@amd.com>>
>
> ---
>   amdgpu/amdgpu-symbol-check |  3 ++
>   amdgpu/amdgpu.h            | 56
+-
>   amdgpu/amdgpu_bo.c         | 36 
>   amdgpu/amdgpu_cs.c         | 25 +
>   4 files changed, 119 insertions(+), 1 deletion(-)
>
> diff --git a/amdgpu/amdgpu-symbol-check b/amdgpu/amdgpu-symbol-check
> index 6f5e0f95..96a44b40 100755
> --- a/amdgpu/amdgpu-symbol-check
> +++ b/amdgpu/amdgpu-symbol-check
> @@ -12,20 +12,22 @@ _edata
>   _end
>   _fini
>   _init
>   amdgpu_bo_alloc
>   amdgpu_bo_cpu_map
>   amdgpu_bo_cpu_unmap
>   amdgpu_bo_export
>   amdgpu_bo_free
>   amdgpu_bo_import
>   amdgpu_bo_inc_ref
> +amdgpu_bo_list_create_raw
> +amdgpu_bo_list_destroy_raw
>   amdgpu_bo_list_create
>   amdgpu_bo_list_destroy
>   amdgpu_bo_list_update
>   amdgpu_bo_query_info
>   amdgpu_bo_set_metadata
>   amdgpu_bo_va_op
>   amdgpu_bo_va_op_raw
>   amdgpu_bo_wait_for_idle
>   amdgpu_create_bo_from_user_mem
>   amdgpu_cs_chunk_fence_info_to_data
> @@ -40,20 +42,21 @@ amdgpu_cs_destroy_semaphore
>   amdgpu_cs_destroy_syncobj
>   amdgpu_cs_export_syncobj
>   amdgpu_cs_fence_to_handle
>   amdgpu_cs_import_syncobj
>   amdgpu_cs_query_fence_status
>   amdgpu_cs_query_reset_state
>   amdgpu_query_sw_info
>   amdgpu_cs_signal_semaphore
>   amdgpu_cs_submit
>   amdgpu_cs_submit_raw
> +amdgpu_cs_submit_raw2
>   amdgpu_cs_syncobj_export_sync_file
>   amdgpu_cs_syncobj_import_sync_file
>   amdgpu_cs_syncobj_reset
>   amdgpu_cs_syncobj_signal
>   amdgpu_cs_syncobj_wait
>   amdgpu_cs_wait_fences
>   amdgpu_cs_wait_semaphore
>   amdgpu_device_deinitialize
>   amdgpu_device_initialize
>   amdgpu_find_bo_by_cpu_mapping
> diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h
> index dc51659a..5b800033 100644
> --- a/amdgpu/amdgpu.h
> +++ b/amdgpu/amdgpu.h
> @@ -35,20 +35,21 @@
>   #define _AMDGPU_H_
>
>   #include 
>   #include 
>
>   #ifdef __cplusplus
>   extern "C" {
>   #endif
>
>   struct drm_amdgpu_info_hw_ip;
> +struct drm_amdgpu_bo_list_entry;
>
>
 
/*--*/
>   /* --- Defines
 */
>
 
/*--*/
>
>   /**
>    * Define max. number of Command Buffers (IB) which could be
sent to the single
>    * hardware IP to accommodate CE/DE requirements
>    *
>    * \sa amdgpu_cs_ib_info
> @@ -767,34 +768,65 @@ int amdgpu_bo_cpu_unmap(amdgpu_bo_handle
buf_handle);
>    *                            and no GPU access is scheduled.
>    *                          1 GPU access is in fly or scheduled
>    *
>    * \return   0 - on success
>    *          <0 - Negative POSIX Error code
>    */
>   int amdgpu_bo_wait_for_idle(amdgpu_bo_handle buf_handle,
>                           uint64_t timeout_ns,
>                           bool *buffer_busy);
>
> +/**
> + * Creates a BO list handle for command submission.
> + *
> + * \param   dev                      - \c [in] Device handle.
> + *                              See #amdgpu_device_initialize()
> + * \param   number_of_buffers        - \c [in] Number of BOs in
the list
> + * \param   buffers          - \c [in] List of BO handles
> + * \param   result           - \c [out] Created BO list handle
> + *
> + * \return   0 on success\n
> + *          <0 - Negative POSIX Error code
> + *
> + * \sa amdgpu_bo_list_destroy_raw()
> +*/
> +int amdgpu_bo_list_create_raw(amdgpu_device_handle dev,
> +                           uint32_t number_of_buffers,
> +                           struct drm_amdgpu_bo_list_entry
*buffers,
> +                           uint32_t *result);
> +
> +/**
> + * Destroys a BO list handle.
> + *
> + * \param   bo_list  - \c [in] BO list handle.
> + *
> + * \return   0 on success\n
> + *          <0 - Negative POSIX Error code
> + *
> + * \sa amdgpu_bo_list_create_raw(), amdgpu_cs_submit_raw2()
> +*/
> +int amdgpu_bo_list_destroy_raw(amdgpu_device_handle 

RE: [PATCH] drm/amdgpu: Add sysfs file for PCIe usage v3

[Russell, Kent]

> -Original Message-
> From: Alex Deucher 
> Sent: Tuesday, January 08, 2019 11:26 AM
> To: Kuehling, Felix 
> Cc: Russell, Kent ; amd-gfx@lists.freedesktop.org;
> Deucher, Alexander 
> Subject: Re: [PATCH] drm/amdgpu: Add sysfs file for PCIe usage v3
> 
> On Tue, Jan 8, 2019 at 11:02 AM Kuehling, Felix 
> wrote:
> >
> >
> > On 2019-01-08 6:28 a.m., Russell, Kent wrote:
> > > Add a sysfs file that reports the number of bytes transmitted and
> > > received in the last second. This can be used to approximate the
> > > PCIe bandwidth usage over the last second.
> > >
> > > v2: Clarify use of mps as estimation of bandwidth
> >
> > I think you only updated the code comment, but not the output in sysfs.
> >
> > More generally, most amdgpu sysfs files report a single value, or a
> > set of values separated by spaces. That makes it easier to parse by
> > external tools. It's also supposed to be a stable API. They don't
> > usually include human readable text such as "bytes received:". It
> > would be up to a tool such as rocm-smi to turn this into human-readable
> text.
> >
> > In keeping with that convention I'd suggest reporting the PCIe
> > bandwidth as three numbers:
> >
> >   
> >
> > Then let the tool calculate the bytes estimate with the appropriate
> > warnings about how accurate that is.
> >
> > Alex does this match your understanding regarding sysfs conventions?
> 
> Yes, agreed.
> 
> Alex
That works for me. I always let the sclk/mclk sysfs file with their multi-line 
outputs get into my head. I'll make the appropriate change, which will also 
make it easier for the SMI to communicate how the values are established.

 Kent

> 
> >
> > Regards,
> >   Felix
> >
> > > v3: Don't make the file on APUs
> > >
> > > Signed-off-by: Kent Russell 
> > > ---
> > >  drivers/gpu/drm/amd/amdgpu/amdgpu.h|  4 
> > >  drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 38
> +
> > >  drivers/gpu/drm/amd/amdgpu/cik.c   | 41
> +++
> > >  drivers/gpu/drm/amd/amdgpu/si.c| 41
> +++
> > >  drivers/gpu/drm/amd/amdgpu/soc15.c | 44
> ++
> > >  drivers/gpu/drm/amd/amdgpu/vi.c| 41
> +++
> > >  6 files changed, 209 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > > b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > > index e1b2c64..512b124 100644
> > > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > > @@ -542,6 +542,9 @@ struct amdgpu_asic_funcs {
> > >   bool (*need_full_reset)(struct amdgpu_device *adev);
> > >   /* initialize doorbell layout for specific asic*/
> > >   void (*init_doorbell_index)(struct amdgpu_device *adev);
> > > + /* PCIe bandwidth usage */
> > > + void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t
> *count0,
> > > +uint64_t *count1);
> > >  };
> > >
> > >  /*
> > > @@ -1045,6 +1048,7 @@ int emu_soc_asic_init(struct amdgpu_device
> > > *adev);  #define amdgpu_asic_invalidate_hdp(adev, r)
> > > (adev)->asic_funcs->invalidate_hdp((adev), (r))  #define
> > > amdgpu_asic_need_full_reset(adev)
> > > (adev)->asic_funcs->need_full_reset((adev))
> > >  #define amdgpu_asic_init_doorbell_index(adev)
> > > (adev)->asic_funcs->init_doorbell_index((adev))
> > > +#define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1)
> > > +((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1)))
> > >
> > >  /* Common functions */
> > >  bool amdgpu_device_should_recover_gpu(struct amdgpu_device
> *adev);
> > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> > > b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> > > index 6896dec..d2b29fd 100644
> > > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> > > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> > > @@ -990,6 +990,33 @@ static ssize_t amdgpu_get_busy_percent(struct
> device *dev,
> > >   return snprintf(buf, PAGE_SIZE, "%d\n", value);  }
> > >
> > > +/**
> > > + * DOC: pcie_bw
> > > + *
> > > + * The amdgpu driver provides a sysfs API for reading how much data
> > > + * has been sent and received by the GPU in the last second through
> PCIe.
> > > + * The file pcie_bw is used for this.
> > > + * The Perf counters calculate this and return the number of sent
> > > +and received
> > > + * messages, which we multiply by the maxsize of our PCIe packets
> (mps).
> > > + * Note that it is not possible to easily and quickly obtain the
> > > +size of each
> > > + * packet transmitted, so we use the max payload size (mps) to
> > > +estimate the
> > > + * PCIe bandwidth usage
> > > + */
> > > +static ssize_t amdgpu_get_pcie_bw(struct device *dev,
> > > + struct device_attribute *attr,
> > > + char *buf)
> > > +{
> > > + struct drm_device *ddev = dev_get_drvdata(dev);
> > > + struct amdgpu_device *adev = ddev->dev_private;
> > > + uint64_t mps = 

Re: [PATCH libdrm] amdgpu: add a faster BO list API

[Marek Olšák]

On Wed, Jan 9, 2019, 5:28 AM Christian König <
ckoenig.leichtzumer...@gmail.com wrote:

> Looks good, but I'm wondering what's the actual improvement?
>

No malloc calls and 1 less for loop copying the bo list.

Marek


> Christian.
>
> Am 07.01.19 um 20:31 schrieb Marek Olšák:
> > From: Marek Olšák 
> >
> > ---
> >   amdgpu/amdgpu-symbol-check |  3 ++
> >   amdgpu/amdgpu.h| 56 +-
> >   amdgpu/amdgpu_bo.c | 36 
> >   amdgpu/amdgpu_cs.c | 25 +
> >   4 files changed, 119 insertions(+), 1 deletion(-)
> >
> > diff --git a/amdgpu/amdgpu-symbol-check b/amdgpu/amdgpu-symbol-check
> > index 6f5e0f95..96a44b40 100755
> > --- a/amdgpu/amdgpu-symbol-check
> > +++ b/amdgpu/amdgpu-symbol-check
> > @@ -12,20 +12,22 @@ _edata
> >   _end
> >   _fini
> >   _init
> >   amdgpu_bo_alloc
> >   amdgpu_bo_cpu_map
> >   amdgpu_bo_cpu_unmap
> >   amdgpu_bo_export
> >   amdgpu_bo_free
> >   amdgpu_bo_import
> >   amdgpu_bo_inc_ref
> > +amdgpu_bo_list_create_raw
> > +amdgpu_bo_list_destroy_raw
> >   amdgpu_bo_list_create
> >   amdgpu_bo_list_destroy
> >   amdgpu_bo_list_update
> >   amdgpu_bo_query_info
> >   amdgpu_bo_set_metadata
> >   amdgpu_bo_va_op
> >   amdgpu_bo_va_op_raw
> >   amdgpu_bo_wait_for_idle
> >   amdgpu_create_bo_from_user_mem
> >   amdgpu_cs_chunk_fence_info_to_data
> > @@ -40,20 +42,21 @@ amdgpu_cs_destroy_semaphore
> >   amdgpu_cs_destroy_syncobj
> >   amdgpu_cs_export_syncobj
> >   amdgpu_cs_fence_to_handle
> >   amdgpu_cs_import_syncobj
> >   amdgpu_cs_query_fence_status
> >   amdgpu_cs_query_reset_state
> >   amdgpu_query_sw_info
> >   amdgpu_cs_signal_semaphore
> >   amdgpu_cs_submit
> >   amdgpu_cs_submit_raw
> > +amdgpu_cs_submit_raw2
> >   amdgpu_cs_syncobj_export_sync_file
> >   amdgpu_cs_syncobj_import_sync_file
> >   amdgpu_cs_syncobj_reset
> >   amdgpu_cs_syncobj_signal
> >   amdgpu_cs_syncobj_wait
> >   amdgpu_cs_wait_fences
> >   amdgpu_cs_wait_semaphore
> >   amdgpu_device_deinitialize
> >   amdgpu_device_initialize
> >   amdgpu_find_bo_by_cpu_mapping
> > diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h
> > index dc51659a..5b800033 100644
> > --- a/amdgpu/amdgpu.h
> > +++ b/amdgpu/amdgpu.h
> > @@ -35,20 +35,21 @@
> >   #define _AMDGPU_H_
> >
> >   #include 
> >   #include 
> >
> >   #ifdef __cplusplus
> >   extern "C" {
> >   #endif
> >
> >   struct drm_amdgpu_info_hw_ip;
> > +struct drm_amdgpu_bo_list_entry;
> >
> >
>  
> /*--*/
> >   /* --- Defines
>  */
> >
>  
> /*--*/
> >
> >   /**
> >* Define max. number of Command Buffers (IB) which could be sent to
> the single
> >* hardware IP to accommodate CE/DE requirements
> >*
> >* \sa amdgpu_cs_ib_info
> > @@ -767,34 +768,65 @@ int amdgpu_bo_cpu_unmap(amdgpu_bo_handle
> buf_handle);
> >*and no GPU access is scheduled.
> >*  1 GPU access is in fly or scheduled
> >*
> >* \return   0 - on success
> >*  <0 - Negative POSIX Error code
> >*/
> >   int amdgpu_bo_wait_for_idle(amdgpu_bo_handle buf_handle,
> >   uint64_t timeout_ns,
> >   bool *buffer_busy);
> >
> > +/**
> > + * Creates a BO list handle for command submission.
> > + *
> > + * \param   dev  - \c [in] Device handle.
> > + *  See #amdgpu_device_initialize()
> > + * \param   number_of_buffers- \c [in] Number of BOs in the list
> > + * \param   buffers  - \c [in] List of BO handles
> > + * \param   result   - \c [out] Created BO list handle
> > + *
> > + * \return   0 on success\n
> > + *  <0 - Negative POSIX Error code
> > + *
> > + * \sa amdgpu_bo_list_destroy_raw()
> > +*/
> > +int amdgpu_bo_list_create_raw(amdgpu_device_handle dev,
> > +   uint32_t number_of_buffers,
> > +   struct drm_amdgpu_bo_list_entry *buffers,
> > +   uint32_t *result);
> > +
> > +/**
> > + * Destroys a BO list handle.
> > + *
> > + * \param   bo_list  - \c [in] BO list handle.
> > + *
> > + * \return   0 on success\n
> > + *  <0 - Negative POSIX Error code
> > + *
> > + * \sa amdgpu_bo_list_create_raw(), amdgpu_cs_submit_raw2()
> > +*/
> > +int amdgpu_bo_list_destroy_raw(amdgpu_device_handle dev, uint32_t
> bo_list);
> > +
> >   /**
> >* Creates a BO list handle for command submission.
> >*
> >* \param   dev - \c [in] Device handle.
> >* See #amdgpu_device_initialize()
> >* \param   number_of_resources - \c [in] Number of BOs in the list
> >* \param   resources   - \c [in] List of BO handles
> >* \param   resource_prios  - \c 

[PATCH xf86-video-ati 1/2] Only call drmmode_uevent_init if RandR is enabled

[Michel Dänzer]

From: Michel Dänzer 

There's no point in listening for hotplug events if RandR is disabled,
as there's no other mechanism for them to be propagated. We were already
mostly ignoring them in that case.

Inspired by
https://gitlab.freedesktop.org/xorg/driver/xf86-video-intel/commit/1a489142c8e6a4828348cc9afbd0f430d3b1e2d8
(via https://bugs.freedesktop.org/109230#c11).

Signed-off-by: Michel Dänzer 
---
 src/drmmode_display.c | 2 +-
 src/radeon_kms.c  | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index d433e0611..e04a17d5e 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -3273,7 +3273,7 @@ restart_destroy:
/* Check to see if a lessee has disappeared */
drmmode_validate_leases(scrn);
 
-   if (changed && dixPrivateKeyRegistered(rrPrivKey)) {
+   if (changed) {
 #if XORG_VERSION_CURRENT >= XORG_VERSION_NUMERIC(1,14,99,2,0)
RRSetChanged(xf86ScrnToScreen(scrn));
 #else
diff --git a/src/radeon_kms.c b/src/radeon_kms.c
index bb6885fb9..67f42e0fe 100644
--- a/src/radeon_kms.c
+++ b/src/radeon_kms.c
@@ -349,13 +349,13 @@ static Bool RADEONCreateScreenResources_KMS(ScreenPtr 
pScreen)
RROutputChanged(rrScrPriv->primaryOutput, FALSE);
rrScrPriv->layoutChanged = TRUE;
}
+
+   drmmode_uevent_init(pScrn, >drmmode);
 }
 
 if (!drmmode_set_desired_modes(pScrn, >drmmode, pScreen->isGPU))
return FALSE;
 
-drmmode_uevent_init(pScrn, >drmmode);
-
 if (info->r600_shadow_fb) {
pixmap = pScreen->GetScreenPixmap(pScreen);
 
-- 
2.20.1

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[PATCH xf86-video-ati 2/2] Only call drmmode_validate_leases if RandR is enabled

[Michel Dänzer]

From: Michel Dänzer 

It would crash if RandR is disabled, e.g. because Xinerama is enabled.

Bugzilla: https://bugs.freedesktop.org/109230
Signed-off-by: Michel Dänzer 
---
 src/drmmode_display.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index e04a17d5e..71f3539f6 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -3100,7 +3100,8 @@ Bool drmmode_set_desired_modes(ScrnInfoPtr pScrn, 
drmmode_ptr drmmode,
}
 
/* Validate leases on VT re-entry */
-   drmmode_validate_leases(pScrn);
+   if (dixPrivateKeyRegistered(rrPrivKey))
+   drmmode_validate_leases(pScrn);
 
return TRUE;
 }
-- 
2.20.1

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Re: [PATCH libdrm] amdgpu: add a faster BO list API

[Christian König]

Looks good, but I'm wondering what's the actual improvement?

Christian.

Am 07.01.19 um 20:31 schrieb Marek Olšák:

From: Marek Olšák 

---
  amdgpu/amdgpu-symbol-check |  3 ++
  amdgpu/amdgpu.h| 56 +-
  amdgpu/amdgpu_bo.c | 36 
  amdgpu/amdgpu_cs.c | 25 +
  4 files changed, 119 insertions(+), 1 deletion(-)

diff --git a/amdgpu/amdgpu-symbol-check b/amdgpu/amdgpu-symbol-check
index 6f5e0f95..96a44b40 100755
--- a/amdgpu/amdgpu-symbol-check
+++ b/amdgpu/amdgpu-symbol-check
@@ -12,20 +12,22 @@ _edata
  _end
  _fini
  _init
  amdgpu_bo_alloc
  amdgpu_bo_cpu_map
  amdgpu_bo_cpu_unmap
  amdgpu_bo_export
  amdgpu_bo_free
  amdgpu_bo_import
  amdgpu_bo_inc_ref
+amdgpu_bo_list_create_raw
+amdgpu_bo_list_destroy_raw
  amdgpu_bo_list_create
  amdgpu_bo_list_destroy
  amdgpu_bo_list_update
  amdgpu_bo_query_info
  amdgpu_bo_set_metadata
  amdgpu_bo_va_op
  amdgpu_bo_va_op_raw
  amdgpu_bo_wait_for_idle
  amdgpu_create_bo_from_user_mem
  amdgpu_cs_chunk_fence_info_to_data
@@ -40,20 +42,21 @@ amdgpu_cs_destroy_semaphore
  amdgpu_cs_destroy_syncobj
  amdgpu_cs_export_syncobj
  amdgpu_cs_fence_to_handle
  amdgpu_cs_import_syncobj
  amdgpu_cs_query_fence_status
  amdgpu_cs_query_reset_state
  amdgpu_query_sw_info
  amdgpu_cs_signal_semaphore
  amdgpu_cs_submit
  amdgpu_cs_submit_raw
+amdgpu_cs_submit_raw2
  amdgpu_cs_syncobj_export_sync_file
  amdgpu_cs_syncobj_import_sync_file
  amdgpu_cs_syncobj_reset
  amdgpu_cs_syncobj_signal
  amdgpu_cs_syncobj_wait
  amdgpu_cs_wait_fences
  amdgpu_cs_wait_semaphore
  amdgpu_device_deinitialize
  amdgpu_device_initialize
  amdgpu_find_bo_by_cpu_mapping
diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h
index dc51659a..5b800033 100644
--- a/amdgpu/amdgpu.h
+++ b/amdgpu/amdgpu.h
@@ -35,20 +35,21 @@
  #define _AMDGPU_H_
  
  #include 

  #include 
  
  #ifdef __cplusplus

  extern "C" {
  #endif
  
  struct drm_amdgpu_info_hw_ip;

+struct drm_amdgpu_bo_list_entry;
  
  /*--*/

  /* --- Defines  */
  /*--*/
  
  /**

   * Define max. number of Command Buffers (IB) which could be sent to the 
single
   * hardware IP to accommodate CE/DE requirements
   *
   * \sa amdgpu_cs_ib_info
@@ -767,34 +768,65 @@ int amdgpu_bo_cpu_unmap(amdgpu_bo_handle buf_handle);
   *and no GPU access is scheduled.
   *  1 GPU access is in fly or scheduled
   *
   * \return   0 - on success
   *  <0 - Negative POSIX Error code
   */
  int amdgpu_bo_wait_for_idle(amdgpu_bo_handle buf_handle,
uint64_t timeout_ns,
bool *buffer_busy);
  
+/**

+ * Creates a BO list handle for command submission.
+ *
+ * \param   dev- \c [in] Device handle.
+ *See #amdgpu_device_initialize()
+ * \param   number_of_buffers  - \c [in] Number of BOs in the list
+ * \param   buffers- \c [in] List of BO handles
+ * \param   result - \c [out] Created BO list handle
+ *
+ * \return   0 on success\n
+ *  <0 - Negative POSIX Error code
+ *
+ * \sa amdgpu_bo_list_destroy_raw()
+*/
+int amdgpu_bo_list_create_raw(amdgpu_device_handle dev,
+ uint32_t number_of_buffers,
+ struct drm_amdgpu_bo_list_entry *buffers,
+ uint32_t *result);
+
+/**
+ * Destroys a BO list handle.
+ *
+ * \param   bo_list- \c [in] BO list handle.
+ *
+ * \return   0 on success\n
+ *  <0 - Negative POSIX Error code
+ *
+ * \sa amdgpu_bo_list_create_raw(), amdgpu_cs_submit_raw2()
+*/
+int amdgpu_bo_list_destroy_raw(amdgpu_device_handle dev, uint32_t bo_list);
+
  /**
   * Creates a BO list handle for command submission.
   *
   * \param   dev   - \c [in] Device handle.
   *   See #amdgpu_device_initialize()
   * \param   number_of_resources   - \c [in] Number of BOs in the list
   * \param   resources - \c [in] List of BO handles
   * \param   resource_prios- \c [in] Optional priority for each handle
   * \param   result- \c [out] Created BO list handle
   *
   * \return   0 on success\n
   *  <0 - Negative POSIX Error code
   *
- * \sa amdgpu_bo_list_destroy()
+ * \sa amdgpu_bo_list_destroy(), amdgpu_cs_submit_raw2()
  */
  int amdgpu_bo_list_create(amdgpu_device_handle dev,
  uint32_t number_of_resources,
  amdgpu_bo_handle *resources,
  uint8_t *resource_prios,
  amdgpu_bo_list_handle *result);
  
  /**

   * Destroys a BO list handle.
   *
@@ -1580,20 +1612,42 @@ struct drm_amdgpu_cs_chunk;
  struct 

Re: [PATCH v5 1/2] drm/sched: Refactor ring mirror list handling.

[Christian König]

Am 07.01.19 um 20:47 schrieb Grodzovsky, Andrey:


On 01/07/2019 09:13 AM, Christian König wrote:

Am 03.01.19 um 18:42 schrieb Grodzovsky, Andrey:

On 01/03/2019 11:20 AM, Grodzovsky, Andrey wrote:

On 01/03/2019 03:54 AM, Koenig, Christian wrote:

Am 21.12.18 um 21:36 schrieb Grodzovsky, Andrey:

On 12/21/2018 01:37 PM, Christian König wrote:

Am 20.12.18 um 20:23 schrieb Andrey Grodzovsky:

Decauple sched threads stop and start and ring mirror
list handling from the policy of what to do about the
guilty jobs.
When stoppping the sched thread and detaching sched fences
from non signaled HW fenes wait for all signaled HW fences
to complete before rerunning the jobs.

v2: Fix resubmission of guilty job into HW after refactoring.

v4:
Full restart for all the jobs, not only from guilty ring.
Extract karma increase into standalone function.

v5:
Rework waiting for signaled jobs without relying on the job
struct itself as those might already be freed for non 'guilty'
job's schedulers.
Expose karma increase to drivers.

Suggested-by: Christian Koenig 
Signed-off-by: Andrey Grodzovsky 
---
       drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  18 +--
       drivers/gpu/drm/etnaviv/etnaviv_sched.c    |  11 +-
       drivers/gpu/drm/scheduler/sched_main.c | 188
+++--
       drivers/gpu/drm/v3d/v3d_sched.c    |  12 +-
       include/drm/gpu_scheduler.h    |  10 +-
       5 files changed, 151 insertions(+), 88 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 8a078f4..a4bd2d3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3298,12 +3298,10 @@ static int
amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
       if (!ring || !ring->sched.thread)
       continue;
       -    kthread_park(ring->sched.thread);
+    drm_sched_stop(>sched, job ? >base : NULL);
       -    if (job && job->base.sched != >sched)
-    continue;
-
-    drm_sched_hw_job_reset(>sched, job ? >base :
NULL);
+    if(job)
+ drm_sched_increase_karma(>base);

Since we dropped the "job && job->base.sched != >sched" check
above this will now increase the jobs karma multiple times.

Maybe just move that outside of the loop.


         /* after all hw jobs are reset, hw fence is
meaningless,
so force_completion */
amdgpu_fence_driver_force_completion(ring);
@@ -3454,14 +3452,10 @@ static void
amdgpu_device_post_asic_reset(struct amdgpu_device *adev,
       if (!ring || !ring->sched.thread)
       continue;
       -    /* only need recovery sched of the given job's ring
- * or all rings (in the case @job is NULL)
- * after above amdgpu_reset accomplished
- */
-    if ((!job || job->base.sched == >sched) &&
!adev->asic_reset_res)
- drm_sched_job_recovery(>sched);
+    if (!adev->asic_reset_res)
+ drm_sched_resubmit_jobs(>sched);
       -    kthread_unpark(ring->sched.thread);
+    drm_sched_start(>sched, !adev->asic_reset_res);
       }
         if (!amdgpu_device_has_dc_support(adev)) {
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_sched.c
b/drivers/gpu/drm/etnaviv/etnaviv_sched.c
index 49a6763..6f1268f 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_sched.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_sched.c
@@ -109,16 +109,19 @@ static void etnaviv_sched_timedout_job(struct
drm_sched_job *sched_job)
       }
         /* block scheduler */
-    kthread_park(gpu->sched.thread);
-    drm_sched_hw_job_reset(>sched, sched_job);
+    drm_sched_stop(>sched, sched_job);
+
+    if(sched_job)
+    drm_sched_increase_karma(sched_job);
         /* get the GPU back into the init state */
       etnaviv_core_dump(gpu);
       etnaviv_gpu_recover_hang(gpu);
       + drm_sched_resubmit_jobs(>sched);
+
       /* restart scheduler after GPU is usable again */
-    drm_sched_job_recovery(>sched);
-    kthread_unpark(gpu->sched.thread);
+    drm_sched_start(>sched, true);
       }
         static void etnaviv_sched_free_job(struct drm_sched_job
*sched_job)
diff --git a/drivers/gpu/drm/scheduler/sched_main.c
b/drivers/gpu/drm/scheduler/sched_main.c
index dbb6906..b5c5bee 100644
--- a/drivers/gpu/drm/scheduler/sched_main.c
+++ b/drivers/gpu/drm/scheduler/sched_main.c
@@ -60,8 +60,6 @@
         static void drm_sched_process_job(struct dma_fence *f,
struct
dma_fence_cb *cb);
       -static void drm_sched_expel_job_unlocked(struct
drm_sched_job
*s_job);
-
       /**
        * drm_sched_rq_init - initialize a given run queue struct
        *
@@ -335,6 +333,42 @@ static void drm_sched_job_timedout(struct
work_struct *work)
spin_unlock_irqrestore(>job_list_lock, flags);
       }

Kernel doc here would be nice to have.


+void drm_sched_increase_karma(struct drm_sched_job *bad)
+{
+    int i;
+    struct drm_sched_entity *tmp;
+    struct drm_sched_entity 

Re: [PATCH AUTOSEL 4.20 034/117] drm/amdgpu: Correct get_crtc_scanoutpos behavior when vpos >= vtotal

[Michel Dänzer]

On 2019-01-08 8:25 p.m., Sasha Levin wrote:
> From: Nicholas Kazlauskas 
> 
> [ Upstream commit 520f08df45fbe300ed650da786a74093d658b7e1 ]
> 
> When variable refresh rate is active [...]

Variable refresh rate (FreeSync) support is only landing in 5.0,
therefore this fix isn't needed in older kernels.


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Earthling Michel Dänzer   |   http://www.amd.com
Libre software enthusiast | Mesa and X developer
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