RE: [PATCH] drm/amdgpu: return err if input is not valid
Reviewed-by: Feifei Xu
-Original Message-
From: Pan, Xinhui
Sent: Tuesday, March 5, 2019 3:11 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Xu, Feifei ;
Deucher, Alexander
Subject: [PATCH] drm/amdgpu: return err if input is not valid
Signed-off-by: xinhui pan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index 8b1088dac686..1df6b03a3680 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -240,6 +240,9 @@ static int amdgpu_ras_debugfs_ctrl_parse_data(struct file
*f,
op = 1;
else if (sscanf(str, "inject %32s %8s", block_name, err) == 2)
op = 2;
+ else if (sscanf(str, "%32s", block_name) == 1)
+ /* ascii string, but commands are not matched. */
+ return -EINVAL;
if (op != -1) {
if (amdgpu_ras_find_block_id_by_name(block_name, &block_id)) @@
-352,6 +355,9 @@ static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f,
const char __user *
case 2:
ret = amdgpu_ras_error_inject(adev, &data.inject);
break;
+ default:
+ ret = -EINVAL;
+ break;
};
if (ret)
--
2.17.1
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[PATCH] drm/amdgpu: return err if input is not valid
Signed-off-by: xinhui pan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index 8b1088dac686..1df6b03a3680 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -240,6 +240,9 @@ static int amdgpu_ras_debugfs_ctrl_parse_data(struct file
*f,
op = 1;
else if (sscanf(str, "inject %32s %8s", block_name, err) == 2)
op = 2;
+ else if (sscanf(str, "%32s", block_name) == 1)
+ /* ascii string, but commands are not matched. */
+ return -EINVAL;
if (op != -1) {
if (amdgpu_ras_find_block_id_by_name(block_name, &block_id))
@@ -352,6 +355,9 @@ static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file
*f, const char __user *
case 2:
ret = amdgpu_ras_error_inject(adev, &data.inject);
break;
+ default:
+ ret = -EINVAL;
+ break;
};
if (ret)
--
2.17.1
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[PATCH] drm/amdgpu: fix kernel Oops caused by change_bit in ARM64
I got this kernel Oops when running ROCm kernel in a ARM64 machine with
Vega64 card.
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 20d7e4775d49..b6945af39b95 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -726,8 +726,8 @@ static bool gmc_v9_0_keep_stolen_memory(struct
amdgpu_device *adev)
static int gmc_v9_0_allocate_vm_inv_eng(struct amdgpu_device *adev)
{
struct amdgpu_ring *ring;
- unsigned vm_inv_engs[AMDGPU_MAX_VMHUBS] =
- {GFXHUB_FREE_VM_INV_ENGS_BITMAP, MMHUB_FREE_VM_INV_ENGS_BITMAP};
+ unsigned long vm_inv_engs[AMDGPU_MAX_VMHUBS] =
+ {GFXHUB_FREE_VM_INV_ENGS_BITMAP,
MMHUB_FREE_VM_INV_ENGS_BITMAP};
unsigned i;
unsigned vmhub, inv_eng;
@@ -743,7 +743,7 @@ static int gmc_v9_0_allocate_vm_inv_eng(struct
amdgpu_device *adev)
}
ring->vm_inv_eng = inv_eng - 1;
- change_bit(inv_eng - 1, (unsigned long *)(&vm_inv_engs[vmhub]));
+ change_bit(inv_eng - 1, &vm_inv_engs[vmhub]);
dev_info(adev->dev, "ring %s uses VM inv eng %u on hub %u\n",
ring->name, ring->vm_inv_eng, ring->funcs->vmhub);
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Re: [PATCH] drm/amdgpu: fix typing in amdgpu_virt_ops::trans_msg
On Mon, Mar 04, 2019 at 02:10:00PM +0100, Luc Van Oostenryck wrote:
> The method in struct amdgpu_virt_ops::trans_msg() is defined as
> using an 'u32' for its 2nd argument (the request) but the actual
> implementation()s and calls use an 'enum idh_request' for it.
>
> Fix this by using 'enum idh_request' for the method declaration too.
>
> Signed-off-by: Luc Van Oostenryck
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
> index 722deefc0a7e..3e9aec6f2795 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
> @@ -56,7 +56,7 @@ struct amdgpu_virt_ops {
> int (*rel_full_gpu)(struct amdgpu_device *adev, bool init);
> int (*reset_gpu)(struct amdgpu_device *adev);
> int (*wait_reset)(struct amdgpu_device *adev);
> - void (*trans_msg)(struct amdgpu_device *adev, u32 req, u32 data1, u32
> data2, u32 data3);
> + void (*trans_msg)(struct amdgpu_device *adev, enum idh_request req, u32
> data1, u32 data2, u32 data3);
> };
Sorry, this is patch is incorrect. Please ignore it.
-- Luc
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Re: [PATCH 1/2] drm/amdgpu: rework shadow handling during PD clear v3
One not so obvious change here: The fence on the page table after
clear_bo now waits for clearing both the page table and the shadow. That
may make clearing of page tables appear a bit slower. On the other hand,
if you're clearing a bunch of page tables at once, then difference will
be minimal because clearing the second page table will have to wait for
clearing the first shadow either way.
If that is acceptable, then the series is Reviewed-by: Felix Kuehling
Regards,
Felix
On 2019-03-04 11:28 a.m., Christian König wrote:
> This way we only deal with the real BO in here.
>
> v2: use a do { ... } while loop instead
> v3: fix NULL pointer in v2
>
> Signed-off-by: Christian König
> Acked-by: Huang Rui
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 67 +++---
> 1 file changed, 39 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index 12d51d96491e..d9a0ac14c4ca 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -788,44 +788,61 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device
> *adev,
>
> r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
> if (r)
> - goto error;
> + return r;
>
> r = amdgpu_ttm_alloc_gart(&bo->tbo);
> if (r)
> return r;
>
> + if (bo->shadow) {
> + r = ttm_bo_validate(&bo->shadow->tbo, &bo->shadow->placement,
> + &ctx);
> + if (r)
> + return r;
> +
> + r = amdgpu_ttm_alloc_gart(&bo->shadow->tbo);
> + if (r)
> + return r;
> +
> + }
> +
> r = amdgpu_job_alloc_with_ib(adev, 64, &job);
> if (r)
> - goto error;
> + return r;
> +
> + do {
> + addr = amdgpu_bo_gpu_offset(bo);
> + if (ats_entries) {
> + uint64_t ats_value;
>
> - addr = amdgpu_bo_gpu_offset(bo);
> - if (ats_entries) {
> - uint64_t ats_value;
> + ats_value = AMDGPU_PTE_DEFAULT_ATC;
> + if (level != AMDGPU_VM_PTB)
> + ats_value |= AMDGPU_PDE_PTE;
>
> - ats_value = AMDGPU_PTE_DEFAULT_ATC;
> - if (level != AMDGPU_VM_PTB)
> - ats_value |= AMDGPU_PDE_PTE;
> + amdgpu_vm_set_pte_pde(adev, &job->ibs[0], addr, 0,
> + ats_entries, 0, ats_value);
> + addr += ats_entries * 8;
> + }
>
> - amdgpu_vm_set_pte_pde(adev, &job->ibs[0], addr, 0,
> - ats_entries, 0, ats_value);
> - addr += ats_entries * 8;
> - }
> + if (entries) {
> + uint64_t value = 0;
>
> - if (entries) {
> - uint64_t value = 0;
> + /* Workaround for fault priority problem on GMC9 */
> + if (level == AMDGPU_VM_PTB &&
> + adev->asic_type >= CHIP_VEGA10)
> + value = AMDGPU_PTE_EXECUTABLE;
>
> - /* Workaround for fault priority problem on GMC9 */
> - if (level == AMDGPU_VM_PTB && adev->asic_type >= CHIP_VEGA10)
> - value = AMDGPU_PTE_EXECUTABLE;
> + amdgpu_vm_set_pte_pde(adev, &job->ibs[0], addr, 0,
> + entries, 0, value);
> + }
>
> - amdgpu_vm_set_pte_pde(adev, &job->ibs[0], addr, 0,
> - entries, 0, value);
> - }
> + bo = bo->shadow;
> + } while (bo);
>
> amdgpu_ring_pad_ib(ring, &job->ibs[0]);
>
> WARN_ON(job->ibs[0].length_dw > 64);
> - r = amdgpu_sync_resv(adev, &job->sync, bo->tbo.resv,
> + r = amdgpu_sync_resv(adev, &job->sync, vm->root.base.bo->tbo.resv,
>AMDGPU_FENCE_OWNER_KFD, false);
> if (r)
> goto error_free;
> @@ -835,19 +852,13 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device
> *adev,
> if (r)
> goto error_free;
>
> - amdgpu_bo_fence(bo, fence, true);
> + amdgpu_bo_fence(vm->root.base.bo, fence, true);
> dma_fence_put(fence);
>
> - if (bo->shadow)
> - return amdgpu_vm_clear_bo(adev, vm, bo->shadow,
> - level, pte_support_ats);
> -
> return 0;
>
> error_free:
> amdgpu_job_free(job);
> -
> -error:
> return r;
> }
>
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[PATCH] drm/amdgpu: Enable XGMI mapping for peer device
Adjust vram base offset for XGMI mapping when update the PT entry so
the address will fall into correct XGMI aperture for peer device
Change-Id: I78bdf244da699d2559481ef5afe9663b3e752236
Signed-off-by: shaoyunl
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 21 +
1 file changed, 17 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 12d51d9..0bc32c9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1876,6 +1876,7 @@ static int amdgpu_vm_bo_update_mapping(struct
amdgpu_device *adev,
* @vm: requested vm
* @mapping: mapped range and flags to use for the update
* @flags: HW flags for the mapping
+ * @bo_adev: amdgpu_device pointer that bo actually been allocated
* @nodes: array of drm_mm_nodes with the MC addresses
* @fence: optional resulting fence
*
@@ -1891,11 +1892,13 @@ static int amdgpu_vm_bo_split_mapping(struct
amdgpu_device *adev,
struct amdgpu_vm *vm,
struct amdgpu_bo_va_mapping *mapping,
uint64_t flags,
+ struct amdgpu_device *bo_adev,
struct drm_mm_node *nodes,
struct dma_fence **fence)
{
unsigned min_linear_pages = 1 << adev->vm_manager.fragment_size;
uint64_t pfn, start = mapping->start;
+ bool is_xgmi = false;
int r;
/* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go
here
@@ -1917,6 +1920,10 @@ static int amdgpu_vm_bo_split_mapping(struct
amdgpu_device *adev,
flags |= AMDGPU_PTE_PRT;
flags &= ~AMDGPU_PTE_VALID;
}
+ if (adev != bo_adev &&
+ adev->gmc.xgmi.hive_id &&
+ adev->gmc.xgmi.hive_id == bo_adev->gmc.xgmi.hive_id)
+ is_xgmi = true;
trace_amdgpu_vm_bo_update(mapping);
@@ -1965,7 +1972,11 @@ static int amdgpu_vm_bo_split_mapping(struct
amdgpu_device *adev,
}
} else if (flags & AMDGPU_PTE_VALID) {
- addr += adev->vm_manager.vram_base_offset;
+ if (is_xgmi == false) {
+ DRM_ERROR("Failed to map the VRAM for other
device access.\n");
+ return -EINVAL;
+ }
+ addr += bo_adev->vm_manager.vram_base_offset;
addr += pfn << PAGE_SHIFT;
}
@@ -2012,6 +2023,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
struct drm_mm_node *nodes;
struct dma_fence *exclusive, **last_update;
uint64_t flags;
+ struct amdgpu_device *bo_adev = adev;
int r;
if (clear || !bo) {
@@ -2030,9 +2042,10 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
exclusive = reservation_object_get_excl(bo->tbo.resv);
}
- if (bo)
+ if (bo) {
flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem);
- else
+ bo_adev = amdgpu_ttm_adev(bo->tbo.bdev);
+ } else
flags = 0x0;
if (clear || (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv))
@@ -2050,7 +2063,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
list_for_each_entry(mapping, &bo_va->invalids, list) {
r = amdgpu_vm_bo_split_mapping(adev, exclusive, pages_addr, vm,
- mapping, flags, nodes,
+ mapping, flags, bo_adev, nodes,
last_update);
if (r)
return r;
--
2.7.4
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[PATCH] drm/amdgpu: Enable XGMI mapping for peer device
Adjust vram base offset for XGMI mapping when update the PT entry so
the address will fall into correct XGMI aperture for peer device
Change-Id: I78bdf244da699d2559481ef5afe9663b3e752236
Signed-off-by: shaoyunl
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 18 ++
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 12d51d9..c8f98b2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1876,6 +1876,7 @@ static int amdgpu_vm_bo_update_mapping(struct
amdgpu_device *adev,
* @vm: requested vm
* @mapping: mapped range and flags to use for the update
* @flags: HW flags for the mapping
+ * @bo_adev: amdgpu_device pointer to the bo been actually allocated
* @nodes: array of drm_mm_nodes with the MC addresses
* @fence: optional resulting fence
*
@@ -1891,6 +1892,7 @@ static int amdgpu_vm_bo_split_mapping(struct
amdgpu_device *adev,
struct amdgpu_vm *vm,
struct amdgpu_bo_va_mapping *mapping,
uint64_t flags,
+ struct amdgpu_device *bo_adev,
struct drm_mm_node *nodes,
struct dma_fence **fence)
{
@@ -1965,7 +1967,13 @@ static int amdgpu_vm_bo_split_mapping(struct
amdgpu_device *adev,
}
} else if (flags & AMDGPU_PTE_VALID) {
- addr += adev->vm_manager.vram_base_offset;
+ if ((adev != bo_adev) &&
+ (!adev->gmc.xgmi.hive_id ||
+adev->gmc.xgmi.hive_id !=
bo_adev->gmc.xgmi.hive_id)) {
+ DRM_ERROR("Failed to map the VRAM for other
device access.\n");
+ return -EINVAL;
+ }
+ addr += bo_adev->vm_manager.vram_base_offset;
addr += pfn << PAGE_SHIFT;
}
@@ -2012,6 +2020,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
struct drm_mm_node *nodes;
struct dma_fence *exclusive, **last_update;
uint64_t flags;
+ struct amdgpu_device *bo_adev = adev;
int r;
if (clear || !bo) {
@@ -2030,9 +2039,10 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
exclusive = reservation_object_get_excl(bo->tbo.resv);
}
- if (bo)
+ if (bo) {
flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem);
- else
+ bo_adev = amdgpu_ttm_adev(bo->tbo.bdev);
+ } else
flags = 0x0;
if (clear || (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv))
@@ -2050,7 +2060,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
list_for_each_entry(mapping, &bo_va->invalids, list) {
r = amdgpu_vm_bo_split_mapping(adev, exclusive, pages_addr, vm,
- mapping, flags, nodes,
+ mapping, flags, bo_adev, nodes,
last_update);
if (r)
return r;
--
2.7.4
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[PATCH 3/3] drm/amdgpu: enable IH ring 1&2 for Vega20 as well
That doesn't seem to have any negative effects.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 30 +++---
1 file changed, 13 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
index fa45234f020f..1b2f69a9a24e 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
@@ -469,23 +469,19 @@ static int vega10_ih_sw_init(void *handle)
adev->irq.ih.use_doorbell = true;
adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1;
- if (adev->asic_type == CHIP_VEGA10) {
- r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, true);
- if (r)
- return r;
-
- adev->irq.ih1.use_doorbell = true;
- adev->irq.ih1.doorbell_index =
- (adev->doorbell_index.ih + 1) << 1;
-
- r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true);
- if (r)
- return r;
-
- adev->irq.ih2.use_doorbell = true;
- adev->irq.ih2.doorbell_index =
- (adev->doorbell_index.ih + 2) << 1;
- }
+ r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, true);
+ if (r)
+ return r;
+
+ adev->irq.ih1.use_doorbell = true;
+ adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1;
+
+ r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true);
+ if (r)
+ return r;
+
+ adev->irq.ih2.use_doorbell = true;
+ adev->irq.ih2.doorbell_index = (adev->doorbell_index.ih + 2) << 1;
r = amdgpu_irq_init(adev);
--
2.17.1
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[PATCH 2/3] drm/amdgpu: enable IH doorbell for ring 1&2 on Vega
The doorbells should already be reserved, just enable them.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c | 3 +-
drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 66 +-
2 files changed, 45 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
index cc967dbfd631..6590143c3f75 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
@@ -118,7 +118,8 @@ static void nbio_v6_1_ih_doorbell_range(struct
amdgpu_device *adev,
if (use_doorbell) {
ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index);
- ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
BIF_IH_DOORBELL_RANGE, SIZE, 2);
+ ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
+ BIF_IH_DOORBELL_RANGE, SIZE,
6);
} else
ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
BIF_IH_DOORBELL_RANGE, SIZE, 0);
diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
index d4a3cc413af8..fa45234f020f 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
@@ -136,6 +136,25 @@ static uint32_t vega10_ih_rb_cntl(struct amdgpu_ih_ring
*ih, uint32_t ih_rb_cntl
return ih_rb_cntl;
}
+static uint32_t vega10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih)
+{
+ u32 ih_doorbell_rtpr = 0;
+
+ if (ih->use_doorbell) {
+ ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
+IH_DOORBELL_RPTR, OFFSET,
+ih->doorbell_index);
+ ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
+IH_DOORBELL_RPTR,
+ENABLE, 1);
+ } else {
+ ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
+IH_DOORBELL_RPTR,
+ENABLE, 0);
+ }
+ return ih_doorbell_rtpr;
+}
+
/**
* vega10_ih_irq_init - init and enable the interrupt ring
*
@@ -150,8 +169,8 @@ static uint32_t vega10_ih_rb_cntl(struct amdgpu_ih_ring
*ih, uint32_t ih_rb_cntl
static int vega10_ih_irq_init(struct amdgpu_device *adev)
{
struct amdgpu_ih_ring *ih;
+ u32 ih_rb_cntl;
int ret = 0;
- u32 ih_rb_cntl, ih_doorbell_rtpr;
u32 tmp;
/* disable irqs */
@@ -177,23 +196,11 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev)
upper_32_bits(ih->wptr_addr) & 0x);
/* set rptr, wptr to 0 */
- WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0);
WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0);
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0);
- ih_doorbell_rtpr = RREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR);
- if (adev->irq.ih.use_doorbell) {
- ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
-IH_DOORBELL_RPTR, OFFSET,
-adev->irq.ih.doorbell_index);
- ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
-IH_DOORBELL_RPTR,
-ENABLE, 1);
- } else {
- ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
-IH_DOORBELL_RPTR,
-ENABLE, 0);
- }
- WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR, ih_doorbell_rtpr);
+ WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR,
+vega10_ih_doorbell_rptr(ih));
ih = &adev->irq.ih1;
if (ih->ring_size) {
@@ -210,8 +217,11 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev)
WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
/* set rptr, wptr to 0 */
- WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0);
WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0);
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0);
+
+ WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1,
+vega10_ih_doorbell_rptr(ih));
}
ih = &adev->irq.ih2;
@@ -220,13 +230,16 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev)
WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING2,
(ih->gpu_addr >> 40) & 0xff);
- ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);
+ ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl);
WREG32_SOC15(OSSSYS, 0,
[PATCH 1/3] drm/amdgpu: change Vega IH ring 1 config
Disable overflow and enable full drain. This makes fault handling on ring 1 much more reliable since we don't generate back pressure any more. Signed-off-by: Christian König --- drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c index 6d1f804277f8..d4a3cc413af8 100644 --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c @@ -203,6 +203,10 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev) ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl); + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, + WPTR_OVERFLOW_ENABLE, 0); + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, + RB_FULL_DRAIN_ENABLE, 1); WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); /* set rptr, wptr to 0 */ -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH][drm-next] drm/amdgpu: fix missing assignment of error return code to variable ret
On Sat, Mar 2, 2019 at 5:17 PM Colin King wrote:
>
> From: Colin Ian King
>
> An earlier commit replaced ttm_bo_wait with amdgpu_bo_sync_wait and
> removed the error return assignment to variable ret. Fix this by adding
> the assignment back. Also break line to clean up checkpatch overly
> long line warning.
>
> Detected by CoverityScan, CID#1477327 ("Logically dead code")
>
> Fixes: c60cd590cb7d ("drm/amdgpu: Replace ttm_bo_wait with
> amdgpu_bo_sync_wait")
> Signed-off-by: Colin Ian King
Applied. thanks!
Alex
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> index 1921dec3df7a..92993baac91a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> @@ -906,7 +906,8 @@ static int init_kfd_vm(struct amdgpu_vm *vm, void
> **process_info,
> pr_err("validate_pt_pd_bos() failed\n");
> goto validate_pd_fail;
> }
> - amdgpu_bo_sync_wait(vm->root.base.bo, AMDGPU_FENCE_OWNER_KFD, false);
> + ret = amdgpu_bo_sync_wait(vm->root.base.bo,
> + AMDGPU_FENCE_OWNER_KFD, false);
> if (ret)
> goto wait_pd_fail;
> amdgpu_bo_fence(vm->root.base.bo,
> --
> 2.20.1
>
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Re: [PATCH] drm/amdgpu: fix typing in amdgpu_virt_ops::trans_msg
Hi Luc,
I love your patch! Yet something to improve:
[auto build test ERROR on linus/master]
[also build test ERROR on v5.0 next-20190304]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Luc-Van-Oostenryck/drm-amdgpu-fix-typing-in-amdgpu_virt_ops-trans_msg/20190305-001104
config: ia64-allmodconfig (attached as .config)
compiler: ia64-linux-gcc (GCC) 8.2.0
reproduce:
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
GCC_VERSION=8.2.0 make.cross ARCH=ia64
All error/warnings (new ones prefixed by >>):
In file included from drivers/gpu/drm/amd/amdgpu/amdgpu.h:77,
from
drivers/gpu/drm/amd/amdgpu/../powerplay/inc/amd_powerplay.h:33,
from drivers/gpu/drm/amd/amdgpu/../powerplay/inc/hwmgr.h:27,
from
drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/vega12_thermal.h:27,
from
drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/vega12_thermal.c:24:
>> drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h:59:53: warning: 'enum idh_request'
>> declared inside parameter list will not be visible outside of this
>> definition or declaration
void (*trans_msg)(struct amdgpu_device *adev, enum idh_request req, u32
data1, u32 data2, u32 data3);
^~~
--
In file included from drivers/gpu/drm/amd/amdgpu/amdgpu.h:77,
from drivers/gpu/drm/amd/amdgpu/amdgpu_vf_error.c:24:
>> drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h:59:53: warning: 'enum idh_request'
>> declared inside parameter list will not be visible outside of this
>> definition or declaration
void (*trans_msg)(struct amdgpu_device *adev, enum idh_request req, u32
data1, u32 data2, u32 data3);
^~~
drivers/gpu/drm/amd/amdgpu/amdgpu_vf_error.c: In function
'amdgpu_vf_error_trans_all':
>> drivers/gpu/drm/amd/amdgpu/amdgpu_vf_error.c:82:35: error: type of formal
>> parameter 2 is incomplete
adev->virt.ops->trans_msg(adev, IDH_LOG_VF_ERROR, data1, data2, data3);
^~~~
--
In file included from drivers/gpu/drm/amd/amdgpu/amdgpu.h:77,
from drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c:24:
>> drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h:59:53: warning: 'enum idh_request'
>> declared inside parameter list will not be visible outside of this
>> definition or declaration
void (*trans_msg)(struct amdgpu_device *adev, enum idh_request req, u32
data1, u32 data2, u32 data3);
^~~
>> drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c:376:15: error: initialization of 'void
>> (*)(struct amdgpu_device *, enum idh_request, u32, u32, u32)' {aka 'void
>> (*)(struct amdgpu_device *, enum idh_request, unsigned int, unsigned int,
>> unsigned int)'} from incompatible pointer type 'void (*)(struct
>> amdgpu_device *, enum idh_request, u32, u32, u32)' {aka 'void (*)(struct
>> amdgpu_device *, enum idh_request, unsigned int, unsigned int, unsigned
>> int)'} [-Werror=incompatible-pointer-types]
.trans_msg = xgpu_ai_mailbox_trans_msg,
^
drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c:376:15: note: (near initialization for
'xgpu_ai_virt_ops.trans_msg')
cc1: some warnings being treated as errors
vim +376 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
f98b617e Monk Liu 2017-04-05 370
c9c9de93 Xiangliang Yu 2017-03-10 371 const struct amdgpu_virt_ops
xgpu_ai_virt_ops = {
c9c9de93 Xiangliang Yu 2017-03-10 372 .req_full_gpu =
xgpu_ai_request_full_gpu_access,
c9c9de93 Xiangliang Yu 2017-03-10 373 .rel_full_gpu =
xgpu_ai_release_full_gpu_access,
f98b617e Monk Liu 2017-04-05 374 .reset_gpu =
xgpu_ai_request_reset,
b5914238 pding 2017-10-24 375 .wait_reset = NULL,
89041940 Gavin Wan 2017-06-23 @376 .trans_msg =
xgpu_ai_mailbox_trans_msg,
:: The code at line 376 was first introduced by commit
:: 890419409a3aba2ca7185a824e47d8ded8df11a2 drm/amdgpu: Support passing
amdgpu critical error to host via GPU Mailbox.
:: TO: Gavin Wan
:: CC: Alex Deucher
---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
.config.gz
Description: application/gzip
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Re: [PATCH] drm/amdgpu: also reroute VMC and UMD to IH ring 1 on Vega 20
Reviewed-by: Alex Deucher
From: amd-gfx on behalf of Christian
König
Sent: Monday, March 4, 2019 1:36 PM
To: amd-gfx@lists.freedesktop.org
Subject: [PATCH] drm/amdgpu: also reroute VMC and UMD to IH ring 1 on Vega 20
Same patch we alredy did for Vega10. Just re-route page faults to a separate
ring to avoid drowning in interrupts.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 36 ++
1 file changed, 36 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index 3f59a4477a7b..2b3429d90690 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -33,6 +33,9 @@
#include "sdma0/sdma0_4_0_offset.h"
#include "nbio/nbio_7_4_offset.h"
+#include "oss/osssys_4_0_offset.h"
+#include "oss/osssys_4_0_sh_mask.h"
+
MODULE_FIRMWARE("amdgpu/vega20_sos.bin");
MODULE_FIRMWARE("amdgpu/vega20_asd.bin");
MODULE_FIRMWARE("amdgpu/vega20_ta.bin");
@@ -224,6 +227,37 @@ static int psp_v11_0_bootloader_load_sos(struct
psp_context *psp)
return ret;
}
+static void psp_v11_0_reroute_ih(struct psp_context *psp)
+{
+ struct amdgpu_device *adev = psp->adev;
+ uint32_t tmp;
+
+ /* Change IH ring for VMC */
+ tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b);
+ tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
+ tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
+
+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3);
+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
+
+ mdelay(20);
+ psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
+0x8000, 0x8000, false);
+
+ /* Change IH ring for UMC */
+ tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b);
+ tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
+
+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4);
+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
+
+ mdelay(20);
+ psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
+0x8000, 0x8000, false);
+}
+
static int psp_v11_0_ring_init(struct psp_context *psp,
enum psp_ring_type ring_type)
{
@@ -231,6 +265,8 @@ static int psp_v11_0_ring_init(struct psp_context *psp,
struct psp_ring *ring;
struct amdgpu_device *adev = psp->adev;
+ psp_v11_0_reroute_ih(psp);
+
ring = &psp->km_ring;
ring->ring_type = ring_type;
--
2.17.1
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[PATCH] drm/amdgpu: also reroute VMC and UMD to IH ring 1 on Vega 20
Same patch we alredy did for Vega10. Just re-route page faults to a separate
ring to avoid drowning in interrupts.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 36 ++
1 file changed, 36 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index 3f59a4477a7b..2b3429d90690 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -33,6 +33,9 @@
#include "sdma0/sdma0_4_0_offset.h"
#include "nbio/nbio_7_4_offset.h"
+#include "oss/osssys_4_0_offset.h"
+#include "oss/osssys_4_0_sh_mask.h"
+
MODULE_FIRMWARE("amdgpu/vega20_sos.bin");
MODULE_FIRMWARE("amdgpu/vega20_asd.bin");
MODULE_FIRMWARE("amdgpu/vega20_ta.bin");
@@ -224,6 +227,37 @@ static int psp_v11_0_bootloader_load_sos(struct
psp_context *psp)
return ret;
}
+static void psp_v11_0_reroute_ih(struct psp_context *psp)
+{
+ struct amdgpu_device *adev = psp->adev;
+ uint32_t tmp;
+
+ /* Change IH ring for VMC */
+ tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b);
+ tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
+ tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
+
+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3);
+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
+
+ mdelay(20);
+ psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
+0x8000, 0x8000, false);
+
+ /* Change IH ring for UMC */
+ tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b);
+ tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
+
+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4);
+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
+
+ mdelay(20);
+ psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
+0x8000, 0x8000, false);
+}
+
static int psp_v11_0_ring_init(struct psp_context *psp,
enum psp_ring_type ring_type)
{
@@ -231,6 +265,8 @@ static int psp_v11_0_ring_init(struct psp_context *psp,
struct psp_ring *ring;
struct amdgpu_device *adev = psp->adev;
+ psp_v11_0_reroute_ih(psp);
+
ring = &psp->km_ring;
ring->ring_type = ring_type;
--
2.17.1
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Re: [PATCH] drm/amdgpu: handle userptr corner cases with HMM path
Hi Felix,
I will split this and submit two patches for review.
I didn't realize mprotect can have userptr with more than 2 vmas. For
malloc, it will always be one or two vmas. I will loop over all VMAs to
call hmm_vma_fault to get userptr pages.
Thanks,
Philip
On 2019-03-01 7:46 p.m., Kuehling, Felix wrote:
> Since you're addressing two distinct bugs, please split this into two patches.
>
> For the multiple VMAs, should we generalize that to handle any number of
> VMAs? It's not a typical case, but you could easily construct situations with
> mprotect where different parts of the same buffer have different VMAs and
> then register that as a single user pointer. Or you could user MAP_FIXED to
> map multiple files to adjacent virtual addresses.
>
> There may be two ways to handle this:
> 1. If the userptr address range spans more than one VMA, fail
> 2. Loop over all the VMAs in the address range
>
> Thanks,
>Felix
>
> -Original Message-
> From: amd-gfx On Behalf Of Yang,
> Philip
> Sent: Friday, March 01, 2019 12:30 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Yang, Philip
> Subject: [PATCH] drm/amdgpu: handle userptr corner cases with HMM path
>
> Those corner cases are found by kfdtest.KFDIPCTest.
>
> userptr may cross two vmas if the forked child process (not call exec
> after fork) malloc buffer, then free it, and then malloc larger size
> buf, kerenl will create new vma adjacent to old vma which was cloned
> from parent process, some pages of userptr are in the first vma, the
> rest pages are in the second vma. HMM expects range only have one vma,
> we have to use two ranges to handle this case. See is_mergeable_anon_vma
> in mm/mmap.c for details.
>
> kfd userptr restore may have concurrent userptr invalidation, reschedule
> to restore and then needs call hmm_vma_range_done to remove range from
> hmm->ranges list, otherwise hmm_vma_fault add same range to the list
> will cause loop in the list because range->next point to range itself.
>
> Change-Id: I641ba7406c32bd8b7ae715f52bd896d53fe56801
> Signed-off-by: Philip Yang
> ---
> .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 28 +--
> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 73 +--
> 2 files changed, 71 insertions(+), 30 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> index f8104760f1e6..179af9d3ab19 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> @@ -1738,6 +1738,23 @@ static int update_invalid_user_pages(struct
> amdkfd_process_info *process_info,
> return 0;
> }
>
> +/* Untrack invalid userptr BOs
> + *
> + * Stop HMM track the userptr update
> + */
> +static void untrack_invalid_user_pages(struct amdkfd_process_info
> *process_info)
> +{
> + struct kgd_mem *mem, *tmp_mem;
> + struct amdgpu_bo *bo;
> +
> + list_for_each_entry_safe(mem, tmp_mem,
> + &process_info->userptr_inval_list,
> + validate_list.head) {
> + bo = mem->bo;
> + amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm);
> + }
> +}
> +
> /* Validate invalid userptr BOs
>*
>* Validates BOs on the userptr_inval_list, and moves them back to the
> @@ -1855,12 +1872,7 @@ static int validate_invalid_user_pages(struct
> amdkfd_process_info *process_info)
> out_free:
> kfree(pd_bo_list_entries);
> out_no_mem:
> - list_for_each_entry_safe(mem, tmp_mem,
> - &process_info->userptr_inval_list,
> - validate_list.head) {
> - bo = mem->bo;
> - amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm);
> - }
> + untrack_invalid_user_pages(process_info);
>
> return ret;
> }
> @@ -1904,8 +1916,10 @@ static void
> amdgpu_amdkfd_restore_userptr_worker(struct work_struct *work)
>* and we can just restart the queues.
>*/
> if (!list_empty(&process_info->userptr_inval_list)) {
> - if (atomic_read(&process_info->evicted_bos) != evicted_bos)
> + if (atomic_read(&process_info->evicted_bos) != evicted_bos) {
> + untrack_invalid_user_pages(process_info);
> goto unlock_out; /* Concurrent eviction, try again */
> + }
>
> if (validate_invalid_user_pages(process_info))
> goto unlock_out;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index cd0ccfbbcb84..e5736225f513 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -711,7 +711,7 @@ struct amdgpu_ttm_tt {
> struct task_struct *usertask;
> uint32_tuserflags;
> #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
> - struct hmm_rangerange;
> +
[PATCH 2/2] drm/amdgpu: let amdgpu_vm_clear_bo figure out ats status v2
Instead of providing it from outside figure out the ats status in the
function itself from the data structures.
v2: simplify finding the right level
v3: partially revert changes from v2, more cleanup and split code
into more functions.
Signed-off-by: Christian König
Acked-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 72 +-
1 file changed, 47 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index d9a0ac14c4ca..90c6970e080f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -182,6 +182,22 @@ static unsigned amdgpu_vm_num_entries(struct amdgpu_device
*adev,
return AMDGPU_VM_PTE_COUNT(adev);
}
+/**
+ * amdgpu_vm_num_ats_entries - return the number of ATS entries in the root PD
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * Returns:
+ * The number of entries in the root page directory which needs the ATS
setting.
+ */
+static unsigned amdgpu_vm_num_ats_entries(struct amdgpu_device *adev)
+{
+ unsigned shift;
+
+ shift = amdgpu_vm_level_shift(adev, adev->vm_manager.root_level);
+ return AMDGPU_GMC_HOLE_START >> (shift + AMDGPU_GPU_PAGE_SHIFT);
+}
+
/**
* amdgpu_vm_entries_mask - the mask to get the entry number of a PD/PT
*
@@ -747,8 +763,6 @@ bool amdgpu_vm_ready(struct amdgpu_vm *vm)
* @adev: amdgpu_device pointer
* @vm: VM to clear BO from
* @bo: BO to clear
- * @level: level this BO is at
- * @pte_support_ats: indicate ATS support from PTE
*
* Root PD needs to be reserved when calling this.
*
@@ -756,10 +770,12 @@ bool amdgpu_vm_ready(struct amdgpu_vm *vm)
* 0 on success, errno otherwise.
*/
static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
- struct amdgpu_vm *vm, struct amdgpu_bo *bo,
- unsigned level, bool pte_support_ats)
+ struct amdgpu_vm *vm,
+ struct amdgpu_bo *bo)
{
struct ttm_operation_ctx ctx = { true, false };
+ unsigned level = adev->vm_manager.root_level;
+ struct amdgpu_bo *ancestor = bo;
struct dma_fence *fence = NULL;
unsigned entries, ats_entries;
struct amdgpu_ring *ring;
@@ -767,21 +783,35 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
uint64_t addr;
int r;
+ /* Figure out our place in the hierarchy */
+ if (ancestor->parent) {
+ ++level;
+ while (ancestor->parent->parent) {
+ ++level;
+ ancestor = ancestor->parent;
+ }
+ }
+
entries = amdgpu_bo_size(bo) / 8;
+ if (!vm->pte_support_ats) {
+ ats_entries = 0;
+
+ } else if (!bo->parent) {
+ ats_entries = amdgpu_vm_num_ats_entries(adev);
+ ats_entries = min(ats_entries, entries);
+ entries -= ats_entries;
- if (pte_support_ats) {
- if (level == adev->vm_manager.root_level) {
- ats_entries = amdgpu_vm_level_shift(adev, level);
- ats_entries += AMDGPU_GPU_PAGE_SHIFT;
- ats_entries = AMDGPU_GMC_HOLE_START >> ats_entries;
- ats_entries = min(ats_entries, entries);
- entries -= ats_entries;
+ } else {
+ struct amdgpu_vm_pt *pt;
+
+ pt = container_of(ancestor->vm_bo, struct amdgpu_vm_pt, base);
+ ats_entries = amdgpu_vm_num_ats_entries(adev);
+ if ((pt - vm->root.entries) >= ats_entries) {
+ ats_entries = 0;
} else {
ats_entries = entries;
entries = 0;
}
- } else {
- ats_entries = 0;
}
ring = container_of(vm->entity.rq->sched, struct amdgpu_ring, sched);
@@ -908,7 +938,6 @@ int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
{
struct amdgpu_vm_pt_cursor cursor;
struct amdgpu_bo *pt;
- bool ats = false;
uint64_t eaddr;
int r;
@@ -918,9 +947,6 @@ int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
eaddr = saddr + size - 1;
- if (vm->pte_support_ats)
- ats = saddr < AMDGPU_GMC_HOLE_START;
-
saddr /= AMDGPU_GPU_PAGE_SIZE;
eaddr /= AMDGPU_GPU_PAGE_SIZE;
@@ -969,7 +995,7 @@ int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
amdgpu_vm_bo_base_init(&entry->base, vm, pt);
- r = amdgpu_vm_clear_bo(adev, vm, pt, cursor.level, ats);
+ r = amdgpu_vm_clear_bo(adev, vm, pt);
if (r)
goto error_free_pt;
}
@@ -3044,9 +3070,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct
amdgpu_vm *vm,
amdgpu_vm_bo_base_init(&vm->root.base, vm, root);
[PATCH 1/2] drm/amdgpu: rework shadow handling during PD clear v3
This way we only deal with the real BO in here.
v2: use a do { ... } while loop instead
v3: fix NULL pointer in v2
Signed-off-by: Christian König
Acked-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 67 +++---
1 file changed, 39 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 12d51d96491e..d9a0ac14c4ca 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -788,44 +788,61 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
if (r)
- goto error;
+ return r;
r = amdgpu_ttm_alloc_gart(&bo->tbo);
if (r)
return r;
+ if (bo->shadow) {
+ r = ttm_bo_validate(&bo->shadow->tbo, &bo->shadow->placement,
+ &ctx);
+ if (r)
+ return r;
+
+ r = amdgpu_ttm_alloc_gart(&bo->shadow->tbo);
+ if (r)
+ return r;
+
+ }
+
r = amdgpu_job_alloc_with_ib(adev, 64, &job);
if (r)
- goto error;
+ return r;
+
+ do {
+ addr = amdgpu_bo_gpu_offset(bo);
+ if (ats_entries) {
+ uint64_t ats_value;
- addr = amdgpu_bo_gpu_offset(bo);
- if (ats_entries) {
- uint64_t ats_value;
+ ats_value = AMDGPU_PTE_DEFAULT_ATC;
+ if (level != AMDGPU_VM_PTB)
+ ats_value |= AMDGPU_PDE_PTE;
- ats_value = AMDGPU_PTE_DEFAULT_ATC;
- if (level != AMDGPU_VM_PTB)
- ats_value |= AMDGPU_PDE_PTE;
+ amdgpu_vm_set_pte_pde(adev, &job->ibs[0], addr, 0,
+ ats_entries, 0, ats_value);
+ addr += ats_entries * 8;
+ }
- amdgpu_vm_set_pte_pde(adev, &job->ibs[0], addr, 0,
- ats_entries, 0, ats_value);
- addr += ats_entries * 8;
- }
+ if (entries) {
+ uint64_t value = 0;
- if (entries) {
- uint64_t value = 0;
+ /* Workaround for fault priority problem on GMC9 */
+ if (level == AMDGPU_VM_PTB &&
+ adev->asic_type >= CHIP_VEGA10)
+ value = AMDGPU_PTE_EXECUTABLE;
- /* Workaround for fault priority problem on GMC9 */
- if (level == AMDGPU_VM_PTB && adev->asic_type >= CHIP_VEGA10)
- value = AMDGPU_PTE_EXECUTABLE;
+ amdgpu_vm_set_pte_pde(adev, &job->ibs[0], addr, 0,
+ entries, 0, value);
+ }
- amdgpu_vm_set_pte_pde(adev, &job->ibs[0], addr, 0,
- entries, 0, value);
- }
+ bo = bo->shadow;
+ } while (bo);
amdgpu_ring_pad_ib(ring, &job->ibs[0]);
WARN_ON(job->ibs[0].length_dw > 64);
- r = amdgpu_sync_resv(adev, &job->sync, bo->tbo.resv,
+ r = amdgpu_sync_resv(adev, &job->sync, vm->root.base.bo->tbo.resv,
AMDGPU_FENCE_OWNER_KFD, false);
if (r)
goto error_free;
@@ -835,19 +852,13 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
if (r)
goto error_free;
- amdgpu_bo_fence(bo, fence, true);
+ amdgpu_bo_fence(vm->root.base.bo, fence, true);
dma_fence_put(fence);
- if (bo->shadow)
- return amdgpu_vm_clear_bo(adev, vm, bo->shadow,
- level, pte_support_ats);
-
return 0;
error_free:
amdgpu_job_free(job);
-
-error:
return r;
}
--
2.17.1
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Re: [PATCH] drm/amd/amdgpu: Add ENGINE_CNTL register to vcn10 headers
Am 04.03.19 um 16:59 schrieb StDenis, Tom: Signed-off-by: Tom St Denis Acked-by: Christian König --- drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h | 2 ++ drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h | 5 + 2 files changed, 7 insertions(+) diff --git a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h index 442ca7c471a5..6109f5ad25ad 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h @@ -141,6 +141,8 @@ #define mmUVD_GPCOM_VCPU_DATA0_BASE_IDX 1 #define mmUVD_GPCOM_VCPU_DATA1 0x03c5 #define mmUVD_GPCOM_VCPU_DATA1_BASE_IDX 1 +#define mmUVD_ENGINE_CNTL 0x03c6 +#define mmUVD_ENGINE_CNTL_BASE_IDX 1 #define mmUVD_UDEC_DBW_UV_ADDR_CONFIG 0x03d2 #define mmUVD_UDEC_DBW_UV_ADDR_CONFIG_BASE_IDX 1 #define mmUVD_UDEC_ADDR_CONFIG 0x03d3 diff --git a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h index 63457f9df4c5..f84bed6eecb9 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h @@ -312,6 +312,11 @@ //UVD_GPCOM_VCPU_DATA1 #define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x0 #define UVD_GPCOM_VCPU_DATA1__DATA1_MASK 0xL +//UVD_ENGINE_CNTL +#define UVD_ENGINE_CNTL__ENGINE_START_MASK 0x1 +#define UVD_ENGINE_CNTL__ENGINE_START__SHIFT 0x0 +#define UVD_ENGINE_CNTL__ENGINE_START_MODE_MASK 0x2 +#define UVD_ENGINE_CNTL__ENGINE_START_MODE__SHIFT 0x1 //UVD_UDEC_DBW_UV_ADDR_CONFIG #define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amd/amdgpu: Add ENGINE_CNTL register to vcn10 headers
Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h | 2 ++ drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h | 5 + 2 files changed, 7 insertions(+) diff --git a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h index 442ca7c471a5..6109f5ad25ad 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h @@ -141,6 +141,8 @@ #define mmUVD_GPCOM_VCPU_DATA0_BASE_IDX 1 #define mmUVD_GPCOM_VCPU_DATA1 0x03c5 #define mmUVD_GPCOM_VCPU_DATA1_BASE_IDX 1 +#define mmUVD_ENGINE_CNTL 0x03c6 +#define mmUVD_ENGINE_CNTL_BASE_IDX 1 #define mmUVD_UDEC_DBW_UV_ADDR_CONFIG 0x03d2 #define mmUVD_UDEC_DBW_UV_ADDR_CONFIG_BASE_IDX 1 #define mmUVD_UDEC_ADDR_CONFIG 0x03d3 diff --git a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h index 63457f9df4c5..f84bed6eecb9 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h @@ -312,6 +312,11 @@ //UVD_GPCOM_VCPU_DATA1 #define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x0 #define UVD_GPCOM_VCPU_DATA1__DATA1_MASK 0xL +//UVD_ENGINE_CNTL +#define UVD_ENGINE_CNTL__ENGINE_START_MASK 0x1 +#define UVD_ENGINE_CNTL__ENGINE_START__SHIFT 0x0 +#define UVD_ENGINE_CNTL__ENGINE_START_MODE_MASK 0x2 +#define UVD_ENGINE_CNTL__ENGINE_START_MODE__SHIFT 0x1 //UVD_UDEC_DBW_UV_ADDR_CONFIG #define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 -- 2.17.2 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: fix typing in amdgpu_virt_ops::trans_msg
The method in struct amdgpu_virt_ops::trans_msg() is defined as
using an 'u32' for its 2nd argument (the request) but the actual
implementation()s and calls use an 'enum idh_request' for it.
Fix this by using 'enum idh_request' for the method declaration too.
Signed-off-by: Luc Van Oostenryck
---
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
index 722deefc0a7e..3e9aec6f2795 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
@@ -56,7 +56,7 @@ struct amdgpu_virt_ops {
int (*rel_full_gpu)(struct amdgpu_device *adev, bool init);
int (*reset_gpu)(struct amdgpu_device *adev);
int (*wait_reset)(struct amdgpu_device *adev);
- void (*trans_msg)(struct amdgpu_device *adev, u32 req, u32 data1, u32
data2, u32 data3);
+ void (*trans_msg)(struct amdgpu_device *adev, enum idh_request req, u32
data1, u32 data2, u32 data3);
};
/*
--
2.21.0
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Re: [PATCH] drm/amdgpu: reroute VMC and UMD to IH ring 1
Would be good to verify this across all vega parts (10/12/20). Other than that:
Reviewed-by: Alex Deucher
From: amd-gfx on behalf of Christian
König
Sent: Monday, March 4, 2019 8:15 AM
To: amd-gfx@lists.freedesktop.org
Subject: [PATCH] drm/amdgpu: reroute VMC and UMD to IH ring 1
Page faults can easily overwhelm the interrupt handler.
So to make sure that we never lose valuable interrupts on the primary ring
we re-route page faults to IH ring 1.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h | 1 +
drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 36 +
2 files changed, 37 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
index f3a7d207af07..2f79765b4bdb 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
+++ b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
@@ -43,6 +43,7 @@ enum psp_gfx_crtl_cmd_id
GFX_CTRL_CMD_ID_ENABLE_INT = 0x0005, /* enable PSP-to-Gfx
interrupt */
GFX_CTRL_CMD_ID_DISABLE_INT = 0x0006, /* disable PSP-to-Gfx
interrupt */
GFX_CTRL_CMD_ID_MODE1_RST = 0x0007, /* trigger the Mode 1
reset */
+GFX_CTRL_CMD_ID_GBR_IH_SET = 0x0008, /* set Gbr IH_RB_CNTL
registers */
GFX_CTRL_CMD_ID_CONSUME_CMD = 0x000A, /* send interrupt to psp
for updating write pointer of vf */
GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING = 0x000C, /* destroy GPCOM ring */
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
index 0487e3a4e9e7..143f0fae69d5 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
@@ -37,6 +37,9 @@
#include "sdma0/sdma0_4_0_offset.h"
#include "nbio/nbio_6_1_offset.h"
+#include "oss/osssys_4_0_offset.h"
+#include "oss/osssys_4_0_sh_mask.h"
+
MODULE_FIRMWARE("amdgpu/vega10_sos.bin");
MODULE_FIRMWARE("amdgpu/vega10_asd.bin");
MODULE_FIRMWARE("amdgpu/vega12_sos.bin");
@@ -252,6 +255,37 @@ static int psp_v3_1_ring_init(struct psp_context *psp,
return 0;
}
+static void psp_v3_1_reroute_ih(struct psp_context *psp)
+{
+ struct amdgpu_device *adev = psp->adev;
+ uint32_t tmp;
+
+ /* Change IH ring for VMC */
+ tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b);
+ tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
+ tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
+
+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3);
+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
+
+ mdelay(20);
+ psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
+0x8000, 0x8000, false);
+
+ /* Change IH ring for UMC */
+ tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b);
+ tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
+
+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4);
+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
+
+ mdelay(20);
+ psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
+0x8000, 0x8000, false);
+}
+
static int psp_v3_1_ring_create(struct psp_context *psp,
enum psp_ring_type ring_type)
{
@@ -260,6 +294,8 @@ static int psp_v3_1_ring_create(struct psp_context *psp,
struct psp_ring *ring = &psp->km_ring;
struct amdgpu_device *adev = psp->adev;
+ psp_v3_1_reroute_ih(psp);
+
/* Write low address of the ring to C2PMSG_69 */
psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
--
2.17.1
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[PATCH] drm/amdgpu: reroute VMC and UMD to IH ring 1
Page faults can easily overwhelm the interrupt handler.
So to make sure that we never lose valuable interrupts on the primary ring
we re-route page faults to IH ring 1.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h | 1 +
drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 36 +
2 files changed, 37 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
index f3a7d207af07..2f79765b4bdb 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
+++ b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
@@ -43,6 +43,7 @@ enum psp_gfx_crtl_cmd_id
GFX_CTRL_CMD_ID_ENABLE_INT = 0x0005, /* enable PSP-to-Gfx
interrupt */
GFX_CTRL_CMD_ID_DISABLE_INT = 0x0006, /* disable PSP-to-Gfx
interrupt */
GFX_CTRL_CMD_ID_MODE1_RST = 0x0007, /* trigger the Mode 1
reset */
+GFX_CTRL_CMD_ID_GBR_IH_SET = 0x0008, /* set Gbr IH_RB_CNTL
registers */
GFX_CTRL_CMD_ID_CONSUME_CMD = 0x000A, /* send interrupt to psp
for updating write pointer of vf */
GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING = 0x000C, /* destroy GPCOM ring */
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
index 0487e3a4e9e7..143f0fae69d5 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
@@ -37,6 +37,9 @@
#include "sdma0/sdma0_4_0_offset.h"
#include "nbio/nbio_6_1_offset.h"
+#include "oss/osssys_4_0_offset.h"
+#include "oss/osssys_4_0_sh_mask.h"
+
MODULE_FIRMWARE("amdgpu/vega10_sos.bin");
MODULE_FIRMWARE("amdgpu/vega10_asd.bin");
MODULE_FIRMWARE("amdgpu/vega12_sos.bin");
@@ -252,6 +255,37 @@ static int psp_v3_1_ring_init(struct psp_context *psp,
return 0;
}
+static void psp_v3_1_reroute_ih(struct psp_context *psp)
+{
+ struct amdgpu_device *adev = psp->adev;
+ uint32_t tmp;
+
+ /* Change IH ring for VMC */
+ tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b);
+ tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
+ tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
+
+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3);
+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
+
+ mdelay(20);
+ psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
+0x8000, 0x8000, false);
+
+ /* Change IH ring for UMC */
+ tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b);
+ tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
+
+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4);
+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
+
+ mdelay(20);
+ psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
+0x8000, 0x8000, false);
+}
+
static int psp_v3_1_ring_create(struct psp_context *psp,
enum psp_ring_type ring_type)
{
@@ -260,6 +294,8 @@ static int psp_v3_1_ring_create(struct psp_context *psp,
struct psp_ring *ring = &psp->km_ring;
struct amdgpu_device *adev = psp->adev;
+ psp_v3_1_reroute_ih(psp);
+
/* Write low address of the ring to C2PMSG_69 */
psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
--
2.17.1
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Re: [PATCH] drm/amdgpu: fix compile warnings
Am 01.03.19 um 17:43 schrieb Bhawanpreet Lakha:
Fixes the warnings below
warning: ‘ta_hdr’ may be used uninitialized in this function
[-Wmaybe-uninitialized]
warning: ISO C90 forbids mixed declarations and code
[-Wdeclaration-after-statement]
warning: unused variable ‘ras_cmd’ [-Wunused-variable]
warning: comparison of distinct pointer types lacks a cast
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 1 -
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 2 +-
5 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 933822eb1227..0bbbc7cd2bea 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -927,7 +927,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void
*data, struct drm_file
if (!ras)
return -EINVAL;
return copy_to_user(out, &ras->features,
- min(size, sizeof(ras->features))) ? -EFAULT : 0;
+ min((size_t)size, sizeof(ras->features))) ?
-EFAULT : 0;
}
default:
DRM_DEBUG_KMS("Invalid request %d\n", info->query);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 607c696db56b..7e3e1d588d74 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -654,7 +654,6 @@ static int psp_ras_terminate(struct psp_context *psp)
static int psp_ras_initialize(struct psp_context *psp)
{
- struct ta_ras_shared_memory *ras_cmd;
int ret;
if (!psp->ras.ras_initialized) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index 604762263221..29552e39816c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -142,7 +142,7 @@ static ssize_t amdgpu_ras_debugfs_read(struct file *f, char
__user *buf,
return 0;
s -= *pos;
- s = min(s, size);
+ s = min((size_t)s, size);
if (copy_to_user(buf, &val[*pos], s))
return -EINVAL;
@@ -159,7 +159,7 @@ static ssize_t amdgpu_ras_debugfs_write(struct file *f,
const char __user *buf,
struct ras_inject_if info = {
.head = obj->head,
};
- ssize_t s = min(64ULL, size);
+ ssize_t s = min((size_t)64ULL, size);
When you cast it anyway, you can drop the ULL.
char val[64];
char *str = val;
memset(val, 0, sizeof(val));
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index e1d3bef5a60c..88c45f990f05 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -4813,11 +4813,11 @@ static int gfx_v9_0_cp_ecc_error_irq(struct
amdgpu_device *adev,
struct amdgpu_irq_src *source,
struct amdgpu_iv_entry *entry)
{
- DRM_ERROR("CP ECC ERROR IRQ\n");
struct ras_dispatch_if ih_data = {
.head = *adev->gfx.ras_if,
.entry = entry,
};
+ DRM_ERROR("CP ECC ERROR IRQ\n");
A newline between declaration and code please.
Christian.
amdgpu_ras_interrupt_dispatch(adev, &ih_data);
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index 8f694968c0ad..2f6f82d13cc8 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -48,7 +48,7 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
int err = 0;
const struct psp_firmware_header_v1_0 *sos_hdr;
const struct psp_firmware_header_v1_0 *asd_hdr;
- const struct ta_firmware_header_v1_0 *ta_hdr;
+ const struct ta_firmware_header_v1_0 *ta_hdr = NULL;
DRM_DEBUG("\n");
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RE: [PATCH] drm/amd/powerplay: fix memdup.cocci warnings
> -Original Message-
> From: Julia Lawall [mailto:julia.law...@lip6.fr]
> Sent: Saturday, March 02, 2019 2:51 PM
> To: Gao, Likun
> Cc: Deucher, Alexander ; Wang, Kevin(Yang)
> ; Quan, Evan ; Koenig,
> Christian ; David Airlie ;
> Daniel Vetter ; Huang, Ray ; amd-
> g...@lists.freedesktop.org; kbuild test robot ; dri-
> de...@lists.freedesktop.org; kbuild-...@01.org
> Subject: [PATCH] drm/amd/powerplay: fix memdup.cocci warnings
>
> From: kbuild test robot
>
> Simplify the code a bit by using kmemdup instead of kzalloc and memcpy.
>
> Generated by: scripts/coccinelle/api/memdup.cocci
>
> Fixes: 76760fe3c00d ("drm/amd/powerplay: add function to store overdrive
> information for smu11")
> CC: Likun Gao
> Signed-off-by: kbuild test robot
> Signed-off-by: Julia Lawall
Acked-by: Huang Rui
> ---
>
> tree: git://people.freedesktop.org/~agd5f/linux.git drm-next-5.2-wip
> head: 25752e1fc83e9f983b11d680fc7bfc129b4eaae6
> commit: 76760fe3c00d04f25cc1a6115294310d4effeb77 [161/226]
> drm/amd/powerplay: add function to store overdrive information for smu11
> :: branch date: 6 hours ago
> :: commit date: 6 hours ago
>
> vega20_ppt.c | 24 +---
> 1 file changed, 9 insertions(+), 15 deletions(-)
>
> --- a/drivers/gpu/drm/amd/amdgpu/../powerplay/vega20_ppt.c
> +++ b/drivers/gpu/drm/amd/amdgpu/../powerplay/vega20_ppt.c
> @@ -173,14 +173,12 @@ static int vega20_setup_od8_information(
> if (table_context->od_feature_capabilities)
> return -EINVAL;
>
> - table_context->od_feature_capabilities =
> kzalloc(od_feature_array_size, GFP_KERNEL);
> + table_context->od_feature_capabilities =
> kmemdup(&powerplay_table->OverDrive8Table.ODFeatureCapabilities,
> +
> od_feature_array_size,
> +
> GFP_KERNEL);
> if (!table_context->od_feature_capabilities)
> return -ENOMEM;
>
> - memcpy(table_context->od_feature_capabilities,
> -&powerplay_table-
> >OverDrive8Table.ODFeatureCapabilities,
> -od_feature_array_size);
> -
> /* Setup correct ODSettingCount, and store ODSettingArray
> from
>* powerplay table to od_settings_max and od_setting_min
> */
> od_setting_count =
> @@ -194,7 +192,9 @@ static int vega20_setup_od8_information(
> if (table_context->od_settings_max)
> return -EINVAL;
>
> - table_context->od_settings_max =
> kzalloc(od_setting_array_size, GFP_KERNEL);
> + table_context->od_settings_max =
> kmemdup(&powerplay_table->OverDrive8Table.ODSettingsMax,
> +
> od_setting_array_size,
> + GFP_KERNEL);
>
> if (!table_context->od_settings_max) {
> kfree(table_context->od_feature_capabilities);
> @@ -202,14 +202,12 @@ static int vega20_setup_od8_information(
> return -ENOMEM;
> }
>
> - memcpy(table_context->od_settings_max,
> -&powerplay_table->OverDrive8Table.ODSettingsMax,
> -od_setting_array_size);
> -
> if (table_context->od_settings_min)
> return -EINVAL;
>
> - table_context->od_settings_min =
> kzalloc(od_setting_array_size, GFP_KERNEL);
> + table_context->od_settings_min =
> kmemdup(&powerplay_table->OverDrive8Table.ODSettingsMin,
> +
> od_setting_array_size,
> + GFP_KERNEL);
>
> if (!table_context->od_settings_min) {
> kfree(table_context->od_feature_capabilities);
> @@ -218,10 +216,6 @@ static int vega20_setup_od8_information(
> table_context->od_settings_max = NULL;
> return -ENOMEM;
> }
> -
> - memcpy(table_context->od_settings_min,
> -&powerplay_table->OverDrive8Table.ODSettingsMin,
> -od_setting_array_size);
> }
>
> return 0;
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[PATCH][drm-next] drm/amdgpu: fix missing assignment of error return code to variable ret
From: Colin Ian King
An earlier commit replaced ttm_bo_wait with amdgpu_bo_sync_wait and
removed the error return assignment to variable ret. Fix this by adding
the assignment back. Also break line to clean up checkpatch overly
long line warning.
Detected by CoverityScan, CID#1477327 ("Logically dead code")
Fixes: c60cd590cb7d ("drm/amdgpu: Replace ttm_bo_wait with amdgpu_bo_sync_wait")
Signed-off-by: Colin Ian King
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index 1921dec3df7a..92993baac91a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -906,7 +906,8 @@ static int init_kfd_vm(struct amdgpu_vm *vm, void
**process_info,
pr_err("validate_pt_pd_bos() failed\n");
goto validate_pd_fail;
}
- amdgpu_bo_sync_wait(vm->root.base.bo, AMDGPU_FENCE_OWNER_KFD, false);
+ ret = amdgpu_bo_sync_wait(vm->root.base.bo,
+ AMDGPU_FENCE_OWNER_KFD, false);
if (ret)
goto wait_pd_fail;
amdgpu_bo_fence(vm->root.base.bo,
--
2.20.1
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Re: [PATCH] drm/amdgpu/powerplay: Fix missing break in switch statement
On 3/1/19 5:54 PM, Alex Deucher wrote:
> On Fri, Mar 1, 2019 at 4:51 PM Gustavo A. R. Silva
> wrote:
>>
>> Add missing break statement in order to prevent the code from falling
>> through to case SMU_Discrete_DpmTable.
>>
>> This bug was found thanks to the ongoing efforts to enable
>> -Wimplicit-fallthrough.
>>
>> Fixes: 34a564eaf528 ("drm/amd/powerplay: implement fw image related smum
>> interface for Polaris.")
>> Cc: sta...@vger.kernel.org
>> Signed-off-by: Gustavo A. R. Silva
>
> Already fixed:
> https://cgit.freedesktop.org/~agd5f/linux/commit/?h=drm-next-5.2-wip&id=6feaa4194c18578623565017f95d1b2f6b243567
>
Awesome. :)
I was looking for that link, but I didn't find it. That's why
I sent this patch.
Happy to see it is fixed now.
Thanks, Alex.
--
Gustavo
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[PATCH] drm/amd/powerplay: fix memdup.cocci warnings
From: kbuild test robot
Simplify the code a bit by using kmemdup instead of kzalloc and memcpy.
Generated by: scripts/coccinelle/api/memdup.cocci
Fixes: 76760fe3c00d ("drm/amd/powerplay: add function to store overdrive
information for smu11")
CC: Likun Gao
Signed-off-by: kbuild test robot
Signed-off-by: Julia Lawall
---
tree: git://people.freedesktop.org/~agd5f/linux.git drm-next-5.2-wip
head: 25752e1fc83e9f983b11d680fc7bfc129b4eaae6
commit: 76760fe3c00d04f25cc1a6115294310d4effeb77 [161/226] drm/amd/powerplay:
add function to store overdrive information for smu11
:: branch date: 6 hours ago
:: commit date: 6 hours ago
vega20_ppt.c | 24 +---
1 file changed, 9 insertions(+), 15 deletions(-)
--- a/drivers/gpu/drm/amd/amdgpu/../powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/amdgpu/../powerplay/vega20_ppt.c
@@ -173,14 +173,12 @@ static int vega20_setup_od8_information(
if (table_context->od_feature_capabilities)
return -EINVAL;
- table_context->od_feature_capabilities =
kzalloc(od_feature_array_size, GFP_KERNEL);
+ table_context->od_feature_capabilities =
kmemdup(&powerplay_table->OverDrive8Table.ODFeatureCapabilities,
+
od_feature_array_size,
+GFP_KERNEL);
if (!table_context->od_feature_capabilities)
return -ENOMEM;
- memcpy(table_context->od_feature_capabilities,
- &powerplay_table->OverDrive8Table.ODFeatureCapabilities,
- od_feature_array_size);
-
/* Setup correct ODSettingCount, and store ODSettingArray from
* powerplay table to od_settings_max and od_setting_min */
od_setting_count =
@@ -194,7 +192,9 @@ static int vega20_setup_od8_information(
if (table_context->od_settings_max)
return -EINVAL;
- table_context->od_settings_max = kzalloc(od_setting_array_size,
GFP_KERNEL);
+ table_context->od_settings_max =
kmemdup(&powerplay_table->OverDrive8Table.ODSettingsMax,
+od_setting_array_size,
+GFP_KERNEL);
if (!table_context->od_settings_max) {
kfree(table_context->od_feature_capabilities);
@@ -202,14 +202,12 @@ static int vega20_setup_od8_information(
return -ENOMEM;
}
- memcpy(table_context->od_settings_max,
- &powerplay_table->OverDrive8Table.ODSettingsMax,
- od_setting_array_size);
-
if (table_context->od_settings_min)
return -EINVAL;
- table_context->od_settings_min = kzalloc(od_setting_array_size,
GFP_KERNEL);
+ table_context->od_settings_min =
kmemdup(&powerplay_table->OverDrive8Table.ODSettingsMin,
+od_setting_array_size,
+GFP_KERNEL);
if (!table_context->od_settings_min) {
kfree(table_context->od_feature_capabilities);
@@ -218,10 +216,6 @@ static int vega20_setup_od8_information(
table_context->od_settings_max = NULL;
return -ENOMEM;
}
-
- memcpy(table_context->od_settings_min,
- &powerplay_table->OverDrive8Table.ODSettingsMin,
- od_setting_array_size);
}
return 0;
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