[PATCH 10/13] drm/amd/display: use dc_is_virtual instead of ENUM
From: Eric Bernstein
Signed-off-by: Eric Bernstein
Reviewed-by: Dmytro Laktyushkin
Reviewed-by: Nevenko Stupar
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 7 +++
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 3 ++-
.../gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c| 2 +-
drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c| 2 +-
4 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index f5ec65ec1460..b39f76e61039 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -640,7 +640,8 @@ bool dc_link_detect(struct dc_link *link, enum
dc_detect_reason reason)
bool same_dpcd = true;
enum dc_connection_type new_connection_type = dc_connection_none;
DC_LOGGER_INIT(link->ctx->logger);
- if (link->connector_signal == SIGNAL_TYPE_VIRTUAL)
+
+ if (dc_is_virtual_signal(link->connector_signal))
return false;
if (false == dc_link_detect_sink(link, _connection_type)) {
@@ -1171,8 +1172,6 @@ static bool construct(
goto create_fail;
}
-
-
/* TODO: #DAL3 Implement id to str function.*/
LINK_INFO("Connector[%d] description:"
"signal %d\n",
@@ -2562,7 +2561,7 @@ void core_link_enable_stream(
enum dc_status status;
DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
- if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL) {
+ if (!dc_is_virtual_signal(pipe_ctx->stream->signal)) {
stream->link->link_enc->funcs->setup(
stream->link->link_enc,
pipe_ctx->stream->signal);
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 42ef04230ea2..caf9d894f95f 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -2788,10 +2788,11 @@ enum dc_status dc_validate_stream(struct dc *dc, struct
dc_stream_state *stream)
if (!tg->funcs->validate_timing(tg, >timing))
res = DC_FAIL_CONTROLLER_VALIDATE;
- if (res == DC_OK)
+ if (res == DC_OK) {
if (!link->link_enc->funcs->validate_output_with_stream(
link->link_enc, stream))
res = DC_FAIL_ENC_VALIDATE;
+ }
/* TODO: validate audio ASIC caps, encoder */
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index d0cc18aa2dc6..a1c4d26c6747 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1368,7 +1368,7 @@ static enum dc_status apply_single_controller_ctx_to_hw(
pipe_ctx->stream_res.tg->funcs->set_static_screen_control(
pipe_ctx->stream_res.tg, event_triggers);
- if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL)
+ if (!dc_is_virtual_signal(pipe_ctx->stream->signal))
pipe_ctx->stream_res.stream_enc->funcs->dig_connect_to_otg(
pipe_ctx->stream_res.stream_enc,
pipe_ctx->stream_res.tg->inst);
diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
index 02e9343951dd..2f28a74383f5 100644
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
@@ -892,7 +892,7 @@ enum dc_status resource_map_phy_clock_resources(
return DC_ERROR_UNEXPECTED;
if (dc_is_dp_signal(pipe_ctx->stream->signal)
- || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL)
+ || dc_is_virtual_signal(pipe_ctx->stream->signal))
pipe_ctx->clock_source =
dc->res_pool->dp_clock_source;
else
--
2.17.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 00/13] DC Patches 22 Mar 2019
Summary of changes *Program default gamma *cleanup unused functions *preferred pipe split logic Aric Cyr (1): drm/amd/display: 3.2.24 Dmytro Laktyushkin (1): drm/amd/display: fix odm output gamma programming Eric Bernstein (1): drm/amd/display: use dc_is_virtual instead of ENUM Eryk Brol (1): drm/amd/display: Create clock funcs Fatemeh Darbehani (1): drm/amd/display: Clean up old pplib interface functions Harry Wentland (1): drm/amd/display: Pass init_data into DCN resource creation Hugo Hu (1): drm/amd/display: Handle branch device with DFP count = 0 case. Joshua Aberback (1): drm/amd/display: Populate macro_tile_size field for dml Jun Lei (1): drm/amd/display: add preferred pipe split logic Nicholas Kazlauskas (1): drm/amd/display: Prevent cursor hotspot overflow for RV overlay planes Nikola Cornij (1): drm/amd/display: Pass SDP spliting in parameters Paul Hsieh (1): drm/amd/display: VBIOS can't be light up HDMI when restart system hersen wu (1): drm/amd/display: program default output gamma .../amd/display/amdgpu_dm/amdgpu_dm_color.c | 53 ++- .../amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 25 -- .../gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 90 ++- drivers/gpu/drm/amd/display/dc/core/dc.c | 6 +- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 21 +++-- .../gpu/drm/amd/display/dc/core/dc_link_dp.c | 9 +- .../gpu/drm/amd/display/dc/core/dc_resource.c | 87 -- drivers/gpu/drm/amd/display/dc/dc.h | 4 +- .../amd/display/dc/dce/dce_stream_encoder.c | 3 +- .../display/dc/dce110/dce110_hw_sequencer.c | 2 +- .../amd/display/dc/dce112/dce112_resource.c | 2 +- .../drm/amd/display/dc/dcn10/dcn10_clk_mgr.c | 17 .../drm/amd/display/dc/dcn10/dcn10_clk_mgr.h | 4 - .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 12 ++- .../drm/amd/display/dc/dcn10/dcn10_resource.c | 6 +- .../drm/amd/display/dc/dcn10/dcn10_resource.h | 2 +- .../display/dc/dcn10/dcn10_stream_encoder.c | 3 +- .../display/dc/dcn10/dcn10_stream_encoder.h | 3 +- drivers/gpu/drm/amd/display/dc/dm_pp_smu.h| 6 -- .../gpu/drm/amd/display/dc/inc/dcn_calcs.h| 2 + .../gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | 2 + drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h | 1 + .../amd/display/dc/inc/hw/stream_encoder.h| 3 +- drivers/gpu/drm/amd/display/dc/inc/resource.h | 12 +-- .../dc/virtual/virtual_stream_encoder.c | 3 +- 25 files changed, 196 insertions(+), 182 deletions(-) -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 09/13] drm/amd/display: 3.2.24
From: Aric Cyr Change-Id: I17892ab59c946d855c262ddbb6711feedbb5a74d Signed-off-by: Aric Cyr Reviewed-by: Aric Cyr Acked-by: Bhawanpreet Lakha --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 669f0f3e2490..54b0759325a0 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -42,7 +42,7 @@ #include "inc/hw/dmcu.h" #include "dml/display_mode_lib.h" -#define DC_VER "3.2.23" +#define DC_VER "3.2.24" #define MAX_SURFACES 3 #define MAX_PLANES 6 -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 12/13] drm/amd/display: fix odm output gamma programming
From: Dmytro Laktyushkin
Currently only top pipe gets output tf programmed. This change
makes all odm head pipes get output tf programmed.
Change-Id: I7f7c18d79668ba8cf7ffcfa1784a1fee82a108d6
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Nikola Cornij
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 4 ++--
drivers/gpu/drm/amd/display/dc/inc/resource.h | 1 +
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index caf9d894f95f..d0ed95eda508 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -1302,7 +1302,7 @@ struct pipe_ctx *dc_res_get_odm_bottom_pipe(struct
pipe_ctx *pipe_ctx)
return bottom_pipe;
}
-static bool dc_res_is_odm_bottom_pipe(struct pipe_ctx *pipe_ctx)
+bool dc_res_is_odm_head_pipe(struct pipe_ctx *pipe_ctx)
{
struct pipe_ctx *top_pipe = pipe_ctx->top_pipe;
bool result = false;
@@ -1345,7 +1345,7 @@ bool dc_remove_plane_from_context(
struct pipe_ctx *pipe_ctx = >res_ctx.pipe_ctx[i];
if (pipe_ctx->plane_state == plane_state) {
- if (dc_res_is_odm_bottom_pipe(pipe_ctx)) {
+ if (dc_res_is_odm_head_pipe(pipe_ctx)) {
pipe_ctx->plane_state = NULL;
pipe_ctx->bottom_pipe = NULL;
continue;
diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h
b/drivers/gpu/drm/amd/display/dc/inc/resource.h
index 0a70254d204f..3ce0a4fc5822 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/resource.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h
@@ -172,5 +172,6 @@ void update_audio_usage(
unsigned int resource_pixel_format_to_bpp(enum surface_pixel_format format);
struct pipe_ctx *dc_res_get_odm_bottom_pipe(struct pipe_ctx *pipe_ctx);
+bool dc_res_is_odm_head_pipe(struct pipe_ctx *pipe_ctx);
#endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_RESOURCE_H_ */
--
2.17.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 03/13] drm/amd/display: Handle branch device with DFP count = 0 case.
From: Hugo Hu
[Why]
When you have a SST branch device the driver, Even no sink device connected,
it also send HPD with a valid EDID. Driver will config it to DP sink.
Therefore, there're two displays in display setting.
DPCD 0x05, DFP_PRESENT = 1 (branch device),
DFP_TYPE = 00 (Display Port)
[How]
Driver determine DPCD 0x05 DFP_PRESENT = 1(branch) as an active dongle
And check DFP count.
Change-Id: Iccfc7b08a72b6ab732afab1ff66ab9aa5dbc28f8
Signed-off-by: Hugo Hu
Reviewed-by: Hugo Hu
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c| 5 ++---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 9 -
drivers/gpu/drm/amd/display/dc/dc.h | 2 ++
3 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 5575d1adb9b5..ac128f7a9d85 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -720,9 +720,8 @@ bool dc_link_detect(struct dc_link *link, enum
dc_detect_reason reason)
same_dpcd = false;
}
/* Active dongle plug in without display or downstream
unplug*/
- if (link->type == dc_connection_active_dongle
- && link->dpcd_caps.sink_count.
- bits.SINK_COUNT == 0) {
+ if (link->type == dc_connection_active_dongle &&
+ link->dpcd_caps.sink_count.bits.SINK_COUNT ==
0) {
if (prev_sink != NULL) {
/* Downstream unplug */
dc_sink_release(prev_sink);
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 72a88b1808fe..063d019a3f6f 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -2226,11 +2226,7 @@ bool is_mst_supported(struct dc_link *link)
bool is_dp_active_dongle(const struct dc_link *link)
{
- enum display_dongle_type dongle_type = link->dpcd_caps.dongle_type;
-
- return (dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) ||
- (dongle_type == DISPLAY_DONGLE_DP_DVI_CONVERTER) ||
- (dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER);
+ return link->dpcd_caps.is_branch_dev;
}
static int translate_dpcd_max_bpc(enum dpcd_downstream_port_max_bpc bpc)
@@ -2264,6 +2260,9 @@ static void get_active_converter_info(
return;
}
+ /* DPCD 0x5 bit 0 = 1, it indicate it's branch device */
+ link->dpcd_caps.is_branch_dev = ds_port.fields.PORT_PRESENT;
+
switch (ds_port.fields.PORT_TYPE) {
case DOWNSTREAM_VGA:
link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_VGA_CONVERTER;
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 4102a3213896..669f0f3e2490 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -704,6 +704,8 @@ struct dpcd_caps {
/* dongle type (DP converter, CV smart dongle) */
enum display_dongle_type dongle_type;
+ /* branch device or sink device */
+ bool is_branch_dev;
/* Dongle's downstream count. */
union sink_count sink_count;
/* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER,
--
2.17.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 02/13] drm/amd/display: program default output gamma
From: hersen wu
program default output gamma if no user specific gamma
parameters passed.
Change-Id: I909e6d145f8bdc49c405e8ca80839818a7c5d152
Signed-off-by: hersen wu
Reviewed-by: Sun peng Li
Acked-by: Bhawanpreet Lakha
---
.../amd/display/amdgpu_dm/amdgpu_dm_color.c | 53 ++-
1 file changed, 29 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
index 216e48cec716..7258c992a2bf 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
@@ -126,46 +126,51 @@ int amdgpu_dm_set_regamma_lut(struct dm_crtc_state *crtc)
crtc->base.state->dev->dev_private;
struct drm_color_lut *lut;
uint32_t lut_size;
- struct dc_gamma *gamma;
+ struct dc_gamma *gamma = NULL;
enum dc_transfer_func_type old_type = stream->out_transfer_func->type;
bool ret;
- if (!blob) {
+ if (!blob && adev->asic_type <= CHIP_RAVEN) {
/* By default, use the SRGB predefined curve.*/
stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
return 0;
}
- lut = (struct drm_color_lut *)blob->data;
- lut_size = blob->length / sizeof(struct drm_color_lut);
-
- gamma = dc_create_gamma();
- if (!gamma)
- return -ENOMEM;
+ if (blob) {
+ lut = (struct drm_color_lut *)blob->data;
+ lut_size = blob->length / sizeof(struct drm_color_lut);
+
+ gamma = dc_create_gamma();
+ if (!gamma)
+ return -ENOMEM;
+
+ gamma->num_entries = lut_size;
+ if (gamma->num_entries == MAX_COLOR_LEGACY_LUT_ENTRIES)
+ gamma->type = GAMMA_RGB_256;
+ else if (gamma->num_entries == MAX_COLOR_LUT_ENTRIES)
+ gamma->type = GAMMA_CS_TFM_1D;
+ else {
+ /* Invalid lut size */
+ dc_gamma_release();
+ return -EINVAL;
+ }
- gamma->num_entries = lut_size;
- if (gamma->num_entries == MAX_COLOR_LEGACY_LUT_ENTRIES)
- gamma->type = GAMMA_RGB_256;
- else if (gamma->num_entries == MAX_COLOR_LUT_ENTRIES)
- gamma->type = GAMMA_CS_TFM_1D;
- else {
- /* Invalid lut size */
- dc_gamma_release();
- return -EINVAL;
+ /* Convert drm_lut into dc_gamma */
+ __drm_lut_to_dc_gamma(lut, gamma, gamma->type == GAMMA_RGB_256);
}
- /* Convert drm_lut into dc_gamma */
- __drm_lut_to_dc_gamma(lut, gamma, gamma->type == GAMMA_RGB_256);
-
- /* Call color module to translate into something DC understands. Namely
-* a transfer function.
+ /* predefined gamma ROM only exist for RAVEN and pre-RAVEN ASIC,
+* set canRomBeUsed accordingly
*/
stream->out_transfer_func->type = TF_TYPE_DISTRIBUTED_POINTS;
ret = mod_color_calculate_regamma_params(stream->out_transfer_func,
-gamma, true, adev->asic_type
<= CHIP_RAVEN, NULL);
- dc_gamma_release();
+ gamma, true, adev->asic_type <= CHIP_RAVEN, NULL);
+
+ if (gamma)
+ dc_gamma_release();
+
if (!ret) {
stream->out_transfer_func->type = old_type;
DRM_ERROR("Out of memory when calculating regamma params\n");
--
2.17.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 11/13] drm/amd/display: Populate macro_tile_size field for dml
From: Joshua Aberback
Create a functions to return swizzle types for dml
Change-Id: Ieaeb9ce26568ee1ebdb4d2d5ce9a17af07e56c54
Signed-off-by: Joshua Aberback
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 88 ++-
.../gpu/drm/amd/display/dc/inc/dcn_calcs.h| 2 +
2 files changed, 50 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index e572ac59b035..8843361e842d 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -247,6 +247,53 @@ static enum dcn_bw_defs tl_pixel_format_to_bw_defs(enum
surface_pixel_format for
}
}
+enum source_macro_tile_size swizzle_mode_to_macro_tile_size(enum
swizzle_mode_values sw_mode)
+{
+ switch (sw_mode) {
+ /* for 4/8/16 high tiles */
+ case DC_SW_LINEAR:
+ return dm_4k_tile;
+ case DC_SW_4KB_S:
+ case DC_SW_4KB_S_X:
+ return dm_4k_tile;
+ case DC_SW_64KB_S:
+ case DC_SW_64KB_S_X:
+ case DC_SW_64KB_S_T:
+ return dm_64k_tile;
+ case DC_SW_VAR_S:
+ case DC_SW_VAR_S_X:
+ return dm_256k_tile;
+
+ /* For 64bpp 2 high tiles */
+ case DC_SW_4KB_D:
+ case DC_SW_4KB_D_X:
+ return dm_4k_tile;
+ case DC_SW_64KB_D:
+ case DC_SW_64KB_D_X:
+ case DC_SW_64KB_D_T:
+ return dm_64k_tile;
+ case DC_SW_VAR_D:
+ case DC_SW_VAR_D_X:
+ return dm_256k_tile;
+
+ case DC_SW_4KB_R:
+ case DC_SW_4KB_R_X:
+ return dm_4k_tile;
+ case DC_SW_64KB_R:
+ case DC_SW_64KB_R_X:
+ return dm_64k_tile;
+ case DC_SW_VAR_R:
+ case DC_SW_VAR_R_X:
+ return dm_256k_tile;
+
+ /* Unsupported swizzle modes for dcn */
+ case DC_SW_256B_S:
+ default:
+ ASSERT(0); /* Not supported */
+ return 0;
+ }
+}
+
static void pipe_ctx_to_e2e_pipe_params (
const struct pipe_ctx *pipe,
struct _vcs_dpi_display_pipe_params_st *input)
@@ -287,46 +334,7 @@ static void pipe_ctx_to_e2e_pipe_params (
input->src.cur0_src_width = 128; /* TODO: Cursor calcs, not
curently stored */
input->src.cur0_bpp= 32;
- switch (pipe->plane_state->tiling_info.gfx9.swizzle) {
- /* for 4/8/16 high tiles */
- case DC_SW_LINEAR:
- input->src.macro_tile_size = dm_4k_tile;
- break;
- case DC_SW_4KB_S:
- case DC_SW_4KB_S_X:
- input->src.macro_tile_size = dm_4k_tile;
- break;
- case DC_SW_64KB_S:
- case DC_SW_64KB_S_X:
- case DC_SW_64KB_S_T:
- input->src.macro_tile_size = dm_64k_tile;
- break;
- case DC_SW_VAR_S:
- case DC_SW_VAR_S_X:
- input->src.macro_tile_size = dm_256k_tile;
- break;
-
- /* For 64bpp 2 high tiles */
- case DC_SW_4KB_D:
- case DC_SW_4KB_D_X:
- input->src.macro_tile_size = dm_4k_tile;
- break;
- case DC_SW_64KB_D:
- case DC_SW_64KB_D_X:
- case DC_SW_64KB_D_T:
- input->src.macro_tile_size = dm_64k_tile;
- break;
- case DC_SW_VAR_D:
- case DC_SW_VAR_D_X:
- input->src.macro_tile_size = dm_256k_tile;
- break;
-
- /* Unsupported swizzle modes for dcn */
- case DC_SW_256B_S:
- default:
- ASSERT(0); /* Not supported */
- break;
- }
+ input->src.macro_tile_size =
swizzle_mode_to_macro_tile_size(pipe->plane_state->tiling_info.gfx9.swizzle);
switch (pipe->plane_state->rotation) {
case ROTATION_ANGLE_0:
diff --git a/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h
b/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h
index ece954a40a8e..86ec3f69c765 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h
@@ -631,5 +631,7 @@ void dcn_bw_update_from_pplib(struct dc *dc);
void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc);
void dcn_bw_sync_calcs_and_dml(struct dc *dc);
+enum source_macro_tile_size swizzle_mode_to_macro_tile_size(enum
swizzle_mode_values sw_mode);
+
#endif /* __DCN_CALCS_H__ */
--
2.17.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 04/13] drm/amd/display: Pass init_data into DCN resource creation
From: Harry Wentland
[WHY]
The resource constructor currently needs num_virtual_links from
init_data but will need access to other items provided by DM.
[HOW]
Pass init_data into DCN create_resource_pool functions.
Change-Id: I3e250583c1a05c3ee9281fbbe59c42091b4f5ba3
Signed-off-by: Harry Wentland
Reviewed-by: Nicholas Kazlauskas
Acked-by: Bhawanpreet Lakha
Acked-by: Hersen Wu
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 6 +
.../gpu/drm/amd/display/dc/core/dc_resource.c | 26 +--
.../drm/amd/display/dc/dcn10/dcn10_resource.c | 4 +--
.../drm/amd/display/dc/dcn10/dcn10_resource.h | 2 +-
drivers/gpu/drm/amd/display/dc/inc/resource.h | 8 +++---
5 files changed, 19 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index cebd083df07a..365af56c4c7e 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -735,11 +735,7 @@ static bool construct(struct dc *dc,
goto fail;
}
- dc->res_pool = dc_create_resource_pool(
- dc,
- init_params->num_virtual_links,
- dc_version,
- init_params->asic_id);
+ dc->res_pool = dc_create_resource_pool(dc, init_params, dc_version);
if (!dc->res_pool)
goto fail;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 4a651d7dd052..42ef04230ea2 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -106,44 +106,43 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id
asic_id)
return dc_version;
}
-struct resource_pool *dc_create_resource_pool(
- struct dc *dc,
- int num_virtual_links,
- enum dce_version dc_version,
- struct hw_asic_id asic_id)
+struct resource_pool *dc_create_resource_pool(struct dc *dc,
+ const struct dc_init_data
*init_data,
+ enum dce_version dc_version)
{
struct resource_pool *res_pool = NULL;
switch (dc_version) {
case DCE_VERSION_8_0:
res_pool = dce80_create_resource_pool(
- num_virtual_links, dc);
+ init_data->num_virtual_links, dc);
break;
case DCE_VERSION_8_1:
res_pool = dce81_create_resource_pool(
- num_virtual_links, dc);
+ init_data->num_virtual_links, dc);
break;
case DCE_VERSION_8_3:
res_pool = dce83_create_resource_pool(
- num_virtual_links, dc);
+ init_data->num_virtual_links, dc);
break;
case DCE_VERSION_10_0:
res_pool = dce100_create_resource_pool(
- num_virtual_links, dc);
+ init_data->num_virtual_links, dc);
break;
case DCE_VERSION_11_0:
res_pool = dce110_create_resource_pool(
- num_virtual_links, dc, asic_id);
+ init_data->num_virtual_links, dc,
+ init_data->asic_id);
break;
case DCE_VERSION_11_2:
case DCE_VERSION_11_22:
res_pool = dce112_create_resource_pool(
- num_virtual_links, dc);
+ init_data->num_virtual_links, dc);
break;
case DCE_VERSION_12_0:
case DCE_VERSION_12_1:
res_pool = dce120_create_resource_pool(
- num_virtual_links, dc);
+ init_data->num_virtual_links, dc);
break;
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
@@ -151,8 +150,7 @@ struct resource_pool *dc_create_resource_pool(
#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
case DCN_VERSION_1_01:
#endif
- res_pool = dcn10_create_resource_pool(
- num_virtual_links, dc);
+ res_pool = dcn10_create_resource_pool(init_data, dc);
break;
#endif
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index 29f8893e44b6..7c37836bb9cc 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -1528,7 +1528,7 @@ static bool construct(
}
struct resource_pool *dcn10_create_resource_pool(
- uint8_t num_virtual_links,
+ const struct dc_init_data *init_data,
struct dc
[PATCH 01/13] drm/amd/display: add preferred pipe split logic
From: Jun Lei
[why]
existing logic finds "first free pipe from 5 -> 0" to split
this will cause certain sequences to require DC to move
an MPCC from one tree to another, which is unsupported
this leads to blackscreen
to mitigate this problem, we will always try to acquire the
"preferred" pipe, and each pipe has a unique preferred pipe
this means we avoid most of the scenarios where
pipe splitting leads to moving MPCC from one tree
to another
Change-Id: Ia6fc5a942cd9da243b824af80d889c0b015bb69f
Signed-off-by: Jun Lei
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 2 +-
.../gpu/drm/amd/display/dc/core/dc_resource.c | 54 +++
.../drm/amd/display/dc/dcn10/dcn10_resource.c | 2 +-
drivers/gpu/drm/amd/display/dc/inc/resource.h | 3 +-
4 files changed, 49 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index d2083e0b59a7..e572ac59b035 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -1141,7 +1141,7 @@ bool dcn_validate_bandwidth(
hsplit_pipe->pipe_dlg_param.vblank_end = pipe->pipe_dlg_param.vblank_end;
} else {
/* pipe not split previously
needs split */
- hsplit_pipe =
find_idle_secondary_pipe(>res_ctx, pool);
+ hsplit_pipe =
find_idle_secondary_pipe(>res_ctx, pool, pipe);
ASSERT(hsplit_pipe);
split_stream_across_pipes(
>res_ctx, pool,
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 374ce43096ac..4a651d7dd052 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -1038,24 +1038,60 @@ enum dc_status
resource_build_scaling_params_for_context(
struct pipe_ctx *find_idle_secondary_pipe(
struct resource_context *res_ctx,
- const struct resource_pool *pool)
+ const struct resource_pool *pool,
+ const struct pipe_ctx *primary_pipe)
{
int i;
struct pipe_ctx *secondary_pipe = NULL;
/*
-* search backwards for the second pipe to keep pipe
-* assignment more consistent
+* We add a preferred pipe mapping to avoid the chance that
+* MPCCs already in use will need to be reassigned to other trees.
+* For example, if we went with the strict, assign backwards logic:
+*
+* (State 1)
+* Display A on, no surface, top pipe = 0
+* Display B on, no surface, top pipe = 1
+*
+* (State 2)
+* Display A on, no surface, top pipe = 0
+* Display B on, surface enable, top pipe = 1, bottom pipe = 5
+*
+* (State 3)
+* Display A on, surface enable, top pipe = 0, bottom pipe = 5
+* Display B on, surface enable, top pipe = 1, bottom pipe = 4
+*
+* The state 2->3 transition requires remapping MPCC 5 from display B
+* to display A.
+*
+* However, with the preferred pipe logic, state 2 would look like:
+*
+* (State 2)
+* Display A on, no surface, top pipe = 0
+* Display B on, surface enable, top pipe = 1, bottom pipe = 4
+*
+* This would then cause 2->3 to not require remapping any MPCCs.
*/
-
- for (i = pool->pipe_count - 1; i >= 0; i--) {
- if (res_ctx->pipe_ctx[i].stream == NULL) {
- secondary_pipe = _ctx->pipe_ctx[i];
- secondary_pipe->pipe_idx = i;
- break;
+ if (primary_pipe) {
+ int preferred_pipe_idx = (pool->pipe_count - 1) -
primary_pipe->pipe_idx;
+ if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
+ secondary_pipe = _ctx->pipe_ctx[preferred_pipe_idx];
+ secondary_pipe->pipe_idx = preferred_pipe_idx;
}
}
+ /*
+* search backwards for the second pipe to keep pipe
+* assignment more consistent
+*/
+ if (!secondary_pipe)
+ for (i = pool->pipe_count - 1; i >= 0; i--) {
+ if (res_ctx->pipe_ctx[i].stream == NULL) {
+ secondary_pipe = _ctx->pipe_ctx[i];
+ secondary_pipe->pipe_idx = i;
+ break;
+ }
+ }
return secondary_pipe;
}
diff --git
[PATCH 05/13] drm/amd/display: Clean up old pplib interface functions
From: Fatemeh Darbehani
[Why]
set_display_requirement, dcn1_pplib_apply_display_requirements
are no longer used and should be removed.
Change-Id: Ie4d61d873d2f3ef2d5587fbc0b38079bdcf93ceb
Signed-off-by: Fatemeh Darbehani
Reviewed-by: Hersen Wu
Acked-by: Bhawanpreet Lakha
---
.../amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 25 ---
.../drm/amd/display/dc/dcn10/dcn10_clk_mgr.c | 17 -
.../drm/amd/display/dc/dcn10/dcn10_clk_mgr.h | 4 ---
drivers/gpu/drm/amd/display/dc/dm_pp_smu.h| 6 -
4 files changed, 52 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
index b902b0a89294..905b28198352 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
@@ -509,30 +509,6 @@ bool dm_pp_get_static_clocks(
return true;
}
-void pp_rv_set_display_requirement(struct pp_smu *pp,
- struct pp_smu_display_requirement_rv *req)
-{
- const struct dc_context *ctx = pp->dm;
- struct amdgpu_device *adev = ctx->driver_context;
- void *pp_handle = adev->powerplay.pp_handle;
- const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
- struct pp_display_clock_request clock = {0};
-
- clock.clock_type = amd_pp_dcf_clock;
- clock.clock_freq_in_khz = req->hard_min_dcefclk_mhz * 1000;
- if (pp_funcs && pp_funcs->display_clock_voltage_request)
- pp_funcs->display_clock_voltage_request(pp_handle, );
- else if (adev->smu.funcs &&
adev->smu.funcs->display_clock_voltage_request)
- smu_display_clock_voltage_request(>smu, );
-
- clock.clock_type = amd_pp_f_clock;
- clock.clock_freq_in_khz = req->hard_min_fclk_mhz * 1000;
- if (pp_funcs && pp_funcs->display_clock_voltage_request)
- pp_funcs->display_clock_voltage_request(pp_handle, );
- else if (adev->smu.funcs &&
adev->smu.funcs->display_clock_voltage_request)
- smu_display_clock_voltage_request(>smu, );
-}
-
void pp_rv_set_wm_ranges(struct pp_smu *pp,
struct pp_smu_wm_range_sets *ranges)
{
@@ -659,7 +635,6 @@ void dm_pp_get_funcs(
struct pp_smu_funcs *funcs)
{
funcs->rv_funcs.pp_smu.dm = ctx;
- funcs->rv_funcs.set_display_requirement = pp_rv_set_display_requirement;
funcs->rv_funcs.set_wm_ranges = pp_rv_set_wm_ranges;
funcs->rv_funcs.set_pme_wa_enable = pp_rv_set_pme_wa_enable;
funcs->rv_funcs.set_display_count = pp_rv_set_active_display_count;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_clk_mgr.c
index 072ecf9e52c2..0d9bee8d5ab9 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_clk_mgr.c
@@ -43,23 +43,6 @@
#define DC_LOGGER \
clk_mgr->ctx->logger
-void dcn1_pplib_apply_display_requirements(
- struct dc *dc,
- struct dc_state *context)
-{
- struct dm_pp_display_configuration *pp_display_cfg =
>pp_display_cfg;
-
- pp_display_cfg->min_engine_clock_khz =
dc->res_pool->clk_mgr->clks.dcfclk_khz;
- pp_display_cfg->min_memory_clock_khz =
dc->res_pool->clk_mgr->clks.fclk_khz;
- pp_display_cfg->min_engine_clock_deep_sleep_khz =
dc->res_pool->clk_mgr->clks.dcfclk_deep_sleep_khz;
- pp_display_cfg->min_dcfc_deep_sleep_clock_khz =
dc->res_pool->clk_mgr->clks.dcfclk_deep_sleep_khz;
- pp_display_cfg->min_dcfclock_khz =
dc->res_pool->clk_mgr->clks.dcfclk_khz;
- pp_display_cfg->disp_clk_khz = dc->res_pool->clk_mgr->clks.dispclk_khz;
- dce110_fill_display_configs(context, pp_display_cfg);
-
- dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
-}
-
static int dcn1_determine_dppclk_threshold(struct clk_mgr *clk_mgr, struct
dc_clocks *new_clocks)
{
bool request_dpp_div = new_clocks->dispclk_khz > new_clocks->dppclk_khz;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_clk_mgr.h
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_clk_mgr.h
index a995eda443a3..97007cf33665 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_clk_mgr.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_clk_mgr.h
@@ -34,10 +34,6 @@ struct clk_bypass {
uint32_t dprefclk_bypass;
};
-void dcn1_pplib_apply_display_requirements(
- struct dc *dc,
- struct dc_state *context);
-
struct clk_mgr *dcn1_clk_mgr_create(struct dc_context *ctx);
#endif //__DCN10_CLK_MGR_H__
diff --git a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
index 96c49a0df4a6..cc6891b8ea69 100644
--- a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
@@ -139,12 +139,6 @@ struct pp_smu_funcs_rv {
/* PME w/a */
void (*set_pme_wa_enable)(struct pp_smu *pp);
- /*
-
[PATCH 06/13] drm/amd/display: Create clock funcs
From: Eryk Brol
Create dccg_init and init_clocks for future use
Change-Id: If0fd1891eebc526d67c3108e74f3d739ba8dfdc4
Signed-off-by: Eryk Brol
Reviewed-by: Jun Lei
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | 2 ++
drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h| 1 +
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
index 23a4b18e5fee..31bd6d5183ab 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
@@ -42,6 +42,8 @@ struct clk_mgr_funcs {
bool safe_to_lower);
int (*get_dp_ref_clk_frequency)(struct clk_mgr *clk_mgr);
+
+ void (*init_clocks)(struct clk_mgr *clk_mgr);
};
#endif /* __DAL_CLK_MGR_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
index 0ae6bf60a53c..05ee5295d2c1 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
@@ -42,6 +42,7 @@ struct dccg_funcs {
void (*get_dccg_ref_freq)(struct dccg *dccg,
unsigned int xtalin_freq_inKhz,
unsigned int *dccg_ref_freq_inKhz);
+ void (*dccg_init)(struct dccg *dccg);
};
#endif //__DAL_DCCG_H__
--
2.17.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 07/13] drm/amd/display: Prevent cursor hotspot overflow for RV overlay planes
From: Nicholas Kazlauskas [Why] The actual position for the cursor on the screen is essentially: x_out = x - x_plane - x_hotspot y_out = y - y_plane - y_hotspot The register values for cursor position and cursor hotspot need to be greater than zero when programmed, but we also need to subtract off the plane position to display the cursor at the correct position. Since we don't want x or y to be less than zero, we add the plane position as a positive value to x_hotspot or y_hotspot. However, what this doesn't take into account is that the hotspot registers are limited by the maximum cursor size. On DCN10 the cursor hotspot regitsers are masked to 0xFF, so they have a maximum value of 0-255. Values greater this will wrap, causing the cursor to display in the wrong position. In practice this means that for sufficiently large plane positions, the cursor will be drawn twice on the screen, and can cause screen flashes or p-state WARNS depending on what the wrapped value is. So we need a way to remove the value from x_plane and y_plane without exceeding the maximum cursor size. [How] Subtract as much as x_plane/y_plane as possible from x and y and place the remainder in the cursor hotspot register. The value for x_hotspot and y_hotspot can still wrap around but it won't happen in a case where the cursor is actually enabled. The cursor plane needs to intersect at least one pixel of the plane's rectangle to be enabled, so the cursor position + hotspot provided by userspace must always be strictly less than the maximum cursor size for the cursor to actually be enabled. Change-Id: Ib1fe26aecaa10abad36547ab36a7d0246217c69b Signed-off-by: Nicholas Kazlauskas Reviewed-by: Sun peng Li Acked-by: Bhawanpreet Lakha --- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c| 12 +--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 3f2ff27ff86d..4969fa5e6f1d 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -2710,9 +2710,15 @@ static void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx) .rotation = pipe_ctx->plane_state->rotation, .mirror = pipe_ctx->plane_state->horizontal_mirror }; - - pos_cpy.x_hotspot += pipe_ctx->plane_state->dst_rect.x; - pos_cpy.y_hotspot += pipe_ctx->plane_state->dst_rect.y; + uint32_t x_plane = pipe_ctx->plane_state->dst_rect.x; + uint32_t y_plane = pipe_ctx->plane_state->dst_rect.y; + uint32_t x_offset = min(x_plane, pos_cpy.x); + uint32_t y_offset = min(y_plane, pos_cpy.y); + + pos_cpy.x -= x_offset; + pos_cpy.y -= y_offset; + pos_cpy.x_hotspot += (x_plane - x_offset); + pos_cpy.y_hotspot += (y_plane - y_offset); if (pipe_ctx->plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE) -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 08/13] drm/amd/display: Pass SDP spliting in parameters
From: Nikola Cornij
pass SDP splitting when setting stream attributes for future use
Change-Id: Ida059f1b6bacee097d8abd209aac6b509d27502b
Signed-off-by: Nikola Cornij
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 3 ++-
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c| 3 ++-
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c| 3 ++-
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h| 3 ++-
drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h | 3 ++-
.../gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c| 3 ++-
6 files changed, 12 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index ac128f7a9d85..f5ec65ec1460 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -2576,7 +2576,8 @@ void core_link_enable_stream(
pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(
pipe_ctx->stream_res.stream_enc,
>timing,
- stream->output_color_space);
+ stream->output_color_space,
+
stream->link->dpcd_caps.dprx_feature.bits.SST_SPLIT_SDP_CAP);
if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))
pipe_ctx->stream_res.stream_enc->funcs->hdmi_set_stream_attribute(
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
index 67cad0016f96..14309fe6f2e6 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
@@ -272,7 +272,8 @@ static void dce110_update_hdmi_info_packet(
static void dce110_stream_encoder_dp_set_stream_attribute(
struct stream_encoder *enc,
struct dc_crtc_timing *crtc_timing,
- enum dc_color_space output_color_space)
+ enum dc_color_space output_color_space,
+ uint32_t enable_sdp_splitting)
{
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
uint32_t h_active_start;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
index 6a0e748f0e57..8ee9f6dc1d62 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
@@ -245,7 +245,8 @@ static void enc1_update_hdmi_info_packet(
void enc1_stream_encoder_dp_set_stream_attribute(
struct stream_encoder *enc,
struct dc_crtc_timing *crtc_timing,
- enum dc_color_space output_color_space)
+ enum dc_color_space output_color_space,
+ uint32_t enable_sdp_splitting)
{
uint32_t h_active_start;
uint32_t v_active_start;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
index b7c800e10a32..e654c2f55971 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
@@ -462,7 +462,8 @@ void enc1_update_generic_info_packet(
void enc1_stream_encoder_dp_set_stream_attribute(
struct stream_encoder *enc,
struct dc_crtc_timing *crtc_timing,
- enum dc_color_space output_color_space);
+ enum dc_color_space output_color_space,
+ uint32_t enable_sdp_splitting);
void enc1_stream_encoder_hdmi_set_stream_attribute(
struct stream_encoder *enc,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
index ce3c4ecd9c24..49854eb73d1d 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
@@ -90,7 +90,8 @@ struct stream_encoder_funcs {
void (*dp_set_stream_attribute)(
struct stream_encoder *enc,
struct dc_crtc_timing *crtc_timing,
- enum dc_color_space output_color_space);
+ enum dc_color_space output_color_space,
+ uint32_t enable_sdp_splitting);
void (*hdmi_set_stream_attribute)(
struct stream_encoder *enc,
diff --git a/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c
b/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c
index 3dc1733eea20..fdcf9e66d852 100644
--- a/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c
@@ -29,7 +29,8 @@
static void virtual_stream_encoder_dp_set_stream_attribute(
struct stream_encoder *enc,
struct dc_crtc_timing *crtc_timing,
- enum dc_color_space output_color_space) {}
+ enum dc_color_space output_color_space,
+ uint32_t
[PATCH 4/4] drm/amd/display: Make pageflip event delivery compatible with VRR.
We want vblank counts and timestamps of flip completion as sent
in pageflip completion events to be consistent with the vblank
count and timestamp of the vblank of flip completion, like in non
VRR mode.
In VRR mode, drm_update_vblank_count() - and thereby vblank
count and timestamp updates - must be delayed until after the
end of front-porch of each vblank, as it is only safe to
calculate vblank timestamps outside of the front-porch, when
we actually know when the vblank will end or has ended.
The function drm_update_vblank_count() which updates timestamps
and counts gets called by drm_crtc_accurate_vblank_count() or by
drm_crtc_handle_vblank().
Therefore we must make sure that pageflip events for a completed
flip are only sent out after drm_crtc_accurate_vblank_count() or
drm_crtc_handle_vblank() is executed, after end of front-porch
for the vblank of flip completion.
Two cases:
a) Pageflip irq handler executes inside front-porch:
In this case we must defer sending pageflip events until
drm_crtc_handle_vblank() executes after end of front-porch,
and thereby calculates proper vblank count and timestamp.
Iow. the pflip irq handler must just arm a pageflip event
to be sent out by drm_crtc_handle_vblank() later on.
b) Pageflip irq handler executes after end of front-porch, e.g.,
after flip completion in back-porch or due to a massively
delayed handler invocation into the active scanout of the new
frame. In this case we can call drm_crtc_accurate_vblank_count()
to safely force calculation of a proper vblank count and
timestamp, and must send the pageflip completion event
ourselves from the pageflip irq handler.
This is the same behaviour as needed for standard fixed refresh
rate mode.
To decide from within pageflip handler if we are in case a) or b),
we check the current scanout position against the boundary of
front-porch. In non-VRR mode we just do what we did in the past.
Signed-off-by: Mario Kleiner
Reviewed-by: Nicholas Kazlauskas
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 68 +++
1 file changed, 55 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index fe207988d0b2..c20e9f695f11 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -263,6 +263,10 @@ static void dm_pflip_high_irq(void *interrupt_params)
struct common_irq_params *irq_params = interrupt_params;
struct amdgpu_device *adev = irq_params->adev;
unsigned long flags;
+ struct drm_pending_vblank_event *e;
+ struct dm_crtc_state *acrtc_state;
+ uint32_t vpos, hpos, v_blank_start, v_blank_end;
+ bool vrr_active;
amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src -
IRQ_TYPE_PFLIP);
@@ -285,18 +289,57 @@ static void dm_pflip_high_irq(void *interrupt_params)
return;
}
- /* Update to correct count(s) if racing with vblank irq */
- drm_crtc_accurate_vblank_count(_crtc->base);
+ /* page flip completed. */
+ e = amdgpu_crtc->event;
+ amdgpu_crtc->event = NULL;
- /* wake up userspace */
- if (amdgpu_crtc->event) {
- drm_crtc_send_vblank_event(_crtc->base,
amdgpu_crtc->event);
+ if (!e)
+ WARN_ON(1);
- /* page flip completed. clean up */
- amdgpu_crtc->event = NULL;
+ acrtc_state = to_dm_crtc_state(amdgpu_crtc->base.state);
+ vrr_active = amdgpu_dm_vrr_active(acrtc_state);
+
+ /* Fixed refresh rate, or VRR scanout position outside front-porch? */
+ if (!vrr_active ||
+ !dc_stream_get_scanoutpos(acrtc_state->stream, _blank_start,
+ _blank_end, , ) ||
+ (vpos < v_blank_start)) {
+ /* Update to correct count and vblank timestamp if racing with
+* vblank irq. This also updates to the correct vblank timestamp
+* even in VRR mode, as scanout is past the front-porch atm.
+*/
+ drm_crtc_accurate_vblank_count(_crtc->base);
- } else
- WARN_ON(1);
+ /* Wake up userspace by sending the pageflip event with proper
+* count and timestamp of vblank of flip completion.
+*/
+ if (e) {
+ drm_crtc_send_vblank_event(_crtc->base, e);
+
+ /* Event sent, so done with vblank for this flip */
+ drm_crtc_vblank_put(_crtc->base);
+ }
+ } else if (e) {
+ /* VRR active and inside front-porch: vblank count and
+* timestamp for pageflip event will only be up to date after
+* drm_crtc_handle_vblank() has been executed from late vblank
+* irq handler after start of
[PATCH 1/4] drm/amd/display: Prevent vblank irq disable while VRR is active. (v2)
During VRR mode we can not allow vblank irq dis-/enable
transitions, as an enable after a disable can happen at
an arbitrary time during the video refresh cycle, e.g.,
with a high likelyhood inside vblank front-porch. An
enable during front-porch would cause vblank timestamp
updates/calculations which are completely bogus, given
the code can't know when the vblank will end as long
as we are in front-porch with no page flip completed.
Hold a permanent vblank reference on the crtc while
in active VRR mode to prevent a vblank disable, and
drop the reference again when switching back to fixed
refresh rate non-VRR mode.
v2: Make sure transition is also handled if vrr is
disabled and stream gets disabled in the same
atomic commit. Suggested by Nicholas.
Signed-off-by: Mario Kleiner
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 36 +++
1 file changed, 36 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 42531ed6ae75..b73313d6450f 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -251,6 +251,12 @@ get_crtc_by_otg_inst(struct amdgpu_device *adev,
return NULL;
}
+static inline bool amdgpu_dm_vrr_active(struct dm_crtc_state *dm_state)
+{
+ return dm_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE ||
+ dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
+}
+
static void dm_pflip_high_irq(void *interrupt_params)
{
struct amdgpu_crtc *amdgpu_crtc;
@@ -4712,6 +4718,31 @@ static void update_freesync_state_on_stream(
(int)vrr_params.state);
}
+static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state,
+ struct dm_crtc_state *new_state)
+{
+ bool old_vrr_active = amdgpu_dm_vrr_active(old_state);
+ bool new_vrr_active = amdgpu_dm_vrr_active(new_state);
+
+ if (!old_vrr_active && new_vrr_active) {
+ /* Transition VRR inactive -> active:
+* While VRR is active, we must not disable vblank irq, as a
+* reenable after disable would compute bogus vblank/pflip
+* timestamps if it likely happened inside display front-porch.
+*/
+ drm_crtc_vblank_get(new_state->base.crtc);
+ DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n",
+__func__, new_state->base.crtc->base.id);
+ } else if (old_vrr_active && !new_vrr_active) {
+ /* Transition VRR active -> inactive:
+* Allow vblank irq disable again for fixed refresh rate.
+*/
+ drm_crtc_vblank_put(new_state->base.crtc);
+ DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n",
+__func__, new_state->base.crtc->base.id);
+ }
+}
+
static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
struct dc_state *dc_state,
struct drm_device *dev,
@@ -5246,6 +5277,11 @@ static void amdgpu_dm_atomic_commit_tail(struct
drm_atomic_state *state)
dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
+
+ /* Handle vrr on->off / off->on transitions */
+ amdgpu_dm_handle_vrr_transition(dm_old_crtc_state,
+ dm_new_crtc_state);
+
modeset_needed = modeset_required(
new_crtc_state,
dm_new_crtc_state->stream,
--
2.17.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
AMD Freesync patches v2
The current patch series, with feedback from Paul, Nicholas and Harry applied and r-b / acked-by tags added. Thanks for the feedback. Rebased to current drm-5.2-wip branch. Patch 1/4 is still the same though. Don't know if i or Nicholas could fix it in a followup patch, or this one needs more work directly, or who does what. Nicholas? thanks, -mario ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 3/4] drm/amd/display: In VRR mode, do DRM core vblank handling at end of vblank. (v2)
In VRR mode, proper vblank/pageflip timestamps can only be computed
after the display scanout position has left front-porch. Therefore
delay calls to drm_crtc_handle_vblank(), and thereby calls to
drm_update_vblank_count() and pageflip event delivery, to after the
end of front-porch when in VRR mode.
We add a new vupdate irq, which triggers at the end of the vupdate
interval, ie. at the end of vblank, and calls the core vblank handler
function. The new irq handler is not executed in standard non-VRR
mode, so vblank handling for fixed refresh rate mode is identical
to the past implementation.
v2: Implement feedback by Nicholas and Paul Menzel.
Signed-off-by: Mario Kleiner
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 128 +-
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 9 ++
.../drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c | 22 +++
.../dc/irq/dce110/irq_service_dce110.c| 7 +-
.../dc/irq/dce120/irq_service_dce120.c| 7 +-
.../display/dc/irq/dce80/irq_service_dce80.c | 6 +-
.../display/dc/irq/dcn10/irq_service_dcn10.c | 40 --
8 files changed, 204 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 6e71749cb3bb..6294316f24c7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -827,6 +827,7 @@ struct amdgpu_device {
/* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */
struct work_struct hotplug_work;
struct amdgpu_irq_src crtc_irq;
+ struct amdgpu_irq_src vupdate_irq;
struct amdgpu_irq_src pageflip_irq;
struct amdgpu_irq_src hpd_irq;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index aabd23fa0766..fe207988d0b2 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -315,6 +315,32 @@ static void dm_pflip_high_irq(void *interrupt_params)
drm_crtc_vblank_put(_crtc->base);
}
+static void dm_vupdate_high_irq(void *interrupt_params)
+{
+ struct common_irq_params *irq_params = interrupt_params;
+ struct amdgpu_device *adev = irq_params->adev;
+ struct amdgpu_crtc *acrtc;
+ struct dm_crtc_state *acrtc_state;
+
+ acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src -
IRQ_TYPE_VUPDATE);
+
+ if (acrtc) {
+ acrtc_state = to_dm_crtc_state(acrtc->base.state);
+
+ DRM_DEBUG_DRIVER("crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id,
+amdgpu_dm_vrr_active(acrtc_state));
+
+ /* Core vblank handling is done here after end of front-porch in
+* vrr mode, as vblank timestamping will give valid results
+* while now done after front-porch. This will also deliver
+* page-flip completion events that have been queued to us
+* if a pageflip happened inside front-porch.
+*/
+ if (amdgpu_dm_vrr_active(acrtc_state))
+ drm_crtc_handle_vblank(>base);
+ }
+}
+
static void dm_crtc_high_irq(void *interrupt_params)
{
struct common_irq_params *irq_params = interrupt_params;
@@ -325,11 +351,24 @@ static void dm_crtc_high_irq(void *interrupt_params)
acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src -
IRQ_TYPE_VBLANK);
if (acrtc) {
- drm_crtc_handle_vblank(>base);
- amdgpu_dm_crtc_handle_crc_irq(>base);
-
acrtc_state = to_dm_crtc_state(acrtc->base.state);
+ DRM_DEBUG_DRIVER("crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id,
+amdgpu_dm_vrr_active(acrtc_state));
+
+ /* Core vblank handling at start of front-porch is only possible
+* in non-vrr mode, as only there vblank timestamping will give
+* valid results while done in front-porch. Otherwise defer it
+* to dm_vupdate_high_irq after end of front-porch.
+*/
+ if (!amdgpu_dm_vrr_active(acrtc_state))
+ drm_crtc_handle_vblank(>base);
+
+ /* Following stuff must happen at start of vblank, for crc
+* computation and below-the-range btr support in vrr mode.
+*/
+ amdgpu_dm_crtc_handle_crc_irq(>base);
+
if (acrtc_state->stream &&
acrtc_state->vrr_params.supported &&
acrtc_state->freesync_config.state ==
VRR_STATE_ACTIVE_VARIABLE) {
@@ -1447,6 +1486,27 @@ static int dce110_register_irq_handlers(struct
amdgpu_device *adev)
dm_crtc_high_irq, c_irq_params);
}
+ /* Use VUPDATE
[PATCH 2/4] drm/amd/display: Rework vrr flip throttling for late vblank irq.
For throttling to work correctly, we always need a baseline vblank
count last_flip_vblank that increments at start of front-porch.
This is the case for drm_crtc_vblank_count() in non-VRR mode, where
the vblank irq fires at start of front-porch and triggers DRM core
vblank handling, but it is no longer the case in VRR mode, where
core vblank handling is done later, after end of front-porch.
Therefore drm_crtc_vblank_count() is no longer useful for this.
We also can't use drm_crtc_accurate_vblank_count(), as that would
screw up vblank timestamps in VRR mode when called in front-porch.
To solve this, use the cooked hardware vblank counter returned by
amdgpu_get_vblank_counter_kms() instead, as that one is cooked to
always increment at start of front-porch, independent of when
vblank related irq's fire.
This patch allows vblank irq handling to happen anywhere within
vblank of even after it, without a negative impact on flip
throttling, so followup patches can shift the vblank core
handling trigger point wherever they need it.
Signed-off-by: Mario Kleiner
Reviewed-by: Nicholas Kazlauskas
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 2 +-
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 23 +++
2 files changed, 14 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
index 889e4437..add238fe4b57 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
@@ -406,7 +406,7 @@ struct amdgpu_crtc {
struct amdgpu_flip_work *pflip_works;
enum amdgpu_flip_status pflip_status;
int deferred_flip_completion;
- u64 last_flip_vblank;
+ u32 last_flip_vblank;
/* pll sharing */
struct amdgpu_atom_ss ss;
bool ss_enabled;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index b73313d6450f..aabd23fa0766 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -286,7 +286,7 @@ static void dm_pflip_high_irq(void *interrupt_params)
}
/* Update to correct count(s) if racing with vblank irq */
- amdgpu_crtc->last_flip_vblank =
drm_crtc_accurate_vblank_count(_crtc->base);
+ drm_crtc_accurate_vblank_count(_crtc->base);
/* wake up userspace */
if (amdgpu_crtc->event) {
@@ -298,6 +298,14 @@ static void dm_pflip_high_irq(void *interrupt_params)
} else
WARN_ON(1);
+ /* Keep track of vblank of this flip for flip throttling. We use the
+* cooked hw counter, as that one incremented at start of this vblank
+* of pageflip completion, so last_flip_vblank is the forbidden count
+* for queueing new pageflips if vsync + VRR is enabled.
+*/
+ amdgpu_crtc->last_flip_vblank =
amdgpu_get_vblank_counter_kms(adev->ddev,
+ amdgpu_crtc->crtc_id);
+
amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
spin_unlock_irqrestore(>ddev->event_lock, flags);
@@ -4764,9 +4772,8 @@ static void amdgpu_dm_commit_planes(struct
drm_atomic_state *state,
unsigned long flags;
struct amdgpu_bo *abo;
uint64_t tiling_flags;
- uint32_t target, target_vblank;
- uint64_t last_flip_vblank;
- bool vrr_active = acrtc_state->freesync_config.state ==
VRR_STATE_ACTIVE_VARIABLE;
+ uint32_t target_vblank, last_flip_vblank;
+ bool vrr_active = amdgpu_dm_vrr_active(acrtc_state);
bool pflip_present = false;
struct {
@@ -4910,7 +4917,7 @@ static void amdgpu_dm_commit_planes(struct
drm_atomic_state *state,
* clients using the GLX_OML_sync_control extension or
* DRI3/Present extension with defined target_msc.
*/
- last_flip_vblank = drm_crtc_vblank_count(pcrtc);
+ last_flip_vblank =
amdgpu_get_vblank_counter_kms(dm->ddev, acrtc_attach->crtc_id);
}
else {
/* For variable refresh rate mode only:
@@ -4926,11 +4933,7 @@ static void amdgpu_dm_commit_planes(struct
drm_atomic_state *state,
spin_unlock_irqrestore(>dev->event_lock, flags);
}
- target = (uint32_t)last_flip_vblank + wait_for_vblank;
-
- /* Prepare wait for target vblank early - before the
fence-waits */
- target_vblank = target - (uint32_t)drm_crtc_vblank_count(pcrtc)
+
- amdgpu_get_vblank_counter_kms(pcrtc->dev,
acrtc_attach->crtc_id);
+ target_vblank = last_flip_vblank + wait_for_vblank;
/*
* Wait until we're out of the vertical blank period before the
one
--
2.17.1
[PATCH] drm/amdgpu: XGMI pstate switch initial support
Driver vote low to high pstate switch whenever there is an outstanding
XGMI mapping request. Driver vote high to low pstate when all the
outstanding XGMI mapping is terminated.
Change-Id: I197501f853c47f844055c0e28c0ac00a1ff06607
Signed-off-by: shaoyunl
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 2 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 21 +
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 4
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 16 +++-
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h | 10 ++
6 files changed, 56 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index ec9562d..c4c61e9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2018,6 +2018,10 @@ static void
amdgpu_device_ip_late_init_func_handler(struct work_struct *work)
r = amdgpu_device_enable_mgpu_fan_boost();
if (r)
DRM_ERROR("enable mgpu fan boost failed (%d).\n", r);
+
+ /*set to low pstate by default */
+ amdgpu_xgmi_set_pstate(adev, 0);
+
}
static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
index 220a6a7..c430e82 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
@@ -72,6 +72,8 @@ struct amdgpu_bo_va {
/* If the mappings are cleared or filled */
boolcleared;
+
+ boolis_xgmi;
};
struct amdgpu_bo {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 729da1c..a7247d5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -34,6 +34,7 @@
#include "amdgpu_trace.h"
#include "amdgpu_amdkfd.h"
#include "amdgpu_gmc.h"
+#include "amdgpu_xgmi.h"
/**
* DOC: GPUVM
@@ -2072,6 +2073,15 @@ struct amdgpu_bo_va *amdgpu_vm_bo_add(struct
amdgpu_device *adev,
INIT_LIST_HEAD(_va->valids);
INIT_LIST_HEAD(_va->invalids);
+ if (bo && amdgpu_xgmi_same_hive(adev, amdgpu_ttm_adev(bo->tbo.bdev))) {
+ bo_va->is_xgmi = true;
+ mutex_lock(>vm_manager.lock_pstate);
+ /* Power up XGMI if it can be potentially used */
+ if (++adev->vm_manager.xgmi_map_counter == 1)
+ amdgpu_xgmi_set_pstate(adev, 1);
+ mutex_unlock(>vm_manager.lock_pstate);
+ }
+
return bo_va;
}
@@ -2490,6 +2500,14 @@ void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
}
dma_fence_put(bo_va->last_pt_update);
+
+ if (bo && bo_va->is_xgmi) {
+ mutex_lock(>vm_manager.lock_pstate);
+ if (--adev->vm_manager.xgmi_map_counter == 0)
+ amdgpu_xgmi_set_pstate(adev, 0);
+ mutex_unlock(>vm_manager.lock_pstate);
+ }
+
kfree(bo_va);
}
@@ -2997,6 +3015,9 @@ void amdgpu_vm_manager_init(struct amdgpu_device *adev)
idr_init(>vm_manager.pasid_idr);
spin_lock_init(>vm_manager.pasid_lock);
+
+ adev->vm_manager.xgmi_map_counter = 0;
+ mutex_init(>vm_manager.lock_pstate);
}
/**
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 520122b..f586b38 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -324,6 +324,10 @@ struct amdgpu_vm_manager {
*/
struct idr pasid_idr;
spinlock_t pasid_lock;
+
+ /* counter of mapped memory through xgmi */
+ uint32_txgmi_map_counter;
+ struct mutexlock_pstate;
};
#define amdgpu_vm_copy_pte(adev, ib, pe, src, count)
((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
index fcc4b05..3368347 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
@@ -200,12 +200,26 @@ struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct
amdgpu_device *adev, int lo
if (lock)
mutex_lock(>hive_lock);
-
+ tmp->pstate = -1;
mutex_unlock(_mutex);
return tmp;
}
+int amdgpu_xgmi_set_pstate(struct amdgpu_device *adev, int pstate)
+{
+ int ret = 0;
+ struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev, 0);
+
+ if (!hive)
+ return 0;
+
+ if (hive->pstate == pstate)
+ return 0;
+ /* Todo : sent the message to SMU for pstate change */
+ return ret;
+}
+
int
[PATCH 1/2] drm/amd/powerplay: add ECC feature bit
It's OK to have this feature bit with old SMU firmwares.
But the feature should be disabled on them.
Change-Id: I6fb4869ef454ea7b6d01cf368b457be01eeb5058
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 10 +-
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h | 1 +
drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h | 3 ++-
3 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
index fac7a5df7c27..49be888fcd50 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
@@ -91,6 +91,12 @@ static void vega20_set_default_registry_data(struct pp_hwmgr
*hwmgr)
* MP0CLK DS
*/
data->registry_data.disallowed_features = 0xE0041C00;
+ /* ECC feature should be disabled on old SMUs */
+ smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetSmuVersion);
+ hwmgr->smu_version = smum_get_argument(hwmgr);
+ if (hwmgr->smu_version < 0x282100)
+ data->registry_data.disallowed_features |= FEATURE_ECC_MASK;
+
data->registry_data.od_state_in_dc_support = 0;
data->registry_data.thermal_support = 1;
data->registry_data.skip_baco_hardware = 0;
@@ -357,6 +363,7 @@ static void vega20_init_dpm_defaults(struct pp_hwmgr *hwmgr)
data->smu_features[GNLD_DS_MP1CLK].smu_feature_id =
FEATURE_DS_MP1CLK_BIT;
data->smu_features[GNLD_DS_MP0CLK].smu_feature_id =
FEATURE_DS_MP0CLK_BIT;
data->smu_features[GNLD_XGMI].smu_feature_id = FEATURE_XGMI_BIT;
+ data->smu_features[GNLD_ECC].smu_feature_id = FEATURE_ECC_BIT;
for (i = 0; i < GNLD_FEATURES_MAX; i++) {
data->smu_features[i].smu_feature_bitmap =
@@ -3048,7 +3055,8 @@ static int vega20_get_ppfeature_status(struct pp_hwmgr
*hwmgr, char *buf)
"FCLK_DS",
"MP1CLK_DS",
"MP0CLK_DS",
- "XGMI"};
+ "XGMI",
+ "ECC"};
static const char *output_title[] = {
"FEATURES",
"BITMASK",
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h
index a46cdeb7da70..c3890b5e076c 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h
@@ -81,6 +81,7 @@ enum {
GNLD_DS_MP1CLK,
GNLD_DS_MP0CLK,
GNLD_XGMI,
+ GNLD_ECC,
GNLD_FEATURES_MAX
};
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h
b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h
index 63d5cf691549..b90089a4fb6a 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h
@@ -99,7 +99,7 @@
#define FEATURE_DS_MP1CLK_BIT 30
#define FEATURE_DS_MP0CLK_BIT 31
#define FEATURE_XGMI_BIT32
-#define FEATURE_SPARE_33_BIT33
+#define FEATURE_ECC_BIT 33
#define FEATURE_SPARE_34_BIT34
#define FEATURE_SPARE_35_BIT35
#define FEATURE_SPARE_36_BIT36
@@ -166,6 +166,7 @@
#define FEATURE_DS_MP1CLK_MASK (1 << FEATURE_DS_MP1CLK_BIT )
#define FEATURE_DS_MP0CLK_MASK (1 << FEATURE_DS_MP0CLK_BIT )
#define FEATURE_XGMI_MASK (1 << FEATURE_XGMI_BIT )
+#define FEATURE_ECC_MASK(1ULL << FEATURE_ECC_BIT
)
#define DPM_OVERRIDE_DISABLE_SOCCLK_PID 0x0001
#define DPM_OVERRIDE_DISABLE_UCLK_PID 0x0002
--
2.21.0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 2/2] drm/amd/powerplay: correct data type to avoid overflow
Avoid left shift overflow. Change-Id: If03f4f4d440b6d742d8eaa23d0bae6ddd21c01ea Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h index b90089a4fb6a..195c4ae67058 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h +++ b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h @@ -165,7 +165,7 @@ #define FEATURE_DS_FCLK_MASK(1 << FEATURE_DS_FCLK_BIT) #define FEATURE_DS_MP1CLK_MASK (1 << FEATURE_DS_MP1CLK_BIT ) #define FEATURE_DS_MP0CLK_MASK (1 << FEATURE_DS_MP0CLK_BIT ) -#define FEATURE_XGMI_MASK (1 << FEATURE_XGMI_BIT ) +#define FEATURE_XGMI_MASK (1ULL << FEATURE_XGMI_BIT ) #define FEATURE_ECC_MASK(1ULL << FEATURE_ECC_BIT ) #define DPM_OVERRIDE_DISABLE_SOCCLK_PID 0x0001 -- 2.21.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH v13 18/20] tee/optee, arm64: untag user pointers in check_mem_type
On Wed, Mar 20, 2019 at 03:51:32PM +0100, Andrey Konovalov wrote: > This patch is a part of a series that extends arm64 kernel ABI to allow to > pass tagged user pointers (with the top byte set to something else other > than 0x00) as syscall arguments. > > check_mem_type() uses provided user pointers for vma lookups (via > __check_mem_type()), which can only by done with untagged pointers. > > Untag user pointers in this function. > > Signed-off-by: Andrey Konovalov > --- > drivers/tee/optee/call.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/tee/optee/call.c b/drivers/tee/optee/call.c > index a5afbe6dee68..e3be20264092 100644 > --- a/drivers/tee/optee/call.c > +++ b/drivers/tee/optee/call.c > @@ -563,6 +563,7 @@ static int check_mem_type(unsigned long start, size_t > num_pages) > int rc; > > down_read(>mmap_sem); > + start = untagged_addr(start); > rc = __check_mem_type(find_vma(mm, start), > start + num_pages * PAGE_SIZE); > up_read(>mmap_sem); I guess we could just untag this in tee_shm_register(). The tag is not relevant to a TEE implementation (firmware) anyway. -- Catalin ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH v13 10/20] kernel, arm64: untag user pointers in prctl_set_mm*
On Wed, Mar 20, 2019 at 03:51:24PM +0100, Andrey Konovalov wrote: > @@ -2120,13 +2135,14 @@ static int prctl_set_mm(int opt, unsigned long addr, > if (opt == PR_SET_MM_AUXV) > return prctl_set_auxv(mm, addr, arg4); > > - if (addr >= TASK_SIZE || addr < mmap_min_addr) > + if (untagged_addr(addr) >= TASK_SIZE || > + untagged_addr(addr) < mmap_min_addr) > return -EINVAL; > > error = -EINVAL; > > down_write(>mmap_sem); > - vma = find_vma(mm, addr); > + vma = find_vma(mm, untagged_addr(addr)); > > prctl_map.start_code= mm->start_code; > prctl_map.end_code = mm->end_code; Does this mean that we are left with tagged addresses for the mm->start_code etc. values? I really don't think we should allow this, I'm not sure what the implications are in other parts of the kernel. Arguably, these are not even pointer values but some address ranges. I know we decided to relax this notion for mmap/mprotect/madvise() since the user function prototypes take pointer as arguments but it feels like we are overdoing it here (struct prctl_mm_map doesn't even have pointers). What is the use-case for allowing tagged addresses here? Can user space handle untagging? -- Catalin ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH v13 13/20] bpf, arm64: untag user pointers in stack_map_get_build_id_offset
On Wed, Mar 20, 2019 at 03:51:27PM +0100, Andrey Konovalov wrote:
> This patch is a part of a series that extends arm64 kernel ABI to allow to
> pass tagged user pointers (with the top byte set to something else other
> than 0x00) as syscall arguments.
>
> stack_map_get_build_id_offset() uses provided user pointers for vma
> lookups, which can only by done with untagged pointers.
>
> Untag user pointers in this function for doing the lookup and
> calculating the offset, but save as is in the bpf_stack_build_id
> struct.
>
> Signed-off-by: Andrey Konovalov
> ---
> kernel/bpf/stackmap.c | 6 --
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/kernel/bpf/stackmap.c b/kernel/bpf/stackmap.c
> index 950ab2f28922..bb89341d3faf 100644
> --- a/kernel/bpf/stackmap.c
> +++ b/kernel/bpf/stackmap.c
> @@ -320,7 +320,9 @@ static void stack_map_get_build_id_offset(struct
> bpf_stack_build_id *id_offs,
> }
>
> for (i = 0; i < trace_nr; i++) {
> - vma = find_vma(current->mm, ips[i]);
> + u64 untagged_ip = untagged_addr(ips[i]);
> +
> + vma = find_vma(current->mm, untagged_ip);
> if (!vma || stack_map_get_build_id(vma, id_offs[i].build_id)) {
> /* per entry fall back to ips */
> id_offs[i].status = BPF_STACK_BUILD_ID_IP;
> @@ -328,7 +330,7 @@ static void stack_map_get_build_id_offset(struct
> bpf_stack_build_id *id_offs,
> memset(id_offs[i].build_id, 0, BPF_BUILD_ID_SIZE);
> continue;
> }
> - id_offs[i].offset = (vma->vm_pgoff << PAGE_SHIFT) + ips[i]
> + id_offs[i].offset = (vma->vm_pgoff << PAGE_SHIFT) + untagged_ip
> - vma->vm_start;
> id_offs[i].status = BPF_STACK_BUILD_ID_VALID;
> }
Can the ips[*] here ever be tagged?
--
Catalin
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH v13 15/20] drm/radeon, arm64: untag user pointers in radeon_ttm_tt_pin_userptr
On Wed, Mar 20, 2019 at 03:51:29PM +0100, Andrey Konovalov wrote:
> This patch is a part of a series that extends arm64 kernel ABI to allow to
> pass tagged user pointers (with the top byte set to something else other
> than 0x00) as syscall arguments.
>
> radeon_ttm_tt_pin_userptr() uses provided user pointers for vma
> lookups, which can only by done with untagged pointers.
>
> Untag user pointers in this function.
>
> Signed-off-by: Andrey Konovalov
> ---
> drivers/gpu/drm/radeon/radeon_ttm.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c
> b/drivers/gpu/drm/radeon/radeon_ttm.c
> index 9920a6fc11bf..872a98796117 100644
> --- a/drivers/gpu/drm/radeon/radeon_ttm.c
> +++ b/drivers/gpu/drm/radeon/radeon_ttm.c
> @@ -497,9 +497,10 @@ static int radeon_ttm_tt_pin_userptr(struct ttm_tt *ttm)
> if (gtt->userflags & RADEON_GEM_USERPTR_ANONONLY) {
> /* check that we only pin down anonymous memory
> to prevent problems with writeback */
> - unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE;
> + unsigned long userptr = untagged_addr(gtt->userptr);
> + unsigned long end = userptr + ttm->num_pages * PAGE_SIZE;
> struct vm_area_struct *vma;
> - vma = find_vma(gtt->usermm, gtt->userptr);
> + vma = find_vma(gtt->usermm, userptr);
> if (!vma || vma->vm_file || vma->vm_end < end)
> return -EPERM;
> }
Same comment as on the previous patch.
--
Catalin
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH v13 11/20] tracing, arm64: untag user pointers in seq_print_user_ip
On Wed, Mar 20, 2019 at 03:51:25PM +0100, Andrey Konovalov wrote:
> This patch is a part of a series that extends arm64 kernel ABI to allow to
> pass tagged user pointers (with the top byte set to something else other
> than 0x00) as syscall arguments.
>
> seq_print_user_ip() uses provided user pointers for vma lookups, which
> can only by done with untagged pointers.
>
> Untag user pointers in this function.
>
> Signed-off-by: Andrey Konovalov
> ---
> kernel/trace/trace_output.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/kernel/trace/trace_output.c b/kernel/trace/trace_output.c
> index 54373d93e251..6376bee93c84 100644
> --- a/kernel/trace/trace_output.c
> +++ b/kernel/trace/trace_output.c
> @@ -370,6 +370,7 @@ static int seq_print_user_ip(struct trace_seq *s, struct
> mm_struct *mm,
> {
> struct file *file = NULL;
> unsigned long vmstart = 0;
> + unsigned long untagged_ip = untagged_addr(ip);
> int ret = 1;
>
> if (s->full)
> @@ -379,7 +380,7 @@ static int seq_print_user_ip(struct trace_seq *s, struct
> mm_struct *mm,
> const struct vm_area_struct *vma;
>
> down_read(>mmap_sem);
> - vma = find_vma(mm, ip);
> + vma = find_vma(mm, untagged_ip);
> if (vma) {
> file = vma->vm_file;
> vmstart = vma->vm_start;
> @@ -388,7 +389,7 @@ static int seq_print_user_ip(struct trace_seq *s, struct
> mm_struct *mm,
> ret = trace_seq_path(s, >f_path);
> if (ret)
> trace_seq_printf(s, "[+0x%lx]",
> - ip - vmstart);
> + untagged_ip - vmstart);
> }
> up_read(>mmap_sem);
> }
How would we end up with a tagged address here? Does "ip" here imply
instruction pointer, which we wouldn't tag?
--
Catalin
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH v13 17/20] media/v4l2-core, arm64: untag user pointers in videobuf_dma_contig_user_get
On Wed, Mar 20, 2019 at 03:51:31PM +0100, Andrey Konovalov wrote:
> This patch is a part of a series that extends arm64 kernel ABI to allow to
> pass tagged user pointers (with the top byte set to something else other
> than 0x00) as syscall arguments.
>
> videobuf_dma_contig_user_get() uses provided user pointers for vma
> lookups, which can only by done with untagged pointers.
>
> Untag the pointers in this function.
>
> Signed-off-by: Andrey Konovalov
> ---
> drivers/media/v4l2-core/videobuf-dma-contig.c | 9 +
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/media/v4l2-core/videobuf-dma-contig.c
> b/drivers/media/v4l2-core/videobuf-dma-contig.c
> index e1bf50df4c70..8a1ddd146b17 100644
> --- a/drivers/media/v4l2-core/videobuf-dma-contig.c
> +++ b/drivers/media/v4l2-core/videobuf-dma-contig.c
> @@ -160,6 +160,7 @@ static void videobuf_dma_contig_user_put(struct
> videobuf_dma_contig_memory *mem)
> static int videobuf_dma_contig_user_get(struct videobuf_dma_contig_memory
> *mem,
> struct videobuf_buffer *vb)
> {
> + unsigned long untagged_baddr = untagged_addr(vb->baddr);
> struct mm_struct *mm = current->mm;
> struct vm_area_struct *vma;
> unsigned long prev_pfn, this_pfn;
> @@ -167,22 +168,22 @@ static int videobuf_dma_contig_user_get(struct
> videobuf_dma_contig_memory *mem,
> unsigned int offset;
> int ret;
>
> - offset = vb->baddr & ~PAGE_MASK;
> + offset = untagged_baddr & ~PAGE_MASK;
> mem->size = PAGE_ALIGN(vb->size + offset);
> ret = -EINVAL;
>
> down_read(>mmap_sem);
>
> - vma = find_vma(mm, vb->baddr);
> + vma = find_vma(mm, untagged_baddr);
> if (!vma)
> goto out_up;
>
> - if ((vb->baddr + mem->size) > vma->vm_end)
> + if ((untagged_baddr + mem->size) > vma->vm_end)
> goto out_up;
>
> pages_done = 0;
> prev_pfn = 0; /* kill warning */
> - user_address = vb->baddr;
> + user_address = untagged_baddr;
>
> while (pages_done < (mem->size >> PAGE_SHIFT)) {
> ret = follow_pfn(vma, user_address, _pfn);
I don't think vb->baddr here is anonymous mmap() but worth checking the
call paths.
--
Catalin
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Kernel panic while “ modprobe amdkfd ; modprobe -r amdkfd ; 4.14.35 kernel
Hello , I am investigating a issue reported by a test group concerning this driver. Their test loads and unloads every kernel module included in the 4.14.35 kernel release . You don’t even need a AMD platform . It occurs on any Intel, or a KVM VM instance too. Kernel panic while “ modprobe amdkfd ; modprobe -r amdkfd “ [ 329.425334] ? __slab_free+0x9b/0x2ba [ 329.427836] ? process_slab+0x3c1/0x45c [ 329.430336] dev_printk_emit+0x4e/0x65 [ 329.432829] __dev_printk+0x46/0x8b [ 329.435183] _dev_info+0x6c/0x85 [ 329.437435] ? kfree+0x141/0x182 [ 329.439646] kfd_module_exit+0x37/0x39 [amdkfd] [ 329.442258] SyS_delete_module+0x1c3/0x26f [ 329.444722] ? entry_SYSCALL_64_after_hwframe+0xaa/0x0 [ 329.447479] ? entry_SYSCALL_64_after_hwframe+0xa3/0x0 [ 329.450206] ? entry_SYSCALL_64_after_hwframe+0x9c/0x0 [ 329.452912] ? entry_SYSCALL_64_after_hwframe+0x95/0x0 [ 329.455586] do_syscall_64+0x79/0x1ae [ 329.457766] entry_SYSCALL_64_after_hwframe+0x151/0x0 [ 329.460369] RIP: 0033:0x7f1757a1b457 [ 329.462502] RSP: 002b:7ffd62ce1f48 EFLAGS: 0206 ORIG_RAX: Sometimes the unload works but the message logged is garbage: [root@jpd-vmbase02 ~]# modprobe -r amdkfd [ 144.449981] hn??蟟??xn??ן??kfd: Removed module Is this something one of team members could have possibly corrected in an upstream version ? #define KFD_DRIVER_DESC "Standalone HSA driver for AMD's GPUs" #define KFD_DRIVER_DATE "20150421" #define KFD_DRIVER_MAJOR0 #define KFD_DRIVER_MINOR7 #define KFD_DRIVER_PATCHLEVEL 2 Any advise welcome. Thank you, John ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH v13 12/20] uprobes, arm64: untag user pointers in find_active_uprobe
On Wed, Mar 20, 2019 at 03:51:26PM +0100, Andrey Konovalov wrote:
> This patch is a part of a series that extends arm64 kernel ABI to allow to
> pass tagged user pointers (with the top byte set to something else other
> than 0x00) as syscall arguments.
>
> find_active_uprobe() uses user pointers (obtained via
> instruction_pointer(regs)) for vma lookups, which can only by done with
> untagged pointers.
>
> Untag user pointers in this function.
>
> Signed-off-by: Andrey Konovalov
> ---
> kernel/events/uprobes.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/kernel/events/uprobes.c b/kernel/events/uprobes.c
> index c5cde87329c7..d3a2716a813a 100644
> --- a/kernel/events/uprobes.c
> +++ b/kernel/events/uprobes.c
> @@ -1992,6 +1992,8 @@ static struct uprobe *find_active_uprobe(unsigned long
> bp_vaddr, int *is_swbp)
> struct uprobe *uprobe = NULL;
> struct vm_area_struct *vma;
>
> + bp_vaddr = untagged_addr(bp_vaddr);
> +
> down_read(>mmap_sem);
> vma = find_vma(mm, bp_vaddr);
> if (vma && vma->vm_start <= bp_vaddr) {
Similarly here, that's a breakpoint address, hence instruction pointer
(PC) which is untagged.
--
Catalin
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu: XGMI pstate switch initial support
Am 20.03.19 um 21:21 schrieb Liu, Shaoyun:
Driver vote low to high pstate switch whenever there is an outstanding
XGMI mapping request. Driver vote high to low pstate when all the
outstanding XGMI mapping is terminated.
Only a few style nit picks, but apart from that reviewed-by: Christian
König
Change-Id: I197501f853c47f844055c0e28c0ac00a1ff06607
Signed-off-by: shaoyunl
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 5 +
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 +
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 2 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 26 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 16 +++-
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h | 2 ++
6 files changed, 55 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 1db1921..c9c24d6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -932,6 +932,11 @@ struct amdgpu_device {
struct work_struct xgmi_reset_work;
boolin_baco_reset;
+
+ /* counter of mapped memory through xgmi */
+ atomic_txgmi_map_counter;
This doesn't need to be an atomic any more when you protect it with a
mutex anyway.
+ struct mutexlock_pstate;
Better put both fields that into the VM manager structure.
+
};
static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 2065837..a5af885 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2018,6 +2018,10 @@ static void
amdgpu_device_ip_late_init_func_handler(struct work_struct *work)
r = amdgpu_device_enable_mgpu_fan_boost();
if (r)
DRM_ERROR("enable mgpu fan boost failed (%d).\n", r);
+
+ /*set to low pstate by default */
+ amdgpu_xgmi_set_pstate(adev, 0);
+
}
static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work)
@@ -2467,6 +2471,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
mutex_init(>virt.vf_errors.lock);
hash_init(adev->mn_hash);
mutex_init(>lock_reset);
+ mutex_init(>lock_pstate);
amdgpu_device_check_arguments(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
index 220a6a7..c430e82 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
@@ -72,6 +72,8 @@ struct amdgpu_bo_va {
/* If the mappings are cleared or filled */
boolcleared;
+
+ boolis_xgmi;
};
struct amdgpu_bo {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index c8f0e4c..3639cf6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -34,6 +34,7 @@
#include "amdgpu_trace.h"
#include "amdgpu_amdkfd.h"
#include "amdgpu_gmc.h"
+#include "amdgpu_xgmi.h"
/**
* DOC: GPUVM
@@ -2352,6 +2353,14 @@ int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
return 0;
}
+static bool amdgpu_xgmi_same_hive(struct amdgpu_device *adev,
+ struct amdgpu_device *bo_adev)
+{
+ return (adev != bo_adev &&
+ adev->gmc.xgmi.hive_id &&
+ adev->gmc.xgmi.hive_id == bo_adev->gmc.xgmi.hive_id);
+}
Maybe put that into amdgpu_xgmi.h, could be useful in other cases as well.
Regards,
Christian.
+
/**
* amdgpu_vm_bo_add - add a bo to a specific vm
*
@@ -2383,6 +2392,15 @@ struct amdgpu_bo_va *amdgpu_vm_bo_add(struct
amdgpu_device *adev,
INIT_LIST_HEAD(_va->valids);
INIT_LIST_HEAD(_va->invalids);
+ if (amdgpu_xgmi_same_hive(adev, amdgpu_ttm_adev(bo->tbo.bdev))) {
+ bo_va->is_xgmi = true;
+ mutex_lock(>lock_pstate);
+ /* Power up XGMI if it can be potentially used */
+ if (atomic_inc_return(>xgmi_map_counter) == 1)
+ amdgpu_xgmi_set_pstate(adev, 1);
+ mutex_unlock(>lock_pstate);
+ }
+
return bo_va;
}
@@ -2801,6 +2819,14 @@ void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
}
dma_fence_put(bo_va->last_pt_update);
+
+ if (bo_va->is_xgmi) {
+ mutex_lock(>lock_pstate);
+ if (atomic_dec_return(>xgmi_map_counter) == 0)
+ amdgpu_xgmi_set_pstate(adev, 0);
+ mutex_unlock(>lock_pstate);
+ }
+
kfree(bo_va);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
index fcc4b05..3368347 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
+++
Re: [PATCH 1/9] dma-buf: add new dma_fence_chain container v6
Yeah, that should work.
Christian.
Am 22.03.19 um 08:34 schrieb zhoucm1:
how about the attached?
If ok, I will merge to pathc#1.
-David
On 2019年03月21日 22:40, Christian König wrote:
No, atomic cmpxchg is a hardware operation. If you want to replace
that you need a lock again.
Maybe just add a comment and use an explicit cast to void* ? Not sure
if that silences the warning.
Christian.
Am 21.03.19 um 15:13 schrieb Zhou, David(ChunMing):
cmpxchg be replaced by some simple c sentance?
otherwise we have to remove __rcu of chian->prev.
-David
Original Message
Subject: Re: [PATCH 1/9] dma-buf: add new dma_fence_chain container v6
From: Christian König
To: "Zhou, David(ChunMing)" ,kbuild test robot ,"Zhou, David(ChunMing)"
CC:
kbuild-...@01.org,dri-de...@lists.freedesktop.org,amd-gfx@lists.freedesktop.org,lionel.g.landwer...@intel.com,ja...@jlekstrand.net,"Koenig,
Christian" ,"Hector, Tobias"
Hi David,
For the cmpxchg() case I of hand don't know either. Looks like so far
nobody has used cmpxchg() with rcu protected structures.
The other cases should be replaced by RCU_INIT_POINTER() or
rcu_dereference_protected(.., true);
Regards,
Christian.
Am 21.03.19 um 07:34 schrieb zhoucm1:
> Hi Lionel and Christian,
>
> Below is robot report for chain->prev, which was added __rcu as you
> suggested.
>
> How to fix this line "tmp = cmpxchg(>prev, prev,
replacement); "?
> I checked kernel header file, seems it has no cmpxchg for rcu.
>
> Any suggestion to fix this robot report?
>
> Thanks,
> -David
>
> On 2019年03月21日 08:24, kbuild test robot wrote:
>> Hi Chunming,
>>
>> I love your patch! Perhaps something to improve:
>>
>> [auto build test WARNING on linus/master]
>> [also build test WARNING on v5.1-rc1 next-20190320]
>> [if your patch is applied to the wrong git tree, please drop us a
>> note to help improve the system]
>>
>> url:
>>
https://github.com/0day-ci/linux/commits/Chunming-Zhou/dma-buf-add-new-dma_fence_chain-container-v6/20190320-223607
>> reproduce:
>> # apt-get install sparse
>> make ARCH=x86_64 allmodconfig
>> make C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__'
>>
>>
>> sparse warnings: (new ones prefixed by >>)
>>
drivers/dma-buf/dma-fence-chain.c:73:23: sparse: incorrect type in
initializer (different address spaces) @@ expected struct
dma_fence [noderef] *__old @@ got dma_fence [noderef]
*__old @@
>> drivers/dma-buf/dma-fence-chain.c:73:23: expected struct
>> dma_fence [noderef] *__old
>> drivers/dma-buf/dma-fence-chain.c:73:23: got struct dma_fence
>> *[assigned] prev
drivers/dma-buf/dma-fence-chain.c:73:23: sparse: incorrect type in
initializer (different address spaces) @@ expected struct
dma_fence [noderef] *__new @@ got dma_fence [noderef]
*__new @@
>> drivers/dma-buf/dma-fence-chain.c:73:23: expected struct
>> dma_fence [noderef] *__new
>> drivers/dma-buf/dma-fence-chain.c:73:23: got struct dma_fence
>> *[assigned] replacement
drivers/dma-buf/dma-fence-chain.c:73:21: sparse: incorrect type in
assignment (different address spaces) @@ expected struct
dma_fence *tmp @@ got struct dma_fence [noderef] >>> dma_fence *tmp @@
>> drivers/dma-buf/dma-fence-chain.c:73:21: expected struct
>> dma_fence *tmp
>> drivers/dma-buf/dma-fence-chain.c:73:21: got struct dma_fence
>> [noderef] *[assigned] __ret
drivers/dma-buf/dma-fence-chain.c:190:28: sparse: incorrect
type in
argument 1 (different address spaces) @@ expected struct
dma_fence *fence @@ got struct dma_fence struct dma_fence
*fence @@
>> drivers/dma-buf/dma-fence-chain.c:190:28: expected struct
>> dma_fence *fence
>> drivers/dma-buf/dma-fence-chain.c:190:28: got struct dma_fence
>> [noderef] *prev
drivers/dma-buf/dma-fence-chain.c:222:21: sparse: incorrect
type in
assignment (different address spaces) @@ expected struct
dma_fence [noderef] *prev @@ got [noderef]
*prev @@
>> drivers/dma-buf/dma-fence-chain.c:222:21: expected struct
>> dma_fence [noderef] *prev
>> drivers/dma-buf/dma-fence-chain.c:222:21: got struct dma_fence
>> *prev
>> drivers/dma-buf/dma-fence-chain.c:235:33: sparse: expression
>> using sizeof(void)
>> drivers/dma-buf/dma-fence-chain.c:235:33: sparse: expression
>> using sizeof(void)
>>
>> vim +73 drivers/dma-buf/dma-fence-chain.c
>>
>> 38
>> 39 /**
>> 40 * dma_fence_chain_walk - chain walking function
>> 41 * @fence: current chain node
>> 42 *
>> 43 * Walk the chain to the next node. Returns the next
fence
>> or NULL if we are at
>> 44 * the end of the chain. Garbage collects chain nodes
>> which are already
>> 45 * signaled.
>> 46 */
>> 47 struct dma_fence *dma_fence_chain_walk(struct dma_fence
>> *fence)
>> 48 {
>> 49 struct dma_fence_chain *chain, *prev_chain;
>> 50 struct
Re: [PATCH] drm/amdgpu: fix vm_cpu_update hit NULL pointer
Am 22.03.19 um 06:30 schrieb Monk Liu:
should use amdgpu_bo_map, otherwise you'll hit NULL
pointer bug if with amdgpu_bo_kptr
Yeah that is a known problem. NAK to this one cause that would map the
BO at the wrong time.
But in general I have a proper fix for this in the pipeline.
Christian.
Signed-off-by: Monk Liu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c
index 9d53982..1fb6295a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c
@@ -76,8 +76,10 @@ static int amdgpu_vm_cpu_update(struct
amdgpu_vm_update_params *p,
{
unsigned int i;
uint64_t value;
+ void *ptr;
- pe += (unsigned long)amdgpu_bo_kptr(bo);
+ amdgpu_bo_kmap(bo, );
+ pe += (unsigned long)ptr;
trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags);
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: Radeon HD 7450 brightness oversaturated
Kernels are 5.0 and 5.1-rc1. Is it just kernels 5.0 and 5.1? There haven't really been any display related changes to radeon in ages. Possibly a duplicate of: https://bugzilla.kernel.org/show_bug.cgi?id=198123 No, I just put the card in and tested with only the current kernels I had. I can get some older kernel and test with that if that is of any help. Just tested Debianis 4.19.0-4 package (4.19.28) and it exhibits the same symptoms. Slight additional detail: chenaging between fbcon vt-s does not fix it, only changing between fbcon and X fixes it. -- Meelis Roos ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH] drm/amdgpu: XGMI pstate switch initial support
ping
-Original Message-
From: Liu, Shaoyun
Sent: Wednesday, March 20, 2019 4:22 PM
To: amd-gfx@lists.freedesktop.org
Cc: Liu, Shaoyun
Subject: [PATCH] drm/amdgpu: XGMI pstate switch initial support
Driver vote low to high pstate switch whenever there is an outstanding XGMI
mapping request. Driver vote high to low pstate when all the outstanding XGMI
mapping is terminated.
Change-Id: I197501f853c47f844055c0e28c0ac00a1ff06607
Signed-off-by: shaoyunl
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 5 +
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 +
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 2 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 26 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 16 +++-
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h | 2 ++
6 files changed, 55 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 1db1921..c9c24d6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -932,6 +932,11 @@ struct amdgpu_device {
struct work_struct xgmi_reset_work;
boolin_baco_reset;
+
+ /* counter of mapped memory through xgmi */
+ atomic_txgmi_map_counter;
+ struct mutexlock_pstate;
+
};
static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device
*bdev) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 2065837..a5af885 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2018,6 +2018,10 @@ static void
amdgpu_device_ip_late_init_func_handler(struct work_struct *work)
r = amdgpu_device_enable_mgpu_fan_boost();
if (r)
DRM_ERROR("enable mgpu fan boost failed (%d).\n", r);
+
+ /*set to low pstate by default */
+ amdgpu_xgmi_set_pstate(adev, 0);
+
}
static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work) @@
-2467,6 +2471,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
mutex_init(>virt.vf_errors.lock);
hash_init(adev->mn_hash);
mutex_init(>lock_reset);
+ mutex_init(>lock_pstate);
amdgpu_device_check_arguments(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
index 220a6a7..c430e82 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
@@ -72,6 +72,8 @@ struct amdgpu_bo_va {
/* If the mappings are cleared or filled */
boolcleared;
+
+ boolis_xgmi;
};
struct amdgpu_bo {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index c8f0e4c..3639cf6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -34,6 +34,7 @@
#include "amdgpu_trace.h"
#include "amdgpu_amdkfd.h"
#include "amdgpu_gmc.h"
+#include "amdgpu_xgmi.h"
/**
* DOC: GPUVM
@@ -2352,6 +2353,14 @@ int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
return 0;
}
+static bool amdgpu_xgmi_same_hive(struct amdgpu_device *adev,
+ struct amdgpu_device *bo_adev)
+{
+ return (adev != bo_adev &&
+ adev->gmc.xgmi.hive_id &&
+ adev->gmc.xgmi.hive_id == bo_adev->gmc.xgmi.hive_id); }
+
/**
* amdgpu_vm_bo_add - add a bo to a specific vm
*
@@ -2383,6 +2392,15 @@ struct amdgpu_bo_va *amdgpu_vm_bo_add(struct
amdgpu_device *adev,
INIT_LIST_HEAD(_va->valids);
INIT_LIST_HEAD(_va->invalids);
+ if (amdgpu_xgmi_same_hive(adev, amdgpu_ttm_adev(bo->tbo.bdev))) {
+ bo_va->is_xgmi = true;
+ mutex_lock(>lock_pstate);
+ /* Power up XGMI if it can be potentially used */
+ if (atomic_inc_return(>xgmi_map_counter) == 1)
+ amdgpu_xgmi_set_pstate(adev, 1);
+ mutex_unlock(>lock_pstate);
+ }
+
return bo_va;
}
@@ -2801,6 +2819,14 @@ void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
}
dma_fence_put(bo_va->last_pt_update);
+
+ if (bo_va->is_xgmi) {
+ mutex_lock(>lock_pstate);
+ if (atomic_dec_return(>xgmi_map_counter) == 0)
+ amdgpu_xgmi_set_pstate(adev, 0);
+ mutex_unlock(>lock_pstate);
+ }
+
kfree(bo_va);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
index fcc4b05..3368347 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
@@ -200,12 +200,26 @@ struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct
amdgpu_device *adev, int lo
if (lock)
[PATCH v2] drm/amd/display: Add debugfs entry for amdgpu_dm_visual_confirm
[Why]
DC provides a few visual confirmation debug options that can be
dynamically changed at runtime to help debug surface programming issues
but we don't have any way to access it from userspace.
[How]
Add the amdgpu_dm_visual_confirm debugfs entry.
It accepts a string containing the DC visual confirm enum value using
the debugfs attribute helpers.
The debugfs_create_file_unsafe can be used instead of
debugfs_create_file as per the documentation.
v2: Use debugfs helpers for getting and setting the value (Christian)
Cc: Leo Li
Cc: Harry Wentland
Signed-off-by: Nicholas Kazlauskas
---
.../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 39 ++-
1 file changed, 38 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index 1a9e3d3dfa38..1d5fc5ad3bee 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -995,6 +995,35 @@ static const struct drm_info_list amdgpu_dm_debugfs_list[]
= {
{"amdgpu_target_backlight_pwm", _backlight_read},
};
+/*
+ * Sets the DC visual confirm debug option from the given string.
+ * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_visual_confirm
+ */
+static int visual_confirm_set(void *data, u64 val)
+{
+ struct amdgpu_device *adev = data;
+
+ adev->dm.dc->debug.visual_confirm = (enum visual_confirm)val;
+
+ return 0;
+}
+
+/*
+ * Reads the DC visual confirm debug option value into the given buffer.
+ * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_visual_confirm
+ */
+static int visual_confirm_get(void *data, u64 *val)
+{
+ struct amdgpu_device *adev = data;
+
+ *val = adev->dm.dc->debug.visual_confirm;
+
+ return 0;
+}
+
+DEFINE_DEBUGFS_ATTRIBUTE(visual_confirm_fops, visual_confirm_get,
+visual_confirm_set, "%llu\n");
+
int dtn_debugfs_init(struct amdgpu_device *adev)
{
static const struct file_operations dtn_log_fops = {
@@ -1020,5 +1049,13 @@ int dtn_debugfs_init(struct amdgpu_device *adev)
adev,
_log_fops);
- return PTR_ERR_OR_ZERO(ent);
+ if (IS_ERR(ent))
+ return PTR_ERR(ent);
+
+ ent = debugfs_create_file_unsafe("amdgpu_dm_visual_confirm", 0644, root,
+adev, _confirm_fops);
+ if (IS_ERR(ent))
+ return PTR_ERR(ent);
+
+ return 0;
}
--
2.17.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH v2] drm/amd/display: Initialize stream_update with memset
The brace initialization used here generates warnings on some
compilers. For example, on GCC 4.9:
[...] In function ‘dm_determine_update_type_for_commit’:
[...] error: missing braces around initializer [-Werror=missing-braces]
struct dc_stream_update stream_update = { 0 };
^
Use memset to make this more portable.
v2: Specify the compiler / diagnostic in the commit message (Paul)
Cc: Sun peng Li
Cc: Harry Wentland
Signed-off-by: Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 5b7a85e28fab..9cdd52edfc3d 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -5982,7 +5982,9 @@ dm_determine_update_type_for_commit(struct dc *dc,
}
for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
new_crtc_state, i) {
- struct dc_stream_update stream_update = { 0 };
+ struct dc_stream_update stream_update;
+
+ memset(_update, 0, sizeof(stream_update));
new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
old_dm_crtc_state = to_dm_crtc_state(old_crtc_state);
--
2.17.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amd/display: Initialize stream_update with memset
On 3/22/19 9:49 AM, Paul Menzel wrote: > Dear Nicholas, > > > On 03/22/19 14:15, Nicholas Kazlauskas wrote: >> The brace initialization used here generates errors on some >> compilers. Use memset to make this more portable. > > Could you please specify the problematic compiler/toolchain in > the commit message? > > […] > > > Kind regards, > > Paul > I actually meant warning in this case - since I usually build amdgpu with warnings as errors. In this case it was an older version of GCC that generated the warning (4.9). Though I think clang does as well, I forgot to make this patch after I saw the email from Nils Wallménius a while back. There were similar issues in a few other places: https://lists.freedesktop.org/archives/amd-gfx/2019-February/031116.html I'll update the commit message and post a v2, thanks! Nicholas Kazlauskas ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amd/display: Initialize stream_update with memset
Dear Nicholas, On 03/22/19 14:15, Nicholas Kazlauskas wrote: > The brace initialization used here generates errors on some > compilers. Use memset to make this more portable. Could you please specify the problematic compiler/toolchain in the commit message? […] Kind regards, Paul smime.p7s Description: S/MIME Cryptographic Signature ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: Radeon HD 7450 brightness oversaturated
I decided to put a discrete graphics card into a PC and found a fitting Radeon HD 7450. It works, but there is strange whiteness like the brightness is oversaturated and light places turn into other colors: * on fbcon, right after radeondrmfb initializes * in X after powersave The colors return to normal after a VT switch or two. Screenshot of one such washed view is at http://kodu.ut.ee/~mroos/radeon_washed.jpg Kernels are 5.0 and 5.1-rc1. Is it just kernels 5.0 and 5.1? There haven't really been any display related changes to radeon in ages. Possibly a duplicate of: https://bugzilla.kernel.org/show_bug.cgi?id=198123 No, I just put the card in and tested with only the current kernels I had. I can get some older kernel and test with that if that is of any help. -- Meelis Roos ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH v13 04/20] mm, arm64: untag user pointers passed to memory syscalls
On Wed, Mar 20, 2019 at 03:51:18PM +0100, Andrey Konovalov wrote: > This patch is a part of a series that extends arm64 kernel ABI to allow to > pass tagged user pointers (with the top byte set to something else other > than 0x00) as syscall arguments. > > This patch allows tagged pointers to be passed to the following memory > syscalls: madvise, mbind, get_mempolicy, mincore, mlock, mlock2, brk, > mmap_pgoff, old_mmap, munmap, remap_file_pages, mprotect, pkey_mprotect, > mremap, msync and shmdt. > > This is done by untagging pointers passed to these syscalls in the > prologues of their handlers. > > Signed-off-by: Andrey Konovalov > --- > ipc/shm.c | 2 ++ > mm/madvise.c | 2 ++ > mm/mempolicy.c | 5 + > mm/migrate.c | 1 + > mm/mincore.c | 2 ++ > mm/mlock.c | 5 + > mm/mmap.c | 7 +++ > mm/mprotect.c | 1 + > mm/mremap.c| 2 ++ > mm/msync.c | 2 ++ > 10 files changed, 29 insertions(+) I wonder whether it's better to keep these as wrappers in the arm64 code. -- Catalin ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH v13 09/20] net, arm64: untag user pointers in tcp_zerocopy_receive
On Wed, Mar 20, 2019 at 03:51:23PM +0100, Andrey Konovalov wrote: > This patch is a part of a series that extends arm64 kernel ABI to allow to > pass tagged user pointers (with the top byte set to something else other > than 0x00) as syscall arguments. > > tcp_zerocopy_receive() uses provided user pointers for vma lookups, which > can only by done with untagged pointers. > > Untag user pointers in this function. > > Signed-off-by: Andrey Konovalov > --- > net/ipv4/tcp.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/net/ipv4/tcp.c b/net/ipv4/tcp.c > index 6baa6dc1b13b..855a1f68c1ea 100644 > --- a/net/ipv4/tcp.c > +++ b/net/ipv4/tcp.c > @@ -1761,6 +1761,8 @@ static int tcp_zerocopy_receive(struct sock *sk, > if (address & (PAGE_SIZE - 1) || address != zc->address) > return -EINVAL; > > + address = untagged_addr(address); > + > if (sk->sk_state == TCP_LISTEN) > return -ENOTCONN; I don't think we need this patch if we stick to Vincenzo's ABI restrictions. Can zc->address be an anonymous mmap()? My understanding of TCP_ZEROCOPY_RECEIVE is that this is an mmap() on a socket, so user should not tag such pointer. We want to allow tagged pointers to work transparently only for heap and stack, hence the restriction to anonymous mmap() and those addresses below sbrk(0). -- Catalin ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amd/display: Initialize stream_update with memset
The brace initialization used here generates errors on some
compilers. Use memset to make this more portable.
Cc: Sun peng Li
Cc: Harry Wentland
Signed-off-by: Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 5b7a85e28fab..9cdd52edfc3d 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -5982,7 +5982,9 @@ dm_determine_update_type_for_commit(struct dc *dc,
}
for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
new_crtc_state, i) {
- struct dc_stream_update stream_update = { 0 };
+ struct dc_stream_update stream_update;
+
+ memset(_update, 0, sizeof(stream_update));
new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
old_dm_crtc_state = to_dm_crtc_state(old_crtc_state);
--
2.17.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: Limit gpu max clock for ryzen 2400g
Found a way how to do it by modifying amdgpu driver. If there's any better way please let me know.. diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c index 5273de3c5b98..70b9fb8d6041 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c @@ -497,6 +497,8 @@ static int smu10_populate_clock_table(struct pp_hwmgr *hwmgr) smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency); result = smum_get_argument(hwmgr); //smu10_data->gfx_max_freq_limit = result / 10 * 1000; +smu10_data->gfx_max_freq_limit = 5; -- Lauri On Fri, Mar 22, 2019 at 12:18 PM Lauri Ehrenpreis wrote: > Hi! > > Is there a way how to limit gpu max clock rate? Currently I can either > leave the clock to automatic mode or force it to specific level > via /sys/class/drm/card0/device/pp_dpm_sclk. But ideally I would like the > clock to be automatically regulated but specify a different upper limit for > power saving reasons. > > -- > Lauri > ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Limit gpu max clock for ryzen 2400g
Hi! Is there a way how to limit gpu max clock rate? Currently I can either leave the clock to automatic mode or force it to specific level via /sys/class/drm/card0/device/pp_dpm_sclk. But ideally I would like the clock to be automatically regulated but specify a different upper limit for power saving reasons. -- Lauri ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH] drm/amdgpu: defer cmd/fence/fw buffers destroy on hw_init failure
This affects hw_init only. It's not on the path of S3/resume and
gpu_recovery/resume.
So, they are not affected.
Regards,
Evan
> -Original Message-
> From: Xu, Feifei
> Sent: 2019年3月22日 16:56
> To: Quan, Evan ; amd-gfx@lists.freedesktop.org
> Cc: Quan, Evan
> Subject: RE: [PATCH] drm/amdgpu: defer cmd/fence/fw buffers destroy on
> hw_init failure
>
> Have you tested in S3 and gpu_recovery?
>
> If yes. Reviewed-by: Feifei Xu
>
> -Original Message-
> From: amd-gfx On Behalf Of Evan
> Quan
> Sent: Monday, March 18, 2019 10:42 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Quan, Evan
> Subject: [PATCH] drm/amdgpu: defer cmd/fence/fw buffers destroy on
> hw_init failure
>
> As the cleanup jobs performed in pre_fini may still need these buffers. NULL
> pointer dereference will be triggered without them.
>
> Change-Id: I398efd652584e022debf237950207199a4ea78fc
> Signed-off-by: Evan Quan
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 31 ++--
> -
> 1 file changed, 12 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> index 5888e24219d9..2206bb4b0903 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> @@ -890,59 +890,52 @@ static int psp_load_fw(struct amdgpu_device
> *adev)
> >fence_buf_mc_addr,
> >fence_buf);
> if (ret)
> - goto failed_mem2;
> + goto failed;
>
> ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE,
> PAGE_SIZE,
> AMDGPU_GEM_DOMAIN_VRAM,
> >cmd_buf_bo,
> >cmd_buf_mc_addr,
> (void **)>cmd_buf_mem);
> if (ret)
> - goto failed_mem1;
> + goto failed;
>
> memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
>
> ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
> if (ret) {
> DRM_ERROR("PSP ring init failed!\n");
> - goto failed_mem;
> + goto failed;
> }
>
> ret = psp_tmr_init(psp);
> if (ret) {
> DRM_ERROR("PSP tmr init failed!\n");
> - goto failed_mem;
> + goto failed;
> }
>
> ret = psp_asd_init(psp);
> if (ret) {
> DRM_ERROR("PSP asd init failed!\n");
> - goto failed_mem;
> + goto failed;
> }
>
> skip_memalloc:
> ret = psp_hw_start(psp);
> if (ret)
> - goto failed_mem;
> + goto failed;
>
> ret = psp_np_fw_load(psp);
> if (ret)
> - goto failed_mem;
> + goto failed;
>
> return 0;
>
> -failed_mem:
> - amdgpu_bo_free_kernel(>cmd_buf_bo,
> - >cmd_buf_mc_addr,
> - (void **)>cmd_buf_mem);
> -failed_mem1:
> - amdgpu_bo_free_kernel(>fence_buf_bo,
> - >fence_buf_mc_addr, >fence_buf);
> -failed_mem2:
> - amdgpu_bo_free_kernel(>fw_pri_bo,
> - >fw_pri_mc_addr, >fw_pri_buf);
> failed:
> - kfree(psp->cmd);
> - psp->cmd = NULL;
> + /*
> + * all cleanup jobs (xgmi terminate, ras terminate,
> + * ring destroy, cmd/fence/fw buffers destory,
> + * psp->cmd destory) are delayed to psp_hw_fini
> + */
> return ret;
> }
>
> --
> 2.21.0
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH 1/3] drm/amdgpu: error out on mode1 reset failure
Reviewed-by: Feifei Xu
-Original Message-
From: amd-gfx On Behalf Of Quan, Evan
Sent: Friday, March 22, 2019 4:32 PM
To: Quan, Evan ; amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH 1/3] drm/amdgpu: error out on mode1 reset failure
Ping..
> -Original Message-
> From: Evan Quan
> Sent: 2019年3月15日 14:02
> To: amd-gfx@lists.freedesktop.org
> Cc: Quan, Evan
> Subject: [PATCH 1/3] drm/amdgpu: error out on mode1 reset failure
>
> The error return value should be correctly reflected.
>
> Change-Id: I93bf6fa77193d4e3f102a4e223aa8cb18cb525cc
> Signed-off-by: Evan Quan
> ---
> drivers/gpu/drm/amd/amdgpu/soc15.c | 7 +--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
> b/drivers/gpu/drm/amd/amdgpu/soc15.c
> index 0c5ce4bd6feb..9d33a5d73072 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> @@ -393,6 +393,7 @@ void soc15_program_register_sequence(struct
> amdgpu_device *adev, static int soc15_asic_mode1_reset(struct
> amdgpu_device *adev) {
> u32 i;
> + int ret = 0;
>
> amdgpu_atombios_scratch_regs_engine_hung(adev, true);
>
> @@ -403,7 +404,9 @@ static int soc15_asic_mode1_reset(struct
> amdgpu_device *adev)
>
> pci_save_state(adev->pdev);
>
> - psp_gpu_reset(adev);
> + ret = psp_gpu_reset(adev);
> + if (ret)
> + dev_err(adev->dev, "GPU mode1 reset failed\n");
>
> pci_restore_state(adev->pdev);
>
> @@ -418,7 +421,7 @@ static int soc15_asic_mode1_reset(struct
> amdgpu_device *adev)
>
> amdgpu_atombios_scratch_regs_engine_hung(adev, false);
>
> - return 0;
> + return ret;
> }
>
> static int soc15_asic_get_baco_capability(struct amdgpu_device *adev,
> bool
> *cap)
> --
> 2.21.0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH 3/3] drm/amdgpu: add more debug friendly prompts
Reviewed-by: Feifei Xu
-Original Message-
From: amd-gfx On Behalf Of Quan, Evan
Sent: Friday, March 22, 2019 4:31 PM
To: Quan, Evan ; amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH 3/3] drm/amdgpu: add more debug friendly prompts
Ping..
> -Original Message-
> From: Evan Quan
> Sent: 2019年3月15日 14:02
> To: amd-gfx@lists.freedesktop.org
> Cc: Quan, Evan
> Subject: [PATCH 3/3] drm/amdgpu: add more debug friendly prompts
>
> Large piece of codes share one error prompt. That is not friendly for
> debugging.
>
> Change-Id: I15f77210af6a409981fe44cf5dd3aa8ce48d948f
> Signed-off-by: Evan Quan
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 38 ++-
> --
> 1 file changed, 28 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> index 32388b5218e9..5888e24219d9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> @@ -136,7 +136,7 @@ psp_cmd_submit_buf(struct psp_context *psp,
>
> while (*((unsigned int *)psp->fence_buf) != index) {
> if (--timeout == 0)
> - return -EINVAL;
> + break;
> msleep(1);
> }
>
> @@ -147,12 +147,14 @@ psp_cmd_submit_buf(struct psp_context *psp,
>* during psp initialization to avoid breaking hw_init and it doesn't
>* return -EINVAL.
>*/
> - if (psp->cmd_buf_mem->resp.status) {
> + if (psp->cmd_buf_mem->resp.status || !timeout) {
> if (ucode)
> DRM_WARN("failed to load ucode id (%d) ",
> ucode->ucode_id);
> DRM_WARN("psp command failed and response status is (%d)\n",
> psp->cmd_buf_mem->resp.status);
> + if (!timeout)
> + return -EINVAL;
> }
>
> /* get xGMI session id from response buffer */ @@ -677,25 +679,35 @@
> static int psp_hw_start(struct psp_context *psp)
>
> if (!amdgpu_sriov_vf(adev) || !adev->in_gpu_reset) {
> ret = psp_bootloader_load_sysdrv(psp);
> - if (ret)
> + if (ret) {
> + DRM_ERROR("PSP load sysdrv failed!\n");
> return ret;
> + }
>
> ret = psp_bootloader_load_sos(psp);
> - if (ret)
> + if (ret) {
> + DRM_ERROR("PSP load sos failed!\n");
> return ret;
> + }
> }
>
> ret = psp_ring_create(psp, PSP_RING_TYPE__KM);
> - if (ret)
> + if (ret) {
> + DRM_ERROR("PSP create ring failed!\n");
> return ret;
> + }
>
> ret = psp_tmr_load(psp);
> - if (ret)
> + if (ret) {
> + DRM_ERROR("PSP load tmr failed!\n");
> return ret;
> + }
>
> ret = psp_asd_load(psp);
> - if (ret)
> + if (ret) {
> + DRM_ERROR("PSP load asd failed!\n");
> return ret;
> + }
>
> if (adev->gmc.xgmi.num_physical_nodes > 1) {
> ret = psp_xgmi_initialize(psp);
> @@ -890,16 +902,22 @@ static int psp_load_fw(struct amdgpu_device
> *adev)
> memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
>
> ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
> - if (ret)
> + if (ret) {
> + DRM_ERROR("PSP ring init failed!\n");
> goto failed_mem;
> + }
>
> ret = psp_tmr_init(psp);
> - if (ret)
> + if (ret) {
> + DRM_ERROR("PSP tmr init failed!\n");
> goto failed_mem;
> + }
>
> ret = psp_asd_init(psp);
> - if (ret)
> + if (ret) {
> + DRM_ERROR("PSP asd init failed!\n");
> goto failed_mem;
> + }
>
> skip_memalloc:
> ret = psp_hw_start(psp);
> --
> 2.21.0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH] drm/amdgpu: defer cmd/fence/fw buffers destroy on hw_init failure
Ping..
> -Original Message-
> From: Evan Quan
> Sent: 2019年3月18日 10:42
> To: amd-gfx@lists.freedesktop.org
> Cc: Quan, Evan
> Subject: [PATCH] drm/amdgpu: defer cmd/fence/fw buffers destroy on
> hw_init failure
>
> As the cleanup jobs performed in pre_fini may still need these buffers. NULL
> pointer dereference will be triggered without them.
>
> Change-Id: I398efd652584e022debf237950207199a4ea78fc
> Signed-off-by: Evan Quan
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 31 ++--
> -
> 1 file changed, 12 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> index 5888e24219d9..2206bb4b0903 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> @@ -890,59 +890,52 @@ static int psp_load_fw(struct amdgpu_device
> *adev)
> >fence_buf_mc_addr,
> >fence_buf);
> if (ret)
> - goto failed_mem2;
> + goto failed;
>
> ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE,
> PAGE_SIZE,
> AMDGPU_GEM_DOMAIN_VRAM,
> >cmd_buf_bo,
> >cmd_buf_mc_addr,
> (void **)>cmd_buf_mem);
> if (ret)
> - goto failed_mem1;
> + goto failed;
>
> memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
>
> ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
> if (ret) {
> DRM_ERROR("PSP ring init failed!\n");
> - goto failed_mem;
> + goto failed;
> }
>
> ret = psp_tmr_init(psp);
> if (ret) {
> DRM_ERROR("PSP tmr init failed!\n");
> - goto failed_mem;
> + goto failed;
> }
>
> ret = psp_asd_init(psp);
> if (ret) {
> DRM_ERROR("PSP asd init failed!\n");
> - goto failed_mem;
> + goto failed;
> }
>
> skip_memalloc:
> ret = psp_hw_start(psp);
> if (ret)
> - goto failed_mem;
> + goto failed;
>
> ret = psp_np_fw_load(psp);
> if (ret)
> - goto failed_mem;
> + goto failed;
>
> return 0;
>
> -failed_mem:
> - amdgpu_bo_free_kernel(>cmd_buf_bo,
> - >cmd_buf_mc_addr,
> - (void **)>cmd_buf_mem);
> -failed_mem1:
> - amdgpu_bo_free_kernel(>fence_buf_bo,
> - >fence_buf_mc_addr, >fence_buf);
> -failed_mem2:
> - amdgpu_bo_free_kernel(>fw_pri_bo,
> - >fw_pri_mc_addr, >fw_pri_buf);
> failed:
> - kfree(psp->cmd);
> - psp->cmd = NULL;
> + /*
> + * all cleanup jobs (xgmi terminate, ras terminate,
> + * ring destroy, cmd/fence/fw buffers destory,
> + * psp->cmd destory) are delayed to psp_hw_fini
> + */
> return ret;
> }
>
> --
> 2.21.0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH 1/3] drm/amdgpu: error out on mode1 reset failure
Ping..
> -Original Message-
> From: Evan Quan
> Sent: 2019年3月15日 14:02
> To: amd-gfx@lists.freedesktop.org
> Cc: Quan, Evan
> Subject: [PATCH 1/3] drm/amdgpu: error out on mode1 reset failure
>
> The error return value should be correctly reflected.
>
> Change-Id: I93bf6fa77193d4e3f102a4e223aa8cb18cb525cc
> Signed-off-by: Evan Quan
> ---
> drivers/gpu/drm/amd/amdgpu/soc15.c | 7 +--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
> b/drivers/gpu/drm/amd/amdgpu/soc15.c
> index 0c5ce4bd6feb..9d33a5d73072 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> @@ -393,6 +393,7 @@ void soc15_program_register_sequence(struct
> amdgpu_device *adev, static int soc15_asic_mode1_reset(struct
> amdgpu_device *adev) {
> u32 i;
> + int ret = 0;
>
> amdgpu_atombios_scratch_regs_engine_hung(adev, true);
>
> @@ -403,7 +404,9 @@ static int soc15_asic_mode1_reset(struct
> amdgpu_device *adev)
>
> pci_save_state(adev->pdev);
>
> - psp_gpu_reset(adev);
> + ret = psp_gpu_reset(adev);
> + if (ret)
> + dev_err(adev->dev, "GPU mode1 reset failed\n");
>
> pci_restore_state(adev->pdev);
>
> @@ -418,7 +421,7 @@ static int soc15_asic_mode1_reset(struct
> amdgpu_device *adev)
>
> amdgpu_atombios_scratch_regs_engine_hung(adev, false);
>
> - return 0;
> + return ret;
> }
>
> static int soc15_asic_get_baco_capability(struct amdgpu_device *adev, bool
> *cap)
> --
> 2.21.0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH 3/3] drm/amdgpu: add more debug friendly prompts
Ping..
> -Original Message-
> From: Evan Quan
> Sent: 2019年3月15日 14:02
> To: amd-gfx@lists.freedesktop.org
> Cc: Quan, Evan
> Subject: [PATCH 3/3] drm/amdgpu: add more debug friendly prompts
>
> Large piece of codes share one error prompt. That is not friendly for
> debugging.
>
> Change-Id: I15f77210af6a409981fe44cf5dd3aa8ce48d948f
> Signed-off-by: Evan Quan
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 38 ++-
> --
> 1 file changed, 28 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> index 32388b5218e9..5888e24219d9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> @@ -136,7 +136,7 @@ psp_cmd_submit_buf(struct psp_context *psp,
>
> while (*((unsigned int *)psp->fence_buf) != index) {
> if (--timeout == 0)
> - return -EINVAL;
> + break;
> msleep(1);
> }
>
> @@ -147,12 +147,14 @@ psp_cmd_submit_buf(struct psp_context *psp,
>* during psp initialization to avoid breaking hw_init and it doesn't
>* return -EINVAL.
>*/
> - if (psp->cmd_buf_mem->resp.status) {
> + if (psp->cmd_buf_mem->resp.status || !timeout) {
> if (ucode)
> DRM_WARN("failed to load ucode id (%d) ",
> ucode->ucode_id);
> DRM_WARN("psp command failed and response status is
> (%d)\n",
> psp->cmd_buf_mem->resp.status);
> + if (!timeout)
> + return -EINVAL;
> }
>
> /* get xGMI session id from response buffer */ @@ -677,25 +679,35
> @@ static int psp_hw_start(struct psp_context *psp)
>
> if (!amdgpu_sriov_vf(adev) || !adev->in_gpu_reset) {
> ret = psp_bootloader_load_sysdrv(psp);
> - if (ret)
> + if (ret) {
> + DRM_ERROR("PSP load sysdrv failed!\n");
> return ret;
> + }
>
> ret = psp_bootloader_load_sos(psp);
> - if (ret)
> + if (ret) {
> + DRM_ERROR("PSP load sos failed!\n");
> return ret;
> + }
> }
>
> ret = psp_ring_create(psp, PSP_RING_TYPE__KM);
> - if (ret)
> + if (ret) {
> + DRM_ERROR("PSP create ring failed!\n");
> return ret;
> + }
>
> ret = psp_tmr_load(psp);
> - if (ret)
> + if (ret) {
> + DRM_ERROR("PSP load tmr failed!\n");
> return ret;
> + }
>
> ret = psp_asd_load(psp);
> - if (ret)
> + if (ret) {
> + DRM_ERROR("PSP load asd failed!\n");
> return ret;
> + }
>
> if (adev->gmc.xgmi.num_physical_nodes > 1) {
> ret = psp_xgmi_initialize(psp);
> @@ -890,16 +902,22 @@ static int psp_load_fw(struct amdgpu_device
> *adev)
> memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
>
> ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
> - if (ret)
> + if (ret) {
> + DRM_ERROR("PSP ring init failed!\n");
> goto failed_mem;
> + }
>
> ret = psp_tmr_init(psp);
> - if (ret)
> + if (ret) {
> + DRM_ERROR("PSP tmr init failed!\n");
> goto failed_mem;
> + }
>
> ret = psp_asd_init(psp);
> - if (ret)
> + if (ret) {
> + DRM_ERROR("PSP asd init failed!\n");
> goto failed_mem;
> + }
>
> skip_memalloc:
> ret = psp_hw_start(psp);
> --
> 2.21.0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 1/9] dma-buf: add new dma_fence_chain container v6
how about the attached?
If ok, I will merge to pathc#1.
-David
On 2019年03月21日 22:40, Christian König wrote:
No, atomic cmpxchg is a hardware operation. If you want to replace
that you need a lock again.
Maybe just add a comment and use an explicit cast to void* ? Not sure
if that silences the warning.
Christian.
Am 21.03.19 um 15:13 schrieb Zhou, David(ChunMing):
cmpxchg be replaced by some simple c sentance?
otherwise we have to remove __rcu of chian->prev.
-David
Original Message
Subject: Re: [PATCH 1/9] dma-buf: add new dma_fence_chain container v6
From: Christian König
To: "Zhou, David(ChunMing)" ,kbuild test robot ,"Zhou, David(ChunMing)"
CC:
kbuild-...@01.org,dri-de...@lists.freedesktop.org,amd-gfx@lists.freedesktop.org,lionel.g.landwer...@intel.com,ja...@jlekstrand.net,"Koenig,
Christian" ,"Hector, Tobias"
Hi David,
For the cmpxchg() case I of hand don't know either. Looks like so far
nobody has used cmpxchg() with rcu protected structures.
The other cases should be replaced by RCU_INIT_POINTER() or
rcu_dereference_protected(.., true);
Regards,
Christian.
Am 21.03.19 um 07:34 schrieb zhoucm1:
> Hi Lionel and Christian,
>
> Below is robot report for chain->prev, which was added __rcu as you
> suggested.
>
> How to fix this line "tmp = cmpxchg(>prev, prev,
replacement); "?
> I checked kernel header file, seems it has no cmpxchg for rcu.
>
> Any suggestion to fix this robot report?
>
> Thanks,
> -David
>
> On 2019年03月21日 08:24, kbuild test robot wrote:
>> Hi Chunming,
>>
>> I love your patch! Perhaps something to improve:
>>
>> [auto build test WARNING on linus/master]
>> [also build test WARNING on v5.1-rc1 next-20190320]
>> [if your patch is applied to the wrong git tree, please drop us a
>> note to help improve the system]
>>
>> url:
>>
https://github.com/0day-ci/linux/commits/Chunming-Zhou/dma-buf-add-new-dma_fence_chain-container-v6/20190320-223607
>> reproduce:
>> # apt-get install sparse
>> make ARCH=x86_64 allmodconfig
>> make C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__'
>>
>>
>> sparse warnings: (new ones prefixed by >>)
>>
drivers/dma-buf/dma-fence-chain.c:73:23: sparse: incorrect type in
initializer (different address spaces) @@ expected struct
dma_fence [noderef] *__old @@ got dma_fence [noderef]
*__old @@
>> drivers/dma-buf/dma-fence-chain.c:73:23: expected struct
>> dma_fence [noderef] *__old
>> drivers/dma-buf/dma-fence-chain.c:73:23: got struct dma_fence
>> *[assigned] prev
drivers/dma-buf/dma-fence-chain.c:73:23: sparse: incorrect type in
initializer (different address spaces) @@ expected struct
dma_fence [noderef] *__new @@ got dma_fence [noderef]
*__new @@
>> drivers/dma-buf/dma-fence-chain.c:73:23: expected struct
>> dma_fence [noderef] *__new
>> drivers/dma-buf/dma-fence-chain.c:73:23: got struct dma_fence
>> *[assigned] replacement
drivers/dma-buf/dma-fence-chain.c:73:21: sparse: incorrect type in
assignment (different address spaces) @@ expected struct
dma_fence *tmp @@ got struct dma_fence [noderef] >>> dma_fence *tmp @@
>> drivers/dma-buf/dma-fence-chain.c:73:21: expected struct
>> dma_fence *tmp
>> drivers/dma-buf/dma-fence-chain.c:73:21: got struct dma_fence
>> [noderef] *[assigned] __ret
drivers/dma-buf/dma-fence-chain.c:190:28: sparse: incorrect type in
argument 1 (different address spaces) @@ expected struct
dma_fence *fence @@ got struct dma_fence struct dma_fence
*fence @@
>> drivers/dma-buf/dma-fence-chain.c:190:28: expected struct
>> dma_fence *fence
>> drivers/dma-buf/dma-fence-chain.c:190:28: got struct dma_fence
>> [noderef] *prev
drivers/dma-buf/dma-fence-chain.c:222:21: sparse: incorrect type in
assignment (different address spaces) @@ expected struct
dma_fence [noderef] *prev @@ got [noderef] *prev @@
>> drivers/dma-buf/dma-fence-chain.c:222:21: expected struct
>> dma_fence [noderef] *prev
>> drivers/dma-buf/dma-fence-chain.c:222:21: got struct dma_fence
>> *prev
>> drivers/dma-buf/dma-fence-chain.c:235:33: sparse: expression
>> using sizeof(void)
>> drivers/dma-buf/dma-fence-chain.c:235:33: sparse: expression
>> using sizeof(void)
>>
>> vim +73 drivers/dma-buf/dma-fence-chain.c
>>
>> 38
>> 39 /**
>> 40 * dma_fence_chain_walk - chain walking function
>> 41 * @fence: current chain node
>> 42 *
>> 43 * Walk the chain to the next node. Returns the next fence
>> or NULL if we are at
>> 44 * the end of the chain. Garbage collects chain nodes
>> which are already
>> 45 * signaled.
>> 46 */
>> 47 struct dma_fence *dma_fence_chain_walk(struct dma_fence
>> *fence)
>> 48 {
>> 49 struct dma_fence_chain *chain, *prev_chain;
>> 50 struct dma_fence *prev, *replacement, *tmp;
>> 51
>> 52 chain =
