Re: [PATCH] drm/amdgpu/powerplay: provide the interface to disable uclk switch for DAL
On 7/30/19 12:09 PM, Kenneth Feng wrote:
> provide the interface for DAL to disable uclk switch on navi10.
> in this case, the uclk will be fixed to maximum.
> this is a workaround when display configuration causes underflow issue.
>
> Signed-off-by: Kenneth Feng
> ---
> .../drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 17 +++
> drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 5 +
> drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 25
> ++
> drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 7 ++
> 4 files changed, 54 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
> index 7bc7abc..5b4323b 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
> @@ -802,6 +802,22 @@ enum pp_smu_status
> pp_nv_set_hard_min_uclk_by_freq(struct pp_smu *pp, int mhz)
> return PP_SMU_RESULT_OK;
> }
>
> +enum pp_smu_status pp_nv_set_pstate_handshake_support(struct pp_smu *pp,
> +
> BOOLEAN pstate_handshake_supported)
[kevin]:
please take care of code format.
> +{
> + const struct dc_context *ctx = pp->dm;
> + struct amdgpu_device *adev = ctx->driver_context;
> + struct smu_context *smu = >smu;
> +
> + if (!smu->ppt_funcs)
> + return PP_SMU_RESULT_UNSUPPORTED;
> +
> + if (smu_display_disable_memory_clock_switch(smu,
> !pstate_handshake_supported))
> + return PP_SMU_RESULT_FAIL;
> +
> + return PP_SMU_RESULT_OK;
> +}
> +
> enum pp_smu_status pp_nv_set_voltage_by_freq(struct pp_smu *pp,
> enum pp_smu_nv_clock_id clock_id, int mhz)
> {
> @@ -917,6 +933,7 @@ void dm_pp_get_funcs(
> funcs->nv_funcs.get_maximum_sustainable_clocks =
> pp_nv_get_maximum_sustainable_clocks;
> /*todo compare data with window driver */
> funcs->nv_funcs.get_uclk_dpm_states = pp_nv_get_uclk_dpm_states;
> + funcs->nv_funcs.set_pstate_handshake_support =
> pp_nv_set_pstate_handshake_support;
> break;
> #endif
> default:
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> index 33d2d75..642a1b1 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> @@ -549,6 +549,8 @@ struct smu_context
> #define WATERMARKS_EXIST(1 << 0)
> #define WATERMARKS_LOADED (1 << 1)
> uint32_t watermarks_bitmap;
> + uint32_t hard_min_uclk_req_from_dal;
> + bool disable_uclk_switch;
>
> uint32_t workload_mask;
> uint32_t workload_prority[WORKLOAD_POLICY_MAX];
> @@ -632,6 +634,7 @@ struct pptable_funcs {
> int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t
> *clocks_in_khz, uint32_t *num_states);
> int (*set_default_od_settings)(struct smu_context *smu, bool
> initialize);
> int (*set_performance_level)(struct smu_context *smu, enum
> amd_dpm_forced_level level);
> + int (*display_disable_memory_clock_switch)(struct smu_context *smu,
> bool disable_memory_clock_switch);
> };
>
> struct smu_funcs
> @@ -884,6 +887,8 @@ struct smu_funcs
> ((smu)->ppt_funcs->get_clock_by_type_with_voltage ?
> (smu)->ppt_funcs->get_clock_by_type_with_voltage((smu), (type), (clocks)) : 0)
> #define smu_display_clock_voltage_request(smu, clock_req) \
> ((smu)->funcs->display_clock_voltage_request ?
> (smu)->funcs->display_clock_voltage_request((smu), (clock_req)) : 0)
> +#define smu_display_disable_memory_clock_switch(smu,
> disable_memory_clock_switch) \
> + ((smu)->ppt_funcs->display_disable_memory_clock_switch ?
> (smu)->ppt_funcs->display_disable_memory_clock_switch((smu),
> (disable_memory_clock_switch)) : 0)
[kevin]:
could you replace 0 with -EINVAL as default return value. if so, you can
call this function directly, and not check "!smu->ppt_funct".
> #define smu_get_dal_power_level(smu, clocks) \
> ((smu)->funcs->get_dal_power_level ?
> (smu)->funcs->get_dal_power_level((smu), (clocks)) : 0)
> #define smu_get_perf_level(smu, designation, level) \
> diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> index c873228..a8c98c4 100644
> --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> @@ -1655,6 +1655,30 @@ static int navi10_get_thermal_temperature_range(struct
> smu_context *smu,
> return 0;
> }
>
> +static int navi10_display_disable_memory_clock_switch(struct smu_context
> *smu,
> + bool
> disable_memory_clock_switch)
> +{
> + int ret = 0;
> + struct smu_11_0_max_sustainable_clocks
[PATCH] drm/amdgpu/powerplay: provide the interface to disable uclk switch for DAL
provide the interface for DAL to disable uclk switch on navi10.
in this case, the uclk will be fixed to maximum.
this is a workaround when display configuration causes underflow issue.
Signed-off-by: Kenneth Feng
---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 17 +++
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 5 +
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 25 ++
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 7 ++
4 files changed, 54 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
index 7bc7abc..5b4323b 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
@@ -802,6 +802,22 @@ enum pp_smu_status pp_nv_set_hard_min_uclk_by_freq(struct
pp_smu *pp, int mhz)
return PP_SMU_RESULT_OK;
}
+enum pp_smu_status pp_nv_set_pstate_handshake_support(struct pp_smu *pp,
+
BOOLEAN pstate_handshake_supported)
+{
+ const struct dc_context *ctx = pp->dm;
+ struct amdgpu_device *adev = ctx->driver_context;
+ struct smu_context *smu = >smu;
+
+ if (!smu->ppt_funcs)
+ return PP_SMU_RESULT_UNSUPPORTED;
+
+ if (smu_display_disable_memory_clock_switch(smu,
!pstate_handshake_supported))
+ return PP_SMU_RESULT_FAIL;
+
+ return PP_SMU_RESULT_OK;
+}
+
enum pp_smu_status pp_nv_set_voltage_by_freq(struct pp_smu *pp,
enum pp_smu_nv_clock_id clock_id, int mhz)
{
@@ -917,6 +933,7 @@ void dm_pp_get_funcs(
funcs->nv_funcs.get_maximum_sustainable_clocks =
pp_nv_get_maximum_sustainable_clocks;
/*todo compare data with window driver */
funcs->nv_funcs.get_uclk_dpm_states = pp_nv_get_uclk_dpm_states;
+ funcs->nv_funcs.set_pstate_handshake_support =
pp_nv_set_pstate_handshake_support;
break;
#endif
default:
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 33d2d75..642a1b1 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -549,6 +549,8 @@ struct smu_context
#define WATERMARKS_EXIST (1 << 0)
#define WATERMARKS_LOADED (1 << 1)
uint32_t watermarks_bitmap;
+ uint32_t hard_min_uclk_req_from_dal;
+ bool disable_uclk_switch;
uint32_t workload_mask;
uint32_t workload_prority[WORKLOAD_POLICY_MAX];
@@ -632,6 +634,7 @@ struct pptable_funcs {
int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t
*clocks_in_khz, uint32_t *num_states);
int (*set_default_od_settings)(struct smu_context *smu, bool
initialize);
int (*set_performance_level)(struct smu_context *smu, enum
amd_dpm_forced_level level);
+ int (*display_disable_memory_clock_switch)(struct smu_context *smu,
bool disable_memory_clock_switch);
};
struct smu_funcs
@@ -884,6 +887,8 @@ struct smu_funcs
((smu)->ppt_funcs->get_clock_by_type_with_voltage ?
(smu)->ppt_funcs->get_clock_by_type_with_voltage((smu), (type), (clocks)) : 0)
#define smu_display_clock_voltage_request(smu, clock_req) \
((smu)->funcs->display_clock_voltage_request ?
(smu)->funcs->display_clock_voltage_request((smu), (clock_req)) : 0)
+#define smu_display_disable_memory_clock_switch(smu,
disable_memory_clock_switch) \
+ ((smu)->ppt_funcs->display_disable_memory_clock_switch ?
(smu)->ppt_funcs->display_disable_memory_clock_switch((smu),
(disable_memory_clock_switch)) : 0)
#define smu_get_dal_power_level(smu, clocks) \
((smu)->funcs->get_dal_power_level ?
(smu)->funcs->get_dal_power_level((smu), (clocks)) : 0)
#define smu_get_perf_level(smu, designation, level) \
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index c873228..a8c98c4 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -1655,6 +1655,30 @@ static int navi10_get_thermal_temperature_range(struct
smu_context *smu,
return 0;
}
+static int navi10_display_disable_memory_clock_switch(struct smu_context *smu,
+ bool
disable_memory_clock_switch)
+{
+ int ret = 0;
+ struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
+ (struct smu_11_0_max_sustainable_clocks *)
+ smu->smu_table.max_sustainable_clocks;
+ uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
+ uint32_t max_memory_clock = max_sustainable_clocks->uclock;
+
+ if(smu->disable_uclk_switch == disable_memory_clock_switch)
+ return 0;
+
+
Re: [PATCH 18/30] drm/amd/powerplay: init arcturus SMU metrics table on bootup
On 7/30/19 4:14 AM, Alex Deucher wrote:
> From: Evan Quan
>
> Initialize arcturus SMU metrics table.
>
> Signed-off-by: Evan Quan
> Reviewed-by: Kevin Wang
> Reviewed-by: Alex Deucher
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 7 +++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
> b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
> index a0644ef267a9..5f911f092311 100644
> --- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
> @@ -267,6 +267,8 @@ static int arcturus_get_workload_type(struct smu_context
> *smu, enum PP_SMC_POWER
>
> static int arcturus_tables_init(struct smu_context *smu, struct smu_table
> *tables)
> {
> + struct smu_table_context *smu_table = >smu_table;
> +
> SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
> PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
>
> @@ -276,6 +278,11 @@ static int arcturus_tables_init(struct smu_context *smu,
> struct smu_table *table
> SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
> PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
>
> + smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
> [kevin]: where is do free operation in driver code ?
> + if (!smu_table->metrics_table)
> + return -ENOMEM;
> + smu_table->metrics_time = 0;
> +
> return 0;
> }
>
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Re: [PATCH 16/30] drm/amd/powerplay: correct Navi10 VCN powergate control
On 7/30/19 4:14 AM, Alex Deucher wrote:
> From: Evan Quan
>
> No VCN DPM bit check as that's different from VCN PG. Also
> no extra check for possible double enablement/disablement
> as that's already done by VCN.
>
> Signed-off-by: Evan Quan
> Reviewed-by: Kenneth Feng
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 26 --
> 1 file changed, 9 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> index 9dd96d8b8dd5..01d534c8442e 100644
> --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> @@ -591,27 +591,19 @@ static int navi10_set_default_dpm_table(struct
> smu_context *smu)
> static int navi10_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
> {
> int ret = 0;
> - struct smu_power_context *smu_power = >smu_power;
> - struct smu_power_gate *power_gate = _power->power_gate;
>
> - if (enable && power_gate->uvd_gated) {
> - if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT)) {
> - ret = smu_send_smc_msg_with_param(smu,
> SMU_MSG_PowerUpVcn, 1);
> - if (ret)
> - return ret;
> - }
> - power_gate->uvd_gated = false;
> + if (enable) {
> + ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1);
> + if (ret)
> + return ret;
> } else {
> - if (!enable && !power_gate->uvd_gated) {
> - if (smu_feature_is_enabled(smu,
> SMU_FEATURE_DPM_UVD_BIT)) {
> - ret = smu_send_smc_msg(smu,
> SMU_MSG_PowerDownVcn);
> - if (ret)
> - return ret;
> - }
> - power_gate->uvd_gated = true;
> - }
> + ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn);
> + if (ret)
> + return ret;
> }
>
> + smu_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, enable);
[kevin]:
you should check return value, this should not be based on some assumptions.
> +
> return 0;
> }
>
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[RFC PATCH 0/3] Propose new struct drm_mem_region
[ By request, resending to include amd-gfx + intel-gfx. Since resending, I fixed the nit with ordering of header includes that Sam noted. ] This RFC series is first implementation of some ideas expressed earlier on dri-devel [1]. Some of the goals (open for much debate) are: - Create common base structure (subclass) for memory regions (patch #1) - Create common memory region types (patch #2) - Create common set of memory_region function callbacks (based on ttm_mem_type_manager_funcs and intel_memory_regions_ops) - Create common helpers that operate on drm_mem_region to be leveraged by both TTM drivers and i915, reducing code duplication - Above might start with refactoring ttm_bo_manager.c as these are helpers for using drm_mm's range allocator and could be made to operate on DRM structures instead of TTM ones. - Larger goal might be to make LRU management of GEM objects common, and migrate those fields into drm_mem_region and drm_gem_object strucures. Patches 1-2 implement the proposed struct drm_mem_region and adds associated common set of definitions for memory region type. Patch #3 is update to i915 and is based upon another series which is in progress to add vram support to i915 [2]. [1] https://lists.freedesktop.org/archives/dri-devel/2019-June/224501.html [2] https://lists.freedesktop.org/archives/intel-gfx/2019-June/203649.html Brian Welty (3): drm: introduce new struct drm_mem_region drm: Introduce DRM_MEM defines for specifying type of drm_mem_region drm/i915: Update intel_memory_region to use nested drm_mem_region drivers/gpu/drm/i915/gem/i915_gem_object.c| 2 +- drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 2 +- drivers/gpu/drm/i915/i915_gem_gtt.c | 10 ++--- drivers/gpu/drm/i915/i915_gpu_error.c | 2 +- drivers/gpu/drm/i915/i915_query.c | 2 +- drivers/gpu/drm/i915/intel_memory_region.c| 10 +++-- drivers/gpu/drm/i915/intel_memory_region.h| 19 +++-- drivers/gpu/drm/i915/intel_region_lmem.c | 26 ++--- .../drm/i915/selftests/intel_memory_region.c | 8 ++-- drivers/gpu/drm/ttm/ttm_bo.c | 34 +--- drivers/gpu/drm/ttm/ttm_bo_manager.c | 14 +++ drivers/gpu/drm/ttm/ttm_bo_util.c | 11 +++--- drivers/gpu/drm/vmwgfx/vmwgfx_gmrid_manager.c | 8 ++-- drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c| 4 +- include/drm/drm_mm.h | 39 ++- include/drm/ttm/ttm_bo_api.h | 2 +- include/drm/ttm/ttm_bo_driver.h | 16 include/drm/ttm/ttm_placement.h | 8 ++-- 18 files changed, 124 insertions(+), 93 deletions(-) -- 2.21.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[RFC PATCH 2/3] drm: Introduce DRM_MEM defines for specifying type of drm_mem_region
Introduce DRM memory region types to be common for both drivers using TTM and for i915. For now, TTM continues to define it's own set but uses the DRM base definitions. Signed-off-by: Brian Welty --- include/drm/drm_mm.h| 8 include/drm/ttm/ttm_placement.h | 8 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/include/drm/drm_mm.h b/include/drm/drm_mm.h index 465f8d10d863..b78dc9284702 100644 --- a/include/drm/drm_mm.h +++ b/include/drm/drm_mm.h @@ -59,6 +59,14 @@ struct drm_device; struct drm_mm; +/* + * Memory types for drm_mem_region + */ +#define DRM_MEM_SYSTEM 0 +#define DRM_MEM_STOLEN 1 +#define DRM_MEM_VRAM 2 +#define DRM_MEM_PRIV 3 + /** * struct drm_mem_region * diff --git a/include/drm/ttm/ttm_placement.h b/include/drm/ttm/ttm_placement.h index e88a8e39767b..976cf8d2f899 100644 --- a/include/drm/ttm/ttm_placement.h +++ b/include/drm/ttm/ttm_placement.h @@ -37,10 +37,10 @@ * Memory regions for data placement. */ -#define TTM_PL_SYSTEM 0 -#define TTM_PL_TT 1 -#define TTM_PL_VRAM 2 -#define TTM_PL_PRIV 3 +#define TTM_PL_SYSTEM DRM_MEM_SYSTEM +#define TTM_PL_TT DRM_MEM_STOLEN +#define TTM_PL_VRAM DRM_MEM_VRAM +#define TTM_PL_PRIV DRM_MEM_PRIV #define TTM_PL_FLAG_SYSTEM (1 << TTM_PL_SYSTEM) #define TTM_PL_FLAG_TT (1 << TTM_PL_TT) -- 2.21.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[RFC PATCH 3/3] drm/i915: Update intel_memory_region to use nested drm_mem_region
Some fields are deleted from intel_memory_region in favor of instead
using the new nested drm_mem_region structure.
Note, this is based upon unmerged i915 series [1] in order to show how
i915 might begin to integrate the proposed drm_mem_region.
[1] https://lists.freedesktop.org/archives/intel-gfx/2019-June/203649.html
Signed-off-by: Brian Welty
---
drivers/gpu/drm/i915/gem/i915_gem_object.c| 2 +-
drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 10 +++
drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
drivers/gpu/drm/i915/i915_query.c | 2 +-
drivers/gpu/drm/i915/intel_memory_region.c| 10 ---
drivers/gpu/drm/i915/intel_memory_region.h| 19 --
drivers/gpu/drm/i915/intel_region_lmem.c | 26 +--
.../drm/i915/selftests/intel_memory_region.c | 8 +++---
9 files changed, 37 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c
b/drivers/gpu/drm/i915/gem/i915_gem_object.c
index 73d2d72adc19..7e56fd89a972 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
@@ -606,7 +606,7 @@ static int i915_gem_object_region_select(struct
drm_i915_private *dev_priv,
ret = i915_gem_object_migrate(obj, ce, id);
if (!ret) {
if (MEMORY_TYPE_FROM_REGION(region) ==
- INTEL_LMEM) {
+ DRM_MEM_VRAM) {
/*
* TODO: this should be part of get_pages(),
* when async get_pages arrives
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
index d24f34443c4c..ac18e73665d4 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
@@ -53,7 +53,7 @@ static int shmem_get_pages(struct drm_i915_gem_object *obj)
* If there's no chance of allocating enough pages for the whole
* object, bail early.
*/
- if (obj->base.size > resource_size(>region))
+ if (obj->base.size > mem->region.size)
return -ENOMEM;
st = kmalloc(sizeof(*st), GFP_KERNEL);
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 2288a55f27f1..f4adc7e397ff 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2737,20 +2737,20 @@ int i915_gem_init_memory_regions(struct
drm_i915_private *i915)
for (i = 0; i < ARRAY_SIZE(intel_region_map); i++) {
struct intel_memory_region *mem = NULL;
- u32 type;
+ u8 type;
if (!HAS_REGION(i915, BIT(i)))
continue;
type = MEMORY_TYPE_FROM_REGION(intel_region_map[i]);
switch (type) {
- case INTEL_SMEM:
+ case DRM_MEM_SYSTEM:
mem = i915_gem_shmem_setup(i915);
break;
- case INTEL_STOLEN:
+ case DRM_MEM_STOLEN:
mem = i915_gem_stolen_setup(i915);
break;
- case INTEL_LMEM:
+ case DRM_MEM_VRAM:
mem = i915_gem_setup_fake_lmem(i915);
break;
}
@@ -2762,7 +2762,7 @@ int i915_gem_init_memory_regions(struct drm_i915_private
*i915)
}
mem->id = intel_region_map[i];
- mem->type = type;
+ mem->region.type = type;
mem->instance =
MEMORY_INSTANCE_FROM_REGION(intel_region_map[i]);
i915->regions[i] = mem;
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 9feb597f2b01..908691c3aadb 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1048,7 +1048,7 @@ i915_error_object_create(struct drm_i915_private *i915,
struct intel_memory_region *mem = vma->obj->memory_region;
for_each_sgt_dma(dma, iter, vma->pages) {
- s = io_mapping_map_atomic_wc(>iomap, dma);
+ s = io_mapping_map_atomic_wc(>region.iomap, dma);
ret = compress_page(compress, s, dst);
io_mapping_unmap_atomic(s);
diff --git a/drivers/gpu/drm/i915/i915_query.c
b/drivers/gpu/drm/i915/i915_query.c
index 21c4c2592d6c..d16b4a6688e8 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -184,7 +184,7 @@ static int query_memregion_info(struct drm_i915_private
*dev_priv,
continue;
info.id = region->id;
- info.size = resource_size(>region);
+ info.size = region->region.size;
if
[RFC PATCH 1/3] drm: introduce new struct drm_mem_region
Move basic members of ttm_mem_type_manager into a new DRM memory region
structure. The idea is for this base structure to be nested inside
the TTM structure and later in Intel's proposed intel_memory_region.
As comments in the code suggest, the following future work can extend
the usefulness of this:
- Create common memory region types (next patch)
- Create common set of memory_region function callbacks (based on
ttm_mem_type_manager_funcs and intel_memory_regions_ops)
- Create common helpers that operate on drm_mem_region to be leveraged
by both TTM drivers and i915, reducing code duplication
- Above might start with refactoring ttm_bo_manager.c as these are
helpers for using drm_mm's range allocator and could be made to
operate on DRM structures instead of TTM ones.
- Larger goal might be to make LRU management of GEM objects common, and
migrate those fields into drm_mem_region and drm_gem_object strucures.
vmwgfx changes included here as just example of what driver updates will
look like, and can be moved later to separate patch. Other TTM drivers
need to be updated similarly.
Signed-off-by: Brian Welty
---
drivers/gpu/drm/ttm/ttm_bo.c | 34 +++
drivers/gpu/drm/ttm/ttm_bo_manager.c | 14
drivers/gpu/drm/ttm/ttm_bo_util.c | 11 +++---
drivers/gpu/drm/vmwgfx/vmwgfx_gmrid_manager.c | 8 ++---
drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c| 4 +--
include/drm/drm_mm.h | 31 +++--
include/drm/ttm/ttm_bo_api.h | 2 +-
include/drm/ttm/ttm_bo_driver.h | 16 -
8 files changed, 75 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index 58c403eda04e..45434ea513dd 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -84,8 +84,8 @@ static void ttm_mem_type_debug(struct ttm_bo_device *bdev,
struct drm_printer *p
drm_printf(p, "has_type: %d\n", man->has_type);
drm_printf(p, "use_type: %d\n", man->use_type);
drm_printf(p, "flags: 0x%08X\n", man->flags);
- drm_printf(p, "gpu_offset: 0x%08llX\n", man->gpu_offset);
- drm_printf(p, "size: %llu\n", man->size);
+ drm_printf(p, "gpu_offset: 0x%08llX\n", man->region.start);
+ drm_printf(p, "size: %llu\n", man->region.size);
drm_printf(p, "available_caching: 0x%08X\n",
man->available_caching);
drm_printf(p, "default_caching: 0x%08X\n", man->default_caching);
if (mem_type != TTM_PL_SYSTEM)
@@ -399,7 +399,7 @@ static int ttm_bo_handle_move_mem(struct ttm_buffer_object
*bo,
if (bo->mem.mm_node)
bo->offset = (bo->mem.start << PAGE_SHIFT) +
- bdev->man[bo->mem.mem_type].gpu_offset;
+ bdev->man[bo->mem.mem_type].region.start;
else
bo->offset = 0;
@@ -926,9 +926,9 @@ static int ttm_bo_add_move_fence(struct ttm_buffer_object
*bo,
struct dma_fence *fence;
int ret;
- spin_lock(>move_lock);
- fence = dma_fence_get(man->move);
- spin_unlock(>move_lock);
+ spin_lock(>region.move_lock);
+ fence = dma_fence_get(man->region.move);
+ spin_unlock(>region.move_lock);
if (fence) {
reservation_object_add_shared_fence(bo->resv, fence);
@@ -1490,9 +1490,9 @@ static int ttm_bo_force_list_clean(struct ttm_bo_device
*bdev,
}
spin_unlock(>lru_lock);
- spin_lock(>move_lock);
- fence = dma_fence_get(man->move);
- spin_unlock(>move_lock);
+ spin_lock(>region.move_lock);
+ fence = dma_fence_get(man->region.move);
+ spin_unlock(>region.move_lock);
if (fence) {
ret = dma_fence_wait(fence, false);
@@ -1535,8 +1535,8 @@ int ttm_bo_clean_mm(struct ttm_bo_device *bdev, unsigned
mem_type)
ret = (*man->func->takedown)(man);
}
- dma_fence_put(man->move);
- man->move = NULL;
+ dma_fence_put(man->region.move);
+ man->region.move = NULL;
return ret;
}
@@ -1561,7 +1561,7 @@ int ttm_bo_evict_mm(struct ttm_bo_device *bdev, unsigned
mem_type)
EXPORT_SYMBOL(ttm_bo_evict_mm);
int ttm_bo_init_mm(struct ttm_bo_device *bdev, unsigned type,
- unsigned long p_size)
+ resource_size_t p_size)
{
int ret;
struct ttm_mem_type_manager *man;
@@ -1570,10 +1570,16 @@ int ttm_bo_init_mm(struct ttm_bo_device *bdev, unsigned
type,
BUG_ON(type >= TTM_NUM_MEM_TYPES);
man = >man[type];
BUG_ON(man->has_type);
+
+ /* FIXME: add call to (new) drm_mem_region_init ? */
+ man->region.size = p_size;
+ man->region.type = type;
+ spin_lock_init(>region.move_lock);
+ man->region.move = NULL;
+
man->io_reserve_fastpath = true;
man->use_io_reserve_lru = false;
[PATCH 28/30] drm/amd/powerplay: make power limit retrieval as asic specific
From: Evan Quan
The power limit retrieval should be done per asic. Since we may
need to lookup in the pptable and that's really asic specific.
Signed-off-by: Evan Quan
Reviewed-by: Kenneth Feng
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 2 +-
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 51 +
.../gpu/drm/amd/powerplay/inc/amdgpu_smu.h| 4 +-
drivers/gpu/drm/amd/powerplay/navi10_ppt.c| 51 +
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 55 ---
5 files changed, 116 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 3f615d4624c7..330cc3258e61 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -1136,7 +1136,7 @@ static int smu_smc_table_hw_init(struct smu_context *smu,
if (ret)
return ret;
- ret = smu_get_power_limit(smu, >default_power_limit,
false);
+ ret = smu_get_power_limit(smu, >default_power_limit, true);
if (ret)
return ret;
}
diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
index c67a9914ce7b..9360f5a25b69 100644
--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
@@ -1323,6 +1323,56 @@ arcturus_get_profiling_clk_mask(struct smu_context *smu,
return 0;
}
+static int arcturus_get_power_limit(struct smu_context *smu,
+uint32_t *limit,
+bool asic_default)
+{
+ PPTable_t *pptable = smu->smu_table.driver_pptable;
+ uint32_t asic_default_power_limit;
+ int ret = 0;
+ int power_src;
+
+ if (!smu->default_power_limit ||
+ !smu->power_limit) {
+ if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
+ power_src = smu_power_get_index(smu,
SMU_POWER_SOURCE_AC);
+ if (power_src < 0)
+ return -EINVAL;
+
+ ret = smu_send_smc_msg_with_param(smu,
SMU_MSG_GetPptLimit,
+ power_src << 16);
+ if (ret) {
+ pr_err("[%s] get PPT limit failed!", __func__);
+ return ret;
+ }
+ smu_read_smc_arg(smu, _default_power_limit);
+ } else {
+ /* the last hope to figure out the ppt limit */
+ if (!pptable) {
+ pr_err("Cannot get PPT limit due to pptable
missing!");
+ return -EINVAL;
+ }
+ asic_default_power_limit =
+ pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
+ }
+
+ if (smu->od_enabled) {
+ asic_default_power_limit *= (100 +
smu->smu_table.TDPODLimit);
+ asic_default_power_limit /= 100;
+ }
+
+ smu->default_power_limit = asic_default_power_limit;
+ smu->power_limit = asic_default_power_limit;
+ }
+
+ if (asic_default)
+ *limit = smu->default_power_limit;
+ else
+ *limit = smu->power_limit;
+
+ return 0;
+}
+
static void arcturus_dump_pptable(struct smu_context *smu)
{
struct smu_table_context *table_context = >smu_table;
@@ -1788,6 +1838,7 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
.get_profiling_clk_mask = arcturus_get_profiling_clk_mask,
/* debug (internal used) */
.dump_pptable = arcturus_dump_pptable,
+ .get_power_limit = arcturus_get_power_limit,
};
void arcturus_set_ppt_funcs(struct smu_context *smu)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 519aeac706a5..093e70fe684d 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -447,6 +447,7 @@ struct pptable_funcs {
int (*set_default_od_settings)(struct smu_context *smu, bool
initialize);
int (*set_performance_level)(struct smu_context *smu, enum
amd_dpm_forced_level level);
void (*dump_pptable)(struct smu_context *smu);
+ int (*get_power_limit)(struct smu_context *smu, uint32_t *limit, bool
asic_default);
};
struct smu_funcs
@@ -479,7 +480,6 @@ struct smu_funcs
int (*set_allowed_mask)(struct smu_context *smu);
int (*get_enabled_mask)(struct smu_context *smu, uint32_t
*feature_mask, uint32_t num);
int (*notify_display_change)(struct smu_context *smu);
- int (*get_power_limit)(struct smu_context *smu, uint32_t
[PATCH 22/30] drm/amd/powerplay: add missing arcturus feature maps
From: Evan Quan
Add missing feature maps for arcturus.
Signed-off-by: Evan Quan
Reviewed-by: Kevin Wang
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
index 2b6dfc7cfe1a..203fcb7cd724 100644
--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
@@ -43,6 +43,8 @@
#define MSG_MAP(msg, index) \
[SMU_MSG_##msg] = {1, (index)}
+#define ARCTURUS_FEA_MAP(smu_feature, arcturus_feature) \
+ [smu_feature] = {1, (arcturus_feature)}
#define SMU_FEATURES_LOW_MASK0x
#define SMU_FEATURES_LOW_SHIFT 0
@@ -125,12 +127,15 @@ static struct smu_11_0_cmn2aisc_mapping
arcturus_feature_mask_map[SMU_FEATURE_CO
FEA_MAP(DPM_GFXCLK),
FEA_MAP(DPM_UCLK),
FEA_MAP(DPM_SOCCLK),
+ FEA_MAP(DPM_FCLK),
FEA_MAP(DPM_MP0CLK),
FEA_MAP(DS_GFXCLK),
FEA_MAP(DS_SOCCLK),
FEA_MAP(DS_LCLK),
+ FEA_MAP(DS_FCLK),
FEA_MAP(DS_UCLK),
FEA_MAP(GFX_ULV),
+ ARCTURUS_FEA_MAP(SMU_FEATURE_VCN_PG_BIT, FEATURE_DPM_VCN_BIT),
FEA_MAP(RSMU_SMN_CG),
FEA_MAP(PPT),
FEA_MAP(TDC),
--
2.20.1
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[PATCH 21/30] drm/amd/powerplay: support fan speed retrieval on arcturus
From: Evan Quan
Support arcturus fan speed retrieval.
Signed-off-by: Evan Quan
Reviewed-by: Kevin Wang
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 40
1 file changed, 40 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
index 3a702110d9bc..2b6dfc7cfe1a 100644
--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
@@ -994,6 +994,44 @@ static int arcturus_read_sensor(struct smu_context *smu,
return ret;
}
+static int arcturus_get_fan_speed_rpm(struct smu_context *smu,
+ uint32_t *speed)
+{
+ SmuMetrics_t metrics;
+ int ret = 0;
+
+ if (!speed)
+ return -EINVAL;
+
+ ret = arcturus_get_metrics_table(smu, );
+ if (ret)
+ return ret;
+
+ *speed = metrics.CurrFanSpeed;
+
+ return ret;
+}
+
+static int arcturus_get_fan_speed_percent(struct smu_context *smu,
+ uint32_t *speed)
+{
+ PPTable_t *pptable = smu->smu_table.driver_pptable;
+ uint32_t percent, current_rpm;
+ int ret = 0;
+
+ if (!speed)
+ return -EINVAL;
+
+ ret = arcturus_get_fan_speed_rpm(smu, _rpm);
+ if (ret)
+ return ret;
+
+ percent = current_rpm * 100 / pptable->FanMaximumRpm;
+ *speed = percent > 100 ? 100 : percent;
+
+ return ret;
+}
+
static int arcturus_get_current_clk_freq_by_table(struct smu_context *smu,
enum smu_clk_type clk_type,
uint32_t *value)
@@ -1475,6 +1513,8 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
.print_clk_levels = arcturus_print_clk_levels,
.force_clk_levels = arcturus_force_clk_levels,
.read_sensor = arcturus_read_sensor,
+ .get_fan_speed_percent = arcturus_get_fan_speed_percent,
+ .get_fan_speed_rpm = arcturus_get_fan_speed_rpm,
/* debug (internal used) */
.dump_pptable = arcturus_dump_pptable,
};
--
2.20.1
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[PATCH 13/30] drm/amd/powerplay: add new sensor type for VCN powergate status
From: Evan Quan
VCN is widely used in new ASICs and different from tranditional
UVD and VCE.
Signed-off-by: Evan Quan
Reviewed-by: Kenneth Feng
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/include/kgd_pp_interface.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index 95edc3d3a9c4..bba1291ae405 100644
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -123,6 +123,7 @@ enum amd_pp_sensors {
AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK,
AMDGPU_PP_SENSOR_MIN_FAN_RPM,
AMDGPU_PP_SENSOR_MAX_FAN_RPM,
+ AMDGPU_PP_SENSOR_VCN_POWER_STATE,
};
enum amd_pp_task {
--
2.20.1
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[PATCH 24/30] drm/amd/powerplay: remove redundancy debug log in smu
From: Kevin Wang
remove redundacy debug log in smu.
eg:
[ 6897.969447] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
[ 6897.969448] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
[ 6897.969448] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
[ 6899.024114] amdgpu: [powerplay] Unsupported SMU message: 38
[ 6899.024151] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
[ 6899.024151] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
[ 6899.024152] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
[ 6900.078296] amdgpu: [powerplay] Unsupported SMU message: 38
[ 6900.078332] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
[ 6900.078332] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
[ 6900.078333] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
[ 6901.133230] amdgpu: [powerplay] Unsupported SMU message: 38
Signed-off-by: Kevin Wang
Reviewed-by: Kenneth Feng
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
index eaca0381e8bd..30317cf9dc9a 100644
--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
@@ -181,10 +181,8 @@ static int arcturus_get_smu_msg_index(struct smu_context
*smc, uint32_t index)
return -EINVAL;
mapping = arcturus_message_map[index];
- if (!(mapping.valid_mapping)) {
- pr_warn("Unsupported SMU message: %d\n", index);
+ if (!(mapping.valid_mapping))
return -EINVAL;
- }
return mapping.map_to;
}
--
2.20.1
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[PATCH 23/30] drm/amd/powerplay: correct the bitmask used in arcturus
From: Evan Quan
Those bitmask prefixed by "SMU_" should be used.
Signed-off-by: Evan Quan
Reviewed-by: Kevin Wang
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
index 203fcb7cd724..eaca0381e8bd 100644
--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
@@ -403,7 +403,7 @@ static int arcturus_set_default_dpm_table(struct
smu_context *smu)
/* socclk */
single_dpm_table = &(dpm_table->soc_table);
- if (smu_feature_is_enabled(smu, FEATURE_DPM_SOCCLK_BIT)) {
+ if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
PPCLK_SOCCLK);
if (ret) {
@@ -418,7 +418,7 @@ static int arcturus_set_default_dpm_table(struct
smu_context *smu)
/* gfxclk */
single_dpm_table = &(dpm_table->gfx_table);
- if (smu_feature_is_enabled(smu, FEATURE_DPM_GFXCLK_BIT)) {
+ if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
PPCLK_GFXCLK);
if (ret) {
@@ -433,7 +433,7 @@ static int arcturus_set_default_dpm_table(struct
smu_context *smu)
/* memclk */
single_dpm_table = &(dpm_table->mem_table);
- if (smu_feature_is_enabled(smu, FEATURE_DPM_UCLK_BIT)) {
+ if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
PPCLK_UCLK);
if (ret) {
@@ -448,7 +448,7 @@ static int arcturus_set_default_dpm_table(struct
smu_context *smu)
/* fclk */
single_dpm_table = &(dpm_table->fclk_table);
- if (smu_feature_is_enabled(smu,FEATURE_DPM_FCLK_BIT)) {
+ if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
PPCLK_FCLK);
if (ret) {
--
2.20.1
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[PATCH 25/30] drm/amd/powerplay: fix arcturus real-time clock frequency retrieval
From: Evan Quan
Make sure we can still get the accurate gfxclk/uclk/socclk frequency
even on dpm disabled.
Signed-off-by: Evan Quan
Reviewed-by: Kenneth Feng
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 30 +++-
1 file changed, 29 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
index 30317cf9dc9a..1b6d41c2462f 100644
--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
@@ -1053,7 +1053,35 @@ static int arcturus_get_current_clk_freq_by_table(struct
smu_context *smu,
if (ret)
return ret;
- *value = metrics.CurrClock[clk_id];
+ switch (clk_id) {
+ case PPCLK_GFXCLK:
+ /*
+* CurrClock[clk_id] can provide accurate
+* output only when the dpm feature is enabled.
+* We can use Average_* for dpm disabled case.
+* But this is available for gfxclk/uclk/socclk.
+*/
+ if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT))
+ *value = metrics.CurrClock[PPCLK_GFXCLK];
+ else
+ *value = metrics.AverageGfxclkFrequency;
+ break;
+ case PPCLK_UCLK:
+ if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
+ *value = metrics.CurrClock[PPCLK_UCLK];
+ else
+ *value = metrics.AverageUclkFrequency;
+ break;
+ case PPCLK_SOCCLK:
+ if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT))
+ *value = metrics.CurrClock[PPCLK_SOCCLK];
+ else
+ *value = metrics.AverageSocclkFrequency;
+ break;
+ default:
+ *value = metrics.CurrClock[clk_id];
+ break;
+ }
return ret;
}
--
2.20.1
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[PATCH 27/30] drm/amd/powerplay: correct arcturus current clock level calculation
From: Evan Quan
There may be 1Mhz delta between target and actual frequency. That
should be taken into consideration for current level check.
Signed-off-by: Evan Quan
Reviewed-by: Kenneth Feng
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 35 +++-
1 file changed, 27 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
index fa2845b9330b..c67a9914ce7b 100644
--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
@@ -51,6 +51,9 @@
#define SMU_FEATURES_HIGH_MASK 0x
#define SMU_FEATURES_HIGH_SHIFT 32
+/* possible frequency drift (1Mhz) */
+#define EPSILON1
+
static struct smu_11_0_cmn2aisc_mapping
arcturus_message_map[SMU_MSG_MAX_COUNT] = {
MSG_MAP(TestMessage, PPSMC_MSG_TestMessage),
MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion),
@@ -565,6 +568,12 @@ static int arcturus_get_clk_table(struct smu_context *smu,
return 0;
}
+static int arcturus_freqs_in_same_level(int32_t frequency1,
+ int32_t frequency2)
+{
+ return (abs(frequency1 - frequency2) <= EPSILON);
+}
+
static int arcturus_print_clk_levels(struct smu_context *smu,
enum smu_clk_type type, char *buf)
{
@@ -595,8 +604,9 @@ static int arcturus_print_clk_levels(struct smu_context
*smu,
for (i = 0; i < clocks.num_levels; i++)
size += sprintf(buf + size, "%d: %uMhz %s\n", i,
clocks.data[i].clocks_in_khz / 1000,
- (clocks.data[i].clocks_in_khz == now *
10)
- ? "*" : "");
+ arcturus_freqs_in_same_level(
+ clocks.data[i].clocks_in_khz / 1000,
+ now / 100) ? "*" : "");
break;
case SMU_MCLK:
@@ -616,8 +626,9 @@ static int arcturus_print_clk_levels(struct smu_context
*smu,
for (i = 0; i < clocks.num_levels; i++)
size += sprintf(buf + size, "%d: %uMhz %s\n",
i, clocks.data[i].clocks_in_khz / 1000,
- (clocks.data[i].clocks_in_khz == now * 10)
- ? "*" : "");
+ arcturus_freqs_in_same_level(
+ clocks.data[i].clocks_in_khz / 1000,
+ now / 100) ? "*" : "");
break;
case SMU_SOCCLK:
@@ -637,8 +648,9 @@ static int arcturus_print_clk_levels(struct smu_context
*smu,
for (i = 0; i < clocks.num_levels; i++)
size += sprintf(buf + size, "%d: %uMhz %s\n",
i, clocks.data[i].clocks_in_khz / 1000,
- (clocks.data[i].clocks_in_khz == now * 10)
- ? "*" : "");
+ arcturus_freqs_in_same_level(
+ clocks.data[i].clocks_in_khz / 1000,
+ now / 100) ? "*" : "");
break;
case SMU_FCLK:
@@ -649,11 +661,18 @@ static int arcturus_print_clk_levels(struct smu_context
*smu,
}
single_dpm_table = &(dpm_table->fclk_table);
+ ret = arcturus_get_clk_table(smu, , single_dpm_table);
+ if (ret) {
+ pr_err("Attempt to get fclk levels Failed!");
+ return ret;
+ }
+
for (i = 0; i < single_dpm_table->count; i++)
size += sprintf(buf + size, "%d: %uMhz %s\n",
i, single_dpm_table->dpm_levels[i].value,
- (single_dpm_table->dpm_levels[i].value == now /
100)
- ? "*" : "");
+ arcturus_freqs_in_same_level(
+ clocks.data[i].clocks_in_khz / 1000,
+ now / 100) ? "*" : "");
break;
default:
--
2.20.1
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[PATCH 15/30] drm/amd/powerplay: support VCN powergate status retrieval for SW SMU
From: Evan Quan Commonly used for VCN powergate status retrieval for SW SMU. Signed-off-by: Evan Quan Reviewed-by: Kenneth Feng Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c index 8ebfe41a4dc9..3f615d4624c7 100644 --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c @@ -424,6 +424,10 @@ int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor, *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0; *size = 4; break; + case AMDGPU_PP_SENSOR_VCN_POWER_STATE: + *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT) ? 1 : 0; + *size = 4; + break; default: ret = -EINVAL; break; -- 2.20.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 16/30] drm/amd/powerplay: correct Navi10 VCN powergate control
From: Evan Quan
No VCN DPM bit check as that's different from VCN PG. Also
no extra check for possible double enablement/disablement
as that's already done by VCN.
Signed-off-by: Evan Quan
Reviewed-by: Kenneth Feng
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 26 --
1 file changed, 9 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 9dd96d8b8dd5..01d534c8442e 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -591,27 +591,19 @@ static int navi10_set_default_dpm_table(struct
smu_context *smu)
static int navi10_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
{
int ret = 0;
- struct smu_power_context *smu_power = >smu_power;
- struct smu_power_gate *power_gate = _power->power_gate;
- if (enable && power_gate->uvd_gated) {
- if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT)) {
- ret = smu_send_smc_msg_with_param(smu,
SMU_MSG_PowerUpVcn, 1);
- if (ret)
- return ret;
- }
- power_gate->uvd_gated = false;
+ if (enable) {
+ ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1);
+ if (ret)
+ return ret;
} else {
- if (!enable && !power_gate->uvd_gated) {
- if (smu_feature_is_enabled(smu,
SMU_FEATURE_DPM_UVD_BIT)) {
- ret = smu_send_smc_msg(smu,
SMU_MSG_PowerDownVcn);
- if (ret)
- return ret;
- }
- power_gate->uvd_gated = true;
- }
+ ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn);
+ if (ret)
+ return ret;
}
+ smu_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, enable);
+
return 0;
}
--
2.20.1
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[PATCH 05/30] drm/amd/powerplay: update arcturus_ppt.c/h V3
From: Evan Quan
Arcturus ASIC specific powerplay interfaces.
V2: correct SMU msg naming
drop unnecessary debugs
V3: rebase (Alex)
Signed-off-by: Evan Quan
Reviewed-by: Kevin Wang
Reviewed-by: Le Ma
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 1193 -
drivers/gpu/drm/amd/powerplay/arcturus_ppt.h | 44 +
drivers/gpu/drm/amd/powerplay/inc/smu_types.h |2 +-
3 files changed, 1237 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
index 7d680f33ce3c..b284ebcbe545 100644
--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
@@ -33,12 +33,22 @@
#include "atom.h"
#include "power_state.h"
#include "arcturus_ppt.h"
+#include "smu_v11_0_pptable.h"
#include "arcturus_ppsmc.h"
#include "nbio/nbio_7_4_sh_mask.h"
+#define CTF_OFFSET_EDGE5
+#define CTF_OFFSET_HOTSPOT 5
+#define CTF_OFFSET_HBM 5
+
#define MSG_MAP(msg, index) \
[SMU_MSG_##msg] = {1, (index)}
+#define SMU_FEATURES_LOW_MASK0x
+#define SMU_FEATURES_LOW_SHIFT 0
+#define SMU_FEATURES_HIGH_MASK 0x
+#define SMU_FEATURES_HIGH_SHIFT 32
+
static struct smu_11_0_cmn2aisc_mapping
arcturus_message_map[SMU_MSG_MAX_COUNT] = {
MSG_MAP(TestMessage, PPSMC_MSG_TestMessage),
MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion),
@@ -80,7 +90,7 @@ static struct smu_11_0_cmn2aisc_mapping
arcturus_message_map[SMU_MSG_MAX_COUNT]
MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit),
MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit),
MSG_MAP(PowerUpVcn0, PPSMC_MSG_PowerUpVcn0),
- MSG_MAP(PowerDownVcn01, PPSMC_MSG_PowerDownVcn01),
+ MSG_MAP(PowerDownVcn0, PPSMC_MSG_PowerDownVcn0),
MSG_MAP(PowerUpVcn1, PPSMC_MSG_PowerUpVcn1),
MSG_MAP(PowerDownVcn1, PPSMC_MSG_PowerDownVcn1),
MSG_MAP(PrepareMp1ForUnload,
PPSMC_MSG_PrepareMp1ForUnload),
@@ -99,6 +109,65 @@ static struct smu_11_0_cmn2aisc_mapping
arcturus_message_map[SMU_MSG_MAX_COUNT]
MSG_MAP(SetMemoryChannelEnable,
PPSMC_MSG_SetMemoryChannelEnable),
};
+static struct smu_11_0_cmn2aisc_mapping arcturus_clk_map[SMU_CLK_COUNT] = {
+ CLK_MAP(GFXCLK, PPCLK_GFXCLK),
+ CLK_MAP(SCLK, PPCLK_GFXCLK),
+ CLK_MAP(SOCCLK, PPCLK_SOCCLK),
+ CLK_MAP(FCLK, PPCLK_FCLK),
+ CLK_MAP(UCLK, PPCLK_UCLK),
+ CLK_MAP(MCLK, PPCLK_UCLK),
+ CLK_MAP(DCLK, PPCLK_DCLK),
+ CLK_MAP(VCLK, PPCLK_VCLK),
+};
+
+static struct smu_11_0_cmn2aisc_mapping
arcturus_feature_mask_map[SMU_FEATURE_COUNT] = {
+ FEA_MAP(DPM_PREFETCHER),
+ FEA_MAP(DPM_GFXCLK),
+ FEA_MAP(DPM_UCLK),
+ FEA_MAP(DPM_SOCCLK),
+ FEA_MAP(DPM_MP0CLK),
+ FEA_MAP(DS_GFXCLK),
+ FEA_MAP(DS_SOCCLK),
+ FEA_MAP(DS_LCLK),
+ FEA_MAP(DS_UCLK),
+ FEA_MAP(GFX_ULV),
+ FEA_MAP(RSMU_SMN_CG),
+ FEA_MAP(PPT),
+ FEA_MAP(TDC),
+ FEA_MAP(APCC_PLUS),
+ FEA_MAP(VR0HOT),
+ FEA_MAP(VR1HOT),
+ FEA_MAP(FW_CTF),
+ FEA_MAP(FAN_CONTROL),
+ FEA_MAP(THERMAL),
+ FEA_MAP(OUT_OF_BAND_MONITOR),
+ FEA_MAP(TEMP_DEPENDENT_VMIN),
+};
+
+static struct smu_11_0_cmn2aisc_mapping arcturus_table_map[SMU_TABLE_COUNT] = {
+ TAB_MAP(PPTABLE),
+ TAB_MAP(AVFS),
+ TAB_MAP(AVFS_PSM_DEBUG),
+ TAB_MAP(AVFS_FUSE_OVERRIDE),
+ TAB_MAP(PMSTATUSLOG),
+ TAB_MAP(SMU_METRICS),
+ TAB_MAP(DRIVER_SMU_CONFIG),
+ TAB_MAP(OVERDRIVE),
+};
+
+static struct smu_11_0_cmn2aisc_mapping
arcturus_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
+ PWR_MAP(AC),
+ PWR_MAP(DC),
+};
+
+static struct smu_11_0_cmn2aisc_mapping
arcturus_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
+ WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,
WORKLOAD_PPLIB_DEFAULT_BIT),
+ WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,
WORKLOAD_PPLIB_POWER_SAVING_BIT),
+ WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,
WORKLOAD_PPLIB_VIDEO_BIT),
+ WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,
WORKLOAD_PPLIB_CUSTOM_BIT),
+ WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,
WORKLOAD_PPLIB_CUSTOM_BIT),
+};
+
static int arcturus_get_smu_msg_index(struct smu_context *smc, uint32_t index)
{
struct smu_11_0_cmn2aisc_mapping mapping;
@@ -115,12 +184,1134 @@ static int arcturus_get_smu_msg_index(struct
smu_context *smc, uint32_t index)
return mapping.map_to;
}
+static int arcturus_get_smu_clk_index(struct smu_context *smc, uint32_t index)
+{
+ struct smu_11_0_cmn2aisc_mapping
[PATCH 06/30] drm/amd/powerplay: enable SW SMU routine support for arcturus
From: Evan Quan
Enable arcturus SW SMU routines.
Signed-off-by: Evan Quan
Reviewed-by: Kenneth Feng
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 49 +-
1 file changed, 30 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index c45fa2fb4da9..8ebfe41a4dc9 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -476,7 +476,7 @@ bool is_support_sw_smu(struct amdgpu_device *adev)
{
if (adev->asic_type == CHIP_VEGA20)
return (amdgpu_dpm == 2) ? true: false;
- else if (adev->asic_type >= CHIP_NAVI10)
+ else if (adev->asic_type >= CHIP_ARCTURUS)
return true;
else
return false;
@@ -708,6 +708,7 @@ static int smu_set_funcs(struct amdgpu_device *adev)
case CHIP_VEGA20:
case CHIP_NAVI10:
case CHIP_NAVI14:
+ case CHIP_ARCTURUS:
if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
smu->od_enabled = true;
smu_v11_0_set_smu_funcs(smu);
@@ -1013,9 +1014,11 @@ static int smu_smc_table_hw_init(struct smu_context *smu,
return 0;
}
- ret = smu_init_display_count(smu, 0);
- if (ret)
- return ret;
+ if (adev->asic_type != CHIP_ARCTURUS) {
+ ret = smu_init_display_count(smu, 0);
+ if (ret)
+ return ret;
+ }
if (initialize) {
/* get boot_values from vbios to set revision, gfxclk, and etc.
*/
@@ -1091,17 +1094,19 @@ static int smu_smc_table_hw_init(struct smu_context
*smu,
if (ret)
return ret;
- ret = smu_notify_display_change(smu);
- if (ret)
- return ret;
+ if (adev->asic_type != CHIP_ARCTURUS) {
+ ret = smu_notify_display_change(smu);
+ if (ret)
+ return ret;
- /*
-* Set min deep sleep dce fclk with bootup value from vbios via
-* SetMinDeepSleepDcefclk MSG.
-*/
- ret = smu_set_min_dcef_deep_sleep(smu);
- if (ret)
- return ret;
+ /*
+* Set min deep sleep dce fclk with bootup value from vbios via
+* SetMinDeepSleepDcefclk MSG.
+*/
+ ret = smu_set_min_dcef_deep_sleep(smu);
+ if (ret)
+ return ret;
+ }
/*
* Set initialized values (get from vbios) to dpm tables context such as
@@ -1212,14 +1217,20 @@ static int smu_hw_init(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct smu_context *smu = >smu;
- if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
- ret = smu_check_fw_status(smu);
- if (ret) {
- pr_err("SMC firmware status is not correct\n");
- return ret;
+ if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
+ if (adev->asic_type < CHIP_NAVI10) {
+ ret = smu_load_microcode(smu);
+ if (ret)
+ return ret;
}
}
+ ret = smu_check_fw_status(smu);
+ if (ret) {
+ pr_err("SMC firmware status is not correct\n");
+ return ret;
+ }
+
if (!smu->pm_enabled)
return 0;
--
2.20.1
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[PATCH 29/30] drm/amdgpu: correct irq type used for sdma ecc
From: Hawking Zhang
we should pass irq type, instead of irq client id,
to irq_get/put interface
Signed-off-by: Hawking Zhang
Reviewed-by: Feifei Xu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 560d6038bbb3..36dc5025c461 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -1702,7 +1702,7 @@ static int sdma_v4_0_late_init(void *handle)
resume:
for (i = 0; i < adev->sdma.num_instances; i++) {
r = amdgpu_irq_get(adev, >sdma.ecc_irq,
- sdma_v4_0_seq_to_irq_id(i));
+ AMDGPU_SDMA_IRQ_INSTANCE0 + i);
if (r)
goto irq;
}
@@ -1846,7 +1846,7 @@ static int sdma_v4_0_hw_fini(void *handle)
for (i = 0; i < adev->sdma.num_instances; i++) {
amdgpu_irq_put(adev, >sdma.ecc_irq,
- sdma_v4_0_seq_to_irq_id(i));
+ AMDGPU_SDMA_IRQ_INSTANCE0 + i);
}
sdma_v4_0_ctx_switch_enable(adev, false);
--
2.20.1
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[PATCH 20/30] drm/amd/powerplay: support real-time clock retrieval on arcturus
From: Evan Quan
Enable arcturus real-time clock retrieval.
Signed-off-by: Evan Quan
Reviewed-by: Kevin Wang
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 24
1 file changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
index 1dbb917fb916..3a702110d9bc 100644
--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
@@ -994,6 +994,29 @@ static int arcturus_read_sensor(struct smu_context *smu,
return ret;
}
+static int arcturus_get_current_clk_freq_by_table(struct smu_context *smu,
+ enum smu_clk_type clk_type,
+ uint32_t *value)
+{
+ static SmuMetrics_t metrics;
+ int ret = 0, clk_id = 0;
+
+ if (!value)
+ return -EINVAL;
+
+ clk_id = smu_clk_get_index(smu, clk_type);
+ if (clk_id < 0)
+ return -EINVAL;
+
+ ret = arcturus_get_metrics_table(smu, );
+ if (ret)
+ return ret;
+
+ *value = metrics.CurrClock[clk_id];
+
+ return ret;
+}
+
static void arcturus_dump_pptable(struct smu_context *smu)
{
struct smu_table_context *table_context = >smu_table;
@@ -1448,6 +1471,7 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
.set_default_dpm_table = arcturus_set_default_dpm_table,
.populate_umd_state_clk = arcturus_populate_umd_state_clk,
.get_thermal_temperature_range = arcturus_get_thermal_temperature_range,
+ .get_current_clk_freq_by_table = arcturus_get_current_clk_freq_by_table,
.print_clk_levels = arcturus_print_clk_levels,
.force_clk_levels = arcturus_force_clk_levels,
.read_sensor = arcturus_read_sensor,
--
2.20.1
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[PATCH 09/30] drm/amdgpu: correct VCN powergate routine for acturus
From: Evan Quan
Arcturus VCN should powergate in the way as Navi.
Signed-off-by: Evan Quan
Reviewed-by: Le Ma
Reviewed-by: Kenneth Feng
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index be34bdc47174..21ca8e0ab8b6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -304,7 +304,7 @@ static void amdgpu_vcn_idle_work_handler(struct work_struct
*work)
if (fences == 0) {
amdgpu_gfx_off_ctrl(adev, true);
- if (adev->asic_type < CHIP_NAVI10 && adev->pm.dpm_enabled)
+ if (adev->asic_type < CHIP_ARCTURUS && adev->pm.dpm_enabled)
amdgpu_dpm_enable_uvd(adev, false);
else
amdgpu_device_ip_set_powergating_state(adev,
AMD_IP_BLOCK_TYPE_VCN,
@@ -321,7 +321,7 @@ void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
if (set_clocks) {
amdgpu_gfx_off_ctrl(adev, false);
- if (adev->asic_type < CHIP_NAVI10 && adev->pm.dpm_enabled)
+ if (adev->asic_type < CHIP_ARCTURUS && adev->pm.dpm_enabled)
amdgpu_dpm_enable_uvd(adev, true);
else
amdgpu_device_ip_set_powergating_state(adev,
AMD_IP_BLOCK_TYPE_VCN,
--
2.20.1
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[PATCH 26/30] drm/amd/powerplay: support UMD PSTATE settings on arcturus
From: Evan Quan
Enable arcturus UMD PSTATE support.
Signed-off-by: Evan Quan
Reviewed-by: Kenneth Feng
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 229 ++-
1 file changed, 225 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
index 1b6d41c2462f..fa2845b9330b 100644
--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
@@ -664,15 +664,15 @@ static int arcturus_print_clk_levels(struct smu_context
*smu,
}
static int arcturus_upload_dpm_level(struct smu_context *smu, bool max,
- uint32_t feature_mask)
+uint32_t feature_mask)
{
- struct arcturus_dpm_table *dpm_table;
struct arcturus_single_dpm_table *single_dpm_table;
+ struct arcturus_dpm_table *dpm_table =
+ smu->smu_dpm.dpm_context;
uint32_t freq;
int ret = 0;
- dpm_table = smu->smu_dpm.dpm_context;
- if (smu_feature_is_enabled(smu, FEATURE_DPM_GFXCLK_BIT) &&
+ if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
(feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
single_dpm_table = &(dpm_table->gfx_table);
freq = max ? single_dpm_table->dpm_state.soft_max_level :
@@ -687,6 +687,36 @@ static int arcturus_upload_dpm_level(struct smu_context
*smu, bool max,
}
}
+ if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
+ (feature_mask & FEATURE_DPM_UCLK_MASK)) {
+ single_dpm_table = &(dpm_table->mem_table);
+ freq = max ? single_dpm_table->dpm_state.soft_max_level :
+ single_dpm_table->dpm_state.soft_min_level;
+ ret = smu_send_smc_msg_with_param(smu,
+ (max ? SMU_MSG_SetSoftMaxByFreq :
SMU_MSG_SetSoftMinByFreq),
+ (PPCLK_UCLK << 16) | (freq & 0x));
+ if (ret) {
+ pr_err("Failed to set soft %s memclk !\n",
+ max ? "max" : "min");
+ return ret;
+ }
+ }
+
+ if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
+ (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
+ single_dpm_table = &(dpm_table->soc_table);
+ freq = max ? single_dpm_table->dpm_state.soft_max_level :
+ single_dpm_table->dpm_state.soft_min_level;
+ ret = smu_send_smc_msg_with_param(smu,
+ (max ? SMU_MSG_SetSoftMaxByFreq :
SMU_MSG_SetSoftMinByFreq),
+ (PPCLK_SOCCLK << 16) | (freq & 0x));
+ if (ret) {
+ pr_err("Failed to set soft %s socclk !\n",
+ max ? "max" : "min");
+ return ret;
+ }
+ }
+
return ret;
}
@@ -1086,6 +1116,194 @@ static int
arcturus_get_current_clk_freq_by_table(struct smu_context *smu,
return ret;
}
+static uint32_t arcturus_find_lowest_dpm_level(struct
arcturus_single_dpm_table *table)
+{
+ uint32_t i;
+
+ for (i = 0; i < table->count; i++) {
+ if (table->dpm_levels[i].enabled)
+ break;
+ }
+ if (i >= table->count) {
+ i = 0;
+ table->dpm_levels[i].enabled = true;
+ }
+
+ return i;
+}
+
+static uint32_t arcturus_find_highest_dpm_level(struct
arcturus_single_dpm_table *table)
+{
+ int i = 0;
+
+ if (table->count <= 0) {
+ pr_err("[%s] DPM Table has no entry!", __func__);
+ return 0;
+ }
+ if (table->count > MAX_DPM_NUMBER) {
+ pr_err("[%s] DPM Table has too many entries!", __func__);
+ return MAX_DPM_NUMBER - 1;
+ }
+
+ for (i = table->count - 1; i >= 0; i--) {
+ if (table->dpm_levels[i].enabled)
+ break;
+ }
+ if (i < 0) {
+ i = 0;
+ table->dpm_levels[i].enabled = true;
+ }
+
+ return i;
+}
+
+
+
+static int arcturus_force_dpm_limit_value(struct smu_context *smu, bool
highest)
+{
+ struct arcturus_dpm_table *dpm_table =
+ (struct arcturus_dpm_table *)smu->smu_dpm.dpm_context;
+ uint32_t soft_level;
+ int ret = 0;
+
+ /* gfxclk */
+ if (highest)
+ soft_level =
arcturus_find_highest_dpm_level(&(dpm_table->gfx_table));
+ else
+ soft_level =
arcturus_find_lowest_dpm_level(&(dpm_table->gfx_table));
+
+ dpm_table->gfx_table.dpm_state.soft_min_level =
+ dpm_table->gfx_table.dpm_state.soft_max_level =
+ dpm_table->gfx_table.dpm_levels[soft_level].value;
+
+
[PATCH 07/30] drm/amd/powerplay: initialize arcturus MP1 and THM base address
From: Evan Quan Initialize base address for those IPs which are used in powerplay. Signed-off-by: Evan Quan Reviewed-by: Kenneth Feng Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/arct_reg_init.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/arct_reg_init.c b/drivers/gpu/drm/amd/amdgpu/arct_reg_init.c index 51b8cdffb196..4853899b1824 100644 --- a/drivers/gpu/drm/amd/amdgpu/arct_reg_init.c +++ b/drivers/gpu/drm/amd/amdgpu/arct_reg_init.c @@ -38,6 +38,7 @@ int arct_reg_base_init(struct amdgpu_device *adev) adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i])); adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIF0_BASE.instance[i])); adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); + adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i])); adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i])); adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i])); @@ -50,6 +51,7 @@ int arct_reg_base_init(struct amdgpu_device *adev) adev->reg_offset[SDMA6_HWIP][i] = (uint32_t *)(&(SDMA6_BASE.instance[i])); adev->reg_offset[SDMA7_HWIP][i] = (uint32_t *)(&(SDMA7_BASE.instance[i])); adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i])); + adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i])); } return 0; } -- 2.20.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 30/30] drm/amd/powerplay: determine the features to enable by pptable only
From: Evan Quan Per current logics, the features to enable are determined together by driver and pptable. This is not efficient in co-debug with firmware team. Signed-off-by: Evan Quan Reviewed-by: Kenneth Feng Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c index 9360f5a25b69..215f7173fca8 100644 --- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c @@ -327,7 +327,6 @@ static int arcturus_allocate_dpm_context(struct smu_context *smu) return 0; } -#define FEATURE_MASK(feature) (1ULL << feature) static int arcturus_get_allowed_feature_mask(struct smu_context *smu, uint32_t *feature_mask, uint32_t num) @@ -335,9 +334,8 @@ arcturus_get_allowed_feature_mask(struct smu_context *smu, if (num > 2) return -EINVAL; - memset(feature_mask, 0, sizeof(uint32_t) * num); - - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT); + /* pptable will handle the features to enable */ + memset(feature_mask, 0xFF, sizeof(uint32_t) * num); return 0; } -- 2.20.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 17/30] drm/amd/powerplay: correct UVD/VCE/VCN power status retrieval
From: Evan Quan
VCN should be used for Vega20 later ASICs while UVD and VCE
are for previous ASICs.
Signed-off-by: Evan Quan
Reviewed-by: Kenneth Feng
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 56 +-
1 file changed, 36 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 783cd0192d33..6cff61802400 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -3070,28 +3070,44 @@ static int amdgpu_debugfs_pm_info_pp(struct seq_file
*m, struct amdgpu_device *a
if (!amdgpu_dpm_read_sensor(adev,
AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, (void *), ))
seq_printf(m, "SMC Feature Mask: 0x%016llx\n", value64);
- /* UVD clocks */
- if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void
*), )) {
- if (!value) {
- seq_printf(m, "UVD: Disabled\n");
- } else {
- seq_printf(m, "UVD: Enabled\n");
- if (!amdgpu_dpm_read_sensor(adev,
AMDGPU_PP_SENSOR_UVD_DCLK, (void *), ))
- seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
- if (!amdgpu_dpm_read_sensor(adev,
AMDGPU_PP_SENSOR_UVD_VCLK, (void *), ))
- seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
+ if (adev->asic_type > CHIP_VEGA20) {
+ /* VCN clocks */
+ if (!amdgpu_dpm_read_sensor(adev,
AMDGPU_PP_SENSOR_VCN_POWER_STATE, (void *), )) {
+ if (!value) {
+ seq_printf(m, "VCN: Disabled\n");
+ } else {
+ seq_printf(m, "VCN: Enabled\n");
+ if (!amdgpu_dpm_read_sensor(adev,
AMDGPU_PP_SENSOR_UVD_DCLK, (void *), ))
+ seq_printf(m, "\t%u MHz (DCLK)\n",
value/100);
+ if (!amdgpu_dpm_read_sensor(adev,
AMDGPU_PP_SENSOR_UVD_VCLK, (void *), ))
+ seq_printf(m, "\t%u MHz (VCLK)\n",
value/100);
+ }
}
- }
- seq_printf(m, "\n");
+ seq_printf(m, "\n");
+ } else {
+ /* UVD clocks */
+ if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER,
(void *), )) {
+ if (!value) {
+ seq_printf(m, "UVD: Disabled\n");
+ } else {
+ seq_printf(m, "UVD: Enabled\n");
+ if (!amdgpu_dpm_read_sensor(adev,
AMDGPU_PP_SENSOR_UVD_DCLK, (void *), ))
+ seq_printf(m, "\t%u MHz (DCLK)\n",
value/100);
+ if (!amdgpu_dpm_read_sensor(adev,
AMDGPU_PP_SENSOR_UVD_VCLK, (void *), ))
+ seq_printf(m, "\t%u MHz (VCLK)\n",
value/100);
+ }
+ }
+ seq_printf(m, "\n");
- /* VCE clocks */
- if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void
*), )) {
- if (!value) {
- seq_printf(m, "VCE: Disabled\n");
- } else {
- seq_printf(m, "VCE: Enabled\n");
- if (!amdgpu_dpm_read_sensor(adev,
AMDGPU_PP_SENSOR_VCE_ECCLK, (void *), ))
- seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
+ /* VCE clocks */
+ if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER,
(void *), )) {
+ if (!value) {
+ seq_printf(m, "VCE: Disabled\n");
+ } else {
+ seq_printf(m, "VCE: Enabled\n");
+ if (!amdgpu_dpm_read_sensor(adev,
AMDGPU_PP_SENSOR_VCE_ECCLK, (void *), ))
+ seq_printf(m, "\t%u MHz (ECCLK)\n",
value/100);
+ }
}
}
--
2.20.1
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[PATCH 10/30] drm/amd/powerplay: hold on the arcturus gfx dpm support in driver
From: Evan Quan As for now, only "Prefetcher" is guarded to be working from SMU firmware. Signed-off-by: Evan Quan Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c index b284ebcbe545..a0644ef267a9 100644 --- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c @@ -324,8 +324,7 @@ arcturus_get_allowed_feature_mask(struct smu_context *smu, memset(feature_mask, 0, sizeof(uint32_t) * num); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) - | FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); + *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT); return 0; } -- 2.20.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 14/30] drm/amd/powerplay: support VCN powergate status retrieval on Raven
From: Evan Quan
Enable VCN powergate status report on Raven.
Signed-off-by: Evan Quan
Reviewed-by: Kenneth Feng
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
index e32ae9d3373c..18e780f566fa 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
@@ -,6 +,7 @@ static int smu10_thermal_get_temperature(struct pp_hwmgr
*hwmgr)
static int smu10_read_sensor(struct pp_hwmgr *hwmgr, int idx,
void *value, int *size)
{
+ struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
uint32_t sclk, mclk;
int ret = 0;
@@ -1132,6 +1133,10 @@ static int smu10_read_sensor(struct pp_hwmgr *hwmgr, int
idx,
case AMDGPU_PP_SENSOR_GPU_TEMP:
*((uint32_t *)value) = smu10_thermal_get_temperature(hwmgr);
break;
+ case AMDGPU_PP_SENSOR_VCN_POWER_STATE:
+ *(uint32_t *)value = smu10_data->vcn_power_gated ? 0 : 1;
+ *size = 4;
+ break;
default:
ret = -EINVAL;
break;
@@ -1175,18 +1180,22 @@ static int smu10_powergate_sdma(struct pp_hwmgr *hwmgr,
bool gate)
static void smu10_powergate_vcn(struct pp_hwmgr *hwmgr, bool bgate)
{
+ struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
+
if (bgate) {
amdgpu_device_ip_set_powergating_state(hwmgr->adev,
AMD_IP_BLOCK_TYPE_VCN,
AMD_PG_STATE_GATE);
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_PowerDownVcn, 0);
+ smu10_data->vcn_power_gated = true;
} else {
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_PowerUpVcn, 0);
amdgpu_device_ip_set_powergating_state(hwmgr->adev,
AMD_IP_BLOCK_TYPE_VCN,
AMD_PG_STATE_UNGATE);
+ smu10_data->vcn_power_gated = false;
}
}
--
2.20.1
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[PATCH 08/30] drm/amd/powerplay: enable arcturus powerplay
From: Evan Quan Arcturus powerplay is ready to use. Signed-off-by: Evan Quan Reviewed-by: Kenneth Feng Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/soc15.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index 4405b983dd09..347a44f2757a 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -696,6 +696,7 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev) amdgpu_device_ip_block_add(adev, _virtual_ip_block); amdgpu_device_ip_block_add(adev, _v9_0_ip_block); amdgpu_device_ip_block_add(adev, _v4_0_ip_block); + amdgpu_device_ip_block_add(adev, _v11_0_ip_block); amdgpu_device_ip_block_add(adev, _v2_5_ip_block); break; default: -- 2.20.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 18/30] drm/amd/powerplay: init arcturus SMU metrics table on bootup
From: Evan Quan
Initialize arcturus SMU metrics table.
Signed-off-by: Evan Quan
Reviewed-by: Kevin Wang
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
index a0644ef267a9..5f911f092311 100644
--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
@@ -267,6 +267,8 @@ static int arcturus_get_workload_type(struct smu_context
*smu, enum PP_SMC_POWER
static int arcturus_tables_init(struct smu_context *smu, struct smu_table
*tables)
{
+ struct smu_table_context *smu_table = >smu_table;
+
SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
@@ -276,6 +278,11 @@ static int arcturus_tables_init(struct smu_context *smu,
struct smu_table *table
SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
+ smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
+ if (!smu_table->metrics_table)
+ return -ENOMEM;
+ smu_table->metrics_time = 0;
+
return 0;
}
--
2.20.1
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[PATCH 19/30] drm/amd/powerplay: support sensor reading on arcturus
From: Evan Quan
Support sensor reading for gpu loading, power and
temperatures.
Signed-off-by: Evan Quan
Reviewed-by: Kevin Wang
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 142 +++
1 file changed, 142 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
index 5f911f092311..1dbb917fb916 100644
--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
@@ -853,6 +853,147 @@ static int arcturus_get_thermal_temperature_range(struct
smu_context *smu,
return 0;
}
+static int arcturus_get_metrics_table(struct smu_context *smu,
+ SmuMetrics_t *metrics_table)
+{
+ struct smu_table_context *smu_table= >smu_table;
+ int ret = 0;
+
+ if (!smu_table->metrics_time ||
+time_after(jiffies, smu_table->metrics_time + HZ / 1000)) {
+ ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
+ (void *)smu_table->metrics_table, false);
+ if (ret) {
+ pr_info("Failed to export SMU metrics table!\n");
+ return ret;
+ }
+ smu_table->metrics_time = jiffies;
+ }
+
+ memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
+
+ return ret;
+}
+
+static int arcturus_get_current_activity_percent(struct smu_context *smu,
+enum amd_pp_sensors sensor,
+uint32_t *value)
+{
+ SmuMetrics_t metrics;
+ int ret = 0;
+
+ if (!value)
+ return -EINVAL;
+
+ ret = arcturus_get_metrics_table(smu, );
+ if (ret)
+ return ret;
+
+ switch (sensor) {
+ case AMDGPU_PP_SENSOR_GPU_LOAD:
+ *value = metrics.AverageGfxActivity;
+ break;
+ case AMDGPU_PP_SENSOR_MEM_LOAD:
+ *value = metrics.AverageUclkActivity;
+ break;
+ default:
+ pr_err("Invalid sensor for retrieving clock activity\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int arcturus_get_gpu_power(struct smu_context *smu, uint32_t *value)
+{
+ SmuMetrics_t metrics;
+ int ret = 0;
+
+ if (!value)
+ return -EINVAL;
+
+ ret = arcturus_get_metrics_table(smu, );
+ if (ret)
+ return ret;
+
+ *value = metrics.AverageSocketPower << 8;
+
+ return 0;
+}
+
+static int arcturus_thermal_get_temperature(struct smu_context *smu,
+ enum amd_pp_sensors sensor,
+ uint32_t *value)
+{
+ SmuMetrics_t metrics;
+ int ret = 0;
+
+ if (!value)
+ return -EINVAL;
+
+ ret = arcturus_get_metrics_table(smu, );
+ if (ret)
+ return ret;
+
+ switch (sensor) {
+ case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
+ *value = metrics.TemperatureHotspot *
+ SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+ break;
+ case AMDGPU_PP_SENSOR_EDGE_TEMP:
+ *value = metrics.TemperatureEdge *
+ SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+ break;
+ case AMDGPU_PP_SENSOR_MEM_TEMP:
+ *value = metrics.TemperatureHBM *
+ SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+ break;
+ default:
+ pr_err("Invalid sensor for retrieving temp\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int arcturus_read_sensor(struct smu_context *smu,
+ enum amd_pp_sensors sensor,
+ void *data, uint32_t *size)
+{
+ struct smu_table_context *table_context = >smu_table;
+ PPTable_t *pptable = table_context->driver_pptable;
+ int ret = 0;
+
+ switch (sensor) {
+ case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
+ *(uint32_t *)data = pptable->FanMaximumRpm;
+ *size = 4;
+ break;
+ case AMDGPU_PP_SENSOR_MEM_LOAD:
+ case AMDGPU_PP_SENSOR_GPU_LOAD:
+ ret = arcturus_get_current_activity_percent(smu,
+ sensor,
+ (uint32_t *)data);
+ *size = 4;
+ break;
+ case AMDGPU_PP_SENSOR_GPU_POWER:
+ ret = arcturus_get_gpu_power(smu, (uint32_t *)data);
+ *size = 4;
+ break;
+ case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
+ case AMDGPU_PP_SENSOR_EDGE_TEMP:
+ case AMDGPU_PP_SENSOR_MEM_TEMP:
+ ret = arcturus_thermal_get_temperature(smu, sensor,
+
[PATCH 12/30] drm/amdgpu: update more sdma instances irq support
From: Le Ma
Update for sdma ras ecc_irq and other minors.
Signed-off-by: Le Ma
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 77 +-
1 file changed, 27 insertions(+), 50 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index bbfb9cf2fd88..560d6038bbb3 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -295,7 +295,7 @@ static unsigned sdma_v4_0_seq_to_irq_id(int seq_num)
default:
break;
}
- return 0;
+ return -EINVAL;
}
static int sdma_v4_0_irq_id_to_seq(unsigned client_id)
@@ -320,7 +320,7 @@ static int sdma_v4_0_irq_id_to_seq(unsigned client_id)
default:
break;
}
- return 0;
+ return -EINVAL;
}
static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
@@ -1643,7 +1643,7 @@ static int sdma_v4_0_late_init(void *handle)
.sub_block_index = 0,
.name = "sdma",
};
- int r;
+ int r, i;
if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
amdgpu_ras_feature_enable_on_boot(adev, _block, 0);
@@ -1700,14 +1700,11 @@ static int sdma_v4_0_late_init(void *handle)
if (r)
goto sysfs;
resume:
- r = amdgpu_irq_get(adev, >sdma.ecc_irq,
AMDGPU_SDMA_IRQ_INSTANCE0);
- if (r)
- goto irq;
-
- r = amdgpu_irq_get(adev, >sdma.ecc_irq,
AMDGPU_SDMA_IRQ_INSTANCE1);
- if (r) {
- amdgpu_irq_put(adev, >sdma.ecc_irq,
AMDGPU_SDMA_IRQ_INSTANCE0);
- goto irq;
+ for (i = 0; i < adev->sdma.num_instances; i++) {
+ r = amdgpu_irq_get(adev, >sdma.ecc_irq,
+ sdma_v4_0_seq_to_irq_id(i));
+ if (r)
+ goto irq;
}
return 0;
@@ -1740,16 +1737,13 @@ static int sdma_v4_0_sw_init(void *handle)
}
/* SDMA SRAM ECC event */
- r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0,
SDMA0_4_0__SRCID__SDMA_SRAM_ECC,
- >sdma.ecc_irq);
- if (r)
- return r;
-
- /* SDMA SRAM ECC event */
- r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1,
SDMA1_4_0__SRCID__SDMA_SRAM_ECC,
- >sdma.ecc_irq);
- if (r)
- return r;
+ for (i = 0; i < adev->sdma.num_instances; i++) {
+ r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
+ SDMA0_4_0__SRCID__SDMA_SRAM_ECC,
+ >sdma.ecc_irq);
+ if (r)
+ return r;
+ }
for (i = 0; i < adev->sdma.num_instances; i++) {
ring = >sdma.instance[i].ring;
@@ -1782,9 +1776,7 @@ static int sdma_v4_0_sw_init(void *handle)
sprintf(ring->name, "page%d", i);
r = amdgpu_ring_init(adev, ring, 1024,
>sdma.trap_irq,
-(i == 0) ?
-AMDGPU_SDMA_IRQ_INSTANCE0 :
-AMDGPU_SDMA_IRQ_INSTANCE1);
+AMDGPU_SDMA_IRQ_INSTANCE0 + i);
if (r)
return r;
}
@@ -1847,12 +1839,15 @@ static int sdma_v4_0_hw_init(void *handle)
static int sdma_v4_0_hw_fini(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ int i;
if (amdgpu_sriov_vf(adev))
return 0;
- amdgpu_irq_put(adev, >sdma.ecc_irq, AMDGPU_SDMA_IRQ_INSTANCE0);
- amdgpu_irq_put(adev, >sdma.ecc_irq, AMDGPU_SDMA_IRQ_INSTANCE1);
+ for (i = 0; i < adev->sdma.num_instances; i++) {
+ amdgpu_irq_put(adev, >sdma.ecc_irq,
+ sdma_v4_0_seq_to_irq_id(i));
+ }
sdma_v4_0_ctx_switch_enable(adev, false);
sdma_v4_0_enable(adev, false);
@@ -1966,16 +1961,9 @@ static int sdma_v4_0_process_ras_data_cb(struct
amdgpu_device *adev,
{
uint32_t instance, err_source;
- switch (entry->client_id) {
- case SOC15_IH_CLIENTID_SDMA0:
- instance = 0;
- break;
- case SOC15_IH_CLIENTID_SDMA1:
- instance = 1;
- break;
- default:
+ instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
+ if (instance < 0)
return 0;
- }
switch (entry->src_id) {
case SDMA0_4_0__SRCID__SDMA_SRAM_ECC:
@@ -2021,16 +2009,9 @@ static int sdma_v4_0_process_illegal_inst_irq(struct
amdgpu_device *adev,
DRM_ERROR("Illegal instruction in SDMA command stream\n");
- switch (entry->client_id) {
- case
[PATCH 02/30] drm/amd/powerplay: add SW SMU interface for dumping pptable out (v2)
From: Evan Quan
This is especially useful in early bring up phase.
v2: disabled by default (Alex)
Signed-off-by: Evan Quan
Reviewed-by: Le Ma
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 2 ++
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 4 +++-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 974472015487..c45fa2fb4da9 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -1064,6 +1064,8 @@ static int smu_smc_table_hw_init(struct smu_context *smu,
return ret;
}
+ /* smu_dump_pptable(smu); */
+
/*
* Copy pptable bo in the vram to smc with SMU MSGs such as
* SetDriverDramAddr and TransferTableDram2Smu.
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index ac9e9d5d8a5c..519aeac706a5 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -446,6 +446,7 @@ struct pptable_funcs {
int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t
*clocks_in_khz, uint32_t *num_states);
int (*set_default_od_settings)(struct smu_context *smu, bool
initialize);
int (*set_performance_level)(struct smu_context *smu, enum
amd_dpm_forced_level level);
+ void (*dump_pptable)(struct smu_context *smu);
};
struct smu_funcs
@@ -737,7 +738,8 @@ struct smu_funcs
((smu)->funcs->baco_reset? (smu)->funcs->baco_reset((smu)) : 0)
#define smu_asic_set_performance_level(smu, level) \
((smu)->ppt_funcs->set_performance_level?
(smu)->ppt_funcs->set_performance_level((smu), (level)) : -EINVAL);
-
+#define smu_dump_pptable(smu) \
+ ((smu)->ppt_funcs->dump_pptable ? (smu)->ppt_funcs->dump_pptable((smu))
: 0)
extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
uint16_t *size, uint8_t *frev, uint8_t *crev,
--
2.20.1
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[PATCH 03/30] drm/amd/powerplay: update smu11_driver_if_arcturus.h
From: Evan Quan
It guides how driver should interface with SMU in arcturus.
Signed-off-by: Evan Quan
Reviewed-by: Kenneth Feng
Signed-off-by: Alex Deucher
---
.../powerplay/inc/smu11_driver_if_arcturus.h | 58 +++
1 file changed, 33 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h
b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h
index 7a9969e075d4..c7a7953b52b7 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h
@@ -21,16 +21,15 @@
*
*/
-
#ifndef SMU11_DRIVER_IF_ARCTURUS_H
#define SMU11_DRIVER_IF_ARCTURUS_H
// *** IMPORTANT ***
// SMU TEAM: Always increment the interface version if
// any structure is changed in this file
-#define SMU11_DRIVER_IF_VERSION 0x06
+#define SMU11_DRIVER_IF_VERSION 0x08
-#define PPTABLE_ARCTURUS_SMU_VERSION 3
+#define PPTABLE_ARCTURUS_SMU_VERSION 4
#define NUM_GFXCLK_DPM_LEVELS 16
#define NUM_VCLK_DPM_LEVELS8
@@ -40,6 +39,7 @@
#define NUM_UCLK_DPM_LEVELS4
#define NUM_FCLK_DPM_LEVELS8
#define NUM_XGMI_LEVELS2
+#define NUM_XGMI_PSTATE_LEVELS 4
#define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1)
#define MAX_VCLK_DPM_LEVEL(NUM_VCLK_DPM_LEVELS- 1)
@@ -49,6 +49,7 @@
#define MAX_UCLK_DPM_LEVEL(NUM_UCLK_DPM_LEVELS- 1)
#define MAX_FCLK_DPM_LEVEL(NUM_FCLK_DPM_LEVELS- 1)
#define MAX_XGMI_LEVEL(NUM_XGMI_LEVELS- 1)
+#define MAX_XGMI_PSTATE_LEVEL (NUM_XGMI_PSTATE_LEVELS - 1)
// Feature Control Defines
// DPM
@@ -213,8 +214,8 @@
#define WORKLOAD_PPLIB_COUNT 5
//XGMI performance states
-#define XGMI_STATE_D0 1
-#define XGMI_STATE_D3 0
+#define XGMI_STATE_D0 1
+#define XGMI_STATE_D3 0
#define NUM_I2C_CONTROLLERS8
@@ -314,7 +315,6 @@ typedef struct {
} SwI2cRequest_t; // SW I2C Request Table
//D3HOT sequences
-//sequence codes from spec:
atlvp4p01.amd.com:1677@//gpu/doc/soc_arch/spec/feature/BACO/Navi/Navi2x/
typedef enum {
BACO_SEQUENCE,
MSR_SEQUENCE,
@@ -368,6 +368,12 @@ typedef enum {
PPCLK_COUNT,
} PPCLK_e;
+typedef enum {
+ POWER_SOURCE_AC,
+ POWER_SOURCE_DC,
+ POWER_SOURCE_COUNT,
+} POWER_SOURCE_e;
+
typedef enum {
TEMP_EDGE,
TEMP_HOTSPOT,
@@ -568,14 +574,9 @@ typedef struct {
uint16_t DcBtcGb[AVFS_VOLTAGE_COUNT];// mV Q2
- uint16_t SsFmin[10]; // PPtable value to function similar to
VFTFmin for SS Curve; Size is PPCLK_COUNT rounded to nearest multiple of 2
-
// SECTION: XGMI
- uint8_t XgmiLinkSpeed [NUM_XGMI_LEVELS];
- uint8_t XgmiLinkWidth [NUM_XGMI_LEVELS];
-
- uint16_t XgmiFclkFreq[NUM_XGMI_LEVELS];
- uint16_t XgmiSocVoltage [NUM_XGMI_LEVELS];
+ uint8_t XgmiDpmPstates[NUM_XGMI_LEVELS]; // 2 DPM states, high and
low. 0-P0, 1-P1, 2-P2, 3-P3.
+ uint8_t XgmiDpmSpare[2];
// Temperature Dependent Vmin
uint16_t VDDGFX_TVmin; //Celcius
@@ -683,6 +684,13 @@ typedef struct {
uint16_t TotalBoardPower; //Only needed for TCP Estimated case,
where TCP = TGP+Total Board Power
uint16_t BoardPadding;
+ // SECTION: XGMI Training
+ uint8_t XgmiLinkSpeed [NUM_XGMI_PSTATE_LEVELS];
+ uint8_t XgmiLinkWidth [NUM_XGMI_PSTATE_LEVELS];
+
+ uint16_t XgmiFclkFreq[NUM_XGMI_PSTATE_LEVELS];
+ uint16_t XgmiSocVoltage [NUM_XGMI_PSTATE_LEVELS];
+
uint32_t BoardReserved[10];
// Padding for MMHUB - do not modify this
@@ -698,7 +706,7 @@ typedef struct {
uint16_t GfxActivityLpfTau;
uint16_t UclkActivityLpfTau;
- uint16_t Padding;
+ uint16_t SocketPowerLpfTau;
// Padding - ignore
uint32_t MmHubPadding[8]; // SMU internal use
@@ -715,7 +723,7 @@ typedef struct {
uint8_t CurrGfxVoltageOffset ;
uint8_t CurrMemVidOffset ;
uint8_t Padding8 ;
- uint16_t CurrSocketPower ;
+ uint16_t AverageSocketPower;
uint16_t TemperatureEdge ;
uint16_t TemperatureHotspot;
uint16_t TemperatureHBM;
@@ -724,23 +732,23 @@ typedef struct {
uint16_t TemperatureVrMem ;
uint32_t ThrottlerStatus ;
+ uint16_t CurrFanSpeed ;
+ uint16_t Padding16;
+
+ uint32_t Padding[4];
+
// Padding - ignore
uint32_t MmHubPadding[7]; // SMU internal use
} SmuMetrics_t;
typedef struct {
- uint16_t avgPsmCount[45];
- uint16_t minPsmCount[45];
- floatavgPsmVoltage[45];
- floatminPsmVoltage[45];
-
- uint16_t avgScsPsmCount;
- uint16_t minScsPsmCount;
- floatavgScsPsmVoltage;
- floatminScsPsmVoltage;
+ uint16_t avgPsmCount[75];
+ uint16_t minPsmCount[75];
+ floatavgPsmVoltage[75];
+ floatminPsmVoltage[75];
- uint32_t MmHubPadding[6]; // SMU internal use
+ uint32_t MmHubPadding[3]; // SMU
[PATCH 01/30] drm/amd/powerplay: add smcdpminfo table v4_6 support
From: Evan Quan
New smcdpminfo table used in arcturus.
Signed-off-by: Evan Quan
Reviewed-by: Kenneth Feng
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/include/atomfirmware.h | 86 ++
1 file changed, 86 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h
b/drivers/gpu/drm/amd/include/atomfirmware.h
index 24cfe84d7322..e88541d67aa0 100644
--- a/drivers/gpu/drm/amd/include/atomfirmware.h
+++ b/drivers/gpu/drm/amd/include/atomfirmware.h
@@ -1789,6 +1789,92 @@ struct atom_smc_dpm_info_v4_5
};
+struct atom_smc_dpm_info_v4_6
+{
+ struct atom_common_table_header table_header;
+ // section: board parameters
+ uint32_t i2c_padding[3]; // old i2c control are moved to new area
+
+ uint16_t maxvoltagestepgfx; // in mv(q2) max voltage step that smu will
request. multiple steps are taken if voltage change exceeds this value.
+ uint16_t maxvoltagestepsoc; // in mv(q2) max voltage step that smu will
request. multiple steps are taken if voltage change exceeds this value.
+
+ uint8_t vddgfxvrmapping; // use vr_mapping* bitfields
+ uint8_t vddsocvrmapping; // use vr_mapping* bitfields
+ uint8_t vddmemvrmapping; // use vr_mapping* bitfields
+ uint8_t boardvrmapping; // use vr_mapping* bitfields
+
+ uint8_t gfxulvphasesheddingmask; // set this to 1 to set psi0/1 to 1 in
ulv mode
+ uint8_t externalsensorpresent; // external rdi connected to tmon (aka
temp in)
+ uint8_t padding8_v[2];
+
+ // telemetry settings
+ uint16_t gfxmaxcurrent; // in amps
+ uint8_t gfxoffset; // in amps
+ uint8_t padding_telemetrygfx;
+
+ uint16_t socmaxcurrent; // in amps
+ uint8_t socoffset; // in amps
+ uint8_t padding_telemetrysoc;
+
+ uint16_t memmaxcurrent; // in amps
+ uint8_t memoffset; // in amps
+ uint8_t padding_telemetrymem;
+
+ uint16_t boardmaxcurrent; // in amps
+ uint8_t boardoffset; // in amps
+ uint8_t padding_telemetryboardinput;
+
+ // gpio settings
+ uint8_t vr0hotgpio; // gpio pin configured for vr0 hot event
+ uint8_t vr0hotpolarity; // gpio polarity for vr0 hot event
+ uint8_t vr1hotgpio; // gpio pin configured for vr1 hot event
+ uint8_t vr1hotpolarity; // gpio polarity for vr1 hot event
+
+ // gfxclk pll spread spectrum
+ uint8_t pllgfxclkspreadenabled; // on or off
+ uint8_t pllgfxclkspreadpercent; // q4.4
+ uint16_tpllgfxclkspreadfreq; // khz
+
+ // uclk spread spectrum
+ uint8_t uclkspreadenabled; // on or off
+ uint8_t uclkspreadpercent; // q4.4
+ uint16_tuclkspreadfreq; // khz
+
+ // fclk spread spectrum
+ uint8_t fclkspreadenabled; // on or off
+ uint8_t fclkspreadpercent; // q4.4
+ uint16_tfclkspreadfreq; // khz
+
+
+ // gfxclk fll spread spectrum
+ uint8_t fllgfxclkspreadenabled; // on or off
+ uint8_t fllgfxclkspreadpercent; // q4.4
+ uint16_t fllgfxclkspreadfreq; // khz
+
+ // i2c controller structure
+ struct smudpm_i2c_controller_config_v2 i2ccontrollers[8];
+
+ // memory section
+ uint32_t memorychannelenabled; // for dram use only, max 32 channels
enabled bit mask.
+
+ uint8_t drambitwidth; // for dram use only. see dram bit width type
defines
+ uint8_t paddingmem[3];
+
+ // total board power
+ uint16_t totalboardpower; //only needed for tcp estimated case,
where tcp = tgp+total board power
+ uint16_t boardpadding;
+
+ // section: xgmi training
+ uint8_t xgmilinkspeed[4];
+ uint8_t xgmilinkwidth[4];
+
+ uint16_t xgmifclkfreq[4];
+ uint16_t xgmisocvoltage[4];
+
+ // reserved
+ uint32_t boardreserved[10];
+};
+
/*
***
Data Table asic_profiling_info structure
--
2.20.1
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[PATCH 11/30] drm/amd/include: adjust base offset of SMUIO and THM for Arcturus
From: Le Ma
Arcturus has different _BASE_IDX value in some HWIP_offset.h. To make source
files like smu_v11_0.c and soc15.c that include HWIP_offset.h of Vega20
reusable for Arcturus, align this base offset with Vega20.
Signed-off-by: Le Ma
Reviewed-by: Kenneth Feng
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/include/arct_ip_offset.h | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/include/arct_ip_offset.h
b/drivers/gpu/drm/amd/include/arct_ip_offset.h
index 3211b3a96d68..a7791a9e1f90 100644
--- a/drivers/gpu/drm/amd/include/arct_ip_offset.h
+++ b/drivers/gpu/drm/amd/include/arct_ip_offset.h
@@ -196,17 +196,13 @@ static const struct IP_BASE SDMA7_BASE={ { {
{ 0x00013800, 0x0001F40
{ { 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE SMUIO_BASE={ { { { 0x00012080,
0x00016800, 0x00016A00, 0x00401000, 0x0044, 0 } },
-{ { 0, 0, 0, 0, 0, 0 } },
-{ { 0, 0, 0, 0, 0, 0 } },
+static const struct IP_BASE SMUIO_BASE={ { { { 0x00016800,
0x00016A00, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0 } } } };
-static const struct IP_BASE THM_BASE={ { { { 0x00012060,
0x00016600, 0x00400C00, 0, 0, 0 } },
-{ { 0, 0, 0, 0, 0, 0 } },
-{ { 0, 0, 0, 0, 0, 0 } },
+static const struct IP_BASE THM_BASE={ { { { 0x00016600, 0, 0, 0,
0, 0 } },
{ { 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0 } },
--
2.20.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 04/30] drm/amd/powerplay: update arcturus_ppsmc.h
From: Evan Quan Correct header and fix typo. Signed-off-by: Evan Quan Reviewed-by: Le Ma Reviewed-by: Kenneth Feng Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/inc/arcturus_ppsmc.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/inc/arcturus_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/arcturus_ppsmc.h index b86bb2bc8a31..78e5927b7711 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/arcturus_ppsmc.h +++ b/drivers/gpu/drm/amd/powerplay/inc/arcturus_ppsmc.h @@ -1,5 +1,5 @@ /* - * Copyright 2018 Advanced Micro Devices, Inc. + * Copyright 2019 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -83,7 +83,7 @@ //Power Gating #define PPSMC_MSG_PowerUpVcn00x28 -#define PPSMC_MSG_PowerDownVcn01 0x29 +#define PPSMC_MSG_PowerDownVcn0 0x29 #define PPSMC_MSG_PowerUpVcn10x2A #define PPSMC_MSG_PowerDownVcn1 0x2B -- 2.20.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 00/30] Arcturus updates
This series updates arcturus support enabling powerplay and assorted bug fixes. Evan Quan (26): drm/amd/powerplay: add smcdpminfo table v4_6 support drm/amd/powerplay: add SW SMU interface for dumping pptable out (v2) drm/amd/powerplay: update smu11_driver_if_arcturus.h drm/amd/powerplay: update arcturus_ppsmc.h drm/amd/powerplay: update arcturus_ppt.c/h V3 drm/amd/powerplay: enable SW SMU routine support for arcturus drm/amd/powerplay: initialize arcturus MP1 and THM base address drm/amd/powerplay: enable arcturus powerplay drm/amdgpu: correct VCN powergate routine for acturus drm/amd/powerplay: hold on the arcturus gfx dpm support in driver drm/amd/powerplay: add new sensor type for VCN powergate status drm/amd/powerplay: support VCN powergate status retrieval on Raven drm/amd/powerplay: support VCN powergate status retrieval for SW SMU drm/amd/powerplay: correct Navi10 VCN powergate control drm/amd/powerplay: correct UVD/VCE/VCN power status retrieval drm/amd/powerplay: init arcturus SMU metrics table on bootup drm/amd/powerplay: support sensor reading on arcturus drm/amd/powerplay: support real-time clock retrieval on arcturus drm/amd/powerplay: support fan speed retrieval on arcturus drm/amd/powerplay: add missing arcturus feature maps drm/amd/powerplay: correct the bitmask used in arcturus drm/amd/powerplay: fix arcturus real-time clock frequency retrieval drm/amd/powerplay: support UMD PSTATE settings on arcturus drm/amd/powerplay: correct arcturus current clock level calculation drm/amd/powerplay: make power limit retrieval as asic specific drm/amd/powerplay: determine the features to enable by pptable only Hawking Zhang (1): drm/amdgpu: correct irq type used for sdma ecc Kevin Wang (1): drm/amd/powerplay: remove redundancy debug log in smu Le Ma (2): drm/amd/include: adjust base offset of SMUIO and THM for Arcturus drm/amdgpu: update more sdma instances irq support drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c| 56 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c |4 +- drivers/gpu/drm/amd/amdgpu/arct_reg_init.c|2 + drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c| 77 +- drivers/gpu/drm/amd/amdgpu/soc15.c|1 + drivers/gpu/drm/amd/include/arct_ip_offset.h |8 +- drivers/gpu/drm/amd/include/atomfirmware.h| 86 + .../gpu/drm/amd/include/kgd_pp_interface.h|1 + drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 57 +- drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 1727 - drivers/gpu/drm/amd/powerplay/arcturus_ppt.h | 44 + .../gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c |9 + .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h|8 +- .../drm/amd/powerplay/inc/arcturus_ppsmc.h|4 +- .../powerplay/inc/smu11_driver_if_arcturus.h | 58 +- drivers/gpu/drm/amd/powerplay/inc/smu_types.h |2 +- drivers/gpu/drm/amd/powerplay/navi10_ppt.c| 77 +- drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 55 +- 18 files changed, 2084 insertions(+), 192 deletions(-) -- 2.20.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 3/3] drm/amdkfd: Save/restore vcc on gfx10
Series is:
reviewed-by: shaoyunl
On 2019-07-29 11:31 a.m., Cornwall, Jay wrote:
> VCC moved out of user SGPR allocation in gfx10. It's now stored
> in SGPRs 106-107.
>
> Also fixes incorrect SGPR read offsets.
>
> Cc: Shaoyun Liu
> Signed-off-by: Jay Cornwall
> ---
> drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h | 452
> ++---
> .../gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm | 34 +-
> 2 files changed, 243 insertions(+), 243 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
> b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
> index 8089bb3..a8cf82d 100644
> --- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
> +++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
> @@ -680,7 +680,7 @@ static const uint32_t cwsr_trap_gfx9_hex[] = {
> };
>
> static const uint32_t cwsr_trap_gfx10_hex[] = {
> - 0xbf820001, 0xbf8201c0,
> + 0xbf820001, 0xbf8201c1,
> 0xb0804004, 0xb978f802,
> 0x8a788678, 0xb971f803,
> 0x876eff71, 0x0400,
> @@ -804,271 +804,271 @@ static const uint32_t cwsr_trap_gfx10_hex[] = {
> 0x0060, 0xbf85ffea,
> 0xbe802f00, 0xbe822f02,
> 0xbe842f04, 0xbe862f06,
> - 0xbe882f08, 0xf469003a,
> - 0xfa00, 0xf469013a,
> - 0xfa10, 0xf465023a,
> - 0xfa20, 0x8074c074,
> - 0x82758075, 0xbef40372,
> - 0xbefa0380, 0xbefe03c1,
> - 0x907c9973, 0x877c817c,
> - 0xbf06817c, 0xbf850002,
> - 0xbeff0380, 0xbf820002,
> - 0xbeff03c1, 0xbf82000b,
> + 0xbe882f08, 0xbe8a2f0a,
> + 0xf469003a, 0xfa00,
> + 0xf469013a, 0xfa10,
> + 0xf469023a, 0xfa20,
> + 0x8074b074, 0x82758075,
> + 0xbef40372, 0xbefa0380,
> + 0xbefe03c1, 0x907c9973,
> + 0x877c817c, 0xbf06817c,
> + 0xbf850002, 0xbeff0380,
> + 0xbf820002, 0xbeff03c1,
> + 0xbf82000b, 0xbef603ff,
> + 0x0100, 0xe0704000,
> + 0x7a5d, 0xe0704080,
> + 0x7a5d0100, 0xe0704100,
> + 0x7a5d0200, 0xe0704180,
> + 0x7a5d0300, 0xbf82000a,
> 0xbef603ff, 0x0100,
> 0xe0704000, 0x7a5d,
> - 0xe0704080, 0x7a5d0100,
> - 0xe0704100, 0x7a5d0200,
> - 0xe0704180, 0x7a5d0300,
> - 0xbf82000a, 0xbef603ff,
> - 0x0100, 0xe0704000,
> - 0x7a5d, 0xe0704100,
> - 0x7a5d0100, 0xe0704200,
> - 0x7a5d0200, 0xe0704300,
> - 0x7a5d0300, 0xbefe03c1,
> + 0xe0704100, 0x7a5d0100,
> + 0xe0704200, 0x7a5d0200,
> + 0xe0704300, 0x7a5d0300,
> + 0xbefe03c1, 0x907c9973,
> + 0x877c817c, 0xbf06817c,
> + 0xbf850002, 0xbeff0380,
> + 0xbf820001, 0xbeff03c1,
> + 0xb9714306, 0x8771c171,
> + 0xbf840046, 0xbf8a,
> + 0x8776ff6f, 0x0400,
> + 0xbf840042, 0x8f718671,
> + 0x8f718271, 0xbef60371,
> + 0xb97a2a05, 0x807a817a,
> 0x907c9973, 0x877c817c,
> 0xbf06817c, 0xbf850002,
> - 0xbeff0380, 0xbf820001,
> - 0xbeff03c1, 0xb9714306,
> - 0x8771c171, 0xbf840046,
> - 0xbf8a, 0x8776ff6f,
> - 0x0400, 0xbf840042,
> - 0x8f718671, 0x8f718271,
> - 0xbef60371, 0xb97a2a05,
> - 0x807a817a, 0x907c9973,
> + 0x8f7a897a, 0xbf820001,
> + 0x8f7a8a7a, 0xb9761e06,
> + 0x8f768a76, 0x807a767a,
> + 0x807aff7a, 0x0200,
> + 0x807aff7a, 0x0080,
> + 0xbef603ff, 0x0100,
> + 0xd765, 0x000100c1,
> + 0xd766, 0x000200c1,
> + 0x1684, 0x907c9973,
> 0x877c817c, 0xbf06817c,
> - 0xbf850002, 0x8f7a897a,
> - 0xbf820001, 0x8f7a8a7a,
> - 0xb9761e06, 0x8f768a76,
> - 0x807a767a, 0x807aff7a,
> - 0x0200, 0x807aff7a,
> - 0x0080, 0xbef603ff,
> - 0x0100, 0xd765,
> - 0x000100c1, 0xd766,
> - 0x000200c1, 0x1684,
> - 0x907c9973, 0x877c817c,
> - 0xbf06817c, 0xbefc0380,
> - 0xbf850012, 0xbe8303ff,
> - 0x0080, 0xbf80,
> + 0xbefc0380, 0xbf850012,
> + 0xbe8303ff, 0x0080,
> 0xbf80, 0xbf80,
> - 0xd8d8, 0x0100,
> - 0xbf8c, 0xe0704000,
> - 0x7a5d0100, 0x807c037c,
> - 0x807a037a, 0xd525,
> - 0x0001ff00, 0x0080,
> - 0xbf0a717c, 0xbf85fff4,
> - 0xbf820011, 0xbe8303ff,
> - 0x0100, 0xbf80,
> + 0xbf80, 0xd8d8,
> + 0x0100, 0xbf8c,
> + 0xe0704000, 0x7a5d0100,
> + 0x807c037c, 0x807a037a,
> + 0xd525, 0x0001ff00,
> + 0x0080, 0xbf0a717c,
> + 0xbf85fff4, 0xbf820011,
> + 0xbe8303ff, 0x0100,
> 0xbf80, 0xbf80,
> - 0xd8d8, 0x0100,
> - 0xbf8c, 0xe0704000,
> - 0x7a5d0100, 0x807c037c,
> - 0x807a037a, 0xd525,
> - 0x0001ff00, 0x0100,
> - 0xbf0a717c, 0xbf85fff4,
> - 0xbefe03c1, 0x907c9973,
> - 0x877c817c, 0xbf06817c,
> - 0xbf850004, 0xbefa03ff,
> - 0x0200, 0xbeff0380,
> - 0xbf820003, 0xbefa03ff,
> - 0x0400, 0xbeff03c1,
> - 0xb9712a05, 0x80718171,
> - 0x8f718271, 0x907c9973,
> - 0x877c817c, 0xbf06817c,
> - 0xbf850017,
Re: [PATCH 3/3] drm/amdkfd: Save/restore vcc on gfx10
On Mon, Jul 29, 2019 at 11:31 AM Cornwall, Jay wrote:
>
> VCC moved out of user SGPR allocation in gfx10. It's now stored
> in SGPRs 106-107.
>
> Also fixes incorrect SGPR read offsets.
>
> Cc: Shaoyun Liu
> Signed-off-by: Jay Cornwall
Series is:
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h | 452
> ++---
> .../gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm | 34 +-
> 2 files changed, 243 insertions(+), 243 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
> b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
> index 8089bb3..a8cf82d 100644
> --- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
> +++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
> @@ -680,7 +680,7 @@ static const uint32_t cwsr_trap_gfx9_hex[] = {
> };
>
> static const uint32_t cwsr_trap_gfx10_hex[] = {
> - 0xbf820001, 0xbf8201c0,
> + 0xbf820001, 0xbf8201c1,
> 0xb0804004, 0xb978f802,
> 0x8a788678, 0xb971f803,
> 0x876eff71, 0x0400,
> @@ -804,271 +804,271 @@ static const uint32_t cwsr_trap_gfx10_hex[] = {
> 0x0060, 0xbf85ffea,
> 0xbe802f00, 0xbe822f02,
> 0xbe842f04, 0xbe862f06,
> - 0xbe882f08, 0xf469003a,
> - 0xfa00, 0xf469013a,
> - 0xfa10, 0xf465023a,
> - 0xfa20, 0x8074c074,
> - 0x82758075, 0xbef40372,
> - 0xbefa0380, 0xbefe03c1,
> - 0x907c9973, 0x877c817c,
> - 0xbf06817c, 0xbf850002,
> - 0xbeff0380, 0xbf820002,
> - 0xbeff03c1, 0xbf82000b,
> + 0xbe882f08, 0xbe8a2f0a,
> + 0xf469003a, 0xfa00,
> + 0xf469013a, 0xfa10,
> + 0xf469023a, 0xfa20,
> + 0x8074b074, 0x82758075,
> + 0xbef40372, 0xbefa0380,
> + 0xbefe03c1, 0x907c9973,
> + 0x877c817c, 0xbf06817c,
> + 0xbf850002, 0xbeff0380,
> + 0xbf820002, 0xbeff03c1,
> + 0xbf82000b, 0xbef603ff,
> + 0x0100, 0xe0704000,
> + 0x7a5d, 0xe0704080,
> + 0x7a5d0100, 0xe0704100,
> + 0x7a5d0200, 0xe0704180,
> + 0x7a5d0300, 0xbf82000a,
> 0xbef603ff, 0x0100,
> 0xe0704000, 0x7a5d,
> - 0xe0704080, 0x7a5d0100,
> - 0xe0704100, 0x7a5d0200,
> - 0xe0704180, 0x7a5d0300,
> - 0xbf82000a, 0xbef603ff,
> - 0x0100, 0xe0704000,
> - 0x7a5d, 0xe0704100,
> - 0x7a5d0100, 0xe0704200,
> - 0x7a5d0200, 0xe0704300,
> - 0x7a5d0300, 0xbefe03c1,
> + 0xe0704100, 0x7a5d0100,
> + 0xe0704200, 0x7a5d0200,
> + 0xe0704300, 0x7a5d0300,
> + 0xbefe03c1, 0x907c9973,
> + 0x877c817c, 0xbf06817c,
> + 0xbf850002, 0xbeff0380,
> + 0xbf820001, 0xbeff03c1,
> + 0xb9714306, 0x8771c171,
> + 0xbf840046, 0xbf8a,
> + 0x8776ff6f, 0x0400,
> + 0xbf840042, 0x8f718671,
> + 0x8f718271, 0xbef60371,
> + 0xb97a2a05, 0x807a817a,
> 0x907c9973, 0x877c817c,
> 0xbf06817c, 0xbf850002,
> - 0xbeff0380, 0xbf820001,
> - 0xbeff03c1, 0xb9714306,
> - 0x8771c171, 0xbf840046,
> - 0xbf8a, 0x8776ff6f,
> - 0x0400, 0xbf840042,
> - 0x8f718671, 0x8f718271,
> - 0xbef60371, 0xb97a2a05,
> - 0x807a817a, 0x907c9973,
> + 0x8f7a897a, 0xbf820001,
> + 0x8f7a8a7a, 0xb9761e06,
> + 0x8f768a76, 0x807a767a,
> + 0x807aff7a, 0x0200,
> + 0x807aff7a, 0x0080,
> + 0xbef603ff, 0x0100,
> + 0xd765, 0x000100c1,
> + 0xd766, 0x000200c1,
> + 0x1684, 0x907c9973,
> 0x877c817c, 0xbf06817c,
> - 0xbf850002, 0x8f7a897a,
> - 0xbf820001, 0x8f7a8a7a,
> - 0xb9761e06, 0x8f768a76,
> - 0x807a767a, 0x807aff7a,
> - 0x0200, 0x807aff7a,
> - 0x0080, 0xbef603ff,
> - 0x0100, 0xd765,
> - 0x000100c1, 0xd766,
> - 0x000200c1, 0x1684,
> - 0x907c9973, 0x877c817c,
> - 0xbf06817c, 0xbefc0380,
> - 0xbf850012, 0xbe8303ff,
> - 0x0080, 0xbf80,
> + 0xbefc0380, 0xbf850012,
> + 0xbe8303ff, 0x0080,
> 0xbf80, 0xbf80,
> - 0xd8d8, 0x0100,
> - 0xbf8c, 0xe0704000,
> - 0x7a5d0100, 0x807c037c,
> - 0x807a037a, 0xd525,
> - 0x0001ff00, 0x0080,
> - 0xbf0a717c, 0xbf85fff4,
> - 0xbf820011, 0xbe8303ff,
> - 0x0100, 0xbf80,
> + 0xbf80, 0xd8d8,
> + 0x0100, 0xbf8c,
> + 0xe0704000, 0x7a5d0100,
> + 0x807c037c, 0x807a037a,
> + 0xd525, 0x0001ff00,
> + 0x0080, 0xbf0a717c,
> + 0xbf85fff4, 0xbf820011,
> + 0xbe8303ff, 0x0100,
> 0xbf80, 0xbf80,
> - 0xd8d8, 0x0100,
> - 0xbf8c, 0xe0704000,
> - 0x7a5d0100, 0x807c037c,
> - 0x807a037a, 0xd525,
> - 0x0001ff00, 0x0100,
> - 0xbf0a717c, 0xbf85fff4,
> - 0xbefe03c1, 0x907c9973,
> - 0x877c817c, 0xbf06817c,
> -
Re: [PATCH] drm/amdgpu: Update pitch on page flips without DC as well
Reviewed-by: Alex Deucher
From: amd-gfx on behalf of Michel
Dänzer
Sent: Monday, July 29, 2019 12:20 PM
To: amd-gfx@lists.freedesktop.org
Subject: [PATCH] drm/amdgpu: Update pitch on page flips without DC as well
From: Michel Dänzer
DC already handles this correctly since amdgpu minor version 31. Bump
the minor version again so that xf86-video-amdgpu can take advantage of
this working without DC as well now.
Signed-off-by: Michel Dänzer
---
See
https://gitlab.freedesktop.org/xorg/driver/xf86-video-amdgpu/merge_requests/39
for the corresponding xf86-video-amdgpu change.
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++-
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 4
drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 4
drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 4
drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 4
5 files changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 800d0ceb14b4..cf334c465805 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -77,9 +77,10 @@
* - 3.31.0 - Add support for per-flip tiling attribute changes with DC
* - 3.32.0 - Add syncobj timeline support to AMDGPU_CS.
* - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS.
+ * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches
*/
#define KMS_DRIVER_MAJOR3
-#define KMS_DRIVER_MINOR 33
+#define KMS_DRIVER_MINOR 34
#define KMS_DRIVER_PATCHLEVEL 0
#define AMDGPU_MAX_TIMEOUT_PARAM_LENTH 256
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index 1f0426d2fc2a..c609b7af0b6b 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -233,6 +233,7 @@ static void dce_v10_0_page_flip(struct amdgpu_device *adev,
int crtc_id, u64 crtc_base, bool async)
{
struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
+ struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;
u32 tmp;
/* flip at hsync for async, default is vsync */
@@ -240,6 +241,9 @@ static void dce_v10_0_page_flip(struct amdgpu_device *adev,
tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
GRPH_SURFACE_UPDATE_H_RETRACE_EN, async ? 1 : 0);
WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
+ /* update pitch */
+ WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,
+ fb->pitches[0] / fb->format->cpp[0]);
/* update the primary scanout address */
WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
upper_32_bits(crtc_base));
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index 2280b971d758..719db058b306 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -251,6 +251,7 @@ static void dce_v11_0_page_flip(struct amdgpu_device *adev,
int crtc_id, u64 crtc_base, bool async)
{
struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
+ struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;
u32 tmp;
/* flip immediate for async, default is vsync */
@@ -258,6 +259,9 @@ static void dce_v11_0_page_flip(struct amdgpu_device *adev,
tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
GRPH_SURFACE_UPDATE_IMMEDIATE_EN, async ? 1 : 0);
WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
+ /* update pitch */
+ WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,
+ fb->pitches[0] / fb->format->cpp[0]);
/* update the scanout addresses */
WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
upper_32_bits(crtc_base));
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
index bea32f076b91..8ee99651d01a 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
@@ -186,10 +186,14 @@ static void dce_v6_0_page_flip(struct amdgpu_device *adev,
int crtc_id, u64 crtc_base, bool async)
{
struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
+ struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;
/* flip at hsync for async, default is vsync */
WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ?
GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0);
+ /* update pitch */
+ WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,
+ fb->pitches[0] / fb->format->cpp[0]);
/* update the scanout addresses */
WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
[PATCH] drm/amdgpu: Update pitch on page flips without DC as well
From: Michel Dänzer
DC already handles this correctly since amdgpu minor version 31. Bump
the minor version again so that xf86-video-amdgpu can take advantage of
this working without DC as well now.
Signed-off-by: Michel Dänzer
---
See
https://gitlab.freedesktop.org/xorg/driver/xf86-video-amdgpu/merge_requests/39
for the corresponding xf86-video-amdgpu change.
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++-
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 4
drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 4
drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 4
drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 4
5 files changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 800d0ceb14b4..cf334c465805 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -77,9 +77,10 @@
* - 3.31.0 - Add support for per-flip tiling attribute changes with DC
* - 3.32.0 - Add syncobj timeline support to AMDGPU_CS.
* - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS.
+ * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches
*/
#define KMS_DRIVER_MAJOR 3
-#define KMS_DRIVER_MINOR 33
+#define KMS_DRIVER_MINOR 34
#define KMS_DRIVER_PATCHLEVEL 0
#define AMDGPU_MAX_TIMEOUT_PARAM_LENTH 256
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index 1f0426d2fc2a..c609b7af0b6b 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -233,6 +233,7 @@ static void dce_v10_0_page_flip(struct amdgpu_device *adev,
int crtc_id, u64 crtc_base, bool async)
{
struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
+ struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;
u32 tmp;
/* flip at hsync for async, default is vsync */
@@ -240,6 +241,9 @@ static void dce_v10_0_page_flip(struct amdgpu_device *adev,
tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
GRPH_SURFACE_UPDATE_H_RETRACE_EN, async ? 1 : 0);
WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
+ /* update pitch */
+ WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,
+ fb->pitches[0] / fb->format->cpp[0]);
/* update the primary scanout address */
WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
upper_32_bits(crtc_base));
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index 2280b971d758..719db058b306 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -251,6 +251,7 @@ static void dce_v11_0_page_flip(struct amdgpu_device *adev,
int crtc_id, u64 crtc_base, bool async)
{
struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
+ struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;
u32 tmp;
/* flip immediate for async, default is vsync */
@@ -258,6 +259,9 @@ static void dce_v11_0_page_flip(struct amdgpu_device *adev,
tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
GRPH_SURFACE_UPDATE_IMMEDIATE_EN, async ? 1 : 0);
WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
+ /* update pitch */
+ WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,
+ fb->pitches[0] / fb->format->cpp[0]);
/* update the scanout addresses */
WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
upper_32_bits(crtc_base));
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
index bea32f076b91..8ee99651d01a 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
@@ -186,10 +186,14 @@ static void dce_v6_0_page_flip(struct amdgpu_device *adev,
int crtc_id, u64 crtc_base, bool async)
{
struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
+ struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;
/* flip at hsync for async, default is vsync */
WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ?
GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0);
+ /* update pitch */
+ WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,
+ fb->pitches[0] / fb->format->cpp[0]);
/* update the scanout addresses */
WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
upper_32_bits(crtc_base));
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
index 13da915991dd..7037e016493c 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
@@ -181,10 +181,14 @@
[PATCH 3/3] drm/amdkfd: Save/restore vcc on gfx10
VCC moved out of user SGPR allocation in gfx10. It's now stored
in SGPRs 106-107.
Also fixes incorrect SGPR read offsets.
Cc: Shaoyun Liu
Signed-off-by: Jay Cornwall
---
drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h | 452 ++---
.../gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm | 34 +-
2 files changed, 243 insertions(+), 243 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
index 8089bb3..a8cf82d 100644
--- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
+++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
@@ -680,7 +680,7 @@ static const uint32_t cwsr_trap_gfx9_hex[] = {
};
static const uint32_t cwsr_trap_gfx10_hex[] = {
- 0xbf820001, 0xbf8201c0,
+ 0xbf820001, 0xbf8201c1,
0xb0804004, 0xb978f802,
0x8a788678, 0xb971f803,
0x876eff71, 0x0400,
@@ -804,271 +804,271 @@ static const uint32_t cwsr_trap_gfx10_hex[] = {
0x0060, 0xbf85ffea,
0xbe802f00, 0xbe822f02,
0xbe842f04, 0xbe862f06,
- 0xbe882f08, 0xf469003a,
- 0xfa00, 0xf469013a,
- 0xfa10, 0xf465023a,
- 0xfa20, 0x8074c074,
- 0x82758075, 0xbef40372,
- 0xbefa0380, 0xbefe03c1,
- 0x907c9973, 0x877c817c,
- 0xbf06817c, 0xbf850002,
- 0xbeff0380, 0xbf820002,
- 0xbeff03c1, 0xbf82000b,
+ 0xbe882f08, 0xbe8a2f0a,
+ 0xf469003a, 0xfa00,
+ 0xf469013a, 0xfa10,
+ 0xf469023a, 0xfa20,
+ 0x8074b074, 0x82758075,
+ 0xbef40372, 0xbefa0380,
+ 0xbefe03c1, 0x907c9973,
+ 0x877c817c, 0xbf06817c,
+ 0xbf850002, 0xbeff0380,
+ 0xbf820002, 0xbeff03c1,
+ 0xbf82000b, 0xbef603ff,
+ 0x0100, 0xe0704000,
+ 0x7a5d, 0xe0704080,
+ 0x7a5d0100, 0xe0704100,
+ 0x7a5d0200, 0xe0704180,
+ 0x7a5d0300, 0xbf82000a,
0xbef603ff, 0x0100,
0xe0704000, 0x7a5d,
- 0xe0704080, 0x7a5d0100,
- 0xe0704100, 0x7a5d0200,
- 0xe0704180, 0x7a5d0300,
- 0xbf82000a, 0xbef603ff,
- 0x0100, 0xe0704000,
- 0x7a5d, 0xe0704100,
- 0x7a5d0100, 0xe0704200,
- 0x7a5d0200, 0xe0704300,
- 0x7a5d0300, 0xbefe03c1,
+ 0xe0704100, 0x7a5d0100,
+ 0xe0704200, 0x7a5d0200,
+ 0xe0704300, 0x7a5d0300,
+ 0xbefe03c1, 0x907c9973,
+ 0x877c817c, 0xbf06817c,
+ 0xbf850002, 0xbeff0380,
+ 0xbf820001, 0xbeff03c1,
+ 0xb9714306, 0x8771c171,
+ 0xbf840046, 0xbf8a,
+ 0x8776ff6f, 0x0400,
+ 0xbf840042, 0x8f718671,
+ 0x8f718271, 0xbef60371,
+ 0xb97a2a05, 0x807a817a,
0x907c9973, 0x877c817c,
0xbf06817c, 0xbf850002,
- 0xbeff0380, 0xbf820001,
- 0xbeff03c1, 0xb9714306,
- 0x8771c171, 0xbf840046,
- 0xbf8a, 0x8776ff6f,
- 0x0400, 0xbf840042,
- 0x8f718671, 0x8f718271,
- 0xbef60371, 0xb97a2a05,
- 0x807a817a, 0x907c9973,
+ 0x8f7a897a, 0xbf820001,
+ 0x8f7a8a7a, 0xb9761e06,
+ 0x8f768a76, 0x807a767a,
+ 0x807aff7a, 0x0200,
+ 0x807aff7a, 0x0080,
+ 0xbef603ff, 0x0100,
+ 0xd765, 0x000100c1,
+ 0xd766, 0x000200c1,
+ 0x1684, 0x907c9973,
0x877c817c, 0xbf06817c,
- 0xbf850002, 0x8f7a897a,
- 0xbf820001, 0x8f7a8a7a,
- 0xb9761e06, 0x8f768a76,
- 0x807a767a, 0x807aff7a,
- 0x0200, 0x807aff7a,
- 0x0080, 0xbef603ff,
- 0x0100, 0xd765,
- 0x000100c1, 0xd766,
- 0x000200c1, 0x1684,
- 0x907c9973, 0x877c817c,
- 0xbf06817c, 0xbefc0380,
- 0xbf850012, 0xbe8303ff,
- 0x0080, 0xbf80,
+ 0xbefc0380, 0xbf850012,
+ 0xbe8303ff, 0x0080,
0xbf80, 0xbf80,
- 0xd8d8, 0x0100,
- 0xbf8c, 0xe0704000,
- 0x7a5d0100, 0x807c037c,
- 0x807a037a, 0xd525,
- 0x0001ff00, 0x0080,
- 0xbf0a717c, 0xbf85fff4,
- 0xbf820011, 0xbe8303ff,
- 0x0100, 0xbf80,
+ 0xbf80, 0xd8d8,
+ 0x0100, 0xbf8c,
+ 0xe0704000, 0x7a5d0100,
+ 0x807c037c, 0x807a037a,
+ 0xd525, 0x0001ff00,
+ 0x0080, 0xbf0a717c,
+ 0xbf85fff4, 0xbf820011,
+ 0xbe8303ff, 0x0100,
0xbf80, 0xbf80,
- 0xd8d8, 0x0100,
- 0xbf8c, 0xe0704000,
- 0x7a5d0100, 0x807c037c,
- 0x807a037a, 0xd525,
- 0x0001ff00, 0x0100,
- 0xbf0a717c, 0xbf85fff4,
- 0xbefe03c1, 0x907c9973,
- 0x877c817c, 0xbf06817c,
- 0xbf850004, 0xbefa03ff,
- 0x0200, 0xbeff0380,
- 0xbf820003, 0xbefa03ff,
- 0x0400, 0xbeff03c1,
- 0xb9712a05, 0x80718171,
- 0x8f718271, 0x907c9973,
- 0x877c817c, 0xbf06817c,
- 0xbf850017, 0xbef603ff,
- 0x0100, 0xbefc0384,
- 0xbf0a717c, 0xbf840037,
- 0x7e008700, 0x7e028701,
- 0x7e048702,
[PATCH 1/3] drm/amdkfd: Fix gfx10 wave64 VGPR context restore
Copy/paste error, first 4 VGPRs are separated by 64 dwords (256 bytes).
Cc: Shaoyun Liu
Signed-off-by: Jay Cornwall
---
drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h | 6 +++---
drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm | 6 +++---
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
index 2b3d701..c10e424 100644
--- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
+++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
@@ -982,9 +982,9 @@ static const uint32_t cwsr_trap_gfx10_hex[] = {
0x0080, 0xbf0a6f7c,
0xbf85fff7, 0xbeff03c1,
0xe0304000, 0x725d,
- 0xe0304080, 0x725d0100,
- 0xe0304100, 0x725d0200,
- 0xe0304180, 0x725d0300,
+ 0xe0304100, 0x725d0100,
+ 0xe0304200, 0x725d0200,
+ 0xe0304300, 0x725d0300,
0xb9782a05, 0x80788178,
0x907c9973, 0x877c817c,
0xbf06817c, 0xbf850002,
diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm
b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm
index 261e054..be6f7d1 100644
--- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm
+++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm
@@ -747,9 +747,9 @@ L_RESTORE_SHARED_VGPR_WAVE64_LOOP:
/* VGPR restore on v0 */
L_RESTORE_V0:
buffer_load_dword v0, v0, s_restore_buf_rsrc0,
s_restore_mem_offset_save slc:1 glc:1
- buffer_load_dword v1, v0, s_restore_buf_rsrc0,
s_restore_mem_offset_save slc:1 glc:1 offset:128
- buffer_load_dword v2, v0, s_restore_buf_rsrc0,
s_restore_mem_offset_save slc:1 glc:1 offset:128*2
- buffer_load_dword v3, v0, s_restore_buf_rsrc0,
s_restore_mem_offset_save slc:1 glc:1 offset:128*3
+ buffer_load_dword v1, v0, s_restore_buf_rsrc0,
s_restore_mem_offset_save slc:1 glc:1 offset:256
+ buffer_load_dword v2, v0, s_restore_buf_rsrc0,
s_restore_mem_offset_save slc:1 glc:1 offset:256*2
+ buffer_load_dword v3, v0, s_restore_buf_rsrc0,
s_restore_mem_offset_save slc:1 glc:1 offset:256*3
/* restore SGPRs */
//will be 2+8+16*6
--
2.7.4
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 2/3] drm/amdkfd: Save/restore flat_scratch_lo/hi on gfx10
These moved from SGPRs in gfx9 to HWREG in gfx10.
Cc: Shaoyun Liu
Signed-off-by: Jay Cornwall
---
drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h | 56 +-
.../gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm | 14 ++
2 files changed, 48 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
index c10e424..8089bb3 100644
--- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
+++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
@@ -680,7 +680,7 @@ static const uint32_t cwsr_trap_gfx9_hex[] = {
};
static const uint32_t cwsr_trap_gfx10_hex[] = {
- 0xbf820001, 0xbf8201b2,
+ 0xbf820001, 0xbf8201c0,
0xb0804004, 0xb978f802,
0x8a788678, 0xb971f803,
0x876eff71, 0x0400,
@@ -772,6 +772,13 @@ static const uint32_t cwsr_trap_gfx10_hex[] = {
0xb97bf801, 0xbefe037c,
0xbefc037a, 0xf4611efa,
0xf800, 0x807a847a,
+ 0xbefc037e, 0xb97bf814,
+ 0xbefe037c, 0xbefc037a,
+ 0xf4611efa, 0xf800,
+ 0x807a847a, 0xbefc037e,
+ 0xb97bf815, 0xbefe037c,
+ 0xbefc037a, 0xf4611efa,
+ 0xf800, 0x807a847a,
0xbefc037e, 0x8776ff7f,
0x0400, 0xbeef0380,
0x886f6f76, 0xb97a2a05,
@@ -897,7 +904,7 @@ static const uint32_t cwsr_trap_gfx10_hex[] = {
0xe0704000, 0x7a5d,
0x807c817c, 0x807aff7a,
0x0080, 0xbf0a717c,
- 0xbf85fff8, 0xbf820138,
+ 0xbf85fff8, 0xbf820141,
0xbef4037e, 0x8775ff7f,
0x, 0x8875ff75,
0x0004, 0xbef60380,
@@ -1033,30 +1040,35 @@ static const uint32_t cwsr_trap_gfx10_hex[] = {
0x80788478, 0xf4211e7a,
0xf000, 0x80788478,
0xf4211cfa, 0xf000,
+ 0x80788478, 0xf4211bba,
+ 0xf000, 0x80788478,
+ 0xbf8cc07f, 0xb9eef814,
+ 0xf4211bba, 0xf000,
0x80788478, 0xbf8cc07f,
- 0xbef2036d, 0x876dff72,
- 0x, 0xbefc036f,
- 0xbefe037a, 0xbeff037b,
- 0x876f71ff, 0x03ff,
- 0xb9ef4803, 0xb9f9f816,
- 0x876f71ff, 0xf800,
- 0x906f8b6f, 0xb9efa2c3,
- 0xb9f3f801, 0x876fff72,
- 0xfc00, 0x906f9a6f,
- 0x8f6f906f, 0xbef30380,
+ 0xb9eef815, 0xbef2036d,
+ 0x876dff72, 0x,
+ 0xbefc036f, 0xbefe037a,
+ 0xbeff037b, 0x876f71ff,
+ 0x03ff, 0xb9ef4803,
+ 0xb9f9f816, 0x876f71ff,
+ 0xf800, 0x906f8b6f,
+ 0xb9efa2c3, 0xb9f3f801,
+ 0x876fff72, 0xfc00,
+ 0x906f9a6f, 0x8f6f906f,
+ 0xbef30380, 0x88736f73,
+ 0x876fff72, 0x0200,
+ 0x906f996f, 0x8f6f8f6f,
0x88736f73, 0x876fff72,
- 0x0200, 0x906f996f,
- 0x8f6f8f6f, 0x88736f73,
- 0x876fff72, 0x0100,
- 0x906f986f, 0x8f6f996f,
- 0x88736f73, 0x876fff70,
- 0x0080, 0x906f976f,
- 0xb9f3f807, 0x87fe7e7e,
- 0x87ea6a6a, 0xb9f0f802,
- 0xbf8a, 0xbe80226c,
- 0xbf81, 0xbf9f,
+ 0x0100, 0x906f986f,
+ 0x8f6f996f, 0x88736f73,
+ 0x876fff70, 0x0080,
+ 0x906f976f, 0xb9f3f807,
+ 0x87fe7e7e, 0x87ea6a6a,
+ 0xb9f0f802, 0xbf8a,
+ 0xbe80226c, 0xbf81,
0xbf9f, 0xbf9f,
0xbf9f, 0xbf9f,
+ 0xbf9f, 0x,
};
static const uint32_t cwsr_trap_arcturus_hex[] = {
0xbf820001, 0xbf8202c4,
diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm
b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm
index be6f7d1..fafdfd2 100644
--- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm
+++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm
@@ -132,6 +132,7 @@ var s_restore_tmp = ttmp6
var s_restore_mem_offset_save = s_restore_tmp
var s_restore_m0 = s_restore_alloc_size
var s_restore_mode = ttmp7
+var s_restore_flat_scratch = ttmp2
var s_restore_pc_lo= ttmp0
var s_restore_pc_hi= ttmp1
var s_restore_exec_lo = ttmp14
@@ -313,6 +314,12 @@ L_SAVE_HWREG:
s_getreg_b32s_save_m0, hwreg(HW_REG_MODE)
write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset)
+ s_getreg_b32s_save_m0, hwreg(HW_REG_SHADER_FLAT_SCRATCH_LO)
+ write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset)
+
+ s_getreg_b32s_save_m0, hwreg(HW_REG_SHADER_FLAT_SCRATCH_HI)
+ write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset)
+
/* the first wave in the threadgroup */
s_and_b32 s_save_tmp, s_save_spi_init_hi,
S_SAVE_SPI_INIT_FIRST_WAVE_MASK
s_mov_b32 s_save_exec_hi, 0x0
@@ -824,9 +831,16 @@ L_RESTORE_HWREG:
read_hwreg_from_mem(s_restore_trapsts, s_restore_buf_rsrc0,
s_restore_mem_offset)
Re: TTM refcount problem.
Is this a known issue? No, that looks like a new one to me. Is that somehow reproducible? Christian. Am 29.07.19 um 10:14 schrieb Bas Nieuwenhuizen: Hi all, I have a TTM refcount issue: [173774.309968] [ cut here ] [173774.309970] kernel BUG at drivers/gpu/drm/ttm/ttm_bo.c:202! [173774.309982] invalid opcode: [#1] PREEMPT SMP NOPTI [173774.309985] CPU: 13 PID: 128214 Comm: kworker/13:2 Not tainted 5.2.0-rc1-g3f2e519b0974 #10 [173774.309986] Hardware name: To Be Filled By O.E.M. To Be Filled By O.E.M./X399 Taichi, BIOS P1.50 09/05/2017 [173774.309995] Workqueue: events ttm_bo_delayed_workqueue [ttm] [173774.31] RIP: 0010:ttm_bo_ref_bug+0x5/0x10 [ttm] [173774.310002] Code: c0 c3 b8 01 00 00 00 c3 66 66 2e 0f 1f 84 00 00 00 00 00 66 90 0f 1f 44 00 00 f0 ff 8f a4 00 00 00 c3 0f 1f 00 0f 1f 44 00 00 <0f> 0b 66 0f 1f 84 00 00 00 00 00 0f 1f 44 00 00 53 48 8b 07 48 89 [173774.310003] RSP: 0018:b42e5589bde8 EFLAGS: 00010246 [173774.310005] RAX: b42e5589be40 RBX: 9395fd0cd908 RCX: 9395fd0cd8f8 [173774.310006] RDX: b42e5589be40 RSI: 939b59b64f18 RDI: 9395fd0cd87c [173774.310007] RBP: c0930f40 R08: 0014 R09: c091f100 [173774.310008] R10: 9399f69b0800 R11: 0001 R12: [173774.310009] R13: 9395fd0cd850 R14: 0001 R15: 0001 [173774.310010] FS: () GS:939b7d34() knlGS: [173774.310011] CS: 0010 DS: ES: CR0: 80050033 [173774.310012] CR2: 7f4f64008838 CR3: 000643baa000 CR4: 003406e0 [173774.310013] Call Trace: [173774.310019] ttm_bo_cleanup_refs+0x160/0x1e0 [ttm] [173774.310025] ttm_bo_delayed_delete+0xa8/0x1e0 [ttm] [173774.310029] ttm_bo_delayed_workqueue+0x17/0x40 [ttm] [173774.310033] process_one_work+0x1fd/0x430 [173774.310036] worker_thread+0x2d/0x3d0 [173774.310038] ? process_one_work+0x430/0x430 [173774.310040] kthread+0x112/0x130 [173774.310042] ? kthread_create_on_node+0x60/0x60 [173774.310045] ret_from_fork+0x22/0x40 [173774.310048] Modules linked in: fuse nct6775 hwmon_vid nls_iso8859_1 nls_cp437 vfat fat edac_mce_amd kvm_amd kvm irqbypass amdgpu arc4 iwlmvm mac80211 snd_usb_audio uvcvideo snd_usbmidi_lib videobuf2_vmalloc crct10dif_pclmul videobuf2_memops snd_hda_codec_realtek videobuf2_v4l2 btusb gpu_sched snd_rawmidi videobuf2_common snd_hda_codec_generic btrtl videodev crc32_pclmul btbcm snd_seq_device ledtrig_audio ttm btintel ghash_clmulni_intel wmi_bmof mxm_wmi snd_hda_codec_hdmi media bluetooth drm_kms_helper iwlwifi snd_hda_intel drm aesni_intel snd_hda_codec joydev input_leds aes_x86_64 snd_hda_core mousedev evdev crypto_simd cryptd ecdh_generic led_class agpgart snd_hwdep mac_hid cdc_acm glue_helper ecc snd_pcm igb syscopyarea pcspkr cfg80211 sysfillrect snd_timer sysimgblt snd fb_sys_fops ccp ptp soundcore pps_core rng_core k10temp i2c_algo_bit sp5100_tco dca i2c_piix4 rfkill wmi pcc_cpufreq button acpi_cpufreq sch_fq_codel ip_tables x_tables ext4 crc32c_generic crc16 mbcache jbd2 sd_mod [173774.310085] hid_generic usbhid hid crc32c_intel ahci xhci_pci libahci xhci_hcd libata usbcore scsi_mod usb_common [173774.310094] ---[ end trace 1f8d21980c0b3fd5 ]--- [173774.310097] RIP: 0010:ttm_bo_ref_bug+0x5/0x10 [ttm] [173774.310099] Code: c0 c3 b8 01 00 00 00 c3 66 66 2e 0f 1f 84 00 00 00 00 00 66 90 0f 1f 44 00 00 f0 ff 8f a4 00 00 00 c3 0f 1f 00 0f 1f 44 00 00 <0f> 0b 66 0f 1f 84 00 00 00 00 00 0f 1f 44 00 00 53 48 8b 07 48 89 [173774.310100] RSP: 0018:b42e5589bde8 EFLAGS: 00010246 [173774.310101] RAX: b42e5589be40 RBX: 9395fd0cd908 RCX: 9395fd0cd8f8 [173774.310102] RDX: b42e5589be40 RSI: 939b59b64f18 RDI: 9395fd0cd87c [173774.310103] RBP: c0930f40 R08: 0014 R09: c091f100 [173774.310104] R10: 9399f69b0800 R11: 0001 R12: [173774.310104] R13: 9395fd0cd850 R14: 0001 R15: 0001 [173774.310106] FS: () GS:939b7d34() knlGS: [173774.310107] CS: 0010 DS: ES: CR0: 80050033 [173774.310107] CR2: 7f4f64008838 CR3: 000643baa000 CR4: 003406e0 [173774.310110] note: kworker/13:2[128214] exited with preempt_count 1 With amd-staging-drm-next: commit 20d6b9c3b7f40ec427af912d140f2be0de098d2d (origin/amd-staging-drm-next) Author: Gustavo A. R. Silva Date: Mon Jul 22 12:47:16 2019 -0500 drm/amdkfd/kfd_mqd_manager_v10: Avoid fall-through warning with a Vega10. Is this a known issue? Thanks, Bas ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH v6 10/24] drm/imx: imx-ldb: Provide ddc symlink in connector's sysfs
On Fri, 2019-07-26 at 19:23 +0200, Andrzej Pietrasiewicz wrote: > Use the ddc pointer provided by the generic connector. > > Signed-off-by: Andrzej Pietrasiewicz Acked-by: Philipp Zabel Thanks! regards Philipp > --- > drivers/gpu/drm/imx/imx-ldb.c | 7 --- > 1 file changed, 4 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/imx/imx-ldb.c b/drivers/gpu/drm/imx/imx-ldb.c > index de62a4cd4827..db461b6a257f 100644 > --- a/drivers/gpu/drm/imx/imx-ldb.c > +++ b/drivers/gpu/drm/imx/imx-ldb.c > @@ -462,9 +462,10 @@ static int imx_ldb_register(struct drm_device *drm, >*/ > drm_connector_helper_add(_ldb_ch->connector, > _ldb_connector_helper_funcs); > - drm_connector_init(drm, _ldb_ch->connector, > - _ldb_connector_funcs, > - DRM_MODE_CONNECTOR_LVDS); > + drm_connector_init_with_ddc(drm, _ldb_ch->connector, > + _ldb_connector_funcs, > + DRM_MODE_CONNECTOR_LVDS, > + imx_ldb_ch->ddc); > drm_connector_attach_encoder(_ldb_ch->connector, encoder); > } > ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH v6 11/24] drm/imx: imx-tve: Provide ddc symlink in connector's sysfs
On Fri, 2019-07-26 at 19:23 +0200, Andrzej Pietrasiewicz wrote: > Use the ddc pointer provided by the generic connector. > > Signed-off-by: Andrzej Pietrasiewicz Acked-by: Philipp Zabel regards Philipp > --- > drivers/gpu/drm/imx/imx-tve.c | 6 -- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/imx/imx-tve.c b/drivers/gpu/drm/imx/imx-tve.c > index 649515868f86..5bbfaa2cd0f4 100644 > --- a/drivers/gpu/drm/imx/imx-tve.c > +++ b/drivers/gpu/drm/imx/imx-tve.c > @@ -484,8 +484,10 @@ static int imx_tve_register(struct drm_device *drm, > struct imx_tve *tve) > > drm_connector_helper_add(>connector, > _tve_connector_helper_funcs); > - drm_connector_init(drm, >connector, _tve_connector_funcs, > -DRM_MODE_CONNECTOR_VGA); > + drm_connector_init_with_ddc(drm, >connector, > + _tve_connector_funcs, > + DRM_MODE_CONNECTOR_VGA, > + tve->ddc); > > drm_connector_attach_encoder(>connector, >encoder); > ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH v5 02/24] drm: Add drm_connector_init() variant with ddc
On Wed, 24 Jul 2019, Andrzej Pietrasiewicz wrote:
> Allow passing ddc adapter pointer to the init function. Even if
> drm_connector_init() sometime in the future decides to e.g. memset() all
> connector fields to zeros, the newly added function ensures that at its
> completion the ddc member of connector is correctly set.
>
> Signed-off-by: Andrzej Pietrasiewicz
> ---
> drivers/gpu/drm/drm_connector.c | 19 +++
> include/drm/drm_connector.h | 5 +
> 2 files changed, 24 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
> index 068d4b05f1be..06fbfc44fb48 100644
> --- a/drivers/gpu/drm/drm_connector.c
> +++ b/drivers/gpu/drm/drm_connector.c
> @@ -296,6 +296,25 @@ int drm_connector_init(struct drm_device *dev,
> }
> EXPORT_SYMBOL(drm_connector_init);
>
> +int drm_connector_init_with_ddc(struct drm_device *dev,
> + struct drm_connector *connector,
> + const struct drm_connector_funcs *funcs,
> + int connector_type,
> + struct i2c_adapter *ddc)
Playing the devil's advocate here a bit. What if you end up adding
another thing you need to initialize like this? Are you going to need
three more functions to account for the combinations? Init with ddc,
with foo, with ddc and foo? So I generally frown upon interfaces like
this.
If everyone thinks this is the way to go, I'm not going to stand in the
way, but personally I'd rather switch over all of i915 to a new version
of drm_connector_init() that just takes another parameter.
BR,
Jani.
> +{
> + int ret;
> +
> + ret = drm_connector_init(dev, connector, funcs, connector_type);
> + if (ret)
> + return ret;
> +
> + /* provide ddc symlink in sysfs */
> + connector->ddc = ddc;
> +
> + return ret;
> +}
> +EXPORT_SYMBOL(drm_connector_init_with_ddc);
> +
> /**
> * drm_connector_attach_edid_property - attach edid property.
> * @connector: the connector
> diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
> index 33a6fff85fdb..937fda9c1374 100644
> --- a/include/drm/drm_connector.h
> +++ b/include/drm/drm_connector.h
> @@ -1410,6 +1410,11 @@ int drm_connector_init(struct drm_device *dev,
> struct drm_connector *connector,
> const struct drm_connector_funcs *funcs,
> int connector_type);
> +int drm_connector_init_with_ddc(struct drm_device *dev,
> + struct drm_connector *connector,
> + const struct drm_connector_funcs *funcs,
> + int connector_type,
> + struct i2c_adapter *ddc);
> void drm_connector_attach_edid_property(struct drm_connector *connector);
> int drm_connector_register(struct drm_connector *connector);
> void drm_connector_unregister(struct drm_connector *connector);
--
Jani Nikula, Intel Open Source Graphics Center
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] gpu: drm: radeon: Fix a possible null-pointer dereference in radeon_connector_set_property()
In radeon_connector_set_property(), there is an if statement on line 743
to check whether connector->encoder is NULL:
if (connector->encoder)
When connector->encoder is NULL, it is used on line 755:
if (connector->encoder->crtc)
Thus, a possible null-pointer dereference may occur.
To fix this bug, connector->encoder is checked before being used.
This bug is found by a static analysis tool STCheck written by us.
Signed-off-by: Jia-Ju Bai
---
drivers/gpu/drm/radeon/radeon_connectors.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c
b/drivers/gpu/drm/radeon/radeon_connectors.c
index c60d1a44d22a..b684cd719612 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -752,7 +752,7 @@ static int radeon_connector_set_property(struct
drm_connector *connector, struct
radeon_encoder->output_csc = val;
- if (connector->encoder->crtc) {
+ if (connector->encoder && connector->encoder->crtc) {
struct drm_crtc *crtc = connector->encoder->crtc;
struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
--
2.17.0
TTM refcount problem.
Hi all, I have a TTM refcount issue: [173774.309968] [ cut here ] [173774.309970] kernel BUG at drivers/gpu/drm/ttm/ttm_bo.c:202! [173774.309982] invalid opcode: [#1] PREEMPT SMP NOPTI [173774.309985] CPU: 13 PID: 128214 Comm: kworker/13:2 Not tainted 5.2.0-rc1-g3f2e519b0974 #10 [173774.309986] Hardware name: To Be Filled By O.E.M. To Be Filled By O.E.M./X399 Taichi, BIOS P1.50 09/05/2017 [173774.309995] Workqueue: events ttm_bo_delayed_workqueue [ttm] [173774.31] RIP: 0010:ttm_bo_ref_bug+0x5/0x10 [ttm] [173774.310002] Code: c0 c3 b8 01 00 00 00 c3 66 66 2e 0f 1f 84 00 00 00 00 00 66 90 0f 1f 44 00 00 f0 ff 8f a4 00 00 00 c3 0f 1f 00 0f 1f 44 00 00 <0f> 0b 66 0f 1f 84 00 00 00 00 00 0f 1f 44 00 00 53 48 8b 07 48 89 [173774.310003] RSP: 0018:b42e5589bde8 EFLAGS: 00010246 [173774.310005] RAX: b42e5589be40 RBX: 9395fd0cd908 RCX: 9395fd0cd8f8 [173774.310006] RDX: b42e5589be40 RSI: 939b59b64f18 RDI: 9395fd0cd87c [173774.310007] RBP: c0930f40 R08: 0014 R09: c091f100 [173774.310008] R10: 9399f69b0800 R11: 0001 R12: [173774.310009] R13: 9395fd0cd850 R14: 0001 R15: 0001 [173774.310010] FS: () GS:939b7d34() knlGS: [173774.310011] CS: 0010 DS: ES: CR0: 80050033 [173774.310012] CR2: 7f4f64008838 CR3: 000643baa000 CR4: 003406e0 [173774.310013] Call Trace: [173774.310019] ttm_bo_cleanup_refs+0x160/0x1e0 [ttm] [173774.310025] ttm_bo_delayed_delete+0xa8/0x1e0 [ttm] [173774.310029] ttm_bo_delayed_workqueue+0x17/0x40 [ttm] [173774.310033] process_one_work+0x1fd/0x430 [173774.310036] worker_thread+0x2d/0x3d0 [173774.310038] ? process_one_work+0x430/0x430 [173774.310040] kthread+0x112/0x130 [173774.310042] ? kthread_create_on_node+0x60/0x60 [173774.310045] ret_from_fork+0x22/0x40 [173774.310048] Modules linked in: fuse nct6775 hwmon_vid nls_iso8859_1 nls_cp437 vfat fat edac_mce_amd kvm_amd kvm irqbypass amdgpu arc4 iwlmvm mac80211 snd_usb_audio uvcvideo snd_usbmidi_lib videobuf2_vmalloc crct10dif_pclmul videobuf2_memops snd_hda_codec_realtek videobuf2_v4l2 btusb gpu_sched snd_rawmidi videobuf2_common snd_hda_codec_generic btrtl videodev crc32_pclmul btbcm snd_seq_device ledtrig_audio ttm btintel ghash_clmulni_intel wmi_bmof mxm_wmi snd_hda_codec_hdmi media bluetooth drm_kms_helper iwlwifi snd_hda_intel drm aesni_intel snd_hda_codec joydev input_leds aes_x86_64 snd_hda_core mousedev evdev crypto_simd cryptd ecdh_generic led_class agpgart snd_hwdep mac_hid cdc_acm glue_helper ecc snd_pcm igb syscopyarea pcspkr cfg80211 sysfillrect snd_timer sysimgblt snd fb_sys_fops ccp ptp soundcore pps_core rng_core k10temp i2c_algo_bit sp5100_tco dca i2c_piix4 rfkill wmi pcc_cpufreq button acpi_cpufreq sch_fq_codel ip_tables x_tables ext4 crc32c_generic crc16 mbcache jbd2 sd_mod [173774.310085] hid_generic usbhid hid crc32c_intel ahci xhci_pci libahci xhci_hcd libata usbcore scsi_mod usb_common [173774.310094] ---[ end trace 1f8d21980c0b3fd5 ]--- [173774.310097] RIP: 0010:ttm_bo_ref_bug+0x5/0x10 [ttm] [173774.310099] Code: c0 c3 b8 01 00 00 00 c3 66 66 2e 0f 1f 84 00 00 00 00 00 66 90 0f 1f 44 00 00 f0 ff 8f a4 00 00 00 c3 0f 1f 00 0f 1f 44 00 00 <0f> 0b 66 0f 1f 84 00 00 00 00 00 0f 1f 44 00 00 53 48 8b 07 48 89 [173774.310100] RSP: 0018:b42e5589bde8 EFLAGS: 00010246 [173774.310101] RAX: b42e5589be40 RBX: 9395fd0cd908 RCX: 9395fd0cd8f8 [173774.310102] RDX: b42e5589be40 RSI: 939b59b64f18 RDI: 9395fd0cd87c [173774.310103] RBP: c0930f40 R08: 0014 R09: c091f100 [173774.310104] R10: 9399f69b0800 R11: 0001 R12: [173774.310104] R13: 9395fd0cd850 R14: 0001 R15: 0001 [173774.310106] FS: () GS:939b7d34() knlGS: [173774.310107] CS: 0010 DS: ES: CR0: 80050033 [173774.310107] CR2: 7f4f64008838 CR3: 000643baa000 CR4: 003406e0 [173774.310110] note: kworker/13:2[128214] exited with preempt_count 1 With amd-staging-drm-next: commit 20d6b9c3b7f40ec427af912d140f2be0de098d2d (origin/amd-staging-drm-next) Author: Gustavo A. R. Silva Date: Mon Jul 22 12:47:16 2019 -0500 drm/amdkfd/kfd_mqd_manager_v10: Avoid fall-through warning with a Vega10. Is this a known issue? Thanks, Bas ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: fix a potential information leaking bug
Coccinelle reports a path that the array "data" is never initialized. The path skips the checks in the conditional branches when either of callback functions, read_wave_vgprs and read_wave_sgprs, is not registered. Later, the uninitialized "data" array is read in the while-loop below and passed to put_user(). Fix the path by allocating the array with kcalloc(). The patch is simplier than adding a fall-back branch that explicitly calls memset(data, 0, ...). Also it does not need the multiplication 1024*sizeof(*data) as the size parameter for memset() though there is no risk of integer overflow. Signed-off-by: Wang Xiayang --- drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c index 6d54decef7f8..5652cc72ed3a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c @@ -707,7 +707,7 @@ static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user *buf, thread = (*pos & GENMASK_ULL(59, 52)) >> 52; bank = (*pos & GENMASK_ULL(61, 60)) >> 60; - data = kmalloc_array(1024, sizeof(*data), GFP_KERNEL); + data = kcalloc(1024, sizeof(*data), GFP_KERNEL); if (!data) return -ENOMEM; -- 2.11.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
