Re: [PATCH] drm/amdgpu: user pages array memory leak fix

2019-10-03 Thread Joe Barnett 
I've tested applying v2 of this patch against a v5.3 tagged kernel and it
appears to fix the issue I reported.

Thanks,
-Joe

On Thu, Oct 3, 2019 at 12:07 PM Yang, Philip  wrote:

> user_pages array should be freed regardless if user pages are
> invalidated after bo is created because HMM change to always allocate
> user pages array to get user pages while parsing user page bo.
>
> Don't need to to get user pages while creating bo because user pages
> will only be used after parsing user page bo.
>
> Bugzilla: https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1844962
>
> Signed-off-by: Philip Yang 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c  |  2 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 23 +--
>  2 files changed, 2 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> index 49b767b7238f..e861de259def 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> @@ -498,7 +498,7 @@ static int amdgpu_cs_list_validate(struct
> amdgpu_cs_parser *p,
> if (r)
> return r;
>
> -   if (binding_userptr) {
> +   if (lobj->user_pages) {
> kvfree(lobj->user_pages);
> lobj->user_pages = NULL;
> }
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> index a828e3d0bfbd..3ccd61d69964 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> @@ -283,7 +283,6 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev,
> void *data,
>  int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
>  struct drm_file *filp)
>  {
> -   struct ttm_operation_ctx ctx = { true, false };
> struct amdgpu_device *adev = dev->dev_private;
> struct drm_amdgpu_gem_userptr *args = data;
> struct drm_gem_object *gobj;
> @@ -326,32 +325,12 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev,
> void *data,
> goto release_object;
> }
>
> -   if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) {
> -   r = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages);
> -   if (r)
> -   goto release_object;
> -
> -   r = amdgpu_bo_reserve(bo, true);
> -   if (r)
> -   goto user_pages_done;
> -
> -   amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
> -   r = ttm_bo_validate(>tbo, >placement, );
> -   amdgpu_bo_unreserve(bo);
> -   if (r)
> -   goto user_pages_done;
> -   }
> -
> r = drm_gem_handle_create(filp, gobj, );
> if (r)
> -   goto user_pages_done;
> +   goto release_object;
>
> args->handle = handle;
>
> -user_pages_done:
> -   if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE)
> -   amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm);
> -
>  release_object:
> drm_gem_object_put_unlocked(gobj);
>
> --
> 2.17.1
>
>
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[PATCH] drm/amdgpu: Use the ALIGN() macro

2019-10-03 Thread Tuikov, Luben 
Use the ALIGN() macro to set "num_dw" to a
multiple of 8, i.e. lower 3 bits cleared.

Signed-off-by: Luben Tuikov 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 11 ++-
 1 file changed, 2 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 68c541e11189..73c628bc6a5b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1923,10 +1923,7 @@ static int amdgpu_map_buffer(struct ttm_buffer_object 
*bo,
*addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
AMDGPU_GPU_PAGE_SIZE;
 
-   num_dw = adev->mman.buffer_funcs->copy_num_dw;
-   while (num_dw & 0x7)
-   num_dw++;
-
+   num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
num_bytes = num_pages * 8;
 
r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes, );
@@ -1986,11 +1983,7 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, 
uint64_t src_offset,
 
max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
num_loops = DIV_ROUND_UP(byte_count, max_bytes);
-   num_dw = num_loops * adev->mman.buffer_funcs->copy_num_dw;
-
-   /* for IB padding */
-   while (num_dw & 0x7)
-   num_dw++;
+   num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8);
 
r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, );
if (r)
-- 
2.23.0.169.g8a3a6817e2

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re: drm/amd/display: Add HDCP module - static analysis bug report

2019-10-03 Thread Colin Ian King 
Hi,

Static analysis with Coverity has detected a potential issue with
function validate_bksv in
drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c with recent
commit:

commit ed9d8e2bcb003ec94658cafe9b1bb3960e2139ec
Author: Bhawanpreet Lakha 
Date:   Tue Aug 6 17:52:01 2019 -0400

drm/amd/display: Add HDCP module


The analysis is as follows:

 28 static inline enum mod_hdcp_status validate_bksv(struct mod_hdcp *hdcp)
 29 {

CID 89852 (#1 of 1): Out-of-bounds read (OVERRUN)

1. overrun-local:
Overrunning array of 5 bytes at byte offset 7 by dereferencing pointer
(uint64_t *)hdcp->auth.msg.hdcp1.bksv.

 30uint64_t n = *(uint64_t *)hdcp->auth.msg.hdcp1.bksv;
 31uint8_t count = 0;
 32
 33while (n) {
 34count++;
 35n &= (n - 1);
 36}

hdcp->auth.msg.hdcp1.bksv is an array of 5 uint8_t as defined in
drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h as follows:

struct mod_hdcp_message_hdcp1 {
uint8_t an[8];
uint8_t aksv[5];
uint8_t ainfo;
uint8_t bksv[5];
uint16_tr0p;
uint8_t bcaps;
uint16_tbstatus;
uint8_t ksvlist[635];
uint16_tksvlist_size;
uint8_t vp[20];

uint16_tbinfo_dp;
};

variable n is going to contain the contains of r0p and bcaps. I'm not
sure if that is intentional. If not, then the count is going to be
incorrect if these are non-zero.

Colin

[PATCH 1/1] drm/amdgpu: Fix error handling in amdgpu_ras_recovery_init

2019-10-03 Thread Kuehling, Felix 
Don't set a struct pointer to NULL before freeing its members. It's
hard to see what's happening due to a local pointer-to-pointer data
aliasing con->eh_data.

Signed-off-by: Felix Kuehling 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index 486568ded6d6..0e2ee5869b5f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -1542,10 +1542,10 @@ int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
 release:
amdgpu_ras_release_bad_pages(adev);
 free:
-   con->eh_data = NULL;
kfree((*data)->bps);
kfree((*data)->bps_bo);
kfree(*data);
+   con->eh_data = NULL;
 out:
DRM_WARN("Failed to initialize ras recovery!\n");
 
-- 
2.17.1

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[PATCH][next] drm/amdgpu: fix uninitialized variable pasid_mapping_needed

2019-10-03 Thread Colin King 
From: Colin Ian King 

The boolean variable pasid_mapping_needed is not initialized and
there are code paths that do not assign it any value before it is
is read later.  Fix this by initializing pasid_mapping_needed to
false.

Addresses-Coverity: ("Uninitialized scalar variable")
Fixes: 6817bf283b2b ("drm/amdgpu: grab the id mgr lock while accessing 
passid_mapping")
Signed-off-by: Colin Ian King 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index a2c797e34a29..be10e4b9a94d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1055,7 +1055,7 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct 
amdgpu_job *job,
id->oa_size != job->oa_size);
bool vm_flush_needed = job->vm_needs_flush;
struct dma_fence *fence = NULL;
-   bool pasid_mapping_needed;
+   bool pasid_mapping_needed = false;
unsigned patch_offset = 0;
int r;
 
-- 
2.20.1

[PATCH][next] drm/amdgpu: remove redundant variable r and redundant return statement

2019-10-03 Thread Colin King 
From: Colin Ian King 

There is a return statement that is not reachable and a variable that
is not used.  Remove them.

Addresses-Coverity: ("Structurally dead code")
Fixes: de7b45babd9b ("drm/amdgpu: cleanup creating BOs at fixed location (v2)")
Signed-off-by: Colin Ian King 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 481e4c381083..814159f15633 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1636,7 +1636,6 @@ static void amdgpu_ttm_fw_reserve_vram_fini(struct 
amdgpu_device *adev)
 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
 {
uint64_t vram_size = adev->gmc.visible_vram_size;
-   int r;
 
adev->fw_vram_usage.va = NULL;
adev->fw_vram_usage.reserved_bo = NULL;
@@ -1651,7 +1650,6 @@ static int amdgpu_ttm_fw_reserve_vram_init(struct 
amdgpu_device *adev)
  AMDGPU_GEM_DOMAIN_VRAM,
  >fw_vram_usage.reserved_bo,
  >fw_vram_usage.va);
-   return r;
 }
 
 /**
-- 
2.20.1

[PATCH v3] drm/amd/display: fix struct init in update_bounding_box

2019-10-03 Thread Raul E Rangel 
dcn20_resource.c:2636:9: error: missing braces around initializer 
[-Werror=missing-braces]
  struct _vcs_dpi_voltage_scaling_st calculated_states[MAX_CLOCK_LIMIT_STATES] 
= {0};
 ^

Fixes: 7ed4e6352c16f ("drm/amd/display: Add DCN2 HW Sequencer and Resource")

Signed-off-by: Raul E Rangel 

---

Changes in v3:
- Use memset

Changes in v2:
- Use {{0}} instead of {}

 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index b949e202d6cb7..f72c26ae41def 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -2633,7 +2633,7 @@ static void cap_soc_clocks(
 static void update_bounding_box(struct dc *dc, struct 
_vcs_dpi_soc_bounding_box_st *bb,
struct pp_smu_nv_clock_table *max_clocks, unsigned int 
*uclk_states, unsigned int num_states)
 {
-   struct _vcs_dpi_voltage_scaling_st 
calculated_states[MAX_CLOCK_LIMIT_STATES] = {0};
+   struct _vcs_dpi_voltage_scaling_st 
calculated_states[MAX_CLOCK_LIMIT_STATES];
int i;
int num_calculated_states = 0;
int min_dcfclk = 0;
@@ -2641,6 +2641,8 @@ static void update_bounding_box(struct dc *dc, struct 
_vcs_dpi_soc_bounding_box_
if (num_states == 0)
return;
 
+   memset(calculated_states, 0, sizeof(calculated_states));
+
if (dc->bb_overrides.min_dcfclk_mhz > 0)
min_dcfclk = dc->bb_overrides.min_dcfclk_mhz;
else
-- 
2.23.0.444.g18eeb5a265-goog

[PATCH 03/11] drm/amdgpu: convert amdgpu_vm_it to half closed intervals

2019-10-03 Thread Davidlohr Bueso 
The amdgpu_vm interval tree really wants [a, b) intervals,
not fully closed ones. As such convert it to use the new
interval_tree_gen.h, and also rename the 'last' endpoint
in the node to 'end', which is both a more suitable name
for the half closed interval and also reduces the chances
of missing a conversion when doing insertion or lookup.

Cc: Jerome Glisse 
Cc: Alex Deucher 
Cc: "Christian König" 
Cc: Daniel Vetter 
Cc: amd-gfx@lists.freedesktop.org
Signed-off-by: Davidlohr Bueso 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.h |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h  | 18 ++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c|  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c|  3 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 46 +++---
 6 files changed, 36 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 49b767b7238f..290bfe820890 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -756,7 +756,7 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)
}
 
if ((va_start + chunk_ib->ib_bytes) >
-   (m->last + 1) * AMDGPU_GPU_PAGE_SIZE) {
+   m->end * AMDGPU_GPU_PAGE_SIZE) {
DRM_ERROR("IB va_start+ib_bytes is invalid\n");
return -EINVAL;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
index 7e99f6c58c48..60b73bc4d11a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
@@ -51,7 +51,7 @@ struct amdgpu_bo_va_mapping {
struct list_headlist;
struct rb_node  rb;
uint64_tstart;
-   uint64_tlast;
+   uint64_tend;
uint64_t__subtree_last;
uint64_toffset;
uint64_tflags;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
index 8227ebd0f511..c5b0e88d019c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
@@ -247,7 +247,7 @@ TRACE_EVENT(amdgpu_vm_bo_map,
TP_STRUCT__entry(
 __field(struct amdgpu_bo *, bo)
 __field(long, start)
-__field(long, last)
+__field(long, end)
 __field(u64, offset)
 __field(u64, flags)
 ),
@@ -255,12 +255,12 @@ TRACE_EVENT(amdgpu_vm_bo_map,
TP_fast_assign(
   __entry->bo = bo_va ? bo_va->base.bo : NULL;
   __entry->start = mapping->start;
-  __entry->last = mapping->last;
+  __entry->end = mapping->end;
   __entry->offset = mapping->offset;
   __entry->flags = mapping->flags;
   ),
-   TP_printk("bo=%p, start=%lx, last=%lx, offset=%010llx, flags=%llx",
- __entry->bo, __entry->start, __entry->last,
+   TP_printk("bo=%p, start=%lx, end=%lx, offset=%010llx, flags=%llx",
+ __entry->bo, __entry->start, __entry->end,
  __entry->offset, __entry->flags)
 );
 
@@ -271,7 +271,7 @@ TRACE_EVENT(amdgpu_vm_bo_unmap,
TP_STRUCT__entry(
 __field(struct amdgpu_bo *, bo)
 __field(long, start)
-__field(long, last)
+__field(long, end)
 __field(u64, offset)
 __field(u64, flags)
 ),
@@ -279,12 +279,12 @@ TRACE_EVENT(amdgpu_vm_bo_unmap,
TP_fast_assign(
   __entry->bo = bo_va ? bo_va->base.bo : NULL;
   __entry->start = mapping->start;
-  __entry->last = mapping->last;
+  __entry->end = mapping->end;
   __entry->offset = mapping->offset;
   __entry->flags = mapping->flags;
   ),
-   TP_printk("bo=%p, start=%lx, last=%lx, offset=%010llx, flags=%llx",
- __entry->bo, __entry->start, __entry->last,
+   TP_printk("bo=%p, start=%lx, end=%lx, offset=%010llx, flags=%llx",
+ __entry->bo, __entry->start, __entry->end,
  __entry->offset, __entry->flags)
 );
 
@@ -299,7 +299,7 @@

[PATCH] drm/amdgpu: user pages array memory leak fix

2019-10-03 Thread Yang, Philip 
user_pages array should always be freed after validation regardless if
user pages are changed after bo is created because with HMM change parse
bo always allocate user pages array to get user pages for userptr bo.

Don't need to get user pages while creating uerptr bo because user pages
will only be used while validating after parsing userptr bo.

Bugzilla: https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1844962

v2: remove unused local variable and amend commit

Signed-off-by: Philip Yang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c  |  4 +---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 23 +--
 2 files changed, 2 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 49b767b7238f..961186e7113e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -474,7 +474,6 @@ static int amdgpu_cs_list_validate(struct amdgpu_cs_parser 
*p,
 
list_for_each_entry(lobj, validated, tv.head) {
struct amdgpu_bo *bo = ttm_to_amdgpu_bo(lobj->tv.bo);
-   bool binding_userptr = false;
struct mm_struct *usermm;
 
usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm);
@@ -491,14 +490,13 @@ static int amdgpu_cs_list_validate(struct 
amdgpu_cs_parser *p,
 
amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm,
 lobj->user_pages);
-   binding_userptr = true;
}
 
r = amdgpu_cs_validate(p, bo);
if (r)
return r;
 
-   if (binding_userptr) {
+   if (lobj->user_pages) {
kvfree(lobj->user_pages);
lobj->user_pages = NULL;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index a828e3d0bfbd..3ccd61d69964 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -283,7 +283,6 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void 
*data,
 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
 struct drm_file *filp)
 {
-   struct ttm_operation_ctx ctx = { true, false };
struct amdgpu_device *adev = dev->dev_private;
struct drm_amdgpu_gem_userptr *args = data;
struct drm_gem_object *gobj;
@@ -326,32 +325,12 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void 
*data,
goto release_object;
}
 
-   if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) {
-   r = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages);
-   if (r)
-   goto release_object;
-
-   r = amdgpu_bo_reserve(bo, true);
-   if (r)
-   goto user_pages_done;
-
-   amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
-   r = ttm_bo_validate(>tbo, >placement, );
-   amdgpu_bo_unreserve(bo);
-   if (r)
-   goto user_pages_done;
-   }
-
r = drm_gem_handle_create(filp, gobj, );
if (r)
-   goto user_pages_done;
+   goto release_object;
 
args->handle = handle;
 
-user_pages_done:
-   if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE)
-   amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm);
-
 release_object:
drm_gem_object_put_unlocked(gobj);
 
-- 
2.17.1

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[PATCH] drm/amdgpu: user pages array memory leak fix

2019-10-03 Thread Yang, Philip 
user_pages array should be freed regardless if user pages are
invalidated after bo is created because HMM change to always allocate
user pages array to get user pages while parsing user page bo.

Don't need to to get user pages while creating bo because user pages
will only be used after parsing user page bo.

Bugzilla: https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1844962

Signed-off-by: Philip Yang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c  |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 23 +--
 2 files changed, 2 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 49b767b7238f..e861de259def 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -498,7 +498,7 @@ static int amdgpu_cs_list_validate(struct amdgpu_cs_parser 
*p,
if (r)
return r;
 
-   if (binding_userptr) {
+   if (lobj->user_pages) {
kvfree(lobj->user_pages);
lobj->user_pages = NULL;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index a828e3d0bfbd..3ccd61d69964 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -283,7 +283,6 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void 
*data,
 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
 struct drm_file *filp)
 {
-   struct ttm_operation_ctx ctx = { true, false };
struct amdgpu_device *adev = dev->dev_private;
struct drm_amdgpu_gem_userptr *args = data;
struct drm_gem_object *gobj;
@@ -326,32 +325,12 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void 
*data,
goto release_object;
}
 
-   if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) {
-   r = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages);
-   if (r)
-   goto release_object;
-
-   r = amdgpu_bo_reserve(bo, true);
-   if (r)
-   goto user_pages_done;
-
-   amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
-   r = ttm_bo_validate(>tbo, >placement, );
-   amdgpu_bo_unreserve(bo);
-   if (r)
-   goto user_pages_done;
-   }
-
r = drm_gem_handle_create(filp, gobj, );
if (r)
-   goto user_pages_done;
+   goto release_object;
 
args->handle = handle;
 
-user_pages_done:
-   if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE)
-   amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm);
-
 release_object:
drm_gem_object_put_unlocked(gobj);
 
-- 
2.17.1

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Re: [Follow-up] Status of AMD Sensor Fusion HUB for Linux

2019-10-03 Thread Alex Deucher 
On Wed, Oct 2, 2019 at 3:35 AM Luya Tshimbalanga  wrote:
>
>
> On 2019-09-26 10:03 a.m., Alex Deucher wrote:
> > On Thu, Sep 26, 2019 at 3:59 AM Luya Tshimbalanga
> >  wrote:
> >> Hello,
> >>
> >> What is the current status of the driver or module for AMD Sensor Fusion
> >> HUB for mobile Raven Ridge family? To this day, majority of mobile
> >> powered device equipped with that APU family lacks gyroscopic function
> >> for the screen.
> >>
> > The FCH team has an initial implementation done.  IIRC, they are just
> > cleaning things up and restructuring based on community
> > recommendations.  I think the patches should be available soon if they
> > are not already.
> >
> > Alex
> >
> Which repository could we view the patch once it lands?

HID subsystem I think.

Alex

>
> --
> Luya Tshimbalanga
> Fedora Design Team
> Fedora Design Suite maintainer
>
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Re: [PATCH] drm/amdgpu: improve MSI-X handling (v3)

2019-10-03 Thread Liu, Shaoyun 
Looks good to me .

Reviewed-by: Shaoyun liu  


On 2019-10-03 1:33 p.m., Tom St Denis wrote:

Tested-by: Tom St Denis 

Cheers,
Tom

On Thu, Oct 3, 2019 at 1:30 PM Alex Deucher 
 wrote:



Check the number of supported vectors and fall back to MSI if
we return or error or 0 MSI-X vectors.

v2: only allocate one vector.  We can't currently use more than
one anyway.

v3: install the irq on vector 0.

Signed-off-by: Alex Deucher 

---
 drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 17 +
 1 file changed, 13 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
index 50771b2757dc..6f3b03f6224f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
@@ -245,11 +245,19 @@ int amdgpu_irq_init(struct amdgpu_device *adev)
adev->irq.msi_enabled = false;

if (amdgpu_msi_ok(adev)) {
-   int nvec = pci_alloc_irq_vectors(adev->pdev, 1,
pci_msix_vec_count(adev->pdev),
-   PCI_IRQ_MSI | PCI_IRQ_MSIX);
+   int nvec = pci_msix_vec_count(adev->pdev);
+   unsigned int flags;
+
+   if (nvec <= 0) {
+   flags = PCI_IRQ_MSI;
+   } else {
+   flags = PCI_IRQ_MSI | PCI_IRQ_MSIX;
+   }
+   /* we only need one vector */
+   nvec = pci_alloc_irq_vectors(adev->pdev, 1, 1, flags);
if (nvec > 0) {
adev->irq.msi_enabled = true;
-   dev_dbg(adev->dev, "amdgpu: using MSI.\n");
+   dev_dbg(adev->dev, "amdgpu: using MSI/MSI-X.\n");
}
}

@@ -272,7 +280,8 @@ int amdgpu_irq_init(struct amdgpu_device *adev)
INIT_WORK(>irq.ih2_work, amdgpu_irq_handle_ih2);

adev->irq.installed = true;
-   r = drm_irq_install(adev->ddev, adev->ddev->pdev->irq);
+   /* Use vector 0 for MSI-X */
+   r = drm_irq_install(adev->ddev, pci_irq_vector(adev->pdev, 0));
if (r) {
adev->irq.installed = false;
if (!amdgpu_device_has_dc_support(adev))
--
2.20.1

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Re: [PATCH] drm/amdgpu: improve MSI-X handling (v3)

2019-10-03 Thread Tom St Denis 
Tested-by: Tom St Denis 

Cheers,
Tom

On Thu, Oct 3, 2019 at 1:30 PM Alex Deucher  wrote:

> Check the number of supported vectors and fall back to MSI if
> we return or error or 0 MSI-X vectors.
>
> v2: only allocate one vector.  We can't currently use more than
> one anyway.
>
> v3: install the irq on vector 0.
>
> Signed-off-by: Alex Deucher 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 17 +
>  1 file changed, 13 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> index 50771b2757dc..6f3b03f6224f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> @@ -245,11 +245,19 @@ int amdgpu_irq_init(struct amdgpu_device *adev)
> adev->irq.msi_enabled = false;
>
> if (amdgpu_msi_ok(adev)) {
> -   int nvec = pci_alloc_irq_vectors(adev->pdev, 1,
> pci_msix_vec_count(adev->pdev),
> -   PCI_IRQ_MSI | PCI_IRQ_MSIX);
> +   int nvec = pci_msix_vec_count(adev->pdev);
> +   unsigned int flags;
> +
> +   if (nvec <= 0) {
> +   flags = PCI_IRQ_MSI;
> +   } else {
> +   flags = PCI_IRQ_MSI | PCI_IRQ_MSIX;
> +   }
> +   /* we only need one vector */
> +   nvec = pci_alloc_irq_vectors(adev->pdev, 1, 1, flags);
> if (nvec > 0) {
> adev->irq.msi_enabled = true;
> -   dev_dbg(adev->dev, "amdgpu: using MSI.\n");
> +   dev_dbg(adev->dev, "amdgpu: using MSI/MSI-X.\n");
> }
> }
>
> @@ -272,7 +280,8 @@ int amdgpu_irq_init(struct amdgpu_device *adev)
> INIT_WORK(>irq.ih2_work, amdgpu_irq_handle_ih2);
>
> adev->irq.installed = true;
> -   r = drm_irq_install(adev->ddev, adev->ddev->pdev->irq);
> +   /* Use vector 0 for MSI-X */
> +   r = drm_irq_install(adev->ddev, pci_irq_vector(adev->pdev, 0));
> if (r) {
> adev->irq.installed = false;
> if (!amdgpu_device_has_dc_support(adev))
> --
> 2.20.1
>
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[PATCH] drm/amdgpu: improve MSI-X handling (v3)

2019-10-03 Thread Alex Deucher 
Check the number of supported vectors and fall back to MSI if
we return or error or 0 MSI-X vectors.

v2: only allocate one vector.  We can't currently use more than
one anyway.

v3: install the irq on vector 0.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 17 +
 1 file changed, 13 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
index 50771b2757dc..6f3b03f6224f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
@@ -245,11 +245,19 @@ int amdgpu_irq_init(struct amdgpu_device *adev)
adev->irq.msi_enabled = false;
 
if (amdgpu_msi_ok(adev)) {
-   int nvec = pci_alloc_irq_vectors(adev->pdev, 1, 
pci_msix_vec_count(adev->pdev),
-   PCI_IRQ_MSI | PCI_IRQ_MSIX);
+   int nvec = pci_msix_vec_count(adev->pdev);
+   unsigned int flags;
+
+   if (nvec <= 0) {
+   flags = PCI_IRQ_MSI;
+   } else {
+   flags = PCI_IRQ_MSI | PCI_IRQ_MSIX;
+   }
+   /* we only need one vector */
+   nvec = pci_alloc_irq_vectors(adev->pdev, 1, 1, flags);
if (nvec > 0) {
adev->irq.msi_enabled = true;
-   dev_dbg(adev->dev, "amdgpu: using MSI.\n");
+   dev_dbg(adev->dev, "amdgpu: using MSI/MSI-X.\n");
}
}
 
@@ -272,7 +280,8 @@ int amdgpu_irq_init(struct amdgpu_device *adev)
INIT_WORK(>irq.ih2_work, amdgpu_irq_handle_ih2);
 
adev->irq.installed = true;
-   r = drm_irq_install(adev->ddev, adev->ddev->pdev->irq);
+   /* Use vector 0 for MSI-X */
+   r = drm_irq_install(adev->ddev, pci_irq_vector(adev->pdev, 0));
if (r) {
adev->irq.installed = false;
if (!amdgpu_device_has_dc_support(adev))
-- 
2.20.1

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Re: [PATCH][drm-next] drm/amd/display: fix spelling mistake AUTHENICATED -> AUTHENTICATED

2019-10-03 Thread Alex Deucher 
On Thu, Oct 3, 2019 at 9:27 AM Harry Wentland  wrote:
>
> On 2019-10-03 4:22 a.m., Colin King wrote:
> > From: Colin Ian King 
> >
> > There is a spelling mistake in the macros H1_A45_AUTHENICATED and
> > D1_A4_AUTHENICATED, fix these by adding the missing T.
> >
> > Signed-off-by: Colin Ian King 
>
> Reviewed-by: Harry Wentland 
>

Applied.  thanks!

Alex

> Harry
>
> > ---
> >  drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h  |  4 ++--
> >  .../drm/amd/display/modules/hdcp/hdcp1_execution.c   |  4 ++--
> >  .../drm/amd/display/modules/hdcp/hdcp1_transition.c  | 12 ++--
> >  drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c  |  8 
> >  4 files changed, 14 insertions(+), 14 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h 
> > b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
> > index 402bb7999093..5664bc0b5bd0 100644
> > --- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
> > +++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
> > @@ -176,7 +176,7 @@ enum mod_hdcp_hdcp1_state_id {
> >   H1_A0_WAIT_FOR_ACTIVE_RX,
> >   H1_A1_EXCHANGE_KSVS,
> >   H1_A2_COMPUTATIONS_A3_VALIDATE_RX_A6_TEST_FOR_REPEATER,
> > - H1_A45_AUTHENICATED,
> > + H1_A45_AUTHENTICATED,
> >   H1_A8_WAIT_FOR_READY,
> >   H1_A9_READ_KSV_LIST,
> >   HDCP1_STATE_END = H1_A9_READ_KSV_LIST
> > @@ -188,7 +188,7 @@ enum mod_hdcp_hdcp1_dp_state_id {
> >   D1_A1_EXCHANGE_KSVS,
> >   D1_A23_WAIT_FOR_R0_PRIME,
> >   D1_A2_COMPUTATIONS_A3_VALIDATE_RX_A5_TEST_FOR_REPEATER,
> > - D1_A4_AUTHENICATED,
> > + D1_A4_AUTHENTICATED,
> >   D1_A6_WAIT_FOR_READY,
> >   D1_A7_READ_KSV_LIST,
> >   HDCP1_DP_STATE_END = D1_A7_READ_KSV_LIST,
> > diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c 
> > b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c
> > index 9e7302eac299..3db4a7da414f 100644
> > --- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c
> > +++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c
> > @@ -476,7 +476,7 @@ enum mod_hdcp_status mod_hdcp_hdcp1_execution(struct 
> > mod_hdcp *hdcp,
> >   status = computations_validate_rx_test_for_repeater(hdcp,
> >   event_ctx, input);
> >   break;
> > - case H1_A45_AUTHENICATED:
> > + case H1_A45_AUTHENTICATED:
> >   status = authenticated(hdcp, event_ctx, input);
> >   break;
> >   case H1_A8_WAIT_FOR_READY:
> > @@ -513,7 +513,7 @@ extern enum mod_hdcp_status 
> > mod_hdcp_hdcp1_dp_execution(struct mod_hdcp *hdcp,
> >   status = computations_validate_rx_test_for_repeater(
> >   hdcp, event_ctx, input);
> >   break;
> > - case D1_A4_AUTHENICATED:
> > + case D1_A4_AUTHENTICATED:
> >   status = authenticated_dp(hdcp, event_ctx, input);
> >   break;
> >   case D1_A6_WAIT_FOR_READY:
> > diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_transition.c 
> > b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_transition.c
> > index 1d187809b709..136b8011ff3f 100644
> > --- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_transition.c
> > +++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_transition.c
> > @@ -81,11 +81,11 @@ enum mod_hdcp_status mod_hdcp_hdcp1_transition(struct 
> > mod_hdcp *hdcp,
> >   set_state_id(hdcp, output, H1_A8_WAIT_FOR_READY);
> >   } else {
> >   callback_in_ms(0, output);
> > - set_state_id(hdcp, output, H1_A45_AUTHENICATED);
> > + set_state_id(hdcp, output, H1_A45_AUTHENTICATED);
> >   HDCP_FULL_DDC_TRACE(hdcp);
> >   }
> >   break;
> > - case H1_A45_AUTHENICATED:
> > + case H1_A45_AUTHENTICATED:
> >   if (input->link_maintenance != PASS) {
> >   /* 1A-07: consider invalid ri' a failure */
> >   /* 1A-07a: consider read ri' not returned a failure */
> > @@ -129,7 +129,7 @@ enum mod_hdcp_status mod_hdcp_hdcp1_transition(struct 
> > mod_hdcp *hdcp,
> >   break;
> >   }
> >   callback_in_ms(0, output);
> > - set_state_id(hdcp, output, H1_A45_AUTHENICATED);
> > + set_state_id(hdcp, output, H1_A45_AUTHENTICATED);
> >   HDCP_FULL_DDC_TRACE(hdcp);
> >   break;
> >   default:
> > @@ -224,11 +224,11 @@ enum mod_hdcp_status 
> > mod_hdcp_hdcp1_dp_transition(struct mod_hdcp *hdcp,
> >   set_watchdog_in_ms(hdcp, 5000, output);
> >   set_state_id(hdcp, output, D1_A6_WAIT_FOR_READY);
> >   } else {
> > - set_state_id(hdcp, output, D1_A4_AUTHENICATED);
> > + set_state_id(hdcp, output, D1_A4_AUTHENTICATED);
> >   HDCP_FULL_DDC_TRACE(hdcp);
> >

RE: [PATCH 1/2] drm/amdgpu: improve MSI-X handling

2019-10-03 Thread Huang, Ray 
Series are Reviewed-by: Huang Rui 

-Original Message-
From: amd-gfx  On Behalf Of Alex Deucher
Sent: Thursday, October 3, 2019 10:13 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander 
Subject: [PATCH 1/2] drm/amdgpu: improve MSI-X handling

Check the number of supported vectors and fall back to MSI if we return or 
error or 0 MSI-X vectors.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 14 +++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
index 50771b2757dc..98aa28edba6a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
@@ -245,11 +245,19 @@ int amdgpu_irq_init(struct amdgpu_device *adev)
adev->irq.msi_enabled = false;
 
if (amdgpu_msi_ok(adev)) {
-   int nvec = pci_alloc_irq_vectors(adev->pdev, 1, 
pci_msix_vec_count(adev->pdev),
-   PCI_IRQ_MSI | PCI_IRQ_MSIX);
+   unsigned int flags;
+   int nvec = pci_msix_vec_count(adev->pdev);
+
+   if (nvec <= 0) {
+   flags = PCI_IRQ_MSI;
+   nvec = 1;
+   } else {
+   flags = PCI_IRQ_MSI | PCI_IRQ_MSIX;
+   }
+   nvec = pci_alloc_irq_vectors(adev->pdev, 1, nvec, flags);
if (nvec > 0) {
adev->irq.msi_enabled = true;
-   dev_dbg(adev->dev, "amdgpu: using MSI.\n");
+   dev_dbg(adev->dev, "amdgpu: using MSI/MSI-X.\n");
}
}
 
--
2.20.1

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[PATCH 10/11] drm/amd/display: Refactor HDCP encryption status update

2019-10-03 Thread Bhawanpreet Lakha 
[Why]
The old way was to poll PSP and update the properties. But due to a
limitation in the PSP interface this doesn't work for MST.

[How]
According to PSP if set_encryption return success, the link is encrypted
and the only way it will not be is if we get a link loss(which we handle
already).

So this method should be good enough to report HDCP status.

Signed-off-by: Bhawanpreet Lakha 
---
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c |  3 +--
 .../gpu/drm/amd/display/modules/hdcp/hdcp.c| 18 ++
 .../gpu/drm/amd/display/modules/inc/mod_hdcp.h |  4 ++--
 3 files changed, 17 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
index 6c4b3134e786..603909416398 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
@@ -81,6 +81,7 @@ static void process_output(struct hdcp_workqueue *hdcp_work)
schedule_delayed_work(_work->watchdog_timer_dwork,
  
msecs_to_jiffies(output.watchdog_timer_delay));
 
+   schedule_delayed_work(_work->property_validate_dwork, 
msecs_to_jiffies(0));
 }
 
 void hdcp_update_display(struct hdcp_workqueue *hdcp_work,
@@ -233,8 +234,6 @@ static void event_property_validate(struct work_struct 
*work)
schedule_work(_work->property_update_work);
}
 
-   schedule_delayed_work(_work->property_validate_dwork, 
msecs_to_jiffies(DRM_HDCP_CHECK_PERIOD_MS));
-
mutex_unlock(_work->mutex);
 }
 
diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c 
b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
index 0f2f242710b3..cbb5e9c063ec 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
@@ -417,10 +417,20 @@ enum mod_hdcp_status mod_hdcp_query_display(struct 
mod_hdcp *hdcp,
query->trace = >connection.trace;
query->encryption_status = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF;
 
-   if (is_hdcp1(hdcp))
-   mod_hdcp_hdcp1_get_link_encryption_status(hdcp, 
>encryption_status);
-   else if (is_hdcp2(hdcp))
-   mod_hdcp_hdcp2_get_link_encryption_status(hdcp, 
>encryption_status);
+   if (is_display_encryption_enabled(display)) {
+   if (is_hdcp1(hdcp)) {
+   query->encryption_status = 
MOD_HDCP_ENCRYPTION_STATUS_HDCP1_ON;
+   } else if (is_hdcp2(hdcp)) {
+   if (query->link->adjust.hdcp2.force_type == 
MOD_HDCP_FORCE_TYPE_0)
+   query->encryption_status = 
MOD_HDCP_ENCRYPTION_STATUS_HDCP2_TYPE0_ON;
+   else if (query->link->adjust.hdcp2.force_type == 
MOD_HDCP_FORCE_TYPE_1)
+   query->encryption_status = 
MOD_HDCP_ENCRYPTION_STATUS_HDCP2_TYPE1_ON;
+   else
+   query->encryption_status = 
MOD_HDCP_ENCRYPTION_STATUS_HDCP2_ON;
+   }
+   } else {
+   query->encryption_status = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF;
+   }
 
 out:
return status;
diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h 
b/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h
index ff2bb2bfbb53..f2a0e1a064da 100644
--- a/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h
+++ b/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h
@@ -191,9 +191,9 @@ struct mod_hdcp_trace {
 enum mod_hdcp_encryption_status {
MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF = 0,
MOD_HDCP_ENCRYPTION_STATUS_HDCP1_ON,
-   MOD_HDCP_ENCRYPTION_STATUS_HDCP2_ON,
MOD_HDCP_ENCRYPTION_STATUS_HDCP2_TYPE0_ON,
-   MOD_HDCP_ENCRYPTION_STATUS_HDCP2_TYPE1_ON
+   MOD_HDCP_ENCRYPTION_STATUS_HDCP2_TYPE1_ON,
+   MOD_HDCP_ENCRYPTION_STATUS_HDCP2_ON
 };
 
 /* per link events dm has to notify to hdcp module */
-- 
2.17.1

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[PATCH 11/11] drm/amd/display: fix events handling for hdcp

2019-10-03 Thread Bhawanpreet Lakha 
[Why]
When we execute a event, pending events should be canceled. This leads
to cases where we execute the same event twice,if the new event is
scheduled to run before the old event.

Also watchdog event was being canceled inside callback event. This is
incorrect.

[How]
Cancel pending events before executing the current and fix watchdog
event being canceled by callback event

Change-Id: I3c595901d63f3393c83d898cdb2d7dfc1a769142
Signed-off-by: Bhawanpreet Lakha 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
index 603909416398..715f650715b3 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
@@ -169,7 +169,7 @@ static void event_callback(struct work_struct *work)
 
mutex_lock(_work->mutex);
 
-   cancel_delayed_work(_work->watchdog_timer_dwork);
+   cancel_delayed_work(_work->callback_dwork);
 
mod_hdcp_process_event(_work->hdcp, MOD_HDCP_EVENT_CALLBACK,
   _work->output);
@@ -247,6 +247,8 @@ static void event_watchdog_timer(struct work_struct *work)
 
mutex_lock(_work->mutex);
 
+   cancel_delayed_work(_work->watchdog_timer_dwork);
+
mod_hdcp_process_event(_work->hdcp,
   MOD_HDCP_EVENT_WATCHDOG_TIMEOUT,
   _work->output);
-- 
2.17.1

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[PATCH 04/11] drm/amd/display: Add logging for HDCP2.2

2019-10-03 Thread Bhawanpreet Lakha 
[Why]
We need to log the state changes for 2.2
This patch extends the existing logging functions to handle
HDCP2.2.

[How]
We do this by adding if/else in the defines, and output the log
 based on the hdcp version

Signed-off-by: Bhawanpreet Lakha 
---
 .../drm/amd/display/modules/hdcp/hdcp_log.c   | 118 ++
 .../drm/amd/display/modules/hdcp/hdcp_log.h   |  94 +++---
 .../drm/amd/display/modules/hdcp/hdcp_psp.c   |   4 +
 3 files changed, 196 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c 
b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c
index d868f556d180..a1d640e485da 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c
@@ -116,6 +116,58 @@ char *mod_hdcp_status_to_str(int32_t status)
return "MOD_HDCP_STATUS_DDC_FAILURE";
case MOD_HDCP_STATUS_INVALID_OPERATION:
return "MOD_HDCP_STATUS_INVALID_OPERATION";
+   case MOD_HDCP_STATUS_HDCP2_NOT_CAPABLE:
+   return "MOD_HDCP_STATUS_HDCP2_NOT_CAPABLE";
+   case MOD_HDCP_STATUS_HDCP2_CREATE_SESSION_FAILURE:
+   return "MOD_HDCP_STATUS_HDCP2_CREATE_SESSION_FAILURE";
+   case MOD_HDCP_STATUS_HDCP2_DESTROY_SESSION_FAILURE:
+   return "MOD_HDCP_STATUS_HDCP2_DESTROY_SESSION_FAILURE";
+   case MOD_HDCP_STATUS_HDCP2_PREP_AKE_INIT_FAILURE:
+   return "MOD_HDCP_STATUS_HDCP2_PREP_AKE_INIT_FAILURE";
+   case MOD_HDCP_STATUS_HDCP2_AKE_CERT_PENDING:
+   return "MOD_HDCP_STATUS_HDCP2_AKE_CERT_PENDING";
+   case MOD_HDCP_STATUS_HDCP2_H_PRIME_PENDING:
+   return "MOD_HDCP_STATUS_HDCP2_H_PRIME_PENDING";
+   case MOD_HDCP_STATUS_HDCP2_PAIRING_INFO_PENDING:
+   return "MOD_HDCP_STATUS_HDCP2_PAIRING_INFO_PENDING";
+   case MOD_HDCP_STATUS_HDCP2_VALIDATE_AKE_CERT_FAILURE:
+   return "MOD_HDCP_STATUS_HDCP2_VALIDATE_AKE_CERT_FAILURE";
+   case MOD_HDCP_STATUS_HDCP2_AKE_CERT_REVOKED:
+   return "MOD_HDCP_STATUS_HDCP2_AKE_CERT_REVOKED";
+   case MOD_HDCP_STATUS_HDCP2_VALIDATE_H_PRIME_FAILURE:
+   return "MOD_HDCP_STATUS_HDCP2_VALIDATE_H_PRIME_FAILURE";
+   case MOD_HDCP_STATUS_HDCP2_VALIDATE_PAIRING_INFO_FAILURE:
+   return "MOD_HDCP_STATUS_HDCP2_VALIDATE_PAIRING_INFO_FAILURE";
+   case MOD_HDCP_STATUS_HDCP2_PREP_LC_INIT_FAILURE:
+   return "MOD_HDCP_STATUS_HDCP2_PREP_LC_INIT_FAILURE";
+   case MOD_HDCP_STATUS_HDCP2_L_PRIME_PENDING:
+   return "MOD_HDCP_STATUS_HDCP2_L_PRIME_PENDING";
+   case MOD_HDCP_STATUS_HDCP2_VALIDATE_L_PRIME_FAILURE:
+   return "MOD_HDCP_STATUS_HDCP2_VALIDATE_L_PRIME_FAILURE";
+   case MOD_HDCP_STATUS_HDCP2_PREP_EKS_FAILURE:
+   return "MOD_HDCP_STATUS_HDCP2_PREP_EKS_FAILURE";
+   case MOD_HDCP_STATUS_HDCP2_ENABLE_ENCRYPTION_FAILURE:
+   return "MOD_HDCP_STATUS_HDCP2_ENABLE_ENCRYPTION_FAILURE";
+   case MOD_HDCP_STATUS_HDCP2_VALIDATE_RX_ID_LIST_FAILURE:
+   return "MOD_HDCP_STATUS_HDCP2_VALIDATE_RX_ID_LIST_FAILURE";
+   case MOD_HDCP_STATUS_HDCP2_RX_ID_LIST_REVOKED:
+   return "MOD_HDCP_STATUS_HDCP2_RX_ID_LIST_REVOKED";
+   case MOD_HDCP_STATUS_HDCP2_RX_ID_LIST_NOT_READY:
+   return "MOD_HDCP_STATUS_HDCP2_RX_ID_LIST_NOT_READY";
+   case MOD_HDCP_STATUS_HDCP2_ENABLE_STREAM_ENCRYPTION:
+   return "MOD_HDCP_STATUS_HDCP2_ENABLE_STREAM_ENCRYPTION";
+   case MOD_HDCP_STATUS_HDCP2_STREAM_READY_PENDING:
+   return "MOD_HDCP_STATUS_HDCP2_STREAM_READY_PENDING";
+   case MOD_HDCP_STATUS_HDCP2_VALIDATE_STREAM_READY_FAILURE:
+   return "MOD_HDCP_STATUS_HDCP2_VALIDATE_STREAM_READY_FAILURE";
+   case MOD_HDCP_STATUS_HDCP2_PREPARE_STREAM_MANAGEMENT_FAILURE:
+   return 
"MOD_HDCP_STATUS_HDCP2_PREPARE_STREAM_MANAGEMENT_FAILURE";
+   case MOD_HDCP_STATUS_HDCP2_REAUTH_REQUEST:
+   return "MOD_HDCP_STATUS_HDCP2_REAUTH_REQUEST";
+   case MOD_HDCP_STATUS_HDCP2_REAUTH_LINK_INTEGRITY_FAILURE:
+   return "MOD_HDCP_STATUS_HDCP2_REAUTH_LINK_INTEGRITY_FAILURE";
+   case MOD_HDCP_STATUS_HDCP2_DEVICE_COUNT_MISMATCH_FAILURE:
+   return "MOD_HDCP_STATUS_HDCP2_DEVICE_COUNT_MISMATCH_FAILURE";
default:
return "MOD_HDCP_STATUS_UNKNOWN";
}
@@ -156,6 +208,72 @@ char *mod_hdcp_state_id_to_str(int32_t id)
return "D1_A6_WAIT_FOR_READY";
case D1_A7_READ_KSV_LIST:
return "D1_A7_READ_KSV_LIST";
+   case H2_A0_KNOWN_HDCP2_CAPABLE_RX:
+   return "H2_A0_KNOWN_HDCP2_CAPABLE_RX";
+   case H2_A1_SEND_AKE_INIT:
+   return "H2_A1_SEND_AKE_INIT";
+   case H2_A1_VALIDATE_AKE_CERT:
+   return "H2_A1_VALIDATE_AKE_CERT";
+   case H2_A1_SEND_NO_STORED_KM:
+   return "H2_A1_SEND_NO_STORED_KM";
+

[PATCH 07/11] drm/amd/display: Handle hdcp2.2 type0/1 in dm

2019-10-03 Thread Bhawanpreet Lakha 
[Why]
HDCP 2.2 uses type0 and type1 content type. This is passed to the receiver
to stream the proper content.

For example, in a MST case if the main
device is HDCP2.2 capable but the secondary device is only 1.4 capabale
we can use Type0

Type0 content: use HDCP 1.4 or HDCP2.2 type0
Type1 content: Only use HDCP 2.2 type1

[How]
We use the "hdcp content type" property in drm. We use the
disable_type1 flag in hdcp module to select the type based on the
properties.

For updating the property we use the same logic as 1.4, but now we
consider content_type as well and update the property if the
requirements are met

Signed-off-by: Bhawanpreet Lakha 
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c  | 18 ++
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c | 17 +
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h |  4 ++--
 .../gpu/drm/amd/display/modules/hdcp/hdcp.c|  5 -
 4 files changed, 33 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 7b0ca2e1ed8b..e9a9edac6ea7 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -39,6 +39,7 @@
 #include "amdgpu_dm.h"
 #ifdef CONFIG_DRM_AMD_DC_HDCP
 #include "amdgpu_dm_hdcp.h"
+#include 
 #endif
 #include "amdgpu_pm.h"
 
@@ -5118,7 +5119,7 @@ void amdgpu_dm_connector_init_helper(struct 
amdgpu_display_manager *dm,
adev->mode_info.freesync_capable_property, 0);
 #ifdef CONFIG_DRM_AMD_DC_HDCP
if (adev->asic_type >= CHIP_RAVEN)
-   
drm_connector_attach_content_protection_property(>base, false);
+   
drm_connector_attach_content_protection_property(>base, true);
 #endif
}
 }
@@ -5369,6 +5370,12 @@ static bool is_content_protection_different(struct 
drm_connector_state *state,
 {
struct amdgpu_dm_connector *aconnector = 
to_amdgpu_dm_connector(connector);
 
+   if (old_state->hdcp_content_type != state->hdcp_content_type &&
+   state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) 
{
+   state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
+   return true;
+   }
+
/* CP is being re enabled, ignore this */
if (old_state->content_protection == 
DRM_MODE_CONTENT_PROTECTION_ENABLED &&
state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
@@ -5401,11 +5408,14 @@ static void update_content_protection(struct 
drm_connector_state *state, const s
  struct hdcp_workqueue *hdcp_w)
 {
struct amdgpu_dm_connector *aconnector = 
to_amdgpu_dm_connector(connector);
+   bool disable_type1 = state->hdcp_content_type == 
DRM_MODE_HDCP_CONTENT_TYPE0 ? true : false;
 
-   if (state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED)
-   hdcp_add_display(hdcp_w, aconnector->dc_link->link_index, 
aconnector);
-   else if (state->content_protection == 
DRM_MODE_CONTENT_PROTECTION_UNDESIRED)
+   if (state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
+   hdcp_reset_display(hdcp_w, aconnector->dc_link->link_index);
+   hdcp_add_display(hdcp_w, aconnector->dc_link->link_index, 
aconnector, disable_type1);
+   } else if (state->content_protection == 
DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
hdcp_remove_display(hdcp_w, aconnector->dc_link->link_index, 
aconnector->base.index);
+   }
 
 }
 #endif
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
index fc775c0795d8..75f7045f04dd 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
@@ -83,7 +83,8 @@ static void process_output(struct hdcp_workqueue *hdcp_work)
 
 }
 
-void hdcp_add_display(struct hdcp_workqueue *hdcp_work, unsigned int 
link_index, struct amdgpu_dm_connector *aconnector)
+void hdcp_add_display(struct hdcp_workqueue *hdcp_work, unsigned int 
link_index, struct amdgpu_dm_connector *aconnector,
+ bool disable_type1)
 {
struct hdcp_workqueue *hdcp_w = _work[link_index];
struct mod_hdcp_display *display = _work[link_index].display;
@@ -92,6 +93,8 @@ void hdcp_add_display(struct hdcp_workqueue *hdcp_work, 
unsigned int link_index,
mutex_lock(_w->mutex);
hdcp_w->aconnector = aconnector;
 
+   hdcp_w->link.adjust.hdcp2.disable_type1 = disable_type1;
+
mod_hdcp_add_display(_w->hdcp, link, display, _w->output);
 
schedule_delayed_work(_w->property_validate_dwork, 
msecs_to_jiffies(DRM_HDCP_CHECK_PERIOD_MS));
@@ -186,10 +189,16 @@ static void event_property_update(struct work_struct 
*work)
}
}
 
-   if (hdcp_work->encryption_status !=

[PATCH 08/11] drm/amd/display: Refactor HDCP to handle multiple displays per link

2019-10-03 Thread Bhawanpreet Lakha 
[Why]
We need to do this to support HDCP over MST

Currently we save a display per link, in a MST case we need to save
multiple displays per link.

[How]
We can create an array per link to cache the displays, but it
complicates the design. Instead we can use the module to cache the
displays.

Now we will always add all the displays to the module, but we use the
adjustment flag to disable hdcp on all of them before they are added.

When we want to enable hdcp we just query the display(cache), remove
it then add it back with different adjustments. Its the similar for
disable.

Signed-off-by: Bhawanpreet Lakha 
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 20 ++-
 .../amd/display/amdgpu_dm/amdgpu_dm_hdcp.c| 53 ++-
 .../amd/display/amdgpu_dm/amdgpu_dm_hdcp.h|  9 ++--
 3 files changed, 40 insertions(+), 42 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index e9a9edac6ea7..0bb212e47766 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -5404,20 +5404,6 @@ static bool is_content_protection_different(struct 
drm_connector_state *state,
return false;
 }
 
-static void update_content_protection(struct drm_connector_state *state, const 
struct drm_connector *connector,
- struct hdcp_workqueue *hdcp_w)
-{
-   struct amdgpu_dm_connector *aconnector = 
to_amdgpu_dm_connector(connector);
-   bool disable_type1 = state->hdcp_content_type == 
DRM_MODE_HDCP_CONTENT_TYPE0 ? true : false;
-
-   if (state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
-   hdcp_reset_display(hdcp_w, aconnector->dc_link->link_index);
-   hdcp_add_display(hdcp_w, aconnector->dc_link->link_index, 
aconnector, disable_type1);
-   } else if (state->content_protection == 
DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
-   hdcp_remove_display(hdcp_w, aconnector->dc_link->link_index, 
aconnector->base.index);
-   }
-
-}
 #endif
 static void remove_stream(struct amdgpu_device *adev,
  struct amdgpu_crtc *acrtc,
@@ -6364,7 +6350,11 @@ static void amdgpu_dm_atomic_commit_tail(struct 
drm_atomic_state *state)
}
 
if (is_content_protection_different(new_con_state, 
old_con_state, connector, adev->dm.hdcp_workqueue))
-   update_content_protection(new_con_state, connector, 
adev->dm.hdcp_workqueue);
+   hdcp_update_display(
+   adev->dm.hdcp_workqueue, 
aconnector->dc_link->link_index, aconnector,
+   new_con_state->hdcp_content_type == 
DRM_MODE_HDCP_CONTENT_TYPE0 ? true : false,
+   new_con_state->content_protection == 
DRM_MODE_CONTENT_PROTECTION_DESIRED ? true
+   
 : false);
}
 #endif
 
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
index 75f7045f04dd..ca12362e799a 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
@@ -83,43 +83,45 @@ static void process_output(struct hdcp_workqueue *hdcp_work)
 
 }
 
-void hdcp_add_display(struct hdcp_workqueue *hdcp_work, unsigned int 
link_index, struct amdgpu_dm_connector *aconnector,
- bool disable_type1)
+void hdcp_update_display(struct hdcp_workqueue *hdcp_work,
+unsigned int link_index,
+struct amdgpu_dm_connector *aconnector,
+bool disable_type1,
+bool enable_encryption)
 {
struct hdcp_workqueue *hdcp_w = _work[link_index];
struct mod_hdcp_display *display = _work[link_index].display;
struct mod_hdcp_link *link = _work[link_index].link;
+   struct mod_hdcp_display_query query;
 
mutex_lock(_w->mutex);
hdcp_w->aconnector = aconnector;
 
-   hdcp_w->link.adjust.hdcp2.disable_type1 = disable_type1;
-
-   mod_hdcp_add_display(_w->hdcp, link, display, _w->output);
-
-   schedule_delayed_work(_w->property_validate_dwork, 
msecs_to_jiffies(DRM_HDCP_CHECK_PERIOD_MS));
-
-   process_output(hdcp_w);
-
-   mutex_unlock(_w->mutex);
-
-}
-
-void hdcp_remove_display(struct hdcp_workqueue *hdcp_work, unsigned int 
link_index,  unsigned int display_index)
-{
-   struct hdcp_workqueue *hdcp_w = _work[link_index];
-
-   mutex_lock(_w->mutex);
+   query.display = NULL;
+   mod_hdcp_query_display(_w->hdcp, aconnector->base.index, );
+
+   if (query.display != NULL) {
+   memcpy(display, query.display, sizeof(struct mod_hdcp_display));
+   mod_hdcp_remove_display(_w->hdcp,

[PATCH 06/11] drm/amd/display: Enable HDCP 2.2

2019-10-03 Thread Bhawanpreet Lakha 
[Why]
HDCP 2.2 was disabled, we need to enable it

[How]
-Update display topology to support 2.2
-Unset hdcp2.disable in update_config
-Change logic of event_update_property, now we set the property to be
ENABLED for any level of encryption (2.2 or 1.4).

Signed-off-by: Bhawanpreet Lakha 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c | 3 +--
 drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c| 2 +-
 2 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
index 2443c238c188..fc775c0795d8 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
@@ -186,7 +186,7 @@ static void event_property_update(struct work_struct *work)
}
}
 
-   if (hdcp_work->encryption_status == MOD_HDCP_ENCRYPTION_STATUS_HDCP1_ON)
+   if (hdcp_work->encryption_status != MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF)
drm_hdcp_update_content_protection(>base, 
DRM_MODE_CONTENT_PROTECTION_ENABLED);
else
drm_hdcp_update_content_protection(>base, 
DRM_MODE_CONTENT_PROTECTION_DESIRED);
@@ -290,7 +290,6 @@ static void update_config(void *handle, struct 
cp_psp_stream_config *config)
link->dig_be = config->link_enc_inst;
link->ddc_line = aconnector->dc_link->ddc_hw_inst + 1;
link->dp.rev = aconnector->dc_link->dpcd_caps.dpcd_rev.raw;
-   link->adjust.hdcp2.disable = 1;
 
 }
 
diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c 
b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
index 82283c3804df..4a6b95d7b44e 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
@@ -109,7 +109,7 @@ enum mod_hdcp_status mod_hdcp_add_display_topology(struct 
mod_hdcp *hdcp)
dtm_cmd->dtm_in_message.topology_update_v2.dig_fe = 
display->dig_fe;
dtm_cmd->dtm_in_message.topology_update_v2.dp_mst_vcid 
= display->vc_id;

dtm_cmd->dtm_in_message.topology_update_v2.max_hdcp_supported_version =
-   TA_DTM_HDCP_VERSION_MAX_SUPPORTED__1_x;
+   TA_DTM_HDCP_VERSION_MAX_SUPPORTED__2_2;
dtm_cmd->dtm_status = TA_DTM_STATUS__GENERIC_FAILURE;
 
psp_dtm_invoke(psp, dtm_cmd->cmd_id);
-- 
2.17.1

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[PATCH 09/11] drm/amd/display: add force Type0/1 flag

2019-10-03 Thread Bhawanpreet Lakha 
[Why]
Before we had a disable_type1 flag, this forced HDCP 2.2 to type0
There was no way to force type1.

[How]
Remove disable_type1 flag and instead add a flag to force type0/1.

Signed-off-by: Bhawanpreet Lakha 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  2 +-
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c| 15 ---
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h|  2 +-
 .../amd/display/modules/hdcp/hdcp2_transition.c   |  2 +-
 .../gpu/drm/amd/display/modules/hdcp/hdcp_psp.c   |  7 +--
 .../gpu/drm/amd/display/modules/inc/mod_hdcp.h| 11 +--
 6 files changed, 29 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 0bb212e47766..482cde62b555 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -6352,7 +6352,7 @@ static void amdgpu_dm_atomic_commit_tail(struct 
drm_atomic_state *state)
if (is_content_protection_different(new_con_state, 
old_con_state, connector, adev->dm.hdcp_workqueue))
hdcp_update_display(
adev->dm.hdcp_workqueue, 
aconnector->dc_link->link_index, aconnector,
-   new_con_state->hdcp_content_type == 
DRM_MODE_HDCP_CONTENT_TYPE0 ? true : false,
+   new_con_state->hdcp_content_type,
new_con_state->content_protection == 
DRM_MODE_CONTENT_PROTECTION_DESIRED ? true

 : false);
}
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
index ca12362e799a..6c4b3134e786 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
@@ -86,7 +86,7 @@ static void process_output(struct hdcp_workqueue *hdcp_work)
 void hdcp_update_display(struct hdcp_workqueue *hdcp_work,
 unsigned int link_index,
 struct amdgpu_dm_connector *aconnector,
-bool disable_type1,
+uint8_t content_type,
 bool enable_encryption)
 {
struct hdcp_workqueue *hdcp_w = _work[link_index];
@@ -104,9 +104,18 @@ void hdcp_update_display(struct hdcp_workqueue *hdcp_work,
memcpy(display, query.display, sizeof(struct mod_hdcp_display));
mod_hdcp_remove_display(_w->hdcp, aconnector->base.index, 
_w->output);
 
+   hdcp_w->link.adjust.hdcp2.force_type = MOD_HDCP_FORCE_TYPE_0;
+
if (enable_encryption) {
display->adjust.disable = 0;
-   hdcp_w->link.adjust.hdcp2.disable_type1 = disable_type1;
+   if (content_type == DRM_MODE_HDCP_CONTENT_TYPE0) {
+   hdcp_w->link.adjust.hdcp1.disable = 0;
+   hdcp_w->link.adjust.hdcp2.force_type = 
MOD_HDCP_FORCE_TYPE_0;
+   } else if (content_type == DRM_MODE_HDCP_CONTENT_TYPE1) 
{
+   hdcp_w->link.adjust.hdcp1.disable = 1;
+   hdcp_w->link.adjust.hdcp2.force_type = 
MOD_HDCP_FORCE_TYPE_1;
+   }
+
schedule_delayed_work(_w->property_validate_dwork,
  
msecs_to_jiffies(DRM_HDCP_CHECK_PERIOD_MS));
} else {
@@ -304,7 +313,7 @@ static void update_config(void *handle, struct 
cp_psp_stream_config *config)
display->adjust.disable = 1;
link->adjust.auth_delay = 2;
 
-   hdcp_update_display(hdcp_work, link_index, aconnector, false, false);
+   hdcp_update_display(hdcp_work, link_index, aconnector, 
DRM_MODE_HDCP_CONTENT_TYPE0, false);
 }
 
 struct hdcp_workqueue *hdcp_create_workqueue(void *psp_context, struct cp_psp 
*cp_psp, struct dc *dc)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h
index 71e121f037cb..6abde86bce4a 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h
@@ -57,7 +57,7 @@ struct hdcp_workqueue {
 void hdcp_update_display(struct hdcp_workqueue *hdcp_work,
 unsigned int link_index,
 struct amdgpu_dm_connector *aconnector,
-bool disable_type1,
+uint8_t content_type,
 bool enable_encryption);
 
 void hdcp_reset_display(struct hdcp_workqueue *work, unsigned int link_index);
diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c 
b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c
index

[PATCH 03/11] drm/amd/display: Add execution and transition states for HDCP2.2

2019-10-03 Thread Bhawanpreet Lakha 
The module works like a state machine

+-+
--> | Execution.c | --
|   +-+   |
| V
++  ++ +--+
| DM |->| Hdcp.c |  <  | Transition.c |
++<-++ +--+

This patch adds the execution and transition files for 2.2

Extension to "40a702d427 drm/amd/display: Add HDCP module" for 2.2

Signed-off-by: Bhawanpreet Lakha 
---
 .../gpu/drm/amd/display/modules/hdcp/Makefile |   3 +-
 .../gpu/drm/amd/display/modules/hdcp/hdcp.c   |  86 +-
 .../gpu/drm/amd/display/modules/hdcp/hdcp.h   | 127 +++
 .../display/modules/hdcp/hdcp2_execution.c| 881 ++
 .../display/modules/hdcp/hdcp2_transition.c   | 674 ++
 .../drm/amd/display/modules/inc/mod_hdcp.h|   2 +
 6 files changed, 1764 insertions(+), 9 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c
 create mode 100644 drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c

diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/Makefile 
b/drivers/gpu/drm/amd/display/modules/hdcp/Makefile
index 1c3c6d47973a..904424da01b5 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/Makefile
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/Makefile
@@ -24,7 +24,8 @@
 #
 
 HDCP = hdcp_ddc.o hdcp_log.o hdcp_psp.o hdcp.o \
-   hdcp1_execution.o hdcp1_transition.o
+   hdcp1_execution.o hdcp1_transition.o \
+   hdcp2_execution.o hdcp2_transition.o
 
 AMD_DAL_HDCP = $(addprefix $(AMDDALPATH)/modules/hdcp/,$(HDCP))
 #$(info   DAL-HDCP_MAKEFILE )
diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c 
b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
index d7ac445dec6f..a74812977963 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
@@ -37,24 +37,52 @@ static void push_error_status(struct mod_hdcp *hdcp,
HDCP_ERROR_TRACE(hdcp, status);
}
 
-   hdcp->connection.hdcp1_retry_count++;
+   if (is_hdcp1(hdcp)) {
+   hdcp->connection.hdcp1_retry_count++;
+   } else if (is_hdcp2(hdcp)) {
+   hdcp->connection.hdcp2_retry_count++;
+   }
 }
 
 static uint8_t is_cp_desired_hdcp1(struct mod_hdcp *hdcp)
 {
-   int i, display_enabled = 0;
+   int i, is_auth_needed = 0;
 
-   /* if all displays on the link are disabled, hdcp is not desired */
+   /* if all displays on the link don't need authentication,
+* hdcp is not desired
+*/
for (i = 0; i < MAX_NUM_OF_DISPLAYS; i++) {
if (hdcp->connection.displays[i].state != 
MOD_HDCP_DISPLAY_INACTIVE &&
!hdcp->connection.displays[i].adjust.disable) {
-   display_enabled = 1;
+   is_auth_needed = 1;
break;
}
}
 
return (hdcp->connection.hdcp1_retry_count < MAX_NUM_OF_ATTEMPTS) &&
-   display_enabled && 
!hdcp->connection.link.adjust.hdcp1.disable;
+   is_auth_needed &&
+   !hdcp->connection.link.adjust.hdcp1.disable;
+}
+
+static uint8_t is_cp_desired_hdcp2(struct mod_hdcp *hdcp)
+{
+   int i, is_auth_needed = 0;
+
+   /* if all displays on the link don't need authentication,
+* hdcp is not desired
+*/
+   for (i = 0; i < MAX_NUM_OF_DISPLAYS; i++) {
+   if (hdcp->connection.displays[i].state != 
MOD_HDCP_DISPLAY_INACTIVE &&
+   !hdcp->connection.displays[i].adjust.disable) {
+   is_auth_needed = 1;
+   break;
+   }
+   }
+
+   return (hdcp->connection.hdcp2_retry_count < MAX_NUM_OF_ATTEMPTS) &&
+   is_auth_needed &&
+   !hdcp->connection.link.adjust.hdcp2.disable &&
+   !hdcp->connection.is_hdcp2_revoked;
 }
 
 static enum mod_hdcp_status execution(struct mod_hdcp *hdcp,
@@ -82,6 +110,11 @@ static enum mod_hdcp_status execution(struct mod_hdcp *hdcp,
} else if (is_in_hdcp1_dp_states(hdcp)) {
status = mod_hdcp_hdcp1_dp_execution(hdcp,
event_ctx, >hdcp1);
+   } else if (is_in_hdcp2_states(hdcp)) {
+   status = mod_hdcp_hdcp2_execution(hdcp, event_ctx, 
>hdcp2);
+   } else if (is_in_hdcp2_dp_states(hdcp)) {
+   status = mod_hdcp_hdcp2_dp_execution(hdcp,
+   event_ctx, >hdcp2);
}
 out:
return status;
@@ -99,7 +132,10 @@ static enum mod_hdcp_status transition(struct mod_hdcp 
*hdcp,
 
if (is_in_initialized_state(hdcp)) {

[PATCH 00/11] HDCP 2 Content Protection

2019-10-03 Thread Bhawanpreet Lakha 
Just like with the 1.4 series of patches This only introduces the
ability to authenticate and encrypt the link. These patches by
themselves don't constitute a complete and compliant HDCP content
protection solution but are a requirement for such a solution.

Summary of the changes
*Adds 2.2 code to the module
*Enabled HDCP 2.2 authentication/encryption
*Add type0/1 selection for 2.2
*Add MST support (Only tested single daisy chain usecase)

Bhawanpreet Lakha (11):
  drm/amd/display: Add PSP block to verify HDCP2.2 steps
  drm/amd/display: Add DDC handles for HDCP2.2
  drm/amd/display: Add execution and transition states for HDCP2.2
  drm/amd/display: Add logging for HDCP2.2
  drm/amd/display: Change ERROR to WARN for HDCP module
  drm/amd/display: Enable HDCP 2.2
  drm/amd/display: Handle hdcp2.2 type0/1 in dm
  drm/amd/display: Refactor HDCP to handle multiple displays per link
  drm/amd/display: add force Type0/1 flag
  drm/amd/display: Refactor HDCP encryption status update
  drm/amd/display: fix events handling for hdcp

 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  26 +-
 .../amd/display/amdgpu_dm/amdgpu_dm_hdcp.c|  79 +-
 .../amd/display/amdgpu_dm/amdgpu_dm_hdcp.h|   9 +-
 .../gpu/drm/amd/display/modules/hdcp/Makefile |   3 +-
 .../gpu/drm/amd/display/modules/hdcp/hdcp.c   | 101 +-
 .../gpu/drm/amd/display/modules/hdcp/hdcp.h   | 171 
 .../display/modules/hdcp/hdcp2_execution.c| 881 ++
 .../display/modules/hdcp/hdcp2_transition.c   | 674 ++
 .../drm/amd/display/modules/hdcp/hdcp_ddc.c   | 326 +++
 .../drm/amd/display/modules/hdcp/hdcp_log.c   | 118 +++
 .../drm/amd/display/modules/hdcp/hdcp_log.h   |  98 +-
 .../drm/amd/display/modules/hdcp/hdcp_psp.c   | 511 +-
 .../drm/amd/display/modules/hdcp/hdcp_psp.h   | 194 
 .../drm/amd/display/modules/inc/mod_hdcp.h|  15 +-
 14 files changed, 3125 insertions(+), 81 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c
 create mode 100644 drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c

-- 
2.17.1

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[PATCH 01/11] drm/amd/display: Add PSP block to verify HDCP2.2 steps

2019-10-03 Thread Bhawanpreet Lakha 
[Why]
All the HDCP transactions should be verified using PSP

[How]
This patch adds the psp calls we need to verify the steps

Signed-off-by: Bhawanpreet Lakha 
---
 .../gpu/drm/amd/display/modules/hdcp/hdcp.h   |  44 ++
 .../drm/amd/display/modules/hdcp/hdcp_psp.c   | 502 +-
 .../drm/amd/display/modules/hdcp/hdcp_psp.h   | 194 +++
 3 files changed, 739 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h 
b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
index 402bb7999093..596a0192784c 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
@@ -111,8 +111,33 @@ struct mod_hdcp_message_hdcp1 {
uint16_tbinfo_dp;
 };
 
+struct mod_hdcp_message_hdcp2 {
+   uint8_t hdcp2version_hdmi;
+   uint8_t rxcaps_dp[3];
+   uint16_trxstatus;
+
+   uint8_t ake_init[12];
+   uint8_t ake_cert[534];
+   uint8_t ake_no_stored_km[129];
+   uint8_t ake_stored_km[33];
+   uint8_t ake_h_prime[33];
+   uint8_t ake_pairing_info[17];
+   uint8_t lc_init[9];
+   uint8_t lc_l_prime[33];
+   uint8_t ske_eks[25];
+   uint8_t rx_id_list[177]; // 22 + 5 * 31
+   uint16_trx_id_list_size;
+   uint8_t repeater_auth_ack[17];
+   uint8_t repeater_auth_stream_manage[68]; // 6 + 2 * 31
+   uint16_tstream_manage_size;
+   uint8_t repeater_auth_stream_ready[33];
+
+   uint8_t content_stream_type_dp[2];
+};
+
 union mod_hdcp_message {
struct mod_hdcp_message_hdcp1 hdcp1;
+   struct mod_hdcp_message_hdcp2 hdcp2;
 };
 
 struct mod_hdcp_auth_counters {
@@ -234,6 +259,25 @@ enum mod_hdcp_status 
mod_hdcp_hdcp1_enable_dp_stream_encryption(
 enum mod_hdcp_status mod_hdcp_hdcp1_link_maintenance(struct mod_hdcp *hdcp);
 enum mod_hdcp_status mod_hdcp_hdcp1_get_link_encryption_status(struct mod_hdcp 
*hdcp,
   enum 
mod_hdcp_encryption_status *encryption_status);
+enum mod_hdcp_status mod_hdcp_hdcp2_create_session(struct mod_hdcp *hdcp);
+enum mod_hdcp_status mod_hdcp_hdcp2_destroy_session(struct mod_hdcp *hdcp);
+enum mod_hdcp_status mod_hdcp_hdcp2_prepare_ake_init(struct mod_hdcp *hdcp);
+enum mod_hdcp_status mod_hdcp_hdcp2_validate_ake_cert(struct mod_hdcp *hdcp);
+enum mod_hdcp_status mod_hdcp_hdcp2_validate_h_prime(struct mod_hdcp *hdcp);
+enum mod_hdcp_status mod_hdcp_hdcp2_prepare_lc_init(struct mod_hdcp *hdcp);
+enum mod_hdcp_status mod_hdcp_hdcp2_validate_l_prime(struct mod_hdcp *hdcp);
+enum mod_hdcp_status mod_hdcp_hdcp2_prepare_eks(struct mod_hdcp *hdcp);
+enum mod_hdcp_status mod_hdcp_hdcp2_enable_encryption(struct mod_hdcp *hdcp);
+enum mod_hdcp_status mod_hdcp_hdcp2_validate_rx_id_list(struct mod_hdcp *hdcp);
+enum mod_hdcp_status mod_hdcp_hdcp2_enable_dp_stream_encryption(
+   struct mod_hdcp *hdcp);
+enum mod_hdcp_status mod_hdcp_hdcp2_prepare_stream_management(
+   struct mod_hdcp *hdcp);
+enum mod_hdcp_status mod_hdcp_hdcp2_validate_stream_ready(
+   struct mod_hdcp *hdcp);
+enum mod_hdcp_status mod_hdcp_hdcp2_get_link_encryption_status(struct mod_hdcp 
*hdcp,
+  enum 
mod_hdcp_encryption_status *encryption_status);
+
 /* ddc functions */
 enum mod_hdcp_status mod_hdcp_read_bksv(struct mod_hdcp *hdcp);
 enum mod_hdcp_status mod_hdcp_read_bcaps(struct mod_hdcp *hdcp);
diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c 
b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
index 646d909bbc37..8187cae5f5ca 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
@@ -31,6 +31,19 @@
 #include "amdgpu.h"
 #include "hdcp_psp.h"
 
+static void hdcp2_message_init(struct mod_hdcp *hdcp,
+  struct 
ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_input_v2 *in)
+{
+   in->session_handle = hdcp->auth.id;
+   in->prepare.msg1_id = TA_HDCP_HDCP2_MSG_ID__NULL_MESSAGE;
+   in->prepare.msg2_id = TA_HDCP_HDCP2_MSG_ID__NULL_MESSAGE;
+   in->process.msg1_desc.msg_id = TA_HDCP_HDCP2_MSG_ID__NULL_MESSAGE;
+   in->process.msg1_desc.msg_size = 0;
+   in->process.msg2_desc.msg_id = TA_HDCP_HDCP2_MSG_ID__NULL_MESSAGE;
+   in->process.msg2_desc.msg_size = 0;
+   in->process.msg3_desc.msg_id = TA_HDCP_HDCP2_MSG_ID__NULL_MESSAGE;
+   in->process.msg3_desc.msg_id = 0;
+}
 enum mod_hdcp_status mod_hdcp_remove_display_topology(struct mod_hdcp *hdcp)
 {
 
@@ -42,7 +55,7 @@ enum mod_hdcp_status mod_hdcp_remove_display_topology(struct 
mod_hdcp *hdcp)
dtm_cmd = (struct ta_dtm_shared_memory 
*)psp->dtm_context.dtm_shared_buf;
 
for (i = 0; i < MAX_NUM_OF_DISPLAYS; i++) {
-   if

[PATCH 05/11] drm/amd/display: Change ERROR to WARN for HDCP module

2019-10-03 Thread Bhawanpreet Lakha 
[Why]
HDCP is a bit finicky so we try it 3 times, this leads to a case where
if we fail the first time and pass the second time the error is still
shown in dmesg for the first failed attempt.

This leads to false positive errors.

[How]
Change the logging from ERROR to WARNING. Warnings are still shown in dmesg
to know what went wrong.

Signed-off-by: Bhawanpreet Lakha 
---
 drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.h 
b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.h
index b29322e7d5fe..ff91373ebada 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.h
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.h
@@ -27,7 +27,7 @@
 #define MOD_HDCP_LOG_H_
 
 #ifdef CONFIG_DRM_AMD_DC_HDCP
-#define HDCP_LOG_ERR(hdcp, ...) DRM_ERROR(__VA_ARGS__)
+#define HDCP_LOG_ERR(hdcp, ...) DRM_WARN(__VA_ARGS__)
 #define HDCP_LOG_VER(hdcp, ...) DRM_DEBUG_KMS(__VA_ARGS__)
 #define HDCP_LOG_FSM(hdcp, ...) DRM_DEBUG_KMS(__VA_ARGS__)
 #define HDCP_LOG_TOP(hdcp, ...) pr_debug("[HDCP_TOP]:"__VA_ARGS__)
@@ -37,7 +37,7 @@
 /* default logs */
 #define HDCP_ERROR_TRACE(hdcp, status) \
HDCP_LOG_ERR(hdcp, \
-   "[Link %d] ERROR %s IN STATE %s", \
+   "[Link %d] WARNING %s IN STATE %s", \
hdcp->config.index, \
mod_hdcp_status_to_str(status), \
mod_hdcp_state_id_to_str(hdcp->state.id))
-- 
2.17.1

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[PATCH 02/11] drm/amd/display: Add DDC handles for HDCP2.2

2019-10-03 Thread Bhawanpreet Lakha 
[Why]
We need these to read and write to aux/i2c, during
authentication

[How]
Create read/write functions for all the steps
(Eg, h_prime, paring_info etc)

Signed-off-by: Bhawanpreet Lakha 
---
 .../drm/amd/display/modules/hdcp/hdcp_ddc.c   | 326 ++
 1 file changed, 326 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c 
b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c
index e7baae059b85..8059aff9911f 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c
@@ -51,6 +51,26 @@ enum mod_hdcp_ddc_message_id {
MOD_HDCP_MESSAGE_ID_READ_KSV_FIFO,
MOD_HDCP_MESSAGE_ID_READ_BINFO,
 
+   /* HDCP 2.2 */
+
+   MOD_HDCP_MESSAGE_ID_HDCP2VERSION,
+   MOD_HDCP_MESSAGE_ID_RX_CAPS,
+   MOD_HDCP_MESSAGE_ID_WRITE_AKE_INIT,
+   MOD_HDCP_MESSAGE_ID_READ_AKE_SEND_CERT,
+   MOD_HDCP_MESSAGE_ID_WRITE_AKE_NO_STORED_KM,
+   MOD_HDCP_MESSAGE_ID_WRITE_AKE_STORED_KM,
+   MOD_HDCP_MESSAGE_ID_READ_AKE_SEND_H_PRIME,
+   MOD_HDCP_MESSAGE_ID_READ_AKE_SEND_PAIRING_INFO,
+   MOD_HDCP_MESSAGE_ID_WRITE_LC_INIT,
+   MOD_HDCP_MESSAGE_ID_READ_LC_SEND_L_PRIME,
+   MOD_HDCP_MESSAGE_ID_WRITE_SKE_SEND_EKS,
+   MOD_HDCP_MESSAGE_ID_READ_REPEATER_AUTH_SEND_RECEIVERID_LIST,
+   MOD_HDCP_MESSAGE_ID_WRITE_REPEATER_AUTH_SEND_ACK,
+   MOD_HDCP_MESSAGE_ID_WRITE_REPEATER_AUTH_STREAM_MANAGE,
+   MOD_HDCP_MESSAGE_ID_READ_REPEATER_AUTH_STREAM_READY,
+   MOD_HDCP_MESSAGE_ID_READ_RXSTATUS,
+   MOD_HDCP_MESSAGE_ID_WRITE_CONTENT_STREAM_TYPE,
+
MOD_HDCP_MESSAGE_ID_MAX
 };
 
@@ -70,6 +90,22 @@ static const uint8_t hdcp_i2c_offsets[] = {
[MOD_HDCP_MESSAGE_ID_READ_BSTATUS] = 0x41,
[MOD_HDCP_MESSAGE_ID_READ_KSV_FIFO] = 0x43,
[MOD_HDCP_MESSAGE_ID_READ_BINFO] = 0xFF,
+   [MOD_HDCP_MESSAGE_ID_HDCP2VERSION] = 0x50,
+   [MOD_HDCP_MESSAGE_ID_WRITE_AKE_INIT] = 0x60,
+   [MOD_HDCP_MESSAGE_ID_READ_AKE_SEND_CERT] = 0x80,
+   [MOD_HDCP_MESSAGE_ID_WRITE_AKE_NO_STORED_KM] = 0x60,
+   [MOD_HDCP_MESSAGE_ID_WRITE_AKE_STORED_KM] = 0x60,
+   [MOD_HDCP_MESSAGE_ID_READ_AKE_SEND_H_PRIME] = 0x80,
+   [MOD_HDCP_MESSAGE_ID_READ_AKE_SEND_PAIRING_INFO] = 0x80,
+   [MOD_HDCP_MESSAGE_ID_WRITE_LC_INIT] = 0x60,
+   [MOD_HDCP_MESSAGE_ID_READ_LC_SEND_L_PRIME] = 0x80,
+   [MOD_HDCP_MESSAGE_ID_WRITE_SKE_SEND_EKS] = 0x60,
+   [MOD_HDCP_MESSAGE_ID_READ_REPEATER_AUTH_SEND_RECEIVERID_LIST] = 0x80,
+   [MOD_HDCP_MESSAGE_ID_WRITE_REPEATER_AUTH_SEND_ACK] = 0x60,
+   [MOD_HDCP_MESSAGE_ID_WRITE_REPEATER_AUTH_STREAM_MANAGE] = 0x60,
+   [MOD_HDCP_MESSAGE_ID_READ_REPEATER_AUTH_STREAM_READY] = 0x80,
+   [MOD_HDCP_MESSAGE_ID_READ_RXSTATUS] = 0x70,
+   [MOD_HDCP_MESSAGE_ID_WRITE_CONTENT_STREAM_TYPE] = 0x0
 };
 
 static const uint32_t hdcp_dpcd_addrs[] = {
@@ -88,6 +124,22 @@ static const uint32_t hdcp_dpcd_addrs[] = {
[MOD_HDCP_MESSAGE_ID_READ_BSTATUS] = 0x68029,
[MOD_HDCP_MESSAGE_ID_READ_KSV_FIFO] = 0x6802c,
[MOD_HDCP_MESSAGE_ID_READ_BINFO] = 0x6802a,
+   [MOD_HDCP_MESSAGE_ID_RX_CAPS] = 0x6921d,
+   [MOD_HDCP_MESSAGE_ID_WRITE_AKE_INIT] = 0x69000,
+   [MOD_HDCP_MESSAGE_ID_READ_AKE_SEND_CERT] = 0x6900b,
+   [MOD_HDCP_MESSAGE_ID_WRITE_AKE_NO_STORED_KM] = 0x69220,
+   [MOD_HDCP_MESSAGE_ID_WRITE_AKE_STORED_KM] = 0x692a0,
+   [MOD_HDCP_MESSAGE_ID_READ_AKE_SEND_H_PRIME] = 0x692c0,
+   [MOD_HDCP_MESSAGE_ID_READ_AKE_SEND_PAIRING_INFO] = 0x692e0,
+   [MOD_HDCP_MESSAGE_ID_WRITE_LC_INIT] = 0x692f0,
+   [MOD_HDCP_MESSAGE_ID_READ_LC_SEND_L_PRIME] = 0x692f8,
+   [MOD_HDCP_MESSAGE_ID_WRITE_SKE_SEND_EKS] = 0x69318,
+   [MOD_HDCP_MESSAGE_ID_READ_REPEATER_AUTH_SEND_RECEIVERID_LIST] = 0x69330,
+   [MOD_HDCP_MESSAGE_ID_WRITE_REPEATER_AUTH_SEND_ACK] = 0x693e0,
+   [MOD_HDCP_MESSAGE_ID_WRITE_REPEATER_AUTH_STREAM_MANAGE] = 0x693f0,
+   [MOD_HDCP_MESSAGE_ID_READ_REPEATER_AUTH_STREAM_READY] = 0x69473,
+   [MOD_HDCP_MESSAGE_ID_READ_RXSTATUS] = 0x69493,
+   [MOD_HDCP_MESSAGE_ID_WRITE_CONTENT_STREAM_TYPE] = 0x69494
 };
 
 static enum mod_hdcp_status read(struct mod_hdcp *hdcp,
@@ -303,3 +355,277 @@ enum mod_hdcp_status mod_hdcp_write_an(struct mod_hdcp 
*hdcp)
hdcp->auth.msg.hdcp1.an,
sizeof(hdcp->auth.msg.hdcp1.an));
 }
+
+enum mod_hdcp_status mod_hdcp_read_hdcp2version(struct mod_hdcp *hdcp)
+{
+   enum mod_hdcp_status status;
+
+   if (is_dp_hdcp(hdcp))
+   status = MOD_HDCP_STATUS_INVALID_OPERATION;
+   else
+   status = read(hdcp, MOD_HDCP_MESSAGE_ID_HDCP2VERSION,
+   >auth.msg.hdcp2.hdcp2version_hdmi,
+   sizeof(hdcp->auth.msg.hdcp2.hdcp2version_hdmi));
+
+   return status;
+}
+
+enum mod_hdcp_status mod_hdcp_read_rxcaps(struct mod_hdcp *hdcp)
+{
+   enum mod_hdcp_status status;
+
+   if (!is_dp_hdcp(hdcp))
+

[PATCH] drm/amd/display: Make plane z-pos explicit to userspace

2019-10-03 Thread Nicholas Kazlauskas 
[Why]
Many userspace assumes that the DRM plane index indicates the plane
z-order, with a lower index being lower depth and a higher index being
higher depth. This is currently what we assume in DM.

DRM has a zpos plane property to make this explicit to userspace and
there are clients that make use of this information.

[How]
Attach the immutable zpos property to the plane.

While we can technically order the planes in any manner since we
virtualize them in DC we don't currently have the software support.

The z-pos could potentially become immutable later but for now
just let userspace do the ordering.

Cc: Leo Li 
Cc: Harry Wentland 
Cc: Rodrigo Siqueira 
Signed-off-by: Nicholas Kazlauskas 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 239b1ae86007..e58b0b7e3c52 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4897,6 +4897,9 @@ static int amdgpu_dm_plane_init(struct 
amdgpu_display_manager *dm,
if (res)
return res;
 
+   /* Make z-pos of each plane explicit - lower ID is lower depth */
+   drm_plane_create_zpos_immutable_property(plane, plane->index);
+
if (plane->type == DRM_PLANE_TYPE_OVERLAY &&
plane_cap && plane_cap->per_pixel_alpha) {
unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
-- 
2.20.1

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Re: [PATCH 2/2] drm/amdgpu: disable MSI-X on APUs

2019-10-03 Thread Liu, Shaoyun 
Thanks Alex and  Tom to catch and  revolve the issue .  I didn't do 
enough test on original test.

We don't need to enable msix  on APU .   The serials is reviewed by 
shaoyun.liu 


Regards

shaoyun.liu



On 2019-10-03 10:13 a.m., Alex Deucher wrote:
> Raven claims to support them, but seems to have problems.  Stick
> with MSIs for now on APUs.
>
> Tested-by: Tom St Denis 
> Signed-off-by: Alex Deucher 
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 3 ++-
>   1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> index 98aa28edba6a..8f2236bd7d0e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> @@ -248,7 +248,8 @@ int amdgpu_irq_init(struct amdgpu_device *adev)
>   unsigned int flags;
>   int nvec = pci_msix_vec_count(adev->pdev);
>   
> - if (nvec <= 0) {
> + /* Raven claims to support MSI-X, but seems to have problems */
> + if ((nvec <= 0) || (adev->flags & AMD_IS_APU)) {
>   flags = PCI_IRQ_MSI;
>   nvec = 1;
>   } else {
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[PATCH] drm/amdgpu/powerplay: fix typo in mvdd table setup

2019-10-03 Thread Alex Deucher 
Polaris and vegam use count for the value rather than
level.  This looks like a copy paste typo from when
the code was adapted from previous asics.

I'm not sure that the SMU actually uses this value, so
I don't know that it actually is a bug per se.

Bug: https://bugs.freedesktop.org/show_bug.cgi?id=108609
Reported-by: Robert Strube 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c | 2 +-
 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
index dc754447f0dd..23c12018dbc1 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
@@ -655,7 +655,7 @@ static int polaris10_populate_smc_mvdd_table(struct 
pp_hwmgr *hwmgr,
count = SMU_MAX_SMIO_LEVELS;
for (level = 0; level < count; level++) {
table->SmioTable2.Pattern[level].Voltage =
-   
PP_HOST_TO_SMC_US(data->mvdd_voltage_table.entries[count].value * 
VOLTAGE_SCALE);
+   
PP_HOST_TO_SMC_US(data->mvdd_voltage_table.entries[level].value * 
VOLTAGE_SCALE);
/* Index into DpmTable.Smio. Drive bits from Smio entry 
to get this voltage level.*/
table->SmioTable2.Pattern[level].Smio =
(uint8_t) level;
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c
index 7c960b07746f..ae18fbcb26fb 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c
@@ -456,7 +456,7 @@ static int vegam_populate_smc_mvdd_table(struct pp_hwmgr 
*hwmgr,
count = SMU_MAX_SMIO_LEVELS;
for (level = 0; level < count; level++) {
table->SmioTable2.Pattern[level].Voltage = 
PP_HOST_TO_SMC_US(
-   
data->mvdd_voltage_table.entries[count].value * VOLTAGE_SCALE);
+   
data->mvdd_voltage_table.entries[level].value * VOLTAGE_SCALE);
/* Index into DpmTable.Smio. Drive bits from Smio entry 
to get this voltage level.*/
table->SmioTable2.Pattern[level].Smio =
(uint8_t) level;
-- 
2.20.1

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[PATCH 2/2] drm/amdgpu: disable MSI-X on APUs

2019-10-03 Thread Alex Deucher 
Raven claims to support them, but seems to have problems.  Stick
with MSIs for now on APUs.

Tested-by: Tom St Denis 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
index 98aa28edba6a..8f2236bd7d0e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
@@ -248,7 +248,8 @@ int amdgpu_irq_init(struct amdgpu_device *adev)
unsigned int flags;
int nvec = pci_msix_vec_count(adev->pdev);
 
-   if (nvec <= 0) {
+   /* Raven claims to support MSI-X, but seems to have problems */
+   if ((nvec <= 0) || (adev->flags & AMD_IS_APU)) {
flags = PCI_IRQ_MSI;
nvec = 1;
} else {
-- 
2.20.1

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[PATCH 1/2] drm/amdgpu: improve MSI-X handling

2019-10-03 Thread Alex Deucher 
Check the number of supported vectors and fall back to MSI if
we return or error or 0 MSI-X vectors.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 14 +++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
index 50771b2757dc..98aa28edba6a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
@@ -245,11 +245,19 @@ int amdgpu_irq_init(struct amdgpu_device *adev)
adev->irq.msi_enabled = false;
 
if (amdgpu_msi_ok(adev)) {
-   int nvec = pci_alloc_irq_vectors(adev->pdev, 1, 
pci_msix_vec_count(adev->pdev),
-   PCI_IRQ_MSI | PCI_IRQ_MSIX);
+   unsigned int flags;
+   int nvec = pci_msix_vec_count(adev->pdev);
+
+   if (nvec <= 0) {
+   flags = PCI_IRQ_MSI;
+   nvec = 1;
+   } else {
+   flags = PCI_IRQ_MSI | PCI_IRQ_MSIX;
+   }
+   nvec = pci_alloc_irq_vectors(adev->pdev, 1, nvec, flags);
if (nvec > 0) {
adev->irq.msi_enabled = true;
-   dev_dbg(adev->dev, "amdgpu: using MSI.\n");
+   dev_dbg(adev->dev, "amdgpu: using MSI/MSI-X.\n");
}
}
 
-- 
2.20.1

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Re: [PATCH] drm/amdgpu: do not execute 0-sized IBs

2019-10-03 Thread Pelloux-prayer, Pierre-eric 
On 03/10/2019 15:12, Deucher, Alexander wrote:
> Does some variant of the patch on this thread help?
> https://patchwork.freedesktop.org/patch/333068/

Hi Alex,

The added condition in this patch is:

   !(adev->asic_type >= CHIP_NAVI10 && adev->asic_type <= CHIP_NAVI12) ||

which will evaluate to "false ||" on Navi10 so I don't think it'll help.

I'll send an updated version of my patch that will only modify 
gmc_v10_0_flush_gpu_tlb
to not send a 0-sized IB.

Thanks,
Pierre-Eric


> 
> Alex
> 
> --
> *From:* amd-gfx  on behalf of 
> Pelloux-prayer, Pierre-eric 
> *Sent:* Thursday, October 3, 2019 4:25 AM
> *To:* Koenig, Christian ; 
> amd-gfx@lists.freedesktop.org 
> *Subject:* Re: [PATCH] drm/amdgpu: do not execute 0-sized IBs
>  
> 
> On 03/10/2019 10:09, Christian König wrote:
>> Am 03.10.19 um 10:03 schrieb Pelloux-prayer, Pierre-eric:
>>> This can be safely skipped entirely.
>>> This seems to help with https://bugs.freedesktop.org/show_bug.cgi?id=111481.
>> 
>> NAK, please instead fix gmc_v10_0_flush_gpu_tlb to include at least some NOP 
>> in the submitted IBs.
> 
> Is there any interest in executing an empty (or only filled with NOPs) IB?
> 
> Anyway I can modify the patch to do this.
> 
> Thanks,
> Pierre-Eric
> 
>> 
>> Christian.
>> 
>>>
>>> Signed-off-by: Pierre-Eric Pelloux-Prayer 
>>> 
>>> ---
>>>   drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 5 +
>>>   1 file changed, 5 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c 
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
>>> index 60655834d649..aa163e679f1f 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
>>> @@ -227,6 +227,11 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, 
>>> unsigned num_ibs,
>>>   !amdgpu_sriov_vf(adev)) /* for SRIOV preemption, Preamble CE 
>>> ib must be inserted anyway */
>>>   continue;
>>>   +    if (ib->length_dw == 0) {
>>> +    /* On Navi gmc_v10_0_flush_gpu_tlb emits 0 sized IB */
>>> +    continue;
>>> +    }
>>> +
>>>   amdgpu_ring_emit_ib(ring, job, ib, status);
>>>   status &= ~AMDGPU_HAVE_CTX_SWITCH;
>>>   }
>> 
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Re: [PATCH] drm/drm_edid: correct VIC and HDMI_VIC under HDMI 2.0

2019-10-03 Thread Ville Syrjälä 
On Thu, Oct 03, 2019 at 06:49:05AM +, Lin, Wayne wrote:
> 
> 
> 
> From: Ville Syrjälä 
> Sent: Wednesday, October 2, 2019 19:58
> To: Lin, Wayne 
> Cc: dri-de...@lists.freedesktop.org ; 
> amd-gfx@lists.freedesktop.org ; Li, Sun peng 
> (Leo) ; Kazlauskas, Nicholas 
> Subject: Re: [PATCH] drm/drm_edid: correct VIC and HDMI_VIC under HDMI 2.0
> 
> On Tue, Sep 24, 2019 at 01:26:21PM +0800, Wayne Lin wrote:
> > In HDMI 1.4 defines 4k modes without specific aspect ratio.
> > However, in HDMI 2.0, adds aspect ratio attribute to distinguish different
> > 4k modes.
> >
> > According to Appendix E of HDMI 2.0 spec, source should use VSIF to
> > indicate VIC mode only when the mode is one defined in HDMI 1.4b 4K modes.
> > Otherwise, use AVI infoframes to convey VIC.
> >
> > eg: VIC_103 should use AVI infoframes and VIC_93 use VSIF
> >
> > When the sink is HDMI 2.0, current code in
> > drm_hdmi_avi_infoframe_from_display_mode will also force mode VIC_103 to
> > have VIC value 0. This violates the spec and needs to be corrected.
> 
> > Where is that being done? We only set the AVI VIC to zero if we're going
> > to use the HDMI VIC instead.
> 
> Appreciate for your time and apologize for not explaining it clearly.
> Current code in drm_hdmi_avi_infoframe_from_display_mode() will call
> drm_match_hdmi_mode() to set up vendor_if_vic. By checking
> drm_valid_hdmi_vic(vendor_if_vic) to see if the vic info should be conveyed 
> by avi
> or not.
> 
> But in drm_match_hdmi_mode(), code doesn't enable match_flags with
> DRM_MODE_MATCH_ASPECT_RATIO. I think it's due to HDMI1.4b doesn't specify
> 4K mode conveyed by HDMI VIC with particular aspect ratio. But in Appendix E 
> of
> HDMI 2.0 spec, it specify only 4k modes with particular aspect ratio should 
> use VSIF to convey.
> Hence, when the sink support HDMI 2.0 and set the mode to be VIC_103, calling
> drm_match_hdmi_mode(mode) will return vendor_if_vic = 3 (VIC_93 and VIC_103 
> are having
> the same timing but different aspect ratio). Thereafter will set the  
> frame->video_code to 0.
> However, VIC_103 should use AVI VIC according to HDMI 2.0 spec (only VIC: 93, 
> 94, 95 &
> 98 should use VSIF).
> 
> This patch try to revise that, when the sink support HDMI 2.0, 
> drm_match_hdmi_mode()
> should also take aspect ratio into consideration.
> But for easy reading, I add another function "drm_match_hdmi_1_4_mode" to do 
> so.

Seems rather convoluted. I think we should just add the aspect ratios
to edid_4k_modes[]. Or is there some problem with that approach?

> 
> > The same situation occurs in drm_hdmi_vendor_infoframe_from_display_mode
> > and should set HDMI_VIC when the mode is one defined in HDMI 1.4b 4K
> > modes.
> 
> > Yes, and we do that. "vic = drm_match_hdmi_mode(mode);"
> 
> > Apart from adding the aspect ratios I don't really understand what
> > you're trying to achieve here.
> 
> For HDMI 2.0 sink, drm_match_hdmi_mode() should also take aspect ratio into 
> consideration.
> Once again, very appreciate for your time.
> 
> > ---
> >  drivers/gpu/drm/drm_edid.c | 95 --
> >  1 file changed, 92 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> > index 649cfd8b4200..0fea9bf4ec67 100644
> > --- a/drivers/gpu/drm/drm_edid.c
> > +++ b/drivers/gpu/drm/drm_edid.c
> > @@ -1306,6 +1306,37 @@ static const struct drm_display_mode edid_4k_modes[] 
> > = {
> >  .vrefresh = 24, },
> >  };
> >
> > +/*
> > + * 4k modes of HDMI 1.4 defined in HDMI 2.0. Index using the VIC.
> > + */
> > +static const struct drm_display_mode hdmi_1_4_edid_4k_modes[] = {
> > + /* 0 - dummy, VICs start at 1 */
> > + { },
> > + /* 1 - 3840x2160@30Hz */
> > + { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
> > +3840, 4016, 4104, 4400, 0,
> > +2160, 2168, 2178, 2250, 0,
> > +DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
> > +   .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
> > + /* 2 - 3840x2160@25Hz */
> > + { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
> > +3840, 4896, 4984, 5280, 0,
> > +2160, 2168, 2178, 2250, 0,
> > +DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
> > +   .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
> > + /* 3 - 3840x2160@24Hz */
> > + { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
> > +3840, 5116, 5204, 5500, 0,
> > +2160, 2168, 2178, 2250, 0,
> > +DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
> > +   .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
> > + /* 4 - 4096x2160@24Hz (SMPTE) */
> > + { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
> > +4096, 5116, 5204, 5500, 0,
> > +2160, 2168, 2178, 2250, 0,
> > +

Re: [PATCH][drm-next] drm/amd/display: fix spelling mistake AUTHENICATED -> AUTHENTICATED

2019-10-03 Thread Harry Wentland 
On 2019-10-03 4:22 a.m., Colin King wrote:
> From: Colin Ian King 
> 
> There is a spelling mistake in the macros H1_A45_AUTHENICATED and
> D1_A4_AUTHENICATED, fix these by adding the missing T.
> 
> Signed-off-by: Colin Ian King 

Reviewed-by: Harry Wentland 

Harry

> ---
>  drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h  |  4 ++--
>  .../drm/amd/display/modules/hdcp/hdcp1_execution.c   |  4 ++--
>  .../drm/amd/display/modules/hdcp/hdcp1_transition.c  | 12 ++--
>  drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c  |  8 
>  4 files changed, 14 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h 
> b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
> index 402bb7999093..5664bc0b5bd0 100644
> --- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
> +++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
> @@ -176,7 +176,7 @@ enum mod_hdcp_hdcp1_state_id {
>   H1_A0_WAIT_FOR_ACTIVE_RX,
>   H1_A1_EXCHANGE_KSVS,
>   H1_A2_COMPUTATIONS_A3_VALIDATE_RX_A6_TEST_FOR_REPEATER,
> - H1_A45_AUTHENICATED,
> + H1_A45_AUTHENTICATED,
>   H1_A8_WAIT_FOR_READY,
>   H1_A9_READ_KSV_LIST,
>   HDCP1_STATE_END = H1_A9_READ_KSV_LIST
> @@ -188,7 +188,7 @@ enum mod_hdcp_hdcp1_dp_state_id {
>   D1_A1_EXCHANGE_KSVS,
>   D1_A23_WAIT_FOR_R0_PRIME,
>   D1_A2_COMPUTATIONS_A3_VALIDATE_RX_A5_TEST_FOR_REPEATER,
> - D1_A4_AUTHENICATED,
> + D1_A4_AUTHENTICATED,
>   D1_A6_WAIT_FOR_READY,
>   D1_A7_READ_KSV_LIST,
>   HDCP1_DP_STATE_END = D1_A7_READ_KSV_LIST,
> diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c 
> b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c
> index 9e7302eac299..3db4a7da414f 100644
> --- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c
> +++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c
> @@ -476,7 +476,7 @@ enum mod_hdcp_status mod_hdcp_hdcp1_execution(struct 
> mod_hdcp *hdcp,
>   status = computations_validate_rx_test_for_repeater(hdcp,
>   event_ctx, input);
>   break;
> - case H1_A45_AUTHENICATED:
> + case H1_A45_AUTHENTICATED:
>   status = authenticated(hdcp, event_ctx, input);
>   break;
>   case H1_A8_WAIT_FOR_READY:
> @@ -513,7 +513,7 @@ extern enum mod_hdcp_status 
> mod_hdcp_hdcp1_dp_execution(struct mod_hdcp *hdcp,
>   status = computations_validate_rx_test_for_repeater(
>   hdcp, event_ctx, input);
>   break;
> - case D1_A4_AUTHENICATED:
> + case D1_A4_AUTHENTICATED:
>   status = authenticated_dp(hdcp, event_ctx, input);
>   break;
>   case D1_A6_WAIT_FOR_READY:
> diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_transition.c 
> b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_transition.c
> index 1d187809b709..136b8011ff3f 100644
> --- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_transition.c
> +++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_transition.c
> @@ -81,11 +81,11 @@ enum mod_hdcp_status mod_hdcp_hdcp1_transition(struct 
> mod_hdcp *hdcp,
>   set_state_id(hdcp, output, H1_A8_WAIT_FOR_READY);
>   } else {
>   callback_in_ms(0, output);
> - set_state_id(hdcp, output, H1_A45_AUTHENICATED);
> + set_state_id(hdcp, output, H1_A45_AUTHENTICATED);
>   HDCP_FULL_DDC_TRACE(hdcp);
>   }
>   break;
> - case H1_A45_AUTHENICATED:
> + case H1_A45_AUTHENTICATED:
>   if (input->link_maintenance != PASS) {
>   /* 1A-07: consider invalid ri' a failure */
>   /* 1A-07a: consider read ri' not returned a failure */
> @@ -129,7 +129,7 @@ enum mod_hdcp_status mod_hdcp_hdcp1_transition(struct 
> mod_hdcp *hdcp,
>   break;
>   }
>   callback_in_ms(0, output);
> - set_state_id(hdcp, output, H1_A45_AUTHENICATED);
> + set_state_id(hdcp, output, H1_A45_AUTHENTICATED);
>   HDCP_FULL_DDC_TRACE(hdcp);
>   break;
>   default:
> @@ -224,11 +224,11 @@ enum mod_hdcp_status 
> mod_hdcp_hdcp1_dp_transition(struct mod_hdcp *hdcp,
>   set_watchdog_in_ms(hdcp, 5000, output);
>   set_state_id(hdcp, output, D1_A6_WAIT_FOR_READY);
>   } else {
> - set_state_id(hdcp, output, D1_A4_AUTHENICATED);
> + set_state_id(hdcp, output, D1_A4_AUTHENTICATED);
>   HDCP_FULL_DDC_TRACE(hdcp);
>   }
>   break;
> - case D1_A4_AUTHENICATED:
> + case D1_A4_AUTHENTICATED:
>   if (input->link_integiry_check != PASS ||
>   input->reauth_request_check != PASS) {
>   /* 1A-07: restart hdcp on a link

Re: [PATCH] drm/amdgpu: do not execute 0-sized IBs

2019-10-03 Thread Deucher, Alexander 
Does some variant of the patch on this thread help?
https://patchwork.freedesktop.org/patch/333068/

Alex


From: amd-gfx  on behalf of 
Pelloux-prayer, Pierre-eric 
Sent: Thursday, October 3, 2019 4:25 AM
To: Koenig, Christian ; amd-gfx@lists.freedesktop.org 

Subject: Re: [PATCH] drm/amdgpu: do not execute 0-sized IBs


On 03/10/2019 10:09, Christian König wrote:
> Am 03.10.19 um 10:03 schrieb Pelloux-prayer, Pierre-eric:
>> This can be safely skipped entirely.
>> This seems to help with https://bugs.freedesktop.org/show_bug.cgi?id=111481.
>
> NAK, please instead fix gmc_v10_0_flush_gpu_tlb to include at least some NOP 
> in the submitted IBs.

Is there any interest in executing an empty (or only filled with NOPs) IB?

Anyway I can modify the patch to do this.

Thanks,
Pierre-Eric

>
> Christian.
>
>>
>> Signed-off-by: Pierre-Eric Pelloux-Prayer 
>> 
>> ---
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 5 +
>>   1 file changed, 5 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c 
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
>> index 60655834d649..aa163e679f1f 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
>> @@ -227,6 +227,11 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, 
>> unsigned num_ibs,
>>   !amdgpu_sriov_vf(adev)) /* for SRIOV preemption, Preamble CE 
>> ib must be inserted anyway */
>>   continue;
>>   +if (ib->length_dw == 0) {
>> +/* On Navi gmc_v10_0_flush_gpu_tlb emits 0 sized IB */
>> +continue;
>> +}
>> +
>>   amdgpu_ring_emit_ib(ring, job, ib, status);
>>   status &= ~AMDGPU_HAVE_CTX_SWITCH;
>>   }
>
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Re: [PATCH v2 00/14] DSC MST support for AMDGPU

2019-10-03 Thread Jani Nikula 
On Tue, 01 Oct 2019,  wrote:
> This set of patches is a continuation of DSC enablement
> patches for AMDGPU. This set enables DSC on MST. It also
> contains implementation of both encoder and connector
> atomic check routines.

Please consider *not* using git send-email --chain-reply-to option (or
sendemail.chainReplyTo configuration). Or, if it comes from git
format-patch, --thread=deep / format.thread=deep.

BR,
Jani.

-- 
Jani Nikula, Intel Open Source Graphics Center
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Re: [PATCH] drm/amdgpu: do not execute 0-sized IBs

2019-10-03 Thread Koenig, Christian 


Am 03.10.2019 10:25 schrieb "Pelloux-prayer, Pierre-eric" 
:

On 03/10/2019 10:09, Christian König wrote:
> Am 03.10.19 um 10:03 schrieb Pelloux-prayer, Pierre-eric:
>> This can be safely skipped entirely.
>> This seems to help with https://bugs.freedesktop.org/show_bug.cgi?id=111481.
>
> NAK, please instead fix gmc_v10_0_flush_gpu_tlb to include at least some NOP 
> in the submitted IBs.

Is there any interest in executing an empty (or only filled with NOPs) IB?

Yeah, we used to have some dummy zero sized IBs for the MM engines which 
otherwise couldn't execute a fence command.

It shouldn't matter for modern firmware/hardware, but you could actually 
silently break somewhere else with this, so better not do this.

Sorry should have mentioned that directly,
Christian.


Anyway I can modify the patch to do this.

Thanks,
Pierre-Eric

>
> Christian.
>
>>
>> Signed-off-by: Pierre-Eric Pelloux-Prayer 
>> 
>> ---
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 5 +
>>   1 file changed, 5 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c 
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
>> index 60655834d649..aa163e679f1f 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
>> @@ -227,6 +227,11 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, 
>> unsigned num_ibs,
>>   !amdgpu_sriov_vf(adev)) /* for SRIOV preemption, Preamble CE 
>> ib must be inserted anyway */
>>   continue;
>>   +if (ib->length_dw == 0) {
>> +/* On Navi gmc_v10_0_flush_gpu_tlb emits 0 sized IB */
>> +continue;
>> +}
>> +
>>   amdgpu_ring_emit_ib(ring, job, ib, status);
>>   status &= ~AMDGPU_HAVE_CTX_SWITCH;
>>   }
>

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Re: [PATCH] drm/amdgpu: do not execute 0-sized IBs

2019-10-03 Thread Pelloux-prayer, Pierre-eric 

On 03/10/2019 10:09, Christian König wrote:
> Am 03.10.19 um 10:03 schrieb Pelloux-prayer, Pierre-eric:
>> This can be safely skipped entirely.
>> This seems to help with https://bugs.freedesktop.org/show_bug.cgi?id=111481.
> 
> NAK, please instead fix gmc_v10_0_flush_gpu_tlb to include at least some NOP 
> in the submitted IBs.

Is there any interest in executing an empty (or only filled with NOPs) IB?

Anyway I can modify the patch to do this.

Thanks,
Pierre-Eric

> 
> Christian.
> 
>>
>> Signed-off-by: Pierre-Eric Pelloux-Prayer 
>> 
>> ---
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 5 +
>>   1 file changed, 5 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c 
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
>> index 60655834d649..aa163e679f1f 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
>> @@ -227,6 +227,11 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, 
>> unsigned num_ibs,
>>   !amdgpu_sriov_vf(adev)) /* for SRIOV preemption, Preamble CE 
>> ib must be inserted anyway */
>>   continue;
>>   +    if (ib->length_dw == 0) {
>> +    /* On Navi gmc_v10_0_flush_gpu_tlb emits 0 sized IB */
>> +    continue;
>> +    }
>> +
>>   amdgpu_ring_emit_ib(ring, job, ib, status);
>>   status &= ~AMDGPU_HAVE_CTX_SWITCH;
>>   }
> 
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[PATCH][drm-next] drm/amd/display: fix spelling mistake AUTHENICATED -> AUTHENTICATED

2019-10-03 Thread Colin King 
From: Colin Ian King 

There is a spelling mistake in the macros H1_A45_AUTHENICATED and
D1_A4_AUTHENICATED, fix these by adding the missing T.

Signed-off-by: Colin Ian King 
---
 drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h  |  4 ++--
 .../drm/amd/display/modules/hdcp/hdcp1_execution.c   |  4 ++--
 .../drm/amd/display/modules/hdcp/hdcp1_transition.c  | 12 ++--
 drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c  |  8 
 4 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h 
b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
index 402bb7999093..5664bc0b5bd0 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
@@ -176,7 +176,7 @@ enum mod_hdcp_hdcp1_state_id {
H1_A0_WAIT_FOR_ACTIVE_RX,
H1_A1_EXCHANGE_KSVS,
H1_A2_COMPUTATIONS_A3_VALIDATE_RX_A6_TEST_FOR_REPEATER,
-   H1_A45_AUTHENICATED,
+   H1_A45_AUTHENTICATED,
H1_A8_WAIT_FOR_READY,
H1_A9_READ_KSV_LIST,
HDCP1_STATE_END = H1_A9_READ_KSV_LIST
@@ -188,7 +188,7 @@ enum mod_hdcp_hdcp1_dp_state_id {
D1_A1_EXCHANGE_KSVS,
D1_A23_WAIT_FOR_R0_PRIME,
D1_A2_COMPUTATIONS_A3_VALIDATE_RX_A5_TEST_FOR_REPEATER,
-   D1_A4_AUTHENICATED,
+   D1_A4_AUTHENTICATED,
D1_A6_WAIT_FOR_READY,
D1_A7_READ_KSV_LIST,
HDCP1_DP_STATE_END = D1_A7_READ_KSV_LIST,
diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c 
b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c
index 9e7302eac299..3db4a7da414f 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c
@@ -476,7 +476,7 @@ enum mod_hdcp_status mod_hdcp_hdcp1_execution(struct 
mod_hdcp *hdcp,
status = computations_validate_rx_test_for_repeater(hdcp,
event_ctx, input);
break;
-   case H1_A45_AUTHENICATED:
+   case H1_A45_AUTHENTICATED:
status = authenticated(hdcp, event_ctx, input);
break;
case H1_A8_WAIT_FOR_READY:
@@ -513,7 +513,7 @@ extern enum mod_hdcp_status 
mod_hdcp_hdcp1_dp_execution(struct mod_hdcp *hdcp,
status = computations_validate_rx_test_for_repeater(
hdcp, event_ctx, input);
break;
-   case D1_A4_AUTHENICATED:
+   case D1_A4_AUTHENTICATED:
status = authenticated_dp(hdcp, event_ctx, input);
break;
case D1_A6_WAIT_FOR_READY:
diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_transition.c 
b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_transition.c
index 1d187809b709..136b8011ff3f 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_transition.c
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_transition.c
@@ -81,11 +81,11 @@ enum mod_hdcp_status mod_hdcp_hdcp1_transition(struct 
mod_hdcp *hdcp,
set_state_id(hdcp, output, H1_A8_WAIT_FOR_READY);
} else {
callback_in_ms(0, output);
-   set_state_id(hdcp, output, H1_A45_AUTHENICATED);
+   set_state_id(hdcp, output, H1_A45_AUTHENTICATED);
HDCP_FULL_DDC_TRACE(hdcp);
}
break;
-   case H1_A45_AUTHENICATED:
+   case H1_A45_AUTHENTICATED:
if (input->link_maintenance != PASS) {
/* 1A-07: consider invalid ri' a failure */
/* 1A-07a: consider read ri' not returned a failure */
@@ -129,7 +129,7 @@ enum mod_hdcp_status mod_hdcp_hdcp1_transition(struct 
mod_hdcp *hdcp,
break;
}
callback_in_ms(0, output);
-   set_state_id(hdcp, output, H1_A45_AUTHENICATED);
+   set_state_id(hdcp, output, H1_A45_AUTHENTICATED);
HDCP_FULL_DDC_TRACE(hdcp);
break;
default:
@@ -224,11 +224,11 @@ enum mod_hdcp_status mod_hdcp_hdcp1_dp_transition(struct 
mod_hdcp *hdcp,
set_watchdog_in_ms(hdcp, 5000, output);
set_state_id(hdcp, output, D1_A6_WAIT_FOR_READY);
} else {
-   set_state_id(hdcp, output, D1_A4_AUTHENICATED);
+   set_state_id(hdcp, output, D1_A4_AUTHENTICATED);
HDCP_FULL_DDC_TRACE(hdcp);
}
break;
-   case D1_A4_AUTHENICATED:
+   case D1_A4_AUTHENTICATED:
if (input->link_integiry_check != PASS ||
input->reauth_request_check != PASS) {
/* 1A-07: restart hdcp on a link integrity failure */
@@ -295,7 +295,7 @@ enum mod_hdcp_status mod_hdcp_hdcp1_dp_transition(struct 
mod_hdcp *hdcp,
fail_and_restart_in_ms(0, ,

Re: [PATCH] drm/amdgpu: do not execute 0-sized IBs

2019-10-03 Thread Christian König 

Am 03.10.19 um 10:03 schrieb Pelloux-prayer, Pierre-eric:

This can be safely skipped entirely.
This seems to help with https://bugs.freedesktop.org/show_bug.cgi?id=111481.


NAK, please instead fix gmc_v10_0_flush_gpu_tlb to include at least some 
NOP in the submitted IBs.


Christian.



Signed-off-by: Pierre-Eric Pelloux-Prayer 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 5 +
  1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index 60655834d649..aa163e679f1f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -227,6 +227,11 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned 
num_ibs,
!amdgpu_sriov_vf(adev)) /* for SRIOV preemption, Preamble 
CE ib must be inserted anyway */
continue;
  
+		if (ib->length_dw == 0) {

+   /* On Navi gmc_v10_0_flush_gpu_tlb emits 0 sized IB */
+   continue;
+   }
+
amdgpu_ring_emit_ib(ring, job, ib, status);
status &= ~AMDGPU_HAVE_CTX_SWITCH;
}


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[PATCH] drm/amdgpu: do not execute 0-sized IBs

2019-10-03 Thread Pelloux-prayer, Pierre-eric 
This can be safely skipped entirely.
This seems to help with https://bugs.freedesktop.org/show_bug.cgi?id=111481.

Signed-off-by: Pierre-Eric Pelloux-Prayer 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index 60655834d649..aa163e679f1f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -227,6 +227,11 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned 
num_ibs,
!amdgpu_sriov_vf(adev)) /* for SRIOV preemption, Preamble 
CE ib must be inserted anyway */
continue;
 
+   if (ib->length_dw == 0) {
+   /* On Navi gmc_v10_0_flush_gpu_tlb emits 0 sized IB */
+   continue;
+   }
+
amdgpu_ring_emit_ib(ring, job, ib, status);
status &= ~AMDGPU_HAVE_CTX_SWITCH;
}
-- 
2.23.0.rc1

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Re: [PATCH] drm/drm_edid: correct VIC and HDMI_VIC under HDMI 2.0

2019-10-03 Thread Lin, Wayne 



From: Ville Syrjälä 
Sent: Wednesday, October 2, 2019 19:58
To: Lin, Wayne 
Cc: dri-de...@lists.freedesktop.org ; 
amd-gfx@lists.freedesktop.org ; Li, Sun peng 
(Leo) ; Kazlauskas, Nicholas 
Subject: Re: [PATCH] drm/drm_edid: correct VIC and HDMI_VIC under HDMI 2.0

On Tue, Sep 24, 2019 at 01:26:21PM +0800, Wayne Lin wrote:
> In HDMI 1.4 defines 4k modes without specific aspect ratio.
> However, in HDMI 2.0, adds aspect ratio attribute to distinguish different
> 4k modes.
>
> According to Appendix E of HDMI 2.0 spec, source should use VSIF to
> indicate VIC mode only when the mode is one defined in HDMI 1.4b 4K modes.
> Otherwise, use AVI infoframes to convey VIC.
>
> eg: VIC_103 should use AVI infoframes and VIC_93 use VSIF
>
> When the sink is HDMI 2.0, current code in
> drm_hdmi_avi_infoframe_from_display_mode will also force mode VIC_103 to
> have VIC value 0. This violates the spec and needs to be corrected.

> Where is that being done? We only set the AVI VIC to zero if we're going
> to use the HDMI VIC instead.

Appreciate for your time and apologize for not explaining it clearly.
Current code in drm_hdmi_avi_infoframe_from_display_mode() will call
drm_match_hdmi_mode() to set up vendor_if_vic. By checking
drm_valid_hdmi_vic(vendor_if_vic) to see if the vic info should be conveyed by 
avi
or not.

But in drm_match_hdmi_mode(), code doesn't enable match_flags with
DRM_MODE_MATCH_ASPECT_RATIO. I think it's due to HDMI1.4b doesn't specify
4K mode conveyed by HDMI VIC with particular aspect ratio. But in Appendix E of
HDMI 2.0 spec, it specify only 4k modes with particular aspect ratio should use 
VSIF to convey.
Hence, when the sink support HDMI 2.0 and set the mode to be VIC_103, calling
drm_match_hdmi_mode(mode) will return vendor_if_vic = 3 (VIC_93 and VIC_103 are 
having
the same timing but different aspect ratio). Thereafter will set the  
frame->video_code to 0.
However, VIC_103 should use AVI VIC according to HDMI 2.0 spec (only VIC: 93, 
94, 95 &
98 should use VSIF).

This patch try to revise that, when the sink support HDMI 2.0, 
drm_match_hdmi_mode()
should also take aspect ratio into consideration.
But for easy reading, I add another function "drm_match_hdmi_1_4_mode" to do so.

> The same situation occurs in drm_hdmi_vendor_infoframe_from_display_mode
> and should set HDMI_VIC when the mode is one defined in HDMI 1.4b 4K
> modes.

> Yes, and we do that. "vic = drm_match_hdmi_mode(mode);"

> Apart from adding the aspect ratios I don't really understand what
> you're trying to achieve here.

For HDMI 2.0 sink, drm_match_hdmi_mode() should also take aspect ratio into 
consideration.
Once again, very appreciate for your time.

> ---
>  drivers/gpu/drm/drm_edid.c | 95 --
>  1 file changed, 92 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index 649cfd8b4200..0fea9bf4ec67 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -1306,6 +1306,37 @@ static const struct drm_display_mode edid_4k_modes[] = 
> {
>  .vrefresh = 24, },
>  };
>
> +/*
> + * 4k modes of HDMI 1.4 defined in HDMI 2.0. Index using the VIC.
> + */
> +static const struct drm_display_mode hdmi_1_4_edid_4k_modes[] = {
> + /* 0 - dummy, VICs start at 1 */
> + { },
> + /* 1 - 3840x2160@30Hz */
> + { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
> +3840, 4016, 4104, 4400, 0,
> +2160, 2168, 2178, 2250, 0,
> +DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
> +   .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
> + /* 2 - 3840x2160@25Hz */
> + { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
> +3840, 4896, 4984, 5280, 0,
> +2160, 2168, 2178, 2250, 0,
> +DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
> +   .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
> + /* 3 - 3840x2160@24Hz */
> + { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
> +3840, 5116, 5204, 5500, 0,
> +2160, 2168, 2178, 2250, 0,
> +DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
> +   .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
> + /* 4 - 4096x2160@24Hz (SMPTE) */
> + { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
> +4096, 5116, 5204, 5500, 0,
> +2160, 2168, 2178, 2250, 0,
> +DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
> +   .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, 
> },
> +};
>  /*** DDC fetch and block validation ***/
>
>  static const u8 edid_header[] = {
> @@ -3061,6 +3092,19 @@ hdmi_mode_alternate_clock(const struct 
> drm_display_mode *hdmi_mode)
>return cea_mode_alternate_clock(hdmi_mode);
>  }
>
> +/*
> + * Calculate the alternate clock for