Re: [PATCH] drm/amdgpu: Use the ALIGN() macro
On Fri, Oct 4, 2019 at 7:29 PM Tuikov, Luben wrote: > > On 2019-10-04 3:16 a.m., Christian König wrote: > > Am 04.10.19 um 01:39 schrieb Tuikov, Luben: > >> Use the ALIGN() macro to set "num_dw" to a > >> multiple of 8, i.e. lower 3 bits cleared. > >> > >> Signed-off-by: Luben Tuikov > > > > Reviewed-by: Christian König > > Hi Christian, > > No ACK? > > I've been running this version of the driver and no problems. > You can go ahead and commit. You have a reviewed-by. Alex > Regards, > Luben > > > > >> --- > >> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 11 ++- > >> 1 file changed, 2 insertions(+), 9 deletions(-) > >> > >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c > >> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c > >> index 68c541e11189..73c628bc6a5b 100644 > >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c > >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c > >> @@ -1923,10 +1923,7 @@ static int amdgpu_map_buffer(struct > >> ttm_buffer_object *bo, > >> *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE * > >> AMDGPU_GPU_PAGE_SIZE; > >> > >> -num_dw = adev->mman.buffer_funcs->copy_num_dw; > >> -while (num_dw & 0x7) > >> -num_dw++; > >> - > >> +num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8); > >> num_bytes = num_pages * 8; > >> > >> r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes, ); > >> @@ -1986,11 +1983,7 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, > >> uint64_t src_offset, > >> > >> max_bytes = adev->mman.buffer_funcs->copy_max_bytes; > >> num_loops = DIV_ROUND_UP(byte_count, max_bytes); > >> -num_dw = num_loops * adev->mman.buffer_funcs->copy_num_dw; > >> - > >> -/* for IB padding */ > >> -while (num_dw & 0x7) > >> -num_dw++; > >> +num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8); > >> > >> r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, ); > >> if (r) > > > > ___ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 5/5] drm/amd/display: Remove set but not used variables 'pp_smu', 'old_pipe'
Fixes gcc '-Wunused-but-set-variable' warning:
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c: In function
dce110_enable_audio_stream:
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c:949:23: warning:
variable pp_smu set but not used [-Wunused-but-set-variable]
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c: In function
dce110_disable_audio_stream:
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c:983:23: warning:
variable pp_smu set but not used [-Wunused-but-set-variable]
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c: In function
dce110_program_front_end_for_pipe:
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c:2429:19: warning:
variable old_pipe set but not used [-Wunused-but-set-variable]
'pp_smu' is not used since commit 170a2398d2d8 ("drm/amd/display:
make clk_mgr call enable_pme_wa")
'old_pipe' is not used since commit 65d38262b3e8 ("drm/amd/display:
fbc state could not reach while enable fbc")
Reported-by: Hulk Robot
Signed-off-by: zhengbin
---
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 12
1 file changed, 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 01a924b..f8c1b4f 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -944,7 +944,6 @@ void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx)
{
/* notify audio driver for audio modes of monitor */
struct dc *core_dc;
- struct pp_smu_funcs *pp_smu = NULL;
struct clk_mgr *clk_mgr;
unsigned int i, num_audio = 1;
@@ -957,9 +956,6 @@ void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx)
if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled
== true)
return;
- if (core_dc->res_pool->pp_smu)
- pp_smu = core_dc->res_pool->pp_smu;
-
if (pipe_ctx->stream_res.audio) {
for (i = 0; i < MAX_PIPES; i++) {
/*current_state not updated yet*/
@@ -984,7 +980,6 @@ void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx)
void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx)
{
struct dc *dc;
- struct pp_smu_funcs *pp_smu = NULL;
struct clk_mgr *clk_mgr;
if (!pipe_ctx || !pipe_ctx->stream)
@@ -1001,9 +996,6 @@ void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx)
if (pipe_ctx->stream_res.audio) {
pipe_ctx->stream_res.audio->enabled = false;
- if (dc->res_pool->pp_smu)
- pp_smu = dc->res_pool->pp_smu;
-
if (dc_is_dp_signal(pipe_ctx->stream->signal))
pipe_ctx->stream_res.stream_enc->funcs->dp_audio_disable(
pipe_ctx->stream_res.stream_enc);
@@ -2464,7 +2456,6 @@ static void dce110_program_front_end_for_pipe(
struct dc *dc, struct pipe_ctx *pipe_ctx)
{
struct mem_input *mi = pipe_ctx->plane_res.mi;
- struct pipe_ctx *old_pipe = NULL;
struct dc_plane_state *plane_state = pipe_ctx->plane_state;
struct xfm_grph_csc_adjustment adjust;
struct out_csc_color_matrix tbl_entry;
@@ -2472,9 +2463,6 @@ static void dce110_program_front_end_for_pipe(
DC_LOGGER_INIT();
memset(_entry, 0, sizeof(tbl_entry));
- if (dc->current_state)
- old_pipe =
>current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
-
memset(, 0, sizeof(adjust));
adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
--
2.7.4
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[PATCH 3/5] drm/amd/display: Remove set but not used variables 'h_ratio_chroma', 'v_ratio_chroma'
Fixes gcc '-Wunused-but-set-variable' warning:
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c: In function
dwb_program_horz_scalar:
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c:725:11: warning: variable
h_ratio_chroma set but not used [-Wunused-but-set-variable]
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c: In function
dwb_program_vert_scalar:
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c:806:11: warning: variable
v_ratio_chroma set but not used [-Wunused-but-set-variable]
They are not used since commit 345429a67c48 ("drm/amd/display:
Add DCN2 DWB")
Reported-by: Hulk Robot
Signed-off-by: zhengbin
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c
index cd8bc92..880954a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c
@@ -722,7 +722,6 @@ bool dwb_program_horz_scalar(struct dcn20_dwbc *dwbc20,
struct scaling_taps num_taps)
{
uint32_t h_ratio_luma = 1;
- uint32_t h_ratio_chroma = 1;
uint32_t h_taps_luma = num_taps.h_taps;
uint32_t h_taps_chroma = num_taps.h_taps_c;
int32_t h_init_phase_luma = 0;
@@ -747,7 +746,6 @@ bool dwb_program_horz_scalar(struct dcn20_dwbc *dwbc20,
h_ratio_luma = -1;
else
h_ratio_luma = dc_fixpt_u3d19(tmp_h_ratio_luma) << 5;
- h_ratio_chroma = h_ratio_luma * 2;
/*Program ratio*/
REG_UPDATE(WBSCL_HORZ_FILTER_SCALE_RATIO, WBSCL_H_SCALE_RATIO,
h_ratio_luma);
@@ -803,7 +801,6 @@ bool dwb_program_vert_scalar(struct dcn20_dwbc *dwbc20,
enum dwb_subsample_position subsample_position)
{
uint32_t v_ratio_luma = 1;
- uint32_t v_ratio_chroma = 1;
uint32_t v_taps_luma = num_taps.v_taps;
uint32_t v_taps_chroma = num_taps.v_taps_c;
int32_t v_init_phase_luma = 0;
@@ -827,7 +824,6 @@ bool dwb_program_vert_scalar(struct dcn20_dwbc *dwbc20,
v_ratio_luma = -1;
else
v_ratio_luma = dc_fixpt_u3d19(tmp_v_ratio_luma) << 5;
- v_ratio_chroma = v_ratio_luma * 2;
/*Program ratio*/
REG_UPDATE(WBSCL_VERT_FILTER_SCALE_RATIO, WBSCL_V_SCALE_RATIO,
v_ratio_luma);
--
2.7.4
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[PATCH 4/5] drm/amd/display: Remove set but not used variable 'pixel_width'
Fixes gcc '-Wunused-but-set-variable' warning:
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c: In function
dpp2_get_optimal_number_of_taps:
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c:359:11: warning: variable
pixel_width set but not used [-Wunused-but-set-variable]
It is not used since commit f7de96ee8b5f ("drm/amd/display:
Add DCN2 DPP")
Reported-by: Hulk Robot
Signed-off-by: zhengbin
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c
index 2f5aade..ae85343 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c
@@ -376,13 +376,6 @@ bool dpp2_get_optimal_number_of_taps(
struct scaler_data *scl_data,
const struct scaling_taps *in_taps)
{
- uint32_t pixel_width;
-
- if (scl_data->viewport.width > scl_data->recout.width)
- pixel_width = scl_data->recout.width;
- else
- pixel_width = scl_data->viewport.width;
-
/* Some ASICs does not support FP16 scaling, so we reject modes
require this*/
if (scl_data->viewport.width != scl_data->h_active &&
scl_data->viewport.height != scl_data->v_active &&
--
2.7.4
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[PATCH 2/5] drm/amd/display: Remove set but not used variable 'source_bpp'
Fixes gcc '-Wunused-but-set-variable' warning:
drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c: In function calc_rc_params:
drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c:180:6: warning: variable
source_bpp set but not used [-Wunused-but-set-variable]
It is not used since commit 97bda0322b8a ("drm/amd/display:
Add DSC support for Navi (v2)")
Reported-by: Hulk Robot
Signed-off-by: zhengbin
---
drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c
b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c
index ca51e83..76c4b12 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c
@@ -177,7 +177,6 @@ void calc_rc_params(struct rc_params *rc, enum colour_mode
cm, enum bits_per_com
{
float bpp_group;
float initial_xmit_delay_factor;
- int source_bpp;
int padding_pixels;
int i;
@@ -217,8 +216,6 @@ void calc_rc_params(struct rc_params *rc, enum colour_mode
cm, enum bits_per_com
rc->initial_xmit_delay++;
}
- source_bpp = MODE_SELECT(bpc * 3, bpc * 2, bpc * 1.5);
-
rc->flatness_min_qp = ((bpc == BPC_8) ? (3) : ((bpc == BPC_10) ?
(7) : (11))) - ((minor_version == 1 && cm == CM_444) ? 1 : 0);
rc->flatness_max_qp = ((bpc == BPC_8) ? (12) : ((bpc == BPC_10) ?
(16) : (20))) - ((minor_version == 1 && cm == CM_444) ? 1 : 0);
rc->flatness_det_thresh = 2 << (bpc - 8);
--
2.7.4
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[PATCH 1/5] drm/amd/display: Make function wait_for_alt_mode static
Fix sparse warnings:
drivers/gpu/drm/amd/display/dc/core/dc_link.c:687:6: warning: symbol
'wait_for_alt_mode' was not declared. Should it be static?
Reported-by: Hulk Robot
Signed-off-by: zhengbin
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 33d4cc4..152c564 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -685,7 +685,7 @@ static bool is_same_edid(struct dc_edid *old_edid, struct
dc_edid *new_edid)
return (memcmp(old_edid->raw_edid, new_edid->raw_edid,
new_edid->length) == 0);
}
-bool wait_for_alt_mode(struct dc_link *link)
+static bool wait_for_alt_mode(struct dc_link *link)
{
/**
--
2.7.4
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[PATCH 0/5] drm/amd/display: some fixes for gcc warning
zhengbin (5): drm/amd/display: Make function wait_for_alt_mode static drm/amd/display: Remove set but not used variable 'source_bpp' drm/amd/display: Remove set but not used variables 'h_ratio_chroma','v_ratio_chroma' drm/amd/display: Remove set but not used variable 'pixel_width' drm/amd/display: Remove set but not used variables 'pp_smu','old_pipe' drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 +- drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 12 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c| 7 --- drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c| 4 drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c| 3 --- 5 files changed, 1 insertion(+), 27 deletions(-) -- 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu: Use the ALIGN() macro
On 2019-10-04 3:16 a.m., Christian König wrote: > Am 04.10.19 um 01:39 schrieb Tuikov, Luben: >> Use the ALIGN() macro to set "num_dw" to a >> multiple of 8, i.e. lower 3 bits cleared. >> >> Signed-off-by: Luben Tuikov > > Reviewed-by: Christian König Hi Christian, No ACK? I've been running this version of the driver and no problems. Regards, Luben > >> --- >> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 11 ++- >> 1 file changed, 2 insertions(+), 9 deletions(-) >> >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c >> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c >> index 68c541e11189..73c628bc6a5b 100644 >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c >> @@ -1923,10 +1923,7 @@ static int amdgpu_map_buffer(struct ttm_buffer_object >> *bo, >> *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE * >> AMDGPU_GPU_PAGE_SIZE; >> >> -num_dw = adev->mman.buffer_funcs->copy_num_dw; >> -while (num_dw & 0x7) >> -num_dw++; >> - >> +num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8); >> num_bytes = num_pages * 8; >> >> r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes, ); >> @@ -1986,11 +1983,7 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, >> uint64_t src_offset, >> >> max_bytes = adev->mman.buffer_funcs->copy_max_bytes; >> num_loops = DIV_ROUND_UP(byte_count, max_bytes); >> -num_dw = num_loops * adev->mman.buffer_funcs->copy_num_dw; >> - >> -/* for IB padding */ >> -while (num_dw & 0x7) >> -num_dw++; >> +num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8); >> >> r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, ); >> if (r) > ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH] drm/amd/include: add aux timeout vega registers
Looks good to me. Reviewed-by: Zhan Liu -Original Message- From: amd-gfx On Behalf Of roman...@amd.com Sent: 2019/October/04, Friday 3:45 PM To: amd-gfx@lists.freedesktop.org Cc: Berthe, Abdoulaye ; Liu, Zhan ; Li, Roman ; Wentland, Harry ; Deucher, Alexander ; Lakha, Bhawanpreet Subject: [PATCH] drm/amd/include: add aux timeout vega registers From: Roman Li DC needs them to support configurable aux timeout on vega Signed-off-by: Roman Li --- drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h index bcd190a..832d7b2 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h @@ -35549,7 +35549,11 @@ #define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x7000L //DP_AUX0_AUX_DPHY_RX_CONTROL1 #define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0 +#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT 0x8 +#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT 0xf #define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x00FFL +#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK 0x7F00L +#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK 0x00018000L //DP_AUX0_AUX_DPHY_TX_STATUS #define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0 #define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4 -- 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu: Report vram vendor with sysfs
On Fri, Oct 4, 2019 at 3:01 PM Messinger, Ori wrote:
>
> The vram vendor can be found as a separate sysfs file at:
> /sys/class/drm/card[X]/device/mem_info_vram_vendor
> The vram vendor is displayed as a string value.
>
> Change-Id: Iaa3ccf3f483ee6536281fe72ba241a6e0d43
> Signed-off-by: Ori Messinger
> ---
> .../gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | 63 ++-
> .../gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h | 5 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 43 +
> drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c| 5 +-
> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 5 +-
> 5 files changed, 114 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
> index 19913c39588b..59009726494b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
> @@ -169,8 +169,11 @@ static int convert_atom_mem_type_to_vram_type(struct
> amdgpu_device *adev,
> return vram_type;
> }
>
> -int amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
> - int *vram_width, int *vram_type)
> +
> +int
> +amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
> + int *vram_width, int *vram_type,
> + int *vram_vendor)
> {
> struct amdgpu_mode_info *mode_info = >mode_info;
> int index, i = 0;
> @@ -180,6 +183,7 @@ int amdgpu_atomfirmware_get_vram_info(struct
> amdgpu_device *adev,
> union vram_module *vram_module;
> u8 frev, crev;
> u8 mem_type;
> + u8 mem_vendor;
> u32 mem_channel_number;
> u32 mem_channel_width;
> u32 module_id;
> @@ -231,6 +235,9 @@ int amdgpu_atomfirmware_get_vram_info(struct
> amdgpu_device *adev,
> mem_channel_width =
> vram_module->v9.channel_width;
> if (vram_width)
> *vram_width = mem_channel_number * (1
> << mem_channel_width);
> + mem_vendor = vram_module->v9.vender_rev_id;
Don't you need to mask this? I think only the lower 4 bits are the vendor.
> + if (vram_vendor)
> + *vram_vendor = mem_vendor;
> break;
> case 4:
> if (module_id >
> vram_info->v24.vram_module_num)
> @@ -248,6 +255,9 @@ int amdgpu_atomfirmware_get_vram_info(struct
> amdgpu_device *adev,
> mem_channel_width =
> vram_module->v10.channel_width;
> if (vram_width)
> *vram_width = mem_channel_number * (1
> << mem_channel_width);
> + mem_vendor = vram_module->v10.vender_rev_id;
Same comment here.
> + if (vram_vendor)
> + *vram_vendor = mem_vendor;
> break;
> default:
> return -EINVAL;
> @@ -259,6 +269,55 @@ int amdgpu_atomfirmware_get_vram_info(struct
> amdgpu_device *adev,
> return 0;
> }
>
> +/*
> + * Return vram width from integrated system info table, if available,
> + * or 0 if not.
> + */
> +int amdgpu_atomfirmware_get_vram_width(struct amdgpu_device *adev)
> +{
> + int vram_width = 0, vram_type = 0, vram_vendor = 0;
> + int r = amdgpu_atomfirmware_get_vram_info(adev,
> + _width, _type, _vendor);
> +
> + if (r)
> + return 0;
> +
> + return vram_width;
> +}
> +
> +/*
> + * Return vram type from either integrated system info table
> + * or umc info table, if available, or 0 (TYPE_UNKNOWN) if not
> + */
> +int amdgpu_atomfirmware_get_vram_type(struct amdgpu_device *adev)
> +{
> + int vram_width = 0, vram_type = 0, vram_vendor = 0;
> + int r = amdgpu_atomfirmware_get_vram_info(adev,
> + _width, _type, _vendor);
> +
> + if (r)
> + return 0;
> +
> + return vram_type;
> +}
> +
> +/*
> + * Return vram vendor from either integrated system info table
> + * or umc info table, if available, or 0 (TYPE_UNKNOWN) if not
> + */
> +int amdgpu_atomfirmware_get_vram_vendor(struct amdgpu_device *adev)
> +{
> + int vram_width = 0, vram_type = 0, vram_vendor = 0;
> + int r = amdgpu_atomfirmware_get_vram_info(adev,
> + _width, _type, _vendor);
> +
> + if (r)
> + return 0;
> +
> + return vram_vendor;
> +
> +}
They aren't used. Drop them. See my comment below.
> +
> /*
> * Return true if vbios enabled ecc by default, if umc info table is
> available
> * or false if ecc is not enabled or umc info table is not available
> diff --git
[PATCH] drm/amd/include: add aux timeout vega registers
From: Roman Li DC needs them to support configurable aux timeout on vega Signed-off-by: Roman Li --- drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h index bcd190a..832d7b2 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h @@ -35549,7 +35549,11 @@ #define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x7000L //DP_AUX0_AUX_DPHY_RX_CONTROL1 #define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0 +#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT 0x8 +#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT 0xf #define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x00FFL +#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK 0x7F00L +#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK 0x00018000L //DP_AUX0_AUX_DPHY_TX_STATUS #define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0 #define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4 -- 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: Report vram vendor with sysfs
The vram vendor can be found as a separate sysfs file at:
/sys/class/drm/card[X]/device/mem_info_vram_vendor
The vram vendor is displayed as a string value.
Change-Id: Iaa3ccf3f483ee6536281fe72ba241a6e0d43
Signed-off-by: Ori Messinger
---
.../gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | 63 ++-
.../gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h | 5 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 43 +
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c| 5 +-
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 5 +-
5 files changed, 114 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
index 19913c39588b..59009726494b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
@@ -169,8 +169,11 @@ static int convert_atom_mem_type_to_vram_type(struct
amdgpu_device *adev,
return vram_type;
}
-int amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
- int *vram_width, int *vram_type)
+
+int
+amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
+ int *vram_width, int *vram_type,
+ int *vram_vendor)
{
struct amdgpu_mode_info *mode_info = >mode_info;
int index, i = 0;
@@ -180,6 +183,7 @@ int amdgpu_atomfirmware_get_vram_info(struct amdgpu_device
*adev,
union vram_module *vram_module;
u8 frev, crev;
u8 mem_type;
+ u8 mem_vendor;
u32 mem_channel_number;
u32 mem_channel_width;
u32 module_id;
@@ -231,6 +235,9 @@ int amdgpu_atomfirmware_get_vram_info(struct amdgpu_device
*adev,
mem_channel_width =
vram_module->v9.channel_width;
if (vram_width)
*vram_width = mem_channel_number * (1
<< mem_channel_width);
+ mem_vendor = vram_module->v9.vender_rev_id;
+ if (vram_vendor)
+ *vram_vendor = mem_vendor;
break;
case 4:
if (module_id > vram_info->v24.vram_module_num)
@@ -248,6 +255,9 @@ int amdgpu_atomfirmware_get_vram_info(struct amdgpu_device
*adev,
mem_channel_width =
vram_module->v10.channel_width;
if (vram_width)
*vram_width = mem_channel_number * (1
<< mem_channel_width);
+ mem_vendor = vram_module->v10.vender_rev_id;
+ if (vram_vendor)
+ *vram_vendor = mem_vendor;
break;
default:
return -EINVAL;
@@ -259,6 +269,55 @@ int amdgpu_atomfirmware_get_vram_info(struct amdgpu_device
*adev,
return 0;
}
+/*
+ * Return vram width from integrated system info table, if available,
+ * or 0 if not.
+ */
+int amdgpu_atomfirmware_get_vram_width(struct amdgpu_device *adev)
+{
+ int vram_width = 0, vram_type = 0, vram_vendor = 0;
+ int r = amdgpu_atomfirmware_get_vram_info(adev,
+ _width, _type, _vendor);
+
+ if (r)
+ return 0;
+
+ return vram_width;
+}
+
+/*
+ * Return vram type from either integrated system info table
+ * or umc info table, if available, or 0 (TYPE_UNKNOWN) if not
+ */
+int amdgpu_atomfirmware_get_vram_type(struct amdgpu_device *adev)
+{
+ int vram_width = 0, vram_type = 0, vram_vendor = 0;
+ int r = amdgpu_atomfirmware_get_vram_info(adev,
+ _width, _type, _vendor);
+
+ if (r)
+ return 0;
+
+ return vram_type;
+}
+
+/*
+ * Return vram vendor from either integrated system info table
+ * or umc info table, if available, or 0 (TYPE_UNKNOWN) if not
+ */
+int amdgpu_atomfirmware_get_vram_vendor(struct amdgpu_device *adev)
+{
+ int vram_width = 0, vram_type = 0, vram_vendor = 0;
+ int r = amdgpu_atomfirmware_get_vram_info(adev,
+ _width, _type, _vendor);
+
+ if (r)
+ return 0;
+
+ return vram_vendor;
+
+}
+
/*
* Return true if vbios enabled ecc by default, if umc info table is available
* or false if ecc is not enabled or umc info table is not available
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h
index 82819f03e444..738e538ee26c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h
@@ -30,7 +30,10 @@ bool amdgpu_atomfirmware_gpu_supports_virtualization(struct
amdgpu_device *adev)
void amdgpu_atomfirmware_scratch_regs_init(struct amdgpu_device *adev);
int
Re: [PATCH] drm/amdgpu: move amdgpu_device_get_job_timeout_settings
Reviewed-by: Andrey Grodzovsky
Andrey
On 10/4/19 2:38 PM, Alex Deucher wrote:
> It's only used in amdgpu_device.c and the naming also
> reflects that. Move it there.
>
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h| 4 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 64 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c| 67 --
> 3 files changed, 67 insertions(+), 68 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 79ea620aac04..f321dc2751e4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -107,6 +107,8 @@ struct amdgpu_mgpu_info
> uint32_tnum_apu;
> };
>
> +#define AMDGPU_MAX_TIMEOUT_PARAM_LENTH 256
> +
> /*
>* Modules parameters.
>*/
> @@ -123,6 +125,7 @@ extern int amdgpu_disp_priority;
> extern int amdgpu_hw_i2c;
> extern int amdgpu_pcie_gen2;
> extern int amdgpu_msi;
> +extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENTH];
> extern int amdgpu_dpm;
> extern int amdgpu_fw_load_type;
> extern int amdgpu_aspm;
> @@ -427,7 +430,6 @@ struct amdgpu_fpriv {
> };
>
> int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv);
> -int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev);
>
> int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
> unsigned size, struct amdgpu_ib *ib);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index ba7d1fa58c5b..660ce71e1ea1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -2579,6 +2579,70 @@ static void amdgpu_device_xgmi_reset_func(struct
> work_struct *__work)
>adev->asic_reset_res, adev->ddev->unique);
> }
>
> +static int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev)
> +{
> + char *input = amdgpu_lockup_timeout;
> + char *timeout_setting = NULL;
> + int index = 0;
> + long timeout;
> + int ret = 0;
> +
> + /*
> + * By default timeout for non compute jobs is 1.
> + * And there is no timeout enforced on compute jobs.
> + * In SR-IOV or passthrough mode, timeout for compute
> + * jobs are 1 by default.
> + */
> + adev->gfx_timeout = msecs_to_jiffies(1);
> + adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout;
> + if (amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev))
> + adev->compute_timeout = adev->gfx_timeout;
> + else
> + adev->compute_timeout = MAX_SCHEDULE_TIMEOUT;
> +
> + if (strnlen(input, AMDGPU_MAX_TIMEOUT_PARAM_LENTH)) {
> + while ((timeout_setting = strsep(, ",")) &&
> + strnlen(timeout_setting,
> AMDGPU_MAX_TIMEOUT_PARAM_LENTH)) {
> + ret = kstrtol(timeout_setting, 0, );
> + if (ret)
> + return ret;
> +
> + if (timeout == 0) {
> + index++;
> + continue;
> + } else if (timeout < 0) {
> + timeout = MAX_SCHEDULE_TIMEOUT;
> + } else {
> + timeout = msecs_to_jiffies(timeout);
> + }
> +
> + switch (index++) {
> + case 0:
> + adev->gfx_timeout = timeout;
> + break;
> + case 1:
> + adev->compute_timeout = timeout;
> + break;
> + case 2:
> + adev->sdma_timeout = timeout;
> + break;
> + case 3:
> + adev->video_timeout = timeout;
> + break;
> + default:
> + break;
> + }
> + }
> + /*
> + * There is only one value specified and
> + * it should apply to all non-compute jobs.
> + */
> + if (index == 1)
> + adev->sdma_timeout = adev->video_timeout =
> adev->gfx_timeout;
> + }
> +
> + return ret;
> +}
>
> /**
>* amdgpu_device_init - initialize the driver
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index 5edf74b5c860..bfb4504fa195 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -88,8 +88,6 @@
> #define KMS_DRIVER_MINOR35
> #define KMS_DRIVER_PATCHLEVEL 0
>
> -#define AMDGPU_MAX_TIMEOUT_PARAM_LENTH 256
> -
> int
[PATCH] drm/amdgpu: move amdgpu_device_get_job_timeout_settings
It's only used in amdgpu_device.c and the naming also
reflects that. Move it there.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 4 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 64 +
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c| 67 --
3 files changed, 67 insertions(+), 68 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 79ea620aac04..f321dc2751e4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -107,6 +107,8 @@ struct amdgpu_mgpu_info
uint32_tnum_apu;
};
+#define AMDGPU_MAX_TIMEOUT_PARAM_LENTH 256
+
/*
* Modules parameters.
*/
@@ -123,6 +125,7 @@ extern int amdgpu_disp_priority;
extern int amdgpu_hw_i2c;
extern int amdgpu_pcie_gen2;
extern int amdgpu_msi;
+extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENTH];
extern int amdgpu_dpm;
extern int amdgpu_fw_load_type;
extern int amdgpu_aspm;
@@ -427,7 +430,6 @@ struct amdgpu_fpriv {
};
int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv);
-int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev);
int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
unsigned size, struct amdgpu_ib *ib);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index ba7d1fa58c5b..660ce71e1ea1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2579,6 +2579,70 @@ static void amdgpu_device_xgmi_reset_func(struct
work_struct *__work)
adev->asic_reset_res, adev->ddev->unique);
}
+static int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev)
+{
+ char *input = amdgpu_lockup_timeout;
+ char *timeout_setting = NULL;
+ int index = 0;
+ long timeout;
+ int ret = 0;
+
+ /*
+* By default timeout for non compute jobs is 1.
+* And there is no timeout enforced on compute jobs.
+* In SR-IOV or passthrough mode, timeout for compute
+* jobs are 1 by default.
+*/
+ adev->gfx_timeout = msecs_to_jiffies(1);
+ adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout;
+ if (amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev))
+ adev->compute_timeout = adev->gfx_timeout;
+ else
+ adev->compute_timeout = MAX_SCHEDULE_TIMEOUT;
+
+ if (strnlen(input, AMDGPU_MAX_TIMEOUT_PARAM_LENTH)) {
+ while ((timeout_setting = strsep(, ",")) &&
+ strnlen(timeout_setting,
AMDGPU_MAX_TIMEOUT_PARAM_LENTH)) {
+ ret = kstrtol(timeout_setting, 0, );
+ if (ret)
+ return ret;
+
+ if (timeout == 0) {
+ index++;
+ continue;
+ } else if (timeout < 0) {
+ timeout = MAX_SCHEDULE_TIMEOUT;
+ } else {
+ timeout = msecs_to_jiffies(timeout);
+ }
+
+ switch (index++) {
+ case 0:
+ adev->gfx_timeout = timeout;
+ break;
+ case 1:
+ adev->compute_timeout = timeout;
+ break;
+ case 2:
+ adev->sdma_timeout = timeout;
+ break;
+ case 3:
+ adev->video_timeout = timeout;
+ break;
+ default:
+ break;
+ }
+ }
+ /*
+* There is only one value specified and
+* it should apply to all non-compute jobs.
+*/
+ if (index == 1)
+ adev->sdma_timeout = adev->video_timeout =
adev->gfx_timeout;
+ }
+
+ return ret;
+}
/**
* amdgpu_device_init - initialize the driver
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 5edf74b5c860..bfb4504fa195 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -88,8 +88,6 @@
#define KMS_DRIVER_MINOR 35
#define KMS_DRIVER_PATCHLEVEL 0
-#define AMDGPU_MAX_TIMEOUT_PARAM_LENTH 256
-
int amdgpu_vram_limit = 0;
int amdgpu_vis_vram_limit = 0;
int amdgpu_gart_size = -1; /* auto */
@@ -1306,71 +1304,6 @@ int amdgpu_file_to_fpriv(struct file *filp, struct
amdgpu_fpriv **fpriv)
return 0;
}
-int amdgpu_device_get_job_timeout_settings(struct
Re: Issues with hibernation and resume
Martin wrote: Dear AMD Developers, I am building your amd-staging-drm-next kernels for more than 2 years now and patch this up with the official kernel patches and ubuntu's sauce patches: [1] One of the kernel users reports about hibernation problems since quite a while and he gives detailed feedback but I am not a hibernation user and had no time to bisect this. Could you please look into this issue and try to help: [2] Thanks for your great work about open-source linux graphics and keep it up! Many regards, Martin (M-bab) Hello, Martin and all, that user would be me :) Once I managed to reproduce the issue with the kernel currently in Debian / testing (5.2.0) I figured it would make sense to try and ask for help myself. I'll give a quick summary here then I can answer requests for more information in followups: * I have a Ryzen3 2200G on a Debian/testing system with a HDMI TV as display / audio sink. * until end of august, I was using Martin's 5.0.1 kernel, with xfce4 as desktop environment, and I could hibernate and resume multiple times with no issues * beginning roughly with 5.0.2, I started running into issues with poweroff at the end of hibernation (not happening) or corrupted graphics on resume, so I stuck with Martin's 5.0.1 * once I got back from my holidays at the end of september and upgraded the system, I always get a corrupted greenish display when resuming. If I use xfce4 I get this green screen right at first login (unless I clear the config), whereas with KDE the first login is usable but hibernate / resume gives a green screen (system is reachable via ssh, though) * I have checked and rechecked the HW and it seems to be fine, since I can dualboot Windows and it runs just ok. I'm not saying it is a kernel issue: I thought it was until the old trusty 5.0.1 no longer worked but it looks like some kind of weird interaction between kernel and (possibly) xserver and I'm hoping to find somehere who has already encountered a similar issue and could provide guidance. Thanks, Andrea. [1] https://github.com/M-Bab/linux-kernel-amdgpu-binaries [2] https://github.com/M-Bab/linux-kernel-amdgpu-binaries/issues/81 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 1/2] drm/amdkfd: Fix MQD size calculation
On Fri, Oct 4, 2019 at 10:48 AM Zeng, Oak wrote: > > On device initialization, a trunk of GTT memory is pre-allocated for typo: trunk -> chunk Alex > HIQ and all SDMA queues mqd. The size of this allocation was wrong. > The correct sdma engine number should be PCIe-optimized SDMA engine > number plus xgmi SDMA engine number. > > Change-Id: Iecd11ae4f5a314591566772aa2a23e1fe4b94275 > Reported-by: Jonathan Kim > Signed-off-by: Jonathan Kim > Signed-off-by: Oak Zeng > --- > drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c > b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c > index 16c04f8..e55d021 100644 > --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c > +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c > @@ -1849,7 +1849,8 @@ static int allocate_hiq_sdma_mqd(struct > device_queue_manager *dqm) > struct kfd_dev *dev = dqm->dev; > struct kfd_mem_obj *mem_obj = >hiq_sdma_mqd; > uint32_t size = dqm->mqd_mgrs[KFD_MQD_TYPE_SDMA]->mqd_size * > - dev->device_info->num_sdma_engines * > + (dev->device_info->num_sdma_engines + > + dev->device_info->num_xgmi_sdma_engines)* > dev->device_info->num_sdma_queues_per_engine + > dqm->mqd_mgrs[KFD_MQD_TYPE_HIQ]->mqd_size; > > -- > 2.7.4 > > ___ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: linux-next: Tree for Oct 4 (amdgpu)
On Fri, Oct 4, 2019 at 11:08 AM Randy Dunlap wrote: > > On 10/3/19 10:59 PM, Stephen Rothwell wrote: > > Hi all, > > > > Changes since 20191003: > > > > on x86_64: > CONFIG_DRM_AMDGPU=y > # CONFIG_DRM_AMDGPU_SI is not set > # CONFIG_DRM_AMDGPU_CIK is not set > CONFIG_DRM_AMDGPU_USERPTR=y > CONFIG_DRM_AMDGPU_GART_DEBUGFS=y > > ld: drivers/gpu/drm/amd/amdkfd/kfd_device.o:(.rodata+0xf60): undefined > reference to `gfx_v7_kfd2kgd' > Fixed: https://patchwork.freedesktop.org/patch/334412/ Alex > -- > ~Randy > ___ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amd/display: Make plane z-pos explicit to userspace
On 2019-10-03 10:46 a.m., Nicholas Kazlauskas wrote:
> [Why]
> Many userspace assumes that the DRM plane index indicates the plane
> z-order, with a lower index being lower depth and a higher index being
> higher depth. This is currently what we assume in DM.
>
> DRM has a zpos plane property to make this explicit to userspace and
> there are clients that make use of this information.
>
> [How]
> Attach the immutable zpos property to the plane.
>
> While we can technically order the planes in any manner since we
> virtualize them in DC we don't currently have the software support.
>
> The z-pos could potentially become immutable later but for now
> just let userspace do the ordering.
>
> Cc: Leo Li
> Cc: Harry Wentland
> Cc: Rodrigo Siqueira
> Signed-off-by: Nicholas Kazlauskas
Reviewed-by: Harry Wentland
Harry
> ---
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 239b1ae86007..e58b0b7e3c52 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -4897,6 +4897,9 @@ static int amdgpu_dm_plane_init(struct
> amdgpu_display_manager *dm,
> if (res)
> return res;
>
> + /* Make z-pos of each plane explicit - lower ID is lower depth */
> + drm_plane_create_zpos_immutable_property(plane, plane->index);
> +
> if (plane->type == DRM_PLANE_TYPE_OVERLAY &&
> plane_cap && plane_cap->per_pixel_alpha) {
> unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
>
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Re: [PATCH] drm/amdgpu: Enable gfx cache probing on HDP write for arcturus
I'm pretty sure the gart_enable function is not the right place for this. GART is for GPU access to system memory. HDP is for host access to GPU memory. Also, I would expect anything done in gart_enable to be undone in gart_disable. If that's not the intention, maybe this should go in gmc_v9_0_hw_init. Regards, Felix On 2019-10-04 10:56, Zeng, Oak wrote: > Ping... > > Regards, > Oak > > -Original Message- > From: Zeng, Oak > Sent: Thursday, September 19, 2019 5:17 PM > To: amd-gfx@lists.freedesktop.org > Cc: Kuehling, Felix ; Koenig, Christian > ; Zeng, Oak > Subject: [PATCH] drm/amdgpu: Enable gfx cache probing on HDP write for > arcturus > > This allows gfx cache to be probed and invalidated (for none-dirty cache > lines) on a HDP write (from either another GPU or CPU). This should work only > for the memory mapped as RW memory type newly added for arcturus, to achieve > some cache coherence b/t multiple memory clients. > > Change-Id: I0a69de48706bb713235bfbc83fcc67774614 > Signed-off-by: Oak Zeng > --- > drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > index 57d76ee..e01a359 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > @@ -1272,6 +1272,9 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device > *adev) > /* TODO for renoir */ > mmhub_v1_0_update_power_gating(adev, true); > break; > + case CHIP_ARCTURUS: > + WREG32_FIELD15(HDP, 0, HDP_MMHUB_CNTL, HDP_MMHUB_GCC, 1); > + break; > default: > break; > } > -- > 2.7.4 > ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu: user pages array memory leak fix
Hi Philip,
Am 04.10.19 um 15:40 schrieb Yang, Philip:
> Thanks Joe for the test, I will add your Tested-by.
>
> Hi Christian,
>
> May you help review? The change removes the get user pages from
> gem_userptr_ioctl, this was done if flags AMDGPU_GEM_USERPTR_VALIDATE is
> set, and delay the get user pages to amdgpu_cs_parser_bos, and check if
> user pages are invalidated when amdgpu_cs_submit. I don't find issue for
> overnight test, but not sure if there is potential side effect.
Yeah, seen that.
The AMDGPU_GEM_USERPTR_VALIDATE was explicitly added to cause a
validation during BO creation because of some very stupid applications.
I didn't wanted to reject that without offering an alternative, but we
seriously can't do this or it would break Vulkan/OpenGL.
I need more time to take a closer look,
Christian.
>
> Thanks,
> Philip
>
> On 2019-10-03 3:44 p.m., Yang, Philip wrote:
>> user_pages array should always be freed after validation regardless if
>> user pages are changed after bo is created because with HMM change parse
>> bo always allocate user pages array to get user pages for userptr bo.
>>
>> Don't need to get user pages while creating uerptr bo because user pages
>> will only be used while validating after parsing userptr bo.
>>
>> Bugzilla: https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1844962
>>
>> v2: remove unused local variable and amend commit
>>
>> Signed-off-by: Philip Yang
>> ---
>>drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 4 +---
>>drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 23 +--
>>2 files changed, 2 insertions(+), 25 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
>> index 49b767b7238f..961186e7113e 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
>> @@ -474,7 +474,6 @@ static int amdgpu_cs_list_validate(struct
>> amdgpu_cs_parser *p,
>>
>> list_for_each_entry(lobj, validated, tv.head) {
>> struct amdgpu_bo *bo = ttm_to_amdgpu_bo(lobj->tv.bo);
>> -bool binding_userptr = false;
>> struct mm_struct *usermm;
>>
>> usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm);
>> @@ -491,14 +490,13 @@ static int amdgpu_cs_list_validate(struct
>> amdgpu_cs_parser *p,
>>
>> amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm,
>> lobj->user_pages);
>> -binding_userptr = true;
>> }
>>
>> r = amdgpu_cs_validate(p, bo);
>> if (r)
>> return r;
>>
>> -if (binding_userptr) {
>> +if (lobj->user_pages) {
>> kvfree(lobj->user_pages);
>> lobj->user_pages = NULL;
>> }
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
>> index a828e3d0bfbd..3ccd61d69964 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
>> @@ -283,7 +283,6 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void
>> *data,
>>int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
>> struct drm_file *filp)
>>{
>> -struct ttm_operation_ctx ctx = { true, false };
>> struct amdgpu_device *adev = dev->dev_private;
>> struct drm_amdgpu_gem_userptr *args = data;
>> struct drm_gem_object *gobj;
>> @@ -326,32 +325,12 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev,
>> void *data,
>> goto release_object;
>> }
>>
>> -if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) {
>> -r = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages);
>> -if (r)
>> -goto release_object;
>> -
>> -r = amdgpu_bo_reserve(bo, true);
>> -if (r)
>> -goto user_pages_done;
>> -
>> -amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
>> -r = ttm_bo_validate(>tbo, >placement, );
>> -amdgpu_bo_unreserve(bo);
>> -if (r)
>> -goto user_pages_done;
>> -}
>> -
>> r = drm_gem_handle_create(filp, gobj, );
>> if (r)
>> -goto user_pages_done;
>> +goto release_object;
>>
>> args->handle = handle;
>>
>> -user_pages_done:
>> -if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE)
>> -amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm);
>> -
>>release_object:
>> drm_gem_object_put_unlocked(gobj);
>>
>>
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Re: [PATCH] drm/amdgpu: fix memory leak
Am 04.10.19 um 15:51 schrieb Nirmoy Das:
> cleanup error handling code and make sure temporary info array
> with the handles are freed by amdgpu_bo_list_put() on
> idr_replace()'s failure.
>
> Signed-off-by: Nirmoy Das
Reviewed-by: Christian König
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c | 14 +++---
> 1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
> index 7bcf86c61999..61e38e43ad1d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
> @@ -270,7 +270,7 @@ int amdgpu_bo_list_ioctl(struct drm_device *dev, void
> *data,
>
> r = amdgpu_bo_create_list_entry_array(>in, );
> if (r)
> - goto error_free;
> + return r;
>
> switch (args->in.operation) {
> case AMDGPU_BO_LIST_OP_CREATE:
> @@ -283,8 +283,7 @@ int amdgpu_bo_list_ioctl(struct drm_device *dev, void
> *data,
> r = idr_alloc(>bo_list_handles, list, 1, 0, GFP_KERNEL);
> mutex_unlock(>bo_list_lock);
> if (r < 0) {
> - amdgpu_bo_list_put(list);
> - return r;
> + goto error_put_list;
> }
>
> handle = r;
> @@ -306,9 +305,8 @@ int amdgpu_bo_list_ioctl(struct drm_device *dev, void
> *data,
> mutex_unlock(>bo_list_lock);
>
> if (IS_ERR(old)) {
> - amdgpu_bo_list_put(list);
> r = PTR_ERR(old);
> - goto error_free;
> + goto error_put_list;
> }
>
> amdgpu_bo_list_put(old);
> @@ -325,8 +323,10 @@ int amdgpu_bo_list_ioctl(struct drm_device *dev, void
> *data,
>
> return 0;
>
> +error_put_list:
> + amdgpu_bo_list_put(list);
> +
> error_free:
> - if (info)
> - kvfree(info);
> + kvfree(info);
> return r;
> }
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RE: [PATCH] drm/amdgpu: Enable gfx cache probing on HDP write for arcturus
Ping... Regards, Oak -Original Message- From: Zeng, Oak Sent: Thursday, September 19, 2019 5:17 PM To: amd-gfx@lists.freedesktop.org Cc: Kuehling, Felix ; Koenig, Christian ; Zeng, Oak Subject: [PATCH] drm/amdgpu: Enable gfx cache probing on HDP write for arcturus This allows gfx cache to be probed and invalidated (for none-dirty cache lines) on a HDP write (from either another GPU or CPU). This should work only for the memory mapped as RW memory type newly added for arcturus, to achieve some cache coherence b/t multiple memory clients. Change-Id: I0a69de48706bb713235bfbc83fcc67774614 Signed-off-by: Oak Zeng --- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index 57d76ee..e01a359 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -1272,6 +1272,9 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) /* TODO for renoir */ mmhub_v1_0_update_power_gating(adev, true); break; + case CHIP_ARCTURUS: + WREG32_FIELD15(HDP, 0, HDP_MMHUB_CNTL, HDP_MMHUB_GCC, 1); + break; default: break; } -- 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 2/2] drm/amdkfd: Print more sdma engine hqds in debug fs
On 2019-10-04 10:48, Zeng, Oak wrote:
> Previously only PCIe-optimized SDMA engine hqds were
> exposed in debug fs. Print all SDMA engine hqds.
>
> Change-Id: I03756fc0fa99169d88e265560f505ed186242b02
> Reported-by: Jonathan Kim
> Signed-off-by: Jonathan Kim
> Signed-off-by: Oak Zeng
Minor cosmetic nit-pick inline that checkpatch.pl would probably warn
about. With that fixed, this patch is
Reviewed-by: Felix Kuehling
> ---
> drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> index e55d021..0ebc604 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> @@ -2416,7 +2416,7 @@ int dqm_debugfs_hqds(struct seq_file *m, void *data)
> }
> }
>
> - for (pipe = 0; pipe < get_num_sdma_engines(dqm); pipe++) {
> + for (pipe = 0; pipe < get_num_sdma_engines(dqm) +
> get_num_xgmi_sdma_engines(dqm); pipe++) {
This line looks longer than 80 characters. Try to find a good place to
break it.
> for (queue = 0;
>queue < dqm->dev->device_info->num_sdma_queues_per_engine;
>queue++) {
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Re: linux-next: Tree for Oct 4 (amdgpu)
On 10/3/19 10:59 PM, Stephen Rothwell wrote: > Hi all, > > Changes since 20191003: > on x86_64: CONFIG_DRM_AMDGPU=y # CONFIG_DRM_AMDGPU_SI is not set # CONFIG_DRM_AMDGPU_CIK is not set CONFIG_DRM_AMDGPU_USERPTR=y CONFIG_DRM_AMDGPU_GART_DEBUGFS=y ld: drivers/gpu/drm/amd/amdkfd/kfd_device.o:(.rodata+0xf60): undefined reference to `gfx_v7_kfd2kgd' -- ~Randy
Re: [PATCH 1/2] drm/amdkfd: Fix MQD size calculation
On 2019-10-04 10:48, Zeng, Oak wrote: > On device initialization, a trunk of GTT memory is pre-allocated for > HIQ and all SDMA queues mqd. The size of this allocation was wrong. > The correct sdma engine number should be PCIe-optimized SDMA engine > number plus xgmi SDMA engine number. > > Change-Id: Iecd11ae4f5a314591566772aa2a23e1fe4b94275 > Reported-by: Jonathan Kim > Signed-off-by: Jonathan Kim > Signed-off-by: Oak Zeng Minor cosmetic nit-pick inline that checkpatch.pl would probably warn about. With that fixed, this patch is Reviewed-by: Felix Kuehling > --- > drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c > b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c > index 16c04f8..e55d021 100644 > --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c > +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c > @@ -1849,7 +1849,8 @@ static int allocate_hiq_sdma_mqd(struct > device_queue_manager *dqm) > struct kfd_dev *dev = dqm->dev; > struct kfd_mem_obj *mem_obj = >hiq_sdma_mqd; > uint32_t size = dqm->mqd_mgrs[KFD_MQD_TYPE_SDMA]->mqd_size * > - dev->device_info->num_sdma_engines * > + (dev->device_info->num_sdma_engines + > + dev->device_info->num_xgmi_sdma_engines)* There should be a space between ) and *. > dev->device_info->num_sdma_queues_per_engine + > dqm->mqd_mgrs[KFD_MQD_TYPE_HIQ]->mqd_size; > ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 1/2] drm/amdkfd: Fix MQD size calculation
On device initialization, a trunk of GTT memory is pre-allocated for HIQ and all SDMA queues mqd. The size of this allocation was wrong. The correct sdma engine number should be PCIe-optimized SDMA engine number plus xgmi SDMA engine number. Change-Id: Iecd11ae4f5a314591566772aa2a23e1fe4b94275 Reported-by: Jonathan Kim Signed-off-by: Jonathan Kim Signed-off-by: Oak Zeng --- drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index 16c04f8..e55d021 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -1849,7 +1849,8 @@ static int allocate_hiq_sdma_mqd(struct device_queue_manager *dqm) struct kfd_dev *dev = dqm->dev; struct kfd_mem_obj *mem_obj = >hiq_sdma_mqd; uint32_t size = dqm->mqd_mgrs[KFD_MQD_TYPE_SDMA]->mqd_size * - dev->device_info->num_sdma_engines * + (dev->device_info->num_sdma_engines + + dev->device_info->num_xgmi_sdma_engines)* dev->device_info->num_sdma_queues_per_engine + dqm->mqd_mgrs[KFD_MQD_TYPE_HIQ]->mqd_size; -- 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 2/2] drm/amdkfd: Print more sdma engine hqds in debug fs
Previously only PCIe-optimized SDMA engine hqds were
exposed in debug fs. Print all SDMA engine hqds.
Change-Id: I03756fc0fa99169d88e265560f505ed186242b02
Reported-by: Jonathan Kim
Signed-off-by: Jonathan Kim
Signed-off-by: Oak Zeng
---
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index e55d021..0ebc604 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -2416,7 +2416,7 @@ int dqm_debugfs_hqds(struct seq_file *m, void *data)
}
}
- for (pipe = 0; pipe < get_num_sdma_engines(dqm); pipe++) {
+ for (pipe = 0; pipe < get_num_sdma_engines(dqm) +
get_num_xgmi_sdma_engines(dqm); pipe++) {
for (queue = 0;
queue < dqm->dev->device_info->num_sdma_queues_per_engine;
queue++) {
--
2.7.4
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[PATCH TRIVIAL v2] gpu: Fix Kconfig indentation
Adjust indentation from spaces to tab (+optional two spaces) as in coding style with command like: $ sed -e 's/^/\t/' -i */Kconfig Signed-off-by: Krzysztof Kozlowski --- Changes since v1: 1. Fix also DRM_AMD_DC_HDCP (new arrival since v1). --- drivers/gpu/drm/Kconfig | 10 +- drivers/gpu/drm/amd/display/Kconfig | 32 ++--- drivers/gpu/drm/bridge/Kconfig | 8 +- drivers/gpu/drm/i915/Kconfig | 12 +- drivers/gpu/drm/i915/Kconfig.debug | 144 +++ drivers/gpu/drm/lima/Kconfig | 2 +- drivers/gpu/drm/mgag200/Kconfig | 8 +- drivers/gpu/drm/nouveau/Kconfig | 2 +- drivers/gpu/drm/omapdrm/displays/Kconfig | 6 +- drivers/gpu/drm/omapdrm/dss/Kconfig | 12 +- drivers/gpu/drm/rockchip/Kconfig | 8 +- drivers/gpu/drm/udl/Kconfig | 2 +- drivers/gpu/vga/Kconfig | 2 +- 13 files changed, 124 insertions(+), 124 deletions(-) diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig index e67c194c2aca..7cb6e4eb99e8 100644 --- a/drivers/gpu/drm/Kconfig +++ b/drivers/gpu/drm/Kconfig @@ -207,8 +207,8 @@ config DRM_RADEON tristate "ATI Radeon" depends on DRM && PCI && MMU select FW_LOADER -select DRM_KMS_HELPER -select DRM_TTM + select DRM_KMS_HELPER + select DRM_TTM select POWER_SUPPLY select HWMON select BACKLIGHT_CLASS_DEVICE @@ -226,9 +226,9 @@ config DRM_AMDGPU tristate "AMD GPU" depends on DRM && PCI && MMU select FW_LOADER -select DRM_KMS_HELPER + select DRM_KMS_HELPER select DRM_SCHED -select DRM_TTM + select DRM_TTM select POWER_SUPPLY select HWMON select BACKLIGHT_CLASS_DEVICE @@ -266,7 +266,7 @@ config DRM_VKMS If M is selected the module will be called vkms. config DRM_ATI_PCIGART -bool + bool source "drivers/gpu/drm/exynos/Kconfig" diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/display/Kconfig index 1bbe762ee6ba..313183b80032 100644 --- a/drivers/gpu/drm/amd/display/Kconfig +++ b/drivers/gpu/drm/amd/display/Kconfig @@ -23,16 +23,16 @@ config DRM_AMD_DC_DCN2_0 depends on DRM_AMD_DC && X86 depends on DRM_AMD_DC_DCN1_0 help - Choose this option if you want to have - Navi support for display engine + Choose this option if you want to have + Navi support for display engine config DRM_AMD_DC_DCN2_1 -bool "DCN 2.1 family" -depends on DRM_AMD_DC && X86 -depends on DRM_AMD_DC_DCN2_0 -help -Choose this option if you want to have -Renoir support for display engine + bool "DCN 2.1 family" + depends on DRM_AMD_DC && X86 + depends on DRM_AMD_DC_DCN2_0 + help + Choose this option if you want to have + Renoir support for display engine config DRM_AMD_DC_DSC_SUPPORT bool "DSC support" @@ -41,16 +41,16 @@ config DRM_AMD_DC_DSC_SUPPORT depends on DRM_AMD_DC_DCN1_0 depends on DRM_AMD_DC_DCN2_0 help - Choose this option if you want to have - Dynamic Stream Compression support + Choose this option if you want to have + Dynamic Stream Compression support config DRM_AMD_DC_HDCP -bool "Enable HDCP support in DC" -depends on DRM_AMD_DC -help - Choose this option - if you want to support - HDCP authentication + bool "Enable HDCP support in DC" + depends on DRM_AMD_DC + help +Choose this option +if you want to support +HDCP authentication config DEBUG_KERNEL_DC bool "Enable kgdb break in DC" diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig index 1cc9f502c1f2..a5aa7ec16000 100644 --- a/drivers/gpu/drm/bridge/Kconfig +++ b/drivers/gpu/drm/bridge/Kconfig @@ -60,10 +60,10 @@ config DRM_MEGACHIPS_STDP_GE_B850V3_FW select DRM_KMS_HELPER select DRM_PANEL ---help--- - This is a driver for the display bridges of - GE B850v3 that convert dual channel LVDS - to DP++. This is used with the i.MX6 imx-ldb - driver. You are likely to say N here. + This is a driver for the display bridges of + GE B850v3 that convert dual channel LVDS + to DP++. This is used with the i.MX6 imx-ldb + driver. You are likely to say N here. config DRM_NXP_PTN3460 tristate "NXP PTN3460 DP/LVDS bridge" diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig index 0d21402945ab..3c6d57df262d 100644 --- a/drivers/gpu/drm/i915/Kconfig +++ b/drivers/gpu/drm/i915/Kconfig @@ -76,7 +76,7 @@ config DRM_I915_CAPTURE_ERROR This option enables capturing the GPU state when a hang is detected. This
Re: [PATCH] drm/drm_edid: correct VIC and HDMI_VIC under HDMI 2.0
On Fri, Oct 04, 2019 at 10:41:20AM +, Lin, Wayne wrote: > > > > From: Ville Syrjälä > Sent: Thursday, October 3, 2019 21:29 > To: Lin, Wayne > Cc: dri-de...@lists.freedesktop.org ; > amd-gfx@lists.freedesktop.org ; Li, Sun peng > (Leo) ; Kazlauskas, Nicholas > Subject: Re: [PATCH] drm/drm_edid: correct VIC and HDMI_VIC under HDMI 2.0 > > On Thu, Oct 03, 2019 at 06:49:05AM +, Lin, Wayne wrote: > > > > > > > > From: Ville Syrjälä > > Sent: Wednesday, October 2, 2019 19:58 > > To: Lin, Wayne > > Cc: dri-de...@lists.freedesktop.org ; > > amd-gfx@lists.freedesktop.org ; Li, Sun peng > > (Leo) ; Kazlauskas, Nicholas > > > > Subject: Re: [PATCH] drm/drm_edid: correct VIC and HDMI_VIC under HDMI 2.0 > > > > On Tue, Sep 24, 2019 at 01:26:21PM +0800, Wayne Lin wrote: > > > In HDMI 1.4 defines 4k modes without specific aspect ratio. > > > However, in HDMI 2.0, adds aspect ratio attribute to distinguish different > > > 4k modes. > > > > > > According to Appendix E of HDMI 2.0 spec, source should use VSIF to > > > indicate VIC mode only when the mode is one defined in HDMI 1.4b 4K modes. > > > Otherwise, use AVI infoframes to convey VIC. > > > > > > eg: VIC_103 should use AVI infoframes and VIC_93 use VSIF > > > > > > When the sink is HDMI 2.0, current code in > > > drm_hdmi_avi_infoframe_from_display_mode will also force mode VIC_103 to > > > have VIC value 0. This violates the spec and needs to be corrected. > > > > > Where is that being done? We only set the AVI VIC to zero if we're going > > > to use the HDMI VIC instead. > > > > Appreciate for your time and apologize for not explaining it clearly. > > Current code in drm_hdmi_avi_infoframe_from_display_mode() will call > > drm_match_hdmi_mode() to set up vendor_if_vic. By checking > > drm_valid_hdmi_vic(vendor_if_vic) to see if the vic info should be conveyed > > by avi > > or not. > > > > But in drm_match_hdmi_mode(), code doesn't enable match_flags with > > DRM_MODE_MATCH_ASPECT_RATIO. I think it's due to HDMI1.4b doesn't specify > > 4K mode conveyed by HDMI VIC with particular aspect ratio. But in Appendix > > E of > > HDMI 2.0 spec, it specify only 4k modes with particular aspect ratio should > > use VSIF to convey. > > Hence, when the sink support HDMI 2.0 and set the mode to be VIC_103, > > calling > > drm_match_hdmi_mode(mode) will return vendor_if_vic = 3 (VIC_93 and VIC_103 > > are having > > the same timing but different aspect ratio). Thereafter will set the > > frame->video_code to 0. > > However, VIC_103 should use AVI VIC according to HDMI 2.0 spec (only VIC: > > 93, 94, 95 & > > 98 should use VSIF). > > > > This patch try to revise that, when the sink support HDMI 2.0, > > drm_match_hdmi_mode() > > should also take aspect ratio into consideration. > > But for easy reading, I add another function "drm_match_hdmi_1_4_mode" to > > do so. > > > Seems rather convoluted. I think we should just add the aspect ratios > > to edid_4k_modes[]. Or is there some problem with that approach? > > Thanks for your time. > > Since HDMI 1.4b doesn't require edid_4k_modes[] with specific aspect ratio, > modes as the same > timing in edid_4k_modes[] but with different aspect ratios are also expected > to convey VIC by > VSIF to HDMI 1.4 sink. Might can't guarantee that there wont't be any > compatibility side effect with > that approach when the sink is HDMI 1.4b . I think adding them should be fine. But while checking the existing code I noticed a few problems, so I sent out some fixes (cc:d you). -- Ville Syrjälä Intel ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: fix memory leak
cleanup error handling code and make sure temporary info array
with the handles are freed by amdgpu_bo_list_put() on
idr_replace()'s failure.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
index 7bcf86c61999..61e38e43ad1d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
@@ -270,7 +270,7 @@ int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
r = amdgpu_bo_create_list_entry_array(>in, );
if (r)
- goto error_free;
+ return r;
switch (args->in.operation) {
case AMDGPU_BO_LIST_OP_CREATE:
@@ -283,8 +283,7 @@ int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
r = idr_alloc(>bo_list_handles, list, 1, 0, GFP_KERNEL);
mutex_unlock(>bo_list_lock);
if (r < 0) {
- amdgpu_bo_list_put(list);
- return r;
+ goto error_put_list;
}
handle = r;
@@ -306,9 +305,8 @@ int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
mutex_unlock(>bo_list_lock);
if (IS_ERR(old)) {
- amdgpu_bo_list_put(list);
r = PTR_ERR(old);
- goto error_free;
+ goto error_put_list;
}
amdgpu_bo_list_put(old);
@@ -325,8 +323,10 @@ int amdgpu_bo_list_ioctl(struct drm_device *dev, void
*data,
return 0;
+error_put_list:
+ amdgpu_bo_list_put(list);
+
error_free:
- if (info)
- kvfree(info);
+ kvfree(info);
return r;
}
--
2.23.0
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[PATCH] drm/amdkfd: fix the build when CIK support is disabled
Add proper ifdefs around CIK code in kfd setup.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdkfd/kfd_device.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index 0db273587af4..d898adf25fbb 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -39,7 +39,9 @@
*/
static atomic_t kfd_locked = ATOMIC_INIT(0);
+#ifdef CONFIG_DRM_AMDGPU_CIK
extern const struct kfd2kgd_calls gfx_v7_kfd2kgd;
+#endif
extern const struct kfd2kgd_calls gfx_v8_kfd2kgd;
extern const struct kfd2kgd_calls gfx_v9_kfd2kgd;
extern const struct kfd2kgd_calls arcturus_kfd2kgd;
@@ -47,11 +49,15 @@ extern const struct kfd2kgd_calls gfx_v10_kfd2kgd;
static const struct kfd2kgd_calls *kfd2kgd_funcs[] = {
#ifdef KFD_SUPPORT_IOMMU_V2
+#ifdef CONFIG_DRM_AMDGPU_CIK
[CHIP_KAVERI] = _v7_kfd2kgd,
+#endif
[CHIP_CARRIZO] = _v8_kfd2kgd,
[CHIP_RAVEN] = _v9_kfd2kgd,
#endif
+#ifdef CONFIG_DRM_AMDGPU_CIK
[CHIP_HAWAII] = _v7_kfd2kgd,
+#endif
[CHIP_TONGA] = _v8_kfd2kgd,
[CHIP_FIJI] = _v8_kfd2kgd,
[CHIP_POLARIS10] = _v8_kfd2kgd,
--
2.20.1
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Re: [PATCH] drm/amdgpu: user pages array memory leak fix
Thanks Joe for the test, I will add your Tested-by.
Hi Christian,
May you help review? The change removes the get user pages from
gem_userptr_ioctl, this was done if flags AMDGPU_GEM_USERPTR_VALIDATE is
set, and delay the get user pages to amdgpu_cs_parser_bos, and check if
user pages are invalidated when amdgpu_cs_submit. I don't find issue for
overnight test, but not sure if there is potential side effect.
Thanks,
Philip
On 2019-10-03 3:44 p.m., Yang, Philip wrote:
> user_pages array should always be freed after validation regardless if
> user pages are changed after bo is created because with HMM change parse
> bo always allocate user pages array to get user pages for userptr bo.
>
> Don't need to get user pages while creating uerptr bo because user pages
> will only be used while validating after parsing userptr bo.
>
> Bugzilla: https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1844962
>
> v2: remove unused local variable and amend commit
>
> Signed-off-by: Philip Yang
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 4 +---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 23 +--
> 2 files changed, 2 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> index 49b767b7238f..961186e7113e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> @@ -474,7 +474,6 @@ static int amdgpu_cs_list_validate(struct
> amdgpu_cs_parser *p,
>
> list_for_each_entry(lobj, validated, tv.head) {
> struct amdgpu_bo *bo = ttm_to_amdgpu_bo(lobj->tv.bo);
> - bool binding_userptr = false;
> struct mm_struct *usermm;
>
> usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm);
> @@ -491,14 +490,13 @@ static int amdgpu_cs_list_validate(struct
> amdgpu_cs_parser *p,
>
> amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm,
>lobj->user_pages);
> - binding_userptr = true;
> }
>
> r = amdgpu_cs_validate(p, bo);
> if (r)
> return r;
>
> - if (binding_userptr) {
> + if (lobj->user_pages) {
> kvfree(lobj->user_pages);
> lobj->user_pages = NULL;
> }
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> index a828e3d0bfbd..3ccd61d69964 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> @@ -283,7 +283,6 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void
> *data,
> int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
>struct drm_file *filp)
> {
> - struct ttm_operation_ctx ctx = { true, false };
> struct amdgpu_device *adev = dev->dev_private;
> struct drm_amdgpu_gem_userptr *args = data;
> struct drm_gem_object *gobj;
> @@ -326,32 +325,12 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev,
> void *data,
> goto release_object;
> }
>
> - if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) {
> - r = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages);
> - if (r)
> - goto release_object;
> -
> - r = amdgpu_bo_reserve(bo, true);
> - if (r)
> - goto user_pages_done;
> -
> - amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
> - r = ttm_bo_validate(>tbo, >placement, );
> - amdgpu_bo_unreserve(bo);
> - if (r)
> - goto user_pages_done;
> - }
> -
> r = drm_gem_handle_create(filp, gobj, );
> if (r)
> - goto user_pages_done;
> + goto release_object;
>
> args->handle = handle;
>
> -user_pages_done:
> - if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE)
> - amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm);
> -
> release_object:
> drm_gem_object_put_unlocked(gobj);
>
>
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Re: [PATCH][next] drm/amdgpu: remove redundant variable r and redundant return statement
On Fri, Oct 4, 2019 at 3:29 AM Koenig, Christian
wrote:
>
> Am 03.10.19 um 23:40 schrieb Colin King:
> > From: Colin Ian King
> >
> > There is a return statement that is not reachable and a variable that
> > is not used. Remove them.
> >
> > Addresses-Coverity: ("Structurally dead code")
> > Fixes: de7b45babd9b ("drm/amdgpu: cleanup creating BOs at fixed location
> > (v2)")
> > Signed-off-by: Colin Ian King
>
> Reviewed-by: Christian König
Applied. Thanks!
Alex
>
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 --
> > 1 file changed, 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> > index 481e4c381083..814159f15633 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> > @@ -1636,7 +1636,6 @@ static void amdgpu_ttm_fw_reserve_vram_fini(struct
> > amdgpu_device *adev)
> > static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
> > {
> > uint64_t vram_size = adev->gmc.visible_vram_size;
> > - int r;
> >
> > adev->fw_vram_usage.va = NULL;
> > adev->fw_vram_usage.reserved_bo = NULL;
> > @@ -1651,7 +1650,6 @@ static int amdgpu_ttm_fw_reserve_vram_init(struct
> > amdgpu_device *adev)
> > AMDGPU_GEM_DOMAIN_VRAM,
> > >fw_vram_usage.reserved_bo,
> > >fw_vram_usage.va);
> > - return r;
> > }
> >
> > /**
>
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Re: [PATCH][next] drm/amdgpu: fix uninitialized variable pasid_mapping_needed
On Fri, Oct 4, 2019 at 3:28 AM Koenig, Christian
wrote:
>
> Am 03.10.19 um 23:52 schrieb Colin King:
> > From: Colin Ian King
> >
> > The boolean variable pasid_mapping_needed is not initialized and
> > there are code paths that do not assign it any value before it is
> > is read later. Fix this by initializing pasid_mapping_needed to
> > false.
> >
> > Addresses-Coverity: ("Uninitialized scalar variable")
> > Fixes: 6817bf283b2b ("drm/amdgpu: grab the id mgr lock while accessing
> > passid_mapping")
> > Signed-off-by: Colin Ian King
>
> Reviewed-by: Christian König
>
Applied. thanks!
Alex
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> > index a2c797e34a29..be10e4b9a94d 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> > @@ -1055,7 +1055,7 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct
> > amdgpu_job *job,
> > id->oa_size != job->oa_size);
> > bool vm_flush_needed = job->vm_needs_flush;
> > struct dma_fence *fence = NULL;
> > - bool pasid_mapping_needed;
> > + bool pasid_mapping_needed = false;
> > unsigned patch_offset = 0;
> > int r;
> >
>
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Re: [PATCH] drm/amd/display: Make some functions static
On Fri, Oct 4, 2019 at 8:25 AM zhengbin wrote:
>
> Fix sparse warnings:
>
> drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_hdcp.c:32:6:
> warning: symbol 'lp_write_i2c' was not declared. Should it be static?
> drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_hdcp.c:42:6:
> warning: symbol 'lp_read_i2c' was not declared. Should it be static?
> drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_hdcp.c:52:6:
> warning: symbol 'lp_write_dpcd' was not declared. Should it be static?
> drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_hdcp.c:59:6:
> warning: symbol 'lp_read_dpcd' was not declared. Should it be static?
>
> Reported-by: Hulk Robot
> Signed-off-by: zhengbin
Applied. thanks!
Alex
> ---
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c | 12
> 1 file changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
> index 2443c23..77181dd 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
> @@ -29,7 +29,8 @@
> #include "dm_helpers.h"
> #include
>
> -bool lp_write_i2c(void *handle, uint32_t address, const uint8_t *data,
> uint32_t size)
> +static bool
> +lp_write_i2c(void *handle, uint32_t address, const uint8_t *data, uint32_t
> size)
> {
>
> struct dc_link *link = handle;
> @@ -39,7 +40,8 @@ bool lp_write_i2c(void *handle, uint32_t address, const
> uint8_t *data, uint32_t
> return dm_helpers_submit_i2c(link->ctx, link, );
> }
>
> -bool lp_read_i2c(void *handle, uint32_t address, uint8_t offset, uint8_t
> *data, uint32_t size)
> +static bool
> +lp_read_i2c(void *handle, uint32_t address, uint8_t offset, uint8_t *data,
> uint32_t size)
> {
> struct dc_link *link = handle;
>
> @@ -49,14 +51,16 @@ bool lp_read_i2c(void *handle, uint32_t address, uint8_t
> offset, uint8_t *data,
> return dm_helpers_submit_i2c(link->ctx, link, );
> }
>
> -bool lp_write_dpcd(void *handle, uint32_t address, const uint8_t *data,
> uint32_t size)
> +static bool
> +lp_write_dpcd(void *handle, uint32_t address, const uint8_t *data, uint32_t
> size)
> {
> struct dc_link *link = handle;
>
> return dm_helpers_dp_write_dpcd(link->ctx, link, address, data, size);
> }
>
> -bool lp_read_dpcd(void *handle, uint32_t address, uint8_t *data, uint32_t
> size)
> +static bool
> +lp_read_dpcd(void *handle, uint32_t address, uint8_t *data, uint32_t size)
> {
> struct dc_link *link = handle;
>
> --
> 2.7.4
>
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Re: [PATCH v3] drm/amd/display: fix struct init in update_bounding_box
On Thu, Oct 3, 2019 at 4:35 PM Raul E Rangel wrote:
>
> dcn20_resource.c:2636:9: error: missing braces around initializer
> [-Werror=missing-braces]
> struct _vcs_dpi_voltage_scaling_st
> calculated_states[MAX_CLOCK_LIMIT_STATES] = {0};
> ^
>
> Fixes: 7ed4e6352c16f ("drm/amd/display: Add DCN2 HW Sequencer and Resource")
>
> Signed-off-by: Raul E Rangel
Applied. thanks!
Alex
>
> ---
>
> Changes in v3:
> - Use memset
>
> Changes in v2:
> - Use {{0}} instead of {}
>
> drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> index b949e202d6cb7..f72c26ae41def 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> @@ -2633,7 +2633,7 @@ static void cap_soc_clocks(
> static void update_bounding_box(struct dc *dc, struct
> _vcs_dpi_soc_bounding_box_st *bb,
> struct pp_smu_nv_clock_table *max_clocks, unsigned int
> *uclk_states, unsigned int num_states)
> {
> - struct _vcs_dpi_voltage_scaling_st
> calculated_states[MAX_CLOCK_LIMIT_STATES] = {0};
> + struct _vcs_dpi_voltage_scaling_st
> calculated_states[MAX_CLOCK_LIMIT_STATES];
> int i;
> int num_calculated_states = 0;
> int min_dcfclk = 0;
> @@ -2641,6 +2641,8 @@ static void update_bounding_box(struct dc *dc, struct
> _vcs_dpi_soc_bounding_box_
> if (num_states == 0)
> return;
>
> + memset(calculated_states, 0, sizeof(calculated_states));
> +
> if (dc->bb_overrides.min_dcfclk_mhz > 0)
> min_dcfclk = dc->bb_overrides.min_dcfclk_mhz;
> else
> --
> 2.23.0.444.g18eeb5a265-goog
>
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Re: [PATCH 03/11] drm/amdgpu: convert amdgpu_vm_it to half closed intervals
Hi Michel, Am 04.10.19 um 13:36 schrieb Michel Lespinasse: On Fri, Oct 04, 2019 at 06:54:54AM +, Koenig, Christian wrote: Am 03.10.19 um 22:18 schrieb Davidlohr Bueso: The amdgpu_vm interval tree really wants [a, b) intervals, NAK, we explicitly do need an [a, b[ interval here. Hi Christian, Just wanted to confirm where you stand on this patch, since I think you reconsidered your initial position after first looking at 9/11 from this series. I do not know the amdgpu code well, but I think the changes should be fine - in struct amdgpu_bo_va_mapping, the "end" field will hold what was previously stored in the "last" field, plus one. The expectation is that overflows should not be an issue there, as "end" is explicitly declared as an uint64, and as the code was previously computing "last + 1" in many places. Does that seem workable to you ? No, we computed last + 1 in a couple of debug places were it doesn't hurt us and IIRC we currently cheat a bit because we use pfn instead of addresses on some other places. But that is only a leftover from radeon and we need to fix that sooner or later, cause essentially the physical address space of the device is really full 64bits, e.g. 0x0-0x. So that only fits into a 64bit int when we use half open/closed intervals, but would wrap around to zero if we use a closed interval. I initially thought that the set was changing the interval tree into always using a closed interval, but that seems to have been a misunderstanding. Regards, Christian. Thanks, ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amd/display: Make some functions static
Fix sparse warnings:
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_hdcp.c:32:6: warning:
symbol 'lp_write_i2c' was not declared. Should it be static?
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_hdcp.c:42:6: warning:
symbol 'lp_read_i2c' was not declared. Should it be static?
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_hdcp.c:52:6: warning:
symbol 'lp_write_dpcd' was not declared. Should it be static?
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_hdcp.c:59:6: warning:
symbol 'lp_read_dpcd' was not declared. Should it be static?
Reported-by: Hulk Robot
Signed-off-by: zhengbin
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
index 2443c23..77181dd 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
@@ -29,7 +29,8 @@
#include "dm_helpers.h"
#include
-bool lp_write_i2c(void *handle, uint32_t address, const uint8_t *data,
uint32_t size)
+static bool
+lp_write_i2c(void *handle, uint32_t address, const uint8_t *data, uint32_t
size)
{
struct dc_link *link = handle;
@@ -39,7 +40,8 @@ bool lp_write_i2c(void *handle, uint32_t address, const
uint8_t *data, uint32_t
return dm_helpers_submit_i2c(link->ctx, link, );
}
-bool lp_read_i2c(void *handle, uint32_t address, uint8_t offset, uint8_t
*data, uint32_t size)
+static bool
+lp_read_i2c(void *handle, uint32_t address, uint8_t offset, uint8_t *data,
uint32_t size)
{
struct dc_link *link = handle;
@@ -49,14 +51,16 @@ bool lp_read_i2c(void *handle, uint32_t address, uint8_t
offset, uint8_t *data,
return dm_helpers_submit_i2c(link->ctx, link, );
}
-bool lp_write_dpcd(void *handle, uint32_t address, const uint8_t *data,
uint32_t size)
+static bool
+lp_write_dpcd(void *handle, uint32_t address, const uint8_t *data, uint32_t
size)
{
struct dc_link *link = handle;
return dm_helpers_dp_write_dpcd(link->ctx, link, address, data, size);
}
-bool lp_read_dpcd(void *handle, uint32_t address, uint8_t *data, uint32_t size)
+static bool
+lp_read_dpcd(void *handle, uint32_t address, uint8_t *data, uint32_t size)
{
struct dc_link *link = handle;
--
2.7.4
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Re: [PATCH 03/11] drm/amdgpu: convert amdgpu_vm_it to half closed intervals
On Fri, Oct 04, 2019 at 06:54:54AM +, Koenig, Christian wrote: > Am 03.10.19 um 22:18 schrieb Davidlohr Bueso: > > The amdgpu_vm interval tree really wants [a, b) intervals, > > NAK, we explicitly do need an [a, b[ interval here. Hi Christian, Just wanted to confirm where you stand on this patch, since I think you reconsidered your initial position after first looking at 9/11 from this series. I do not know the amdgpu code well, but I think the changes should be fine - in struct amdgpu_bo_va_mapping, the "end" field will hold what was previously stored in the "last" field, plus one. The expectation is that overflows should not be an issue there, as "end" is explicitly declared as an uint64, and as the code was previously computing "last + 1" in many places. Does that seem workable to you ? Thanks, -- Michel "Walken" Lespinasse A program is never fully debugged until the last user dies.
Re: [PATCH] drm/drm_edid: correct VIC and HDMI_VIC under HDMI 2.0
From: Ville Syrjälä
Sent: Thursday, October 3, 2019 21:29
To: Lin, Wayne
Cc: dri-de...@lists.freedesktop.org ;
amd-gfx@lists.freedesktop.org ; Li, Sun peng
(Leo) ; Kazlauskas, Nicholas
Subject: Re: [PATCH] drm/drm_edid: correct VIC and HDMI_VIC under HDMI 2.0
On Thu, Oct 03, 2019 at 06:49:05AM +, Lin, Wayne wrote:
>
>
>
> From: Ville Syrjälä
> Sent: Wednesday, October 2, 2019 19:58
> To: Lin, Wayne
> Cc: dri-de...@lists.freedesktop.org ;
> amd-gfx@lists.freedesktop.org ; Li, Sun peng
> (Leo) ; Kazlauskas, Nicholas
> Subject: Re: [PATCH] drm/drm_edid: correct VIC and HDMI_VIC under HDMI 2.0
>
> On Tue, Sep 24, 2019 at 01:26:21PM +0800, Wayne Lin wrote:
> > In HDMI 1.4 defines 4k modes without specific aspect ratio.
> > However, in HDMI 2.0, adds aspect ratio attribute to distinguish different
> > 4k modes.
> >
> > According to Appendix E of HDMI 2.0 spec, source should use VSIF to
> > indicate VIC mode only when the mode is one defined in HDMI 1.4b 4K modes.
> > Otherwise, use AVI infoframes to convey VIC.
> >
> > eg: VIC_103 should use AVI infoframes and VIC_93 use VSIF
> >
> > When the sink is HDMI 2.0, current code in
> > drm_hdmi_avi_infoframe_from_display_mode will also force mode VIC_103 to
> > have VIC value 0. This violates the spec and needs to be corrected.
>
> > Where is that being done? We only set the AVI VIC to zero if we're going
> > to use the HDMI VIC instead.
>
> Appreciate for your time and apologize for not explaining it clearly.
> Current code in drm_hdmi_avi_infoframe_from_display_mode() will call
> drm_match_hdmi_mode() to set up vendor_if_vic. By checking
> drm_valid_hdmi_vic(vendor_if_vic) to see if the vic info should be conveyed
> by avi
> or not.
>
> But in drm_match_hdmi_mode(), code doesn't enable match_flags with
> DRM_MODE_MATCH_ASPECT_RATIO. I think it's due to HDMI1.4b doesn't specify
> 4K mode conveyed by HDMI VIC with particular aspect ratio. But in Appendix E
> of
> HDMI 2.0 spec, it specify only 4k modes with particular aspect ratio should
> use VSIF to convey.
> Hence, when the sink support HDMI 2.0 and set the mode to be VIC_103, calling
> drm_match_hdmi_mode(mode) will return vendor_if_vic = 3 (VIC_93 and VIC_103
> are having
> the same timing but different aspect ratio). Thereafter will set the
> frame->video_code to 0.
> However, VIC_103 should use AVI VIC according to HDMI 2.0 spec (only VIC: 93,
> 94, 95 &
> 98 should use VSIF).
>
> This patch try to revise that, when the sink support HDMI 2.0,
> drm_match_hdmi_mode()
> should also take aspect ratio into consideration.
> But for easy reading, I add another function "drm_match_hdmi_1_4_mode" to do
> so.
> Seems rather convoluted. I think we should just add the aspect ratios
> to edid_4k_modes[]. Or is there some problem with that approach?
Thanks for your time.
Since HDMI 1.4b doesn't require edid_4k_modes[] with specific aspect ratio,
modes as the same
timing in edid_4k_modes[] but with different aspect ratios are also expected to
convey VIC by
VSIF to HDMI 1.4 sink. Might can't guarantee that there wont't be any
compatibility side effect with
that approach when the sink is HDMI 1.4b .
>
> > The same situation occurs in drm_hdmi_vendor_infoframe_from_display_mode
> > and should set HDMI_VIC when the mode is one defined in HDMI 1.4b 4K
> > modes.
>
> > Yes, and we do that. "vic = drm_match_hdmi_mode(mode);"
>
> > Apart from adding the aspect ratios I don't really understand what
> > you're trying to achieve here.
>
> For HDMI 2.0 sink, drm_match_hdmi_mode() should also take aspect ratio into
> consideration.
> Once again, very appreciate for your time.
>
> > ---
> > drivers/gpu/drm/drm_edid.c | 95 --
> > 1 file changed, 92 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> > index 649cfd8b4200..0fea9bf4ec67 100644
> > --- a/drivers/gpu/drm/drm_edid.c
> > +++ b/drivers/gpu/drm/drm_edid.c
> > @@ -1306,6 +1306,37 @@ static const struct drm_display_mode edid_4k_modes[]
> > = {
> > .vrefresh = 24, },
> > };
> >
> > +/*
> > + * 4k modes of HDMI 1.4 defined in HDMI 2.0. Index using the VIC.
> > + */
> > +static const struct drm_display_mode hdmi_1_4_edid_4k_modes[] = {
> > + /* 0 - dummy, VICs start at 1 */
> > + { },
> > + /* 1 - 3840x2160@30Hz */
> > + { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
> > +3840, 4016, 4104, 4400, 0,
> > +2160, 2168, 2178, 2250, 0,
> > +DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
> > + .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
> > + /* 2 - 3840x2160@25Hz */
> > + { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
> > +3840, 4896, 4984, 5280, 0,
> > +2160, 2168, 2178, 2250, 0,
> > +DRM_MODE_FLAG_PHSYNC |
RE: [PATCH 1/1] drm/amdgpu: Fix error handling in amdgpu_ras_recovery_init
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: amd-gfx On Behalf Of Kuehling,
Felix
Sent: 2019年10月4日 6:01
To: amd-gfx@lists.freedesktop.org; Grodzovsky, Andrey
Cc: Cox, Philip
Subject: [PATCH 1/1] drm/amdgpu: Fix error handling in amdgpu_ras_recovery_init
Don't set a struct pointer to NULL before freeing its members. It's hard to see
what's happening due to a local pointer-to-pointer data aliasing con->eh_data.
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index 486568ded6d6..0e2ee5869b5f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -1542,10 +1542,10 @@ int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
release:
amdgpu_ras_release_bad_pages(adev);
free:
- con->eh_data = NULL;
kfree((*data)->bps);
kfree((*data)->bps_bo);
kfree(*data);
+ con->eh_data = NULL;
out:
DRM_WARN("Failed to initialize ras recovery!\n");
--
2.17.1
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Re: [PATCH][next] drm/amdgpu: remove redundant variable r and redundant return statement
Am 03.10.19 um 23:40 schrieb Colin King:
> From: Colin Ian King
>
> There is a return statement that is not reachable and a variable that
> is not used. Remove them.
>
> Addresses-Coverity: ("Structurally dead code")
> Fixes: de7b45babd9b ("drm/amdgpu: cleanup creating BOs at fixed location
> (v2)")
> Signed-off-by: Colin Ian King
Reviewed-by: Christian König
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index 481e4c381083..814159f15633 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -1636,7 +1636,6 @@ static void amdgpu_ttm_fw_reserve_vram_fini(struct
> amdgpu_device *adev)
> static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
> {
> uint64_t vram_size = adev->gmc.visible_vram_size;
> - int r;
>
> adev->fw_vram_usage.va = NULL;
> adev->fw_vram_usage.reserved_bo = NULL;
> @@ -1651,7 +1650,6 @@ static int amdgpu_ttm_fw_reserve_vram_init(struct
> amdgpu_device *adev)
> AMDGPU_GEM_DOMAIN_VRAM,
> >fw_vram_usage.reserved_bo,
> >fw_vram_usage.va);
> - return r;
> }
>
> /**
Re: [PATCH][next] drm/amdgpu: fix uninitialized variable pasid_mapping_needed
Am 03.10.19 um 23:52 schrieb Colin King:
> From: Colin Ian King
>
> The boolean variable pasid_mapping_needed is not initialized and
> there are code paths that do not assign it any value before it is
> is read later. Fix this by initializing pasid_mapping_needed to
> false.
>
> Addresses-Coverity: ("Uninitialized scalar variable")
> Fixes: 6817bf283b2b ("drm/amdgpu: grab the id mgr lock while accessing
> passid_mapping")
> Signed-off-by: Colin Ian King
Reviewed-by: Christian König
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index a2c797e34a29..be10e4b9a94d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -1055,7 +1055,7 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct
> amdgpu_job *job,
> id->oa_size != job->oa_size);
> bool vm_flush_needed = job->vm_needs_flush;
> struct dma_fence *fence = NULL;
> - bool pasid_mapping_needed;
> + bool pasid_mapping_needed = false;
> unsigned patch_offset = 0;
> int r;
>
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Re: [PATCH] drm/amdgpu: Use the ALIGN() macro
Am 04.10.19 um 01:39 schrieb Tuikov, Luben: Use the ALIGN() macro to set "num_dw" to a multiple of 8, i.e. lower 3 bits cleared. Signed-off-by: Luben Tuikov Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 11 ++- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 68c541e11189..73c628bc6a5b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -1923,10 +1923,7 @@ static int amdgpu_map_buffer(struct ttm_buffer_object *bo, *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE * AMDGPU_GPU_PAGE_SIZE; - num_dw = adev->mman.buffer_funcs->copy_num_dw; - while (num_dw & 0x7) - num_dw++; - + num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8); num_bytes = num_pages * 8; r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes, ); @@ -1986,11 +1983,7 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset, max_bytes = adev->mman.buffer_funcs->copy_max_bytes; num_loops = DIV_ROUND_UP(byte_count, max_bytes); - num_dw = num_loops * adev->mman.buffer_funcs->copy_num_dw; - - /* for IB padding */ - while (num_dw & 0x7) - num_dw++; + num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8); r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, ); if (r) ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 03/11] drm/amdgpu: convert amdgpu_vm_it to half closed intervals
Am 03.10.19 um 22:18 schrieb Davidlohr Bueso:
> The amdgpu_vm interval tree really wants [a, b) intervals,
NAK, we explicitly do need an [a, b[ interval here.
Regards,
Christian.
> not fully closed ones. As such convert it to use the new
> interval_tree_gen.h, and also rename the 'last' endpoint
> in the node to 'end', which is both a more suitable name
> for the half closed interval and also reduces the chances
> of missing a conversion when doing insertion or lookup.
>
> Cc: Jerome Glisse
> Cc: Alex Deucher
> Cc: "Christian König"
> Cc: Daniel Vetter
> Cc: amd-gfx@lists.freedesktop.org
> Signed-off-by: Davidlohr Bueso
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 2 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 18 ++--
> drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c| 2 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c| 3 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 46
> +++---
> 6 files changed, 36 insertions(+), 37 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> index 49b767b7238f..290bfe820890 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> @@ -756,7 +756,7 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser
> *p)
> }
>
> if ((va_start + chunk_ib->ib_bytes) >
> - (m->last + 1) * AMDGPU_GPU_PAGE_SIZE) {
> + m->end * AMDGPU_GPU_PAGE_SIZE) {
> DRM_ERROR("IB va_start+ib_bytes is invalid\n");
> return -EINVAL;
> }
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
> index 7e99f6c58c48..60b73bc4d11a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
> @@ -51,7 +51,7 @@ struct amdgpu_bo_va_mapping {
> struct list_headlist;
> struct rb_node rb;
> uint64_tstart;
> - uint64_tlast;
> + uint64_tend;
> uint64_t__subtree_last;
> uint64_toffset;
> uint64_tflags;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
> index 8227ebd0f511..c5b0e88d019c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
> @@ -247,7 +247,7 @@ TRACE_EVENT(amdgpu_vm_bo_map,
> TP_STRUCT__entry(
>__field(struct amdgpu_bo *, bo)
>__field(long, start)
> - __field(long, last)
> + __field(long, end)
>__field(u64, offset)
>__field(u64, flags)
>),
> @@ -255,12 +255,12 @@ TRACE_EVENT(amdgpu_vm_bo_map,
> TP_fast_assign(
> __entry->bo = bo_va ? bo_va->base.bo : NULL;
> __entry->start = mapping->start;
> -__entry->last = mapping->last;
> +__entry->end = mapping->end;
> __entry->offset = mapping->offset;
> __entry->flags = mapping->flags;
> ),
> - TP_printk("bo=%p, start=%lx, last=%lx, offset=%010llx, flags=%llx",
> - __entry->bo, __entry->start, __entry->last,
> + TP_printk("bo=%p, start=%lx, end=%lx, offset=%010llx, flags=%llx",
> + __entry->bo, __entry->start, __entry->end,
> __entry->offset, __entry->flags)
> );
>
> @@ -271,7 +271,7 @@ TRACE_EVENT(amdgpu_vm_bo_unmap,
> TP_STRUCT__entry(
>__field(struct amdgpu_bo *, bo)
>__field(long, start)
> - __field(long, last)
> + __field(long, end)
>__field(u64, offset)
>__field(u64, flags)
>),
> @@ -279,12 +279,12 @@ TRACE_EVENT(amdgpu_vm_bo_unmap,
> TP_fast_assign(
> __entry->bo = bo_va ? bo_va->base.bo : NULL;
> __entry->start = mapping->start;
> -__entry->last = mapping->last;
> +__entry->end = mapping->end;
> __entry->offset = mapping->offset;
> __entry->flags = mapping->flags;
> ),
> - TP_printk("bo=%p, start=%lx, last=%lx, offset=%010llx, flags=%llx",
> - __entry->bo, __entry->start,
