RE: [PATCH] drm/amdgpu/SRIOV: Only reset hw.status for target IP

[Liu, Monk]

Hi Jiange

You need to send the patch to amd-gfx for review if it intend to go drm-next 
branch

For gibraltar branch your patch is -1 by CI

_
Monk Liu|GPU Virtualization Team |AMD
[sig-cloud-gpu]

From: Zhao, Jiange 
Sent: Wednesday, October 30, 2019 10:26 AM
To: Zhao, Jiange ; amd-gfx@lists.freedesktop.org
Cc: Deng, Emily ; Liu, Monk ; Chang, 
HaiJun 
Subject: Re: [PATCH] drm/amdgpu/SRIOV: Only reset hw.status for target IP

Ping.

@Deng, Emily @Liu, Monk, 
can you help review this patch?

Thanks!
Jiange

From: Zhao, Jiange mailto:jia...@amd.com>>
Sent: Tuesday, October 29, 2019 3:43 PM
To: amd-gfx@lists.freedesktop.org 
mailto:amd-gfx@lists.freedesktop.org>>
Cc: Deng, Emily mailto:emily.d...@amd.com>>; Liu, Monk 
mailto:monk@amd.com>>; Chang, HaiJun 
mailto:haijun.ch...@amd.com>>; Zhao, Jiange 
mailto:jiange.z...@amd.com>>
Subject: [PATCH] drm/amdgpu/SRIOV: Only reset hw.status for target IP

From: Jiange Zhao mailto:jiange.z...@amd.com>>

In the old way, when doing IH hw_init, PSP, nv_common
and GMC hw.status would be reset to false, even though
their hw_init have been done. In the next step, fw_loading,
PSP would do hw_init again.

In the new way, only reset hw.status to false for the target
IP in the list. In this way, PSP will only do hw_init once.

Signed-off-by: Jiange Zhao mailto:jiange.z...@amd.com>>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 4eee40b9d0b0..ad6d2452fed9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2352,11 +2352,11 @@ static int amdgpu_device_ip_reinit_early_sriov(struct 
amdgpu_device *adev)
 for (j = 0; j < adev->num_ip_blocks; j++) {
 block = >ip_blocks[j];

-   block->status.hw = false;
 if (block->version->type != ip_order[i] ||
 !block->status.valid)
 continue;

+   block->status.hw = false;
 r = block->version->funcs->hw_init(adev);
 DRM_INFO("RE-INIT-early: %s %s\n", 
block->version->funcs->name, r?"failed":"succeeded");
 if (r)
--
2.20.1
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Re: [PATCH] drm/amdgpu/SRIOV: Only reset hw.status for target IP

[Zhao, Jiange]

Ping.

@Deng, Emily @Liu, Monk, 
can you help review this patch?

Thanks!
Jiange

From: Zhao, Jiange 
Sent: Tuesday, October 29, 2019 3:43 PM
To: amd-gfx@lists.freedesktop.org 
Cc: Deng, Emily ; Liu, Monk ; Chang, 
HaiJun ; Zhao, Jiange 
Subject: [PATCH] drm/amdgpu/SRIOV: Only reset hw.status for target IP

From: Jiange Zhao 

In the old way, when doing IH hw_init, PSP, nv_common
and GMC hw.status would be reset to false, even though
their hw_init have been done. In the next step, fw_loading,
PSP would do hw_init again.

In the new way, only reset hw.status to false for the target
IP in the list. In this way, PSP will only do hw_init once.

Signed-off-by: Jiange Zhao 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 4eee40b9d0b0..ad6d2452fed9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2352,11 +2352,11 @@ static int amdgpu_device_ip_reinit_early_sriov(struct 
amdgpu_device *adev)
 for (j = 0; j < adev->num_ip_blocks; j++) {
 block = >ip_blocks[j];

-   block->status.hw = false;
 if (block->version->type != ip_order[i] ||
 !block->status.valid)
 continue;

+   block->status.hw = false;
 r = block->version->funcs->hw_init(adev);
 DRM_INFO("RE-INIT-early: %s %s\n", 
block->version->funcs->name, r?"failed":"succeeded");
 if (r)
--
2.20.1

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Re: [PATCH v2 13/15] drm/amdgpu: Use mmu_range_insert instead of hmm_mirror

[Kuehling, Felix]

On 2019-10-28 4:10 p.m., Jason Gunthorpe wrote:
> From: Jason Gunthorpe 
>
> Remove the interval tree in the driver and rely on the tree maintained by
> the mmu_notifier for delivering mmu_notifier invalidation callbacks.
>
> For some reason amdgpu has a very complicated arrangement where it tries
> to prevent duplicate entries in the interval_tree, this is not necessary,
> each amdgpu_bo can be its own stand alone entry. interval_tree already
> allows duplicates and overlaps in the tree.
>
> Also, there is no need to remove entries upon a release callback, the
> mmu_range API safely allows objects to remain registered beyond the
> lifetime of the mm. The driver only has to stop touching the pages during
> release.
>
> Cc: Alex Deucher 
> Cc: Christian König 
> Cc: David (ChunMing) Zhou 
> Cc: amd-gfx@lists.freedesktop.org
> Signed-off-by: Jason Gunthorpe 
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu.h   |   2 +
>   .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c  |   5 +-
>   drivers/gpu/drm/amd/amdgpu/amdgpu_device.c|   1 +
>   drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c| 341 --
>   drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h|   4 -
>   drivers/gpu/drm/amd/amdgpu/amdgpu_object.h|  13 +-
>   6 files changed, 84 insertions(+), 282 deletions(-)
[snip]
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
> index 31d4deb5d29484..4ffd7b90f4d907 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
[snip]
> @@ -50,66 +50,6 @@
>   #include "amdgpu.h"
>   #include "amdgpu_amdkfd.h"
>   
> -/**
> - * struct amdgpu_mn_node
> - *
> - * @it: interval node defining start-last of the affected address range
> - * @bos: list of all BOs in the affected address range
> - *
> - * Manages all BOs which are affected of a certain range of address space.
> - */
> -struct amdgpu_mn_node {
> - struct interval_tree_node   it;
> - struct list_headbos;
> -};
> -
> -/**
> - * amdgpu_mn_destroy - destroy the HMM mirror
> - *
> - * @work: previously sheduled work item
> - *
> - * Lazy destroys the notifier from a work item
> - */
> -static void amdgpu_mn_destroy(struct work_struct *work)
> -{
> - struct amdgpu_mn *amn = container_of(work, struct amdgpu_mn, work);
> - struct amdgpu_device *adev = amn->adev;
> - struct amdgpu_mn_node *node, *next_node;
> - struct amdgpu_bo *bo, *next_bo;
> -
> - mutex_lock(>mn_lock);
> - down_write(>lock);
> - hash_del(>node);
> - rbtree_postorder_for_each_entry_safe(node, next_node,
> -  >objects.rb_root, it.rb) {
> - list_for_each_entry_safe(bo, next_bo, >bos, mn_list) {
> - bo->mn = NULL;
> - list_del_init(>mn_list);
> - }
> - kfree(node);
> - }
> - up_write(>lock);
> - mutex_unlock(>mn_lock);
> -
> - hmm_mirror_unregister(>mirror);
> - kfree(amn);
> -}
> -
> -/**
> - * amdgpu_hmm_mirror_release - callback to notify about mm destruction
> - *
> - * @mirror: the HMM mirror (mm) this callback is about
> - *
> - * Shedule a work item to lazy destroy HMM mirror.
> - */
> -static void amdgpu_hmm_mirror_release(struct hmm_mirror *mirror)
> -{
> - struct amdgpu_mn *amn = container_of(mirror, struct amdgpu_mn, mirror);
> -
> - INIT_WORK(>work, amdgpu_mn_destroy);
> - schedule_work(>work);
> -}
> -
>   /**
>* amdgpu_mn_lock - take the write side lock for this notifier
>*
> @@ -133,157 +73,86 @@ void amdgpu_mn_unlock(struct amdgpu_mn *mn)
>   }
>   
>   /**
> - * amdgpu_mn_read_lock - take the read side lock for this notifier
> - *
> - * @amn: our notifier
> - */
> -static int amdgpu_mn_read_lock(struct amdgpu_mn *amn, bool blockable)
> -{
> - if (blockable)
> - down_read(>lock);
> - else if (!down_read_trylock(>lock))
> - return -EAGAIN;
> -
> - return 0;
> -}
> -
> -/**
> - * amdgpu_mn_read_unlock - drop the read side lock for this notifier
> - *
> - * @amn: our notifier
> - */
> -static void amdgpu_mn_read_unlock(struct amdgpu_mn *amn)
> -{
> - up_read(>lock);
> -}
> -
> -/**
> - * amdgpu_mn_invalidate_node - unmap all BOs of a node
> + * amdgpu_mn_invalidate_gfx - callback to notify about mm change
>*
> - * @node: the node with the BOs to unmap
> - * @start: start of address range affected
> - * @end: end of address range affected
> + * @mrn: the range (mm) is about to update
> + * @range: details on the invalidation
>*
>* Block for operations on BOs to finish and mark pages as accessed and
>* potentially dirty.
>*/
> -static void amdgpu_mn_invalidate_node(struct amdgpu_mn_node *node,
> -   unsigned long start,
> -   unsigned long end)
> +static bool amdgpu_mn_invalidate_gfx(struct mmu_range_notifier *mrn,
> +  const 

Re: [PATCH v2 02/15] mm/mmu_notifier: add an interval tree notifier

[Kuehling, Felix]

I haven't had enough time to fully understand the deferred logic in this 
change. I spotted one problem, see comments inline.

On 2019-10-28 4:10 p.m., Jason Gunthorpe wrote:
> From: Jason Gunthorpe 
>
> Of the 13 users of mmu_notifiers, 8 of them use only
> invalidate_range_start/end() and immediately intersect the
> mmu_notifier_range with some kind of internal list of VAs.  4 use an
> interval tree (i915_gem, radeon_mn, umem_odp, hfi1). 4 use a linked list
> of some kind (scif_dma, vhost, gntdev, hmm)
>
> And the remaining 5 either don't use invalidate_range_start() or do some
> special thing with it.
>
> It turns out that building a correct scheme with an interval tree is
> pretty complicated, particularly if the use case is synchronizing against
> another thread doing get_user_pages().  Many of these implementations have
> various subtle and difficult to fix races.
>
> This approach puts the interval tree as common code at the top of the mmu
> notifier call tree and implements a shareable locking scheme.
>
> It includes:
>   - An interval tree tracking VA ranges, with per-range callbacks
>   - A read/write locking scheme for the interval tree that avoids
> sleeping in the notifier path (for OOM killer)
>   - A sequence counter based collision-retry locking scheme to tell
> device page fault that a VA range is being concurrently invalidated.
>
> This is based on various ideas:
> - hmm accumulates invalidated VA ranges and releases them when all
>invalidates are done, via active_invalidate_ranges count.
>This approach avoids having to intersect the interval tree twice (as
>umem_odp does) at the potential cost of a longer device page fault.
>
> - kvm/umem_odp use a sequence counter to drive the collision retry,
>via invalidate_seq
>
> - a deferred work todo list on unlock scheme like RTNL, via deferred_list.
>This makes adding/removing interval tree members more deterministic
>
> - seqlock, except this version makes the seqlock idea multi-holder on the
>write side by protecting it with active_invalidate_ranges and a spinlock
>
> To minimize MM overhead when only the interval tree is being used, the
> entire SRCU and hlist overheads are dropped using some simple
> branches. Similarly the interval tree overhead is dropped when in hlist
> mode.
>
> The overhead from the mandatory spinlock is broadly the same as most of
> existing users which already had a lock (or two) of some sort on the
> invalidation path.
>
> Cc: Andrea Arcangeli 
> Cc: Michal Hocko 
> Acked-by: Christian König 
> Signed-off-by: Jason Gunthorpe 
> ---
>   include/linux/mmu_notifier.h |  98 +++
>   mm/Kconfig   |   1 +
>   mm/mmu_notifier.c| 533 +--
>   3 files changed, 607 insertions(+), 25 deletions(-)
>
[snip]
> diff --git a/mm/mmu_notifier.c b/mm/mmu_notifier.c
> index 367670cfd02b7b..d02d3c8c223eb7 100644
> --- a/mm/mmu_notifier.c
> +++ b/mm/mmu_notifier.c
[snip]
>* because mm->mm_users > 0 during mmu_notifier_register and exit_mmap
> @@ -52,17 +286,24 @@ struct mmu_notifier_mm {
>* can't go away from under us as exit_mmap holds an mm_count pin
>* itself.
>*/
> -void __mmu_notifier_release(struct mm_struct *mm)
> +static void mn_hlist_release(struct mmu_notifier_mm *mmn_mm,
> +  struct mm_struct *mm)
>   {
>   struct mmu_notifier *mn;
>   int id;
>   
> + if (mmn_mm->has_interval)
> + mn_itree_release(mmn_mm, mm);
> +
> + if (hlist_empty(_mm->list))
> + return;

This seems to duplicate the conditions in __mmu_notifier_release. See my 
comments below, I think one of them is wrong. I suspect this one, 
because __mmu_notifier_release follows the same pattern as the other 
notifiers.


> +
>   /*
>* SRCU here will block mmu_notifier_unregister until
>* ->release returns.
>*/
>   id = srcu_read_lock();
> - hlist_for_each_entry_rcu(mn, >mmu_notifier_mm->list, hlist)
> + hlist_for_each_entry_rcu(mn, _mm->list, hlist)
>   /*
>* If ->release runs before mmu_notifier_unregister it must be
>* handled, as it's the only way for the driver to flush all
> @@ -72,9 +313,9 @@ void __mmu_notifier_release(struct mm_struct *mm)
>   if (mn->ops->release)
>   mn->ops->release(mn, mm);
>   
> - spin_lock(>mmu_notifier_mm->lock);
> - while (unlikely(!hlist_empty(>mmu_notifier_mm->list))) {
> - mn = hlist_entry(mm->mmu_notifier_mm->list.first,
> + spin_lock(_mm->lock);
> + while (unlikely(!hlist_empty(_mm->list))) {
> + mn = hlist_entry(mmn_mm->list.first,
>struct mmu_notifier,
>hlist);
>   /*
> @@ -85,7 +326,7 @@ void __mmu_notifier_release(struct mm_struct *mm)
>*/
>   hlist_del_init_rcu(>hlist);
>   }
> - 

21:9 monitor resolution incorrect since 4.14 kernel

[Neil Mayhew]

I have a 21:9 ultrawide monitor connected to an RX 570 with the amdgpu
driver. I'm still using the 4.14 kernel since with later kernels I can't
get the driver to allow use of the full resolution of 2560x1080 and I'm
limited to regular HD, ie 1920x1080. The latest kernel I've tried is
5.4-rc2. My distro is NixOS unstable-small. I have two other monitors
(16:9 and 16:10) connected to the same graphics card.

Is there anything I can do to work around this or try to fix it? I had a
look at the driver sources but couldn't find where the mode is set. I'm
happy to try things if someone can point me in the right direction, even
if it's just to gather better info for a bug report. Using such an old
kernel is becoming really inconvenient.

Some additional info about the situation on 4.14 that may or may not help:

1. The resolution is limited with Wayland but not with X11

2. When the system boots up the resolution is square and the image is
squished horizontally with many columns dropped, both during the boot
process and at the gdm login screen. It's not until after I log with X11
that the resolution is set correctly.

3. The output of xrandr --props is below.

TIA for any help.

--Neil

Screen 0: minimum 320 x 200, current 6160 x 1080, maximum 16384 x 16384
DP-1 connected primary 2560x1080+1920+0 (normal left inverted right x
axis y axis) 798mm x 334mm
    _MUTTER_PRESENTATION_OUTPUT: 0
    EDID:
        00001e6df9765de80500
        091c010380502278eaca95a6554ea126
        0f5054256b807140818081c0a9c0b300
        d1c08100d1cfcd4600a0a0381f403020
        3a001e4e311a003a801871382d40
        582c4500132a211e00fd0038
        4b1e5a18000a20202020202000fc
        004c4720554c545241574944450a01b5
        02031af12309070747100403011f1312
        830165030c0010008c0ad08a20e0
        2d10103e96001e4e3118295900a0
        a038274030203a001e4e311a
        
        
        00ff003830394e544b464244
        3136350a00a4
    dither: off
        supported: off, on
    audio: auto
        supported: off, on, auto
    scaling mode: None
        supported: None, Full, Center, Full aspect
    underscan vborder: 0
        range: (0, 128)
    underscan hborder: 0
        range: (0, 128)
    underscan: off
        supported: off, on, auto
    coherent: 1
        range: (0, 1)
    link-status: Good
        supported: Good, Bad
    CONNECTOR_ID: 48
        supported: 48
    non-desktop: 0
        supported: 0, 1
   2560x1080 59.98 +  74.99*
   1920x1080 74.99    59.96    50.00    59.99    59.94    59.93 
   1680x1050 59.95    59.88 

[etc.]
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[PATCH] drm/amdgpu/gmc10: properly set BANK_SELECT and FRAGMENT_SIZE

[Alex Deucher]

These were not aligned for optimal performance for GPUVM.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c | 9 +
 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c  | 9 +
 2 files changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
index b601c6740ef5..b4f32d853ca1 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
@@ -155,6 +155,15 @@ static void gfxhub_v2_0_init_cache_regs(struct 
amdgpu_device *adev)
WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2, tmp);
 
tmp = mmGCVM_L2_CNTL3_DEFAULT;
+   if (adev->gmc.translate_further) {
+   tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12);
+   tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
+   L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
+   } else {
+   tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9);
+   tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
+   L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
+   }
WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, tmp);
 
tmp = mmGCVM_L2_CNTL4_DEFAULT;
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 
b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
index 2eea702de8ee..945533634711 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
@@ -142,6 +142,15 @@ static void mmhub_v2_0_init_cache_regs(struct 
amdgpu_device *adev)
WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2, tmp);
 
tmp = mmMMVM_L2_CNTL3_DEFAULT;
+   if (adev->gmc.translate_further) {
+   tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12);
+   tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
+   L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
+   } else {
+   tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9);
+   tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
+   L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
+   }
WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL3, tmp);
 
tmp = mmMMVM_L2_CNTL4_DEFAULT;
-- 
2.23.0

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[PATCH] drm/amdgpu/renoir: move gfxoff handling into gfx9 module

[Alex Deucher]

To properly handle the option parsing ordering.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 6 ++
 drivers/gpu/drm/amd/amdgpu/soc15.c| 5 -
 2 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 9fe95e7693d5..b2b3eb75c48c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1051,6 +1051,12 @@ static void gfx_v9_0_check_if_need_gfxoff(struct 
amdgpu_device *adev)
!adev->gfx.rlc.is_rlc_v2_1))
adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
 
+   if (adev->pm.pp_feature & PP_GFXOFF_MASK)
+   adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
+   AMD_PG_SUPPORT_CP |
+   AMD_PG_SUPPORT_RLC_SMU_HS;
+   break;
+   case CHIP_RENOIR:
if (adev->pm.pp_feature & PP_GFXOFF_MASK)
adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
AMD_PG_SUPPORT_CP |
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c 
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 16c5bb75889f..25e69ea74a41 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -1263,11 +1263,6 @@ static int soc15_common_early_init(void *handle)
 AMD_PG_SUPPORT_VCN |
 AMD_PG_SUPPORT_VCN_DPG;
adev->external_rev_id = adev->rev_id + 0x91;
-
-   if (adev->pm.pp_feature & PP_GFXOFF_MASK)
-   adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
-   AMD_PG_SUPPORT_CP |
-   AMD_PG_SUPPORT_RLC_SMU_HS;
break;
default:
/* FIXME: not supported yet */
-- 
2.23.0

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[PATCH] drm/amdgpu: remove PT BOs when unmapping

[Huang, JinHuiEric]

The issue is PT BOs are not freed when unmapping VA,
which causes vram usage accumulated is huge in some
memory stress test, such as kfd big buffer stress test.
Function amdgpu_vm_bo_update_mapping() is called by both
amdgpu_vm_bo_update() and amdgpu_vm_clear_freed(). The
solution is replacing amdgpu_vm_bo_update_mapping() in
amdgpu_vm_clear_freed() with removing PT BOs function
to save vram usage.

Change-Id: Ic24e35bff8ca85265b418a642373f189d972a924
Signed-off-by: Eric Huang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 56 +-
 1 file changed, 48 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 0f4c3b2..8a480c7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1930,6 +1930,51 @@ static void amdgpu_vm_prt_fini(struct amdgpu_device 
*adev, struct amdgpu_vm *vm)
 }
 
 /**
+ * amdgpu_vm_remove_ptes - free PT BOs
+ *
+ * @adev: amdgpu device structure
+ * @vm: amdgpu vm structure
+ * @start: start of mapped range
+ * @end: end of mapped entry
+ *
+ * Free the page table level.
+ */
+static int amdgpu_vm_remove_ptes(struct amdgpu_device *adev,
+   struct amdgpu_vm *vm, uint64_t start, uint64_t end)
+{
+   struct amdgpu_vm_pt_cursor cursor;
+   unsigned shift, num_entries;
+
+   amdgpu_vm_pt_start(adev, vm, start, );
+   while (cursor.level < AMDGPU_VM_PTB) {
+   if (!amdgpu_vm_pt_descendant(adev, ))
+   return -ENOENT;
+   }
+
+   while (cursor.pfn < end) {
+   amdgpu_vm_free_table(cursor.entry);
+   num_entries = amdgpu_vm_num_entries(adev, cursor.level - 1);
+
+   if (cursor.entry != >entries[num_entries - 1]) {
+   /* Next ptb entry */
+   shift = amdgpu_vm_level_shift(adev, cursor.level - 1);
+   cursor.pfn += 1ULL << shift;
+   cursor.pfn &= ~((1ULL << shift) - 1);
+   cursor.entry++;
+   } else {
+   /* Next ptb entry in next pd0 entry */
+   amdgpu_vm_pt_ancestor();
+   shift = amdgpu_vm_level_shift(adev, cursor.level - 1);
+   cursor.pfn += 1ULL << shift;
+   cursor.pfn &= ~((1ULL << shift) - 1);
+   amdgpu_vm_pt_descendant(adev, );
+   }
+   }
+
+   return 0;
+}
+
+/**
  * amdgpu_vm_clear_freed - clear freed BOs in the PT
  *
  * @adev: amdgpu_device pointer
@@ -1949,7 +1994,6 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
  struct dma_fence **fence)
 {
struct amdgpu_bo_va_mapping *mapping;
-   uint64_t init_pte_value = 0;
struct dma_fence *f = NULL;
int r;
 
@@ -1958,13 +2002,10 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
struct amdgpu_bo_va_mapping, list);
list_del(>list);
 
-   if (vm->pte_support_ats &&
-   mapping->start < AMDGPU_GMC_HOLE_START)
-   init_pte_value = AMDGPU_PTE_DEFAULT_ATC;
+   r = amdgpu_vm_remove_ptes(adev, vm,
+   (mapping->start + 0x1ff) & (~0x1ffll),
+   (mapping->last + 1) & (~0x1ffll));
 
-   r = amdgpu_vm_bo_update_mapping(adev, vm, false, NULL,
-   mapping->start, mapping->last,
-   init_pte_value, 0, NULL, );
amdgpu_vm_free_mapping(adev, vm, mapping, f);
if (r) {
dma_fence_put(f);
@@ -1980,7 +2021,6 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
}
 
return 0;
-
 }
 
 /**
-- 
2.7.4

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Re: [PATCH v2 14/15] drm/amdgpu: Use mmu_range_notifier instead of hmm_mirror

[Jason Gunthorpe]

On Tue, Oct 29, 2019 at 07:22:37PM +, Yang, Philip wrote:
> Hi Jason,
> 
> I did quick test after merging amd-staging-drm-next with the 
> mmu_notifier branch, which includes this set changes. The test result 
> has different failures, app stuck intermittently, GUI no display etc. I 
> am understanding the changes and will try to figure out the cause.

Thanks! I'm not surprised by this given how difficult this patch was
to make. Let me know if I can assist in any way

Please ensure to run with lockdep enabled.. Your symptops sounds sort
of like deadlocking?

Regards,
Jason
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Re: [PATCH v2 14/15] drm/amdgpu: Use mmu_range_notifier instead of hmm_mirror

[Yang, Philip]

Hi Jason,

I did quick test after merging amd-staging-drm-next with the 
mmu_notifier branch, which includes this set changes. The test result 
has different failures, app stuck intermittently, GUI no display etc. I 
am understanding the changes and will try to figure out the cause.

Regards,
Philip

On 2019-10-28 4:10 p.m., Jason Gunthorpe wrote:
> From: Jason Gunthorpe 
> 
> Convert the collision-retry lock around hmm_range_fault to use the one now
> provided by the mmu_range notifier.
> 
> Although this driver does not seem to use the collision retry lock that
> hmm provides correctly, it can still be converted over to use the
> mmu_range_notifier api instead of hmm_mirror without too much trouble.
> 
> This also deletes another place where a driver is associating additional
> data (struct amdgpu_mn) with a mmu_struct.
> 
> Cc: Alex Deucher 
> Cc: Christian König 
> Cc: David (ChunMing) Zhou 
> Cc: amd-gfx@lists.freedesktop.org
> Signed-off-by: Jason Gunthorpe 
> ---
>   .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c  |   4 +
>   drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c|  14 +-
>   drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c| 148 ++
>   drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h|  49 --
>   drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c   |  76 -
>   5 files changed, 66 insertions(+), 225 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> index 47700302a08b7f..1bcedb9b477dce 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> @@ -1738,6 +1738,10 @@ static int update_invalid_user_pages(struct 
> amdkfd_process_info *process_info,
>   return ret;
>   }
>   
> + /*
> +  * FIXME: Cannot ignore the return code, must hold
> +  * notifier_lock
> +  */
>   amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm);
>   
>   /* Mark the BO as valid unless it was invalidated
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> index 2e53feed40e230..76771f5f0b60ab 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> @@ -607,8 +607,6 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser 
> *p,
>   e->tv.num_shared = 2;
>   
>   amdgpu_bo_list_get_list(p->bo_list, >validated);
> - if (p->bo_list->first_userptr != p->bo_list->num_entries)
> - p->mn = amdgpu_mn_get(p->adev, AMDGPU_MN_TYPE_GFX);
>   
>   INIT_LIST_HEAD();
>   amdgpu_vm_get_pd_bo(>vm, >validated, >vm_pd);
> @@ -1291,11 +1289,11 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser 
> *p,
>   if (r)
>   goto error_unlock;
>   
> - /* No memory allocation is allowed while holding the mn lock.
> -  * p->mn is hold until amdgpu_cs_submit is finished and fence is added
> -  * to BOs.
> + /* No memory allocation is allowed while holding the notifier lock.
> +  * The lock is held until amdgpu_cs_submit is finished and fence is
> +  * added to BOs.
>*/
> - amdgpu_mn_lock(p->mn);
> + mutex_lock(>adev->notifier_lock);
>   
>   /* If userptr are invalidated after amdgpu_cs_parser_bos(), return
>* -EAGAIN, drmIoctl in libdrm will restart the amdgpu_cs_ioctl.
> @@ -1338,13 +1336,13 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser 
> *p,
>   amdgpu_vm_move_to_lru_tail(p->adev, >vm);
>   
>   ttm_eu_fence_buffer_objects(>ticket, >validated, p->fence);
> - amdgpu_mn_unlock(p->mn);
> + mutex_unlock(>adev->notifier_lock);
>   
>   return 0;
>   
>   error_abort:
>   drm_sched_job_cleanup(>base);
> - amdgpu_mn_unlock(p->mn);
> + mutex_unlock(>adev->notifier_lock);
>   
>   error_unlock:
>   amdgpu_job_free(job);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
> index 4ffd7b90f4d907..cb718a064eb491 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
> @@ -50,28 +50,6 @@
>   #include "amdgpu.h"
>   #include "amdgpu_amdkfd.h"
>   
> -/**
> - * amdgpu_mn_lock - take the write side lock for this notifier
> - *
> - * @mn: our notifier
> - */
> -void amdgpu_mn_lock(struct amdgpu_mn *mn)
> -{
> - if (mn)
> - down_write(>lock);
> -}
> -
> -/**
> - * amdgpu_mn_unlock - drop the write side lock for this notifier
> - *
> - * @mn: our notifier
> - */
> -void amdgpu_mn_unlock(struct amdgpu_mn *mn)
> -{
> - if (mn)
> - up_write(>lock);
> -}
> -
>   /**
>* amdgpu_mn_invalidate_gfx - callback to notify about mm change
>*
> @@ -82,12 +60,19 @@ void amdgpu_mn_unlock(struct amdgpu_mn *mn)
>* potentially dirty.
>*/
>   static bool amdgpu_mn_invalidate_gfx(struct mmu_range_notifier *mrn,
> -

[bug report] drm/amd/display: move wm ranges reporting to end of init hw

[Dan Carpenter]

Hello Eric Yang,

This is a semi-automatic email about new static checker warnings.

The patch 622a88c8259e: "drm/amd/display: move wm ranges reporting to 
end of init hw" from Sep 24, 2019, leads to the following Smatch 
complaint:

drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:1308 
dcn10_init_hw()
error: we previously assumed 'dc->clk_mgr' could be null (see line 1188)

drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c
  1187  
  1188  if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
^^^
The existing code assumed this could be NULL.  (Probably we should
remove this check?).

  1189  dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
  1190  
  1191  // Initialize the dccg
  1192  if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->dccg_init)
  1193  dc->res_pool->dccg->funcs->dccg_init(res_pool->dccg);
  1194  
  1195  if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
  1196  
  1197  REG_WRITE(REFCLK_CNTL, 0);
  1198  REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, 
DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
  1199  REG_WRITE(DIO_MEM_PWR_CTRL, 0);
  1200  
  1201  if (!dc->debug.disable_clock_gate) {
  1202  /* enable all DCN clock gating */
  1203  REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
  1204  
  1205  REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
  1206  
  1207  REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
  1208  }
  1209  
  1210  //Enable ability to power gate / don't force power on 
permanently
  1211  dc->hwss.enable_power_gating_plane(hws, true);
  1212  
  1213  return;
  1214  }
  1215  
  1216  if (!dcb->funcs->is_accelerated_mode(dcb))
  1217  dc->hwss.disable_vga(dc->hwseq);
  1218  
  1219  dc->hwss.bios_golden_init(dc);
  1220  if (dc->ctx->dc_bios->fw_info_valid) {
  1221  res_pool->ref_clocks.xtalin_clock_inKhz =
  1222  
dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
  1223  
  1224  if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
  1225  if (res_pool->dccg && res_pool->hubbub) {
  1226  
  1227  
(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
  1228  
dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
  1229  
_pool->ref_clocks.dccg_ref_clock_inKhz);
  1230  
  1231  
(res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
  1232  
res_pool->ref_clocks.dccg_ref_clock_inKhz,
  1233  
_pool->ref_clocks.dchub_ref_clock_inKhz);
  1234  } else {
  1235  // Not all ASICs have DCCG sw component
  1236  
res_pool->ref_clocks.dccg_ref_clock_inKhz =
  1237  
res_pool->ref_clocks.xtalin_clock_inKhz;
  1238  
res_pool->ref_clocks.dchub_ref_clock_inKhz =
  1239  
res_pool->ref_clocks.xtalin_clock_inKhz;
  1240  }
  1241  }
  1242  } else
  1243  ASSERT_CRITICAL(false);
  1244  
  1245  for (i = 0; i < dc->link_count; i++) {
  1246  /* Power up AND update implementation according to the
  1247   * required signal (which may be different from the
  1248   * default signal on connector).
  1249   */
  1250  struct dc_link *link = dc->links[i];
  1251  
  1252  link->link_enc->funcs->hw_init(link->link_enc);
  1253  
  1254  /* Check for enabled DIG to identify enabled display */
  1255  if (link->link_enc->funcs->is_dig_enabled &&
  1256  
link->link_enc->funcs->is_dig_enabled(link->link_enc))
  1257  link->link_status.link_active = true;
  1258  }
  1259  
  1260  /* Power gate DSCs */
  1261  #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
  1262  for (i = 0; i < res_pool->res_cap->num_dsc; i++)
  1263  if (dc->hwss.dsc_pg_control != NULL)
  1264  dc->hwss.dsc_pg_control(hws, 
res_pool->dscs[i]->inst, false);
  1265  #endif
  1266  
  1267  /* If taking control over from VBIOS, we may want to optimize 
our first
  1268   * mode set, so we need to skip powering down pipes until we 
know which
  1269   * pipes we 

Re: [PATCH] drm/sched: Fix passing zero to 'PTR_ERR' warning

[Grodzovsky, Andrey]

On 10/29/19 2:03 PM, Dan Carpenter wrote:
> On Tue, Oct 29, 2019 at 11:04:44AM -0400, Andrey Grodzovsky wrote:
>> Fix a static code checker warning.
>>
>> Signed-off-by: Andrey Grodzovsky 
>> ---
>>   drivers/gpu/drm/scheduler/sched_main.c | 4 ++--
>>   1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/scheduler/sched_main.c 
>> b/drivers/gpu/drm/scheduler/sched_main.c
>> index f39b97e..898b0c9 100644
>> --- a/drivers/gpu/drm/scheduler/sched_main.c
>> +++ b/drivers/gpu/drm/scheduler/sched_main.c
>> @@ -497,7 +497,7 @@ void drm_sched_resubmit_jobs(struct drm_gpu_scheduler 
>> *sched)
>>  fence = sched->ops->run_job(s_job);
>>   
>>  if (IS_ERR_OR_NULL(fence)) {
>>  s_job->s_fence->parent = NULL;
>> -dma_fence_set_error(_fence->finished, PTR_ERR(fence));
>> +dma_fence_set_error(_fence->finished, 
>> PTR_ERR_OR_ZERO(fence));
> I feel like I should explain better.  It's generally bad to mix NULL and
> error pointers.  The situation where you would do it is when NULL is a
> special case of success.  A typical situation is you request a feature,
> like maybe logging for example:
>
>   p = get_logger();
>
> If there isn't enough memory then get_logger() returns ERR_PTR(-ENOMEM);
> but if the user has disabled logging then we can't return a valid
> pointer but it's also not an error so we return NULL.  It's a special
> case of success.
>
> In this situation sched->ops->run_job(s_job); appears to only ever
> return NULL and it's not a special case of success, it's a regular old
> error.  I guess we are transitioning from returning NULL to returning
> error pointers?


No, check patch 'drm/amdgpu: If amdgpu_ib_schedule fails return back the 
error.' , amdgpu_job_run will pack an actual error code into ERR_PTR

Andrey


>
> So we should just do something like:
>
>   fence = sched->ops->run_job(s_job);
>
>   /* FIXME: Oct 2019: Remove this code when fence can't be NULL. */
>   if (!fence)
>   fence = ERR_PTR(-EINVAL);
>
>   if (IS_ERR(fence)) {
>   ...
>
> regards,
> dan carpenter
>
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[PATCH v2] drm/sched: Fix passing zero to 'PTR_ERR' warning

[Andrey Grodzovsky]

Fix a static code checker warning.

v2: Drop PTR_ERR_OR_ZERO.

Signed-off-by: Andrey Grodzovsky 
---
 drivers/gpu/drm/scheduler/sched_main.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/scheduler/sched_main.c 
b/drivers/gpu/drm/scheduler/sched_main.c
index f39b97e..dba4390 100644
--- a/drivers/gpu/drm/scheduler/sched_main.c
+++ b/drivers/gpu/drm/scheduler/sched_main.c
@@ -496,8 +496,10 @@ void drm_sched_resubmit_jobs(struct drm_gpu_scheduler 
*sched)
fence = sched->ops->run_job(s_job);
 
if (IS_ERR_OR_NULL(fence)) {
+   if (IS_ERR(fence))
+   dma_fence_set_error(_fence->finished, 
PTR_ERR(fence));
+
s_job->s_fence->parent = NULL;
-   dma_fence_set_error(_fence->finished, PTR_ERR(fence));
} else {
s_job->s_fence->parent = fence;
}
@@ -741,8 +743,9 @@ static int drm_sched_main(void *param)
  r);
dma_fence_put(fence);
} else {
+   if (IS_ERR(fence))
+   dma_fence_set_error(_fence->finished, 
PTR_ERR(fence));
 
-   dma_fence_set_error(_fence->finished, PTR_ERR(fence));
drm_sched_process_job(NULL, _job->cb);
}
 
-- 
2.7.4

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Re: [PATCH] drm/sched: Fix passing zero to 'PTR_ERR' warning

[Dan Carpenter]

On Tue, Oct 29, 2019 at 11:04:44AM -0400, Andrey Grodzovsky wrote:
> Fix a static code checker warning.
> 
> Signed-off-by: Andrey Grodzovsky 
> ---
>  drivers/gpu/drm/scheduler/sched_main.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/scheduler/sched_main.c 
> b/drivers/gpu/drm/scheduler/sched_main.c
> index f39b97e..898b0c9 100644
> --- a/drivers/gpu/drm/scheduler/sched_main.c
> +++ b/drivers/gpu/drm/scheduler/sched_main.c
> @@ -497,7 +497,7 @@ void drm_sched_resubmit_jobs(struct drm_gpu_scheduler 
> *sched)
>   fence = sched->ops->run_job(s_job);
>  
>   if (IS_ERR_OR_NULL(fence)) {
>   s_job->s_fence->parent = NULL;
> - dma_fence_set_error(_fence->finished, PTR_ERR(fence));
> + dma_fence_set_error(_fence->finished, 
> PTR_ERR_OR_ZERO(fence));

I feel like I should explain better.  It's generally bad to mix NULL and
error pointers.  The situation where you would do it is when NULL is a
special case of success.  A typical situation is you request a feature,
like maybe logging for example:

p = get_logger();

If there isn't enough memory then get_logger() returns ERR_PTR(-ENOMEM);
but if the user has disabled logging then we can't return a valid
pointer but it's also not an error so we return NULL.  It's a special
case of success.

In this situation sched->ops->run_job(s_job); appears to only ever
return NULL and it's not a special case of success, it's a regular old
error.  I guess we are transitioning from returning NULL to returning
error pointers?

So we should just do something like:

fence = sched->ops->run_job(s_job);

/* FIXME: Oct 2019: Remove this code when fence can't be NULL. */
if (!fence)
fence = ERR_PTR(-EINVAL);

if (IS_ERR(fence)) {
...

regards,
dan carpenter

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Re: [PATCH] drm/sched: Fix passing zero to 'PTR_ERR' warning

[Dan Carpenter]

On Tue, Oct 29, 2019 at 11:04:44AM -0400, Andrey Grodzovsky wrote:
> Fix a static code checker warning.
> 
> Signed-off-by: Andrey Grodzovsky 
> ---
>  drivers/gpu/drm/scheduler/sched_main.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/scheduler/sched_main.c 
> b/drivers/gpu/drm/scheduler/sched_main.c
> index f39b97e..898b0c9 100644
> --- a/drivers/gpu/drm/scheduler/sched_main.c
> +++ b/drivers/gpu/drm/scheduler/sched_main.c
> @@ -497,7 +497,7 @@ void drm_sched_resubmit_jobs(struct drm_gpu_scheduler 
> *sched)
>  
>   if (IS_ERR_OR_NULL(fence)) {
>   s_job->s_fence->parent = NULL;
> - dma_fence_set_error(_fence->finished, PTR_ERR(fence));
> + dma_fence_set_error(_fence->finished, 
> PTR_ERR_OR_ZERO(fence));

This will silence the static checker warning, but it will still trigger
a WARN_ON().  And it sort of has inspired me to generate a new warning
because that's not how PTR_ERR_OR_ZERO() is supposed to be used.  :P

PTR_ERR_OR_ZERO() is short hand for this situation:

-   if (IS_ERR(fence))
-   return PTR_ERR(fence);
-   return 0;
+   return PTR_ERR_OR_ZERO(fence);

regards,
dan carpenter


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Re: [PATCH v2 12/15] drm/amdgpu: Call find_vma under mmap_sem

[Jason Gunthorpe]

On Tue, Oct 29, 2019 at 04:28:43PM +, Kuehling, Felix wrote:
> On 2019-10-28 4:10 p.m., Jason Gunthorpe wrote:
> > From: Jason Gunthorpe 
> >
> > find_vma() must be called under the mmap_sem, reorganize this code to
> > do the vma check after entering the lock.
> >
> > Further, fix the unlocked use of struct task_struct's mm, instead use
> > the mm from hmm_mirror which has an active mm_grab. Also the mm_grab
> > must be converted to a mm_get before acquiring mmap_sem or calling
> > find_vma().
> >
> > Fixes: 66c45500bfdc ("drm/amdgpu: use new HMM APIs and helpers")
> > Fixes: 0919195f2b0d ("drm/amdgpu: Enable amdgpu_ttm_tt_get_user_pages in 
> > worker threads")
> > Cc: Alex Deucher 
> > Cc: Christian König 
> > Cc: David (ChunMing) Zhou 
> > Cc: amd-gfx@lists.freedesktop.org
> > Signed-off-by: Jason Gunthorpe 
> 
> One question inline to confirm my understanding. Otherwise this patch is
> 
> Reviewed-by: Felix Kuehling 

Thanks

> > -   if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&
> > -   vma->vm_file)) {
> > -   r = -EPERM;
> > -   goto out;
> > -   }
> > +   mm = mirror->hmm->mmu_notifier.mm;
> > +   if (!mmget_not_zero(mm)) /* Happens during process shutdown */
> 
> This works because mirror->hmm->mmu_notifier holds an mmgrab reference 
> to the mm?

Yes, this makes sure the mm pointer remains valid

> So the MM will not just go away, but if the mmget refcount is 0, it
> means the mm is marked for destruction and shouldn't be used any
> more.

Not just marked for destruction, but that another thread is
progressing or finished release().

The other detail here is that in general you can't get the mmap_sem
without also having a mmget as exit_mmap() does not lock the mmap_sem
in some places where it alters the datastructures. ie racing
find_vma() with exit_mmap() is not allowed.

This means we have to hold the mmget across the hmm_range_fault(), but
we can drop the mmget and then test mmu_range_read_retry() under the
driver lock. It will return true if the mmget refcount has gone to
zero in the mean time.

But I think this is probably a poor driver design, a driver should
just hold the mmget() until it has completed establishing the shadow
PTEs, as it is hard to see a reason not to..

Jason
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Re: [PATCH v2 12/15] drm/amdgpu: Call find_vma under mmap_sem

[Christian König]

Am 29.10.19 um 17:28 schrieb Kuehling, Felix:

On 2019-10-28 4:10 p.m., Jason Gunthorpe wrote:

From: Jason Gunthorpe 

find_vma() must be called under the mmap_sem, reorganize this code to
do the vma check after entering the lock.

Further, fix the unlocked use of struct task_struct's mm, instead use
the mm from hmm_mirror which has an active mm_grab. Also the mm_grab
must be converted to a mm_get before acquiring mmap_sem or calling
find_vma().

Fixes: 66c45500bfdc ("drm/amdgpu: use new HMM APIs and helpers")
Fixes: 0919195f2b0d ("drm/amdgpu: Enable amdgpu_ttm_tt_get_user_pages in worker 
threads")
Cc: Alex Deucher 
Cc: Christian König 
Cc: David (ChunMing) Zhou 
Cc: amd-gfx@lists.freedesktop.org
Signed-off-by: Jason Gunthorpe 

One question inline to confirm my understanding. Otherwise this patch is

Reviewed-by: Felix Kuehling 



---
   drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 37 ++---
   1 file changed, 21 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index dff41d0a85fe96..c0e41f1f0c2365 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -35,6 +35,7 @@
   #include 
   #include 
   #include 
+#include 
   #include 
   #include 
   #include 
@@ -788,7 +789,7 @@ int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, 
struct page **pages)
struct hmm_mirror *mirror = bo->mn ? >mn->mirror : NULL;
struct ttm_tt *ttm = bo->tbo.ttm;
struct amdgpu_ttm_tt *gtt = (void *)ttm;
-   struct mm_struct *mm = gtt->usertask->mm;
+   struct mm_struct *mm;
unsigned long start = gtt->userptr;
struct vm_area_struct *vma;
struct hmm_range *range;
@@ -796,25 +797,14 @@ int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, 
struct page **pages)
uint64_t *pfns;
int r = 0;
   
-	if (!mm) /* Happens during process shutdown */

-   return -ESRCH;
-
if (unlikely(!mirror)) {
DRM_DEBUG_DRIVER("Failed to get hmm_mirror\n");
-   r = -EFAULT;
-   goto out;
+   return -EFAULT;
}
   
-	vma = find_vma(mm, start);

-   if (unlikely(!vma || start < vma->vm_start)) {
-   r = -EFAULT;
-   goto out;
-   }
-   if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&
-   vma->vm_file)) {
-   r = -EPERM;
-   goto out;
-   }
+   mm = mirror->hmm->mmu_notifier.mm;
+   if (!mmget_not_zero(mm)) /* Happens during process shutdown */

This works because mirror->hmm->mmu_notifier holds an mmgrab reference
to the mm? So the MM will not just go away, but if the mmget refcount is
0, it means the mm is marked for destruction and shouldn't be used any more.


Yes, exactly. That is a rather common pattern, one reference count for 
the functionality and one for the structure.


When the functionality is gone the structure might still be alive for 
some reason. TTM and a couple of other structures use the same approach.


Christian.





+   return -ESRCH;
   
   	range = kzalloc(sizeof(*range), GFP_KERNEL);

if (unlikely(!range)) {
@@ -847,6 +837,17 @@ int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, 
struct page **pages)
hmm_range_wait_until_valid(range, HMM_RANGE_DEFAULT_TIMEOUT);
   
   	down_read(>mmap_sem);

+   vma = find_vma(mm, start);
+   if (unlikely(!vma || start < vma->vm_start)) {
+   r = -EFAULT;
+   goto out_unlock;
+   }
+   if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&
+   vma->vm_file)) {
+   r = -EPERM;
+   goto out_unlock;
+   }
+
r = hmm_range_fault(range, 0);
up_read(>mmap_sem);
   
@@ -865,15 +866,19 @@ int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages)

}
   
   	gtt->range = range;

+   mmput(mm);
   
   	return 0;
   
+out_unlock:

+   up_read(>mmap_sem);
   out_free_pfns:
hmm_range_unregister(range);
kvfree(pfns);
   out_free_ranges:
kfree(range);
   out:
+   mmput(mm);
return r;
   }
   

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Re: [PATCH] drm/sched: Fix passing zero to 'PTR_ERR' warning

[Christian König]

Am 29.10.19 um 16:04 schrieb Andrey Grodzovsky:

Fix a static code checker warning.

Signed-off-by: Andrey Grodzovsky 


Well that one was even new to me.

Patch is Reviewed-by: Christian König 


---
  drivers/gpu/drm/scheduler/sched_main.c | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/scheduler/sched_main.c 
b/drivers/gpu/drm/scheduler/sched_main.c
index f39b97e..898b0c9 100644
--- a/drivers/gpu/drm/scheduler/sched_main.c
+++ b/drivers/gpu/drm/scheduler/sched_main.c
@@ -497,7 +497,7 @@ void drm_sched_resubmit_jobs(struct drm_gpu_scheduler 
*sched)
  
  		if (IS_ERR_OR_NULL(fence)) {

s_job->s_fence->parent = NULL;
-   dma_fence_set_error(_fence->finished, PTR_ERR(fence));
+   dma_fence_set_error(_fence->finished, 
PTR_ERR_OR_ZERO(fence));
} else {
s_job->s_fence->parent = fence;
}
@@ -742,7 +742,7 @@ static int drm_sched_main(void *param)
dma_fence_put(fence);
} else {
  
-			dma_fence_set_error(_fence->finished, PTR_ERR(fence));

+   dma_fence_set_error(_fence->finished, 
PTR_ERR_OR_ZERO(fence));
drm_sched_process_job(NULL, _job->cb);
}
  


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Re: [PATCH v2 12/15] drm/amdgpu: Call find_vma under mmap_sem

[Kuehling, Felix]

On 2019-10-28 4:10 p.m., Jason Gunthorpe wrote:
> From: Jason Gunthorpe 
>
> find_vma() must be called under the mmap_sem, reorganize this code to
> do the vma check after entering the lock.
>
> Further, fix the unlocked use of struct task_struct's mm, instead use
> the mm from hmm_mirror which has an active mm_grab. Also the mm_grab
> must be converted to a mm_get before acquiring mmap_sem or calling
> find_vma().
>
> Fixes: 66c45500bfdc ("drm/amdgpu: use new HMM APIs and helpers")
> Fixes: 0919195f2b0d ("drm/amdgpu: Enable amdgpu_ttm_tt_get_user_pages in 
> worker threads")
> Cc: Alex Deucher 
> Cc: Christian König 
> Cc: David (ChunMing) Zhou 
> Cc: amd-gfx@lists.freedesktop.org
> Signed-off-by: Jason Gunthorpe 

One question inline to confirm my understanding. Otherwise this patch is

Reviewed-by: Felix Kuehling 


> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 37 ++---
>   1 file changed, 21 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index dff41d0a85fe96..c0e41f1f0c2365 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -35,6 +35,7 @@
>   #include 
>   #include 
>   #include 
> +#include 
>   #include 
>   #include 
>   #include 
> @@ -788,7 +789,7 @@ int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, 
> struct page **pages)
>   struct hmm_mirror *mirror = bo->mn ? >mn->mirror : NULL;
>   struct ttm_tt *ttm = bo->tbo.ttm;
>   struct amdgpu_ttm_tt *gtt = (void *)ttm;
> - struct mm_struct *mm = gtt->usertask->mm;
> + struct mm_struct *mm;
>   unsigned long start = gtt->userptr;
>   struct vm_area_struct *vma;
>   struct hmm_range *range;
> @@ -796,25 +797,14 @@ int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, 
> struct page **pages)
>   uint64_t *pfns;
>   int r = 0;
>   
> - if (!mm) /* Happens during process shutdown */
> - return -ESRCH;
> -
>   if (unlikely(!mirror)) {
>   DRM_DEBUG_DRIVER("Failed to get hmm_mirror\n");
> - r = -EFAULT;
> - goto out;
> + return -EFAULT;
>   }
>   
> - vma = find_vma(mm, start);
> - if (unlikely(!vma || start < vma->vm_start)) {
> - r = -EFAULT;
> - goto out;
> - }
> - if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&
> - vma->vm_file)) {
> - r = -EPERM;
> - goto out;
> - }
> + mm = mirror->hmm->mmu_notifier.mm;
> + if (!mmget_not_zero(mm)) /* Happens during process shutdown */

This works because mirror->hmm->mmu_notifier holds an mmgrab reference 
to the mm? So the MM will not just go away, but if the mmget refcount is 
0, it means the mm is marked for destruction and shouldn't be used any more.


> + return -ESRCH;
>   
>   range = kzalloc(sizeof(*range), GFP_KERNEL);
>   if (unlikely(!range)) {
> @@ -847,6 +837,17 @@ int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, 
> struct page **pages)
>   hmm_range_wait_until_valid(range, HMM_RANGE_DEFAULT_TIMEOUT);
>   
>   down_read(>mmap_sem);
> + vma = find_vma(mm, start);
> + if (unlikely(!vma || start < vma->vm_start)) {
> + r = -EFAULT;
> + goto out_unlock;
> + }
> + if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&
> + vma->vm_file)) {
> + r = -EPERM;
> + goto out_unlock;
> + }
> +
>   r = hmm_range_fault(range, 0);
>   up_read(>mmap_sem);
>   
> @@ -865,15 +866,19 @@ int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, 
> struct page **pages)
>   }
>   
>   gtt->range = range;
> + mmput(mm);
>   
>   return 0;
>   
> +out_unlock:
> + up_read(>mmap_sem);
>   out_free_pfns:
>   hmm_range_unregister(range);
>   kvfree(pfns);
>   out_free_ranges:
>   kfree(range);
>   out:
> + mmput(mm);
>   return r;
>   }
>   
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[PATCH] drm/sched: Fix passing zero to 'PTR_ERR' warning

[Andrey Grodzovsky]

Fix a static code checker warning.

Signed-off-by: Andrey Grodzovsky 
---
 drivers/gpu/drm/scheduler/sched_main.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/scheduler/sched_main.c 
b/drivers/gpu/drm/scheduler/sched_main.c
index f39b97e..898b0c9 100644
--- a/drivers/gpu/drm/scheduler/sched_main.c
+++ b/drivers/gpu/drm/scheduler/sched_main.c
@@ -497,7 +497,7 @@ void drm_sched_resubmit_jobs(struct drm_gpu_scheduler 
*sched)
 
if (IS_ERR_OR_NULL(fence)) {
s_job->s_fence->parent = NULL;
-   dma_fence_set_error(_fence->finished, PTR_ERR(fence));
+   dma_fence_set_error(_fence->finished, 
PTR_ERR_OR_ZERO(fence));
} else {
s_job->s_fence->parent = fence;
}
@@ -742,7 +742,7 @@ static int drm_sched_main(void *param)
dma_fence_put(fence);
} else {
 
-   dma_fence_set_error(_fence->finished, PTR_ERR(fence));
+   dma_fence_set_error(_fence->finished, 
PTR_ERR_OR_ZERO(fence));
drm_sched_process_job(NULL, _job->cb);
}
 
-- 
2.7.4

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Re: [PATCH v2 13/15] drm/amdgpu: Use mmu_range_insert instead of hmm_mirror

[Jason Gunthorpe]

On Tue, Oct 29, 2019 at 07:51:30AM +, Koenig, Christian wrote:
> > +static bool amdgpu_mn_invalidate_gfx(struct mmu_range_notifier *mrn,
> > +const struct mmu_notifier_range *range)
> >   {
> > -   struct amdgpu_bo *bo;
> > +   struct amdgpu_bo *bo = container_of(mrn, struct amdgpu_bo, notifier);
> > +   struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
> > long r;
> >   
> > -   list_for_each_entry(bo, >bos, mn_list) {
> > -
> > -   if (!amdgpu_ttm_tt_affect_userptr(bo->tbo.ttm, start, end))
> > -   continue;
> > -
> > -   r = dma_resv_wait_timeout_rcu(bo->tbo.base.resv,
> > -   true, false, MAX_SCHEDULE_TIMEOUT);
> > -   if (r <= 0)
> > -   DRM_ERROR("(%ld) failed to wait for user bo\n", r);
> > -   }
> > +   /* FIXME: Is this necessary? */
> 
> Most likely not.
> 
> Christian.
> 
> > +   if (!amdgpu_ttm_tt_affect_userptr(bo->tbo.ttm, range->start,
> > + range->end))
> > +   return true;

So is the bo->tbo.mem.num_pages == bo->tbo.ttm.num_pages always?

And userptr can't be zero here, or at least it doesn't matter if it is?

> > +static bool amdgpu_mn_invalidate_hsa(struct mmu_range_notifier *mrn,
> > +const struct mmu_notifier_range *range)
> >   {
> > -   struct amdgpu_mn *amn = container_of(mirror, struct amdgpu_mn, mirror);
> > -   unsigned long start = update->start;
> > -   unsigned long end = update->end;
> > -   bool blockable = mmu_notifier_range_blockable(update);
> > -   struct interval_tree_node *it;
> > -
> > -   /* notification is exclusive, but interval is inclusive */
> > -   end -= 1;
> > -
> > -   /* TODO we should be able to split locking for interval tree and
> > -* amdgpu_mn_invalidate_node
> > -*/
> > -   if (amdgpu_mn_read_lock(amn, blockable))
> > -   return -EAGAIN;
> > -
> > -   it = interval_tree_iter_first(>objects, start, end);
> > -   while (it) {
> > -   struct amdgpu_mn_node *node;
> > -
> > -   if (!blockable) {
> > -   amdgpu_mn_read_unlock(amn);
> > -   return -EAGAIN;
> > -   }
> > +   struct amdgpu_bo *bo = container_of(mrn, struct amdgpu_bo, notifier);
> > +   struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
> >   
> > -   node = container_of(it, struct amdgpu_mn_node, it);
> > -   it = interval_tree_iter_next(it, start, end);
> > +   /* FIXME: Is this necessary? */
> > +   if (!amdgpu_ttm_tt_affect_userptr(bo->tbo.ttm, range->start,
> > + range->end))
> > +   return true;
> >   
> > -   amdgpu_mn_invalidate_node(node, start, end);
> > -   }

This one too right?

Jason
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[PATCH 09/13] drm/amd/display: Validate DSC caps on MST endpoints

[mikita.lipski]

From: David Francis 

During MST mode enumeration, if a new dc_sink is created,
populate it with dsc caps as appropriate.

Use drm_dp_mst_dsc_aux_for_port to get the raw caps,
then parse them onto dc_sink with dc_dsc_parse_dsc_dpcd.

Reviewed-by: Wenjing Liu 
Signed-off-by: David Francis 
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h |  3 ++
 .../display/amdgpu_dm/amdgpu_dm_mst_types.c   | 31 ++-
 2 files changed, 33 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index 910c8598faf9..37ca191a5b1c 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -279,6 +279,9 @@ struct amdgpu_dm_connector {
struct drm_dp_mst_port *port;
struct amdgpu_dm_connector *mst_port;
struct amdgpu_encoder *mst_encoder;
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+   struct drm_dp_aux *dsc_aux;
+#endif
 
/* TODO see if we can merge with ddc_bus or make a dm_connector */
struct amdgpu_i2c_adapter *i2c;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 1a17ea1b42e0..804a00082bee 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -25,6 +25,7 @@
 
 #include 
 #include 
+#include 
 #include "dm_services.h"
 #include "amdgpu.h"
 #include "amdgpu_dm.h"
@@ -188,6 +189,28 @@ static const struct drm_connector_funcs 
dm_dp_mst_connector_funcs = {
.early_unregister = amdgpu_dm_mst_connector_early_unregister,
 };
 
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector 
*aconnector)
+{
+   struct dc_sink *dc_sink = aconnector->dc_sink;
+   struct drm_dp_mst_port *port = aconnector->port;
+   u8 dsc_caps[16] = { 0 };
+
+   aconnector->dsc_aux = drm_dp_mst_dsc_aux_for_port(port);
+
+   if (!aconnector->dsc_aux)
+   return false;
+
+   if (drm_dp_dpcd_read(aconnector->dsc_aux, DP_DSC_SUPPORT, dsc_caps, 16) 
< 0)
+   return false;
+
+   if (!dc_dsc_parse_dsc_dpcd(dsc_caps, NULL, 
_sink->sink_dsc_caps.dsc_dec_caps))
+   return false;
+
+   return true;
+}
+#endif
+
 static int dm_dp_mst_get_modes(struct drm_connector *connector)
 {
struct amdgpu_dm_connector *aconnector = 
to_amdgpu_dm_connector(connector);
@@ -230,10 +253,16 @@ static int dm_dp_mst_get_modes(struct drm_connector 
*connector)
/* dc_link_add_remote_sink returns a new reference */
aconnector->dc_sink = dc_sink;
 
-   if (aconnector->dc_sink)
+   if (aconnector->dc_sink) {
amdgpu_dm_update_freesync_caps(
connector, aconnector->edid);
 
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+   if (!validate_dsc_caps_on_connector(aconnector))
+   memset(>dc_sink->sink_dsc_caps,
+  0, 
sizeof(aconnector->dc_sink->sink_dsc_caps));
+#endif
+   }
}
 
drm_connector_update_edid_property(
-- 
2.17.1

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[PATCH 05/13] drm/dp_mst: Fill branch->num_ports

[mikita.lipski]

From: David Francis 

This field on drm_dp_mst_branch was never filled

It is initialized to zero when the port is kzallocced.
When a port is added to the list, increment num_ports,
and when a port is removed from the list, decrement num_ports.

v2: remember to decrement on port removal
v3: don't explicitly init to 0

Reviewed-by: Lyude Paul 
Reviewed-by: Harry Wentland 
Signed-off-by: David Francis 
---
 drivers/gpu/drm/drm_dp_mst_topology.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c 
b/drivers/gpu/drm/drm_dp_mst_topology.c
index 9f3604355705..502923c24450 100644
--- a/drivers/gpu/drm/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/drm_dp_mst_topology.c
@@ -1669,6 +1669,7 @@ static void drm_dp_add_port(struct drm_dp_mst_branch 
*mstb,
mutex_lock(>mgr->lock);
drm_dp_mst_topology_get_port(port);
list_add(>next, >ports);
+   mstb->num_ports++;
mutex_unlock(>mgr->lock);
}
 
@@ -1703,6 +1704,7 @@ static void drm_dp_add_port(struct drm_dp_mst_branch 
*mstb,
/* remove it from the port list */
mutex_lock(>mgr->lock);
list_del(>next);
+   mstb->num_ports--;
mutex_unlock(>mgr->lock);
/* drop port list reference */
drm_dp_mst_topology_put_port(port);
-- 
2.17.1

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[PATCH 02/13] drm/dp_mst: Add PBN calculation for DSC modes

[mikita.lipski]

From: David Francis 

With DSC, bpp can be fractional in multiples of 1/16.

Change drm_dp_calc_pbn_mode to reflect this, adding a new
parameter bool dsc. When this parameter is true, treat the
bpp parameter as having units not of bits per pixel, but
1/16 of a bit per pixel

v2: Don't add separate function for this

Reviewed-by: Manasi Navare 
Reviewed-by: Lyude Paul 
Reviewed-by: Harry Wentland 
Signed-off-by: David Francis 
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c|  2 +-
 drivers/gpu/drm/drm_dp_mst_topology.c| 16 
 drivers/gpu/drm/i915/display/intel_dp_mst.c  |  3 ++-
 drivers/gpu/drm/nouveau/dispnv50/disp.c  |  3 ++-
 drivers/gpu/drm/radeon/radeon_dp_mst.c   |  2 +-
 include/drm/drm_dp_mst_helper.h  |  3 +--
 6 files changed, 19 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 28f6b93ab371..0909ace4f1b4 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4633,7 +4633,7 @@ static int dm_encoder_helper_atomic_check(struct 
drm_encoder *encoder,
if (!state->duplicated) {
bpp = (uint8_t)connector->display_info.bpc * 3;
clock = adjusted_mode->clock;
-   dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp);
+   dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, 
false);
}
dm_new_connector_state->vcpi_slots = 
drm_dp_atomic_find_vcpi_slots(state,
   mst_mgr,
diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c 
b/drivers/gpu/drm/drm_dp_mst_topology.c
index 82add736e17d..3e7b7553cf4d 100644
--- a/drivers/gpu/drm/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/drm_dp_mst_topology.c
@@ -3534,10 +3534,11 @@ EXPORT_SYMBOL(drm_dp_check_act_status);
  * drm_dp_calc_pbn_mode() - Calculate the PBN for a mode.
  * @clock: dot clock for the mode
  * @bpp: bpp for the mode.
+ * @dsc: DSC mode. If true, bpp has units of 1/16 of a bit per pixel
  *
  * This uses the formula in the spec to calculate the PBN value for a mode.
  */
-int drm_dp_calc_pbn_mode(int clock, int bpp)
+int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc)
 {
u64 kbps;
s64 peak_kbps;
@@ -3555,11 +3556,18 @@ int drm_dp_calc_pbn_mode(int clock, int bpp)
 * peak_kbps *= (1006/1000)
 * peak_kbps *= (64/54)
 * peak_kbps *= 8convert to bytes
+*
+* If the bpp is in units of 1/16, further divide by 16. Put this
+* factor in the numerator rather than the denominator to avoid
+* integer overflow
 */
 
numerator = 64 * 1006;
denominator = 54 * 8 * 1000 * 1000;
 
+   if (dsc)
+   numerator /= 16;
+
kbps *= numerator;
peak_kbps = drm_fixp_from_fraction(kbps, denominator);
 
@@ -3570,19 +3578,19 @@ EXPORT_SYMBOL(drm_dp_calc_pbn_mode);
 static int test_calc_pbn_mode(void)
 {
int ret;
-   ret = drm_dp_calc_pbn_mode(154000, 30);
+   ret = drm_dp_calc_pbn_mode(154000, 30, false);
if (ret != 689) {
DRM_ERROR("PBN calculation test failed - clock %d, bpp %d, 
expected PBN %d, actual PBN %d.\n",
154000, 30, 689, ret);
return -EINVAL;
}
-   ret = drm_dp_calc_pbn_mode(234000, 30);
+   ret = drm_dp_calc_pbn_mode(234000, 30, false);
if (ret != 1047) {
DRM_ERROR("PBN calculation test failed - clock %d, bpp %d, 
expected PBN %d, actual PBN %d.\n",
234000, 30, 1047, ret);
return -EINVAL;
}
-   ret = drm_dp_calc_pbn_mode(297000, 24);
+   ret = drm_dp_calc_pbn_mode(297000, 24, false);
if (ret != 1063) {
DRM_ERROR("PBN calculation test failed - clock %d, bpp %d, 
expected PBN %d, actual PBN %d.\n",
297000, 24, 1063, ret);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c 
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 2c5ac3dd647f..dfac450841df 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -61,7 +61,8 @@ static int intel_dp_mst_compute_link_config(struct 
intel_encoder *encoder,
crtc_state->pipe_bpp = bpp;
 
crtc_state->pbn = 
drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock,
-  crtc_state->pipe_bpp);
+  crtc_state->pipe_bpp,
+  false);
 
slots = drm_dp_atomic_find_vcpi_slots(state, _dp->mst_mgr,
  port, crtc_state->pbn);
diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c 

[PATCH 10/13] drm/amd/display: Write DSC enable to MST DPCD

[mikita.lipski]

From: David Francis 

Rework the dm_helpers_write_dsc_enable callback to
handle the MST case.

Use the cached dsc_aux field.

Reviewed-by: Wenjing Liu 
Signed-off-by: David Francis 
---
 .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 19 ++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index 1b2cc85b4815..2144b65f4806 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -37,6 +37,7 @@
 #include "dc.h"
 #include "amdgpu_dm.h"
 #include "amdgpu_dm_irq.h"
+#include "amdgpu_dm_mst_types.h"
 
 #include "dm_helpers.h"
 
@@ -521,8 +522,24 @@ bool dm_helpers_dp_write_dsc_enable(
 )
 {
uint8_t enable_dsc = enable ? 1 : 0;
+   struct amdgpu_dm_connector *aconnector;
+
+   if (!stream)
+   return false;
+
+   if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
+   aconnector = (struct amdgpu_dm_connector 
*)stream->dm_stream_context;
+
+   if (!aconnector->dsc_aux)
+   return false;
+
+   return (drm_dp_dpcd_write(aconnector->dsc_aux, DP_DSC_ENABLE, 
_dsc, 1) >= 0);
+   }
+
+   if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT)
+   return dm_helpers_dp_write_dpcd(ctx, stream->link, 
DP_DSC_ENABLE, _dsc, 1);
 
-   return dm_helpers_dp_write_dpcd(ctx, stream->sink->link, DP_DSC_ENABLE, 
_dsc, 1);
+   return false;
 }
 #endif
 
-- 
2.17.1

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[PATCH 13/13] drm/amd/display: Recalculate VCPI slots for new DSC connectors

[mikita.lipski]

From: Mikita Lipski 

Since for DSC MST connector's PBN is claculated differently
due to compression, we have to recalculate both PBN and
VCPI slots for that connector.

The function iterates through all the active streams to
find, which have DSC enabled, then recalculates PBN for
it and calls drm_dp_helper_update_vcpi_slots_for_dsc to
update connector's VCPI slots.

Cc: Jerry Zuo 
Cc: Harry Wentland 
Cc: Lyude Paul 
Signed-off-by: Mikita Lipski 
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 71 +--
 1 file changed, 66 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index adbd28e17947..664def4e4652 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4608,6 +4608,27 @@ static void dm_encoder_helper_disable(struct drm_encoder 
*encoder)
 
 }
 
+static int convert_dc_color_depth_into_bpc (enum dc_color_depth 
display_color_depth)
+{
+   switch (display_color_depth) {
+   case COLOR_DEPTH_666:
+   return 6;
+   case COLOR_DEPTH_888:
+   return 8;
+   case COLOR_DEPTH_101010:
+   return 10;
+   case COLOR_DEPTH_121212:
+   return 12;
+   case COLOR_DEPTH_141414:
+   return 14;
+   case COLOR_DEPTH_161616:
+   return 16;
+   default:
+   break;
+   }
+   return 0;
+}
+
 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
  struct drm_crtc_state *crtc_state,
  struct drm_connector_state 
*conn_state)
@@ -4651,6 +4672,43 @@ const struct drm_encoder_helper_funcs 
amdgpu_dm_encoder_helper_funcs = {
.atomic_check = dm_encoder_helper_atomic_check
 };
 
+static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
+   struct dc_state *dc_state)
+{
+   struct dc_stream_state *stream;
+   struct amdgpu_dm_connector *aconnector;
+   struct dm_connector_state *dm_conn_state;
+   int i = 0, clock = 0, bpp = 0;
+
+   for (i = 0; i < dc_state->stream_count; i++) {
+
+   stream = dc_state->streams[i];
+
+   if (!stream)
+   continue;
+
+   aconnector = (struct amdgpu_dm_connector 
*)stream->dm_stream_context;
+   dm_conn_state = to_dm_connector_state(aconnector->base.state);
+
+   if (!aconnector->port)
+   continue;
+
+   if (stream->timing.flags.DSC != 1)
+   continue;
+
+   bpp = 
convert_dc_color_depth_into_bpc(stream->timing.display_color_depth)* 3;
+   clock = stream->timing.pix_clk_100hz / 10;
+
+   dm_conn_state->pbn =  drm_dp_calc_pbn_mode(clock, bpp, true);
+
+   dm_conn_state->vcpi_slots = 
drm_dp_helper_update_vcpi_slots_for_dsc(state, aconnector->port, 
dm_conn_state->pbn);
+
+   if (dm_conn_state->vcpi_slots < 0)
+   return dm_conn_state->vcpi_slots;
+   }
+   return 0;
+}
+
 static void dm_drm_plane_reset(struct drm_plane *plane)
 {
struct dm_plane_state *amdgpu_state = NULL;
@@ -7684,11 +7742,6 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
if (ret)
goto fail;
 
-   /* Perform validation of MST topology in the state*/
-   ret = drm_dp_mst_atomic_check(state);
-   if (ret)
-   goto fail;
-
if (state->legacy_cursor_update) {
/*
 * This is a fast cursor update coming from the plane update
@@ -7760,6 +7813,10 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
if (!compute_mst_dsc_configs_for_state(dm_state->context))
goto fail;
+
+   ret = dm_update_mst_vcpi_slots_for_dsc(state, 
dm_state->context);
+   if (ret)
+   goto fail;
 #endif
if (dc_validate_global_state(dc, dm_state->context, false) != 
DC_OK) {
ret = -EINVAL;
@@ -7789,6 +7846,10 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
dc_retain_state(old_dm_state->context);
}
}
+   /* Perform validation of MST topology in the state*/
+   ret = drm_dp_mst_atomic_check(state);
+   if (ret)
+   goto fail;
 
/* Store the overall update type for use later in atomic check. */
for_each_new_crtc_in_state (state, crtc, new_crtc_state, i) {
-- 
2.17.1

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[PATCH 06/13] drm/dp_mst: Add helpers for MST DSC and virtual DPCD aux

[mikita.lipski]

From: David Francis 

Add drm_dp_mst_dsc_aux_for_port. To enable DSC, the DSC_ENABLED
register might have to be written on the leaf port's DPCD,
its parent's DPCD, or the MST manager's DPCD. This function
finds the correct aux for the job.

As part of this, add drm_dp_mst_is_virtual_dpcd. Virtual DPCD
is a DP feature new in DP v1.4, which exposes certain DPCD
registers on virtual ports.

v2: Remember to unlock mutex on all paths
v3: Refactor to match coding style and increase brevity

Reviewed-by: Lyude Paul 
Reviewed-by: Wenjing Liu 
Signed-off-by: David Francis 
---
 drivers/gpu/drm/drm_dp_mst_topology.c | 127 ++
 include/drm/drm_dp_mst_helper.h   |   2 +
 2 files changed, 129 insertions(+)

diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c 
b/drivers/gpu/drm/drm_dp_mst_topology.c
index 502923c24450..d8f9ba27b559 100644
--- a/drivers/gpu/drm/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/drm_dp_mst_topology.c
@@ -4150,3 +4150,130 @@ static void drm_dp_mst_unregister_i2c_bus(struct 
drm_dp_aux *aux)
 {
i2c_del_adapter(>ddc);
 }
+
+/**
+ * drm_dp_mst_is_virtual_dpcd() - Is the given port a virtual DP Peer Device
+ * @port: The port to check
+ *
+ * A single physical MST hub object can be represented in the topology
+ * by multiple branches, with virtual ports between those branches.
+ *
+ * As of DP1.4, An MST hub with internal (virtual) ports must expose
+ * certain DPCD registers over those ports. See sections 2.6.1.1.1
+ * and 2.6.1.1.2 of Display Port specification v1.4 for details.
+ *
+ * May acquire mgr->lock
+ *
+ * Returns:
+ * true if the port is a virtual DP peer device, false otherwise
+ */
+static bool drm_dp_mst_is_virtual_dpcd(struct drm_dp_mst_port *port)
+{
+   struct drm_dp_mst_port *downstream_port;
+
+   if (!port || port->dpcd_rev < DP_DPCD_REV_14)
+   return false;
+
+   /* Virtual DP Sink (Internal Display Panel) */
+   if (port->port_num >= 8)
+   return true;
+
+   /* DP-to-HDMI Protocol Converter */
+   if (port->pdt == DP_PEER_DEVICE_DP_LEGACY_CONV &&
+   !port->mcs &&
+   port->ldps)
+   return true;
+
+   /* DP-to-DP */
+   mutex_lock(>mgr->lock);
+   if (port->pdt == DP_PEER_DEVICE_MST_BRANCHING &&
+   port->mstb &&
+   port->mstb->num_ports == 2) {
+   list_for_each_entry(downstream_port, >mstb->ports, next) {
+   if (downstream_port->pdt == DP_PEER_DEVICE_SST_SINK &&
+   !downstream_port->input) {
+   mutex_unlock(>mgr->lock);
+   return true;
+   }
+   }
+   }
+   mutex_unlock(>mgr->lock);
+
+   return false;
+}
+
+/**
+ * drm_dp_mst_dsc_aux_for_port() - Find the correct aux for DSC
+ * @port: The port to check. A leaf of the MST tree with an attached display.
+ *
+ * Depending on the situation, DSC may be enabled via the endpoint aux,
+ * the immediately upstream aux, or the connector's physical aux.
+ *
+ * This is both the correct aux to read DSC_CAPABILITY and the
+ * correct aux to write DSC_ENABLED.
+ *
+ * This operation can be expensive (up to four aux reads), so
+ * the caller should cache the return.
+ *
+ * Returns:
+ * NULL if DSC cannot be enabled on this port, otherwise the aux device
+ */
+struct drm_dp_aux *drm_dp_mst_dsc_aux_for_port(struct drm_dp_mst_port *port)
+{
+   struct drm_dp_mst_port *immediate_upstream_port;
+   struct drm_dp_mst_port *fec_port;
+
+   if (!port)
+   return NULL;
+
+   if (port->parent)
+   immediate_upstream_port = port->parent->port_parent;
+   else
+   immediate_upstream_port = NULL;
+
+   fec_port = immediate_upstream_port;
+   while (fec_port) {
+   /*
+* Each physical link (i.e. not a virtual port) between the
+* output and the primary device must support FEC
+*/
+   if (!drm_dp_mst_is_virtual_dpcd(fec_port) &&
+   !fec_port->fec_capable)
+   return NULL;
+
+   fec_port = fec_port->parent->port_parent;
+   }
+
+   /* DP-to-DP peer device */
+   if (drm_dp_mst_is_virtual_dpcd(immediate_upstream_port)) {
+   u8 upstream_dsc;
+   u8 endpoint_dsc;
+   u8 endpoint_fec;
+
+   if (drm_dp_dpcd_read(>aux,
+DP_DSC_SUPPORT, _dsc, 1) < 0)
+   return NULL;
+   if (drm_dp_dpcd_read(>aux,
+DP_FEC_CAPABILITY, _fec, 1) < 0)
+   return NULL;
+   if (drm_dp_dpcd_read(_upstream_port->aux,
+DP_DSC_SUPPORT, _dsc, 1) < 0)
+   return NULL;
+
+   /* Enpoint decompression with DP-to-DP peer device */
+   if 

[PATCH 01/13] drm/amd/display: Add MST atomic routines

[mikita.lipski]

From: Mikita Lipski 

- Adding encoder atomic check to find vcpi slots for a connector
- Using DRM helper functions to calculate PBN
- Adding connector atomic check to release vcpi slots if connector
loses CRTC
- Calculate  PBN and VCPI slots only once during atomic
check and store them on crtc_state to eliminate
redundant calculation
- Call drm_dp_mst_atomic_check to verify validity of MST topology
during state atomic check

v2: squashed previous 3 separate patches, removed DSC PBN calculation,
and added PBN and VCPI slots properties to amdgpu connector

v3:
- moved vcpi_slots and pbn properties to dm_crtc_state and dc_stream_state
- updates stream's vcpi_slots and pbn on commit
- separated patch from the DSC MST series

v4:
- set vcpi_slots and pbn properties to dm_connector_state
- copy porperties from connector state on to crtc state

v5:
- keep the pbn and vcpi values only on connnector state
- added a void pointer to the stream state instead on two ints,
because dc_stream_state is OS agnostic. Pointer points to the
current dm_connector_state.

v6:
- Remove new param from stream

Cc: Jun Lei 
Cc: Jerry Zuo 
Cc: Harry Wentland 
Cc: Nicholas Kazlauskas 
Cc: Lyude Paul 
Signed-off-by: Mikita Lipski 
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 42 ++-
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h |  2 +
 .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 51 +--
 .../display/amdgpu_dm/amdgpu_dm_mst_types.c   | 32 
 4 files changed, 86 insertions(+), 41 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 48f5b43e2698..28f6b93ab371 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4180,7 +4180,8 @@ void amdgpu_dm_connector_funcs_reset(struct drm_connector 
*connector)
state->underscan_hborder = 0;
state->underscan_vborder = 0;
state->base.max_requested_bpc = 8;
-
+   state->vcpi_slots = 0;
+   state->pbn = 0;
if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
state->abm_level = amdgpu_dm_abm_level;
 
@@ -4209,7 +4210,8 @@ amdgpu_dm_connector_atomic_duplicate_state(struct 
drm_connector *connector)
new_state->underscan_enable = state->underscan_enable;
new_state->underscan_hborder = state->underscan_hborder;
new_state->underscan_vborder = state->underscan_vborder;
-
+   new_state->vcpi_slots = state->vcpi_slots;
+   new_state->pbn = state->pbn;
return _state->base;
 }
 
@@ -4610,6 +4612,37 @@ static int dm_encoder_helper_atomic_check(struct 
drm_encoder *encoder,
  struct drm_crtc_state *crtc_state,
  struct drm_connector_state 
*conn_state)
 {
+   struct drm_atomic_state *state = crtc_state->state;
+   struct drm_connector *connector = conn_state->connector;
+   struct amdgpu_dm_connector *aconnector = 
to_amdgpu_dm_connector(connector);
+   struct dm_connector_state *dm_new_connector_state = 
to_dm_connector_state(conn_state);
+   const struct drm_display_mode *adjusted_mode = 
_state->adjusted_mode;
+   struct drm_dp_mst_topology_mgr *mst_mgr;
+   struct drm_dp_mst_port *mst_port;
+   int clock, bpp = 0;
+
+   if (!aconnector->port || !aconnector->dc_sink)
+   return 0;
+
+   mst_port = aconnector->port;
+   mst_mgr = >mst_port->mst_mgr;
+
+   if (!crtc_state->connectors_changed && !crtc_state->mode_changed)
+   return 0;
+
+   if (!state->duplicated) {
+   bpp = (uint8_t)connector->display_info.bpc * 3;
+   clock = adjusted_mode->clock;
+   dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp);
+   }
+   dm_new_connector_state->vcpi_slots = 
drm_dp_atomic_find_vcpi_slots(state,
+  mst_mgr,
+  mst_port,
+  
dm_new_connector_state->pbn);
+   if (dm_new_connector_state->vcpi_slots < 0) {
+   DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", 
dm_new_connector_state->vcpi_slots);
+   return dm_new_connector_state->vcpi_slots;
+   }
return 0;
 }
 
@@ -7651,6 +7684,11 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
if (ret)
goto fail;
 
+   /* Perform validation of MST topology in the state*/
+   ret = drm_dp_mst_atomic_check(state);
+   if (ret)
+   goto fail;
+
if (state->legacy_cursor_update) {
/*
 * This is a fast cursor update coming from the plane update
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h 

[PATCH 04/13] drm/dp_mst: Add MST support to DP DPCD R/W functions

[mikita.lipski]

From: David Francis 

Instead of having drm_dp_dpcd_read/write and
drm_dp_mst_dpcd_read/write as entry points into the
aux code, have drm_dp_dpcd_read/write handle both.

This means that DRM drivers can make MST DPCD read/writes.

v2: Fix spacing
v3: Dump dpcd access on MST read/writes
v4: Fix calling wrong function on DPCD write

Reviewed-by: Lyude Paul 
Reviewed-by: Harry Wentland 
Signed-off-by: David Francis 
Signed-off-by: Mikita Lipski 
---
 drivers/gpu/drm/drm_dp_aux_dev.c | 12 ++--
 drivers/gpu/drm/drm_dp_helper.c  | 31 +--
 2 files changed, 23 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/drm_dp_aux_dev.c b/drivers/gpu/drm/drm_dp_aux_dev.c
index 0cfb386754c3..2510717d5a08 100644
--- a/drivers/gpu/drm/drm_dp_aux_dev.c
+++ b/drivers/gpu/drm/drm_dp_aux_dev.c
@@ -163,11 +163,7 @@ static ssize_t auxdev_read_iter(struct kiocb *iocb, struct 
iov_iter *to)
break;
}
 
-   if (aux_dev->aux->is_remote)
-   res = drm_dp_mst_dpcd_read(aux_dev->aux, pos, buf,
-  todo);
-   else
-   res = drm_dp_dpcd_read(aux_dev->aux, pos, buf, todo);
+   res = drm_dp_dpcd_read(aux_dev->aux, pos, buf, todo);
 
if (res <= 0)
break;
@@ -215,11 +211,7 @@ static ssize_t auxdev_write_iter(struct kiocb *iocb, 
struct iov_iter *from)
break;
}
 
-   if (aux_dev->aux->is_remote)
-   res = drm_dp_mst_dpcd_write(aux_dev->aux, pos, buf,
-   todo);
-   else
-   res = drm_dp_dpcd_write(aux_dev->aux, pos, buf, todo);
+   res = drm_dp_dpcd_write(aux_dev->aux, pos, buf, todo);
 
if (res <= 0)
break;
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index ffc68d305afe..af1cd968adfd 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -32,6 +32,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 
 #include "drm_crtc_helper_internal.h"
 
@@ -251,7 +253,7 @@ static int drm_dp_dpcd_access(struct drm_dp_aux *aux, u8 
request,
 
 /**
  * drm_dp_dpcd_read() - read a series of bytes from the DPCD
- * @aux: DisplayPort AUX channel
+ * @aux: DisplayPort AUX channel (SST or MST)
  * @offset: address of the (first) register to read
  * @buffer: buffer to store the register values
  * @size: number of bytes in @buffer
@@ -280,13 +282,18 @@ ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned 
int offset,
 * We just have to do it before any DPCD access and hope that the
 * monitor doesn't power down exactly after the throw away read.
 */
-   ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, DP_DPCD_REV, buffer,
-1);
-   if (ret != 1)
-   goto out;
+   if (!aux->is_remote) {
+   ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, DP_DPCD_REV,
+buffer, 1);
+   if (ret != 1)
+   goto out;
+   }
 
-   ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, offset, buffer,
-size);
+   if (aux->is_remote)
+   ret = drm_dp_mst_dpcd_read(aux, offset, buffer, size);
+   else
+   ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, offset,
+buffer, size);
 
 out:
drm_dp_dump_access(aux, DP_AUX_NATIVE_READ, offset, buffer, ret);
@@ -296,7 +303,7 @@ EXPORT_SYMBOL(drm_dp_dpcd_read);
 
 /**
  * drm_dp_dpcd_write() - write a series of bytes to the DPCD
- * @aux: DisplayPort AUX channel
+ * @aux: DisplayPort AUX channel (SST or MST)
  * @offset: address of the (first) register to write
  * @buffer: buffer containing the values to write
  * @size: number of bytes in @buffer
@@ -313,8 +320,12 @@ ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned 
int offset,
 {
int ret;
 
-   ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_WRITE, offset, buffer,
-size);
+   if (aux->is_remote)
+   ret = drm_dp_mst_dpcd_write(aux, offset, buffer, size);
+   else
+   ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_WRITE, offset,
+buffer, size);
+
drm_dp_dump_access(aux, DP_AUX_NATIVE_WRITE, offset, buffer, ret);
return ret;
 }
-- 
2.17.1

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[PATCH 11/13] drm/amd/display: MST DSC compute fair share

[mikita.lipski]

From: David Francis 

If there is limited link bandwidth on a MST network,
it must be divided fairly between the streams on that network

Implement an algorithm to determine the correct DSC config
for each stream

The algorithm:
This
 [   ]  ( )
represents the range of bandwidths possible for a given stream.
The [] area represents the range of DSC configs, and the ()
represents no DSC. The bandwidth used increases from left to right.

First, try disabling DSC on all streams
 [  ]  (|)
 [ ](|)
Check this against the bandwidth limits of the link and each branch
(including each endpoint). If it passes, the job is done

Second, try maximum DSC compression on all streams
that support DSC
 [| ]( )
 [|] ( )
If this does not pass, then enabling this combination of streams
is impossible

Otherwise, divide the remaining bandwidth evenly amongst the streams
 [|  ] ( )
 [|  ]( )

If one or more of the streams reach minimum compression, evenly
divide the reamining bandwidth amongst the remaining streams
 [|] ( )
 [   |]   ( )
 [ |   ]   ( )
 [ |  ]  ( )

If all streams can reach minimum compression, disable compression
greedily
 [  |]  ( )
 [|]( )
 [ ](|)

Perform this algorithm on each full update, on each MST link
with at least one DSC stream on it

After the configs are computed, call
dcn20_add_dsc_to_stream_resource on each stream with DSC enabled.
It is only after all streams are created that we can know which
of them will need DSC.

Do all of this at the end of amdgpu atomic check.  If it fails,
fail check; This combination of timings cannot be supported.

Reviewed-by: Wenjing Liu 
Signed-off-by: David Francis 
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |   4 +
 .../display/amdgpu_dm/amdgpu_dm_mst_types.c   | 386 ++
 .../display/amdgpu_dm/amdgpu_dm_mst_types.h   |   4 +
 .../drm/amd/display/dc/dcn20/dcn20_resource.c |   7 +-
 .../drm/amd/display/dc/dcn20/dcn20_resource.h |   1 +
 5 files changed, 400 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 0909ace4f1b4..adbd28e17947 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -7757,6 +7757,10 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
if (ret)
goto fail;
 
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+   if (!compute_mst_dsc_configs_for_state(dm_state->context))
+   goto fail;
+#endif
if (dc_validate_global_state(dc, dm_state->context, false) != 
DC_OK) {
ret = -EINVAL;
goto fail;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 804a00082bee..c58cf41f3086 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -38,6 +38,8 @@
 
 #include "i2caux_interface.h"
 
+#include "dc/dcn20/dcn20_resource.h"
+
 /* #define TRACE_DPCD */
 
 #ifdef TRACE_DPCD
@@ -491,3 +493,387 @@ void amdgpu_dm_initialize_dp_connector(struct 
amdgpu_display_manager *dm,
aconnector->connector_id);
 }
 
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+struct dsc_mst_fairness_params {
+   struct dc_crtc_timing *timing;
+   struct dc_sink *sink;
+   struct dc_dsc_bw_range bw_range;
+   bool compression_possible;
+   struct drm_dp_mst_port *port;
+};
+
+struct dsc_mst_fairness_vars {
+   int pbn;
+   bool dsc_enabled;
+   int bpp_x16;
+};
+
+static bool port_downstream_of_branch(struct drm_dp_mst_port *port,
+   struct drm_dp_mst_branch *branch)
+{
+   while (port->parent) {
+   if (port->parent == branch)
+   return true;
+
+   if (port->parent->port_parent)
+   port = port->parent->port_parent;
+   else
+   break;
+   }
+   return false;
+}
+
+static bool check_pbn_limit_on_branch(struct drm_dp_mst_branch *branch,
+   struct dsc_mst_fairness_params *params,
+   struct dsc_mst_fairness_vars *vars, int count)
+{
+   struct drm_dp_mst_port *port;
+   int i;
+   int pbn_limit = 0;
+   int pbn_used = 0;
+
+   list_for_each_entry(port, >ports, next) {
+   if (port->mstb)
+   if (!check_pbn_limit_on_branch(port->mstb, params, 
vars, count))
+   return false;
+
+   if 

[PATCH 08/13] drm/amd/display: Initialize DSC PPS variables to 0

[mikita.lipski]

From: David Francis 

For DSC MST, sometimes monitors would break out
in full-screen static. The issue traced back to the
PPS generation code, where these variables were being used
uninitialized and were picking up garbage.

memset to 0 to avoid this

Reviewed-by: Nicholas Kazlauskas 
Signed-off-by: David Francis 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 3 +++
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c   | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
index a519dbc5ecb6..5d6cbaebebc0 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
@@ -496,6 +496,9 @@ bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool 
enable)
struct dsc_config dsc_cfg;
uint8_t dsc_packed_pps[128];
 
+   memset(_cfg, 0, sizeof(dsc_cfg));
+   memset(dsc_packed_pps, 0, 128);
+
/* Enable DSC hw block */
dsc_cfg.pic_width = stream->timing.h_addressable + 
stream->timing.h_border_left + stream->timing.h_border_right;
dsc_cfg.pic_height = stream->timing.v_addressable + 
stream->timing.v_border_top + stream->timing.v_border_bottom;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
index 63eb377ed9c0..296eeff00296 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
@@ -207,6 +207,9 @@ static bool dsc2_get_packed_pps(struct 
display_stream_compressor *dsc, const str
struct dsc_reg_values dsc_reg_vals;
struct dsc_optc_config dsc_optc_cfg;
 
+   memset(_reg_vals, 0, sizeof(dsc_reg_vals));
+   memset(_optc_cfg, 0, sizeof(dsc_optc_cfg));
+
DC_LOG_DSC("Getting packed DSC PPS for DSC Config:");
dsc_config_log(dsc, dsc_cfg);
DC_LOG_DSC("DSC Picture Parameter Set (PPS):");
-- 
2.17.1

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[PATCH 07/13] drm/dp_mst: Add new quirk for Synaptics MST hubs

[mikita.lipski]

From: Mikita Lipski 

Synaptics DP1.4 hubs (BRANCH_ID 0x90CC24) do not
support virtual DPCD registers, but do support DSC.
The DSC caps can be read from the physical aux,
like in SST DSC. These hubs have many different
DEVICE_IDs.  Add a new quirk to detect this case.

Reviewed-by: Wenjing Liu 
Reviewed-by: Lyude Paul 
Signed-off-by: David Francis 
---
 drivers/gpu/drm/drm_dp_helper.c   |  2 ++
 drivers/gpu/drm/drm_dp_mst_topology.c | 27 +++
 include/drm/drm_dp_helper.h   |  7 +++
 3 files changed, 36 insertions(+)

diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index af1cd968adfd..02fa8c3d9a82 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -1271,6 +1271,8 @@ static const struct dpcd_quirk dpcd_quirk_list[] = {
{ OUI(0x00, 0x10, 0xfa), DEVICE_ID_ANY, false, 
BIT(DP_DPCD_QUIRK_NO_PSR) },
/* CH7511 seems to leave SINK_COUNT zeroed */
{ OUI(0x00, 0x00, 0x00), DEVICE_ID('C', 'H', '7', '5', '1', '1'), 
false, BIT(DP_DPCD_QUIRK_NO_SINK_COUNT) },
+   /* Synaptics DP1.4 MST hubs can support DSC without virtual DPCD */
+   { OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true, 
BIT(DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD) },
 };
 
 #undef OUI
diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c 
b/drivers/gpu/drm/drm_dp_mst_topology.c
index d8f9ba27b559..d5df02315e14 100644
--- a/drivers/gpu/drm/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/drm_dp_mst_topology.c
@@ -4222,6 +4222,7 @@ struct drm_dp_aux *drm_dp_mst_dsc_aux_for_port(struct 
drm_dp_mst_port *port)
 {
struct drm_dp_mst_port *immediate_upstream_port;
struct drm_dp_mst_port *fec_port;
+   struct drm_dp_desc desc = { 0 };
 
if (!port)
return NULL;
@@ -4274,6 +4275,32 @@ struct drm_dp_aux *drm_dp_mst_dsc_aux_for_port(struct 
drm_dp_mst_port *port)
if (drm_dp_mst_is_virtual_dpcd(port))
return >aux;
 
+   /*
+* Synaptics quirk
+* Applies to ports for which:
+* - Physical aux has Synaptics OUI
+* - DPv1.4 or higher
+* - Port is on primary branch device
+* - Not a VGA adapter (DP_DWN_STRM_PORT_TYPE_ANALOG)
+*/
+   if (!drm_dp_read_desc(port->mgr->aux, , true))
+   return NULL;
+
+   if (drm_dp_has_quirk(, DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD) &&
+   port->mgr->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14 &&
+   port->parent == port->mgr->mst_primary) {
+   u8 downstreamport;
+
+   if (drm_dp_dpcd_read(>aux, DP_DOWNSTREAMPORT_PRESENT,
+, 1) < 0)
+   return NULL;
+
+   if ((downstreamport & DP_DWN_STRM_PORT_PRESENT) &&
+  ((downstreamport & DP_DWN_STRM_PORT_TYPE_MASK)
+!= DP_DWN_STRM_PORT_TYPE_ANALOG))
+   return port->mgr->aux;
+   }
+
return NULL;
 }
 EXPORT_SYMBOL(drm_dp_mst_dsc_aux_for_port);
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 6e17410a0417..61ef351c5fca 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1460,6 +1460,13 @@ enum drm_dp_quirk {
 * The driver should ignore SINK_COUNT during detection.
 */
DP_DPCD_QUIRK_NO_SINK_COUNT,
+   /**
+* @DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD:
+*
+* The device supports MST DSC despite not supporting Virtual DPCD.
+* The DSC caps can be read from the physical aux instead.
+*/
+   DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD,
 };
 
 /**
-- 
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[PATCH 12/13] drm/dp_mst: Add DSC enablement helpers to DRM

[mikita.lipski]

From: Mikita Lipski 

Adding the following elements to add MST DSC support to DRM:

- dsc_enable boolean flag to drm_dp_vcpi_allocation structure to signal,
which port got DSC enabled

- function drm_dp_helper_update_vcpi_slots_for_dsc allows reallocation
of newly recalculated VCPI slots and raises dsc_enable flag on the port.

- function drm_dp_mst_update_dsc_crtcs is called in drm_dp_mst_atomic_check,
its purpose is to iterate through all the ports in the topology and set
mode_changed flag on crtc if DSC has been enabled.

Cc: Harry Wentland 
Cc: Lyude Paul 
Signed-off-by: Mikita Lipski 
---
 drivers/gpu/drm/drm_dp_mst_topology.c | 103 +-
 include/drm/drm_dp_mst_helper.h   |   4 +
 2 files changed, 106 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c 
b/drivers/gpu/drm/drm_dp_mst_topology.c
index d5df02315e14..4f2f09fe32f8 100644
--- a/drivers/gpu/drm/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/drm_dp_mst_topology.c
@@ -73,6 +73,7 @@ static bool drm_dp_validate_guid(struct 
drm_dp_mst_topology_mgr *mgr,
 static int drm_dp_mst_register_i2c_bus(struct drm_dp_aux *aux);
 static void drm_dp_mst_unregister_i2c_bus(struct drm_dp_aux *aux);
 static void drm_dp_mst_kick_tx(struct drm_dp_mst_topology_mgr *mgr);
+static void drm_dp_mst_update_dsc_crtcs(struct drm_dp_mst_topology_state 
*mst_state);
 
 #define DP_STR(x) [DP_ ## x] = #x
 
@@ -3293,6 +3294,65 @@ int drm_dp_atomic_find_vcpi_slots(struct 
drm_atomic_state *state,
 }
 EXPORT_SYMBOL(drm_dp_atomic_find_vcpi_slots);
 
+/**
+ * drm_dp_helper_update_vcpi_slots_for_dsc() - Update VCPI slots with new on 
the state
+ *
+ * @state: global atomic state
+ * @port: port to find vcpi slots
+ * @pbn: updated bandwidth required for the mode in PBN
+ *
+ * Function reallocates VCPI slots to the @port by calling
+ * drm_dp_atomic_find_vcpi_slots. The assumption is that VCPI slots
+ * have already been allocated and this is second call overwritting
+ * initial values. After the VCPI is allocated dsc_enable flag is set to
+ * true for atomic check.
+ *
+ * It is driver's responsibility to call this function after it decides
+ * to enable DSC.
+ *
+ * See also:
+ * drm_dp_mst_update_dsc_crtcs()
+ *
+ * Returns:
+ * Total slots in the atomic state assigned for this port, or a negative error
+ * code if the port no longer exists or vcpi slots haven't been assigned.
+ */
+int drm_dp_helper_update_vcpi_slots_for_dsc(struct drm_atomic_state *state,
+   struct drm_dp_mst_port *port,
+   int pbn)
+{
+   struct drm_dp_mst_topology_state *topology_state;
+   struct drm_dp_vcpi_allocation *pos;
+   bool found = false;
+   int vcpi = 0;
+
+   topology_state = drm_atomic_get_mst_topology_state(state, port->mgr);
+
+   if (IS_ERR(topology_state))
+   return PTR_ERR(topology_state);
+
+   list_for_each_entry(pos, _state->vcpis, next) {
+   if (pos->port == port) {
+   found = true;
+   break;
+   }
+   }
+
+   if (!found || !pos->vcpi)
+   return -EINVAL;
+
+   vcpi = drm_dp_atomic_find_vcpi_slots(state, port->mgr,
+port, pbn);
+
+   if (vcpi < 0)
+   return -EINVAL;
+
+   pos->dsc_enable = true;
+
+   return vcpi;
+}
+
+EXPORT_SYMBOL(drm_dp_helper_update_vcpi_slots_for_dsc);
 /**
  * drm_dp_atomic_release_vcpi_slots() - Release allocated vcpi slots
  * @state: global atomic state
@@ -3871,6 +3931,46 @@ drm_dp_mst_atomic_check_topology_state(struct 
drm_dp_mst_topology_mgr *mgr,
return 0;
 }
 
+/**
+ * drm_dp_mst_update_dsc_crtcs - Set mode change flag on CRTCs which
+ * just got DSC enabled
+ * @state: Pointer to the new  drm_dp_mst_topology_state
+ *
+ * Itearate through all the ports in MST topology to check if DSC
+ * has been enabled on any of them. Set mode_changed to true on
+ * crtc state that just got DSC enabled.
+ *
+ * See also:
+ * drm_dp_helper_update_vcpi_slots_for_dsc()
+ */
+static void
+drm_dp_mst_update_dsc_crtcs(struct drm_dp_mst_topology_state *mst_state)
+{
+   struct drm_dp_vcpi_allocation *pos;
+   struct drm_dp_mst_port *port;
+   struct drm_connector_state *conn_state;
+   struct drm_crtc *crtc;
+   struct drm_crtc_state *crtc_state;
+
+   list_for_each_entry(pos, _state->vcpis, next) {
+
+   port = pos->port;
+   conn_state = 
drm_atomic_get_connector_state(mst_state->base.state,
+   port->connector);
+   crtc = conn_state->crtc;
+   if (!crtc)
+   continue;
+
+   crtc_state = drm_atomic_get_crtc_state(mst_state->base.state, 
crtc);
+   if (port->vcpi.vcpi == pos->vcpi)
+   continue;
+
+   if (pos->dsc_enable) {
+ 

[PATCH 03/13] drm/dp_mst: Parse FEC capability on MST ports

[mikita.lipski]

From: David Francis 

As of DP1.4, ENUM_PATH_RESOURCES returns a bit indicating
if FEC can be supported up to that point in the MST network.

The bit is the first byte of the ENUM_PATH_RESOURCES ack reply,
bottom-most bit (refer to section 2.11.9.4 of DP standard,
v1.4)

That value is needed for FEC and DSC support

Store it on drm_dp_mst_port

Reviewed-by: Lyude Paul 
Reviewed-by: Harry Wentland 
Signed-off-by: David Francis 
---
 drivers/gpu/drm/drm_dp_mst_topology.c | 2 ++
 include/drm/drm_dp_mst_helper.h   | 3 +++
 2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c 
b/drivers/gpu/drm/drm_dp_mst_topology.c
index 3e7b7553cf4d..9f3604355705 100644
--- a/drivers/gpu/drm/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/drm_dp_mst_topology.c
@@ -553,6 +553,7 @@ static bool 
drm_dp_sideband_parse_enum_path_resources_ack(struct drm_dp_sideband
 {
int idx = 1;
repmsg->u.path_resources.port_number = (raw->msg[idx] >> 4) & 0xf;
+   repmsg->u.path_resources.fec_capable = raw->msg[idx] & 0x1;
idx++;
if (idx > raw->curlen)
goto fail_len;
@@ -2183,6 +2184,7 @@ static int drm_dp_send_enum_path_resources(struct 
drm_dp_mst_topology_mgr *mgr,
DRM_DEBUG_KMS("enum path resources %d: %d %d\n", 
txmsg->reply.u.path_resources.port_number, 
txmsg->reply.u.path_resources.full_payload_bw_number,
   
txmsg->reply.u.path_resources.avail_payload_bw_number);
port->available_pbn = 
txmsg->reply.u.path_resources.avail_payload_bw_number;
+   port->fec_capable = 
txmsg->reply.u.path_resources.fec_capable;
}
}
 
diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h
index 9116b2c95239..f113ae04fa88 100644
--- a/include/drm/drm_dp_mst_helper.h
+++ b/include/drm/drm_dp_mst_helper.h
@@ -108,6 +108,8 @@ struct drm_dp_mst_port {
 * audio-capable.
 */
bool has_audio;
+
+   bool fec_capable;
 };
 
 /**
@@ -312,6 +314,7 @@ struct drm_dp_port_number_req {
 
 struct drm_dp_enum_path_resources_ack_reply {
u8 port_number;
+   bool fec_capable;
u16 full_payload_bw_number;
u16 avail_payload_bw_number;
 };
-- 
2.17.1

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[PATCH v3 00/13] DSC MST support for AMDGPU

[mikita.lipski]

From: Mikita Lipski 


This set of patches is a continuation of DSC enablement
patches for AMDGPU. This set enables DSC on MST. It also
contains implementation of both encoder and connector
atomic check routines.

First 10 patches have been introduced in multiple
iterations to the mailing list before. These patches were
developed by David Francis as part of his work on DSC.

Other 3 patches add atomic check functionality to
encoder and connector to allocate and release VCPI
slots on each state atomic check. These changes
utilize newly added drm_mst_helper functions for
better tracking of VCPI slots.

v2: squashed previously 3 separate atomic check patches,
separate atomic check for dsc connectors, track vcpi and
pbn on connectors.

v3: Moved modeset trigger on affected MST displays to DRM

David Francis (10):
  drm/dp_mst: Add PBN calculation for DSC modes
  drm/dp_mst: Parse FEC capability on MST ports
  drm/dp_mst: Add MST support to DP DPCD R/W functions
  drm/dp_mst: Fill branch->num_ports
  drm/dp_mst: Add helpers for MST DSC and virtual DPCD aux
  drm/amd/display: Initialize DSC PPS variables to 0
  drm/amd/display: Validate DSC caps on MST endpoints
  drm/amd/display: Write DSC enable to MST DPCD
  drm/amd/display: MST DSC compute fair share
  drm/dp_mst: Add new quirk for Synaptics MST hubs

Mikita Lipski (3):
  drm/amd/display: Add MST atomic routines
  drm/dp_mst: Add DSC enablement helpers to DRM
  drm/amd/display: Recalculate VCPI slots for new DSC connectors

 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 107 -
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h |   5 +
 .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c |  70 ++-
 .../display/amdgpu_dm/amdgpu_dm_mst_types.c   | 449 +-
 .../display/amdgpu_dm/amdgpu_dm_mst_types.h   |   4 +
 .../drm/amd/display/dc/core/dc_link_hwss.c|   3 +
 .../gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c  |   3 +
 .../drm/amd/display/dc/dcn20/dcn20_resource.c |   7 +-
 .../drm/amd/display/dc/dcn20/dcn20_resource.h |   1 +
 drivers/gpu/drm/drm_dp_aux_dev.c  |  12 +-
 drivers/gpu/drm/drm_dp_helper.c   |  33 +-
 drivers/gpu/drm/drm_dp_mst_topology.c | 277 ++-
 drivers/gpu/drm/i915/display/intel_dp_mst.c   |   3 +-
 drivers/gpu/drm/nouveau/dispnv50/disp.c   |   3 +-
 drivers/gpu/drm/radeon/radeon_dp_mst.c|   2 +-
 include/drm/drm_dp_helper.h   |   7 +
 include/drm/drm_dp_mst_helper.h   |  12 +-
 17 files changed, 923 insertions(+), 75 deletions(-)

-- 
2.17.1

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Re: Spontaneous reboots when using RX 560

[Sylvain Munaut]

Hi Alex,

> Can you send me a copy of the vbios from that board?

Did you get a chance to look at the bios see if you can find anything
interesting in it ?
(I guess you need some special tools for that, I'm not sure how I'd
find anything in there myself).

After a couple of back and forth with AsRock support they basically
just want me to return the card to get another one which I'm pretty
sure isn't going to accomplish anything except for wasting 1 or 2
weeks shipping stuff around ...

Cheers,

Sylvain
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Re: [PATCH] drm/amdgpu: fix gfx VF FLR test fail on navi

[Deucher, Alexander]

Acked-by: Alex Deucher 

From: amd-gfx  on behalf of HaiJun Chang 

Sent: Tuesday, October 29, 2019 5:18 AM
To: amd-gfx@lists.freedesktop.org 
Cc: Chang, HaiJun 
Subject: [PATCH] drm/amdgpu: fix gfx VF FLR test fail on navi

Cp wptr in wb buffer is outdated after VF FLR.
The outdated wptr may cause cp to execute unexpected packets.
Reset cp wptr in wb buffer.

Signed-off-by: HaiJun Chang 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index d126d66..13363f2 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -3107,6 +3107,7 @@ static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring 
*ring)
 memcpy(mqd, 
adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS], sizeof(*mqd));
 /* reset the ring */
 ring->wptr = 0;
+   adev->wb.wb[ring->wptr_offs] = 0;
 amdgpu_ring_clear_ring(ring);
 #ifdef BRING_UP_DEBUG
 mutex_lock(>srbm_mutex);
--
2.7.4

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RE: [PATCH 1/1] drm/amdgpu: add missing amdgpu_ras.h header include

[Zhang, Hawking]

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: amd-gfx  On Behalf Of Le Ma
Sent: 2019年10月29日 20:43
To: amd-gfx@lists.freedesktop.org
Cc: StDenis, Tom ; Ma, Le 
Subject: [PATCH 1/1] drm/amdgpu: add missing amdgpu_ras.h header include

Fix compilation error.

Change-Id: I461c558778f9a52378269324dc41b8d639f3ccbe
Signed-off-by: Le Ma 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index fce206f..bbe9ac7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -34,6 +34,8 @@
 #include "psp_v11_0.h"
 #include "psp_v12_0.h"
 
+#include "amdgpu_ras.h"
+
 static void psp_set_funcs(struct amdgpu_device *adev);
 
 static int psp_early_init(void *handle)
-- 
2.7.4

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Re: [PATCH v2 06/15] RDMA/hfi1: Use mmu_range_notifier_inset for user_exp_rcv

[Jason Gunthorpe]

On Tue, Oct 29, 2019 at 08:19:20AM -0400, Dennis Dalessandro wrote:
> On 10/28/2019 4:10 PM, Jason Gunthorpe wrote:
> > From: Jason Gunthorpe 
> > 
> > This converts one of the two users of mmu_notifiers to use the new API.
> > The conversion is fairly straightforward, however the existing use of
> > notifiers here seems to be racey.
> > 
> > Cc: Mike Marciniszyn 
> > Cc: Dennis Dalessandro 
> > Signed-off-by: Jason Gunthorpe 
> 
> I tested v1, and replied to it [1]. I can re-test with this version if you
> like as well.
> 
> [1] https://marc.info/?l=linux-rdma=157235130606412=2

I think it is fine, nothing really changed in v2, thanks

Jason
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Re: [PATCH 1/1] drm/amdgpu: add missing amdgpu_ras.h header include

[Christian König]

Am 29.10.19 um 13:42 schrieb Le Ma:

Fix compilation error.

Change-Id: I461c558778f9a52378269324dc41b8d639f3ccbe
Signed-off-by: Le Ma 


Acked-by: Christian König 


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 ++
  1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index fce206f..bbe9ac7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -34,6 +34,8 @@
  #include "psp_v11_0.h"
  #include "psp_v12_0.h"
  
+#include "amdgpu_ras.h"

+
  static void psp_set_funcs(struct amdgpu_device *adev);
  
  static int psp_early_init(void *handle)


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Re: [PATCH 1/1] drm/amdgpu: add missing amdgpu_ras.h header include

[StDenis, Tom]

Compiles fine.


Tested-by: Tom St Denis 


On 2019-10-29 8:43 a.m., Deucher, Alexander wrote:
> Acked-by: Alex Deucher 
> 
> *From:* amd-gfx  on behalf of 
> Le Ma 
> *Sent:* Tuesday, October 29, 2019 8:42 AM
> *To:* amd-gfx@lists.freedesktop.org 
> *Cc:* StDenis, Tom ; Ma, Le 
> *Subject:* [PATCH 1/1] drm/amdgpu: add missing amdgpu_ras.h header 
> include
> Fix compilation error.
>
> Change-Id: I461c558778f9a52378269324dc41b8d639f3ccbe
> Signed-off-by: Le Ma 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> index fce206f..bbe9ac7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> @@ -34,6 +34,8 @@
>  #include "psp_v11_0.h"
>  #include "psp_v12_0.h"
>
> +#include "amdgpu_ras.h"
> +
>  static void psp_set_funcs(struct amdgpu_device *adev);
>
>  static int psp_early_init(void *handle)
> -- 
> 2.7.4
>
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Re: [PATCH 1/1] drm/amdgpu: add missing amdgpu_ras.h header include

[Deucher, Alexander]

Acked-by: Alex Deucher 

From: amd-gfx  on behalf of Le Ma 

Sent: Tuesday, October 29, 2019 8:42 AM
To: amd-gfx@lists.freedesktop.org 
Cc: StDenis, Tom ; Ma, Le 
Subject: [PATCH 1/1] drm/amdgpu: add missing amdgpu_ras.h header include

Fix compilation error.

Change-Id: I461c558778f9a52378269324dc41b8d639f3ccbe
Signed-off-by: Le Ma 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index fce206f..bbe9ac7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -34,6 +34,8 @@
 #include "psp_v11_0.h"
 #include "psp_v12_0.h"

+#include "amdgpu_ras.h"
+
 static void psp_set_funcs(struct amdgpu_device *adev);

 static int psp_early_init(void *handle)
--
2.7.4

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[PATCH 1/1] drm/amdgpu: add missing amdgpu_ras.h header include

[Le Ma]

Fix compilation error.

Change-Id: I461c558778f9a52378269324dc41b8d639f3ccbe
Signed-off-by: Le Ma 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index fce206f..bbe9ac7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -34,6 +34,8 @@
 #include "psp_v11_0.h"
 #include "psp_v12_0.h"
 
+#include "amdgpu_ras.h"
+
 static void psp_set_funcs(struct amdgpu_device *adev);
 
 static int psp_early_init(void *handle)
-- 
2.7.4

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Re: [PATCH v2 06/15] RDMA/hfi1: Use mmu_range_notifier_inset for user_exp_rcv

[Dennis Dalessandro]

On 10/28/2019 4:10 PM, Jason Gunthorpe wrote:

From: Jason Gunthorpe 

This converts one of the two users of mmu_notifiers to use the new API.
The conversion is fairly straightforward, however the existing use of
notifiers here seems to be racey.

Cc: Mike Marciniszyn 
Cc: Dennis Dalessandro 
Signed-off-by: Jason Gunthorpe 


I tested v1, and replied to it [1]. I can re-test with this version if 
you like as well.


[1] https://marc.info/?l=linux-rdma=157235130606412=2

-Denny
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[PATCH] drm: amd: amdgpu: Remove NULL check not needed before freeing functions

[Saurav Girepunje]

Remove unneeded NULL check before freeing functions
kfree and debugfs_remove.

Signed-off-by: Saurav Girepunje 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 6 ++
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index 5652cc72ed3a..cb94627fc0f4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -1077,8 +1077,7 @@ static int amdgpu_debugfs_ib_preempt(void *data, u64 val)
 
ttm_bo_unlock_delayed_workqueue(>mman.bdev, resched);
 
-   if (fences)
-   kfree(fences);
+   kfree(fences);
 
return 0;
 }
@@ -1103,8 +1102,7 @@ int amdgpu_debugfs_init(struct amdgpu_device *adev)
 
 void amdgpu_debugfs_preempt_cleanup(struct amdgpu_device *adev)
 {
-   if (adev->debugfs_preempt)
-   debugfs_remove(adev->debugfs_preempt);
+   debugfs_remove(adev->debugfs_preempt);
 }
 
 #else
-- 
2.20.1

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Re: [PATCH hmm 06/15] RDMA/hfi1: Use mmu_range_notifier_inset for user_exp_rcv

[Dennis Dalessandro]

On 10/15/2019 2:12 PM, Jason Gunthorpe wrote:

From: Jason Gunthorpe 

This converts one of the two users of mmu_notifiers to use the new API.
The conversion is fairly straightforward, however the existing use of
notifiers here seems to be racey.

Cc: Mike Marciniszyn 
Cc: Dennis Dalessandro 
Signed-off-by: Jason Gunthorpe 


Typo in subject s/inset/insert.

Tested-by: Dennis Dalessandro 

Thanks

-Denny
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[PATCH] drm/amdgpu/gfx10: fix mqd backup/restore for gfx rings

[Yuan, Xiaojie]

1. no need to allocate an extra member for 'mqd_backup' array
2. backup/restore mqd to/from the correct 'mqd_backup' array slot

Signed-off-by: Xiaojie Yuan 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 2 +-
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c  | 9 +
 2 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index 459aa9059542..6d19e7891491 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -225,7 +225,7 @@ struct amdgpu_me {
uint32_tnum_me;
uint32_tnum_pipe_per_me;
uint32_tnum_queue_per_pipe;
-   void*mqd_backup[AMDGPU_MAX_GFX_RINGS + 1];
+   void*mqd_backup[AMDGPU_MAX_GFX_RINGS];
 
/* These are the resources for which amdgpu takes ownership */
DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index ef1975a5323a..2c5dc9b58e23 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -3075,6 +3075,7 @@ static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring 
*ring)
 {
struct amdgpu_device *adev = ring->adev;
struct v10_gfx_mqd *mqd = ring->mqd_ptr;
+   int mqd_idx = ring - >gfx.gfx_ring[0];
 
if (!adev->in_gpu_reset && !adev->in_suspend) {
memset((void *)mqd, 0, sizeof(*mqd));
@@ -3086,12 +3087,12 @@ static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring 
*ring)
 #endif
nv_grbm_select(adev, 0, 0, 0, 0);
mutex_unlock(>srbm_mutex);
-   if (adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS])
-   memcpy(adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS], 
mqd, sizeof(*mqd));
+   if (adev->gfx.me.mqd_backup[mqd_idx])
+   memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, 
sizeof(*mqd));
} else if (adev->in_gpu_reset) {
/* reset mqd with the backup copy */
-   if (adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS])
-   memcpy(mqd, 
adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS], sizeof(*mqd));
+   if (adev->gfx.me.mqd_backup[mqd_idx])
+   memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], 
sizeof(*mqd));
/* reset the ring */
ring->wptr = 0;
amdgpu_ring_clear_ring(ring);
-- 
2.20.1

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Re: [PATCH] drm: amd: amdgpu: Remove NULL check not needed before freeing functions

[Wang, Kevin(Yang)]

Hi Saurav,

the driver already has the same fix patch,
you can pull the latest driver tree and check it again,
thanks.

>From 2032324682c1ca563e33c56e51d9ae17a2b38105 Mon Sep 17 00:00:00 2001
From: zhong jiang 
Date: Tue, 3 Sep 2019 14:15:05 +0800
Subject: [PATCH] drm/amdgpu: remove the redundant null checks

debugfs_remove and kfree has taken the null check in account.
hence it is unnecessary to check it. Just remove the condition.
No functional change.

This issue was detected by using the Coccinelle software.

Signed-off-by: zhong jiang 
Signed-off-by: Alex Deucher 

Best Regards,
Kevin

From: Saurav Girepunje 
Sent: Tuesday, October 29, 2019 5:19 PM
To: Deucher, Alexander ; Koenig, Christian 
; Zhou, David(ChunMing) ; 
airl...@linux.ie ; dan...@ffwll.ch ; 
StDenis, Tom ; xywang.s...@sjtu.edu.cn 
; Xiao, Jack ; s...@ravnborg.org 
; Wang, Kevin(Yang) ; 
saurav.girepu...@gmail.com ; 
amd-gfx@lists.freedesktop.org ; 
dri-de...@lists.freedesktop.org ; 
linux-ker...@vger.kernel.org 
Cc: saurav.girepu...@hotmail.com 
Subject: [PATCH] drm: amd: amdgpu: Remove NULL check not needed before freeing 
functions

Remove unneeded NULL check before freeing functions
kfree and debugfs_remove.

Signed-off-by: Saurav Girepunje 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 6 ++
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index 5652cc72ed3a..cb94627fc0f4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -1077,8 +1077,7 @@ static int amdgpu_debugfs_ib_preempt(void *data, u64 val)

 ttm_bo_unlock_delayed_workqueue(>mman.bdev, resched);

-   if (fences)
-   kfree(fences);
+   kfree(fences);

 return 0;
 }
@@ -1103,8 +1102,7 @@ int amdgpu_debugfs_init(struct amdgpu_device *adev)

 void amdgpu_debugfs_preempt_cleanup(struct amdgpu_device *adev)
 {
-   if (adev->debugfs_preempt)
-   debugfs_remove(adev->debugfs_preempt);
+   debugfs_remove(adev->debugfs_preempt);
 }

 #else
--
2.20.1

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[PATCH] drm/amdgpu: fix gfx VF FLR test fail on navi

[HaiJun Chang]

Cp wptr in wb buffer is outdated after VF FLR.
The outdated wptr may cause cp to execute unexpected packets.
Reset cp wptr in wb buffer.

Signed-off-by: HaiJun Chang 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index d126d66..13363f2 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -3107,6 +3107,7 @@ static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring 
*ring)
memcpy(mqd, 
adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS], sizeof(*mqd));
/* reset the ring */
ring->wptr = 0;
+   adev->wb.wb[ring->wptr_offs] = 0;
amdgpu_ring_clear_ring(ring);
 #ifdef BRING_UP_DEBUG
mutex_lock(>srbm_mutex);
-- 
2.7.4

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Re: [PATCH v2 13/15] drm/amdgpu: Use mmu_range_insert instead of hmm_mirror

[Koenig, Christian]

Am 28.10.19 um 21:10 schrieb Jason Gunthorpe:
> From: Jason Gunthorpe 
>
> Remove the interval tree in the driver and rely on the tree maintained by
> the mmu_notifier for delivering mmu_notifier invalidation callbacks.
>
> For some reason amdgpu has a very complicated arrangement where it tries
> to prevent duplicate entries in the interval_tree, this is not necessary,
> each amdgpu_bo can be its own stand alone entry. interval_tree already
> allows duplicates and overlaps in the tree.
>
> Also, there is no need to remove entries upon a release callback, the
> mmu_range API safely allows objects to remain registered beyond the
> lifetime of the mm. The driver only has to stop touching the pages during
> release.
>
> Cc: Alex Deucher 
> Cc: Christian König 
> Cc: David (ChunMing) Zhou 
> Cc: amd-gfx@lists.freedesktop.org
> Signed-off-by: Jason Gunthorpe 
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu.h   |   2 +
>   .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c  |   5 +-
>   drivers/gpu/drm/amd/amdgpu/amdgpu_device.c|   1 +
>   drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c| 341 --
>   drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h|   4 -
>   drivers/gpu/drm/amd/amdgpu/amdgpu_object.h|  13 +-
>   6 files changed, 84 insertions(+), 282 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index bd37df5dd6d048..60591a5d420021 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -1006,6 +1006,8 @@ struct amdgpu_device {
>   struct mutex  lock_reset;
>   struct amdgpu_doorbell_index doorbell_index;
>   
> + struct mutexnotifier_lock;
> +
>   int asic_reset_res;
>   struct work_struct  xgmi_reset_work;
>   
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> index 6d021ecc8d598f..47700302a08b7f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> @@ -481,8 +481,7 @@ static void remove_kgd_mem_from_kfd_bo_list(struct 
> kgd_mem *mem,
>*
>* Returns 0 for success, negative errno for errors.
>*/
> -static int init_user_pages(struct kgd_mem *mem, struct mm_struct *mm,
> -uint64_t user_addr)
> +static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr)
>   {
>   struct amdkfd_process_info *process_info = mem->process_info;
>   struct amdgpu_bo *bo = mem->bo;
> @@ -1195,7 +1194,7 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
>   add_kgd_mem_to_kfd_bo_list(*mem, avm->process_info, user_addr);
>   
>   if (user_addr) {
> - ret = init_user_pages(*mem, current->mm, user_addr);
> + ret = init_user_pages(*mem, user_addr);
>   if (ret)
>   goto allocate_init_user_pages_failed;
>   }
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 5a1939dbd4e3e6..38f97998aaddb2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -2633,6 +2633,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
>   mutex_init(>virt.vf_errors.lock);
>   hash_init(adev->mn_hash);
>   mutex_init(>lock_reset);
> + mutex_init(>notifier_lock);
>   mutex_init(>virt.dpm_mutex);
>   mutex_init(>psp.mutex);
>   
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
> index 31d4deb5d29484..4ffd7b90f4d907 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
> @@ -50,66 +50,6 @@
>   #include "amdgpu.h"
>   #include "amdgpu_amdkfd.h"
>   
> -/**
> - * struct amdgpu_mn_node
> - *
> - * @it: interval node defining start-last of the affected address range
> - * @bos: list of all BOs in the affected address range
> - *
> - * Manages all BOs which are affected of a certain range of address space.
> - */
> -struct amdgpu_mn_node {
> - struct interval_tree_node   it;
> - struct list_headbos;
> -};
> -
> -/**
> - * amdgpu_mn_destroy - destroy the HMM mirror
> - *
> - * @work: previously sheduled work item
> - *
> - * Lazy destroys the notifier from a work item
> - */
> -static void amdgpu_mn_destroy(struct work_struct *work)
> -{
> - struct amdgpu_mn *amn = container_of(work, struct amdgpu_mn, work);
> - struct amdgpu_device *adev = amn->adev;
> - struct amdgpu_mn_node *node, *next_node;
> - struct amdgpu_bo *bo, *next_bo;
> -
> - mutex_lock(>mn_lock);
> - down_write(>lock);
> - hash_del(>node);
> - rbtree_postorder_for_each_entry_safe(node, next_node,
> -  >objects.rb_root, it.rb) {
> - list_for_each_entry_safe(bo, next_bo, >bos, mn_list) {
> - bo->mn = NULL;
> -   

Re: [PATCH v2 12/15] drm/amdgpu: Call find_vma under mmap_sem

[Koenig, Christian]

Am 28.10.19 um 21:10 schrieb Jason Gunthorpe:
> From: Jason Gunthorpe 
>
> find_vma() must be called under the mmap_sem, reorganize this code to
> do the vma check after entering the lock.
>
> Further, fix the unlocked use of struct task_struct's mm, instead use
> the mm from hmm_mirror which has an active mm_grab. Also the mm_grab
> must be converted to a mm_get before acquiring mmap_sem or calling
> find_vma().
>
> Fixes: 66c45500bfdc ("drm/amdgpu: use new HMM APIs and helpers")
> Fixes: 0919195f2b0d ("drm/amdgpu: Enable amdgpu_ttm_tt_get_user_pages in 
> worker threads")
> Cc: Alex Deucher 
> Cc: Christian König 
> Cc: David (ChunMing) Zhou 
> Cc: amd-gfx@lists.freedesktop.org
> Signed-off-by: Jason Gunthorpe 

Acked-by: Christian König 

> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 37 ++---
>   1 file changed, 21 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index dff41d0a85fe96..c0e41f1f0c2365 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -35,6 +35,7 @@
>   #include 
>   #include 
>   #include 
> +#include 
>   #include 
>   #include 
>   #include 
> @@ -788,7 +789,7 @@ int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, 
> struct page **pages)
>   struct hmm_mirror *mirror = bo->mn ? >mn->mirror : NULL;
>   struct ttm_tt *ttm = bo->tbo.ttm;
>   struct amdgpu_ttm_tt *gtt = (void *)ttm;
> - struct mm_struct *mm = gtt->usertask->mm;
> + struct mm_struct *mm;
>   unsigned long start = gtt->userptr;
>   struct vm_area_struct *vma;
>   struct hmm_range *range;
> @@ -796,25 +797,14 @@ int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, 
> struct page **pages)
>   uint64_t *pfns;
>   int r = 0;
>   
> - if (!mm) /* Happens during process shutdown */
> - return -ESRCH;
> -
>   if (unlikely(!mirror)) {
>   DRM_DEBUG_DRIVER("Failed to get hmm_mirror\n");
> - r = -EFAULT;
> - goto out;
> + return -EFAULT;
>   }
>   
> - vma = find_vma(mm, start);
> - if (unlikely(!vma || start < vma->vm_start)) {
> - r = -EFAULT;
> - goto out;
> - }
> - if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&
> - vma->vm_file)) {
> - r = -EPERM;
> - goto out;
> - }
> + mm = mirror->hmm->mmu_notifier.mm;
> + if (!mmget_not_zero(mm)) /* Happens during process shutdown */
> + return -ESRCH;
>   
>   range = kzalloc(sizeof(*range), GFP_KERNEL);
>   if (unlikely(!range)) {
> @@ -847,6 +837,17 @@ int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, 
> struct page **pages)
>   hmm_range_wait_until_valid(range, HMM_RANGE_DEFAULT_TIMEOUT);
>   
>   down_read(>mmap_sem);
> + vma = find_vma(mm, start);
> + if (unlikely(!vma || start < vma->vm_start)) {
> + r = -EFAULT;
> + goto out_unlock;
> + }
> + if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&
> + vma->vm_file)) {
> + r = -EPERM;
> + goto out_unlock;
> + }
> +
>   r = hmm_range_fault(range, 0);
>   up_read(>mmap_sem);
>   
> @@ -865,15 +866,19 @@ int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, 
> struct page **pages)
>   }
>   
>   gtt->range = range;
> + mmput(mm);
>   
>   return 0;
>   
> +out_unlock:
> + up_read(>mmap_sem);
>   out_free_pfns:
>   hmm_range_unregister(range);
>   kvfree(pfns);
>   out_free_ranges:
>   kfree(range);
>   out:
> + mmput(mm);
>   return r;
>   }
>   

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Re: [PATCH v2 07/15] drm/radeon: use mmu_range_notifier_insert

[Koenig, Christian]

Am 28.10.19 um 21:10 schrieb Jason Gunthorpe:
> From: Jason Gunthorpe 
>
> The new API is an exact match for the needs of radeon.
>
> For some reason radeon tries to remove overlapping ranges from the
> interval tree, but interval trees (and mmu_range_notifier_insert)
> support overlapping ranges directly. Simply delete all this code.
>
> Since this driver is missing a invalidate_range_end callback, but
> still calls get_user_pages(), it cannot be correct against all races.
>
> Cc: Alex Deucher 
> Cc: Christian König 
> Cc: David (ChunMing) Zhou 
> Cc: amd-gfx@lists.freedesktop.org
> Cc: Petr Cvek 
> Signed-off-by: Jason Gunthorpe 

Reviewed-by: Christian König 

> ---
>   drivers/gpu/drm/radeon/radeon.h|   9 +-
>   drivers/gpu/drm/radeon/radeon_mn.c | 219 ++---
>   2 files changed, 52 insertions(+), 176 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
> index d59b004f669583..27959f3ace1152 100644
> --- a/drivers/gpu/drm/radeon/radeon.h
> +++ b/drivers/gpu/drm/radeon/radeon.h
> @@ -68,6 +68,10 @@
>   #include 
>   #include 
>   
> +#ifdef CONFIG_MMU_NOTIFIER
> +#include 
> +#endif
> +
>   #include 
>   #include 
>   #include 
> @@ -509,8 +513,9 @@ struct radeon_bo {
>   struct ttm_bo_kmap_obj  dma_buf_vmap;
>   pid_t   pid;
>   
> - struct radeon_mn*mn;
> - struct list_headmn_list;
> +#ifdef CONFIG_MMU_NOTIFIER
> + struct mmu_range_notifier   notifier;
> +#endif
>   };
>   #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, 
> tbo.base)
>   
> diff --git a/drivers/gpu/drm/radeon/radeon_mn.c 
> b/drivers/gpu/drm/radeon/radeon_mn.c
> index dbab9a3a969b9e..d3d41e20a64922 100644
> --- a/drivers/gpu/drm/radeon/radeon_mn.c
> +++ b/drivers/gpu/drm/radeon/radeon_mn.c
> @@ -36,131 +36,51 @@
>   
>   #include "radeon.h"
>   
> -struct radeon_mn {
> - struct mmu_notifier mn;
> -
> - /* objects protected by lock */
> - struct mutexlock;
> - struct rb_root_cached   objects;
> -};
> -
> -struct radeon_mn_node {
> - struct interval_tree_node   it;
> - struct list_headbos;
> -};
> -
>   /**
> - * radeon_mn_invalidate_range_start - callback to notify about mm change
> + * radeon_mn_invalidate - callback to notify about mm change
>*
>* @mn: our notifier
> - * @mn: the mm this callback is about
> - * @start: start of updated range
> - * @end: end of updated range
> + * @range: the VMA under invalidation
>*
>* We block for all BOs between start and end to be idle and
>* unmap them by move them into system domain again.
>*/
> -static int radeon_mn_invalidate_range_start(struct mmu_notifier *mn,
> - const struct mmu_notifier_range *range)
> +static bool radeon_mn_invalidate(struct mmu_range_notifier *mn,
> +  const struct mmu_notifier_range *range,
> +  unsigned long cur_seq)
>   {
> - struct radeon_mn *rmn = container_of(mn, struct radeon_mn, mn);
> + struct radeon_bo *bo = container_of(mn, struct radeon_bo, notifier);
>   struct ttm_operation_ctx ctx = { false, false };
> - struct interval_tree_node *it;
> - unsigned long end;
> - int ret = 0;
> -
> - /* notification is exclusive, but interval is inclusive */
> - end = range->end - 1;
> -
> - /* TODO we should be able to split locking for interval tree and
> -  * the tear down.
> -  */
> - if (mmu_notifier_range_blockable(range))
> - mutex_lock(>lock);
> - else if (!mutex_trylock(>lock))
> - return -EAGAIN;
> -
> - it = interval_tree_iter_first(>objects, range->start, end);
> - while (it) {
> - struct radeon_mn_node *node;
> - struct radeon_bo *bo;
> - long r;
> -
> - if (!mmu_notifier_range_blockable(range)) {
> - ret = -EAGAIN;
> - goto out_unlock;
> - }
> -
> - node = container_of(it, struct radeon_mn_node, it);
> - it = interval_tree_iter_next(it, range->start, end);
> + long r;
>   
> - list_for_each_entry(bo, >bos, mn_list) {
> + if (!bo->tbo.ttm || bo->tbo.ttm->state != tt_bound)
> + return true;
>   
> - if (!bo->tbo.ttm || bo->tbo.ttm->state != tt_bound)
> - continue;
> + if (!mmu_notifier_range_blockable(range))
> + return false;
>   
> - r = radeon_bo_reserve(bo, true);
> - if (r) {
> - DRM_ERROR("(%ld) failed to reserve user bo\n", 
> r);
> - continue;
> - }
> -
> - r = dma_resv_wait_timeout_rcu(bo->tbo.base.resv,
> - true, false, MAX_SCHEDULE_TIMEOUT);
> -  

[PATCH] drm/amdgpu/SRIOV: Only reset hw.status for target IP

[jianzh]

From: Jiange Zhao 

In the old way, when doing IH hw_init, PSP, nv_common
and GMC hw.status would be reset to false, even though
their hw_init have been done. In the next step, fw_loading,
PSP would do hw_init again.

In the new way, only reset hw.status to false for the target
IP in the list. In this way, PSP will only do hw_init once.

Signed-off-by: Jiange Zhao 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 4eee40b9d0b0..ad6d2452fed9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2352,11 +2352,11 @@ static int amdgpu_device_ip_reinit_early_sriov(struct 
amdgpu_device *adev)
for (j = 0; j < adev->num_ip_blocks; j++) {
block = >ip_blocks[j];
 
-   block->status.hw = false;
if (block->version->type != ip_order[i] ||
!block->status.valid)
continue;
 
+   block->status.hw = false;
r = block->version->funcs->hw_init(adev);
DRM_INFO("RE-INIT-early: %s %s\n", 
block->version->funcs->name, r?"failed":"succeeded");
if (r)
-- 
2.20.1

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RE: [PATCH 4/4] drm/amdgpu: remove ras global recovery handling from ras_controller_int handler

[Ma, Le]

-Original Message-
From: Chen, Guchun 
Sent: Tuesday, October 29, 2019 9:37 AM
To: Ma, Le ; amd-gfx@lists.freedesktop.org
Cc: Ma, Le 
Subject: RE: [PATCH 4/4] drm/amdgpu: remove ras global recovery handling from 
ras_controller_int handler









Regards,

Guchun



-Original Message-

From: amd-gfx 
mailto:amd-gfx-boun...@lists.freedesktop.org>>
 On Behalf Of Le Ma

Sent: Monday, October 28, 2019 7:31 PM

To: amd-gfx@lists.freedesktop.org

Cc: Ma, Le mailto:le...@amd.com>>

Subject: [PATCH 4/4] drm/amdgpu: remove ras global recovery handling from 
ras_controller_int handler



From: Le Ma mailto:le...@amd.com>>



Change-Id: Ia8a61a4b3bd529f0f691e43e69b299d7d151c0c2

Signed-off-by: Le Ma mailto:le...@amd.com>>

---

drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 6 +-

1 file changed, 5 insertions(+), 1 deletion(-)



diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c 
b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c

index 0db458f..876690a 100644

--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c

+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c

@@ -324,7 +324,11 @@ static void 
nbio_v7_4_handle_ras_controller_intr_no_bifring(struct amdgpu_device

   
RAS_CNTLR_INTERRUPT_CLEAR, 1);

   WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, 
bif_doorbell_intr_cntl);

-   amdgpu_ras_global_ras_isr(adev);

+  /*

+  * ras_controller_int is dedicated for nbif ras error,

+  * not the global interrupt for sync flood

+  */

+  amdgpu_ras_reset_gpu(adev, true);

[Guchun]We need to add one printing here to tell audience, who and why resets 
gpu? And moreover, in the removed global ras isr handler 
amdgpu_ras_global_ras_isr, we call amdgpu_ras_reset_gpu with is_baco parameter 
"false", but now we use "true" here?

[Le] We may consider add printing here to indicate it’s ras controller 
interrupt issue. The is_baco parameter is unused and has no effect. Anyway, I 
will revise and hold on patch #2 and #4 when baco based RAS recovery totally 
works as Hawking’s comment.

   }

}

--

2.7.4



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RE: [PATCH 2/4] drm/amdgpu: reset err_event_athub flag if gpu recovery succeeded

[Ma, Le]

> -Original Message-

> From: Chen, Guchun 

> Sent: Tuesday, October 29, 2019 9:28 AM

> To: Ma, Le ; amd-gfx@lists.freedesktop.org

> Cc: Ma, Le 

> Subject: RE: [PATCH 2/4] drm/amdgpu: reset err_event_athub flag if gpu

> recovery succeeded

>

>

>

> Regards,

> Guchun

>

> -Original Message-

> From: amd-gfx 
> mailto:amd-gfx-boun...@lists.freedesktop.org>>
>  On Behalf Of Le Ma

> Sent: Monday, October 28, 2019 7:31 PM

> To: amd-gfx@lists.freedesktop.org

> Cc: Ma, Le mailto:le...@amd.com>>

> Subject: [PATCH 2/4] drm/amdgpu: reset err_event_athub flag if gpu recovery

> succeeded

>

> Otherwise next err_event_athub error cannot call gpu reset.

>

> Change-Id: I5cd293f30f23876bf2a1860681bcb50f47713ecd

> Signed-off-by: Le Ma mailto:le...@amd.com>>

> ---

>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 +++

>  1 file changed, 3 insertions(+)

>

> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

> index 676cad1..51d74bb 100644

> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

> @@ -4089,6 +4089,9 @@ int amdgpu_device_gpu_recover(struct

> amdgpu_device *adev,

>  }

>  }

>

> +  if (!r && in_ras_intr)

> +  atomic_set(_ras_in_intr, 0);

> [Guchun]To access this atomic variable, maybe it's better we create a new

> function like reset or clear in amdgpu_ras.h or .c first, then we can call 
> that

> function here, like we we do to amdgpu_ras_intr_triggered in this same

> function. This will do assist to modularity of ras driver.

> [Le] Agree with you. We could make it paired with amdgpu_ras_intr_triggered.



>  skip_sched_resume:

>  list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {

>  /*unlock kfd: SRIOV would do it separately */

> --

> 2.7.4

>

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