Re: [PATCH] drm/amdgpu: Fix the null pointer issue for tdr
The question is where do we rearm the timer for this problem to occur?
Regards,
Christian.
Am 12.11.19 um 20:21 schrieb Andrey Grodzovsky:
I was able to reproduce the crash by using the attached
simulate_crash.patch - waiting on guilty job to signal in reset work
and artificially rearming the timeout timer just before the check for
!cancel_delayed_work(>work_tdr) in drm_sched_cleanup_jobs -
crash log attached in crash.log. This I think confirms my theory i
described earlier in this thread.
basic_fix.patch handles this by testing whether another timer already
armed ob this scheduler or is there a timeout work in execution right
now (see documentation for work_busy) - obviously this is not a full
solution as this will not protect from races if for example there is
immediate work scheduling such as in drm_sched_fault - so we probably
need to account for this by making drm_sched_cleanup_jobs (at least in
the part where it iterates ring mirror list and frees jobs) and GPU
reset really mutually exclusive and not like now.
Andrey
On 11/11/19 4:11 PM, Christian König wrote:
Hi Emily,
you need to print which scheduler instance is freeing the jobs and
which one is triggering the reset. The TID and PID is completely
meaningless here since we are called from different worker threads
and the TID/PID can change on each call.
Apart from that I will look into this a bit deeper when I have time.
Regards,
Christian.
Am 12.11.19 um 07:02 schrieb Deng, Emily:
Hi Christian,
I add the follow print in function drm_sched_cleanup_jobs. From
the log it shows that only use cancel_delayed_work could not avoid
to free job when the sched is in reset. But don’t know exactly where
it is wrong about the driver. Do you have any suggestion about this?
+ printk("Emily:drm_sched_cleanup_jobs:begin,tid:%lu, pid:%lu\n",
current->tgid, current->pid);
/*
* Don't destroy jobs while the timeout worker is running
OR thread
* is being parked and hence assumed to not touch
ring_mirror_list
*/
if ((sched->timeout != MAX_SCHEDULE_TIMEOUT &&
!cancel_delayed_work(>work_tdr)))
return;
+ printk("Emily:drm_sched_cleanup_jobs,tid:%lu, pid:%lu\n",
current->tgid, current->pid);
Best wishes
Emily Deng
Nov 12 12:58:20 ubuntu-drop-August-2018-rc2-gpu0-vf02 kernel:
[11380.695091] Emily:drm_sched_cleanup_jobs:begin,tid:2262, pid:2262
Nov 12 12:58:20 ubuntu-drop-August-2018-rc2-gpu0-vf02 kernel:
[11380.695104] Emily:drm_sched_cleanup_jobs:begin,tid:2262, pid:2262
Nov 12 12:58:20 ubuntu-drop-August-2018-rc2-gpu0-vf02 kernel:
[11380.695105] Emily:drm_sched_cleanup_jobs,tid:2262, pid:2262
Nov 12 12:58:20 ubuntu-drop-August-2018-rc2-gpu0-vf02 kernel:
[11380.695107] Emily:drm_sched_cleanup_jobs:begin,tid:2262, pid:2262
Nov 12 12:58:20 ubuntu-drop-August-2018-rc2-gpu0-vf02 kernel:
[11380.695107] Emily:drm_sched_cleanup_jobs,tid:2262, pid:2262
Nov 12 12:58:20 ubuntu-drop-August-2018-rc2-gpu0-vf02 kernel:
[11381.222954] [drm:amdgpu_job_timedout [amdgpu]] *ERROR* ring sdma0
timeout, signaled seq=78585, emitted seq=78587
Nov 12 12:58:20 ubuntu-drop-August-2018-rc2-gpu0-vf02 kernel:
[11381.224275] [drm:amdgpu_job_timedout [amdgpu]] *ERROR* Process
information: process pid 0 thread pid 0,
s_job:fe75ab36,tid=15603, pid=15603
Nov 12 12:58:20 ubuntu-drop-August-2018-rc2-gpu0-vf02 kernel:
[11381.225413] amdgpu :00:08.0: GPU reset begin!
Nov 12 12:58:20 ubuntu-drop-August-2018-rc2-gpu0-vf02 kernel:
[11381.225417] Emily:drm_sched_cleanup_jobs:begin,tid:2262, pid:2262
Nov 12 12:58:20 ubuntu-drop-August-2018-rc2-gpu0-vf02 kernel:
[11381.225425] Emily:drm_sched_cleanup_jobs:begin,tid:2262, pid:2262
Nov 12 12:58:20 ubuntu-drop-August-2018-rc2-gpu0-vf02 kernel:
[11381.225425] Emily:drm_sched_cleanup_jobs,tid:2262, pid:2262
Nov 12 12:58:20 ubuntu-drop-August-2018-rc2-gpu0-vf02 kernel:
[11381.225428] Emily:amdgpu_job_free_cb,Process information:
process pid 0 thread pid 0, s_job:fe75ab36, tid:2262, pid:2262
Nov 12 12:58:20 ubuntu-drop-August-2018-rc2-gpu0-vf02 kernel:
[11381.225429] Emily:drm_sched_cleanup_jobs:begin,tid:2262, pid:2262
Nov 12 12:58:20 ubuntu-drop-August-2018-rc2-gpu0-vf02 kernel:
[11381.225430] Emily:drm_sched_cleanup_jobs,tid:2262, pid:2262
Nov 12 12:58:20 ubuntu-drop-August-2018-rc2-gpu0-vf02 kernel:
[11381.225473] Emily:drm_sched_cleanup_jobs:begin,tid:2253, pid:2253
Nov 12 12:58:20 ubuntu-drop-August-2018-rc2-gpu0-vf02 kernel:
[11381.225486] Emily:drm_sched_cleanup_jobs:begin,tid:2262, pid:2262
Nov 12 12:58:20 ubuntu-drop-August-2018-rc2-gpu0-vf02 kernel:
[11381.225489] Emily:drm_sched_cleanup_jobs,tid:2262, pid:2262
Nov 12 12:58:20 ubuntu-drop-August-2018-rc2-gpu0-vf02 kernel:
[11381.225494] Emily:amdgpu_job_free_cb,Process information:
process pid 0 thread pid 0, s_job:f086ec84, tid:2262, pid:2262
>-Original Message-
>From: Grodzovsky, Andrey
>Sent: Tuesday, November 12, 2019 11:28 AM
RE: [PATCH 13/21] drm/amd/powerplay: add Powergate JPEG for Renoir
On Renior, both SMU_MSG_PowerDownJpeg and SMU_MSG_PowerUpJpeg need an argument.
> -Original Message-
> From: amd-gfx On Behalf Of Leo Liu
> Sent: Wednesday, November 13, 2019 2:03 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Liu, Leo
> Subject: [PATCH 13/21] drm/amd/powerplay: add Powergate JPEG for Renoir
>
> Similar to SDMA, VCN etc.
>
> Signed-off-by: Leo Liu
> ---
> drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 2 ++
> drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h | 2 ++
> drivers/gpu/drm/amd/powerplay/renoir_ppt.c| 1 +
> drivers/gpu/drm/amd/powerplay/smu_internal.h | 2 ++
> drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 11 +++
> 5 files changed, 18 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> index 69243a858dd5..211934521d37 100644
> --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> @@ -1229,6 +1229,7 @@ static int smu_hw_init(void *handle)
> if (adev->flags & AMD_IS_APU) {
> smu_powergate_sdma(>smu, false);
> smu_powergate_vcn(>smu, false);
> + smu_powergate_jpeg(>smu, false);
> smu_set_gfx_cgpg(>smu, true);
> }
>
> @@ -1287,6 +1288,7 @@ static int smu_hw_fini(void *handle)
> if (adev->flags & AMD_IS_APU) {
> smu_powergate_sdma(>smu, true);
> smu_powergate_vcn(>smu, true);
> + smu_powergate_jpeg(>smu, true);
> }
>
> ret = smu_stop_thermal_control(smu);
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
> b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
> index 9b9f5df0911c..1745e0146fba 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
> @@ -58,6 +58,8 @@ int smu_v12_0_powergate_sdma(struct smu_context
> *smu, bool gate);
>
> int smu_v12_0_powergate_vcn(struct smu_context *smu, bool gate);
>
> +int smu_v12_0_powergate_jpeg(struct smu_context *smu, bool gate);
> +
> int smu_v12_0_set_gfx_cgpg(struct smu_context *smu, bool enable);
>
> uint32_t smu_v12_0_get_gfxoff_status(struct smu_context *smu); diff --git
> a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
> b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
> index 04daf7e9fe05..492a201554e8 100644
> --- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
> @@ -697,6 +697,7 @@ static const struct pptable_funcs renoir_ppt_funcs = {
> .check_fw_version = smu_v12_0_check_fw_version,
> .powergate_sdma = smu_v12_0_powergate_sdma,
> .powergate_vcn = smu_v12_0_powergate_vcn,
> + .powergate_jpeg = smu_v12_0_powergate_jpeg,
> .send_smc_msg = smu_v12_0_send_msg,
> .send_smc_msg_with_param = smu_v12_0_send_msg_with_param,
> .read_smc_arg = smu_v12_0_read_arg,
> diff --git a/drivers/gpu/drm/amd/powerplay/smu_internal.h
> b/drivers/gpu/drm/amd/powerplay/smu_internal.h
> index 8bcda7871309..70c4d66721cd 100644
> --- a/drivers/gpu/drm/amd/powerplay/smu_internal.h
> +++ b/drivers/gpu/drm/amd/powerplay/smu_internal.h
> @@ -42,6 +42,8 @@
> ((smu)->ppt_funcs->powergate_sdma ? (smu)->ppt_funcs-
> >powergate_sdma((smu), (gate)) : 0) #define smu_powergate_vcn(smu, gate)
> \
> ((smu)->ppt_funcs->powergate_vcn ? (smu)->ppt_funcs-
> >powergate_vcn((smu), (gate)) : 0)
> +#define smu_powergate_jpeg(smu, gate) \
> + ((smu)->ppt_funcs->powergate_jpeg ?
> +(smu)->ppt_funcs->powergate_jpeg((smu), (gate)) : 0)
>
> #define smu_get_vbios_bootup_values(smu) \
> ((smu)->ppt_funcs->get_vbios_bootup_values ? (smu)->ppt_funcs-
> >get_vbios_bootup_values((smu)) : 0) diff --git
> a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
> b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
> index 139dd737eaa5..f5d87110ec34 100644
> --- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
> +++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
> @@ -203,6 +203,17 @@ int smu_v12_0_powergate_vcn(struct smu_context
> *smu, bool gate)
> return smu_send_smc_msg(smu, SMU_MSG_PowerUpVcn); }
>
> +int smu_v12_0_powergate_jpeg(struct smu_context *smu, bool gate) {
> + if (!(smu->adev->flags & AMD_IS_APU))
> + return 0;
> +
> + if (gate)
> + return smu_send_smc_msg(smu, SMU_MSG_PowerDownJpeg);
> + else
> + return smu_send_smc_msg(smu, SMU_MSG_PowerUpJpeg); }
> +
> int smu_v12_0_set_gfx_cgpg(struct smu_context *smu, bool enable) {
> if (!(smu->adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
> --
> 2.17.1
>
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RE: [PATCH 14/21] drm/amd/powerplay: add JPEG power control for Renoir
On Renior, both SMU_MSG_PowerDownJpeg and SMU_MSG_PowerUpJpeg need an argument.
> -Original Message-
> From: amd-gfx On Behalf Of Leo Liu
> Sent: Wednesday, November 13, 2019 2:03 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Liu, Leo
> Subject: [PATCH 14/21] drm/amd/powerplay: add JPEG power control for
> Renoir
>
> By using its own JPEG PowerUp and PowerDown messages
>
> Signed-off-by: Leo Liu
> ---
> drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 26 ++
> 1 file changed, 26 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
> b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
> index 492a201554e8..f561fb9cc951 100644
> --- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
> @@ -301,6 +301,31 @@ static int renoir_dpm_set_uvd_enable(struct
> smu_context *smu, bool enable)
> return ret;
> }
>
> +static int renoir_dpm_set_jpeg_enable(struct smu_context *smu, bool
> +enable) {
> + struct smu_power_context *smu_power = >smu_power;
> + struct smu_power_gate *power_gate = _power->power_gate;
> + int ret = 0;
> +
> + if (enable) {
> + if (smu_feature_is_enabled(smu,
> SMU_FEATURE_JPEG_PG_BIT)) {
> + ret = smu_send_smc_msg_with_param(smu,
> SMU_MSG_PowerUpJpeg, 0);
> + if (ret)
> + return ret;
> + }
> + power_gate->jpeg_gated = false;
> + } else {
> + if (smu_feature_is_enabled(smu,
> SMU_FEATURE_JPEG_PG_BIT)) {
> + ret = smu_send_smc_msg(smu,
> SMU_MSG_PowerDownJpeg);
> + if (ret)
> + return ret;
> + }
> + power_gate->jpeg_gated = true;
> + }
> +
> + return ret;
> +}
> +
> static int renoir_force_dpm_limit_value(struct smu_context *smu, bool
> highest)
> {
> int ret = 0, i = 0;
> @@ -683,6 +708,7 @@ static const struct pptable_funcs renoir_ppt_funcs = {
> .print_clk_levels = renoir_print_clk_levels,
> .get_current_power_state = renoir_get_current_power_state,
> .dpm_set_uvd_enable = renoir_dpm_set_uvd_enable,
> + .dpm_set_jpeg_enable = renoir_dpm_set_jpeg_enable,
> .force_dpm_limit_value = renoir_force_dpm_limit_value,
> .unforce_dpm_levels = renoir_unforce_dpm_levels,
> .get_workload_type = renoir_get_workload_type,
> --
> 2.17.1
>
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RE: [PATCH 12/21] drm/amd/powerplay: add JPEG power control for Navi1x
For Navi10, SMU_MSG_PowerUpJpeg message does not need an argument.
> -Original Message-
> From: amd-gfx On Behalf Of Leo Liu
> Sent: Wednesday, November 13, 2019 2:03 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Liu, Leo
> Subject: [PATCH 12/21] drm/amd/powerplay: add JPEG power control for
> Navi1x
>
> By separating the JPEG power feature, and using its own PowerUp and
> PowerDown messages
>
> Signed-off-by: Leo Liu
> ---
> drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 32 --
> 1 file changed, 30 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> index aeb9c1e341c7..760568debe6c 100644
> --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> @@ -384,8 +384,10 @@ navi10_get_allowed_feature_mask(struct
> smu_context *smu,
> *(uint64_t *)feature_mask |=
> FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
>
> if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN)
> - *(uint64_t *)feature_mask |=
> FEATURE_MASK(FEATURE_VCN_PG_BIT)
> - | FEATURE_MASK(FEATURE_JPEG_PG_BIT);
> + *(uint64_t *)feature_mask |=
> FEATURE_MASK(FEATURE_VCN_PG_BIT);
> +
> + if (smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
> + *(uint64_t *)feature_mask |=
> FEATURE_MASK(FEATURE_JPEG_PG_BIT);
>
> /* disable DPM UCLK and DS SOCCLK on navi10 A0 secure board */
> if (is_asic_secure(smu)) {
> @@ -665,6 +667,31 @@ static int navi10_dpm_set_uvd_enable(struct
> smu_context *smu, bool enable)
> return ret;
> }
>
> +static int navi10_dpm_set_jpeg_enable(struct smu_context *smu, bool
> +enable) {
> + struct smu_power_context *smu_power = >smu_power;
> + struct smu_power_gate *power_gate = _power->power_gate;
> + int ret = 0;
> +
> + if (enable) {
> + if (smu_feature_is_enabled(smu,
> SMU_FEATURE_JPEG_PG_BIT)) {
> + ret = smu_send_smc_msg_with_param(smu,
> SMU_MSG_PowerUpJpeg, 1);
> + if (ret)
> + return ret;
> + }
> + power_gate->jpeg_gated = false;
> + } else {
> + if (smu_feature_is_enabled(smu,
> SMU_FEATURE_JPEG_PG_BIT)) {
> + ret = smu_send_smc_msg(smu,
> SMU_MSG_PowerDownJpeg);
> + if (ret)
> + return ret;
> + }
> + power_gate->jpeg_gated = true;
> + }
> +
> + return ret;
> +}
> +
> static int navi10_get_current_clk_freq_by_table(struct smu_context *smu,
> enum smu_clk_type clk_type,
> uint32_t *value)
> @@ -1996,6 +2023,7 @@ static const struct pptable_funcs navi10_ppt_funcs =
> {
> .get_allowed_feature_mask = navi10_get_allowed_feature_mask,
> .set_default_dpm_table = navi10_set_default_dpm_table,
> .dpm_set_uvd_enable = navi10_dpm_set_uvd_enable,
> + .dpm_set_jpeg_enable = navi10_dpm_set_jpeg_enable,
> .get_current_clk_freq_by_table =
> navi10_get_current_clk_freq_by_table,
> .print_clk_levels = navi10_print_clk_levels,
> .force_clk_levels = navi10_force_clk_levels,
> --
> 2.17.1
>
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RE: [PATCH] drm/amdgpu: don't read registers if gfxoff is enabled (v2)
This patch is reviewed-by: Evan Quan
However, i just find we need a separate patch to clear PP_GFXOFF_MASK support
from Arcturus.
Can you do that or you want me to do that?
> -Original Message-
> From: amd-gfx On Behalf Of Alex
> Deucher
> Sent: Tuesday, November 12, 2019 11:13 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander
> Subject: [PATCH] drm/amdgpu: don't read registers if gfxoff is enabled (v2)
>
> When gfxoff is enabled, accessing gfx registers via MMIO
> can lead to a hang.
>
> v2: return cached registers properly.
>
> Bug: https://bugzilla.kernel.org/show_bug.cgi?id=205497
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/nv.c| 27 --
> drivers/gpu/drm/amd/amdgpu/soc15.c | 31 ++
> 2 files changed, 36 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c
> b/drivers/gpu/drm/amd/amdgpu/nv.c
> index af68f9815f28..7283d6198b89 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nv.c
> @@ -201,17 +201,25 @@ static uint32_t nv_read_indexed_register(struct
> amdgpu_device *adev, u32 se_num,
> return val;
> }
>
> -static uint32_t nv_get_register_value(struct amdgpu_device *adev,
> +static int nv_get_register_value(struct amdgpu_device *adev,
> bool indexed, u32 se_num,
> - u32 sh_num, u32 reg_offset)
> + u32 sh_num, u32 reg_offset,
> + u32 *value)
> {
> if (indexed) {
> - return nv_read_indexed_register(adev, se_num, sh_num,
> reg_offset);
> + if (adev->pm.pp_feature & PP_GFXOFF_MASK)
> + return -EINVAL;
> + *value = nv_read_indexed_register(adev, se_num, sh_num,
> reg_offset);
> } else {
> - if (reg_offset == SOC15_REG_OFFSET(GC, 0,
> mmGB_ADDR_CONFIG))
> - return adev->gfx.config.gb_addr_config;
> - return RREG32(reg_offset);
> + if (reg_offset == SOC15_REG_OFFSET(GC, 0,
> mmGB_ADDR_CONFIG)) {
> + *value = adev->gfx.config.gb_addr_config;
> + } else {
> + if (adev->pm.pp_feature & PP_GFXOFF_MASK)
> + return -EINVAL;
> + *value = RREG32(reg_offset);
> + }
> }
> + return 0;
> }
>
> static int nv_read_register(struct amdgpu_device *adev, u32 se_num,
> @@ -227,10 +235,9 @@ static int nv_read_register(struct amdgpu_device
> *adev, u32 se_num,
> (adev->reg_offset[en->hwip][en->inst][en->seg] + en-
> >reg_offset))
> continue;
>
> - *value = nv_get_register_value(adev,
> -
> nv_allowed_read_registers[i].grbm_indexed,
> -se_num, sh_num, reg_offset);
> - return 0;
> + return nv_get_register_value(adev,
> +
> nv_allowed_read_registers[i].grbm_indexed,
> + se_num, sh_num, reg_offset, value);
> }
> return -EINVAL;
> }
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
> b/drivers/gpu/drm/amd/amdgpu/soc15.c
> index 305ad3eec987..2cc16e9f39fb 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> @@ -363,19 +363,27 @@ static uint32_t soc15_read_indexed_register(struct
> amdgpu_device *adev, u32 se_n
> return val;
> }
>
> -static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
> +static int soc15_get_register_value(struct amdgpu_device *adev,
>bool indexed, u32 se_num,
> - u32 sh_num, u32 reg_offset)
> + u32 sh_num, u32 reg_offset,
> + u32 *value)
> {
> if (indexed) {
> - return soc15_read_indexed_register(adev, se_num, sh_num,
> reg_offset);
> + if (adev->pm.pp_feature & PP_GFXOFF_MASK)
> + return -EINVAL;
> + *value = soc15_read_indexed_register(adev, se_num, sh_num,
> reg_offset);
> } else {
> - if (reg_offset == SOC15_REG_OFFSET(GC, 0,
> mmGB_ADDR_CONFIG))
> - return adev->gfx.config.gb_addr_config;
> - else if (reg_offset == SOC15_REG_OFFSET(GC, 0,
> mmDB_DEBUG2))
> - return adev->gfx.config.db_debug2;
> - return RREG32(reg_offset);
> + if (reg_offset == SOC15_REG_OFFSET(GC, 0,
> mmGB_ADDR_CONFIG)) {
> + *value = adev->gfx.config.gb_addr_config;
> + } else if (reg_offset == SOC15_REG_OFFSET(GC, 0,
> mmDB_DEBUG2)) {
> + *value = adev->gfx.config.db_debug2;
> + } else {
> + if (adev->pm.pp_feature & PP_GFXOFF_MASK)
> +
[PATCH 1/2] drm/amdkfd: Merge CIK kernel queue functions into VI
The only difference that CIK kernel queue functions are different from
VI is avoid allocating eop_mem. We can achieve that by using a if
condition.
Change-Id: Iea9cbc82f603ff008a906c5ee32325ddcd02d963
Signed-off-by: Yong Zhao
---
drivers/gpu/drm/amd/amdkfd/Makefile | 1 -
drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c | 7 +--
drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.h | 1 -
.../gpu/drm/amd/amdkfd/kfd_kernel_queue_cik.c | 53 ---
.../gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c | 7 +++
5 files changed, 9 insertions(+), 60 deletions(-)
delete mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_cik.c
diff --git a/drivers/gpu/drm/amd/amdkfd/Makefile
b/drivers/gpu/drm/amd/amdkfd/Makefile
index 017a8b7156da..f93a16372325 100644
--- a/drivers/gpu/drm/amd/amdkfd/Makefile
+++ b/drivers/gpu/drm/amd/amdkfd/Makefile
@@ -38,7 +38,6 @@ AMDKFD_FILES := $(AMDKFD_PATH)/kfd_module.o \
$(AMDKFD_PATH)/kfd_mqd_manager_v9.o \
$(AMDKFD_PATH)/kfd_mqd_manager_v10.o \
$(AMDKFD_PATH)/kfd_kernel_queue.o \
- $(AMDKFD_PATH)/kfd_kernel_queue_cik.o \
$(AMDKFD_PATH)/kfd_kernel_queue_vi.o \
$(AMDKFD_PATH)/kfd_kernel_queue_v9.o \
$(AMDKFD_PATH)/kfd_packet_manager.o \
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
index 0d966408ea87..a750b1d110eb 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
@@ -311,6 +311,8 @@ struct kernel_queue *kernel_queue_init(struct kfd_dev *dev,
kq->ops.rollback_packet = rollback_packet;
switch (dev->device_info->asic_family) {
+ case CHIP_KAVERI:
+ case CHIP_HAWAII:
case CHIP_CARRIZO:
case CHIP_TONGA:
case CHIP_FIJI:
@@ -321,11 +323,6 @@ struct kernel_queue *kernel_queue_init(struct kfd_dev *dev,
kernel_queue_init_vi(>ops_asic_specific);
break;
- case CHIP_KAVERI:
- case CHIP_HAWAII:
- kernel_queue_init_cik(>ops_asic_specific);
- break;
-
case CHIP_VEGA10:
case CHIP_VEGA12:
case CHIP_VEGA20:
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.h
b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.h
index a7116a939029..a9a35897d8b7 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.h
@@ -99,7 +99,6 @@ struct kernel_queue {
struct list_headlist;
};
-void kernel_queue_init_cik(struct kernel_queue_ops *ops);
void kernel_queue_init_vi(struct kernel_queue_ops *ops);
void kernel_queue_init_v9(struct kernel_queue_ops *ops);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_cik.c
b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_cik.c
deleted file mode 100644
index 19e54acb4125..
--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_cik.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * Copyright 2014 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#include "kfd_kernel_queue.h"
-
-static bool initialize_cik(struct kernel_queue *kq, struct kfd_dev *dev,
- enum kfd_queue_type type, unsigned int queue_size);
-static void uninitialize_cik(struct kernel_queue *kq);
-static void submit_packet_cik(struct kernel_queue *kq);
-
-void kernel_queue_init_cik(struct kernel_queue_ops *ops)
-{
- ops->initialize = initialize_cik;
- ops->uninitialize = uninitialize_cik;
- ops->submit_packet = submit_packet_cik;
-}
-
-static bool initialize_cik(struct kernel_queue *kq, struct kfd_dev *dev,
- enum kfd_queue_type type, unsigned int queue_size)
-{
- return true;
-}
-
-static void uninitialize_cik(struct kernel_queue *kq)
-{
-}
-
-static void submit_packet_cik(struct kernel_queue *kq)
-{
-
[PATCH 2/2] drm/amdkfd: Eliminate ops_asic_specific in kernel queue
The ops_asic_specific function pointers are actually quite generic after
using a simple if condition. Eliminate it by code refactoring.
Change-Id: Icb891289cca31acdbe2d2eea76a426f1738b9c08
Signed-off-by: Yong Zhao
---
drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c | 63 ---
drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.h | 4 --
.../gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c | 36 ---
.../gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c | 48 --
4 files changed, 26 insertions(+), 125 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
index a750b1d110eb..59ee9053498c 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
@@ -87,9 +87,17 @@ static bool initialize(struct kernel_queue *kq, struct
kfd_dev *dev,
kq->pq_kernel_addr = kq->pq->cpu_ptr;
kq->pq_gpu_addr = kq->pq->gpu_addr;
- retval = kq->ops_asic_specific.initialize(kq, dev, type, queue_size);
- if (!retval)
- goto err_eop_allocate_vidmem;
+ /* For CIK family asics, kq->eop_mem is not needed */
+ if (dev->device_info->asic_family > CHIP_HAWAII) {
+ retval = kfd_gtt_sa_allocate(dev, PAGE_SIZE, >eop_mem);
+ if (retval != 0)
+ goto err_eop_allocate_vidmem;
+
+ kq->eop_gpu_addr = kq->eop_mem->gpu_addr;
+ kq->eop_kernel_addr = kq->eop_mem->cpu_ptr;
+
+ memset(kq->eop_kernel_addr, 0, PAGE_SIZE);
+ }
retval = kfd_gtt_sa_allocate(dev, sizeof(*kq->rptr_kernel),
>rptr_mem);
@@ -200,7 +208,12 @@ static void uninitialize(struct kernel_queue *kq)
kfd_gtt_sa_free(kq->dev, kq->rptr_mem);
kfd_gtt_sa_free(kq->dev, kq->wptr_mem);
- kq->ops_asic_specific.uninitialize(kq);
+
+ /* For CIK family asics, kq->eop_mem is Null, kfd_gtt_sa_free()
+* is able to handle NULL properly.
+*/
+ kfd_gtt_sa_free(kq->dev, kq->eop_mem);
+
kfd_gtt_sa_free(kq->dev, kq->pq);
kfd_release_kernel_doorbell(kq->dev,
kq->queue->properties.doorbell_ptr);
@@ -280,8 +293,15 @@ static void submit_packet(struct kernel_queue *kq)
}
pr_debug("\n");
#endif
-
- kq->ops_asic_specific.submit_packet(kq);
+ if (kq->dev->device_info->doorbell_size == 8) {
+ *kq->wptr64_kernel = kq->pending_wptr64;
+ write_kernel_doorbell64(kq->queue->properties.doorbell_ptr,
+ kq->pending_wptr64);
+ } else {
+ *kq->wptr_kernel = kq->pending_wptr;
+ write_kernel_doorbell(kq->queue->properties.doorbell_ptr,
+ kq->pending_wptr);
+ }
}
static void rollback_packet(struct kernel_queue *kq)
@@ -310,42 +330,11 @@ struct kernel_queue *kernel_queue_init(struct kfd_dev
*dev,
kq->ops.submit_packet = submit_packet;
kq->ops.rollback_packet = rollback_packet;
- switch (dev->device_info->asic_family) {
- case CHIP_KAVERI:
- case CHIP_HAWAII:
- case CHIP_CARRIZO:
- case CHIP_TONGA:
- case CHIP_FIJI:
- case CHIP_POLARIS10:
- case CHIP_POLARIS11:
- case CHIP_POLARIS12:
- case CHIP_VEGAM:
- kernel_queue_init_vi(>ops_asic_specific);
- break;
-
- case CHIP_VEGA10:
- case CHIP_VEGA12:
- case CHIP_VEGA20:
- case CHIP_RAVEN:
- case CHIP_RENOIR:
- case CHIP_ARCTURUS:
- case CHIP_NAVI10:
- case CHIP_NAVI12:
- case CHIP_NAVI14:
- kernel_queue_init_v9(>ops_asic_specific);
- break;
- default:
- WARN(1, "Unexpected ASIC family %u",
-dev->device_info->asic_family);
- goto out_free;
- }
-
if (kq->ops.initialize(kq, dev, type, KFD_KERNEL_QUEUE_SIZE))
return kq;
pr_err("Failed to init kernel queue\n");
-out_free:
kfree(kq);
return NULL;
}
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.h
b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.h
index a9a35897d8b7..475e9499c0af 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.h
@@ -66,7 +66,6 @@ struct kernel_queue_ops {
struct kernel_queue {
struct kernel_queue_ops ops;
- struct kernel_queue_ops ops_asic_specific;
/* data */
struct kfd_dev *dev;
@@ -99,7 +98,4 @@ struct kernel_queue {
struct list_headlist;
};
-void kernel_queue_init_vi(struct kernel_queue_ops *ops);
-void kernel_queue_init_v9(struct kernel_queue_ops *ops);
-
#endif /* KFD_KERNEL_QUEUE_H_ */
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c
Re: [PATCH 2/3] drm/amdkfd: Update get_wave_state() for GFX10
On 2019-11-11 6:25 p.m., Yong Zhao wrote:
Given control stack is now in the userspace context save restore area
on GFX10, the same as GFX8, it is not needed to copy it back to userspace.
Change-Id: I063ddc3026eefa57713ec47b466a90f9bf9d49b8
Signed-off-by: Yong Zhao
Patches 1 and 2 are
Reviewed-by: Felix Kuehling
Patch 3 should arguably not be part of this series, because it does not
affect GFXv10.
Regards,
Felix
---
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
index 4884cd6c65ce..954dc8ac4ff1 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
@@ -251,18 +251,22 @@ static int get_wave_state(struct mqd_manager *mm, void
*mqd,
{
struct v10_compute_mqd *m;
- /* Control stack is located one page after MQD. */
- void *mqd_ctl_stack = (void *)((uintptr_t)mqd + PAGE_SIZE);
-
m = get_mqd(mqd);
+ /* Control stack is written backwards, while workgroup context data
+* is written forwards. Both starts from m->cp_hqd_cntl_stack_size.
+* Current position is at m->cp_hqd_cntl_stack_offset and
+* m->cp_hqd_wg_state_offset, respectively.
+*/
*ctl_stack_used_size = m->cp_hqd_cntl_stack_size -
m->cp_hqd_cntl_stack_offset;
*save_area_used_size = m->cp_hqd_wg_state_offset -
m->cp_hqd_cntl_stack_size;
- if (copy_to_user(ctl_stack, mqd_ctl_stack, m->cp_hqd_cntl_stack_size))
- return -EFAULT;
+ /* Control stack is not copied to user mode for GFXv10 because
+* it's part of the context save area that is already
+* accessible to user mode
+*/
return 0;
}
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Re: [PATCH V3 0/3] drm: replace magic numbers
On Tue, Nov 12, 2019 at 07:35:53PM +, Deucher, Alexander wrote:
> > -Original Message-
> > From: amd-gfx On Behalf Of
> > Bjorn Helgaas
> > Sent: Tuesday, November 12, 2019 12:35 PM
> > To: Deucher, Alexander ; Koenig, Christian
> > ; Zhou, David(ChunMing)
> > ; David Airlie ; Daniel Vetter
> >
> > Cc: Frederick Lawler ; linux-...@vger.kernel.org;
> > Michel Dänzer ; linux-ker...@vger.kernel.org; dri-
> > de...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org; Bjorn Helgaas
> > ; Ilia Mirkin
> > Subject: [PATCH V3 0/3] drm: replace magic numbers
> >
> > From: Bjorn Helgaas
> >
> > amdgpu and radeon do a bit of mucking with the PCIe Link Control 2 register,
> > some of it using hard-coded magic numbers. The idea here is to replace
> > those with #defines.
> >
> > Since v2:
> > - Fix a gpu_cfg2 case in amdgpu/si.c that I had missed
> > - Separate out the functional changes for better bisection (thanks,
> > Michel!)
> > - Add #defines in a patch by themselves (so a GPU revert wouldn't break
> > other potential users)
> > - Squash all the magic number -> #define changes into one patch
> >
> > Since v1:
> > - Add my signed-off-by and Alex's reviewed-by.
> >
>
> Series is:
> Reviewed-by: Alex Deucher
>
> I'm happy to have it go through whatever tree is easiest for you.
OK, thanks! I applied your reviewed-by and put these on my pci/misc
branch for v5.5, in hopes that we might get a followup patch from Fred
along the lines of 6133b9204c0a ("cxgb4: Prefer
pcie_capability_read_word()")
> > Bjorn Helgaas (3):
> > PCI: Add #defines for Enter Compliance, Transmit Margin
> > drm: correct Transmit Margin masks
> > drm: replace numbers with PCI_EXP_LNKCTL2 definitions
> >
> > drivers/gpu/drm/amd/amdgpu/cik.c | 22 ++
> > drivers/gpu/drm/amd/amdgpu/si.c | 22 ++
> > drivers/gpu/drm/radeon/cik.c | 22 ++
> > drivers/gpu/drm/radeon/si.c | 22 ++
> > include/uapi/linux/pci_regs.h| 2 ++
> > 5 files changed, 58 insertions(+), 32 deletions(-)
> >
> > --
> > 2.24.0.rc1.363.gb1bccd3e3d-goog
> >
> > ___
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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Re: [PATCH 2/2] drm/amdkfd: Stop using GFP_NOIO explicitly for GFX10
On 2019-11-12 4:35 p.m., Yong Zhao wrote:
Hi Felix,
See one thing inline I am not too sure.
Yong
On 2019-11-12 4:30 p.m., Felix Kuehling wrote:
On 2019-11-12 4:26 p.m., Yong Zhao wrote:
Adapt the change from 1cd106ecfc1f04
The change is:
drm/amdkfd: Stop using GFP_NOIO explicitly
This is no longer needed with the memalloc_nofs_save/restore in
dqm_lock/unlock
Change-Id: I42450b2c149d2b1842be99a8f355c829a0079e7c
Signed-off-by: Yong Zhao
The series is
Reviewed-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c | 2 +-
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
index 46ddb33b624a..579c5ffcfa79 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
@@ -393,7 +393,7 @@ struct mqd_manager *mqd_manager_init_v10(enum
KFD_MQD_TYPE type,
if (WARN_ON(type >= KFD_MQD_TYPE_MAX))
return NULL;
- mqd = kzalloc(sizeof(*mqd), GFP_NOIO);
+ mqd = kzalloc(sizeof(*mqd), GFP_KERNEL);
if (!mqd)
return NULL;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
index be27ff01cdb8..22a819c888d8 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
@@ -92,7 +92,7 @@ static struct kfd_mem_obj *allocate_mqd(struct
kfd_dev *kfd,
* instead of sub-allocation function.
*/
if (kfd->cwsr_enabled && (q->type == KFD_QUEUE_TYPE_COMPUTE)) {
- mqd_mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_NOIO);
+ mqd_mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL);
[yz] This should be kept probably. With the latest code,
allocate_mqd() is called outside of the dqm. So now the situation is
different from the original one.
Memory allocations outside the DQM lock are not problematic. Only memory
allocations under the DQM lock need to be careful to avoid FS reclaim,
because that can lead to deadlocks with MMU notifiers. GFP_NOIO is no
longer needed for that.
Regards,
Felix
if (!mqd_mem_obj)
return NULL;
retval = amdgpu_amdkfd_alloc_gtt_mem(kfd->kgd,
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Re: [PATCH 3/3] drm/amdkfd: Fix a bug when calculating save_area_used_size
On 2019-11-11 6:25 p.m., Yong Zhao wrote: workgroup context data writes from m->cp_hqd_cntl_stack_size, so we should deduct it when calculating the used size. Looks like something I missed in upstreaming. As far as I can tell this was originally part of a commit by Jay on amd-kfd-staging. Another part of his commit seems to be upstream. Not sure how this got lost. See one comment inline. Change-Id: I5252e25662c3b8221f451c39115bf084d1911eae Signed-off-by: Yong Zhao --- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c index d3380c5bdbde..3a2ee1f01aae 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c @@ -302,7 +302,8 @@ static int get_wave_state(struct mqd_manager *mm, void *mqd, *ctl_stack_used_size = m->cp_hqd_cntl_stack_size - m->cp_hqd_cntl_stack_offset; - *save_area_used_size = m->cp_hqd_wg_state_offset; + *save_area_used_size = m->cp_hqd_wg_state_offset - + m->cp_hqd_cntl_stack_size;; Please fix the double-semicolon. With that fixed this change is Reviewed-by: Felix Kuehling if (copy_to_user(ctl_stack, mqd_ctl_stack, m->cp_hqd_cntl_stack_size)) return -EFAULT; ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 2/2] drm/amdkfd: Stop using GFP_NOIO explicitly for GFX10
Hi Felix,
See one thing inline I am not too sure.
Yong
On 2019-11-12 4:30 p.m., Felix Kuehling wrote:
On 2019-11-12 4:26 p.m., Yong Zhao wrote:
Adapt the change from 1cd106ecfc1f04
The change is:
drm/amdkfd: Stop using GFP_NOIO explicitly
This is no longer needed with the memalloc_nofs_save/restore in
dqm_lock/unlock
Change-Id: I42450b2c149d2b1842be99a8f355c829a0079e7c
Signed-off-by: Yong Zhao
The series is
Reviewed-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c | 2 +-
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
index 46ddb33b624a..579c5ffcfa79 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
@@ -393,7 +393,7 @@ struct mqd_manager *mqd_manager_init_v10(enum
KFD_MQD_TYPE type,
if (WARN_ON(type >= KFD_MQD_TYPE_MAX))
return NULL;
- mqd = kzalloc(sizeof(*mqd), GFP_NOIO);
+ mqd = kzalloc(sizeof(*mqd), GFP_KERNEL);
if (!mqd)
return NULL;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
index be27ff01cdb8..22a819c888d8 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
@@ -92,7 +92,7 @@ static struct kfd_mem_obj *allocate_mqd(struct
kfd_dev *kfd,
* instead of sub-allocation function.
*/
if (kfd->cwsr_enabled && (q->type == KFD_QUEUE_TYPE_COMPUTE)) {
- mqd_mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_NOIO);
+ mqd_mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL);
[yz] This should be kept probably. With the latest code, allocate_mqd()
is called outside of the dqm. So now the situation is different from the
original one.
if (!mqd_mem_obj)
return NULL;
retval = amdgpu_amdkfd_alloc_gtt_mem(kfd->kgd,
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Re: [PATCH 2/2] drm/amdkfd: Stop using GFP_NOIO explicitly for GFX10
On 2019-11-12 4:26 p.m., Yong Zhao wrote:
Adapt the change from 1cd106ecfc1f04
The change is:
drm/amdkfd: Stop using GFP_NOIO explicitly
This is no longer needed with the memalloc_nofs_save/restore in
dqm_lock/unlock
Change-Id: I42450b2c149d2b1842be99a8f355c829a0079e7c
Signed-off-by: Yong Zhao
The series is
Reviewed-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c | 2 +-
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
index 46ddb33b624a..579c5ffcfa79 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
@@ -393,7 +393,7 @@ struct mqd_manager *mqd_manager_init_v10(enum KFD_MQD_TYPE
type,
if (WARN_ON(type >= KFD_MQD_TYPE_MAX))
return NULL;
- mqd = kzalloc(sizeof(*mqd), GFP_NOIO);
+ mqd = kzalloc(sizeof(*mqd), GFP_KERNEL);
if (!mqd)
return NULL;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
index be27ff01cdb8..22a819c888d8 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
@@ -92,7 +92,7 @@ static struct kfd_mem_obj *allocate_mqd(struct kfd_dev *kfd,
* instead of sub-allocation function.
*/
if (kfd->cwsr_enabled && (q->type == KFD_QUEUE_TYPE_COMPUTE)) {
- mqd_mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_NOIO);
+ mqd_mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL);
if (!mqd_mem_obj)
return NULL;
retval = amdgpu_amdkfd_alloc_gtt_mem(kfd->kgd,
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[PATCH 1/2] drm/amdkfd: Use QUEUE_IS_ACTIVE macro in mqd v10
This is done for other GFX in commit bb2d2128a54c4. Port it to GFX10. Change-Id: I9e04872be3af0e90f5f6930226896b1ea545f3d9 Signed-off-by: Yong Zhao --- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c | 11 ++- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c index 954dc8ac4ff1..46ddb33b624a 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c @@ -213,10 +213,7 @@ static void update_mqd(struct mqd_manager *mm, void *mqd, update_cu_mask(mm, mqd, q); set_priority(m, q); - q->is_active = (q->queue_size > 0 && - q->queue_address != 0 && - q->queue_percent > 0 && - !q->is_evicted); + q->is_active = QUEUE_IS_ACTIVE(*q); } static int destroy_mqd(struct mqd_manager *mm, void *mqd, @@ -348,11 +345,7 @@ static void update_mqd_sdma(struct mqd_manager *mm, void *mqd, m->sdma_queue_id = q->sdma_queue_id; m->sdmax_rlcx_dummy_reg = SDMA_RLC_DUMMY_DEFAULT; - - q->is_active = (q->queue_size > 0 && - q->queue_address != 0 && - q->queue_percent > 0 && - !q->is_evicted); + q->is_active = QUEUE_IS_ACTIVE(*q); } /* -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 2/2] drm/amdkfd: Stop using GFP_NOIO explicitly for GFX10
Adapt the change from 1cd106ecfc1f04
The change is:
drm/amdkfd: Stop using GFP_NOIO explicitly
This is no longer needed with the memalloc_nofs_save/restore in
dqm_lock/unlock
Change-Id: I42450b2c149d2b1842be99a8f355c829a0079e7c
Signed-off-by: Yong Zhao
---
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c | 2 +-
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
index 46ddb33b624a..579c5ffcfa79 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
@@ -393,7 +393,7 @@ struct mqd_manager *mqd_manager_init_v10(enum KFD_MQD_TYPE
type,
if (WARN_ON(type >= KFD_MQD_TYPE_MAX))
return NULL;
- mqd = kzalloc(sizeof(*mqd), GFP_NOIO);
+ mqd = kzalloc(sizeof(*mqd), GFP_KERNEL);
if (!mqd)
return NULL;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
index be27ff01cdb8..22a819c888d8 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
@@ -92,7 +92,7 @@ static struct kfd_mem_obj *allocate_mqd(struct kfd_dev *kfd,
* instead of sub-allocation function.
*/
if (kfd->cwsr_enabled && (q->type == KFD_QUEUE_TYPE_COMPUTE)) {
- mqd_mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_NOIO);
+ mqd_mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL);
if (!mqd_mem_obj)
return NULL;
retval = amdgpu_amdkfd_alloc_gtt_mem(kfd->kgd,
--
2.17.1
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Re: [PATCH 3/3] drm/amdkfd: Fix a bug when calculating save_area_used_size
+ Laurent From: Zhao, Yong Sent: Monday, November 11, 2019 6:25 PM To: amd-gfx@lists.freedesktop.org ; Cornwall, Jay Cc: Zhao, Yong Subject: [PATCH 3/3] drm/amdkfd: Fix a bug when calculating save_area_used_size workgroup context data writes from m->cp_hqd_cntl_stack_size, so we should deduct it when calculating the used size. Change-Id: I5252e25662c3b8221f451c39115bf084d1911eae Signed-off-by: Yong Zhao --- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c index d3380c5bdbde..3a2ee1f01aae 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c @@ -302,7 +302,8 @@ static int get_wave_state(struct mqd_manager *mm, void *mqd, *ctl_stack_used_size = m->cp_hqd_cntl_stack_size - m->cp_hqd_cntl_stack_offset; - *save_area_used_size = m->cp_hqd_wg_state_offset; + *save_area_used_size = m->cp_hqd_wg_state_offset - + m->cp_hqd_cntl_stack_size;; if (copy_to_user(ctl_stack, mqd_ctl_stack, m->cp_hqd_cntl_stack_size)) return -EFAULT; -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH v3 10/14] drm/amdgpu: Call find_vma under mmap_sem
From: Jason Gunthorpe
find_vma() must be called under the mmap_sem, reorganize this code to
do the vma check after entering the lock.
Further, fix the unlocked use of struct task_struct's mm, instead use
the mm from hmm_mirror which has an active mm_grab. Also the mm_grab
must be converted to a mm_get before acquiring mmap_sem or calling
find_vma().
Fixes: 66c45500bfdc ("drm/amdgpu: use new HMM APIs and helpers")
Fixes: 0919195f2b0d ("drm/amdgpu: Enable amdgpu_ttm_tt_get_user_pages in worker
threads")
Acked-by: Christian König
Reviewed-by: Felix Kuehling
Reviewed-by: Philip Yang
Tested-by: Philip Yang
Signed-off-by: Jason Gunthorpe
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 37 ++---
1 file changed, 21 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index dff41d0a85fe96..c0e41f1f0c2365 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -35,6 +35,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -788,7 +789,7 @@ int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo,
struct page **pages)
struct hmm_mirror *mirror = bo->mn ? >mn->mirror : NULL;
struct ttm_tt *ttm = bo->tbo.ttm;
struct amdgpu_ttm_tt *gtt = (void *)ttm;
- struct mm_struct *mm = gtt->usertask->mm;
+ struct mm_struct *mm;
unsigned long start = gtt->userptr;
struct vm_area_struct *vma;
struct hmm_range *range;
@@ -796,25 +797,14 @@ int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo,
struct page **pages)
uint64_t *pfns;
int r = 0;
- if (!mm) /* Happens during process shutdown */
- return -ESRCH;
-
if (unlikely(!mirror)) {
DRM_DEBUG_DRIVER("Failed to get hmm_mirror\n");
- r = -EFAULT;
- goto out;
+ return -EFAULT;
}
- vma = find_vma(mm, start);
- if (unlikely(!vma || start < vma->vm_start)) {
- r = -EFAULT;
- goto out;
- }
- if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&
- vma->vm_file)) {
- r = -EPERM;
- goto out;
- }
+ mm = mirror->hmm->mmu_notifier.mm;
+ if (!mmget_not_zero(mm)) /* Happens during process shutdown */
+ return -ESRCH;
range = kzalloc(sizeof(*range), GFP_KERNEL);
if (unlikely(!range)) {
@@ -847,6 +837,17 @@ int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo,
struct page **pages)
hmm_range_wait_until_valid(range, HMM_RANGE_DEFAULT_TIMEOUT);
down_read(>mmap_sem);
+ vma = find_vma(mm, start);
+ if (unlikely(!vma || start < vma->vm_start)) {
+ r = -EFAULT;
+ goto out_unlock;
+ }
+ if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&
+ vma->vm_file)) {
+ r = -EPERM;
+ goto out_unlock;
+ }
+
r = hmm_range_fault(range, 0);
up_read(>mmap_sem);
@@ -865,15 +866,19 @@ int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo,
struct page **pages)
}
gtt->range = range;
+ mmput(mm);
return 0;
+out_unlock:
+ up_read(>mmap_sem);
out_free_pfns:
hmm_range_unregister(range);
kvfree(pfns);
out_free_ranges:
kfree(range);
out:
+ mmput(mm);
return r;
}
--
2.24.0
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[PATCH v3 05/14] RDMA/odp: Use mmu_interval_notifier_insert()
From: Jason Gunthorpe
Replace the internal interval tree based mmu notifier with the new common
mmu_interval_notifier_insert() API. This removes a lot of code and fixes a
deadlock that can be triggered in ODP:
zap_page_range()
mmu_notifier_invalidate_range_start()
[..]
ib_umem_notifier_invalidate_range_start()
down_read(_mm->umem_rwsem)
unmap_single_vma()
[..]
__split_huge_page_pmd()
mmu_notifier_invalidate_range_start()
[..]
ib_umem_notifier_invalidate_range_start()
down_read(_mm->umem_rwsem) // DEADLOCK
mmu_notifier_invalidate_range_end()
up_read(_mm->umem_rwsem)
mmu_notifier_invalidate_range_end()
up_read(_mm->umem_rwsem)
The umem_rwsem is held across the range_start/end as the ODP algorithm for
invalidate_range_end cannot tolerate changes to the interval
tree. However, due to the nested invalidation regions the second
down_read() can deadlock if there are competing writers. The new core code
provides an alternative scheme to solve this problem.
Fixes: ca748c39ea3f ("RDMA/umem: Get rid of per_mm->notifier_count")
Tested-by: Artemy Kovalyov
Signed-off-by: Jason Gunthorpe
---
drivers/infiniband/core/device.c | 1 -
drivers/infiniband/core/umem_odp.c | 303 ---
drivers/infiniband/hw/mlx5/mlx5_ib.h | 7 +-
drivers/infiniband/hw/mlx5/mr.c | 3 +-
drivers/infiniband/hw/mlx5/odp.c | 50 ++---
include/rdma/ib_umem_odp.h | 68 ++
include/rdma/ib_verbs.h | 2 -
7 files changed, 82 insertions(+), 352 deletions(-)
diff --git a/drivers/infiniband/core/device.c b/drivers/infiniband/core/device.c
index 2dd2cfe9b56136..ac7924b3c73abe 100644
--- a/drivers/infiniband/core/device.c
+++ b/drivers/infiniband/core/device.c
@@ -2617,7 +2617,6 @@ void ib_set_device_ops(struct ib_device *dev, const
struct ib_device_ops *ops)
SET_DEVICE_OP(dev_ops, get_vf_config);
SET_DEVICE_OP(dev_ops, get_vf_stats);
SET_DEVICE_OP(dev_ops, init_port);
- SET_DEVICE_OP(dev_ops, invalidate_range);
SET_DEVICE_OP(dev_ops, iw_accept);
SET_DEVICE_OP(dev_ops, iw_add_ref);
SET_DEVICE_OP(dev_ops, iw_connect);
diff --git a/drivers/infiniband/core/umem_odp.c
b/drivers/infiniband/core/umem_odp.c
index d7d5fadf0899ad..e42d44e501fd54 100644
--- a/drivers/infiniband/core/umem_odp.c
+++ b/drivers/infiniband/core/umem_odp.c
@@ -48,197 +48,33 @@
#include "uverbs.h"
-static void ib_umem_notifier_start_account(struct ib_umem_odp *umem_odp)
+static inline int ib_init_umem_odp(struct ib_umem_odp *umem_odp,
+ const struct mmu_interval_notifier_ops *ops)
{
- mutex_lock(_odp->umem_mutex);
- if (umem_odp->notifiers_count++ == 0)
- /*
-* Initialize the completion object for waiting on
-* notifiers. Since notifier_count is zero, no one should be
-* waiting right now.
-*/
- reinit_completion(_odp->notifier_completion);
- mutex_unlock(_odp->umem_mutex);
-}
-
-static void ib_umem_notifier_end_account(struct ib_umem_odp *umem_odp)
-{
- mutex_lock(_odp->umem_mutex);
- /*
-* This sequence increase will notify the QP page fault that the page
-* that is going to be mapped in the spte could have been freed.
-*/
- ++umem_odp->notifiers_seq;
- if (--umem_odp->notifiers_count == 0)
- complete_all(_odp->notifier_completion);
- mutex_unlock(_odp->umem_mutex);
-}
-
-static void ib_umem_notifier_release(struct mmu_notifier *mn,
-struct mm_struct *mm)
-{
- struct ib_ucontext_per_mm *per_mm =
- container_of(mn, struct ib_ucontext_per_mm, mn);
- struct rb_node *node;
-
- down_read(_mm->umem_rwsem);
- if (!per_mm->mn.users)
- goto out;
-
- for (node = rb_first_cached(_mm->umem_tree); node;
-node = rb_next(node)) {
- struct ib_umem_odp *umem_odp =
- rb_entry(node, struct ib_umem_odp, interval_tree.rb);
-
- /*
-* Increase the number of notifiers running, to prevent any
-* further fault handling on this MR.
-*/
- ib_umem_notifier_start_account(umem_odp);
- complete_all(_odp->notifier_completion);
- umem_odp->umem.ibdev->ops.invalidate_range(
- umem_odp, ib_umem_start(umem_odp),
- ib_umem_end(umem_odp));
- }
-
-out:
- up_read(_mm->umem_rwsem);
-}
-
-static int invalidate_range_start_trampoline(struct ib_umem_odp *item,
-u64 start, u64 end, void *cookie)
-{
- ib_umem_notifier_start_account(item);
- item->umem.ibdev->ops.invalidate_range(item, start, end);
- return 0;
-}
-
-static int
[PATCH v3 04/14] mm/hmm: define the pre-processor related parts of hmm.h even if disabled
From: Jason Gunthorpe
Only the function calls are stubbed out with static inlines that always
fail. This is the standard way to write a header for an optional component
and makes it easier for drivers that only optionally need HMM_MIRROR.
Reviewed-by: Jérôme Glisse
Tested-by: Ralph Campbell
Signed-off-by: Jason Gunthorpe
---
include/linux/hmm.h | 59 -
kernel/fork.c | 1 -
2 files changed, 47 insertions(+), 13 deletions(-)
diff --git a/include/linux/hmm.h b/include/linux/hmm.h
index fbb35c78637e57..cb69bf10dc788c 100644
--- a/include/linux/hmm.h
+++ b/include/linux/hmm.h
@@ -62,8 +62,6 @@
#include
#include
-#ifdef CONFIG_HMM_MIRROR
-
#include
#include
#include
@@ -374,6 +372,15 @@ struct hmm_mirror {
struct list_headlist;
};
+/*
+ * Retry fault if non-blocking, drop mmap_sem and return -EAGAIN in that case.
+ */
+#define HMM_FAULT_ALLOW_RETRY (1 << 0)
+
+/* Don't fault in missing PTEs, just snapshot the current state. */
+#define HMM_FAULT_SNAPSHOT (1 << 1)
+
+#ifdef CONFIG_HMM_MIRROR
int hmm_mirror_register(struct hmm_mirror *mirror, struct mm_struct *mm);
void hmm_mirror_unregister(struct hmm_mirror *mirror);
@@ -383,14 +390,6 @@ void hmm_mirror_unregister(struct hmm_mirror *mirror);
int hmm_range_register(struct hmm_range *range, struct hmm_mirror *mirror);
void hmm_range_unregister(struct hmm_range *range);
-/*
- * Retry fault if non-blocking, drop mmap_sem and return -EAGAIN in that case.
- */
-#define HMM_FAULT_ALLOW_RETRY (1 << 0)
-
-/* Don't fault in missing PTEs, just snapshot the current state. */
-#define HMM_FAULT_SNAPSHOT (1 << 1)
-
long hmm_range_fault(struct hmm_range *range, unsigned int flags);
long hmm_range_dma_map(struct hmm_range *range,
@@ -401,6 +400,44 @@ long hmm_range_dma_unmap(struct hmm_range *range,
struct device *device,
dma_addr_t *daddrs,
bool dirty);
+#else
+int hmm_mirror_register(struct hmm_mirror *mirror, struct mm_struct *mm)
+{
+ return -EOPNOTSUPP;
+}
+
+void hmm_mirror_unregister(struct hmm_mirror *mirror)
+{
+}
+
+int hmm_range_register(struct hmm_range *range, struct hmm_mirror *mirror)
+{
+ return -EOPNOTSUPP;
+}
+
+void hmm_range_unregister(struct hmm_range *range)
+{
+}
+
+static inline long hmm_range_fault(struct hmm_range *range, unsigned int flags)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline long hmm_range_dma_map(struct hmm_range *range,
+struct device *device, dma_addr_t *daddrs,
+unsigned int flags)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline long hmm_range_dma_unmap(struct hmm_range *range,
+ struct device *device,
+ dma_addr_t *daddrs, bool dirty)
+{
+ return -EOPNOTSUPP;
+}
+#endif
/*
* HMM_RANGE_DEFAULT_TIMEOUT - default timeout (ms) when waiting for a range
@@ -411,6 +448,4 @@ long hmm_range_dma_unmap(struct hmm_range *range,
*/
#define HMM_RANGE_DEFAULT_TIMEOUT 1000
-#endif /* IS_ENABLED(CONFIG_HMM_MIRROR) */
-
#endif /* LINUX_HMM_H */
diff --git a/kernel/fork.c b/kernel/fork.c
index bcdf5312521036..ca39cfc404e3db 100644
--- a/kernel/fork.c
+++ b/kernel/fork.c
@@ -40,7 +40,6 @@
#include
#include
#include
-#include
#include
#include
#include
--
2.24.0
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[PATCH v3 12/14] drm/amdgpu: Use mmu_interval_notifier instead of hmm_mirror
From: Jason Gunthorpe
Convert the collision-retry lock around hmm_range_fault to use the one now
provided by the mmu_interval notifier.
Although this driver does not seem to use the collision retry lock that
hmm provides correctly, it can still be converted over to use the
mmu_interval_notifier api instead of hmm_mirror without too much trouble.
This also deletes another place where a driver is associating additional
data (struct amdgpu_mn) with a mmu_struct.
Signed-off-by: Philip Yang
Reviewed-by: Philip Yang
Tested-by: Philip Yang
Signed-off-by: Jason Gunthorpe
---
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 4 +
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c| 14 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c| 148 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h| 49 --
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 116 --
5 files changed, 94 insertions(+), 237 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index 47700302a08b7f..1bcedb9b477dce 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -1738,6 +1738,10 @@ static int update_invalid_user_pages(struct
amdkfd_process_info *process_info,
return ret;
}
+ /*
+* FIXME: Cannot ignore the return code, must hold
+* notifier_lock
+*/
amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm);
/* Mark the BO as valid unless it was invalidated
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 82823d9a8ba887..22c989bca7514c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -603,8 +603,6 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
e->tv.num_shared = 2;
amdgpu_bo_list_get_list(p->bo_list, >validated);
- if (p->bo_list->first_userptr != p->bo_list->num_entries)
- p->mn = amdgpu_mn_get(p->adev, AMDGPU_MN_TYPE_GFX);
INIT_LIST_HEAD();
amdgpu_vm_get_pd_bo(>vm, >validated, >vm_pd);
@@ -1287,11 +1285,11 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
if (r)
goto error_unlock;
- /* No memory allocation is allowed while holding the mn lock.
-* p->mn is hold until amdgpu_cs_submit is finished and fence is added
-* to BOs.
+ /* No memory allocation is allowed while holding the notifier lock.
+* The lock is held until amdgpu_cs_submit is finished and fence is
+* added to BOs.
*/
- amdgpu_mn_lock(p->mn);
+ mutex_lock(>adev->notifier_lock);
/* If userptr are invalidated after amdgpu_cs_parser_bos(), return
* -EAGAIN, drmIoctl in libdrm will restart the amdgpu_cs_ioctl.
@@ -1334,13 +1332,13 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
amdgpu_vm_move_to_lru_tail(p->adev, >vm);
ttm_eu_fence_buffer_objects(>ticket, >validated, p->fence);
- amdgpu_mn_unlock(p->mn);
+ mutex_unlock(>adev->notifier_lock);
return 0;
error_abort:
drm_sched_job_cleanup(>base);
- amdgpu_mn_unlock(p->mn);
+ mutex_unlock(>adev->notifier_lock);
error_unlock:
amdgpu_job_free(job);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
index 9fe1c31ce17a30..828b5167ff128f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
@@ -50,28 +50,6 @@
#include "amdgpu.h"
#include "amdgpu_amdkfd.h"
-/**
- * amdgpu_mn_lock - take the write side lock for this notifier
- *
- * @mn: our notifier
- */
-void amdgpu_mn_lock(struct amdgpu_mn *mn)
-{
- if (mn)
- down_write(>lock);
-}
-
-/**
- * amdgpu_mn_unlock - drop the write side lock for this notifier
- *
- * @mn: our notifier
- */
-void amdgpu_mn_unlock(struct amdgpu_mn *mn)
-{
- if (mn)
- up_write(>lock);
-}
-
/**
* amdgpu_mn_invalidate_gfx - callback to notify about mm change
*
@@ -94,6 +72,9 @@ static bool amdgpu_mn_invalidate_gfx(struct
mmu_interval_notifier *mni,
return false;
mutex_lock(>notifier_lock);
+
+ mmu_interval_set_seq(mni, cur_seq);
+
r = dma_resv_wait_timeout_rcu(bo->tbo.base.resv, true, false,
MAX_SCHEDULE_TIMEOUT);
mutex_unlock(>notifier_lock);
@@ -127,6 +108,9 @@ static bool amdgpu_mn_invalidate_hsa(struct
mmu_interval_notifier *mni,
return false;
mutex_lock(>notifier_lock);
+
+ mmu_interval_set_seq(mni, cur_seq);
+
amdgpu_amdkfd_evict_userptr(bo->kfd_bo, bo->notifier.mm);
mutex_unlock(>notifier_lock);
@@ -137,92 +121,6 @@ static const struct mmu_interval_notifier_ops
[PATCH v3 14/14] xen/gntdev: use mmu_interval_notifier_insert
From: Jason Gunthorpe
gntdev simply wants to monitor a specific VMA for any notifier events,
this can be done straightforwardly using mmu_interval_notifier_insert()
over the VMA's VA range.
The notifier should be attached until the original VMA is destroyed.
It is unclear if any of this is even sane, but at least a lot of duplicate
code is removed.
Reviewed-by: Boris Ostrovsky
Signed-off-by: Jason Gunthorpe
---
drivers/xen/gntdev-common.h | 8 +-
drivers/xen/gntdev.c| 179 ++--
2 files changed, 49 insertions(+), 138 deletions(-)
diff --git a/drivers/xen/gntdev-common.h b/drivers/xen/gntdev-common.h
index 2f8b949c3eeb14..91e44c04f7876c 100644
--- a/drivers/xen/gntdev-common.h
+++ b/drivers/xen/gntdev-common.h
@@ -21,15 +21,8 @@ struct gntdev_dmabuf_priv;
struct gntdev_priv {
/* Maps with visible offsets in the file descriptor. */
struct list_head maps;
- /*
-* Maps that are not visible; will be freed on munmap.
-* Only populated if populate_freeable_maps == 1
-*/
- struct list_head freeable_maps;
/* lock protects maps and freeable_maps. */
struct mutex lock;
- struct mm_struct *mm;
- struct mmu_notifier mn;
#ifdef CONFIG_XEN_GRANT_DMA_ALLOC
/* Device for which DMA memory is allocated. */
@@ -49,6 +42,7 @@ struct gntdev_unmap_notify {
};
struct gntdev_grant_map {
+ struct mmu_interval_notifier notifier;
struct list_head next;
struct vm_area_struct *vma;
int index;
diff --git a/drivers/xen/gntdev.c b/drivers/xen/gntdev.c
index 81401f386c9ce0..a04ddf2a68afa5 100644
--- a/drivers/xen/gntdev.c
+++ b/drivers/xen/gntdev.c
@@ -63,7 +63,6 @@ MODULE_PARM_DESC(limit, "Maximum number of grants that may be
mapped by "
static atomic_t pages_mapped = ATOMIC_INIT(0);
static int use_ptemod;
-#define populate_freeable_maps use_ptemod
static int unmap_grant_pages(struct gntdev_grant_map *map,
int offset, int pages);
@@ -249,12 +248,6 @@ void gntdev_put_map(struct gntdev_priv *priv, struct
gntdev_grant_map *map)
evtchn_put(map->notify.event);
}
- if (populate_freeable_maps && priv) {
- mutex_lock(>lock);
- list_del(>next);
- mutex_unlock(>lock);
- }
-
if (map->pages && !use_ptemod)
unmap_grant_pages(map, 0, map->count);
gntdev_free_map(map);
@@ -444,16 +437,9 @@ static void gntdev_vma_close(struct vm_area_struct *vma)
pr_debug("gntdev_vma_close %p\n", vma);
if (use_ptemod) {
- /* It is possible that an mmu notifier could be running
-* concurrently, so take priv->lock to ensure that the vma won't
-* vanishing during the unmap_grant_pages call, since we will
-* spin here until that completes. Such a concurrent call will
-* not do any unmapping, since that has been done prior to
-* closing the vma, but it may still iterate the unmap_ops list.
-*/
- mutex_lock(>lock);
+ WARN_ON(map->vma != vma);
+ mmu_interval_notifier_remove(>notifier);
map->vma = NULL;
- mutex_unlock(>lock);
}
vma->vm_private_data = NULL;
gntdev_put_map(priv, map);
@@ -475,109 +461,44 @@ static const struct vm_operations_struct gntdev_vmops = {
/* -- */
-static bool in_range(struct gntdev_grant_map *map,
- unsigned long start, unsigned long end)
-{
- if (!map->vma)
- return false;
- if (map->vma->vm_start >= end)
- return false;
- if (map->vma->vm_end <= start)
- return false;
-
- return true;
-}
-
-static int unmap_if_in_range(struct gntdev_grant_map *map,
- unsigned long start, unsigned long end,
- bool blockable)
+static bool gntdev_invalidate(struct mmu_interval_notifier *mn,
+ const struct mmu_notifier_range *range,
+ unsigned long cur_seq)
{
+ struct gntdev_grant_map *map =
+ container_of(mn, struct gntdev_grant_map, notifier);
unsigned long mstart, mend;
int err;
- if (!in_range(map, start, end))
- return 0;
+ if (!mmu_notifier_range_blockable(range))
+ return false;
- if (!blockable)
- return -EAGAIN;
+ /*
+* If the VMA is split or otherwise changed the notifier is not
+* updated, but we don't want to process VA's outside the modified
+* VMA. FIXME: It would be much more understandable to just prevent
+* modifying the VMA in the first place.
+*/
+ if (map->vma->vm_start >= range->end ||
+
[PATCH v3 07/14] drm/radeon: use mmu_interval_notifier_insert
From: Jason Gunthorpe
The new API is an exact match for the needs of radeon.
For some reason radeon tries to remove overlapping ranges from the
interval tree, but interval trees (and mmu_interval_notifier_insert())
support overlapping ranges directly. Simply delete all this code.
Since this driver is missing a invalidate_range_end callback, but
still calls get_user_pages(), it cannot be correct against all races.
Reviewed-by: Christian König
Signed-off-by: Jason Gunthorpe
---
drivers/gpu/drm/radeon/radeon.h| 9 +-
drivers/gpu/drm/radeon/radeon_mn.c | 218 ++---
2 files changed, 51 insertions(+), 176 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index d59b004f669583..30e32adc1fc666 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -68,6 +68,10 @@
#include
#include
+#ifdef CONFIG_MMU_NOTIFIER
+#include
+#endif
+
#include
#include
#include
@@ -509,8 +513,9 @@ struct radeon_bo {
struct ttm_bo_kmap_obj dma_buf_vmap;
pid_t pid;
- struct radeon_mn*mn;
- struct list_headmn_list;
+#ifdef CONFIG_MMU_NOTIFIER
+ struct mmu_interval_notifiernotifier;
+#endif
};
#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, tbo.base)
diff --git a/drivers/gpu/drm/radeon/radeon_mn.c
b/drivers/gpu/drm/radeon/radeon_mn.c
index dbab9a3a969b9e..f93829f08a4dc1 100644
--- a/drivers/gpu/drm/radeon/radeon_mn.c
+++ b/drivers/gpu/drm/radeon/radeon_mn.c
@@ -36,131 +36,51 @@
#include "radeon.h"
-struct radeon_mn {
- struct mmu_notifier mn;
-
- /* objects protected by lock */
- struct mutexlock;
- struct rb_root_cached objects;
-};
-
-struct radeon_mn_node {
- struct interval_tree_node it;
- struct list_headbos;
-};
-
/**
- * radeon_mn_invalidate_range_start - callback to notify about mm change
+ * radeon_mn_invalidate - callback to notify about mm change
*
* @mn: our notifier
- * @mn: the mm this callback is about
- * @start: start of updated range
- * @end: end of updated range
+ * @range: the VMA under invalidation
*
* We block for all BOs between start and end to be idle and
* unmap them by move them into system domain again.
*/
-static int radeon_mn_invalidate_range_start(struct mmu_notifier *mn,
- const struct mmu_notifier_range *range)
+static bool radeon_mn_invalidate(struct mmu_interval_notifier *mn,
+const struct mmu_notifier_range *range,
+unsigned long cur_seq)
{
- struct radeon_mn *rmn = container_of(mn, struct radeon_mn, mn);
+ struct radeon_bo *bo = container_of(mn, struct radeon_bo, notifier);
struct ttm_operation_ctx ctx = { false, false };
- struct interval_tree_node *it;
- unsigned long end;
- int ret = 0;
-
- /* notification is exclusive, but interval is inclusive */
- end = range->end - 1;
-
- /* TODO we should be able to split locking for interval tree and
-* the tear down.
-*/
- if (mmu_notifier_range_blockable(range))
- mutex_lock(>lock);
- else if (!mutex_trylock(>lock))
- return -EAGAIN;
-
- it = interval_tree_iter_first(>objects, range->start, end);
- while (it) {
- struct radeon_mn_node *node;
- struct radeon_bo *bo;
- long r;
-
- if (!mmu_notifier_range_blockable(range)) {
- ret = -EAGAIN;
- goto out_unlock;
- }
-
- node = container_of(it, struct radeon_mn_node, it);
- it = interval_tree_iter_next(it, range->start, end);
+ long r;
- list_for_each_entry(bo, >bos, mn_list) {
+ if (!bo->tbo.ttm || bo->tbo.ttm->state != tt_bound)
+ return true;
- if (!bo->tbo.ttm || bo->tbo.ttm->state != tt_bound)
- continue;
+ if (!mmu_notifier_range_blockable(range))
+ return false;
- r = radeon_bo_reserve(bo, true);
- if (r) {
- DRM_ERROR("(%ld) failed to reserve user bo\n",
r);
- continue;
- }
-
- r = dma_resv_wait_timeout_rcu(bo->tbo.base.resv,
- true, false, MAX_SCHEDULE_TIMEOUT);
- if (r <= 0)
- DRM_ERROR("(%ld) failed to wait for user bo\n",
r);
-
- radeon_ttm_placement_from_domain(bo,
RADEON_GEM_DOMAIN_CPU);
- r = ttm_bo_validate(>tbo, >placement, );
- if (r)
- DRM_ERROR("(%ld) failed
[PATCH v3 03/14] mm/hmm: allow hmm_range to be used with a mmu_interval_notifier or hmm_mirror
From: Jason Gunthorpe
hmm_mirror's handling of ranges does not use a sequence count which
results in this bug:
CPU0 CPU1
hmm_range_wait_until_valid(range)
valid == true
hmm_range_fault(range)
hmm_invalidate_range_start()
range->valid = false
hmm_invalidate_range_end()
range->valid = true
hmm_range_valid(range)
valid == true
Where the hmm_range_valid() should not have succeeded.
Adding the required sequence count would make it nearly identical to the
new mmu_interval_notifier. Instead replace the hmm_mirror stuff with
mmu_interval_notifier.
Co-existence of the two APIs is the first step.
Reviewed-by: Jérôme Glisse
Tested-by: Philip Yang
Tested-by: Ralph Campbell
Signed-off-by: Jason Gunthorpe
---
include/linux/hmm.h | 5 +
mm/hmm.c| 25 +++--
2 files changed, 24 insertions(+), 6 deletions(-)
diff --git a/include/linux/hmm.h b/include/linux/hmm.h
index 3fec513b9c00f1..fbb35c78637e57 100644
--- a/include/linux/hmm.h
+++ b/include/linux/hmm.h
@@ -145,6 +145,9 @@ enum hmm_pfn_value_e {
/*
* struct hmm_range - track invalidation lock on virtual address range
*
+ * @notifier: an optional mmu_interval_notifier
+ * @notifier_seq: when notifier is used this is the result of
+ *mmu_interval_read_begin()
* @hmm: the core HMM structure this range is active against
* @vma: the vm area struct for the range
* @list: all range lock are on a list
@@ -159,6 +162,8 @@ enum hmm_pfn_value_e {
* @valid: pfns array did not change since it has been fill by an HMM function
*/
struct hmm_range {
+ struct mmu_interval_notifier *notifier;
+ unsigned long notifier_seq;
struct hmm *hmm;
struct list_headlist;
unsigned long start;
diff --git a/mm/hmm.c b/mm/hmm.c
index 6b0136665407a3..8d060c5dabe37b 100644
--- a/mm/hmm.c
+++ b/mm/hmm.c
@@ -858,6 +858,14 @@ void hmm_range_unregister(struct hmm_range *range)
}
EXPORT_SYMBOL(hmm_range_unregister);
+static bool needs_retry(struct hmm_range *range)
+{
+ if (range->notifier)
+ return mmu_interval_check_retry(range->notifier,
+ range->notifier_seq);
+ return !range->valid;
+}
+
static const struct mm_walk_ops hmm_walk_ops = {
.pud_entry = hmm_vma_walk_pud,
.pmd_entry = hmm_vma_walk_pmd,
@@ -898,18 +906,23 @@ long hmm_range_fault(struct hmm_range *range, unsigned
int flags)
const unsigned long device_vma = VM_IO | VM_PFNMAP | VM_MIXEDMAP;
unsigned long start = range->start, end;
struct hmm_vma_walk hmm_vma_walk;
- struct hmm *hmm = range->hmm;
+ struct mm_struct *mm;
struct vm_area_struct *vma;
int ret;
- lockdep_assert_held(>mmu_notifier.mm->mmap_sem);
+ if (range->notifier)
+ mm = range->notifier->mm;
+ else
+ mm = range->hmm->mmu_notifier.mm;
+
+ lockdep_assert_held(>mmap_sem);
do {
/* If range is no longer valid force retry. */
- if (!range->valid)
+ if (needs_retry(range))
return -EBUSY;
- vma = find_vma(hmm->mmu_notifier.mm, start);
+ vma = find_vma(mm, start);
if (vma == NULL || (vma->vm_flags & device_vma))
return -EFAULT;
@@ -939,7 +952,7 @@ long hmm_range_fault(struct hmm_range *range, unsigned int
flags)
start = hmm_vma_walk.last;
/* Keep trying while the range is valid. */
- } while (ret == -EBUSY && range->valid);
+ } while (ret == -EBUSY && !needs_retry(range));
if (ret) {
unsigned long i;
@@ -997,7 +1010,7 @@ long hmm_range_dma_map(struct hmm_range *range, struct
device *device,
continue;
/* Check if range is being invalidated */
- if (!range->valid) {
+ if (needs_retry(range)) {
ret = -EBUSY;
goto unmap;
}
--
2.24.0
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[PATCH v3 01/14] mm/mmu_notifier: define the header pre-processor parts even if disabled
From: Jason Gunthorpe
Now that we have KERNEL_HEADER_TEST all headers are generally compile
tested, so relying on makefile tricks to avoid compiling code that depends
on CONFIG_MMU_NOTIFIER is more annoying.
Instead follow the usual pattern and provide most of the header with only
the functions stubbed out when CONFIG_MMU_NOTIFIER is disabled. This
ensures code compiles no matter what the config setting is.
While here, struct mmu_notifier_mm is private to mmu_notifier.c, move it.
Reviewed-by: Jérôme Glisse
Tested-by: Ralph Campbell
Reviewed-by: John Hubbard
Signed-off-by: Jason Gunthorpe
---
include/linux/mmu_notifier.h | 46 +---
mm/mmu_notifier.c| 13 ++
2 files changed, 30 insertions(+), 29 deletions(-)
diff --git a/include/linux/mmu_notifier.h b/include/linux/mmu_notifier.h
index 1bd8e6a09a3c27..12bd603d318ce7 100644
--- a/include/linux/mmu_notifier.h
+++ b/include/linux/mmu_notifier.h
@@ -7,8 +7,9 @@
#include
#include
+struct mmu_notifier_mm;
struct mmu_notifier;
-struct mmu_notifier_ops;
+struct mmu_notifier_range;
/**
* enum mmu_notifier_event - reason for the mmu notifier callback
@@ -40,36 +41,8 @@ enum mmu_notifier_event {
MMU_NOTIFY_SOFT_DIRTY,
};
-#ifdef CONFIG_MMU_NOTIFIER
-
-#ifdef CONFIG_LOCKDEP
-extern struct lockdep_map __mmu_notifier_invalidate_range_start_map;
-#endif
-
-/*
- * The mmu notifier_mm structure is allocated and installed in
- * mm->mmu_notifier_mm inside the mm_take_all_locks() protected
- * critical section and it's released only when mm_count reaches zero
- * in mmdrop().
- */
-struct mmu_notifier_mm {
- /* all mmu notifiers registerd in this mm are queued in this list */
- struct hlist_head list;
- /* to serialize the list modifications and hlist_unhashed */
- spinlock_t lock;
-};
-
#define MMU_NOTIFIER_RANGE_BLOCKABLE (1 << 0)
-struct mmu_notifier_range {
- struct vm_area_struct *vma;
- struct mm_struct *mm;
- unsigned long start;
- unsigned long end;
- unsigned flags;
- enum mmu_notifier_event event;
-};
-
struct mmu_notifier_ops {
/*
* Called either by mmu_notifier_unregister or when the mm is
@@ -249,6 +222,21 @@ struct mmu_notifier {
unsigned int users;
};
+#ifdef CONFIG_MMU_NOTIFIER
+
+#ifdef CONFIG_LOCKDEP
+extern struct lockdep_map __mmu_notifier_invalidate_range_start_map;
+#endif
+
+struct mmu_notifier_range {
+ struct vm_area_struct *vma;
+ struct mm_struct *mm;
+ unsigned long start;
+ unsigned long end;
+ unsigned flags;
+ enum mmu_notifier_event event;
+};
+
static inline int mm_has_notifiers(struct mm_struct *mm)
{
return unlikely(mm->mmu_notifier_mm);
diff --git a/mm/mmu_notifier.c b/mm/mmu_notifier.c
index 7fde88695f35d6..367670cfd02b7b 100644
--- a/mm/mmu_notifier.c
+++ b/mm/mmu_notifier.c
@@ -27,6 +27,19 @@ struct lockdep_map __mmu_notifier_invalidate_range_start_map
= {
};
#endif
+/*
+ * The mmu notifier_mm structure is allocated and installed in
+ * mm->mmu_notifier_mm inside the mm_take_all_locks() protected
+ * critical section and it's released only when mm_count reaches zero
+ * in mmdrop().
+ */
+struct mmu_notifier_mm {
+ /* all mmu notifiers registered in this mm are queued in this list */
+ struct hlist_head list;
+ /* to serialize the list modifications and hlist_unhashed */
+ spinlock_t lock;
+};
+
/*
* This function can't run concurrently against mmu_notifier_register
* because mm->mm_users > 0 during mmu_notifier_register and exit_mmap
--
2.24.0
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[PATCH v3 06/14] RDMA/hfi1: Use mmu_interval_notifier_insert for user_exp_rcv
From: Jason Gunthorpe
This converts one of the two users of mmu_notifiers to use the new API.
The conversion is fairly straightforward, however the existing use of
notifiers here seems to be racey.
Tested-by: Dennis Dalessandro
Signed-off-by: Jason Gunthorpe
---
drivers/infiniband/hw/hfi1/file_ops.c | 2 +-
drivers/infiniband/hw/hfi1/hfi.h | 2 +-
drivers/infiniband/hw/hfi1/user_exp_rcv.c | 146 +-
drivers/infiniband/hw/hfi1/user_exp_rcv.h | 3 +-
4 files changed, 60 insertions(+), 93 deletions(-)
diff --git a/drivers/infiniband/hw/hfi1/file_ops.c
b/drivers/infiniband/hw/hfi1/file_ops.c
index f9a7e9d29c8ba2..7c5e3fb224139a 100644
--- a/drivers/infiniband/hw/hfi1/file_ops.c
+++ b/drivers/infiniband/hw/hfi1/file_ops.c
@@ -1138,7 +1138,7 @@ static int get_ctxt_info(struct hfi1_filedata *fd,
unsigned long arg, u32 len)
HFI1_CAP_UGET_MASK(uctxt->flags, MASK) |
HFI1_CAP_KGET_MASK(uctxt->flags, K2U);
/* adjust flag if this fd is not able to cache */
- if (!fd->handler)
+ if (!fd->use_mn)
cinfo.runtime_flags |= HFI1_CAP_TID_UNMAP; /* no caching */
cinfo.num_active = hfi1_count_active_units();
diff --git a/drivers/infiniband/hw/hfi1/hfi.h b/drivers/infiniband/hw/hfi1/hfi.h
index fa45350a9a1d32..fc10d65fc3e13c 100644
--- a/drivers/infiniband/hw/hfi1/hfi.h
+++ b/drivers/infiniband/hw/hfi1/hfi.h
@@ -1444,7 +1444,7 @@ struct hfi1_filedata {
/* for cpu affinity; -1 if none */
int rec_cpu_num;
u32 tid_n_pinned;
- struct mmu_rb_handler *handler;
+ bool use_mn;
struct tid_rb_node **entry_to_rb;
spinlock_t tid_lock; /* protect tid_[limit,used] counters */
u32 tid_limit;
diff --git a/drivers/infiniband/hw/hfi1/user_exp_rcv.c
b/drivers/infiniband/hw/hfi1/user_exp_rcv.c
index 3592a9ec155e85..75a378162162d3 100644
--- a/drivers/infiniband/hw/hfi1/user_exp_rcv.c
+++ b/drivers/infiniband/hw/hfi1/user_exp_rcv.c
@@ -59,11 +59,11 @@ static int set_rcvarray_entry(struct hfi1_filedata *fd,
struct tid_user_buf *tbuf,
u32 rcventry, struct tid_group *grp,
u16 pageidx, unsigned int npages);
-static int tid_rb_insert(void *arg, struct mmu_rb_node *node);
static void cacheless_tid_rb_remove(struct hfi1_filedata *fdata,
struct tid_rb_node *tnode);
-static void tid_rb_remove(void *arg, struct mmu_rb_node *node);
-static int tid_rb_invalidate(void *arg, struct mmu_rb_node *mnode);
+static bool tid_rb_invalidate(struct mmu_interval_notifier *mni,
+ const struct mmu_notifier_range *range,
+ unsigned long cur_seq);
static int program_rcvarray(struct hfi1_filedata *fd, struct tid_user_buf *,
struct tid_group *grp,
unsigned int start, u16 count,
@@ -73,10 +73,8 @@ static int unprogram_rcvarray(struct hfi1_filedata *fd, u32
tidinfo,
struct tid_group **grp);
static void clear_tid_node(struct hfi1_filedata *fd, struct tid_rb_node *node);
-static struct mmu_rb_ops tid_rb_ops = {
- .insert = tid_rb_insert,
- .remove = tid_rb_remove,
- .invalidate = tid_rb_invalidate
+static const struct mmu_interval_notifier_ops tid_mn_ops = {
+ .invalidate = tid_rb_invalidate,
};
/*
@@ -87,7 +85,6 @@ static struct mmu_rb_ops tid_rb_ops = {
int hfi1_user_exp_rcv_init(struct hfi1_filedata *fd,
struct hfi1_ctxtdata *uctxt)
{
- struct hfi1_devdata *dd = uctxt->dd;
int ret = 0;
spin_lock_init(>tid_lock);
@@ -109,20 +106,7 @@ int hfi1_user_exp_rcv_init(struct hfi1_filedata *fd,
fd->entry_to_rb = NULL;
return -ENOMEM;
}
-
- /*
-* Register MMU notifier callbacks. If the registration
-* fails, continue without TID caching for this context.
-*/
- ret = hfi1_mmu_rb_register(fd, fd->mm, _rb_ops,
- dd->pport->hfi1_wq,
- >handler);
- if (ret) {
- dd_dev_info(dd,
- "Failed MMU notifier registration %d\n",
- ret);
- ret = 0;
- }
+ fd->use_mn = true;
}
/*
@@ -139,7 +123,7 @@ int hfi1_user_exp_rcv_init(struct hfi1_filedata *fd,
* init.
*/
spin_lock(>tid_lock);
- if (uctxt->subctxt_cnt && fd->handler) {
+ if (uctxt->subctxt_cnt && fd->use_mn) {
u16 remainder;
fd->tid_limit = uctxt->expected_count / uctxt->subctxt_cnt;
@@ -158,18 +142,10 @@ void hfi1_user_exp_rcv_free(struct
[PATCH v3 13/14] mm/hmm: remove hmm_mirror and related
From: Jason Gunthorpe
The only two users of this are now converted to use mmu_interval_notifier,
delete all the code and update hmm.rst.
Reviewed-by: Jérôme Glisse
Tested-by: Ralph Campbell
Signed-off-by: Jason Gunthorpe
---
Documentation/vm/hmm.rst | 105 ---
include/linux/hmm.h | 183 +
mm/Kconfig | 1 -
mm/hmm.c | 285 ++-
4 files changed, 34 insertions(+), 540 deletions(-)
diff --git a/Documentation/vm/hmm.rst b/Documentation/vm/hmm.rst
index 0a5960beccf76d..893a8ba0e9fefb 100644
--- a/Documentation/vm/hmm.rst
+++ b/Documentation/vm/hmm.rst
@@ -147,49 +147,16 @@ Address space mirroring implementation and API
Address space mirroring's main objective is to allow duplication of a range of
CPU page table into a device page table; HMM helps keep both synchronized. A
device driver that wants to mirror a process address space must start with the
-registration of an hmm_mirror struct::
-
- int hmm_mirror_register(struct hmm_mirror *mirror,
- struct mm_struct *mm);
-
-The mirror struct has a set of callbacks that are used
-to propagate CPU page tables::
-
- struct hmm_mirror_ops {
- /* release() - release hmm_mirror
- *
- * @mirror: pointer to struct hmm_mirror
- *
- * This is called when the mm_struct is being released. The callback
- * must ensure that all access to any pages obtained from this mirror
- * is halted before the callback returns. All future access should
- * fault.
- */
- void (*release)(struct hmm_mirror *mirror);
-
- /* sync_cpu_device_pagetables() - synchronize page tables
- *
- * @mirror: pointer to struct hmm_mirror
- * @update: update information (see struct mmu_notifier_range)
- * Return: -EAGAIN if update.blockable false and callback need to
- * block, 0 otherwise.
- *
- * This callback ultimately originates from mmu_notifiers when the CPU
- * page table is updated. The device driver must update its page table
- * in response to this callback. The update argument tells what action
- * to perform.
- *
- * The device driver must not return from this callback until the device
- * page tables are completely updated (TLBs flushed, etc); this is a
- * synchronous call.
- */
- int (*sync_cpu_device_pagetables)(struct hmm_mirror *mirror,
- const struct hmm_update *update);
- };
-
-The device driver must perform the update action to the range (mark range
-read only, or fully unmap, etc.). The device must complete the update before
-the driver callback returns.
+registration of a mmu_interval_notifier::
+
+ mni->ops = _ops;
+ int mmu_interval_notifier_insert(struct mmu_interval_notifier *mni,
+ unsigned long start, unsigned long length,
+ struct mm_struct *mm);
+
+During the driver_ops->invalidate() callback the device driver must perform
+the update action to the range (mark range read only, or fully unmap,
+etc.). The device must complete the update before the driver callback returns.
When the device driver wants to populate a range of virtual addresses, it can
use::
@@ -216,70 +183,46 @@ The usage pattern is::
struct hmm_range range;
...
+ range.notifier =
range.start = ...;
range.end = ...;
range.pfns = ...;
range.flags = ...;
range.values = ...;
range.pfn_shift = ...;
- hmm_range_register(, mirror);
- /*
- * Just wait for range to be valid, safe to ignore return value as we
- * will use the return value of hmm_range_fault() below under the
- * mmap_sem to ascertain the validity of the range.
- */
- hmm_range_wait_until_valid(, TIMEOUT_IN_MSEC);
+ if (!mmget_not_zero(mni->notifier.mm))
+ return -EFAULT;
again:
+ range.notifier_seq = mmu_interval_read_begin();
down_read(>mmap_sem);
ret = hmm_range_fault(, HMM_RANGE_SNAPSHOT);
if (ret) {
up_read(>mmap_sem);
- if (ret == -EBUSY) {
-/*
- * No need to check hmm_range_wait_until_valid() return value
- * on retry we will get proper error with hmm_range_fault()
- */
-hmm_range_wait_until_valid(, TIMEOUT_IN_MSEC);
-goto again;
- }
- hmm_range_unregister();
+ if (ret == -EBUSY)
+ goto again;
return ret;
}
+ up_read(>mmap_sem);
+
take_lock(driver->update);
- if (!hmm_range_valid()) {
+ if (mmu_interval_read_retry(, range.notifier_seq) {
release_lock(driver->update);
- up_read(>mmap_sem);
goto again;
}
- // Use pfns array content to update device page table
+ /* Use pfns array content to update device
[PATCH hmm v3 00/14] Consolidate the mmu notifier interval_tree and locking
From: Jason Gunthorpe 8 of the mmu_notifier using drivers (i915_gem, radeon_mn, umem_odp, hfi1, scif_dma, vhost, gntdev, hmm) drivers are using a common pattern where they only use invalidate_range_start/end and immediately check the invalidating range against some driver data structure to tell if the driver is interested. Half of them use an interval_tree, the others are simple linear search lists. Of the ones I checked they largely seem to have various kinds of races, bugs and poor implementation. This is a result of the complexity in how the notifier interacts with get_user_pages(). It is extremely difficult to use it correctly. Consolidate all of this code together into the core mmu_notifier and provide a locking scheme similar to hmm_mirror that allows the user to safely use get_user_pages() and reliably know if the page list still matches the mm. This new arrangment plays nicely with the !blockable mode for OOM. Scanning the interval tree is done such that the intersection test will always succeed, and since there is no invalidate_range_end exposed to drivers the scheme safely allows multiple drivers to be subscribed. Four places are converted as an example of how the new API is used. Four are left for future patches: - i915_gem has complex locking around destruction of a registration, needs more study - hfi1 (2nd user) needs access to the rbtree - scif_dma has a complicated logic flow - vhost's mmu notifiers are already being rewritten This is already in linux-next, a git tree is available here: https://github.com/jgunthorpe/linux/commits/mmu_notifier v3: - Rename mmu_range_notifier to mmu_interval_notifier for clarity Avoids confusion with struct mmu_notifier_range - Fix bugs in odp, amdgpu and xen gntdev from testing - Make ops an argument to mmu_interval_notifier_insert() to make it harder to misuse - Update many comments - Add testing of mm_count during insertion v2: https://lore.kernel.org/r/20191028201032.6352-1-...@ziepe.ca v1: https://lore.kernel.org/r/20191015181242.8343-1-...@ziepe.ca Absent any new discussion I think this will go to Linus at the next merge window. Thanks to everyone to helped! Jason Gunthorpe (14): mm/mmu_notifier: define the header pre-processor parts even if disabled mm/mmu_notifier: add an interval tree notifier mm/hmm: allow hmm_range to be used with a mmu_interval_notifier or hmm_mirror mm/hmm: define the pre-processor related parts of hmm.h even if disabled RDMA/odp: Use mmu_interval_notifier_insert() RDMA/hfi1: Use mmu_interval_notifier_insert for user_exp_rcv drm/radeon: use mmu_interval_notifier_insert nouveau: use mmu_notifier directly for invalidate_range_start nouveau: use mmu_interval_notifier instead of hmm_mirror drm/amdgpu: Call find_vma under mmap_sem drm/amdgpu: Use mmu_interval_insert instead of hmm_mirror drm/amdgpu: Use mmu_interval_notifier instead of hmm_mirror mm/hmm: remove hmm_mirror and related xen/gntdev: use mmu_interval_notifier_insert Documentation/vm/hmm.rst | 105 +--- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 + .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 9 +- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c| 14 +- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c| 443 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h| 53 -- drivers/gpu/drm/amd/amdgpu/amdgpu_object.h| 13 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 145 +++-- drivers/gpu/drm/nouveau/nouveau_svm.c | 230 --- drivers/gpu/drm/radeon/radeon.h | 9 +- drivers/gpu/drm/radeon/radeon_mn.c| 218 ++- drivers/infiniband/core/device.c | 1 - drivers/infiniband/core/umem_odp.c| 303 ++ drivers/infiniband/hw/hfi1/file_ops.c | 2 +- drivers/infiniband/hw/hfi1/hfi.h | 2 +- drivers/infiniband/hw/hfi1/user_exp_rcv.c | 146 ++--- drivers/infiniband/hw/hfi1/user_exp_rcv.h | 3 +- drivers/infiniband/hw/mlx5/mlx5_ib.h | 7 +- drivers/infiniband/hw/mlx5/mr.c | 3 +- drivers/infiniband/hw/mlx5/odp.c | 50 +- drivers/xen/gntdev-common.h | 8 +- drivers/xen/gntdev.c | 179 ++ include/linux/hmm.h | 195 +- include/linux/mmu_notifier.h | 147 - include/rdma/ib_umem_odp.h| 68 +-- include/rdma/ib_verbs.h | 2 - kernel/fork.c | 1 - mm/Kconfig| 2 +- mm/hmm.c | 276 + mm/mmu_notifier.c | 565 +- 31 files changed, 1271 insertions(+), 1931 deletions(-) -- 2.24.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org
[PATCH v3 11/14] drm/amdgpu: Use mmu_interval_insert instead of hmm_mirror
From: Jason Gunthorpe
Remove the interval tree in the driver and rely on the tree maintained by
the mmu_notifier for delivering mmu_notifier invalidation callbacks.
For some reason amdgpu has a very complicated arrangement where it tries
to prevent duplicate entries in the interval_tree, this is not necessary,
each amdgpu_bo can be its own stand alone entry. interval_tree already
allows duplicates and overlaps in the tree.
Also, there is no need to remove entries upon a release callback, the
mmu_interval API safely allows objects to remain registered beyond the
lifetime of the mm. The driver only has to stop touching the pages during
release.
Reviewed-by: Philip Yang
Tested-by: Philip Yang
Signed-off-by: Jason Gunthorpe
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 +
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 5 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c| 333 --
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h| 4 -
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h| 13 +-
6 files changed, 77 insertions(+), 281 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index bd37df5dd6d048..60591a5d420021 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1006,6 +1006,8 @@ struct amdgpu_device {
struct mutex lock_reset;
struct amdgpu_doorbell_index doorbell_index;
+ struct mutexnotifier_lock;
+
int asic_reset_res;
struct work_struct xgmi_reset_work;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index 6d021ecc8d598f..47700302a08b7f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -481,8 +481,7 @@ static void remove_kgd_mem_from_kfd_bo_list(struct kgd_mem
*mem,
*
* Returns 0 for success, negative errno for errors.
*/
-static int init_user_pages(struct kgd_mem *mem, struct mm_struct *mm,
- uint64_t user_addr)
+static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr)
{
struct amdkfd_process_info *process_info = mem->process_info;
struct amdgpu_bo *bo = mem->bo;
@@ -1195,7 +1194,7 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
add_kgd_mem_to_kfd_bo_list(*mem, avm->process_info, user_addr);
if (user_addr) {
- ret = init_user_pages(*mem, current->mm, user_addr);
+ ret = init_user_pages(*mem, user_addr);
if (ret)
goto allocate_init_user_pages_failed;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 5a1939dbd4e3e6..38f97998aaddb2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2633,6 +2633,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
mutex_init(>virt.vf_errors.lock);
hash_init(adev->mn_hash);
mutex_init(>lock_reset);
+ mutex_init(>notifier_lock);
mutex_init(>virt.dpm_mutex);
mutex_init(>psp.mutex);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
index 31d4deb5d29484..9fe1c31ce17a30 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
@@ -50,66 +50,6 @@
#include "amdgpu.h"
#include "amdgpu_amdkfd.h"
-/**
- * struct amdgpu_mn_node
- *
- * @it: interval node defining start-last of the affected address range
- * @bos: list of all BOs in the affected address range
- *
- * Manages all BOs which are affected of a certain range of address space.
- */
-struct amdgpu_mn_node {
- struct interval_tree_node it;
- struct list_headbos;
-};
-
-/**
- * amdgpu_mn_destroy - destroy the HMM mirror
- *
- * @work: previously sheduled work item
- *
- * Lazy destroys the notifier from a work item
- */
-static void amdgpu_mn_destroy(struct work_struct *work)
-{
- struct amdgpu_mn *amn = container_of(work, struct amdgpu_mn, work);
- struct amdgpu_device *adev = amn->adev;
- struct amdgpu_mn_node *node, *next_node;
- struct amdgpu_bo *bo, *next_bo;
-
- mutex_lock(>mn_lock);
- down_write(>lock);
- hash_del(>node);
- rbtree_postorder_for_each_entry_safe(node, next_node,
->objects.rb_root, it.rb) {
- list_for_each_entry_safe(bo, next_bo, >bos, mn_list) {
- bo->mn = NULL;
- list_del_init(>mn_list);
- }
- kfree(node);
- }
- up_write(>lock);
- mutex_unlock(>mn_lock);
-
- hmm_mirror_unregister(>mirror);
- kfree(amn);
-}
-
-/**
- * amdgpu_hmm_mirror_release - callback to notify about mm
[PATCH v3 02/14] mm/mmu_notifier: add an interval tree notifier
From: Jason Gunthorpe
Of the 13 users of mmu_notifiers, 8 of them use only
invalidate_range_start/end() and immediately intersect the
mmu_notifier_range with some kind of internal list of VAs. 4 use an
interval tree (i915_gem, radeon_mn, umem_odp, hfi1). 4 use a linked list
of some kind (scif_dma, vhost, gntdev, hmm)
And the remaining 5 either don't use invalidate_range_start() or do some
special thing with it.
It turns out that building a correct scheme with an interval tree is
pretty complicated, particularly if the use case is synchronizing against
another thread doing get_user_pages(). Many of these implementations have
various subtle and difficult to fix races.
This approach puts the interval tree as common code at the top of the mmu
notifier call tree and implements a shareable locking scheme.
It includes:
- An interval tree tracking VA ranges, with per-range callbacks
- A read/write locking scheme for the interval tree that avoids
sleeping in the notifier path (for OOM killer)
- A sequence counter based collision-retry locking scheme to tell
device page fault that a VA range is being concurrently invalidated.
This is based on various ideas:
- hmm accumulates invalidated VA ranges and releases them when all
invalidates are done, via active_invalidate_ranges count.
This approach avoids having to intersect the interval tree twice (as
umem_odp does) at the potential cost of a longer device page fault.
- kvm/umem_odp use a sequence counter to drive the collision retry,
via invalidate_seq
- a deferred work todo list on unlock scheme like RTNL, via deferred_list.
This makes adding/removing interval tree members more deterministic
- seqlock, except this version makes the seqlock idea multi-holder on the
write side by protecting it with active_invalidate_ranges and a spinlock
To minimize MM overhead when only the interval tree is being used, the
entire SRCU and hlist overheads are dropped using some simple
branches. Similarly the interval tree overhead is dropped when in hlist
mode.
The overhead from the mandatory spinlock is broadly the same as most of
existing users which already had a lock (or two) of some sort on the
invalidation path.
Acked-by: Christian König
Tested-by: Philip Yang
Tested-by: Ralph Campbell
Reviewed-by: John Hubbard
Signed-off-by: Jason Gunthorpe
---
include/linux/mmu_notifier.h | 101 +++
mm/Kconfig | 1 +
mm/mmu_notifier.c| 552 +--
3 files changed, 628 insertions(+), 26 deletions(-)
diff --git a/include/linux/mmu_notifier.h b/include/linux/mmu_notifier.h
index 12bd603d318ce7..9e6caa8ecd1938 100644
--- a/include/linux/mmu_notifier.h
+++ b/include/linux/mmu_notifier.h
@@ -6,10 +6,12 @@
#include
#include
#include
+#include
struct mmu_notifier_mm;
struct mmu_notifier;
struct mmu_notifier_range;
+struct mmu_interval_notifier;
/**
* enum mmu_notifier_event - reason for the mmu notifier callback
@@ -32,6 +34,9 @@ struct mmu_notifier_range;
* access flags). User should soft dirty the page in the end callback to make
* sure that anyone relying on soft dirtyness catch pages that might be written
* through non CPU mappings.
+ *
+ * @MMU_NOTIFY_RELEASE: used during mmu_interval_notifier invalidate to signal
+ * that the mm refcount is zero and the range is no longer accessible.
*/
enum mmu_notifier_event {
MMU_NOTIFY_UNMAP = 0,
@@ -39,6 +44,7 @@ enum mmu_notifier_event {
MMU_NOTIFY_PROTECTION_VMA,
MMU_NOTIFY_PROTECTION_PAGE,
MMU_NOTIFY_SOFT_DIRTY,
+ MMU_NOTIFY_RELEASE,
};
#define MMU_NOTIFIER_RANGE_BLOCKABLE (1 << 0)
@@ -222,6 +228,26 @@ struct mmu_notifier {
unsigned int users;
};
+/**
+ * struct mmu_interval_notifier_ops
+ * @invalidate: Upon return the caller must stop using any SPTEs within this
+ * range. This function can sleep. Return false only if sleeping
+ * was required but mmu_notifier_range_blockable(range) is false.
+ */
+struct mmu_interval_notifier_ops {
+ bool (*invalidate)(struct mmu_interval_notifier *mni,
+ const struct mmu_notifier_range *range,
+ unsigned long cur_seq);
+};
+
+struct mmu_interval_notifier {
+ struct interval_tree_node interval_tree;
+ const struct mmu_interval_notifier_ops *ops;
+ struct mm_struct *mm;
+ struct hlist_node deferred_item;
+ unsigned long invalidate_seq;
+};
+
#ifdef CONFIG_MMU_NOTIFIER
#ifdef CONFIG_LOCKDEP
@@ -263,6 +289,81 @@ extern int __mmu_notifier_register(struct mmu_notifier *mn,
struct mm_struct *mm);
extern void mmu_notifier_unregister(struct mmu_notifier *mn,
struct mm_struct *mm);
+
+unsigned long mmu_interval_read_begin(struct mmu_interval_notifier *mni);
+int mmu_interval_notifier_insert(struct mmu_interval_notifier *mni,
+
[PATCH v3 08/14] nouveau: use mmu_notifier directly for invalidate_range_start
From: Jason Gunthorpe
There is no reason to get the invalidate_range_start() callback via an
indirection through hmm_mirror, just register a normal notifier directly.
Tested-by: Ralph Campbell
Signed-off-by: Jason Gunthorpe
---
drivers/gpu/drm/nouveau/nouveau_svm.c | 95 ++-
1 file changed, 63 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/nouveau_svm.c
b/drivers/gpu/drm/nouveau/nouveau_svm.c
index 668d4bd0c118f1..577f8811925a59 100644
--- a/drivers/gpu/drm/nouveau/nouveau_svm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_svm.c
@@ -88,6 +88,7 @@ nouveau_ivmm_find(struct nouveau_svm *svm, u64 inst)
}
struct nouveau_svmm {
+ struct mmu_notifier notifier;
struct nouveau_vmm *vmm;
struct {
unsigned long start;
@@ -96,7 +97,6 @@ struct nouveau_svmm {
struct mutex mutex;
- struct mm_struct *mm;
struct hmm_mirror mirror;
};
@@ -251,10 +251,11 @@ nouveau_svmm_invalidate(struct nouveau_svmm *svmm, u64
start, u64 limit)
}
static int
-nouveau_svmm_sync_cpu_device_pagetables(struct hmm_mirror *mirror,
- const struct mmu_notifier_range *update)
+nouveau_svmm_invalidate_range_start(struct mmu_notifier *mn,
+ const struct mmu_notifier_range *update)
{
- struct nouveau_svmm *svmm = container_of(mirror, typeof(*svmm), mirror);
+ struct nouveau_svmm *svmm =
+ container_of(mn, struct nouveau_svmm, notifier);
unsigned long start = update->start;
unsigned long limit = update->end;
@@ -264,6 +265,9 @@ nouveau_svmm_sync_cpu_device_pagetables(struct hmm_mirror
*mirror,
SVMM_DBG(svmm, "invalidate %016lx-%016lx", start, limit);
mutex_lock(>mutex);
+ if (unlikely(!svmm->vmm))
+ goto out;
+
if (limit > svmm->unmanaged.start && start < svmm->unmanaged.limit) {
if (start < svmm->unmanaged.start) {
nouveau_svmm_invalidate(svmm, start,
@@ -273,19 +277,31 @@ nouveau_svmm_sync_cpu_device_pagetables(struct hmm_mirror
*mirror,
}
nouveau_svmm_invalidate(svmm, start, limit);
+
+out:
mutex_unlock(>mutex);
return 0;
}
-static void
-nouveau_svmm_release(struct hmm_mirror *mirror)
+static void nouveau_svmm_free_notifier(struct mmu_notifier *mn)
+{
+ kfree(container_of(mn, struct nouveau_svmm, notifier));
+}
+
+static const struct mmu_notifier_ops nouveau_mn_ops = {
+ .invalidate_range_start = nouveau_svmm_invalidate_range_start,
+ .free_notifier = nouveau_svmm_free_notifier,
+};
+
+static int
+nouveau_svmm_sync_cpu_device_pagetables(struct hmm_mirror *mirror,
+ const struct mmu_notifier_range *update)
{
+ return 0;
}
-static const struct hmm_mirror_ops
-nouveau_svmm = {
+static const struct hmm_mirror_ops nouveau_svmm = {
.sync_cpu_device_pagetables = nouveau_svmm_sync_cpu_device_pagetables,
- .release = nouveau_svmm_release,
};
void
@@ -294,7 +310,10 @@ nouveau_svmm_fini(struct nouveau_svmm **psvmm)
struct nouveau_svmm *svmm = *psvmm;
if (svmm) {
hmm_mirror_unregister(>mirror);
- kfree(*psvmm);
+ mutex_lock(>mutex);
+ svmm->vmm = NULL;
+ mutex_unlock(>mutex);
+ mmu_notifier_put(>notifier);
*psvmm = NULL;
}
}
@@ -320,7 +339,7 @@ nouveau_svmm_init(struct drm_device *dev, void *data,
mutex_lock(>mutex);
if (cli->svm.cli) {
ret = -EBUSY;
- goto done;
+ goto out_free;
}
/* Allocate a new GPU VMM that can support SVM (managed by the
@@ -335,24 +354,33 @@ nouveau_svmm_init(struct drm_device *dev, void *data,
.fault_replay = true,
}, sizeof(struct gp100_vmm_v0), >svm.vmm);
if (ret)
- goto done;
+ goto out_free;
- /* Enable HMM mirroring of CPU address-space to VMM. */
- svmm->mm = get_task_mm(current);
- down_write(>mm->mmap_sem);
+ down_write(>mm->mmap_sem);
svmm->mirror.ops = _svmm;
- ret = hmm_mirror_register(>mirror, svmm->mm);
- if (ret == 0) {
- cli->svm.svmm = svmm;
- cli->svm.cli = cli;
- }
- up_write(>mm->mmap_sem);
- mmput(svmm->mm);
+ ret = hmm_mirror_register(>mirror, current->mm);
+ if (ret)
+ goto out_mm_unlock;
-done:
+ svmm->notifier.ops = _mn_ops;
+ ret = __mmu_notifier_register(>notifier, current->mm);
if (ret)
- nouveau_svmm_fini();
+ goto out_hmm_unregister;
+ /* Note, ownership of svmm transfers to mmu_notifier */
+
+ cli->svm.svmm = svmm;
+ cli->svm.cli = cli;
+ up_write(>mm->mmap_sem);
Re: [PATCH 00/21] Separate JPEG from VCN
On 2019-11-12 3:34 p.m., Alex Deucher wrote: On Tue, Nov 12, 2019 at 3:16 PM Leo Liu wrote: On 2019-11-12 3:12 p.m., Alex Deucher wrote: On Tue, Nov 12, 2019 at 2:57 PM Leo Liu wrote: On 2019-11-12 2:49 p.m., Alex Deucher wrote: On Tue, Nov 12, 2019 at 1:03 PM Leo Liu wrote: From JPEG2.0, JPEG is a separated IP block, and has it own PG/CG, and power management. It doesn't require FW, so indepedent from FW loading as well. Patch 1-4: Separate JPEG1.0 from SW wise, since JPEG1.0 is still combined with VCN1.0 esp. in power management; Patch 5-10: Separate JPEG2.0 as an independent IP with PG/CG; Patch 11-15: Add power management for JPEG of Navi1x and Renoir; Patch 16: Enable JPEG2.0; Patch 17-20: Separate JPEG2.5 from VCN2.5; Patch 21: Enable JPEG2.5 Is the jpeg powergating dynamic or do we need a idle work thread to turn it off like we do for vcn? It has static PG/CG for JPEG2.0 and static CG for JPEG2.5. It also has DPM for JPEG2.0. So we need idle work thread and begin_use like VCN to init/deinit JPEG and turn on/off JPEG power through SMU messages such as PowerUPJpeg and PowerDownJpeg. Ok, so that still has to be implemented then. I didn't see that in the patch set. "amdgpu_jpeg_idle_work_handler" is in patch 6, and calling those SMU messages are in those powerplay patches. The set is complete for all JPEGs Ah, yeah, I missed that patch the first time around. Thanks! Yeah, the set is too big. Sorry about that. Should do this changes earlier, but just get around to it:-) Leo Alex Thanks, Leo Thanks, Alex Thanks, Leo Alex Leo Liu (21): drm/amdgpu: add JPEG HW IP and SW structures drm/amdgpu: add amdgpu_jpeg and JPEG tests drm/amdgpu: separate JPEG1.0 code out from VCN1.0 drm/amdgpu: use the JPEG structure for general driver support drm/amdgpu: add JPEG IP block type drm/amdgpu: add JPEG common functions to amdgpu_jpeg drm/amdgpu: add JPEG v2.0 function supports drm/amdgpu: remove unnecessary JPEG2.0 code from VCN2.0 drm/amdgpu: add JPEG PG and CG interface drm/amdgpu: add PG and CG for JPEG2.0 drm/amd/powerplay: add JPEG Powerplay interface drm/amd/powerplay: add JPEG power control for Navi1x drm/amd/powerplay: add Powergate JPEG for Renoir drm/amd/powerplay: add JPEG power control for Renoir drm/amd/powerplay: set JPEG to SMU dpm drm/amdgpu: enable JPEG2.0 dpm drm/amdgpu: add driver support for JPEG2.0 and above drm/amdgpu: enable JPEG2.0 for Navi1x and Renoir drm/amdgpu: move JPEG2.5 out from VCN2.5 drm/amdgpu: enable Arcturus CG for VCN and JPEG blocks drm/amdgpu: enable Arcturus JPEG2.5 block drivers/gpu/drm/amd/amdgpu/Makefile | 8 +- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 5 + drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 4 +- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c | 215 + drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h | 62 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 15 +- drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c| 8 + drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h| 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 113 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 5 - drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c| 584 + drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.h| 32 + drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c| 827 ++ drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.h| 42 + drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c| 641 ++ drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.h| 29 + drivers/gpu/drm/amd/amdgpu/nv.c | 11 +- drivers/gpu/drm/amd/amdgpu/soc15.c| 10 +- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 481 +- drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 496 +-- drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h | 13 - drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 246 +- drivers/gpu/drm/amd/include/amd_shared.h | 5 +- drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 5 + .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h| 3 + drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h | 2 + drivers/gpu/drm/amd/powerplay/navi10_ppt.c| 32 +- drivers/gpu/drm/amd/powerplay/renoir_ppt.c| 27 + drivers/gpu/drm/amd/powerplay/smu_internal.h | 4 + drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 11 + 31 files changed, 2593 insertions(+), 1346 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h create mode 100644 drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c create mode 100644 drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.h create mode 100644 drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c create mode 100644
Re: [PATCH 00/21] Separate JPEG from VCN
On Tue, Nov 12, 2019 at 3:16 PM Leo Liu wrote: > > > On 2019-11-12 3:12 p.m., Alex Deucher wrote: > > On Tue, Nov 12, 2019 at 2:57 PM Leo Liu wrote: > >> > >> On 2019-11-12 2:49 p.m., Alex Deucher wrote: > >>> On Tue, Nov 12, 2019 at 1:03 PM Leo Liu wrote: > From JPEG2.0, JPEG is a separated IP block, and has it own PG/CG, > and power management. It doesn't require FW, so indepedent from FW > loading as well. > > Patch 1-4: Separate JPEG1.0 from SW wise, since JPEG1.0 is still > combined with VCN1.0 esp. in power management; > Patch 5-10: Separate JPEG2.0 as an independent IP with PG/CG; > Patch 11-15: Add power management for JPEG of Navi1x and Renoir; > Patch 16: Enable JPEG2.0; > Patch 17-20: Separate JPEG2.5 from VCN2.5; > Patch 21: Enable JPEG2.5 > > >>> Is the jpeg powergating dynamic or do we need a idle work thread to > >>> turn it off like we do for vcn? > >> It has static PG/CG for JPEG2.0 and static CG for JPEG2.5. > >> > >> It also has DPM for JPEG2.0. So we need idle work thread and begin_use > >> like VCN to init/deinit JPEG and turn on/off JPEG power through SMU > >> messages such as PowerUPJpeg and PowerDownJpeg. > > Ok, so that still has to be implemented then. I didn't see that in > > the patch set. > > "amdgpu_jpeg_idle_work_handler" is in patch 6, and calling those SMU messages > are in those powerplay patches. > > The set is complete for all JPEGs Ah, yeah, I missed that patch the first time around. Thanks! Alex > > Thanks, > Leo > > > > Thanks, > > > > Alex > > > >> > >> Thanks, > >> Leo > >> > >> > >>> Alex > >>> > Leo Liu (21): > drm/amdgpu: add JPEG HW IP and SW structures > drm/amdgpu: add amdgpu_jpeg and JPEG tests > drm/amdgpu: separate JPEG1.0 code out from VCN1.0 > drm/amdgpu: use the JPEG structure for general driver support > drm/amdgpu: add JPEG IP block type > drm/amdgpu: add JPEG common functions to amdgpu_jpeg > drm/amdgpu: add JPEG v2.0 function supports > drm/amdgpu: remove unnecessary JPEG2.0 code from VCN2.0 > drm/amdgpu: add JPEG PG and CG interface > drm/amdgpu: add PG and CG for JPEG2.0 > drm/amd/powerplay: add JPEG Powerplay interface > drm/amd/powerplay: add JPEG power control for Navi1x > drm/amd/powerplay: add Powergate JPEG for Renoir > drm/amd/powerplay: add JPEG power control for Renoir > drm/amd/powerplay: set JPEG to SMU dpm > drm/amdgpu: enable JPEG2.0 dpm > drm/amdgpu: add driver support for JPEG2.0 and above > drm/amdgpu: enable JPEG2.0 for Navi1x and Renoir > drm/amdgpu: move JPEG2.5 out from VCN2.5 > drm/amdgpu: enable Arcturus CG for VCN and JPEG blocks > drm/amdgpu: enable Arcturus JPEG2.5 block > > drivers/gpu/drm/amd/amdgpu/Makefile | 8 +- > drivers/gpu/drm/amd/amdgpu/amdgpu.h | 5 + > drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 4 +- > drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 2 + > drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c | 215 + > drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h | 62 ++ > drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 15 +- > drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c| 8 + > drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h| 1 + > drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 113 +-- > drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 5 - > drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c| 584 + > drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.h| 32 + > drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c| 827 ++ > drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.h| 42 + > drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c| 641 ++ > drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.h| 29 + > drivers/gpu/drm/amd/amdgpu/nv.c | 11 +- > drivers/gpu/drm/amd/amdgpu/soc15.c| 10 +- > drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 481 +- > drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 496 +-- > drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h | 13 - > drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 246 +- > drivers/gpu/drm/amd/include/amd_shared.h | 5 +- > drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 5 + > .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h| 3 + > drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h | 2 + > drivers/gpu/drm/amd/powerplay/navi10_ppt.c| 32 +- > drivers/gpu/drm/amd/powerplay/renoir_ppt.c| 27 + > drivers/gpu/drm/amd/powerplay/smu_internal.h | 4 + > drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 11 + > 31 files changed, 2593 insertions(+), 1346
Re: [PATCH -next] drm/amd/display: Fix old-style declaration
On 2019-11-12 2:51 a.m., Yuehaibing wrote:
> On 2019/11/12 10:39, Joe Perches wrote:
>> On Mon, 2019-11-11 at 20:28 +0800, YueHaibing wrote:
>>> Fix a build warning:
>>>
>>> drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:75:1:
>>> warning: 'static' is not at beginning of declaration
>>> [-Wold-style-declaration]
>> []
>>> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
>>> b/drivers/gpu/drm/amd/display/dc/core/dc.c
>> []
>>> @@ -69,7 +69,7 @@
>>> #define DC_LOGGER \
>>> dc->ctx->logger
>>>
>>> -const static char DC_BUILD_ID[] = "production-build";
>>> +static const char DC_BUILD_ID[] = "production-build";
>>
>> DC_BUILD_ID is used exactly once.
>> Maybe just use it directly and remove DC_BUILD_ID instead?
>
> commit be61df574256ae8c0dbd45ac148ca7260a0483c0
> Author: Jun Lei
> Date: Thu Sep 13 09:32:26 2018 -0400
>
> drm/amd/display: Add DC build_id to determine build type
>
> [why]
> Sometimes there are indications that the incorrect driver is being
> loaded in automated tests. This change adds the ability for builds to
> be tagged with a string, and picked up by the test infrastructure.
>
> [how]
> dc.c will allocate const for build id, which is init-ed with default
> value, indicating production build. For test builds, build server will
> find/replace this value. The test machine will then verify this value.
>
> It seems DC_BUILD_ID is used by the build server, so maybe we should keep it.
Thanks, Haibing. Yes, we'll want to keep it for build purposes.
Harry
>
>>
>> ---
>> drivers/gpu/drm/amd/display/dc/core/dc.c | 4 +---
>> 1 file changed, 1 insertion(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
>> b/drivers/gpu/drm/amd/display/dc/core/dc.c
>> index 1fdba13..803dc14 100644
>> --- a/drivers/gpu/drm/amd/display/dc/core/dc.c
>> +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
>> @@ -69,8 +69,6 @@
>> #define DC_LOGGER \
>> dc->ctx->logger
>>
>> -const static char DC_BUILD_ID[] = "production-build";
>> -
>> /**
>> * DOC: Overview
>> *
>> @@ -815,7 +813,7 @@ struct dc *dc_create(const struct dc_init_data
>> *init_params)
>> if (dc->res_pool->dmcu != NULL)
>> dc->versions.dmcu_version = dc->res_pool->dmcu->dmcu_version;
>>
>> -dc->build_id = DC_BUILD_ID;
>> +dc->build_id = "production-build";
>>
>> DC_LOG_DC("Display Core initialized\n");
>>
>>
>>
>>
>> .
>>
>
___
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Re: [PATCH -next] drm/amd/display: Fix old-style declaration
On 2019-11-11 7:28 a.m., YueHaibing wrote: > Fix a build warning: > > drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:75:1: > warning: 'static' is not at beginning of declaration > [-Wold-style-declaration] > > Signed-off-by: YueHaibing Reviewed-by: Harry Wentland Harry > --- > drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c > b/drivers/gpu/drm/amd/display/dc/core/dc.c > index 1fdba13..0d8c663 100644 > --- a/drivers/gpu/drm/amd/display/dc/core/dc.c > +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c > @@ -69,7 +69,7 @@ > #define DC_LOGGER \ > dc->ctx->logger > > -const static char DC_BUILD_ID[] = "production-build"; > +static const char DC_BUILD_ID[] = "production-build"; > > /** > * DOC: Overview > ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 00/21] Separate JPEG from VCN
On 2019-11-12 3:12 p.m., Alex Deucher wrote: On Tue, Nov 12, 2019 at 2:57 PM Leo Liu wrote: On 2019-11-12 2:49 p.m., Alex Deucher wrote: On Tue, Nov 12, 2019 at 1:03 PM Leo Liu wrote: From JPEG2.0, JPEG is a separated IP block, and has it own PG/CG, and power management. It doesn't require FW, so indepedent from FW loading as well. Patch 1-4: Separate JPEG1.0 from SW wise, since JPEG1.0 is still combined with VCN1.0 esp. in power management; Patch 5-10: Separate JPEG2.0 as an independent IP with PG/CG; Patch 11-15: Add power management for JPEG of Navi1x and Renoir; Patch 16: Enable JPEG2.0; Patch 17-20: Separate JPEG2.5 from VCN2.5; Patch 21: Enable JPEG2.5 Is the jpeg powergating dynamic or do we need a idle work thread to turn it off like we do for vcn? It has static PG/CG for JPEG2.0 and static CG for JPEG2.5. It also has DPM for JPEG2.0. So we need idle work thread and begin_use like VCN to init/deinit JPEG and turn on/off JPEG power through SMU messages such as PowerUPJpeg and PowerDownJpeg. Ok, so that still has to be implemented then. I didn't see that in the patch set. "amdgpu_jpeg_idle_work_handler" is in patch 6, and calling those SMU messages are in those powerplay patches. The set is complete for all JPEGs Thanks, Leo Thanks, Alex Thanks, Leo Alex Leo Liu (21): drm/amdgpu: add JPEG HW IP and SW structures drm/amdgpu: add amdgpu_jpeg and JPEG tests drm/amdgpu: separate JPEG1.0 code out from VCN1.0 drm/amdgpu: use the JPEG structure for general driver support drm/amdgpu: add JPEG IP block type drm/amdgpu: add JPEG common functions to amdgpu_jpeg drm/amdgpu: add JPEG v2.0 function supports drm/amdgpu: remove unnecessary JPEG2.0 code from VCN2.0 drm/amdgpu: add JPEG PG and CG interface drm/amdgpu: add PG and CG for JPEG2.0 drm/amd/powerplay: add JPEG Powerplay interface drm/amd/powerplay: add JPEG power control for Navi1x drm/amd/powerplay: add Powergate JPEG for Renoir drm/amd/powerplay: add JPEG power control for Renoir drm/amd/powerplay: set JPEG to SMU dpm drm/amdgpu: enable JPEG2.0 dpm drm/amdgpu: add driver support for JPEG2.0 and above drm/amdgpu: enable JPEG2.0 for Navi1x and Renoir drm/amdgpu: move JPEG2.5 out from VCN2.5 drm/amdgpu: enable Arcturus CG for VCN and JPEG blocks drm/amdgpu: enable Arcturus JPEG2.5 block drivers/gpu/drm/amd/amdgpu/Makefile | 8 +- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 5 + drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 4 +- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c | 215 + drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h | 62 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 15 +- drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c| 8 + drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h| 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 113 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 5 - drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c| 584 + drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.h| 32 + drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c| 827 ++ drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.h| 42 + drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c| 641 ++ drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.h| 29 + drivers/gpu/drm/amd/amdgpu/nv.c | 11 +- drivers/gpu/drm/amd/amdgpu/soc15.c| 10 +- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 481 +- drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 496 +-- drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h | 13 - drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 246 +- drivers/gpu/drm/amd/include/amd_shared.h | 5 +- drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 5 + .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h| 3 + drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h | 2 + drivers/gpu/drm/amd/powerplay/navi10_ppt.c| 32 +- drivers/gpu/drm/amd/powerplay/renoir_ppt.c| 27 + drivers/gpu/drm/amd/powerplay/smu_internal.h | 4 + drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 11 + 31 files changed, 2593 insertions(+), 1346 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h create mode 100644 drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c create mode 100644 drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.h create mode 100644 drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c create mode 100644 drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.h create mode 100644 drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c create mode 100644 drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.h -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 1/2] drm/amd/display: Return correct error value
On 2019-11-12 11:08 a.m., Kazlauskas, Nicholas wrote:
> On 2019-11-12 10:16 a.m., mikita.lip...@amd.com wrote:
>> From: Mikita Lipski
>>
>> [why]
>> The function is expected to return instance of the timing generator
>> therefore we shouldn't be returning boolean in integer function,
>> and we shouldn't be returning zero so changing it to -1.
>>
>> Signed-off-by: Mikita Lipski
>
> I wonder if some of these were intentional for returning 0. These lines
> were originally introduced for enabling seamless boot support with eDP
> and I think you're guaranteed to have those resources as instance 0.
>
That sounds like an incorrect way of handling this. Mikita, can you
check, though, with the original authors (Anthony?) of this function and
make sure you get an ack from them?
If there's no objections from Anthony you can add my
Reviewed-by: Harry Wentland
Harry
> Nicholas Kazlauskas
>
>> ---
>> drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 6 +++---
>> 1 file changed, 3 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
>> b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
>> index 89b5f86cd40b..75cc58ecf647 100644
>> --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
>> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
>> @@ -1866,7 +1866,7 @@ static int acquire_resource_from_hw_enabled_state(
>> inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
>> if (inst == ENGINE_ID_UNKNOWN)
>> - return false;
>> + return -1;
>> for (i = 0; i < pool->stream_enc_count; i++) {
>> if (pool->stream_enc[i]->id == inst) {
>> @@ -1878,10 +1878,10 @@ static int
>> acquire_resource_from_hw_enabled_state(
>> // tg_inst not found
>> if (i == pool->stream_enc_count)
>> - return false;
>> + return -1;
>> if (tg_inst >= pool->timing_generator_count)
>> - return false;
>> + return -1;
>> if (!res_ctx->pipe_ctx[tg_inst].stream) {
>> struct pipe_ctx *pipe_ctx = _ctx->pipe_ctx[tg_inst];
>>
>
___
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 00/21] Separate JPEG from VCN
On Tue, Nov 12, 2019 at 2:57 PM Leo Liu wrote: > > > On 2019-11-12 2:49 p.m., Alex Deucher wrote: > > On Tue, Nov 12, 2019 at 1:03 PM Leo Liu wrote: > >> From JPEG2.0, JPEG is a separated IP block, and has it own PG/CG, > >> and power management. It doesn't require FW, so indepedent from FW > >> loading as well. > >> > >> Patch 1-4: Separate JPEG1.0 from SW wise, since JPEG1.0 is still > >> combined with VCN1.0 esp. in power management; > >> Patch 5-10: Separate JPEG2.0 as an independent IP with PG/CG; > >> Patch 11-15: Add power management for JPEG of Navi1x and Renoir; > >> Patch 16: Enable JPEG2.0; > >> Patch 17-20: Separate JPEG2.5 from VCN2.5; > >> Patch 21: Enable JPEG2.5 > >> > > Is the jpeg powergating dynamic or do we need a idle work thread to > > turn it off like we do for vcn? > > It has static PG/CG for JPEG2.0 and static CG for JPEG2.5. > > It also has DPM for JPEG2.0. So we need idle work thread and begin_use > like VCN to init/deinit JPEG and turn on/off JPEG power through SMU > messages such as PowerUPJpeg and PowerDownJpeg. Ok, so that still has to be implemented then. I didn't see that in the patch set. Thanks, Alex > > > Thanks, > Leo > > > > > > Alex > > > >> Leo Liu (21): > >>drm/amdgpu: add JPEG HW IP and SW structures > >>drm/amdgpu: add amdgpu_jpeg and JPEG tests > >>drm/amdgpu: separate JPEG1.0 code out from VCN1.0 > >>drm/amdgpu: use the JPEG structure for general driver support > >>drm/amdgpu: add JPEG IP block type > >>drm/amdgpu: add JPEG common functions to amdgpu_jpeg > >>drm/amdgpu: add JPEG v2.0 function supports > >>drm/amdgpu: remove unnecessary JPEG2.0 code from VCN2.0 > >>drm/amdgpu: add JPEG PG and CG interface > >>drm/amdgpu: add PG and CG for JPEG2.0 > >>drm/amd/powerplay: add JPEG Powerplay interface > >>drm/amd/powerplay: add JPEG power control for Navi1x > >>drm/amd/powerplay: add Powergate JPEG for Renoir > >>drm/amd/powerplay: add JPEG power control for Renoir > >>drm/amd/powerplay: set JPEG to SMU dpm > >>drm/amdgpu: enable JPEG2.0 dpm > >>drm/amdgpu: add driver support for JPEG2.0 and above > >>drm/amdgpu: enable JPEG2.0 for Navi1x and Renoir > >>drm/amdgpu: move JPEG2.5 out from VCN2.5 > >>drm/amdgpu: enable Arcturus CG for VCN and JPEG blocks > >>drm/amdgpu: enable Arcturus JPEG2.5 block > >> > >> drivers/gpu/drm/amd/amdgpu/Makefile | 8 +- > >> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 5 + > >> drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 4 +- > >> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 2 + > >> drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c | 215 + > >> drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h | 62 ++ > >> drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 15 +- > >> drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c| 8 + > >> drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h| 1 + > >> drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 113 +-- > >> drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 5 - > >> drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c| 584 + > >> drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.h| 32 + > >> drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c| 827 ++ > >> drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.h| 42 + > >> drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c| 641 ++ > >> drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.h| 29 + > >> drivers/gpu/drm/amd/amdgpu/nv.c | 11 +- > >> drivers/gpu/drm/amd/amdgpu/soc15.c| 10 +- > >> drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 481 +- > >> drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 496 +-- > >> drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h | 13 - > >> drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 246 +- > >> drivers/gpu/drm/amd/include/amd_shared.h | 5 +- > >> drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 5 + > >> .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h| 3 + > >> drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h | 2 + > >> drivers/gpu/drm/amd/powerplay/navi10_ppt.c| 32 +- > >> drivers/gpu/drm/amd/powerplay/renoir_ppt.c| 27 + > >> drivers/gpu/drm/amd/powerplay/smu_internal.h | 4 + > >> drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 11 + > >> 31 files changed, 2593 insertions(+), 1346 deletions(-) > >> create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c > >> create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h > >> create mode 100644 drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c > >> create mode 100644 drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.h > >> create mode 100644 drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c > >> create mode 100644 drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.h > >> create mode 100644 drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c > >> create mode 100644 drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.h > >> > >> -- > >> 2.17.1 > >> > >>
Re: [PATCH 00/21] Separate JPEG from VCN
On 2019-11-12 2:49 p.m., Alex Deucher wrote: On Tue, Nov 12, 2019 at 1:03 PM Leo Liu wrote: From JPEG2.0, JPEG is a separated IP block, and has it own PG/CG, and power management. It doesn't require FW, so indepedent from FW loading as well. Patch 1-4: Separate JPEG1.0 from SW wise, since JPEG1.0 is still combined with VCN1.0 esp. in power management; Patch 5-10: Separate JPEG2.0 as an independent IP with PG/CG; Patch 11-15: Add power management for JPEG of Navi1x and Renoir; Patch 16: Enable JPEG2.0; Patch 17-20: Separate JPEG2.5 from VCN2.5; Patch 21: Enable JPEG2.5 Is the jpeg powergating dynamic or do we need a idle work thread to turn it off like we do for vcn? It has static PG/CG for JPEG2.0 and static CG for JPEG2.5. It also has DPM for JPEG2.0. So we need idle work thread and begin_use like VCN to init/deinit JPEG and turn on/off JPEG power through SMU messages such as PowerUPJpeg and PowerDownJpeg. Thanks, Leo Alex Leo Liu (21): drm/amdgpu: add JPEG HW IP and SW structures drm/amdgpu: add amdgpu_jpeg and JPEG tests drm/amdgpu: separate JPEG1.0 code out from VCN1.0 drm/amdgpu: use the JPEG structure for general driver support drm/amdgpu: add JPEG IP block type drm/amdgpu: add JPEG common functions to amdgpu_jpeg drm/amdgpu: add JPEG v2.0 function supports drm/amdgpu: remove unnecessary JPEG2.0 code from VCN2.0 drm/amdgpu: add JPEG PG and CG interface drm/amdgpu: add PG and CG for JPEG2.0 drm/amd/powerplay: add JPEG Powerplay interface drm/amd/powerplay: add JPEG power control for Navi1x drm/amd/powerplay: add Powergate JPEG for Renoir drm/amd/powerplay: add JPEG power control for Renoir drm/amd/powerplay: set JPEG to SMU dpm drm/amdgpu: enable JPEG2.0 dpm drm/amdgpu: add driver support for JPEG2.0 and above drm/amdgpu: enable JPEG2.0 for Navi1x and Renoir drm/amdgpu: move JPEG2.5 out from VCN2.5 drm/amdgpu: enable Arcturus CG for VCN and JPEG blocks drm/amdgpu: enable Arcturus JPEG2.5 block drivers/gpu/drm/amd/amdgpu/Makefile | 8 +- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 5 + drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 4 +- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c | 215 + drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h | 62 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 15 +- drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c| 8 + drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h| 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 113 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 5 - drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c| 584 + drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.h| 32 + drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c| 827 ++ drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.h| 42 + drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c| 641 ++ drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.h| 29 + drivers/gpu/drm/amd/amdgpu/nv.c | 11 +- drivers/gpu/drm/amd/amdgpu/soc15.c| 10 +- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 481 +- drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 496 +-- drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h | 13 - drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 246 +- drivers/gpu/drm/amd/include/amd_shared.h | 5 +- drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 5 + .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h| 3 + drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h | 2 + drivers/gpu/drm/amd/powerplay/navi10_ppt.c| 32 +- drivers/gpu/drm/amd/powerplay/renoir_ppt.c| 27 + drivers/gpu/drm/amd/powerplay/smu_internal.h | 4 + drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 11 + 31 files changed, 2593 insertions(+), 1346 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h create mode 100644 drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c create mode 100644 drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.h create mode 100644 drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c create mode 100644 drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.h create mode 100644 drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c create mode 100644 drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.h -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 00/21] Separate JPEG from VCN
On Tue, Nov 12, 2019 at 1:03 PM Leo Liu wrote: > > From JPEG2.0, JPEG is a separated IP block, and has it own PG/CG, > and power management. It doesn't require FW, so indepedent from FW > loading as well. > > Patch 1-4: Separate JPEG1.0 from SW wise, since JPEG1.0 is still > combined with VCN1.0 esp. in power management; > Patch 5-10: Separate JPEG2.0 as an independent IP with PG/CG; > Patch 11-15: Add power management for JPEG of Navi1x and Renoir; > Patch 16: Enable JPEG2.0; > Patch 17-20: Separate JPEG2.5 from VCN2.5; > Patch 21: Enable JPEG2.5 > Is the jpeg powergating dynamic or do we need a idle work thread to turn it off like we do for vcn? Alex > Leo Liu (21): > drm/amdgpu: add JPEG HW IP and SW structures > drm/amdgpu: add amdgpu_jpeg and JPEG tests > drm/amdgpu: separate JPEG1.0 code out from VCN1.0 > drm/amdgpu: use the JPEG structure for general driver support > drm/amdgpu: add JPEG IP block type > drm/amdgpu: add JPEG common functions to amdgpu_jpeg > drm/amdgpu: add JPEG v2.0 function supports > drm/amdgpu: remove unnecessary JPEG2.0 code from VCN2.0 > drm/amdgpu: add JPEG PG and CG interface > drm/amdgpu: add PG and CG for JPEG2.0 > drm/amd/powerplay: add JPEG Powerplay interface > drm/amd/powerplay: add JPEG power control for Navi1x > drm/amd/powerplay: add Powergate JPEG for Renoir > drm/amd/powerplay: add JPEG power control for Renoir > drm/amd/powerplay: set JPEG to SMU dpm > drm/amdgpu: enable JPEG2.0 dpm > drm/amdgpu: add driver support for JPEG2.0 and above > drm/amdgpu: enable JPEG2.0 for Navi1x and Renoir > drm/amdgpu: move JPEG2.5 out from VCN2.5 > drm/amdgpu: enable Arcturus CG for VCN and JPEG blocks > drm/amdgpu: enable Arcturus JPEG2.5 block > > drivers/gpu/drm/amd/amdgpu/Makefile | 8 +- > drivers/gpu/drm/amd/amdgpu/amdgpu.h | 5 + > drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 4 +- > drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 2 + > drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c | 215 + > drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h | 62 ++ > drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 15 +- > drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c| 8 + > drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h| 1 + > drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 113 +-- > drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 5 - > drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c| 584 + > drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.h| 32 + > drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c| 827 ++ > drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.h| 42 + > drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c| 641 ++ > drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.h| 29 + > drivers/gpu/drm/amd/amdgpu/nv.c | 11 +- > drivers/gpu/drm/amd/amdgpu/soc15.c| 10 +- > drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 481 +- > drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 496 +-- > drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h | 13 - > drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 246 +- > drivers/gpu/drm/amd/include/amd_shared.h | 5 +- > drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 5 + > .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h| 3 + > drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h | 2 + > drivers/gpu/drm/amd/powerplay/navi10_ppt.c| 32 +- > drivers/gpu/drm/amd/powerplay/renoir_ppt.c| 27 + > drivers/gpu/drm/amd/powerplay/smu_internal.h | 4 + > drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 11 + > 31 files changed, 2593 insertions(+), 1346 deletions(-) > create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c > create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h > create mode 100644 drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c > create mode 100644 drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.h > create mode 100644 drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c > create mode 100644 drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.h > create mode 100644 drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c > create mode 100644 drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.h > > -- > 2.17.1 > > ___ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH V3 0/3] drm: replace magic numbers
> -Original Message- > From: amd-gfx On Behalf Of > Bjorn Helgaas > Sent: Tuesday, November 12, 2019 12:35 PM > To: Deucher, Alexander ; Koenig, Christian > ; Zhou, David(ChunMing) > ; David Airlie ; Daniel Vetter > > Cc: Frederick Lawler ; linux-...@vger.kernel.org; > Michel Dänzer ; linux-ker...@vger.kernel.org; dri- > de...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org; Bjorn Helgaas > ; Ilia Mirkin > Subject: [PATCH V3 0/3] drm: replace magic numbers > > From: Bjorn Helgaas > > amdgpu and radeon do a bit of mucking with the PCIe Link Control 2 register, > some of it using hard-coded magic numbers. The idea here is to replace > those with #defines. > > Since v2: > - Fix a gpu_cfg2 case in amdgpu/si.c that I had missed > - Separate out the functional changes for better bisection (thanks, > Michel!) > - Add #defines in a patch by themselves (so a GPU revert wouldn't break > other potential users) > - Squash all the magic number -> #define changes into one patch > > Since v1: > - Add my signed-off-by and Alex's reviewed-by. > Series is: Reviewed-by: Alex Deucher I'm happy to have it go through whatever tree is easiest for you. Thanks, Alex > Bjorn Helgaas (3): > PCI: Add #defines for Enter Compliance, Transmit Margin > drm: correct Transmit Margin masks > drm: replace numbers with PCI_EXP_LNKCTL2 definitions > > drivers/gpu/drm/amd/amdgpu/cik.c | 22 ++ > drivers/gpu/drm/amd/amdgpu/si.c | 22 ++ > drivers/gpu/drm/radeon/cik.c | 22 ++ > drivers/gpu/drm/radeon/si.c | 22 ++ > include/uapi/linux/pci_regs.h| 2 ++ > 5 files changed, 58 insertions(+), 32 deletions(-) > > -- > 2.24.0.rc1.363.gb1bccd3e3d-goog > > ___ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu: Fix the null pointer issue for tdr
I was able to reproduce the crash by using the attached
simulate_crash.patch - waiting on guilty job to signal in reset work and
artificially rearming the timeout timer just before the check for
!cancel_delayed_work(>work_tdr) in drm_sched_cleanup_jobs -
crash log attached in crash.log. This I think confirms my theory i
described earlier in this thread.
basic_fix.patch handles this by testing whether another timer already
armed ob this scheduler or is there a timeout work in execution right
now (see documentation for work_busy) - obviously this is not a full
solution as this will not protect from races if for example there is
immediate work scheduling such as in drm_sched_fault - so we probably
need to account for this by making drm_sched_cleanup_jobs (at least in
the part where it iterates ring mirror list and frees jobs) and GPU
reset really mutually exclusive and not like now.
Andrey
On 11/11/19 4:11 PM, Christian König wrote:
Hi Emily,
you need to print which scheduler instance is freeing the jobs and
which one is triggering the reset. The TID and PID is completely
meaningless here since we are called from different worker threads and
the TID/PID can change on each call.
Apart from that I will look into this a bit deeper when I have time.
Regards,
Christian.
Am 12.11.19 um 07:02 schrieb Deng, Emily:
Hi Christian,
I add the follow print in function drm_sched_cleanup_jobs. From
the log it shows that only use cancel_delayed_work could not avoid to
free job when the sched is in reset. But don’t know exactly where it
is wrong about the driver. Do you have any suggestion about this?
+ printk("Emily:drm_sched_cleanup_jobs:begin,tid:%lu, pid:%lu\n",
current->tgid, current->pid);
/*
* Don't destroy jobs while the timeout worker is running OR
thread
* is being parked and hence assumed to not touch
ring_mirror_list
*/
if ((sched->timeout != MAX_SCHEDULE_TIMEOUT &&
!cancel_delayed_work(>work_tdr)))
return;
+ printk("Emily:drm_sched_cleanup_jobs,tid:%lu, pid:%lu\n",
current->tgid, current->pid);
Best wishes
Emily Deng
Nov 12 12:58:20 ubuntu-drop-August-2018-rc2-gpu0-vf02 kernel:
[11380.695091] Emily:drm_sched_cleanup_jobs:begin,tid:2262, pid:2262
Nov 12 12:58:20 ubuntu-drop-August-2018-rc2-gpu0-vf02 kernel:
[11380.695104] Emily:drm_sched_cleanup_jobs:begin,tid:2262, pid:2262
Nov 12 12:58:20 ubuntu-drop-August-2018-rc2-gpu0-vf02 kernel:
[11380.695105] Emily:drm_sched_cleanup_jobs,tid:2262, pid:2262
Nov 12 12:58:20 ubuntu-drop-August-2018-rc2-gpu0-vf02 kernel:
[11380.695107] Emily:drm_sched_cleanup_jobs:begin,tid:2262, pid:2262
Nov 12 12:58:20 ubuntu-drop-August-2018-rc2-gpu0-vf02 kernel:
[11380.695107] Emily:drm_sched_cleanup_jobs,tid:2262, pid:2262
Nov 12 12:58:20 ubuntu-drop-August-2018-rc2-gpu0-vf02 kernel:
[11381.222954] [drm:amdgpu_job_timedout [amdgpu]] *ERROR* ring sdma0
timeout, signaled seq=78585, emitted seq=78587
Nov 12 12:58:20 ubuntu-drop-August-2018-rc2-gpu0-vf02 kernel:
[11381.224275] [drm:amdgpu_job_timedout [amdgpu]] *ERROR* Process
information: process pid 0 thread pid 0,
s_job:fe75ab36,tid=15603, pid=15603
Nov 12 12:58:20 ubuntu-drop-August-2018-rc2-gpu0-vf02 kernel:
[11381.225413] amdgpu :00:08.0: GPU reset begin!
Nov 12 12:58:20 ubuntu-drop-August-2018-rc2-gpu0-vf02 kernel:
[11381.225417] Emily:drm_sched_cleanup_jobs:begin,tid:2262, pid:2262
Nov 12 12:58:20 ubuntu-drop-August-2018-rc2-gpu0-vf02 kernel:
[11381.225425] Emily:drm_sched_cleanup_jobs:begin,tid:2262, pid:2262
Nov 12 12:58:20 ubuntu-drop-August-2018-rc2-gpu0-vf02 kernel:
[11381.225425] Emily:drm_sched_cleanup_jobs,tid:2262, pid:2262
Nov 12 12:58:20 ubuntu-drop-August-2018-rc2-gpu0-vf02 kernel:
[11381.225428] Emily:amdgpu_job_free_cb,Process information: process
pid 0 thread pid 0, s_job:fe75ab36, tid:2262, pid:2262
Nov 12 12:58:20 ubuntu-drop-August-2018-rc2-gpu0-vf02 kernel:
[11381.225429] Emily:drm_sched_cleanup_jobs:begin,tid:2262, pid:2262
Nov 12 12:58:20 ubuntu-drop-August-2018-rc2-gpu0-vf02 kernel:
[11381.225430] Emily:drm_sched_cleanup_jobs,tid:2262, pid:2262
Nov 12 12:58:20 ubuntu-drop-August-2018-rc2-gpu0-vf02 kernel:
[11381.225473] Emily:drm_sched_cleanup_jobs:begin,tid:2253, pid:2253
Nov 12 12:58:20 ubuntu-drop-August-2018-rc2-gpu0-vf02 kernel:
[11381.225486] Emily:drm_sched_cleanup_jobs:begin,tid:2262, pid:2262
Nov 12 12:58:20 ubuntu-drop-August-2018-rc2-gpu0-vf02 kernel:
[11381.225489] Emily:drm_sched_cleanup_jobs,tid:2262, pid:2262
Nov 12 12:58:20 ubuntu-drop-August-2018-rc2-gpu0-vf02 kernel:
[11381.225494] Emily:amdgpu_job_free_cb,Process information: process
pid 0 thread pid 0, s_job:f086ec84, tid:2262, pid:2262
>-Original Message-
>From: Grodzovsky, Andrey
>Sent: Tuesday, November 12, 2019 11:28 AM
>To: Koenig, Christian ; Deng, Emily
>; amd-gfx@lists.freedesktop.org
>Subject: Re: [PATCH] drm/amdgpu: Fix the null pointer issue for tdr
>
[PATCH 00/21] Separate JPEG from VCN
From JPEG2.0, JPEG is a separated IP block, and has it own PG/CG, and power management. It doesn't require FW, so indepedent from FW loading as well. Patch 1-4: Separate JPEG1.0 from SW wise, since JPEG1.0 is still combined with VCN1.0 esp. in power management; Patch 5-8: Separate JPEG2.0 as an independent IP; Patch 9-10: Add JPEG2.0 with PG and CG; Patch 11-15: Add power management for JPEG of Navi1x and Renoir; Patch 16: Enable JPEG2.0 DPM; Patch 17-18: Enable JPEG2.0; Patch 19: Separate JPEG2.5 from VCN2.5; Patch 20: Add CG for VCN2.5 and JPEG2.5; Patch 21: Enable JPEG2.5 Leo Liu (21): drm/amdgpu: add JPEG HW IP and SW structures drm/amdgpu: add amdgpu_jpeg and JPEG tests drm/amdgpu: separate JPEG1.0 code out from VCN1.0 drm/amdgpu: use the JPEG structure for general driver support drm/amdgpu: add JPEG IP block type drm/amdgpu: add JPEG common functions to amdgpu_jpeg drm/amdgpu: add JPEG v2.0 function supports drm/amdgpu: remove unnecessary JPEG2.0 code from VCN2.0 drm/amdgpu: add JPEG PG and CG interface drm/amdgpu: add PG and CG for JPEG2.0 drm/amd/powerplay: add JPEG Powerplay interface drm/amd/powerplay: add JPEG power control for Navi1x drm/amd/powerplay: add Powergate JPEG for Renoir drm/amd/powerplay: add JPEG power control for Renoir drm/amd/powerplay: set JPEG to SMU dpm drm/amdgpu: enable JPEG2.0 dpm drm/amdgpu: add driver support for JPEG2.0 and above drm/amdgpu: enable JPEG2.0 for Navi1x and Renoir drm/amdgpu: move JPEG2.5 out from VCN2.5 drm/amdgpu: enable Arcturus CG for VCN and JPEG blocks drm/amdgpu: enable Arcturus JPEG2.5 block drivers/gpu/drm/amd/amdgpu/Makefile | 8 +- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 5 + drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 4 +- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c | 215 + drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h | 62 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 15 +- drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c| 8 + drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h| 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 113 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 5 - drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c| 584 + drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.h| 32 + drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c| 827 ++ drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.h| 42 + drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c| 641 ++ drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.h| 29 + drivers/gpu/drm/amd/amdgpu/nv.c | 11 +- drivers/gpu/drm/amd/amdgpu/soc15.c| 10 +- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 481 +- drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 496 +-- drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h | 13 - drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 246 +- drivers/gpu/drm/amd/include/amd_shared.h | 5 +- drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 5 + .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h| 3 + drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h | 2 + drivers/gpu/drm/amd/powerplay/navi10_ppt.c| 32 +- drivers/gpu/drm/amd/powerplay/renoir_ppt.c| 27 + drivers/gpu/drm/amd/powerplay/smu_internal.h | 4 + drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 11 + 31 files changed, 2593 insertions(+), 1346 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h create mode 100644 drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c create mode 100644 drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.h create mode 100644 drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c create mode 100644 drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.h create mode 100644 drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c create mode 100644 drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.h -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 19/21] drm/amdgpu: move JPEG2.5 out from VCN2.5
And clean up the duplicated stuff
Signed-off-by: Leo Liu
---
drivers/gpu/drm/amd/amdgpu/Makefile | 3 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h | 3 +
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 105
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 5 -
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c | 641 +++
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.h | 29 +
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c| 236 -
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h| 13 -
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c| 246 +
9 files changed, 679 insertions(+), 602 deletions(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.h
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
b/drivers/gpu/drm/amd/amdgpu/Makefile
index d40af6519356..83ee1c676e3a 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -155,7 +155,8 @@ amdgpu-y += \
vcn_v2_5.o \
amdgpu_jpeg.o \
jpeg_v1_0.o \
- jpeg_v2_0.o
+ jpeg_v2_0.o \
+ jpeg_v2_5.o
# add ATHUB block
amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h
index 5e2e06ec13df..5131a0a1bc8a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h
@@ -26,6 +26,9 @@
#define AMDGPU_MAX_JPEG_INSTANCES 2
+#define AMDGPU_JPEG_HARVEST_JPEG0 (1 << 0)
+#define AMDGPU_JPEG_HARVEST_JPEG1 (1 << 1)
+
struct amdgpu_jpeg_reg{
unsigned jpeg_pitch;
};
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 6b6c8f8efaff..6995461a5413 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -704,108 +704,3 @@ int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring,
long timeout)
amdgpu_bo_unref();
return r;
}
-
-int amdgpu_vcn_jpeg_ring_test_ring(struct amdgpu_ring *ring)
-{
- struct amdgpu_device *adev = ring->adev;
- uint32_t tmp = 0;
- unsigned i;
- int r;
-
- WREG32(adev->vcn.inst[ring->me].external.jpeg_pitch, 0xCAFEDEAD);
- r = amdgpu_ring_alloc(ring, 3);
- if (r)
- return r;
-
- amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.jpeg_pitch, 0));
- amdgpu_ring_write(ring, 0xDEADBEEF);
- amdgpu_ring_commit(ring);
-
- for (i = 0; i < adev->usec_timeout; i++) {
- tmp = RREG32(adev->vcn.inst[ring->me].external.jpeg_pitch);
- if (tmp == 0xDEADBEEF)
- break;
- udelay(1);
- }
-
- if (i >= adev->usec_timeout)
- r = -ETIMEDOUT;
-
- return r;
-}
-
-static int amdgpu_vcn_jpeg_set_reg(struct amdgpu_ring *ring, uint32_t handle,
- struct dma_fence **fence)
-{
- struct amdgpu_device *adev = ring->adev;
- struct amdgpu_job *job;
- struct amdgpu_ib *ib;
- struct dma_fence *f = NULL;
- const unsigned ib_size_dw = 16;
- int i, r;
-
- r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, );
- if (r)
- return r;
-
- ib = >ibs[0];
-
- ib->ptr[0] = PACKETJ(adev->vcn.internal.jpeg_pitch, 0, 0,
PACKETJ_TYPE0);
- ib->ptr[1] = 0xDEADBEEF;
- for (i = 2; i < 16; i += 2) {
- ib->ptr[i] = PACKETJ(0, 0, 0, PACKETJ_TYPE6);
- ib->ptr[i+1] = 0;
- }
- ib->length_dw = 16;
-
- r = amdgpu_job_submit_direct(job, ring, );
- if (r)
- goto err;
-
- if (fence)
- *fence = dma_fence_get(f);
- dma_fence_put(f);
-
- return 0;
-
-err:
- amdgpu_job_free(job);
- return r;
-}
-
-int amdgpu_vcn_jpeg_ring_test_ib(struct amdgpu_ring *ring, long timeout)
-{
- struct amdgpu_device *adev = ring->adev;
- uint32_t tmp = 0;
- unsigned i;
- struct dma_fence *fence = NULL;
- long r = 0;
-
- r = amdgpu_vcn_jpeg_set_reg(ring, 1, );
- if (r)
- goto error;
-
- r = dma_fence_wait_timeout(fence, false, timeout);
- if (r == 0) {
- r = -ETIMEDOUT;
- goto error;
- } else if (r < 0) {
- goto error;
- } else {
- r = 0;
- }
-
- for (i = 0; i < adev->usec_timeout; i++) {
- tmp = RREG32(adev->vcn.inst[ring->me].external.jpeg_pitch);
- if (tmp == 0xDEADBEEF)
- break;
- udelay(1);
- }
-
- if (i >= adev->usec_timeout)
- r = -ETIMEDOUT;
-
- dma_fence_put(fence);
-error:
- return r;
-}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index dface275c81a..402a5046b985 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -158,7 +158,6 @@ struct
[PATCH 16/21] drm/amdgpu: enable JPEG2.0 dpm
By using its own enabling function
Signed-off-by: Leo Liu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 8
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h | 1 +
drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 10 +-
3 files changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index f205f56e3358..b7150171e8d7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -2718,6 +2718,14 @@ void amdgpu_pm_print_power_states(struct amdgpu_device
*adev)
}
+void amdgpu_dpm_enable_jpeg(struct amdgpu_device *adev, bool enable)
+{
+ int ret = smu_dpm_set_power_gate(>smu, AMD_IP_BLOCK_TYPE_JPEG,
enable);
+ if (ret)
+ DRM_ERROR("[SW SMU]: dpm enable jpeg failed, state = %s, ret =
%d. \n",
+ enable ? "true" : "false", ret);
+}
+
int amdgpu_pm_virt_sysfs_init(struct amdgpu_device *adev)
{
int ret = 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h
index ef31448ee8d8..3da1da277805 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h
@@ -41,5 +41,6 @@ void amdgpu_pm_compute_clocks(struct amdgpu_device *adev);
void amdgpu_dpm_thermal_work_handler(struct work_struct *work);
void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable);
void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable);
+void amdgpu_dpm_enable_jpeg(struct amdgpu_device *adev, bool enable);
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
index 3869730b2331..a78292d84854 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
@@ -333,6 +333,9 @@ static int jpeg_v2_0_start(struct amdgpu_device *adev)
struct amdgpu_ring *ring = >jpeg.inst->ring_dec;
int r;
+ if (adev->pm.dpm_enabled)
+ amdgpu_dpm_enable_jpeg(adev, true);
+
/* disable power gating */
r = jpeg_v2_0_disable_power_gating(adev);
if (r)
@@ -388,8 +391,13 @@ static int jpeg_v2_0_stop(struct amdgpu_device *adev)
/* enable power gating */
r = jpeg_v2_0_enable_power_gating(adev);
+ if (r)
+ return r;
- return r;
+ if (adev->pm.dpm_enabled)
+ amdgpu_dpm_enable_jpeg(adev, false);
+
+ return 0;
}
/**
--
2.17.1
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[PATCH 21/21] drm/amdgpu: enable Arcturus JPEG2.5 block
It also doen't care about FW loading type, so enabling it directly. Signed-off-by: Leo Liu --- drivers/gpu/drm/amd/amdgpu/soc15.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index b404b7a6e593..689ffa6ede57 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -69,6 +69,7 @@ #include "vcn_v2_0.h" #include "jpeg_v2_0.h" #include "vcn_v2_5.h" +#include "jpeg_v2_5.h" #include "dce_virtual.h" #include "mxgpu_ai.h" #include "amdgpu_smu.h" @@ -804,6 +805,7 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev) if (unlikely(adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT)) amdgpu_device_ip_block_add(adev, _v2_5_ip_block); + amdgpu_device_ip_block_add(adev, _v2_5_ip_block); break; case CHIP_RENOIR: amdgpu_device_ip_block_add(adev, _common_ip_block); -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 14/21] drm/amd/powerplay: add JPEG power control for Renoir
By using its own JPEG PowerUp and PowerDown messages
Signed-off-by: Leo Liu
---
drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index 492a201554e8..f561fb9cc951 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -301,6 +301,31 @@ static int renoir_dpm_set_uvd_enable(struct smu_context
*smu, bool enable)
return ret;
}
+static int renoir_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
+{
+ struct smu_power_context *smu_power = >smu_power;
+ struct smu_power_gate *power_gate = _power->power_gate;
+ int ret = 0;
+
+ if (enable) {
+ if (smu_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
+ ret = smu_send_smc_msg_with_param(smu,
SMU_MSG_PowerUpJpeg, 0);
+ if (ret)
+ return ret;
+ }
+ power_gate->jpeg_gated = false;
+ } else {
+ if (smu_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
+ ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownJpeg);
+ if (ret)
+ return ret;
+ }
+ power_gate->jpeg_gated = true;
+ }
+
+ return ret;
+}
+
static int renoir_force_dpm_limit_value(struct smu_context *smu, bool highest)
{
int ret = 0, i = 0;
@@ -683,6 +708,7 @@ static const struct pptable_funcs renoir_ppt_funcs = {
.print_clk_levels = renoir_print_clk_levels,
.get_current_power_state = renoir_get_current_power_state,
.dpm_set_uvd_enable = renoir_dpm_set_uvd_enable,
+ .dpm_set_jpeg_enable = renoir_dpm_set_jpeg_enable,
.force_dpm_limit_value = renoir_force_dpm_limit_value,
.unforce_dpm_levels = renoir_unforce_dpm_levels,
.get_workload_type = renoir_get_workload_type,
--
2.17.1
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[PATCH 20/21] drm/amdgpu: enable Arcturus CG for VCN and JPEG blocks
Arcturus VCN and JPEG only got CG support, and no PG support Signed-off-by: Leo Liu --- drivers/gpu/drm/amd/amdgpu/soc15.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index f3977abbd1e2..b404b7a6e593 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -1210,7 +1210,9 @@ static int soc15_common_early_init(void *handle) AMD_CG_SUPPORT_SDMA_LS | AMD_CG_SUPPORT_MC_MGCG | AMD_CG_SUPPORT_MC_LS | - AMD_CG_SUPPORT_IH_CG; + AMD_CG_SUPPORT_IH_CG | + AMD_CG_SUPPORT_VCN_MGCG | + AMD_CG_SUPPORT_JPEG_MGCG; adev->pg_flags = 0; adev->external_rev_id = adev->rev_id + 0x32; break; -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 18/21] drm/amdgpu: enable JPEG2.0 for Navi1x and Renoir
By adding JPEG IP block to the family Signed-off-by: Leo Liu --- drivers/gpu/drm/amd/amdgpu/nv.c| 3 +++ drivers/gpu/drm/amd/amdgpu/soc15.c | 2 ++ 2 files changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index 7c1068efe651..d2989e9484bd 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c @@ -52,6 +52,7 @@ #include "gfx_v10_0.h" #include "sdma_v5_0.h" #include "vcn_v2_0.h" +#include "jpeg_v2_0.h" #include "dce_virtual.h" #include "mes_v10_1.h" #include "mxgpu_nv.h" @@ -456,6 +457,7 @@ int nv_set_ip_blocks(struct amdgpu_device *adev) is_support_sw_smu(adev) && !amdgpu_sriov_vf(adev)) amdgpu_device_ip_block_add(adev, _v11_0_ip_block); amdgpu_device_ip_block_add(adev, _v2_0_ip_block); + amdgpu_device_ip_block_add(adev, _v2_0_ip_block); if (adev->enable_mes) amdgpu_device_ip_block_add(adev, _v10_1_ip_block); break; @@ -479,6 +481,7 @@ int nv_set_ip_blocks(struct amdgpu_device *adev) is_support_sw_smu(adev) && !amdgpu_sriov_vf(adev)) amdgpu_device_ip_block_add(adev, _v11_0_ip_block); amdgpu_device_ip_block_add(adev, _v2_0_ip_block); + amdgpu_device_ip_block_add(adev, _v2_0_ip_block); break; default: return -EINVAL; diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index 0c36cb784009..f3977abbd1e2 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -67,6 +67,7 @@ #include "vce_v4_0.h" #include "vcn_v1_0.h" #include "vcn_v2_0.h" +#include "jpeg_v2_0.h" #include "vcn_v2_5.h" #include "dce_virtual.h" #include "mxgpu_ai.h" @@ -821,6 +822,7 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev) amdgpu_device_ip_block_add(adev, _ip_block); #endif amdgpu_device_ip_block_add(adev, _v2_0_ip_block); + amdgpu_device_ip_block_add(adev, _v2_0_ip_block); break; default: return -EINVAL; -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 07/21] drm/amdgpu: add JPEG v2.0 function supports
It got separated from VCN2.0 with a new jpeg_v2_0_ip_block
Signed-off-by: Leo Liu
---
drivers/gpu/drm/amd/amdgpu/Makefile| 3 +-
drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 809 +
drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.h | 42 ++
3 files changed, 853 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.h
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
b/drivers/gpu/drm/amd/amdgpu/Makefile
index 2936c292379d..d40af6519356 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -154,7 +154,8 @@ amdgpu-y += \
vcn_v2_0.o \
vcn_v2_5.o \
amdgpu_jpeg.o \
- jpeg_v1_0.o
+ jpeg_v1_0.o \
+ jpeg_v2_0.o
# add ATHUB block
amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
new file mode 100644
index ..4143ef6905b8
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
@@ -0,0 +1,809 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include "amdgpu.h"
+#include "amdgpu_jpeg.h"
+#include "amdgpu_pm.h"
+#include "soc15.h"
+#include "soc15d.h"
+
+#include "vcn/vcn_2_0_0_offset.h"
+#include "vcn/vcn_2_0_0_sh_mask.h"
+#include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"
+
+#define mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET0x1bfff
+#define mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET 0x4029
+#define mmUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET 0x402a
+#define mmUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET 0x402b
+#define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET 0x40ea
+#define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET0x40eb
+#define mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET 0x40cf
+#define mmUVD_LMI_JPEG_VMID_INTERNAL_OFFSET0x40d1
+#define mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET0x40e8
+#define mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x40e9
+#define mmUVD_JRBC_IB_SIZE_INTERNAL_OFFSET 0x4082
+#define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET 0x40ec
+#define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET0x40ed
+#define mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET0x4085
+#define mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET 0x4084
+#define mmUVD_JRBC_STATUS_INTERNAL_OFFSET 0x4089
+#define mmUVD_JPEG_PITCH_INTERNAL_OFFSET 0x401f
+
+#define JRBC_DEC_EXTERNAL_REG_WRITE_ADDR 0x18000
+
+static void jpeg_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev);
+static void jpeg_v2_0_set_irq_funcs(struct amdgpu_device *adev);
+static int jpeg_v2_0_set_powergating_state(void *handle,
+ enum amd_powergating_state state);
+
+/**
+ * jpeg_v2_0_early_init - set function pointers
+ *
+ * @handle: amdgpu_device pointer
+ *
+ * Set ring and irq function pointers
+ */
+static int jpeg_v2_0_early_init(void *handle)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+ adev->jpeg.num_jpeg_inst = 1;
+
+ jpeg_v2_0_set_dec_ring_funcs(adev);
+ jpeg_v2_0_set_irq_funcs(adev);
+
+ return 0;
+}
+
+/**
+ * jpeg_v2_0_sw_init - sw init for JPEG block
+ *
+ * @handle: amdgpu_device pointer
+ *
+ * Load firmware and sw initialization
+ */
+static int jpeg_v2_0_sw_init(void *handle)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_ring *ring;
+ int r;
+
+ /* JPEG TRAP */
+ r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
+ VCN_2_0__SRCID__JPEG_DECODE,
[PATCH 17/21] drm/amdgpu: add driver support for JPEG2.0 and above
By using JPEG IP block type
Signed-off-by: Leo Liu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c| 9 +++--
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 85c024b74d6d..17be6389adf7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1964,6 +1964,7 @@ static int amdgpu_device_set_cg_state(struct
amdgpu_device *adev,
if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
+ adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG
&&
adev->ip_blocks[i].version->funcs->set_clockgating_state) {
/* enable clockgating to save power */
r =
adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
@@ -1994,6 +1995,7 @@ static int amdgpu_device_set_pg_state(struct
amdgpu_device *adev, enum amd_power
if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
+ adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG
&&
adev->ip_blocks[i].version->funcs->set_powergating_state) {
/* enable powergating to save power */
r =
adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 4a4085ec53e0..6c775a65a206 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -400,7 +400,9 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
ib_size_alignment = 1;
break;
case AMDGPU_HW_IP_VCN_JPEG:
- type = AMD_IP_BLOCK_TYPE_VCN;
+ type = (amdgpu_device_ip_get_ip_block(adev,
AMD_IP_BLOCK_TYPE_JPEG)) ?
+ AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
+
for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
if (adev->jpeg.harvest_config & (1 << i))
continue;
@@ -521,9 +523,12 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void
*data, struct drm_file
break;
case AMDGPU_HW_IP_VCN_DEC:
case AMDGPU_HW_IP_VCN_ENC:
- case AMDGPU_HW_IP_VCN_JPEG:
type = AMD_IP_BLOCK_TYPE_VCN;
break;
+ case AMDGPU_HW_IP_VCN_JPEG:
+ type = (amdgpu_device_ip_get_ip_block(adev,
AMD_IP_BLOCK_TYPE_JPEG)) ?
+ AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
+ break;
default:
return -EINVAL;
}
--
2.17.1
___
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[PATCH 13/21] drm/amd/powerplay: add Powergate JPEG for Renoir
Similar to SDMA, VCN etc.
Signed-off-by: Leo Liu
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 2 ++
drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h | 2 ++
drivers/gpu/drm/amd/powerplay/renoir_ppt.c| 1 +
drivers/gpu/drm/amd/powerplay/smu_internal.h | 2 ++
drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 11 +++
5 files changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 69243a858dd5..211934521d37 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -1229,6 +1229,7 @@ static int smu_hw_init(void *handle)
if (adev->flags & AMD_IS_APU) {
smu_powergate_sdma(>smu, false);
smu_powergate_vcn(>smu, false);
+ smu_powergate_jpeg(>smu, false);
smu_set_gfx_cgpg(>smu, true);
}
@@ -1287,6 +1288,7 @@ static int smu_hw_fini(void *handle)
if (adev->flags & AMD_IS_APU) {
smu_powergate_sdma(>smu, true);
smu_powergate_vcn(>smu, true);
+ smu_powergate_jpeg(>smu, true);
}
ret = smu_stop_thermal_control(smu);
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
index 9b9f5df0911c..1745e0146fba 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
@@ -58,6 +58,8 @@ int smu_v12_0_powergate_sdma(struct smu_context *smu, bool
gate);
int smu_v12_0_powergate_vcn(struct smu_context *smu, bool gate);
+int smu_v12_0_powergate_jpeg(struct smu_context *smu, bool gate);
+
int smu_v12_0_set_gfx_cgpg(struct smu_context *smu, bool enable);
uint32_t smu_v12_0_get_gfxoff_status(struct smu_context *smu);
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index 04daf7e9fe05..492a201554e8 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -697,6 +697,7 @@ static const struct pptable_funcs renoir_ppt_funcs = {
.check_fw_version = smu_v12_0_check_fw_version,
.powergate_sdma = smu_v12_0_powergate_sdma,
.powergate_vcn = smu_v12_0_powergate_vcn,
+ .powergate_jpeg = smu_v12_0_powergate_jpeg,
.send_smc_msg = smu_v12_0_send_msg,
.send_smc_msg_with_param = smu_v12_0_send_msg_with_param,
.read_smc_arg = smu_v12_0_read_arg,
diff --git a/drivers/gpu/drm/amd/powerplay/smu_internal.h
b/drivers/gpu/drm/amd/powerplay/smu_internal.h
index 8bcda7871309..70c4d66721cd 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_internal.h
+++ b/drivers/gpu/drm/amd/powerplay/smu_internal.h
@@ -42,6 +42,8 @@
((smu)->ppt_funcs->powergate_sdma ?
(smu)->ppt_funcs->powergate_sdma((smu), (gate)) : 0)
#define smu_powergate_vcn(smu, gate) \
((smu)->ppt_funcs->powergate_vcn ?
(smu)->ppt_funcs->powergate_vcn((smu), (gate)) : 0)
+#define smu_powergate_jpeg(smu, gate) \
+ ((smu)->ppt_funcs->powergate_jpeg ?
(smu)->ppt_funcs->powergate_jpeg((smu), (gate)) : 0)
#define smu_get_vbios_bootup_values(smu) \
((smu)->ppt_funcs->get_vbios_bootup_values ?
(smu)->ppt_funcs->get_vbios_bootup_values((smu)) : 0)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
index 139dd737eaa5..f5d87110ec34 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
@@ -203,6 +203,17 @@ int smu_v12_0_powergate_vcn(struct smu_context *smu, bool
gate)
return smu_send_smc_msg(smu, SMU_MSG_PowerUpVcn);
}
+int smu_v12_0_powergate_jpeg(struct smu_context *smu, bool gate)
+{
+ if (!(smu->adev->flags & AMD_IS_APU))
+ return 0;
+
+ if (gate)
+ return smu_send_smc_msg(smu, SMU_MSG_PowerDownJpeg);
+ else
+ return smu_send_smc_msg(smu, SMU_MSG_PowerUpJpeg);
+}
+
int smu_v12_0_set_gfx_cgpg(struct smu_context *smu, bool enable)
{
if (!(smu->adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
--
2.17.1
___
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[PATCH 09/21] drm/amdgpu: add JPEG PG and CG interface
From JPEG2.0, it will use its own PG/CG
Signed-off-by: Leo Liu
---
drivers/gpu/drm/amd/include/amd_shared.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/amd_shared.h
b/drivers/gpu/drm/amd/include/amd_shared.h
index d5bc8be4d70c..d655a76bedc6 100644
--- a/drivers/gpu/drm/amd/include/amd_shared.h
+++ b/drivers/gpu/drm/amd/include/amd_shared.h
@@ -100,6 +100,7 @@ enum amd_powergating_state {
#define AMD_CG_SUPPORT_IH_CG (1 << 27)
#define AMD_CG_SUPPORT_ATHUB_LS(1 << 28)
#define AMD_CG_SUPPORT_ATHUB_MGCG (1 << 29)
+#define AMD_CG_SUPPORT_JPEG_MGCG (1 << 30)
/* PG flags */
#define AMD_PG_SUPPORT_GFX_PG (1 << 0)
#define AMD_PG_SUPPORT_GFX_SMG (1 << 1)
@@ -118,6 +119,7 @@ enum amd_powergating_state {
#define AMD_PG_SUPPORT_VCN (1 << 14)
#define AMD_PG_SUPPORT_VCN_DPG (1 << 15)
#define AMD_PG_SUPPORT_ATHUB (1 << 16)
+#define AMD_PG_SUPPORT_JPEG(1 << 17)
enum PP_FEATURE_MASK {
PP_SCLK_DPM_MASK = 0x1,
--
2.17.1
___
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[PATCH 15/21] drm/amd/powerplay: set JPEG to SMU dpm
By using its own IP block type. Signed-off-by: Leo Liu --- drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 3 +++ drivers/gpu/drm/amd/powerplay/smu_internal.h | 2 ++ 2 files changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c index 211934521d37..a1453157eefe 100644 --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c @@ -415,6 +415,9 @@ int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type, case AMD_IP_BLOCK_TYPE_SDMA: ret = smu_powergate_sdma(smu, gate); break; + case AMD_IP_BLOCK_TYPE_JPEG: + ret = smu_dpm_set_jpeg_enable(smu, gate); + break; default: break; } diff --git a/drivers/gpu/drm/amd/powerplay/smu_internal.h b/drivers/gpu/drm/amd/powerplay/smu_internal.h index 70c4d66721cd..b2d81d3490cd 100644 --- a/drivers/gpu/drm/amd/powerplay/smu_internal.h +++ b/drivers/gpu/drm/amd/powerplay/smu_internal.h @@ -172,6 +172,8 @@ ((smu)->ppt_funcs->dpm_set_uvd_enable ? (smu)->ppt_funcs->dpm_set_uvd_enable((smu), (enable)) : 0) #define smu_dpm_set_vce_enable(smu, enable) \ ((smu)->ppt_funcs->dpm_set_vce_enable ? (smu)->ppt_funcs->dpm_set_vce_enable((smu), (enable)) : 0) +#define smu_dpm_set_jpeg_enable(smu, enable) \ + ((smu)->ppt_funcs->dpm_set_jpeg_enable ? (smu)->ppt_funcs->dpm_set_jpeg_enable((smu), (enable)) : 0) #define smu_set_watermarks_table(smu, tab, clock_ranges) \ ((smu)->ppt_funcs->set_watermarks_table ? (smu)->ppt_funcs->set_watermarks_table((smu), (tab), (clock_ranges)) : 0) -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 06/21] drm/amdgpu: add JPEG common functions to amdgpu_jpeg
They will be used for JPEG2.0 and later.
Signed-off-by: Leo Liu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c | 80
drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h | 10 +++
2 files changed, 90 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c
index d9a547d4d3b2..51f98ab90d7f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c
@@ -26,9 +26,89 @@
#include "amdgpu.h"
#include "amdgpu_jpeg.h"
+#include "amdgpu_pm.h"
#include "soc15d.h"
#include "soc15_common.h"
+#define JPEG_IDLE_TIMEOUT msecs_to_jiffies(1000)
+
+static void amdgpu_jpeg_idle_work_handler(struct work_struct *work);
+
+int amdgpu_jpeg_sw_init(struct amdgpu_device *adev)
+{
+ INIT_DELAYED_WORK(>jpeg.idle_work, amdgpu_jpeg_idle_work_handler);
+
+ return 0;
+}
+
+int amdgpu_jpeg_sw_fini(struct amdgpu_device *adev)
+{
+ int i;
+
+ cancel_delayed_work_sync(>jpeg.idle_work);
+
+ for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
+ if (adev->jpeg.harvest_config & (1 << i))
+ continue;
+
+ amdgpu_ring_fini(>jpeg.inst[i].ring_dec);
+ }
+
+ return 0;
+}
+
+int amdgpu_jpeg_suspend(struct amdgpu_device *adev)
+{
+ cancel_delayed_work_sync(>jpeg.idle_work);
+
+ return 0;
+}
+
+int amdgpu_jpeg_resume(struct amdgpu_device *adev)
+{
+ return 0;
+}
+
+static void amdgpu_jpeg_idle_work_handler(struct work_struct *work)
+{
+ struct amdgpu_device *adev =
+ container_of(work, struct amdgpu_device, jpeg.idle_work.work);
+ unsigned int fences = 0;
+ unsigned int i;
+
+ for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
+ if (adev->jpeg.harvest_config & (1 << i))
+ continue;
+
+ fences +=
amdgpu_fence_count_emitted(>jpeg.inst[i].ring_dec);
+ }
+
+ if (fences == 0) {
+ amdgpu_gfx_off_ctrl(adev, true);
+ amdgpu_device_ip_set_powergating_state(adev,
AMD_IP_BLOCK_TYPE_JPEG,
+ AMD_PG_STATE_GATE);
+ } else {
+ schedule_delayed_work(>jpeg.idle_work, JPEG_IDLE_TIMEOUT);
+ }
+}
+
+void amdgpu_jpeg_ring_begin_use(struct amdgpu_ring *ring)
+{
+ struct amdgpu_device *adev = ring->adev;
+ bool set_clocks = !cancel_delayed_work_sync(>jpeg.idle_work);
+
+ if (set_clocks) {
+ amdgpu_gfx_off_ctrl(adev, false);
+ amdgpu_device_ip_set_powergating_state(adev,
AMD_IP_BLOCK_TYPE_JPEG,
+ AMD_PG_STATE_UNGATE);
+ }
+}
+
+void amdgpu_jpeg_ring_end_use(struct amdgpu_ring *ring)
+{
+ schedule_delayed_work(>adev->jpeg.idle_work, JPEG_IDLE_TIMEOUT);
+}
+
int amdgpu_jpeg_dec_ring_test_ring(struct amdgpu_ring *ring)
{
struct amdgpu_device *adev = ring->adev;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h
index a8d988c25f45..5e2e06ec13df 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h
@@ -41,8 +41,18 @@ struct amdgpu_jpeg {
struct amdgpu_jpeg_inst inst[AMDGPU_MAX_JPEG_INSTANCES];
struct amdgpu_jpeg_reg internal;
unsigned harvest_config;
+ struct delayed_work idle_work;
+ enum amd_powergating_state cur_state;
};
+int amdgpu_jpeg_sw_init(struct amdgpu_device *adev);
+int amdgpu_jpeg_sw_fini(struct amdgpu_device *adev);
+int amdgpu_jpeg_suspend(struct amdgpu_device *adev);
+int amdgpu_jpeg_resume(struct amdgpu_device *adev);
+
+void amdgpu_jpeg_ring_begin_use(struct amdgpu_ring *ring);
+void amdgpu_jpeg_ring_end_use(struct amdgpu_ring *ring);
+
int amdgpu_jpeg_dec_ring_test_ring(struct amdgpu_ring *ring);
int amdgpu_jpeg_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout);
--
2.17.1
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[PATCH 10/21] drm/amdgpu: add PG and CG for JPEG2.0
And enable them for Navi1x and Renoir
Signed-off-by: Leo Liu
---
drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 62 +++---
drivers/gpu/drm/amd/amdgpu/nv.c| 8 +++-
drivers/gpu/drm/amd/amdgpu/soc15.c | 2 +
3 files changed, 45 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
index 4143ef6905b8..3869730b2331 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
@@ -227,16 +227,18 @@ static int jpeg_v2_0_disable_power_gating(struct
amdgpu_device *adev)
uint32_t data;
int r = 0;
- data = 1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT;
- WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);
-
- SOC15_WAIT_ON_RREG(JPEG, 0,
- mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS_UVDJ_PWR_ON,
- UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK, r);
-
- if (r) {
- DRM_ERROR("amdgpu: JPEG disable power gating failed\n");
- return r;
+ if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) {
+ data = 1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT;
+ WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);
+
+ SOC15_WAIT_ON_RREG(JPEG, 0,
+ mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS_UVDJ_PWR_ON,
+ UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK, r);
+
+ if (r) {
+ DRM_ERROR("amdgpu: JPEG disable power gating failed\n");
+ return r;
+ }
}
/* Removing the anti hang mechanism to indicate the UVDJ tile is ON */
@@ -248,24 +250,26 @@ static int jpeg_v2_0_disable_power_gating(struct
amdgpu_device *adev)
static int jpeg_v2_0_enable_power_gating(struct amdgpu_device* adev)
{
- uint32_t data;
- int r = 0;
+ if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) {
+ uint32_t data;
+ int r = 0;
- data = RREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS));
- data &= ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK;
- data |= 0x1; //UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_TILES_OFF;
- WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), data);
+ data = RREG32(SOC15_REG_OFFSET(JPEG, 0,
mmUVD_JPEG_POWER_STATUS));
+ data &= ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK;
+ data |= 0x1;
//UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_TILES_OFF;
+ WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS),
data);
- data = 2 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT;
- WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);
+ data = 2 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT;
+ WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);
- SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_PGFSM_STATUS,
- (2 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT),
- UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK, r);
+ SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_PGFSM_STATUS,
+ (2 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT),
+ UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK, r);
- if (r) {
- DRM_ERROR("amdgpu: JPEG enable power gating failed\n");
- return r;
+ if (r) {
+ DRM_ERROR("amdgpu: JPEG enable power gating failed\n");
+ return r;
+ }
}
return 0;
@@ -276,7 +280,10 @@ static void jpeg_v2_0_disable_clock_gating(struct
amdgpu_device* adev)
uint32_t data;
data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL);
- data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
+ if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG)
+ data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
+ else
+ data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
@@ -296,7 +303,10 @@ static void jpeg_v2_0_enable_clock_gating(struct
amdgpu_device* adev)
uint32_t data;
data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL);
- data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
+ if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG)
+ data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
+ else
+ data |= 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index af68f9815f28..7c1068efe651 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -636,10 +636,12 @@ static int nv_common_early_init(void *handle)
[PATCH 12/21] drm/amd/powerplay: add JPEG power control for Navi1x
By separating the JPEG power feature, and using its
own PowerUp and PowerDown messages
Signed-off-by: Leo Liu
---
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 32 --
1 file changed, 30 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index aeb9c1e341c7..760568debe6c 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -384,8 +384,10 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN)
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT)
- | FEATURE_MASK(FEATURE_JPEG_PG_BIT);
+ *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT);
+
+ if (smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
+ *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_JPEG_PG_BIT);
/* disable DPM UCLK and DS SOCCLK on navi10 A0 secure board */
if (is_asic_secure(smu)) {
@@ -665,6 +667,31 @@ static int navi10_dpm_set_uvd_enable(struct smu_context
*smu, bool enable)
return ret;
}
+static int navi10_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
+{
+ struct smu_power_context *smu_power = >smu_power;
+ struct smu_power_gate *power_gate = _power->power_gate;
+ int ret = 0;
+
+ if (enable) {
+ if (smu_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
+ ret = smu_send_smc_msg_with_param(smu,
SMU_MSG_PowerUpJpeg, 1);
+ if (ret)
+ return ret;
+ }
+ power_gate->jpeg_gated = false;
+ } else {
+ if (smu_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
+ ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownJpeg);
+ if (ret)
+ return ret;
+ }
+ power_gate->jpeg_gated = true;
+ }
+
+ return ret;
+}
+
static int navi10_get_current_clk_freq_by_table(struct smu_context *smu,
enum smu_clk_type clk_type,
uint32_t *value)
@@ -1996,6 +2023,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
.get_allowed_feature_mask = navi10_get_allowed_feature_mask,
.set_default_dpm_table = navi10_set_default_dpm_table,
.dpm_set_uvd_enable = navi10_dpm_set_uvd_enable,
+ .dpm_set_jpeg_enable = navi10_dpm_set_jpeg_enable,
.get_current_clk_freq_by_table = navi10_get_current_clk_freq_by_table,
.print_clk_levels = navi10_print_clk_levels,
.force_clk_levels = navi10_force_clk_levels,
--
2.17.1
___
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[PATCH 05/21] drm/amdgpu: add JPEG IP block type
From VCN2.0, JPEG2.0 is a separated IP block.
Signed-off-by: Leo Liu
---
drivers/gpu/drm/amd/include/amd_shared.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/include/amd_shared.h
b/drivers/gpu/drm/amd/include/amd_shared.h
index dc7eb28f0296..d5bc8be4d70c 100644
--- a/drivers/gpu/drm/amd/include/amd_shared.h
+++ b/drivers/gpu/drm/amd/include/amd_shared.h
@@ -53,7 +53,8 @@ enum amd_ip_block_type {
AMD_IP_BLOCK_TYPE_VCE,
AMD_IP_BLOCK_TYPE_ACP,
AMD_IP_BLOCK_TYPE_VCN,
- AMD_IP_BLOCK_TYPE_MES
+ AMD_IP_BLOCK_TYPE_MES,
+ AMD_IP_BLOCK_TYPE_JPEG
};
enum amd_clockgating_state {
--
2.17.1
___
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[PATCH 11/21] drm/amd/powerplay: add JPEG Powerplay interface
It will be used for different SMU specific to HW
Signed-off-by: Leo Liu
---
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 999445c5c010..cdd46cdaffb8 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -282,6 +282,7 @@ struct smu_power_gate {
bool uvd_gated;
bool vce_gated;
bool vcn_gated;
+ bool jpeg_gated;
};
struct smu_power_context {
@@ -435,6 +436,7 @@ struct pptable_funcs {
int (*set_power_profile_mode)(struct smu_context *smu, long *input,
uint32_t size);
int (*dpm_set_uvd_enable)(struct smu_context *smu, bool enable);
int (*dpm_set_vce_enable)(struct smu_context *smu, bool enable);
+ int (*dpm_set_jpeg_enable)(struct smu_context *smu, bool enable);
int (*read_sensor)(struct smu_context *smu, enum amd_pp_sensors sensor,
void *data, uint32_t *size);
int (*pre_display_config_changed)(struct smu_context *smu);
@@ -489,6 +491,7 @@ struct pptable_funcs {
int (*check_fw_version)(struct smu_context *smu);
int (*powergate_sdma)(struct smu_context *smu, bool gate);
int (*powergate_vcn)(struct smu_context *smu, bool gate);
+ int (*powergate_jpeg)(struct smu_context *smu, bool gate);
int (*set_gfx_cgpg)(struct smu_context *smu, bool enable);
int (*write_pptable)(struct smu_context *smu);
int (*set_min_dcef_deep_sleep)(struct smu_context *smu);
--
2.17.1
___
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[PATCH 03/21] drm/amdgpu: separate JPEG1.0 code out from VCN1.0
For VCN1.0, the separation is just in code wise, JPEG1.0 HW is still
included in the VCN1.0 HW.
Signed-off-by: Leo Liu
---
drivers/gpu/drm/amd/amdgpu/Makefile| 3 +-
drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c | 584 +
drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.h | 32 ++
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 481 +---
4 files changed, 630 insertions(+), 470 deletions(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.h
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
b/drivers/gpu/drm/amd/amdgpu/Makefile
index 11ca70105eeb..2936c292379d 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -153,7 +153,8 @@ amdgpu-y += \
vcn_v1_0.o \
vcn_v2_0.o \
vcn_v2_5.o \
- amdgpu_jpeg.o
+ amdgpu_jpeg.o \
+ jpeg_v1_0.o
# add ATHUB block
amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c
b/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c
new file mode 100644
index ..553506df077d
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c
@@ -0,0 +1,584 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include "amdgpu.h"
+#include "amdgpu_jpeg.h"
+#include "soc15.h"
+#include "soc15d.h"
+
+#include "vcn/vcn_1_0_offset.h"
+#include "vcn/vcn_1_0_sh_mask.h"
+
+static void jpeg_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev);
+static void jpeg_v1_0_set_irq_funcs(struct amdgpu_device *adev);
+
+static void jpeg_v1_0_decode_ring_patch_wreg(struct amdgpu_ring *ring,
uint32_t *ptr, uint32_t reg_offset, uint32_t val)
+{
+ struct amdgpu_device *adev = ring->adev;
+ ring->ring[(*ptr)++] = PACKETJ(SOC15_REG_OFFSET(JPEG, 0,
mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0);
+ if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) ||
+ ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) {
+ ring->ring[(*ptr)++] = 0;
+ ring->ring[(*ptr)++] = PACKETJ((reg_offset >> 2), 0, 0,
PACKETJ_TYPE0);
+ } else {
+ ring->ring[(*ptr)++] = reg_offset;
+ ring->ring[(*ptr)++] = PACKETJ(0, 0, 0, PACKETJ_TYPE0);
+ }
+ ring->ring[(*ptr)++] = val;
+}
+
+static void jpeg_v1_0_decode_ring_set_patch_ring(struct amdgpu_ring *ring,
uint32_t ptr)
+{
+ struct amdgpu_device *adev = ring->adev;
+
+ uint32_t reg, reg_offset, val, mask, i;
+
+ // 1st: program mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW
+ reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW);
+ reg_offset = (reg << 2);
+ val = lower_32_bits(ring->gpu_addr);
+ jpeg_v1_0_decode_ring_patch_wreg(ring, , reg_offset, val);
+
+ // 2nd: program mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH
+ reg = SOC15_REG_OFFSET(JPEG, 0,
mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH);
+ reg_offset = (reg << 2);
+ val = upper_32_bits(ring->gpu_addr);
+ jpeg_v1_0_decode_ring_patch_wreg(ring, , reg_offset, val);
+
+ // 3rd to 5th: issue MEM_READ commands
+ for (i = 0; i <= 2; i++) {
+ ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE2);
+ ring->ring[ptr++] = 0;
+ }
+
+ // 6th: program mmUVD_JRBC_RB_CNTL register to enable NO_FETCH and RPTR
write ability
+ reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_CNTL);
+ reg_offset = (reg << 2);
+ val = 0x13;
+ jpeg_v1_0_decode_ring_patch_wreg(ring, , reg_offset, val);
+
+ // 7th: program mmUVD_JRBC_RB_REF_DATA
+ reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_REF_DATA);
+ reg_offset = (reg << 2);
+ val = 0x1;
+ jpeg_v1_0_decode_ring_patch_wreg(ring, , reg_offset, val);
+
+ // 8th: issue conditional register read mmUVD_JRBC_RB_CNTL
+ reg = SOC15_REG_OFFSET(JPEG, 0,
[PATCH 08/21] drm/amdgpu: remove unnecessary JPEG2.0 code from VCN2.0
They are no longer needed, using from JPEG2.0 instead.
Signed-off-by: Leo Liu
---
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 260 +-
1 file changed, 3 insertions(+), 257 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index 38f787a560cb..ded0ab574f4e 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -74,7 +74,6 @@
static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev);
static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev);
-static void vcn_v2_0_set_jpeg_ring_funcs(struct amdgpu_device *adev);
static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev);
static int vcn_v2_0_set_powergating_state(void *handle,
enum amd_powergating_state state);
@@ -97,7 +96,6 @@ static int vcn_v2_0_early_init(void *handle)
vcn_v2_0_set_dec_ring_funcs(adev);
vcn_v2_0_set_enc_ring_funcs(adev);
- vcn_v2_0_set_jpeg_ring_funcs(adev);
vcn_v2_0_set_irq_funcs(adev);
return 0;
@@ -132,12 +130,6 @@ static int vcn_v2_0_sw_init(void *handle)
return r;
}
- /* VCN JPEG TRAP */
- r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
- VCN_2_0__SRCID__JPEG_DECODE,
>vcn.inst->irq);
- if (r)
- return r;
-
r = amdgpu_vcn_sw_init(adev);
if (r)
return r;
@@ -194,19 +186,8 @@ static int vcn_v2_0_sw_init(void *handle)
return r;
}
- ring = >vcn.inst->ring_jpeg;
- ring->use_doorbell = true;
- ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1;
- sprintf(ring->name, "vcn_jpeg");
- r = amdgpu_ring_init(adev, ring, 512, >vcn.inst->irq, 0);
- if (r)
- return r;
-
adev->vcn.pause_dpg_mode = vcn_v2_0_pause_dpg_mode;
- adev->vcn.internal.jpeg_pitch = mmUVD_JPEG_PITCH_INTERNAL_OFFSET;
- adev->vcn.inst->external.jpeg_pitch = SOC15_REG_OFFSET(UVD, 0,
mmUVD_JPEG_PITCH);
-
return 0;
}
@@ -258,11 +239,6 @@ static int vcn_v2_0_hw_init(void *handle)
goto done;
}
- ring = >vcn.inst->ring_jpeg;
- r = amdgpu_ring_test_helper(ring);
- if (r)
- goto done;
-
done:
if (!r)
DRM_INFO("VCN decode and encode initialized successfully(under
%s).\n",
@@ -296,9 +272,6 @@ static int vcn_v2_0_hw_fini(void *handle)
ring->sched.ready = false;
}
- ring = >vcn.inst->ring_jpeg;
- ring->sched.ready = false;
-
return 0;
}
@@ -393,7 +366,6 @@ static void vcn_v2_0_mc_resume(struct amdgpu_device *adev)
WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
WREG32_SOC15(UVD, 0, mmUVD_GFX10_ADDR_CONFIG,
adev->gfx.config.gb_addr_config);
- WREG32_SOC15(UVD, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG,
adev->gfx.config.gb_addr_config);
}
static void vcn_v2_0_mc_resume_dpg_mode(struct amdgpu_device *adev, bool
indirect)
@@ -647,129 +619,6 @@ static void vcn_v2_0_clock_gating_dpg_mode(struct
amdgpu_device *adev,
UVD, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
}
-/**
- * jpeg_v2_0_start - start JPEG block
- *
- * @adev: amdgpu_device pointer
- *
- * Setup and start the JPEG block
- */
-static int jpeg_v2_0_start(struct amdgpu_device *adev)
-{
- struct amdgpu_ring *ring = >vcn.inst->ring_jpeg;
- uint32_t tmp;
- int r = 0;
-
- /* disable power gating */
- tmp = 1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT;
- WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_PGFSM_CONFIG), tmp);
-
- SOC15_WAIT_ON_RREG(VCN, 0,
- mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS_UVDJ_PWR_ON,
- UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK, r);
-
- if (r) {
- DRM_ERROR("amdgpu: JPEG disable power gating failed\n");
- return r;
- }
-
- /* Removing the anti hang mechanism to indicate the UVDJ tile is ON */
- tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_POWER_STATUS)) & ~0x1;
- WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_POWER_STATUS), tmp);
-
- /* JPEG disable CGC */
- tmp = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL);
- tmp |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
- tmp |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
- tmp |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
- WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, tmp);
-
- tmp = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE);
- tmp &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK
- | JPEG_CGC_GATE__JPEG2_DEC_MASK
- | JPEG_CGC_GATE__JPEG_ENC_MASK
- | JPEG_CGC_GATE__JMCIF_MASK
- | JPEG_CGC_GATE__JRBBM_MASK);
- WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, tmp);
-
- /* enable JMI channel */
-
[PATCH 01/21] drm/amdgpu: add JPEG HW IP and SW structures
It will be used for JPEG IP 1.0, 2.0, 2.5 and later.
Signed-off-by: Leo Liu
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 5 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h | 46
2 files changed, 51 insertions(+)
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index bdc7de5b583d..b99e7772ac01 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -69,6 +69,7 @@
#include "amdgpu_uvd.h"
#include "amdgpu_vce.h"
#include "amdgpu_vcn.h"
+#include "amdgpu_jpeg.h"
#include "amdgpu_mn.h"
#include "amdgpu_gmc.h"
#include "amdgpu_gfx.h"
@@ -710,6 +711,7 @@ enum amd_hw_ip_block_type {
MP1_HWIP,
UVD_HWIP,
VCN_HWIP = UVD_HWIP,
+ JPEG_HWIP = VCN_HWIP,
VCE_HWIP,
DF_HWIP,
DCE_HWIP,
@@ -905,6 +907,9 @@ struct amdgpu_device {
/* vcn */
struct amdgpu_vcn vcn;
+ /* jpeg */
+ struct amdgpu_jpeg jpeg;
+
/* firmwares */
struct amdgpu_firmware firmware;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h
new file mode 100644
index ..36e2b7340c97
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __AMDGPU_JPEG_H__
+#define __AMDGPU_JPEG_H__
+
+#define AMDGPU_MAX_JPEG_INSTANCES 2
+
+struct amdgpu_jpeg_reg{
+ unsigned jpeg_pitch;
+};
+
+struct amdgpu_jpeg_inst {
+ struct amdgpu_ring ring_dec;
+ struct amdgpu_irq_src irq;
+ struct amdgpu_jpeg_reg external;
+};
+
+struct amdgpu_jpeg {
+ uint8_t num_jpeg_inst;
+ struct amdgpu_jpeg_inst inst[AMDGPU_MAX_JPEG_INSTANCES];
+ struct amdgpu_jpeg_reg internal;
+ unsigned harvest_config;
+};
+
+#endif /*__AMDGPU_JPEG_H__*/
--
2.17.1
___
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 04/21] drm/amdgpu: use the JPEG structure for general driver support
JPEG1.0 will be functional along with VCN1.0
Signed-off-by: Leo Liu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 8 +++-
3 files changed, 8 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index 6614d8a6f4c8..8f2eea92d67c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -169,10 +169,10 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
}
break;
case AMDGPU_HW_IP_VCN_JPEG:
- for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
+ for (j = 0; j < adev->jpeg.num_jpeg_inst; ++j) {
if (adev->vcn.harvest_config & (1 << j))
continue;
- rings[num_rings++] =
>vcn.inst[j].ring_jpeg;
+ rings[num_rings++] =
>jpeg.inst[j].ring_dec;
}
break;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 6ddea7607ad0..4a4085ec53e0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -401,11 +401,11 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
break;
case AMDGPU_HW_IP_VCN_JPEG:
type = AMD_IP_BLOCK_TYPE_VCN;
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
- if (adev->uvd.harvest_config & (1 << i))
+ for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
+ if (adev->jpeg.harvest_config & (1 << i))
continue;
- if (adev->vcn.inst[i].ring_jpeg.sched.ready)
+ if (adev->jpeg.inst[i].ring_dec.sched.ready)
++num_rings;
}
ib_start_alignment = 16;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 3199e4a5ff12..6b6c8f8efaff 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -212,8 +212,6 @@ int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
for (i = 0; i < adev->vcn.num_enc_rings; ++i)
amdgpu_ring_fini(>vcn.inst[j].ring_enc[i]);
-
- amdgpu_ring_fini(>vcn.inst[j].ring_jpeg);
}
release_firmware(adev->vcn.fw);
@@ -306,7 +304,7 @@ static void amdgpu_vcn_idle_work_handler(struct work_struct
*work)
else
new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
- if
(amdgpu_fence_count_emitted(>vcn.inst[j].ring_jpeg))
+ if
(amdgpu_fence_count_emitted(>jpeg.inst[j].ring_dec))
new_state.jpeg = VCN_DPG_STATE__PAUSE;
else
new_state.jpeg = VCN_DPG_STATE__UNPAUSE;
@@ -314,7 +312,7 @@ static void amdgpu_vcn_idle_work_handler(struct work_struct
*work)
adev->vcn.pause_dpg_mode(adev, _state);
}
- fence[j] +=
amdgpu_fence_count_emitted(>vcn.inst[j].ring_jpeg);
+ fence[j] +=
amdgpu_fence_count_emitted(>jpeg.inst[j].ring_dec);
fence[j] +=
amdgpu_fence_count_emitted(>vcn.inst[j].ring_dec);
fences += fence[j];
}
@@ -358,7 +356,7 @@ void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
else
new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
- if
(amdgpu_fence_count_emitted(>vcn.inst[ring->me].ring_jpeg))
+ if
(amdgpu_fence_count_emitted(>jpeg.inst[ring->me].ring_dec))
new_state.jpeg = VCN_DPG_STATE__PAUSE;
else
new_state.jpeg = VCN_DPG_STATE__UNPAUSE;
--
2.17.1
___
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 02/21] drm/amdgpu: add amdgpu_jpeg and JPEG tests
It will be used for all versions of JPEG eventually. Previous
JPEG tests will be removed later since they are still used by
JPEG2.x.
Signed-off-by: Leo Liu
---
drivers/gpu/drm/amd/amdgpu/Makefile | 5 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c | 135 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h | 3 +
3 files changed, 141 insertions(+), 2 deletions(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
b/drivers/gpu/drm/amd/amdgpu/Makefile
index 7eb172ebf3f8..11ca70105eeb 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -147,12 +147,13 @@ amdgpu-y += \
vce_v3_0.o \
vce_v4_0.o
-# add VCN block
+# add VCN and JPEG block
amdgpu-y += \
amdgpu_vcn.o \
vcn_v1_0.o \
vcn_v2_0.o \
- vcn_v2_5.o
+ vcn_v2_5.o \
+ amdgpu_jpeg.o
# add ATHUB block
amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c
new file mode 100644
index ..d9a547d4d3b2
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c
@@ -0,0 +1,135 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ */
+
+#include "amdgpu.h"
+#include "amdgpu_jpeg.h"
+#include "soc15d.h"
+#include "soc15_common.h"
+
+int amdgpu_jpeg_dec_ring_test_ring(struct amdgpu_ring *ring)
+{
+ struct amdgpu_device *adev = ring->adev;
+ uint32_t tmp = 0;
+ unsigned i;
+ int r;
+
+ WREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch, 0xCAFEDEAD);
+ r = amdgpu_ring_alloc(ring, 3);
+ if (r)
+ return r;
+
+ amdgpu_ring_write(ring, PACKET0(adev->jpeg.internal.jpeg_pitch, 0));
+ amdgpu_ring_write(ring, 0xDEADBEEF);
+ amdgpu_ring_commit(ring);
+
+ for (i = 0; i < adev->usec_timeout; i++) {
+ tmp = RREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch);
+ if (tmp == 0xDEADBEEF)
+ break;
+ udelay(1);
+ }
+
+ if (i >= adev->usec_timeout)
+ r = -ETIMEDOUT;
+
+ return r;
+}
+
+static int amdgpu_jpeg_dec_set_reg(struct amdgpu_ring *ring, uint32_t handle,
+ struct dma_fence **fence)
+{
+ struct amdgpu_device *adev = ring->adev;
+ struct amdgpu_job *job;
+ struct amdgpu_ib *ib;
+ struct dma_fence *f = NULL;
+ const unsigned ib_size_dw = 16;
+ int i, r;
+
+ r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, );
+ if (r)
+ return r;
+
+ ib = >ibs[0];
+
+ ib->ptr[0] = PACKETJ(adev->jpeg.internal.jpeg_pitch, 0, 0,
PACKETJ_TYPE0);
+ ib->ptr[1] = 0xDEADBEEF;
+ for (i = 2; i < 16; i += 2) {
+ ib->ptr[i] = PACKETJ(0, 0, 0, PACKETJ_TYPE6);
+ ib->ptr[i+1] = 0;
+ }
+ ib->length_dw = 16;
+
+ r = amdgpu_job_submit_direct(job, ring, );
+ if (r)
+ goto err;
+
+ if (fence)
+ *fence = dma_fence_get(f);
+ dma_fence_put(f);
+
+ return 0;
+
+err:
+ amdgpu_job_free(job);
+ return r;
+}
+
+int amdgpu_jpeg_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout)
+{
+ struct amdgpu_device *adev = ring->adev;
+ uint32_t tmp = 0;
+ unsigned i;
+ struct dma_fence *fence = NULL;
+ long r = 0;
+
+ r = amdgpu_jpeg_dec_set_reg(ring, 1, );
+ if (r)
+ goto error;
+
+ r = dma_fence_wait_timeout(fence, false, timeout);
+ if (r == 0) {
+ r = -ETIMEDOUT;
+ goto error;
+ } else if (r < 0) {
+ goto error;
+ } else {
+ r = 0;
+ }
+
+ for (i = 0; i < adev->usec_timeout; i++)
[PATCH 00/21] Separate JPEG from VCN
From JPEG2.0, JPEG is a separated IP block, and has it own PG/CG, and power management. It doesn't require FW, so indepedent from FW loading as well. Patch 1-4: Separate JPEG1.0 from SW wise, since JPEG1.0 is still combined with VCN1.0 esp. in power management; Patch 5-10: Separate JPEG2.0 as an independent IP with PG/CG; Patch 11-15: Add power management for JPEG of Navi1x and Renoir; Patch 16: Enable JPEG2.0; Patch 17-20: Separate JPEG2.5 from VCN2.5; Patch 21: Enable JPEG2.5 Leo Liu (21): drm/amdgpu: add JPEG HW IP and SW structures drm/amdgpu: add amdgpu_jpeg and JPEG tests drm/amdgpu: separate JPEG1.0 code out from VCN1.0 drm/amdgpu: use the JPEG structure for general driver support drm/amdgpu: add JPEG IP block type drm/amdgpu: add JPEG common functions to amdgpu_jpeg drm/amdgpu: add JPEG v2.0 function supports drm/amdgpu: remove unnecessary JPEG2.0 code from VCN2.0 drm/amdgpu: add JPEG PG and CG interface drm/amdgpu: add PG and CG for JPEG2.0 drm/amd/powerplay: add JPEG Powerplay interface drm/amd/powerplay: add JPEG power control for Navi1x drm/amd/powerplay: add Powergate JPEG for Renoir drm/amd/powerplay: add JPEG power control for Renoir drm/amd/powerplay: set JPEG to SMU dpm drm/amdgpu: enable JPEG2.0 dpm drm/amdgpu: add driver support for JPEG2.0 and above drm/amdgpu: enable JPEG2.0 for Navi1x and Renoir drm/amdgpu: move JPEG2.5 out from VCN2.5 drm/amdgpu: enable Arcturus CG for VCN and JPEG blocks drm/amdgpu: enable Arcturus JPEG2.5 block drivers/gpu/drm/amd/amdgpu/Makefile | 8 +- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 5 + drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 4 +- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c | 215 + drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h | 62 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 15 +- drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c| 8 + drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h| 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 113 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 5 - drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c| 584 + drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.h| 32 + drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c| 827 ++ drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.h| 42 + drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c| 641 ++ drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.h| 29 + drivers/gpu/drm/amd/amdgpu/nv.c | 11 +- drivers/gpu/drm/amd/amdgpu/soc15.c| 10 +- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 481 +- drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 496 +-- drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h | 13 - drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 246 +- drivers/gpu/drm/amd/include/amd_shared.h | 5 +- drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 5 + .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h| 3 + drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h | 2 + drivers/gpu/drm/amd/powerplay/navi10_ppt.c| 32 +- drivers/gpu/drm/amd/powerplay/renoir_ppt.c| 27 + drivers/gpu/drm/amd/powerplay/smu_internal.h | 4 + drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 11 + 31 files changed, 2593 insertions(+), 1346 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h create mode 100644 drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c create mode 100644 drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.h create mode 100644 drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c create mode 100644 drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.h create mode 100644 drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c create mode 100644 drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.h -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH V3 0/3] drm: replace magic numbers
From: Bjorn Helgaas amdgpu and radeon do a bit of mucking with the PCIe Link Control 2 register, some of it using hard-coded magic numbers. The idea here is to replace those with #defines. Since v2: - Fix a gpu_cfg2 case in amdgpu/si.c that I had missed - Separate out the functional changes for better bisection (thanks, Michel!) - Add #defines in a patch by themselves (so a GPU revert wouldn't break other potential users) - Squash all the magic number -> #define changes into one patch Since v1: - Add my signed-off-by and Alex's reviewed-by. Bjorn Helgaas (3): PCI: Add #defines for Enter Compliance, Transmit Margin drm: correct Transmit Margin masks drm: replace numbers with PCI_EXP_LNKCTL2 definitions drivers/gpu/drm/amd/amdgpu/cik.c | 22 ++ drivers/gpu/drm/amd/amdgpu/si.c | 22 ++ drivers/gpu/drm/radeon/cik.c | 22 ++ drivers/gpu/drm/radeon/si.c | 22 ++ include/uapi/linux/pci_regs.h| 2 ++ 5 files changed, 58 insertions(+), 32 deletions(-) -- 2.24.0.rc1.363.gb1bccd3e3d-goog ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 1/3] PCI: Add #defines for Enter Compliance, Transmit Margin
From: Bjorn Helgaas Add definitions for the Enter Compliance and Transmit Margin fields of the PCIe Link Control 2 register. Signed-off-by: Bjorn Helgaas --- include/uapi/linux/pci_regs.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 29d6e93fd15e..5869e5778a05 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -673,6 +673,8 @@ #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ #define PCI_EXP_LNKCTL2_TLS_16_0GT0x0004 /* Supported Speed 16GT/s */ #define PCI_EXP_LNKCTL2_TLS_32_0GT0x0005 /* Supported Speed 32GT/s */ +#define PCI_EXP_LNKCTL2_ENTER_COMP0x0010 /* Enter Compliance */ +#define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */ #define PCI_EXP_LNKSTA250 /* Link Status 2 */ #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 52 /* v2 endpoints with link end here */ #define PCI_EXP_SLTCAP252 /* Slot Capabilities 2 */ -- 2.24.0.rc1.363.gb1bccd3e3d-goog ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 2/3] drm: correct Transmit Margin masks
From: Bjorn Helgaas Previously we masked PCIe Link Control 2 register values with "7 << 9", which was apparently intended to be the Transmit Margin field, but instead was the high order bit of Transmit Margin, the Enter Modified Compliance bit, and the Compliance SOS bit. Correct the mask to "7 << 7", which is the Transmit Margin field. Signed-off-by: Bjorn Helgaas --- drivers/gpu/drm/amd/amdgpu/cik.c | 8 drivers/gpu/drm/amd/amdgpu/si.c | 8 drivers/gpu/drm/radeon/cik.c | 8 drivers/gpu/drm/radeon/si.c | 8 4 files changed, 16 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c index b81bb414fcb3..13a5696d2a6a 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik.c +++ b/drivers/gpu/drm/amd/amdgpu/cik.c @@ -1498,13 +1498,13 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev) /* linkctl2 */ pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, ); - tmp16 &= ~((1 << 4) | (7 << 9)); - tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9))); + tmp16 &= ~((1 << 4) | (7 << 7)); + tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 7))); pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16); pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, ); - tmp16 &= ~((1 << 4) | (7 << 9)); - tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9))); + tmp16 &= ~((1 << 4) | (7 << 7)); + tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 7))); pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); tmp = RREG32_PCIE(ixPCIE_LC_CNTL4); diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c index 493af42152f2..1e350172dc7b 100644 --- a/drivers/gpu/drm/amd/amdgpu/si.c +++ b/drivers/gpu/drm/amd/amdgpu/si.c @@ -1737,13 +1737,13 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev) pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16); pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, ); - tmp16 &= ~((1 << 4) | (7 << 9)); - tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9))); + tmp16 &= ~((1 << 4) | (7 << 7)); + tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 7))); pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16); pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, ); - tmp16 &= ~((1 << 4) | (7 << 9)); - tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9))); + tmp16 &= ~((1 << 4) | (7 << 7)); + tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 7))); pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4); diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c index 62eab82a64f9..14cdfdf78bde 100644 --- a/drivers/gpu/drm/radeon/cik.c +++ b/drivers/gpu/drm/radeon/cik.c @@ -9619,13 +9619,13 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev) /* linkctl2 */ pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, ); - tmp16 &= ~((1 << 4) | (7 << 9)); - tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9))); + tmp16 &= ~((1 << 4) | (7 << 7)); + tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 7))); pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16); pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, ); - tmp16 &= ~((1 << 4) | (7 << 9)); - tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9))); + tmp16 &= ~((1 << 4) | (7 << 7)); + tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 7))); pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4); diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c index 05894d198a79..9b7042d3ef1b 100644 --- a/drivers/gpu/drm/radeon/si.c +++ b/drivers/gpu/drm/radeon/si.c @@ -7202,13 +7202,13 @@ static void
[PATCH 3/3] drm: replace numbers with PCI_EXP_LNKCTL2 definitions
From: Bjorn Helgaas Replace hard-coded magic numbers with the descriptive PCI_EXP_LNKCTL2 definitions. No functional change intended. Signed-off-by: Bjorn Helgaas Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/cik.c | 22 ++ drivers/gpu/drm/amd/amdgpu/si.c | 22 ++ drivers/gpu/drm/radeon/cik.c | 22 ++ drivers/gpu/drm/radeon/si.c | 22 ++ 4 files changed, 56 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c index 13a5696d2a6a..3067bb874032 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik.c +++ b/drivers/gpu/drm/amd/amdgpu/cik.c @@ -1498,13 +1498,19 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev) /* linkctl2 */ pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, ); - tmp16 &= ~((1 << 4) | (7 << 7)); - tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 7))); + tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP | + PCI_EXP_LNKCTL2_TX_MARGIN); + tmp16 |= (bridge_cfg2 & + (PCI_EXP_LNKCTL2_ENTER_COMP | + PCI_EXP_LNKCTL2_TX_MARGIN)); pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16); pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, ); - tmp16 &= ~((1 << 4) | (7 << 7)); - tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 7))); + tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP | + PCI_EXP_LNKCTL2_TX_MARGIN); + tmp16 |= (gpu_cfg2 & + (PCI_EXP_LNKCTL2_ENTER_COMP | + PCI_EXP_LNKCTL2_TX_MARGIN)); pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); tmp = RREG32_PCIE(ixPCIE_LC_CNTL4); @@ -1521,13 +1527,13 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev) WREG32_PCIE(ixPCIE_LC_SPEED_CNTL, speed_cntl); pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, ); - tmp16 &= ~0xf; + tmp16 &= ~PCI_EXP_LNKCTL2_TLS; if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) - tmp16 |= 3; /* gen3 */ + tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */ else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) - tmp16 |= 2; /* gen2 */ + tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */ else - tmp16 |= 1; /* gen1 */ + tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */ pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL); diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c index 1e350172dc7b..a7dcb0d0f039 100644 --- a/drivers/gpu/drm/amd/amdgpu/si.c +++ b/drivers/gpu/drm/amd/amdgpu/si.c @@ -1737,13 +1737,19 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev) pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16); pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, ); - tmp16 &= ~((1 << 4) | (7 << 7)); - tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 7))); + tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP | + PCI_EXP_LNKCTL2_TX_MARGIN); + tmp16 |= (bridge_cfg2 & + (PCI_EXP_LNKCTL2_ENTER_COMP | + PCI_EXP_LNKCTL2_TX_MARGIN)); pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16); pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, ); - tmp16 &= ~((1 << 4) | (7 << 7)); - tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 7))); + tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP | + PCI_EXP_LNKCTL2_TX_MARGIN); + tmp16 |= (gpu_cfg2 & + (PCI_EXP_LNKCTL2_ENTER_COMP | + PCI_EXP_LNKCTL2_TX_MARGIN)); pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4); @@ -1758,13 +1764,13 @@ static void
Re: [PATCH 1/2] drm: replace incorrect Compliance/Margin magic numbers with PCI_EXP_LNKCTL2 definitions
On Tue, Nov 12, 2019 at 05:45:15PM +0100, Michel Dänzer wrote: > On 2019-11-11 8:29 p.m., Bjorn Helgaas wrote: > > From: Bjorn Helgaas > > > > Add definitions for these PCIe Link Control 2 register fields: > > > > Enter Compliance > > Transmit Margin > > > > and use them in amdgpu and radeon. > > > > NOTE: This is a functional change because "7 << 9" was apparently a typo. > > That mask included the high order bit of Transmit Margin, the Enter > > Modified Compliance bit, and the Compliance SOS bit, but I think what > > was intended was the 3-bit Transmit Margin field at bits 9:7. > > Can you split out the functional change into a separate patch 1? That > could make things easier for anyone who bisects the functional change > for whatever reason. Great idea, thanks! Wish I'd thought of that. While fixing that, I also noticed I missed one case in amdgpu/si.c. I'll post a v3. ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 1/2] drm: replace incorrect Compliance/Margin magic numbers with PCI_EXP_LNKCTL2 definitions
On 2019-11-11 8:29 p.m., Bjorn Helgaas wrote: > From: Bjorn Helgaas > > Add definitions for these PCIe Link Control 2 register fields: > > Enter Compliance > Transmit Margin > > and use them in amdgpu and radeon. > > NOTE: This is a functional change because "7 << 9" was apparently a typo. > That mask included the high order bit of Transmit Margin, the Enter > Modified Compliance bit, and the Compliance SOS bit, but I think what > was intended was the 3-bit Transmit Margin field at bits 9:7. Can you split out the functional change into a separate patch 1? That could make things easier for anyone who bisects the functional change for whatever reason. -- Earthling Michel Dänzer | https://redhat.com Libre software enthusiast | Mesa and X developer ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 1/2] drm/amd/display: Return correct error value
On 2019-11-12 10:16 a.m., mikita.lip...@amd.com wrote:
From: Mikita Lipski
[why]
The function is expected to return instance of the timing generator
therefore we shouldn't be returning boolean in integer function,
and we shouldn't be returning zero so changing it to -1.
Signed-off-by: Mikita Lipski
I wonder if some of these were intentional for returning 0. These lines
were originally introduced for enabling seamless boot support with eDP
and I think you're guaranteed to have those resources as instance 0.
Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 89b5f86cd40b..75cc58ecf647 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -1866,7 +1866,7 @@ static int acquire_resource_from_hw_enabled_state(
inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
if (inst == ENGINE_ID_UNKNOWN)
- return false;
+ return -1;
for (i = 0; i < pool->stream_enc_count; i++) {
if (pool->stream_enc[i]->id == inst) {
@@ -1878,10 +1878,10 @@ static int acquire_resource_from_hw_enabled_state(
// tg_inst not found
if (i == pool->stream_enc_count)
- return false;
+ return -1;
if (tg_inst >= pool->timing_generator_count)
- return false;
+ return -1;
if (!res_ctx->pipe_ctx[tg_inst].stream) {
struct pipe_ctx *pipe_ctx = _ctx->pipe_ctx[tg_inst];
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Re: [PATCH 2/2] drm/amd/display: Fix coding error in connector atomic check
On 2019-11-12 10:15 a.m., mikita.lip...@amd.com wrote:
From: Mikita Lipski
[why]
For MST connector atomic check we have to check a new CRTC state
instead of an old one, when checking if CRTC is disabled to
release VCPI slots allocated.
Signed-off-by: Mikita Lipski
Reviewed-by: Nicholas Kazlauskas
Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 21f09b61ee88..00cb2f109853 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -299,7 +299,7 @@ static int dm_dp_mst_atomic_check(struct drm_connector
*connector,
return 0;
if (new_conn_state->crtc) {
- new_crtc_state = drm_atomic_get_old_crtc_state(state,
new_conn_state->crtc);
+ new_crtc_state = drm_atomic_get_new_crtc_state(state,
new_conn_state->crtc);
if (!new_crtc_state ||
!drm_atomic_crtc_needs_modeset(new_crtc_state) ||
new_crtc_state->enable)
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Re: [PATCH v2 -next] drm/amd/display: remove set but not used variable 'bpc'
On Tue, Nov 12, 2019 at 3:13 AM YueHaibing wrote:
>
> Fixes gcc '-Wunused-but-set-variable' warning:
>
> drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link.c: In function
> get_pbn_from_timing:
> drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link.c:2364:11: warning:
> variable bpc set but not used [-Wunused-but-set-variable]
>
> It is not used since commit e49f69363adf ("drm/amd/display: use
> proper formula to calculate bandwidth from timing"), this also
> remove get_color_depth(), which is only used here.
>
> Signed-off-by: YueHaibing
Applied. Thanks!
Alex
> ---
> v2: also remove unused get_color_depth()
> ---
> drivers/gpu/drm/amd/display/dc/core/dc_link.c | 15 ---
> 1 file changed, 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> index bdc8be3..1be4277 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> @@ -2638,28 +2638,13 @@ static struct fixed31_32 get_pbn_per_slot(struct
> dc_stream_state *stream)
> return dc_fixpt_div_int(mbytes_per_sec, 54);
> }
>
> -static int get_color_depth(enum dc_color_depth color_depth)
> -{
> - switch (color_depth) {
> - case COLOR_DEPTH_666: return 6;
> - case COLOR_DEPTH_888: return 8;
> - case COLOR_DEPTH_101010: return 10;
> - case COLOR_DEPTH_121212: return 12;
> - case COLOR_DEPTH_141414: return 14;
> - case COLOR_DEPTH_161616: return 16;
> - default: return 0;
> - }
> -}
> -
> static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx)
> {
> - uint32_t bpc;
> uint64_t kbps;
> struct fixed31_32 peak_kbps;
> uint32_t numerator;
> uint32_t denominator;
>
> - bpc =
> get_color_depth(pipe_ctx->stream_res.pix_clk_params.color_depth);
> kbps = dc_bandwidth_in_kbps_from_timing(_ctx->stream->timing);
>
> /*
> --
> 2.7.4
>
>
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[PATCH 1/2] drm/amd/display: Return correct error value
From: Mikita Lipski
[why]
The function is expected to return instance of the timing generator
therefore we shouldn't be returning boolean in integer function,
and we shouldn't be returning zero so changing it to -1.
Signed-off-by: Mikita Lipski
---
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 89b5f86cd40b..75cc58ecf647 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -1866,7 +1866,7 @@ static int acquire_resource_from_hw_enabled_state(
inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
if (inst == ENGINE_ID_UNKNOWN)
- return false;
+ return -1;
for (i = 0; i < pool->stream_enc_count; i++) {
if (pool->stream_enc[i]->id == inst) {
@@ -1878,10 +1878,10 @@ static int acquire_resource_from_hw_enabled_state(
// tg_inst not found
if (i == pool->stream_enc_count)
- return false;
+ return -1;
if (tg_inst >= pool->timing_generator_count)
- return false;
+ return -1;
if (!res_ctx->pipe_ctx[tg_inst].stream) {
struct pipe_ctx *pipe_ctx = _ctx->pipe_ctx[tg_inst];
--
2.17.1
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[PATCH 2/2] drm/amd/display: Fix coding error in connector atomic check
From: Mikita Lipski
[why]
For MST connector atomic check we have to check a new CRTC state
instead of an old one, when checking if CRTC is disabled to
release VCPI slots allocated.
Signed-off-by: Mikita Lipski
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 21f09b61ee88..00cb2f109853 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -299,7 +299,7 @@ static int dm_dp_mst_atomic_check(struct drm_connector
*connector,
return 0;
if (new_conn_state->crtc) {
- new_crtc_state = drm_atomic_get_old_crtc_state(state,
new_conn_state->crtc);
+ new_crtc_state = drm_atomic_get_new_crtc_state(state,
new_conn_state->crtc);
if (!new_crtc_state ||
!drm_atomic_crtc_needs_modeset(new_crtc_state) ||
new_crtc_state->enable)
--
2.17.1
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[PATCH] drm/amdgpu: don't read registers if gfxoff is enabled (v2)
When gfxoff is enabled, accessing gfx registers via MMIO
can lead to a hang.
v2: return cached registers properly.
Bug: https://bugzilla.kernel.org/show_bug.cgi?id=205497
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/nv.c| 27 --
drivers/gpu/drm/amd/amdgpu/soc15.c | 31 ++
2 files changed, 36 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index af68f9815f28..7283d6198b89 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -201,17 +201,25 @@ static uint32_t nv_read_indexed_register(struct
amdgpu_device *adev, u32 se_num,
return val;
}
-static uint32_t nv_get_register_value(struct amdgpu_device *adev,
+static int nv_get_register_value(struct amdgpu_device *adev,
bool indexed, u32 se_num,
- u32 sh_num, u32 reg_offset)
+ u32 sh_num, u32 reg_offset,
+ u32 *value)
{
if (indexed) {
- return nv_read_indexed_register(adev, se_num, sh_num,
reg_offset);
+ if (adev->pm.pp_feature & PP_GFXOFF_MASK)
+ return -EINVAL;
+ *value = nv_read_indexed_register(adev, se_num, sh_num,
reg_offset);
} else {
- if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
- return adev->gfx.config.gb_addr_config;
- return RREG32(reg_offset);
+ if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) {
+ *value = adev->gfx.config.gb_addr_config;
+ } else {
+ if (adev->pm.pp_feature & PP_GFXOFF_MASK)
+ return -EINVAL;
+ *value = RREG32(reg_offset);
+ }
}
+ return 0;
}
static int nv_read_register(struct amdgpu_device *adev, u32 se_num,
@@ -227,10 +235,9 @@ static int nv_read_register(struct amdgpu_device *adev,
u32 se_num,
(adev->reg_offset[en->hwip][en->inst][en->seg] +
en->reg_offset))
continue;
- *value = nv_get_register_value(adev,
-
nv_allowed_read_registers[i].grbm_indexed,
- se_num, sh_num, reg_offset);
- return 0;
+ return nv_get_register_value(adev,
+
nv_allowed_read_registers[i].grbm_indexed,
+se_num, sh_num, reg_offset, value);
}
return -EINVAL;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 305ad3eec987..2cc16e9f39fb 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -363,19 +363,27 @@ static uint32_t soc15_read_indexed_register(struct
amdgpu_device *adev, u32 se_n
return val;
}
-static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
+static int soc15_get_register_value(struct amdgpu_device *adev,
bool indexed, u32 se_num,
-u32 sh_num, u32 reg_offset)
+u32 sh_num, u32 reg_offset,
+u32 *value)
{
if (indexed) {
- return soc15_read_indexed_register(adev, se_num, sh_num,
reg_offset);
+ if (adev->pm.pp_feature & PP_GFXOFF_MASK)
+ return -EINVAL;
+ *value = soc15_read_indexed_register(adev, se_num, sh_num,
reg_offset);
} else {
- if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
- return adev->gfx.config.gb_addr_config;
- else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))
- return adev->gfx.config.db_debug2;
- return RREG32(reg_offset);
+ if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) {
+ *value = adev->gfx.config.gb_addr_config;
+ } else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2)) {
+ *value = adev->gfx.config.db_debug2;
+ } else {
+ if (adev->pm.pp_feature & PP_GFXOFF_MASK)
+ return -EINVAL;
+ *value = RREG32(reg_offset);
+ }
}
+ return 0;
}
static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
@@ -391,10 +399,9 @@ static int soc15_read_register(struct amdgpu_device *adev,
u32 se_num,
+ en->reg_offset))
continue;
- *value = soc15_get_register_value(adev,
-
drm core/helpers and MIT license
Hi all, Dave and me chatted about this last week on irc. Essentially we have: $ git grep SPDX.*GPL -- ':(glob)drivers/gpu/drm/*c' drivers/gpu/drm/drm_client.c:// SPDX-License-Identifier: GPL-2.0 drivers/gpu/drm/drm_damage_helper.c:// SPDX-License-Identifier: GPL-2.0 OR MIT drivers/gpu/drm/drm_dp_cec.c:// SPDX-License-Identifier: GPL-2.0 drivers/gpu/drm/drm_edid_load.c:// SPDX-License-Identifier: GPL-2.0-or-later drivers/gpu/drm/drm_fb_cma_helper.c:// SPDX-License-Identifier: GPL-2.0-or-later drivers/gpu/drm/drm_format_helper.c:/* SPDX-License-Identifier: GPL-2.0 */ drivers/gpu/drm/drm_gem_cma_helper.c:// SPDX-License-Identifier: GPL-2.0-or-later drivers/gpu/drm/drm_gem_framebuffer_helper.c:// SPDX-License-Identifier: GPL-2.0-or-later drivers/gpu/drm/drm_gem_shmem_helper.c:// SPDX-License-Identifier: GPL-2.0 drivers/gpu/drm/drm_gem_ttm_helper.c:// SPDX-License-Identifier: GPL-2.0-or-later drivers/gpu/drm/drm_gem_vram_helper.c:// SPDX-License-Identifier: GPL-2.0-or-later drivers/gpu/drm/drm_hdcp.c:// SPDX-License-Identifier: GPL-2.0 drivers/gpu/drm/drm_lease.c:// SPDX-License-Identifier: GPL-2.0-or-later drivers/gpu/drm/drm_mipi_dbi.c:// SPDX-License-Identifier: GPL-2.0-or-later drivers/gpu/drm/drm_of.c:// SPDX-License-Identifier: GPL-2.0-only drivers/gpu/drm/drm_simple_kms_helper.c:// SPDX-License-Identifier: GPL-2.0-or-later drivers/gpu/drm/drm_sysfs.c:// SPDX-License-Identifier: GPL-2.0-only drivers/gpu/drm/drm_vma_manager.c:// SPDX-License-Identifier: GPL-2.0 OR MIT drivers/gpu/drm/drm_vram_helper_common.c:// SPDX-License-Identifier: GPL-2.0-or-later drivers/gpu/drm/drm_writeback.c:// SPDX-License-Identifier: GPL-2.0 One is GPL+MIT, so ok, and one is a default GPL-only header from Greg's infamous patch (so could probably be changed to MIT license header). I only looked at .c sources, since headers are worse wrt having questionable default headers. So about 18 files with clear GPL licenses thus far in drm core/helpers. Looking at where that code came from, it is mostly from GPL-only drivers (we have a lot of those nowadays), so seems legit non-MIT licensed. Question is now what do we do: - Nothing, which means GPL will slowly encroach on drm core/helpers, which is roughly the same as ... - Throw in the towel on MIT drm core officially. Same as above, except lets just make it official. - Try to counter this, which means at least a) relicensing a bunch of stuff b) rewriting a bunch of stuff c) making sure that's ok with everyone, there's a lot of GPL-by-default for the kernel (that's how we got most of the above code through merged drivers I think). I suspect that whomever cares will need to put in the work to make this happen (since it will need a pile of active resistance at least). Cc maintainers/driver teams who might care most about this. Also if people could cc *bsd, they probably care and I don't know best contacts for graphics stuff (or anything else really at all). Cheers, Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: don't read registers if gfxoff is enabled
When gfxoff is enabled, accessing gfx registers via MMIO can lead to a hang. Bug: https://bugzilla.kernel.org/show_bug.cgi?id=205497 Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index c975ca92e8fa..08c4cda3a569 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -665,6 +665,9 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file if (info->read_mmr_reg.count > 128) return -EINVAL; + if (adev->pm.pp_feature & PP_GFXOFF_MASK) + return -EINVAL; + regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL); if (!regs) return -ENOMEM; -- 2.23.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu/vcn: finish delay work before release resources
Am 11.11.19 um 21:49 schrieb Alex Deucher:
flush/cancel delayed works before doing finalization
to avoid concurrently requests.
Signed-off-by: Alex Deucher
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 3199e4a5ff12..9d870444d7d6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -193,6 +193,8 @@ int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
{
int i, j;
+ cancel_delayed_work_sync(>vcn.idle_work);
+
if (adev->vcn.indirect_sram) {
amdgpu_bo_free_kernel(>vcn.dpg_sram_bo,
>vcn.dpg_sram_gpu_addr,
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Re: [PATCH] drm/amdgpu: Fix the null pointer issue for tdr
Hi Emily,
you need to print which scheduler instance is freeing the jobs and which
one is triggering the reset. The TID and PID is completely meaningless
here since we are called from different worker threads and the TID/PID
can change on each call.
Apart from that I will look into this a bit deeper when I have time.
Regards,
Christian.
Am 12.11.19 um 07:02 schrieb Deng, Emily:
Hi Christian,
I add the follow print in function drm_sched_cleanup_jobs. From
the log it shows that only use cancel_delayed_work could not avoid to
free job when the sched is in reset. But don’t know exactly where it
is wrong about the driver. Do you have any suggestion about this?
+ printk("Emily:drm_sched_cleanup_jobs:begin,tid:%lu, pid:%lu\n",
current->tgid, current->pid);
/*
* Don't destroy jobs while the timeout worker is running OR
thread
* is being parked and hence assumed to not touch ring_mirror_list
*/
if ((sched->timeout != MAX_SCHEDULE_TIMEOUT &&
!cancel_delayed_work(>work_tdr)))
return;
+ printk("Emily:drm_sched_cleanup_jobs,tid:%lu, pid:%lu\n",
current->tgid, current->pid);
Best wishes
Emily Deng
Nov 12 12:58:20 ubuntu-drop-August-2018-rc2-gpu0-vf02 kernel:
[11380.695091] Emily:drm_sched_cleanup_jobs:begin,tid:2262, pid:2262
Nov 12 12:58:20 ubuntu-drop-August-2018-rc2-gpu0-vf02 kernel:
[11380.695104] Emily:drm_sched_cleanup_jobs:begin,tid:2262, pid:2262
Nov 12 12:58:20 ubuntu-drop-August-2018-rc2-gpu0-vf02 kernel:
[11380.695105] Emily:drm_sched_cleanup_jobs,tid:2262, pid:2262
Nov 12 12:58:20 ubuntu-drop-August-2018-rc2-gpu0-vf02 kernel:
[11380.695107] Emily:drm_sched_cleanup_jobs:begin,tid:2262, pid:2262
Nov 12 12:58:20 ubuntu-drop-August-2018-rc2-gpu0-vf02 kernel:
[11380.695107] Emily:drm_sched_cleanup_jobs,tid:2262, pid:2262
Nov 12 12:58:20 ubuntu-drop-August-2018-rc2-gpu0-vf02 kernel:
[11381.222954] [drm:amdgpu_job_timedout [amdgpu]] *ERROR* ring sdma0
timeout, signaled seq=78585, emitted seq=78587
Nov 12 12:58:20 ubuntu-drop-August-2018-rc2-gpu0-vf02 kernel:
[11381.224275] [drm:amdgpu_job_timedout [amdgpu]] *ERROR* Process
information: process pid 0 thread pid 0,
s_job:fe75ab36,tid=15603, pid=15603
Nov 12 12:58:20 ubuntu-drop-August-2018-rc2-gpu0-vf02 kernel:
[11381.225413] amdgpu :00:08.0: GPU reset begin!
Nov 12 12:58:20 ubuntu-drop-August-2018-rc2-gpu0-vf02 kernel:
[11381.225417] Emily:drm_sched_cleanup_jobs:begin,tid:2262, pid:2262
Nov 12 12:58:20 ubuntu-drop-August-2018-rc2-gpu0-vf02 kernel:
[11381.225425] Emily:drm_sched_cleanup_jobs:begin,tid:2262, pid:2262
Nov 12 12:58:20 ubuntu-drop-August-2018-rc2-gpu0-vf02 kernel:
[11381.225425] Emily:drm_sched_cleanup_jobs,tid:2262, pid:2262
Nov 12 12:58:20 ubuntu-drop-August-2018-rc2-gpu0-vf02 kernel:
[11381.225428] Emily:amdgpu_job_free_cb,Process information: process
pid 0 thread pid 0, s_job:fe75ab36, tid:2262, pid:2262
Nov 12 12:58:20 ubuntu-drop-August-2018-rc2-gpu0-vf02 kernel:
[11381.225429] Emily:drm_sched_cleanup_jobs:begin,tid:2262, pid:2262
Nov 12 12:58:20 ubuntu-drop-August-2018-rc2-gpu0-vf02 kernel:
[11381.225430] Emily:drm_sched_cleanup_jobs,tid:2262, pid:2262
Nov 12 12:58:20 ubuntu-drop-August-2018-rc2-gpu0-vf02 kernel:
[11381.225473] Emily:drm_sched_cleanup_jobs:begin,tid:2253, pid:2253
Nov 12 12:58:20 ubuntu-drop-August-2018-rc2-gpu0-vf02 kernel:
[11381.225486] Emily:drm_sched_cleanup_jobs:begin,tid:2262, pid:2262
Nov 12 12:58:20 ubuntu-drop-August-2018-rc2-gpu0-vf02 kernel:
[11381.225489] Emily:drm_sched_cleanup_jobs,tid:2262, pid:2262
Nov 12 12:58:20 ubuntu-drop-August-2018-rc2-gpu0-vf02 kernel:
[11381.225494] Emily:amdgpu_job_free_cb,Process information: process
pid 0 thread pid 0, s_job:f086ec84, tid:2262, pid:2262
>-Original Message-
>From: Grodzovsky, Andrey
>Sent: Tuesday, November 12, 2019 11:28 AM
>To: Koenig, Christian ; Deng, Emily
>; amd-gfx@lists.freedesktop.org
>Subject: Re: [PATCH] drm/amdgpu: Fix the null pointer issue for tdr
>
>Thinking more about this claim - we assume here that if cancel_delayed_work
>returned true it guarantees that timeout work is not running but, it merely
>means there was a pending timeout work which was removed from the
>workqueue before it's timer elapsed and so it didn't have a chance to be
>dequeued and executed, it doesn't cover already executing work. So there is a
>possibility where while timeout work started executing another timeout work
>already got enqueued (maybe through earlier cleanup jobs or through
>drm_sched_fault) and if at this point another drm_sched_cleanup_jobs runs
>cancel_delayed_work(>work_tdr) will return true even while there is a
>timeout job in progress.
>Unfortunately we cannot change cancel_delayed_work to
>cancel_delayed_work_sync to flush the timeout work as timeout work itself
>waits for schedule thread to be parked again when calling park_thread.
>
>Andrey
>
>
>From: amd-gfx on
Re: [PATCH 1/4] drm/ttm: refine ghost BO resv criteria
On Mon, Nov 11, 2019 at 03:58:29PM +0100, Christian König wrote: > Ghost BOs need to stick with the resv object only when the origin is imported. > > This is a low hanging fruit to avoid OOM situations on evictions. > > Signed-off-by: Christian König I guess I still don't get what ghost objects all do and cause ... How does this lead to OOM cases where the eviction can't find memory anymore? -Daniel > --- > drivers/gpu/drm/ttm/ttm_bo_util.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c > b/drivers/gpu/drm/ttm/ttm_bo_util.c > index 2b0e5a088da0..86d152472f38 100644 > --- a/drivers/gpu/drm/ttm/ttm_bo_util.c > +++ b/drivers/gpu/drm/ttm/ttm_bo_util.c > @@ -511,7 +511,7 @@ static int ttm_buffer_object_transfer(struct > ttm_buffer_object *bo, > kref_init(>base.kref); > fbo->base.destroy = _transfered_destroy; > fbo->base.acc_size = 0; > - if (bo->base.resv == >base._resv) > + if (bo->type != ttm_bo_type_sg) > fbo->base.base.resv = >base.base._resv; > > dma_resv_init(>base.base._resv); > -- > 2.17.1 > > ___ > dri-devel mailing list > dri-de...@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH] drm/amd/powerplay: avoid DPM reenable process on Navi1x ASICs V2
Reviewed-by: Kenneth Feng
-Original Message-
From: amd-gfx On Behalf Of Evan Quan
Sent: Tuesday, November 12, 2019 9:47 AM
To: amd-gfx@lists.freedesktop.org
Cc: alexdeuc...@gmail.com; Matt Coffin ; Quan, Evan
Subject: [PATCH] drm/amd/powerplay: avoid DPM reenable process on Navi1x ASICs
V2
[CAUTION: External Email]
Otherwise, without RLC reinitialization, the DPM reenablement will fail. That
affects the custom pptable uploading.
V2: setting/clearing uploading_custom_pp_table in
smu_sys_set_pp_table()
Change-Id: I6fe2ed5ce23f2a5b66f371c0b6d1f924837e5af6
Reported-by: Matt Coffin
Signed-off-by: Evan Quan
Tested-by: Matt Coffin
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 31 ---
.../gpu/drm/amd/powerplay/inc/amdgpu_smu.h| 1 +
2 files changed, 28 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 76a4154b3be2..54c21f5a1861 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -591,10 +591,18 @@ int smu_sys_set_pp_table(struct smu_context *smu, void
*buf, size_t size)
smu_table->power_play_table = smu_table->hardcode_pptable;
smu_table->power_play_table_size = size;
+ /*
+* Special hw_fini action(for Navi1x, the DPMs disablement will be
+* skipped) may be needed for custom pptable uploading.
+*/
+ smu->uploading_custom_pp_table = true;
+
ret = smu_reset(smu);
if (ret)
pr_info("smu reset failed, ret = %d\n", ret);
+ smu->uploading_custom_pp_table = false;
+
failed:
mutex_unlock(>mutex);
return ret;
@@ -1293,10 +1301,25 @@ static int smu_hw_fini(void *handle)
return ret;
}
- ret = smu_stop_dpms(smu);
- if (ret) {
- pr_warn("Fail to stop Dpms!\n");
- return ret;
+ /*
+* For custom pptable uploading, skip the DPM features
+* disable process on Navi1x ASICs.
+* - As the gfx related features are under control of
+* RLC on those ASICs. RLC reinitialization will be
+* needed to reenable them. That will cost much more
+* efforts.
+*
+* - SMU firmware can handle the DPM reenablement
+* properly.
+*/
+ if (!smu->uploading_custom_pp_table ||
+ !((adev->asic_type >= CHIP_NAVI10) &&
+ (adev->asic_type <= CHIP_NAVI12))) {
+ ret = smu_stop_dpms(smu);
+ if (ret) {
+ pr_warn("Fail to stop Dpms!\n");
+ return ret;
+ }
}
kfree(table_context->driver_pptable);
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 8120e7587585..215841f5fb93 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -391,6 +391,7 @@ struct smu_context
uint32_t smc_if_version;
+ bool uploading_custom_pp_table;
};
struct i2c_adapter;
--
2.24.0
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Re: [PATCH 2/2] drm/edid: Add alternate clock for SMPTE 4K
On 12/11/2019 08:53, Wayne Lin wrote:
> [Why]
> In hdmi_mode_alternate_clock(), it adds an exception for VIC 4
> mode (4096x2160@24) due to there is no alternate clock defined for
> that mode in HDMI1.4b. But HDMI2.0 adds 23.98Hz for that mode.
>
> [How]
> Remove the exception
Shouldn't it be only bypassed when the sink is HDMI2 ?
Neil
>
> Signed-off-by: Wayne Lin
> ---
> drivers/gpu/drm/drm_edid.c | 3 ---
> 1 file changed, 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index fcd7ae29049d..ed2782c53a93 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -3126,9 +3126,6 @@ static enum hdmi_picture_aspect
> drm_get_hdmi_aspect_ratio(const u8 video_code)
> static unsigned int
> hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
> {
> - if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160)
> - return hdmi_mode->clock;
> -
> return cea_mode_alternate_clock(hdmi_mode);
> }
>
>
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RE: [PATCH] drm/amd/powerplay: read pcie speed/width info
> -Original Message-
> From: amd-gfx On Behalf Of
> Kenneth Feng
> Sent: Tuesday, November 12, 2019 4:40 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Feng, Kenneth
> Subject: [PATCH] drm/amd/powerplay: read pcie speed/width info
>
> sysfs interface to read pcie speed info on navi1x.
>
> Signed-off-by: Kenneth Feng
> ---
> drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 10 +++---
> drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 8 +
> drivers/gpu/drm/amd/powerplay/navi10_ppt.c| 50
> ++-
> drivers/gpu/drm/amd/powerplay/navi10_ppt.h| 3 ++
> 4 files changed, 66 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> index 57459a6..69243a8 100644
> --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> @@ -1068,10 +1068,6 @@ static int smu_smc_table_hw_init(struct
> smu_context *smu,
> return ret;
>
> if (adev->asic_type != CHIP_ARCTURUS) {
> - ret = smu_override_pcie_parameters(smu);
> - if (ret)
> - return ret;
> -
> ret = smu_notify_display_change(smu);
> if (ret)
> return ret;
> @@ -1100,6 +1096,12 @@ static int smu_smc_table_hw_init(struct
> smu_context *smu,
> return ret;
> }
>
> + if (adev->asic_type != CHIP_ARCTURUS) {
> + ret = smu_override_pcie_parameters(smu);
> + if (ret)
> + return ret;
> + }
> +
> ret = smu_set_default_od_settings(smu, initialize);
> if (ret)
> return ret;
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
> b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
> index 0ba7a72..6061490 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
> @@ -48,6 +48,8 @@
>
> #define SMU11_TOOL_SIZE 0x19000
>
> +#define MAX_PCIE_CONF 2
> +
> #define CLK_MAP(clk, index) \
> [SMU_##clk] = {1, (index)}
>
> @@ -88,6 +90,11 @@ struct smu_11_0_dpm_table {
> uint32_tmax;/* MHz */
> };
>
> +struct smu_11_0_pcie_table {
> +uint8_t pcie_gen[MAX_PCIE_CONF];
> +uint8_t pcie_lane[MAX_PCIE_CONF];
> +};
> +
> struct smu_11_0_dpm_tables {
> struct smu_11_0_dpm_tablesoc_table;
> struct smu_11_0_dpm_tablegfx_table;
> @@ -100,6 +107,7 @@ struct smu_11_0_dpm_tables {
> struct smu_11_0_dpm_tabledisplay_table;
> struct smu_11_0_dpm_tablephy_table;
> struct smu_11_0_dpm_tablefclk_table;
> + struct smu_11_0_pcie_table pcie_table;
> };
>
> struct smu_11_0_dpm_context {
> diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> index 36cf313..8855bcc 100644
> --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> @@ -36,6 +36,7 @@
> #include "navi10_ppt.h"
> #include "smu_v11_0_pptable.h"
> #include "smu_v11_0_ppsmc.h"
> +#include "nbio/nbio_7_4_sh_mask.h"
>
> #include "asic_reg/mp/mp_11_0_sh_mask.h"
>
> @@ -599,6 +600,7 @@ static int navi10_set_default_dpm_table(struct
> smu_context *smu)
> struct smu_table_context *table_context = >smu_table;
> struct smu_11_0_dpm_context *dpm_context = smu_dpm-
> >dpm_context;
> PPTable_t *driver_ppt = NULL;
> + int i;
>
> driver_ppt = table_context->driver_pptable;
>
> @@ -629,6 +631,11 @@ static int navi10_set_default_dpm_table(struct
> smu_context *smu)
> dpm_context->dpm_tables.phy_table.min = driver_ppt-
> >FreqTablePhyclk[0];
> dpm_context->dpm_tables.phy_table.max = driver_ppt-
> >FreqTablePhyclk[NUM_PHYCLK_DPM_LEVELS - 1];
>
> + for (i = 0; i < MAX_PCIE_CONF; i++) {
> + dpm_context->dpm_tables.pcie_table.pcie_gen[i] = driver_ppt-
> >PcieGenSpeed[i];
> + dpm_context->dpm_tables.pcie_table.pcie_lane[i] =
> driver_ppt->PcieLaneCount[i];
> + }
> +
> return 0;
> }
>
> @@ -710,6 +717,11 @@ static int navi10_print_clk_levels(struct smu_context
> *smu,
> struct smu_table_context *table_context = >smu_table;
> od_table = (OverDriveTable_t *)table_context->overdrive_table;
> od_settings = smu->od_settings;
> + uint32_t gen_speed, lane_width;
> + struct smu_dpm_context *smu_dpm = >smu_dpm;
> + struct smu_11_0_dpm_context *dpm_context = smu_dpm-
> >dpm_context;
> + struct amdgpu_device *adev = smu->adev;
> + PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
>
> switch (clk_type) {
> case SMU_GFXCLK:
> @@ -760,6 +772,30 @@ static int navi10_print_clk_levels(struct smu_context
> *smu,
>
> }
> break;
> + case SMU_PCIE:
> + gen_speed = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
> +
>
RE: [PATCH] drm/amd/powerplay: issue BTC on Navi during SMU setup
Reviewed-by: Kenneth Feng
-Original Message-
From: amd-gfx On Behalf Of Evan Quan
Sent: Tuesday, November 12, 2019 2:37 PM
To: amd-gfx@lists.freedesktop.org
Cc: Quan, Evan
Subject: [PATCH] drm/amd/powerplay: issue BTC on Navi during SMU setup
[CAUTION: External Email]
RunBTC is added for Navi ASIC on hardware setup.
Change-Id: I1c04b481ed14d5f12c20b7b0d592b62a65889e4a
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 010be21bee5b..433acb0f459d 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -1652,6 +1652,16 @@ static int navi10_update_pcie_parameters(struct
smu_context *smu,
return ret;
}
+static int navi10_run_btc(struct smu_context *smu) {
+ int ret = 0;
+
+ ret = smu_send_smc_msg(smu, SMU_MSG_RunBtc);
+ if (ret)
+ pr_err("RunBtc failed!\n");
+
+ return ret;
+}
static const struct pptable_funcs navi10_ppt_funcs = {
.tables_init = navi10_tables_init, @@ -1741,6 +1751,7 @@ static const
struct pptable_funcs navi10_ppt_funcs = {
.get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
.set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
.override_pcie_parameters = smu_v11_0_override_pcie_parameters,
+ .run_btc = navi10_run_btc,
};
void navi10_set_ppt_funcs(struct smu_context *smu)
--
2.24.0
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Re: [PATCH -next] drm/amd/display: Fix old-style declaration
On Mon, 2019-11-11 at 20:28 +0800, YueHaibing wrote:
> Fix a build warning:
>
> drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:75:1:
> warning: 'static' is not at beginning of declaration
> [-Wold-style-declaration]
[]
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
> b/drivers/gpu/drm/amd/display/dc/core/dc.c
[]
> @@ -69,7 +69,7 @@
> #define DC_LOGGER \
> dc->ctx->logger
>
> -const static char DC_BUILD_ID[] = "production-build";
> +static const char DC_BUILD_ID[] = "production-build";
DC_BUILD_ID is used exactly once.
Maybe just use it directly and remove DC_BUILD_ID instead?
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 1fdba13..803dc14 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -69,8 +69,6 @@
#define DC_LOGGER \
dc->ctx->logger
-const static char DC_BUILD_ID[] = "production-build";
-
/**
* DOC: Overview
*
@@ -815,7 +813,7 @@ struct dc *dc_create(const struct dc_init_data *init_params)
if (dc->res_pool->dmcu != NULL)
dc->versions.dmcu_version = dc->res_pool->dmcu->dmcu_version;
- dc->build_id = DC_BUILD_ID;
+ dc->build_id = "production-build";
DC_LOG_DC("Display Core initialized\n");
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Re: [PATCH -next] drm/amd/display: Fix old-style declaration
On 2019/11/12 10:39, Joe Perches wrote:
> On Mon, 2019-11-11 at 20:28 +0800, YueHaibing wrote:
>> Fix a build warning:
>>
>> drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:75:1:
>> warning: 'static' is not at beginning of declaration
>> [-Wold-style-declaration]
> []
>> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
>> b/drivers/gpu/drm/amd/display/dc/core/dc.c
> []
>> @@ -69,7 +69,7 @@
>> #define DC_LOGGER \
>> dc->ctx->logger
>>
>> -const static char DC_BUILD_ID[] = "production-build";
>> +static const char DC_BUILD_ID[] = "production-build";
>
> DC_BUILD_ID is used exactly once.
> Maybe just use it directly and remove DC_BUILD_ID instead?
commit be61df574256ae8c0dbd45ac148ca7260a0483c0
Author: Jun Lei
Date: Thu Sep 13 09:32:26 2018 -0400
drm/amd/display: Add DC build_id to determine build type
[why]
Sometimes there are indications that the incorrect driver is being
loaded in automated tests. This change adds the ability for builds to
be tagged with a string, and picked up by the test infrastructure.
[how]
dc.c will allocate const for build id, which is init-ed with default
value, indicating production build. For test builds, build server will
find/replace this value. The test machine will then verify this value.
It seems DC_BUILD_ID is used by the build server, so maybe we should keep it.
>
> ---
> drivers/gpu/drm/amd/display/dc/core/dc.c | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
> b/drivers/gpu/drm/amd/display/dc/core/dc.c
> index 1fdba13..803dc14 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
> @@ -69,8 +69,6 @@
> #define DC_LOGGER \
> dc->ctx->logger
>
> -const static char DC_BUILD_ID[] = "production-build";
> -
> /**
> * DOC: Overview
> *
> @@ -815,7 +813,7 @@ struct dc *dc_create(const struct dc_init_data
> *init_params)
> if (dc->res_pool->dmcu != NULL)
> dc->versions.dmcu_version = dc->res_pool->dmcu->dmcu_version;
>
> - dc->build_id = DC_BUILD_ID;
> + dc->build_id = "production-build";
>
> DC_LOG_DC("Display Core initialized\n");
>
>
>
>
> .
>
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[PATCH v2 -next] drm/amd/display: remove set but not used variable 'bpc'
Fixes gcc '-Wunused-but-set-variable' warning:
drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link.c: In function
get_pbn_from_timing:
drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link.c:2364:11: warning:
variable bpc set but not used [-Wunused-but-set-variable]
It is not used since commit e49f69363adf ("drm/amd/display: use
proper formula to calculate bandwidth from timing"), this also
remove get_color_depth(), which is only used here.
Signed-off-by: YueHaibing
---
v2: also remove unused get_color_depth()
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 15 ---
1 file changed, 15 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index bdc8be3..1be4277 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -2638,28 +2638,13 @@ static struct fixed31_32 get_pbn_per_slot(struct
dc_stream_state *stream)
return dc_fixpt_div_int(mbytes_per_sec, 54);
}
-static int get_color_depth(enum dc_color_depth color_depth)
-{
- switch (color_depth) {
- case COLOR_DEPTH_666: return 6;
- case COLOR_DEPTH_888: return 8;
- case COLOR_DEPTH_101010: return 10;
- case COLOR_DEPTH_121212: return 12;
- case COLOR_DEPTH_141414: return 14;
- case COLOR_DEPTH_161616: return 16;
- default: return 0;
- }
-}
-
static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx)
{
- uint32_t bpc;
uint64_t kbps;
struct fixed31_32 peak_kbps;
uint32_t numerator;
uint32_t denominator;
- bpc = get_color_depth(pipe_ctx->stream_res.pix_clk_params.color_depth);
kbps = dc_bandwidth_in_kbps_from_timing(_ctx->stream->timing);
/*
--
2.7.4
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[PATCH] drm/amd/powerplay: read pcie speed/width info
sysfs interface to read pcie speed info on navi1x.
Signed-off-by: Kenneth Feng
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 10 +++---
drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 8 +
drivers/gpu/drm/amd/powerplay/navi10_ppt.c| 50 ++-
drivers/gpu/drm/amd/powerplay/navi10_ppt.h| 3 ++
4 files changed, 66 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 57459a6..69243a8 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -1068,10 +1068,6 @@ static int smu_smc_table_hw_init(struct smu_context *smu,
return ret;
if (adev->asic_type != CHIP_ARCTURUS) {
- ret = smu_override_pcie_parameters(smu);
- if (ret)
- return ret;
-
ret = smu_notify_display_change(smu);
if (ret)
return ret;
@@ -1100,6 +1096,12 @@ static int smu_smc_table_hw_init(struct smu_context *smu,
return ret;
}
+ if (adev->asic_type != CHIP_ARCTURUS) {
+ ret = smu_override_pcie_parameters(smu);
+ if (ret)
+ return ret;
+ }
+
ret = smu_set_default_od_settings(smu, initialize);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
index 0ba7a72..6061490 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
@@ -48,6 +48,8 @@
#define SMU11_TOOL_SIZE0x19000
+#define MAX_PCIE_CONF 2
+
#define CLK_MAP(clk, index) \
[SMU_##clk] = {1, (index)}
@@ -88,6 +90,11 @@ struct smu_11_0_dpm_table {
uint32_tmax;/* MHz */
};
+struct smu_11_0_pcie_table {
+uint8_t pcie_gen[MAX_PCIE_CONF];
+uint8_t pcie_lane[MAX_PCIE_CONF];
+};
+
struct smu_11_0_dpm_tables {
struct smu_11_0_dpm_tablesoc_table;
struct smu_11_0_dpm_tablegfx_table;
@@ -100,6 +107,7 @@ struct smu_11_0_dpm_tables {
struct smu_11_0_dpm_tabledisplay_table;
struct smu_11_0_dpm_tablephy_table;
struct smu_11_0_dpm_tablefclk_table;
+ struct smu_11_0_pcie_table pcie_table;
};
struct smu_11_0_dpm_context {
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 36cf313..8855bcc 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -36,6 +36,7 @@
#include "navi10_ppt.h"
#include "smu_v11_0_pptable.h"
#include "smu_v11_0_ppsmc.h"
+#include "nbio/nbio_7_4_sh_mask.h"
#include "asic_reg/mp/mp_11_0_sh_mask.h"
@@ -599,6 +600,7 @@ static int navi10_set_default_dpm_table(struct smu_context
*smu)
struct smu_table_context *table_context = >smu_table;
struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
PPTable_t *driver_ppt = NULL;
+ int i;
driver_ppt = table_context->driver_pptable;
@@ -629,6 +631,11 @@ static int navi10_set_default_dpm_table(struct smu_context
*smu)
dpm_context->dpm_tables.phy_table.min = driver_ppt->FreqTablePhyclk[0];
dpm_context->dpm_tables.phy_table.max =
driver_ppt->FreqTablePhyclk[NUM_PHYCLK_DPM_LEVELS - 1];
+ for (i = 0; i < MAX_PCIE_CONF; i++) {
+ dpm_context->dpm_tables.pcie_table.pcie_gen[i] =
driver_ppt->PcieGenSpeed[i];
+ dpm_context->dpm_tables.pcie_table.pcie_lane[i] =
driver_ppt->PcieLaneCount[i];
+ }
+
return 0;
}
@@ -710,6 +717,11 @@ static int navi10_print_clk_levels(struct smu_context *smu,
struct smu_table_context *table_context = >smu_table;
od_table = (OverDriveTable_t *)table_context->overdrive_table;
od_settings = smu->od_settings;
+ uint32_t gen_speed, lane_width;
+ struct smu_dpm_context *smu_dpm = >smu_dpm;
+ struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
+ struct amdgpu_device *adev = smu->adev;
+ PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
switch (clk_type) {
case SMU_GFXCLK:
@@ -760,6 +772,30 @@ static int navi10_print_clk_levels(struct smu_context *smu,
}
break;
+ case SMU_PCIE:
+ gen_speed = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
+
PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
+ >>
PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
+ lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
+ PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
+ >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
+
