RE: [PATCH] drm/amd/powerplay: skip soc clk setting under pp one vf
Reviewed-by : Monk Liu
_
Monk Liu|GPU Virtualization Team |AMD
-Original Message-
From: amd-gfx On Behalf Of Yintian Tao
Sent: Tuesday, December 17, 2019 11:47 AM
To: Deucher, Alexander ; Feng, Kenneth
; Quan, Evan
Cc: amd-gfx@lists.freedesktop.org; Tao, Yintian
Subject: [PATCH] drm/amd/powerplay: skip soc clk setting under pp one vf
Under sriov pp one vf mode, there is no need to set soc clk under pp one vf
because smu firmware will depend on the mclk to set the appropriate soc clk for
it.
Signed-off-by: Yintian Tao
---
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index 148446570e21..92a65e3daff4 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -3538,7 +3538,8 @@ static int vega10_upload_dpm_bootup_level(struct pp_hwmgr
*hwmgr)
if (!data->registry_data.mclk_dpm_key_disabled) {
if (data->smc_state_table.mem_boot_level !=
data->dpm_table.mem_table.dpm_state.soft_min_level) {
- if (data->smc_state_table.mem_boot_level ==
NUM_UCLK_DPM_LEVELS - 1) {
+ if ((data->smc_state_table.mem_boot_level ==
NUM_UCLK_DPM_LEVELS - 1)
+ && hwmgr->not_vf) {
socclk_idx =
vega10_get_soc_index_for_max_uclk(hwmgr);
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSoftMinSocclkByIndex,
--
2.17.1
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RE: [PATCH] drm/amdgpu/smu: fix spelling
Reviewed-by: Evan Quan
> -Original Message-
> From: amd-gfx On Behalf Of Alex
> Deucher
> Sent: Tuesday, December 17, 2019 4:09 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander
> Subject: [PATCH] drm/amdgpu/smu: fix spelling
>
> s/dispaly/display/g
>
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 2 +-
> drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 2 +-
> drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 4 ++--
> drivers/gpu/drm/amd/powerplay/smu_internal.h | 4 ++--
> drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 4 ++--
> 5 files changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> index 67818558..f76a1717ffbd 100644
> --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> @@ -1670,7 +1670,7 @@ int smu_adjust_power_state_dynamic(struct
> smu_context *smu,
> }
>
> if (!skip_display_settings) {
> - ret = smu_notify_smc_dispaly_config(smu);
> + ret = smu_notify_smc_display_config(smu);
> if (ret) {
> pr_err("Failed to notify smc display config!");
> return ret;
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> index ca3fdc6777cf..a7d0ad831491 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> @@ -443,7 +443,7 @@ struct pptable_funcs {
> int (*pre_display_config_changed)(struct smu_context *smu);
> int (*display_config_changed)(struct smu_context *smu);
> int (*apply_clocks_adjust_rules)(struct smu_context *smu);
> - int (*notify_smc_dispaly_config)(struct smu_context *smu);
> + int (*notify_smc_display_config)(struct smu_context *smu);
> int (*force_dpm_limit_value)(struct smu_context *smu, bool highest);
> int (*unforce_dpm_levels)(struct smu_context *smu);
> int (*get_profiling_clk_mask)(struct smu_context *smu, diff --git
> a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> index 15403b7979d6..7b42e72dc939 100644
> --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> @@ -1374,7 +1374,7 @@ static int navi10_get_profiling_clk_mask(struct
> smu_context *smu,
> return ret;
> }
>
> -static int navi10_notify_smc_dispaly_config(struct smu_context *smu)
> +static int navi10_notify_smc_display_config(struct smu_context *smu)
> {
> struct smu_clocks min_clocks = {0};
> struct pp_display_clock_request clock_req; @@ -2047,7 +2047,7 @@
> static const struct pptable_funcs navi10_ppt_funcs = {
> .get_clock_by_type_with_latency =
> navi10_get_clock_by_type_with_latency,
> .pre_display_config_changed = navi10_pre_display_config_changed,
> .display_config_changed = navi10_display_config_changed,
> - .notify_smc_dispaly_config = navi10_notify_smc_dispaly_config,
> + .notify_smc_display_config = navi10_notify_smc_display_config,
> .force_dpm_limit_value = navi10_force_dpm_limit_value,
> .unforce_dpm_levels = navi10_unforce_dpm_levels,
> .is_dpm_running = navi10_is_dpm_running, diff --git
> a/drivers/gpu/drm/amd/powerplay/smu_internal.h
> b/drivers/gpu/drm/amd/powerplay/smu_internal.h
> index 60ce1fccaeb5..77864e4236c4 100644
> --- a/drivers/gpu/drm/amd/powerplay/smu_internal.h
> +++ b/drivers/gpu/drm/amd/powerplay/smu_internal.h
> @@ -129,8 +129,8 @@ int smu_send_smc_msg(struct smu_context *smu,
> enum smu_message_type msg);
> ((smu)->ppt_funcs->display_config_changed ? (smu)->ppt_funcs-
> >display_config_changed((smu)) : 0) #define
> smu_apply_clocks_adjust_rules(smu) \
> ((smu)->ppt_funcs->apply_clocks_adjust_rules ? (smu)->ppt_funcs-
> >apply_clocks_adjust_rules((smu)) : 0) -#define
> smu_notify_smc_dispaly_config(smu) \
> - ((smu)->ppt_funcs->notify_smc_dispaly_config ? (smu)->ppt_funcs-
> >notify_smc_dispaly_config((smu)) : 0)
> +#define smu_notify_smc_display_config(smu) \
> + ((smu)->ppt_funcs->notify_smc_display_config ?
> +(smu)->ppt_funcs->notify_smc_display_config((smu)) : 0)
> #define smu_force_dpm_limit_value(smu, highest) \
> ((smu)->ppt_funcs->force_dpm_limit_value ? (smu)->ppt_funcs-
> >force_dpm_limit_value((smu), (highest)) : 0) #define
> smu_unforce_dpm_levels(smu) \ diff --git
> a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
> b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
> index 12bcc3e3ba99..2b1c3f8a0415 100644
> --- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
> @@ -2232,7 +2232,7 @@ static int vega20_apply_clocks_adjust_rules(struct
> smu_context *smu) }
>
> static int
> -vega20_notify_smc_dispaly_config(struct smu_context *smu)
> +vega20_notify_smc_display_config(struct smu_
[PATCH] drm/amd/powerplay: skip soc clk setting under pp one vf
Under sriov pp one vf mode, there is no need to set
soc clk under pp one vf because smu firmware will depend
on the mclk to set the appropriate soc clk for it.
Signed-off-by: Yintian Tao
---
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index 148446570e21..92a65e3daff4 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -3538,7 +3538,8 @@ static int vega10_upload_dpm_bootup_level(struct pp_hwmgr
*hwmgr)
if (!data->registry_data.mclk_dpm_key_disabled) {
if (data->smc_state_table.mem_boot_level !=
data->dpm_table.mem_table.dpm_state.soft_min_level) {
- if (data->smc_state_table.mem_boot_level ==
NUM_UCLK_DPM_LEVELS - 1) {
+ if ((data->smc_state_table.mem_boot_level ==
NUM_UCLK_DPM_LEVELS - 1)
+ && hwmgr->not_vf) {
socclk_idx =
vega10_get_soc_index_for_max_uclk(hwmgr);
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSoftMinSocclkByIndex,
--
2.17.1
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Re: [PATCH] amd/amdgpu: add missing break statement
On Mon, Dec 16, 2019 at 4:29 PM Nirmoy Das wrote: > > Fixes: 8c066a8c7a9ac9a66 (amd/amdgpu: add sched array to IPs with multiple > run-queues) > > Signed-off-by: Nirmoy Das Reviewed-by: Alex Deucher > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c > index f5fe60465524..63f6365312d5 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c > @@ -160,6 +160,7 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev, > case AMDGPU_HW_IP_VCN_ENC: > scheds = adev->vcn.vcn_enc_sched; > num_scheds = adev->vcn.num_vcn_enc_sched; > + break; > case AMDGPU_HW_IP_VCN_JPEG: > scheds = adev->jpeg.jpeg_sched; > num_scheds = adev->jpeg.num_jpeg_sched; > -- > 2.24.0 > > ___ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] amd/amdgpu: add missing break statement
Fixes: 8c066a8c7a9ac9a66 (amd/amdgpu: add sched array to IPs with multiple run-queues) Signed-off-by: Nirmoy Das --- drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c index f5fe60465524..63f6365312d5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c @@ -160,6 +160,7 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev, case AMDGPU_HW_IP_VCN_ENC: scheds = adev->vcn.vcn_enc_sched; num_scheds = adev->vcn.num_vcn_enc_sched; + break; case AMDGPU_HW_IP_VCN_JPEG: scheds = adev->jpeg.jpeg_sched; num_scheds = adev->jpeg.num_jpeg_sched; -- 2.24.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH 2/3] drm/amdgpu/pm_runtime: update usage count in fence handling
[AMD Official Use Only - Internal Distribution Only]
Regards,
Oak
-Original Message-
From: amd-gfx On Behalf Of Christian
König
Sent: Monday, December 16, 2019 3:25 PM
To: Alex Deucher ; Koenig, Christian
Cc: Deucher, Alexander ; amd-gfx list
Subject: Re: [PATCH 2/3] drm/amdgpu/pm_runtime: update usage count in fence
handling
Am 16.12.19 um 21:22 schrieb Alex Deucher:
> On Mon, Dec 16, 2019 at 3:19 PM Christian König
> wrote:
>> Am 16.12.19 um 18:18 schrieb Alex Deucher:
>>> Increment the usage count in emit fence, and decrement in process
>>> fence to make sure the GPU is always considered in use while there
>>> are fences outstanding. We always wait for the engines to drain in
>>> runtime suspend, but in practice that only covers short lived jobs
>>> for gfx. This should cover us for longer lived fences.
>>>
>>> Signed-off-by: Alex Deucher
>>> ---
>>>drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 6 +-
>>>1 file changed, 5 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
>>> index 377fe20bce23..e9efee04ca23 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
>>> @@ -34,6 +34,7 @@
>>>#include
>>>#include
>>>#include
>>> +#include
>>>
>>>#include
>>>
>>> @@ -154,7 +155,7 @@ int amdgpu_fence_emit(struct amdgpu_ring *ring, struct
>>> dma_fence **f,
>>> seq);
>>>amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
>>> seq, flags | AMDGPU_FENCE_FLAG_INT);
>>> -
>>> + pm_runtime_get_noresume(adev->ddev->dev);
>>>ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask];
>>>if (unlikely(rcu_dereference_protected(*ptr, 1))) {
>>>struct dma_fence *old; @@ -234,6 +235,7 @@ static
>>> void amdgpu_fence_schedule_fallback(struct amdgpu_ring *ring)
>>>bool amdgpu_fence_process(struct amdgpu_ring *ring)
>>>{
>>>struct amdgpu_fence_driver *drv = &ring->fence_drv;
>>> + struct amdgpu_device *adev = ring->adev;
>>>uint32_t seq, last_seq;
>>>int r;
>>>
>>> @@ -274,6 +276,8 @@ bool amdgpu_fence_process(struct amdgpu_ring *ring)
>>>BUG();
>>>
>>>dma_fence_put(fence);
>>> + pm_runtime_mark_last_busy(adev->ddev->dev);
>>> + pm_runtime_put_autosuspend(adev->ddev->dev);
>> Are you sure this is ok? Keep in mind that this function is called in
>> interrupt context.
> According to:
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.
> kernel.org%2Fdoc%2FDocumentation%2Fpower%2Fruntime_pm.txt&data=02%
> 7C01%7Coak.zeng%40amd.com%7C7008cf5373094160552b08d78266032d%7C3dd8961
> fe4884e608e11a82d994e183d%7C0%7C0%7C637121247082078997&sdata=kfUKc
> dw0PSXWspOBfXQT6BF4r4q3m64cPMbkX7xjOaA%3D&reserved=0
> it's ok to call those in an interrupt context.
In this case the patch is Reviewed-by: Christian König
.
[Oak] Yes, pm_runtime_put_autosuspend calls __pm_runtime_suspend in the
rpmflags set to RPM_ASYNC flag so it can be called in atomic context.
Christian.
>
> Alex
>
>> Christian.
>>
>>>} while (last_seq != seq);
>>>
>>>return true;
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Re: [PATCH 2/3] drm/amdgpu/pm_runtime: update usage count in fence handling
Am 16.12.19 um 21:22 schrieb Alex Deucher:
On Mon, Dec 16, 2019 at 3:19 PM Christian König
wrote:
Am 16.12.19 um 18:18 schrieb Alex Deucher:
Increment the usage count in emit fence, and decrement in
process fence to make sure the GPU is always considered in
use while there are fences outstanding. We always wait for
the engines to drain in runtime suspend, but in practice
that only covers short lived jobs for gfx. This should
cover us for longer lived fences.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
index 377fe20bce23..e9efee04ca23 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
@@ -34,6 +34,7 @@
#include
#include
#include
+#include
#include
@@ -154,7 +155,7 @@ int amdgpu_fence_emit(struct amdgpu_ring *ring, struct
dma_fence **f,
seq);
amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
seq, flags | AMDGPU_FENCE_FLAG_INT);
-
+ pm_runtime_get_noresume(adev->ddev->dev);
ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask];
if (unlikely(rcu_dereference_protected(*ptr, 1))) {
struct dma_fence *old;
@@ -234,6 +235,7 @@ static void amdgpu_fence_schedule_fallback(struct
amdgpu_ring *ring)
bool amdgpu_fence_process(struct amdgpu_ring *ring)
{
struct amdgpu_fence_driver *drv = &ring->fence_drv;
+ struct amdgpu_device *adev = ring->adev;
uint32_t seq, last_seq;
int r;
@@ -274,6 +276,8 @@ bool amdgpu_fence_process(struct amdgpu_ring *ring)
BUG();
dma_fence_put(fence);
+ pm_runtime_mark_last_busy(adev->ddev->dev);
+ pm_runtime_put_autosuspend(adev->ddev->dev);
Are you sure this is ok? Keep in mind that this function is called in
interrupt context.
According to:
https://www.kernel.org/doc/Documentation/power/runtime_pm.txt
it's ok to call those in an interrupt context.
In this case the patch is Reviewed-by: Christian König
.
Christian.
Alex
Christian.
} while (last_seq != seq);
return true;
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Re: [PATCH] drm/amdkfd: Improve function get_sdma_rlc_reg_offset()
Am 16.12.19 um 21:13 schrieb Felix Kuehling:
On 2019-12-16 3:06 p.m., Zhao, Yong wrote:
[AMD Official Use Only - Internal Distribution Only]
The problem happens when we want to reuse the same function for ASICs
which have fewer SDMA engines. Some pointers on which
SOC15_REG_OFFSET depends for some higher index SDMA engines are 0,
causing NULL pointer.
The only way to do that would be to copy the code into another source
file that includes different register headers. At that time you can
update the code to support fewer SDMA engines in the new source file.
There is no need to change this Arturus-specific source file.
A pretty fundamental design decision for amdgpu is that we want to
duplicate the code for each hardware generation even if that means we
end up with a lot of identical/similar code.
The reason for this is that we have so many hardware generation specific
workarounds and we don't want to break older generations when there is a
new issue found on new ones.
Regards,
Christian.
Regards,
Felix
I will fix the default case in switch.
Yong
*From:* Kuehling, Felix
*Sent:* Monday, December 16, 2019 2:39 PM
*To:* Zhao, Yong ; amd-gfx@lists.freedesktop.org
*Subject:* Re: [PATCH] drm/amdkfd: Improve function
get_sdma_rlc_reg_offset()
On 2019-12-13 8:38, Yong Zhao wrote:
> This prevents the NULL pointer access when there are fewer than 8 sdma
> engines.
I don't see where you got a NULL pointer in the old code. Also this
change is in an Arcturus-specific source file. AFAIK Arcturus always has
8 SDMA engines.
The new code is much longer than the old code. I don't see how that's an
improvement. See one more comment inline.
>
> Change-Id: Iabae9bff7546b344720905d5d4a5cfc066a79d25
> Signed-off-by: Yong Zhao
> ---
> .../drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c | 64
---
> 1 file changed, 42 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
> index 3c119407dc34..2ad088f10493 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
> @@ -71,32 +71,52 @@ static uint32_t get_sdma_rlc_reg_offset(struct
amdgpu_device *adev,
> unsigned int engine_id,
> unsigned int queue_id)
> {
> - uint32_t sdma_engine_reg_base[8] = {
> - SOC15_REG_OFFSET(SDMA0, 0,
> - mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL,
> - SOC15_REG_OFFSET(SDMA1, 0,
> - mmSDMA1_RLC0_RB_CNTL) - mmSDMA1_RLC0_RB_CNTL,
> - SOC15_REG_OFFSET(SDMA2, 0,
> - mmSDMA2_RLC0_RB_CNTL) - mmSDMA2_RLC0_RB_CNTL,
> - SOC15_REG_OFFSET(SDMA3, 0,
> - mmSDMA3_RLC0_RB_CNTL) - mmSDMA3_RLC0_RB_CNTL,
> - SOC15_REG_OFFSET(SDMA4, 0,
> - mmSDMA4_RLC0_RB_CNTL) - mmSDMA4_RLC0_RB_CNTL,
> - SOC15_REG_OFFSET(SDMA5, 0,
> - mmSDMA5_RLC0_RB_CNTL) - mmSDMA5_RLC0_RB_CNTL,
> - SOC15_REG_OFFSET(SDMA6, 0,
> - mmSDMA6_RLC0_RB_CNTL) - mmSDMA6_RLC0_RB_CNTL,
> - SOC15_REG_OFFSET(SDMA7, 0,
> - mmSDMA7_RLC0_RB_CNTL) - mmSDMA7_RLC0_RB_CNTL
> - };
> -
> - uint32_t retval = sdma_engine_reg_base[engine_id]
I'm not sure where you were getting a NULL pointer, but I guess this
could have used a range check to make sure engine_id is < 8 before
indexing into the array. The equivalent in the switch statement would be
a default case. See below.
> + uint32_t sdma_engine_reg_base;
> + uint32_t sdma_rlc_reg_offset;
> +
> + switch (engine_id) {
> + case 0:
> + sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0,
> + mmSDMA0_RLC0_RB_CNTL) -
mmSDMA0_RLC0_RB_CNTL;
> + break;
> + case 1:
> + sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA1, 0,
> + mmSDMA1_RLC0_RB_CNTL) -
mmSDMA1_RLC0_RB_CNTL;
> + break;
> + case 2:
> + sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA2, 0,
> + mmSDMA2_RLC0_RB_CNTL) -
mmSDMA2_RLC0_RB_CNTL;
> + break;
> + case 3:
> + sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA3, 0,
> + mmSDMA3_RLC0_RB_CNTL) -
mmSDMA3_RLC0_RB_CNTL;
> + break;
> + case 4:
> + sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA4, 0,
> + mmSDMA4_RLC0_RB_CNTL) -
mmSDMA4_RLC0_RB_CNTL;
> + break;
> + case 5:
> + sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA5, 0,
> + mmSDMA5_RLC0_RB_CNTL) -
mmSDMA5_RLC0_RB_CNTL;
> + break;
> + case 6:
> + sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA6, 0,
> + mmSDMA6_RLC0_RB_CNTL) -
mmSDMA6_RLC0_RB_CNTL;
> + break;
> + c
Re: [PATCH 2/3] drm/amdgpu/pm_runtime: update usage count in fence handling
On Mon, Dec 16, 2019 at 3:19 PM Christian König
wrote:
>
> Am 16.12.19 um 18:18 schrieb Alex Deucher:
> > Increment the usage count in emit fence, and decrement in
> > process fence to make sure the GPU is always considered in
> > use while there are fences outstanding. We always wait for
> > the engines to drain in runtime suspend, but in practice
> > that only covers short lived jobs for gfx. This should
> > cover us for longer lived fences.
> >
> > Signed-off-by: Alex Deucher
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 6 +-
> > 1 file changed, 5 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
> > index 377fe20bce23..e9efee04ca23 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
> > @@ -34,6 +34,7 @@
> > #include
> > #include
> > #include
> > +#include
> >
> > #include
> >
> > @@ -154,7 +155,7 @@ int amdgpu_fence_emit(struct amdgpu_ring *ring, struct
> > dma_fence **f,
> > seq);
> > amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
> > seq, flags | AMDGPU_FENCE_FLAG_INT);
> > -
> > + pm_runtime_get_noresume(adev->ddev->dev);
> > ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask];
> > if (unlikely(rcu_dereference_protected(*ptr, 1))) {
> > struct dma_fence *old;
> > @@ -234,6 +235,7 @@ static void amdgpu_fence_schedule_fallback(struct
> > amdgpu_ring *ring)
> > bool amdgpu_fence_process(struct amdgpu_ring *ring)
> > {
> > struct amdgpu_fence_driver *drv = &ring->fence_drv;
> > + struct amdgpu_device *adev = ring->adev;
> > uint32_t seq, last_seq;
> > int r;
> >
> > @@ -274,6 +276,8 @@ bool amdgpu_fence_process(struct amdgpu_ring *ring)
> > BUG();
> >
> > dma_fence_put(fence);
> > + pm_runtime_mark_last_busy(adev->ddev->dev);
> > + pm_runtime_put_autosuspend(adev->ddev->dev);
>
> Are you sure this is ok? Keep in mind that this function is called in
> interrupt context.
According to:
https://www.kernel.org/doc/Documentation/power/runtime_pm.txt
it's ok to call those in an interrupt context.
Alex
>
> Christian.
>
> > } while (last_seq != seq);
> >
> > return true;
>
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Re: [PATCH 2/3] drm/amdgpu/pm_runtime: update usage count in fence handling
Am 16.12.19 um 18:18 schrieb Alex Deucher:
Increment the usage count in emit fence, and decrement in
process fence to make sure the GPU is always considered in
use while there are fences outstanding. We always wait for
the engines to drain in runtime suspend, but in practice
that only covers short lived jobs for gfx. This should
cover us for longer lived fences.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
index 377fe20bce23..e9efee04ca23 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
@@ -34,6 +34,7 @@
#include
#include
#include
+#include
#include
@@ -154,7 +155,7 @@ int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **f,
seq);
amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
seq, flags | AMDGPU_FENCE_FLAG_INT);
-
+ pm_runtime_get_noresume(adev->ddev->dev);
ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask];
if (unlikely(rcu_dereference_protected(*ptr, 1))) {
struct dma_fence *old;
@@ -234,6 +235,7 @@ static void amdgpu_fence_schedule_fallback(struct
amdgpu_ring *ring)
bool amdgpu_fence_process(struct amdgpu_ring *ring)
{
struct amdgpu_fence_driver *drv = &ring->fence_drv;
+ struct amdgpu_device *adev = ring->adev;
uint32_t seq, last_seq;
int r;
@@ -274,6 +276,8 @@ bool amdgpu_fence_process(struct amdgpu_ring *ring)
BUG();
dma_fence_put(fence);
+ pm_runtime_mark_last_busy(adev->ddev->dev);
+ pm_runtime_put_autosuspend(adev->ddev->dev);
Are you sure this is ok? Keep in mind that this function is called in
interrupt context.
Christian.
} while (last_seq != seq);
return true;
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Re: [PATCH] drm/amdgpu/vcn: remove unnecessary included headers
On Mon, Dec 16, 2019 at 3:15 PM Leo Liu wrote: > > Esp. VCN1.0 headers should not be here > > v2: add back the to keep consistent. > > Signed-off-by: Leo Liu Reviewed-by: Alex Deucher > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 6 -- > 1 file changed, 6 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c > index e522025430c7..623b9f9ef1ea 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c > @@ -28,16 +28,10 @@ > #include > #include > > -#include > - > #include "amdgpu.h" > #include "amdgpu_pm.h" > #include "amdgpu_vcn.h" > #include "soc15d.h" > -#include "soc15_common.h" > - > -#include "vcn/vcn_1_0_offset.h" > -#include "vcn/vcn_1_0_sh_mask.h" > > /* Firmware Names */ > #define FIRMWARE_RAVEN "amdgpu/raven_vcn.bin" > -- > 2.17.1 > > ___ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu/vcn: remove unnecessary included headers
Esp. VCN1.0 headers should not be here v2: add back the to keep consistent. Signed-off-by: Leo Liu --- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 6 -- 1 file changed, 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c index e522025430c7..623b9f9ef1ea 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c @@ -28,16 +28,10 @@ #include #include -#include - #include "amdgpu.h" #include "amdgpu_pm.h" #include "amdgpu_vcn.h" #include "soc15d.h" -#include "soc15_common.h" - -#include "vcn/vcn_1_0_offset.h" -#include "vcn/vcn_1_0_sh_mask.h" /* Firmware Names */ #define FIRMWARE_RAVEN "amdgpu/raven_vcn.bin" -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdkfd: Improve function get_sdma_rlc_reg_offset()
On 2019-12-16 3:06 p.m., Zhao, Yong wrote:
[AMD Official Use Only - Internal Distribution Only]
The problem happens when we want to reuse the same function for ASICs
which have fewer SDMA engines. Some pointers on which SOC15_REG_OFFSET
depends for some higher index SDMA engines are 0, causing NULL pointer.
The only way to do that would be to copy the code into another source
file that includes different register headers. At that time you can
update the code to support fewer SDMA engines in the new source file.
There is no need to change this Arturus-specific source file.
Regards,
Felix
I will fix the default case in switch.
Yong
*From:* Kuehling, Felix
*Sent:* Monday, December 16, 2019 2:39 PM
*To:* Zhao, Yong ; amd-gfx@lists.freedesktop.org
*Subject:* Re: [PATCH] drm/amdkfd: Improve function
get_sdma_rlc_reg_offset()
On 2019-12-13 8:38, Yong Zhao wrote:
> This prevents the NULL pointer access when there are fewer than 8 sdma
> engines.
I don't see where you got a NULL pointer in the old code. Also this
change is in an Arcturus-specific source file. AFAIK Arcturus always has
8 SDMA engines.
The new code is much longer than the old code. I don't see how that's an
improvement. See one more comment inline.
>
> Change-Id: Iabae9bff7546b344720905d5d4a5cfc066a79d25
> Signed-off-by: Yong Zhao
> ---
> .../drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c | 64 ---
> 1 file changed, 42 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
> index 3c119407dc34..2ad088f10493 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
> @@ -71,32 +71,52 @@ static uint32_t get_sdma_rlc_reg_offset(struct
amdgpu_device *adev,
> unsigned int engine_id,
> unsigned int queue_id)
> {
> - uint32_t sdma_engine_reg_base[8] = {
> - SOC15_REG_OFFSET(SDMA0, 0,
> - mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL,
> - SOC15_REG_OFFSET(SDMA1, 0,
> - mmSDMA1_RLC0_RB_CNTL) - mmSDMA1_RLC0_RB_CNTL,
> - SOC15_REG_OFFSET(SDMA2, 0,
> - mmSDMA2_RLC0_RB_CNTL) - mmSDMA2_RLC0_RB_CNTL,
> - SOC15_REG_OFFSET(SDMA3, 0,
> - mmSDMA3_RLC0_RB_CNTL) - mmSDMA3_RLC0_RB_CNTL,
> - SOC15_REG_OFFSET(SDMA4, 0,
> - mmSDMA4_RLC0_RB_CNTL) - mmSDMA4_RLC0_RB_CNTL,
> - SOC15_REG_OFFSET(SDMA5, 0,
> - mmSDMA5_RLC0_RB_CNTL) - mmSDMA5_RLC0_RB_CNTL,
> - SOC15_REG_OFFSET(SDMA6, 0,
> - mmSDMA6_RLC0_RB_CNTL) - mmSDMA6_RLC0_RB_CNTL,
> - SOC15_REG_OFFSET(SDMA7, 0,
> - mmSDMA7_RLC0_RB_CNTL) - mmSDMA7_RLC0_RB_CNTL
> - };
> -
> - uint32_t retval = sdma_engine_reg_base[engine_id]
I'm not sure where you were getting a NULL pointer, but I guess this
could have used a range check to make sure engine_id is < 8 before
indexing into the array. The equivalent in the switch statement would be
a default case. See below.
> + uint32_t sdma_engine_reg_base;
> + uint32_t sdma_rlc_reg_offset;
> +
> + switch (engine_id) {
> + case 0:
> + sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0,
> + mmSDMA0_RLC0_RB_CNTL) -
mmSDMA0_RLC0_RB_CNTL;
> + break;
> + case 1:
> + sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA1, 0,
> + mmSDMA1_RLC0_RB_CNTL) -
mmSDMA1_RLC0_RB_CNTL;
> + break;
> + case 2:
> + sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA2, 0,
> + mmSDMA2_RLC0_RB_CNTL) -
mmSDMA2_RLC0_RB_CNTL;
> + break;
> + case 3:
> + sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA3, 0,
> + mmSDMA3_RLC0_RB_CNTL) -
mmSDMA3_RLC0_RB_CNTL;
> + break;
> + case 4:
> + sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA4, 0,
> + mmSDMA4_RLC0_RB_CNTL) -
mmSDMA4_RLC0_RB_CNTL;
> + break;
> + case 5:
> + sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA5, 0,
> + mmSDMA5_RLC0_RB_CNTL) -
mmSDMA5_RLC0_RB_CNTL;
> + break;
> + case 6:
> + sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA6, 0,
> + mmSDMA6_RLC0_RB_CNTL) -
mmSDMA6_RLC0_RB_CNTL;
> + break;
> + case 7:
> + sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA7, 0,
> + mmSDMA7_RLC0_RB_CNTL) -
mmSDMA7_RLC0_RB_CNTL;
> + break;
> +
Do you need a default case for the switch statement? I think you get a
compiler warning without one.
Regards,
Felix
> + }
> +
> + sdma_rlc_reg_offset = sdma_engine_reg_base
> + queue_id * (mmSDMA0_RLC1_RB_CNTL -
mmSDMA0_RLC0_R
Re: [PATCH] drm/amdgpu/vcn: remove unnecessary included headers
Hi Alex, I searched and found why it get built okay: amdgpu.h includes amdgpu_mode.h, and that include linux/i2c.h. And linux/i2c.h includes linux/acpi.h and that includes linux/modules.h. Tested it by commenting out linux/modules.h from linux/acpi.h, then the build for amdgpu.ko would fail at the MODULE_FIRMWARE for VCN. So in order to keep it consistent, and I will send v2 to keep Regards, Leo On 2019-12-16 11:50 a.m., Leo Liu wrote: On 2019-12-16 11:36 a.m., Alex Deucher wrote: On Mon, Dec 16, 2019 at 11:06 AM Leo Liu wrote: Esp. VCN1.0 headers should not be here Signed-off-by: Leo Liu --- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 7 --- 1 file changed, 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c index e522025430c7..371f55de42dc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c @@ -25,19 +25,12 @@ */ #include -#include Don't we still need module.h for MODULE_FIRMWARE()? It's got built okay by removing it. I will keep it anyway. Regards, Leo Alex #include -#include - #include "amdgpu.h" #include "amdgpu_pm.h" #include "amdgpu_vcn.h" #include "soc15d.h" -#include "soc15_common.h" - -#include "vcn/vcn_1_0_offset.h" -#include "vcn/vcn_1_0_sh_mask.h" /* Firmware Names */ #define FIRMWARE_RAVEN "amdgpu/raven_vcn.bin" -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Cleo.liu%40amd.com%7C041e573a661b498216ea08d782481d8e%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637121119112744072&sdata=TtjVEgl%2BB2sprSvHOJvCpZsxXD5jw9WSreusaDoeKmU%3D&reserved=0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Cleo.liu%40amd.com%7C041e573a661b498216ea08d782481d8e%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637121119112744072&sdata=TtjVEgl%2BB2sprSvHOJvCpZsxXD5jw9WSreusaDoeKmU%3D&reserved=0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu/smu: fix spelling
s/dispaly/display/g
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 2 +-
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 2 +-
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 4 ++--
drivers/gpu/drm/amd/powerplay/smu_internal.h | 4 ++--
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 4 ++--
5 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 67818558..f76a1717ffbd 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -1670,7 +1670,7 @@ int smu_adjust_power_state_dynamic(struct smu_context
*smu,
}
if (!skip_display_settings) {
- ret = smu_notify_smc_dispaly_config(smu);
+ ret = smu_notify_smc_display_config(smu);
if (ret) {
pr_err("Failed to notify smc display config!");
return ret;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index ca3fdc6777cf..a7d0ad831491 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -443,7 +443,7 @@ struct pptable_funcs {
int (*pre_display_config_changed)(struct smu_context *smu);
int (*display_config_changed)(struct smu_context *smu);
int (*apply_clocks_adjust_rules)(struct smu_context *smu);
- int (*notify_smc_dispaly_config)(struct smu_context *smu);
+ int (*notify_smc_display_config)(struct smu_context *smu);
int (*force_dpm_limit_value)(struct smu_context *smu, bool highest);
int (*unforce_dpm_levels)(struct smu_context *smu);
int (*get_profiling_clk_mask)(struct smu_context *smu,
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 15403b7979d6..7b42e72dc939 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -1374,7 +1374,7 @@ static int navi10_get_profiling_clk_mask(struct
smu_context *smu,
return ret;
}
-static int navi10_notify_smc_dispaly_config(struct smu_context *smu)
+static int navi10_notify_smc_display_config(struct smu_context *smu)
{
struct smu_clocks min_clocks = {0};
struct pp_display_clock_request clock_req;
@@ -2047,7 +2047,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
.get_clock_by_type_with_latency = navi10_get_clock_by_type_with_latency,
.pre_display_config_changed = navi10_pre_display_config_changed,
.display_config_changed = navi10_display_config_changed,
- .notify_smc_dispaly_config = navi10_notify_smc_dispaly_config,
+ .notify_smc_display_config = navi10_notify_smc_display_config,
.force_dpm_limit_value = navi10_force_dpm_limit_value,
.unforce_dpm_levels = navi10_unforce_dpm_levels,
.is_dpm_running = navi10_is_dpm_running,
diff --git a/drivers/gpu/drm/amd/powerplay/smu_internal.h
b/drivers/gpu/drm/amd/powerplay/smu_internal.h
index 60ce1fccaeb5..77864e4236c4 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_internal.h
+++ b/drivers/gpu/drm/amd/powerplay/smu_internal.h
@@ -129,8 +129,8 @@ int smu_send_smc_msg(struct smu_context *smu, enum
smu_message_type msg);
((smu)->ppt_funcs->display_config_changed ?
(smu)->ppt_funcs->display_config_changed((smu)) : 0)
#define smu_apply_clocks_adjust_rules(smu) \
((smu)->ppt_funcs->apply_clocks_adjust_rules ?
(smu)->ppt_funcs->apply_clocks_adjust_rules((smu)) : 0)
-#define smu_notify_smc_dispaly_config(smu) \
- ((smu)->ppt_funcs->notify_smc_dispaly_config ?
(smu)->ppt_funcs->notify_smc_dispaly_config((smu)) : 0)
+#define smu_notify_smc_display_config(smu) \
+ ((smu)->ppt_funcs->notify_smc_display_config ?
(smu)->ppt_funcs->notify_smc_display_config((smu)) : 0)
#define smu_force_dpm_limit_value(smu, highest) \
((smu)->ppt_funcs->force_dpm_limit_value ?
(smu)->ppt_funcs->force_dpm_limit_value((smu), (highest)) : 0)
#define smu_unforce_dpm_levels(smu) \
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index 12bcc3e3ba99..2b1c3f8a0415 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -2232,7 +2232,7 @@ static int vega20_apply_clocks_adjust_rules(struct
smu_context *smu)
}
static int
-vega20_notify_smc_dispaly_config(struct smu_context *smu)
+vega20_notify_smc_display_config(struct smu_context *smu)
{
struct vega20_dpm_table *dpm_table = smu->smu_dpm.dpm_context;
struct vega20_single_dpm_table *memtable = &dpm_table->mem_table;
@@ -3200,7 +3200,7 @@ static const struct pptable_funcs vega20_ppt_funcs = {
.pre_display_config_changed = vega20_pre_display_config_changed,
.display_config_changed = vega20_display_config_changed,
Re: [PATCH] drm/amdkfd: Improve function get_sdma_rlc_reg_offset()
[AMD Official Use Only - Internal Distribution Only]
The problem happens when we want to reuse the same function for ASICs which
have fewer SDMA engines. Some pointers on which SOC15_REG_OFFSET depends for
some higher index SDMA engines are 0, causing NULL pointer.
I will fix the default case in switch.
Yong
From: Kuehling, Felix
Sent: Monday, December 16, 2019 2:39 PM
To: Zhao, Yong ; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdkfd: Improve function get_sdma_rlc_reg_offset()
On 2019-12-13 8:38, Yong Zhao wrote:
> This prevents the NULL pointer access when there are fewer than 8 sdma
> engines.
I don't see where you got a NULL pointer in the old code. Also this
change is in an Arcturus-specific source file. AFAIK Arcturus always has
8 SDMA engines.
The new code is much longer than the old code. I don't see how that's an
improvement. See one more comment inline.
>
> Change-Id: Iabae9bff7546b344720905d5d4a5cfc066a79d25
> Signed-off-by: Yong Zhao
> ---
> .../drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c | 64 ---
> 1 file changed, 42 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
> index 3c119407dc34..2ad088f10493 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
> @@ -71,32 +71,52 @@ static uint32_t get_sdma_rlc_reg_offset(struct
> amdgpu_device *adev,
>unsigned int engine_id,
>unsigned int queue_id)
> {
> - uint32_t sdma_engine_reg_base[8] = {
> - SOC15_REG_OFFSET(SDMA0, 0,
> - mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL,
> - SOC15_REG_OFFSET(SDMA1, 0,
> - mmSDMA1_RLC0_RB_CNTL) - mmSDMA1_RLC0_RB_CNTL,
> - SOC15_REG_OFFSET(SDMA2, 0,
> - mmSDMA2_RLC0_RB_CNTL) - mmSDMA2_RLC0_RB_CNTL,
> - SOC15_REG_OFFSET(SDMA3, 0,
> - mmSDMA3_RLC0_RB_CNTL) - mmSDMA3_RLC0_RB_CNTL,
> - SOC15_REG_OFFSET(SDMA4, 0,
> - mmSDMA4_RLC0_RB_CNTL) - mmSDMA4_RLC0_RB_CNTL,
> - SOC15_REG_OFFSET(SDMA5, 0,
> - mmSDMA5_RLC0_RB_CNTL) - mmSDMA5_RLC0_RB_CNTL,
> - SOC15_REG_OFFSET(SDMA6, 0,
> - mmSDMA6_RLC0_RB_CNTL) - mmSDMA6_RLC0_RB_CNTL,
> - SOC15_REG_OFFSET(SDMA7, 0,
> - mmSDMA7_RLC0_RB_CNTL) - mmSDMA7_RLC0_RB_CNTL
> - };
> -
> - uint32_t retval = sdma_engine_reg_base[engine_id]
I'm not sure where you were getting a NULL pointer, but I guess this
could have used a range check to make sure engine_id is < 8 before
indexing into the array. The equivalent in the switch statement would be
a default case. See below.
> + uint32_t sdma_engine_reg_base;
> + uint32_t sdma_rlc_reg_offset;
> +
> + switch (engine_id) {
> + case 0:
> + sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0,
> + mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL;
> + break;
> + case 1:
> + sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA1, 0,
> + mmSDMA1_RLC0_RB_CNTL) - mmSDMA1_RLC0_RB_CNTL;
> + break;
> + case 2:
> + sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA2, 0,
> + mmSDMA2_RLC0_RB_CNTL) - mmSDMA2_RLC0_RB_CNTL;
> + break;
> + case 3:
> + sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA3, 0,
> + mmSDMA3_RLC0_RB_CNTL) - mmSDMA3_RLC0_RB_CNTL;
> + break;
> + case 4:
> + sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA4, 0,
> + mmSDMA4_RLC0_RB_CNTL) - mmSDMA4_RLC0_RB_CNTL;
> + break;
> + case 5:
> + sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA5, 0,
> + mmSDMA5_RLC0_RB_CNTL) - mmSDMA5_RLC0_RB_CNTL;
> + break;
> + case 6:
> + sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA6, 0,
> + mmSDMA6_RLC0_RB_CNTL) - mmSDMA6_RLC0_RB_CNTL;
> + break;
> + case 7:
> + sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA7, 0,
> + mmSDMA7_RLC0_RB_CNTL) - mmSDMA7_RLC0_RB_CNTL;
> + break;
> +
Do you need a default case for the switch statement? I think you get a
compiler warning without one.
Regards,
Felix
> + }
> +
> + sdma_rlc_reg_offset = sdma_engine_reg_base
>+ queue_id * (mmSDMA0_RLC1_RB_CNTL - mmSDMA0_RLC0_RB_CNTL);
>
>pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n", engine_id,
> - queue_id, retval);
> + queue_id, sdma_rlc_reg_
Re: [PATCH] drm/amdkfd: Improve function get_sdma_rlc_reg_offset()
On 2019-12-13 8:38, Yong Zhao wrote:
This prevents the NULL pointer access when there are fewer than 8 sdma
engines.
I don't see where you got a NULL pointer in the old code. Also this
change is in an Arcturus-specific source file. AFAIK Arcturus always has
8 SDMA engines.
The new code is much longer than the old code. I don't see how that's an
improvement. See one more comment inline.
Change-Id: Iabae9bff7546b344720905d5d4a5cfc066a79d25
Signed-off-by: Yong Zhao
---
.../drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c | 64 ---
1 file changed, 42 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
index 3c119407dc34..2ad088f10493 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
@@ -71,32 +71,52 @@ static uint32_t get_sdma_rlc_reg_offset(struct
amdgpu_device *adev,
unsigned int engine_id,
unsigned int queue_id)
{
- uint32_t sdma_engine_reg_base[8] = {
- SOC15_REG_OFFSET(SDMA0, 0,
-mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL,
- SOC15_REG_OFFSET(SDMA1, 0,
-mmSDMA1_RLC0_RB_CNTL) - mmSDMA1_RLC0_RB_CNTL,
- SOC15_REG_OFFSET(SDMA2, 0,
-mmSDMA2_RLC0_RB_CNTL) - mmSDMA2_RLC0_RB_CNTL,
- SOC15_REG_OFFSET(SDMA3, 0,
-mmSDMA3_RLC0_RB_CNTL) - mmSDMA3_RLC0_RB_CNTL,
- SOC15_REG_OFFSET(SDMA4, 0,
-mmSDMA4_RLC0_RB_CNTL) - mmSDMA4_RLC0_RB_CNTL,
- SOC15_REG_OFFSET(SDMA5, 0,
-mmSDMA5_RLC0_RB_CNTL) - mmSDMA5_RLC0_RB_CNTL,
- SOC15_REG_OFFSET(SDMA6, 0,
-mmSDMA6_RLC0_RB_CNTL) - mmSDMA6_RLC0_RB_CNTL,
- SOC15_REG_OFFSET(SDMA7, 0,
-mmSDMA7_RLC0_RB_CNTL) - mmSDMA7_RLC0_RB_CNTL
- };
-
- uint32_t retval = sdma_engine_reg_base[engine_id]
I'm not sure where you were getting a NULL pointer, but I guess this
could have used a range check to make sure engine_id is < 8 before
indexing into the array. The equivalent in the switch statement would be
a default case. See below.
+ uint32_t sdma_engine_reg_base;
+ uint32_t sdma_rlc_reg_offset;
+
+ switch (engine_id) {
+ case 0:
+ sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0,
+ mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL;
+ break;
+ case 1:
+ sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA1, 0,
+ mmSDMA1_RLC0_RB_CNTL) - mmSDMA1_RLC0_RB_CNTL;
+ break;
+ case 2:
+ sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA2, 0,
+ mmSDMA2_RLC0_RB_CNTL) - mmSDMA2_RLC0_RB_CNTL;
+ break;
+ case 3:
+ sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA3, 0,
+ mmSDMA3_RLC0_RB_CNTL) - mmSDMA3_RLC0_RB_CNTL;
+ break;
+ case 4:
+ sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA4, 0,
+ mmSDMA4_RLC0_RB_CNTL) - mmSDMA4_RLC0_RB_CNTL;
+ break;
+ case 5:
+ sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA5, 0,
+ mmSDMA5_RLC0_RB_CNTL) - mmSDMA5_RLC0_RB_CNTL;
+ break;
+ case 6:
+ sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA6, 0,
+ mmSDMA6_RLC0_RB_CNTL) - mmSDMA6_RLC0_RB_CNTL;
+ break;
+ case 7:
+ sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA7, 0,
+ mmSDMA7_RLC0_RB_CNTL) - mmSDMA7_RLC0_RB_CNTL;
+ break;
+
Do you need a default case for the switch statement? I think you get a
compiler warning without one.
Regards,
Felix
+ }
+
+ sdma_rlc_reg_offset = sdma_engine_reg_base
+ queue_id * (mmSDMA0_RLC1_RB_CNTL - mmSDMA0_RLC0_RB_CNTL);
pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n", engine_id,
- queue_id, retval);
+ queue_id, sdma_rlc_reg_offset);
- return retval;
+ return sdma_rlc_reg_offset;
}
static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
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RE: [PATCH] drm/amd/powerplay: Add SMU WMTABLE Validity Check for Renoir
[AMD Official Use Only - Internal Distribution Only]
The patch looks good.
Reviewed-by: Hersen Wu
-Original Message-
From: Liu, Zhan
Sent: Friday, December 13, 2019 11:50 AM
To: amd-gfx@lists.freedesktop.org; Wu, Hersen ; Deucher,
Alexander ; Wang, Kevin(Yang) ;
Quan, Evan ; Yin, Tianci (Rico)
Cc: Liu, Zhan
Subject: [PATCH] drm/amd/powerplay: Add SMU WMTABLE Validity Check for Renoir
[Why]
SMU watermark table (WMTABLE) validity check is missing on Renoir. This
validity check is very useful for checking whether WMTABLE is updated
successfully.
[How]
Add SMU watermark validity check.
Signed-off-by: Zhan Liu
---
drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index 89a54f8e08d3..81520b0fca68 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -777,9 +777,17 @@ static int renoir_set_watermarks_table(
}
/* pass data to smu controller */
- ret = smu_write_watermarks_table(smu);
+ if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
+ !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
+ ret = smu_write_watermarks_table(smu);
+ if (ret) {
+ pr_err("Failed to update WMTABLE!");
+ return ret;
+ }
+ smu->watermarks_bitmap |= WATERMARKS_LOADED;
+ }
- return ret;
+ return 0;
}
static int renoir_get_power_profile_mode(struct smu_context *smu,
--
2.17.1
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RE: [PATCH] drm/amd/powerplay: Add SMU WMTABLE Validity Check for Renoir
Ping...
> -Original Message-
> From: Liu, Zhan
> Sent: 2019/December/13, Friday 11:50 AM
> To: amd-gfx@lists.freedesktop.org; Wu, Hersen ;
> Deucher, Alexander ; Wang, Kevin(Yang)
> ; Quan, Evan ; Yin, Tianci
> (Rico)
> Cc: Liu, Zhan
> Subject: [PATCH] drm/amd/powerplay: Add SMU WMTABLE Validity Check
> for Renoir
>
> [Why]
> SMU watermark table (WMTABLE) validity check is missing on Renoir. This
> validity check is very useful for checking whether WMTABLE is updated
> successfully.
>
> [How]
> Add SMU watermark validity check.
>
> Signed-off-by: Zhan Liu
> ---
> drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 12 ++--
> 1 file changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
> b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
> index 89a54f8e08d3..81520b0fca68 100644
> --- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
> @@ -777,9 +777,17 @@ static int renoir_set_watermarks_table(
> }
>
> /* pass data to smu controller */
> - ret = smu_write_watermarks_table(smu);
> + if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
> + !(smu->watermarks_bitmap &
> WATERMARKS_LOADED)) {
> + ret = smu_write_watermarks_table(smu);
> + if (ret) {
> + pr_err("Failed to update WMTABLE!");
> + return ret;
> + }
> + smu->watermarks_bitmap |= WATERMARKS_LOADED;
> + }
>
> - return ret;
> + return 0;
> }
>
> static int renoir_get_power_profile_mode(struct smu_context *smu,
> --
> 2.17.1
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Re: [PATCH 0/3] drm/amdgpu: Remove unneeded semicolon
Applied the series. Thanks! Alex On Sat, Dec 14, 2019 at 9:44 AM zhengbin wrote: > > zhengbin (3): > drm/amdgpu: Remove unneeded semicolon in amdgpu_pmu.c > drm/amdgpu: Remove unneeded semicolon in gfx_v10_0.c > drm/amdgpu: Remove unneeded semicolon in amdgpu_ras.c > > drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c | 8 > drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 2 +- > drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +- > 3 files changed, 6 insertions(+), 6 deletions(-) > > -- > 2.7.4 > > ___ > dri-devel mailing list > dri-de...@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amd/display: Remove unneeded semicolon
On Mon, Dec 16, 2019 at 9:32 AM Harry Wentland wrote: > > On 2019-12-14 4:12 a.m., zhengbin wrote: > > Fixes coccicheck warning: > > > > drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c:412:90-91: > > Unneeded semicolon > > > > Reported-by: Hulk Robot > > Signed-off-by: zhengbin > > Reviewed-by: Harry Wentland > Applied. Thanks! Alex > Harry > > > --- > > drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c > > b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c > > index de51ef1..a1b7e76 100644 > > --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c > > +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c > > @@ -409,7 +409,7 @@ void build_watermark_ranges(struct clk_bw_params > > *bw_params, struct pp_smu_wm_ra > > continue; > > > > ranges->reader_wm_sets[num_valid_sets].wm_inst = > > bw_params->wm_table.entries[i].wm_inst; > > - ranges->reader_wm_sets[num_valid_sets].wm_type = > > bw_params->wm_table.entries[i].wm_type;; > > + ranges->reader_wm_sets[num_valid_sets].wm_type = > > bw_params->wm_table.entries[i].wm_type; > > /* We will not select WM based on dcfclk, so leave it as > > unconstrained */ > > ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz = > > PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; > > ranges->reader_wm_sets[num_valid_sets].max_drain_clk_mhz = > > PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; > > -- > > 2.7.4 > > > ___ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 3/3] drm/amdgpu: Enter low power state if CRTC active.
From: Andrey Grodzovsky
CRTC in DPMS state off calls for low power state entry.
Support both atomic mode setting and pre-atomic mode setting.
v2: move comment
Signed-off-by: Andrey Grodzovsky
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 45 +
1 file changed, 38 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 61dc26515c7e..e7f7463a0cbe 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -1296,24 +1296,55 @@ static int amdgpu_pmops_runtime_idle(struct device *dev)
{
struct drm_device *drm_dev = dev_get_drvdata(dev);
struct amdgpu_device *adev = drm_dev->dev_private;
- struct drm_crtc *crtc;
+ /* we don't want the main rpm_idle to call suspend - we want to
autosuspend */
+ int ret = 1;
if (!adev->runpm) {
pm_runtime_forbid(dev);
return -EBUSY;
}
- list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) {
- if (crtc->enabled) {
- DRM_DEBUG_DRIVER("failing to power off - crtc
active\n");
- return -EBUSY;
+ if (amdgpu_device_has_dc_support(adev)) {
+ struct drm_crtc *crtc;
+
+ drm_modeset_lock_all(drm_dev);
+
+ drm_for_each_crtc(crtc, drm_dev) {
+ if (crtc->state->active) {
+ ret = -EBUSY;
+ break;
+ }
}
+
+ drm_modeset_unlock_all(drm_dev);
+
+ } else {
+ struct drm_connector *list_connector;
+ struct drm_connector_list_iter iter;
+
+ mutex_lock(&drm_dev->mode_config.mutex);
+ drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL);
+
+ drm_connector_list_iter_begin(drm_dev, &iter);
+ drm_for_each_connector_iter(list_connector, &iter) {
+ if (list_connector->dpms == DRM_MODE_DPMS_ON) {
+ ret = -EBUSY;
+ break;
+ }
+ }
+
+ drm_connector_list_iter_end(&iter);
+
+ drm_modeset_unlock(&drm_dev->mode_config.connection_mutex);
+ mutex_unlock(&drm_dev->mode_config.mutex);
}
+ if (ret == -EBUSY)
+ DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
+
pm_runtime_mark_last_busy(dev);
pm_runtime_autosuspend(dev);
- /* we don't want the main rpm_idle to call suspend - we want to
autosuspend */
- return 1;
+ return ret;
}
long amdgpu_drm_ioctl(struct file *filp,
--
2.23.0
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[PATCH 2/3] drm/amdgpu/pm_runtime: update usage count in fence handling
Increment the usage count in emit fence, and decrement in
process fence to make sure the GPU is always considered in
use while there are fences outstanding. We always wait for
the engines to drain in runtime suspend, but in practice
that only covers short lived jobs for gfx. This should
cover us for longer lived fences.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
index 377fe20bce23..e9efee04ca23 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
@@ -34,6 +34,7 @@
#include
#include
#include
+#include
#include
@@ -154,7 +155,7 @@ int amdgpu_fence_emit(struct amdgpu_ring *ring, struct
dma_fence **f,
seq);
amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
seq, flags | AMDGPU_FENCE_FLAG_INT);
-
+ pm_runtime_get_noresume(adev->ddev->dev);
ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask];
if (unlikely(rcu_dereference_protected(*ptr, 1))) {
struct dma_fence *old;
@@ -234,6 +235,7 @@ static void amdgpu_fence_schedule_fallback(struct
amdgpu_ring *ring)
bool amdgpu_fence_process(struct amdgpu_ring *ring)
{
struct amdgpu_fence_driver *drv = &ring->fence_drv;
+ struct amdgpu_device *adev = ring->adev;
uint32_t seq, last_seq;
int r;
@@ -274,6 +276,8 @@ bool amdgpu_fence_process(struct amdgpu_ring *ring)
BUG();
dma_fence_put(fence);
+ pm_runtime_mark_last_busy(adev->ddev->dev);
+ pm_runtime_put_autosuspend(adev->ddev->dev);
} while (last_seq != seq);
return true;
--
2.23.0
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[PATCH 1/3] drm/amdgpu: wait for all rings to drain before runtime suspending
Add a safety check to runtime suspend to make sure all outstanding
fences have signaled before we suspend. Doesn't fix any known issue.
We already do this via the fence driver suspend function, but we
just force completion rather than bailing. This bails on runtime
suspend so we can try again later once the fences are signaled to
avoid missing any outstanding work.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index d1e9946ac218..61dc26515c7e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -1214,13 +1214,23 @@ static int amdgpu_pmops_runtime_suspend(struct device
*dev)
struct pci_dev *pdev = to_pci_dev(dev);
struct drm_device *drm_dev = pci_get_drvdata(pdev);
struct amdgpu_device *adev = drm_dev->dev_private;
- int ret;
+ int ret, i;
if (!adev->runpm) {
pm_runtime_forbid(dev);
return -EBUSY;
}
+ /* wait for all rings to drain before suspending */
+ for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
+ struct amdgpu_ring *ring = adev->rings[i];
+ if (ring && ring->sched.ready) {
+ ret = amdgpu_fence_wait_empty(ring);
+ if (ret)
+ return -EBUSY;
+ }
+ }
+
if (amdgpu_device_supports_boco(drm_dev))
drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
drm_kms_helper_poll_disable(drm_dev);
--
2.23.0
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Re: [PATCH] drm/amdgpu/vcn: remove unnecessary included headers
On 2019-12-16 11:36 a.m., Alex Deucher wrote: On Mon, Dec 16, 2019 at 11:06 AM Leo Liu wrote: Esp. VCN1.0 headers should not be here Signed-off-by: Leo Liu --- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 7 --- 1 file changed, 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c index e522025430c7..371f55de42dc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c @@ -25,19 +25,12 @@ */ #include -#include Don't we still need module.h for MODULE_FIRMWARE()? It's got built okay by removing it. I will keep it anyway. Regards, Leo Alex #include -#include - #include "amdgpu.h" #include "amdgpu_pm.h" #include "amdgpu_vcn.h" #include "soc15d.h" -#include "soc15_common.h" - -#include "vcn/vcn_1_0_offset.h" -#include "vcn/vcn_1_0_sh_mask.h" /* Firmware Names */ #define FIRMWARE_RAVEN "amdgpu/raven_vcn.bin" -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Cleo.liu%40amd.com%7C471b86fd37a94fdefe8008d7824612b5%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637121109780682361&sdata=7rC8gPrHsi5xa8Zsis%2B%2FXH0URESxBb6AQaMgppVGDJs%3D&reserved=0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH v2 1/5] drm/amdgpu: reverts commit b01245ff54db66073b104ac9d9fbefb7b264b36d.
Ping on unreviewed V2s...
Andrey
On 12/13/19 11:54 AM, Andrey Grodzovsky wrote:
In preparation for doing XGMI reset synchronization using task barrier.
Signed-off-by: Andrey Grodzovsky
Reviewed-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 2 -
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 76 +-
2 files changed, 12 insertions(+), 66 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index a78a363..50bab33 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1001,8 +1001,6 @@ struct amdgpu_device {
boolpm_sysfs_en;
boolucode_sysfs_en;
-
- boolin_baco;
};
static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 7324a5f..1d19edfa 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2667,7 +2667,7 @@ static void amdgpu_device_xgmi_reset_func(struct
work_struct *__work)
if (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)
adev->asic_reset_res = (adev->in_baco == false) ?
amdgpu_device_baco_enter(adev->ddev) :
- amdgpu_device_baco_exit(adev->ddev);
+ qamdgpu_device_baco_exit(adev->ddev);
else
adev->asic_reset_res = amdgpu_asic_reset(adev);
@@ -3796,18 +3796,13 @@ static int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
return r;
}
-static int amdgpu_do_asic_reset(struct amdgpu_device *adev,
- struct amdgpu_hive_info *hive,
+static int amdgpu_do_asic_reset(struct amdgpu_hive_info *hive,
struct list_head *device_list_handle,
bool *need_full_reset_arg)
{
struct amdgpu_device *tmp_adev = NULL;
bool need_full_reset = *need_full_reset_arg, vram_lost = false;
int r = 0;
- int cpu = smp_processor_id();
- bool use_baco =
- (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) ?
- true : false;
/*
* ASIC reset has to be done on all HGMI hive nodes ASAP
@@ -3815,62 +3810,22 @@ static int amdgpu_do_asic_reset(struct amdgpu_device
*adev,
*/
if (need_full_reset) {
list_for_each_entry(tmp_adev, device_list_handle,
gmc.xgmi.head) {
- /*
-* For XGMI run all resets in parallel to speed up the
-* process by scheduling the highpri wq on different
-* cpus. For XGMI with baco reset, all nodes must enter
-* baco within close proximity before anyone exit.
-*/
+ /* For XGMI run all resets in parallel to speed up the
process */
if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
- if (!queue_work_on(cpu, system_highpri_wq,
- &tmp_adev->xgmi_reset_work))
+ if (!queue_work(system_highpri_wq,
&tmp_adev->xgmi_reset_work))
r = -EALREADY;
- cpu = cpumask_next(cpu, cpu_online_mask);
} else
r = amdgpu_asic_reset(tmp_adev);
- if (r)
- break;
- }
-
- /* For XGMI wait for all work to complete before proceed */
- if (!r) {
- list_for_each_entry(tmp_adev, device_list_handle,
- gmc.xgmi.head) {
- if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
- flush_work(&tmp_adev->xgmi_reset_work);
- r = tmp_adev->asic_reset_res;
- if (r)
- break;
- if (use_baco)
- tmp_adev->in_baco = true;
- }
- }
- }
- /*
-* For XGMI with baco reset, need exit baco phase by scheduling
-* xgmi_reset_work one more time. PSP reset and sGPU skips this
-* phase. Not assume the situation that PSP reset and baco reset
-* coexist within an XGMI hive.
-*/
-
- if (!r && use_baco) {
- cpu = smp_processor_id();
- list_for_each_
Re: [PATCH] drm/amdgpu/vcn: remove unnecessary included headers
On Mon, Dec 16, 2019 at 11:06 AM Leo Liu wrote: > > Esp. VCN1.0 headers should not be here > > Signed-off-by: Leo Liu > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 7 --- > 1 file changed, 7 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c > index e522025430c7..371f55de42dc 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c > @@ -25,19 +25,12 @@ > */ > > #include > -#include Don't we still need module.h for MODULE_FIRMWARE()? Alex > #include > > -#include > - > #include "amdgpu.h" > #include "amdgpu_pm.h" > #include "amdgpu_vcn.h" > #include "soc15d.h" > -#include "soc15_common.h" > - > -#include "vcn/vcn_1_0_offset.h" > -#include "vcn/vcn_1_0_sh_mask.h" > > /* Firmware Names */ > #define FIRMWARE_RAVEN "amdgpu/raven_vcn.bin" > -- > 2.17.1 > > ___ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu/vcn: remove unnecessary included headers
Esp. VCN1.0 headers should not be here Signed-off-by: Leo Liu --- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 7 --- 1 file changed, 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c index e522025430c7..371f55de42dc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c @@ -25,19 +25,12 @@ */ #include -#include #include -#include - #include "amdgpu.h" #include "amdgpu_pm.h" #include "amdgpu_vcn.h" #include "soc15d.h" -#include "soc15_common.h" - -#include "vcn/vcn_1_0_offset.h" -#include "vcn/vcn_1_0_sh_mask.h" /* Firmware Names */ #define FIRMWARE_RAVEN "amdgpu/raven_vcn.bin" -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amd/display: Remove unneeded semicolon
On 2019-12-14 4:12 a.m., zhengbin wrote: > Fixes coccicheck warning: > > drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c:412:90-91: Unneeded > semicolon > > Reported-by: Hulk Robot > Signed-off-by: zhengbin Reviewed-by: Harry Wentland Harry > --- > drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c > b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c > index de51ef1..a1b7e76 100644 > --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c > +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c > @@ -409,7 +409,7 @@ void build_watermark_ranges(struct clk_bw_params > *bw_params, struct pp_smu_wm_ra > continue; > > ranges->reader_wm_sets[num_valid_sets].wm_inst = > bw_params->wm_table.entries[i].wm_inst; > - ranges->reader_wm_sets[num_valid_sets].wm_type = > bw_params->wm_table.entries[i].wm_type;; > + ranges->reader_wm_sets[num_valid_sets].wm_type = > bw_params->wm_table.entries[i].wm_type; > /* We will not select WM based on dcfclk, so leave it as > unconstrained */ > ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz = > PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; > ranges->reader_wm_sets[num_valid_sets].max_drain_clk_mhz = > PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; > -- > 2.7.4 > ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH v2 3/4] amd/amdgpu: add sched array to IPs with multiple run-queues
Hi Christian, On 12/16/19 3:03 PM, Nirmoy Das wrote: Reviewed-by: Christian König I am keeping Reviewed-by again :) I had to minor rebase related change. Regards, Nirmoy ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH v2 2/4] drm/amdgpu: replace vm_pte's run-queue list with drm gpu scheds list
drm_sched_entity_init() takes drm gpu scheduler list instead of
drm_sched_rq list. This makes conversion of drm_sched_rq list
to drm gpu scheduler list unnecessary
Signed-off-by: Nirmoy Das
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 11 ---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 4 ++--
drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 8 +++-
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 8 +++-
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 8 +++-
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 5 ++---
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 8 +++-
drivers/gpu/drm/amd/amdgpu/si_dma.c| 8 +++-
9 files changed, 24 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 403632104377..7c40390b4ed4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2789,7 +2789,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
adev->mman.buffer_funcs = NULL;
adev->mman.buffer_funcs_ring = NULL;
adev->vm_manager.vm_pte_funcs = NULL;
- adev->vm_manager.vm_pte_num_rqs = 0;
+ adev->vm_manager.vm_pte_num_scheds = 0;
adev->gmc.gmc_funcs = NULL;
adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS);
bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 1c65b5bffa6b..b999b67ff57a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -2744,7 +2744,6 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct
amdgpu_vm *vm,
{
struct amdgpu_bo_param bp;
struct amdgpu_bo *root;
- struct drm_gpu_scheduler *sched_list[AMDGPU_MAX_RINGS];
int r, i;
vm->va = RB_ROOT_CACHED;
@@ -2758,19 +2757,17 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct
amdgpu_vm *vm,
spin_lock_init(&vm->invalidated_lock);
INIT_LIST_HEAD(&vm->freed);
- for (i = 0; i < adev->vm_manager.vm_pte_num_rqs; i++)
- sched_list[i] = adev->vm_manager.vm_pte_rqs[i]->sched;
/* create scheduler entities for page table updates */
r = drm_sched_entity_init(&vm->direct, DRM_SCHED_PRIORITY_NORMAL,
- sched_list, adev->vm_manager.vm_pte_num_rqs,
- NULL);
+ adev->vm_manager.vm_pte_scheds,
+ adev->vm_manager.vm_pte_num_scheds, NULL);
if (r)
return r;
r = drm_sched_entity_init(&vm->delayed, DRM_SCHED_PRIORITY_NORMAL,
- sched_list, adev->vm_manager.vm_pte_num_rqs,
- NULL);
+ adev->vm_manager.vm_pte_scheds,
+ adev->vm_manager.vm_pte_num_scheds, NULL);
if (r)
goto error_free_direct;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index d5613d184e99..100547f094ff 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -330,8 +330,8 @@ struct amdgpu_vm_manager {
u64 vram_base_offset;
/* vm pte handling */
const struct amdgpu_vm_pte_funcs*vm_pte_funcs;
- struct drm_sched_rq *vm_pte_rqs[AMDGPU_MAX_RINGS];
- unsignedvm_pte_num_rqs;
+ struct drm_gpu_scheduler
*vm_pte_scheds[AMDGPU_MAX_RINGS];
+ unsignedvm_pte_num_scheds;
struct amdgpu_ring *page_fault;
/* partial resident texture handling */
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index 82cdb8f57bfd..1f22a8d0f7f3 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -1373,16 +1373,14 @@ static const struct amdgpu_vm_pte_funcs
cik_sdma_vm_pte_funcs = {
static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev)
{
- struct drm_gpu_scheduler *sched;
unsigned i;
adev->vm_manager.vm_pte_funcs = &cik_sdma_vm_pte_funcs;
for (i = 0; i < adev->sdma.num_instances; i++) {
- sched = &adev->sdma.instance[i].ring.sched;
- adev->vm_manager.vm_pte_rqs[i] =
- &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL];
+ adev->vm_manager.vm_pte_scheds[i] =
+ &adev->sdma.instance[i].ring.sched;
}
- adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances;
+ adev->vm_manager.vm_pte_num_scheds = adev->sdma.num
[PATCH v2 0/4] drm/amdgpu: cleanup entity creation
v2 Changes: rebased 0003-amd-amdgpu-add-sched-array-to-IPs-with-multiple-run-.patch because of a5c191e9cd09a8fa697865882619692b4dba8417(drm/amdgpu: fix JPEG instance checking when ctx init) Nirmoy Das (4): drm/scheduler: rework entity creation drm/amdgpu: replace vm_pte's run-queue list with drm gpu scheds list amd/amdgpu: add sched array to IPs with multiple run-queues drm/scheduler: do not keep a copy of sched list drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c| 113 + drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h| 3 + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 +- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h| 4 + drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h | 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h | 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c| 8 +- drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c| 7 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c| 7 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h| 9 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 11 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 4 +- drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 8 +- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 8 +- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 8 +- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 5 +- drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 8 +- drivers/gpu/drm/amd/amdgpu/si_dma.c| 8 +- drivers/gpu/drm/etnaviv/etnaviv_drv.c | 7 +- drivers/gpu/drm/lima/lima_sched.c | 5 +- drivers/gpu/drm/panfrost/panfrost_job.c| 8 +- drivers/gpu/drm/scheduler/sched_entity.c | 77 +- drivers/gpu/drm/v3d/v3d_drv.c | 8 +- include/drm/gpu_scheduler.h| 8 +- 24 files changed, 176 insertions(+), 156 deletions(-) -- 2.24.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH v2 4/4] drm/scheduler: do not keep a copy of sched list
entity should not keep copy and maintain sched list for
itself.
Signed-off-by: Nirmoy Das
Reviewed-by: Christian König
---
drivers/gpu/drm/scheduler/sched_entity.c | 19 ---
1 file changed, 4 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/scheduler/sched_entity.c
b/drivers/gpu/drm/scheduler/sched_entity.c
index f9b6ce29c58f..2e3a058fc239 100644
--- a/drivers/gpu/drm/scheduler/sched_entity.c
+++ b/drivers/gpu/drm/scheduler/sched_entity.c
@@ -56,8 +56,6 @@ int drm_sched_entity_init(struct drm_sched_entity *entity,
unsigned int num_sched_list,
atomic_t *guilty)
{
- int i;
-
if (!(entity && sched_list && (num_sched_list == 0 || sched_list[0])))
return -EINVAL;
@@ -67,22 +65,14 @@ int drm_sched_entity_init(struct drm_sched_entity *entity,
entity->guilty = guilty;
entity->num_sched_list = num_sched_list;
entity->priority = priority;
- entity->sched_list = kcalloc(num_sched_list,
- sizeof(struct drm_gpu_scheduler *),
GFP_KERNEL);
+ entity->sched_list = num_sched_list > 1 ? sched_list : NULL;
+ entity->last_scheduled = NULL;
- if(!entity->sched_list)
- return -ENOMEM;
+ if(num_sched_list)
+ entity->rq = &sched_list[0]->sched_rq[entity->priority];
init_completion(&entity->entity_idle);
- for (i = 0; i < num_sched_list; i++)
- entity->sched_list[i] = sched_list[i];
-
- if (num_sched_list)
- entity->rq = &entity->sched_list[0]->sched_rq[entity->priority];
-
- entity->last_scheduled = NULL;
-
spin_lock_init(&entity->rq_lock);
spsc_queue_init(&entity->job_queue);
@@ -312,7 +302,6 @@ void drm_sched_entity_fini(struct drm_sched_entity *entity)
dma_fence_put(entity->last_scheduled);
entity->last_scheduled = NULL;
- kfree(entity->sched_list);
}
EXPORT_SYMBOL(drm_sched_entity_fini);
--
2.24.0
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[PATCH v2 3/4] amd/amdgpu: add sched array to IPs with multiple run-queues
This sched array can be passed on to entity creation routine
instead of manually creating such sched array on every context creation.
Signed-off-by: Nirmoy Das
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c| 114 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h| 3 +
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h| 4 +
drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h | 2 +
drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h | 2 +
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h| 9 +-
7 files changed, 89 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index 38ec5c919bd9..f5fe60465524 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -74,7 +74,7 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
struct amdgpu_ctx *ctx)
{
unsigned num_entities = amdgpu_ctx_total_num_entities();
- unsigned i, j, k;
+ unsigned i, j;
int r;
if (priority < 0 || priority >= DRM_SCHED_PRIORITY_MAX)
@@ -121,73 +121,55 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
ctx->override_priority = DRM_SCHED_PRIORITY_UNSET;
for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) {
- struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
- struct drm_gpu_scheduler *sched_list[AMDGPU_MAX_RINGS];
- unsigned num_rings = 0;
- unsigned num_rqs = 0;
+ struct drm_gpu_scheduler **scheds;
+ struct drm_gpu_scheduler *sched;
+ unsigned num_scheds = 0;
switch (i) {
case AMDGPU_HW_IP_GFX:
- rings[0] = &adev->gfx.gfx_ring[0];
- num_rings = 1;
+ scheds = adev->gfx.gfx_sched;
+ num_scheds = 1;
break;
case AMDGPU_HW_IP_COMPUTE:
- for (j = 0; j < adev->gfx.num_compute_rings; ++j)
- rings[j] = &adev->gfx.compute_ring[j];
- num_rings = adev->gfx.num_compute_rings;
+ scheds = adev->gfx.compute_sched;
+ num_scheds = adev->gfx.num_compute_sched;
break;
case AMDGPU_HW_IP_DMA:
- for (j = 0; j < adev->sdma.num_instances; ++j)
- rings[j] = &adev->sdma.instance[j].ring;
- num_rings = adev->sdma.num_instances;
+ scheds = adev->sdma.sdma_sched;
+ num_scheds = adev->sdma.num_sdma_sched;
break;
case AMDGPU_HW_IP_UVD:
- rings[0] = &adev->uvd.inst[0].ring;
- num_rings = 1;
+ sched = &adev->uvd.inst[0].ring.sched;
+ scheds = &sched;
+ num_scheds = 1;
break;
case AMDGPU_HW_IP_VCE:
- rings[0] = &adev->vce.ring[0];
- num_rings = 1;
+ sched = &adev->vce.ring[0].sched;
+ scheds = &sched;
+ num_scheds = 1;
break;
case AMDGPU_HW_IP_UVD_ENC:
- rings[0] = &adev->uvd.inst[0].ring_enc[0];
- num_rings = 1;
+ sched = &adev->uvd.inst[0].ring_enc[0].sched;
+ scheds = &sched;
+ num_scheds = 1;
break;
case AMDGPU_HW_IP_VCN_DEC:
- for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
- if (adev->vcn.harvest_config & (1 << j))
- continue;
- rings[num_rings++] =
&adev->vcn.inst[j].ring_dec;
- }
+ scheds = adev->vcn.vcn_dec_sched;
+ num_scheds = adev->vcn.num_vcn_dec_sched;
break;
case AMDGPU_HW_IP_VCN_ENC:
- for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
- if (adev->vcn.harvest_config & (1 << j))
- continue;
- for (k = 0; k < adev->vcn.num_enc_rings; ++k)
- rings[num_rings++] =
&adev->vcn.inst[j].ring_enc[k];
- }
- break;
+ scheds = adev->vcn.vcn_enc_sched;
+ num_scheds = adev->vcn.num_vcn_enc_sched;
case AMDGPU_HW_IP_VCN_JPEG:
- for (j = 0; j < adev->jpeg.num_jpeg_inst; ++j) {
-
[PATCH v2 1/4] drm/scheduler: rework entity creation
Entity currently keeps a copy of run_queue list and modify it in
drm_sched_entity_set_priority(). Entities shouldn't modify run_queue
list. Use drm_gpu_scheduler list instead of drm_sched_rq list
in drm_sched_entity struct. In this way we can select a runqueue based
on entity/ctx's priority for a drm scheduler.
Signed-off-by: Nirmoy Das
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 7 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 8 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 7 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 7 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 14 +++--
drivers/gpu/drm/etnaviv/etnaviv_drv.c| 7 ++-
drivers/gpu/drm/lima/lima_sched.c| 5 +-
drivers/gpu/drm/panfrost/panfrost_job.c | 8 ++-
drivers/gpu/drm/scheduler/sched_entity.c | 74 ++--
drivers/gpu/drm/v3d/v3d_drv.c| 8 ++-
include/drm/gpu_scheduler.h | 8 ++-
11 files changed, 78 insertions(+), 75 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index 1d2bbf10614e..38ec5c919bd9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -122,7 +122,7 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) {
struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
- struct drm_sched_rq *rqs[AMDGPU_MAX_RINGS];
+ struct drm_gpu_scheduler *sched_list[AMDGPU_MAX_RINGS];
unsigned num_rings = 0;
unsigned num_rqs = 0;
@@ -181,12 +181,13 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
if (!rings[j]->adev)
continue;
- rqs[num_rqs++] = &rings[j]->sched.sched_rq[priority];
+ sched_list[num_rqs++] = &rings[j]->sched;
}
for (j = 0; j < amdgpu_ctx_num_entities[i]; ++j)
r = drm_sched_entity_init(&ctx->entities[i][j].entity,
- rqs, num_rqs, &ctx->guilty);
+ priority, sched_list,
+ num_rqs, &ctx->guilty);
if (r)
goto error_cleanup_entities;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 81f6764f1ba6..2ff63d0414c9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1954,11 +1954,13 @@ void amdgpu_ttm_set_buffer_funcs_status(struct
amdgpu_device *adev, bool enable)
if (enable) {
struct amdgpu_ring *ring;
- struct drm_sched_rq *rq;
+ struct drm_gpu_scheduler *sched;
ring = adev->mman.buffer_funcs_ring;
- rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_KERNEL];
- r = drm_sched_entity_init(&adev->mman.entity, &rq, 1, NULL);
+ sched = &ring->sched;
+ r = drm_sched_entity_init(&adev->mman.entity,
+ DRM_SCHED_PRIORITY_KERNEL, &sched,
+ 1, NULL);
if (r) {
DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
r);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
index d587ffe2af8e..a92f3b18e657 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
@@ -330,12 +330,13 @@ int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
int amdgpu_uvd_entity_init(struct amdgpu_device *adev)
{
struct amdgpu_ring *ring;
- struct drm_sched_rq *rq;
+ struct drm_gpu_scheduler *sched;
int r;
ring = &adev->uvd.inst[0].ring;
- rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
- r = drm_sched_entity_init(&adev->uvd.entity, &rq, 1, NULL);
+ sched = &ring->sched;
+ r = drm_sched_entity_init(&adev->uvd.entity, DRM_SCHED_PRIORITY_NORMAL,
+ &sched, 1, NULL);
if (r) {
DRM_ERROR("Failed setting up UVD kernel entity.\n");
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
index 46b590af2fd2..ceb0dbf685f1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
@@ -240,12 +240,13 @@ int amdgpu_vce_sw_fini(struct amdgpu_device *adev)
int amdgpu_vce_entity_init(struct amdgpu_device *adev)
{
struct amdgpu_ring *ring;
- struct drm_sched_rq *rq;
+ struct drm_gpu_scheduler *sched;
int r;
ring = &adev->vce.ring[0];
- rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORM
RE: [PATCH] drm/amdgpu: drop useless BACO arg in amdgpu_ras_reset_gpu
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: Chen, Guchun
Sent: Friday, December 13, 2019 16:54
To: Zhang, Hawking ; Ma, Le ; Zhou1, Tao
; Deucher, Alexander ;
amd-gfx@lists.freedesktop.org
Cc: Chen, Guchun
Subject: [PATCH] drm/amdgpu: drop useless BACO arg in amdgpu_ras_reset_gpu
BACO reset mode strategy is determined by latter func when calling
amdgpu_ras_reset_gpu. So not to confuse audience, drop it.
Signed-off-by: Guchun Chen
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 3 +--
drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c | 2 +-
drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 2 +-
6 files changed, 7 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index 52c27e49bc7b..056c7e7a6040 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -641,7 +641,7 @@ int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device
*adev,
kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
if (adev->gfx.funcs->query_ras_error_count)
adev->gfx.funcs->query_ras_error_count(adev, err_data);
- amdgpu_ras_reset_gpu(adev, 0);
+ amdgpu_ras_reset_gpu(adev);
}
return AMDGPU_RAS_SUCCESS;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index 3f4ba408aee0..e9f8decfbc69 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -1872,7 +1872,7 @@ void amdgpu_ras_resume(struct amdgpu_device *adev)
* See feature_enable_on_boot
*/
amdgpu_ras_disable_all_features(adev, 1);
- amdgpu_ras_reset_gpu(adev, 0);
+ amdgpu_ras_reset_gpu(adev);
}
}
@@ -1935,6 +1935,6 @@ void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev)
if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) {
DRM_WARN("RAS event of type ERREVENT_ATHUB_INTERRUPT
detected!\n");
- amdgpu_ras_reset_gpu(adev, false);
+ amdgpu_ras_reset_gpu(adev);
}
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
index d4ade4739245..a5fe29a9373e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
@@ -494,8 +494,7 @@ int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
int amdgpu_ras_reserve_bad_pages(struct amdgpu_device *adev);
-static inline int amdgpu_ras_reset_gpu(struct amdgpu_device *adev,
- bool is_baco)
+static inline int amdgpu_ras_reset_gpu(struct amdgpu_device *adev)
{
struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
index 6361b2c9ae1a..9bbe819de46a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
@@ -160,7 +160,7 @@ int amdgpu_sdma_process_ras_data_cb(struct amdgpu_device
*adev,
struct amdgpu_iv_entry *entry)
{
kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
- amdgpu_ras_reset_gpu(adev, 0);
+ amdgpu_ras_reset_gpu(adev);
return AMDGPU_RAS_SUCCESS;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
index d4fb9cf27e21..8a6c733d170c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
@@ -132,7 +132,7 @@ int amdgpu_umc_process_ras_data_cb(struct amdgpu_device
*adev,
err_data->err_addr_cnt))
DRM_WARN("Failed to add ras bad page!\n");
- amdgpu_ras_reset_gpu(adev, 0);
+ amdgpu_ras_reset_gpu(adev);
}
kfree(err_data->err_addr);
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
index bb701dbfd472..7091782266b9 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
@@ -339,7 +339,7 @@ static void
nbio_v7_4_handle_ras_controller_intr_no_bifring(struct amdgpu_device
/* ras_controller_int is dedicated for nbif ras error,
* not the global interrupt for sync flood
*/
- amdgpu_ras_reset_gpu(adev, true);
+ amdgpu_ras_reset_gpu(adev);
}
}
--
2.17.1
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Re: [PATCH] drm/amdgpu: enable gfxoff for raven1 refresh
On Fri, Dec 13, 2019 at 11:24:00AM +0800, Zhu, Changfeng wrote: > From: changzhu > > When smu version is larger than 0x41e2b, it will load > raven_kicker_rlc.bin.To enable gfxoff for raven_kicker_rlc.bin,it > needs to avoid adev->pm.pp_feature &= ~PP_GFXOFF_MASK when it loads > raven_kicker_rlc.bin. > > Change-Id: I4dffa1783c9ceb5d40df9756d821e2cd7feff84d > Signed-off-by: changzhu Reviewed-by: Huang Rui > --- > drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 15 --- > 1 file changed, 4 insertions(+), 11 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > index ea58d0e5be4c..68409bb7c9e0 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > @@ -1038,17 +1038,10 @@ static void gfx_v9_0_check_if_need_gfxoff(struct > amdgpu_device *adev) > case CHIP_VEGA20: > break; > case CHIP_RAVEN: > - /* Disable GFXOFF on original raven. There are combinations > - * of sbios and platforms that are not stable. > - */ > - if (!(adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8)) > - adev->pm.pp_feature &= ~PP_GFXOFF_MASK; > - else if (!(adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8) > - &&((adev->gfx.rlc_fw_version != 106 && > - adev->gfx.rlc_fw_version < 531) || > - (adev->gfx.rlc_fw_version == 53815) || > - (adev->gfx.rlc_feature_version < 1) || > - !adev->gfx.rlc.is_rlc_v2_1)) > + if (!(adev->rev_id >= 0x8 || > + adev->pdev->device == 0x15d8) && > + (adev->pm.fw_version < 0x41e2b || /* not raven1 fresh */ > + !adev->gfx.rlc.is_rlc_v2_1)) /* without rlc save restore > ucodes */ > adev->pm.pp_feature &= ~PP_GFXOFF_MASK; > > if (adev->pm.pp_feature & PP_GFXOFF_MASK) > -- > 2.17.1 > ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH] drm/amdgpu/sriov: Tonga sriov also need load firmware with smu
Reviewd-by Yintian Tao
-Original Message-
From: amd-gfx On Behalf Of Emily Deng
Sent: 2019年12月16日 17:17
To: amd-gfx@lists.freedesktop.org
Cc: Deng, Emily
Subject: [PATCH] drm/amdgpu/sriov: Tonga sriov also need load firmware with smu
Fix Tonga sriov load driver fail issue.
Signed-off-by: Emily Deng
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 3 ++-
drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 3 ---
2 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 26d1a4c..52d3f66 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1818,7 +1818,8 @@ static int amdgpu_device_fw_loading(struct amdgpu_device
*adev)
}
}
- r = amdgpu_pm_load_smu_firmware(adev, &smu_version);
+ if (!amdgpu_sriov_vf(adev) || adev->asic_type == CHIP_TONGA)
+ r = amdgpu_pm_load_smu_firmware(adev, &smu_version);
return r;
}
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 5087d6b..7293763 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -275,9 +275,6 @@ static int pp_dpm_load_fw(void *handle) {
struct pp_hwmgr *hwmgr = handle;
- if (!hwmgr->not_vf)
- return 0;
-
if (!hwmgr || !hwmgr->smumgr_funcs || !hwmgr->smumgr_funcs->start_smu)
return -EINVAL;
--
2.7.4
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[PATCH] drm/amdgpu/sriov: Tonga sriov also need load firmware with smu
Fix Tonga sriov load driver fail issue.
Signed-off-by: Emily Deng
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 3 ++-
drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 3 ---
2 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 26d1a4c..52d3f66 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1818,7 +1818,8 @@ static int amdgpu_device_fw_loading(struct amdgpu_device
*adev)
}
}
- r = amdgpu_pm_load_smu_firmware(adev, &smu_version);
+ if (!amdgpu_sriov_vf(adev) || adev->asic_type == CHIP_TONGA)
+ r = amdgpu_pm_load_smu_firmware(adev, &smu_version);
return r;
}
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 5087d6b..7293763 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -275,9 +275,6 @@ static int pp_dpm_load_fw(void *handle)
{
struct pp_hwmgr *hwmgr = handle;
- if (!hwmgr->not_vf)
- return 0;
-
if (!hwmgr || !hwmgr->smumgr_funcs || !hwmgr->smumgr_funcs->start_smu)
return -EINVAL;
--
2.7.4
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Re: [PATCH] drm/amdgpu: always reset asic when going into suspend
Hi Alex, On Mon, Nov 25, 2019 at 1:17 PM Daniel Drake wrote: > Unfortunately not. The original issue still exists (dead gfx after > resume from s2idle) and also when I trigger execution of the suspend > or runtime suspend routines the power usage increases around 1.5W as > before. > > Have you confirmed that amdgpu s2idle is working on platforms you have in > hand? Any further ideas here? Or any workarounds that you would consider? This platform has been rather tricky but all of the other problems are now solved: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=f897e60a12f0b9146357780d317879bce2a877dc https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=d21b8adbd475dba19ac2086d3306327b4a297418 https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=406857f773b082bc88edfd24967facf4ed07ac85 https://patchwork.kernel.org/patch/11263477/ amdgpu is the only breakage left before Linux can be shipped on this family of products. Thanks Daniel ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
