RE: [PATCH 1/1] drm/amdkfd: Don't touch the hardware in pre_reset callback
Okay
Can you send me the patch (in attachment) once you finished it, I need to
verify it on SRIOV
Thanks
_
Monk Liu|GPU Virtualization Team |AMD
-Original Message-
From: Kuehling, Felix
Sent: Friday, December 20, 2019 3:56 PM
To: Liu, Monk ; amd-gfx@lists.freedesktop.org
Cc: Liu, Shaoyun
Subject: Re: [PATCH 1/1] drm/amdkfd: Don't touch the hardware in pre_reset
callback
You should be able to save the plain text email and pass that to "git am". It's
trivial with Thunderbird on a Linux system. If you're using outlook, I'm not
sure.
Anyway, I'm already reworking the patch based on Shaoyun's suggestion and some
ideas it gave me.
Regards,
Felix
On 2019-12-19 23:23, Liu, Monk wrote:
> Hi Felix
>
> Do you know how I can get a "xxx.patch" file from the email from you ??
>
> _
> Monk Liu|GPU Virtualization Team |AMD
>
>
> -Original Message-
> From: Kuehling, Felix
> Sent: Friday, December 20, 2019 10:09 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Liu, Shaoyun ; Liu, Monk
> Subject: [PATCH 1/1] drm/amdkfd: Don't touch the hardware in pre_reset
> callback
>
> The intention of the pre_reset callback is to update the driver state to
> reflect that all user mode queues are preempted and the HIQ is destroyed.
> However we should not actually preempt any queues or otherwise touch the
> hardware because it is presumably hanging.
> The impending reset will take care of actually stopping all queues.
>
> This should prevent KIQ register access hanging on SRIOV function level reset
> (FLR). It should also speed up the reset by avoiding unnecessary timeouts
> from a potentially hanging GPU scheduler.
>
> CC: shaoyunl
> CC: Liu Monk
> Signed-off-by: Felix Kuehling
> ---
> drivers/gpu/drm/amd/amdkfd/kfd_device.c | 24 ++---
> .../drm/amd/amdkfd/kfd_device_queue_manager.c | 27 ---
> .../drm/amd/amdkfd/kfd_device_queue_manager.h | 5 ++--
> drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c | 8 +++---
> .../gpu/drm/amd/amdkfd/kfd_packet_manager.c | 4 +--
> drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 8 +++---
> drivers/gpu/drm/amd/amdkfd/kfd_process.c | 11
> .../amd/amdkfd/kfd_process_queue_manager.c| 2 +-
> 8 files changed, 53 insertions(+), 36 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
> b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
> index c6b6901bbda3..796996a0d926 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
> @@ -486,6 +486,7 @@ static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned
> int buf_size,
> unsigned int chunk_size);
> static void kfd_gtt_sa_fini(struct kfd_dev *kfd);
>
> +static void kfd_suspend(struct kfd_dev *kfd, bool pre_reset);
> static int kfd_resume(struct kfd_dev *kfd);
>
> struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, @@ -728,7 +729,7 @@ int
> kgd2kfd_pre_reset(struct kfd_dev *kfd) {
> if (!kfd->init_complete)
> return 0;
> - kgd2kfd_suspend(kfd);
> + kfd_suspend(kfd, true);
>
> kfd_signal_reset_event(kfd);
> return 0;
> @@ -767,13 +768,7 @@ void kgd2kfd_suspend(struct kfd_dev *kfd)
> if (!kfd->init_complete)
> return;
>
> - /* For first KFD device suspend all the KFD processes */
> - if (atomic_inc_return(&kfd_locked) == 1)
> - kfd_suspend_all_processes();
> -
> - kfd->dqm->ops.stop(kfd->dqm);
> -
> - kfd_iommu_suspend(kfd);
> + kfd_suspend(kfd, false);
> }
>
> int kgd2kfd_resume(struct kfd_dev *kfd) @@ -795,6 +790,17 @@ int
> kgd2kfd_resume(struct kfd_dev *kfd)
> return ret;
> }
>
> +static void kfd_suspend(struct kfd_dev *kfd, bool pre_reset) {
> + /* For first KFD device suspend all the KFD processes */
> + if (atomic_inc_return(&kfd_locked) == 1)
> + kfd_suspend_all_processes(pre_reset);
> +
> + kfd->dqm->ops.stop(kfd->dqm, pre_reset);
> +
> + kfd_iommu_suspend(kfd);
> +}
> +
> static int kfd_resume(struct kfd_dev *kfd) {
> int err = 0;
> @@ -877,7 +883,7 @@ int kgd2kfd_quiesce_mm(struct mm_struct *mm)
> if (!p)
> return -ESRCH;
>
> - r = kfd_process_evict_queues(p);
> + r = kfd_process_evict_queues(p, false);
>
> kfd_unref_process(p);
> return r;
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> index f7f6df40875e..3a49944164da 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> @@ -592,7 +592,8 @@ static int update_queue(struct
> device_queue_manager *dqm, struct queue *q) }
>
> static int evict_process_queues_nocpsch(struct device_queue_manager *dqm,
> - struct qcm_process_device
[PATCH 2/4] drm/amdkfd: Remove unused variable
dqm->pipeline_mem wasn't used anywhere.
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 1 -
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h | 1 -
2 files changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index f7f6df40875e..558c0ad81848 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -930,7 +930,6 @@ static void uninitialize(struct device_queue_manager *dqm)
for (i = 0 ; i < KFD_MQD_TYPE_MAX ; i++)
kfree(dqm->mqd_mgrs[i]);
mutex_destroy(&dqm->lock_hidden);
- kfd_gtt_sa_free(dqm->dev, dqm->pipeline_mem);
}
static int start_nocpsch(struct device_queue_manager *dqm)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
index a8c37e6da027..8991120c4fa2 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
@@ -190,7 +190,6 @@ struct device_queue_manager {
/* the pasid mapping for each kfd vmid */
uint16_tvmid_pasid[VMID_NUM];
uint64_tpipelines_addr;
- struct kfd_mem_obj *pipeline_mem;
uint64_tfence_gpu_addr;
unsigned int*fence_addr;
struct kfd_mem_obj *fence_mem;
--
2.24.1
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[PATCH 4/4] drm/amdkfd: Avoid hanging hardware in stop_cpsch
Don't use the HWS if it's known to be hanging. In a reset also
don't try to destroy the HIQ because that may hang on SRIOV if the
KIQ is unresponsive.
Signed-off-by: Felix Kuehling
---
.../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c| 12
drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c| 8
drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c | 4 ++--
drivers/gpu/drm/amd/amdkfd/kfd_priv.h| 4 ++--
.../gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 2 +-
5 files changed, 17 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index a7e9ec1b3ce3..d7eb6ac37f62 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -946,7 +946,7 @@ static int start_nocpsch(struct device_queue_manager *dqm)
static int stop_nocpsch(struct device_queue_manager *dqm)
{
if (dqm->dev->device_info->asic_family == CHIP_HAWAII)
- pm_uninit(&dqm->packets);
+ pm_uninit(&dqm->packets, false);
dqm->sched_running = false;
return 0;
@@ -1114,20 +1114,24 @@ static int start_cpsch(struct device_queue_manager *dqm)
return 0;
fail_allocate_vidmem:
fail_set_sched_resources:
- pm_uninit(&dqm->packets);
+ pm_uninit(&dqm->packets, false);
fail_packet_manager_init:
return retval;
}
static int stop_cpsch(struct device_queue_manager *dqm)
{
+ bool hanging;
+
dqm_lock(dqm);
- unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0);
+ if (!dqm->is_hws_hang)
+ unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0);
+ hanging = dqm->is_hws_hang || dqm->is_resetting;
dqm->sched_running = false;
dqm_unlock(dqm);
kfd_gtt_sa_free(dqm->dev, dqm->fence_mem);
- pm_uninit(&dqm->packets);
+ pm_uninit(&dqm->packets, hanging);
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
index 2d56dc534459..bae706462f96 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
@@ -195,9 +195,9 @@ static bool kq_initialize(struct kernel_queue *kq, struct
kfd_dev *dev,
}
/* Uninitialize a kernel queue and free all its memory usages. */
-static void kq_uninitialize(struct kernel_queue *kq)
+static void kq_uninitialize(struct kernel_queue *kq, bool hanging)
{
- if (kq->queue->properties.type == KFD_QUEUE_TYPE_HIQ)
+ if (kq->queue->properties.type == KFD_QUEUE_TYPE_HIQ && !hanging)
kq->mqd_mgr->destroy_mqd(kq->mqd_mgr,
kq->queue->mqd,
KFD_PREEMPT_TYPE_WAVEFRONT_RESET,
@@ -337,9 +337,9 @@ struct kernel_queue *kernel_queue_init(struct kfd_dev *dev,
return NULL;
}
-void kernel_queue_uninit(struct kernel_queue *kq)
+void kernel_queue_uninit(struct kernel_queue *kq, bool hanging)
{
- kq_uninitialize(kq);
+ kq_uninitialize(kq, hanging);
kfree(kq);
}
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
index 6cabed06ef5d..dc406e6dee23 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
@@ -264,10 +264,10 @@ int pm_init(struct packet_manager *pm, struct
device_queue_manager *dqm)
return 0;
}
-void pm_uninit(struct packet_manager *pm)
+void pm_uninit(struct packet_manager *pm, bool hanging)
{
mutex_destroy(&pm->lock);
- kernel_queue_uninit(pm->priv_queue);
+ kernel_queue_uninit(pm->priv_queue, hanging);
}
int pm_send_set_resources(struct packet_manager *pm,
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
index 087e96838997..8ac680dc90f1 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
@@ -883,7 +883,7 @@ struct device_queue_manager
*device_queue_manager_init(struct kfd_dev *dev);
void device_queue_manager_uninit(struct device_queue_manager *dqm);
struct kernel_queue *kernel_queue_init(struct kfd_dev *dev,
enum kfd_queue_type type);
-void kernel_queue_uninit(struct kernel_queue *kq);
+void kernel_queue_uninit(struct kernel_queue *kq, bool hanging);
int kfd_process_vm_fault(struct device_queue_manager *dqm, unsigned int pasid);
/* Process Queue Manager */
@@ -974,7 +974,7 @@ extern const struct packet_manager_funcs kfd_vi_pm_funcs;
extern const struct packet_manager_funcs kfd_v9_pm_funcs;
int pm_init(struct packet_manager *pm, struct device_queue_manager *dqm);
-void pm_uninit(struct packet_manager *pm);
+void pm_uninit(struct packet_manager *pm, bool hanging);
int pm_send_set_resources(struct packet_
[PATCH 3/4] drm/amdkfd: Improve HWS hang detection and handling
Move HWS hand detection into unmap_queues_cpsch to catch hangs in all
cases. If this happens during a reset, don't schedule another reset
because the reset already in progress is expected to take care of it.
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdkfd/kfd_device.c | 3 +++
.../drm/amd/amdkfd/kfd_device_queue_manager.c | 27 ++-
.../drm/amd/amdkfd/kfd_device_queue_manager.h | 2 ++
3 files changed, 26 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index c6b6901bbda3..2a9e40131735 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -728,6 +728,9 @@ int kgd2kfd_pre_reset(struct kfd_dev *kfd)
{
if (!kfd->init_complete)
return 0;
+
+ kfd->dqm->ops.pre_reset(kfd->dqm);
+
kgd2kfd_suspend(kfd);
kfd_signal_reset_event(kfd);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index 558c0ad81848..a7e9ec1b3ce3 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -952,6 +952,13 @@ static int stop_nocpsch(struct device_queue_manager *dqm)
return 0;
}
+static void pre_reset(struct device_queue_manager *dqm)
+{
+ dqm_lock(dqm);
+ dqm->is_resetting = true;
+ dqm_unlock(dqm);
+}
+
static int allocate_sdma_queue(struct device_queue_manager *dqm,
struct queue *q)
{
@@ -1099,6 +1106,7 @@ static int start_cpsch(struct device_queue_manager *dqm)
dqm_lock(dqm);
/* clear hang status when driver try to start the hw scheduler */
dqm->is_hws_hang = false;
+ dqm->is_resetting = false;
dqm->sched_running = true;
execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
dqm_unlock(dqm);
@@ -1351,8 +1359,17 @@ static int unmap_queues_cpsch(struct
device_queue_manager *dqm,
/* should be timed out */
retval = amdkfd_fence_wait_timeout(dqm->fence_addr, KFD_FENCE_COMPLETED,
queue_preemption_timeout_ms);
- if (retval)
+ if (retval) {
+ pr_err("The cp might be in an unrecoverable state due to an
unsuccessful queues preemption\n");
+ dqm->is_hws_hang = true;
+ /* It's possible we're detecting a HWS hang in the
+* middle of a GPU reset. No need to schedule another
+* reset in this case.
+*/
+ if (!dqm->is_resetting)
+ schedule_work(&dqm->hw_exception_work);
return retval;
+ }
pm_release_ib(&dqm->packets);
dqm->active_runlist = false;
@@ -1370,12 +1387,8 @@ static int execute_queues_cpsch(struct
device_queue_manager *dqm,
if (dqm->is_hws_hang)
return -EIO;
retval = unmap_queues_cpsch(dqm, filter, filter_param);
- if (retval) {
- pr_err("The cp might be in an unrecoverable state due to an
unsuccessful queues preemption\n");
- dqm->is_hws_hang = true;
- schedule_work(&dqm->hw_exception_work);
+ if (retval)
return retval;
- }
return map_queues_cpsch(dqm);
}
@@ -1769,6 +1782,7 @@ struct device_queue_manager
*device_queue_manager_init(struct kfd_dev *dev)
dqm->ops.initialize = initialize_cpsch;
dqm->ops.start = start_cpsch;
dqm->ops.stop = stop_cpsch;
+ dqm->ops.pre_reset = pre_reset;
dqm->ops.destroy_queue = destroy_queue_cpsch;
dqm->ops.update_queue = update_queue;
dqm->ops.register_process = register_process;
@@ -1787,6 +1801,7 @@ struct device_queue_manager
*device_queue_manager_init(struct kfd_dev *dev)
/* initialize dqm for no cp scheduling */
dqm->ops.start = start_nocpsch;
dqm->ops.stop = stop_nocpsch;
+ dqm->ops.pre_reset = pre_reset;
dqm->ops.create_queue = create_queue_nocpsch;
dqm->ops.destroy_queue = destroy_queue_nocpsch;
dqm->ops.update_queue = update_queue;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
index 8991120c4fa2..871d3b628d2d 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
@@ -104,6 +104,7 @@ struct device_queue_manager_ops {
int (*initialize)(struct device_queue_manager *dqm);
int (*start)(struct device_queue_manager *dqm);
int (*stop)(struct device_queue_manager *dqm);
+ void(*pre_reset)(struct device_queue_manager *dqm);
void(*uninitialize)(struct device_queue_m
[PATCH 1/4] drm/amdkfd: Fix permissions of hang_hws
Reading from /sys/kernel/debug/kfd/hang_hws would cause a kernel
oops because we didn't implement a read callback. Set the permission
to write-only to prevent that.
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdkfd/kfd_debugfs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_debugfs.c
b/drivers/gpu/drm/amd/amdkfd/kfd_debugfs.c
index 15c523027285..511712c2e382 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_debugfs.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_debugfs.c
@@ -93,7 +93,7 @@ void kfd_debugfs_init(void)
kfd_debugfs_hqds_by_device, &kfd_debugfs_fops);
debugfs_create_file("rls", S_IFREG | 0444, debugfs_root,
kfd_debugfs_rls_by_device, &kfd_debugfs_fops);
- debugfs_create_file("hang_hws", S_IFREG | 0644, debugfs_root,
+ debugfs_create_file("hang_hws", S_IFREG | 0200, debugfs_root,
NULL, &kfd_debugfs_hang_hws_fops);
}
--
2.24.1
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RE: [PATCH 4/4] drm/amdkfd: Avoid hanging hardware in stop_cpsch
[AMD Official Use Only - Internal Distribution Only]
Series Tested-by: Emily Deng on sriov environment with
vege10 about TDR-1, TDR-2 and TDR-3 test cases.
Best wishes
Emily Deng
>-Original Message-
>From: amd-gfx On Behalf Of Felix
>Kuehling
>Sent: Friday, December 20, 2019 4:30 PM
>To: amd-gfx@lists.freedesktop.org
>Subject: [PATCH 4/4] drm/amdkfd: Avoid hanging hardware in stop_cpsch
>
>Don't use the HWS if it's known to be hanging. In a reset also don't try to
>destroy the HIQ because that may hang on SRIOV if the KIQ is unresponsive.
>
>Signed-off-by: Felix Kuehling
>---
> .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c| 12
> drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c| 8
> drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c | 4 ++--
> drivers/gpu/drm/amd/amdkfd/kfd_priv.h| 4 ++--
> .../gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 2 +-
> 5 files changed, 17 insertions(+), 13 deletions(-)
>
>diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
>b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
>index a7e9ec1b3ce3..d7eb6ac37f62 100644
>--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
>+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
>@@ -946,7 +946,7 @@ static int start_nocpsch(struct device_queue_manager
>*dqm) static int stop_nocpsch(struct device_queue_manager *dqm) {
> if (dqm->dev->device_info->asic_family == CHIP_HAWAII)
>- pm_uninit(&dqm->packets);
>+ pm_uninit(&dqm->packets, false);
> dqm->sched_running = false;
>
> return 0;
>@@ -1114,20 +1114,24 @@ static int start_cpsch(struct
>device_queue_manager *dqm)
> return 0;
> fail_allocate_vidmem:
> fail_set_sched_resources:
>- pm_uninit(&dqm->packets);
>+ pm_uninit(&dqm->packets, false);
> fail_packet_manager_init:
> return retval;
> }
>
> static int stop_cpsch(struct device_queue_manager *dqm) {
>+ bool hanging;
>+
> dqm_lock(dqm);
>- unmap_queues_cpsch(dqm,
>KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0);
>+ if (!dqm->is_hws_hang)
>+ unmap_queues_cpsch(dqm,
>KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0);
>+ hanging = dqm->is_hws_hang || dqm->is_resetting;
> dqm->sched_running = false;
> dqm_unlock(dqm);
>
> kfd_gtt_sa_free(dqm->dev, dqm->fence_mem);
>- pm_uninit(&dqm->packets);
>+ pm_uninit(&dqm->packets, hanging);
>
> return 0;
> }
>diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
>b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
>index 2d56dc534459..bae706462f96 100644
>--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
>+++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
>@@ -195,9 +195,9 @@ static bool kq_initialize(struct kernel_queue *kq, struct
>kfd_dev *dev, }
>
> /* Uninitialize a kernel queue and free all its memory usages. */ -static void
>kq_uninitialize(struct kernel_queue *kq)
>+static void kq_uninitialize(struct kernel_queue *kq, bool hanging)
> {
>- if (kq->queue->properties.type == KFD_QUEUE_TYPE_HIQ)
>+ if (kq->queue->properties.type == KFD_QUEUE_TYPE_HIQ && !hanging)
> kq->mqd_mgr->destroy_mqd(kq->mqd_mgr,
> kq->queue->mqd,
>
> KFD_PREEMPT_TYPE_WAVEFRONT_RESET,
>@@ -337,9 +337,9 @@ struct kernel_queue *kernel_queue_init(struct kfd_dev
>*dev,
> return NULL;
> }
>
>-void kernel_queue_uninit(struct kernel_queue *kq)
>+void kernel_queue_uninit(struct kernel_queue *kq, bool hanging)
> {
>- kq_uninitialize(kq);
>+ kq_uninitialize(kq, hanging);
> kfree(kq);
> }
>
>diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
>b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
>index 6cabed06ef5d..dc406e6dee23 100644
>--- a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
>+++ b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
>@@ -264,10 +264,10 @@ int pm_init(struct packet_manager *pm, struct
>device_queue_manager *dqm)
> return 0;
> }
>
>-void pm_uninit(struct packet_manager *pm)
>+void pm_uninit(struct packet_manager *pm, bool hanging)
> {
> mutex_destroy(&pm->lock);
>- kernel_queue_uninit(pm->priv_queue);
>+ kernel_queue_uninit(pm->priv_queue, hanging);
> }
>
> int pm_send_set_resources(struct packet_manager *pm, diff --git
>a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
>b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
>index 087e96838997..8ac680dc90f1 100644
>--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
>+++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
>@@ -883,7 +883,7 @@ struct device_queue_manager
>*device_queue_manager_init(struct kfd_dev *dev); void
>device_queue_manager_uninit(struct device_queue_manager *dqm); struct
>kernel_queue *kernel_queue_init(struct kfd_dev *dev,
> enum kfd_queue_type type);
>-void kernel_queue_uninit(struct kernel_queue *kq);
>+void kernel_queue_uninit(struct kernel_queue *kq, bool hanging);
> int kfd_process_vm_faul
RE: [PATCH 1/2] drm/amdgpu: remove FB location config for sriov
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Emily Deng
Best wishes
Emily Deng
>-Original Message-
>From: amd-gfx On Behalf Of
>Frank.Min
>Sent: Thursday, December 19, 2019 7:44 PM
>To: amd-gfx@lists.freedesktop.org
>Cc: Min, Frank
>Subject: [PATCH 1/2] drm/amdgpu: remove FB location config for sriov
>
>FB location is already programmed by HV driver for arcutus so remove this part
>
>Change-Id: Ia357ae716bfc3084a4dd277ade219e57092f9b42
>Signed-off-by: Frank.Min
>---
> drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 2 +-
>drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c | 16
> 2 files changed, 1 insertion(+), 17 deletions(-)
>
>diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
>b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
>index e91bd7945777..e9a9d24c2b7f 100644
>--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
>+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
>@@ -264,7 +264,7 @@ static void gfxhub_v1_0_program_invalidation(struct
>amdgpu_device *adev)
>
> int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev) {
>- if (amdgpu_sriov_vf(adev)) {
>+ if (amdgpu_sriov_vf(adev) && adev->asic_type != CHIP_ARCTURUS) {
> /*
>* MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase
>they are
>* VF copy registers so vbios post doesn't program them, for
> diff
>--git a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
>b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
>index d9301e80522a..ac61206c4ce6 100644
>--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
>+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
>@@ -368,22 +368,6 @@ int mmhub_v9_4_gart_enable(struct amdgpu_device
>*adev)
> int i;
>
> for (i = 0; i < MMHUB_NUM_INSTANCES; i++) {
>- if (amdgpu_sriov_vf(adev)) {
>- /*
>- * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF,
>becuase
>- * they are VF copy registers so vbios post doesn't
>- * program them, for SRIOV driver need to program
>them
>- */
>- WREG32_SOC15_OFFSET(MMHUB, 0,
>-
>mmVMSHAREDVC0_MC_VM_FB_LOCATION_BASE,
>- i * MMHUB_INSTANCE_REGISTER_OFFSET,
>- adev->gmc.vram_start >> 24);
>- WREG32_SOC15_OFFSET(MMHUB, 0,
>-
>mmVMSHAREDVC0_MC_VM_FB_LOCATION_TOP,
>- i * MMHUB_INSTANCE_REGISTER_OFFSET,
>- adev->gmc.vram_end >> 24);
>- }
>-
> /* GART Enable. */
> mmhub_v9_4_init_gart_aperture_regs(adev, i);
> mmhub_v9_4_init_system_aperture_regs(adev, i);
>--
>2.17.1
>
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>edesktop.org%2Fmailman%2Flistinfo%2Famd-
>gfx&data=02%7C01%7CEmily.Deng%40amd.com%7C564215fe64b245954
>97408d78478b687%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C
>637123526651355885&sdata=Aeag0%2FF6lQHe70aot5ZzB5UP1rZxsEZO2
>WfLyJv1njg%3D&reserved=0
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[PATCH AUTOSEL 5.4 06/52] drm/amdgpu: add cache flush workaround to gfx8 emit_fence
From: Pierre-Eric Pelloux-Prayer
[ Upstream commit bf26da927a1cd57c9deb2db29ae8cf276ba8b17b ]
The same workaround is used for gfx7.
Both PAL and Mesa use it for gfx8 too, so port this commit to
gfx_v8_0_ring_emit_fence_gfx.
Signed-off-by: Pierre-Eric Pelloux-Prayer
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 22 +++---
1 file changed, 19 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 87dd55e9d72b2..cc88ba76a8d4a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -6184,7 +6184,23 @@ static void gfx_v8_0_ring_emit_fence_gfx(struct
amdgpu_ring *ring, u64 addr,
bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
- /* EVENT_WRITE_EOP - flush caches, send int */
+ /* Workaround for cache flush problems. First send a dummy EOP
+* event down the pipe with seq one below.
+*/
+ amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
+ amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
+EOP_TC_ACTION_EN |
+EOP_TC_WB_ACTION_EN |
+EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
+EVENT_INDEX(5)));
+ amdgpu_ring_write(ring, addr & 0xfffc);
+ amdgpu_ring_write(ring, (upper_32_bits(addr) & 0x) |
+ DATA_SEL(1) | INT_SEL(0));
+ amdgpu_ring_write(ring, lower_32_bits(seq - 1));
+ amdgpu_ring_write(ring, upper_32_bits(seq - 1));
+
+ /* Then send the real EOP event down the pipe:
+* EVENT_WRITE_EOP - flush caches, send int */
amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
EOP_TC_ACTION_EN |
@@ -6926,7 +6942,7 @@ static const struct amdgpu_ring_funcs
gfx_v8_0_ring_funcs_gfx = {
5 + /* COND_EXEC */
7 + /* PIPELINE_SYNC */
VI_FLUSH_GPU_TLB_NUM_WREG * 5 + 9 + /* VM_FLUSH */
- 8 + /* FENCE for VM_FLUSH */
+ 12 + /* FENCE for VM_FLUSH */
20 + /* GDS switch */
4 + /* double SWITCH_BUFFER,
the first COND_EXEC jump to the place just
@@ -6938,7 +6954,7 @@ static const struct amdgpu_ring_funcs
gfx_v8_0_ring_funcs_gfx = {
31 + /* DE_META */
3 + /* CNTX_CTRL */
5 + /* HDP_INVL */
- 8 + 8 + /* FENCE x2 */
+ 12 + 12 + /* FENCE x2 */
2, /* SWITCH_BUFFER */
.emit_ib_size = 4, /* gfx_v8_0_ring_emit_ib_gfx */
.emit_ib = gfx_v8_0_ring_emit_ib_gfx,
--
2.20.1
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[PATCH AUTOSEL 5.4 04/52] drm/amdgpu: add check before enabling/disabling broadcast mode
From: Guchun Chen
[ Upstream commit 6e807535dae5dbbd53bcc5e81047a20bf5eb08ea ]
When security violation from new vbios happens, data fabric is
risky to stop working. So prevent the direct access to DF
mmFabricConfigAccessControl from the new vbios and onwards.
Signed-off-by: Guchun Chen
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/amdgpu/df_v3_6.c | 38
1 file changed, 22 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
index 5850c8e34caac..97d11d7923514 100644
--- a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
+++ b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
@@ -261,23 +261,29 @@ static void
df_v3_6_update_medium_grain_clock_gating(struct amdgpu_device *adev,
{
u32 tmp;
- /* Put DF on broadcast mode */
- adev->df_funcs->enable_broadcast_mode(adev, true);
-
- if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DF_MGCG)) {
- tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
- tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
- tmp |= DF_V3_6_MGCG_ENABLE_15_CYCLE_DELAY;
- WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp);
- } else {
- tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
- tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
- tmp |= DF_V3_6_MGCG_DISABLE;
- WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp);
- }
+ if (adev->cg_flags & AMD_CG_SUPPORT_DF_MGCG) {
+ /* Put DF on broadcast mode */
+ adev->df_funcs->enable_broadcast_mode(adev, true);
+
+ if (enable) {
+ tmp = RREG32_SOC15(DF, 0,
+ mmDF_PIE_AON0_DfGlobalClkGater);
+ tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
+ tmp |= DF_V3_6_MGCG_ENABLE_15_CYCLE_DELAY;
+ WREG32_SOC15(DF, 0,
+ mmDF_PIE_AON0_DfGlobalClkGater, tmp);
+ } else {
+ tmp = RREG32_SOC15(DF, 0,
+ mmDF_PIE_AON0_DfGlobalClkGater);
+ tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
+ tmp |= DF_V3_6_MGCG_DISABLE;
+ WREG32_SOC15(DF, 0,
+ mmDF_PIE_AON0_DfGlobalClkGater, tmp);
+ }
- /* Exit broadcast mode */
- adev->df_funcs->enable_broadcast_mode(adev, false);
+ /* Exit broadcast mode */
+ adev->df_funcs->enable_broadcast_mode(adev, false);
+ }
}
static void df_v3_6_get_clockgating_state(struct amdgpu_device *adev,
--
2.20.1
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[PATCH AUTOSEL 5.4 08/52] drm/amd/display: Fixed kernel panic when booting with DP-to-HDMI dongle
From: David Galiffi
[ Upstream commit a51d9f8fe756beac51ce26ef54195da00a260d13 ]
[Why]
In dc_link_is_dp_sink_present, if dal_ddc_open fails, then
dal_gpio_destroy_ddc is called, destroying pin_data and pin_clock. They
are created only on dc_construct, and next aux access will cause a panic.
[How]
Instead of calling dal_gpio_destroy_ddc, call dal_ddc_close.
Signed-off-by: David Galiffi
Reviewed-by: Tony Cheng
Acked-by: Leo Li
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index ca20b150afcc2..6cb91a8eb2e0c 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -373,7 +373,7 @@ bool dc_link_is_dp_sink_present(struct dc_link *link)
if (GPIO_RESULT_OK != dal_ddc_open(
ddc, GPIO_MODE_INPUT, GPIO_DDC_CONFIG_TYPE_MODE_I2C)) {
- dal_gpio_destroy_ddc(&ddc);
+ dal_ddc_close(ddc);
return present;
}
--
2.20.1
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[PATCH AUTOSEL 5.4 10/52] drm/amd/display: Reset steer fifo before unblanking the stream
From: Nikola Cornij [ Upstream commit 87de6cb2f28153bc74d0a001ca099c29453e145f ] [why] During mode transition steer fifo could overflow. Quite often it recovers by itself, but sometimes it doesn't. [how] Add steer fifo reset before unblanking the stream. Also add a short delay when resetting dig resync fifo to make sure register writes don't end up back-to-back, in which case the HW might miss the reset request. Signed-off-by: Nikola Cornij Reviewed-by: Tony Cheng Acked-by: Leo Li Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin --- .../drm/amd/display/dc/dcn20/dcn20_stream_encoder.c | 12 ++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c index 5ab9d62404981..e95025b1d14d2 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c @@ -492,15 +492,23 @@ void enc2_stream_encoder_dp_unblank( DP_VID_N_MUL, n_multiply); } - /* set DIG_START to 0x1 to reset FIFO */ + /* make sure stream is disabled before resetting steer fifo */ + REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, false); + REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, 0, 10, 5000); + /* set DIG_START to 0x1 to reset FIFO */ REG_UPDATE(DIG_FE_CNTL, DIG_START, 1); + udelay(1); /* write 0 to take the FIFO out of reset */ REG_UPDATE(DIG_FE_CNTL, DIG_START, 0); - /* switch DP encoder to CRTC data */ + /* switch DP encoder to CRTC data, but reset it the fifo first. It may happen +* that it overflows during mode transition, and sometimes doesn't recover. +*/ + REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 1); + udelay(10); REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0); -- 2.20.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH AUTOSEL 5.4 05/52] drm/amdgpu: add header line for power profile on Arcturus
From: Alex Deucher
[ Upstream commit 14891c316ca7e15d81dba78f30fb630e3f9ee2c9 ]
So the output is consistent with other asics.
Reviewed-by: Evan Quan
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
index d493a3f8c07a6..b68bf8dcfa783 100644
--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
@@ -1388,12 +1388,17 @@ static int arcturus_get_power_profile_mode(struct
smu_context *smu,
"VR",
"COMPUTE",
"CUSTOM"};
+ static const char *title[] = {
+ "PROFILE_INDEX(NAME)"};
uint32_t i, size = 0;
int16_t workload_type = 0;
if (!smu->pm_enabled || !buf)
return -EINVAL;
+ size += sprintf(buf + size, "%16s\n",
+ title[0]);
+
for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
/*
* Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
--
2.20.1
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[PATCH AUTOSEL 5.4 07/52] drm/amd/display: Map DSC resources 1-to-1 if numbers of OPPs and DSCs are equal
From: Nikola Cornij
[ Upstream commit a1fc44b609b4e9c0941f0e4a1fc69d367af5ab69 ]
[why]
On ASICs where number of DSCs is the same as OPPs there's no need
for DSC resource management. Mappping 1-to-1 fixes mode-set- or S3-
-related issues for such platforms.
[how]
Map DSC resources 1-to-1 to pipes only if number of OPPs is the same
as number of DSCs. This will still keep other ASICs working.
A follow-up patch to fix mode-set issues on those ASICs will be
required if testing shows issues with mode set.
Signed-off-by: Nikola Cornij
Reviewed-by: Dmytro Laktyushkin
Acked-by: Leo Li
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
.../gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 6b2f2f1a1c9ce..d95b265ae9b85 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -1419,13 +1419,20 @@ enum dc_status dcn20_build_mapped_resource(const struct
dc *dc, struct dc_state
static void acquire_dsc(struct resource_context *res_ctx,
const struct resource_pool *pool,
- struct display_stream_compressor **dsc)
+ struct display_stream_compressor **dsc,
+ int pipe_idx)
{
int i;
ASSERT(*dsc == NULL);
*dsc = NULL;
+ if (pool->res_cap->num_dsc == pool->res_cap->num_opp) {
+ *dsc = pool->dscs[pipe_idx];
+ res_ctx->is_dsc_acquired[pipe_idx] = true;
+ return;
+ }
+
/* Find first free DSC */
for (i = 0; i < pool->res_cap->num_dsc; i++)
if (!res_ctx->is_dsc_acquired[i]) {
@@ -1468,7 +1475,7 @@ static enum dc_status add_dsc_to_stream_resource(struct
dc *dc,
if (pipe_ctx->stream != dc_stream)
continue;
- acquire_dsc(&dc_ctx->res_ctx, pool, &pipe_ctx->stream_res.dsc);
+ acquire_dsc(&dc_ctx->res_ctx, pool, &pipe_ctx->stream_res.dsc,
i);
/* The number of DSCs can be less than the number of pipes */
if (!pipe_ctx->stream_res.dsc) {
@@ -1669,7 +1676,7 @@ static bool dcn20_split_stream_for_odm(
next_odm_pipe->stream_res.opp = pool->opps[next_odm_pipe->pipe_idx];
#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
if (next_odm_pipe->stream->timing.flags.DSC == 1) {
- acquire_dsc(res_ctx, pool, &next_odm_pipe->stream_res.dsc);
+ acquire_dsc(res_ctx, pool, &next_odm_pipe->stream_res.dsc,
next_odm_pipe->pipe_idx);
ASSERT(next_odm_pipe->stream_res.dsc);
if (next_odm_pipe->stream_res.dsc == NULL)
return false;
--
2.20.1
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[PATCH AUTOSEL 5.4 11/52] drm/amd/display: update dispclk and dppclk vco frequency
From: Eric Yang
[ Upstream commit 44ce6c3dc8479bb3ed68df13b502b0901675e7d6 ]
Value obtained from DV is not allowing 8k60 CTA mode with DSC to
pass, after checking real value being used in hw, find out that
correct value is 3600, which will allow that mode.
Signed-off-by: Eric Yang
Reviewed-by: Tony Cheng
Acked-by: Leo Li
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index de182185fe1f5..b0e5e64df2127 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -258,7 +258,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = {
.vmm_page_size_bytes = 4096,
.dram_clock_change_latency_us = 23.84,
.return_bus_width_bytes = 64,
- .dispclk_dppclk_vco_speed_mhz = 3550,
+ .dispclk_dppclk_vco_speed_mhz = 3600,
.xfc_bus_transport_time_us = 4,
.xfc_xbuf_latency_tolerance_us = 4,
.use_urgent_burst_bw = 1,
--
2.20.1
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[PATCH AUTOSEL 5.4 09/52] drm/amd/display: Change the delay time before enabling FEC
From: "Leo (Hanghong) Ma"
[ Upstream commit 28fa24ad14e8f7d23c62283eaf9c79b4fd165c16 ]
[why]
DP spec requires 1000 symbols delay between the end of link training
and enabling FEC in the stream. Currently we are using 1 miliseconds
delay which is not accurate.
[how]
One lane RBR should have the maximum time for transmitting 1000 LL
codes which is 6.173 us. So using 7 microseconds delay instead of
1 miliseconds.
Signed-off-by: Leo (Hanghong) Ma
Reviewed-by: Harry Wentland
Reviewed-by: Nikola Cornij
Acked-by: Leo Li
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index f5742719b5d9b..b6e68e9c81d11 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -3490,7 +3490,14 @@ void dp_set_fec_enable(struct dc_link *link, bool enable)
if (link_enc->funcs->fec_set_enable &&
link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
if (link->fec_state == dc_link_fec_ready && enable) {
- msleep(1);
+ /* Accord to DP spec, FEC enable sequence can first
+* be transmitted anytime after 1000 LL codes have
+* been transmitted on the link after link training
+* completion. Using 1 lane RBR should have the maximum
+* time for transmitting 1000 LL codes which is 6.173
us.
+* So use 7 microseconds delay instead.
+*/
+ udelay(7);
link_enc->funcs->fec_set_enable(link_enc, true);
link->fec_state = dc_link_fec_enabled;
} else if (link->fec_state == dc_link_fec_enabled && !enable) {
--
2.20.1
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[PATCH AUTOSEL 4.19 04/34] drm/amdgpu: add cache flush workaround to gfx8 emit_fence
From: Pierre-Eric Pelloux-Prayer
[ Upstream commit bf26da927a1cd57c9deb2db29ae8cf276ba8b17b ]
The same workaround is used for gfx7.
Both PAL and Mesa use it for gfx8 too, so port this commit to
gfx_v8_0_ring_emit_fence_gfx.
Signed-off-by: Pierre-Eric Pelloux-Prayer
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 22 +++---
1 file changed, 19 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 5a9534a82d409..e1cb7fa89e4d6 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -6405,7 +6405,23 @@ static void gfx_v8_0_ring_emit_fence_gfx(struct
amdgpu_ring *ring, u64 addr,
bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
- /* EVENT_WRITE_EOP - flush caches, send int */
+ /* Workaround for cache flush problems. First send a dummy EOP
+* event down the pipe with seq one below.
+*/
+ amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
+ amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
+EOP_TC_ACTION_EN |
+EOP_TC_WB_ACTION_EN |
+EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
+EVENT_INDEX(5)));
+ amdgpu_ring_write(ring, addr & 0xfffc);
+ amdgpu_ring_write(ring, (upper_32_bits(addr) & 0x) |
+ DATA_SEL(1) | INT_SEL(0));
+ amdgpu_ring_write(ring, lower_32_bits(seq - 1));
+ amdgpu_ring_write(ring, upper_32_bits(seq - 1));
+
+ /* Then send the real EOP event down the pipe:
+* EVENT_WRITE_EOP - flush caches, send int */
amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
EOP_TC_ACTION_EN |
@@ -7154,7 +7170,7 @@ static const struct amdgpu_ring_funcs
gfx_v8_0_ring_funcs_gfx = {
5 + /* COND_EXEC */
7 + /* PIPELINE_SYNC */
VI_FLUSH_GPU_TLB_NUM_WREG * 5 + 9 + /* VM_FLUSH */
- 8 + /* FENCE for VM_FLUSH */
+ 12 + /* FENCE for VM_FLUSH */
20 + /* GDS switch */
4 + /* double SWITCH_BUFFER,
the first COND_EXEC jump to the place just
@@ -7166,7 +7182,7 @@ static const struct amdgpu_ring_funcs
gfx_v8_0_ring_funcs_gfx = {
31 + /* DE_META */
3 + /* CNTX_CTRL */
5 + /* HDP_INVL */
- 8 + 8 + /* FENCE x2 */
+ 12 + 12 + /* FENCE x2 */
2, /* SWITCH_BUFFER */
.emit_ib_size = 4, /* gfx_v8_0_ring_emit_ib_gfx */
.emit_ib = gfx_v8_0_ring_emit_ib_gfx,
--
2.20.1
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[PATCH AUTOSEL 4.19 05/34] drm/amd/display: Fixed kernel panic when booting with DP-to-HDMI dongle
From: David Galiffi
[ Upstream commit a51d9f8fe756beac51ce26ef54195da00a260d13 ]
[Why]
In dc_link_is_dp_sink_present, if dal_ddc_open fails, then
dal_gpio_destroy_ddc is called, destroying pin_data and pin_clock. They
are created only on dc_construct, and next aux access will cause a panic.
[How]
Instead of calling dal_gpio_destroy_ddc, call dal_ddc_close.
Signed-off-by: David Galiffi
Reviewed-by: Tony Cheng
Acked-by: Leo Li
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 23a7ef97afdd2..33c8eda97457f 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -348,7 +348,7 @@ bool dc_link_is_dp_sink_present(struct dc_link *link)
if (GPIO_RESULT_OK != dal_ddc_open(
ddc, GPIO_MODE_INPUT, GPIO_DDC_CONFIG_TYPE_MODE_I2C)) {
- dal_gpio_destroy_ddc(&ddc);
+ dal_ddc_close(ddc);
return present;
}
--
2.20.1
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[PATCH AUTOSEL 4.19 03/34] drm/amdgpu: add check before enabling/disabling broadcast mode
From: Guchun Chen
[ Upstream commit 6e807535dae5dbbd53bcc5e81047a20bf5eb08ea ]
When security violation from new vbios happens, data fabric is
risky to stop working. So prevent the direct access to DF
mmFabricConfigAccessControl from the new vbios and onwards.
Signed-off-by: Guchun Chen
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/amdgpu/df_v3_6.c | 38
1 file changed, 22 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
index d5ebe566809b2..a1c941229f4b3 100644
--- a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
+++ b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
@@ -75,23 +75,29 @@ static void df_v3_6_update_medium_grain_clock_gating(struct
amdgpu_device *adev,
{
u32 tmp;
- /* Put DF on broadcast mode */
- adev->df_funcs->enable_broadcast_mode(adev, true);
-
- if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DF_MGCG)) {
- tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
- tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
- tmp |= DF_V3_6_MGCG_ENABLE_15_CYCLE_DELAY;
- WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp);
- } else {
- tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
- tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
- tmp |= DF_V3_6_MGCG_DISABLE;
- WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp);
+ if (adev->cg_flags & AMD_CG_SUPPORT_DF_MGCG) {
+ /* Put DF on broadcast mode */
+ adev->df_funcs->enable_broadcast_mode(adev, true);
+
+ if (enable) {
+ tmp = RREG32_SOC15(DF, 0,
+ mmDF_PIE_AON0_DfGlobalClkGater);
+ tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
+ tmp |= DF_V3_6_MGCG_ENABLE_15_CYCLE_DELAY;
+ WREG32_SOC15(DF, 0,
+ mmDF_PIE_AON0_DfGlobalClkGater, tmp);
+ } else {
+ tmp = RREG32_SOC15(DF, 0,
+ mmDF_PIE_AON0_DfGlobalClkGater);
+ tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
+ tmp |= DF_V3_6_MGCG_DISABLE;
+ WREG32_SOC15(DF, 0,
+ mmDF_PIE_AON0_DfGlobalClkGater, tmp);
+ }
+
+ /* Exit broadcast mode */
+ adev->df_funcs->enable_broadcast_mode(adev, false);
}
-
- /* Exit broadcast mode */
- adev->df_funcs->enable_broadcast_mode(adev, false);
}
static void df_v3_6_get_clockgating_state(struct amdgpu_device *adev,
--
2.20.1
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[PATCH ] drm/radeon: Fix potential buffer overflow in ci_set_mc_special_registers()
Hi,
The length of table->mc_reg_address is SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE.
In ci_set_mc_special_registers(), the boundary checking
here("if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)") allows 'j' equal to
SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE which can easily cause the
table->mc_reg_address to read out of bounds.
To solve this problem, we change ">" to ">=" and check this boundary
of table->mc_reg_address after "pi->mem_gddr5" is false.
Signed-off-by: chenmaodong
---
drivers/gpu/drm/radeon/ci_dpm.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/radeon/ci_dpm.c b/drivers/gpu/drm/radeon/ci_dpm.c
index a97294a..42ef745a 100644
--- a/drivers/gpu/drm/radeon/ci_dpm.c
+++ b/drivers/gpu/drm/radeon/ci_dpm.c
@@ -4364,10 +4364,10 @@ static int ci_set_mc_special_registers(struct
radeon_device *rdev,
table->mc_reg_table_entry[k].mc_data[j]
|= 0x100;
}
j++;
- if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
- return -EINVAL;
if (!pi->mem_gddr5) {
+ if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
+ return -EINVAL;
table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD
>> 2;
table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD
>> 2;
for (k = 0; k < table->num_entries; k++) {
--
2.7.4
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[PATCH] drm/amdgpu: Remove unneeded variable 'ret' in navi10_ih.c
Fixes coccicheck warning:
drivers/gpu/drm/amd/amdgpu/navi10_ih.c:113:5-8: Unneeded variable: "ret".
Return "0" on line 182
Reported-by: Hulk Robot
Signed-off-by: Ma Feng
---
drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
index 9af7356..f737ce4 100644
--- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
@@ -110,7 +110,6 @@ static uint32_t navi10_ih_rb_cntl(struct amdgpu_ih_ring
*ih, uint32_t ih_rb_cntl
static int navi10_ih_irq_init(struct amdgpu_device *adev)
{
struct amdgpu_ih_ring *ih = &adev->irq.ih;
- int ret = 0;
u32 ih_rb_cntl, ih_doorbell_rtpr, ih_chicken;
u32 tmp;
@@ -179,7 +178,7 @@ static int navi10_ih_irq_init(struct amdgpu_device *adev)
/* enable interrupts */
navi10_ih_enable_interrupts(adev);
- return ret;
+ return 0;
}
/**
--
2.6.2
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[PATCH] drm/amdgpu: Remove unneeded variable 'ret' in amdgpu_device.c
Fixes coccicheck warning:
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1036:5-8: Unneeded variable: "ret".
Return "0" on line 1079
Reported-by: Hulk Robot
Signed-off-by: Ma Feng
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 080ec18..6a4b142 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1033,8 +1033,6 @@ static void
amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev)
*/
static int amdgpu_device_check_arguments(struct amdgpu_device *adev)
{
- int ret = 0;
-
if (amdgpu_sched_jobs < 4) {
dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
amdgpu_sched_jobs);
@@ -1076,7 +1074,7 @@ static int amdgpu_device_check_arguments(struct
amdgpu_device *adev)
adev->tmz.enabled = amdgpu_is_tmz(adev);
- return ret;
+ return 0;
}
/**
--
2.6.2
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Re: [PATCH 1/2] drm/amdgpu: update the method to get fb_loc of memory training(V4)
On Thu, Dec 19, 2019 at 9:00 PM Yin, Tianci (Rico) wrote:
>
> [AMD Official Use Only - Internal Distribution Only]
>
>
> Hi Luben,
>
> May I have your Review-by?
>
Series is:
Reviewed-by: Alex Deucher
> Thanks a lot!
> Rico
>
> From: Tuikov, Luben
> Sent: Friday, December 20, 2019 3:47
> To: Yin, Tianci (Rico) ; amd-gfx@lists.freedesktop.org
>
> Cc: Koenig, Christian ; Deucher, Alexander
> ; Zhang, Hawking ; Xu,
> Feifei ; Yuan, Xiaojie ; Long, Gang
> ; Wang, Kevin(Yang)
> Subject: Re: [PATCH 1/2] drm/amdgpu: update the method to get fb_loc of
> memory training(V4)
>
> Yep! That's perfect--good job!
>
> Regards,
> Luben
>
> On 2019-12-19 04:16, Tianci Yin wrote:
> > From: "Tianci.Yin"
> >
> > The method of getting fb_loc changed from parsing VBIOS to
> > taking certain offset from top of VRAM
> >
> > Change-Id: I053b42fdb1d822722fa7980b2cd9f86b3fdce539
> > Signed-off-by: Tianci.Yin
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 +-
> > drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 2 +-
> > .../gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | 38 ++-
> > .../gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h | 2 +-
> > drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 10 -
> > drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 7
> > drivers/gpu/drm/amd/include/atomfirmware.h| 14 ---
> > 7 files changed, 23 insertions(+), 53 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > index a78a363b1d71..fa2cf8e7bc07 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > @@ -642,9 +642,8 @@ struct amdgpu_fw_vram_usage {
> >struct amdgpu_bo *reserved_bo;
> >void *va;
> >
> > - /* Offset on the top of VRAM, used as c2p write buffer.
> > + /* GDDR6 training support flag.
> >*/
> > - u64 mem_train_fb_loc;
> >bool mem_train_support;
> > };
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
> > index 9ba80d828876..fdd52d86a4d7 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
> > @@ -2022,7 +2022,7 @@ int amdgpu_atombios_init(struct amdgpu_device *adev)
> >if (adev->is_atom_fw) {
> >amdgpu_atomfirmware_scratch_regs_init(adev);
> >amdgpu_atomfirmware_allocate_fb_scratch(adev);
> > - ret = amdgpu_atomfirmware_get_mem_train_fb_loc(adev);
> > + ret = amdgpu_atomfirmware_get_mem_train_info(adev);
> >if (ret) {
> >DRM_ERROR("Failed to get mem train fb location.\n");
> >return ret;
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
> > index ff4eb96bdfb5..58f9d8c3a17a 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
> > @@ -525,16 +525,12 @@ static int gddr6_mem_train_support(struct
> > amdgpu_device *adev)
> >return ret;
> > }
> >
> > -int amdgpu_atomfirmware_get_mem_train_fb_loc(struct amdgpu_device *adev)
> > +int amdgpu_atomfirmware_get_mem_train_info(struct amdgpu_device *adev)
> > {
> >struct atom_context *ctx = adev->mode_info.atom_context;
> > - unsigned char *bios = ctx->bios;
> > - struct vram_reserve_block *reserved_block;
> > - int index, block_number;
> > + int index;
> >uint8_t frev, crev;
> >uint16_t data_offset, size;
> > - uint32_t start_address_in_kb;
> > - uint64_t offset;
> >int ret;
> >
> >adev->fw_vram_usage.mem_train_support = false;
> > @@ -569,32 +565,6 @@ int amdgpu_atomfirmware_get_mem_train_fb_loc(struct
> > amdgpu_device *adev)
> >return -EINVAL;
> >}
> >
> > - reserved_block = (struct vram_reserve_block *)
> > - (bios + data_offset + sizeof(struct
> > atom_common_table_header));
> > - block_number = ((unsigned int)size - sizeof(struct
> > atom_common_table_header))
> > - / sizeof(struct vram_reserve_block);
> > - reserved_block += (block_number > 0) ? block_number-1 : 0;
> > - DRM_DEBUG("block_number:0x%04x, last block: 0x%08xkb sz, %dkb fw,
> > %dkb drv.\n",
> > - block_number,
> > - le32_to_cpu(reserved_block->start_address_in_kb),
> > - le16_to_cpu(reserved_block->used_by_firmware_in_kb),
> > - le16_to_cpu(reserved_block->used_by_driver_in_kb));
> > - if (reserved_block->used_by_firmware_in_kb > 0) {
> > - start_address_in_kb =
> > le32_to_cpu(reserved_block->start_address_in_kb);
> > - offset = (uint64_t)start_address_in_kb * ONE_KiB;
> > - if ((offset & (ONE_MiB - 1)) < (4 * ONE_KiB + 1) ) {
> > -
Re: [PATCH 4/4] drm/amdkfd: Avoid hanging hardware in stop_cpsch
Looks like patch 2 is not related to this serial , but anyway .
Patch 1,2,3 are reviewed by shaoyunl
For patch 4 , is it possible we directly check dqm->is_hws_hang ||
dqm->is_resetting inside function kq_uninitialize. so we don't need
other interface change .
I think even Inside that kq_uninitialize function , we still can get dqm
as kq->dev->dqm .
shaoyun.liu
On 2019-12-20 3:30 a.m., Felix Kuehling wrote:
Don't use the HWS if it's known to be hanging. In a reset also
don't try to destroy the HIQ because that may hang on SRIOV if the
KIQ is unresponsive.
Signed-off-by: Felix Kuehling
---
.../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c| 12
drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c| 8
drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c | 4 ++--
drivers/gpu/drm/amd/amdkfd/kfd_priv.h| 4 ++--
.../gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 2 +-
5 files changed, 17 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index a7e9ec1b3ce3..d7eb6ac37f62 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -946,7 +946,7 @@ static int start_nocpsch(struct device_queue_manager *dqm)
static int stop_nocpsch(struct device_queue_manager *dqm)
{
if (dqm->dev->device_info->asic_family == CHIP_HAWAII)
- pm_uninit(&dqm->packets);
+ pm_uninit(&dqm->packets, false);
dqm->sched_running = false;
return 0;
@@ -1114,20 +1114,24 @@ static int start_cpsch(struct device_queue_manager *dqm)
return 0;
fail_allocate_vidmem:
fail_set_sched_resources:
- pm_uninit(&dqm->packets);
+ pm_uninit(&dqm->packets, false);
fail_packet_manager_init:
return retval;
}
static int stop_cpsch(struct device_queue_manager *dqm)
{
+ bool hanging;
+kq_uninitialize(
dqm_lock(dqm);
- unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0);
+ if (!dqm->is_hws_hang)
+ unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0);
+ hanging = dqm->is_hws_hang || dqm->is_resetting;
dqm->sched_running = false;
dqm_unlock(dqm);
kfd_gtt_sa_free(dqm->dev, dqm->fence_mem);
- pm_uninit(&dqm->packets);
+ pm_uninit(&dqm->packets, hanging);
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
index 2d56dc534459..bae706462f96 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
@@ -195,9 +195,9 @@ static bool kq_initialize(struct kernel_queue *kq, struct
kfd_dev *dev,
}
/* Uninitialize a kernel queue and free all its memory usages. */
-static void kq_uninitialize(struct kernel_queue *kq)
+static void kq_uninitialize(struct kernel_queue *kq, bool hanging)
{
- if (kq->queue->properties.type == KFD_QUEUE_TYPE_HIQ)
+ if (kq->queue->properties.type == KFD_QUEUE_TYPE_HIQ && !hanging)
kq->mqd_mgr->destroy_mqd(kq->mqd_mgr,
kq->queue->mqd,
KFD_PREEMPT_TYPE_WAVEFRONT_RESET,
@@ -337,9 +337,9 @@ struct kernel_queue *kernel_queue_init(struct kfd_dev *dev,
return NULL;
}
-void kernel_queue_uninit(struct kernel_queue *kq)
+void kernel_queue_uninit(struct kernel_queue *kq, bool hanging)
{
- kq_uninitialize(kq);
+ kq_uninitialize(kq, hanging);
kfree(kq);
}
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
index 6cabed06ef5d..dc406e6dee23 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
@@ -264,10 +264,10 @@ int pm_init(struct packet_manager *pm, struct
device_queue_manager *dqm)
return 0;
}
-void pm_uninit(struct packet_manager *pm)
+void pm_uninit(struct packet_manager *pm, bool hanging)
{
mutex_destroy(&pm->lock);
- kernel_queue_uninit(pm->priv_queue);
+ kernel_queue_uninit(pm->priv_queue, hanging);
}
int pm_send_set_resources(struct packet_manager *pm,
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
index 087e96838997..8ac680dc90f1 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
@@ -883,7 +883,7 @@ struct device_queue_manager
*device_queue_manager_init(struct kfd_dev *dev);
void device_queue_manager_uninit(struct device_queue_manager *dqm);
struct kernel_queue *kernel_queue_init(struct kfd_dev *dev,
enum kfd_queue_type type);
-void kernel_queue_uninit(struct kernel_queue *kq);
+void kernel_queue_uninit(struct kernel_queue *kq, bool ha
Re: [PATCH 4/4] drm/amdkfd: Avoid hanging hardware in stop_cpsch
dqm->is_hws_hang is protected by the DQM lock. kq_uninitialize runs
outside that lock protection. Therefore I opted to pass in the hanging
flag as a parameter. It also keeps the logic that decides all of that
inside the device queue manager, which I think is cleaner.
I was trying to clean this up further by moving the pm_init/pm_uninit
out of the start_cpsch/stop_cpsch sequence, but gave up on that idea
when I found out that I can't create the kernel queue in the DQM
initialize function because dev->dqm isn't initialized at that time yet.
Regards,
Felix
On 2019-12-20 10:56, shaoyunl wrote:
Looks like patch 2 is not related to this serial , but anyway .
Patch 1,2,3 are reviewed by shaoyunl
For patch 4 , is it possible we directly check dqm->is_hws_hang ||
dqm->is_resetting inside function kq_uninitialize. so we don't need
other interface change .
I think even Inside that kq_uninitialize function , we still can get
dqm as kq->dev->dqm .
shaoyun.liu
On 2019-12-20 3:30 a.m., Felix Kuehling wrote:
Don't use the HWS if it's known to be hanging. In a reset also
don't try to destroy the HIQ because that may hang on SRIOV if the
KIQ is unresponsive.
Signed-off-by: Felix Kuehling
---
.../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 12
drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c | 8
drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c | 4 ++--
drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 4 ++--
.../gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 2 +-
5 files changed, 17 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index a7e9ec1b3ce3..d7eb6ac37f62 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -946,7 +946,7 @@ static int start_nocpsch(struct
device_queue_manager *dqm)
static int stop_nocpsch(struct device_queue_manager *dqm)
{
if (dqm->dev->device_info->asic_family == CHIP_HAWAII)
- pm_uninit(&dqm->packets);
+ pm_uninit(&dqm->packets, false);
dqm->sched_running = false;
return 0;
@@ -1114,20 +1114,24 @@ static int start_cpsch(struct
device_queue_manager *dqm)
return 0;
fail_allocate_vidmem:
fail_set_sched_resources:
- pm_uninit(&dqm->packets);
+ pm_uninit(&dqm->packets, false);
fail_packet_manager_init:
return retval;
}
static int stop_cpsch(struct device_queue_manager *dqm)
{
+ bool hanging;
+kq_uninitialize(
dqm_lock(dqm);
- unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0);
+ if (!dqm->is_hws_hang)
+ unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0);
+ hanging = dqm->is_hws_hang || dqm->is_resetting;
dqm->sched_running = false;
dqm_unlock(dqm);
kfd_gtt_sa_free(dqm->dev, dqm->fence_mem);
- pm_uninit(&dqm->packets);
+ pm_uninit(&dqm->packets, hanging);
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
index 2d56dc534459..bae706462f96 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
@@ -195,9 +195,9 @@ static bool kq_initialize(struct kernel_queue
*kq, struct kfd_dev *dev,
}
/* Uninitialize a kernel queue and free all its memory usages. */
-static void kq_uninitialize(struct kernel_queue *kq)
+static void kq_uninitialize(struct kernel_queue *kq, bool hanging)
{
- if (kq->queue->properties.type == KFD_QUEUE_TYPE_HIQ)
+ if (kq->queue->properties.type == KFD_QUEUE_TYPE_HIQ && !hanging)
kq->mqd_mgr->destroy_mqd(kq->mqd_mgr,
kq->queue->mqd,
KFD_PREEMPT_TYPE_WAVEFRONT_RESET,
@@ -337,9 +337,9 @@ struct kernel_queue *kernel_queue_init(struct
kfd_dev *dev,
return NULL;
}
-void kernel_queue_uninit(struct kernel_queue *kq)
+void kernel_queue_uninit(struct kernel_queue *kq, bool hanging)
{
- kq_uninitialize(kq);
+ kq_uninitialize(kq, hanging);
kfree(kq);
}
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
index 6cabed06ef5d..dc406e6dee23 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
@@ -264,10 +264,10 @@ int pm_init(struct packet_manager *pm, struct
device_queue_manager *dqm)
return 0;
}
-void pm_uninit(struct packet_manager *pm)
+void pm_uninit(struct packet_manager *pm, bool hanging)
{
mutex_destroy(&pm->lock);
- kernel_queue_uninit(pm->priv_queue);
+ kernel_queue_uninit(pm->priv_queue, hanging);
}
int pm_send_set_resources(struct packet_manager *pm,
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
index 087e96838997..8ac680dc90f1 100644
--- a/dr
RE: [PATCH 3/4] drm/amdkfd: Improve HWS hang detection and handling
[AMD Official Use Only - Internal Distribution Only]
With this improvement, it is still possible that two reset be scheduled. There
is a period of time after HWS hang and before kfd pre-reset is called, during
which, if a thread already passed the is_hws_hang check but was scheduled out,
then it will also schedule another reset. The whole sequence is:
Thread 1: call unmap_queues_cpsch, pass the is_hws_hang, scheduled out before
sending unmap command to HWS
Thread 2: send unmap to HWS ->hang, schedule a reset
Thread1: before the reset worker thread is run(resetting is still false),
thread1 continus, another reset is scheduled.
Regards,
Oak
-Original Message-
From: amd-gfx On Behalf Of Felix
Kuehling
Sent: Friday, December 20, 2019 3:30 AM
To: amd-gfx@lists.freedesktop.org
Subject: [PATCH 3/4] drm/amdkfd: Improve HWS hang detection and handling
Move HWS hand detection into unmap_queues_cpsch to catch hangs in all cases. If
this happens during a reset, don't schedule another reset because the reset
already in progress is expected to take care of it.
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdkfd/kfd_device.c | 3 +++
.../drm/amd/amdkfd/kfd_device_queue_manager.c | 27 ++-
.../drm/amd/amdkfd/kfd_device_queue_manager.h | 2 ++
3 files changed, 26 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index c6b6901bbda3..2a9e40131735 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -728,6 +728,9 @@ int kgd2kfd_pre_reset(struct kfd_dev *kfd) {
if (!kfd->init_complete)
return 0;
+
+ kfd->dqm->ops.pre_reset(kfd->dqm);
+
kgd2kfd_suspend(kfd);
kfd_signal_reset_event(kfd);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index 558c0ad81848..a7e9ec1b3ce3 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -952,6 +952,13 @@ static int stop_nocpsch(struct device_queue_manager *dqm)
return 0;
}
+static void pre_reset(struct device_queue_manager *dqm) {
+ dqm_lock(dqm);
+ dqm->is_resetting = true;
+ dqm_unlock(dqm);
+}
+
static int allocate_sdma_queue(struct device_queue_manager *dqm,
struct queue *q)
{
@@ -1099,6 +1106,7 @@ static int start_cpsch(struct device_queue_manager *dqm)
dqm_lock(dqm);
/* clear hang status when driver try to start the hw scheduler */
dqm->is_hws_hang = false;
+ dqm->is_resetting = false;
dqm->sched_running = true;
execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
dqm_unlock(dqm);
@@ -1351,8 +1359,17 @@ static int unmap_queues_cpsch(struct
device_queue_manager *dqm,
/* should be timed out */
retval = amdkfd_fence_wait_timeout(dqm->fence_addr, KFD_FENCE_COMPLETED,
queue_preemption_timeout_ms);
- if (retval)
+ if (retval) {
+ pr_err("The cp might be in an unrecoverable state due to an
unsuccessful queues preemption\n");
+ dqm->is_hws_hang = true;
+ /* It's possible we're detecting a HWS hang in the
+* middle of a GPU reset. No need to schedule another
+* reset in this case.
+*/
+ if (!dqm->is_resetting)
+ schedule_work(&dqm->hw_exception_work);
return retval;
+ }
pm_release_ib(&dqm->packets);
dqm->active_runlist = false;
@@ -1370,12 +1387,8 @@ static int execute_queues_cpsch(struct
device_queue_manager *dqm,
if (dqm->is_hws_hang)
return -EIO;
retval = unmap_queues_cpsch(dqm, filter, filter_param);
- if (retval) {
- pr_err("The cp might be in an unrecoverable state due to an
unsuccessful queues preemption\n");
- dqm->is_hws_hang = true;
- schedule_work(&dqm->hw_exception_work);
+ if (retval)
return retval;
- }
return map_queues_cpsch(dqm);
}
@@ -1769,6 +1782,7 @@ struct device_queue_manager
*device_queue_manager_init(struct kfd_dev *dev)
dqm->ops.initialize = initialize_cpsch;
dqm->ops.start = start_cpsch;
dqm->ops.stop = stop_cpsch;
+ dqm->ops.pre_reset = pre_reset;
dqm->ops.destroy_queue = destroy_queue_cpsch;
dqm->ops.update_queue = update_queue;
dqm->ops.register_process = register_process; @@ -1787,6
+1801,7 @@ struct device_queue_manager *device_queue_manager_init(struct
kfd_dev *dev)
/* initialize dqm for no cp scheduling */
dqm->ops.start = start_nocpsch;
dqm->ops.stop = st
RE: [PATCH 4/4] drm/amdkfd: Avoid hanging hardware in stop_cpsch
[AMD Official Use Only - Internal Distribution Only]
Regards,
Oak
-Original Message-
From: amd-gfx On Behalf Of Felix
Kuehling
Sent: Friday, December 20, 2019 3:30 AM
To: amd-gfx@lists.freedesktop.org
Subject: [PATCH 4/4] drm/amdkfd: Avoid hanging hardware in stop_cpsch
Don't use the HWS if it's known to be hanging. In a reset also don't try to
destroy the HIQ because that may hang on SRIOV if the KIQ is unresponsive.
Signed-off-by: Felix Kuehling
---
.../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c| 12
drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c| 8
drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c | 4 ++--
drivers/gpu/drm/amd/amdkfd/kfd_priv.h| 4 ++--
.../gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 2 +-
5 files changed, 17 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index a7e9ec1b3ce3..d7eb6ac37f62 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -946,7 +946,7 @@ static int start_nocpsch(struct device_queue_manager *dqm)
static int stop_nocpsch(struct device_queue_manager *dqm) {
if (dqm->dev->device_info->asic_family == CHIP_HAWAII)
- pm_uninit(&dqm->packets);
+ pm_uninit(&dqm->packets, false);
dqm->sched_running = false;
return 0;
@@ -1114,20 +1114,24 @@ static int start_cpsch(struct device_queue_manager *dqm)
return 0;
fail_allocate_vidmem:
fail_set_sched_resources:
- pm_uninit(&dqm->packets);
+ pm_uninit(&dqm->packets, false);
fail_packet_manager_init:
return retval;
}
static int stop_cpsch(struct device_queue_manager *dqm) {
+ bool hanging;
+
dqm_lock(dqm);
- unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0);
+ if (!dqm->is_hws_hang)
+ unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0);
+ hanging = dqm->is_hws_hang || dqm->is_resetting;
[Oak] I don't think dqm->is_resetting is necessary. If is_resetting is true,
is_hws_hang is always true. Those two flags are always the same except a period
during which hws hang is detected but kfd_pre_reset is not called. In this
period, hang is true but resetting is false, so "||resetting" doesn't help.
Also see my comment on the 3rd patch.
dqm->sched_running = false;
dqm_unlock(dqm);
kfd_gtt_sa_free(dqm->dev, dqm->fence_mem);
- pm_uninit(&dqm->packets);
+ pm_uninit(&dqm->packets, hanging);
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
index 2d56dc534459..bae706462f96 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
@@ -195,9 +195,9 @@ static bool kq_initialize(struct kernel_queue *kq, struct
kfd_dev *dev, }
/* Uninitialize a kernel queue and free all its memory usages. */ -static void
kq_uninitialize(struct kernel_queue *kq)
+static void kq_uninitialize(struct kernel_queue *kq, bool hanging)
{
- if (kq->queue->properties.type == KFD_QUEUE_TYPE_HIQ)
+ if (kq->queue->properties.type == KFD_QUEUE_TYPE_HIQ && !hanging)
kq->mqd_mgr->destroy_mqd(kq->mqd_mgr,
kq->queue->mqd,
KFD_PREEMPT_TYPE_WAVEFRONT_RESET,
@@ -337,9 +337,9 @@ struct kernel_queue *kernel_queue_init(struct kfd_dev *dev,
return NULL;
}
-void kernel_queue_uninit(struct kernel_queue *kq)
+void kernel_queue_uninit(struct kernel_queue *kq, bool hanging)
{
- kq_uninitialize(kq);
+ kq_uninitialize(kq, hanging);
kfree(kq);
}
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
index 6cabed06ef5d..dc406e6dee23 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
@@ -264,10 +264,10 @@ int pm_init(struct packet_manager *pm, struct
device_queue_manager *dqm)
return 0;
}
-void pm_uninit(struct packet_manager *pm)
+void pm_uninit(struct packet_manager *pm, bool hanging)
{
mutex_destroy(&pm->lock);
- kernel_queue_uninit(pm->priv_queue);
+ kernel_queue_uninit(pm->priv_queue, hanging);
}
int pm_send_set_resources(struct packet_manager *pm, diff --git
a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
index 087e96838997..8ac680dc90f1 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
@@ -883,7 +883,7 @@ struct device_queue_manager
*device_queue_manager_init(struct kfd_dev *dev); void
device_queue_manager_uninit(struct device_queue_manager *dqm); struct
kernel_queue *kernel_queue_init(struct kfd_dev *dev,
Re: [PATCH 4/4] drm/amdkfd: Avoid hanging hardware in stop_cpsch
On 2019-12-20 12:22, Zeng, Oak wrote:
[AMD Official Use Only - Internal Distribution Only]
Regards,
Oak
-Original Message-
From: amd-gfx On Behalf Of Felix
Kuehling
Sent: Friday, December 20, 2019 3:30 AM
To: amd-gfx@lists.freedesktop.org
Subject: [PATCH 4/4] drm/amdkfd: Avoid hanging hardware in stop_cpsch
Don't use the HWS if it's known to be hanging. In a reset also don't try to
destroy the HIQ because that may hang on SRIOV if the KIQ is unresponsive.
Signed-off-by: Felix Kuehling
---
.../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c| 12
drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c| 8
drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c | 4 ++--
drivers/gpu/drm/amd/amdkfd/kfd_priv.h| 4 ++--
.../gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 2 +-
5 files changed, 17 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index a7e9ec1b3ce3..d7eb6ac37f62 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -946,7 +946,7 @@ static int start_nocpsch(struct device_queue_manager *dqm)
static int stop_nocpsch(struct device_queue_manager *dqm) {
if (dqm->dev->device_info->asic_family == CHIP_HAWAII)
- pm_uninit(&dqm->packets);
+ pm_uninit(&dqm->packets, false);
dqm->sched_running = false;
return 0;
@@ -1114,20 +1114,24 @@ static int start_cpsch(struct device_queue_manager *dqm)
return 0;
fail_allocate_vidmem:
fail_set_sched_resources:
- pm_uninit(&dqm->packets);
+ pm_uninit(&dqm->packets, false);
fail_packet_manager_init:
return retval;
}
static int stop_cpsch(struct device_queue_manager *dqm) {
+ bool hanging;
+
dqm_lock(dqm);
- unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0);
+ if (!dqm->is_hws_hang)
+ unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0);
+ hanging = dqm->is_hws_hang || dqm->is_resetting;
[Oak] I don't think dqm->is_resetting is necessary. If is_resetting is true, is_hws_hang
is always true. Those two flags are always the same except a period during which hws hang is
detected but kfd_pre_reset is not called. In this period, hang is true but resetting is
false, so "||resetting" doesn't help.
This is not necessarily true. A GPU reset can be caused by amdgpu for
example when the graphics engine is hanging. In that case HWS isn't
necessarily hanging. I added "|| resetting" here to avoid touching
hardware in an unknown state in pm_uninit=>kq_uninitialize in this case.
Regards,
Felix
Also see my comment on the 3rd patch.
dqm->sched_running = false;
dqm_unlock(dqm);
kfd_gtt_sa_free(dqm->dev, dqm->fence_mem);
- pm_uninit(&dqm->packets);
+ pm_uninit(&dqm->packets, hanging);
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
index 2d56dc534459..bae706462f96 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
@@ -195,9 +195,9 @@ static bool kq_initialize(struct kernel_queue *kq, struct
kfd_dev *dev, }
/* Uninitialize a kernel queue and free all its memory usages. */ -static void kq_uninitialize(struct kernel_queue *kq)
+static void kq_uninitialize(struct kernel_queue *kq, bool hanging)
{
- if (kq->queue->properties.type == KFD_QUEUE_TYPE_HIQ)
+ if (kq->queue->properties.type == KFD_QUEUE_TYPE_HIQ && !hanging)
kq->mqd_mgr->destroy_mqd(kq->mqd_mgr,
kq->queue->mqd,
KFD_PREEMPT_TYPE_WAVEFRONT_RESET,
@@ -337,9 +337,9 @@ struct kernel_queue *kernel_queue_init(struct kfd_dev *dev,
return NULL;
}
-void kernel_queue_uninit(struct kernel_queue *kq)
+void kernel_queue_uninit(struct kernel_queue *kq, bool hanging)
{
- kq_uninitialize(kq);
+ kq_uninitialize(kq, hanging);
kfree(kq);
}
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
index 6cabed06ef5d..dc406e6dee23 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
@@ -264,10 +264,10 @@ int pm_init(struct packet_manager *pm, struct
device_queue_manager *dqm)
return 0;
}
-void pm_uninit(struct packet_manager *pm)
+void pm_uninit(struct packet_manager *pm, bool hanging)
{
mutex_destroy(&pm->lock);
- kernel_queue_uninit(pm->priv_queue);
+ kernel_queue_uninit(pm->priv_queue, hanging);
}
int pm_send_set_resources(struct packet_manager *pm, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
index
RE: [PATCH 4/4] drm/amdkfd: Avoid hanging hardware in stop_cpsch
[AMD Official Use Only - Internal Distribution Only]
I see. Thank you Felix for the explanation.
Regards,
Oak
-Original Message-
From: Kuehling, Felix
Sent: Friday, December 20, 2019 12:28 PM
To: Zeng, Oak ; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 4/4] drm/amdkfd: Avoid hanging hardware in stop_cpsch
On 2019-12-20 12:22, Zeng, Oak wrote:
> [AMD Official Use Only - Internal Distribution Only]
>
>
>
> Regards,
> Oak
>
> -Original Message-
> From: amd-gfx On Behalf Of
> Felix Kuehling
> Sent: Friday, December 20, 2019 3:30 AM
> To: amd-gfx@lists.freedesktop.org
> Subject: [PATCH 4/4] drm/amdkfd: Avoid hanging hardware in stop_cpsch
>
> Don't use the HWS if it's known to be hanging. In a reset also don't try to
> destroy the HIQ because that may hang on SRIOV if the KIQ is unresponsive.
>
> Signed-off-by: Felix Kuehling
> ---
> .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c| 12
> drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c| 8
> drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c | 4 ++--
> drivers/gpu/drm/amd/amdkfd/kfd_priv.h| 4 ++--
> .../gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 2 +-
> 5 files changed, 17 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> index a7e9ec1b3ce3..d7eb6ac37f62 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> @@ -946,7 +946,7 @@ static int start_nocpsch(struct device_queue_manager
> *dqm) static int stop_nocpsch(struct device_queue_manager *dqm) {
> if (dqm->dev->device_info->asic_family == CHIP_HAWAII)
> - pm_uninit(&dqm->packets);
> + pm_uninit(&dqm->packets, false);
> dqm->sched_running = false;
>
> return 0;
> @@ -1114,20 +1114,24 @@ static int start_cpsch(struct device_queue_manager
> *dqm)
> return 0;
> fail_allocate_vidmem:
> fail_set_sched_resources:
> - pm_uninit(&dqm->packets);
> + pm_uninit(&dqm->packets, false);
> fail_packet_manager_init:
> return retval;
> }
>
> static int stop_cpsch(struct device_queue_manager *dqm) {
> + bool hanging;
> +
> dqm_lock(dqm);
> - unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0);
> + if (!dqm->is_hws_hang)
> + unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0);
> + hanging = dqm->is_hws_hang || dqm->is_resetting;
> [Oak] I don't think dqm->is_resetting is necessary. If is_resetting is true,
> is_hws_hang is always true. Those two flags are always the same except a
> period during which hws hang is detected but kfd_pre_reset is not called. In
> this period, hang is true but resetting is false, so "||resetting" doesn't
> help.
This is not necessarily true. A GPU reset can be caused by amdgpu for example
when the graphics engine is hanging. In that case HWS isn't necessarily
hanging. I added "|| resetting" here to avoid touching hardware in an unknown
state in pm_uninit=>kq_uninitialize in this case.
Regards,
Felix
>
> Also see my comment on the 3rd patch.
>
> dqm->sched_running = false;
> dqm_unlock(dqm);
>
> kfd_gtt_sa_free(dqm->dev, dqm->fence_mem);
> - pm_uninit(&dqm->packets);
> + pm_uninit(&dqm->packets, hanging);
>
> return 0;
> }
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
> b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
> index 2d56dc534459..bae706462f96 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
> @@ -195,9 +195,9 @@ static bool kq_initialize(struct kernel_queue *kq,
> struct kfd_dev *dev, }
>
> /* Uninitialize a kernel queue and free all its memory usages. */
> -static void kq_uninitialize(struct kernel_queue *kq)
> +static void kq_uninitialize(struct kernel_queue *kq, bool hanging)
> {
> - if (kq->queue->properties.type == KFD_QUEUE_TYPE_HIQ)
> + if (kq->queue->properties.type == KFD_QUEUE_TYPE_HIQ && !hanging)
> kq->mqd_mgr->destroy_mqd(kq->mqd_mgr,
> kq->queue->mqd,
> KFD_PREEMPT_TYPE_WAVEFRONT_RESET, @@
> -337,9 +337,9 @@ struct
> kernel_queue *kernel_queue_init(struct kfd_dev *dev,
> return NULL;
> }
>
> -void kernel_queue_uninit(struct kernel_queue *kq)
> +void kernel_queue_uninit(struct kernel_queue *kq, bool hanging)
> {
> - kq_uninitialize(kq);
> + kq_uninitialize(kq, hanging);
> kfree(kq);
> }
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
> b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
> index 6cabed06ef5d..dc406e6dee23 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
> @@ -264,10 +264,10 @@ int pm_
Re: [PATCH] drm/dp_mst: clear time slots for ports invalid
Hi! I will try to review this patch today, must have gotten lost in the noise
On Fri, 2019-12-20 at 01:46 +, Lin, Wayne wrote:
> [AMD Official Use Only - Internal Distribution Only]
>
> Pinged.
> Hi, can someone help to review please.
>
> Thanks a lot.
>
> Regards,
> Wayne
>
>
> From: Wayne Lin
> Sent: Friday, December 6, 2019 16:39
> To: dri-de...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org
> Cc: Kazlauskas, Nicholas; Wentland, Harry; Zuo, Jerry; ly...@redhat.com;
> sta...@vger.kernel.org; Lin, Wayne
> Subject: [PATCH] drm/dp_mst: clear time slots for ports invalid
>
> [Why]
> When change the connection status in a MST topology, mst device
> which detect the event will send out CONNECTION_STATUS_NOTIFY messgae.
>
> e.g. src-mst-mst-sst => src-mst (unplug) mst-sst
>
> Currently, under the above case of unplugging device, ports which have
> been allocated payloads and are no longer in the topology still occupy
> time slots and recorded in proposed_vcpi[] of topology manager.
>
> If we don't clean up the proposed_vcpi[], when code flow goes to try to
> update payload table by calling drm_dp_update_payload_part1(), we will
> fail at checking port validation due to there are ports with proposed
> time slots but no longer in the mst topology. As the result of that, we
> will also stop updating the DPCD payload table of down stream port.
>
> [How]
> While handling the CONNECTION_STATUS_NOTIFY message, add a detection to
> see if the event indicates that a device is unplugged to an output port.
> If the detection is true, then iterrate over all proposed_vcpi[] to
> see whether a port of the proposed_vcpi[] is still in the topology or
> not. If the port is invalid, set its num_slots to 0.
>
> Thereafter, when try to update payload table by calling
> drm_dp_update_payload_part1(), we can successfully update the DPCD
> payload table of down stream port and clear the proposed_vcpi[] to NULL.
>
> Signed-off-by: Wayne Lin
> Cc: sta...@vger.kernel.org
> ---
> drivers/gpu/drm/drm_dp_mst_topology.c | 24 +++-
> 1 file changed, 23 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c
> b/drivers/gpu/drm/drm_dp_mst_topology.c
> index 5306c47dc820..2e236b6275c4 100644
> --- a/drivers/gpu/drm/drm_dp_mst_topology.c
> +++ b/drivers/gpu/drm/drm_dp_mst_topology.c
> @@ -2318,7 +2318,7 @@ drm_dp_mst_handle_conn_stat(struct drm_dp_mst_branch
> *mstb,
> {
> struct drm_dp_mst_topology_mgr *mgr = mstb->mgr;
> struct drm_dp_mst_port *port;
> - int old_ddps, ret;
> + int old_ddps, old_input, ret, i;
> u8 new_pdt;
> bool dowork = false, create_connector = false;
>
> @@ -2349,6 +2349,7 @@ drm_dp_mst_handle_conn_stat(struct drm_dp_mst_branch
> *mstb,
> }
>
> old_ddps = port->ddps;
> + old_input = port->input;
> port->input = conn_stat->input_port;
> port->mcs = conn_stat->message_capability_status;
> port->ldps = conn_stat->legacy_device_plug_status;
> @@ -2373,6 +2374,27 @@ drm_dp_mst_handle_conn_stat(struct drm_dp_mst_branch
> *mstb,
> dowork = false;
> }
>
> + if (!old_input && old_ddps != port->ddps && !port->ddps) {
> + for (i = 0; i < mgr->max_payloads; i++) {
> + struct drm_dp_vcpi *vcpi = mgr->proposed_vcpis[i];
> + struct drm_dp_mst_port *port_validated;
> +
> + if (vcpi) {
> + port_validated =
> + container_of(vcpi, struct
> drm_dp_mst_port, vcpi);
> + port_validated =
> + drm_dp_mst_topology_get_port_validat
> ed(mgr, port_validated);
> + if (!port_validated) {
> + mutex_lock(&mgr->payload_lock);
> + vcpi->num_slots = 0;
> + mutex_unlock(&mgr->payload_lock);
> + } else {
> + drm_dp_mst_topology_put_port(port_va
> lidated);
> + }
> + }
> + }
> + }
> +
> if (port->connector)
> drm_modeset_unlock(&mgr->base.lock);
> else if (create_connector)
> --
> 2.17.1
>
--
Cheers,
Lyude Paul
___
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amd-gfx@lists.freedesktop.org
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Re: [PATCH 3/4] drm/amdkfd: Improve HWS hang detection and handling
On 2019-12-20 12:18, Zeng, Oak wrote:
[AMD Official Use Only - Internal Distribution Only]
With this improvement, it is still possible that two reset be scheduled. There
is a period of time after HWS hang and before kfd pre-reset is called, during
which, if a thread already passed the is_hws_hang check but was scheduled out,
then it will also schedule another reset. The whole sequence is:
Thread 1: call unmap_queues_cpsch, pass the is_hws_hang, scheduled out before
sending unmap command to HWS
Thread 2: send unmap to HWS ->hang, schedule a reset
Thread1: before the reset worker thread is run(resetting is still false),
thread1 continus, another reset is scheduled.
Rescheduling the reset worker "before the reset worker thread is run"
results in the reset worker only running once. The work item can be on
the queue twice at the same time. The more interesting case is if the
reset worker is already running but hasn't called
amdgpu_amdkfd_pre_reset yet. In that case we may end up scheduling a
second reset. I can't think of a good way to prevent this race.
It gets more confusing when you consider that GPU resets can be
triggered outside of KFD. So a reset can start outside a KFD reset
worker thread and KFD can schedule another reset. I think the only place
to really prevent this type of race would be in
amdgpu_device_should_recover_gpu with some kind of reset decision flag
protected by a lock.
I could also try to get rid of the worker thread for GPU resets in KFD.
I think we created the worker to avoid locking issues, but there may be
better ways to do this.
Regards,
Felix
Regards,
Oak
-Original Message-
From: amd-gfx On Behalf Of Felix
Kuehling
Sent: Friday, December 20, 2019 3:30 AM
To: amd-gfx@lists.freedesktop.org
Subject: [PATCH 3/4] drm/amdkfd: Improve HWS hang detection and handling
Move HWS hand detection into unmap_queues_cpsch to catch hangs in all cases. If
this happens during a reset, don't schedule another reset because the reset
already in progress is expected to take care of it.
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdkfd/kfd_device.c | 3 +++
.../drm/amd/amdkfd/kfd_device_queue_manager.c | 27 ++-
.../drm/amd/amdkfd/kfd_device_queue_manager.h | 2 ++
3 files changed, 26 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index c6b6901bbda3..2a9e40131735 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -728,6 +728,9 @@ int kgd2kfd_pre_reset(struct kfd_dev *kfd) {
if (!kfd->init_complete)
return 0;
+
+ kfd->dqm->ops.pre_reset(kfd->dqm);
+
kgd2kfd_suspend(kfd);
kfd_signal_reset_event(kfd);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index 558c0ad81848..a7e9ec1b3ce3 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -952,6 +952,13 @@ static int stop_nocpsch(struct device_queue_manager *dqm)
return 0;
}
+static void pre_reset(struct device_queue_manager *dqm) {
+ dqm_lock(dqm);
+ dqm->is_resetting = true;
+ dqm_unlock(dqm);
+}
+
static int allocate_sdma_queue(struct device_queue_manager *dqm,
struct queue *q)
{
@@ -1099,6 +1106,7 @@ static int start_cpsch(struct device_queue_manager *dqm)
dqm_lock(dqm);
/* clear hang status when driver try to start the hw scheduler */
dqm->is_hws_hang = false;
+ dqm->is_resetting = false;
dqm->sched_running = true;
execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
dqm_unlock(dqm);
@@ -1351,8 +1359,17 @@ static int unmap_queues_cpsch(struct
device_queue_manager *dqm,
/* should be timed out */
retval = amdkfd_fence_wait_timeout(dqm->fence_addr, KFD_FENCE_COMPLETED,
queue_preemption_timeout_ms);
- if (retval)
+ if (retval) {
+ pr_err("The cp might be in an unrecoverable state due to an
unsuccessful queues preemption\n");
+ dqm->is_hws_hang = true;
+ /* It's possible we're detecting a HWS hang in the
+* middle of a GPU reset. No need to schedule another
+* reset in this case.
+*/
+ if (!dqm->is_resetting)
+ schedule_work(&dqm->hw_exception_work);
return retval;
+ }
pm_release_ib(&dqm->packets);
dqm->active_runlist = false;
@@ -1370,12 +1387,8 @@ static int execute_queues_cpsch(struct
device_queue_manager *dqm,
if (dqm->is_hws_hang)
return -EIO;
retval = unmap_queues_cpsch(dqm, filter, filter_param);
- if (retval) {
- pr_err("The cp might b
Re: [PATCH 4/4] drm/amdkfd: Avoid hanging hardware in stop_cpsch
Can we use the dqm_lock when we try to get the dqm->is_hw_hang and
dqm->is_resetting inside function kq_uninitialize ?
I think more closer we check the status to hqd_destroy it will be more
accurate . It does look better with this logic if the status are changed
after dqm unmap_queue call and before we call hqd_destroy .
Another comment in line.
Regards
shaoyun.liu
On 2019-12-20 11:33 a.m., Felix Kuehling wrote:
dqm->is_hws_hang is protected by the DQM lock. kq_uninitialize runs
outside that lock protection. Therefore I opted to pass in the hanging
flag as a parameter. It also keeps the logic that decides all of that
inside the device queue manager, which I think is cleaner.
I was trying to clean this up further by moving the pm_init/pm_uninit
out of the start_cpsch/stop_cpsch sequence, but gave up on that idea
when I found out that I can't create the kernel queue in the DQM
initialize function because dev->dqm isn't initialized at that time yet.
Regards,
Felix
On 2019-12-20 10:56, shaoyunl wrote:
Looks like patch 2 is not related to this serial , but anyway .
Patch 1,2,3 are reviewed by shaoyunl
For patch 4 , is it possible we directly check dqm->is_hws_hang ||
dqm->is_resetting inside function kq_uninitialize. so we don't need
other interface change .
I think even Inside that kq_uninitialize function , we still can get
dqm as kq->dev->dqm .
shaoyun.liu
On 2019-12-20 3:30 a.m., Felix Kuehling wrote:
Don't use the HWS if it's known to be hanging. In a reset also
don't try to destroy the HIQ because that may hang on SRIOV if the
KIQ is unresponsive.
Signed-off-by: Felix Kuehling
---
.../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 12
drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c | 8
drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c | 4 ++--
drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 4 ++--
.../gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 2 +-
5 files changed, 17 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index a7e9ec1b3ce3..d7eb6ac37f62 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -946,7 +946,7 @@ static int start_nocpsch(struct
device_queue_manager *dqm)
static int stop_nocpsch(struct device_queue_manager *dqm)
{
if (dqm->dev->device_info->asic_family == CHIP_HAWAII)
- pm_uninit(&dqm->packets);
+ pm_uninit(&dqm->packets, false);
dqm->sched_running = false;
return 0;
@@ -1114,20 +1114,24 @@ static int start_cpsch(struct
device_queue_manager *dqm)
return 0;
fail_allocate_vidmem:
fail_set_sched_resources:
- pm_uninit(&dqm->packets);
+ pm_uninit(&dqm->packets, false);
fail_packet_manager_init:
return retval;
}
static int stop_cpsch(struct device_queue_manager *dqm)
{
+ bool hanging;
+kq_uninitialize(
dqm_lock(dqm);
- unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0);
+ if (!dqm->is_hws_hang)
[shaoyunl] should we check is_resetting here as well . so we ignore
the unmap call even HWS still not detect the hang but we know we
currently in resetting precedure
+ unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES,
0);
+ hanging = dqm->is_hws_hang || dqm->is_resetting;
dqm->sched_running = false;
dqm_unlock(dqm);
kfd_gtt_sa_free(dqm->dev, dqm->fence_mem);
- pm_uninit(&dqm->packets);
+ pm_uninit(&dqm->packets, hanging);
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
index 2d56dc534459..bae706462f96 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
@@ -195,9 +195,9 @@ static bool kq_initialize(struct kernel_queue
*kq, struct kfd_dev *dev,
}
/* Uninitialize a kernel queue and free all its memory usages. */
-static void kq_uninitialize(struct kernel_queue *kq)
+static void kq_uninitialize(struct kernel_queue *kq, bool hanging)
{
- if (kq->queue->properties.type == KFD_QUEUE_TYPE_HIQ)
+ if (kq->queue->properties.type == KFD_QUEUE_TYPE_HIQ && !hanging)
kq->mqd_mgr->destroy_mqd(kq->mqd_mgr,
kq->queue->mqd,
KFD_PREEMPT_TYPE_WAVEFRONT_RESET,
@@ -337,9 +337,9 @@ struct kernel_queue *kernel_queue_init(struct
kfd_dev *dev,
return NULL;
}
-void kernel_queue_uninit(struct kernel_queue *kq)
+void kernel_queue_uninit(struct kernel_queue *kq, bool hanging)
{
- kq_uninitialize(kq);
+ kq_uninitialize(kq, hanging);
kfree(kq);
}
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
index 6cabed06ef5d..dc406e6dee23 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manag
Re: [PATCH] drm/amdgpu: Remove unneeded variable 'ret' in amdgpu_device.c
On Fri, Dec 20, 2019 at 10:10 AM Ma Feng wrote:
>
> Fixes coccicheck warning:
>
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1036:5-8: Unneeded variable:
> "ret". Return "0" on line 1079
>
> Reported-by: Hulk Robot
> Signed-off-by: Ma Feng
Applied. thanks!
Alex
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 080ec18..6a4b142 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -1033,8 +1033,6 @@ static void
> amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev)
> */
> static int amdgpu_device_check_arguments(struct amdgpu_device *adev)
> {
> - int ret = 0;
> -
> if (amdgpu_sched_jobs < 4) {
> dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
> amdgpu_sched_jobs);
> @@ -1076,7 +1074,7 @@ static int amdgpu_device_check_arguments(struct
> amdgpu_device *adev)
>
> adev->tmz.enabled = amdgpu_is_tmz(adev);
>
> - return ret;
> + return 0;
> }
>
> /**
> --
> 2.6.2
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu: Remove unneeded variable 'ret' in navi10_ih.c
On Fri, Dec 20, 2019 at 10:10 AM Ma Feng wrote:
>
> Fixes coccicheck warning:
>
> drivers/gpu/drm/amd/amdgpu/navi10_ih.c:113:5-8: Unneeded variable: "ret".
> Return "0" on line 182
>
> Reported-by: Hulk Robot
> Signed-off-by: Ma Feng
Applied. Thanks!
Alex
> ---
> drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> index 9af7356..f737ce4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> @@ -110,7 +110,6 @@ static uint32_t navi10_ih_rb_cntl(struct amdgpu_ih_ring
> *ih, uint32_t ih_rb_cntl
> static int navi10_ih_irq_init(struct amdgpu_device *adev)
> {
> struct amdgpu_ih_ring *ih = &adev->irq.ih;
> - int ret = 0;
> u32 ih_rb_cntl, ih_doorbell_rtpr, ih_chicken;
> u32 tmp;
>
> @@ -179,7 +178,7 @@ static int navi10_ih_irq_init(struct amdgpu_device *adev)
> /* enable interrupts */
> navi10_ih_enable_interrupts(adev);
>
> - return ret;
> + return 0;
> }
>
> /**
> --
> 2.6.2
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: ✗ Fi.CI.BAT: failure for drm: Add support for DP 1.4 Compliance edid corruption test (rev3)
Hi All: I got CI check failures. Among those, hdmi-hpd-fast seems related, but I am not sure why. Please take a brief review and help to determine if it is a real false-positive again. Thanks a lot. Regards, Jerry -Original Message- From: Patchwork Sent: December 9, 2019 4:40 PM To: Zuo, Jerry Cc: intel-...@lists.freedesktop.org Subject: ✗ Fi.CI.BAT: failure for drm: Add support for DP 1.4 Compliance edid corruption test (rev3) == Series Details == Series: drm: Add support for DP 1.4 Compliance edid corruption test (rev3) URL : https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwork.freedesktop.org%2Fseries%2F70530%2F&data=02%7C01%7CJerry.Zuo%40amd.com%7C177d219e9888443af09a08d77cf069e0%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637115246025846384&sdata=aN8A2JbxqjfcxhVAUTnCNjvVGUk%2F2r4x%2BtriQ2JutOo%3D&reserved=0 State : failure == Summary == CI Bug Log - changes from CI_DRM_7522 -> Patchwork_15658 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_15658 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_15658, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fintel-gfx-ci.01.org%2Ftree%2Fdrm-tip%2FPatchwork_15658%2Findex.html&data=02%7C01%7CJerry.Zuo%40amd.com%7C177d219e9888443af09a08d77cf069e0%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637115246025846384&sdata=2SAFCLwq4%2BS4UA4pGK1XJhCmoqYb4zP%2FC0LFT9HYq8w%3D&reserved=0 Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_15658: ### IGT changes ### Possible regressions * igt@gem_ctx_create@basic-files: - fi-byt-j1900: [PASS][1] -> [FAIL][2] [1]: https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fintel-gfx-ci.01.org%2Ftree%2Fdrm-tip%2FCI_DRM_7522%2Ffi-byt-j1900%2Figt%40gem_ctx_create%40basic-files.html&data=02%7C01%7CJerry.Zuo%40amd.com%7C177d219e9888443af09a08d77cf069e0%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637115246025846384&sdata=KyQU%2F5qfyjglZpqN24HnnQ9a5GYdjBjJ1R3pVOhsNsI%3D&reserved=0 [2]: https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fintel-gfx-ci.01.org%2Ftree%2Fdrm-tip%2FPatchwork_15658%2Ffi-byt-j1900%2Figt%40gem_ctx_create%40basic-files.html&data=02%7C01%7CJerry.Zuo%40amd.com%7C177d219e9888443af09a08d77cf069e0%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637115246025846384&sdata=NzzP5pGKY0sGWMZ39hKMtj3uP6tOjIHtqdVCXkvXF7Q%3D&reserved=0 * igt@i915_selftest@live_gt_heartbeat: - fi-whl-u: [PASS][3] -> [DMESG-FAIL][4] [3]: https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fintel-gfx-ci.01.org%2Ftree%2Fdrm-tip%2FCI_DRM_7522%2Ffi-whl-u%2Figt%40i915_selftest%40live_gt_heartbeat.html&data=02%7C01%7CJerry.Zuo%40amd.com%7C177d219e9888443af09a08d77cf069e0%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637115246025846384&sdata=t%2Fs%2FnrUixDnvCLZCFGvYjYNBOo1wXIa61BcUcJBffyU%3D&reserved=0 [4]: https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fintel-gfx-ci.01.org%2Ftree%2Fdrm-tip%2FPatchwork_15658%2Ffi-whl-u%2Figt%40i915_selftest%40live_gt_heartbeat.html&data=02%7C01%7CJerry.Zuo%40amd.com%7C177d219e9888443af09a08d77cf069e0%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637115246025846384&sdata=UYbibmI5DwrQ5FaIMk9Wz%2FcKXQ9yHZietmPmGdgw2pg%3D&reserved=0 Known issues Here are the changes found in Patchwork_15658 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live_blt: - fi-ivb-3770:[PASS][5] -> [DMESG-FAIL][6] ([i915#725]) [5]: https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fintel-gfx-ci.01.org%2Ftree%2Fdrm-tip%2FCI_DRM_7522%2Ffi-ivb-3770%2Figt%40i915_selftest%40live_blt.html&data=02%7C01%7CJerry.Zuo%40amd.com%7C177d219e9888443af09a08d77cf069e0%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637115246025846384&sdata=NEJWpe%2Fclj9A1vJuWzT8RENFFbhOmpZLkCnR3ubrn9A%3D&reserved=0 [6]: https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fintel-gfx-ci.01.org%2Ftree%2Fdrm-tip%2FPatchwork_15658%2Ffi-ivb-3770%2Figt%40i915_selftest%40live_blt.html&data=02%7C01%7CJerry.Zuo%40amd.com%7C177d219e9888443af09a08d77cf069e0%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637115246025846384&sdata=JKN6Uuqur%2BzsVGYNzF%2B7tnWloW5NtBCe66l351fS3uw%3D&reserved=0 - fi-hsw-4770:[PASS][7] -> [DMESG-FAIL][8] ([i915#725]) [7]: https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fintel-gfx-ci.01.org%2Ftree%2Fdrm-tip%2FCI_DRM_7522%2Ffi-hsw-4770%2Figt%40i915_selftest%40live_blt.html&data=02%7C01%7CJerry.Zuo%40amd.com%7C177d219e9888443af09a08d77cf069e0%7C3dd8961fe4884e608e11a82d994e183
Re: [PATCH v2] drm/amd/display: Reduce HDMI pixel encoding if max clock is exceeded
On Fri, Dec 20, 2019 at 10:10 AM Tom Anderson wrote:
>
> Ping. Is there any action required to get this landed?
Looks good to me, but I'd like to hear from the display guys.
Alex
>
> On Tue, Dec 10, 2019 at 10:59:24AM -0800, Tom Anderson wrote:
> > Friendly ping.
> >
> > On Mon, Dec 02, 2019 at 01:47:13PM -0800, Thomas Anderson wrote:
> > > For high-res (8K) or HFR (4K120) displays, using uncompressed pixel
> > > formats like YCbCr444 would exceed the bandwidth of HDMI 2.0, so the
> > > "interesting" modes would be disabled, leaving only low-res or low
> > > framerate modes.
> > >
> > > This change lowers the pixel encoding to 4:2:2 or 4:2:0 if the max TMDS
> > > clock is exceeded. Verified that 8K30 and 4K120 are now available and
> > > working with a Samsung Q900R over an HDMI 2.0b link from a Radeon 5700.
> > >
> > > Signed-off-by: Thomas Anderson
> > > ---
> > > .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 45 ++-
> > > 1 file changed, 23 insertions(+), 22 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > > b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > > index 7aac9568d3be..803e59d97411 100644
> > > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > > @@ -3356,27 +3356,21 @@ get_output_color_space(const struct
> > > dc_crtc_timing *dc_crtc_timing)
> > > return color_space;
> > > }
> > >
> > > -static void reduce_mode_colour_depth(struct dc_crtc_timing *timing_out)
> > > -{
> > > - if (timing_out->display_color_depth <= COLOR_DEPTH_888)
> > > - return;
> > > -
> > > - timing_out->display_color_depth--;
> > > -}
> > > -
> > > -static void adjust_colour_depth_from_display_info(struct dc_crtc_timing
> > > *timing_out,
> > > - const struct drm_display_info
> > > *info)
> > > +static bool adjust_colour_depth_from_display_info(
> > > + struct dc_crtc_timing *timing_out,
> > > + const struct drm_display_info *info)
> > > {
> > > + enum dc_color_depth depth = timing_out->display_color_depth;
> > > int normalized_clk;
> > > - if (timing_out->display_color_depth <= COLOR_DEPTH_888)
> > > - return;
> > > do {
> > > normalized_clk = timing_out->pix_clk_100hz / 10;
> > > /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
> > > if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
> > > normalized_clk /= 2;
> > > /* Adjusting pix clock following on HDMI spec based on colour
> > > depth */
> > > - switch (timing_out->display_color_depth) {
> > > + switch (depth) {
> > > + case COLOR_DEPTH_888:
> > > + break;
> > > case COLOR_DEPTH_101010:
> > > normalized_clk = (normalized_clk * 30) / 24;
> > > break;
> > > @@ -3387,14 +3381,15 @@ static void
> > > adjust_colour_depth_from_display_info(struct dc_crtc_timing *timing_
> > > normalized_clk = (normalized_clk * 48) / 24;
> > > break;
> > > default:
> > > - return;
> > > + /* The above depths are the only ones valid for HDMI.
> > > */
> > > + return false;
> > > }
> > > - if (normalized_clk <= info->max_tmds_clock)
> > > - return;
> > > - reduce_mode_colour_depth(timing_out);
> > > -
> > > - } while (timing_out->display_color_depth > COLOR_DEPTH_888);
> > > -
> > > + if (normalized_clk <= info->max_tmds_clock) {
> > > + timing_out->display_color_depth = depth;
> > > + return true;
> > > + }
> > > + } while (--depth > COLOR_DEPTH_666);
> > > + return false;
> > > }
> > >
> > > static void fill_stream_properties_from_drm_display_mode(
> > > @@ -3474,8 +3469,14 @@ static void
> > > fill_stream_properties_from_drm_display_mode(
> > >
> > > stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
> > > stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
> > > - if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
> > > - adjust_colour_depth_from_display_info(timing_out, info);
> > > + if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
> > > + if (!adjust_colour_depth_from_display_info(timing_out, info)
> > > &&
> > > + drm_mode_is_420_also(info, mode_in) &&
> > > + timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) {
> > > + timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
> > > + adjust_colour_depth_from_display_info(timing_out,
> > > info);
> > > + }
> > > + }
> > > }
> > >
> > > static void fill_audio_info(struct audio_info *audio_info,
> > > --
> > > 2.24.0.393.g34dc348eaf-goog
> > >
> __
Re: [PATCH 4/4] drm/amdkfd: Avoid hanging hardware in stop_cpsch
On 2019-12-20 14:31, shaoyunl wrote:
Can we use the dqm_lock when we try to get the dqm->is_hw_hang and
dqm->is_resetting inside function kq_uninitialize ?
Spreading the DQM lock around is probably not a good idea. Then I'd
rather do more refactoring to move hqd_load and hqd_destroy out of the
kq_init/kq_uninit functions.
I think more closer we check the status to hqd_destroy it will be
more accurate . It does look better with this logic if the status are
changed after dqm unmap_queue call and before we call hqd_destroy .
Another comment in line.
Regards
shaoyun.liu
On 2019-12-20 11:33 a.m., Felix Kuehling wrote:
dqm->is_hws_hang is protected by the DQM lock. kq_uninitialize runs
outside that lock protection. Therefore I opted to pass in the
hanging flag as a parameter. It also keeps the logic that decides all
of that inside the device queue manager, which I think is cleaner.
I was trying to clean this up further by moving the pm_init/pm_uninit
out of the start_cpsch/stop_cpsch sequence, but gave up on that idea
when I found out that I can't create the kernel queue in the DQM
initialize function because dev->dqm isn't initialized at that time yet.
Regards,
Felix
On 2019-12-20 10:56, shaoyunl wrote:
Looks like patch 2 is not related to this serial , but anyway .
Patch 1,2,3 are reviewed by shaoyunl
For patch 4 , is it possible we directly check dqm->is_hws_hang ||
dqm->is_resetting inside function kq_uninitialize. so we don't
need other interface change .
I think even Inside that kq_uninitialize function , we still can get
dqm as kq->dev->dqm .
shaoyun.liu
On 2019-12-20 3:30 a.m., Felix Kuehling wrote:
Don't use the HWS if it's known to be hanging. In a reset also
don't try to destroy the HIQ because that may hang on SRIOV if the
KIQ is unresponsive.
Signed-off-by: Felix Kuehling
---
.../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 12
drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c | 8
drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c | 4 ++--
drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 4 ++--
.../gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 2 +-
5 files changed, 17 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index a7e9ec1b3ce3..d7eb6ac37f62 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -946,7 +946,7 @@ static int start_nocpsch(struct
device_queue_manager *dqm)
static int stop_nocpsch(struct device_queue_manager *dqm)
{
if (dqm->dev->device_info->asic_family == CHIP_HAWAII)
- pm_uninit(&dqm->packets);
+ pm_uninit(&dqm->packets, false);
dqm->sched_running = false;
return 0;
@@ -1114,20 +1114,24 @@ static int start_cpsch(struct
device_queue_manager *dqm)
return 0;
fail_allocate_vidmem:
fail_set_sched_resources:
- pm_uninit(&dqm->packets);
+ pm_uninit(&dqm->packets, false);
fail_packet_manager_init:
return retval;
}
static int stop_cpsch(struct device_queue_manager *dqm)
{
+ bool hanging;
+kq_uninitialize(
dqm_lock(dqm);
- unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0);
+ if (!dqm->is_hws_hang)
[shaoyunl] should we check is_resetting here as well . so we ignore
the unmap call even HWS still not detect the hang but we know we
currently in resetting precedure
GPU reset can be done when the HWS is not hanging. In that case
unmapping queues is perfectly safe. In the worst case it'll time out and
dqm->is_hws_hang will be set as a result. I'm planning to add more
checks later so that we can optionally wait in unmap_queues until a
reset is done. We'll need that to do preemptions reliably while a GPU
reset is in progress. So I need to either unmap the queues or be sure
that HWS is hanging.
With yours and Oak's comments I realize, this is far from complete and
more work is needed. But I still think this is an improvement.
Regards,
Felix
+ unmap_queues_cpsch(dqm,
KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0);
+ hanging = dqm->is_hws_hang || dqm->is_resetting;
dqm->sched_running = false;
dqm_unlock(dqm);
kfd_gtt_sa_free(dqm->dev, dqm->fence_mem);
- pm_uninit(&dqm->packets);
+ pm_uninit(&dqm->packets, hanging);
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
index 2d56dc534459..bae706462f96 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
@@ -195,9 +195,9 @@ static bool kq_initialize(struct kernel_queue
*kq, struct kfd_dev *dev,
}
/* Uninitialize a kernel queue and free all its memory usages. */
-static void kq_uninitialize(struct kernel_queue *kq)
+static void kq_uninitialize(struct kernel_que
Re: ✗ Fi.CI.BAT: failure for drm: Add support for DP 1.4 Compliance edid corruption test (rev3)
On 2019-12-20 2:40 p.m., Zuo, Jerry wrote:
> Hi All:
>
> I got CI check failures. Among those, hdmi-hpd-fast seems related, but I
> am not sure why. Please take a brief review and help to determine if it is a
> real false-positive again.
>
It looks like the hdmi-hpd-fast failures are listed under "Known
issues." I imagine that means we can ignore them.
But we also see these failures that are list as "Possible regressions"
and I'm not sure why our patch would've broken those:
Possible regressions
* igt@gem_ctx_create@basic-files:
- fi-byt-j1900: [PASS][1] -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7522/fi-byt-j1900/igt@gem_ctx_cre...@basic-files.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15658/fi-byt-j1900/igt@gem_ctx_cre...@basic-files.html
* igt@i915_selftest@live_gt_heartbeat:
- fi-whl-u: [PASS][3] -> [DMESG-FAIL][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7522/fi-whl-u/igt@i915_selftest@live_gt_heartbeat.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15658/fi-whl-u/igt@i915_selftest@live_gt_heartbeat.html
Would love some input from Intel guys on this as we don't want to break
you with this patch.
Thanks,
Harry
> Thanks a lot.
>
> Regards,
> Jerry
>
> -Original Message-
> From: Patchwork
> Sent: December 9, 2019 4:40 PM
> To: Zuo, Jerry
> Cc: intel-...@lists.freedesktop.org
> Subject: ✗ Fi.CI.BAT: failure for drm: Add support for DP 1.4 Compliance edid
> corruption test (rev3)
>
> == Series Details ==
>
> Series: drm: Add support for DP 1.4 Compliance edid corruption test (rev3)
> URL : https://patchwork.freedesktop.org/series/70530/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_7522 -> Patchwork_15658
>
>
> Summary
> ---
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_15658 absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_15658, please notify your bug team to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
> External URL:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15658/index.html
>
> Possible new issues
> ---
>
> Here are the unknown changes that may have been introduced in
> Patchwork_15658:
>
> ### IGT changes ###
>
> Possible regressions
>
> * igt@gem_ctx_create@basic-files:
> - fi-byt-j1900: [PASS][1] -> [FAIL][2]
>[1]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7522/fi-byt-j1900/igt@gem_ctx_cre...@basic-files.html
>[2]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15658/fi-byt-j1900/igt@gem_ctx_cre...@basic-files.html
>
> * igt@i915_selftest@live_gt_heartbeat:
> - fi-whl-u: [PASS][3] -> [DMESG-FAIL][4]
>[3]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7522/fi-whl-u/igt@i915_selftest@live_gt_heartbeat.html
>[4]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15658/fi-whl-u/igt@i915_selftest@live_gt_heartbeat.html
>
>
> Known issues
>
>
> Here are the changes found in Patchwork_15658 that come from known issues:
>
> ### IGT changes ###
>
> Issues hit
>
> * igt@i915_selftest@live_blt:
> - fi-ivb-3770:[PASS][5] -> [DMESG-FAIL][6] ([i915#725])
>[5]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7522/fi-ivb-3770/igt@i915_selftest@live_blt.html
>[6]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15658/fi-ivb-3770/igt@i915_selftest@live_blt.html
> - fi-hsw-4770:[PASS][7] -> [DMESG-FAIL][8] ([i915#725])
>[7]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7522/fi-hsw-4770/igt@i915_selftest@live_blt.html
>[8]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15658/fi-hsw-4770/igt@i915_selftest@live_blt.html
>
> * igt@kms_chamelium@hdmi-hpd-fast:
> - fi-kbl-7500u: [PASS][9] -> [FAIL][10] ([fdo#111096] / [i915#323])
>[9]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7522/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
>[10]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15658/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
>
>
> Possible fixes
>
> * igt@gem_exec_parallel@basic:
> - {fi-tgl-u}: [INCOMPLETE][11] ([i915#476]) -> [PASS][12]
>[11]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7522/fi-tgl-u/igt@gem_exec_paral...@basic.html
>[12]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15658/fi-tgl-u/igt@gem_exec_paral...@basic.html
>
> * igt@gem_sync@basic-store-each:
> - fi-tgl-y: [INCOMPLETE][13] ([i915#435]) -> [PASS][14]
>[13]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7522/fi-tgl-y/igt@gem_s...@basic-store-each.html
>[14]:
> https://intel-gfx-ci.01.org/tr
[PATCH] drm/amdgpu/smu/navi: Adjust default behavior for peak sclk profile
Fetch the sclk from the pptable if there is no specified sclk for
the board.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index bf87e93b26fc..c33744a0d46b 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -1587,7 +1587,7 @@ static int navi10_set_peak_clock_by_device(struct
smu_context *smu)
struct amdgpu_device *adev = smu->adev;
int ret = 0;
uint32_t sclk_freq = 0, uclk_freq = 0;
- uint32_t uclk_level = 0;
+ uint32_t sclk_level = 0, uclk_level = 0;
switch (adev->asic_type) {
case CHIP_NAVI10:
@@ -1629,7 +1629,13 @@ static int navi10_set_peak_clock_by_device(struct
smu_context *smu)
}
break;
default:
- return -EINVAL;
+ ret = smu_get_dpm_level_count(smu, SMU_SCLK, &sclk_level);
+ if (ret)
+ return ret;
+ ret = smu_get_dpm_freq_by_index(smu, SMU_SCLK, sclk_level - 1,
&sclk_freq);
+ if (ret)
+ return ret;
+ break;
}
ret = smu_get_dpm_level_count(smu, SMU_UCLK, &uclk_level);
--
2.24.1
___
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 2/2] drm/amdgpu/smu: add peak profile support for navi12
Add defined peak sclk for navi12 peak profile mode. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 3 +++ drivers/gpu/drm/amd/powerplay/navi10_ppt.h | 2 ++ 2 files changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c index c33744a0d46b..106434689ec5 100644 --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c @@ -1628,6 +1628,9 @@ static int navi10_set_peak_clock_by_device(struct smu_context *smu) break; } break; + case CHIP_NAVI12: + sclk_freq = NAVI12_UMD_PSTATE_PEAK_GFXCLK; + break; default: ret = smu_get_dpm_level_count(smu, SMU_SCLK, &sclk_level); if (ret) diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.h b/drivers/gpu/drm/amd/powerplay/navi10_ppt.h index ec03c7992f6d..f109401c2ee8 100644 --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.h +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.h @@ -33,6 +33,8 @@ #define NAVI14_UMD_PSTATE_PEAK_XTX_GFXCLK (1717) #define NAVI14_UMD_PSTATE_PEAK_XL_GFXCLK (1448) +#define NAVI12_UMD_PSTATE_PEAK_GFXCLK (1100) + #define NAVI10_VOLTAGE_SCALE (4) #define smnPCIE_LC_SPEED_CNTL 0x11140290 -- 2.24.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 1/2] drm/amdgpu/smu/navi: Adjust default behavior for peak sclk profile
Fetch the sclk from the pptable if there is no specified sclk for
the board.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index bf87e93b26fc..c33744a0d46b 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -1587,7 +1587,7 @@ static int navi10_set_peak_clock_by_device(struct
smu_context *smu)
struct amdgpu_device *adev = smu->adev;
int ret = 0;
uint32_t sclk_freq = 0, uclk_freq = 0;
- uint32_t uclk_level = 0;
+ uint32_t sclk_level = 0, uclk_level = 0;
switch (adev->asic_type) {
case CHIP_NAVI10:
@@ -1629,7 +1629,13 @@ static int navi10_set_peak_clock_by_device(struct
smu_context *smu)
}
break;
default:
- return -EINVAL;
+ ret = smu_get_dpm_level_count(smu, SMU_SCLK, &sclk_level);
+ if (ret)
+ return ret;
+ ret = smu_get_dpm_freq_by_index(smu, SMU_SCLK, sclk_level - 1,
&sclk_freq);
+ if (ret)
+ return ret;
+ break;
}
ret = smu_get_dpm_level_count(smu, SMU_UCLK, &uclk_level);
--
2.24.1
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Re: [PATCH 2/5] drm/amdgpu: export function to flush TLB via pasid
On 2019-12-20 1:24, Alex Sierra wrote:
This can be used directly from amdgpu and amdkfd to invalidate
TLB through pasid.
It supports gmc v7, v8, v9 and v10.
Two small corrections inline to make the behaviour between KIQ and
MMIO-based flushing consistent. Looks good otherwise.
Change-Id: I6563a8eba2e42d1a67fa2547156c20da41d1e490
Signed-off-by: Alex Sierra
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 6 ++
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 81
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 33 ++
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 34 ++
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 84 +
5 files changed, 238 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
index b499a3de8bb6..b6413a56f546 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
@@ -92,6 +92,9 @@ struct amdgpu_gmc_funcs {
/* flush the vm tlb via mmio */
void (*flush_gpu_tlb)(struct amdgpu_device *adev, uint32_t vmid,
uint32_t vmhub, uint32_t flush_type);
+ /* flush the vm tlb via pasid */
+ int (*flush_gpu_tlb_pasid)(struct amdgpu_device *adev, uint16_t pasid,
+ uint32_t flush_type, bool all_hub);
/* flush the vm tlb via ring */
uint64_t (*emit_flush_gpu_tlb)(struct amdgpu_ring *ring, unsigned vmid,
uint64_t pd_addr);
@@ -216,6 +219,9 @@ struct amdgpu_gmc {
};
#define amdgpu_gmc_flush_gpu_tlb(adev, vmid, vmhub, type) ((adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid), (vmhub), (type)))
+#define amdgpu_gmc_flush_gpu_tlb_pasid(adev, pasid, type, allhub) \
+ ((adev)->gmc.gmc_funcs->flush_gpu_tlb_pasid \
+ ((adev), (pasid), (type), (allhub)))
#define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, addr)
(r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (addr))
#define amdgpu_gmc_emit_pasid_mapping(r, vmid, pasid)
(r)->adev->gmc.gmc_funcs->emit_pasid_mapping((r), (vmid), (pasid))
#define amdgpu_gmc_map_mtype(adev, flags)
(adev)->gmc.gmc_funcs->map_mtype((adev),(flags))
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index f5725336a5f2..b1a5408a8d7e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -30,6 +30,8 @@
#include "hdp/hdp_5_0_0_sh_mask.h"
#include "gc/gc_10_1_0_sh_mask.h"
#include "mmhub/mmhub_2_0_0_sh_mask.h"
+#include "athub/athub_2_0_0_sh_mask.h"
+#include "athub/athub_2_0_0_offset.h"
#include "dcn/dcn_2_0_0_offset.h"
#include "dcn/dcn_2_0_0_sh_mask.h"
#include "oss/osssys_5_0_0_offset.h"
@@ -37,6 +39,7 @@
#include "navi10_enum.h"
#include "soc15.h"
+#include "soc15d.h"
#include "soc15_common.h"
#include "nbio_v2_3.h"
@@ -234,6 +237,48 @@ static bool gmc_v10_0_use_invalidate_semaphore(struct
amdgpu_device *adev,
(!amdgpu_sriov_vf(adev)));
}
+static bool gmc_v10_0_get_atc_vmid_pasid_mapping_info(
+ struct amdgpu_device *adev,
+ uint8_t vmid, uint16_t *p_pasid)
+{
+ uint32_t value;
+
+ value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
++ vmid);
+ *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
+
+ return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
+}
+
+static int gmc_v10_0_invalidate_tlbs_with_kiq(struct amdgpu_device *adev,
+ uint16_t pasid, uint32_t flush_type,
+ bool all_hub)
+{
+ signed long r;
+ uint32_t seq;
+ struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
+
+ spin_lock(&adev->gfx.kiq.ring_lock);
+ amdgpu_ring_alloc(ring, 12); /* fence + invalidate_tlbs package*/
+ amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
+ amdgpu_ring_write(ring,
+ PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
+ PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
+ PACKET3_INVALIDATE_TLBS_PASID(pasid) |
+ PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
+ amdgpu_fence_emit_polling(ring, &seq);
+ amdgpu_ring_commit(ring);
+ spin_unlock(&adev->gfx.kiq.ring_lock);
+
+ r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout);
+ if (r < 1) {
+ DRM_ERROR("wait for kiq fence error: %ld.\n", r);
+ return -ETIME;
+ }
+
+ return 0;
+}
+
/*
* GART
* VMID 0 is the physical GPU addresses as used by the kernel.
@@ -380,6 +425,41 @@ static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device
*adev, uint32_t vmid,
DRM_ERROR("Error flushing GPU TLB using the SDMA (%d)!\n", r);
}
+/**
+ * gmc_v10_0_flush_gpu_tlb_pasid
Re: [PATCH v9 01/18] drm/dp_mst: Add PBN calculation for DSC modes
Actually, one comment on this that should be very simple to add
On Fri, 2019-12-13 at 15:08 -0500, mikita.lip...@amd.com wrote:
> From: David Francis
>
> With DSC, bpp can be fractional in multiples of 1/16.
>
> Change drm_dp_calc_pbn_mode to reflect this, adding a new
> parameter bool dsc. When this parameter is true, treat the
> bpp parameter as having units not of bits per pixel, but
> 1/16 of a bit per pixel
>
> v2: Don't add separate function for this
> v3: In the equation divide bpp by 16 as it is expected
> not to leave any remainder
>
> Reviewed-by: Manasi Navare
> Reviewed-by: Lyude Paul
> Reviewed-by: Harry Wentland
> Signed-off-by: David Francis
> Signed-off-by: Mikita Lipski
> ---
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
> drivers/gpu/drm/drm_dp_mst_topology.c | 12 +++-
> drivers/gpu/drm/i915/display/intel_dp_mst.c| 3 ++-
> drivers/gpu/drm/nouveau/dispnv50/disp.c| 2 +-
> drivers/gpu/drm/radeon/radeon_dp_mst.c | 2 +-
> drivers/gpu/drm/selftests/test-drm_dp_mst_helper.c | 10 ++
> include/drm/drm_dp_mst_helper.h| 3 +--
> 7 files changed, 23 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 455c51c38720..9fc03fc1017d 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -4967,7 +4967,7 @@ static int dm_encoder_helper_atomic_check(struct
> drm_encoder *encoder,
> is_y420);
> bpp = convert_dc_color_depth_into_bpc(color_depth) * 3;
> clock = adjusted_mode->clock;
> - dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock,
> bpp);
> + dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp,
> false);
> }
> dm_new_connector_state->vcpi_slots =
> drm_dp_atomic_find_vcpi_slots(state,
> mst
> _mgr,
> diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c
> b/drivers/gpu/drm/drm_dp_mst_topology.c
> index ae5809a1f19a..363e7e58e7e7 100644
> --- a/drivers/gpu/drm/drm_dp_mst_topology.c
> +++ b/drivers/gpu/drm/drm_dp_mst_topology.c
> @@ -4342,10 +4342,11 @@ EXPORT_SYMBOL(drm_dp_check_act_status);
> * drm_dp_calc_pbn_mode() - Calculate the PBN for a mode.
> * @clock: dot clock for the mode
> * @bpp: bpp for the mode.
> + * @dsc: DSC mode. If true, bpp has units of 1/16 of a bit per pixel
> *
> * This uses the formula in the spec to calculate the PBN value for a mode.
> */
> -int drm_dp_calc_pbn_mode(int clock, int bpp)
> +int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc)
> {
> /*
>* margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
> @@ -4356,7 +4357,16 @@ int drm_dp_calc_pbn_mode(int clock, int bpp)
>* peak_kbps *= (1006/1000)
>* peak_kbps *= (64/54)
>* peak_kbps *= 8convert to bytes
> + *
> + * If the bpp is in units of 1/16, further divide by 16. Put this
> + * factor in the numerator rather than the denominator to avoid
> + * integer overflow
>*/
> +
> + if (dsc)
> + return DIV_ROUND_UP_ULL(mul_u32_u32(clock * (bpp / 16), 64 *
> 1006),
> + 8 * 54 * 1000 * 1000);
> +
> return DIV_ROUND_UP_ULL(mul_u32_u32(clock * bpp, 64 * 1006),
> 8 * 54 * 1000 * 1000);
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 03d1cba0b696..92be17711287 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -61,7 +61,8 @@ static int intel_dp_mst_compute_link_config(struct
> intel_encoder *encoder,
> crtc_state->pipe_bpp = bpp;
>
> crtc_state->pbn = drm_dp_calc_pbn_mode(adjusted_mode-
> >crtc_clock,
> -crtc_state->pipe_bpp);
> +crtc_state->pipe_bpp,
> +false);
>
> slots = drm_dp_atomic_find_vcpi_slots(state, &intel_dp-
> >mst_mgr,
> port, crtc_state->pbn);
> diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c
> b/drivers/gpu/drm/nouveau/dispnv50/disp.c
> index 549486f1d937..1c9e23d5a6fd 100644
> --- a/drivers/gpu/drm/nouveau/dispnv50/disp.c
> +++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c
> @@ -782,7 +782,7 @@ nv50_msto_atomic_check(struct drm_encoder *encoder,
> const int bpp = connector->display_info.bpc * 3;
> const int clock = crtc_state->adjusted_mode.clock;
>
> - asyh->dp.pbn = drm_dp_calc_pbn_mode
Re: [PATCH 3/5] drm/amdgpu: GPU TLB flush API moved to amdgpu_amdkfd
On 2019-12-20 1:24, Alex Sierra wrote:
[Why]
TLB flush method has been deprecated using kfd2kgd interface.
This implementation is now on the amdgpu_amdkfd API.
[How]
TLB flush functions now implemented in amdgpu_amdkfd.
Change-Id: Ic51cccdfe6e71288d78da772b6e1b6ced72f8ef7
Signed-off-by: Alex Sierra
Looks good to me. See my comment about the TODO inline.
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 32 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 2 ++
drivers/gpu/drm/amd/amdkfd/kfd_process.c | 8 --
3 files changed, 39 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index d3da9dde4ee1..b7f6e70c5762 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -634,6 +634,38 @@ bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev,
u32 vmid)
return false;
}
+int amdgpu_amdkfd_flush_gpu_tlb_vmid(struct kgd_dev *kgd, uint16_t vmid)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
+ /* TODO: condition missing for FAMILY above NV */
I'm not sure what's missing here. NV and above don't need any special
treatment. Since SDMA is connected to GFXHUB on NV, only the GFXHUB
needs to be flushed.
Regards,
Felix
+ if (adev->family == AMDGPU_FAMILY_AI) {
+ int i;
+
+ for (i = 0; i < adev->num_vmhubs; i++)
+ amdgpu_gmc_flush_gpu_tlb(adev, vmid, i, 0);
+ } else {
+ amdgpu_gmc_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB_0, 0);
+ }
+
+ return 0;
+}
+
+int amdgpu_amdkfd_flush_gpu_tlb_pasid(struct kgd_dev *kgd, uint16_t pasid)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
+ uint32_t flush_type = 0;
+ bool all_hub = false;
+
+ if (adev->gmc.xgmi.num_physical_nodes &&
+ adev->asic_type == CHIP_VEGA20)
+ flush_type = 2;
+
+ if (adev->family == AMDGPU_FAMILY_AI)
+ all_hub = true;
+
+ return amdgpu_gmc_flush_gpu_tlb_pasid(adev, pasid, flush_type, all_hub);
+}
+
bool amdgpu_amdkfd_have_atomics_support(struct kgd_dev *kgd)
{
struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index 069d5d230810..47b0f2957d1f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -136,6 +136,8 @@ int amdgpu_amdkfd_submit_ib(struct kgd_dev *kgd, enum
kgd_engine_type engine,
uint32_t *ib_cmd, uint32_t ib_len);
void amdgpu_amdkfd_set_compute_idle(struct kgd_dev *kgd, bool idle);
bool amdgpu_amdkfd_have_atomics_support(struct kgd_dev *kgd);
+int amdgpu_amdkfd_flush_gpu_tlb_vmid(struct kgd_dev *kgd, uint16_t vmid);
+int amdgpu_amdkfd_flush_gpu_tlb_pasid(struct kgd_dev *kgd, uint16_t pasid);
bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
index 536a153ac9a4..25b90f70aecd 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
@@ -32,6 +32,7 @@
#include
#include
#include "amdgpu_amdkfd.h"
+#include "amdgpu.h"
struct mm_struct;
@@ -1152,16 +1153,17 @@ int kfd_reserved_mem_mmap(struct kfd_dev *dev, struct kfd_process *process,
void kfd_flush_tlb(struct kfd_process_device *pdd)
{
struct kfd_dev *dev = pdd->dev;
- const struct kfd2kgd_calls *f2g = dev->kfd2kgd;
if (dev->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) {
/* Nothing to flush until a VMID is assigned, which
* only happens when the first queue is created.
*/
if (pdd->qpd.vmid)
- f2g->invalidate_tlbs_vmid(dev->kgd, pdd->qpd.vmid);
+ amdgpu_amdkfd_flush_gpu_tlb_vmid(dev->kgd,
+ pdd->qpd.vmid);
} else {
- f2g->invalidate_tlbs(dev->kgd, pdd->process->pasid);
+ amdgpu_amdkfd_flush_gpu_tlb_pasid(dev->kgd,
+ pdd->process->pasid);
}
}
___
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Re: [PATCH 4/5] drm/amdgpu: flush TLB functions removal from kfd2kgd interface
On 2019-12-20 1:24, Alex Sierra wrote:
[Why]
kfd2kgd interface will be deprecated. This removal only covers TLB
invalidation for now. They have been replaced in amdgpu_amdkfd API.
[How]
TLB invalidate functions removed from the different amdkfd_gfx_v*
versions.
Change-Id: Ic2c7d4a0d19fe1e884dee1ff10a520d31252afee
Signed-off-by: Alex Sierra
This patch is
Reviewed-by: Felix Kuehling
---
.../drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c | 2 -
.../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c| 67 -
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c | 41
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c | 41
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 96 ---
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h | 2 -
.../gpu/drm/amd/include/kgd_kfd_interface.h | 2 -
7 files changed, 251 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
index 3c119407dc34..82e80b92e6ce 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
@@ -296,7 +296,5 @@ const struct kfd2kgd_calls arcturus_kfd2kgd = {
kgd_gfx_v9_get_atc_vmid_pasid_mapping_info,
.get_tile_config = kgd_gfx_v9_get_tile_config,
.set_vm_context_page_table_base = kgd_set_vm_context_page_table_base,
- .invalidate_tlbs = kgd_gfx_v9_invalidate_tlbs,
- .invalidate_tlbs_vmid = kgd_gfx_v9_invalidate_tlbs_vmid,
.get_hive_id = amdgpu_amdkfd_get_hive_id,
};
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
index 61cd707158e4..6132b4874498 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
@@ -686,71 +686,6 @@ static bool get_atc_vmid_pasid_mapping_info(struct kgd_dev
*kgd,
return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
}
-static int invalidate_tlbs_with_kiq(struct amdgpu_device *adev, uint16_t pasid)
-{
- signed long r;
- uint32_t seq;
- struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
-
- spin_lock(&adev->gfx.kiq.ring_lock);
- amdgpu_ring_alloc(ring, 12); /* fence + invalidate_tlbs package*/
- amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
- amdgpu_ring_write(ring,
- PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
- PACKET3_INVALIDATE_TLBS_PASID(pasid));
- amdgpu_fence_emit_polling(ring, &seq);
- amdgpu_ring_commit(ring);
- spin_unlock(&adev->gfx.kiq.ring_lock);
-
- r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout);
- if (r < 1) {
- DRM_ERROR("wait for kiq fence error: %ld.\n", r);
- return -ETIME;
- }
-
- return 0;
-}
-
-static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid)
-{
- struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
- int vmid;
- uint16_t queried_pasid;
- bool ret;
- struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
-
- if (amdgpu_emu_mode == 0 && ring->sched.ready)
- return invalidate_tlbs_with_kiq(adev, pasid);
-
- for (vmid = 0; vmid < 16; vmid++) {
- if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid))
- continue;
-
- ret = get_atc_vmid_pasid_mapping_info(kgd, vmid,
- &queried_pasid);
- if (ret && queried_pasid == pasid) {
- amdgpu_gmc_flush_gpu_tlb(adev, vmid,
- AMDGPU_GFXHUB_0, 0);
- break;
- }
- }
-
- return 0;
-}
-
-static int invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid)
-{
- struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
-
- if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) {
- pr_err("non kfd vmid %d\n", vmid);
- return 0;
- }
-
- amdgpu_gmc_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB_0, 0);
- return 0;
-}
-
static int kgd_address_watch_disable(struct kgd_dev *kgd)
{
return 0;
@@ -832,7 +767,5 @@ const struct kfd2kgd_calls gfx_v10_kfd2kgd = {
get_atc_vmid_pasid_mapping_info,
.get_tile_config = amdgpu_amdkfd_get_tile_config,
.set_vm_context_page_table_base = set_vm_context_page_table_base,
- .invalidate_tlbs = invalidate_tlbs,
- .invalidate_tlbs_vmid = invalidate_tlbs_vmid,
.get_hive_id = amdgpu_amdkfd_get_hive_id,
};
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
index 6e6f0a99ec06..8f052e98a3c6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
@@ -696,45 +696,6 @@ static void set_vm_context_page_table_base(struct kg
Re: [PATCH 1/5] drm/amdgpu: Avoid reclaim fs while eviction lock
On 2019-12-20 1:24, Alex Sierra wrote:
[Why]
Avoid reclaim filesystem while eviction lock is held called from
MMU notifier.
[How]
Setting PF_MEMALLOC_NOFS flags while eviction mutex is locked.
Using memalloc_nofs_save / memalloc_nofs_restore API.
Change-Id: I5531c9337836e7d4a430df3f16dcc82888e8018c
Signed-off-by: Alex Sierra
This patch is
Reviewed-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 14 ++---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 28 +-
2 files changed, 34 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index b999b67ff57a..b36daa6230fb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -678,9 +678,9 @@ int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev,
struct amdgpu_vm *vm,
}
}
- mutex_lock(&vm->eviction_lock);
+ vm_eviction_lock(vm);
vm->evicting = false;
- mutex_unlock(&vm->eviction_lock);
+ vm_eviction_unlock(vm);
return 0;
}
@@ -1559,7 +1559,7 @@ static int amdgpu_vm_bo_update_mapping(struct
amdgpu_device *adev,
if (!(flags & AMDGPU_PTE_VALID))
owner = AMDGPU_FENCE_OWNER_KFD;
- mutex_lock(&vm->eviction_lock);
+ vm_eviction_lock(vm);
if (vm->evicting) {
r = -EBUSY;
goto error_unlock;
@@ -1576,7 +1576,7 @@ static int amdgpu_vm_bo_update_mapping(struct
amdgpu_device *adev,
r = vm->update_funcs->commit(¶ms, fence);
error_unlock:
- mutex_unlock(&vm->eviction_lock);
+ vm_eviction_unlock(vm);
return r;
}
@@ -2537,18 +2537,18 @@ bool amdgpu_vm_evictable(struct amdgpu_bo *bo)
return false;
/* Try to block ongoing updates */
- if (!mutex_trylock(&bo_base->vm->eviction_lock))
+ if (!vm_eviction_trylock(bo_base->vm))
return false;
/* Don't evict VM page tables while they are updated */
if (!dma_fence_is_signaled(bo_base->vm->last_direct) ||
!dma_fence_is_signaled(bo_base->vm->last_delayed)) {
- mutex_unlock(&bo_base->vm->eviction_lock);
+ vm_eviction_unlock(bo_base->vm);
return false;
}
bo_base->vm->evicting = true;
- mutex_unlock(&bo_base->vm->eviction_lock);
+ vm_eviction_unlock(bo_base->vm);
return true;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 100547f094ff..d35aa76469ec 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -30,6 +30,7 @@
#include
#include
#include
+#include
#include "amdgpu_sync.h"
#include "amdgpu_ring.h"
@@ -242,9 +243,12 @@ struct amdgpu_vm {
/* tree of virtual addresses mapped */
struct rb_root_cached va;
- /* Lock to prevent eviction while we are updating page tables */
+ /* Lock to prevent eviction while we are updating page tables
+* use vm_eviction_lock/unlock(vm)
+*/
struct mutexeviction_lock;
boolevicting;
+ unsigned intsaved_flags;
/* BOs who needs a validation */
struct list_headevicted;
@@ -436,4 +440,26 @@ void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev,
struct amdgpu_vm *vm);
void amdgpu_vm_del_from_lru_notify(struct ttm_buffer_object *bo);
+/* vm eviction_lock can be taken in MMU notifiers. Make sure no reclaim-FS
+ * happens while holding this lock anywhere to prevent deadlocks when
+ * an MMU notifier runs in reclaim-FS context.
+ */
+static inline void vm_eviction_lock(struct amdgpu_vm *vm)
+{
+ mutex_lock(&vm->eviction_lock);
+ vm->saved_flags = memalloc_nofs_save();
+}
+static inline int vm_eviction_trylock(struct amdgpu_vm *vm)
+{
+ if (mutex_trylock(&vm->eviction_lock)) {
+ vm->saved_flags = memalloc_nofs_save();
+ return 1;
+ }
+ return 0;
+}
+static inline void vm_eviction_unlock(struct amdgpu_vm *vm)
+{
+ memalloc_nofs_restore(vm->saved_flags);
+ mutex_unlock(&vm->eviction_lock);
+}
#endif
___
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Re: [PATCH 5/5] drm/amdgpu: invalidate BO during userptr mapping
I think this patch is just a proof of concept for now. It should not be
submitted because there are still some known locking issues that need to
be solved, and we don't have the code yet that handles the recoverable
page faults resulting from this.
Regards,
Felix
On 2019-12-20 1:24, Alex Sierra wrote:
This is required for HMM functionality only on GFXv9 GPU, which supports
recoverable page faults.
[Why]
Instead of stopping all user mode queues during a userptr mapping.
The GFXv9 recoverable page fault is used to revalidate userptr mappings.
Now, this will be done on the page fault handler.
[How]
Invalidate buffer objects that correspond to the specific address range
on the mmu notifier.
Change-Id: I94b8fee8d88ff240b619cba1c5458aba98b17736
Signed-off-by: Alex Sierra
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c | 56 --
1 file changed, 52 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
index 392300f77b13..06415d8ad3c1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
@@ -187,6 +187,45 @@ static void amdgpu_mn_invalidate_node(struct
amdgpu_mn_node *node,
}
}
+/**
+ * amdgpu_mn_invalidate_bo - invalidate a BO
+ *
+ * @bo: amdgpu buffer object to invalidate
+ * @adev: amdgpu device pointer
+ *
+ * Block for operations on BO while is cleared.
+ */
+static int amdgpu_mn_invalidate_bo(struct amdgpu_device *adev,
+struct amdgpu_bo *bo)
+{
+ struct amdgpu_vm_bo_base *bo_base;
+ struct amdgpu_bo_va *bo_va;
+ struct kgd_dev *kgd = (struct kgd_dev *)adev;
+ long r = 0;
+ long tmo;
+
+ tmo = msecs_to_jiffies(100);
+ for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) {
+ bo_va = container_of(bo_base, struct amdgpu_bo_va, base);
+ r = amdgpu_vm_bo_update(adev, bo_va, true);
+ if (r)
+ break;
+
+ r = dma_fence_wait_timeout(bo_va->last_pt_update, false, tmo);
+ if (r <= 0) {
+ if (r == 0)
+ r = -ETIMEDOUT;
+
+ break;
+ } else {
+ r = 0;
+ }
+
+ amdgpu_amdkfd_flush_gpu_tlb_pasid(kgd, bo_base->vm->pasid);
+ }
+ return r;
+}
+
/**
* amdgpu_mn_sync_pagetables_gfx - callback to notify about mm change
*
@@ -250,6 +289,7 @@ amdgpu_mn_sync_pagetables_hsa(struct hmm_mirror *mirror,
const struct mmu_notifier_range *update)
{
struct amdgpu_mn *amn = container_of(mirror, struct amdgpu_mn, mirror);
+ struct amdgpu_device *adev = amn->adev;
unsigned long start = update->start;
unsigned long end = update->end;
bool blockable = mmu_notifier_range_blockable(update);
@@ -275,11 +315,19 @@ amdgpu_mn_sync_pagetables_hsa(struct hmm_mirror *mirror,
it = interval_tree_iter_next(it, start, end);
list_for_each_entry(bo, &node->bos, mn_list) {
- struct kgd_mem *mem = bo->kfd_bo;
- if (amdgpu_ttm_tt_affect_userptr(bo->tbo.ttm,
-start, end))
- amdgpu_amdkfd_evict_userptr(mem, amn->mm);
+ if (amdgpu_ttm_tt_affect_userptr(
+ bo->tbo.ttm, start, end)){
+ if (!amdgpu_noretry &&
+ adev->family >= AMDGPU_FAMILY_AI) {
+ amdgpu_mn_invalidate_bo(adev, bo);
+ } else {
+ struct kgd_mem *mem = bo->kfd_bo;
+
+ amdgpu_amdkfd_evict_userptr(mem,
+ amn->mm);
+ }
+ }
}
}
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Re: [PATCH v9 16/18] drm/amd/display: Recalculate VCPI slots for new DSC connectors
So I reviewed this already but realized I made a very silly mistake, comments
down below:
On Fri, 2019-12-13 at 15:08 -0500, mikita.lip...@amd.com wrote:
> From: Mikita Lipski
>
> [why]
> Since for DSC MST connector's PBN is claculated differently
> due to compression, we have to recalculate both PBN and
> VCPI slots for that connector.
>
> [how]
> The function iterates through all the active streams to
> find, which have DSC enabled, then recalculates PBN for
> it and calls drm_dp_helper_update_vcpi_slots_for_dsc to
> update connector's VCPI slots.
>
> v2: - use drm_dp_mst_atomic_enable_dsc per port to
> enable/disable DSC
>
> v3: - Iterate through connector states from the state passed
> - On each connector state get stream from dc_state,
> instead CRTC state
>
> Reviewed-by: Lyude Paul
> Signed-off-by: Mikita Lipski
> ---
> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 76 +--
> 1 file changed, 71 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 93a230d956ee..2ac3a2f0b452 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -4986,6 +4986,69 @@ const struct drm_encoder_helper_funcs
> amdgpu_dm_encoder_helper_funcs = {
> .atomic_check = dm_encoder_helper_atomic_check
> };
>
> +static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
> + struct dc_state *dc_state)
> +{
> + struct dc_stream_state *stream = NULL;
> + struct drm_connector *connector;
> + struct drm_connector_state *new_con_state, *old_con_state;
> + struct amdgpu_dm_connector *aconnector;
> + struct dm_connector_state *dm_conn_state;
> + int i, j, clock, bpp;
> + int vcpi, pbn_div, pbn = 0;
> +
> + for_each_oldnew_connector_in_state(state, connector, old_con_state,
> new_con_state, i) {
> +
> + aconnector = to_amdgpu_dm_connector(connector);
> +
> + if (!aconnector->port)
> + continue;
> +
> + if (!new_con_state || !new_con_state->crtc)
> + continue;
> +
> + dm_conn_state = to_dm_connector_state(new_con_state);
> +
> + for (j = 0; j < dc_state->stream_count; j++) {
> + stream = dc_state->streams[j];
> + if (!stream)
> + continue;
> +
> + if ((struct amdgpu_dm_connector*)stream-
> >dm_stream_context == aconnector)
> + break;
> +
> + stream = NULL;
> + }
> +
> + if (!stream)
> + continue;
> +
> + if (stream->timing.flags.DSC != 1) {
> + drm_dp_mst_atomic_enable_dsc(state,
> + aconnector->port,
> + dm_conn_state->pbn,
> + 0,
> + false);
> + continue;
> + }
> +
> + pbn_div = dm_mst_get_pbn_divider(stream->link);
> + bpp = stream->timing.dsc_cfg.bits_per_pixel;
> + clock = stream->timing.pix_clk_100hz / 10;
> + pbn = drm_dp_calc_pbn_mode(clock, bpp, true);
> + vcpi = drm_dp_mst_atomic_enable_dsc(state,
> + aconnector->port,
> + pbn, pbn_div,
> + true);
> + if (vcpi < 0)
> + return vcpi;
> +
> + dm_conn_state->pbn = pbn;
> + dm_conn_state->vcpi_slots = vcpi;
> + }
> + return 0;
> +}
> +
> static void dm_drm_plane_reset(struct drm_plane *plane)
> {
> struct dm_plane_state *amdgpu_state = NULL;
> @@ -8022,11 +8085,6 @@ static int amdgpu_dm_atomic_check(struct drm_device
> *dev,
> if (ret)
> goto fail;
>
> - /* Perform validation of MST topology in the state*/
> - ret = drm_dp_mst_atomic_check(state);
> - if (ret)
> - goto fail;
> -
> if (state->legacy_cursor_update) {
> /*
>* This is a fast cursor update coming from the plane update
> @@ -8098,6 +8156,10 @@ static int amdgpu_dm_atomic_check(struct drm_device
> *dev,
> if (!compute_mst_dsc_configs_for_state(state, dm_state-
> >context))
> goto fail;
>
> + ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state-
> >context);
> + if (ret)
> + goto fail;
> +
> if (dc_validate_global_state(dc, dm_state->context, false) !=
> DC_OK) {
> ret = -EINVAL;
> goto fail;
> @@ -8126,6 +
Re: [PATCH v9 15/18] drm/amd/display: MST DSC compute fair share
Acked-by: Lyude Paul
On Fri, 2019-12-13 at 15:08 -0500, mikita.lip...@amd.com wrote:
> From: David Francis
>
> If there is limited link bandwidth on a MST network,
> it must be divided fairly between the streams on that network
>
> Implement an algorithm to determine the correct DSC config
> for each stream
>
> The algorithm:
> This
> [ ] ( )
> represents the range of bandwidths possible for a given stream.
> The [] area represents the range of DSC configs, and the ()
> represents no DSC. The bandwidth used increases from left to right.
>
> First, try disabling DSC on all streams
> [ ] (|)
> [ ](|)
> Check this against the bandwidth limits of the link and each branch
> (including each endpoint). If it passes, the job is done
>
> Second, try maximum DSC compression on all streams
> that support DSC
> [| ]( )
> [|] ( )
> If this does not pass, then enabling this combination of streams
> is impossible
>
> Otherwise, divide the remaining bandwidth evenly amongst the streams
> [| ] ( )
> [| ]( )
>
> If one or more of the streams reach minimum compression, evenly
> divide the reamining bandwidth amongst the remaining streams
> [|] ( )
> [ |] ( )
> [ | ] ( )
> [ | ] ( )
>
> If all streams can reach minimum compression, disable compression
> greedily
> [ |] ( )
> [|]( )
> [ ](|)
>
> Perform this algorithm on each full update, on each MST link
> with at least one DSC stream on it
>
> After the configs are computed, call
> dcn20_add_dsc_to_stream_resource on each stream with DSC enabled.
> It is only after all streams are created that we can know which
> of them will need DSC.
>
> Do all of this at the end of amdgpu atomic check. If it fails,
> fail check; This combination of timings cannot be supported.
>
> v2: Use drm_dp_mst_atomic_check to validate bw for certain dsc
> configurations
>
> v3: Use dc_dsc_policy structure to get min and max bpp rate
> for DSC configuration
>
> Cc: Lyude Paul
> Cc: Manasi Navare
> Reviewed-by: Wenjing Liu
> Signed-off-by: David Francis
> Signed-off-by: Mikita Lipski
> ---
> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +
> .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 364 ++
> .../display/amdgpu_dm/amdgpu_dm_mst_types.h | 3 +
> .../drm/amd/display/dc/dcn20/dcn20_resource.c | 7 +-
> .../drm/amd/display/dc/dcn20/dcn20_resource.h | 1 +
> 5 files changed, 376 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 753a79734817..93a230d956ee 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -8095,6 +8095,9 @@ static int amdgpu_dm_atomic_check(struct drm_device
> *dev,
> if (ret)
> goto fail;
>
> + if (!compute_mst_dsc_configs_for_state(state, dm_state-
> >context))
> + goto fail;
> +
> if (dc_validate_global_state(dc, dm_state->context, false) !=
> DC_OK) {
> ret = -EINVAL;
> goto fail;
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> index c376c8ccd391..6d13d1c33530 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> @@ -40,6 +40,10 @@
> #if defined(CONFIG_DEBUG_FS)
> #include "amdgpu_dm_debugfs.h"
> #endif
> +
> +
> +#include "dc/dcn20/dcn20_resource.h"
> +
> /* #define TRACE_DPCD */
>
> #ifdef TRACE_DPCD
> @@ -499,3 +503,363 @@ int dm_mst_get_pbn_divider(struct dc_link *link)
> return dc_link_bandwidth_kbps(link,
> dc_link_get_link_cap(link)) / (8 * 1000 * 54);
> }
> +
> +struct dsc_mst_fairness_params {
> + struct dc_crtc_timing *timing;
> + struct dc_sink *sink;
> + struct dc_dsc_bw_range bw_range;
> + bool compression_possible;
> + struct drm_dp_mst_port *port;
> +};
> +
> +struct dsc_mst_fairness_vars {
> + int pbn;
> + bool dsc_enabled;
> + int bpp_x16;
> +};
> +
> +static int kbps_to_peak_pbn(int kbps)
> +{
> + u64 peak_kbps = kbps;
> +
> + peak_kbps *= 1006;
> + peak_kbps /= 1000;
> + return (int) DIV_ROUND_UP(peak_kbps * 64, (54 * 8 * 1000));
> +}
> +
> +static void set_dsc_configs_from_fairness_vars(struct
> dsc_mst_fairness_params *params,
> + struct dsc_mst_fairness_vars *vars,
> + int count)
> +{
> + int i;
> +
> + for (i = 0; i < count; i++
Re: [PATCH v9 14/18] drm/amd/display: Add PBN per slot calculation for DSC
Acked-by: Lyude Paul
On Fri, 2019-12-13 at 15:08 -0500, mikita.lip...@amd.com wrote:
> From: Mikita Lipski
>
> [why]
> Need to calculate VCPI slots differently for DSC
> to take in account current link rate, link count
> and FEC.
> [how]
> Add helper to get pbn_div from dc_link
>
> Cc: Harry Wentland
> Cc: Lyude Paul
> Signed-off-by: Mikita Lipski
> ---
> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 8
> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h | 2 ++
> 2 files changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> index 7557edee7db0..c376c8ccd391 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> @@ -491,3 +491,11 @@ void amdgpu_dm_initialize_dp_connector(struct
> amdgpu_display_manager *dm,
> aconnector->connector_id);
> }
>
> +int dm_mst_get_pbn_divider(struct dc_link *link)
> +{
> + if (!link)
> + return 0;
> +
> + return dc_link_bandwidth_kbps(link,
> + dc_link_get_link_cap(link)) / (8 * 1000 * 54);
> +}
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
> index 2da851b40042..a553ea046185 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
> @@ -29,6 +29,8 @@
> struct amdgpu_display_manager;
> struct amdgpu_dm_connector;
>
> +int dm_mst_get_pbn_divider(struct dc_link *link);
> +
> void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
> struct amdgpu_dm_connector
> *aconnector);
>
--
Cheers,
Lyude Paul
___
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Re: [PATCH v9 10/18] drm/dp_mst: Manually overwrite PBN divider for calculating timeslots
Reviewed-by: Lyude Paul
On Fri, 2019-12-13 at 15:08 -0500, mikita.lip...@amd.com wrote:
> From: Mikita Lipski
>
> [why]
> For DSC case we cannot use topology manager's PBN divider
> variable. The default divider does not take FEC into account.
> Therefore the driver has to calculate its own divider based
> on the link rate and lane count its handling, as it is hw specific.
>
> [how]
> Pass pbn_div as an argument, which is used if its more than
> zero, otherwise default topology manager's pbn_div will be used.
>
> Cc: Lyude Paul
> Cc: Harry Wentland
> Cc: Manasi Navare
> Signed-off-by: Mikita Lipski
> ---
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++-
> drivers/gpu/drm/drm_dp_mst_topology.c | 9 +++--
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
> drivers/gpu/drm/nouveau/dispnv50/disp.c | 3 ++-
> include/drm/drm_dp_mst_helper.h | 3 ++-
> 5 files changed, 14 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 9fc03fc1017d..753a79734817 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -4972,7 +4972,8 @@ static int dm_encoder_helper_atomic_check(struct
> drm_encoder *encoder,
> dm_new_connector_state->vcpi_slots =
> drm_dp_atomic_find_vcpi_slots(state,
> mst
> _mgr,
> mst
> _port,
> -dm_
> new_connector_state->pbn);
> +dm_
> new_connector_state->pbn,
> +0);
> if (dm_new_connector_state->vcpi_slots < 0) {
> DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n",
> (int)dm_new_connector_state->vcpi_slots);
> return dm_new_connector_state->vcpi_slots;
> diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c
> b/drivers/gpu/drm/drm_dp_mst_topology.c
> index 74bed71f7315..bb0844dfb3d2 100644
> --- a/drivers/gpu/drm/drm_dp_mst_topology.c
> +++ b/drivers/gpu/drm/drm_dp_mst_topology.c
> @@ -4020,6 +4020,7 @@ static int drm_dp_init_vcpi(struct
> drm_dp_mst_topology_mgr *mgr,
> * @mgr: MST topology manager for the port
> * @port: port to find vcpi slots for
> * @pbn: bandwidth required for the mode in PBN
> + * @pbn_div: divider for DSC mode that takes FEC into account
> *
> * Allocates VCPI slots to @port, replacing any previous VCPI allocations
> it
> * may have had. Any atomic drivers which support MST must call this
> function
> @@ -4046,7 +4047,8 @@ static int drm_dp_init_vcpi(struct
> drm_dp_mst_topology_mgr *mgr,
> */
> int drm_dp_atomic_find_vcpi_slots(struct drm_atomic_state *state,
> struct drm_dp_mst_topology_mgr *mgr,
> - struct drm_dp_mst_port *port, int pbn)
> + struct drm_dp_mst_port *port, int pbn,
> + int pbn_div)
> {
> struct drm_dp_mst_topology_state *topology_state;
> struct drm_dp_vcpi_allocation *pos, *vcpi = NULL;
> @@ -4079,7 +4081,10 @@ int drm_dp_atomic_find_vcpi_slots(struct
> drm_atomic_state *state,
> if (!vcpi)
> prev_slots = 0;
>
> - req_slots = DIV_ROUND_UP(pbn, mgr->pbn_div);
> + if (pbn_div <= 0)
> + pbn_div = mgr->pbn_div;
> +
> + req_slots = DIV_ROUND_UP(pbn, pbn_div);
>
> DRM_DEBUG_ATOMIC("[CONNECTOR:%d:%s] [MST PORT:%p] VCPI %d -> %d\n",
>port->connector->base.id, port->connector->name,
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 92be17711287..a068f54a6793 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -65,7 +65,7 @@ static int intel_dp_mst_compute_link_config(struct
> intel_encoder *encoder,
> false);
>
> slots = drm_dp_atomic_find_vcpi_slots(state, &intel_dp-
> >mst_mgr,
> - port, crtc_state->pbn);
> + port, crtc_state->pbn,
> 0);
> if (slots == -EDEADLK)
> return slots;
> if (slots >= 0)
> diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c
> b/drivers/gpu/drm/nouveau/dispnv50/disp.c
> index 1c9e23d5a6fd..edb78966c5b6 100644
> --- a/drivers/gpu/drm/nouveau/dispnv50/disp.c
> +++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c
> @@ -787,7 +787,8 @@ nv50_msto_atomic_check(struct drm_encoder *encoder,
>
> slots = drm_dp_atomic_find_vcpi_slots(
Re: [PATCH 1/2] drm/amdgpu: update the method to get fb_loc of memory training(V4)
On 2019-12-20 10:27 a.m., Alex Deucher wrote:
> On Thu, Dec 19, 2019 at 9:00 PM Yin, Tianci (Rico) wrote:
>>
>> [AMD Official Use Only - Internal Distribution Only]
>>
>>
>> Hi Luben,
>>
>> May I have your Review-by?
>>
If you'd like--it's completely up to you. If you choose to, like Alex's below.
Regards,
Luben
>
> Series is:
> Reviewed-by: Alex Deucher
>
>> Thanks a lot!
>> Rico
>>
>> From: Tuikov, Luben
>> Sent: Friday, December 20, 2019 3:47
>> To: Yin, Tianci (Rico) ; amd-gfx@lists.freedesktop.org
>>
>> Cc: Koenig, Christian ; Deucher, Alexander
>> ; Zhang, Hawking ; Xu,
>> Feifei ; Yuan, Xiaojie ; Long, Gang
>> ; Wang, Kevin(Yang)
>> Subject: Re: [PATCH 1/2] drm/amdgpu: update the method to get fb_loc of
>> memory training(V4)
>>
>> Yep! That's perfect--good job!
>>
>> Regards,
>> Luben
>>
>> On 2019-12-19 04:16, Tianci Yin wrote:
>>> From: "Tianci.Yin"
>>>
>>> The method of getting fb_loc changed from parsing VBIOS to
>>> taking certain offset from top of VRAM
>>>
>>> Change-Id: I053b42fdb1d822722fa7980b2cd9f86b3fdce539
>>> Signed-off-by: Tianci.Yin
>>> ---
>>> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 +-
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 2 +-
>>> .../gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | 38 ++-
>>> .../gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h | 2 +-
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 10 -
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 7
>>> drivers/gpu/drm/amd/include/atomfirmware.h| 14 ---
>>> 7 files changed, 23 insertions(+), 53 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>> index a78a363b1d71..fa2cf8e7bc07 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>> @@ -642,9 +642,8 @@ struct amdgpu_fw_vram_usage {
>>>struct amdgpu_bo *reserved_bo;
>>>void *va;
>>>
>>> - /* Offset on the top of VRAM, used as c2p write buffer.
>>> + /* GDDR6 training support flag.
>>>*/
>>> - u64 mem_train_fb_loc;
>>>bool mem_train_support;
>>> };
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
>>> index 9ba80d828876..fdd52d86a4d7 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
>>> @@ -2022,7 +2022,7 @@ int amdgpu_atombios_init(struct amdgpu_device *adev)
>>>if (adev->is_atom_fw) {
>>>amdgpu_atomfirmware_scratch_regs_init(adev);
>>>amdgpu_atomfirmware_allocate_fb_scratch(adev);
>>> - ret = amdgpu_atomfirmware_get_mem_train_fb_loc(adev);
>>> + ret = amdgpu_atomfirmware_get_mem_train_info(adev);
>>>if (ret) {
>>>DRM_ERROR("Failed to get mem train fb location.\n");
>>>return ret;
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
>>> index ff4eb96bdfb5..58f9d8c3a17a 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
>>> @@ -525,16 +525,12 @@ static int gddr6_mem_train_support(struct
>>> amdgpu_device *adev)
>>>return ret;
>>> }
>>>
>>> -int amdgpu_atomfirmware_get_mem_train_fb_loc(struct amdgpu_device *adev)
>>> +int amdgpu_atomfirmware_get_mem_train_info(struct amdgpu_device *adev)
>>> {
>>>struct atom_context *ctx = adev->mode_info.atom_context;
>>> - unsigned char *bios = ctx->bios;
>>> - struct vram_reserve_block *reserved_block;
>>> - int index, block_number;
>>> + int index;
>>>uint8_t frev, crev;
>>>uint16_t data_offset, size;
>>> - uint32_t start_address_in_kb;
>>> - uint64_t offset;
>>>int ret;
>>>
>>>adev->fw_vram_usage.mem_train_support = false;
>>> @@ -569,32 +565,6 @@ int amdgpu_atomfirmware_get_mem_train_fb_loc(struct
>>> amdgpu_device *adev)
>>>return -EINVAL;
>>>}
>>>
>>> - reserved_block = (struct vram_reserve_block *)
>>> - (bios + data_offset + sizeof(struct
>>> atom_common_table_header));
>>> - block_number = ((unsigned int)size - sizeof(struct
>>> atom_common_table_header))
>>> - / sizeof(struct vram_reserve_block);
>>> - reserved_block += (block_number > 0) ? block_number-1 : 0;
>>> - DRM_DEBUG("block_number:0x%04x, last block: 0x%08xkb sz, %dkb fw,
>>> %dkb drv.\n",
>>> - block_number,
>>> - le32_to_cpu(reserved_block->start_address_in_kb),
>>> - le16_to_cpu(reserved_block->used_by_firmware_in_kb),
>>> - le16_to_cpu(reserved_block->used_by_driver_in_kb));
>>> - if (reserved_block->used_by_firmware_in_kb > 0) {
>>> - start_address_in_kb =
>>> le32_to_cpu(reserved_block->start_
Re: [PATCH 4/4] drm/amdkfd: Avoid hanging hardware in stop_cpsch
I agree this patch is a big improvement , I think we need this patch so
SRIOV can put the amdkfd_pre_reset in right place as bare metal mode .
The further improvement can be in separate change .
This serial is reviewed by shaoyun.liu < shaoyun@amd.com>
Regards
shaoyun.liu
On 2019-12-20 2:46 p.m., Felix Kuehling wrote:
On 2019-12-20 14:31, shaoyunl wrote:
Can we use the dqm_lock when we try to get the dqm->is_hw_hang and
dqm->is_resetting inside function kq_uninitialize ?
Spreading the DQM lock around is probably not a good idea. Then I'd
rather do more refactoring to move hqd_load and hqd_destroy out of the
kq_init/kq_uninit functions.
I think more closer we check the status to hqd_destroy it will be
more accurate . It does look better with this logic if the status are
changed after dqm unmap_queue call and before we call hqd_destroy .
Another comment in line.
Regards
shaoyun.liu
On 2019-12-20 11:33 a.m., Felix Kuehling wrote:
dqm->is_hws_hang is protected by the DQM lock. kq_uninitialize runs
outside that lock protection. Therefore I opted to pass in the
hanging flag as a parameter. It also keeps the logic that decides
all of that inside the device queue manager, which I think is cleaner.
I was trying to clean this up further by moving the
pm_init/pm_uninit out of the start_cpsch/stop_cpsch sequence, but
gave up on that idea when I found out that I can't create the kernel
queue in the DQM initialize function because dev->dqm isn't
initialized at that time yet.
Regards,
Felix
On 2019-12-20 10:56, shaoyunl wrote:
Looks like patch 2 is not related to this serial , but anyway .
Patch 1,2,3 are reviewed by shaoyunl
For patch 4 , is it possible we directly check dqm->is_hws_hang ||
dqm->is_resetting inside function kq_uninitialize. so we don't
need other interface change .
I think even Inside that kq_uninitialize function , we still can
get dqm as kq->dev->dqm .
shaoyun.liu
On 2019-12-20 3:30 a.m., Felix Kuehling wrote:
Don't use the HWS if it's known to be hanging. In a reset also
don't try to destroy the HIQ because that may hang on SRIOV if the
KIQ is unresponsive.
Signed-off-by: Felix Kuehling
---
.../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 12
drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c | 8
drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c | 4 ++--
drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 4 ++--
.../gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 2 +-
5 files changed, 17 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index a7e9ec1b3ce3..d7eb6ac37f62 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -946,7 +946,7 @@ static int start_nocpsch(struct
device_queue_manager *dqm)
static int stop_nocpsch(struct device_queue_manager *dqm)
{
if (dqm->dev->device_info->asic_family == CHIP_HAWAII)
- pm_uninit(&dqm->packets);
+ pm_uninit(&dqm->packets, false);
dqm->sched_running = false;
return 0;
@@ -1114,20 +1114,24 @@ static int start_cpsch(struct
device_queue_manager *dqm)
return 0;
fail_allocate_vidmem:
fail_set_sched_resources:
- pm_uninit(&dqm->packets);
+ pm_uninit(&dqm->packets, false);
fail_packet_manager_init:
return retval;
}
static int stop_cpsch(struct device_queue_manager *dqm)
{
+ bool hanging;
+kq_uninitialize(
dqm_lock(dqm);
- unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0);
+ if (!dqm->is_hws_hang)
[shaoyunl] should we check is_resetting here as well . so we ignore
the unmap call even HWS still not detect the hang but we know we
currently in resetting precedure
GPU reset can be done when the HWS is not hanging. In that case
unmapping queues is perfectly safe. In the worst case it'll time out
and dqm->is_hws_hang will be set as a result. I'm planning to add more
checks later so that we can optionally wait in unmap_queues until a
reset is done. We'll need that to do preemptions reliably while a GPU
reset is in progress. So I need to either unmap the queues or be sure
that HWS is hanging.
With yours and Oak's comments I realize, this is far from complete and
more work is needed. But I still think this is an improvement.
Regards,
Felix
+ unmap_queues_cpsch(dqm,
KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0);
+ hanging = dqm->is_hws_hang || dqm->is_resetting;
dqm->sched_running = false;
dqm_unlock(dqm);
kfd_gtt_sa_free(dqm->dev, dqm->fence_mem);
- pm_uninit(&dqm->packets);
+ pm_uninit(&dqm->packets, hanging);
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
index 2d56dc534459..bae706462f96 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_kern
Re: [PATCH v9 14/18] drm/amd/display: Add PBN per slot calculation for DSC
On 2019-12-13 3:08 p.m., mikita.lip...@amd.com wrote:
> From: Mikita Lipski
>
> [why]
> Need to calculate VCPI slots differently for DSC
> to take in account current link rate, link count
> and FEC.
> [how]
> Add helper to get pbn_div from dc_link
>
> Cc: Harry Wentland
> Cc: Lyude Paul
> Signed-off-by: Mikita Lipski
> ---
> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 8
> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h | 2 ++
> 2 files changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> index 7557edee7db0..c376c8ccd391 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> @@ -491,3 +491,11 @@ void amdgpu_dm_initialize_dp_connector(struct
> amdgpu_display_manager *dm,
> aconnector->connector_id);
> }
>
> +int dm_mst_get_pbn_divider(struct dc_link *link)
> +{
> + if (!link)
> + return 0;
> +
> + return dc_link_bandwidth_kbps(link,
> + dc_link_get_link_cap(link)) / (8 * 1000 * 54);
Had to take a look at the DP spec to understand this conversion here, section
2.6.4.1.
LGTM,
Reviewed-by: Leo Li
> +}
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
> index 2da851b40042..a553ea046185 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
> @@ -29,6 +29,8 @@
> struct amdgpu_display_manager;
> struct amdgpu_dm_connector;
>
> +int dm_mst_get_pbn_divider(struct dc_link *link);
> +
> void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
> struct amdgpu_dm_connector *aconnector);
>
>
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Re: [PATCH 1/5] drm/amdgpu: Avoid reclaim fs while eviction lock
One style comment inline.
Yong
On 2019-12-20 1:24 a.m., Alex Sierra wrote:
[Why]
Avoid reclaim filesystem while eviction lock is held called from
MMU notifier.
[How]
Setting PF_MEMALLOC_NOFS flags while eviction mutex is locked.
Using memalloc_nofs_save / memalloc_nofs_restore API.
Change-Id: I5531c9337836e7d4a430df3f16dcc82888e8018c
Signed-off-by: Alex Sierra
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 14 ++---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 28 +-
2 files changed, 34 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index b999b67ff57a..b36daa6230fb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -678,9 +678,9 @@ int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev,
struct amdgpu_vm *vm,
}
}
- mutex_lock(&vm->eviction_lock);
+ vm_eviction_lock(vm);
vm->evicting = false;
- mutex_unlock(&vm->eviction_lock);
+ vm_eviction_unlock(vm);
return 0;
}
@@ -1559,7 +1559,7 @@ static int amdgpu_vm_bo_update_mapping(struct
amdgpu_device *adev,
if (!(flags & AMDGPU_PTE_VALID))
owner = AMDGPU_FENCE_OWNER_KFD;
- mutex_lock(&vm->eviction_lock);
+ vm_eviction_lock(vm);
if (vm->evicting) {
r = -EBUSY;
goto error_unlock;
@@ -1576,7 +1576,7 @@ static int amdgpu_vm_bo_update_mapping(struct
amdgpu_device *adev,
r = vm->update_funcs->commit(¶ms, fence);
error_unlock:
- mutex_unlock(&vm->eviction_lock);
+ vm_eviction_unlock(vm);
return r;
}
@@ -2537,18 +2537,18 @@ bool amdgpu_vm_evictable(struct amdgpu_bo *bo)
return false;
/* Try to block ongoing updates */
- if (!mutex_trylock(&bo_base->vm->eviction_lock))
+ if (!vm_eviction_trylock(bo_base->vm))
return false;
/* Don't evict VM page tables while they are updated */
if (!dma_fence_is_signaled(bo_base->vm->last_direct) ||
!dma_fence_is_signaled(bo_base->vm->last_delayed)) {
- mutex_unlock(&bo_base->vm->eviction_lock);
+ vm_eviction_unlock(bo_base->vm);
return false;
}
bo_base->vm->evicting = true;
- mutex_unlock(&bo_base->vm->eviction_lock);
+ vm_eviction_unlock(bo_base->vm);
return true;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 100547f094ff..d35aa76469ec 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -30,6 +30,7 @@
#include
#include
#include
+#include
#include "amdgpu_sync.h"
#include "amdgpu_ring.h"
@@ -242,9 +243,12 @@ struct amdgpu_vm {
/* tree of virtual addresses mapped */
struct rb_root_cached va;
- /* Lock to prevent eviction while we are updating page tables */
+ /* Lock to prevent eviction while we are updating page tables
+* use vm_eviction_lock/unlock(vm)
+*/
struct mutexeviction_lock;
boolevicting;
+ unsigned intsaved_flags;
[yz] The tabs should be used here instead of spaces.
/* BOs who needs a validation */
struct list_headevicted;
@@ -436,4 +440,26 @@ void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev,
struct amdgpu_vm *vm);
void amdgpu_vm_del_from_lru_notify(struct ttm_buffer_object *bo);
+/* vm eviction_lock can be taken in MMU notifiers. Make sure no reclaim-FS
+ * happens while holding this lock anywhere to prevent deadlocks when
+ * an MMU notifier runs in reclaim-FS context.
+ */
+static inline void vm_eviction_lock(struct amdgpu_vm *vm)
+{
+ mutex_lock(&vm->eviction_lock);
+ vm->saved_flags = memalloc_nofs_save();
+}
+static inline int vm_eviction_trylock(struct amdgpu_vm *vm)
+{
+ if (mutex_trylock(&vm->eviction_lock)) {
+ vm->saved_flags = memalloc_nofs_save();
+ return 1;
+ }
+ return 0;
+}
+static inline void vm_eviction_unlock(struct amdgpu_vm *vm)
+{
+ memalloc_nofs_restore(vm->saved_flags);
+ mutex_unlock(&vm->eviction_lock);
+}
#endif
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Re: [PATCH 3/5] drm/amdgpu: GPU TLB flush API moved to amdgpu_amdkfd
Inline.
On 2019-12-20 4:35 p.m., Felix Kuehling wrote:
On 2019-12-20 1:24, Alex Sierra wrote:
[Why]
TLB flush method has been deprecated using kfd2kgd interface.
This implementation is now on the amdgpu_amdkfd API.
[How]
TLB flush functions now implemented in amdgpu_amdkfd.
Change-Id: Ic51cccdfe6e71288d78da772b6e1b6ced72f8ef7
Signed-off-by: Alex Sierra
Looks good to me. See my comment about the TODO inline.
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 32 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 2 ++
drivers/gpu/drm/amd/amdkfd/kfd_process.c | 8 --
3 files changed, 39 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index d3da9dde4ee1..b7f6e70c5762 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -634,6 +634,38 @@ bool amdgpu_amdkfd_is_kfd_vmid(struct
amdgpu_device *adev, u32 vmid)
return false;
}
+int amdgpu_amdkfd_flush_gpu_tlb_vmid(struct kgd_dev *kgd, uint16_t
vmid)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
+ /* TODO: condition missing for FAMILY above NV */
I'm not sure what's missing here. NV and above don't need any special
treatment. Since SDMA is connected to GFXHUB on NV, only the GFXHUB
needs to be flushed.
Regards,
Felix
+ if (adev->family == AMDGPU_FAMILY_AI) {
+ int i;
+
+ for (i = 0; i < adev->num_vmhubs; i++)
+ amdgpu_gmc_flush_gpu_tlb(adev, vmid, i, 0);
+ } else {
+ amdgpu_gmc_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB_0, 0);
+ }
This if else can be unified by
for (i = 0; i < adev->num_vmhubs; i++)
amdgpu_gmc_flush_gpu_tlb(adev, vmid, i, 0);
+
+ return 0;
+}
+
+int amdgpu_amdkfd_flush_gpu_tlb_pasid(struct kgd_dev *kgd, uint16_t
pasid)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
+ uint32_t flush_type = 0;
+ bool all_hub = false;
+
+ if (adev->gmc.xgmi.num_physical_nodes &&
+ adev->asic_type == CHIP_VEGA20)
+ flush_type = 2;
+
+ if (adev->family == AMDGPU_FAMILY_AI)
+ all_hub = true;
+
+ return amdgpu_gmc_flush_gpu_tlb_pasid(adev, pasid, flush_type,
all_hub);
+}
+
bool amdgpu_amdkfd_have_atomics_support(struct kgd_dev *kgd)
{
struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index 069d5d230810..47b0f2957d1f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -136,6 +136,8 @@ int amdgpu_amdkfd_submit_ib(struct kgd_dev *kgd,
enum kgd_engine_type engine,
uint32_t *ib_cmd, uint32_t ib_len);
void amdgpu_amdkfd_set_compute_idle(struct kgd_dev *kgd, bool idle);
bool amdgpu_amdkfd_have_atomics_support(struct kgd_dev *kgd);
+int amdgpu_amdkfd_flush_gpu_tlb_vmid(struct kgd_dev *kgd, uint16_t
vmid);
+int amdgpu_amdkfd_flush_gpu_tlb_pasid(struct kgd_dev *kgd, uint16_t
pasid);
bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32
vmid);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
index 536a153ac9a4..25b90f70aecd 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
@@ -32,6 +32,7 @@
#include
#include
#include "amdgpu_amdkfd.h"
+#include "amdgpu.h"
struct mm_struct;
@@ -1152,16 +1153,17 @@ int kfd_reserved_mem_mmap(struct kfd_dev
*dev, struct kfd_process *process,
void kfd_flush_tlb(struct kfd_process_device *pdd)
{
struct kfd_dev *dev = pdd->dev;
- const struct kfd2kgd_calls *f2g = dev->kfd2kgd;
if (dev->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) {
/* Nothing to flush until a VMID is assigned, which
* only happens when the first queue is created.
*/
if (pdd->qpd.vmid)
- f2g->invalidate_tlbs_vmid(dev->kgd, pdd->qpd.vmid);
+ amdgpu_amdkfd_flush_gpu_tlb_vmid(dev->kgd,
+ pdd->qpd.vmid);
} else {
- f2g->invalidate_tlbs(dev->kgd, pdd->process->pasid);
+ amdgpu_amdkfd_flush_gpu_tlb_pasid(dev->kgd,
+ pdd->process->pasid);
}
}
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Re: [PATCH 2/5] drm/amdgpu: export function to flush TLB via pasid
On 2019-12-20 1:24 a.m., Alex Sierra wrote:
This can be used directly from amdgpu and amdkfd to invalidate
TLB through pasid.
It supports gmc v7, v8, v9 and v10.
Change-Id: I6563a8eba2e42d1a67fa2547156c20da41d1e490
Signed-off-by: Alex Sierra
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 6 ++
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 81
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 33 ++
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 34 ++
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 84 +
5 files changed, 238 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
index b499a3de8bb6..b6413a56f546 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
@@ -92,6 +92,9 @@ struct amdgpu_gmc_funcs {
/* flush the vm tlb via mmio */
void (*flush_gpu_tlb)(struct amdgpu_device *adev, uint32_t vmid,
uint32_t vmhub, uint32_t flush_type);
+ /* flush the vm tlb via pasid */
+ int (*flush_gpu_tlb_pasid)(struct amdgpu_device *adev, uint16_t pasid,
+ uint32_t flush_type, bool all_hub);
/* flush the vm tlb via ring */
uint64_t (*emit_flush_gpu_tlb)(struct amdgpu_ring *ring, unsigned vmid,
uint64_t pd_addr);
@@ -216,6 +219,9 @@ struct amdgpu_gmc {
};
#define amdgpu_gmc_flush_gpu_tlb(adev, vmid, vmhub, type) ((adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid), (vmhub), (type)))
+#define amdgpu_gmc_flush_gpu_tlb_pasid(adev, pasid, type, allhub) \
+ ((adev)->gmc.gmc_funcs->flush_gpu_tlb_pasid \
+ ((adev), (pasid), (type), (allhub)))
#define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, addr)
(r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (addr))
#define amdgpu_gmc_emit_pasid_mapping(r, vmid, pasid)
(r)->adev->gmc.gmc_funcs->emit_pasid_mapping((r), (vmid), (pasid))
#define amdgpu_gmc_map_mtype(adev, flags)
(adev)->gmc.gmc_funcs->map_mtype((adev),(flags))
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index f5725336a5f2..b1a5408a8d7e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -30,6 +30,8 @@
#include "hdp/hdp_5_0_0_sh_mask.h"
#include "gc/gc_10_1_0_sh_mask.h"
#include "mmhub/mmhub_2_0_0_sh_mask.h"
+#include "athub/athub_2_0_0_sh_mask.h"
+#include "athub/athub_2_0_0_offset.h"
#include "dcn/dcn_2_0_0_offset.h"
#include "dcn/dcn_2_0_0_sh_mask.h"
#include "oss/osssys_5_0_0_offset.h"
@@ -37,6 +39,7 @@
#include "navi10_enum.h"
#include "soc15.h"
+#include "soc15d.h"
#include "soc15_common.h"
#include "nbio_v2_3.h"
@@ -234,6 +237,48 @@ static bool gmc_v10_0_use_invalidate_semaphore(struct
amdgpu_device *adev,
(!amdgpu_sriov_vf(adev)));
}
+static bool gmc_v10_0_get_atc_vmid_pasid_mapping_info(
+ struct amdgpu_device *adev,
+ uint8_t vmid, uint16_t *p_pasid)
+{
+ uint32_t value;
+
+ value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
++ vmid);
+ *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
+
+ return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
+}
+
+static int gmc_v10_0_invalidate_tlbs_with_kiq(struct amdgpu_device *adev,
+ uint16_t pasid, uint32_t flush_type,
+ bool all_hub)
+{
+ signed long r;
+ uint32_t seq;
+ struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
+
+ spin_lock(&adev->gfx.kiq.ring_lock);
+ amdgpu_ring_alloc(ring, 12); /* fence + invalidate_tlbs package*/
+ amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
+ amdgpu_ring_write(ring,
+ PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
+ PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
+ PACKET3_INVALIDATE_TLBS_PASID(pasid) |
+ PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
+ amdgpu_fence_emit_polling(ring, &seq);
+ amdgpu_ring_commit(ring);
+ spin_unlock(&adev->gfx.kiq.ring_lock);
+
+ r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout);
+ if (r < 1) {
+ DRM_ERROR("wait for kiq fence error: %ld.\n", r);
+ return -ETIME;
+ }
+
+ return 0;
+}
+
/*
* GART
* VMID 0 is the physical GPU addresses as used by the kernel.
@@ -380,6 +425,41 @@ static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device
*adev, uint32_t vmid,
DRM_ERROR("Error flushing GPU TLB using the SDMA (%d)!\n", r);
}
+/**
+ * gmc_v10_0_flush_gpu_tlb_pasid - tlb flush via pasid
+ *
+ * @adev: amdgpu_device pointer
+ * @pasid: pasid to be flush
+ *
+ * Flush the TLB for the r
Re: [PATCH 3/5] drm/amdgpu: GPU TLB flush API moved to amdgpu_amdkfd
On 2019-12-20 6:50 p.m., Yong Zhao wrote:
Inline.
On 2019-12-20 4:35 p.m., Felix Kuehling wrote:
On 2019-12-20 1:24, Alex Sierra wrote:
[Why]
TLB flush method has been deprecated using kfd2kgd interface.
This implementation is now on the amdgpu_amdkfd API.
[How]
TLB flush functions now implemented in amdgpu_amdkfd.
Change-Id: Ic51cccdfe6e71288d78da772b6e1b6ced72f8ef7
Signed-off-by: Alex Sierra
Looks good to me. See my comment about the TODO inline.
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 32
++
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 2 ++
drivers/gpu/drm/amd/amdkfd/kfd_process.c | 8 --
3 files changed, 39 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index d3da9dde4ee1..b7f6e70c5762 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -634,6 +634,38 @@ bool amdgpu_amdkfd_is_kfd_vmid(struct
amdgpu_device *adev, u32 vmid)
return false;
}
+int amdgpu_amdkfd_flush_gpu_tlb_vmid(struct kgd_dev *kgd,
uint16_t vmid)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
+ /* TODO: condition missing for FAMILY above NV */
I'm not sure what's missing here. NV and above don't need any special
treatment. Since SDMA is connected to GFXHUB on NV, only the GFXHUB
needs to be flushed.
Regards,
Felix
+ if (adev->family == AMDGPU_FAMILY_AI) {
+ int i;
+
+ for (i = 0; i < adev->num_vmhubs; i++)
+ amdgpu_gmc_flush_gpu_tlb(adev, vmid, i, 0);
+ } else {
+ amdgpu_gmc_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB_0, 0);
+ }
This if else can be unified by
for (i = 0; i < adev->num_vmhubs; i++)
amdgpu_gmc_flush_gpu_tlb(adev, vmid, i, 0);
+
+ return 0;
+}
+
+int amdgpu_amdkfd_flush_gpu_tlb_pasid(struct kgd_dev *kgd, uint16_t
pasid)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
+ uint32_t flush_type = 0;
+ bool all_hub = false;
+
+ if (adev->gmc.xgmi.num_physical_nodes &&
+ adev->asic_type == CHIP_VEGA20)
+ flush_type = 2;
+
+ if (adev->family == AMDGPU_FAMILY_AI)
+ all_hub = true;
+
+ return amdgpu_gmc_flush_gpu_tlb_pasid(adev, pasid, flush_type,
all_hub);
The all_hub parameter can be inferred from num_vmhubs in
flush_gpu_tlb_pasid(), so it can be optimized out here.
+}
+
bool amdgpu_amdkfd_have_atomics_support(struct kgd_dev *kgd)
{
struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index 069d5d230810..47b0f2957d1f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -136,6 +136,8 @@ int amdgpu_amdkfd_submit_ib(struct kgd_dev *kgd,
enum kgd_engine_type engine,
uint32_t *ib_cmd, uint32_t ib_len);
void amdgpu_amdkfd_set_compute_idle(struct kgd_dev *kgd, bool idle);
bool amdgpu_amdkfd_have_atomics_support(struct kgd_dev *kgd);
+int amdgpu_amdkfd_flush_gpu_tlb_vmid(struct kgd_dev *kgd, uint16_t
vmid);
+int amdgpu_amdkfd_flush_gpu_tlb_pasid(struct kgd_dev *kgd, uint16_t
pasid);
bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32
vmid);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
index 536a153ac9a4..25b90f70aecd 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
@@ -32,6 +32,7 @@
#include
#include
#include "amdgpu_amdkfd.h"
+#include "amdgpu.h"
struct mm_struct;
@@ -1152,16 +1153,17 @@ int kfd_reserved_mem_mmap(struct kfd_dev
*dev, struct kfd_process *process,
void kfd_flush_tlb(struct kfd_process_device *pdd)
{
struct kfd_dev *dev = pdd->dev;
- const struct kfd2kgd_calls *f2g = dev->kfd2kgd;
if (dev->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) {
/* Nothing to flush until a VMID is assigned, which
* only happens when the first queue is created.
*/
if (pdd->qpd.vmid)
- f2g->invalidate_tlbs_vmid(dev->kgd, pdd->qpd.vmid);
+ amdgpu_amdkfd_flush_gpu_tlb_vmid(dev->kgd,
+ pdd->qpd.vmid);
} else {
- f2g->invalidate_tlbs(dev->kgd, pdd->process->pasid);
+ amdgpu_amdkfd_flush_gpu_tlb_pasid(dev->kgd,
+ pdd->process->pasid);
}
}
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[PATCH] Revert "drm/amdgpu: simplify ATPX detection"
This reverts commit f5fda6d89afe6e9cedaa1c3303903c905262f6e8.
You can't use BASE_CLASS in pci_get_class.
Bug: https://gitlab.freedesktop.org/drm/amd/issues/995
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
index a97fb759e2f4..3e35a8f2c5e5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
@@ -613,7 +613,17 @@ static bool amdgpu_atpx_detect(void)
bool d3_supported = false;
struct pci_dev *parent_pdev;
- while ((pdev = pci_get_class(PCI_BASE_CLASS_DISPLAY << 16, pdev)) !=
NULL) {
+ while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) !=
NULL) {
+ vga_count++;
+
+ has_atpx |= (amdgpu_atpx_pci_probe_handle(pdev) == true);
+
+ parent_pdev = pci_upstream_bridge(pdev);
+ d3_supported |= parent_pdev && parent_pdev->bridge_d3;
+ amdgpu_atpx_get_quirks(pdev);
+ }
+
+ while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) !=
NULL) {
vga_count++;
has_atpx |= (amdgpu_atpx_pci_probe_handle(pdev) == true);
--
2.24.1
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Re: [PATCH] drm/dp_mst: clear time slots for ports invalid
Mhh-I think I understand the problem you're trying to solve here but I think
this solution might be a bit overkill. When I did the rework of topology
references for ports, I made it so that we can guarantee memory access to a
port without it needing to be a valid part of the topology. As well, all
parents of the port are guaranteed to be accessible for as long as the child
is. Take a look at:
https://01.org/linuxgraphics/gfx-docs/drm/gpu/drm-kms-helpers.html#refcount-relationships-in-a-topology
It's also worth noting that because of this there's a lot of
get_port_validated()/put_port_validated() calls in the MST helpers that are
now bogus and need to be removed once I get a chance. For new code we should
limit the use of topology references to sections of code where we need a
guarantee that resources on the port/branch (such as a drm connector, dp aux
port, etc.) won't go away for as long as we need to use them.
Do you think we could change this patch so instead of removing it from the
proposed payloads on the CONNECTION_STATUS_NOTIFY, we keep the port's memory
allocation around until it's been removed from the proposed payloads table and
clean it up there on the next payload update?
On Fri, 2019-12-06 at 16:39 +0800, Wayne Lin wrote:
> [Why]
> When change the connection status in a MST topology, mst device
> which detect the event will send out CONNECTION_STATUS_NOTIFY messgae.
>
> e.g. src-mst-mst-sst => src-mst (unplug) mst-sst
>
> Currently, under the above case of unplugging device, ports which have
> been allocated payloads and are no longer in the topology still occupy
> time slots and recorded in proposed_vcpi[] of topology manager.
>
> If we don't clean up the proposed_vcpi[], when code flow goes to try to
> update payload table by calling drm_dp_update_payload_part1(), we will
> fail at checking port validation due to there are ports with proposed
> time slots but no longer in the mst topology. As the result of that, we
> will also stop updating the DPCD payload table of down stream port.
>
> [How]
> While handling the CONNECTION_STATUS_NOTIFY message, add a detection to
> see if the event indicates that a device is unplugged to an output port.
> If the detection is true, then iterrate over all proposed_vcpi[] to
> see whether a port of the proposed_vcpi[] is still in the topology or
> not. If the port is invalid, set its num_slots to 0.
>
> Thereafter, when try to update payload table by calling
> drm_dp_update_payload_part1(), we can successfully update the DPCD
> payload table of down stream port and clear the proposed_vcpi[] to NULL.
>
> Signed-off-by: Wayne Lin
> Cc: sta...@vger.kernel.org
> ---
> drivers/gpu/drm/drm_dp_mst_topology.c | 24 +++-
> 1 file changed, 23 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c
> b/drivers/gpu/drm/drm_dp_mst_topology.c
> index 5306c47dc820..2e236b6275c4 100644
> --- a/drivers/gpu/drm/drm_dp_mst_topology.c
> +++ b/drivers/gpu/drm/drm_dp_mst_topology.c
> @@ -2318,7 +2318,7 @@ drm_dp_mst_handle_conn_stat(struct drm_dp_mst_branch
> *mstb,
> {
> struct drm_dp_mst_topology_mgr *mgr = mstb->mgr;
> struct drm_dp_mst_port *port;
> - int old_ddps, ret;
> + int old_ddps, old_input, ret, i;
> u8 new_pdt;
> bool dowork = false, create_connector = false;
>
> @@ -2349,6 +2349,7 @@ drm_dp_mst_handle_conn_stat(struct drm_dp_mst_branch
> *mstb,
> }
>
> old_ddps = port->ddps;
> + old_input = port->input;
> port->input = conn_stat->input_port;
> port->mcs = conn_stat->message_capability_status;
> port->ldps = conn_stat->legacy_device_plug_status;
> @@ -2373,6 +2374,27 @@ drm_dp_mst_handle_conn_stat(struct drm_dp_mst_branch
> *mstb,
> dowork = false;
> }
>
> + if (!old_input && old_ddps != port->ddps && !port->ddps) {
> + for (i = 0; i < mgr->max_payloads; i++) {
> + struct drm_dp_vcpi *vcpi = mgr->proposed_vcpis[i];
> + struct drm_dp_mst_port *port_validated;
> +
> + if (vcpi) {
> + port_validated =
> + container_of(vcpi, struct
> drm_dp_mst_port, vcpi);
> + port_validated =
> + drm_dp_mst_topology_get_port_validated
> (mgr, port_validated);
> + if (!port_validated) {
> + mutex_lock(&mgr->payload_lock);
> + vcpi->num_slots = 0;
> + mutex_unlock(&mgr->payload_lock);
> + } else {
> + drm_dp_mst_topology_put_port(port_vali
> dated);
> + }
> + }
> + }
> + }
> +
> if (port->connector)
> drm_modeset_unlock(&mgr->base.lock);
> else if (cre
[PATCH] ALSA: hda/hdmi - fix atpx_present when CLASS is not VGA
You can't use PCI_BASE_CLASS with pci_get_class(). This
happens to work by luck on devices with PCI_CLASS_DISPLAY_VGA, but
misses PCI_CLASS_DISPLAY_OTHER. Add a check for those as well.
Signed-off-by: Alex Deucher
---
sound/pci/hda/hda_intel.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c
index b856b89378ac..f69c8de64bd6 100644
--- a/sound/pci/hda/hda_intel.c
+++ b/sound/pci/hda/hda_intel.c
@@ -1410,7 +1410,17 @@ static bool atpx_present(void)
acpi_handle dhandle, atpx_handle;
acpi_status status;
- while ((pdev = pci_get_class(PCI_BASE_CLASS_DISPLAY << 16, pdev)) !=
NULL) {
+ while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) !=
NULL) {
+ dhandle = ACPI_HANDLE(&pdev->dev);
+ if (dhandle) {
+ status = acpi_get_handle(dhandle, "ATPX", &atpx_handle);
+ if (!ACPI_FAILURE(status)) {
+ pci_dev_put(pdev);
+ return true;
+ }
+ }
+ }
+ while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) !=
NULL) {
dhandle = ACPI_HANDLE(&pdev->dev);
if (dhandle) {
status = acpi_get_handle(dhandle, "ATPX", &atpx_handle);
--
2.24.1
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