Re: [PATCH] drm/amdgpu: infinite retries fix from UTLC1 RB SDMA

[philip yang]

Maybe copy paste typo inline.

Philip

On 2020-03-20 10:41 a.m., Felix Kuehling wrote:

On 2020-03-19 20:27, Alex Sierra wrote:

[Why]
Previously these registers were set to 0. This was causing an
infinite retry on the UTCL1 RB, preventing higher priority RB such as 
paging RB.


[How]
Set to one the SDMAx_UTLC1_TIMEOUT registers for all SDMAs on Arcturus.


Please update this description because the patch is no longer limited 
to Arcturus.


One more comment inline. With those fixed, the patch is

Reviewed-by: Felix Kuehling 




Signed-off-by: Alex Sierra 
---
  drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 21 +
  1 file changed, 17 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

index fc664ec6b5fd..09c08906046f 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -115,17 +115,21 @@ static const struct soc15_reg_golden 
golden_settings_sdma_4[] = {

  static const struct soc15_reg_golden golden_settings_sdma_vg10[] = {
  SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 
0x0018773f, 0x00104002),
  SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 
0x0018773f, 0x00104002),
+    SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA0_UTCL1_TIMEOUT, 
0x, 0x00010001),
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0x, 
0x00010001),
  SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 
0xfe931f07, 0x02831d07),
  SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 
0x0018773f, 0x00104002),
-    SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 
0x0018773f, 0x00104002)
+    SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 
0x0018773f, 0x00104002),
+    SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 
0x, 0x00010001),

  };
    static const struct soc15_reg_golden golden_settings_sdma_vg12[] = {
  SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 
0x0018773f, 0x00104001),
  SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 
0x0018773f, 0x00104001),
+    SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA1_UTCL1_TIMEOUT, 
0x, 0x00010001),


mmSDMA0_UTCL1_TIMEOUT, although this is same register offset value, it's 
better to use register offset name same as IP block name


  SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 
0xfe931f07, 0x02831d07),
  SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 
0x0018773f, 0x00104001),
-    SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 
0x0018773f, 0x00104001)
+    SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 
0x0018773f, 0x00104001),
+    SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 
0x, 0x00010001),

  };
    static const struct soc15_reg_golden golden_settings_sdma_4_1[] = {
@@ -174,6 +178,7 @@ static const struct soc15_reg_golden 
golden_settings_sdma0_4_2[] =
  SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_RPTR_ADDR_LO, 
0xfffd, 0x0001),
  SOC15_REG_GOLDEN_VALUE(SDMA0, 0, 
mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfff7, 0x00403000),
  SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 
0x03ff, 0x03c0),
+    SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA1_UTCL1_TIMEOUT, 
0x, 0x00010001),

mmSDMA0_UTCL1_TIMEOUT

  };
    static const struct soc15_reg_golden golden_settings_sdma1_4_2[] = {
@@ -203,6 +208,7 @@ static const struct soc15_reg_golden 
golden_settings_sdma1_4_2[] = {
  SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_RPTR_ADDR_LO, 
0xfffd, 0x0001),
  SOC15_REG_GOLDEN_VALUE(SDMA1, 0, 
mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfff7, 0x00403000),
  SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 
0x03ff, 0x03c0),
+    SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 
0x, 0x00010001),

  };
    static const struct soc15_reg_golden golden_settings_sdma_rv1[] =
@@ -222,27 +228,35 @@ static const struct soc15_reg_golden 
golden_settings_sdma_arct[] =
  SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 
0xfe931f07, 0x02831f07),
  SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 
0x773f, 0x4002),
  SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 
0x773f, 0x4002),
+    SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 
0x, 0x00010001),
  SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 
0xfe931f07, 0x02831f07),
  SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 
0x773f, 0x4002),
  SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 
0x773f, 0x4002),
+    SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 
0x, 0x00010001),
  SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_CHICKEN_BITS, 
0xfe931f07, 0x02831f07),
  SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG, 
0x773f, 0x4002),
  SOC15_REG_GOLDEN_VALUE(SDMA2, 0, 

[PATCH 5/8] drm/amdgpu/swSMU: set AC/DC mode based on the current system state (v2)

[Alex Deucher]

Check of the pointer exists and we are actually on AC power.

v2: fix error message to reflect AC/DC mode.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 2cfb911ab370..9a9eb23d8540 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -1155,17 +1155,17 @@ static int smu_smc_table_hw_init(struct smu_context 
*smu,
}
}
 
-   if (adev->asic_type >= CHIP_NAVI10 &&
-   adev->asic_type <= CHIP_NAVI12) {
+   if (smu->ppt_funcs->set_power_source) {
/*
 * For Navi1X, manually switch it to AC mode as PMFW
 * may boot it with DC mode.
-* TODO: should check whether we are indeed under AC
-* mode before doing this.
 */
-   ret = smu_set_power_source(smu, SMU_POWER_SOURCE_AC);
+   if (adev->pm.ac_power)
+   ret = smu_set_power_source(smu, 
SMU_POWER_SOURCE_AC);
+   else
+   ret = smu_set_power_source(smu, 
SMU_POWER_SOURCE_DC);
if (ret) {
-   pr_err("Failed to switch to AC mode!\n");
+   pr_err("Failed to switch to %s mode!\n", 
adev->pm.ac_power ? "AC" : "DC");
return ret;
}
}
-- 
2.25.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH hmm 0/6] Small hmm_range_fault() cleanups

[Ralph Campbell]

On 3/20/20 9:48 AM, Jason Gunthorpe wrote:

From: Jason Gunthorpe 

I've had these in my work queue for a bit, nothing profound here, just some
small edits for clarity.

Ralph's hmm tester will need a small diff to work after this - which
illustrates how setting default_flags == 0 is the same as what was called
SNAPSHOT:

diff --git a/lib/test_hmm.c b/lib/test_hmm.c
index 6ca953926dc13f..5f31f5b3e64cb9 100644
--- a/lib/test_hmm.c
+++ b/lib/test_hmm.c
@@ -300,7 +300,7 @@ static int dmirror_range_fault(struct dmirror *dmirror,
  
  		range->notifier_seq = mmu_interval_read_begin(range->notifier);

down_read(>mmap_sem);
-   count = hmm_range_fault(range, 0);
+   count = hmm_range_fault(range);
up_read(>mmap_sem);
if (count <= 0) {
if (count == 0 || count == -EBUSY)
@@ -337,8 +337,7 @@ static int dmirror_fault(struct dmirror *dmirror, unsigned 
long start,
.flags = dmirror_hmm_flags,
.values = dmirror_hmm_values,
.pfn_shift = DPT_SHIFT,
-   .pfn_flags_mask = ~(dmirror_hmm_flags[HMM_PFN_VALID] |
-   dmirror_hmm_flags[HMM_PFN_WRITE]),
+   .pfn_flags_mask = 0,
.default_flags = dmirror_hmm_flags[HMM_PFN_VALID] |
(write ? dmirror_hmm_flags[HMM_PFN_WRITE] : 0),
.dev_private_owner = dmirror->mdevice,
@@ -872,7 +871,7 @@ static int dmirror_range_snapshot(struct dmirror *dmirror,
range->notifier_seq = mmu_interval_read_begin(range->notifier);
  
  		down_read(>mmap_sem);

-   count = hmm_range_fault(range, HMM_FAULT_SNAPSHOT);
+   count = hmm_range_fault(range);
up_read(>mmap_sem);
if (count <= 0) {
if (count == 0 || count == -EBUSY)
@@ -916,7 +915,7 @@ static int dmirror_snapshot(struct dmirror *dmirror,
.flags = dmirror_hmm_flags,
.values = dmirror_hmm_values,
.pfn_shift = DPT_SHIFT,
-   .pfn_flags_mask = ~0ULL,
+   .pfn_flags_mask = 0,
.dev_private_owner = dmirror->mdevice,
};
int ret = 0;

Jason Gunthorpe (6):
   mm/hmm: remove pgmap checking for devmap pages
   mm/hmm: return the fault type from hmm_pte_need_fault()
   mm/hmm: remove unused code and tidy comments
   mm/hmm: remove HMM_FAULT_SNAPSHOT
   mm/hmm: remove the CONFIG_TRANSPARENT_HUGEPAGE #ifdef
   mm/hmm: use device_private_entry_to_pfn()

  Documentation/vm/hmm.rst|  12 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c |   2 +-
  drivers/gpu/drm/nouveau/nouveau_svm.c   |   2 +-
  include/linux/hmm.h |  55 +-
  mm/hmm.c| 238 +---
  5 files changed, 98 insertions(+), 211 deletions(-)


The series looks good to me so,
Reviewed-by: Ralph Campbell 
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH hmm 3/6] mm/hmm: remove unused code and tidy comments

[Ralph Campbell]

On 3/20/20 9:49 AM, Jason Gunthorpe wrote:

From: Jason Gunthorpe 

Delete several functions that are never called, fix some desync between
comments and structure content, remove an unused ret, and move one
function only used by hmm.c into hmm.c

Signed-off-by: Jason Gunthorpe 


Reviewed-by: Ralph Campbell 


---
  include/linux/hmm.h | 50 -
  mm/hmm.c| 12 +++
  2 files changed, 12 insertions(+), 50 deletions(-)

diff --git a/include/linux/hmm.h b/include/linux/hmm.h
index bb6be4428633a8..184a8633260f9d 100644
--- a/include/linux/hmm.h
+++ b/include/linux/hmm.h
@@ -120,9 +120,6 @@ enum hmm_pfn_value_e {
   *
   * @notifier: a mmu_interval_notifier that includes the start/end
   * @notifier_seq: result of mmu_interval_read_begin()
- * @hmm: the core HMM structure this range is active against
- * @vma: the vm area struct for the range
- * @list: all range lock are on a list
   * @start: range virtual start address (inclusive)
   * @end: range virtual end address (exclusive)
   * @pfns: array of pfns (big enough for the range)
@@ -131,7 +128,6 @@ enum hmm_pfn_value_e {
   * @default_flags: default flags for the range (write, read, ... see hmm doc)
   * @pfn_flags_mask: allows to mask pfn flags so that only default_flags matter
   * @pfn_shifts: pfn shift value (should be <= PAGE_SHIFT)


s/pfn_shifts/pfn_shift


- * @valid: pfns array did not change since it has been fill by an HMM function
   * @dev_private_owner: owner of device private pages
   */
  struct hmm_range {
@@ -171,52 +167,6 @@ static inline struct page *hmm_device_entry_to_page(const 
struct hmm_range *rang
return pfn_to_page(entry >> range->pfn_shift);
  }
  
-/*

- * hmm_device_entry_to_pfn() - return pfn value store in a device entry
- * @range: range use to decode device entry value
- * @entry: device entry to extract pfn from
- * Return: pfn value if device entry is valid, -1UL otherwise
- */
-static inline unsigned long
-hmm_device_entry_to_pfn(const struct hmm_range *range, uint64_t pfn)
-{
-   if (pfn == range->values[HMM_PFN_NONE])
-   return -1UL;
-   if (pfn == range->values[HMM_PFN_ERROR])
-   return -1UL;
-   if (pfn == range->values[HMM_PFN_SPECIAL])
-   return -1UL;
-   if (!(pfn & range->flags[HMM_PFN_VALID]))
-   return -1UL;
-   return (pfn >> range->pfn_shift);
-}
-
-/*
- * hmm_device_entry_from_page() - create a valid device entry for a page
- * @range: range use to encode HMM pfn value
- * @page: page for which to create the device entry
- * Return: valid device entry for the page
- */
-static inline uint64_t hmm_device_entry_from_page(const struct hmm_range 
*range,
- struct page *page)
-{
-   return (page_to_pfn(page) << range->pfn_shift) |
-   range->flags[HMM_PFN_VALID];
-}
-
-/*
- * hmm_device_entry_from_pfn() - create a valid device entry value from pfn
- * @range: range use to encode HMM pfn value
- * @pfn: pfn value for which to create the device entry
- * Return: valid device entry for the pfn
- */
-static inline uint64_t hmm_device_entry_from_pfn(const struct hmm_range *range,
-unsigned long pfn)
-{
-   return (pfn << range->pfn_shift) |
-   range->flags[HMM_PFN_VALID];
-}
-
  /* Don't fault in missing PTEs, just snapshot the current state. */
  #define HMM_FAULT_SNAPSHOT(1 << 1)
  
diff --git a/mm/hmm.c b/mm/hmm.c

index b4f662eadb7a7c..687d21c675ee60 100644
--- a/mm/hmm.c
+++ b/mm/hmm.c
@@ -37,6 +37,18 @@ enum {
NEED_WRITE_FAULT = 1 << 1,
  };
  
+/*

+ * hmm_device_entry_from_pfn() - create a valid device entry value from pfn
+ * @range: range use to encode HMM pfn value
+ * @pfn: pfn value for which to create the device entry
+ * Return: valid device entry for the pfn
+ */
+static uint64_t hmm_device_entry_from_pfn(const struct hmm_range *range,
+ unsigned long pfn)
+{
+   return (pfn << range->pfn_shift) | range->flags[HMM_PFN_VALID];
+}
+
  static int hmm_pfns_fill(unsigned long addr, unsigned long end,
struct hmm_range *range, enum hmm_pfn_value_e value)
  {


___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH hmm 0/6] Small hmm_range_fault() cleanups

[Jason Gunthorpe]

On Fri, Mar 20, 2020 at 11:51:47AM -0700, Ralph Campbell wrote:
> 
> On 3/20/20 9:48 AM, Jason Gunthorpe wrote:
> > From: Jason Gunthorpe 
> > 
> > I've had these in my work queue for a bit, nothing profound here, just some
> > small edits for clarity.
> 
> The hmm tester changes are clear enough but I'm having a bit of trouble 
> figuring out
> what this series applies cleanly to since I'm trying to apply it on top of the
> other patches you and Christoph have sent out.
> Is there a private git tree/branch where everything is applied?

I accumulate everything here:

https://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma.git/log/?h=hmm

The patches should apply on top of that

Jason
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 1/4] drm/amdgpu: add stride to calculate oss ring offsets

[Christian König]

Am 20.03.20 um 15:20 schrieb Felix Kuehling:

On 2020-03-20 10:06, Deucher, Alexander wrote:


[AMD Public Use]


This seems kind of complicated and error prone.  I didn't realize the 
extent to the changes required.  I think it would be better to either 
add arcturus specific versions of these functions or just go with 
your original approach and add a new arcturus_ih.c.  If you go with 
the second route however, no need to show all your intermediate 
steps, just add the new files in one commit.


Hi Alex,


I suggested the approach in this patch series since to minimize code 
duplication and maintain readability of the code. I don't think it's 
very error prone. I believe this is more maintainable than a separate 
arcturus_ih.c. I'll have some more specific comments on Alejandro's 
patches.




Question is rather if Arcturus has really the same OSS block than Vega10 
or if the registers are just the same and at a different offset?


If the later (which I suspect) than that should really be the same file.

Regards,
Christian.



Regards,
  Felix




Alex


*From:* amd-gfx  on behalf of 
Alex Sierra 

*Sent:* Thursday, March 19, 2020 8:22 PM
*To:* amd-gfx@lists.freedesktop.org 
*Cc:* Sierra Guiza, Alejandro (Alex) 
*Subject:* [PATCH 1/4] drm/amdgpu: add stride to calculate oss ring 
offsets

Arcturus and vega10 share the same vega10_ih, however both
have different register offsets at the ih ring section.
This variable is used to help calculate ih ring register addresses
from the osssys, that corresponds to the current asic type.

Signed-off-by: Alex Sierra 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 4 
 drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h | 1 +
 2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c

index 5ed4227f304b..fa384ae9a9bc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
@@ -279,6 +279,10 @@ int amdgpu_irq_init(struct amdgpu_device *adev)
amdgpu_hotplug_work_func);
 }

+   if (adev->asic_type == CHIP_ARCTURUS)
+   adev->irq.ring_stride = 1;
+   else
+   adev->irq.ring_stride = 0;
 INIT_WORK(>irq.ih1_work, amdgpu_irq_handle_ih1);
 INIT_WORK(>irq.ih2_work, amdgpu_irq_handle_ih2);

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h

index c718e94a55c9..1ec5b735cd9e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
@@ -97,6 +97,7 @@ struct amdgpu_irq {
 struct irq_domain   *domain; /* GPU irq 
controller domain */

 unsigned virq[AMDGPU_MAX_IRQ_SRC_ID];
 uint32_t srbm_soft_reset;
+   unsigned    ring_stride;
 };

 void amdgpu_irq_disable_all(struct amdgpu_device *adev);
--
2.17.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfxdata=02%7C01%7Calexander.deucher%40amd.com%7C17d5391c86ff4ceee12b08d7cc64f056%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637202606831789803sdata=B%2BbtLEKN5A65OEp8se5m1M4aQGX7kxsqYYGTTukF5m8%3Dreserved=0< 
/a>





 


___ amd-gfx mailing list   

Re: [PATCH hmm 0/6] Small hmm_range_fault() cleanups

[Ralph Campbell]

On 3/20/20 9:48 AM, Jason Gunthorpe wrote:

From: Jason Gunthorpe 

I've had these in my work queue for a bit, nothing profound here, just some
small edits for clarity.


The hmm tester changes are clear enough but I'm having a bit of trouble 
figuring out
what this series applies cleanly to since I'm trying to apply it on top of the
other patches you and Christoph have sent out.
Is there a private git tree/branch where everything is applied?



Ralph's hmm tester will need a small diff to work after this - which
illustrates how setting default_flags == 0 is the same as what was called
SNAPSHOT:

diff --git a/lib/test_hmm.c b/lib/test_hmm.c
index 6ca953926dc13f..5f31f5b3e64cb9 100644
--- a/lib/test_hmm.c
+++ b/lib/test_hmm.c
@@ -300,7 +300,7 @@ static int dmirror_range_fault(struct dmirror *dmirror,
  
  		range->notifier_seq = mmu_interval_read_begin(range->notifier);

down_read(>mmap_sem);
-   count = hmm_range_fault(range, 0);
+   count = hmm_range_fault(range);
up_read(>mmap_sem);
if (count <= 0) {
if (count == 0 || count == -EBUSY)
@@ -337,8 +337,7 @@ static int dmirror_fault(struct dmirror *dmirror, unsigned 
long start,
.flags = dmirror_hmm_flags,
.values = dmirror_hmm_values,
.pfn_shift = DPT_SHIFT,
-   .pfn_flags_mask = ~(dmirror_hmm_flags[HMM_PFN_VALID] |
-   dmirror_hmm_flags[HMM_PFN_WRITE]),
+   .pfn_flags_mask = 0,
.default_flags = dmirror_hmm_flags[HMM_PFN_VALID] |
(write ? dmirror_hmm_flags[HMM_PFN_WRITE] : 0),
.dev_private_owner = dmirror->mdevice,
@@ -872,7 +871,7 @@ static int dmirror_range_snapshot(struct dmirror *dmirror,
range->notifier_seq = mmu_interval_read_begin(range->notifier);
  
  		down_read(>mmap_sem);

-   count = hmm_range_fault(range, HMM_FAULT_SNAPSHOT);
+   count = hmm_range_fault(range);
up_read(>mmap_sem);
if (count <= 0) {
if (count == 0 || count == -EBUSY)
@@ -916,7 +915,7 @@ static int dmirror_snapshot(struct dmirror *dmirror,
.flags = dmirror_hmm_flags,
.values = dmirror_hmm_values,
.pfn_shift = DPT_SHIFT,
-   .pfn_flags_mask = ~0ULL,
+   .pfn_flags_mask = 0,
.dev_private_owner = dmirror->mdevice,
};
int ret = 0;

Jason Gunthorpe (6):
   mm/hmm: remove pgmap checking for devmap pages
   mm/hmm: return the fault type from hmm_pte_need_fault()
   mm/hmm: remove unused code and tidy comments
   mm/hmm: remove HMM_FAULT_SNAPSHOT
   mm/hmm: remove the CONFIG_TRANSPARENT_HUGEPAGE #ifdef
   mm/hmm: use device_private_entry_to_pfn()

  Documentation/vm/hmm.rst|  12 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c |   2 +-
  drivers/gpu/drm/nouveau/nouveau_svm.c   |   2 +-
  include/linux/hmm.h |  55 +-
  mm/hmm.c| 238 +---
  5 files changed, 98 insertions(+), 211 deletions(-)


___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 3/8] drm/amdgpu/swSMU: use the smu11 power source helper for navi1x

[Alex Deucher]

The smu_v11_0 version works for navi1x.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c 
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index d66dfa7410b6..a23eaac28095 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -2369,6 +2369,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
.get_pptable_power_limit = navi10_get_pptable_power_limit,
.run_btc = navi10_run_btc,
.disable_umc_cdr_12gbps_workaround = 
navi10_disable_umc_cdr_12gbps_workaround,
+   .set_power_source = smu_v11_0_set_power_source,
 };
 
 void navi10_set_ppt_funcs(struct smu_context *smu)
-- 
2.25.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 5/8] drm/amdgpu/swSMU: set AC/DC mode based on the current system state

[Alex Deucher]

Check of the pointer exists and we are actually on AC power.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 2cfb911ab370..54d156bbc0f3 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -1155,15 +1155,15 @@ static int smu_smc_table_hw_init(struct smu_context 
*smu,
}
}
 
-   if (adev->asic_type >= CHIP_NAVI10 &&
-   adev->asic_type <= CHIP_NAVI12) {
+   if (smu->ppt_funcs->set_power_source) {
/*
 * For Navi1X, manually switch it to AC mode as PMFW
 * may boot it with DC mode.
-* TODO: should check whether we are indeed under AC
-* mode before doing this.
 */
-   ret = smu_set_power_source(smu, SMU_POWER_SOURCE_AC);
+   if (adev->pm.ac_power)
+   ret = smu_set_power_source(smu, 
SMU_POWER_SOURCE_AC);
+   else
+   ret = smu_set_power_source(smu, 
SMU_POWER_SOURCE_DC);
if (ret) {
pr_err("Failed to switch to AC mode!\n");
return ret;
-- 
2.25.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm/amdgpu: fix size validation failure in large buffer creation

[Christian König]

Am 20.03.20 um 10:46 schrieb Tianci Yin:

From: "Tianci.Yin" 

[why]
When GTT domain size is smaller than VRAM, if APP apply a very large
buffer whose size is larger than GTT but smaller than VRAM, the size
validation will fail.

[how]
Validate VRAM domain size at first place, then GTT domain.


NAK, this is intended behavior. VRAM allocations larger than GTT 
allocations are illegal and can crash the memory management.


Regards,
Christian.



Change-Id: Ic1d31b9b0a4939e6bba0241ff79ae9aa2225ee05
Signed-off-by: Tianci.Yin 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 18 +-
  1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 84745f9e7408..bab134b6369f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -464,21 +464,21 @@ static bool amdgpu_bo_validate_size(struct amdgpu_device 
*adev,
  {
struct ttm_mem_type_manager *man = NULL;
  
-	/*

-* If GTT is part of requested domains the check must succeed to
-* allow fall back to GTT
-*/
-   if (domain & AMDGPU_GEM_DOMAIN_GTT) {
-   man = >mman.bdev.man[TTM_PL_TT];
+   if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
+   man = >mman.bdev.man[TTM_PL_VRAM];
  
  		if (size < (man->size << PAGE_SHIFT))

return true;
-   else
+   else if (!(domain & AMDGPU_GEM_DOMAIN_GTT))
goto fail;
}
  
-	if (domain & AMDGPU_GEM_DOMAIN_VRAM) {

-   man = >mman.bdev.man[TTM_PL_VRAM];
+   /*
+* If GTT is part of requested domains the check must succeed to
+* allow fall back to GTT
+*/
+   if (domain & AMDGPU_GEM_DOMAIN_GTT) {
+   man = >mman.bdev.man[TTM_PL_TT];
  
  		if (size < (man->size << PAGE_SHIFT))

return true;


___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 8/8] drm/amdgpu/smu11: add support for SMU AC/DC interrupts

[Alex Deucher]

Driver needs to send the ack message when it receives the
AC/DC interrupt from the SMU.

TODO: verify the client and src ids.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 16 
 1 file changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c 
b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 20174bed11ce..d19e1d0d56c0 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -1525,6 +1525,13 @@ int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
return ret;
 }
 
+static int smu_v11_0_ack_ac_dc_interrupt(struct smu_context *smu)
+{
+   return smu_send_smc_msg(smu,
+   SMU_MSG_ReenableAcDcInterrupt,
+   NULL);
+}
+
 #define THM_11_0__SRCID__THM_DIG_THERM_L2H 0   /* 
ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH  */
 #define THM_11_0__SRCID__THM_DIG_THERM_H2L 1   /* 
ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL  */
 
@@ -1558,6 +1565,9 @@ static int smu_v11_0_irq_process(struct amdgpu_device 
*adev,
break;
 
}
+   } else if (client_id == SOC15_IH_CLIENTID_MP1) {
+   if (src_id == 0xfe)
+   smu_v11_0_ack_ac_dc_interrupt(>smu);
}
 
return 0;
@@ -1597,6 +1607,12 @@ int smu_v11_0_register_irq_handler(struct smu_context 
*smu)
if (ret)
return ret;
 
+   ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1,
+   0xfe,
+   irq_src);
+   if (ret)
+   return ret;
+
return ret;
 }
 
-- 
2.25.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 7/8] drm/amdgpu/swSMU: handle manual AC/DC notifications

[Alex Deucher]

For boards that do not support automatic AC/DC transitions
in firmware, manually tell the firmware when the status
changes.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c|  3 +++
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 23 +++
 .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h|  1 +
 3 files changed, 27 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index bc3cf04a1a94..f197f1be0969 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -92,6 +92,9 @@ void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev)
if (adev->powerplay.pp_funcs->enable_bapm)
amdgpu_dpm_enable_bapm(adev, adev->pm.ac_power);
mutex_unlock(>pm.mutex);
+
+   if (is_support_sw_smu(adev))
+   smu_set_ac_dc(>smu);
}
 }
 
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 54d156bbc0f3..6f4015f87781 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -2087,6 +2087,29 @@ int smu_set_watermarks_for_clock_ranges(struct 
smu_context *smu,
return 0;
 }
 
+int smu_set_ac_dc(struct smu_context *smu)
+{
+   int ret = 0;
+
+   /* controlled by firmware */
+   if (smu->dc_controlled_by_gpio)
+   return 0;
+
+   mutex_lock(>mutex);
+   if (smu->ppt_funcs->set_power_source) {
+   if (smu->adev->pm.ac_power)
+   ret = smu_set_power_source(smu, SMU_POWER_SOURCE_AC);
+   else
+   ret = smu_set_power_source(smu, SMU_POWER_SOURCE_DC);
+   if (ret)
+   pr_err("Failed to switch to %s mode!\n",
+  smu->adev->pm.ac_power ? "AC" : "DC");
+   }
+   mutex_unlock(>mutex);
+
+   return ret;
+}
+
 const struct amd_ip_funcs smu_ip_funcs = {
.name = "smu",
.early_init = smu_early_init,
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 18172dfec947..ae2c318dd6fa 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -720,6 +720,7 @@ int smu_get_dpm_level_range(struct smu_context *smu, enum 
smu_clk_type clk_type,
 enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu);
 int smu_force_performance_level(struct smu_context *smu, enum 
amd_dpm_forced_level level);
 int smu_set_display_count(struct smu_context *smu, uint32_t count);
+int smu_set_ac_dc(struct smu_context *smu);
 bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type 
clk_type);
 const char *smu_get_message_name(struct smu_context *smu, enum 
smu_message_type type);
 const char *smu_get_feature_name(struct smu_context *smu, enum 
smu_feature_mask feature);
-- 
2.25.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 2/8] drm/amdgpu/smu11: add a helper to set the power source

[Alex Deucher]

Add a common smu11 helper to set the AC/DC power source.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h |  3 +++
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 15 +++
 2 files changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h 
b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
index 1c88219fe403..674e426ed59b 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
@@ -267,4 +267,7 @@ uint32_t smu_v11_0_get_max_power_limit(struct smu_context 
*smu);
 int smu_v11_0_set_performance_level(struct smu_context *smu,
enum amd_dpm_forced_level level);
 
+int smu_v11_0_set_power_source(struct smu_context *smu,
+  enum smu_power_src_type power_src);
+
 #endif
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c 
b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 4fd77c7cfc80..20174bed11ce 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -1939,3 +1939,18 @@ int smu_v11_0_set_performance_level(struct smu_context 
*smu,
return ret;
 }
 
+int smu_v11_0_set_power_source(struct smu_context *smu,
+  enum smu_power_src_type power_src)
+{
+   int pwr_source;
+
+   pwr_source = smu_power_get_index(smu, (uint32_t)power_src);
+   if (pwr_source < 0)
+   return -EINVAL;
+
+   return smu_send_smc_msg_with_param(smu,
+   SMU_MSG_NotifyPowerSource,
+   pwr_source,
+   NULL);
+}
+
-- 
2.25.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 6/8] drm/amdgpu/swSMU: handle DC controlled by GPIO for navi1x

[Alex Deucher]

Check the platform caps in the vbios pptable to decide
whether to enable automatic AC/DC transitions.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 1 +
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 7 ++-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 323e7e61493b..18172dfec947 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -408,6 +408,7 @@ struct smu_context
uint32_t smc_if_version;
 
bool uploading_custom_pp_table;
+   bool dc_controlled_by_gpio;
 };
 
 struct i2c_adapter;
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c 
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index a23eaac28095..9c60b38ab53a 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -347,7 +347,6 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
| FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
| FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
| FEATURE_MASK(FEATURE_BACO_BIT)
-   | FEATURE_MASK(FEATURE_ACDC_BIT)
| FEATURE_MASK(FEATURE_GFX_SS_BIT)
| FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
| FEATURE_MASK(FEATURE_FW_CTF_BIT)
@@ -391,6 +390,9 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
if (smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_JPEG_PG_BIT);
 
+   if (smu->dc_controlled_by_gpio)
+   *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT);
+
/* disable DPM UCLK and DS SOCCLK on navi10 A0 secure board */
if (is_asic_secure(smu)) {
/* only for navi10 A0 */
@@ -525,6 +527,9 @@ static int navi10_store_powerplay_table(struct smu_context 
*smu)
 
table_context->thermal_controller_type = 
powerplay_table->thermal_controller_type;
 
+   if (powerplay_table->platform_caps & 
SMU_11_0_PP_PLATFORM_CAP_HARDWAREDC)
+   smu->dc_controlled_by_gpio = true;
+
mutex_lock(_baco->mutex);
if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO)
-- 
2.25.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH hmm 5/6] mm/hmm: remove the CONFIG_TRANSPARENT_HUGEPAGE #ifdef

[Jason Gunthorpe]

From: Jason Gunthorpe 

This code can be compiled when CONFIG_TRANSPARENT_HUGEPAGE is off, so
remove the ifdef.

Signed-off-by: Jason Gunthorpe 
---
 mm/hmm.c | 6 --
 1 file changed, 6 deletions(-)

diff --git a/mm/hmm.c b/mm/hmm.c
index 7f77fb6e35cf78..a09b4908e9c81a 100644
--- a/mm/hmm.c
+++ b/mm/hmm.c
@@ -192,7 +192,6 @@ static inline uint64_t pmd_to_hmm_pfn_flags(struct 
hmm_range *range, pmd_t pmd)
range->flags[HMM_PFN_VALID];
 }
 
-#ifdef CONFIG_TRANSPARENT_HUGEPAGE
 static int hmm_vma_handle_pmd(struct mm_walk *walk, unsigned long addr,
unsigned long end, uint64_t *pfns, pmd_t pmd)
 {
@@ -215,11 +214,6 @@ static int hmm_vma_handle_pmd(struct mm_walk *walk, 
unsigned long addr,
hmm_vma_walk->last = end;
return 0;
 }
-#else /* CONFIG_TRANSPARENT_HUGEPAGE */
-/* stub to allow the code below to compile */
-int hmm_vma_handle_pmd(struct mm_walk *walk, unsigned long addr,
-   unsigned long end, uint64_t *pfns, pmd_t pmd);
-#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
 
 static inline bool hmm_is_device_private_entry(struct hmm_range *range,
swp_entry_t entry)
-- 
2.25.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH hmm 4/6] mm/hmm: remove HMM_FAULT_SNAPSHOT

[Jason Gunthorpe]

From: Jason Gunthorpe 

Now that flags are handled on a fine-grained per-page basis this global
flag is redundant and has a confusing overlap with the pfn_flags_mask and
default_flags.

Normalize the HMM_FAULT_SNAPSHOT behavior into one place. Callers needing
the SNAPSHOT behavior should set a pfn_flags_mask and default_flags that
always results in a cleared HMM_PFN_REQ_FAULT. Then no pages will be
faulted, and HMM_FAULT_SNAPSHOT is not a special flow that overrides the
masking mechanism.

As this is the last flag, also remove the flags argument. If future flags
are needed they can be part of the struct hmm_range function arguments.

Signed-off-by: Jason Gunthorpe 
---
 Documentation/vm/hmm.rst| 12 +---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c |  2 +-
 drivers/gpu/drm/nouveau/nouveau_svm.c   |  2 +-
 include/linux/hmm.h |  5 +
 mm/hmm.c| 17 +
 5 files changed, 17 insertions(+), 21 deletions(-)

diff --git a/Documentation/vm/hmm.rst b/Documentation/vm/hmm.rst
index 95fec596836262..4e3e9362afeb10 100644
--- a/Documentation/vm/hmm.rst
+++ b/Documentation/vm/hmm.rst
@@ -161,13 +161,11 @@ device must complete the update before the driver 
callback returns.
 When the device driver wants to populate a range of virtual addresses, it can
 use::
 
-  long hmm_range_fault(struct hmm_range *range, unsigned int flags);
+  long hmm_range_fault(struct hmm_range *range);
 
-With the HMM_RANGE_SNAPSHOT flag, it will only fetch present CPU page table
-entries and will not trigger a page fault on missing or non-present entries.
-Without that flag, it does trigger a page fault on missing or read-only entries
-if write access is requested (see below). Page faults use the generic mm page
-fault code path just like a CPU page fault.
+It will trigger a page fault on missing or read-only entries if write access is
+requested (see below). Page faults use the generic mm page fault code path just
+like a CPU page fault.
 
 Both functions copy CPU page table entries into their pfns array argument. Each
 entry in that array corresponds to an address in the virtual range. HMM
@@ -197,7 +195,7 @@ The usage pattern is::
  again:
   range.notifier_seq = mmu_interval_read_begin(_sub);
   down_read(>mmap_sem);
-  ret = hmm_range_fault(, HMM_RANGE_SNAPSHOT);
+  ret = hmm_range_fault();
   if (ret) {
   up_read(>mmap_sem);
   if (ret == -EBUSY)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 90821ce5e6cad0..c520290709371b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -856,7 +856,7 @@ int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, 
struct page **pages)
range->notifier_seq = mmu_interval_read_begin(>notifier);
 
down_read(>mmap_sem);
-   r = hmm_range_fault(range, 0);
+   r = hmm_range_fault(range);
up_read(>mmap_sem);
if (unlikely(r <= 0)) {
/*
diff --git a/drivers/gpu/drm/nouveau/nouveau_svm.c 
b/drivers/gpu/drm/nouveau/nouveau_svm.c
index 39c731a99937c6..e3797b2d4d1759 100644
--- a/drivers/gpu/drm/nouveau/nouveau_svm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_svm.c
@@ -540,7 +540,7 @@ static int nouveau_range_fault(struct nouveau_svmm *svmm,
range.default_flags = 0;
range.pfn_flags_mask = -1UL;
down_read(>mmap_sem);
-   ret = hmm_range_fault(, 0);
+   ret = hmm_range_fault();
up_read(>mmap_sem);
if (ret <= 0) {
if (ret == 0 || ret == -EBUSY)
diff --git a/include/linux/hmm.h b/include/linux/hmm.h
index 184a8633260f9d..6b4004905aac89 100644
--- a/include/linux/hmm.h
+++ b/include/linux/hmm.h
@@ -167,13 +167,10 @@ static inline struct page *hmm_device_entry_to_page(const 
struct hmm_range *rang
return pfn_to_page(entry >> range->pfn_shift);
 }
 
-/* Don't fault in missing PTEs, just snapshot the current state. */
-#define HMM_FAULT_SNAPSHOT (1 << 1)
-
 /*
  * Please see Documentation/vm/hmm.rst for how to use the range API.
  */
-long hmm_range_fault(struct hmm_range *range, unsigned int flags);
+long hmm_range_fault(struct hmm_range *range);
 
 /*
  * HMM_RANGE_DEFAULT_TIMEOUT - default timeout (ms) when waiting for a range
diff --git a/mm/hmm.c b/mm/hmm.c
index 687d21c675ee60..7f77fb6e35cf78 100644
--- a/mm/hmm.c
+++ b/mm/hmm.c
@@ -29,7 +29,6 @@
 struct hmm_vma_walk {
struct hmm_range*range;
unsigned long   last;
-   unsigned intflags;
 };
 
 enum {
@@ -111,9 +110,6 @@ static unsigned int hmm_pte_need_fault(const struct 
hmm_vma_walk *hmm_vma_walk,
 {
struct hmm_range *range = hmm_vma_walk->range;
 
-   if (hmm_vma_walk->flags & HMM_FAULT_SNAPSHOT)
-   return 0;
-
/*
 * So we not only consider the individual per 

[PATCH hmm 6/6] mm/hmm: use device_private_entry_to_pfn()

[Jason Gunthorpe]

From: Jason Gunthorpe 

swp_offset() should not be called directly, the wrappers are supposed to
abstract away the encoding of the device_private specific information in
the swap entry.

Signed-off-by: Jason Gunthorpe 
---
 mm/hmm.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/mm/hmm.c b/mm/hmm.c
index a09b4908e9c81a..fd9ee2b5fd9989 100644
--- a/mm/hmm.c
+++ b/mm/hmm.c
@@ -259,8 +259,8 @@ static int hmm_vma_handle_pte(struct mm_walk *walk, 
unsigned long addr,
 * the PFN even if not present.
 */
if (hmm_is_device_private_entry(range, entry)) {
-   *pfn = hmm_device_entry_from_pfn(range,
-   swp_offset(entry));
+   *pfn = hmm_device_entry_from_pfn(
+   range, device_private_entry_to_pfn(entry));
*pfn |= range->flags[HMM_PFN_VALID];
if (is_write_device_private_entry(entry))
*pfn |= range->flags[HMM_PFN_WRITE];
-- 
2.25.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH hmm 3/6] mm/hmm: remove unused code and tidy comments

[Jason Gunthorpe]

From: Jason Gunthorpe 

Delete several functions that are never called, fix some desync between
comments and structure content, remove an unused ret, and move one
function only used by hmm.c into hmm.c

Signed-off-by: Jason Gunthorpe 
---
 include/linux/hmm.h | 50 -
 mm/hmm.c| 12 +++
 2 files changed, 12 insertions(+), 50 deletions(-)

diff --git a/include/linux/hmm.h b/include/linux/hmm.h
index bb6be4428633a8..184a8633260f9d 100644
--- a/include/linux/hmm.h
+++ b/include/linux/hmm.h
@@ -120,9 +120,6 @@ enum hmm_pfn_value_e {
  *
  * @notifier: a mmu_interval_notifier that includes the start/end
  * @notifier_seq: result of mmu_interval_read_begin()
- * @hmm: the core HMM structure this range is active against
- * @vma: the vm area struct for the range
- * @list: all range lock are on a list
  * @start: range virtual start address (inclusive)
  * @end: range virtual end address (exclusive)
  * @pfns: array of pfns (big enough for the range)
@@ -131,7 +128,6 @@ enum hmm_pfn_value_e {
  * @default_flags: default flags for the range (write, read, ... see hmm doc)
  * @pfn_flags_mask: allows to mask pfn flags so that only default_flags matter
  * @pfn_shifts: pfn shift value (should be <= PAGE_SHIFT)
- * @valid: pfns array did not change since it has been fill by an HMM function
  * @dev_private_owner: owner of device private pages
  */
 struct hmm_range {
@@ -171,52 +167,6 @@ static inline struct page *hmm_device_entry_to_page(const 
struct hmm_range *rang
return pfn_to_page(entry >> range->pfn_shift);
 }
 
-/*
- * hmm_device_entry_to_pfn() - return pfn value store in a device entry
- * @range: range use to decode device entry value
- * @entry: device entry to extract pfn from
- * Return: pfn value if device entry is valid, -1UL otherwise
- */
-static inline unsigned long
-hmm_device_entry_to_pfn(const struct hmm_range *range, uint64_t pfn)
-{
-   if (pfn == range->values[HMM_PFN_NONE])
-   return -1UL;
-   if (pfn == range->values[HMM_PFN_ERROR])
-   return -1UL;
-   if (pfn == range->values[HMM_PFN_SPECIAL])
-   return -1UL;
-   if (!(pfn & range->flags[HMM_PFN_VALID]))
-   return -1UL;
-   return (pfn >> range->pfn_shift);
-}
-
-/*
- * hmm_device_entry_from_page() - create a valid device entry for a page
- * @range: range use to encode HMM pfn value
- * @page: page for which to create the device entry
- * Return: valid device entry for the page
- */
-static inline uint64_t hmm_device_entry_from_page(const struct hmm_range 
*range,
- struct page *page)
-{
-   return (page_to_pfn(page) << range->pfn_shift) |
-   range->flags[HMM_PFN_VALID];
-}
-
-/*
- * hmm_device_entry_from_pfn() - create a valid device entry value from pfn
- * @range: range use to encode HMM pfn value
- * @pfn: pfn value for which to create the device entry
- * Return: valid device entry for the pfn
- */
-static inline uint64_t hmm_device_entry_from_pfn(const struct hmm_range *range,
-unsigned long pfn)
-{
-   return (pfn << range->pfn_shift) |
-   range->flags[HMM_PFN_VALID];
-}
-
 /* Don't fault in missing PTEs, just snapshot the current state. */
 #define HMM_FAULT_SNAPSHOT (1 << 1)
 
diff --git a/mm/hmm.c b/mm/hmm.c
index b4f662eadb7a7c..687d21c675ee60 100644
--- a/mm/hmm.c
+++ b/mm/hmm.c
@@ -37,6 +37,18 @@ enum {
NEED_WRITE_FAULT = 1 << 1,
 };
 
+/*
+ * hmm_device_entry_from_pfn() - create a valid device entry value from pfn
+ * @range: range use to encode HMM pfn value
+ * @pfn: pfn value for which to create the device entry
+ * Return: valid device entry for the pfn
+ */
+static uint64_t hmm_device_entry_from_pfn(const struct hmm_range *range,
+ unsigned long pfn)
+{
+   return (pfn << range->pfn_shift) | range->flags[HMM_PFN_VALID];
+}
+
 static int hmm_pfns_fill(unsigned long addr, unsigned long end,
struct hmm_range *range, enum hmm_pfn_value_e value)
 {
-- 
2.25.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH hmm 2/6] mm/hmm: return the fault type from hmm_pte_need_fault()

[Jason Gunthorpe]

From: Jason Gunthorpe 

Using two bools instead of flags return is not necessary and leads to
bugs. Returning a value is easier for the compiler to check and easier to
pass around the code flow.

Convert the two bools into flags and push the change to all callers.

Signed-off-by: Jason Gunthorpe 
---
 mm/hmm.c | 153 ---
 1 file changed, 67 insertions(+), 86 deletions(-)

diff --git a/mm/hmm.c b/mm/hmm.c
index 3a2610e0713329..b4f662eadb7a7c 100644
--- a/mm/hmm.c
+++ b/mm/hmm.c
@@ -32,6 +32,11 @@ struct hmm_vma_walk {
unsigned intflags;
 };
 
+enum {
+   NEED_FAULT = 1 << 0,
+   NEED_WRITE_FAULT = 1 << 1,
+};
+
 static int hmm_pfns_fill(unsigned long addr, unsigned long end,
struct hmm_range *range, enum hmm_pfn_value_e value)
 {
@@ -49,8 +54,7 @@ static int hmm_pfns_fill(unsigned long addr, unsigned long 
end,
  * hmm_vma_fault() - fault in a range lacking valid pmd or pte(s)
  * @addr: range virtual start address (inclusive)
  * @end: range virtual end address (exclusive)
- * @fault: should we fault or not ?
- * @write_fault: write fault ?
+ * @required_fault: NEED_FAULT_* flags
  * @walk: mm_walk structure
  * Return: -EBUSY after page fault, or page fault error
  *
@@ -58,8 +62,7 @@ static int hmm_pfns_fill(unsigned long addr, unsigned long 
end,
  * or whenever there is no page directory covering the virtual address range.
  */
 static int hmm_vma_fault(unsigned long addr, unsigned long end,
- bool fault, bool write_fault,
- struct mm_walk *walk)
+unsigned int required_fault, struct mm_walk *walk)
 {
struct hmm_vma_walk *hmm_vma_walk = walk->private;
struct hmm_range *range = hmm_vma_walk->range;
@@ -68,13 +71,13 @@ static int hmm_vma_fault(unsigned long addr, unsigned long 
end,
unsigned long i = (addr - range->start) >> PAGE_SHIFT;
unsigned int fault_flags = FAULT_FLAG_REMOTE;
 
-   WARN_ON_ONCE(!fault && !write_fault);
+   WARN_ON_ONCE(!required_fault);
hmm_vma_walk->last = addr;
 
if (!vma)
goto out_error;
 
-   if (write_fault) {
+   if (required_fault & NEED_WRITE_FAULT) {
if (!(vma->vm_flags & VM_WRITE))
return -EPERM;
fault_flags |= FAULT_FLAG_WRITE;
@@ -91,14 +94,13 @@ static int hmm_vma_fault(unsigned long addr, unsigned long 
end,
return -EFAULT;
 }
 
-static inline void hmm_pte_need_fault(const struct hmm_vma_walk *hmm_vma_walk,
- uint64_t pfns, uint64_t cpu_flags,
- bool *fault, bool *write_fault)
+static unsigned int hmm_pte_need_fault(const struct hmm_vma_walk *hmm_vma_walk,
+  uint64_t pfns, uint64_t cpu_flags)
 {
struct hmm_range *range = hmm_vma_walk->range;
 
if (hmm_vma_walk->flags & HMM_FAULT_SNAPSHOT)
-   return;
+   return 0;
 
/*
 * So we not only consider the individual per page request we also
@@ -114,37 +116,37 @@ static inline void hmm_pte_need_fault(const struct 
hmm_vma_walk *hmm_vma_walk,
 
/* We aren't ask to do anything ... */
if (!(pfns & range->flags[HMM_PFN_VALID]))
-   return;
+   return 0;
 
-   /* If CPU page table is not valid then we need to fault */
-   *fault = !(cpu_flags & range->flags[HMM_PFN_VALID]);
/* Need to write fault ? */
if ((pfns & range->flags[HMM_PFN_WRITE]) &&
-   !(cpu_flags & range->flags[HMM_PFN_WRITE])) {
-   *write_fault = true;
-   *fault = true;
-   }
+   !(cpu_flags & range->flags[HMM_PFN_WRITE]))
+   return NEED_FAULT | NEED_WRITE_FAULT;
+
+   /* If CPU page table is not valid then we need to fault */
+   if (!(cpu_flags & range->flags[HMM_PFN_VALID]))
+   return NEED_FAULT;
+   return 0;
 }
 
-static void hmm_range_need_fault(const struct hmm_vma_walk *hmm_vma_walk,
-const uint64_t *pfns, unsigned long npages,
-uint64_t cpu_flags, bool *fault,
-bool *write_fault)
+static unsigned int
+hmm_range_need_fault(const struct hmm_vma_walk *hmm_vma_walk,
+const uint64_t *pfns, unsigned long npages,
+uint64_t cpu_flags)
 {
+   unsigned int required_fault = 0;
unsigned long i;
 
-   if (hmm_vma_walk->flags & HMM_FAULT_SNAPSHOT) {
-   *fault = *write_fault = false;
-   return;
-   }
+   if (hmm_vma_walk->flags & HMM_FAULT_SNAPSHOT)
+   return 0;
 
-   *fault = *write_fault = false;
for (i = 0; i < npages; ++i) {
-   hmm_pte_need_fault(hmm_vma_walk, pfns[i], cpu_flags,
-  fault, 

[PATCH hmm 0/6] Small hmm_range_fault() cleanups

[Jason Gunthorpe]

From: Jason Gunthorpe 

I've had these in my work queue for a bit, nothing profound here, just some
small edits for clarity.

Ralph's hmm tester will need a small diff to work after this - which
illustrates how setting default_flags == 0 is the same as what was called
SNAPSHOT:

diff --git a/lib/test_hmm.c b/lib/test_hmm.c
index 6ca953926dc13f..5f31f5b3e64cb9 100644
--- a/lib/test_hmm.c
+++ b/lib/test_hmm.c
@@ -300,7 +300,7 @@ static int dmirror_range_fault(struct dmirror *dmirror,
 
range->notifier_seq = mmu_interval_read_begin(range->notifier);
down_read(>mmap_sem);
-   count = hmm_range_fault(range, 0);
+   count = hmm_range_fault(range);
up_read(>mmap_sem);
if (count <= 0) {
if (count == 0 || count == -EBUSY)
@@ -337,8 +337,7 @@ static int dmirror_fault(struct dmirror *dmirror, unsigned 
long start,
.flags = dmirror_hmm_flags,
.values = dmirror_hmm_values,
.pfn_shift = DPT_SHIFT,
-   .pfn_flags_mask = ~(dmirror_hmm_flags[HMM_PFN_VALID] |
-   dmirror_hmm_flags[HMM_PFN_WRITE]),
+   .pfn_flags_mask = 0,
.default_flags = dmirror_hmm_flags[HMM_PFN_VALID] |
(write ? dmirror_hmm_flags[HMM_PFN_WRITE] : 0),
.dev_private_owner = dmirror->mdevice,
@@ -872,7 +871,7 @@ static int dmirror_range_snapshot(struct dmirror *dmirror,
range->notifier_seq = mmu_interval_read_begin(range->notifier);
 
down_read(>mmap_sem);
-   count = hmm_range_fault(range, HMM_FAULT_SNAPSHOT);
+   count = hmm_range_fault(range);
up_read(>mmap_sem);
if (count <= 0) {
if (count == 0 || count == -EBUSY)
@@ -916,7 +915,7 @@ static int dmirror_snapshot(struct dmirror *dmirror,
.flags = dmirror_hmm_flags,
.values = dmirror_hmm_values,
.pfn_shift = DPT_SHIFT,
-   .pfn_flags_mask = ~0ULL,
+   .pfn_flags_mask = 0,
.dev_private_owner = dmirror->mdevice,
};
int ret = 0;

Jason Gunthorpe (6):
  mm/hmm: remove pgmap checking for devmap pages
  mm/hmm: return the fault type from hmm_pte_need_fault()
  mm/hmm: remove unused code and tidy comments
  mm/hmm: remove HMM_FAULT_SNAPSHOT
  mm/hmm: remove the CONFIG_TRANSPARENT_HUGEPAGE #ifdef
  mm/hmm: use device_private_entry_to_pfn()

 Documentation/vm/hmm.rst|  12 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c |   2 +-
 drivers/gpu/drm/nouveau/nouveau_svm.c   |   2 +-
 include/linux/hmm.h |  55 +-
 mm/hmm.c| 238 +---
 5 files changed, 98 insertions(+), 211 deletions(-)

-- 
2.25.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: amdgpu kernel oops?

[Tristan Vroom]

Yes, it worked.

Thanks!

Tristan

On Wed, Mar 18, 2020 at 9:53 AM Alex Deucher  wrote:

> On Tue, Mar 17, 2020 at 6:24 PM Tristan Vroom 
> wrote:
> >
> > I don't have a lot of experience reading kernel logs, so I apologize if
> I misread something, but it seems like I'm having some trouble with amdgpu
> in kernel 5.5.9.
> >
> > Here's the gist of the bug.
>
> Does this patch fix the issue?
>
> https://cgit.freedesktop.org/~agd5f/linux/commit/?h=drm-next=6c62ce8073daf27ae3fd03b6929d6cea3887eeb2
>
> Alex
>
> >
> > Thank you for your help.
> >
> > Tristan
> > ___
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

RE: [PATCH 1/6] drm/amdgpu: ih doorbell size of range changed for nbio v7.4

[Sierra Guiza, Alejandro (Alex)]

[AMD Official Use Only - Internal Distribution Only]

My bad, please ignore this.
I re-sent this in a separate one patch.

Alejandro S

-Original Message-
From: Kuehling, Felix  
Sent: Friday, March 20, 2020 9:37 AM
To: Sierra Guiza, Alejandro (Alex) ; 
amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/6] drm/amdgpu: ih doorbell size of range changed for nbio 
v7.4

On 2020-03-19 20:24, Alex Sierra wrote:
> [Why]
> nbio v7.4 size of ih doorbell range is 64 bit. This requires 2 DWords per 
> register.
>
> [How]
> Change ih doorbell size from 2 to 4. This means two Dwords per ring.
> Current configuration uses two ih rings.
>
> Signed-off-by: Alex Sierra 

Why is the subject "PATCH 1/6"? It makes me wonder, what are the other 5 
patches. Anyway, this patch is

Reviewed-by: Felix Kuehling 


> ---
>   drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c 
> b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
> index 149d386590df..263dbb1f92ee 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
> @@ -185,7 +185,7 @@ static void nbio_v7_4_ih_doorbell_range(struct 
> amdgpu_device *adev,
>   
>   if (use_doorbell) {
>   ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 
> BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index);
> - ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 
> BIF_IH_DOORBELL_RANGE, SIZE, 2);
> + ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 
> +BIF_IH_DOORBELL_RANGE, SIZE, 4);
>   } else
>   ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 
> BIF_IH_DOORBELL_RANGE, SIZE, 0);
>   
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 09/12] drm/amd/display: LFC not working on 2.0x range monitors

[Rodrigo Siqueira]

From: Aric Cyr 

[Why]
Nominal pixel clock and EDID information differ in precision so although
monitor reports maximum refresh is 2x minimum, LFC was not being
enabled.

[How]
Use minimum refresh rate as nominal/2 when EDID dictates that min
refresh = max refresh/2.

Signed-off-by: Aric Cyr 
Reviewed-by: Nicholas Kazlauskas 
Acked-by: Rodrigo Siqueira 
---
 .../amd/display/modules/freesync/freesync.c   | 34 +++
 1 file changed, 19 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c 
b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
index 4e542826cd26..8911f01671aa 100644
--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
@@ -734,6 +734,7 @@ void mod_freesync_build_vrr_params(struct mod_freesync 
*mod_freesync,
 {
struct core_freesync *core_freesync = NULL;
unsigned long long nominal_field_rate_in_uhz = 0;
+   unsigned long long rounded_nominal_in_uhz = 0;
unsigned int refresh_range = 0;
unsigned long long min_refresh_in_uhz = 0;
unsigned long long max_refresh_in_uhz = 0;
@@ -750,17 +751,20 @@ void mod_freesync_build_vrr_params(struct mod_freesync 
*mod_freesync,
min_refresh_in_uhz = in_config->min_refresh_in_uhz;
max_refresh_in_uhz = in_config->max_refresh_in_uhz;
 
-   // Don't allow min > max
-   if (min_refresh_in_uhz > max_refresh_in_uhz)
-   min_refresh_in_uhz = max_refresh_in_uhz;
-
// Full range may be larger than current video timing, so cap at nominal
if (max_refresh_in_uhz > nominal_field_rate_in_uhz)
max_refresh_in_uhz = nominal_field_rate_in_uhz;
 
// Full range may be larger than current video timing, so cap at nominal
-   if (min_refresh_in_uhz > nominal_field_rate_in_uhz)
-   min_refresh_in_uhz = nominal_field_rate_in_uhz;
+   if (min_refresh_in_uhz > max_refresh_in_uhz)
+   min_refresh_in_uhz = max_refresh_in_uhz;
+
+   // If a monitor reports exactly max refresh of 2x of min, enforce it on 
nominal
+   rounded_nominal_in_uhz =
+   ((nominal_field_rate_in_uhz + 5) / 10) * 10;
+   if (in_config->max_refresh_in_uhz == (2 * 
in_config->min_refresh_in_uhz) &&
+   in_config->max_refresh_in_uhz == rounded_nominal_in_uhz)
+   min_refresh_in_uhz = nominal_field_rate_in_uhz / 2;
 
if (!vrr_settings_require_update(core_freesync,
in_config, (unsigned int)min_refresh_in_uhz, (unsigned 
int)max_refresh_in_uhz,
@@ -792,11 +796,6 @@ void mod_freesync_build_vrr_params(struct mod_freesync 
*mod_freesync,
refresh_range = in_out_vrr->max_refresh_in_uhz -
in_out_vrr->min_refresh_in_uhz;
 
-   in_out_vrr->btr.margin_in_us = in_out_vrr->max_duration_in_us -
-   2 * in_out_vrr->min_duration_in_us;
-   if (in_out_vrr->btr.margin_in_us > BTR_MAX_MARGIN)
-   in_out_vrr->btr.margin_in_us = BTR_MAX_MARGIN;
-
in_out_vrr->supported = true;
}
 
@@ -804,9 +803,14 @@ void mod_freesync_build_vrr_params(struct mod_freesync 
*mod_freesync,
 
in_out_vrr->btr.btr_enabled = in_config->btr;
 
-   if (in_out_vrr->max_refresh_in_uhz <
-   2 * in_out_vrr->min_refresh_in_uhz)
+   if (in_out_vrr->max_refresh_in_uhz < (2 * 
in_out_vrr->min_refresh_in_uhz))
in_out_vrr->btr.btr_enabled = false;
+   else {
+   in_out_vrr->btr.margin_in_us = in_out_vrr->max_duration_in_us -
+   2 * in_out_vrr->min_duration_in_us;
+   if (in_out_vrr->btr.margin_in_us > BTR_MAX_MARGIN)
+   in_out_vrr->btr.margin_in_us = BTR_MAX_MARGIN;
+   }
 
in_out_vrr->btr.btr_active = false;
in_out_vrr->btr.inserted_duration_in_us = 0;
@@ -1008,8 +1012,8 @@ unsigned long long mod_freesync_calc_nominal_field_rate(
unsigned int total = stream->timing.h_total * stream->timing.v_total;
 
/* Calculate nominal field rate for stream, rounded up to nearest 
integer */
-   nominal_field_rate_in_uhz = stream->timing.pix_clk_100hz / 10;
-   nominal_field_rate_in_uhz *= 1000ULL * 1000ULL * 1000ULL;
+   nominal_field_rate_in_uhz = stream->timing.pix_clk_100hz;
+   nominal_field_rate_in_uhz *= 1ULL;
 
nominal_field_rate_in_uhz = div_u64(nominal_field_rate_in_uhz, 
total);
 
-- 
2.25.2

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 08/12] drm/amd/display: Support plane level CTM

[Rodrigo Siqueira]

From: Stylon Wang 

[Why]
CTM was only supported at CRTC level and we need color space conversion
in linear space at plane level.

[How]
- Add plane-level CTM to dc interface
- Program plane-level CTM in DCN

Signed-off-by: Stylon Wang 
Reviewed-by: Nicholas Kazlauskas 
Acked-by: Rodrigo Siqueira 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c   | 10 +-
 drivers/gpu/drm/amd/display/dc/dc.h|  3 +++
 .../gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  |  6 ++
 3 files changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 1a2c2e3dd6d2..f21bbb295ad3 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1726,6 +1726,9 @@ static enum surface_update_type det_surface_update(const 
struct dc *dc,
if (u->coeff_reduction_factor)
update_flags->bits.coeff_reduction_change = 1;
 
+   if (u->gamut_remap_matrix)
+   update_flags->bits.gamut_remap_change = 1;
+
if (u->gamma) {
enum surface_pixel_format format = 
SURFACE_PIXEL_FORMAT_GRPH_BEGIN;
 
@@ -1751,7 +1754,8 @@ static enum surface_update_type det_surface_update(const 
struct dc *dc,
 
if (update_flags->bits.input_csc_change
|| update_flags->bits.coeff_reduction_change
-   || update_flags->bits.gamma_change) {
+   || update_flags->bits.gamma_change
+   || update_flags->bits.gamut_remap_change) {
type = UPDATE_TYPE_FULL;
elevate_update_type(_type, type);
}
@@ -1996,6 +2000,10 @@ static void copy_surface_update_to_plane(
if (srf_update->coeff_reduction_factor)
surface->coeff_reduction_factor =
*srf_update->coeff_reduction_factor;
+
+   if (srf_update->gamut_remap_matrix)
+   surface->gamut_remap_matrix =
+   *srf_update->gamut_remap_matrix;
 }
 
 static void copy_stream_update_to_stream(struct dc *dc,
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 52c7c06d1fde..92123b0d1196 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -726,6 +726,7 @@ union surface_update_flags {
uint32_t output_tf_change:1;
uint32_t pixel_format_change:1;
uint32_t plane_size_change:1;
+   uint32_t gamut_remap_change:1;
 
/* Full updates */
uint32_t new_plane:1;
@@ -760,6 +761,7 @@ struct dc_plane_state {
struct dc_csc_transform input_csc_color_matrix;
struct fixed31_32 coeff_reduction_factor;
struct fixed31_32 hdr_mult;
+   struct colorspace_transform gamut_remap_matrix;
 
// TODO: No longer used, remove
struct dc_hdr_static_metadata hdr_static_ctx;
@@ -839,6 +841,7 @@ struct dc_surface_update {
const struct dc_transfer_func *func_shaper;
const struct dc_3dlut *lut3d_func;
const struct dc_transfer_func *blend_tf;
+   const struct colorspace_transform *gamut_remap_matrix;
 };
 
 /*
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 9cc3314966bd..0be010085575 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2004,6 +2004,12 @@ void dcn10_program_gamut_remap(struct pipe_ctx *pipe_ctx)
for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
adjust.temperature_matrix[i] =
pipe_ctx->stream->gamut_remap_matrix.matrix[i];
+   } else if (pipe_ctx->plane_state &&
+  pipe_ctx->plane_state->gamut_remap_matrix.enable_remap == 
true) {
+   adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
+   for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
+   adjust.temperature_matrix[i] =
+   
pipe_ctx->plane_state->gamut_remap_matrix.matrix[i];
}
 

pipe_ctx->plane_res.dpp->funcs->dpp_set_gamut_remap(pipe_ctx->plane_res.dpp, 
);
-- 
2.25.2

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 06/12] drm/amd/display: Not doing optimize bandwidth if flip pending.

[Rodrigo Siqueira]

From: Yongqiang Sun 

[Why]
In some scenario like 1366x768 VSR enabled connected with a 4K monitor
and playing 4K video in clone mode, underflow will be observed due to
decrease dppclk when previouse surface scan isn't finished

[How]
In this use case, surface flip is switching between 4K and 1366x768,
1366x768 needs smaller dppclk, and when decrease the clk and previous
surface scan is for 4K and scan isn't done, underflow will happen.  Not
doing optimize bandwidth in case of flip pending.

Signed-off-by: Yongqiang Sun 
Reviewed-by: Tony Cheng 
Acked-by: Rodrigo Siqueira 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 23 +++
 1 file changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 2ffb22177df9..1a2c2e3dd6d2 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1360,6 +1360,26 @@ bool dc_commit_state(struct dc *dc, struct dc_state 
*context)
return (result == DC_OK);
 }
 
+static bool is_flip_pending_in_pipes(struct dc *dc, struct dc_state *context)
+{
+   int i;
+   struct pipe_ctx *pipe;
+
+   for (i = 0; i < MAX_PIPES; i++) {
+   pipe = >res_ctx.pipe_ctx[i];
+
+   if (!pipe->plane_state)
+   continue;
+
+   /* Must set to false to start with, due to OR in update 
function */
+   pipe->plane_state->status.is_flip_pending = false;
+   dc->hwss.update_pending_status(pipe);
+   if (pipe->plane_state->status.is_flip_pending)
+   return true;
+   }
+   return false;
+}
+
 bool dc_post_update_surfaces_to_stream(struct dc *dc)
 {
int i;
@@ -1370,6 +1390,9 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc)
 
post_surface_trace(dc);
 
+   if (is_flip_pending_in_pipes(dc, context))
+   return true;
+
for (i = 0; i < dc->res_pool->pipe_count; i++)
if (context->res_ctx.pipe_ctx[i].stream == NULL ||
context->res_ctx.pipe_ctx[i].plane_state == NULL) {
-- 
2.25.2

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 07/12] drm/amd/display: Revert change to HDCP display states

[Rodrigo Siqueira]

From: Isabel Zhang 

[Why]
Change is causing a regression where the OPC app no longer functions
properly.

[How]
Revert the changelist causing the issue.

Signed-off-by: Isabel Zhang 
Reviewed-by: Yongqiang Sun 
Acked-by: Rodrigo Siqueira 
---
 .../gpu/drm/amd/display/modules/hdcp/hdcp.c   |  5 +--
 .../gpu/drm/amd/display/modules/hdcp/hdcp.h   | 28 ++---
 .../display/modules/hdcp/hdcp1_execution.c|  2 +-
 .../display/modules/hdcp/hdcp2_execution.c|  2 +-
 .../drm/amd/display/modules/hdcp/hdcp_psp.c   | 39 +++
 .../drm/amd/display/modules/inc/mod_hdcp.h|  1 +
 6 files changed, 49 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c 
b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
index e9fbd94f8635..cc1d3f470b99 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
@@ -328,8 +328,7 @@ enum mod_hdcp_status mod_hdcp_add_display(struct mod_hdcp 
*hdcp,
/* add display to connection */
hdcp->connection.link = *link;
*display_container = *display;
-   status = mod_hdcp_add_display_to_topology(hdcp, display_container);
-
+   status = mod_hdcp_add_display_to_topology(hdcp, display->index);
if (status != MOD_HDCP_STATUS_SUCCESS)
goto out;
 
@@ -375,7 +374,7 @@ enum mod_hdcp_status mod_hdcp_remove_display(struct 
mod_hdcp *hdcp,
status = mod_hdcp_remove_display_from_topology(hdcp, index);
if (status != MOD_HDCP_STATUS_SUCCESS)
goto out;
-   memset(display, 0, sizeof(struct mod_hdcp_display));
+   display->state = MOD_HDCP_DISPLAY_INACTIVE;
 
/* request authentication when connection is not reset */
if (current_state(hdcp) != HDCP_UNINITIALIZED)
diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h 
b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
index 60ff1a0028ac..5cb4546be0ef 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
@@ -328,7 +328,7 @@ void mod_hdcp_dump_binary_message(uint8_t *msg, uint32_t 
msg_size,
 
 /* psp functions */
 enum mod_hdcp_status mod_hdcp_add_display_to_topology(
-   struct mod_hdcp *hdcp, struct mod_hdcp_display *display);
+   struct mod_hdcp *hdcp, uint8_t index);
 enum mod_hdcp_status mod_hdcp_remove_display_from_topology(
struct mod_hdcp *hdcp, uint8_t index);
 enum mod_hdcp_status mod_hdcp_hdcp1_create_session(struct mod_hdcp *hdcp);
@@ -503,6 +503,11 @@ static inline uint8_t is_display_active(struct 
mod_hdcp_display *display)
return display->state >= MOD_HDCP_DISPLAY_ACTIVE;
 }
 
+static inline uint8_t is_display_added(struct mod_hdcp_display *display)
+{
+   return display->state >= MOD_HDCP_DISPLAY_ACTIVE_AND_ADDED;
+}
+
 static inline uint8_t is_display_encryption_enabled(struct mod_hdcp_display 
*display)
 {
return display->state >= MOD_HDCP_DISPLAY_ENCRYPTION_ENABLED;
@@ -510,23 +515,34 @@ static inline uint8_t 
is_display_encryption_enabled(struct mod_hdcp_display *dis
 
 static inline uint8_t get_active_display_count(struct mod_hdcp *hdcp)
 {
-   uint8_t active_count = 0;
+   uint8_t added_count = 0;
uint8_t i;
 
for (i = 0; i < MAX_NUM_OF_DISPLAYS; i++)
if (is_display_active(>displays[i]))
-   active_count++;
-   return active_count;
+   added_count++;
+   return added_count;
+}
+
+static inline uint8_t get_added_display_count(struct mod_hdcp *hdcp)
+{
+   uint8_t added_count = 0;
+   uint8_t i;
+
+   for (i = 0; i < MAX_NUM_OF_DISPLAYS; i++)
+   if (is_display_added(>displays[i]))
+   added_count++;
+   return added_count;
 }
 
-static inline struct mod_hdcp_display *get_first_active_display(
+static inline struct mod_hdcp_display *get_first_added_display(
struct mod_hdcp *hdcp)
 {
uint8_t i;
struct mod_hdcp_display *display = NULL;
 
for (i = 0; i < MAX_NUM_OF_DISPLAYS; i++)
-   if (is_display_active(>displays[i])) {
+   if (is_display_added(>displays[i])) {
display = >displays[i];
break;
}
diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c 
b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c
index f244b72e74e0..37c8c05497d6 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c
@@ -129,7 +129,7 @@ static inline uint8_t get_device_count(struct mod_hdcp 
*hdcp)
 static inline enum mod_hdcp_status check_device_count(struct mod_hdcp *hdcp)
 {
/* device count must be greater than or equal to tracked hdcp displays 
*/
-   return (get_device_count(hdcp) < get_active_display_count(hdcp)) ?
+   return 

[PATCH 01/12] drm/amd/display: 3.2.77

[Rodrigo Siqueira]

From: Aric Cyr 

Signed-off-by: Aric Cyr 
Reviewed-by: Aric Cyr 
Acked-by: Rodrigo Siqueira 
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index d3ceb39e428e..52c7c06d1fde 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -39,7 +39,7 @@
 #include "inc/hw/dmcu.h"
 #include "dml/display_mode_lib.h"
 
-#define DC_VER "3.2.76"
+#define DC_VER "3.2.77"
 
 #define MAX_SURFACES 3
 #define MAX_PLANES 6
-- 
2.25.2

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 00/12] DC Patches March 23th, 2020

[Rodrigo Siqueira]

This DC patchset brings improvements in multiple areas. In summary, we
highlight:
 
* Rework part of the backlight function call;
* Support plane level CTM, and P010 pixel format;
* Get optimal number of taps;

Aric Cyr (2):
  drm/amd/display: 3.2.77
  drm/amd/display: LFC not working on 2.0x range monitors

Dmytro Laktyushkin (1):
  drm/amd/display: Fix dcn21 num_states

Eric Bernstein (1):
  drm/amd/display: Update function to get optimal number of taps

Isabel Zhang (1):
  drm/amd/display: Revert change to HDCP display states

Nicholas Kazlauskas (1):
  drm/amd/display: Use double buffered DRR timing update by default

Stylon Wang (3):
  drm/amd/display: Support P010 pixel format
  drm/amd/display: Support plane level CTM
  drm/amd/display: Enable BT2020 in COLOR_ENCODING property

Wyatt Wood (2):
  drm/amd/display: Add ABM driver implementation
  drm/amd/display: Move backlight pwm enable function call

Yongqiang Sun (1):
  drm/amd/display: Not doing optimize bandwidth if flip pending.

 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  12 +-
 drivers/gpu/drm/amd/display/dc/core/dc.c  |  33 +-
 .../gpu/drm/amd/display/dc/core/dc_resource.c |   1 +
 drivers/gpu/drm/amd/display/dc/dc.h   |   5 +-
 drivers/gpu/drm/amd/display/dc/dce/Makefile   |   2 +-
 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c  |   1 +
 drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c | 417 ++
 drivers/gpu/drm/amd/display/dc/dce/dmub_abm.h |  40 ++
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c |   6 +
 .../gpu/drm/amd/display/dc/dcn10/dcn10_optc.c |  18 +
 .../gpu/drm/amd/display/dc/dcn10/dcn10_optc.h |   3 +
 .../drm/amd/display/dc/dcn10/dcn10_resource.c |   3 +-
 .../drm/amd/display/dc/dcn20/dcn20_resource.c |   5 +-
 .../drm/amd/display/dc/dcn21/dcn21_resource.c |  81 ++--
 .../gpu/drm/amd/display/dc/dml/dc_features.h  |   2 +-
 .../amd/display/dc/dml/display_mode_structs.h |   7 +-
 drivers/gpu/drm/amd/display/dc/inc/hw/abm.h   |   4 +
 .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h   |  11 +
 .../amd/display/modules/freesync/freesync.c   |  34 +-
 .../gpu/drm/amd/display/modules/hdcp/hdcp.c   |   5 +-
 .../gpu/drm/amd/display/modules/hdcp/hdcp.h   |  28 +-
 .../display/modules/hdcp/hdcp1_execution.c|   2 +-
 .../display/modules/hdcp/hdcp2_execution.c|   2 +-
 .../drm/amd/display/modules/hdcp/hdcp_psp.c   |  39 +-
 .../drm/amd/display/modules/inc/mod_hdcp.h|   1 +
 .../amd/display/modules/power/power_helpers.c |  21 +-
 26 files changed, 680 insertions(+), 103 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/dce/dmub_abm.h

-- 
2.25.2

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 05/12] drm/amd/display: Use double buffered DRR timing update by default

[Rodrigo Siqueira]

From: Nicholas Kazlauskas 

[Why]
For some monitors extreme flickering can occur while using LFC for if
we're not doing the DRR timing update for V_TOTAL_MIN / V_TOTAL_MAX at
the DP start of frame.

Hardware can default to any time in the frame which isn't the behavior
we want.

[How]
Add a new function for setting the double buffering mode for DRR timing.

Default to DP start of frame double buffering on timing generator init.

Signed-off-by: Nicholas Kazlauskas 
Reviewed-by: Aric Cyr 
Acked-by: Rodrigo Siqueira 
---
 .../gpu/drm/amd/display/dc/dcn10/dcn10_optc.c  | 18 ++
 .../gpu/drm/amd/display/dc/dcn10/dcn10_optc.h  |  3 +++
 2 files changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
index 63acb8ff7462..17d96ec6acd8 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
@@ -342,6 +342,23 @@ void optc1_set_blank_data_double_buffer(struct 
timing_generator *optc, bool enab
OTG_BLANK_DATA_DOUBLE_BUFFER_EN, 
blank_data_double_buffer_enable);
 }
 
+/**
+ * optc1_set_timing_double_buffer() - DRR double buffering control
+ *
+ * Sets double buffer point for V_TOTAL, H_TOTAL, VTOTAL_MIN,
+ * VTOTAL_MAX, VTOTAL_MIN_SEL and VTOTAL_MAX_SEL registers.
+ *
+ * Options: any time,  start of frame, dp start of frame (range timing)
+ */
+void optc1_set_timing_double_buffer(struct timing_generator *optc, bool enable)
+{
+   struct optc *optc1 = DCN10TG_FROM_TG(optc);
+   uint32_t mode = enable ? 2 : 0;
+
+   REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL,
+  OTG_RANGE_TIMING_DBUF_UPDATE_MODE, mode);
+}
+
 /**
  * unblank_crtc
  * Call ASIC Control Object to UnBlank CRTC.
@@ -1353,6 +1370,7 @@ void optc1_clear_optc_underflow(struct timing_generator 
*optc)
 void optc1_tg_init(struct timing_generator *optc)
 {
optc1_set_blank_data_double_buffer(optc, true);
+   optc1_set_timing_double_buffer(optc, true);
optc1_clear_optc_underflow(optc);
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
index f277656d5464..9a459a8fe8a0 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
@@ -185,6 +185,7 @@ struct dcn_optc_registers {
SF(OTG0_OTG_GLOBAL_CONTROL0, OTG_MASTER_UPDATE_LOCK_SEL, mask_sh),\
SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_UPDATE_PENDING, mask_sh),\
SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_BLANK_DATA_DOUBLE_BUFFER_EN, 
mask_sh),\
+   SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_RANGE_TIMING_DBUF_UPDATE_MODE, 
mask_sh),\
SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\
SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_START, mask_sh),\
SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_END, mask_sh),\
@@ -643,6 +644,8 @@ bool optc1_is_optc_underflow_occurred(struct 
timing_generator *optc);
 
 void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool 
enable);
 
+void optc1_set_timing_double_buffer(struct timing_generator *optc, bool 
enable);
+
 bool optc1_get_otg_active_size(struct timing_generator *optc,
uint32_t *otg_active_width,
uint32_t *otg_active_height);
-- 
2.25.2

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 10/12] drm/amd/display: Move backlight pwm enable function call

[Rodrigo Siqueira]

From: Wyatt Wood 

[Why]
Can't call dmub_abm_enable_fractional_pwm from dmub_abm_create as
dmub_srv is still null at this init stage, and therefore can't call to
fw.

[How]
Move call to dmub_abm_init_backlight. This should be the first call from
the driver for ABM.

Signed-off-by: Wyatt Wood 
Reviewed-by: Nicholas Kazlauskas 
Acked-by: Rodrigo Siqueira 
---
 drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c | 34 +--
 1 file changed, 17 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c 
b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
index 1d9100f8c0ba..81c967917c5b 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
@@ -257,11 +257,28 @@ static bool dmub_abm_immediate_disable(struct abm *abm)
return true;
 }
 
+static void dmub_abm_enable_fractional_pwm(struct dc_context *dc)
+{
+   union dmub_rb_cmd cmd;
+   uint32_t fractional_pwm = (dc->dc->config.disable_fractional_pwm == 
false) ? 1 : 0;
+
+   cmd.abm_set_pwm_frac.header.type = DMUB_CMD__ABM;
+   cmd.abm_set_pwm_frac.header.sub_type = DMUB_CMD__ABM_SET_PWM_FRAC;
+   cmd.abm_set_pwm_frac.abm_set_pwm_frac_data.fractional_pwm = 
fractional_pwm;
+   cmd.abm_set_pwm_frac.header.payload_bytes = sizeof(struct 
dmub_cmd_abm_set_pwm_frac_data);
+
+   dc_dmub_srv_cmd_queue(dc->dmub_srv, _set_pwm_frac.header);
+   dc_dmub_srv_cmd_execute(dc->dmub_srv);
+   dc_dmub_srv_wait_idle(dc->dmub_srv);
+}
+
 static bool dmub_abm_init_backlight(struct abm *abm)
 {
struct dce_abm *dce_abm = TO_DMUB_ABM(abm);
uint32_t value;
 
+   dmub_abm_enable_fractional_pwm(abm->ctx);
+
/* It must not be 0, so we have to restore them
 * Bios bug w/a - period resets to zero,
 * restoring to cache values which is always correct
@@ -331,21 +348,6 @@ static bool dmub_abm_set_backlight_level_pwm(
return true;
 }
 
-static void dmub_abm_enable_fractional_pwm(struct dc_context *dc)
-{
-   union dmub_rb_cmd cmd;
-   uint32_t fractional_pwm = (dc->dc->config.disable_fractional_pwm == 
false) ? 1 : 0;
-
-   cmd.abm_set_pwm_frac.header.type = DMUB_CMD__ABM;
-   cmd.abm_set_pwm_frac.header.sub_type = DMUB_CMD__ABM_SET_PWM_FRAC;
-   cmd.abm_set_pwm_frac.abm_set_pwm_frac_data.fractional_pwm = 
fractional_pwm;
-   cmd.abm_set_pwm_frac.header.payload_bytes = sizeof(struct 
dmub_cmd_abm_set_pwm_frac_data);
-
-   dc_dmub_srv_cmd_queue(dc->dmub_srv, _set_pwm_frac.header);
-   dc_dmub_srv_cmd_execute(dc->dmub_srv);
-   dc_dmub_srv_wait_idle(dc->dmub_srv);
-}
-
 static bool dmub_abm_load_config(struct abm *abm,
unsigned int start_offset,
const char *src,
@@ -386,8 +388,6 @@ static void dmub_abm_construct(
abm_dce->regs = regs;
abm_dce->abm_shift = abm_shift;
abm_dce->abm_mask = abm_mask;
-
-   dmub_abm_enable_fractional_pwm(ctx);
 }
 
 struct abm *dmub_abm_create(
-- 
2.25.2

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 03/12] drm/amd/display: Support P010 pixel format

[Rodrigo Siqueira]

From: Stylon Wang 

[Why]
P010 pixel format is not declared as supported in DRM and DM.

[How]
Add P010 format to the support list presented to DRM and checked in DM

Signed-off-by: Stylon Wang 
Reviewed-by: Nicholas Kazlauskas 
Acked-by: Rodrigo Siqueira 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 +
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 3 ++-
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 3 ++-
 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 3 ++-
 4 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 36794f7c6232..32d946fa7d89 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -3706,6 +3706,9 @@ fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
case DRM_FORMAT_NV12:
plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
break;
+   case DRM_FORMAT_P010:
+   plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb;
+   break;
default:
DRM_ERROR(
"Unsupported screen format %s\n",
@@ -5617,6 +5620,8 @@ static int get_plane_formats(const struct drm_plane 
*plane,
 
if (plane_cap && plane_cap->pixel_format_support.nv12)
formats[num_formats++] = DRM_FORMAT_NV12;
+   if (plane_cap && plane_cap->pixel_format_support.p010)
+   formats[num_formats++] = DRM_FORMAT_P010;
break;
 
case DRM_PLANE_TYPE_OVERLAY:
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index 261bdc3a8218..8b7122249ddc 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -552,7 +552,8 @@ static const struct dc_plane_cap plane_cap = {
.pixel_format_support = {
.argb = true,
.nv12 = true,
-   .fp16 = true
+   .fp16 = true,
+   .p010 = true
},
 
.max_upscale_factor = {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index a67395208991..54e096055c6f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -1012,7 +1012,8 @@ static const struct dc_plane_cap plane_cap = {
.pixel_format_support = {
.argb = true,
.nv12 = true,
-   .fp16 = true
+   .fp16 = true,
+   .p010 = true
},
 
.max_upscale_factor = {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index 51b5910cd05f..deda1a6b603b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -838,7 +838,8 @@ static const struct dc_plane_cap plane_cap = {
.pixel_format_support = {
.argb = true,
.nv12 = true,
-   .fp16 = true
+   .fp16 = true,
+   .p010 = true
},
 
.max_upscale_factor = {
-- 
2.25.2

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 04/12] drm/amd/display: Add ABM driver implementation

[Rodrigo Siqueira]

From: Wyatt Wood 

[Why]
Moving ABM from DMCU to DMCUB.

[How]
Add ABM driver files and implementation.

Signed-off-by: Wyatt Wood 
Reviewed-by: Nicholas Kazlauskas 
Acked-by: Rodrigo Siqueira 
---
 drivers/gpu/drm/amd/display/dc/dce/Makefile   |   2 +-
 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c  |   1 +
 drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c | 417 ++
 drivers/gpu/drm/amd/display/dc/dce/dmub_abm.h |  40 ++
 .../drm/amd/display/dc/dcn21/dcn21_resource.c |  41 +-
 drivers/gpu/drm/amd/display/dc/inc/hw/abm.h   |   4 +
 .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h   |  11 +
 .../amd/display/modules/power/power_helpers.c |  21 +-
 8 files changed, 514 insertions(+), 23 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/dce/dmub_abm.h

diff --git a/drivers/gpu/drm/amd/display/dc/dce/Makefile 
b/drivers/gpu/drm/amd/display/dc/dce/Makefile
index fbfcff700971..b31a1b71dab0 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dce/Makefile
@@ -29,7 +29,7 @@
 DCE = dce_audio.o dce_stream_encoder.o dce_link_encoder.o dce_hwseq.o \
 dce_mem_input.o dce_clock_source.o dce_scl_filters.o dce_transform.o \
 dce_opp.o dce_dmcu.o dce_abm.o dce_ipp.o dce_aux.o \
-dce_i2c.o dce_i2c_hw.o dce_i2c_sw.o dmub_psr.o
+dce_i2c.o dce_i2c_hw.o dce_i2c_sw.o dmub_psr.o dmub_abm.o
 
 AMD_DAL_DCE = $(addprefix $(AMDDALPATH)/dc/dce/,$(DCE))
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
index b8a3fc505c9b..a4dae31400fa 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
@@ -447,6 +447,7 @@ static const struct abm_funcs dce_funcs = {
.set_backlight_level_pwm = dce_abm_set_backlight_level_pwm,
.get_current_backlight = dce_abm_get_current_backlight,
.get_target_backlight = dce_abm_get_target_backlight,
+   .load_abm_config = NULL,
.set_abm_immediate_disable = dce_abm_immediate_disable
 };
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c 
b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
new file mode 100644
index ..1d9100f8c0ba
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
@@ -0,0 +1,417 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dmub_abm.h"
+#include "dce_abm.h"
+#include "dc.h"
+#include "dc_dmub_srv.h"
+#include "../../dmub/inc/dmub_srv.h"
+#include "core_types.h"
+#include "dm_services.h"
+#include "reg_helper.h"
+#include "fixed31_32.h"
+
+#include "atom.h"
+
+#define TO_DMUB_ABM(abm)\
+   container_of(abm, struct dce_abm, base)
+
+#define REG(reg) \
+   (dce_abm->regs->reg)
+
+#undef FN
+#define FN(reg_name, field_name) \
+   dce_abm->abm_shift->field_name, dce_abm->abm_mask->field_name
+
+#define CTX \
+   dce_abm->base.ctx
+
+#define DISABLE_ABM_IMMEDIATELY 255
+
+static bool dmub_abm_set_pipe(struct abm *abm, uint32_t otg_inst)
+{
+   union dmub_rb_cmd cmd;
+   struct dc_context *dc = abm->ctx;
+   uint32_t ramping_boundary = 0x;
+
+   cmd.abm_set_pipe.header.type = DMUB_CMD__ABM;
+   cmd.abm_set_pipe.header.sub_type = DMUB_CMD__ABM_SET_PIPE;
+   cmd.abm_set_pipe.abm_set_pipe_data.otg_inst = otg_inst;
+   cmd.abm_set_pipe.abm_set_pipe_data.ramping_boundary = ramping_boundary;
+   cmd.abm_set_pipe.header.payload_bytes = sizeof(struct 
dmub_cmd_abm_set_pipe_data);
+
+   dc_dmub_srv_cmd_queue(dc->dmub_srv, _set_pipe.header);
+   dc_dmub_srv_cmd_execute(dc->dmub_srv);
+   dc_dmub_srv_wait_idle(dc->dmub_srv);
+
+   return true;
+}
+
+static unsigned int calculate_16_bit_backlight_from_pwm(struct dce_abm 
*dce_abm)
+{
+   uint64_t current_backlight;
+   uint32_t round_result;
+   uint32_t 

[PATCH 11/12] drm/amd/display: Enable BT2020 in COLOR_ENCODING property

[Rodrigo Siqueira]

From: Stylon Wang 

[Why]
BT2020 is not supported in COLOR_ENCODING property of planes.  Only
BT601 and BT709 was available.

[How]
Allow BT2020 as legit value in setting COLOR_ENCODING property.

Signed-off-by: Stylon Wang 
Reviewed-by: Nicholas Kazlauskas 
Acked-by: Rodrigo Siqueira 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 32d946fa7d89..4f58810e770f 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -5674,12 +5674,15 @@ static int amdgpu_dm_plane_init(struct 
amdgpu_display_manager *dm,
}
 
if (plane->type == DRM_PLANE_TYPE_PRIMARY &&
-   plane_cap && plane_cap->pixel_format_support.nv12) {
+   plane_cap &&
+   (plane_cap->pixel_format_support.nv12 ||
+plane_cap->pixel_format_support.p010)) {
/* This only affects YUV formats. */
drm_plane_create_color_properties(
plane,
BIT(DRM_COLOR_YCBCR_BT601) |
-   BIT(DRM_COLOR_YCBCR_BT709),
+   BIT(DRM_COLOR_YCBCR_BT709) |
+   BIT(DRM_COLOR_YCBCR_BT2020),
BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
BIT(DRM_COLOR_YCBCR_FULL_RANGE),
DRM_COLOR_YCBCR_BT709, DRM_COLOR_YCBCR_LIMITED_RANGE);
-- 
2.25.2

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 02/12] drm/amd/display: Update function to get optimal number of taps

[Rodrigo Siqueira]

From: Eric Bernstein 

[Why]
Diagnostics scaling test failing to set required number of vertical taps
in 4:2:0 surface case

[How]
In dpp3_get_optimal_number_of_taps() need to use LB_MEMORY_CONFIG_3 for
4:2:0 surface case. In resource_build_scaling_params() make sure to also
set plane res alpha enable based on updated surface state

Signed-off-by: Eric Bernstein 
Reviewed-by: Dmytro Laktyushkin 
Acked-by: Rodrigo Siqueira 
---
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 75c7ce4c7581..f4bcc71b2920 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -1077,6 +1077,7 @@ bool resource_build_scaling_params(struct pipe_ctx 
*pipe_ctx)
 * on certain displays, such as the Sharp 4k
 */
pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
+   pipe_ctx->plane_res.scl_data.lb_params.alpha_en = 
plane_state->per_pixel_alpha;
 
pipe_ctx->plane_res.scl_data.recout.x += timing->h_border_left;
pipe_ctx->plane_res.scl_data.recout.y += timing->v_border_top;
-- 
2.25.2

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 12/12] drm/amd/display: Fix dcn21 num_states

[Rodrigo Siqueira]

From: Dmytro Laktyushkin 

[Why]
DML expects num_states to exclude the duplicate state.

[How]
Set num_states to correct value to prevent array off-by-one error.  Also
refactor max clock level code for diags.

Signed-off-by: Dmytro Laktyushkin 
Signed-off-by: George Shen 
Reviewed-by: Dmytro Laktyushkin 
Acked-by: Rodrigo Siqueira 
---
 .../drm/amd/display/dc/dcn20/dcn20_resource.c |  2 +-
 .../drm/amd/display/dc/dcn21/dcn21_resource.c | 37 ++-
 .../gpu/drm/amd/display/dc/dml/dc_features.h  |  2 +-
 .../amd/display/dc/dml/display_mode_structs.h |  7 ++--
 4 files changed, 18 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 54e096055c6f..5cdbba0cd873 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -3343,7 +3343,7 @@ void dcn20_cap_soc_clocks(
 void dcn20_update_bounding_box(struct dc *dc, struct 
_vcs_dpi_soc_bounding_box_st *bb,
struct pp_smu_nv_clock_table *max_clocks, unsigned int 
*uclk_states, unsigned int num_states)
 {
-   struct _vcs_dpi_voltage_scaling_st 
calculated_states[MAX_CLOCK_LIMIT_STATES];
+   struct _vcs_dpi_voltage_scaling_st 
calculated_states[DC__VOLTAGE_STATES];
int i;
int num_calculated_states = 0;
int min_dcfclk = 0;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index 1849f7f9142c..17cef02f7327 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -301,7 +301,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = {
.xfc_bus_transport_time_us = 4,
.xfc_xbuf_latency_tolerance_us = 4,
.use_urgent_burst_bw = 1,
-   .num_states = 9
+   .num_states = 8
 };
 
 #ifndef MAX
@@ -1381,21 +1381,8 @@ static void update_bw_bounding_box(struct dc *dc, struct 
clk_bw_params *bw_param
unsigned int i, j, k;
int closest_clk_lvl;
 
-   // diags does not retrieve proper values from SMU
-   // cap states to 5 and make state 5 the max state
-   if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) || 
IS_DIAG_DC(dc->ctx->dce_environment)) {
-   dcn2_1_soc.num_states = 5;
-
-   dcn2_1_soc.clock_limits[5].state = 5;
-   dcn2_1_soc.clock_limits[5].dcfclk_mhz = 810.0;
-   dcn2_1_soc.clock_limits[5].fabricclk_mhz = 1600.0;
-   dcn2_1_soc.clock_limits[5].dispclk_mhz = 1395.0;
-   dcn2_1_soc.clock_limits[5].dppclk_mhz = 1285.0;
-   dcn2_1_soc.clock_limits[5].phyclk_mhz = 1325.0;
-   dcn2_1_soc.clock_limits[5].socclk_mhz = 953.0;
-   dcn2_1_soc.clock_limits[5].dscclk_mhz = 489.0;
-   dcn2_1_soc.clock_limits[5].dram_speed_mts = 4266.0;
-   } else {
+   // Default clock levels are used for diags, which may lead to 
overclocking.
+   if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) && 
!IS_DIAG_DC(dc->ctx->dce_environment)) {
dcn2_1_ip.max_num_otg = 
pool->base.res_cap->num_timing_generator;
dcn2_1_ip.max_num_dpp = pool->base.pipe_count;
dcn2_1_soc.num_chans = bw_params->num_channels;
@@ -1408,16 +1395,16 @@ static void update_bw_bounding_box(struct dc *dc, 
struct clk_bw_params *bw_param
dcn2_1_soc.clock_limits[0].dram_speed_mts = 
clk_table->entries[0].memclk_mhz * 2;
 
/*
-* Other levels: find cloest DCN clocks that fit the given 
clock limit using dcfclk
-* as indicater
+* Other levels: find closest DCN clocks that fit the given 
clock limit using dcfclk
+* as indicator
 */
 
closest_clk_lvl = -1;
/* index currently being filled */
k = 1;
for (i = 1; i < clk_table->num_entries; i++) {
-   /* loop backwards, skip duplicate state, +1 because SMU 
has precision issue */
-   for (j = dcn2_1_soc.num_states - 2; j >= k; j--) {
+   /* loop backwards, skip duplicate state*/
+   for (j = dcn2_1_soc.num_states - 1; j >= k; j--) {
if ((unsigned int) 
dcn2_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) {
closest_clk_lvl = j;
break;
@@ -1442,13 +1429,13 @@ static void update_bw_bounding_box(struct dc *dc, 
struct clk_bw_params *bw_param
k++;
}
}
-
-   /* duplicate last level */
-   dcn2_1_soc.clock_limits[k] = dcn2_1_soc.clock_limits[k - 1];
-   dcn2_1_soc.clock_limits[k].state = k;
-   

Re: [PATCH 1/4] drm/amdgpu: add stride to calculate oss ring offsets

[Deucher, Alexander]

[AMD Public Use]

Yes, something like that.

Alex

From: Kuehling, Felix 
Sent: Friday, March 20, 2020 10:47 AM
To: Deucher, Alexander ; Sierra Guiza, Alejandro 
(Alex) ; amd-gfx@lists.freedesktop.org 

Subject: Re: [PATCH 1/4] drm/amdgpu: add stride to calculate oss ring offsets



On 2020-03-20 10:39, Deucher, Alexander wrote:

[AMD Public Use]

I'm worried we'll miss a register by accident.  We went with per IP sub drivers 
to avoid handling complexities around IP differences if possible.  Also the 
scheme seems like kind of a one off compared to what we do for other IPs.  Can 
we structure it more like how we handle SDMA instancing since it seems to 
mainly affect IH RB instances?

That's more or less what I had in mind, but haven't looked at the SDMA 
implementation in detail. So do you mean defining macros WREG32_IH_RING(ring, 
offset, value) and RREG32_IH_RING(ring, offset) analogous to WREG32_SDMA and 
RREG32_SDMA? It would only apply to IH ring-specific registers. Not to other 
general IH registers.


Regards,
  Felix


Alex


From: Kuehling, Felix 
Sent: Friday, March 20, 2020 10:20 AM
To: Deucher, Alexander 
; Sierra Guiza, 
Alejandro (Alex) ; 
amd-gfx@lists.freedesktop.org 

Subject: Re: [PATCH 1/4] drm/amdgpu: add stride to calculate oss ring offsets

On 2020-03-20 10:06, Deucher, Alexander wrote:

[AMD Public Use]

This seems kind of complicated and error prone.  I didn't realize the extent to 
the changes required.  I think it would be better to either add arcturus 
specific versions of these functions or just go with your original approach and 
add a new arcturus_ih.c.  If you go with the second route however, no need to 
show all your intermediate steps, just add the new files in one commit.

Hi Alex,


I suggested the approach in this patch series since to minimize code 
duplication and maintain readability of the code. I don't think it's very error 
prone. I believe this is more maintainable than a separate arcturus_ih.c. I'll 
have some more specific comments on Alejandro's patches.


Regards,
  Felix


Alex


From: amd-gfx 

 on behalf of Alex Sierra 
Sent: Thursday, March 19, 2020 8:22 PM
To: amd-gfx@lists.freedesktop.org 

Cc: Sierra Guiza, Alejandro (Alex) 

Subject: [PATCH 1/4] drm/amdgpu: add stride to calculate oss ring offsets

Arcturus and vega10 share the same vega10_ih, however both
have different register offsets at the ih ring section.
This variable is used to help calculate ih ring register addresses
from the osssys, that corresponds to the current asic type.

Signed-off-by: Alex Sierra 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 4 
 drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h | 1 +
 2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
index 5ed4227f304b..fa384ae9a9bc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
@@ -279,6 +279,10 @@ int amdgpu_irq_init(struct amdgpu_device *adev)
 amdgpu_hotplug_work_func);
 }

+   if (adev->asic_type == CHIP_ARCTURUS)
+   adev->irq.ring_stride = 1;
+   else
+   adev->irq.ring_stride = 0;
 INIT_WORK(>irq.ih1_work, amdgpu_irq_handle_ih1);
 INIT_WORK(>irq.ih2_work, amdgpu_irq_handle_ih2);

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
index c718e94a55c9..1ec5b735cd9e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
@@ -97,6 +97,7 @@ struct amdgpu_irq {
 struct irq_domain   *domain; /* GPU irq controller domain 
*/
 unsignedvirq[AMDGPU_MAX_IRQ_SRC_ID];
 uint32_tsrbm_soft_reset;
+   unsignedring_stride;
 };

 void amdgpu_irq_disable_all(struct amdgpu_device *adev);
--
2.17.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org

Re: [PATCH 1/4] drm/amdgpu: add stride to calculate oss ring offsets

[Felix Kuehling]

On 2020-03-20 10:39, Deucher, Alexander wrote:


[AMD Public Use]


I'm worried we'll miss a register by accident.  We went with per IP 
sub drivers to avoid handling complexities around IP differences if 
possible.  Also the scheme seems like kind of a one off compared to 
what we do for other IPs.  Can we structure it more like how we handle 
SDMA instancing since it seems to mainly affect IH RB instances?


That's more or less what I had in mind, but haven't looked at the SDMA 
implementation in detail. So do you mean defining macros 
WREG32_IH_RING(ring, offset, value) and RREG32_IH_RING(ring, offset) 
analogous to WREG32_SDMA and RREG32_SDMA? It would only apply to IH 
ring-specific registers. Not to other general IH registers.



Regards,
  Felix




Alex


*From:* Kuehling, Felix 
*Sent:* Friday, March 20, 2020 10:20 AM
*To:* Deucher, Alexander ; Sierra Guiza, 
Alejandro (Alex) ; amd-gfx@lists.freedesktop.org 

*Subject:* Re: [PATCH 1/4] drm/amdgpu: add stride to calculate oss 
ring offsets

On 2020-03-20 10:06, Deucher, Alexander wrote:


[AMD Public Use]


This seems kind of complicated and error prone.  I didn't realize the 
extent to the changes required.  I think it would be better to either 
add arcturus specific versions of these functions or just go with 
your original approach and add a new arcturus_ih.c.  If you go with 
the second route however, no need to show all your intermediate 
steps, just add the new files in one commit.


Hi Alex,


I suggested the approach in this patch series since to minimize code 
duplication and maintain readability of the code. I don't think it's 
very error prone. I believe this is more maintainable than a separate 
arcturus_ih.c. I'll have some more specific comments on Alejandro's 
patches.



Regards,
  Felix




Alex


*From:* amd-gfx  
 on behalf of Alex 
Sierra  

*Sent:* Thursday, March 19, 2020 8:22 PM
*To:* amd-gfx@lists.freedesktop.org 
 
 
*Cc:* Sierra Guiza, Alejandro (Alex)  

*Subject:* [PATCH 1/4] drm/amdgpu: add stride to calculate oss ring 
offsets

Arcturus and vega10 share the same vega10_ih, however both
have different register offsets at the ih ring section.
This variable is used to help calculate ih ring register addresses
from the osssys, that corresponds to the current asic type.

Signed-off-by: Alex Sierra  


---
 drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 4 
 drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h | 1 +
 2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c

index 5ed4227f304b..fa384ae9a9bc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
@@ -279,6 +279,10 @@ int amdgpu_irq_init(struct amdgpu_device *adev)
amdgpu_hotplug_work_func);
 }

+   if (adev->asic_type == CHIP_ARCTURUS)
+   adev->irq.ring_stride = 1;
+   else
+   adev->irq.ring_stride = 0;
 INIT_WORK(>irq.ih1_work, amdgpu_irq_handle_ih1);
 INIT_WORK(>irq.ih2_work, amdgpu_irq_handle_ih2);

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h

index c718e94a55c9..1ec5b735cd9e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
@@ -97,6 +97,7 @@ struct amdgpu_irq {
 struct irq_domain   *domain; /* GPU irq 
controller domain */

 unsigned virq[AMDGPU_MAX_IRQ_SRC_ID];
 uint32_t srbm_soft_reset;
+   unsigned ring_stride;
 };

 void amdgpu_irq_disable_all(struct amdgpu_device *adev);
--
2.17.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org 
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfxdata=02%7C01%7Calexander.deucher%40amd.com%7C17d5391c86ff4ceee12b08d7cc64f056%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637202606831789803sdata=B%2BbtLEKN5A65OEp8se5m1M4aQGX7kxsqYYGTTukF5m8%3Dreserved=0 



___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org  

Re: [PATCH 4/4] mm: check the device private page owner in hmm_range_fault

[Jason Gunthorpe]

On Mon, Mar 16, 2020 at 08:32:16PM +0100, Christoph Hellwig wrote:
> diff --git a/mm/hmm.c b/mm/hmm.c
> index cfad65f6a67b..b75b3750e03d 100644
> +++ b/mm/hmm.c
> @@ -216,6 +216,14 @@ int hmm_vma_handle_pmd(struct mm_walk *walk, unsigned 
> long addr,
>   unsigned long end, uint64_t *pfns, pmd_t pmd);
>  #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
>  
> +static inline bool hmm_is_device_private_entry(struct hmm_range *range,
> + swp_entry_t entry)
> +{
> + return is_device_private_entry(entry) &&
> + device_private_entry_to_page(entry)->pgmap->owner ==
> + range->dev_private_owner;
> +}

Thinking about this some more, does the locking work out here?

hmm_range_fault() runs with mmap_sem in read, and does not lock any of
the page table levels.

So it relies on accessing stale pte data being safe, and here we
introduce for the first time a page pointer dereference and a pgmap
dereference without any locking/refcounting.

The get_dev_pagemap() worked on the PFN and obtained a refcount, so it
created safety.

Is there some tricky reason this is safe, eg a DEVICE_PRIVATE page
cannot be removed from the vma without holding mmap_sem in write or
something?

Jason
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 3/4] mm: simplify device private page handling in hmm_range_fault

[Jason Gunthorpe]

On Thu, Mar 19, 2020 at 06:33:04PM -0700, Ralph Campbell wrote:

> > > + .default_flags = dmirror_hmm_flags[HMM_PFN_VALID] |
> > > + (write ? dmirror_hmm_flags[HMM_PFN_WRITE] : 0),
> > > + .dev_private_owner = dmirror->mdevice,
> > > + };
> > > + int ret = 0;
> > 
> > > +static int dmirror_snapshot(struct dmirror *dmirror,
> > > + struct hmm_dmirror_cmd *cmd)
> > > +{
> > > + struct mm_struct *mm = dmirror->mm;
> > > + unsigned long start, end;
> > > + unsigned long size = cmd->npages << PAGE_SHIFT;
> > > + unsigned long addr;
> > > + unsigned long next;
> > > + uint64_t pfns[64];
> > > + unsigned char perm[64];
> > > + char __user *uptr;
> > > + struct hmm_range range = {
> > > + .pfns = pfns,
> > > + .flags = dmirror_hmm_flags,
> > > + .values = dmirror_hmm_values,
> > > + .pfn_shift = DPT_SHIFT,
> > > + .pfn_flags_mask = ~0ULL,
> > 
> > Same here, especially since this is snapshot
> > 
> > Jason
> 
> Actually, snapshot ignores pfn_flags_mask and default_flags.

Yes, so no reason to set them to not 0..

Jason
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm/amdgpu: infinite retries fix from UTLC1 RB SDMA

[Felix Kuehling]

On 2020-03-19 20:27, Alex Sierra wrote:

[Why]
Previously these registers were set to 0. This was causing an
infinite retry on the UTCL1 RB, preventing higher priority RB such as paging RB.

[How]
Set to one the SDMAx_UTLC1_TIMEOUT registers for all SDMAs on Arcturus.


Please update this description because the patch is no longer limited to 
Arcturus.


One more comment inline. With those fixed, the patch is

Reviewed-by: Felix Kuehling 




Signed-off-by: Alex Sierra 
---
  drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 21 +
  1 file changed, 17 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index fc664ec6b5fd..09c08906046f 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -115,17 +115,21 @@ static const struct soc15_reg_golden 
golden_settings_sdma_4[] = {
  static const struct soc15_reg_golden golden_settings_sdma_vg10[] = {
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 
0x00104002),
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 
0x0018773f, 0x00104002),
+   SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA0_UTCL1_TIMEOUT, 0x, 
0x00010001),
SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 
0x02831d07),
SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 
0x00104002),
-   SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 
0x0018773f, 0x00104002)
+   SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 
0x0018773f, 0x00104002),
+   SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0x, 
0x00010001),
  };
  
  static const struct soc15_reg_golden golden_settings_sdma_vg12[] = {

SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 
0x00104001),
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 
0x0018773f, 0x00104001),
+   SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA1_UTCL1_TIMEOUT, 0x, 
0x00010001),
SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 
0x02831d07),
SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 
0x00104001),
-   SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 
0x0018773f, 0x00104001)
+   SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 
0x0018773f, 0x00104001),
+   SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0x, 
0x00010001),
  };
  
  static const struct soc15_reg_golden golden_settings_sdma_4_1[] = {

@@ -174,6 +178,7 @@ static const struct soc15_reg_golden 
golden_settings_sdma0_4_2[] =
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_RPTR_ADDR_LO, 
0xfffd, 0x0001),
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 
0xfff7, 0x00403000),
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x03ff, 
0x03c0),
+   SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA1_UTCL1_TIMEOUT, 0x, 
0x00010001),
  };
  
  static const struct soc15_reg_golden golden_settings_sdma1_4_2[] = {

@@ -203,6 +208,7 @@ static const struct soc15_reg_golden 
golden_settings_sdma1_4_2[] = {
SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_RPTR_ADDR_LO, 
0xfffd, 0x0001),
SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 
0xfff7, 0x00403000),
SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x03ff, 
0x03c0),
+   SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0x, 
0x00010001),
  };
  
  static const struct soc15_reg_golden golden_settings_sdma_rv1[] =

@@ -222,27 +228,35 @@ static const struct soc15_reg_golden 
golden_settings_sdma_arct[] =
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 
0x02831f07),
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x773f, 
0x4002),
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 
0x773f, 0x4002),
+   SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0x, 
0x00010001),
SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 
0x02831f07),
SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x773f, 
0x4002),
SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 
0x773f, 0x4002),
+   SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0x, 
0x00010001),
SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_CHICKEN_BITS, 0xfe931f07, 
0x02831f07),
SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG, 0x773f, 
0x4002),
SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG_READ, 
0x773f, 0x4002),
+   SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_UTCL1_TIMEOUT, 0x, 
0x00010001),
SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_CHICKEN_BITS, 0xfe931f07, 
0x02831f07),

Re: [PATCH 1/4] drm/amdgpu: add stride to calculate oss ring offsets

[Deucher, Alexander]

[AMD Public Use]

I'm worried we'll miss a register by accident.  We went with per IP sub drivers 
to avoid handling complexities around IP differences if possible.  Also the 
scheme seems like kind of a one off compared to what we do for other IPs.  Can 
we structure it more like how we handle SDMA instancing since it seems to 
mainly affect IH RB instances?

Alex


From: Kuehling, Felix 
Sent: Friday, March 20, 2020 10:20 AM
To: Deucher, Alexander ; Sierra Guiza, Alejandro 
(Alex) ; amd-gfx@lists.freedesktop.org 

Subject: Re: [PATCH 1/4] drm/amdgpu: add stride to calculate oss ring offsets

On 2020-03-20 10:06, Deucher, Alexander wrote:

[AMD Public Use]

This seems kind of complicated and error prone.  I didn't realize the extent to 
the changes required.  I think it would be better to either add arcturus 
specific versions of these functions or just go with your original approach and 
add a new arcturus_ih.c.  If you go with the second route however, no need to 
show all your intermediate steps, just add the new files in one commit.

Hi Alex,


I suggested the approach in this patch series since to minimize code 
duplication and maintain readability of the code. I don't think it's very error 
prone. I believe this is more maintainable than a separate arcturus_ih.c. I'll 
have some more specific comments on Alejandro's patches.


Regards,
  Felix


Alex


From: amd-gfx 

 on behalf of Alex Sierra 
Sent: Thursday, March 19, 2020 8:22 PM
To: amd-gfx@lists.freedesktop.org 

Cc: Sierra Guiza, Alejandro (Alex) 

Subject: [PATCH 1/4] drm/amdgpu: add stride to calculate oss ring offsets

Arcturus and vega10 share the same vega10_ih, however both
have different register offsets at the ih ring section.
This variable is used to help calculate ih ring register addresses
from the osssys, that corresponds to the current asic type.

Signed-off-by: Alex Sierra 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 4 
 drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h | 1 +
 2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
index 5ed4227f304b..fa384ae9a9bc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
@@ -279,6 +279,10 @@ int amdgpu_irq_init(struct amdgpu_device *adev)
 amdgpu_hotplug_work_func);
 }

+   if (adev->asic_type == CHIP_ARCTURUS)
+   adev->irq.ring_stride = 1;
+   else
+   adev->irq.ring_stride = 0;
 INIT_WORK(>irq.ih1_work, amdgpu_irq_handle_ih1);
 INIT_WORK(>irq.ih2_work, amdgpu_irq_handle_ih2);

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
index c718e94a55c9..1ec5b735cd9e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
@@ -97,6 +97,7 @@ struct amdgpu_irq {
 struct irq_domain   *domain; /* GPU irq controller domain 
*/
 unsignedvirq[AMDGPU_MAX_IRQ_SRC_ID];
 uint32_tsrbm_soft_reset;
+   unsignedring_stride;
 };

 void amdgpu_irq_disable_all(struct amdgpu_device *adev);
--
2.17.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfxdata=02%7C01%7Calexander.deucher%40amd.com%7C17d5391c86ff4ceee12b08d7cc64f056%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637202606831789803sdata=B%2BbtLEKN5A65OEp8se5m1M4aQGX7kxsqYYGTTukF5m8%3Dreserved=0



___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfxdata=02%7C01%7Cfelix.kuehling%40amd.com%7C7e44179e2a0d49c972ba08d7ccd7e626%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637203100032296023sdata=bil9pUebulcGpl5YhTi9k6yqK8wYDzw6XN%2FSZ9YbR44%3Dreserved=0

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 1/6] drm/amdgpu: ih doorbell size of range changed for nbio v7.4

[Felix Kuehling]

On 2020-03-19 20:24, Alex Sierra wrote:

[Why]
nbio v7.4 size of ih doorbell range is 64 bit. This requires 2 DWords per 
register.

[How]
Change ih doorbell size from 2 to 4. This means two Dwords per ring.
Current configuration uses two ih rings.

Signed-off-by: Alex Sierra 


Why is the subject "PATCH 1/6"? It makes me wonder, what are the other 5 
patches. Anyway, this patch is


Reviewed-by: Felix Kuehling 



---
  drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c 
b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
index 149d386590df..263dbb1f92ee 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
@@ -185,7 +185,7 @@ static void nbio_v7_4_ih_doorbell_range(struct 
amdgpu_device *adev,
  
  	if (use_doorbell) {

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 
BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index);
-   ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 
BIF_IH_DOORBELL_RANGE, SIZE, 2);
+   ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 
BIF_IH_DOORBELL_RANGE, SIZE, 4);
} else
ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 
BIF_IH_DOORBELL_RANGE, SIZE, 0);
  

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 2/4] drm/amdgpu: add macro to get proper ih ring register offset

[Felix Kuehling]

On 2020-03-19 20:22, Alex Sierra wrote:

This macro calculates the IH ring register offset based on
the three ring numbers and asic type.
The parameters needed are the register's name without the prefix mmIH
and the ring number taken from RING0, RING1 or RING2 macros.

Signed-off-by: Alex Sierra 
---
  drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 5 +
  1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c 
b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
index 407c6093c2ec..5bd9bc37fadf 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
@@ -34,6 +34,11 @@
  #include "vega10_ih.h"
  
  #define MAX_REARM_RETRY 10

+#define RING0 0
+#define RING1 (RING0 + 4)
+#define RING2 (RING1 + 4)
+
+#define mmIH_RING_REG(reg, ring) (SOC15_REG_OFFSET(OSSSYS, 0, mmIH_##reg) + 
(ring) * adev->irq.ring_stride)


I don't think you need the RINGx definitions. Just use numbers 0-2. The 
ring_stride should be the number of registers to skip from one ring to 
the next, which can be different for different ASICs. E.g. 
(mmIH_RB_CNTL_RING1 - mmIH_RB_CNTL). It's 8 on Vega, 12 on Arcturus.


I'd squash patches 1 and 2 to make this more obvious.

Regards,
  Felix

  
  static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev);
  

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 3/3] drm/amdgpu: Add documentation for unique_id

[Deucher, Alexander]

[AMD Public Use]

Series is:
Reviewed-by: Alex Deucher 

From: amd-gfx  on behalf of Kent Russell 

Sent: Friday, March 20, 2020 9:24 AM
To: amd-gfx@lists.freedesktop.org 
Cc: Russell, Kent 
Subject: [PATCH 3/3] drm/amdgpu: Add documentation for unique_id

Add the amdgpu.rst tie-ins for the unique_id documentation

Signed-off-by: Kent Russell 
---
 Documentation/gpu/amdgpu.rst | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/gpu/amdgpu.rst b/Documentation/gpu/amdgpu.rst
index 9afcc30e0f42..4cc74325bf91 100644
--- a/Documentation/gpu/amdgpu.rst
+++ b/Documentation/gpu/amdgpu.rst
@@ -227,6 +227,12 @@ serial_number
 .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
:doc: serial_number

+unique_id
+-
+
+.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+   :doc: unique_id
+
 GPU Memory Usage Information
 

--
2.17.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfxdata=02%7C01%7Calexander.deucher%40amd.com%7Ce80cd6be2dc74bc51dc308d7ccd2061e%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637203075216673697sdata=w7F1uiIEJMvJAbb%2FsT6bU6zZ%2FboFgzwLHu9RpCMYuhY%3Dreserved=0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 1/4] drm/amdgpu: add stride to calculate oss ring offsets

[Felix Kuehling]

On 2020-03-20 10:06, Deucher, Alexander wrote:


[AMD Public Use]


This seems kind of complicated and error prone.  I didn't realize the 
extent to the changes required.  I think it would be better to either 
add arcturus specific versions of these functions or just go with your 
original approach and add a new arcturus_ih.c.  If you go with the 
second route however, no need to show all your intermediate steps, 
just add the new files in one commit.


Hi Alex,


I suggested the approach in this patch series since to minimize code 
duplication and maintain readability of the code. I don't think it's 
very error prone. I believe this is more maintainable than a separate 
arcturus_ih.c. I'll have some more specific comments on Alejandro's patches.



Regards,
  Felix




Alex


*From:* amd-gfx  on behalf of 
Alex Sierra 

*Sent:* Thursday, March 19, 2020 8:22 PM
*To:* amd-gfx@lists.freedesktop.org 
*Cc:* Sierra Guiza, Alejandro (Alex) 
*Subject:* [PATCH 1/4] drm/amdgpu: add stride to calculate oss ring 
offsets

Arcturus and vega10 share the same vega10_ih, however both
have different register offsets at the ih ring section.
This variable is used to help calculate ih ring register addresses
from the osssys, that corresponds to the current asic type.

Signed-off-by: Alex Sierra 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 4 
 drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h | 1 +
 2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c

index 5ed4227f304b..fa384ae9a9bc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
@@ -279,6 +279,10 @@ int amdgpu_irq_init(struct amdgpu_device *adev)
amdgpu_hotplug_work_func);
 }

+   if (adev->asic_type == CHIP_ARCTURUS)
+   adev->irq.ring_stride = 1;
+   else
+   adev->irq.ring_stride = 0;
 INIT_WORK(>irq.ih1_work, amdgpu_irq_handle_ih1);
 INIT_WORK(>irq.ih2_work, amdgpu_irq_handle_ih2);

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h

index c718e94a55c9..1ec5b735cd9e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
@@ -97,6 +97,7 @@ struct amdgpu_irq {
 struct irq_domain   *domain; /* GPU irq 
controller domain */

 unsigned virq[AMDGPU_MAX_IRQ_SRC_ID];
 uint32_t srbm_soft_reset;
+   unsigned    ring_stride;
 };

 void amdgpu_irq_disable_all(struct amdgpu_device *adev);
--
2.17.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfxdata=02%7C01%7Calexander.deucher%40amd.com%7C17d5391c86ff4ceee12b08d7cc64f056%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637202606831789803sdata=B%2BbtLEKN5A65OEp8se5m1M4aQGX7kxsqYYGTTukF5m8%3Dreserved=0 



___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfxdata=02%7C01%7Cfelix.kuehling%40amd.com%7C7e44179e2a0d49c972ba08d7ccd7e626%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637203100032296023sdata=bil9pUebulcGpl5YhTi9k6yqK8wYDzw6XN%2FSZ9YbR44%3Dreserved=0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 1/4] drm/amdgpu: add stride to calculate oss ring offsets

[Deucher, Alexander]

[AMD Public Use]

This seems kind of complicated and error prone.  I didn't realize the extent to 
the changes required.  I think it would be better to either add arcturus 
specific versions of these functions or just go with your original approach and 
add a new arcturus_ih.c.  If you go with the second route however, no need to 
show all your intermediate steps, just add the new files in one commit.

Alex


From: amd-gfx  on behalf of Alex Sierra 

Sent: Thursday, March 19, 2020 8:22 PM
To: amd-gfx@lists.freedesktop.org 
Cc: Sierra Guiza, Alejandro (Alex) 
Subject: [PATCH 1/4] drm/amdgpu: add stride to calculate oss ring offsets

Arcturus and vega10 share the same vega10_ih, however both
have different register offsets at the ih ring section.
This variable is used to help calculate ih ring register addresses
from the osssys, that corresponds to the current asic type.

Signed-off-by: Alex Sierra 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 4 
 drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h | 1 +
 2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
index 5ed4227f304b..fa384ae9a9bc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
@@ -279,6 +279,10 @@ int amdgpu_irq_init(struct amdgpu_device *adev)
 amdgpu_hotplug_work_func);
 }

+   if (adev->asic_type == CHIP_ARCTURUS)
+   adev->irq.ring_stride = 1;
+   else
+   adev->irq.ring_stride = 0;
 INIT_WORK(>irq.ih1_work, amdgpu_irq_handle_ih1);
 INIT_WORK(>irq.ih2_work, amdgpu_irq_handle_ih2);

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
index c718e94a55c9..1ec5b735cd9e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
@@ -97,6 +97,7 @@ struct amdgpu_irq {
 struct irq_domain   *domain; /* GPU irq controller domain 
*/
 unsignedvirq[AMDGPU_MAX_IRQ_SRC_ID];
 uint32_tsrbm_soft_reset;
+   unsignedring_stride;
 };

 void amdgpu_irq_disable_all(struct amdgpu_device *adev);
--
2.17.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfxdata=02%7C01%7Calexander.deucher%40amd.com%7C17d5391c86ff4ceee12b08d7cc64f056%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637202606831789803sdata=B%2BbtLEKN5A65OEp8se5m1M4aQGX7kxsqYYGTTukF5m8%3Dreserved=0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 1/3] drm/amdgpu: Add documentation for memory info

[Kent Russell]

Add the amdgpu.rst tie-ins for the mem_info documentation

Signed-off-by: Kent Russell 
---
 Documentation/gpu/amdgpu.rst | 41 
 1 file changed, 41 insertions(+)

diff --git a/Documentation/gpu/amdgpu.rst b/Documentation/gpu/amdgpu.rst
index d9ea09ec8e24..cb689fab94c7 100644
--- a/Documentation/gpu/amdgpu.rst
+++ b/Documentation/gpu/amdgpu.rst
@@ -226,3 +226,44 @@ serial_number
 
 .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
:doc: serial_number
+
+GPU Memory Usage Information
+
+
+Various memory accounting can be accessed via sysfs
+
+mem_info_vram_total
+---
+
+.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
+   :doc: mem_info_vram_total
+
+mem_info_vram_used
+--
+
+.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
+   :doc: mem_info_vram_used
+
+mem_info_vis_vram_total
+---
+
+.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
+   :doc: mem_info_vis_vram_total
+
+mem_info_vis_vram_used
+--
+
+.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
+   :doc: mem_info_vis_vram_used
+
+mem_info_gtt_total
+---
+
+.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
+   :doc: mem_info_gtt_total
+
+mem_info_gtt_used
+--
+
+.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
+   :doc: mem_info_gtt_used
-- 
2.17.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 3/3] drm/amdgpu: Add documentation for unique_id

[Kent Russell]

Add the amdgpu.rst tie-ins for the unique_id documentation

Signed-off-by: Kent Russell 
---
 Documentation/gpu/amdgpu.rst | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/gpu/amdgpu.rst b/Documentation/gpu/amdgpu.rst
index 9afcc30e0f42..4cc74325bf91 100644
--- a/Documentation/gpu/amdgpu.rst
+++ b/Documentation/gpu/amdgpu.rst
@@ -227,6 +227,12 @@ serial_number
 .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
:doc: serial_number
 
+unique_id
+-
+
+.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+   :doc: unique_id
+
 GPU Memory Usage Information
 
 
-- 
2.17.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 2/3] drm/amdgpu: Add documentation for PCIe accounting

[Kent Russell]

Add the amdgpu.rst tie-ins for the pcie accounting documentation

Signed-off-by: Kent Russell 
---
 Documentation/gpu/amdgpu.rst | 21 +++--
 1 file changed, 19 insertions(+), 2 deletions(-)

diff --git a/Documentation/gpu/amdgpu.rst b/Documentation/gpu/amdgpu.rst
index cb689fab94c7..9afcc30e0f42 100644
--- a/Documentation/gpu/amdgpu.rst
+++ b/Documentation/gpu/amdgpu.rst
@@ -257,13 +257,30 @@ mem_info_vis_vram_used
:doc: mem_info_vis_vram_used
 
 mem_info_gtt_total

+--
 
 .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
:doc: mem_info_gtt_total
 
 mem_info_gtt_used
---
+-
 
 .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
:doc: mem_info_gtt_used
+
+PCIe Accounting Information
+===
+
+pcie_bw
+---
+
+.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+   :doc: pcie_bw
+
+pcie_replay_count
+-
+
+.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+   :doc: pcie_replay_count
+
+
-- 
2.17.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH net-next] drm/amdgpu: Uninitialized variable in gfx_v9_0_rlcg_wreg()

[Dan Carpenter]

The "shadow" variable was never set to false.

There is a quirk in current versions of GCC where it will sometimes set
it to false and not warn about the uninitiliazed variable.  That means
that this bug wouldn't have been discovered in normal testing.

Fixes: 2e0cc4d48b91 ("drm/amdgpu: revise RLCG access path")
Signed-off-by: Dan Carpenter 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 7bc2486167e7..affbff76758c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -735,7 +735,7 @@ void gfx_v9_0_rlcg_wreg(struct amdgpu_device *adev, u32 
offset, u32 v)
static void *spare_int;
static uint32_t grbm_cntl;
static uint32_t grbm_idx;
-   bool shadow;
+   bool shadow = false;
 
scratch_reg0 = adev->rmmio + 
(adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0)*4;
scratch_reg1 = adev->rmmio + 
(adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1)*4;
-- 
2.25.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH] drm/amdgpu: fix size validation failure in large buffer creation

[Tianci Yin]

From: "Tianci.Yin" 

[why]
When GTT domain size is smaller than VRAM, if APP apply a very large
buffer whose size is larger than GTT but smaller than VRAM, the size
validation will fail.

[how]
Validate VRAM domain size at first place, then GTT domain.

Change-Id: Ic1d31b9b0a4939e6bba0241ff79ae9aa2225ee05
Signed-off-by: Tianci.Yin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 18 +-
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 84745f9e7408..bab134b6369f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -464,21 +464,21 @@ static bool amdgpu_bo_validate_size(struct amdgpu_device 
*adev,
 {
struct ttm_mem_type_manager *man = NULL;
 
-   /*
-* If GTT is part of requested domains the check must succeed to
-* allow fall back to GTT
-*/
-   if (domain & AMDGPU_GEM_DOMAIN_GTT) {
-   man = >mman.bdev.man[TTM_PL_TT];
+   if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
+   man = >mman.bdev.man[TTM_PL_VRAM];
 
if (size < (man->size << PAGE_SHIFT))
return true;
-   else
+   else if (!(domain & AMDGPU_GEM_DOMAIN_GTT))
goto fail;
}
 
-   if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
-   man = >mman.bdev.man[TTM_PL_VRAM];
+   /*
+* If GTT is part of requested domains the check must succeed to
+* allow fall back to GTT
+*/
+   if (domain & AMDGPU_GEM_DOMAIN_GTT) {
+   man = >mman.bdev.man[TTM_PL_TT];
 
if (size < (man->size << PAGE_SHIFT))
return true;
-- 
2.17.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 3/4] mm: simplify device private page handling in hmm_range_fault

[Jason Gunthorpe]

On Tue, Mar 17, 2020 at 04:14:31PM -0700, Ralph Campbell wrote:

> +static int dmirror_fault(struct dmirror *dmirror, unsigned long start,
> +  unsigned long end, bool write)
> +{
> + struct mm_struct *mm = dmirror->mm;
> + unsigned long addr;
> + uint64_t pfns[64];
> + struct hmm_range range = {
> + .notifier = >notifier,
> + .pfns = pfns,
> + .flags = dmirror_hmm_flags,
> + .values = dmirror_hmm_values,
> + .pfn_shift = DPT_SHIFT,
> + .pfn_flags_mask = ~(dmirror_hmm_flags[HMM_PFN_VALID] |
> + dmirror_hmm_flags[HMM_PFN_WRITE]),

Since pfns is not initialized pfn_flags_mask should be 0.

> + .default_flags = dmirror_hmm_flags[HMM_PFN_VALID] |
> + (write ? dmirror_hmm_flags[HMM_PFN_WRITE] : 0),
> + .dev_private_owner = dmirror->mdevice,
> + };
> + int ret = 0;

> +static int dmirror_snapshot(struct dmirror *dmirror,
> + struct hmm_dmirror_cmd *cmd)
> +{
> + struct mm_struct *mm = dmirror->mm;
> + unsigned long start, end;
> + unsigned long size = cmd->npages << PAGE_SHIFT;
> + unsigned long addr;
> + unsigned long next;
> + uint64_t pfns[64];
> + unsigned char perm[64];
> + char __user *uptr;
> + struct hmm_range range = {
> + .pfns = pfns,
> + .flags = dmirror_hmm_flags,
> + .values = dmirror_hmm_values,
> + .pfn_shift = DPT_SHIFT,
> + .pfn_flags_mask = ~0ULL,

Same here, especially since this is snapshot

Jason
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 3/4] mm: simplify device private page handling in hmm_range_fault

[Jason Gunthorpe]

On Thu, Mar 19, 2020 at 03:56:50PM -0700, Ralph Campbell wrote:
> Adding linux-kselft...@vger.kernel.org for the test config question.
> 
> On 3/19/20 11:17 AM, Jason Gunthorpe wrote:
> > On Tue, Mar 17, 2020 at 04:14:31PM -0700, Ralph Campbell wrote:
> > > 
> > > On 3/17/20 5:59 AM, Christoph Hellwig wrote:
> > > > On Tue, Mar 17, 2020 at 09:47:55AM -0300, Jason Gunthorpe wrote:
> > > > > I've been using v7 of Ralph's tester and it is working well - it has
> > > > > DEVICE_PRIVATE support so I think it can test this flow too. Ralph are
> > > > > you able?
> > > > > 
> > > > > This hunk seems trivial enough to me, can we include it now?
> > > > 
> > > > I can send a separate patch for it once the tester covers it.  I don't
> > > > want to add it to the original patch as it is a significant behavior
> > > > change compared to the existing code.
> > > > 
> > > 
> > > Attached is an updated version of my HMM tests based on linux-5.6.0-rc6.
> > > I ran this OK with Jason's 8+1 HMM patches, Christoph's 1-5 misc HMM 
> > > clean ups,
> > > and Christoph's 1-4 device private page changes applied.
> > 
> > I'd like to get this to mergable, it looks pretty good now, but I have
> > no idea about selftests - and I'm struggling to even compile the tools
> > dir
> > 
> > > diff --git a/lib/Kconfig.debug b/lib/Kconfig.debug
> > > index 69def4a9df00..4d22ce7879a7 100644
> > > +++ b/lib/Kconfig.debug
> > > @@ -2162,6 +2162,18 @@ config TEST_MEMINIT
> > > If unsure, say N.
> > > +config TEST_HMM
> > > + tristate "Test HMM (Heterogeneous Memory Management)"
> > > + depends on DEVICE_PRIVATE
> > > + select HMM_MIRROR
> > > +select MMU_NOTIFIER
> > 
> > extra spaces
> 
> Will fix in v8.
> 
> > In general I wonder if it even makes sense that DEVICE_PRIVATE is user
> > selectable?
> 
> Should tests enable the feature or the feature enable the test?
> IMHO, if the feature is being compiled into the kernel, that should
> enable the menu item for the test. If the feature isn't selected,
> no need to test it :-)

I ment if DEVICE_PRIVATE should be a user selectable option at all, or
should it be turned on when a driver like nouveau is selected.

Is there some downside to enabling DEVICE_PRIVATE?

> > The notifier holds a mmgrab, no need for another one
> 
> OK. I'll replace dmirror->mm with dmirror->notifier.mm.

Right that is good too

> > > + filp->private_data = dmirror;
> > 
> > Not sure what this comment means
> 
> I'll change the comment to:
> /*
>  * The first open of the device character file registers the address
>  * space of the process doing the open() system call with the device.
>  * Subsequent file opens by other processes will have access to the
>  * first process' address space.
>  */

How does this happen? The function looks like it always does the same thing

> > > +static bool dmirror_interval_invalidate(struct mmu_interval_notifier 
> > > *mni,
> > > + const struct mmu_notifier_range *range,
> > > + unsigned long cur_seq)
> > > +{
> > > + struct dmirror *dmirror = container_of(mni, struct dmirror, notifier);
> > > + struct mm_struct *mm = dmirror->mm;
> > > +
> > > + /*
> > > +  * If the process doesn't exist, we don't need to invalidate the
> > > +  * device page table since the address space will be torn down.
> > > +  */
> > > + if (!mmget_not_zero(mm))
> > > + return true;
> > 
> > Why? Don't the notifiers provide for this already.
> > 
> > mmget_not_zero() is required before calling hmm_range_fault() though

Oh... This is the invalidate_all path during invalidation

IMHO you should test the invalidation reason in the range to exclude
this.

But xa_erase looks totally safe so there should be no reason to do
that.

> This is a workaround for a problem I don't quite understand.
> If you change tools/testing/selftests/vm/hmm-tests.c line 868 to
>   ASSERT_EQ(ret, -1);
> Then the test will abort, core dump, and cause two problems,
> 1) the migrated page will be faulted back to system memory in order to write
>it to the core dump. This triggers lockdep_assert_held(>mmap_sem)
>in walk_page_range().

Has the migration stuff become entangled with the xarray?

> [  137.980718] Code: 80 2f 1a 83 c6 05 e9 8d 7b 01 01 e8 3e b1 b1 fe e9 05 ff 
> ff ff 66 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 00 41 56 41 55 41 54 55 <48> 89 
> fd 53 4c 8d 6d 10 e8 3c fc ff ff 49 89 c4 4c 89 e0 83 e0 03
> [  137.999461] RSP: 0018:c900015e77c8 EFLAGS: 0246 ORIG_RAX: 
> ff13
> [  138.007028] RAX: 8886e508c408 RBX:  RCX: 
> 82626c89
> [  138.014159] RDX: dc00 RSI:  RDI: 
> c900015e78a0
> [  138.021293] RBP: c900015e78a0 R08: 811461c4 R09: 
> f520002bcf17
> [  138.028426] R10: f520002bcf16 R11: 0003 R12: 
> 02606d10
> [  138.035557] R13: 8886e508c448 R14: 0031 R15: 
>