Re: [PATCH 1/2] drm/amdgpu: fix and cleanup amdgpu_gem_object_close v2
Reviewed-by: xinhui pan
> 2020年3月30日 18:50，Christian König 写道：
>
> The problem is that we can't add the clear fence to the BO
> when there is an exclusive fence on it since we can't
> guarantee the the clear fence will complete after the
> exclusive one.
>
> To fix this refactor the function and also add the exclusive
> fence as shared to the resv object.
>
> v2: fix warning
> v3: add excl fence as shared instead
>
> Signed-off-by: Christian König
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 41 ++---
> 1 file changed, 23 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> index 5bec66e6b1f8..a0be80513e96 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> @@ -161,16 +161,17 @@ void amdgpu_gem_object_close(struct drm_gem_object *obj,
>
> struct amdgpu_bo_list_entry vm_pd;
> struct list_head list, duplicates;
> + struct dma_fence *fence = NULL;
> struct ttm_validate_buffer tv;
> struct ww_acquire_ctx ticket;
> struct amdgpu_bo_va *bo_va;
> - int r;
> + long r;
>
> INIT_LIST_HEAD();
> INIT_LIST_HEAD();
>
> tv.bo = >tbo;
> - tv.num_shared = 1;
> + tv.num_shared = 2;
> list_add(, );
>
> amdgpu_vm_get_pd_bo(vm, , _pd);
> @@ -178,28 +179,32 @@ void amdgpu_gem_object_close(struct drm_gem_object *obj,
> r = ttm_eu_reserve_buffers(, , false, );
> if (r) {
> dev_err(adev->dev, "leaking bo va because "
> - "we fail to reserve bo (%d)\n", r);
> + "we fail to reserve bo (%ld)\n", r);
> return;
> }
> bo_va = amdgpu_vm_bo_find(vm, bo);
> - if (bo_va && --bo_va->ref_count == 0) {
> - amdgpu_vm_bo_rmv(adev, bo_va);
> + if (!bo_va || --bo_va->ref_count)
> + goto out_unlock;
>
> - if (amdgpu_vm_ready(vm)) {
> - struct dma_fence *fence = NULL;
> + amdgpu_vm_bo_rmv(adev, bo_va);
> + if (!amdgpu_vm_ready(vm))
> + goto out_unlock;
>
> - r = amdgpu_vm_clear_freed(adev, vm, );
> - if (unlikely(r)) {
> - dev_err(adev->dev, "failed to clear page "
> - "tables on GEM object close (%d)\n", r);
> - }
> + fence = dma_resv_get_excl(bo->tbo.base.resv);
> + amdgpu_bo_fence(bo, fence, true);
> + fence = NULL;
>
> - if (fence) {
> - amdgpu_bo_fence(bo, fence, true);
> - dma_fence_put(fence);
> - }
> - }
> - }
> + r = amdgpu_vm_clear_freed(adev, vm, );
> + if (r || !fence)
> + goto out_unlock;
> +
> + amdgpu_bo_fence(bo, fence, true);
> + dma_fence_put(fence);
> +
> +out_unlock:
> + if (unlikely(r < 0))
> + dev_err(adev->dev, "failed to clear page "
> + "tables on GEM object close (%ld)\n", r);
> ttm_eu_backoff_reservation(, );
> }
>
> --
> 2.17.1
>
___
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Re: [PATCH v3 1/1] drm/amdgpu: rework sched_list generation
This patch seems to be using DOS line-endings. After converting
it to UNIX line-endings, the output of "git am" using "scripts/checkpatch.pl"
via the pre-commit hook is appended last to my thoughts below.
On 2020-03-30 11:49 a.m., Nirmoy Das wrote:
> Generate HW IP's sched_list in amdgpu_ring_init() instead of
> amdgpu_ctx.c. This makes amdgpu_ctx_init_compute_sched(),
> ring.has_high_prio and amdgpu_ctx_init_sched() unnecessary.
> This patch also stores sched_list for all HW IPs in one big
> array in struct amdgpu_device which makes amdgpu_ctx_init_entity()
> much more leaner.
>
> v2:
> fix a coding style issue
> do not use drm hw_ip const to populate amdgpu_ring_type enum
>
> v3:
> remove ctx reference and move sched array and num_sched to a struct
> use num_scheds to detect uninitialized scheduler list
>
> Signed-off-by: Nirmoy Das
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h| 8 ++
> drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c| 156 -
> drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h| 3 -
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 -
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c| 3 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h| 5 -
> drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h | 2 -
> drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 24 +++-
> drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 12 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h | 2 -
> drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h| 4 -
> drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 3 +-
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 13 +-
> drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 5 +-
> drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 5 +-
> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 11 +-
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 13 +-
> drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c | 3 +-
> drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 3 +-
> drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c | 3 +-
> drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 3 +-
> drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 3 +-
> drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 6 +-
> drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 3 +-
> drivers/gpu/drm/amd/amdgpu/si_dma.c| 3 +-
> drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 3 +-
> drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 3 +-
> drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 7 +-
> drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 6 +-
> drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 3 +-
> drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 3 +-
> drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 6 +-
> drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 6 +-
> drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 6 +-
> 35 files changed, 145 insertions(+), 198 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 29f0a410091b..27abbdc603dd 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -721,6 +721,11 @@ struct amd_powerplay {
> const struct amd_pm_funcs *pp_funcs;
> };
>
> +struct amdgpu_sched {
> + uint32_tnum_scheds;
> + struct drm_gpu_scheduler*sched[HWIP_MAX_INSTANCE];
> +};
> +
> #define AMDGPU_RESET_MAGIC_NUM 64
> #define AMDGPU_MAX_DF_PERFMONS 4
> struct amdgpu_device {
> @@ -858,6 +863,8 @@ struct amdgpu_device {
> struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
> boolib_pool_ready;
> struct amdgpu_sa_managerring_tmp_bo[AMDGPU_IB_POOL_MAX];
> + /* drm scheduler list */
> + struct amdgpu_sched
> gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX];
That's a 2-dimensional array of "struct amdgpu_sched".
I think that the comment should be removed, or at least
not say "drm scheduler list". (I can see the structure
definition above.)
If this is the path you want to go, consider removing
"num_scheds" and creating a three dimensional array,
which would really essentialize the direction you want
to go:
struct drm_gpu_scheduler
*gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX][HWIP_MAX_INSTANCE];
Now that this architecture is stripped down to its essentials,
perhaps we can see some optimizations...?
Also consider that since you're creating an array of pointers,
you don't necessarily need to know their count. Your hot-path
algorithms should not need to know it. If you need to print
their count, say in sysfs, then you can count them up on
behalf of the user-space process cat-ing the sysfs entry.
>
> /* interrupts */
> struct amdgpu_irq irq;
> @@ -993,6 +1000,7 @@ struct amdgpu_device {
> charproduct_number[16];
> charproduct_name[32];
> charserial[16];
> +
> };
Unnecessary empty line above.
>
>
[PATCH] drm/amd/display: Guard calls to hdcp_ta and dtm_ta
[Why]
The buffer used when calling psp is a shared buffer. If we have multiple calls
at the same time we can overwrite the buffer.
[How]
Add mutex to guard the shared buffer.
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 +
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 2 +
.../drm/amd/display/modules/hdcp/hdcp_psp.c | 420 +++---
3 files changed, 257 insertions(+), 167 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index dbaeffc4431e..9d587bc27663 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -888,6 +888,7 @@ static int psp_hdcp_load(struct psp_context *psp)
if (!ret) {
psp->hdcp_context.hdcp_initialized = true;
psp->hdcp_context.session_id = cmd->resp.session_id;
+ mutex_init(>hdcp_context.mutex);
}
kfree(cmd);
@@ -1033,6 +1034,7 @@ static int psp_dtm_load(struct psp_context *psp)
if (!ret) {
psp->dtm_context.dtm_initialized = true;
psp->dtm_context.session_id = cmd->resp.session_id;
+ mutex_init(>dtm_context.mutex);
}
kfree(cmd);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index 297435c0c7c1..6a717fd5efc7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -161,6 +161,7 @@ struct psp_hdcp_context {
struct amdgpu_bo*hdcp_shared_bo;
uint64_thdcp_shared_mc_addr;
void*hdcp_shared_buf;
+ struct mutexmutex;
};
struct psp_dtm_context {
@@ -169,6 +170,7 @@ struct psp_dtm_context {
struct amdgpu_bo*dtm_shared_bo;
uint64_tdtm_shared_mc_addr;
void*dtm_shared_buf;
+ struct mutexmutex;
};
#define MEM_TRAIN_SYSTEM_SIGNATURE 0x54534942
diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
index c2929815c3ee..aa147e171557 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
@@ -51,12 +51,15 @@ enum mod_hdcp_status mod_hdcp_remove_display_from_topology(
struct ta_dtm_shared_memory *dtm_cmd;
struct mod_hdcp_display *display =
get_active_display_at_index(hdcp, index);
+ enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
dtm_cmd = (struct ta_dtm_shared_memory
*)psp->dtm_context.dtm_shared_buf;
if (!display || !is_display_added(display))
return MOD_HDCP_STATUS_DISPLAY_NOT_FOUND;
+ mutex_lock(>dtm_context.mutex);
+
memset(dtm_cmd, 0, sizeof(struct ta_dtm_shared_memory));
dtm_cmd->cmd_id = TA_DTM_COMMAND__TOPOLOGY_UPDATE_V2;
@@ -66,14 +69,15 @@ enum mod_hdcp_status mod_hdcp_remove_display_from_topology(
psp_dtm_invoke(psp, dtm_cmd->cmd_id);
- if (dtm_cmd->dtm_status != TA_DTM_STATUS__SUCCESS)
- return MOD_HDCP_STATUS_UPDATE_TOPOLOGY_FAILURE;
+ if (dtm_cmd->dtm_status != TA_DTM_STATUS__SUCCESS) {
+ status = MOD_HDCP_STATUS_UPDATE_TOPOLOGY_FAILURE;
+ } else {
+ display->state = MOD_HDCP_DISPLAY_ACTIVE;
+ HDCP_TOP_REMOVE_DISPLAY_TRACE(hdcp, display->index);
+ }
- display->state = MOD_HDCP_DISPLAY_ACTIVE;
- HDCP_TOP_REMOVE_DISPLAY_TRACE(hdcp, display->index);
-
- return MOD_HDCP_STATUS_SUCCESS;
-
+ mutex_unlock(>dtm_context.mutex);
+ return status;
}
enum mod_hdcp_status mod_hdcp_add_display_to_topology(struct mod_hdcp *hdcp,
uint8_t index)
@@ -83,6 +87,7 @@ enum mod_hdcp_status mod_hdcp_add_display_to_topology(struct
mod_hdcp *hdcp,
struct mod_hdcp_display *display =
get_active_display_at_index(hdcp, index);
struct mod_hdcp_link *link = >connection.link;
+ enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
if (!psp->dtm_context.dtm_initialized) {
DRM_ERROR("Failed to add display topology, DTM TA is not
initialized.");
@@ -94,6 +99,7 @@ enum mod_hdcp_status mod_hdcp_add_display_to_topology(struct
mod_hdcp *hdcp,
dtm_cmd = (struct ta_dtm_shared_memory
*)psp->dtm_context.dtm_shared_buf;
+ mutex_lock(>dtm_context.mutex);
memset(dtm_cmd, 0, sizeof(struct ta_dtm_shared_memory));
dtm_cmd->cmd_id = TA_DTM_COMMAND__TOPOLOGY_UPDATE_V2;
@@ -113,13 +119,15 @@ enum mod_hdcp_status
mod_hdcp_add_display_to_topology(struct mod_hdcp *hdcp,
psp_dtm_invoke(psp, dtm_cmd->cmd_id);
- if (dtm_cmd->dtm_status != TA_DTM_STATUS__SUCCESS)
- return
Re: [PATCH 3/3] drm/amd/display: increase HDCP authentication delay
On 2020-03-30 2:00 p.m., Bhawanpreet Lakha wrote: [Why] Some displays have an issue where the hdcp chips are initialized after the display has already lit up. This means we can sometimes authentication too early and cause authentication failures. This happens when HDCP is enabled and the display is power cycled. Normally we will authenticate 2 seconds after the display is lit, but some displays need a bit more time. [How] Increase delay to 3 second before we start authentication. Signed-off-by: Bhawanpreet Lakha Series is: Reviewed-by: Nicholas Kazlauskas Regards, Nicholas Kazlauskas --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c index 39804d2df9df..78e1c11d4ae5 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c @@ -419,7 +419,7 @@ static void update_config(void *handle, struct cp_psp_stream_config *config) link->dp.rev = aconnector->dc_link->dpcd_caps.dpcd_rev.raw; link->dp.mst_supported = config->mst_supported; display->adjust.disable = 1; - link->adjust.auth_delay = 2; + link->adjust.auth_delay = 3; link->adjust.hdcp1.disable = 0; hdcp_update_display(hdcp_work, link_index, aconnector, DRM_MODE_HDCP_CONTENT_TYPE0, false); ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 3/3] drm/amd/display: increase HDCP authentication delay
[Why] Some displays have an issue where the hdcp chips are initialized after the display has already lit up. This means we can sometimes authentication too early and cause authentication failures. This happens when HDCP is enabled and the display is power cycled. Normally we will authenticate 2 seconds after the display is lit, but some displays need a bit more time. [How] Increase delay to 3 second before we start authentication. Signed-off-by: Bhawanpreet Lakha --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c index 39804d2df9df..78e1c11d4ae5 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c @@ -419,7 +419,7 @@ static void update_config(void *handle, struct cp_psp_stream_config *config) link->dp.rev = aconnector->dc_link->dpcd_caps.dpcd_rev.raw; link->dp.mst_supported = config->mst_supported; display->adjust.disable = 1; - link->adjust.auth_delay = 2; + link->adjust.auth_delay = 3; link->adjust.hdcp1.disable = 0; hdcp_update_display(hdcp_work, link_index, aconnector, DRM_MODE_HDCP_CONTENT_TYPE0, false); -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 2/3] drm/amd/display: Correctly cancel future watchdog and callback events
[Why] -We need to cancel future callbacks/watchdogs events when a callback/watchdog event happens [How] -fix typo in event_callback() -cancel callback, not watchdog -cancel watchdog events in event_watchdog_timer(). Signed-off-by: Bhawanpreet Lakha --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c index 41fd1f5acff4..39804d2df9df 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c @@ -266,7 +266,7 @@ static void event_callback(struct work_struct *work) mutex_lock(_work->mutex); - cancel_delayed_work(_work->watchdog_timer_dwork); + cancel_delayed_work(_work->callback_dwork); mod_hdcp_process_event(_work->hdcp, MOD_HDCP_EVENT_CALLBACK, _work->output); @@ -347,6 +347,8 @@ static void event_watchdog_timer(struct work_struct *work) mutex_lock(_work->mutex); + cancel_delayed_work(_work->watchdog_timer_dwork); + mod_hdcp_process_event(_work->hdcp, MOD_HDCP_EVENT_WATCHDOG_TIMEOUT, _work->output); -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 3/5] drm/amdgpu/vcn: Add firmware share memory support
On 2020-03-30 10:21 a.m., Leo Liu wrote:
On 2020-03-30 8:13 a.m., James Zhu wrote:
Added firmware share memory support for VCN. Current multiple
queue mode is enabled only.
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 13 +
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 24
2 files changed, 37 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 7a0b074..328b6ce 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -182,6 +182,14 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
return r;
}
}
+
+ r = amdgpu_bo_create_kernel(adev,
AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)),
+ PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
>vcn.inst[i].fw_shared_bo,
+ >vcn.inst[i].fw_shared_gpu_addr,
>vcn.inst[i].fw_shared_cpu_addr);
+ if (r) {
+ dev_err(adev->dev, "VCN %d (%d) failed to allocate
fimware shared bo\n", i, r);
+ return r;
+ }
}
return 0;
@@ -196,6 +204,11 @@ int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
if (adev->vcn.harvest_config & (1 << j))
continue;
+
+ amdgpu_bo_free_kernel(>vcn.inst[j].fw_shared_bo,
+ >vcn.inst[j].fw_shared_gpu_addr,
+ (void **)>vcn.inst[j].fw_shared_cpu_addr);
+
if (adev->vcn.indirect_sram) {
amdgpu_bo_free_kernel(>vcn.inst[j].dpg_sram_bo,
>vcn.inst[j].dpg_sram_gpu_addr,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index e913de8..853f0cc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -179,11 +179,14 @@ struct amdgpu_vcn_inst {
struct amdgpu_irq_src irq;
struct amdgpu_vcn_reg external;
struct amdgpu_bo *dpg_sram_bo;
+ struct amdgpu_bo *fw_shared_bo;
struct dpg_pause_state pause_state;
void *dpg_sram_cpu_addr;
uint64_t dpg_sram_gpu_addr;
uint32_t *dpg_sram_curr_addr;
atomic_t dpg_enc_submission_cnt;
+ void *fw_shared_cpu_addr;
+ uint64_t fw_shared_gpu_addr;
};
struct amdgpu_vcn {
@@ -209,6 +212,27 @@ struct amdgpu_vcn {
int inst_idx, struct dpg_pause_state *new_state);
};
+#define AMDGPU_VCN_MULTI_QUEUE_FLAG (1 << 8)
+
+enum fw_queue_mode {
+ fw_queue_ring_reset = 1,
+ fw_queue_dpg_hold_off = 2,
+};
Please move the define and enum to the top as others. With that fixed,
the series are
Sure. Can you review the patches also?
Thanks!
James
Reviewed-by: Leo Liu
+
+struct amdgpu_fw_shared_multi_queue {
+ uint8_t decode_queue_mode;
+ uint8_t encode_generalpurpose_queue_mode;
+ uint8_t encode_lowlatency_queue_mode;
+ uint8_t encode_realtime_queue_mode;
+ uint8_t padding[4];
+};
+
+struct amdgpu_fw_shared {
+ uint32_t present_flag_0;
+ uint8_t pad[53];
+ struct amdgpu_fw_shared_multi_queue multi_queue;
+} __attribute__((__packed__));
+
int amdgpu_vcn_sw_init(struct amdgpu_device *adev);
int amdgpu_vcn_sw_fini(struct amdgpu_device *adev);
int amdgpu_vcn_suspend(struct amdgpu_device *adev);
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[PATCH v3 1/1] drm/amdgpu: rework sched_list generation
Generate HW IP's sched_list in amdgpu_ring_init() instead of
amdgpu_ctx.c. This makes amdgpu_ctx_init_compute_sched(),
ring.has_high_prio and amdgpu_ctx_init_sched() unnecessary.
This patch also stores sched_list for all HW IPs in one big
array in struct amdgpu_device which makes amdgpu_ctx_init_entity()
much more leaner.
v2:
fix a coding style issue
do not use drm hw_ip const to populate amdgpu_ring_type enum
v3:
remove ctx reference and move sched array and num_sched to a struct
use num_scheds to detect uninitialized scheduler list
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 8 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c| 156 -
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h| 3 -
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 -
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c| 3 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h| 5 -
drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h | 2 -
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 24 +++-
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 12 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h | 2 -
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h| 4 -
drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 3 +-
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 13 +-
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 5 +-
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 5 +-
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 11 +-
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 13 +-
drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c | 3 +-
drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 3 +-
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c | 3 +-
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 3 +-
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 3 +-
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 6 +-
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 3 +-
drivers/gpu/drm/amd/amdgpu/si_dma.c| 3 +-
drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 3 +-
drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 3 +-
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 7 +-
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 6 +-
drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 3 +-
drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 3 +-
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 6 +-
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 6 +-
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 6 +-
35 files changed, 145 insertions(+), 198 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 29f0a410091b..27abbdc603dd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -721,6 +721,11 @@ struct amd_powerplay {
const struct amd_pm_funcs *pp_funcs;
};
+struct amdgpu_sched {
+ uint32_tnum_scheds;
+ struct drm_gpu_scheduler*sched[HWIP_MAX_INSTANCE];
+};
+
#define AMDGPU_RESET_MAGIC_NUM 64
#define AMDGPU_MAX_DF_PERFMONS 4
struct amdgpu_device {
@@ -858,6 +863,8 @@ struct amdgpu_device {
struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
boolib_pool_ready;
struct amdgpu_sa_managerring_tmp_bo[AMDGPU_IB_POOL_MAX];
+ /* drm scheduler list */
+ struct amdgpu_sched
gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX];
/* interrupts */
struct amdgpu_irq irq;
@@ -993,6 +1000,7 @@ struct amdgpu_device {
charproduct_number[16];
charproduct_name[32];
charserial[16];
+
};
static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index 6ed36a2c5f73..331646d472e2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -72,13 +72,30 @@ static enum gfx_pipe_priority
amdgpu_ctx_sched_prio_to_compute_prio(enum drm_sch
}
}
+static unsigned int amdgpu_ctx_sched_prio_to_hw_prio(struct amdgpu_device
*adev,
+enum drm_sched_priority
prio,
+const int hw_ip)
+{
+ unsigned int hw_prio;
+
+ hw_prio = (hw_ip == AMDGPU_HW_IP_COMPUTE) ?
+ amdgpu_ctx_sched_prio_to_compute_prio(prio) :
+ AMDGPU_RING_PRIO_DEFAULT;
+
+ /* set to default prio if sched_list is NULL */
+ if (!adev->gpu_sched[hw_ip][hw_prio].num_scheds)
+ hw_prio = AMDGPU_RING_PRIO_DEFAULT;
+
+ return hw_prio;
+}
+
static int amdgpu_ctx_init_entity(struct amdgpu_ctx *ctx, const u32 hw_ip,
const u32 ring)
{
struct amdgpu_device *adev = ctx->adev;
struct amdgpu_ctx_entity *entity;
struct drm_gpu_scheduler **scheds =
Re: [PATCH] Revert "drm/amdgpu: replace ih ip block for vega20 and arcturus"
Am 2020-03-30 um 11:24 a.m. schrieb Alex Sierra:
> This reverts commit 6237cb9febd7d61780d281e7141e12462c81cfb8.
> Due to Loading driver failed at "*ERROR* ring sdma0 test failed" issue:
> SWDEV-229211
The Jira ticket is not visible to the public. Therefore please include
more information about the error in the change description. At least,
which ASIC is failing.
You're also missing a Signed-off-by line. With that fixed, the patch is
Reviewed-by: Felix Kuehling
> ---
> drivers/gpu/drm/amd/amdgpu/soc15.c | 15 ---
> 1 file changed, 4 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
> b/drivers/gpu/drm/amd/amdgpu/soc15.c
> index 9bd965e88bd9..a8c90d83a9ee 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> @@ -62,7 +62,6 @@
> #include "nbio_v7_0.h"
> #include "nbio_v7_4.h"
> #include "vega10_ih.h"
> -#include "navi10_ih.h"
> #include "sdma_v4_0.h"
> #include "uvd_v7_0.h"
> #include "vce_v4_0.h"
> @@ -732,15 +731,9 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
> else
> amdgpu_device_ip_block_add(adev,
> _v3_1_ip_block);
> }
> - if (adev->asic_type == CHIP_VEGA20)
> - amdgpu_device_ip_block_add(adev,
> _ih_ip_block);
> - else
> - amdgpu_device_ip_block_add(adev,
> _ih_ip_block);
> + amdgpu_device_ip_block_add(adev, _ih_ip_block);
> } else {
> - if (adev->asic_type == CHIP_VEGA20)
> - amdgpu_device_ip_block_add(adev,
> _ih_ip_block);
> - else
> - amdgpu_device_ip_block_add(adev,
> _ih_ip_block);
> + amdgpu_device_ip_block_add(adev, _ih_ip_block);
> if (likely(adev->firmware.load_type ==
> AMDGPU_FW_LOAD_PSP)) {
> if (adev->asic_type == CHIP_VEGA20)
> amdgpu_device_ip_block_add(adev,
> _v11_0_ip_block);
> @@ -791,9 +784,9 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
> if (amdgpu_sriov_vf(adev)) {
> if (likely(adev->firmware.load_type ==
> AMDGPU_FW_LOAD_PSP))
> amdgpu_device_ip_block_add(adev,
> _v11_0_ip_block);
> - amdgpu_device_ip_block_add(adev, _ih_ip_block);
> + amdgpu_device_ip_block_add(adev, _ih_ip_block);
> } else {
> - amdgpu_device_ip_block_add(adev, _ih_ip_block);
> + amdgpu_device_ip_block_add(adev, _ih_ip_block);
> if (likely(adev->firmware.load_type ==
> AMDGPU_FW_LOAD_PSP))
> amdgpu_device_ip_block_add(adev,
> _v11_0_ip_block);
> }
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[PATCH] Revert "drm/amdgpu: replace ih ip block for vega20 and arcturus"
This reverts commit 6237cb9febd7d61780d281e7141e12462c81cfb8.
Due to Loading driver failed at "*ERROR* ring sdma0 test failed" issue:
SWDEV-229211
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 15 ---
1 file changed, 4 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 9bd965e88bd9..a8c90d83a9ee 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -62,7 +62,6 @@
#include "nbio_v7_0.h"
#include "nbio_v7_4.h"
#include "vega10_ih.h"
-#include "navi10_ih.h"
#include "sdma_v4_0.h"
#include "uvd_v7_0.h"
#include "vce_v4_0.h"
@@ -732,15 +731,9 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
else
amdgpu_device_ip_block_add(adev,
_v3_1_ip_block);
}
- if (adev->asic_type == CHIP_VEGA20)
- amdgpu_device_ip_block_add(adev,
_ih_ip_block);
- else
- amdgpu_device_ip_block_add(adev,
_ih_ip_block);
+ amdgpu_device_ip_block_add(adev, _ih_ip_block);
} else {
- if (adev->asic_type == CHIP_VEGA20)
- amdgpu_device_ip_block_add(adev,
_ih_ip_block);
- else
- amdgpu_device_ip_block_add(adev,
_ih_ip_block);
+ amdgpu_device_ip_block_add(adev, _ih_ip_block);
if (likely(adev->firmware.load_type ==
AMDGPU_FW_LOAD_PSP)) {
if (adev->asic_type == CHIP_VEGA20)
amdgpu_device_ip_block_add(adev,
_v11_0_ip_block);
@@ -791,9 +784,9 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
if (amdgpu_sriov_vf(adev)) {
if (likely(adev->firmware.load_type ==
AMDGPU_FW_LOAD_PSP))
amdgpu_device_ip_block_add(adev,
_v11_0_ip_block);
- amdgpu_device_ip_block_add(adev, _ih_ip_block);
+ amdgpu_device_ip_block_add(adev, _ih_ip_block);
} else {
- amdgpu_device_ip_block_add(adev, _ih_ip_block);
+ amdgpu_device_ip_block_add(adev, _ih_ip_block);
if (likely(adev->firmware.load_type ==
AMDGPU_FW_LOAD_PSP))
amdgpu_device_ip_block_add(adev,
_v11_0_ip_block);
}
--
2.17.1
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Re: [PATCH] drm/amd/display: add basic atomic check for cursor plane
On Monday, March 30, 2020 5:18 PM, Kazlauskas, Nicholas wrote: > On 2020-03-30 9:13 a.m., Simon Ser wrote: > > > On Monday, March 30, 2020 3:11 PM, Kazlauskas, Nicholas > > nicholas.kazlaus...@amd.com wrote: > > > > > On 2020-03-30 9:02 a.m., Simon Ser wrote: > > > > > > > On Monday, March 30, 2020 2:59 PM, Kazlauskas, Nicholas > > > > nicholas.kazlaus...@amd.com wrote: > > > > > > > > > We've been doing these checks for position before but I don't think we > > > > > really need them. DC should be disabling the cursor when we ask for a > > > > > position completely off the screen. > > > > > I think that's better than rejecting the commit entirely at least. > > > > > > > > I agree DC should be disabling the cursor in this case, however that's > > > > not yet implemented right? I think implementing this feature is > > > > orthogonal and should be done in a separate patch. > > > > This patch simply copies over the cursor checks in the atomic check > > > > function. > > > > > > It's implemented on DCN but I don't remember if we're doing it on DCE. > > > I guess the drop can be in a separate patch. > > > Reviewed-by: Nicholas Kazlauskas nicholas.kazlaus...@amd.com > > > > Thanks for the review. I'll try to figure out whether we can drop this > > check (from both the atomic check and the other existing check). > > Oh, this was actually the checks for crtc_w/crtc_h. Not the x/y, my bad. > > We probably can't drop this from here, but we can drop it from > get_cursor_position after this patch - since it's now in the atomic check. Hmm, sorry I think I missed something. This patch does copy over the x/y checks. We need to keep the w/h checks right? Yeah, we can probably drop get_cursor_position checks indeed. ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amd/display: add basic atomic check for cursor plane
On 2020-03-30 9:13 a.m., Simon Ser wrote: On Monday, March 30, 2020 3:11 PM, Kazlauskas, Nicholas wrote: On 2020-03-30 9:02 a.m., Simon Ser wrote: On Monday, March 30, 2020 2:59 PM, Kazlauskas, Nicholas nicholas.kazlaus...@amd.com wrote: We've been doing these checks for position before but I don't think we really need them. DC should be disabling the cursor when we ask for a position completely off the screen. I think that's better than rejecting the commit entirely at least. I agree DC should be disabling the cursor in this case, however that's not yet implemented right? I think implementing this feature is orthogonal and should be done in a separate patch. This patch simply copies over the cursor checks in the atomic check function. It's implemented on DCN but I don't remember if we're doing it on DCE. I guess the drop can be in a separate patch. Reviewed-by: Nicholas Kazlauskas Thanks for the review. I'll try to figure out whether we can drop this check (from both the atomic check and the other existing check). Oh, this was actually the checks for crtc_w/crtc_h. Not the x/y, my bad. We probably can't drop this from here, but we can drop it from get_cursor_position after this patch - since it's now in the atomic check. Thanks, Nicholas Kazlauskas ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH v3] PCI: Use ioremap(), not phys_to_virt() for platform ROM
On Mon, Mar 30, 2020 at 01:54:33PM +, Deucher, Alexander wrote: > > -Original Message- > > From: Bjorn Helgaas > > Sent: Saturday, March 28, 2020 4:19 PM > > To: Mikel Rychliski > > Cc: amd-gfx@lists.freedesktop.org; linux-...@vger.kernel.org; > > nouv...@lists.freedesktop.org; Deucher, Alexander > > ; Koenig, Christian > > ; Zhou, David(ChunMing) > > ; Matthew Garrett > > ; Ben Skeggs ; > > Christoph Hellwig > > Subject: Re: [PATCH v3] PCI: Use ioremap(), not phys_to_virt() for platform > > ROM > > > > On Wed, Mar 18, 2020 at 10:16:23PM -0400, Mikel Rychliski wrote: > > > On some EFI systems, the video BIOS is provided by the EFI firmware. > > > The boot stub code stores the physical address of the ROM image in pdev- > > >rom. > > > Currently we attempt to access this pointer using phys_to_virt(), > > > which doesn't work with CONFIG_HIGHMEM. > > > > > > On these systems, attempting to load the radeon module on a x86_32 > > > kernel can result in the following: > > > > > > BUG: unable to handle page fault for address: 3e8ed03c > > > #PF: supervisor read access in kernel mode > > > #PF: error_code(0x) - not-present page > > > *pde = > > > Oops: [#1] PREEMPT SMP > > > CPU: 0 PID: 317 Comm: systemd-udevd Not tainted 5.6.0-rc3-next- > > 20200228 #2 > > > Hardware name: Apple Computer, Inc. MacPro1,1/Mac-F4208DC8, BIOS > > MP11.88Z.005C.B08.0707021221 07/02/07 > > > EIP: radeon_get_bios+0x5ed/0xe50 [radeon] > > > Code: 00 00 84 c0 0f 85 12 fd ff ff c7 87 64 01 00 00 00 00 00 00 8b > > > 47 08 8b > > 55 b0 e8 1e 83 e1 d6 85 c0 74 1a 8b 55 c0 85 d2 74 13 <80> 38 55 75 0e 80 > > 78 01 > > aa 0f 84 a4 03 00 00 8d 74 26 00 68 dc 06 > > > EAX: 3e8ed03c EBX: ECX: 3e8ed03c EDX: 0001 > > > ESI: 0004 EDI: eec04000 EBP: eef3fc60 ESP: eef3fbe0 > > > DS: 007b ES: 007b FS: 00d8 GS: 00e0 SS: 0068 EFLAGS: 00010206 > > > CR0: 80050033 CR2: 3e8ed03c CR3: 2ec77000 CR4: 06d0 > > > Call Trace: > > > ? register_client+0x34/0xe0 > > > ? register_client+0xab/0xe0 > > > r520_init+0x26/0x240 [radeon] > > > radeon_device_init+0x533/0xa50 [radeon] > > > radeon_driver_load_kms+0x80/0x220 [radeon] > > > drm_dev_register+0xa7/0x180 [drm] > > > radeon_pci_probe+0x10f/0x1a0 [radeon] > > > pci_device_probe+0xd4/0x140 > > > really_probe+0x13d/0x3b0 > > > driver_probe_device+0x56/0xd0 > > > device_driver_attach+0x49/0x50 > > > __driver_attach+0x79/0x130 > > > ? device_driver_attach+0x50/0x50 > > > bus_for_each_dev+0x5b/0xa0 > > > driver_attach+0x19/0x20 > > > ? device_driver_attach+0x50/0x50 > > > bus_add_driver+0x117/0x1d0 > > > ? pci_bus_num_vf+0x20/0x20 > > > driver_register+0x66/0xb0 > > > ? 0xf80f4000 > > > __pci_register_driver+0x3d/0x40 > > > radeon_init+0x82/0x1000 [radeon] > > > do_one_initcall+0x42/0x200 > > > ? kvfree+0x25/0x30 > > > ? __vunmap+0x206/0x230 > > > ? kmem_cache_alloc_trace+0x16f/0x220 > > > ? do_init_module+0x21/0x220 > > > do_init_module+0x50/0x220 > > > load_module+0x1f26/0x2200 > > > sys_init_module+0x12d/0x160 > > > do_fast_syscall_32+0x82/0x250 > > > entry_SYSENTER_32+0xa5/0xf8 > > > > > > Fix the issue by updating all drivers which can access a platform > > > provided ROM. Instead of calling the helper function > > > pci_platform_rom() which uses phys_to_virt(), call ioremap() directly on > > the pdev->rom. > > > > > > radeon_read_platform_bios() previously directly accessed an __iomem > > > pointer. Avoid this by calling memcpy_fromio() instead of kmemdup(). > > > > > > pci_platform_rom() now has no remaining callers, so remove it. > > > > > > Signed-off-by: Mikel Rychliski > > > > I applied this to pci/resource for v5.7. I would feel better if some of the > > graphics guys chimed in, or even applied it via the DRM tree since most of > > the > > changes are actually in drivers/gpu. > > Feel free to take it through the PCI tree. These areas of radeon and amdgpu > don't really change much at all so, I'm not too concerned about a conflict. > > Acked-by: Alex Deucher Thanks, I added your ack, and this is queued up for v5.7. > > Feel free to add my > > > > Acked-by: Bjorn Helgaas > > > > and let me know if you do that. > > > > > --- > > > > > > Tested on a MacPro 1,1 with a Radeon X1900 XT card and 32-bit kernel. > > > > > > Changes in v3: > > > - Inline pci_platform_rom() > > > > > > Changes in v2: > > > - Add iounmap() call in nouveau > > > - Update function comment for pci_platform_rom() > > > - Minor changes to commit messages > > > > > > drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c | 31 > > +- > > > .../gpu/drm/nouveau/nvkm/subdev/bios/shadowpci.c | 17 ++- > > - > > > drivers/gpu/drm/radeon/radeon_bios.c | 30 > > > +--- > > - > > > drivers/pci/rom.c
Re: [PATCH v2 1/1] drm/amdgpu: rework sched_list generation
On 3/30/20 4:13 PM, Christian König wrote:
Am 30.03.20 um 16:02 schrieb Nirmoy Das:
Generate HW IP's sched_list in amdgpu_ring_init() instead of
amdgpu_ctx.c. This makes amdgpu_ctx_init_compute_sched(),
ring.has_high_prio and amdgpu_ctx_init_sched() unnecessary.
This patch also stores sched_list for all HW IPs in one big
array in struct amdgpu_device which makes amdgpu_ctx_init_entity()
much more leaner.
v2:
fix a coding style issue
do not use drm hw_ip const to populate amdgpu_ring_type enum
Signed-off-by: Nirmoy Das
Acked-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 156 -
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h | 3 -
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 -
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 3 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 5 -
drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h | 2 -
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 24 +++-
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 12 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h | 2 -
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 4 -
drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 3 +-
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 13 +-
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 5 +-
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 5 +-
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 11 +-
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 13 +-
drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c | 3 +-
drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 3 +-
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c | 3 +-
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 3 +-
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 3 +-
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 6 +-
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 3 +-
drivers/gpu/drm/amd/amdgpu/si_dma.c | 3 +-
drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 3 +-
drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 3 +-
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 7 +-
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 6 +-
drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 3 +-
drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 3 +-
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 6 +-
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 6 +-
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 6 +-
35 files changed, 141 insertions(+), 198 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 29f0a410091b..100f45ed1bfb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -993,6 +993,10 @@ struct amdgpu_device {
char product_number[16];
char product_name[32];
char serial[16];
+
+ /* drm scheduler list */
+ struct drm_gpu_scheduler
*ctx_scheds[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX][AMDGPU_MAX_COMPUTE_RINGS];
+ uint32_t ctx_num_scheds[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX];
As far as I can see this is not related to the userspace ctx any more,
so having ctx in the name doesn't really fit that well any more.
You should probably rather put it close to the rings stuff and maybe
better group that together.
E.g. something like this:
struct {
uint32_t num_scheds;
struct drm_gpu_scheduler
*sched[AMDGPU_MAX_COMPUTE_RINGS];
} gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX];
Thanks Christian, I will update accordingly.
};
static inline struct amdgpu_device *amdgpu_ttm_adev(struct
ttm_bo_device *bdev)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index 6ed36a2c5f73..317d4ffd98fa 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -72,13 +72,30 @@ static enum gfx_pipe_priority
amdgpu_ctx_sched_prio_to_compute_prio(enum drm_sch
}
}
+static unsigned int amdgpu_ctx_sched_prio_to_hw_prio(struct
amdgpu_device *adev,
+ enum drm_sched_priority prio,
+ const int hw_ip)
+{
+ unsigned int hw_prio;
+
+ hw_prio = (hw_ip == AMDGPU_HW_IP_COMPUTE) ?
+ amdgpu_ctx_sched_prio_to_compute_prio(prio) :
+ AMDGPU_RING_PRIO_DEFAULT;
+
+ /* set to default prio if sched_list is NULL */
+ if (!adev->ctx_scheds[hw_ip][hw_prio][0])
It's probably cleaner to check the number of schedulers here instead
of checking if the first one is NULL.
Yes I should use num_scheds here.
Regards,
Nirmoy
Regards,
Christian.
+ hw_prio = AMDGPU_RING_PRIO_DEFAULT;
+
+ return hw_prio;
+}
+
static int amdgpu_ctx_init_entity(struct amdgpu_ctx *ctx, const u32
hw_ip, const u32 ring)
{
struct amdgpu_device *adev = ctx->adev;
struct amdgpu_ctx_entity
Re: [PATCH 3/5] drm/amdgpu/vcn: Add firmware share memory support
On 2020-03-30 8:13 a.m., James Zhu wrote:
Added firmware share memory support for VCN. Current multiple
queue mode is enabled only.
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 13 +
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 24
2 files changed, 37 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 7a0b074..328b6ce 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -182,6 +182,14 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
return r;
}
}
+
+ r = amdgpu_bo_create_kernel(adev,
AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)),
+ PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
>vcn.inst[i].fw_shared_bo,
+ >vcn.inst[i].fw_shared_gpu_addr,
>vcn.inst[i].fw_shared_cpu_addr);
+ if (r) {
+ dev_err(adev->dev, "VCN %d (%d) failed to allocate fimware
shared bo\n", i, r);
+ return r;
+ }
}
return 0;
@@ -196,6 +204,11 @@ int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
if (adev->vcn.harvest_config & (1 << j))
continue;
+
+ amdgpu_bo_free_kernel(>vcn.inst[j].fw_shared_bo,
+ >vcn.inst[j].fw_shared_gpu_addr,
+ (void
**)>vcn.inst[j].fw_shared_cpu_addr);
+
if (adev->vcn.indirect_sram) {
amdgpu_bo_free_kernel(>vcn.inst[j].dpg_sram_bo,
>vcn.inst[j].dpg_sram_gpu_addr,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index e913de8..853f0cc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -179,11 +179,14 @@ struct amdgpu_vcn_inst {
struct amdgpu_irq_src irq;
struct amdgpu_vcn_reg external;
struct amdgpu_bo*dpg_sram_bo;
+ struct amdgpu_bo*fw_shared_bo;
struct dpg_pause_state pause_state;
void*dpg_sram_cpu_addr;
uint64_tdpg_sram_gpu_addr;
uint32_t*dpg_sram_curr_addr;
atomic_tdpg_enc_submission_cnt;
+ void*fw_shared_cpu_addr;
+ uint64_tfw_shared_gpu_addr;
};
struct amdgpu_vcn {
@@ -209,6 +212,27 @@ struct amdgpu_vcn {
int inst_idx, struct dpg_pause_state *new_state);
};
+#define AMDGPU_VCN_MULTI_QUEUE_FLAG(1 << 8)
+
+enum fw_queue_mode {
+ fw_queue_ring_reset = 1,
+ fw_queue_dpg_hold_off = 2,
+};
Please move the define and enum to the top as others. With that fixed,
the series are
Reviewed-by: Leo Liu
+
+struct amdgpu_fw_shared_multi_queue {
+ uint8_t decode_queue_mode;
+ uint8_t encode_generalpurpose_queue_mode;
+ uint8_t encode_lowlatency_queue_mode;
+ uint8_t encode_realtime_queue_mode;
+ uint8_t padding[4];
+};
+
+struct amdgpu_fw_shared {
+ uint32_t present_flag_0;
+ uint8_t pad[53];
+ struct amdgpu_fw_shared_multi_queue multi_queue;
+} __attribute__((__packed__));
+
int amdgpu_vcn_sw_init(struct amdgpu_device *adev);
int amdgpu_vcn_sw_fini(struct amdgpu_device *adev);
int amdgpu_vcn_suspend(struct amdgpu_device *adev);
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Re: [PATCH v2 1/1] drm/amdgpu: rework sched_list generation
Am 30.03.20 um 16:02 schrieb Nirmoy Das:
Generate HW IP's sched_list in amdgpu_ring_init() instead of
amdgpu_ctx.c. This makes amdgpu_ctx_init_compute_sched(),
ring.has_high_prio and amdgpu_ctx_init_sched() unnecessary.
This patch also stores sched_list for all HW IPs in one big
array in struct amdgpu_device which makes amdgpu_ctx_init_entity()
much more leaner.
v2:
fix a coding style issue
do not use drm hw_ip const to populate amdgpu_ring_type enum
Signed-off-by: Nirmoy Das
Acked-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 4 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c| 156 -
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h| 3 -
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 -
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c| 3 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h| 5 -
drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h | 2 -
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 24 +++-
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 12 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h | 2 -
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h| 4 -
drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 3 +-
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 13 +-
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 5 +-
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 5 +-
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 11 +-
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 13 +-
drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c | 3 +-
drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 3 +-
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c | 3 +-
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 3 +-
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 3 +-
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 6 +-
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 3 +-
drivers/gpu/drm/amd/amdgpu/si_dma.c| 3 +-
drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 3 +-
drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 3 +-
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 7 +-
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 6 +-
drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 3 +-
drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 3 +-
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 6 +-
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 6 +-
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 6 +-
35 files changed, 141 insertions(+), 198 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 29f0a410091b..100f45ed1bfb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -993,6 +993,10 @@ struct amdgpu_device {
charproduct_number[16];
charproduct_name[32];
charserial[16];
+
+ /* drm scheduler list */
+ struct drm_gpu_scheduler
*ctx_scheds[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX][AMDGPU_MAX_COMPUTE_RINGS];
+ uint32_t
ctx_num_scheds[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX];
As far as I can see this is not related to the userspace ctx any more,
so having ctx in the name doesn't really fit that well any more.
You should probably rather put it close to the rings stuff and maybe
better group that together.
E.g. something like this:
struct {
uint32_t num_scheds;
struct drm_gpu_scheduler *sched[AMDGPU_MAX_COMPUTE_RINGS];
} gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX];
};
static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device
*bdev)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index 6ed36a2c5f73..317d4ffd98fa 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -72,13 +72,30 @@ static enum gfx_pipe_priority
amdgpu_ctx_sched_prio_to_compute_prio(enum drm_sch
}
}
+static unsigned int amdgpu_ctx_sched_prio_to_hw_prio(struct amdgpu_device
*adev,
+enum drm_sched_priority
prio,
+const int hw_ip)
+{
+ unsigned int hw_prio;
+
+ hw_prio = (hw_ip == AMDGPU_HW_IP_COMPUTE) ?
+ amdgpu_ctx_sched_prio_to_compute_prio(prio) :
+ AMDGPU_RING_PRIO_DEFAULT;
+
+ /* set to default prio if sched_list is NULL */
+ if (!adev->ctx_scheds[hw_ip][hw_prio][0])
It's probably cleaner to check the number of schedulers here instead of
checking if the first one is NULL.
Regards,
Christian.
+ hw_prio = AMDGPU_RING_PRIO_DEFAULT;
+
+ return hw_prio;
+}
+
static int amdgpu_ctx_init_entity(struct amdgpu_ctx *ctx, const u32 hw_ip,
const u32 ring)
{
struct amdgpu_device *adev = ctx->adev;
struct
[PATCH v2 1/1] drm/amdgpu: rework sched_list generation
Generate HW IP's sched_list in amdgpu_ring_init() instead of
amdgpu_ctx.c. This makes amdgpu_ctx_init_compute_sched(),
ring.has_high_prio and amdgpu_ctx_init_sched() unnecessary.
This patch also stores sched_list for all HW IPs in one big
array in struct amdgpu_device which makes amdgpu_ctx_init_entity()
much more leaner.
v2:
fix a coding style issue
do not use drm hw_ip const to populate amdgpu_ring_type enum
Signed-off-by: Nirmoy Das
Acked-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 4 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c| 156 -
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h| 3 -
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 -
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c| 3 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h| 5 -
drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h | 2 -
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 24 +++-
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 12 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h | 2 -
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h| 4 -
drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 3 +-
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 13 +-
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 5 +-
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 5 +-
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 11 +-
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 13 +-
drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c | 3 +-
drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 3 +-
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c | 3 +-
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 3 +-
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 3 +-
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 6 +-
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 3 +-
drivers/gpu/drm/amd/amdgpu/si_dma.c| 3 +-
drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 3 +-
drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 3 +-
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 7 +-
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 6 +-
drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 3 +-
drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 3 +-
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 6 +-
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 6 +-
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 6 +-
35 files changed, 141 insertions(+), 198 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 29f0a410091b..100f45ed1bfb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -993,6 +993,10 @@ struct amdgpu_device {
charproduct_number[16];
charproduct_name[32];
charserial[16];
+
+ /* drm scheduler list */
+ struct drm_gpu_scheduler
*ctx_scheds[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX][AMDGPU_MAX_COMPUTE_RINGS];
+ uint32_t
ctx_num_scheds[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX];
};
static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index 6ed36a2c5f73..317d4ffd98fa 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -72,13 +72,30 @@ static enum gfx_pipe_priority
amdgpu_ctx_sched_prio_to_compute_prio(enum drm_sch
}
}
+static unsigned int amdgpu_ctx_sched_prio_to_hw_prio(struct amdgpu_device
*adev,
+enum drm_sched_priority
prio,
+const int hw_ip)
+{
+ unsigned int hw_prio;
+
+ hw_prio = (hw_ip == AMDGPU_HW_IP_COMPUTE) ?
+ amdgpu_ctx_sched_prio_to_compute_prio(prio) :
+ AMDGPU_RING_PRIO_DEFAULT;
+
+ /* set to default prio if sched_list is NULL */
+ if (!adev->ctx_scheds[hw_ip][hw_prio][0])
+ hw_prio = AMDGPU_RING_PRIO_DEFAULT;
+
+ return hw_prio;
+}
+
static int amdgpu_ctx_init_entity(struct amdgpu_ctx *ctx, const u32 hw_ip,
const u32 ring)
{
struct amdgpu_device *adev = ctx->adev;
struct amdgpu_ctx_entity *entity;
struct drm_gpu_scheduler **scheds = NULL, *sched = NULL;
unsigned num_scheds = 0;
- enum gfx_pipe_priority hw_prio;
+ unsigned int hw_prio;
enum drm_sched_priority priority;
int r;
@@ -90,52 +107,16 @@ static int amdgpu_ctx_init_entity(struct amdgpu_ctx *ctx,
const u32 hw_ip, const
entity->sequence = 1;
priority = (ctx->override_priority == DRM_SCHED_PRIORITY_UNSET) ?
ctx->init_priority : ctx->override_priority;
- switch (hw_ip) {
- case AMDGPU_HW_IP_GFX:
- sched = >gfx.gfx_ring[0].sched;
- scheds =
- num_scheds = 1;
-
[PATCH 3/6] drm/amdgpu: note that we can handle peer2peer DMA-buf
Importing should work out of the box.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
index ffeb20f11c07..aef12ee2f1e3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
@@ -514,6 +514,7 @@ amdgpu_dma_buf_move_notify(struct dma_buf_attachment
*attach)
}
static const struct dma_buf_attach_ops amdgpu_dma_buf_attach_ops = {
+ .allow_peer2peer = true,
.move_notify = amdgpu_dma_buf_move_notify
};
--
2.17.1
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[PATCH 4/6] drm/amdgpu: add checks if DMA-buf P2P is supported
Check if we can do peer2peer on the PCIe bus. Signed-off-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index aef12ee2f1e3..bbf67800c8a6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -38,6 +38,7 @@ #include #include #include +#include /** * amdgpu_gem_prime_vmap - _buf_ops.vmap implementation @@ -179,6 +180,9 @@ static int amdgpu_dma_buf_attach(struct dma_buf *dmabuf, struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); int r; + if (pci_p2pdma_distance_many(adev->pdev, >dev, 1, true) < 0) + attach->peer2peer = false; + if (attach->dev->driver == adev->dev->driver) return 0; -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 2/6] drm/ttm: lock resv object during destruction
Calling ttm_bo_cleanup_memtype_use() destroys the TT object
which in turn could result in warnings without this.
Signed-off-by: Christian König
---
drivers/gpu/drm/ttm/ttm_bo.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index 9e07c3f75156..f73b81c2576e 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -588,7 +588,8 @@ static void ttm_bo_release(struct kref *kref)
ttm_mem_io_unlock(man);
}
- if (!dma_resv_test_signaled_rcu(bo->base.resv, true)) {
+ if (!dma_resv_test_signaled_rcu(bo->base.resv, true) ||
+ !dma_resv_trylock(bo->base.resv)) {
/* The BO is not idle, resurrect it for delayed destroy */
ttm_bo_flush_all_fences(bo);
bo->deleted = true;
@@ -621,6 +622,7 @@ static void ttm_bo_release(struct kref *kref)
spin_unlock(_bo_glob.lru_lock);
ttm_bo_cleanup_memtype_use(bo);
+ dma_resv_unlock(bo->base.resv);
BUG_ON(bo->mem.mm_node != NULL);
atomic_dec(_bo_glob.bo_count);
--
2.17.1
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[PATCH 1/6] dma-buf: add peer2peer flag
Add a peer2peer flag noting that the importer can deal with device
resources which are not backed by pages.
Signed-off-by: Christian König
---
drivers/dma-buf/dma-buf.c | 2 ++
include/linux/dma-buf.h | 10 ++
2 files changed, 12 insertions(+)
diff --git a/drivers/dma-buf/dma-buf.c b/drivers/dma-buf/dma-buf.c
index ccc9eda1bc28..570c923023e6 100644
--- a/drivers/dma-buf/dma-buf.c
+++ b/drivers/dma-buf/dma-buf.c
@@ -690,6 +690,8 @@ dma_buf_dynamic_attach(struct dma_buf *dmabuf, struct
device *dev,
attach->dev = dev;
attach->dmabuf = dmabuf;
+ if (importer_ops)
+ attach->peer2peer = importer_ops->allow_peer2peer;
attach->importer_ops = importer_ops;
attach->importer_priv = importer_priv;
diff --git a/include/linux/dma-buf.h b/include/linux/dma-buf.h
index 1ade486fc2bb..82e0a4a64601 100644
--- a/include/linux/dma-buf.h
+++ b/include/linux/dma-buf.h
@@ -334,6 +334,14 @@ struct dma_buf {
* Attachment operations implemented by the importer.
*/
struct dma_buf_attach_ops {
+ /**
+* @allow_peer2peer:
+*
+* If this is set to true the importer must be able to handle peer
+* resources without struct pages.
+*/
+ bool allow_peer2peer;
+
/**
* @move_notify
*
@@ -362,6 +370,7 @@ struct dma_buf_attach_ops {
* @node: list of dma_buf_attachment, protected by dma_resv lock of the dmabuf.
* @sgt: cached mapping.
* @dir: direction of cached mapping.
+ * @peer2peer: true if the importer can handle peer resources without pages.
* @priv: exporter specific attachment data.
* @importer_ops: importer operations for this attachment, if provided
* dma_buf_map/unmap_attachment() must be called with the dma_resv lock held.
@@ -382,6 +391,7 @@ struct dma_buf_attachment {
struct list_head node;
struct sg_table *sgt;
enum dma_data_direction dir;
+ bool peer2peer;
const struct dma_buf_attach_ops *importer_ops;
void *importer_priv;
void *priv;
--
2.17.1
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[PATCH 5/6] drm/amdgpu: add support for exporting VRAM using DMA-buf v3
We should be able to do this now after checking all the prerequisites.
v2: fix entrie count in the sgt
v3: manually construct the sg
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 56 ---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 12 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 99
3 files changed, 153 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
index bbf67800c8a6..43d8ed7dbd00 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
@@ -276,14 +276,21 @@ static struct sg_table *amdgpu_dma_buf_map(struct
dma_buf_attachment *attach,
struct dma_buf *dma_buf = attach->dmabuf;
struct drm_gem_object *obj = dma_buf->priv;
struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
+ struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
struct sg_table *sgt;
long r;
if (!bo->pin_count) {
- /* move buffer into GTT */
+ /* move buffer into GTT or VRAM */
struct ttm_operation_ctx ctx = { false, false };
+ unsigned domains = AMDGPU_GEM_DOMAIN_GTT;
- amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
+ if (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM &&
+ attach->peer2peer) {
+ bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
+ domains |= AMDGPU_GEM_DOMAIN_VRAM;
+ }
+ amdgpu_bo_placement_from_domain(bo, domains);
r = ttm_bo_validate(>tbo, >placement, );
if (r)
return ERR_PTR(r);
@@ -293,20 +300,34 @@ static struct sg_table *amdgpu_dma_buf_map(struct
dma_buf_attachment *attach,
return ERR_PTR(-EBUSY);
}
- sgt = drm_prime_pages_to_sg(bo->tbo.ttm->pages, bo->tbo.num_pages);
- if (IS_ERR(sgt))
- return sgt;
-
- if (!dma_map_sg_attrs(attach->dev, sgt->sgl, sgt->nents, dir,
- DMA_ATTR_SKIP_CPU_SYNC))
- goto error_free;
+ switch (bo->tbo.mem.mem_type) {
+ case TTM_PL_TT:
+ sgt = drm_prime_pages_to_sg(bo->tbo.ttm->pages,
+ bo->tbo.num_pages);
+ if (IS_ERR(sgt))
+ return sgt;
+
+ if (!dma_map_sg_attrs(attach->dev, sgt->sgl, sgt->nents, dir,
+ DMA_ATTR_SKIP_CPU_SYNC))
+ goto error_free;
+ break;
+
+ case TTM_PL_VRAM:
+ r = amdgpu_vram_mgr_alloc_sgt(adev, >tbo.mem, attach->dev,
+ dir, );
+ if (r)
+ return ERR_PTR(r);
+ break;
+ default:
+ return ERR_PTR(-EINVAL);
+ }
return sgt;
error_free:
sg_free_table(sgt);
kfree(sgt);
- return ERR_PTR(-ENOMEM);
+ return ERR_PTR(-EBUSY);
}
/**
@@ -322,9 +343,18 @@ static void amdgpu_dma_buf_unmap(struct dma_buf_attachment
*attach,
struct sg_table *sgt,
enum dma_data_direction dir)
{
- dma_unmap_sg(attach->dev, sgt->sgl, sgt->nents, dir);
- sg_free_table(sgt);
- kfree(sgt);
+ struct dma_buf *dma_buf = attach->dmabuf;
+ struct drm_gem_object *obj = dma_buf->priv;
+ struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
+ struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
+
+ if (sgt->sgl->page_link) {
+ dma_unmap_sg(attach->dev, sgt->sgl, sgt->nents, dir);
+ sg_free_table(sgt);
+ kfree(sgt);
+ } else {
+ amdgpu_vram_mgr_free_sgt(adev, attach->dev, dir, sgt);
+ }
}
/**
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
index bd05bbb4878d..6b22dc41ef13 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
@@ -24,8 +24,9 @@
#ifndef __AMDGPU_TTM_H__
#define __AMDGPU_TTM_H__
-#include "amdgpu.h"
+#include
#include
+#include "amdgpu.h"
#define AMDGPU_PL_GDS (TTM_PL_PRIV + 0)
#define AMDGPU_PL_GWS (TTM_PL_PRIV + 1)
@@ -74,6 +75,15 @@ uint64_t amdgpu_gtt_mgr_usage(struct ttm_mem_type_manager
*man);
int amdgpu_gtt_mgr_recover(struct ttm_mem_type_manager *man);
u64 amdgpu_vram_mgr_bo_visible_size(struct amdgpu_bo *bo);
+int amdgpu_vram_mgr_alloc_sgt(struct amdgpu_device *adev,
+ struct ttm_mem_reg *mem,
+ struct device *dev,
+ enum dma_data_direction dir,
+ struct sg_table **sgt);
+void
[PATCH 6/6] drm/amdgpu: improve amdgpu_gem_info debugfs file
Note if a buffer was imported using peer2peer. Signed-off-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 4277125a79ee..e42608115c99 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include @@ -854,7 +855,8 @@ static int amdgpu_debugfs_gem_bo_info(int id, void *ptr, void *data) attachment = READ_ONCE(bo->tbo.base.import_attach); if (attachment) - seq_printf(m, " imported from %p", dma_buf); + seq_printf(m, " imported from %p%s", dma_buf, + attachment->peer2peer ? " P2P" : ""); else if (dma_buf) seq_printf(m, " exported as %p", dma_buf); -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH v3] PCI: Use ioremap(), not phys_to_virt() for platform ROM
[AMD Public Use] > -Original Message- > From: Bjorn Helgaas > Sent: Saturday, March 28, 2020 4:19 PM > To: Mikel Rychliski > Cc: amd-gfx@lists.freedesktop.org; linux-...@vger.kernel.org; > nouv...@lists.freedesktop.org; Deucher, Alexander > ; Koenig, Christian > ; Zhou, David(ChunMing) > ; Matthew Garrett > ; Ben Skeggs ; > Christoph Hellwig > Subject: Re: [PATCH v3] PCI: Use ioremap(), not phys_to_virt() for platform > ROM > > On Wed, Mar 18, 2020 at 10:16:23PM -0400, Mikel Rychliski wrote: > > On some EFI systems, the video BIOS is provided by the EFI firmware. > > The boot stub code stores the physical address of the ROM image in pdev- > >rom. > > Currently we attempt to access this pointer using phys_to_virt(), > > which doesn't work with CONFIG_HIGHMEM. > > > > On these systems, attempting to load the radeon module on a x86_32 > > kernel can result in the following: > > > > BUG: unable to handle page fault for address: 3e8ed03c > > #PF: supervisor read access in kernel mode > > #PF: error_code(0x) - not-present page > > *pde = > > Oops: [#1] PREEMPT SMP > > CPU: 0 PID: 317 Comm: systemd-udevd Not tainted 5.6.0-rc3-next- > 20200228 #2 > > Hardware name: Apple Computer, Inc. MacPro1,1/Mac-F4208DC8, BIOS > MP11.88Z.005C.B08.0707021221 07/02/07 > > EIP: radeon_get_bios+0x5ed/0xe50 [radeon] > > Code: 00 00 84 c0 0f 85 12 fd ff ff c7 87 64 01 00 00 00 00 00 00 8b 47 > > 08 8b > 55 b0 e8 1e 83 e1 d6 85 c0 74 1a 8b 55 c0 85 d2 74 13 <80> 38 55 75 0e 80 78 > 01 > aa 0f 84 a4 03 00 00 8d 74 26 00 68 dc 06 > > EAX: 3e8ed03c EBX: ECX: 3e8ed03c EDX: 0001 > > ESI: 0004 EDI: eec04000 EBP: eef3fc60 ESP: eef3fbe0 > > DS: 007b ES: 007b FS: 00d8 GS: 00e0 SS: 0068 EFLAGS: 00010206 > > CR0: 80050033 CR2: 3e8ed03c CR3: 2ec77000 CR4: 06d0 > > Call Trace: > > ? register_client+0x34/0xe0 > > ? register_client+0xab/0xe0 > > r520_init+0x26/0x240 [radeon] > > radeon_device_init+0x533/0xa50 [radeon] > > radeon_driver_load_kms+0x80/0x220 [radeon] > > drm_dev_register+0xa7/0x180 [drm] > > radeon_pci_probe+0x10f/0x1a0 [radeon] > > pci_device_probe+0xd4/0x140 > > really_probe+0x13d/0x3b0 > > driver_probe_device+0x56/0xd0 > > device_driver_attach+0x49/0x50 > > __driver_attach+0x79/0x130 > > ? device_driver_attach+0x50/0x50 > > bus_for_each_dev+0x5b/0xa0 > > driver_attach+0x19/0x20 > > ? device_driver_attach+0x50/0x50 > > bus_add_driver+0x117/0x1d0 > > ? pci_bus_num_vf+0x20/0x20 > > driver_register+0x66/0xb0 > > ? 0xf80f4000 > > __pci_register_driver+0x3d/0x40 > > radeon_init+0x82/0x1000 [radeon] > > do_one_initcall+0x42/0x200 > > ? kvfree+0x25/0x30 > > ? __vunmap+0x206/0x230 > > ? kmem_cache_alloc_trace+0x16f/0x220 > > ? do_init_module+0x21/0x220 > > do_init_module+0x50/0x220 > > load_module+0x1f26/0x2200 > > sys_init_module+0x12d/0x160 > > do_fast_syscall_32+0x82/0x250 > > entry_SYSENTER_32+0xa5/0xf8 > > > > Fix the issue by updating all drivers which can access a platform > > provided ROM. Instead of calling the helper function > > pci_platform_rom() which uses phys_to_virt(), call ioremap() directly on > the pdev->rom. > > > > radeon_read_platform_bios() previously directly accessed an __iomem > > pointer. Avoid this by calling memcpy_fromio() instead of kmemdup(). > > > > pci_platform_rom() now has no remaining callers, so remove it. > > > > Signed-off-by: Mikel Rychliski > > I applied this to pci/resource for v5.7. I would feel better if some of the > graphics guys chimed in, or even applied it via the DRM tree since most of the > changes are actually in drivers/gpu. Feel free to take it through the PCI tree. These areas of radeon and amdgpu don't really change much at all so, I'm not too concerned about a conflict. Acked-by: Alex Deucher > > Feel free to add my > > Acked-by: Bjorn Helgaas > > and let me know if you do that. > > > --- > > > > Tested on a MacPro 1,1 with a Radeon X1900 XT card and 32-bit kernel. > > > > Changes in v3: > > - Inline pci_platform_rom() > > > > Changes in v2: > > - Add iounmap() call in nouveau > > - Update function comment for pci_platform_rom() > > - Minor changes to commit messages > > > > drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c | 31 > +- > > .../gpu/drm/nouveau/nvkm/subdev/bios/shadowpci.c | 17 ++- > - > > drivers/gpu/drm/radeon/radeon_bios.c | 30 > > +--- > - > > drivers/pci/rom.c | 17 > > include/linux/pci.h| 1 - > > 5 files changed, 52 insertions(+), 44 deletions(-) > > > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c > > b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c > > index 50dff69a0f6e..b1172d93c99c 100644 > > ---
Re: [PATCH] drm/amd/display: add basic atomic check for cursor plane
On Monday, March 30, 2020 3:11 PM, Kazlauskas, Nicholas wrote: > On 2020-03-30 9:02 a.m., Simon Ser wrote: > > > On Monday, March 30, 2020 2:59 PM, Kazlauskas, Nicholas > > nicholas.kazlaus...@amd.com wrote: > > > > > We've been doing these checks for position before but I don't think we > > > really need them. DC should be disabling the cursor when we ask for a > > > position completely off the screen. > > > I think that's better than rejecting the commit entirely at least. > > > > I agree DC should be disabling the cursor in this case, however that's > > not yet implemented right? I think implementing this feature is > > orthogonal and should be done in a separate patch. > > This patch simply copies over the cursor checks in the atomic check > > function. > > It's implemented on DCN but I don't remember if we're doing it on DCE. > > I guess the drop can be in a separate patch. > > Reviewed-by: Nicholas Kazlauskas Thanks for the review. I'll try to figure out whether we can drop this check (from both the atomic check and the other existing check). ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amd/display: add basic atomic check for cursor plane
On 2020-03-30 9:02 a.m., Simon Ser wrote: On Monday, March 30, 2020 2:59 PM, Kazlauskas, Nicholas wrote: We've been doing these checks for position before but I don't think we really need them. DC should be disabling the cursor when we ask for a position completely off the screen. I think that's better than rejecting the commit entirely at least. I agree DC should be disabling the cursor in this case, however that's not yet implemented right? I think implementing this feature is orthogonal and should be done in a separate patch. This patch simply copies over the cursor checks in the atomic check function. It's implemented on DCN but I don't remember if we're doing it on DCE. I guess the drop can be in a separate patch. Reviewed-by: Nicholas Kazlauskas Regards, Nicholas Kazlauskas ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amd/display: add basic atomic check for cursor plane
On Monday, March 30, 2020 2:59 PM, Kazlauskas, Nicholas wrote: > We've been doing these checks for position before but I don't think we > really need them. DC should be disabling the cursor when we ask for a > position completely off the screen. > > I think that's better than rejecting the commit entirely at least. I agree DC should be disabling the cursor in this case, however that's not yet implemented right? I think implementing this feature is orthogonal and should be done in a separate patch. This patch simply copies over the cursor checks in the atomic check function. ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amd/display: add basic atomic check for cursor plane
On 2020-03-30 5:23 a.m., Simon Ser wrote:
This patch adds a basic cursor check when an atomic test-only commit is
performed. The position and size of the cursor plane is checked.
This should fix user-space relying on atomic checks to assign buffers to
planes.
Signed-off-by: Simon Ser
Reported-by: Roman Gilg
References: https://github.com/emersion/libliftoff/issues/46
Cc: Alex Deucher
Cc: Harry Wentland
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 26 +--
1 file changed, 24 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index f6b0b9a121fd..e1b084318ad6 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -7843,6 +7843,7 @@ static int dm_update_plane_state(struct dc *dc,
struct drm_crtc_state *old_crtc_state, *new_crtc_state;
struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
+ struct amdgpu_crtc *new_acrtc;
bool needs_reset;
int ret = 0;
@@ -7852,9 +7853,30 @@ static int dm_update_plane_state(struct dc *dc,
dm_new_plane_state = to_dm_plane_state(new_plane_state);
dm_old_plane_state = to_dm_plane_state(old_plane_state);
- /*TODO Implement atomic check for cursor plane */
- if (plane->type == DRM_PLANE_TYPE_CURSOR)
+ /*TODO Implement better atomic check for cursor plane */
+ if (plane->type == DRM_PLANE_TYPE_CURSOR) {
+ if (!enable || !new_plane_crtc ||
+ drm_atomic_plane_disabling(plane->state,
new_plane_state))
+ return 0;
+
+ new_acrtc = to_amdgpu_crtc(new_plane_crtc);
+
+ if ((new_plane_state->crtc_w > new_acrtc->max_cursor_width) ||
+ (new_plane_state->crtc_h >
new_acrtc->max_cursor_height)) {
+ DRM_DEBUG_ATOMIC("Bad cursor size %d x %d\n",
+new_plane_state->crtc_w,
new_plane_state->crtc_h);
+ return -EINVAL;
+ }
+
+ if (new_plane_state->crtc_x <= -new_acrtc->max_cursor_width ||
+ new_plane_state->crtc_y <=
-new_acrtc->max_cursor_height) {
+ DRM_DEBUG_ATOMIC("Bad cursor position %d, %d\n",
+new_plane_state->crtc_x,
new_plane_state->crtc_y);
+ return -EINVAL;
We've been doing these checks for position before but I don't think we
really need them. DC should be disabling the cursor when we ask for a
position completely off the screen.
I think that's better than rejecting the commit entirely at least.
Nicholas Kazlauskas
+ }
+
return 0;
+ }
needs_reset = should_reset_plane(state, plane, old_plane_state,
new_plane_state);
--
2.26.0
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RE: [PATCH] drm/amdgpu: skip access sdma_v5_0 registers under SRIOV
Hi Emily
Many thanks
-Original Message-
From: Deng, Emily
Sent: 2020年3月30日 19:57
To: Tao, Yintian ; Koenig, Christian
; Deucher, Alexander
Cc: amd-gfx@lists.freedesktop.org; Tao, Yintian
Subject: RE: [PATCH] drm/amdgpu: skip access sdma_v5_0 registers under SRIOV
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Emily Deng
Best wishes
Emily Deng
>-Original Message-
>From: amd-gfx On Behalf Of
>Yintian Tao
>Sent: Monday, March 30, 2020 4:50 PM
>To: Koenig, Christian ; Deucher, Alexander
>
>Cc: amd-gfx@lists.freedesktop.org; Tao, Yintian
>Subject: [PATCH] drm/amdgpu: skip access sdma_v5_0 registers under
>SRIOV
>
>Due to the new L1.0b0c011b policy, many SDMA registers are blocked
>which raise the violation warning. There are total 6 pair register
>needed to be skipped when driver init and de-init.
>mmSDMA0/1_CNTL
>mmSDMA0/1_F32_CNTL
>mmSDMA0/1_UTCL1_PAGE
>mmSDMA0/1_UTCL1_CNTL
>mmSDMA0/1_CHICKEN_BITS,
>mmSDMA0/1_SEM_WAIT_FAIL_TIMER_CNTL
>
>Signed-off-by: Yintian Tao
>Change-Id: I9d5087582ceb5f629d37bf856533d00c179e6de3
>---
> drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 110 +
> 1 file changed, 75 insertions(+), 35 deletions(-)
>
>diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
>b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
>index b3c30616d6b4..d7c0269059b0 100644
>--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
>+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
>@@ -88,6 +88,29 @@ static const struct soc15_reg_golden
>golden_settings_sdma_5[] = {
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_UTCL1_PAGE, 0x00ff,
>0x000c5c00) };
>
>+static const struct soc15_reg_golden golden_settings_sdma_5_sriov[] = {
>+ SOC15_REG_GOLDEN_VALUE(GC, 0,
>mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfff7, 0x00403000),
>+ SOC15_REG_GOLDEN_VALUE(GC, 0,
>mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfff7, 0x00403000),
>+ SOC15_REG_GOLDEN_VALUE(GC, 0,
>mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfff7, 0x00403000),
>+ SOC15_REG_GOLDEN_VALUE(GC, 0,
>mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfff7, 0x00403000),
>+ SOC15_REG_GOLDEN_VALUE(GC, 0,
>mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfff7, 0x00403000),
>+ SOC15_REG_GOLDEN_VALUE(GC, 0,
>mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfff7, 0x00403000),
>+ SOC15_REG_GOLDEN_VALUE(GC, 0,
>mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfff7, 0x00403000),
>+ SOC15_REG_GOLDEN_VALUE(GC, 0,
>mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfff7, 0x00403000),
>+ SOC15_REG_GOLDEN_VALUE(GC, 0,
>mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfff7, 0x00403000),
>+ SOC15_REG_GOLDEN_VALUE(GC, 0,
>mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfff7, 0x00403000),
>+ SOC15_REG_GOLDEN_VALUE(GC, 0,
>mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfff7, 0x00403000),
>+ SOC15_REG_GOLDEN_VALUE(GC, 0,
>mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfff7, 0x00403000),
>+ SOC15_REG_GOLDEN_VALUE(GC, 0,
>mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfff7, 0x00403000),
>+ SOC15_REG_GOLDEN_VALUE(GC, 0,
>mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfff7, 0x00403000),
>+ SOC15_REG_GOLDEN_VALUE(GC, 0,
>mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfff7, 0x00403000),
>+ SOC15_REG_GOLDEN_VALUE(GC, 0,
>mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfff7, 0x00403000),
>+ SOC15_REG_GOLDEN_VALUE(GC, 0,
>mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfff7, 0x00403000),
>+ SOC15_REG_GOLDEN_VALUE(GC, 0,
>mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfff7, 0x00403000),
>+ SOC15_REG_GOLDEN_VALUE(GC, 0,
>mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfff7, 0x00403000),
>+ SOC15_REG_GOLDEN_VALUE(GC, 0,
>mmSDMA1_RLC7_RB_WPTR_POLL_CNTL,
>+0xfff7, 0x00403000), };
>+
> static const struct soc15_reg_golden golden_settings_sdma_nv10[] = {
> SOC15_REG_GOLDEN_VALUE(GC, 0,
>mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfff0, 0x00403000),
> SOC15_REG_GOLDEN_VALUE(GC, 0,
>mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfff0, 0x00403000), @@ -141,9
>+164,14 @@ static void sdma_v5_0_init_golden_registers(struct
>amdgpu_device *adev)
> (const
>u32)ARRAY_SIZE(golden_settings_sdma_nv14));
> break;
> case CHIP_NAVI12:
>- soc15_program_register_sequence(adev,
>- golden_settings_sdma_5,
>- (const
>u32)ARRAY_SIZE(golden_settings_sdma_5));
>+ if (amdgpu_sriov_vf(adev))
>+ soc15_program_register_sequence(adev,
>+
> golden_settings_sdma_5_sriov,
>+ (const
>u32)ARRAY_SIZE(golden_settings_sdma_5_sriov));
>+ else
>+ soc15_program_register_sequence(adev,
>+
> golden_settings_sdma_5,
>+ (const
>u32)ARRAY_SIZE(golden_settings_sdma_5));
> soc15_program_register_sequence(adev,
> golden_settings_sdma_nv12,
>
[PATCH 4/5] drm/amdgpu/vcn2.0: Add firmware w/r ptr reset sync
Add firmware write/read point reset sync through shared memory
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 42 ---
1 file changed, 39 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index 28ef7df..852795c 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -92,6 +92,7 @@ static int vcn_v2_0_sw_init(void *handle)
struct amdgpu_ring *ring;
int i, r;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ volatile struct amdgpu_fw_shared *fw_shared;
/* VCN DEC TRAP */
r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
@@ -174,6 +175,8 @@ static int vcn_v2_0_sw_init(void *handle)
if (r)
return r;
+ fw_shared = adev->vcn.inst->fw_shared_cpu_addr;
+ fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG);
return 0;
}
@@ -188,6 +191,9 @@ static int vcn_v2_0_sw_fini(void *handle)
{
int r;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ volatile struct amdgpu_fw_shared *fw_shared =
adev->vcn.inst->fw_shared_cpu_addr;
+
+ fw_shared->present_flag_0 = 0;
amdgpu_virt_free_mm_table(adev);
@@ -363,6 +369,15 @@ static void vcn_v2_0_mc_resume(struct amdgpu_device *adev)
WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0);
WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
+ /* non-cache window */
+ WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW,
+ lower_32_bits(adev->vcn.inst->fw_shared_gpu_addr));
+ WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH,
+ upper_32_bits(adev->vcn.inst->fw_shared_gpu_addr));
+ WREG32_SOC15(UVD, 0, mmUVD_VCPU_NONCACHE_OFFSET0, 0);
+ WREG32_SOC15(UVD, 0, mmUVD_VCPU_NONCACHE_SIZE0,
+ AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)));
+
WREG32_SOC15(UVD, 0, mmUVD_GFX10_ADDR_CONFIG,
adev->gfx.config.gb_addr_config);
}
@@ -446,13 +461,16 @@ static void vcn_v2_0_mc_resume_dpg_mode(struct
amdgpu_device *adev, bool indirec
/* non-cache window */
WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 0, 0, indirect);
+ UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),
+ lower_32_bits(adev->vcn.inst->fw_shared_gpu_addr), 0, indirect);
WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 0, 0, indirect);
+ UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),
+ upper_32_bits(adev->vcn.inst->fw_shared_gpu_addr), 0, indirect);
WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
UVD, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, 0, mmUVD_VCPU_NONCACHE_SIZE0), 0, 0, indirect);
+ UVD, 0, mmUVD_VCPU_NONCACHE_SIZE0),
+ AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0,
indirect);
/* VCN global tiling registers */
WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
@@ -777,6 +795,7 @@ static void vcn_v2_0_enable_static_power_gating(struct
amdgpu_device *adev)
static int vcn_v2_0_start_dpg_mode(struct amdgpu_device *adev, bool indirect)
{
+ volatile struct amdgpu_fw_shared *fw_shared =
adev->vcn.inst->fw_shared_cpu_addr;
struct amdgpu_ring *ring = >vcn.inst->ring_dec;
uint32_t rb_bufsz, tmp;
@@ -880,6 +899,8 @@ static int vcn_v2_0_start_dpg_mode(struct amdgpu_device
*adev, bool indirect)
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),
UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK,
~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
+ fw_shared->multi_queue.decode_queue_mode |= fw_queue_ring_reset;
+
/* set the write pointer delay */
WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0);
@@ -902,6 +923,7 @@ static int vcn_v2_0_start_dpg_mode(struct amdgpu_device
*adev, bool indirect)
WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
lower_32_bits(ring->wptr));
+ fw_shared->multi_queue.decode_queue_mode &= ~fw_queue_ring_reset;
/* Unstall DPG */
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),
0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
@@ -910,6 +932,7 @@ static int vcn_v2_0_start_dpg_mode(struct amdgpu_device
*adev, bool indirect)
static int vcn_v2_0_start(struct amdgpu_device *adev)
{
+ volatile struct amdgpu_fw_shared *fw_shared =
adev->vcn.inst->fw_shared_cpu_addr;
struct amdgpu_ring *ring = >vcn.inst->ring_dec;
uint32_t rb_bufsz, tmp;
uint32_t lmi_swap_cntl;
@@ -1044,6 +1067,7 @@ static
[PATCH 2/5] drm/amdgpu/vcn2.5: stall DPG when WPTR/RPTR reset
Add vcn dpg harware synchronization to fix race condition issue between vcn driver and hardware. Signed-off-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 21 + 1 file changed, 21 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c index c6363f5..7eb3b9d 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c @@ -855,6 +855,12 @@ static int vcn_v2_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); WREG32_SOC15(UVD, inst_idx, mmUVD_RBC_RB_CNTL, tmp); + /* Stall DPG before WPTR/RPTR reset */ + WREG32_P(SOC15_REG_OFFSET(UVD, inst_idx, mmUVD_POWER_STATUS), + UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, + ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); + fw_shared->multi_queue.decode_queue_mode |= fw_queue_ring_reset; + /* set the write pointer delay */ WREG32_SOC15(UVD, inst_idx, mmUVD_RBC_RB_WPTR_CNTL, 0); @@ -877,6 +883,10 @@ static int vcn_v2_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo WREG32_SOC15(UVD, inst_idx, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); + /* Unstall DPG */ + WREG32_P(SOC15_REG_OFFSET(UVD, inst_idx, mmUVD_POWER_STATUS), + 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); + return 0; } @@ -1389,8 +1399,14 @@ static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev, UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, ret_code); + /* Stall DPG before WPTR/RPTR reset */ + WREG32_P(SOC15_REG_OFFSET(UVD, inst_idx, mmUVD_POWER_STATUS), + UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, + ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); + /* Restore */ ring = >vcn.inst[inst_idx].ring_enc[0]; + ring->wptr = 0; WREG32_SOC15(UVD, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr); WREG32_SOC15(UVD, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); WREG32_SOC15(UVD, inst_idx, mmUVD_RB_SIZE, ring->ring_size / 4); @@ -1398,6 +1414,7 @@ static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev, WREG32_SOC15(UVD, inst_idx, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); ring = >vcn.inst[inst_idx].ring_enc[1]; + ring->wptr = 0; WREG32_SOC15(UVD, inst_idx, mmUVD_RB_BASE_LO2, ring->gpu_addr); WREG32_SOC15(UVD, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); WREG32_SOC15(UVD, inst_idx, mmUVD_RB_SIZE2, ring->ring_size / 4); @@ -1407,6 +1424,10 @@ static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev, WREG32_SOC15(UVD, inst_idx, mmUVD_RBC_RB_WPTR, RREG32_SOC15(UVD, inst_idx, mmUVD_SCRATCH2) & 0x7FFF); + /* Unstall DPG */ + WREG32_P(SOC15_REG_OFFSET(UVD, inst_idx, mmUVD_POWER_STATUS), + 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); + SOC15_WAIT_ON_RREG(UVD, inst_idx, mmUVD_POWER_STATUS, UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); } -- 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 1/5] drm/amdgpu/vcn2.0: stall DPG when WPTR/RPTR reset
Add vcn dpg harware synchronization to fix race condition issue between vcn driver and hardware. Signed-off-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 16 1 file changed, 16 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c index febd4c2..28ef7df 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c @@ -876,6 +876,10 @@ static int vcn_v2_0_start_dpg_mode(struct amdgpu_device *adev, bool indirect) tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); + /* Stall DPG before WPTR/RPTR reset */ + WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), + UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, + ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); /* set the write pointer delay */ WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0); @@ -898,6 +902,9 @@ static int vcn_v2_0_start_dpg_mode(struct amdgpu_device *adev, bool indirect) WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); + /* Unstall DPG */ + WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), + 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); return 0; } @@ -1193,8 +1200,13 @@ static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev, UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, ret_code); + /* Stall DPG before WPTR/RPTR reset */ + WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), + UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, + ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); /* Restore */ ring = >vcn.inst->ring_enc[0]; + ring->wptr = 0; WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); @@ -1202,6 +1214,7 @@ static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev, WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); ring = >vcn.inst->ring_enc[1]; + ring->wptr = 0; WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); @@ -1210,6 +1223,9 @@ static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev, WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFF); + /* Unstall DPG */ + WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), + 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, -- 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 5/5] drm/amdgpu/vcn2.5: Add firmware w/r ptr reset sync
Add firmware write/read point reset sync through shared memory
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 51 ---
1 file changed, 47 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
index 7eb3b9d..6aef04f 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
@@ -165,6 +165,8 @@ static int vcn_v2_5_sw_init(void *handle)
return r;
for (j = 0; j < adev->vcn.num_vcn_inst; j++) {
+ volatile struct amdgpu_fw_shared *fw_shared;
+
if (adev->vcn.harvest_config & (1 << j))
continue;
adev->vcn.internal.context_id =
mmUVD_CONTEXT_ID_INTERNAL_OFFSET;
@@ -207,6 +209,9 @@ static int vcn_v2_5_sw_init(void *handle)
if (r)
return r;
}
+
+ fw_shared = adev->vcn.inst[j].fw_shared_cpu_addr;
+ fw_shared->present_flag_0 =
cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG);
}
if (amdgpu_sriov_vf(adev)) {
@@ -230,8 +235,16 @@ static int vcn_v2_5_sw_init(void *handle)
*/
static int vcn_v2_5_sw_fini(void *handle)
{
- int r;
+ int i, r;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ volatile struct amdgpu_fw_shared *fw_shared;
+
+ for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
+ if (adev->vcn.harvest_config & (1 << i))
+ continue;
+ fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr;
+ fw_shared->present_flag_0 = 0;
+ }
if (amdgpu_sriov_vf(adev))
amdgpu_virt_free_mm_table(adev);
@@ -424,6 +437,15 @@ static void vcn_v2_5_mc_resume(struct amdgpu_device *adev)
upper_32_bits(adev->vcn.inst[i].gpu_addr + offset +
AMDGPU_VCN_STACK_SIZE));
WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET2, 0);
WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE2,
AMDGPU_VCN_CONTEXT_SIZE);
+
+ /* non-cache window */
+ WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW,
+ lower_32_bits(adev->vcn.inst[i].fw_shared_gpu_addr));
+ WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH,
+ upper_32_bits(adev->vcn.inst[i].fw_shared_gpu_addr));
+ WREG32_SOC15(UVD, i, mmUVD_VCPU_NONCACHE_OFFSET0, 0);
+ WREG32_SOC15(UVD, i, mmUVD_VCPU_NONCACHE_SIZE0,
+ AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)));
}
}
@@ -507,13 +529,16 @@ static void vcn_v2_5_mc_resume_dpg_mode(struct
amdgpu_device *adev, int inst_idx
/* non-cache window */
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 0, 0, indirect);
+ UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),
+ lower_32_bits(adev->vcn.inst[inst_idx].fw_shared_gpu_addr), 0,
indirect);
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 0, 0, indirect);
+ UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),
+ upper_32_bits(adev->vcn.inst[inst_idx].fw_shared_gpu_addr), 0,
indirect);
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
UVD, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, 0, mmUVD_VCPU_NONCACHE_SIZE0), 0, 0, indirect);
+ UVD, 0, mmUVD_VCPU_NONCACHE_SIZE0),
+ AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0,
indirect);
/* VCN global tiling registers */
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
@@ -750,6 +775,7 @@ static void vcn_v2_5_enable_clock_gating(struct
amdgpu_device *adev)
static int vcn_v2_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx,
bool indirect)
{
+ volatile struct amdgpu_fw_shared *fw_shared =
adev->vcn.inst[inst_idx].fw_shared_cpu_addr;
struct amdgpu_ring *ring;
uint32_t rb_bufsz, tmp;
@@ -883,6 +909,7 @@ static int vcn_v2_5_start_dpg_mode(struct amdgpu_device
*adev, int inst_idx, boo
WREG32_SOC15(UVD, inst_idx, mmUVD_RBC_RB_WPTR,
lower_32_bits(ring->wptr));
+ fw_shared->multi_queue.decode_queue_mode &= ~fw_queue_ring_reset;
/* Unstall DPG */
WREG32_P(SOC15_REG_OFFSET(UVD, inst_idx, mmUVD_POWER_STATUS),
0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
@@ -972,6 +999,7 @@ static int vcn_v2_5_start(struct amdgpu_device *adev)
vcn_v2_5_mc_resume(adev);
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+ volatile struct amdgpu_fw_shared *fw_shared =
[PATCH 3/5] drm/amdgpu/vcn: Add firmware share memory support
Added firmware share memory support for VCN. Current multiple
queue mode is enabled only.
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 13 +
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 24
2 files changed, 37 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 7a0b074..328b6ce 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -182,6 +182,14 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
return r;
}
}
+
+ r = amdgpu_bo_create_kernel(adev,
AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)),
+ PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
>vcn.inst[i].fw_shared_bo,
+ >vcn.inst[i].fw_shared_gpu_addr,
>vcn.inst[i].fw_shared_cpu_addr);
+ if (r) {
+ dev_err(adev->dev, "VCN %d (%d) failed to allocate
fimware shared bo\n", i, r);
+ return r;
+ }
}
return 0;
@@ -196,6 +204,11 @@ int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
if (adev->vcn.harvest_config & (1 << j))
continue;
+
+ amdgpu_bo_free_kernel(>vcn.inst[j].fw_shared_bo,
+ >vcn.inst[j].fw_shared_gpu_addr,
+ (void
**)>vcn.inst[j].fw_shared_cpu_addr);
+
if (adev->vcn.indirect_sram) {
amdgpu_bo_free_kernel(>vcn.inst[j].dpg_sram_bo,
>vcn.inst[j].dpg_sram_gpu_addr,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index e913de8..853f0cc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -179,11 +179,14 @@ struct amdgpu_vcn_inst {
struct amdgpu_irq_src irq;
struct amdgpu_vcn_reg external;
struct amdgpu_bo*dpg_sram_bo;
+ struct amdgpu_bo*fw_shared_bo;
struct dpg_pause_state pause_state;
void*dpg_sram_cpu_addr;
uint64_tdpg_sram_gpu_addr;
uint32_t*dpg_sram_curr_addr;
atomic_tdpg_enc_submission_cnt;
+ void*fw_shared_cpu_addr;
+ uint64_tfw_shared_gpu_addr;
};
struct amdgpu_vcn {
@@ -209,6 +212,27 @@ struct amdgpu_vcn {
int inst_idx, struct dpg_pause_state *new_state);
};
+#define AMDGPU_VCN_MULTI_QUEUE_FLAG(1 << 8)
+
+enum fw_queue_mode {
+ fw_queue_ring_reset = 1,
+ fw_queue_dpg_hold_off = 2,
+};
+
+struct amdgpu_fw_shared_multi_queue {
+ uint8_t decode_queue_mode;
+ uint8_t encode_generalpurpose_queue_mode;
+ uint8_t encode_lowlatency_queue_mode;
+ uint8_t encode_realtime_queue_mode;
+ uint8_t padding[4];
+};
+
+struct amdgpu_fw_shared {
+ uint32_t present_flag_0;
+ uint8_t pad[53];
+ struct amdgpu_fw_shared_multi_queue multi_queue;
+} __attribute__((__packed__));
+
int amdgpu_vcn_sw_init(struct amdgpu_device *adev);
int amdgpu_vcn_sw_fini(struct amdgpu_device *adev);
int amdgpu_vcn_suspend(struct amdgpu_device *adev);
--
2.7.4
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RE: [PATCH] drm/amdgpu: skip access sdma_v5_0 registers under SRIOV
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Emily Deng
Best wishes
Emily Deng
>-Original Message-
>From: amd-gfx On Behalf Of Yintian
>Tao
>Sent: Monday, March 30, 2020 4:50 PM
>To: Koenig, Christian ; Deucher, Alexander
>
>Cc: amd-gfx@lists.freedesktop.org; Tao, Yintian
>Subject: [PATCH] drm/amdgpu: skip access sdma_v5_0 registers under SRIOV
>
>Due to the new L1.0b0c011b policy, many SDMA registers are blocked which
>raise the violation warning. There are total 6 pair register needed to be
>skipped
>when driver init and de-init.
>mmSDMA0/1_CNTL
>mmSDMA0/1_F32_CNTL
>mmSDMA0/1_UTCL1_PAGE
>mmSDMA0/1_UTCL1_CNTL
>mmSDMA0/1_CHICKEN_BITS,
>mmSDMA0/1_SEM_WAIT_FAIL_TIMER_CNTL
>
>Signed-off-by: Yintian Tao
>Change-Id: I9d5087582ceb5f629d37bf856533d00c179e6de3
>---
> drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 110 +
> 1 file changed, 75 insertions(+), 35 deletions(-)
>
>diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
>b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
>index b3c30616d6b4..d7c0269059b0 100644
>--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
>+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
>@@ -88,6 +88,29 @@ static const struct soc15_reg_golden
>golden_settings_sdma_5[] = {
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_UTCL1_PAGE,
>0x00ff, 0x000c5c00) };
>
>+static const struct soc15_reg_golden golden_settings_sdma_5_sriov[] = {
>+ SOC15_REG_GOLDEN_VALUE(GC, 0,
>mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfff7, 0x00403000),
>+ SOC15_REG_GOLDEN_VALUE(GC, 0,
>mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfff7, 0x00403000),
>+ SOC15_REG_GOLDEN_VALUE(GC, 0,
>mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfff7, 0x00403000),
>+ SOC15_REG_GOLDEN_VALUE(GC, 0,
>mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfff7, 0x00403000),
>+ SOC15_REG_GOLDEN_VALUE(GC, 0,
>mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfff7, 0x00403000),
>+ SOC15_REG_GOLDEN_VALUE(GC, 0,
>mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfff7, 0x00403000),
>+ SOC15_REG_GOLDEN_VALUE(GC, 0,
>mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfff7, 0x00403000),
>+ SOC15_REG_GOLDEN_VALUE(GC, 0,
>mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfff7, 0x00403000),
>+ SOC15_REG_GOLDEN_VALUE(GC, 0,
>mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfff7, 0x00403000),
>+ SOC15_REG_GOLDEN_VALUE(GC, 0,
>mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfff7, 0x00403000),
>+ SOC15_REG_GOLDEN_VALUE(GC, 0,
>mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfff7, 0x00403000),
>+ SOC15_REG_GOLDEN_VALUE(GC, 0,
>mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfff7, 0x00403000),
>+ SOC15_REG_GOLDEN_VALUE(GC, 0,
>mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfff7, 0x00403000),
>+ SOC15_REG_GOLDEN_VALUE(GC, 0,
>mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfff7, 0x00403000),
>+ SOC15_REG_GOLDEN_VALUE(GC, 0,
>mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfff7, 0x00403000),
>+ SOC15_REG_GOLDEN_VALUE(GC, 0,
>mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfff7, 0x00403000),
>+ SOC15_REG_GOLDEN_VALUE(GC, 0,
>mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfff7, 0x00403000),
>+ SOC15_REG_GOLDEN_VALUE(GC, 0,
>mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfff7, 0x00403000),
>+ SOC15_REG_GOLDEN_VALUE(GC, 0,
>mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfff7, 0x00403000),
>+ SOC15_REG_GOLDEN_VALUE(GC, 0,
>mmSDMA1_RLC7_RB_WPTR_POLL_CNTL,
>+0xfff7, 0x00403000), };
>+
> static const struct soc15_reg_golden golden_settings_sdma_nv10[] = {
> SOC15_REG_GOLDEN_VALUE(GC, 0,
>mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfff0, 0x00403000),
> SOC15_REG_GOLDEN_VALUE(GC, 0,
>mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfff0, 0x00403000), @@ -141,9
>+164,14 @@ static void sdma_v5_0_init_golden_registers(struct
>amdgpu_device *adev)
> (const
>u32)ARRAY_SIZE(golden_settings_sdma_nv14));
> break;
> case CHIP_NAVI12:
>- soc15_program_register_sequence(adev,
>- golden_settings_sdma_5,
>- (const
>u32)ARRAY_SIZE(golden_settings_sdma_5));
>+ if (amdgpu_sriov_vf(adev))
>+ soc15_program_register_sequence(adev,
>+
> golden_settings_sdma_5_sriov,
>+ (const
>u32)ARRAY_SIZE(golden_settings_sdma_5_sriov));
>+ else
>+ soc15_program_register_sequence(adev,
>+
> golden_settings_sdma_5,
>+ (const
>u32)ARRAY_SIZE(golden_settings_sdma_5));
> soc15_program_register_sequence(adev,
> golden_settings_sdma_nv12,
> (const
>u32)ARRAY_SIZE(golden_settings_sdma_nv12));
>@@ -557,9 +585,12 @@ static void sdma_v5_0_ctx_switch_enable(struct
>amdgpu_device *adev, bool enable)
> }
>
> for (i = 0; i < adev->sdma.num_instances; i++) {
>- f32_cntl =
Re: [PATCH] drm/amdgpu: Check entity rq
Am 25.03.20 um 12:03 schrieb Nirmoy: On 3/25/20 10:23 AM, Pan, Xinhui wrote: 2020年3月25日 15:48，Koenig, Christian 写道： Am 25.03.20 um 06:47 schrieb xinhui pan: Hit panic during GPU recovery test. drm_sched_entity_select_rq might set NULL to rq. So add a check like drm_sched_job_init does. NAK, the rq should never be set to NULL in the first place. How did that happened? well, I have not check the details. but just got the call trace below. looks like sched is not ready, and drm_sched_entity_select_rq set entity->rq to NULL. in the next amdgpu_vm_sdma_commit, hit panic when we deference entity->rq. "drm/amdgpu: stop disable the scheduler during HW fini" from Christian should've fix it already. But I can't find that commit in brahma/amd-staging-drm-next. Yeah, my fault. I actually forgot to push it. Should be fixed by now, Christian. Regards, Nirmoy 297567 [ 44.667677] amdgpu :03:00.0: GPU reset begin! 297568 [ 44.929047] [drm] scheduler sdma0 is not ready, skipping 297569 [ 44.929048] [drm] scheduler sdma1 is not ready, skipping 297570 [ 44.934608] [drm:amdgpu_gem_va_ioctl [amdgpu]] *ERROR* Couldn't update BO_VA (-2) 297571 [ 44.947941] BUG: kernel NULL pointer dereference, address: 0038 297572 [ 44.955132] #PF: supervisor read access in kernel mode 297573 [ 44.960451] #PF: error_code(0x) - not-present page 297574 [ 44.965714] PGD 0 P4D 0 297575 [ 44.968331] Oops: [#1] SMP PTI 297576 [ 44.971911] CPU: 7 PID: 2496 Comm: gnome-shell Tainted: G W 5.4.0-rc7+ #1 297577 [ 44.980221] Hardware name: System manufacturer System Product Name/Z170-A, BIOS 1702 01/28/2016 297578 [ 44.989177] RIP: 0010:amdgpu_vm_sdma_commit+0x55/0x190 [amdgpu] 297579 [ 44.995242] Code: 47 20 80 7f 10 00 4c 8b a0 88 01 00 00 48 8b 47 08 4c 8d a8 70 01 00 00 75 07 4c 8d a8 88 02 00 00 49 8b 45 10 41 8b 54 24 08 <48> 8b 40 38 85 d2 48 8d b8 30 ff ff f f 0f 84 06 01 00 00 48 8b 80 297580 [ 45.014931] RSP: 0018:b66e008839d0 EFLAGS: 00010246 297581 [ 45.020504] RAX: RBX: b66e00883a30 RCX: 00100400 297582 [ 45.028062] RDX: 003c RSI: 8df123662138 RDI: b66e00883a30 297583 [ 45.035662] RBP: b66e00883a00 R08: b66e0088395c R09: b66e00883960 297584 [ 45.043298] R10: 00100240 R11: 0035 R12: 8df1425385e8 297585 [ 45.050916] R13: 8df13cfd1288 R14: 8df123662138 R15: 8df13cfd1000 297586 [ 45.058524] FS: 7fcc8f6b2100() GS:8df15e38() knlGS: 297587 [ 45.067114] CS: 0010 DS: ES: CR0: 80050033 297588 [ 45.073206] CR2: 0038 CR3: 000641fb6006 CR4: 003606e0 297589 [ 45.080791] DR0: DR1: DR2: 297590 [ 45.088277] DR3: DR6: fffe0ff0 DR7: 0400 297591 [ 45.095773] Call Trace: 297592 [ 45.098354] amdgpu_vm_bo_update_mapping+0x1c1/0x1f0 [amdgpu] 297593 [ 45.104427] ? mark_held_locks+0x4d/0x80 297594 [ 45.108682] amdgpu_vm_bo_update+0x3b7/0x960 [amdgpu] 297595 [ 45.114049] ? rcu_read_lock_sched_held+0x4f/0x80 297596 [ 45.119111] amdgpu_gem_va_ioctl+0x4f3/0x510 [amdgpu] 297597 [ 45.124495] ? amdgpu_gem_va_map_flags+0x70/0x70 [amdgpu] 297598 [ 45.130250] drm_ioctl_kernel+0xb0/0x100 [drm] 297599 [ 45.134988] ? amdgpu_gem_va_map_flags+0x70/0x70 [amdgpu] 297600 [ 45.140742] ? drm_ioctl_kernel+0xb0/0x100 [drm] 297601 [ 45.145622] drm_ioctl+0x389/0x450 [drm] 297602 [ 45.149804] ? amdgpu_gem_va_map_flags+0x70/0x70 [amdgpu] 297603 [ 45.11] ? trace_hardirqs_on+0x3b/0xf0 297604 [ 45.159892] amdgpu_drm_ioctl+0x4f/0x80 [amdgpu] 297605 [ 45.172104] do_vfs_ioctl+0xa9/0x6f0 297606 [ 45.175909] ? tomoyo_file_ioctl+0x19/0x20 297607 [ 45.180241] ksys_ioctl+0x75/0x80 297608 [ 45.183760] ? do_syscall_64+0x17/0x230 297609 [ 45.187833] __x64_sys_ioctl+0x1a/0x20 297610 [ 45.191846] do_syscall_64+0x5f/0x230 297611 [ 45.195764] entry_SYSCALL_64_after_hwframe+0x49/0xbe 297612 [ 45.201126] RIP: 0033:0x7fcc8c7725d7 Regards, Christian. Cc: Christian König Cc: Alex Deucher Cc: Felix Kuehling Signed-off-by: xinhui pan --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c index cf96c335b258..d30d103e48a2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c @@ -95,6 +95,8 @@ static int amdgpu_vm_sdma_commit(struct amdgpu_vm_update_params *p, int r; entity = p->direct ? >vm->direct : >vm->delayed; + if (!entity->rq) + return -ENOENT; ring = container_of(entity->rq->sched, struct amdgpu_ring, sched); WARN_ON(ib->length_dw == 0); ___ amd-gfx mailing
[PATCH 1/2] drm/amdgpu: fix and cleanup amdgpu_gem_object_close v2
The problem is that we can't add the clear fence to the BO
when there is an exclusive fence on it since we can't
guarantee the the clear fence will complete after the
exclusive one.
To fix this refactor the function and also add the exclusive
fence as shared to the resv object.
v2: fix warning
v3: add excl fence as shared instead
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 41 ++---
1 file changed, 23 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 5bec66e6b1f8..a0be80513e96 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -161,16 +161,17 @@ void amdgpu_gem_object_close(struct drm_gem_object *obj,
struct amdgpu_bo_list_entry vm_pd;
struct list_head list, duplicates;
+ struct dma_fence *fence = NULL;
struct ttm_validate_buffer tv;
struct ww_acquire_ctx ticket;
struct amdgpu_bo_va *bo_va;
- int r;
+ long r;
INIT_LIST_HEAD();
INIT_LIST_HEAD();
tv.bo = >tbo;
- tv.num_shared = 1;
+ tv.num_shared = 2;
list_add(, );
amdgpu_vm_get_pd_bo(vm, , _pd);
@@ -178,28 +179,32 @@ void amdgpu_gem_object_close(struct drm_gem_object *obj,
r = ttm_eu_reserve_buffers(, , false, );
if (r) {
dev_err(adev->dev, "leaking bo va because "
- "we fail to reserve bo (%d)\n", r);
+ "we fail to reserve bo (%ld)\n", r);
return;
}
bo_va = amdgpu_vm_bo_find(vm, bo);
- if (bo_va && --bo_va->ref_count == 0) {
- amdgpu_vm_bo_rmv(adev, bo_va);
+ if (!bo_va || --bo_va->ref_count)
+ goto out_unlock;
- if (amdgpu_vm_ready(vm)) {
- struct dma_fence *fence = NULL;
+ amdgpu_vm_bo_rmv(adev, bo_va);
+ if (!amdgpu_vm_ready(vm))
+ goto out_unlock;
- r = amdgpu_vm_clear_freed(adev, vm, );
- if (unlikely(r)) {
- dev_err(adev->dev, "failed to clear page "
- "tables on GEM object close (%d)\n", r);
- }
+ fence = dma_resv_get_excl(bo->tbo.base.resv);
+ amdgpu_bo_fence(bo, fence, true);
+ fence = NULL;
- if (fence) {
- amdgpu_bo_fence(bo, fence, true);
- dma_fence_put(fence);
- }
- }
- }
+ r = amdgpu_vm_clear_freed(adev, vm, );
+ if (r || !fence)
+ goto out_unlock;
+
+ amdgpu_bo_fence(bo, fence, true);
+ dma_fence_put(fence);
+
+out_unlock:
+ if (unlikely(r < 0))
+ dev_err(adev->dev, "failed to clear page "
+ "tables on GEM object close (%ld)\n", r);
ttm_eu_backoff_reservation(, );
}
--
2.17.1
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[PATCH 2/2] drm/amdgpu: partial revert VM sync changes
We still need to add the VM update fences to the root PD.
So make sure to never sync to those implicitely.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
index b86392253696..b87ca171986a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
@@ -249,6 +249,11 @@ int amdgpu_sync_resv(struct amdgpu_device *adev, struct
amdgpu_sync *sync,
owner != AMDGPU_FENCE_OWNER_UNDEFINED)
continue;
+ /* Never sync to VM updates either. */
+ if (fence_owner == AMDGPU_FENCE_OWNER_VM &&
+ owner != AMDGPU_FENCE_OWNER_UNDEFINED)
+ continue;
+
/* Ignore fences depending on the sync mode */
switch (mode) {
case AMDGPU_SYNC_ALWAYS:
--
2.17.1
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[PATCH] drm/amd/display: add basic atomic check for cursor plane
This patch adds a basic cursor check when an atomic test-only commit is
performed. The position and size of the cursor plane is checked.
This should fix user-space relying on atomic checks to assign buffers to
planes.
Signed-off-by: Simon Ser
Reported-by: Roman Gilg
References: https://github.com/emersion/libliftoff/issues/46
Cc: Alex Deucher
Cc: Harry Wentland
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 26 +--
1 file changed, 24 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index f6b0b9a121fd..e1b084318ad6 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -7843,6 +7843,7 @@ static int dm_update_plane_state(struct dc *dc,
struct drm_crtc_state *old_crtc_state, *new_crtc_state;
struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
+ struct amdgpu_crtc *new_acrtc;
bool needs_reset;
int ret = 0;
@@ -7852,9 +7853,30 @@ static int dm_update_plane_state(struct dc *dc,
dm_new_plane_state = to_dm_plane_state(new_plane_state);
dm_old_plane_state = to_dm_plane_state(old_plane_state);
- /*TODO Implement atomic check for cursor plane */
- if (plane->type == DRM_PLANE_TYPE_CURSOR)
+ /*TODO Implement better atomic check for cursor plane */
+ if (plane->type == DRM_PLANE_TYPE_CURSOR) {
+ if (!enable || !new_plane_crtc ||
+ drm_atomic_plane_disabling(plane->state,
new_plane_state))
+ return 0;
+
+ new_acrtc = to_amdgpu_crtc(new_plane_crtc);
+
+ if ((new_plane_state->crtc_w > new_acrtc->max_cursor_width) ||
+ (new_plane_state->crtc_h >
new_acrtc->max_cursor_height)) {
+ DRM_DEBUG_ATOMIC("Bad cursor size %d x %d\n",
+
new_plane_state->crtc_w, new_plane_state->crtc_h);
+ return -EINVAL;
+ }
+
+ if (new_plane_state->crtc_x <= -new_acrtc->max_cursor_width ||
+ new_plane_state->crtc_y <=
-new_acrtc->max_cursor_height) {
+ DRM_DEBUG_ATOMIC("Bad cursor position %d, %d\n",
+
new_plane_state->crtc_x, new_plane_state->crtc_y);
+ return -EINVAL;
+ }
+
return 0;
+ }
needs_reset = should_reset_plane(state, plane, old_plane_state,
new_plane_state);
--
2.26.0
___
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amd-gfx@lists.freedesktop.org
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[PATCH] drm/amdgpu: skip access sdma_v5_0 registers under SRIOV
Due to the new L1.0b0c011b policy, many SDMA registers are blocked which raise
the violation warning. There are total 6 pair register needed to be skipped
when driver init and de-init.
mmSDMA0/1_CNTL
mmSDMA0/1_F32_CNTL
mmSDMA0/1_UTCL1_PAGE
mmSDMA0/1_UTCL1_CNTL
mmSDMA0/1_CHICKEN_BITS,
mmSDMA0/1_SEM_WAIT_FAIL_TIMER_CNTL
Signed-off-by: Yintian Tao
Change-Id: I9d5087582ceb5f629d37bf856533d00c179e6de3
---
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 110 +
1 file changed, 75 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
index b3c30616d6b4..d7c0269059b0 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
@@ -88,6 +88,29 @@ static const struct soc15_reg_golden
golden_settings_sdma_5[] = {
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_UTCL1_PAGE, 0x00ff,
0x000c5c00)
};
+static const struct soc15_reg_golden golden_settings_sdma_5_sriov[] = {
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL,
0xfff7, 0x00403000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL,
0xfff7, 0x00403000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL,
0xfff7, 0x00403000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL,
0xfff7, 0x00403000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL,
0xfff7, 0x00403000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL,
0xfff7, 0x00403000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL,
0xfff7, 0x00403000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL,
0xfff7, 0x00403000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL,
0xfff7, 0x00403000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL,
0xfff7, 0x00403000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL,
0xfff7, 0x00403000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL,
0xfff7, 0x00403000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL,
0xfff7, 0x00403000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL,
0xfff7, 0x00403000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL,
0xfff7, 0x00403000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL,
0xfff7, 0x00403000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL,
0xfff7, 0x00403000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL,
0xfff7, 0x00403000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL,
0xfff7, 0x00403000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL,
0xfff7, 0x00403000),
+};
+
static const struct soc15_reg_golden golden_settings_sdma_nv10[] = {
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL,
0xfff0, 0x00403000),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL,
0xfff0, 0x00403000),
@@ -141,9 +164,14 @@ static void sdma_v5_0_init_golden_registers(struct
amdgpu_device *adev)
(const
u32)ARRAY_SIZE(golden_settings_sdma_nv14));
break;
case CHIP_NAVI12:
- soc15_program_register_sequence(adev,
- golden_settings_sdma_5,
- (const
u32)ARRAY_SIZE(golden_settings_sdma_5));
+ if (amdgpu_sriov_vf(adev))
+ soc15_program_register_sequence(adev,
+
golden_settings_sdma_5_sriov,
+ (const
u32)ARRAY_SIZE(golden_settings_sdma_5_sriov));
+ else
+ soc15_program_register_sequence(adev,
+ golden_settings_sdma_5,
+ (const
u32)ARRAY_SIZE(golden_settings_sdma_5));
soc15_program_register_sequence(adev,
golden_settings_sdma_nv12,
(const
u32)ARRAY_SIZE(golden_settings_sdma_nv12));
@@ -557,9 +585,12 @@ static void sdma_v5_0_ctx_switch_enable(struct
amdgpu_device *adev, bool enable)
}
for (i = 0; i < adev->sdma.num_instances; i++) {
- f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i,
mmSDMA0_CNTL));
- f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
- AUTO_CTXSW_ENABLE, enable ? 1 : 0);
+ if (!amdgpu_sriov_vf(adev)) {
+ f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i,
mmSDMA0_CNTL));
+
Re: [PATCH v2 hmm 4/9] mm/hmm: remove HMM_FAULT_SNAPSHOT
On Fri, Mar 27, 2020 at 05:00:16PM -0300, Jason Gunthorpe wrote: > From: Jason Gunthorpe > > Now that flags are handled on a fine-grained per-page basis this global > flag is redundant and has a confusing overlap with the pfn_flags_mask and > default_flags. > > Normalize the HMM_FAULT_SNAPSHOT behavior into one place. Callers needing > the SNAPSHOT behavior should set a pfn_flags_mask and default_flags that > always results in a cleared HMM_PFN_VALID. Then no pages will be faulted, > and HMM_FAULT_SNAPSHOT is not a special flow that overrides the masking > mechanism. > > As this is the last flag, also remove the flags argument. If future flags > are needed they can be part of the struct hmm_range function arguments. > > Signed-off-by: Jason Gunthorpe > --- > Documentation/vm/hmm.rst| 12 +--- > drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +- > drivers/gpu/drm/nouveau/nouveau_svm.c | 2 +- > include/linux/hmm.h | 5 + > mm/hmm.c| 17 + > 5 files changed, 17 insertions(+), 21 deletions(-) Looks good, Reviewed-by: Christoph Hellwig ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH v2 hmm 2/9] mm/hmm: return the fault type from hmm_pte_need_fault()
On Fri, Mar 27, 2020 at 05:00:14PM -0300, Jason Gunthorpe wrote: > From: Jason Gunthorpe > > Using two bools instead of flags return is not necessary and leads to > bugs. Returning a value is easier for the compiler to check and easier to > pass around the code flow. > > Convert the two bools into flags and push the change to all callers. > > Signed-off-by: Jason Gunthorpe Looks good, Reviewed-by: Christoph Hellwig ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
