RE: [PATCH] drm/amd/powerplay: Fix buffer overflow in arcturus_get_unique_id()

[Quan, Evan]

[AMD Official Use Only - Internal Distribution Only]

adev->serial which is used to hold the final serial number may need to be 
enlarged also.
Since it comes with 16 bytes also.

BR,
Evan
-Original Message-
From: Dan Carpenter 
Sent: Monday, June 8, 2020 10:18 PM
To: Quan, Evan ; Russell, Kent 
Cc: Deucher, Alexander ; Koenig, Christian 
; David Airlie ; Daniel Vetter 
; amd-gfx@lists.freedesktop.org; 
kernel-janit...@vger.kernel.org
Subject: [PATCH] drm/amd/powerplay: Fix buffer overflow in 
arcturus_get_unique_id()

The comments say that the "sn" buffer is used to hold a 16-digit HEX string so 
the buffer needs to be at least 17 characters to hold the NUL terminator.

Fixes: 81a16241114b ("drm/amdgpu: Add unique_id and serial_number for Arcturus 
v3")
Signed-off-by: Dan Carpenter 
---
 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 
b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
index df7b408319f76..a575cb9d1574c 100644
--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
@@ -2266,7 +2266,7 @@ static void arcturus_get_unique_id(struct smu_context 
*smu)  {
 struct amdgpu_device *adev = smu->adev;
 uint32_t top32, bottom32, smu_version, size;
-char sn[16];
+char sn[20];
 uint64_t id;

 if (smu_get_smc_version(smu, NULL, _version)) {
--
2.26.2

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RE: [PATCH] drm/amd/powerplay: move maximum sustainable clock retrieving to .hw_init

[Cui, Flora]

[AMD Public Use]

Reported-and-tested-by: Flora Cui 

From: Deucher, Alexander 
Sent: Monday, June 8, 2020 11:02 PM
To: Quan, Evan ; amd-gfx@lists.freedesktop.org
Cc: Cui, Flora 
Subject: Re: [PATCH] drm/amd/powerplay: move maximum sustainable clock 
retrieving to .hw_init


[AMD Public Use]

Acked-by: Alex Deucher 
mailto:alexander.deuc...@amd.com>>

From: Quan, Evan mailto:evan.q...@amd.com>>
Sent: Monday, June 8, 2020 6:46 AM
To: amd-gfx@lists.freedesktop.org 
mailto:amd-gfx@lists.freedesktop.org>>
Cc: Deucher, Alexander 
mailto:alexander.deuc...@amd.com>>; Quan, Evan 
mailto:evan.q...@amd.com>>; Cui, Flora 
mailto:flora@amd.com>>
Subject: [PATCH] drm/amd/powerplay: move maximum sustainable clock retrieving 
to .hw_init

Since DAL settings come between .hw_init and .late_init of SMU. And
DAL needs to know the maximum sustainable clocks.

Change-Id: I0702b7332a0d7c0b29dfdf4999c18efb588b8862
Signed-off-by: Evan Quan mailto:evan.q...@amd.com>>
Reported-by: Flora Cui mailto:flora@amd.com>>
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 19 +--
 1 file changed, 13 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 725ac90c0f36..6beae3b496be 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -819,12 +819,6 @@ static int smu_late_init(void *handle)
 return ret;
 }

-   ret = smu_init_max_sustainable_clocks(smu);
-   if (ret) {
-   dev_err(adev->dev, "Failed to init max sustainable clocks!\n");
-   return ret;
-   }
-
 ret = smu_populate_umd_state_clk(smu);
 if (ret) {
 dev_err(adev->dev, "Failed to populate UMD state clocks!\n");
@@ -1364,6 +1358,19 @@ static int smu_hw_init(void *handle)
 return ret;
 }

+   /*
+* Move maximum sustainable clock retrieving here considering
+* 1. It is not needed on resume(from S3).
+* 2. DAL settings come between .hw_init and .late_init of SMU.
+*And DAL needs to know the maximum sustainable clocks. Thus
+*it cannot be put in .late_init().
+*/
+   ret = smu_init_max_sustainable_clocks(smu);
+   if (ret) {
+   dev_err(adev->dev, "Failed to init max sustainable clocks!\n");
+   return ret;
+   }
+
 adev->pm.dpm_enabled = true;

 dev_info(adev->dev, "SMU is initialized successfully!\n");
--
2.27.0
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[PATCH AUTOSEL 5.4 139/175] drm/amdgpu: Sync with VM root BO when switching VM to CPU update mode

[Sasha Levin]

From: Felix Kuehling 

[ Upstream commit 90ca78deb004abe75b5024968a199acb96bb70f9 ]

This fixes an intermittent bug where a root PD clear operation still in
progress could overwrite a PDE update done by the CPU, resulting in a
VM fault.

Fixes: 108b4d928c03 ("drm/amd/amdgpu: Update VM function pointer")
Reported-by: Jay Cornwall 
Tested-by: Jay Cornwall 
Signed-off-by: Felix Kuehling 
Reviewed-by: Christian König 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 11 +--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index c7514f743409..6335bd4ae374 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -2867,10 +2867,17 @@ int amdgpu_vm_make_compute(struct amdgpu_device *adev, 
struct amdgpu_vm *vm, uns
WARN_ONCE((vm->use_cpu_for_update && 
!amdgpu_gmc_vram_full_visible(>gmc)),
  "CPU update of VM recommended only for large BAR system\n");
 
-   if (vm->use_cpu_for_update)
+   if (vm->use_cpu_for_update) {
+   /* Sync with last SDMA update/clear before switching to CPU */
+   r = amdgpu_bo_sync_wait(vm->root.base.bo,
+   AMDGPU_FENCE_OWNER_UNDEFINED, true);
+   if (r)
+   goto free_idr;
+
vm->update_funcs = _vm_cpu_funcs;
-   else
+   } else {
vm->update_funcs = _vm_sdma_funcs;
+   }
dma_fence_put(vm->last_update);
vm->last_update = NULL;
 
-- 
2.25.1

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[PATCH AUTOSEL 5.4 138/175] drm/amd/powerpay: Disable gfxoff when setting manual mode on picasso and raven

[Sasha Levin]

From: chen gong 

[ Upstream commit cbd2d08c7463e78d625a69e9db27ad3004cbbd99 ]

[Problem description]
1. Boot up picasso platform, launches desktop, Don't do anything (APU enter 
into "gfxoff" state)
2. Remote login to platform using SSH, then type the command line:
sudo su -c "echo manual > 
/sys/class/drm/card0/device/power_dpm_force_performance_level"
sudo su -c "echo 2 > /sys/class/drm/card0/device/pp_dpm_sclk" (fix SCLK 
to 1400MHz)
3. Move the mouse around in Window
4. Phenomenon :  The screen frozen

Tester will switch sclk level during glmark2 run time.
APU will enter "gfxoff" state intermittently during glmark2 run time.
The system got hanged if fix GFXCLK to 1400MHz when APU is in "gfxoff"
state.

[Debug]
1. Fix SCLK to X MHz
1400: screen frozen, screen black, then OS will reboot.
1300: screen frozen.
1200: screen frozen, screen black.
1100: screen frozen, screen black, then OS will reboot.
1000: screen frozen, screen black.
900:  screen frozen, screen black, then OS will reboot.
800:  Situation Nomal, issue disappear.
700:  Situation Nomal, issue disappear.
2. SBIOS setting: AMD CBS --> SMU Debug Options -->SMU Debug --> "GFX DLDO Psm 
Margin Control":
50 : Situation Nomal, issue disappear.
45 : Situation Nomal, issue disappear.
40 : Situation Nomal, issue disappear.
35 : Situation Nomal, issue disappear.
30 : screen black.
25 : screen frozen, then blurred screen.
20 : screen frozen.
15 : screen black.
10 : screen frozen.
5  : screen frozen, then blurred screen.
3. Disable GFXOFF feature
Situation Nomal, issue disappear.

[Why]
Through a period of time debugging with Sys Eng team and SMU team, Sys
Eng team said this is voltage/frequency marginal issue not a F/W or H/W
bug. This experiment proves that default targetPsm [for f=1400MHz] is
not sufficient when GFXOFF is enabled on Picasso.

SMU team think it is an odd test conditions to force sclk="1400MHz" when
GPU is in "gfxoff" state，then wake up the GFX. SCLK should be in the
"lowest frequency" when gfxoff.

[How]
Disable gfxoff when setting manual mode.
Enable gfxoff when setting other mode(exiting manual mode) again.

By the way, from the user point of view, now that user switch to manual
mode and force SCLK Frequency, he don't want SCLK be controlled by
workload.It becomes meaningless to "switch to manual mode" if APU enter "gfxoff"
due to lack of workload at this point.

Tips: Same issue observed on Raven.

Signed-off-by: chen gong 
Reviewed-by: Alex Deucher 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index c8008b956363..d1d2372ab7ca 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -370,6 +370,15 @@ static ssize_t 
amdgpu_set_dpm_forced_performance_level(struct device *dev,
if (current_level == level)
return count;
 
+   if (adev->asic_type == CHIP_RAVEN) {
+   if (adev->rev_id < 8) {
+   if (current_level != AMD_DPM_FORCED_LEVEL_MANUAL && 
level == AMD_DPM_FORCED_LEVEL_MANUAL)
+   amdgpu_gfx_off_ctrl(adev, false);
+   else if (current_level == AMD_DPM_FORCED_LEVEL_MANUAL 
&& level != AMD_DPM_FORCED_LEVEL_MANUAL)
+   amdgpu_gfx_off_ctrl(adev, true);
+   }
+   }
+
/* profile_exit setting is valid only when current mode is in profile 
mode */
if (!(current_level & (AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
-- 
2.25.1

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[PATCH AUTOSEL 5.4 014/175] drm/amdgpu: Init data to avoid oops while reading pp_num_states.

[Sasha Levin]

From: limingyu 

[ Upstream commit 6f81b2d047c59eb77cd04795a44245d6a52cdaec ]

For chip like CHIP_OLAND with si enabled(amdgpu.si_support=1),
the amdgpu will expose pp_num_states to the /sys directory.
In this moment, read the pp_num_states file will excute the
amdgpu_get_pp_num_states func. In our case, the data hasn't
been initialized, so the kernel will access some ilegal
address, trigger the segmentfault and system will reboot soon:

uos@uos-PC:~$ cat /sys/devices/pci\:00/\:00\:00.0/\:01\:00
.0/pp_num_states

Message from syslogd@uos-PC at Apr 22 09:26:20 ...
 kernel:[   82.154129] Internal error: Oops: 9604 [#1] SMP

This patch aims to fix this problem, avoid that reading file
triggers the kernel sementfault.

Signed-off-by: limingyu 
Signed-off-by: zhoubinbin 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 51263b8d94b1..c8008b956363 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -416,8 +416,11 @@ static ssize_t amdgpu_get_pp_num_states(struct device *dev,
ret = smu_get_power_num_states(>smu, );
if (ret)
return ret;
-   } else if (adev->powerplay.pp_funcs->get_pp_num_states)
+   } else if (adev->powerplay.pp_funcs->get_pp_num_states) {
amdgpu_dpm_get_pp_num_states(adev, );
+   } else {
+   memset(, 0, sizeof(data));
+   }
 
buf_len = snprintf(buf, PAGE_SIZE, "states: %d\n", data.nums);
for (i = 0; i < data.nums; i++)
-- 
2.25.1

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[PATCH AUTOSEL 5.4 001/175] drm/amdgpu: fix and cleanup amdgpu_gem_object_close v4

[Sasha Levin]

From: Christian König 

[ Upstream commit 82c416b13cb7d22b96ec0888b296a48dff8a09eb ]

The problem is that we can't add the clear fence to the BO
when there is an exclusive fence on it since we can't
guarantee the the clear fence will complete after the
exclusive one.

To fix this refactor the function and also add the exclusive
fence as shared to the resv object.

v2: fix warning
v3: add excl fence as shared instead
v4: squash in fix for fence handling in amdgpu_gem_object_close

Signed-off-by: Christian König 
Reviewed-by: xinhui pan 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 43 ++---
 1 file changed, 25 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 8ceb44925947..5fa5158d18ee 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -161,16 +161,17 @@ void amdgpu_gem_object_close(struct drm_gem_object *obj,
 
struct amdgpu_bo_list_entry vm_pd;
struct list_head list, duplicates;
+   struct dma_fence *fence = NULL;
struct ttm_validate_buffer tv;
struct ww_acquire_ctx ticket;
struct amdgpu_bo_va *bo_va;
-   int r;
+   long r;
 
INIT_LIST_HEAD();
INIT_LIST_HEAD();
 
tv.bo = >tbo;
-   tv.num_shared = 1;
+   tv.num_shared = 2;
list_add(, );
 
amdgpu_vm_get_pd_bo(vm, , _pd);
@@ -178,28 +179,34 @@ void amdgpu_gem_object_close(struct drm_gem_object *obj,
r = ttm_eu_reserve_buffers(, , false, , false);
if (r) {
dev_err(adev->dev, "leaking bo va because "
-   "we fail to reserve bo (%d)\n", r);
+   "we fail to reserve bo (%ld)\n", r);
return;
}
bo_va = amdgpu_vm_bo_find(vm, bo);
-   if (bo_va && --bo_va->ref_count == 0) {
-   amdgpu_vm_bo_rmv(adev, bo_va);
-
-   if (amdgpu_vm_ready(vm)) {
-   struct dma_fence *fence = NULL;
+   if (!bo_va || --bo_va->ref_count)
+   goto out_unlock;
 
-   r = amdgpu_vm_clear_freed(adev, vm, );
-   if (unlikely(r)) {
-   dev_err(adev->dev, "failed to clear page "
-   "tables on GEM object close (%d)\n", r);
-   }
+   amdgpu_vm_bo_rmv(adev, bo_va);
+   if (!amdgpu_vm_ready(vm))
+   goto out_unlock;
 
-   if (fence) {
-   amdgpu_bo_fence(bo, fence, true);
-   dma_fence_put(fence);
-   }
-   }
+   fence = dma_resv_get_excl(bo->tbo.base.resv);
+   if (fence) {
+   amdgpu_bo_fence(bo, fence, true);
+   fence = NULL;
}
+
+   r = amdgpu_vm_clear_freed(adev, vm, );
+   if (r || !fence)
+   goto out_unlock;
+
+   amdgpu_bo_fence(bo, fence, true);
+   dma_fence_put(fence);
+
+out_unlock:
+   if (unlikely(r < 0))
+   dev_err(adev->dev, "failed to clear page "
+   "tables on GEM object close (%ld)\n", r);
ttm_eu_backoff_reservation(, );
 }
 
-- 
2.25.1

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[PATCH AUTOSEL 5.6 273/606] drm/amd/amdgpu: Update update_config() logic

[Sasha Levin]

From: "Leo (Hanghong) Ma" 

[ Upstream commit 650e723cecf2738dee828564396f3239829aba83 ]

[Why]
For MST case: when update_config is called to disable a stream,
this clears the settings for all the streams on that link.
We should only clear the settings for the stream that was disabled.

[How]
Clear the settings after the call to remove display is called.

Reviewed-by: Harry Wentland 
Reviewed-by: Bhawanpreet Lakha 
Signed-off-by: Leo (Hanghong) Ma 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
index 3abeff7722e3..e80371542622 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
@@ -316,15 +316,15 @@ static void update_config(void *handle, struct 
cp_psp_stream_config *config)
struct mod_hdcp_display *display = _work[link_index].display;
struct mod_hdcp_link *link = _work[link_index].link;
 
-   memset(display, 0, sizeof(*display));
-   memset(link, 0, sizeof(*link));
-
-   display->index = aconnector->base.index;
-
if (config->dpms_off) {
hdcp_remove_display(hdcp_work, link_index, aconnector);
return;
}
+
+   memset(display, 0, sizeof(*display));
+   memset(link, 0, sizeof(*link));
+
+   display->index = aconnector->base.index;
display->state = MOD_HDCP_DISPLAY_ACTIVE;
 
if (aconnector->dc_sink != NULL)
-- 
2.25.1

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[PATCH AUTOSEL 5.6 267/606] drm/amdgpu: Use GEM obj reference for KFD BOs

[Sasha Levin]

From: Felix Kuehling 

[ Upstream commit 39b3128d7ffd44e400e581e6f49e88cb42bef9a1 ]

Releasing the AMDGPU BO ref directly leads to problems when BOs were
exported as DMA bufs. Releasing the GEM reference makes sure that the
AMDGPU/TTM BO is not freed too early.

Also take a GEM reference when importing BOs from DMABufs to keep
references to imported BOs balances properly.

Signed-off-by: Felix Kuehling 
Tested-by: Alex Sierra 
Acked-by: Christian König 
Reviewed-by: Alex Sierra 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index fa8ac9d19a7a..6326c1792270 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -1304,7 +1304,7 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
}
 
/* Free the BO*/
-   amdgpu_bo_unref(>bo);
+   drm_gem_object_put_unlocked(>bo->tbo.base);
mutex_destroy(>lock);
kfree(mem);
 
@@ -1647,7 +1647,8 @@ int amdgpu_amdkfd_gpuvm_import_dmabuf(struct kgd_dev *kgd,
 ALLOC_MEM_FLAGS_VRAM : ALLOC_MEM_FLAGS_GTT) |
ALLOC_MEM_FLAGS_WRITABLE | ALLOC_MEM_FLAGS_EXECUTABLE;
 
-   (*mem)->bo = amdgpu_bo_ref(bo);
+   drm_gem_object_get(>tbo.base);
+   (*mem)->bo = bo;
(*mem)->va = va;
(*mem)->domain = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ?
AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT;
-- 
2.25.1

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[PATCH AUTOSEL 5.6 266/606] drm/amd/powerplay: perform PG ungate prior to CG ungate

[Sasha Levin]

From: Evan Quan 

[ Upstream commit f4fcfa4282c1a1bf51475ebb0ffda623eebf1191 ]

Since gfxoff should be disabled first before trying to access those
GC registers.

Signed-off-by: Evan Quan 
Reviewed-by: Alex Deucher 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 6 +++---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 6 +++---
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c 
b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index e4e5a53b2b4e..8e2acb4df860 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -319,12 +319,12 @@ static void pp_dpm_en_umd_pstate(struct pp_hwmgr  *hwmgr,
if (*level & profile_mode_mask) {
hwmgr->saved_dpm_level = hwmgr->dpm_level;
hwmgr->en_umd_pstate = true;
-   amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
-   AMD_IP_BLOCK_TYPE_GFX,
-   AMD_CG_STATE_UNGATE);
amdgpu_device_ip_set_powergating_state(hwmgr->adev,
AMD_IP_BLOCK_TYPE_GFX,
AMD_PG_STATE_UNGATE);
+   amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
+   AMD_IP_BLOCK_TYPE_GFX,
+   AMD_CG_STATE_UNGATE);
}
} else {
/* exit umd pstate, restore level, enable gfx cg*/
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 96e81c7bc266..e2565967db07 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -1675,12 +1675,12 @@ static int smu_enable_umd_pstate(void *handle,
if (*level & profile_mode_mask) {
smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
smu_dpm_ctx->enable_umd_pstate = true;
-   amdgpu_device_ip_set_clockgating_state(smu->adev,
-  
AMD_IP_BLOCK_TYPE_GFX,
-  
AMD_CG_STATE_UNGATE);
amdgpu_device_ip_set_powergating_state(smu->adev,
   
AMD_IP_BLOCK_TYPE_GFX,
   
AMD_PG_STATE_UNGATE);
+   amdgpu_device_ip_set_clockgating_state(smu->adev,
+  
AMD_IP_BLOCK_TYPE_GFX,
+  
AMD_CG_STATE_UNGATE);
}
} else {
/* exit umd pstate, restore level, enable gfx cg*/
-- 
2.25.1

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[PATCH AUTOSEL 5.6 265/606] drm/amdgpu: drop unnecessary cancel_delayed_work_sync on PG ungate

[Sasha Levin]

From: Evan Quan 

[ Upstream commit 1fe48ec08d9f2e26d893a6c05bd6c99a3490f9ef ]

As this is already properly handled in amdgpu_gfx_off_ctrl(). In fact,
this unnecessary cancel_delayed_work_sync may leave a small time window
for race condition and is dangerous.

Signed-off-by: Evan Quan 
Reviewed-by: Alex Deucher 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c |  6 +-
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c  | 12 +++-
 2 files changed, 4 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 02702597ddeb..012df3d574bf 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4241,11 +4241,7 @@ static int gfx_v10_0_set_powergating_state(void *handle,
switch (adev->asic_type) {
case CHIP_NAVI10:
case CHIP_NAVI14:
-   if (!enable) {
-   amdgpu_gfx_off_ctrl(adev, false);
-   cancel_delayed_work_sync(>gfx.gfx_off_delay_work);
-   } else
-   amdgpu_gfx_off_ctrl(adev, true);
+   amdgpu_gfx_off_ctrl(adev, enable);
break;
default:
break;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 906648fca9ef..914dbd901b98 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -4734,10 +4734,9 @@ static int gfx_v9_0_set_powergating_state(void *handle,
switch (adev->asic_type) {
case CHIP_RAVEN:
case CHIP_RENOIR:
-   if (!enable) {
+   if (!enable)
amdgpu_gfx_off_ctrl(adev, false);
-   cancel_delayed_work_sync(>gfx.gfx_off_delay_work);
-   }
+
if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true);
gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true);
@@ -4761,12 +4760,7 @@ static int gfx_v9_0_set_powergating_state(void *handle,
amdgpu_gfx_off_ctrl(adev, true);
break;
case CHIP_VEGA12:
-   if (!enable) {
-   amdgpu_gfx_off_ctrl(adev, false);
-   cancel_delayed_work_sync(>gfx.gfx_off_delay_work);
-   } else {
-   amdgpu_gfx_off_ctrl(adev, true);
-   }
+   amdgpu_gfx_off_ctrl(adev, enable);
break;
default:
break;
-- 
2.25.1

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[PATCH AUTOSEL 5.6 129/606] drm/amd/display: fix counter in wait_for_no_pipes_pending

[Sasha Levin]

From: Roman Li 

[ Upstream commit 80797dd6f1a525d1160c463d6a9f9d29af182cbb ]

[Why]
Wait counter is not being reset for each pipe.

[How]
Move counter reset into pipe loop scope.

Signed-off-by: Roman Li 
Reviewed-by: Zhan Liu 
Acked-by: Aurabindo Pillai 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 188e51600070..b3987124183a 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -803,11 +803,10 @@ static void disable_dangling_plane(struct dc *dc, struct 
dc_state *context)
 static void wait_for_no_pipes_pending(struct dc *dc, struct dc_state *context)
 {
int i;
-   int count = 0;
-   struct pipe_ctx *pipe;
PERF_TRACE();
for (i = 0; i < MAX_PIPES; i++) {
-   pipe = >res_ctx.pipe_ctx[i];
+   int count = 0;
+   struct pipe_ctx *pipe = >res_ctx.pipe_ctx[i];
 
if (!pipe->plane_state)
continue;
-- 
2.25.1

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[PATCH AUTOSEL 5.6 130/606] drm/amd/display: Prevent dpcd reads with passive dongles

[Sasha Levin]

From: Aurabindo Pillai 

[ Upstream commit e6142dd511425cb827b5db869f489eb81f5f994d ]

[why]
During hotplug, a DP port may be connected to the sink through
passive adapter which does not support DPCD reads. Issuing reads
without checking for this condition will result in errors

[how]
Ensure the link is in aux_mode before initiating operation that result
in a DPCD read.

Signed-off-by: Aurabindo Pillai 
Reviewed-by: Harry Wentland 
Acked-by: Aurabindo Pillai 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c   | 17 +++--
 1 file changed, 11 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 5e27a67fbc58..0cd11d3d4cf4 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1941,17 +1941,22 @@ amdgpu_dm_update_connector_after_detect(struct 
amdgpu_dm_connector *aconnector)
dc_sink_retain(aconnector->dc_sink);
if (sink->dc_edid.length == 0) {
aconnector->edid = NULL;
-   drm_dp_cec_unset_edid(>dm_dp_aux.aux);
+   if (aconnector->dc_link->aux_mode) {
+   drm_dp_cec_unset_edid(
+   >dm_dp_aux.aux);
+   }
} else {
aconnector->edid =
-   (struct edid *) sink->dc_edid.raw_edid;
-
+   (struct edid *)sink->dc_edid.raw_edid;
 
drm_connector_update_edid_property(connector,
-   aconnector->edid);
-   drm_dp_cec_set_edid(>dm_dp_aux.aux,
-   aconnector->edid);
+  aconnector->edid);
+
+   if (aconnector->dc_link->aux_mode)
+   drm_dp_cec_set_edid(>dm_dp_aux.aux,
+   aconnector->edid);
}
+
amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
 
} else {
-- 
2.25.1

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[PATCH AUTOSEL 5.6 036/606] drm/amd/amdgpu: add raven1 part to the gfxoff quirk list

[Sasha Levin]

From: Tom St Denis 

commit 975f543e7522e17b8a4bf34d7daeac44819aee5a upstream.

On my raven1 system (rev c6) with VBIOS 113-RAVEN-114 GFXOFF is
not stable (resulting in large block tiling noise in some applications).

Disabling GFXOFF via the quirk list fixes the problems for me.

Signed-off-by: Tom St Denis 
Reviewed-by: Alex Deucher 
Signed-off-by: Alex Deucher 
Cc: sta...@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 73337e658aff..906648fca9ef 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1177,6 +1177,8 @@ static const struct amdgpu_gfxoff_quirk 
amdgpu_gfxoff_quirk_list[] = {
{ 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 },
/* https://bugzilla.kernel.org/show_bug.cgi?id=207171 */
{ 0x1002, 0x15dd, 0x103c, 0x83e7, 0xd3 },
+   /* GFXOFF is unstable on C6 parts with a VBIOS 113-RAVEN-114 */
+   { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc6 },
{ 0, 0, 0, 0, 0 },
 };
 
-- 
2.25.1

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[PATCH AUTOSEL 5.6 035/606] drm/amd/display: add basic atomic check for cursor plane

[Sasha Levin]

From: Simon Ser 

commit 626bf90fe03fa080d8df06bb0397c95c53ae8e27 upstream.

This patch adds a basic cursor check when an atomic test-only commit is
performed. The position and size of the cursor plane is checked.

This should fix user-space relying on atomic checks to assign buffers to
planes.

Signed-off-by: Simon Ser 
Reported-by: Roman Gilg 
References: https://github.com/emersion/libliftoff/issues/46
Cc: Alex Deucher 
Cc: Harry Wentland 
Reviewed-by: Nicholas Kazlauskas 
Signed-off-by: Alex Deucher 
Cc: sta...@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman 
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 26 +--
 1 file changed, 24 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 8136a58deb39..5e27a67fbc58 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -7716,6 +7716,7 @@ static int dm_update_plane_state(struct dc *dc,
struct drm_crtc_state *old_crtc_state, *new_crtc_state;
struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
+   struct amdgpu_crtc *new_acrtc;
bool needs_reset;
int ret = 0;
 
@@ -7725,9 +7726,30 @@ static int dm_update_plane_state(struct dc *dc,
dm_new_plane_state = to_dm_plane_state(new_plane_state);
dm_old_plane_state = to_dm_plane_state(old_plane_state);
 
-   /*TODO Implement atomic check for cursor plane */
-   if (plane->type == DRM_PLANE_TYPE_CURSOR)
+   /*TODO Implement better atomic check for cursor plane */
+   if (plane->type == DRM_PLANE_TYPE_CURSOR) {
+   if (!enable || !new_plane_crtc ||
+   drm_atomic_plane_disabling(plane->state, 
new_plane_state))
+   return 0;
+
+   new_acrtc = to_amdgpu_crtc(new_plane_crtc);
+
+   if ((new_plane_state->crtc_w > new_acrtc->max_cursor_width) ||
+   (new_plane_state->crtc_h > 
new_acrtc->max_cursor_height)) {
+   DRM_DEBUG_ATOMIC("Bad cursor size %d x %d\n",
+
new_plane_state->crtc_w, new_plane_state->crtc_h);
+   return -EINVAL;
+   }
+
+   if (new_plane_state->crtc_x <= -new_acrtc->max_cursor_width ||
+   new_plane_state->crtc_y <= 
-new_acrtc->max_cursor_height) {
+   DRM_DEBUG_ATOMIC("Bad cursor position %d, %d\n",
+
new_plane_state->crtc_x, new_plane_state->crtc_y);
+   return -EINVAL;
+   }
+
return 0;
+   }
 
needs_reset = should_reset_plane(state, plane, old_plane_state,
 new_plane_state);
-- 
2.25.1

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[PATCH AUTOSEL 5.7 224/274] drm/amdgpu: Sync with VM root BO when switching VM to CPU update mode

[Sasha Levin]

From: Felix Kuehling 

[ Upstream commit 90ca78deb004abe75b5024968a199acb96bb70f9 ]

This fixes an intermittent bug where a root PD clear operation still in
progress could overwrite a PDE update done by the CPU, resulting in a
VM fault.

Fixes: 108b4d928c03 ("drm/amd/amdgpu: Update VM function pointer")
Reported-by: Jay Cornwall 
Tested-by: Jay Cornwall 
Signed-off-by: Felix Kuehling 
Reviewed-by: Christian König 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 11 +--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 6d9252a27916..06242096973c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -2996,10 +2996,17 @@ int amdgpu_vm_make_compute(struct amdgpu_device *adev, 
struct amdgpu_vm *vm,
   !amdgpu_gmc_vram_full_visible(>gmc)),
  "CPU update of VM recommended only for large BAR system\n");
 
-   if (vm->use_cpu_for_update)
+   if (vm->use_cpu_for_update) {
+   /* Sync with last SDMA update/clear before switching to CPU */
+   r = amdgpu_bo_sync_wait(vm->root.base.bo,
+   AMDGPU_FENCE_OWNER_UNDEFINED, true);
+   if (r)
+   goto free_idr;
+
vm->update_funcs = _vm_cpu_funcs;
-   else
+   } else {
vm->update_funcs = _vm_sdma_funcs;
+   }
dma_fence_put(vm->last_update);
vm->last_update = NULL;
vm->is_compute_context = true;
-- 
2.25.1

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[PATCH AUTOSEL 5.7 223/274] drm/amd/powerpay: Disable gfxoff when setting manual mode on picasso and raven

[Sasha Levin]

From: chen gong 

[ Upstream commit cbd2d08c7463e78d625a69e9db27ad3004cbbd99 ]

[Problem description]
1. Boot up picasso platform, launches desktop, Don't do anything (APU enter 
into "gfxoff" state)
2. Remote login to platform using SSH, then type the command line:
sudo su -c "echo manual > 
/sys/class/drm/card0/device/power_dpm_force_performance_level"
sudo su -c "echo 2 > /sys/class/drm/card0/device/pp_dpm_sclk" (fix SCLK 
to 1400MHz)
3. Move the mouse around in Window
4. Phenomenon :  The screen frozen

Tester will switch sclk level during glmark2 run time.
APU will enter "gfxoff" state intermittently during glmark2 run time.
The system got hanged if fix GFXCLK to 1400MHz when APU is in "gfxoff"
state.

[Debug]
1. Fix SCLK to X MHz
1400: screen frozen, screen black, then OS will reboot.
1300: screen frozen.
1200: screen frozen, screen black.
1100: screen frozen, screen black, then OS will reboot.
1000: screen frozen, screen black.
900:  screen frozen, screen black, then OS will reboot.
800:  Situation Nomal, issue disappear.
700:  Situation Nomal, issue disappear.
2. SBIOS setting: AMD CBS --> SMU Debug Options -->SMU Debug --> "GFX DLDO Psm 
Margin Control":
50 : Situation Nomal, issue disappear.
45 : Situation Nomal, issue disappear.
40 : Situation Nomal, issue disappear.
35 : Situation Nomal, issue disappear.
30 : screen black.
25 : screen frozen, then blurred screen.
20 : screen frozen.
15 : screen black.
10 : screen frozen.
5  : screen frozen, then blurred screen.
3. Disable GFXOFF feature
Situation Nomal, issue disappear.

[Why]
Through a period of time debugging with Sys Eng team and SMU team, Sys
Eng team said this is voltage/frequency marginal issue not a F/W or H/W
bug. This experiment proves that default targetPsm [for f=1400MHz] is
not sufficient when GFXOFF is enabled on Picasso.

SMU team think it is an odd test conditions to force sclk="1400MHz" when
GPU is in "gfxoff" state，then wake up the GFX. SCLK should be in the
"lowest frequency" when gfxoff.

[How]
Disable gfxoff when setting manual mode.
Enable gfxoff when setting other mode(exiting manual mode) again.

By the way, from the user point of view, now that user switch to manual
mode and force SCLK Frequency, he don't want SCLK be controlled by
workload.It becomes meaningless to "switch to manual mode" if APU enter "gfxoff"
due to lack of workload at this point.

Tips: Same issue observed on Raven.

Signed-off-by: chen gong 
Reviewed-by: Alex Deucher 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 49e2e43f2e4a..532f4d908b8d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -383,6 +383,15 @@ static ssize_t 
amdgpu_set_dpm_forced_performance_level(struct device *dev,
return count;
}
 
+   if (adev->asic_type == CHIP_RAVEN) {
+   if (adev->rev_id < 8) {
+   if (current_level != AMD_DPM_FORCED_LEVEL_MANUAL && 
level == AMD_DPM_FORCED_LEVEL_MANUAL)
+   amdgpu_gfx_off_ctrl(adev, false);
+   else if (current_level == AMD_DPM_FORCED_LEVEL_MANUAL 
&& level != AMD_DPM_FORCED_LEVEL_MANUAL)
+   amdgpu_gfx_off_ctrl(adev, true);
+   }
+   }
+
/* profile_exit setting is valid only when current mode is in profile 
mode */
if (!(current_level & (AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
-- 
2.25.1

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[PATCH AUTOSEL 5.7 127/274] drm/amd/display: Do not disable pipe split if mode is not supported

[Sasha Levin]

From: Sung Lee 

[ Upstream commit 1dfedb39d38f813357885e19badd1971c17f79a7 ]

[WHY]
If mode is not supported, pipe split should not be disabled.
This may cause more modes to fail.

[HOW]
Check for mode support before disabling pipe split.

This commit was previously reverted as it was thought to
have problems, but those issues have been resolved.

Signed-off-by: Sung Lee 
Reviewed-by: Yongqiang Sun 
Acked-by: Aurabindo Pillai 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 9 +++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index e4348e3b6389..2719cdecc1cb 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -2597,19 +2597,24 @@ int dcn20_validate_apply_pipe_split_flags(
 
/* Avoid split loop looks for lowest voltage level that allows most 
unsplit pipes possible */
if (avoid_split) {
+   int max_mpc_comb = context->bw_ctx.dml.vba.maxMpcComb;
+
for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
if (!context->res_ctx.pipe_ctx[i].stream)
continue;
 
for (vlevel_split = vlevel; vlevel <= 
context->bw_ctx.dml.soc.num_states; vlevel++)
-   if 
(context->bw_ctx.dml.vba.NoOfDPP[vlevel][0][pipe_idx] == 1)
+   if 
(context->bw_ctx.dml.vba.NoOfDPP[vlevel][0][pipe_idx] == 1 &&
+   
context->bw_ctx.dml.vba.ModeSupport[vlevel][0])
break;
/* Impossible to not split this pipe */
if (vlevel > context->bw_ctx.dml.soc.num_states)
vlevel = vlevel_split;
+   else
+   max_mpc_comb = 0;
pipe_idx++;
}
-   context->bw_ctx.dml.vba.maxMpcComb = 0;
+   context->bw_ctx.dml.vba.maxMpcComb = max_mpc_comb;
}
 
/* Split loop sets which pipe should be split based on dml outputs and 
dc flags */
-- 
2.25.1

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[PATCH AUTOSEL 5.7 117/274] drm/amd/display: dmcu wait loop calculation is incorrect in RV

[Sasha Levin]

From: Paul Hsieh 

[ Upstream commit 7fc5c319efceaed1a23b7ef35c333553ce39fecf ]

[Why]
Driver already get display clock from SMU base on MHz, but driver read
again and mutiple 1000 cause wait loop value is overflow.

[How]
remove coding error

Signed-off-by: Paul Hsieh 
Reviewed-by: Eric Yang 
Acked-by: Rodrigo Siqueira 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 .../drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c   | 3 ---
 1 file changed, 3 deletions(-)

diff --git 
a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c
index 97b7f32294fd..c320b7af7d34 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c
@@ -97,9 +97,6 @@ int rv1_vbios_smu_set_dispclk(struct clk_mgr_internal 
*clk_mgr, int requested_di
VBIOSSMC_MSG_SetDispclkFreq,
requested_dispclk_khz / 1000);
 
-   /* Actual dispclk set is returned in the parameter register */
-   actual_dispclk_set_mhz = REG_READ(MP1_SMN_C2PMSG_83) * 1000;
-
if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
if (clk_mgr->dfs_bypass_disp_clk != 
actual_dispclk_set_mhz)
-- 
2.25.1

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[PATCH AUTOSEL 5.7 116/274] drm/amd/display: Correct updating logic of dcn21's pipe VM flags

[Sasha Levin]

From: Dale Zhao 

[ Upstream commit 2a28fe92220a116735ef45939b7edcfee83cc6b0 ]

[Why]:
Renoir's pipe VM flags are not correctly updated if pipe strategy has
changed during some scenarios. It will result in watermarks mistakenly
calculation, thus underflow and garbage appear.

[How]:
Correctly update pipe VM flags to pipes which have been populated.

Signed-off-by: Dale Zhao 
Signed-off-by: Sung Lee 
Reviewed-by: Yongqiang Sun 
Acked-by: Rodrigo Siqueira 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 6 +-
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index a721bb401ef0..6d1736cf5c12 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -1694,12 +1694,8 @@ static int dcn21_populate_dml_pipes_from_context(
 {
uint32_t pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, context, 
pipes);
int i;
-   struct resource_context *res_ctx = >res_ctx;
 
-   for (i = 0; i < dc->res_pool->pipe_count; i++) {
-
-   if (!res_ctx->pipe_ctx[i].stream)
-   continue;
+   for (i = 0; i < pipe_cnt; i++) {
 
pipes[i].pipe.src.hostvm = 1;
pipes[i].pipe.src.gpuvm = 1;
-- 
2.25.1

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[PATCH AUTOSEL 5.7 095/274] drm/amd/display: Revert to old formula in set_vtg_params

[Sasha Levin]

From: Alvin Lee 

[ Upstream commit a1a0e61f3c43c610f0a3c109348c14ce930c1977 ]

[Why]
New formula + cursor change causing underflow
on certain configs

[How]
Rever to old formula

Signed-off-by: Alvin Lee 
Reviewed-by: Yongqiang Sun 
Acked-by: Rodrigo Siqueira 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
index 17d96ec6acd8..ec0ab42becba 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
@@ -299,6 +299,7 @@ void optc1_set_vtg_params(struct timing_generator *optc,
uint32_t asic_blank_end;
uint32_t v_init;
uint32_t v_fp2 = 0;
+   int32_t vertical_line_start;
 
struct optc *optc1 = DCN10TG_FROM_TG(optc);
 
@@ -315,8 +316,9 @@ void optc1_set_vtg_params(struct timing_generator *optc,
patched_crtc_timing.v_border_top;
 
/* if VSTARTUP is before VSYNC, FP2 is the offset, otherwise 0 */
-   if (optc1->vstartup_start > asic_blank_end)
-   v_fp2 = optc1->vstartup_start - asic_blank_end;
+   vertical_line_start = asic_blank_end - optc1->vstartup_start + 1;
+   if (vertical_line_start < 0)
+   v_fp2 = -vertical_line_start;
 
/* Interlace */
if (REG(OTG_INTERLACE_CONTROL)) {
-- 
2.25.1

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[PATCH AUTOSEL 5.7 001/274] drm/amdgpu: fix and cleanup amdgpu_gem_object_close v4

[Sasha Levin]

From: Christian König 

[ Upstream commit 82c416b13cb7d22b96ec0888b296a48dff8a09eb ]

The problem is that we can't add the clear fence to the BO
when there is an exclusive fence on it since we can't
guarantee the the clear fence will complete after the
exclusive one.

To fix this refactor the function and also add the exclusive
fence as shared to the resv object.

v2: fix warning
v3: add excl fence as shared instead
v4: squash in fix for fence handling in amdgpu_gem_object_close

Signed-off-by: Christian König 
Reviewed-by: xinhui pan 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 43 ++---
 1 file changed, 25 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 4277125a79ee..32f36c940abb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -161,16 +161,17 @@ void amdgpu_gem_object_close(struct drm_gem_object *obj,
 
struct amdgpu_bo_list_entry vm_pd;
struct list_head list, duplicates;
+   struct dma_fence *fence = NULL;
struct ttm_validate_buffer tv;
struct ww_acquire_ctx ticket;
struct amdgpu_bo_va *bo_va;
-   int r;
+   long r;
 
INIT_LIST_HEAD();
INIT_LIST_HEAD();
 
tv.bo = >tbo;
-   tv.num_shared = 1;
+   tv.num_shared = 2;
list_add(, );
 
amdgpu_vm_get_pd_bo(vm, , _pd);
@@ -178,28 +179,34 @@ void amdgpu_gem_object_close(struct drm_gem_object *obj,
r = ttm_eu_reserve_buffers(, , false, );
if (r) {
dev_err(adev->dev, "leaking bo va because "
-   "we fail to reserve bo (%d)\n", r);
+   "we fail to reserve bo (%ld)\n", r);
return;
}
bo_va = amdgpu_vm_bo_find(vm, bo);
-   if (bo_va && --bo_va->ref_count == 0) {
-   amdgpu_vm_bo_rmv(adev, bo_va);
-
-   if (amdgpu_vm_ready(vm)) {
-   struct dma_fence *fence = NULL;
+   if (!bo_va || --bo_va->ref_count)
+   goto out_unlock;
 
-   r = amdgpu_vm_clear_freed(adev, vm, );
-   if (unlikely(r)) {
-   dev_err(adev->dev, "failed to clear page "
-   "tables on GEM object close (%d)\n", r);
-   }
+   amdgpu_vm_bo_rmv(adev, bo_va);
+   if (!amdgpu_vm_ready(vm))
+   goto out_unlock;
 
-   if (fence) {
-   amdgpu_bo_fence(bo, fence, true);
-   dma_fence_put(fence);
-   }
-   }
+   fence = dma_resv_get_excl(bo->tbo.base.resv);
+   if (fence) {
+   amdgpu_bo_fence(bo, fence, true);
+   fence = NULL;
}
+
+   r = amdgpu_vm_clear_freed(adev, vm, );
+   if (r || !fence)
+   goto out_unlock;
+
+   amdgpu_bo_fence(bo, fence, true);
+   dma_fence_put(fence);
+
+out_unlock:
+   if (unlikely(r < 0))
+   dev_err(adev->dev, "failed to clear page "
+   "tables on GEM object close (%ld)\n", r);
ttm_eu_backoff_reservation(, );
 }
 
-- 
2.25.1

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[PATCH AUTOSEL 5.7 017/274] drm/amd/display: fix virtual signal dsc setup

[Sasha Levin]

From: Dmytro Laktyushkin 

[ Upstream commit d5bef51f084fccafa984b114ff74a01a64a0e2e3 ]

This prevents dpcd access on virtual links.

Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Eric Bernstein 
Acked-by: Rodrigo Siqueira 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
index 51e0ee6e7695..6590f51caefa 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
@@ -400,7 +400,7 @@ static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, 
bool enable)
struct dc_stream_state *stream = pipe_ctx->stream;
bool result = false;
 
-   if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
+   if (dc_is_virtual_signal(stream->signal) || 
IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
result = true;
else
result = dm_helpers_dp_write_dsc_enable(dc->ctx, stream, 
enable);
-- 
2.25.1

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[PATCH AUTOSEL 5.7 019/274] drm/amdgpu: Init data to avoid oops while reading pp_num_states.

[Sasha Levin]

From: limingyu 

[ Upstream commit 6f81b2d047c59eb77cd04795a44245d6a52cdaec ]

For chip like CHIP_OLAND with si enabled(amdgpu.si_support=1),
the amdgpu will expose pp_num_states to the /sys directory.
In this moment, read the pp_num_states file will excute the
amdgpu_get_pp_num_states func. In our case, the data hasn't
been initialized, so the kernel will access some ilegal
address, trigger the segmentfault and system will reboot soon:

uos@uos-PC:~$ cat /sys/devices/pci\:00/\:00\:00.0/\:01\:00
.0/pp_num_states

Message from syslogd@uos-PC at Apr 22 09:26:20 ...
 kernel:[   82.154129] Internal error: Oops: 9604 [#1] SMP

This patch aims to fix this problem, avoid that reading file
triggers the kernel sementfault.

Signed-off-by: limingyu 
Signed-off-by: zhoubinbin 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index abe94a55ecad..49e2e43f2e4a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -444,8 +444,11 @@ static ssize_t amdgpu_get_pp_num_states(struct device *dev,
ret = smu_get_power_num_states(>smu, );
if (ret)
return ret;
-   } else if (adev->powerplay.pp_funcs->get_pp_num_states)
+   } else if (adev->powerplay.pp_funcs->get_pp_num_states) {
amdgpu_dpm_get_pp_num_states(adev, );
+   } else {
+   memset(, 0, sizeof(data));
+   }
 
pm_runtime_mark_last_busy(ddev->dev);
pm_runtime_put_autosuspend(ddev->dev);
-- 
2.25.1

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[PATCH AUTOSEL 5.7 016/274] drm/amd/display: Force watermark value propagation

[Sasha Levin]

From: Joshua Aberback 

[ Upstream commit 868149c9a072cbdc22a73ce25a487f9fbfa171ef ]

[Why]
The HUBBUB watermark registers are in an area that cannot be power
gated, but the HUBP copies of the watermark values are in areas that can
be power gated. When we power on a pipe, it will not automatically take
the HUBBUB values, we need to force propagation by writing to a
watermark register.

[How]
 - new HUBBUB function to re-write current value in a WM register
 - touch WM register after enabling the plane in program_pipe

Signed-off-by: Joshua Aberback 
Reviewed-by: Jun Lei 
Acked-by: Rodrigo Siqueira 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 5 -
 drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h   | 2 ++
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index a023a4d59f41..c4fa13e4eaf9 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1478,8 +1478,11 @@ static void dcn20_program_pipe(
if (pipe_ctx->update_flags.bits.odm)
hws->funcs.update_odm(dc, context, pipe_ctx);
 
-   if (pipe_ctx->update_flags.bits.enable)
+   if (pipe_ctx->update_flags.bits.enable) {
dcn20_enable_plane(dc, pipe_ctx, context);
+   if (dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes)
+   
dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes(dc->res_pool->hubbub);
+   }
 
if (pipe_ctx->update_flags.raw || 
pipe_ctx->plane_state->update_flags.raw || pipe_ctx->stream->update_flags.raw)
dcn20_update_dchubp_dpp(dc, pipe_ctx, context);
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h 
b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
index f5dd0cc73c63..47a566d82d6e 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
@@ -144,6 +144,8 @@ struct hubbub_funcs {
void (*allow_self_refresh_control)(struct hubbub *hubbub, bool allow);
 
void (*apply_DEDCN21_147_wa)(struct hubbub *hubbub);
+
+   void (*force_wm_propagate_to_pipes)(struct hubbub *hubbub);
 };
 
 struct hubbub {
-- 
2.25.1

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Re: [PATCH 7/7] drm/amd/powerplay: add check for power limit OD support

[Alex Deucher]

On Mon, Jun 8, 2020 at 6:53 AM Evan Quan  wrote:
>
> Before counting the OD percent into max power limit margin.
>
> Change-Id: I83b24d614e07fbc5eac41ff7cd668a1c2f33c6b2
> Signed-off-by: Evan Quan 

Series is:
Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c 
> b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> index 186cdf6696f8..115794557190 100644
> --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> @@ -1920,6 +1920,7 @@ static int navi10_get_power_limit(struct smu_context 
> *smu)
>  {
> struct smu_11_0_powerplay_table *powerplay_table =
> (struct smu_11_0_powerplay_table 
> *)smu->smu_table.power_play_table;
> +   struct smu_11_0_overdrive_table *od_settings = smu->od_settings;
> PPTable_t *pptable = smu->smu_table.driver_pptable;
> uint32_t power_limit, od_percent;
>
> @@ -1934,7 +1935,8 @@ static int navi10_get_power_limit(struct smu_context 
> *smu)
> }
> smu->current_power_limit = power_limit;
>
> -   if (smu->od_enabled) {
> +   if (smu->od_enabled &&
> +   navi10_od_feature_is_supported(od_settings, 
> SMU_11_0_ODCAP_POWER_LIMIT)) {
> od_percent = 
> le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]);
>
> dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d 
> (default: %d)\n", od_percent, power_limit);
> --
> 2.27.0
>
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[PATCH v5 06/13] drm/amd: Gate i2c transaction logs on drm_debug_syslog

[Sean Paul]

From: Sean Paul 

Since the logs protected by these checks specifically target syslog,
use the new drm_debug_syslog_enabled() call to avoid triggering
these prints when only trace is enabled.

Signed-off-by: Sean Paul 

Changes in v5:
-Added to the set
---
 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c 
b/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c
index 9bffbab35041..9bc6baddd302 100644
--- a/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c
+++ b/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c
@@ -233,7 +233,7 @@ static uint32_t smu_v11_0_i2c_transmit(struct i2c_adapter 
*control,
DRM_DEBUG_DRIVER("I2C_Transmit(), address = %x, bytes = %d , data: ",
 (uint16_t)address, numbytes);
 
-   if (drm_debug_enabled(DRM_UT_DRIVER)) {
+   if (drm_debug_syslog_enabled(DRM_UT_DRIVER)) {
print_hex_dump(KERN_INFO, "data: ", DUMP_PREFIX_NONE,
   16, 1, data, numbytes, false);
}
@@ -387,7 +387,7 @@ static uint32_t smu_v11_0_i2c_receive(struct i2c_adapter 
*control,
DRM_DEBUG_DRIVER("I2C_Receive(), address = %x, bytes = %d, data :",
  (uint16_t)address, bytes_received);
 
-   if (drm_debug_enabled(DRM_UT_DRIVER)) {
+   if (drm_debug_syslog_enabled(DRM_UT_DRIVER)) {
print_hex_dump(KERN_INFO, "data: ", DUMP_PREFIX_NONE,
   16, 1, data, bytes_received, false);
}
-- 
Sean Paul, Software Engineer, Google / Chromium OS

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Re: [PATCH] drm/amd/display: Fix indenting in dcn30_set_output_transfer_func()

[Alex Deucher]

On Mon, Jun 8, 2020 at 10:17 AM Dan Carpenter  wrote:
>
> These lines are a part of the if statement and they are supposed to
> be indented one more tab.
>
> Signed-off-by: Dan Carpenter 

Applied.  thanks!

Alex

> ---
>  drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c 
> b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> index ab20320ebc994..37c310dbb3665 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> @@ -203,9 +203,9 @@ bool dcn30_set_output_transfer_func(struct dc *dc,
> stream->out_transfer_func,
> >blender_params, false))
> params = >blender_params;
> -/* there are no ROM LUTs in OUTGAM */
> -   if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED)
> -   BREAK_TO_DEBUGGER();
> +/* there are no ROM LUTs in OUTGAM */
> +   if (stream->out_transfer_func->type == 
> TF_TYPE_PREDEFINED)
> +   BREAK_TO_DEBUGGER();
> }
> }
>
> --
> 2.26.2
>
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Re: [PATCH 3/3] drm/amd/powerplay: correct the APIs' naming

[Alex Deucher]

On Fri, Jun 5, 2020 at 7:04 AM Evan Quan  wrote:
>
> 'UVD' is a HW engine name for Vega20 and before ASICs.
> For newer ASICs, the similar engine is named as 'VCN'.
>
> Change-Id: I5f1b9500ed5d35e395a5da32b81a78eb87bffc68
> Signed-off-by: Evan Quan 

Series is:
Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 13 +
>  drivers/gpu/drm/amd/powerplay/arcturus_ppt.c   |  4 ++--
>  drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h |  2 +-
>  drivers/gpu/drm/amd/powerplay/navi10_ppt.c |  4 ++--
>  drivers/gpu/drm/amd/powerplay/renoir_ppt.c |  4 ++--
>  drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c |  4 ++--
>  drivers/gpu/drm/amd/powerplay/smu_internal.h   |  4 ++--
>  7 files changed, 20 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 
> b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> index 8ea100b3187b..b84eabfc1976 100644
> --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> @@ -455,10 +455,15 @@ int smu_dpm_set_power_gate(struct smu_context *smu, 
> uint32_t block_type,
> return -EOPNOTSUPP;
>
> switch (block_type) {
> +   /*
> +* Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses
> +* AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept.
> +*/
> case AMD_IP_BLOCK_TYPE_UVD:
> -   ret = smu_dpm_set_uvd_enable(smu, !gate);
> +   case AMD_IP_BLOCK_TYPE_VCN:
> +   ret = smu_dpm_set_vcn_enable(smu, !gate);
> if (ret)
> -   dev_err(smu->adev->dev, "Failed to power %s UVD!\n",
> +   dev_err(smu->adev->dev, "Failed to power %s VCN!\n",
> gate ? "gate" : "ungate");
> break;
> case AMD_IP_BLOCK_TYPE_GFX:
> @@ -1328,7 +1333,7 @@ static int smu_hw_init(void *handle)
>
> if (smu->is_apu) {
> smu_powergate_sdma(>smu, false);
> -   smu_dpm_set_uvd_enable(smu, true);
> +   smu_dpm_set_vcn_enable(smu, true);
> smu_dpm_set_jpeg_enable(smu, true);
> smu_set_gfx_cgpg(>smu, true);
> }
> @@ -1460,7 +1465,7 @@ static int smu_hw_fini(void *handle)
>
> if (smu->is_apu) {
> smu_powergate_sdma(>smu, true);
> -   smu_dpm_set_uvd_enable(smu, false);
> +   smu_dpm_set_vcn_enable(smu, false);
> smu_dpm_set_jpeg_enable(smu, false);
> }
>
> diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 
> b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
> index b47b5f257671..e5ef279955d9 100644
> --- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
> @@ -2116,7 +2116,7 @@ static bool arcturus_is_dpm_running(struct smu_context 
> *smu)
> return !!(feature_enabled & SMC_DPM_FEATURE);
>  }
>
> -static int arcturus_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
> +static int arcturus_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
>  {
> struct smu_power_context *smu_power = >smu_power;
> struct smu_power_gate *power_gate = _power->power_gate;
> @@ -2557,7 +2557,7 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
> .dump_pptable = arcturus_dump_pptable,
> .get_power_limit = arcturus_get_power_limit,
> .is_dpm_running = arcturus_is_dpm_running,
> -   .dpm_set_uvd_enable = arcturus_dpm_set_uvd_enable,
> +   .dpm_set_vcn_enable = arcturus_dpm_set_vcn_enable,
> .i2c_eeprom_init = arcturus_i2c_eeprom_control_init,
> .i2c_eeprom_fini = arcturus_i2c_eeprom_control_fini,
> .get_unique_id = arcturus_get_unique_id,
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 
> b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> index 6f31485245bb..b731f9ab05fc 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> @@ -453,7 +453,7 @@ struct pptable_funcs {
>   *clocks);
> int (*get_power_profile_mode)(struct smu_context *smu, char *buf);
> int (*set_power_profile_mode)(struct smu_context *smu, long *input, 
> uint32_t size);
> -   int (*dpm_set_uvd_enable)(struct smu_context *smu, bool enable);
> +   int (*dpm_set_vcn_enable)(struct smu_context *smu, bool enable);
> int (*dpm_set_jpeg_enable)(struct smu_context *smu, bool enable);
> int (*read_sensor)(struct smu_context *smu, enum amd_pp_sensors 
> sensor,
>void *data, uint32_t *size);
> diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c 
> b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> index 70d93a0fd3d0..f21abda8c182 100644
> --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> @@ 

Re: [PATCH 3/3] drm/amd/powerplay: add error messages on some critical paths

[Alex Deucher]

On Fri, Jun 5, 2020 at 7:02 AM Evan Quan  wrote:
>
> Helpful for error diagnostic.
>
> Change-Id: I983ca308a2ee6ed11e16ec59ad97040d98b90512
> Signed-off-by: Evan Quan 

Series is:
Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 118 +++--
>  1 file changed, 87 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 
> b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> index 0c5e062a21a7..11538477da93 100644
> --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> @@ -457,18 +457,30 @@ int smu_dpm_set_power_gate(struct smu_context *smu, 
> uint32_t block_type,
> switch (block_type) {
> case AMD_IP_BLOCK_TYPE_UVD:
> ret = smu_dpm_set_uvd_enable(smu, !gate);
> +   if (ret)
> +   dev_err(smu->adev->dev, "Failed to power %s UVD!\n",
> +   gate ? "gate" : "ungate");
> break;
> case AMD_IP_BLOCK_TYPE_VCE:
> ret = smu_dpm_set_vce_enable(smu, !gate);
> break;
> case AMD_IP_BLOCK_TYPE_GFX:
> ret = smu_gfx_off_control(smu, gate);
> +   if (ret)
> +   dev_err(smu->adev->dev, "Failed to %s gfxoff!\n",
> +   gate ? "enable" : "disable");
> break;
> case AMD_IP_BLOCK_TYPE_SDMA:
> ret = smu_powergate_sdma(smu, gate);
> +   if (ret)
> +   dev_err(smu->adev->dev, "Failed to power %s SDMA!\n",
> +   gate ? "gate" : "ungate");
> break;
> case AMD_IP_BLOCK_TYPE_JPEG:
> ret = smu_dpm_set_jpeg_enable(smu, !gate);
> +   if (ret)
> +   dev_err(smu->adev->dev, "Failed to power %s JPEG!\n",
> +   gate ? "gate" : "ungate");
> break;
> default:
> break;
> @@ -788,8 +800,10 @@ static int smu_late_init(void *handle)
> return 0;
>
> ret = smu_set_default_od_settings(smu);
> -   if (ret)
> +   if (ret) {
> +   dev_err(adev->dev, "Failed to setup default OD settings!\n");
> return ret;
> +   }
>
> /*
>  * Set initialized values (get from vbios) to dpm tables context such 
> as
> @@ -797,20 +811,28 @@ static int smu_late_init(void *handle)
>  * type of clks.
>  */
> ret = smu_populate_smc_tables(smu);
> -   if (ret)
> +   if (ret) {
> +   dev_err(adev->dev, "Failed to setup default dpm clock 
> tables!\n");
> return ret;
> +   }
>
> ret = smu_init_max_sustainable_clocks(smu);
> -   if (ret)
> +   if (ret) {
> +   dev_err(adev->dev, "Failed to init max sustainable 
> clocks!\n");
> return ret;
> +   }
>
> ret = smu_populate_umd_state_clk(smu);
> -   if (ret)
> +   if (ret) {
> +   dev_err(adev->dev, "Failed to populate UMD state clocks!\n");
> return ret;
> +   }
>
> ret = smu_get_power_limit(smu, >default_power_limit, false, 
> false);
> -   if (ret)
> +   if (ret) {
> +   dev_err(adev->dev, "Failed to get default power limit!\n");
> return ret;
> +   }
>
> smu_get_unique_id(smu);
>
> @@ -954,6 +976,8 @@ static int smu_alloc_memory_pool(struct smu_context *smu)
>   _pool->bo,
>   _pool->mc_address,
>   _pool->cpu_addr);
> +   if (ret)
> +   dev_err(adev->dev, "VRAM allocation for dramlog 
> failed!\n");
> break;
> default:
> break;
> @@ -1147,27 +1171,35 @@ static int smu_smc_hw_setup(struct smu_context *smu)
> }
>
> ret = smu_init_display_count(smu, 0);
> -   if (ret)
> +   if (ret) {
> +   dev_info(adev->dev, "Failed to pre-set display count as 
> 0!\n");
> return ret;
> +   }
>
> ret = smu_set_driver_table_location(smu);
> -   if (ret)
> +   if (ret) {
> +   dev_err(adev->dev, "Failed to SetDriverDramAddr!\n");
> return ret;
> +   }
>
> /*
>  * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for 
> tools.
>  */
> ret = smu_set_tool_table_location(smu);
> -   if (ret)
> +   if (ret) {
> +   dev_err(adev->dev, "Failed to SetToolsDramAddr!\n");
> return ret;
> +   }
>
> /*
>  * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify
>  * pool location.
>  */
> ret = smu_notify_memory_pool_location(smu);
> -   if (ret)
> +

Re: [PATCH 1/2] drm/amd/display: Use kvfree() to free coeff in build_regamma()

[Alex Deucher]

On Fri, Jun 5, 2020 at 1:38 PM Denis Efremov  wrote:
>
> Use kvfree() instead of kfree() to free coeff in build_regamma()
> because the memory is allocated with kvzalloc().
>
> Fixes: e752058b8671 ("drm/amd/display: Optimize gamma calculations")
> Cc: sta...@vger.kernel.org
> Signed-off-by: Denis Efremov 

Applied the series.  Thanks!

Alex

> ---
>  drivers/gpu/drm/amd/display/modules/color/color_gamma.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c 
> b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
> index 9431b48aecb4..56bb1f9f77ce 100644
> --- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
> +++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
> @@ -843,7 +843,7 @@ static bool build_regamma(struct pwl_float_data_ex 
> *rgb_regamma,
> pow_buffer_ptr = -1; // reset back to no optimize
> ret = true;
>  release:
> -   kfree(coeff);
> +   kvfree(coeff);
> return ret;
>  }
>
> --
> 2.26.2
>
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Re: [PATCH] drm/amdgpu: skip BAR resizing if the bios already did it

[Felix Kuehling]

Am 2020-06-08 um 3:41 p.m. schrieb Alex Deucher:
> No need to do it again.
>
> Signed-off-by: Alex Deucher 

Acked-by: Felix Kuehling 


> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 +
>  1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 1df28b7bf22e..539010798116 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -909,6 +909,11 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device 
> *adev)
>   if (amdgpu_sriov_vf(adev))
>   return 0;
>  
> + /* skip if the bios has already enabled large BAR */
> + if (adev->gmc.real_vram_size &&
> + (pci_resource_len(adev->pdev, 0) >= adev->gmc.real_vram_size))
> + return 0;
> +
>   /* Check if the root BUS has 64bit memory resources */
>   root = adev->pdev->bus;
>   while (root->parent)
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Re: [PATCH] drm/radeon: Convert get_user_pages() --> pin_user_pages()

[Souptick Joarder]

On Fri, May 29, 2020 at 12:58 PM John Hubbard  wrote:
>
> On 2020-05-28 23:49, Souptick Joarder wrote:
> ...
> >> This is what case 3 was *intended* to cover, but it looks like case 3 
> >> needs to
> >> be written a little better. I'll attempt that, and Cc you on the actual 
> >> patch
> >> to -mm. (I think we also need a case 5 for an unrelated scenario, too, so
> >> it's time.)
> >
> > There were no *case 5* in the other patch posted in -mm. Do we need to add 
> > it ?
> >
>
> Working on figuring that out [1], but it's not directly relevant to this 
> thread.
> Maybe I shouldn't have brought it up here. :)
>
>
> [1] https://lore.kernel.org/r/20200529070343.gl14...@quack2.suse.cz
>
> thanks,
> John Hubbard
> NVIDIA
>
>
>

As this conversion is not relevant ( mentioned above), I have dropped
this patch.
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Re: [PATCH] drm/amdgpu: skip BAR resizing if the bios already did it

[Christian König]

Am 08.06.20 um 21:41 schrieb Alex Deucher:

No need to do it again.

Signed-off-by: Alex Deucher 


Reviewed-by: Christian König 


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 +
  1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 1df28b7bf22e..539010798116 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -909,6 +909,11 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
if (amdgpu_sriov_vf(adev))
return 0;
  
+	/* skip if the bios has already enabled large BAR */

+   if (adev->gmc.real_vram_size &&
+   (pci_resource_len(adev->pdev, 0) >= adev->gmc.real_vram_size))
+   return 0;
+
/* Check if the root BUS has 64bit memory resources */
root = adev->pdev->bus;
while (root->parent)


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[PATCH] drm/amdgpu: skip BAR resizing if the bios already did it

[Alex Deucher]

No need to do it again.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 1df28b7bf22e..539010798116 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -909,6 +909,11 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
if (amdgpu_sriov_vf(adev))
return 0;
 
+   /* skip if the bios has already enabled large BAR */
+   if (adev->gmc.real_vram_size &&
+   (pci_resource_len(adev->pdev, 0) >= adev->gmc.real_vram_size))
+   return 0;
+
/* Check if the root BUS has 64bit memory resources */
root = adev->pdev->bus;
while (root->parent)
-- 
2.25.4

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Re: [PATCH] drm/amd/display: Fix indenting in dcn30_set_output_transfer_func()

[Joe Perches]

On Mon, 2020-06-08 at 20:49 +0300, Dan Carpenter wrote:
> On Mon, Jun 08, 2020 at 10:16:27AM -0700, Joe Perches wrote:
> > On Mon, 2020-06-08 at 17:16 +0300, Dan Carpenter wrote:
> > > These lines are a part of the if statement and they are supposed to
> > > be indented one more tab.
> > > 
> > > Signed-off-by: Dan Carpenter 
> > > ---
> > >  drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c | 6 +++---
> > >  1 file changed, 3 insertions(+), 3 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c 
> > > b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> > > index ab20320ebc994..37c310dbb3665 100644
> > > --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> > > +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> > > @@ -203,9 +203,9 @@ bool dcn30_set_output_transfer_func(struct dc *dc,
> > >   stream->out_transfer_func,
> > >   >blender_params, false))
> > >   params = >blender_params;
> > > -  /* there are no ROM LUTs in OUTGAM */
> > > - if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED)
> > > - BREAK_TO_DEBUGGER();
> > > +  /* there are no ROM LUTs in OUTGAM */
> > > + if (stream->out_transfer_func->type == 
> > > TF_TYPE_PREDEFINED)
> > > + BREAK_TO_DEBUGGER();
> > >   }
> > >   }
> > >  
> > 
> > Maybe the if is at the right indentation but the
> > close brace below the if is misplaced instead?
> > 
> 
> Yeah.  I considered that, but the code is correct, it's just the
> indenting is wrong.  I normally leave drm/amd/ code alone but this
> indenting was so confusing that I though it was worth fixing.

This file seems to heavily use function pointers,
multiple dereferences
with visually similar identifiers,
and it generally makes my eyes hurt
reading the code.

> There are lots of ugly stuff which is not confusing like this:  (The
> line numbers are from next-20200605).

Ick.  Don't give me line numbers.  Now I might have to look...

drivers/gpu/drm/amd/amdgpu/../powerplay/amd_powerplay.c:1530 
pp_asic_reset_mode_2() warn: inconsistent indenting
> drivers/gpu/drm/amd/amdgpu/../display/dc/calcs/dce_calcs.c:3387 bw_calcs() 
> warn: inconsistent indenting
> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dwb.c:104 dwb2_enable() 
> warn: inconsistent indenting
> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp_cm.c:450 
> dpp20_get_blndgam_current() warn: inconsistent indenting
> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp_cm.c:543 
> dpp20_get_shaper_current() warn: inconsistent indenting
> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_mpc.c:306 
> mpc20_get_ogam_current() warn: inconsistent indenting
> drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_dp.c:1519 
> dc_link_dp_perform_link_training() warn: inconsistent indenting
> drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link.c:3137 
> core_link_enable_stream() warn: inconsistent indenting
> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hwseq.c:207 
> dcn30_set_output_transfer_func() warn: inconsistent indenting
> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_dpp.c:650 
> dpp3_get_blndgam_current() warn: inconsistent indenting

OK, so I picked this one at random.

It looks like someone avoided using intentional programming
along with copy/paste combined with being lazy.

It seems as if AMD should use more code reviewers and
perhaps some automated code reformatters before submitting
their code.

This code is:

static enum dc_lut_mode dpp3_get_blndgam_current(struct dpp *dpp_base)
{
enum dc_lut_mode mode;
uint32_t mode_current = 0;
uint32_t in_use = 0;

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

REG_GET(CM_BLNDGAM_CONTROL,
CM_BLNDGAM_MODE_CURRENT, _current);
REG_GET(CM_BLNDGAM_CONTROL,
CM_BLNDGAM_SELECT_CURRENT, _use);

switch (mode_current) {
case 0:
case 1:
mode = LUT_BYPASS;
break;

case 2:
if (in_use == 0)
mode = LUT_RAM_A;
else
mode = LUT_RAM_B;
break;
default:
mode = LUT_BYPASS;
break;
}
return mode;
}

Generic style defects:

o unnecessary initializations
o uint32_t where u32 is simpler
o doesn't fill to 80 columns where reasonable
o magic numbers
o duplicated switch/case blocks
o unnecessary code:
  in_use is only used by case 2
  dpp doesn't seem used at all, but it is via a hidden CTX
  in the REG_GET macro

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h:#define REG_GET(reg_name, 
field, val)   \

Re: [PATCH] drm/amd/display: Fix indenting in dcn30_set_output_transfer_func()

[Joe Perches]

On Mon, 2020-06-08 at 17:16 +0300, Dan Carpenter wrote:
> These lines are a part of the if statement and they are supposed to
> be indented one more tab.
> 
> Signed-off-by: Dan Carpenter 
> ---
>  drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c 
> b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> index ab20320ebc994..37c310dbb3665 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> @@ -203,9 +203,9 @@ bool dcn30_set_output_transfer_func(struct dc *dc,
>   stream->out_transfer_func,
>   >blender_params, false))
>   params = >blender_params;
> -  /* there are no ROM LUTs in OUTGAM */
> - if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED)
> - BREAK_TO_DEBUGGER();
> +  /* there are no ROM LUTs in OUTGAM */
> + if (stream->out_transfer_func->type == 
> TF_TYPE_PREDEFINED)
> + BREAK_TO_DEBUGGER();
>   }
>   }
>  

Maybe the if is at the right indentation but the
close brace below the if is misplaced instead?

Also, because this code uses very long identifiers,
it would read better using wider columns as the
logic in the code itself isn't complicated but the
80 column wrapping makes it seem so.

Wrapping could be something like:
---
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
index ab20320ebc99..56e91a73610f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
@@ -190,18 +190,16 @@ bool dcn30_set_output_transfer_func(struct dc *dc,
struct pwl_params *params = NULL;
bool ret = false;
 
-   /* program OGAM or 3DLUT only for the top pipe*/
+   /* program OGAM or 3DLUT only for the top pipe */
if (pipe_ctx->top_pipe == NULL) {
-   /*program rmu shaper and 3dlut in MPC*/
+   /* program rmu shaper and 3dlut in MPC */
ret = dcn30_set_mpc_shaper_3dlut(pipe_ctx, stream);
-   if (ret == false && mpc->funcs->set_output_gamma && 
stream->out_transfer_func) {
+   if (!ret && mpc->funcs->set_output_gamma && 
stream->out_transfer_func) {
if (stream->out_transfer_func->type == TF_TYPE_HWPWL)
params = >out_transfer_func->pwl;
-   else if (pipe_ctx->stream->out_transfer_func->type ==
-   TF_TYPE_DISTRIBUTED_POINTS &&
-   cm3_helper_translate_curve_to_hw_format(
-   stream->out_transfer_func,
-   >blender_params, false))
+   else if (pipe_ctx->stream->out_transfer_func->type == 
TF_TYPE_DISTRIBUTED_POINTS &&
+
cm3_helper_translate_curve_to_hw_format(stream->out_transfer_func,
+
>blender_params, false))
params = >blender_params;
 /* there are no ROM LUTs in OUTGAM */
if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED)


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Re: [PATCH] drm/amd/display: Fix indenting in dcn30_set_output_transfer_func()

[Dan Carpenter]

On Mon, Jun 08, 2020 at 10:16:27AM -0700, Joe Perches wrote:
> On Mon, 2020-06-08 at 17:16 +0300, Dan Carpenter wrote:
> > These lines are a part of the if statement and they are supposed to
> > be indented one more tab.
> > 
> > Signed-off-by: Dan Carpenter 
> > ---
> >  drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c | 6 +++---
> >  1 file changed, 3 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c 
> > b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> > index ab20320ebc994..37c310dbb3665 100644
> > --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> > +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> > @@ -203,9 +203,9 @@ bool dcn30_set_output_transfer_func(struct dc *dc,
> > stream->out_transfer_func,
> > >blender_params, false))
> > params = >blender_params;
> > -/* there are no ROM LUTs in OUTGAM */
> > -   if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED)
> > -   BREAK_TO_DEBUGGER();
> > +/* there are no ROM LUTs in OUTGAM */
> > +   if (stream->out_transfer_func->type == 
> > TF_TYPE_PREDEFINED)
> > +   BREAK_TO_DEBUGGER();
> > }
> > }
> >  
> 
> Maybe the if is at the right indentation but the
> close brace below the if is misplaced instead?
> 

Yeah.  I considered that, but the code is correct, it's just the
indenting is wrong.  I normally leave drm/amd/ code alone but this
indenting was so confusing that I though it was worth fixing.

There are lots of ugly stuff which is not confusing like this:  (The
line numbers are from next-20200605).

drivers/gpu/drm/amd/amdgpu/../powerplay/amd_powerplay.c:1530 
pp_asic_reset_mode_2() warn: inconsistent indenting
drivers/gpu/drm/amd/amdgpu/../display/dc/calcs/dce_calcs.c:3387 bw_calcs() 
warn: inconsistent indenting
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dwb.c:104 dwb2_enable() 
warn: inconsistent indenting
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp_cm.c:450 
dpp20_get_blndgam_current() warn: inconsistent indenting
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dpp_cm.c:543 
dpp20_get_shaper_current() warn: inconsistent indenting
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_mpc.c:306 
mpc20_get_ogam_current() warn: inconsistent indenting
drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_dp.c:1519 
dc_link_dp_perform_link_training() warn: inconsistent indenting
drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link.c:3137 
core_link_enable_stream() warn: inconsistent indenting
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hwseq.c:207 
dcn30_set_output_transfer_func() warn: inconsistent indenting
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_dpp.c:650 
dpp3_get_blndgam_current() warn: inconsistent indenting
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_dpp.c:747 
dpp3_get_shaper_current() warn: inconsistent indenting
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_dpp_cm.c:67 
dpp30_get_gamcor_current() warn: inconsistent indenting
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_mpc.c:116 
mpc3_get_ogam_current() warn: inconsistent indenting
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_mpc.c:432 
mpc3_get_shaper_current() warn: inconsistent indenting
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_resource.c:2351 
dcn30_update_bw_bounding_box() warn: inconsistent indenting
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_optc.c:178 
optc3_set_dsc_config() warn: inconsistent indenting
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_mode_vba_20.c:2704 
dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
 warn: inconsistent indenting
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_mode_vba_20v2.c:2777 
dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
 warn: inconsistent indenting
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn21/display_mode_vba_21.c:2633 
DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
 warn: inconsistent indenting
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn21/display_mode_vba_21.c:5031 
dml21_ModeSupportAndSystemConfigurationFull() warn: inconsistent indenting
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn21/display_mode_vba_21.c:5036 
dml21_ModeSupportAndSystemConfigurationFull() warn: inconsistent indenting
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn21/display_mode_vba_21.c:5056 
dml21_ModeSupportAndSystemConfigurationFull() warn: inconsistent indenting
drivers/gpu/drm/amd/amdgpu/../display/modules/power/power_helpers.c:731 
dmcu_load_iram() warn: inconsistent indenting
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c:5062 gfx_v8_0_pre_soft_reset() warn: 
inconsistent indenting

regards,
dan carpenter 

Re: [PATCH] drm/amdgpu: stop disable the scheduler during HW fini

[Nirmoy]

Eh sorry. It is merged, I was looking at wrong branch.


Regards,

Nirmoy

On 6/8/20 7:13 PM, Nirmoy wrote:


Hi Christian,


I realized we are still missing this patch while reading dmesg of 
https://gitlab.freedesktop.org/drm/amd/-/issues/1158 




Regards,

Nirmoy

On 2/28/20 4:24 PM, Li, Dennis wrote:


[AMD Public Use]

Looks good to me

Test-by: Dennis Li mailto:dennis...@amd.com>>

Best Regards

Dennis Li

*From:* amd-gfx  *On Behalf Of 
*Deucher, Alexander

*Sent:* Thursday, February 27, 2020 11:18 PM
*To:* Christian König ; Das, Nirmoy 
; amd-gfx@lists.freedesktop.org
*Subject:* Re: [PATCH] drm/amdgpu: stop disable the scheduler during 
HW fini


[AMD Public Use]

Looks good to me.

Reviewed-by: Alex Deucher >




*From:*Christian König >

*Sent:* Thursday, February 27, 2020 9:50 AM
*To:* Das, Nirmoy mailto:nirmoy@amd.com>>; 
amd-gfx@lists.freedesktop.org  
>; Deucher, Alexander 
mailto:alexander.deuc...@amd.com>>
*Subject:* Re: [PATCH] drm/amdgpu: stop disable the scheduler during 
HW fini


Alex any comment on this?

Am 25.02.20 um 14:16 schrieb Nirmoy:
> Acked-by: Nirmoy Das mailto:nirmoy@amd.com>>
>
> On 2/25/20 2:07 PM, Christian König wrote:
>> When we stop the HW for example for GPU reset we should not stop the
>> front-end scheduler. Otherwise we run into intermediate failures 
during

>> command submission.
>>
>> The scheduler should only be stopped in very few cases:
>> 1. We can't get the hardware working in ring or IB test after a GPU
>> reset.
>> 2. The KIQ scheduler is not used in the front-end and should be
>> disabled during GPU reset.
>> 3. In amdgpu_ring_fini() when the driver unloads.
>>
>> Signed-off-by: Christian König >

>> ---
>>   drivers/gpu/drm/amd/amdgpu/cik_sdma.c  |  2 --
>>   drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c |  8 
>>   drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c  |  5 -
>>   drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c  | 25 
+

>>   drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c  |  7 ---
>>   drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c  |  9 -
>>   drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c |  3 ---
>>   drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c |  2 --
>>   drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c |  2 --
>>   drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c |  4 
>>   drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c |  3 ---
>>   drivers/gpu/drm/amd/amdgpu/si_dma.c    |  1 -
>>   drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c  |  3 ---
>>   drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c  |  3 ---
>>   drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c  |  3 ---
>>   drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c  |  7 ---
>>   drivers/gpu/drm/amd/amdgpu/vce_v4_0.c  |  4 
>>   drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c  |  3 ---
>>   drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c  |  9 -
>>   drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c  | 11 +--
>>   20 files changed, 10 insertions(+), 104 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
>> b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
>> index 4274ccf765de..cb3b3a0a1348 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
>> @@ -320,8 +320,6 @@ static void cik_sdma_gfx_stop(struct
>> amdgpu_device *adev)
>>   WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
>>   WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], 0);
>>   }
>> -    sdma0->sched.ready = false;
>> -    sdma1->sched.ready = false;
>>   }
>>     /**
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>> index 7b6158320400..36ce67ce4800 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>> @@ -2391,10 +2391,6 @@ static int gfx_v10_0_cp_gfx_enable(struct
>> amdgpu_device *adev, bool enable)
>>   tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
>>   tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
>>   tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
>> -    if (!enable) {
>> -    for (i = 0; i < adev->gfx.num_gfx_rings; i++)
>> - adev->gfx.gfx_ring[i].sched.ready = false;
>> -    }
>>   WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
>>     for (i = 0; i < adev->usec_timeout; i++) {
>> @@ -2869,16 +2865,12 @@ static int gfx_v10_0_cp_gfx_resume(struct
>> amdgpu_device *adev)
>>     static void gfx_v10_0_cp_compute_enable(struct amdgpu_device
>> *adev, bool enable)
>>   {
>> -    int i;
>> -
>>   

Re: [PATCH] drm/amdgpu: stop disable the scheduler during HW fini

[Nirmoy]

Hi Christian,


I realized we are still missing this patch while reading dmesg of 
https://gitlab.freedesktop.org/drm/amd/-/issues/1158



Regards,

Nirmoy

On 2/28/20 4:24 PM, Li, Dennis wrote:


[AMD Public Use]

Looks good to me

Test-by: Dennis Li mailto:dennis...@amd.com>>

Best Regards

Dennis Li

*From:* amd-gfx  *On Behalf Of 
*Deucher, Alexander

*Sent:* Thursday, February 27, 2020 11:18 PM
*To:* Christian König ; Das, Nirmoy 
; amd-gfx@lists.freedesktop.org
*Subject:* Re: [PATCH] drm/amdgpu: stop disable the scheduler during 
HW fini


[AMD Public Use]

Looks good to me.

Reviewed-by: Alex Deucher >




*From:*Christian König >

*Sent:* Thursday, February 27, 2020 9:50 AM
*To:* Das, Nirmoy mailto:nirmoy@amd.com>>; 
amd-gfx@lists.freedesktop.org  
>; Deucher, Alexander 
mailto:alexander.deuc...@amd.com>>
*Subject:* Re: [PATCH] drm/amdgpu: stop disable the scheduler during 
HW fini


Alex any comment on this?

Am 25.02.20 um 14:16 schrieb Nirmoy:
> Acked-by: Nirmoy Das mailto:nirmoy@amd.com>>
>
> On 2/25/20 2:07 PM, Christian König wrote:
>> When we stop the HW for example for GPU reset we should not stop the
>> front-end scheduler. Otherwise we run into intermediate failures during
>> command submission.
>>
>> The scheduler should only be stopped in very few cases:
>> 1. We can't get the hardware working in ring or IB test after a GPU
>> reset.
>> 2. The KIQ scheduler is not used in the front-end and should be
>> disabled during GPU reset.
>> 3. In amdgpu_ring_fini() when the driver unloads.
>>
>> Signed-off-by: Christian König >

>> ---
>>   drivers/gpu/drm/amd/amdgpu/cik_sdma.c  |  2 --
>>   drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c |  8 
>>   drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c  |  5 -
>>   drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c  | 25 +
>>   drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c  |  7 ---
>>   drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c  |  9 -
>>   drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c |  3 ---
>>   drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c |  2 --
>>   drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c |  2 --
>>   drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c |  4 
>>   drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c |  3 ---
>>   drivers/gpu/drm/amd/amdgpu/si_dma.c    |  1 -
>>   drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c  |  3 ---
>>   drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c  |  3 ---
>>   drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c  |  3 ---
>>   drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c  |  7 ---
>>   drivers/gpu/drm/amd/amdgpu/vce_v4_0.c  |  4 
>>   drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c  |  3 ---
>>   drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c  |  9 -
>>   drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c  | 11 +--
>>   20 files changed, 10 insertions(+), 104 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
>> b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
>> index 4274ccf765de..cb3b3a0a1348 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
>> @@ -320,8 +320,6 @@ static void cik_sdma_gfx_stop(struct
>> amdgpu_device *adev)
>>   WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
>>   WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], 0);
>>   }
>> -    sdma0->sched.ready = false;
>> -    sdma1->sched.ready = false;
>>   }
>>     /**
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>> index 7b6158320400..36ce67ce4800 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>> @@ -2391,10 +2391,6 @@ static int gfx_v10_0_cp_gfx_enable(struct
>> amdgpu_device *adev, bool enable)
>>   tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
>>   tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
>>   tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
>> -    if (!enable) {
>> -    for (i = 0; i < adev->gfx.num_gfx_rings; i++)
>> - adev->gfx.gfx_ring[i].sched.ready = false;
>> -    }
>>   WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
>>     for (i = 0; i < adev->usec_timeout; i++) {
>> @@ -2869,16 +2865,12 @@ static int gfx_v10_0_cp_gfx_resume(struct
>> amdgpu_device *adev)
>>     static void gfx_v10_0_cp_compute_enable(struct amdgpu_device
>> *adev, bool enable)
>>   {
>> -    int i;
>> -
>>   if (enable) {
>>   WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
>>   } else {
>>   WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
>> (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
>> CP_MEC_CNTL__MEC_ME2_HALT_MASK));
>> -    for (i = 0; i < adev->gfx.num_compute_rings; i++)
>> - adev->gfx.compute_ring[i].sched.ready = false;
>>   adev->gfx.kiq.ring.sched.ready = false;
>>   }
>>   udelay(50);
>> diff 

Re: [PATCH] drm/amd/powerplay: move maximum sustainable clock retrieving to .hw_init

[Deucher, Alexander]

[AMD Public Use]

Acked-by: Alex Deucher 

From: Quan, Evan 
Sent: Monday, June 8, 2020 6:46 AM
To: amd-gfx@lists.freedesktop.org 
Cc: Deucher, Alexander ; Quan, Evan 
; Cui, Flora 
Subject: [PATCH] drm/amd/powerplay: move maximum sustainable clock retrieving 
to .hw_init

Since DAL settings come between .hw_init and .late_init of SMU. And
DAL needs to know the maximum sustainable clocks.

Change-Id: I0702b7332a0d7c0b29dfdf4999c18efb588b8862
Signed-off-by: Evan Quan 
Reported-by: Flora Cui 
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 19 +--
 1 file changed, 13 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 725ac90c0f36..6beae3b496be 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -819,12 +819,6 @@ static int smu_late_init(void *handle)
 return ret;
 }

-   ret = smu_init_max_sustainable_clocks(smu);
-   if (ret) {
-   dev_err(adev->dev, "Failed to init max sustainable clocks!\n");
-   return ret;
-   }
-
 ret = smu_populate_umd_state_clk(smu);
 if (ret) {
 dev_err(adev->dev, "Failed to populate UMD state clocks!\n");
@@ -1364,6 +1358,19 @@ static int smu_hw_init(void *handle)
 return ret;
 }

+   /*
+* Move maximum sustainable clock retrieving here considering
+* 1. It is not needed on resume(from S3).
+* 2. DAL settings come between .hw_init and .late_init of SMU.
+*And DAL needs to know the maximum sustainable clocks. Thus
+*it cannot be put in .late_init().
+*/
+   ret = smu_init_max_sustainable_clocks(smu);
+   if (ret) {
+   dev_err(adev->dev, "Failed to init max sustainable clocks!\n");
+   return ret;
+   }
+
 adev->pm.dpm_enabled = true;

 dev_info(adev->dev, "SMU is initialized successfully!\n");
--
2.27.0

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Re: [PATCH] drm/amdgpu/soc15: fix nullptr issue in soc15_read_register() for reg base accessing

[Deucher, Alexander]

[AMD Public Use]

Reviewed-by: Alex Deucher 

From: Liang, Prike 
Sent: Monday, June 8, 2020 3:34 AM
To: amd-gfx@lists.freedesktop.org 
Cc: Deucher, Alexander ; Huang, Ray 
; Liang, Prike 
Subject: [PATCH] drm/amdgpu/soc15: fix nullptr issue in soc15_read_register() 
for reg base accessing

The failed case is no SDMA1 IP for Renoir discovery table while in accessing 
SDMA1 reg base,
thus need have nullptr test for soc15_read_register invoked in MMR addres space 
inqure opt.

Signed-off-by: Prike.Liang 
---
 drivers/gpu/drm/amd/amdgpu/soc15.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c 
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 623745b..3e406ee 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -415,7 +415,8 @@ static int soc15_read_register(struct amdgpu_device *adev, 
u32 se_num,
 *value = 0;
 for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {
 en = _allowed_read_registers[i];
-   if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
+   if (adev->reg_offset[en->hwip][en->inst] &&
+   reg_offset != 
(adev->reg_offset[en->hwip][en->inst][en->seg]
 + en->reg_offset))
 continue;

--
2.7.4

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Re: [PATCH v2 06/18] dma-buf: Use sequence counter with associated wound/wait mutex

[Daniel Vetter]

On Mon, Jun 08, 2020 at 02:57:17AM +0200, Ahmed S. Darwish wrote:
> A sequence counter write side critical section must be protected by some
> form of locking to serialize writers. If the serialization primitive is
> not disabling preemption implicitly, preemption has to be explicitly
> disabled before entering the sequence counter write side critical
> section.
> 
> The dma-buf reservation subsystem uses plain sequence counters to manage
> updates to reservations. Writer serialization is accomplished through a
> wound/wait mutex.
> 
> Acquiring a wound/wait mutex does not disable preemption, so this needs
> to be done manually before and after the write side critical section.
> 
> Use the newly-added seqcount_ww_mutex_t instead:
> 
>   - It associates the ww_mutex with the sequence count, which enables
> lockdep to validate that the write side critical section is properly
> serialized.
> 
>   - It removes the need to explicitly add preempt_disable/enable()
> around the write side critical section because the write_begin/end()
> functions for this new data type automatically do this.
> 
> If lockdep is disabled this ww_mutex lock association is compiled out
> and has neither storage size nor runtime overhead.
> 
> Signed-off-by: Ahmed S. Darwish 

I'm not seeing the patch that adds the seqcount ww_mutex glue and not
quite motivated enough to grab it from lore, so someone else needs to
check the details. Just

Acked-by: Daniel Vetter 

for merging through whatever tree/branch makes sense from me.
-Daniel

> ---
>  drivers/dma-buf/dma-resv.c   | 8 +---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 --
>  include/linux/dma-resv.h | 2 +-
>  3 files changed, 2 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/dma-buf/dma-resv.c b/drivers/dma-buf/dma-resv.c
> index 590ce7ad60a0..3aba2b2bfc48 100644
> --- a/drivers/dma-buf/dma-resv.c
> +++ b/drivers/dma-buf/dma-resv.c
> @@ -128,7 +128,7 @@ subsys_initcall(dma_resv_lockdep);
>  void dma_resv_init(struct dma_resv *obj)
>  {
>   ww_mutex_init(>lock, _ww_class);
> - seqcount_init(>seq);
> + seqcount_ww_mutex_init(>seq, >lock);
>  
>   RCU_INIT_POINTER(obj->fence, NULL);
>   RCU_INIT_POINTER(obj->fence_excl, NULL);
> @@ -259,7 +259,6 @@ void dma_resv_add_shared_fence(struct dma_resv *obj, 
> struct dma_fence *fence)
>   fobj = dma_resv_get_list(obj);
>   count = fobj->shared_count;
>  
> - preempt_disable();
>   write_seqcount_begin(>seq);
>  
>   for (i = 0; i < count; ++i) {
> @@ -281,7 +280,6 @@ void dma_resv_add_shared_fence(struct dma_resv *obj, 
> struct dma_fence *fence)
>   smp_store_mb(fobj->shared_count, count);
>  
>   write_seqcount_end(>seq);
> - preempt_enable();
>   dma_fence_put(old);
>  }
>  EXPORT_SYMBOL(dma_resv_add_shared_fence);
> @@ -308,14 +306,12 @@ void dma_resv_add_excl_fence(struct dma_resv *obj, 
> struct dma_fence *fence)
>   if (fence)
>   dma_fence_get(fence);
>  
> - preempt_disable();
>   write_seqcount_begin(>seq);
>   /* write_seqcount_begin provides the necessary memory barrier */
>   RCU_INIT_POINTER(obj->fence_excl, fence);
>   if (old)
>   old->shared_count = 0;
>   write_seqcount_end(>seq);
> - preempt_enable();
>  
>   /* inplace update, no shared fences */
>   while (i--)
> @@ -393,13 +389,11 @@ int dma_resv_copy_fences(struct dma_resv *dst, struct 
> dma_resv *src)
>   src_list = dma_resv_get_list(dst);
>   old = dma_resv_get_excl(dst);
>  
> - preempt_disable();
>   write_seqcount_begin(>seq);
>   /* write_seqcount_begin provides the necessary memory barrier */
>   RCU_INIT_POINTER(dst->fence_excl, new);
>   RCU_INIT_POINTER(dst->fence, dst_list);
>   write_seqcount_end(>seq);
> - preempt_enable();
>  
>   dma_resv_list_free(src_list);
>   dma_fence_put(old);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> index 6a5b91d23fd9..c71c0bb6ce26 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> @@ -258,11 +258,9 @@ static int amdgpu_amdkfd_remove_eviction_fence(struct 
> amdgpu_bo *bo,
>   new->shared_count = k;
>  
>   /* Install the new fence list, seqcount provides the barriers */
> - preempt_disable();
>   write_seqcount_begin(>seq);
>   RCU_INIT_POINTER(resv->fence, new);
>   write_seqcount_end(>seq);
> - preempt_enable();
>  
>   /* Drop the references to the removed fences or move them to ef_list */
>   for (i = j, k = 0; i < old->shared_count; ++i) {
> diff --git a/include/linux/dma-resv.h b/include/linux/dma-resv.h
> index a6538ae7d93f..d44a77e8a7e3 100644
> --- a/include/linux/dma-resv.h
> +++ b/include/linux/dma-resv.h
> @@ -69,7 +69,7 @@ struct dma_resv_list {
>   */
>  struct dma_resv {
>   struct 

[PATCH] drm/amd/powerplay: Fix buffer overflow in arcturus_get_unique_id()

[Dan Carpenter]

The comments say that the "sn" buffer is used to hold a 16-digit HEX
string so the buffer needs to be at least 17 characters to hold the
NUL terminator.

Fixes: 81a16241114b ("drm/amdgpu: Add unique_id and serial_number for Arcturus 
v3")
Signed-off-by: Dan Carpenter 
---
 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 
b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
index df7b408319f76..a575cb9d1574c 100644
--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
@@ -2266,7 +2266,7 @@ static void arcturus_get_unique_id(struct smu_context 
*smu)
 {
struct amdgpu_device *adev = smu->adev;
uint32_t top32, bottom32, smu_version, size;
-   char sn[16];
+   char sn[20];
uint64_t id;
 
if (smu_get_smc_version(smu, NULL, _version)) {
-- 
2.26.2

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[PATCH] drm/amd/display: Fix indenting in dcn30_set_output_transfer_func()

[Dan Carpenter]

These lines are a part of the if statement and they are supposed to
be indented one more tab.

Signed-off-by: Dan Carpenter 
---
 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
index ab20320ebc994..37c310dbb3665 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
@@ -203,9 +203,9 @@ bool dcn30_set_output_transfer_func(struct dc *dc,
stream->out_transfer_func,
>blender_params, false))
params = >blender_params;
-/* there are no ROM LUTs in OUTGAM */
-   if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED)
-   BREAK_TO_DEBUGGER();
+/* there are no ROM LUTs in OUTGAM */
+   if (stream->out_transfer_func->type == 
TF_TYPE_PREDEFINED)
+   BREAK_TO_DEBUGGER();
}
}
 
-- 
2.26.2

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Re: using amdgpu headless (no monitor)

[Ian Rogers]

Thanks much Alex for responding.

On Thursday, May 28, 2020, 04:29:16 PM EDT, Alex Deucher  wrote:

>> I ask because I want to be able to run a system that is sometimes headless 
>> and sometimes not.  And I'd like to be able to access a current X session 
>> (either logged in or at the login greeter) both remotely (say via VNC) and 
>> locally via the physical display (when it is plugged in).without having to 
>> reboot or lose that X session.
>>
>> However I've noticed that (at least with a Ryzen 3 3200G with Radeon Vega 8) 
>> an X session does not login successfully when accessed remotely if there is 
>> no monitor connected.
>> I assume this is caused by something in the amdgpu driver but I haven't been 
>> able to figure out what.
>
>It's your display manager (X, mutter, kwin, etc.).  They generally
>won't start if they doesn't detect a monitor.  You might be able to
>force one via whatever configuration mechanism is provided by your
>environment.

Yes it seems to be an issue with gnome-shell/mutter (the shell/window manager), 
rather than Xorg (my display server), but I will report back if the relevant 
developer teams of those items have any requests for amdgpu related to this 
issue.

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[PATCH 7/7] drm/amd/powerplay: add check for power limit OD support

[Evan Quan]

Before counting the OD percent into max power limit margin.

Change-Id: I83b24d614e07fbc5eac41ff7cd668a1c2f33c6b2
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c 
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 186cdf6696f8..115794557190 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -1920,6 +1920,7 @@ static int navi10_get_power_limit(struct smu_context *smu)
 {
struct smu_11_0_powerplay_table *powerplay_table =
(struct smu_11_0_powerplay_table 
*)smu->smu_table.power_play_table;
+   struct smu_11_0_overdrive_table *od_settings = smu->od_settings;
PPTable_t *pptable = smu->smu_table.driver_pptable;
uint32_t power_limit, od_percent;
 
@@ -1934,7 +1935,8 @@ static int navi10_get_power_limit(struct smu_context *smu)
}
smu->current_power_limit = power_limit;
 
-   if (smu->od_enabled) {
+   if (smu->od_enabled &&
+   navi10_od_feature_is_supported(od_settings, 
SMU_11_0_ODCAP_POWER_LIMIT)) {
od_percent = 
le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]);
 
dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d 
(default: %d)\n", od_percent, power_limit);
-- 
2.27.0

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[PATCH 4/7] drm/amd/powerplay: simplify the code around setting power limit

[Evan Quan]

Use the cached max/current power limit and move the input check
to the top layer.

Change-Id: Iefc7a89b871ce20422c2e70b8cd7ac85a0a7beba
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 11 +++
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c  | 16 ++--
 2 files changed, 13 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 6757f65fd87e..7cde80c9614f 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -2239,9 +2239,20 @@ int smu_set_power_limit(struct smu_context *smu, 
uint32_t limit)
 
mutex_lock(>mutex);
 
+   if (limit > smu->max_power_limit) {
+   dev_err(smu->adev->dev,
+   "New power limit (%d) is over the max allowed %d\n",
+   limit, smu->max_power_limit);
+   goto out;
+   }
+
+   if (!limit)
+   limit = smu->current_power_limit;
+
if (smu->ppt_funcs->set_power_limit)
ret = smu->ppt_funcs->set_power_limit(smu, limit);
 
+out:
mutex_unlock(>mutex);
 
return ret;
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c 
b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 358c903c4a86..34e9ae813000 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -1082,19 +1082,6 @@ int smu_v11_0_get_current_power_limit(struct smu_context 
*smu,
 int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
 {
int ret = 0;
-   uint32_t max_power_limit;
-
-   max_power_limit = smu_get_max_power_limit(smu);
-
-   if (n > max_power_limit) {
-   dev_err(smu->adev->dev, "New power limit (%d) is over the max 
allowed %d\n",
-   n,
-   max_power_limit);
-   return -EINVAL;
-   }
-
-   if (n == 0)
-   n = smu->default_power_limit;
 
if (!smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
dev_err(smu->adev->dev, "Setting new power limit is not 
supported!\n");
@@ -1106,7 +1093,8 @@ int smu_v11_0_set_power_limit(struct smu_context *smu, 
uint32_t n)
dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", 
__func__);
return ret;
}
-   smu->power_limit = n;
+
+   smu->current_power_limit = n;
 
return 0;
 }
-- 
2.27.0

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[PATCH 2/7] drm/amd/powerplay: maximize code sharing around power limit

[Evan Quan]

Also cache the current and max power limits.

Change-Id: Ida2ce964736bee2e558522441d3505f84c4e00f4
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c  | 49 -
 .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h|  2 +
 drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h |  3 ++
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c| 53 ---
 .../drm/amd/powerplay/sienna_cichlid_ppt.c| 51 --
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 23 
 6 files changed, 94 insertions(+), 87 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 
b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
index 0704a9c1d567..2c78271123f7 100644
--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
@@ -1413,40 +1413,33 @@ static int arcturus_get_power_limit(struct smu_context 
*smu,
 uint32_t *limit,
 bool cap)
 {
+   struct smu_11_0_powerplay_table *powerplay_table =
+   (struct smu_11_0_powerplay_table 
*)smu->smu_table.power_play_table;
PPTable_t *pptable = smu->smu_table.driver_pptable;
-   uint32_t asic_default_power_limit = 0;
-   int ret = 0;
-   int power_src;
-
-   if (!smu->power_limit) {
-   if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
-   power_src = smu_power_get_index(smu, 
SMU_POWER_SOURCE_AC);
-   if (power_src < 0)
-   return -EINVAL;
+   uint32_t power_limit, od_percent;
 
-   ret = smu_send_smc_msg_with_param(smu, 
SMU_MSG_GetPptLimit,
-   power_src << 16, _default_power_limit);
-   if (ret) {
-   dev_err(smu->adev->dev, "[%s] get PPT limit 
failed!", __func__);
-   return ret;
-   }
-   } else {
-   /* the last hope to figure out the ppt limit */
-   if (!pptable) {
-   dev_err(smu->adev->dev, "Cannot get PPT limit 
due to pptable missing!");
-   return -EINVAL;
-   }
-   asic_default_power_limit =
-   pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
+   if (smu_v11_0_get_current_power_limit(smu, _limit)) {
+   /* the last hope to figure out the ppt limit */
+   if (!pptable) {
+   dev_err(smu->adev->dev, "Cannot get PPT limit due to 
pptable missing!");
+   return -EINVAL;
}
+   power_limit =
+   pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
+   }
+   smu->current_power_limit = power_limit;
+
+   if (smu->od_enabled) {
+   od_percent = 
le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]);
+
+   dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d 
(default: %d)\n", od_percent, power_limit);
 
-   smu->power_limit = asic_default_power_limit;
+   power_limit *= (100 + od_percent);
+   power_limit /= 100;
}
+   smu->max_power_limit = power_limit;
 
-   if (cap)
-   *limit = smu_get_max_power_limit(smu);
-   else
-   *limit = smu->power_limit;
+   *limit = (cap ? smu->max_power_limit : smu->current_power_limit);
 
return 0;
 }
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 9276320c09d0..574a793b5d26 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -382,6 +382,8 @@ struct smu_context
bool od_enabled;
uint32_t power_limit;
uint32_t default_power_limit;
+   uint32_t current_power_limit;
+   uint32_t max_power_limit;
 
/* soft pptable */
uint32_t ppt_offset_bytes;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h 
b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
index 9da2f26b7267..2e9939beb128 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
@@ -196,6 +196,9 @@ int smu_v11_0_get_enabled_mask(struct smu_context *smu,
 
 int smu_v11_0_notify_display_change(struct smu_context *smu);
 
+int smu_v11_0_get_current_power_limit(struct smu_context *smu,
+ uint32_t *power_limit);
+
 int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n);
 
 int smu_v11_0_get_current_clk_freq(struct smu_context *smu,
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c 
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index e63498e747ac..b867f94ba559 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ 

[PATCH 6/7] drm/amd/powerplay: correct power limit retrieving based on current power source

[Evan Quan]

Instead of hard coding it as SMU_POWER_SOURCE_AC.

Change-Id: I57066b2c206f8e1e2276f959ff2704dcbe6e5d77
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c 
b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 34e9ae813000..06e3799aa923 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -1065,7 +1065,10 @@ int smu_v11_0_get_current_power_limit(struct smu_context 
*smu,
if (!smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
return -EINVAL;
 
-   power_src = smu_power_get_index(smu, SMU_POWER_SOURCE_AC);
+   power_src = smu_power_get_index(smu,
+   smu->adev->pm.ac_power ?
+   SMU_POWER_SOURCE_AC :
+   SMU_POWER_SOURCE_DC);
if (power_src < 0)
return -EINVAL;
 
-- 
2.27.0

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[PATCH 1/7] drm/amd/powerplay: drop unnecessary get_pptable_power_limit wrappers

[Evan Quan]

Minor code cleanup.

Change-Id: I56a56ebe4a86e7fca5de02d41928f533dda4d185
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 10 --
 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c   |  3 +--
 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h |  3 ---
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c |  3 +--
 drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c |  3 +--
 5 files changed, 3 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index b84eabfc1976..a5fd1284ff1c 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -2827,13 +2827,3 @@ int smu_get_dpm_clock_table(struct smu_context *smu,
 
return ret;
 }
-
-uint32_t smu_get_pptable_power_limit(struct smu_context *smu)
-{
-   uint32_t ret = 0;
-
-   if (smu->ppt_funcs->get_pptable_power_limit)
-   ret = smu->ppt_funcs->get_pptable_power_limit(smu);
-
-   return ret;
-}
diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 
b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
index eb213504c6c5..0704a9c1d567 100644
--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
@@ -2561,7 +2561,7 @@ static uint32_t atcturus_get_max_power_limit(struct 
smu_context *smu) {
struct smu_table_context *table_context = >smu_table;
powerplay_table = table_context->power_play_table;
 
-   max_power_limit = smu_get_pptable_power_limit(smu);
+   max_power_limit = arcturus_get_pptable_power_limit(smu);
 
if (!max_power_limit) {
// If we couldn't get the table limit, fall back on first-read 
value
@@ -2669,7 +2669,6 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
.get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
.set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
.override_pcie_parameters = NULL,
-   .get_pptable_power_limit = arcturus_get_pptable_power_limit,
.set_df_cstate = arcturus_set_df_cstate,
.allow_xgmi_power_down = arcturus_allow_xgmi_power_down,
.log_thermal_throttling_event = arcturus_log_thermal_throttling_event,
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 91e29444134f..9276320c09d0 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -567,7 +567,6 @@ struct pptable_funcs {
int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type 
clk_type, uint32_t *min, uint32_t *max);
int (*set_soft_freq_limited_range)(struct smu_context *smu, enum 
smu_clk_type clk_type, uint32_t min, uint32_t max);
int (*override_pcie_parameters)(struct smu_context *smu);
-   uint32_t (*get_pptable_power_limit)(struct smu_context *smu);
int (*disable_umc_cdr_12gbps_workaround)(struct smu_context *smu);
int (*set_power_source)(struct smu_context *smu, enum 
smu_power_src_type power_src);
void (*log_thermal_throttling_event)(struct smu_context *smu);
@@ -767,6 +766,4 @@ int smu_get_uclk_dpm_states(struct smu_context *smu,
 int smu_get_dpm_clock_table(struct smu_context *smu,
struct dpm_clocks *clock_table);
 
-uint32_t smu_get_pptable_power_limit(struct smu_context *smu);
-
 #endif
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c 
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 9095602bfb6a..e63498e747ac 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -2397,7 +2397,7 @@ static uint32_t navi10_get_max_power_limit(struct 
smu_context *smu) {
struct smu_table_context *table_context = >smu_table;
powerplay_table = table_context->power_play_table;
 
-   max_power_limit = smu_get_pptable_power_limit(smu);
+   max_power_limit = navi10_get_pptable_power_limit(smu);
 
if (!max_power_limit) {
// If we couldn't get the table limit, fall back on first-read 
value
@@ -2504,7 +2504,6 @@ static const struct pptable_funcs navi10_ppt_funcs = {
.override_pcie_parameters = smu_v11_0_override_pcie_parameters,
.set_default_od_settings = navi10_set_default_od_settings,
.od_edit_dpm_table = navi10_od_edit_dpm_table,
-   .get_pptable_power_limit = navi10_get_pptable_power_limit,
.run_btc = navi10_run_btc,
.disable_umc_cdr_12gbps_workaround = 
navi10_disable_umc_cdr_12gbps_workaround,
.set_power_source = smu_v11_0_set_power_source,
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c 
b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index d1018122e474..b83675227a6f 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -1903,7 +1903,7 @@ static 

[PATCH 3/7] drm/amd/powerplay: simplify the code around retrieving power limit

[Evan Quan]

Use the cached max/current power limit for other cases except
.late_init.

Change-Id: Ia4c063207faf051db27be1956f40554913c31c3b
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 7 +++
 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c   | 6 +-
 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 2 +-
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 6 +-
 drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c | 6 +-
 drivers/gpu/drm/amd/powerplay/smu_internal.h   | 3 +++
 6 files changed, 10 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index a5fd1284ff1c..6757f65fd87e 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -831,9 +831,9 @@ static int smu_late_init(void *handle)
return ret;
}
 
-   ret = smu_get_power_limit(smu, >default_power_limit, false, false);
+   ret = smu_get_asic_power_limits(smu);
if (ret) {
-   dev_err(adev->dev, "Failed to get default power limit!\n");
+   dev_err(adev->dev, "Failed to get asic power limits!\n");
return ret;
}
 
@@ -,8 +,7 @@ int smu_get_power_limit(struct smu_context *smu,
mutex_lock(>mutex);
}
 
-   if (smu->ppt_funcs->get_power_limit)
-   ret = smu->ppt_funcs->get_power_limit(smu, limit, def);
+   *limit = (def ? smu->max_power_limit : smu->current_power_limit);
 
if (lock_needed)
mutex_unlock(>mutex);
diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 
b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
index 2c78271123f7..66b8f143cc46 100644
--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
@@ -1409,9 +1409,7 @@ arcturus_get_profiling_clk_mask(struct smu_context *smu,
return 0;
 }
 
-static int arcturus_get_power_limit(struct smu_context *smu,
-uint32_t *limit,
-bool cap)
+static int arcturus_get_power_limit(struct smu_context *smu)
 {
struct smu_11_0_powerplay_table *powerplay_table =
(struct smu_11_0_powerplay_table 
*)smu->smu_table.power_play_table;
@@ -1439,8 +1437,6 @@ static int arcturus_get_power_limit(struct smu_context 
*smu,
}
smu->max_power_limit = power_limit;
 
-   *limit = (cap ? smu->max_power_limit : smu->current_power_limit);
-
return 0;
 }
 
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 574a793b5d26..db63ed057840 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -487,7 +487,7 @@ struct pptable_funcs {
int (*set_performance_level)(struct smu_context *smu, enum 
amd_dpm_forced_level level);
int (*display_disable_memory_clock_switch)(struct smu_context *smu, 
bool disable_memory_clock_switch);
void (*dump_pptable)(struct smu_context *smu);
-   int (*get_power_limit)(struct smu_context *smu, uint32_t *limit, bool 
asic_default);
+   int (*get_power_limit)(struct smu_context *smu);
int (*get_dpm_clk_limited)(struct smu_context *smu, enum smu_clk_type 
clk_type,
   uint32_t dpm_level, uint32_t *freq);
int (*set_df_cstate)(struct smu_context *smu, enum pp_df_cstate state);
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c 
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index b867f94ba559..2e0836976001 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -1922,9 +1922,7 @@ static uint32_t navi10_get_pptable_power_limit(struct 
smu_context *smu)
return pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
 }
 
-static int navi10_get_power_limit(struct smu_context *smu,
- uint32_t *limit,
- bool cap)
+static int navi10_get_power_limit(struct smu_context *smu)
 {
struct smu_11_0_powerplay_table *powerplay_table =
(struct smu_11_0_powerplay_table 
*)smu->smu_table.power_play_table;
@@ -1952,8 +1950,6 @@ static int navi10_get_power_limit(struct smu_context *smu,
}
smu->max_power_limit = power_limit;
 
-   *limit = (cap ? smu->max_power_limit : smu->current_power_limit);
-
return 0;
 }
 
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c 
b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index c427e233dfad..44719c110655 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -1743,9 +1743,7 @@ static uint32_t 
sienna_cichlid_get_pptable_power_limit(struct smu_context *smu)
return pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
 }
 
-static 

[PATCH 5/7] drm/amd/powerplay: drop unused code around power limit

[Evan Quan]

Drop unused APIs, variables and argument.

Change-Id: I59c99de30bf3fa0e5ed058aaa8ab95d0a9c748aa
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c|  4 +--
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 20 ---
 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c  | 35 ---
 .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h|  6 +---
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c| 34 --
 .../drm/amd/powerplay/sienna_cichlid_ppt.c| 34 --
 drivers/gpu/drm/amd/powerplay/smu_internal.h  |  2 --
 7 files changed, 10 insertions(+), 125 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index b2cdc8a1268f..395ddbe2461c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -2739,7 +2739,7 @@ static ssize_t amdgpu_hwmon_show_power_cap_max(struct 
device *dev,
return r;
 
if (is_support_sw_smu(adev)) {
-   smu_get_power_limit(>smu, , true, true);
+   smu_get_power_limit(>smu, , true);
size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 100);
} else if (adev->powerplay.pp_funcs && 
adev->powerplay.pp_funcs->get_power_limit) {

adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, , 
true);
@@ -2771,7 +2771,7 @@ static ssize_t amdgpu_hwmon_show_power_cap(struct device 
*dev,
return r;
 
if (is_support_sw_smu(adev)) {
-   smu_get_power_limit(>smu, , false,  true);
+   smu_get_power_limit(>smu, , false);
size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 100);
} else if (adev->powerplay.pp_funcs && 
adev->powerplay.pp_funcs->get_power_limit) {

adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, , 
false);
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 7cde80c9614f..725ac90c0f36 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -2210,24 +2210,18 @@ int smu_set_fan_speed_rpm(struct smu_context *smu, 
uint32_t speed)
 
 int smu_get_power_limit(struct smu_context *smu,
uint32_t *limit,
-   bool def,
-   bool lock_needed)
+   bool max_setting)
 {
-   int ret = 0;
-
-   if (lock_needed) {
-   if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
-   return -EOPNOTSUPP;
+   if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
+   return -EOPNOTSUPP;
 
-   mutex_lock(>mutex);
-   }
+   mutex_lock(>mutex);
 
-   *limit = (def ? smu->max_power_limit : smu->current_power_limit);
+   *limit = (max_setting ? smu->max_power_limit : 
smu->current_power_limit);
 
-   if (lock_needed)
-   mutex_unlock(>mutex);
+   mutex_unlock(>mutex);
 
-   return ret;
+   return 0;
 }
 
 int smu_set_power_limit(struct smu_context *smu, uint32_t limit)
diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 
b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
index 66b8f143cc46..c104844b28f1 100644
--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
@@ -2411,13 +2411,6 @@ static bool arcturus_is_baco_supported(struct 
smu_context *smu)
return (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : false;
 }
 
-static uint32_t arcturus_get_pptable_power_limit(struct smu_context *smu)
-{
-   PPTable_t *pptable = smu->smu_table.driver_pptable;
-
-   return pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
-}
-
 static int arcturus_set_df_cstate(struct smu_context *smu,
  enum pp_df_cstate state)
 {
@@ -2544,33 +2537,6 @@ static int arcturus_set_thermal_range(struct smu_context 
*smu,
return 0;
 }
 
-static uint32_t atcturus_get_max_power_limit(struct smu_context *smu) {
-   uint32_t od_limit, max_power_limit;
-   struct smu_11_0_powerplay_table *powerplay_table = NULL;
-   struct smu_table_context *table_context = >smu_table;
-   powerplay_table = table_context->power_play_table;
-
-   max_power_limit = arcturus_get_pptable_power_limit(smu);
-
-   if (!max_power_limit) {
-   // If we couldn't get the table limit, fall back on first-read 
value
-   if (!smu->default_power_limit)
-   smu->default_power_limit = smu->power_limit;
-   max_power_limit = smu->default_power_limit;
-   }
-
-   if (smu->od_enabled) {
-   od_limit = 
le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]);
-
-   dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d 
(default: %d)\n", od_limit, smu->default_power_limit);
-
-   max_power_limit 

[PATCH] drm/amd/powerplay: move maximum sustainable clock retrieving to .hw_init

[Evan Quan]

Since DAL settings come between .hw_init and .late_init of SMU. And
DAL needs to know the maximum sustainable clocks.

Change-Id: I0702b7332a0d7c0b29dfdf4999c18efb588b8862
Signed-off-by: Evan Quan 
Reported-by: Flora Cui 
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 19 +--
 1 file changed, 13 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 725ac90c0f36..6beae3b496be 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -819,12 +819,6 @@ static int smu_late_init(void *handle)
return ret;
}
 
-   ret = smu_init_max_sustainable_clocks(smu);
-   if (ret) {
-   dev_err(adev->dev, "Failed to init max sustainable clocks!\n");
-   return ret;
-   }
-
ret = smu_populate_umd_state_clk(smu);
if (ret) {
dev_err(adev->dev, "Failed to populate UMD state clocks!\n");
@@ -1364,6 +1358,19 @@ static int smu_hw_init(void *handle)
return ret;
}
 
+   /*
+* Move maximum sustainable clock retrieving here considering
+* 1. It is not needed on resume(from S3).
+* 2. DAL settings come between .hw_init and .late_init of SMU.
+*And DAL needs to know the maximum sustainable clocks. Thus
+*it cannot be put in .late_init().
+*/
+   ret = smu_init_max_sustainable_clocks(smu);
+   if (ret) {
+   dev_err(adev->dev, "Failed to init max sustainable clocks!\n");
+   return ret;
+   }
+
adev->pm.dpm_enabled = true;
 
dev_info(adev->dev, "SMU is initialized successfully!\n");
-- 
2.27.0

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Re: [PATCH 02/28] drm/amd/display: Rework dsc to isolate FPU operations

[Christian König]

Am 08.06.20 um 06:59 schrieb Qingqing Zhuo:

From: Rodrigo Siqueira 

When we want to use float point operation on Linux
we need to use within special kernel protection
(`kernel_fpu_{begin,end}()`.), otherwise the kernel
can clobber userspace FPU register state. For detecting
these issues we use a tool named objtool (with -Ffa
flags) to highlight the FPU problems, all warnings can
be summed up as follows:

./tools/objtool/objtool check -Ffa
drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.o

[..] dc/dsc/rc_calc.o: warning: objtool: get_qp_set()+0x2f8:
FPU instruction outside of kernel_fpu_{begin,end}()
[..] dc/dsc/rc_calc.o: warning: objtool: dsc_roundf()+0x5:
FPU instruction outside of kernel_fpu_{begin,end}()
[..] dc/dsc/rc_calc.o: warning: objtool: dsc_ceil()+0x5:
FPU instruction outside of kernel_fpu_{begin,end}()
[..] dc/dsc/rc_calc.o: warning: objtool: get_ofs_set()+0x3eb:
FPU instruction outside of kernel_fpu_{begin,end}()
[..] dc/dsc/rc_calc.o: warning: objtool: calc_rc_params()+0x3c:
FPU instruction outside of kernel_fpu_{begin,end}()
[..] dc/dsc/dc_dsc.o: warning: objtool:
get_dsc_bandwidth_range.isra.0()+0x8d:
FPU instruction outside of kernel_fpu_{begin,end}()
[..] dc/dsc/dc_dsc.o: warning: objtool: setup_dsc_config()+0x2ef:
FPU instruction outside of kernel_fpu_{begin,end}()
[..] dc/dsc/rc_calc_dpi.o: warning: objtool:copy_pps_fields()+0xbb:
FPU instruction outside of kernel_fpu_{begin,end}()
[..] dc/dsc/rc_calc_dpi.o: warning: objtool:
dscc_compute_dsc_parameters()+0x7b:
FPU instruction outside of kernel_fpu_{begin,end}()

This commit fixes the above issues by rework DSC as described:

1. Isolate all FPU operations in a single file;
2. Use FPU flags only in the file that handles FPU operations;
3. Isolate all functions that require float point operation in static
functions;
4. Add a mid-layer function that does not use any float point operation,
and that could be safely invoked in other parts of the code.
5. Keep float point operation under DC_FP_{START/END} macro.

CC: Christian König 
CC: Alexander Deucher 
CC: Peter Zijlstra 
CC: Tony Cheng 
CC: Harry Wentland 
Signed-off-by: Rodrigo Siqueira 
Reviewed-by: Mikita Lipski 
Acked-by: Qingqing Zhuo 
---
  drivers/gpu/drm/amd/display/dc/dsc/Makefile   |   2 -
  drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c   |  18 +--
  drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c  | 151 +-
  drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h  |   5 +-
  .../gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c  |  27 +---
  5 files changed, 153 insertions(+), 50 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dsc/Makefile 
b/drivers/gpu/drm/amd/display/dc/dsc/Makefile
index 3f66868df171..ea29cf95d470 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dsc/Makefile
@@ -28,8 +28,6 @@ endif
  endif
  
  CFLAGS_$(AMDDALPATH)/dc/dsc/rc_calc.o := $(dsc_ccflags)

-CFLAGS_$(AMDDALPATH)/dc/dsc/rc_calc_dpi.o := $(dsc_ccflags)
-CFLAGS_$(AMDDALPATH)/dc/dsc/dc_dsc.o := $(dsc_ccflags)
  
  DSC = dc_dsc.o rc_calc.o rc_calc_dpi.o
  
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

index 0ea6662a1563..0c7f247bb7de 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
@@ -22,10 +22,12 @@
   * Author: AMD
   */
  
+#include 

  #include "dc_hw_types.h"
  #include "dsc.h"
  #include 
  #include "dc.h"
+#include "rc_calc.h"
  
  /* This module's internal functions */
  
@@ -304,22 +306,6 @@ static inline uint32_t dsc_div_by_10_round_up(uint32_t value)

return (value + 9) / 10;
  }
  
-static inline uint32_t calc_dsc_bpp_x16(uint32_t stream_bandwidth_kbps, uint32_t pix_clk_100hz, uint32_t bpp_increment_div)

-{
-   uint32_t dsc_target_bpp_x16;
-   float f_dsc_target_bpp;
-   float f_stream_bandwidth_100bps = stream_bandwidth_kbps * 10.0f;
-   uint32_t precision = bpp_increment_div; // bpp_increment_div is 
actually precision
-
-   f_dsc_target_bpp = f_stream_bandwidth_100bps / pix_clk_100hz;
-
-   // Round down to the nearest precision stop to bring it into DSC spec 
range
-   dsc_target_bpp_x16 = (uint32_t)(f_dsc_target_bpp * precision);
-   dsc_target_bpp_x16 = (dsc_target_bpp_x16 * 16) / precision;
-
-   return dsc_target_bpp_x16;
-}
-
  /* Get DSC bandwidth range based on [min_bpp, max_bpp] target bitrate range, 
and timing's pixel clock
   * and uncompressed bandwidth.
   */
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c 
b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c
index 03ae15946c6d..667afbc260f9 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c
@@ -23,6 +23,7 @@
   * Authors: AMD
   *
   */
+#include 
  
  #include "os_types.h"

  #include "rc_calc.h"
@@ -40,7 +41,8 @@
break
  
  
-void get_qp_set(qp_set qps, enum colour_mode cm, enum bits_per_comp bpc, enum max_min max_min, float bpp)

RE: [PATCH] drm/amdgpu/soc15: fix using ip discovery tables on renoir (v2)

[Liang, Prike]

[AMD Official Use Only - Internal Distribution Only]

Regards the gpu info inquire failed during start X, have sent a following fix 
for the issue.

drm/amdgpu/soc15: fix nullptr issue in soc15_read_register() for reg base 
accessing

> -Original Message-
> From: Liang, Prike
> Sent: Monday, June 8, 2020 2:00 PM
> To: Alex Deucher ; amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander 
> Subject: RE: [PATCH] drm/amdgpu/soc15: fix using ip discovery tables on
> renoir (v2)
>
> According to reg_offset assignment in amdgpu_discovery_reg_base_init() the
> reg_offset is calculated as IP base address pointer therefore PWR IP base
> should be map to adev->reg_offset[SMUIO_HWIP][0] + 1. Moreover, not
> sure whether can use/need  the mapped address to access
> PWR_MISC_CNTL_STATUS for controlling  the GFX CGPG in Renoir.
>
> Base on the above modify the PWR IP access  nullptr issue should can be fix,
> but should hold on this patch since  start X will be occur other nullptr issue
> during amdgpu_info_ioctl().
>
> Thanks,
> Prike
> > -Original Message-
> > From: Alex Deucher 
> > Sent: Friday, June 5, 2020 11:40 PM
> > To: amd-gfx@lists.freedesktop.org; Liang, Prike 
> > Cc: Deucher, Alexander 
> > Subject: [PATCH] drm/amdgpu/soc15: fix using ip discovery tables on
> > renoir
> > (v2)
> >
> > The PWR block moved into SMUIO, so the ip discovery table doesn't have
> > an entry for PWR, but the register has the same absolute offset, so
> > just patch up the offsets after updating the offsets from the IP discovery
> table.
> >
> > v2: PWR became SMUIO block 1.  fix the mapping.
> >
> > Signed-off-by: Alex Deucher 
> > ---
> >  drivers/gpu/drm/amd/amdgpu/soc15.c | 3 +++
> >  1 file changed, 3 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
> > b/drivers/gpu/drm/amd/amdgpu/soc15.c
> > index 623745b2d8b3..dd17a8422111 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> > @@ -686,6 +686,9 @@ int soc15_set_ip_blocks(struct amdgpu_device
> *adev)
> >  DRM_WARN("failed to init reg base from ip
> discovery table, "
> >   "fallback to legacy init method\n");
> >  vega10_reg_base_init(adev);
> > +} else {
> > +/* PWR block was merged into SMUIO on
> > renoir and became SMUIO block 1 */
> > +adev->reg_offset[PWR_HWIP][0] = adev-
> > >reg_offset[SMUIO_HWIP][1];
> >  }
> >  }
> >  break;
> > --
> > 2.25.4

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[PATCH] drm/amdgpu/soc15: fix nullptr issue in soc15_read_register() for reg base accessing

[Prike.Liang]

The failed case is no SDMA1 IP for Renoir discovery table while in accessing 
SDMA1 reg base,
thus need have nullptr test for soc15_read_register invoked in MMR addres space 
inqure opt.

Signed-off-by: Prike.Liang 
---
 drivers/gpu/drm/amd/amdgpu/soc15.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c 
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 623745b..3e406ee 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -415,7 +415,8 @@ static int soc15_read_register(struct amdgpu_device *adev, 
u32 se_num,
*value = 0;
for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {
en = _allowed_read_registers[i];
-   if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
+   if (adev->reg_offset[en->hwip][en->inst] &&
+   reg_offset != 
(adev->reg_offset[en->hwip][en->inst][en->seg]
+ en->reg_offset))
continue;
 
-- 
2.7.4

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[PATCH v2 06/18] dma-buf: Use sequence counter with associated wound/wait mutex

[Ahmed S. Darwish]

A sequence counter write side critical section must be protected by some
form of locking to serialize writers. If the serialization primitive is
not disabling preemption implicitly, preemption has to be explicitly
disabled before entering the sequence counter write side critical
section.

The dma-buf reservation subsystem uses plain sequence counters to manage
updates to reservations. Writer serialization is accomplished through a
wound/wait mutex.

Acquiring a wound/wait mutex does not disable preemption, so this needs
to be done manually before and after the write side critical section.

Use the newly-added seqcount_ww_mutex_t instead:

  - It associates the ww_mutex with the sequence count, which enables
lockdep to validate that the write side critical section is properly
serialized.

  - It removes the need to explicitly add preempt_disable/enable()
around the write side critical section because the write_begin/end()
functions for this new data type automatically do this.

If lockdep is disabled this ww_mutex lock association is compiled out
and has neither storage size nor runtime overhead.

Signed-off-by: Ahmed S. Darwish 
---
 drivers/dma-buf/dma-resv.c   | 8 +---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 --
 include/linux/dma-resv.h | 2 +-
 3 files changed, 2 insertions(+), 10 deletions(-)

diff --git a/drivers/dma-buf/dma-resv.c b/drivers/dma-buf/dma-resv.c
index 590ce7ad60a0..3aba2b2bfc48 100644
--- a/drivers/dma-buf/dma-resv.c
+++ b/drivers/dma-buf/dma-resv.c
@@ -128,7 +128,7 @@ subsys_initcall(dma_resv_lockdep);
 void dma_resv_init(struct dma_resv *obj)
 {
ww_mutex_init(>lock, _ww_class);
-   seqcount_init(>seq);
+   seqcount_ww_mutex_init(>seq, >lock);
 
RCU_INIT_POINTER(obj->fence, NULL);
RCU_INIT_POINTER(obj->fence_excl, NULL);
@@ -259,7 +259,6 @@ void dma_resv_add_shared_fence(struct dma_resv *obj, struct 
dma_fence *fence)
fobj = dma_resv_get_list(obj);
count = fobj->shared_count;
 
-   preempt_disable();
write_seqcount_begin(>seq);
 
for (i = 0; i < count; ++i) {
@@ -281,7 +280,6 @@ void dma_resv_add_shared_fence(struct dma_resv *obj, struct 
dma_fence *fence)
smp_store_mb(fobj->shared_count, count);
 
write_seqcount_end(>seq);
-   preempt_enable();
dma_fence_put(old);
 }
 EXPORT_SYMBOL(dma_resv_add_shared_fence);
@@ -308,14 +306,12 @@ void dma_resv_add_excl_fence(struct dma_resv *obj, struct 
dma_fence *fence)
if (fence)
dma_fence_get(fence);
 
-   preempt_disable();
write_seqcount_begin(>seq);
/* write_seqcount_begin provides the necessary memory barrier */
RCU_INIT_POINTER(obj->fence_excl, fence);
if (old)
old->shared_count = 0;
write_seqcount_end(>seq);
-   preempt_enable();
 
/* inplace update, no shared fences */
while (i--)
@@ -393,13 +389,11 @@ int dma_resv_copy_fences(struct dma_resv *dst, struct 
dma_resv *src)
src_list = dma_resv_get_list(dst);
old = dma_resv_get_excl(dst);
 
-   preempt_disable();
write_seqcount_begin(>seq);
/* write_seqcount_begin provides the necessary memory barrier */
RCU_INIT_POINTER(dst->fence_excl, new);
RCU_INIT_POINTER(dst->fence, dst_list);
write_seqcount_end(>seq);
-   preempt_enable();
 
dma_resv_list_free(src_list);
dma_fence_put(old);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index 6a5b91d23fd9..c71c0bb6ce26 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -258,11 +258,9 @@ static int amdgpu_amdkfd_remove_eviction_fence(struct 
amdgpu_bo *bo,
new->shared_count = k;
 
/* Install the new fence list, seqcount provides the barriers */
-   preempt_disable();
write_seqcount_begin(>seq);
RCU_INIT_POINTER(resv->fence, new);
write_seqcount_end(>seq);
-   preempt_enable();
 
/* Drop the references to the removed fences or move them to ef_list */
for (i = j, k = 0; i < old->shared_count; ++i) {
diff --git a/include/linux/dma-resv.h b/include/linux/dma-resv.h
index a6538ae7d93f..d44a77e8a7e3 100644
--- a/include/linux/dma-resv.h
+++ b/include/linux/dma-resv.h
@@ -69,7 +69,7 @@ struct dma_resv_list {
  */
 struct dma_resv {
struct ww_mutex lock;
-   seqcount_t seq;
+   seqcount_ww_mutex_t seq;
 
struct dma_fence __rcu *fence_excl;
struct dma_resv_list __rcu *fence;
-- 
2.20.1

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RE: [PATCH] drm/amdgpu/soc15: fix using ip discovery tables on renoir (v2)

[Liang, Prike]

[AMD Official Use Only - Internal Distribution Only]

According to reg_offset assignment in amdgpu_discovery_reg_base_init() the 
reg_offset is calculated as IP base address pointer therefore PWR IP base 
should be map to adev->reg_offset[SMUIO_HWIP][0] + 1. Moreover, not sure 
whether can use/need  the mapped address to access PWR_MISC_CNTL_STATUS for 
controlling  the GFX CGPG in Renoir.

Base on the above modify the PWR IP access  nullptr issue should can be fix, 
but should hold on this patch since  start X will be occur other nullptr issue 
during amdgpu_info_ioctl().

Thanks,
Prike
> -Original Message-
> From: Alex Deucher 
> Sent: Friday, June 5, 2020 11:40 PM
> To: amd-gfx@lists.freedesktop.org; Liang, Prike 
> Cc: Deucher, Alexander 
> Subject: [PATCH] drm/amdgpu/soc15: fix using ip discovery tables on renoir
> (v2)
>
> The PWR block moved into SMUIO, so the ip discovery table doesn't have an
> entry for PWR, but the register has the same absolute offset, so just patch up
> the offsets after updating the offsets from the IP discovery table.
>
> v2: PWR became SMUIO block 1.  fix the mapping.
>
> Signed-off-by: Alex Deucher 
> ---
>  drivers/gpu/drm/amd/amdgpu/soc15.c | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
> b/drivers/gpu/drm/amd/amdgpu/soc15.c
> index 623745b2d8b3..dd17a8422111 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> @@ -686,6 +686,9 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
>  DRM_WARN("failed to init reg base from ip
> discovery table, "
>   "fallback to legacy init method\n");
>  vega10_reg_base_init(adev);
> +} else {
> +/* PWR block was merged into SMUIO on
> renoir and became SMUIO block 1 */
> +adev->reg_offset[PWR_HWIP][0] = adev-
> >reg_offset[SMUIO_HWIP][1];
>  }
>  }
>  break;
> --
> 2.25.4

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