Re: [PATCH v3 07/15] drm/amdgpu: Use PCI_IRQ_MSI_TYPES where appropriate

2020-06-09 Thread Alex Deucher 
On Tue, Jun 9, 2020 at 5:18 AM Piotr Stankiewicz
 wrote:
>
> Seeing as there is shorthand available to use when asking for any type
> of interrupt, or any type of message signalled interrupt, leverage it.
>
> Signed-off-by: Piotr Stankiewicz 
> Reviewed-by: Andy Shevchenko 

Acked-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 11 +--
>  1 file changed, 1 insertion(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> index 0cc4c67f95f7..97141aa81f32 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> @@ -248,17 +248,8 @@ int amdgpu_irq_init(struct amdgpu_device *adev)
> adev->irq.msi_enabled = false;
>
> if (amdgpu_msi_ok(adev)) {
> -   int nvec = pci_msix_vec_count(adev->pdev);
> -   unsigned int flags;
> -
> -   if (nvec <= 0) {
> -   flags = PCI_IRQ_MSI;
> -   } else {
> -   flags = PCI_IRQ_MSI | PCI_IRQ_MSIX;
> -   }
> /* we only need one vector */
> -   nvec = pci_alloc_irq_vectors(adev->pdev, 1, 1, flags);
> -   if (nvec > 0) {
> +   if (pci_alloc_irq_vectors(adev->pdev, 1, 1, 
> PCI_IRQ_MSI_TYPES) > 0) {
> adev->irq.msi_enabled = true;
> dev_dbg(adev->dev, "using MSI/MSI-X.\n");
> }
> --
> 2.17.2
>
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Re: [PATCH 2/3] drm/amd/powerplay: revise the calling chain on sensor reading

2020-06-09 Thread Alex Deucher 
On Tue, Jun 9, 2020 at 6:21 AM Evan Quan  wrote:
>
> Update the calling chain from "amdgpu_smu.c -> ${asic}_ppt.c ->
> smu_v11/12_0.c -> amdgpu_smu.c (smu_common_read_sensor())" to "
> "amdgpu_smu.c -> ${asic}_ppt.c -> smu_v11/12_0.c". This can help
> to maintain clear code layers. More similar changes will be coming.
>
> Change-Id: I95beba6c117b0cd3b0acea6158bf62240c6eac5a
> Signed-off-by: Evan Quan 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 81 ---
>  .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h|  2 -
>  drivers/gpu/drm/amd/powerplay/smu_v11_0.c |  2 +-
>  drivers/gpu/drm/amd/powerplay/smu_v12_0.c |  2 +-
>  4 files changed, 35 insertions(+), 52 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 
> b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> index 78263de02678..c032680c52b0 100644
> --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> @@ -506,52 +506,6 @@ int smu_get_power_num_states(struct smu_context *smu,
> return 0;
>  }
>
> -int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors 
> sensor,
> -  void *data, uint32_t *size)
> -{
> -   struct smu_power_context *smu_power = >smu_power;
> -   struct smu_power_gate *power_gate = _power->power_gate;
> -   int ret = 0;
> -
> -   if(!data || !size)
> -   return -EINVAL;
> -
> -   switch (sensor) {
> -   case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
> -   *((uint32_t *)data) = smu->pstate_sclk;
> -   *size = 4;
> -   break;
> -   case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK:
> -   *((uint32_t *)data) = smu->pstate_mclk;
> -   *size = 4;
> -   break;
> -   case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
> -   ret = smu_feature_get_enabled_mask(smu, (uint32_t *)data, 2);
> -   *size = 8;
> -   break;
> -   case AMDGPU_PP_SENSOR_UVD_POWER:
> -   *(uint32_t *)data = smu_feature_is_enabled(smu, 
> SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0;
> -   *size = 4;
> -   break;
> -   case AMDGPU_PP_SENSOR_VCE_POWER:
> -   *(uint32_t *)data = smu_feature_is_enabled(smu, 
> SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0;
> -   *size = 4;
> -   break;
> -   case AMDGPU_PP_SENSOR_VCN_POWER_STATE:
> -   *(uint32_t *)data = power_gate->vcn_gated ? 0 : 1;
> -   *size = 4;
> -   break;
> -   default:
> -   ret = -EINVAL;
> -   break;
> -   }
> -
> -   if (ret)
> -   *size = 0;
> -
> -   return ret;
> -}
> -
>  int smu_update_table(struct smu_context *smu, enum smu_table_id table_index, 
> int argument,
>  void *table_data, bool drv2smu)
>  {
> @@ -2338,10 +2292,41 @@ int smu_read_sensor(struct smu_context *smu,
> if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
> return -EOPNOTSUPP;
>
> +   if (!data || !size)
> +   return -EINVAL;
> +
> mutex_lock(>mutex);
>
> -   if (smu->ppt_funcs->read_sensor)
> -   ret = smu->ppt_funcs->read_sensor(smu, sensor, data, size);
> +   switch (sensor) {
> +   case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
> +   *((uint32_t *)data) = smu->pstate_sclk;
> +   *size = 4;
> +   break;
> +   case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK:
> +   *((uint32_t *)data) = smu->pstate_mclk;
> +   *size = 4;
> +   break;
> +   case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
> +   ret = smu_feature_get_enabled_mask(smu, (uint32_t *)data, 2);
> +   *size = 8;
> +   break;
> +   case AMDGPU_PP_SENSOR_UVD_POWER:
> +   *(uint32_t *)data = smu_feature_is_enabled(smu, 
> SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0;
> +   *size = 4;
> +   break;
> +   case AMDGPU_PP_SENSOR_VCE_POWER:
> +   *(uint32_t *)data = smu_feature_is_enabled(smu, 
> SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0;
> +   *size = 4;
> +   break;
> +   case AMDGPU_PP_SENSOR_VCN_POWER_STATE:
> +   *(uint32_t *)data = smu->smu_power.power_gate.vcn_gated ? 0 : 
> 1;
> +   *size = 4;
> +   break;
> +   default:
> +   if (smu->ppt_funcs->read_sensor)
> +   ret = smu->ppt_funcs->read_sensor(smu, sensor, data, 
> size);
> +   break;
> +   }
>
> mutex_unlock(>mutex);
>
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 
> b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> index 0d1429fc791b..41164a8fbe8a 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> @@ -695,8 +695,6 @@ int smu_update_table(struct

Re: [PATCH 3/3] drm/amd/powerplay: maximum code sharing on sensor reading

2020-06-09 Thread Alex Deucher 
On Tue, Jun 9, 2020 at 6:21 AM Evan Quan  wrote:
>
> Move the common code to amdgpu_smu.c instead of having one
> copy in both smu_v11_0.c and smu_v12_0.c.
>
> Change-Id: Idc59c6f686139d034348a613f1a7b9213198312d
> Signed-off-by: Evan Quan 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 4 
>  drivers/gpu/drm/amd/powerplay/smu_v11_0.c  | 4 
>  drivers/gpu/drm/amd/powerplay/smu_v12_0.c  | 4 
>  3 files changed, 4 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 
> b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> index c032680c52b0..8415b383e7ae 100644
> --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> @@ -2322,6 +2322,10 @@ int smu_read_sensor(struct smu_context *smu,
> *(uint32_t *)data = smu->smu_power.power_gate.vcn_gated ? 0 : 
> 1;
> *size = 4;
> break;
> +   case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
> +   *(uint32_t *)data = 0;
> +   *size = 4;
> +   break;
> default:
> if (smu->ppt_funcs->read_sensor)
> ret = smu->ppt_funcs->read_sensor(smu, sensor, data, 
> size);
> diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c 
> b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> index 1a17d853afbd..993976452467 100644
> --- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> +++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> @@ -1193,10 +1193,6 @@ int smu_v11_0_read_sensor(struct smu_context *smu,
> ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
> *size = 4;
> break;
> -   case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
> -   *(uint32_t *)data = 0;
> -   *size = 4;
> -   break;
> default:
> ret = -EOPNOTSUPP;
> break;
> diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c 
> b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
> index ae1035575808..b03127273d56 100644
> --- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
> +++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
> @@ -221,10 +221,6 @@ int smu_v12_0_read_sensor(struct smu_context *smu,
> ret = smu_get_current_clk_freq(smu, SMU_GFXCLK, (uint32_t 
> *)data);
> *size = 4;
> break;
> -   case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
> -   *(uint32_t *)data = 0;
> -   *size = 4;
> -   break;
> default:
> ret = -EOPNOTSUPP;
> break;
> --
> 2.27.0
>
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Re: [PATCH 1/3] drm/amd/powerplay: drop unnecessary SMU_MSG_GetDpmClockFreq check

2020-06-09 Thread Alex Deucher 
On Tue, Jun 9, 2020 at 6:20 AM Evan Quan  wrote:
>
> Since SMU_MSG_GetDpmClockFreq is known to be supported for Vega20
> and before ASICs only. For those ASICs supporting swSMU, it is not
> supported.
>
> Change-Id: I8ee71664baa32e40df5bb793550785120f3770c6
> Signed-off-by: Evan Quan 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 17 +++--
>  1 file changed, 3 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c 
> b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> index 9e3fee9e4aca..d10d15fc7492 100644
> --- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> +++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> @@ -1089,24 +1089,13 @@ int smu_v11_0_get_current_clk_freq(struct smu_context 
> *smu,
>  {
> int ret = 0;
> uint32_t freq = 0;
> -   int asic_clk_id;
>
> if (clk_id >= SMU_CLK_COUNT || !value)
> return -EINVAL;
>
> -   asic_clk_id = smu_clk_get_index(smu, clk_id);
> -   if (asic_clk_id < 0)
> -   return -EINVAL;
> -
> -   /* if don't has GetDpmClockFreq Message, try get current clock by 
> SmuMetrics_t */
> -   if (smu_msg_get_index(smu, SMU_MSG_GetDpmClockFreq) < 0)
> -   ret =  smu_get_current_clk_freq_by_table(smu, clk_id, );
> -   else {
> -   ret = smu_send_smc_msg_with_param(smu, 
> SMU_MSG_GetDpmClockFreq,
> - (asic_clk_id << 16), );
> -   if (ret)
> -   return ret;
> -   }
> +   ret =  smu_get_current_clk_freq_by_table(smu, clk_id, );
> +   if (ret)
> +   return ret;
>
> freq *= 100;
> *value = freq;
> --
> 2.27.0
>
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Re: [PATCH 2/2] drm/amd/powerplay: drop unnecessary wrapper .populate_smc_tables

2020-06-09 Thread Alex Deucher 
On Tue, Jun 9, 2020 at 6:10 AM Evan Quan  wrote:
>
> Since .populate_smc_tables is just a wrapper of .set_default_dpm_table.
>
> Change-Id: I80e89146359d6cf5d80f1887878d371b41b41cb0
> Signed-off-by: Evan Quan 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 2 +-
>  drivers/gpu/drm/amd/powerplay/arcturus_ppt.c   | 1 -
>  drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 1 -
>  drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h  | 2 --
>  drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h  | 2 +-
>  drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 1 -
>  drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 2 +-
>  drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c | 1 -
>  drivers/gpu/drm/amd/powerplay/smu_internal.h   | 2 --
>  drivers/gpu/drm/amd/powerplay/smu_v11_0.c  | 9 -
>  drivers/gpu/drm/amd/powerplay/smu_v12_0.c  | 2 +-
>  11 files changed, 4 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 
> b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> index 89dd12536d58..78263de02678 100644
> --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> @@ -813,7 +813,7 @@ static int smu_late_init(void *handle)
>  * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for 
> each
>  * type of clks.
>  */
> -   ret = smu_populate_smc_tables(smu);
> +   ret = smu_set_default_dpm_table(smu);
> if (ret) {
> dev_err(adev->dev, "Failed to setup default dpm clock 
> tables!\n");
> return ret;
> diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 
> b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
> index 96c9a348f8b3..ee492fc77414 100644
> --- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
> @@ -2587,7 +2587,6 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
> /* pptable related */
> .setup_pptable = arcturus_setup_pptable,
> .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
> -   .populate_smc_tables = smu_v11_0_populate_smc_pptable,
> .check_fw_version = smu_v11_0_check_fw_version,
> .write_pptable = smu_v11_0_write_pptable,
> .set_driver_table_location = smu_v11_0_set_driver_table_location,
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 
> b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> index 3420a58fad03..0d1429fc791b 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> @@ -505,7 +505,6 @@ struct pptable_funcs {
> int (*check_fw_status)(struct smu_context *smu);
> int (*setup_pptable)(struct smu_context *smu);
> int (*get_vbios_bootup_values)(struct smu_context *smu);
> -   int (*populate_smc_tables)(struct smu_context *smu);
> int (*check_fw_version)(struct smu_context *smu);
> int (*powergate_sdma)(struct smu_context *smu, bool gate);
> int (*set_gfx_cgpg)(struct smu_context *smu, bool enable);
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h 
> b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
> index 9ccf62e99dcb..d6cd3d74dcfa 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
> @@ -164,8 +164,6 @@ int smu_v11_0_setup_pptable(struct smu_context *smu);
>
>  int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu);
>
> -int smu_v11_0_populate_smc_pptable(struct smu_context *smu);
> -
>  int smu_v11_0_check_fw_version(struct smu_context *smu);
>
>  int smu_v11_0_write_pptable(struct smu_context *smu);
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h 
> b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
> index 7fbebc1979cf..d29f75223987 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
> @@ -72,7 +72,7 @@ int smu_v12_0_init_smc_tables(struct smu_context *smu);
>
>  int smu_v12_0_fini_smc_tables(struct smu_context *smu);
>
> -int smu_v12_0_populate_smc_tables(struct smu_context *smu);
> +int smu_v12_0_set_default_dpm_tables(struct smu_context *smu);
>
>  int smu_v12_0_get_enabled_mask(struct smu_context *smu,
>   uint32_t *feature_mask, uint32_t num);
> diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c 
> b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> index abbfcce6d9ad..ef04ab1eba94 100644
> --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> @@ -2423,7 +2423,6 @@ static const struct pptable_funcs navi10_ppt_funcs = {
> .check_fw_status = smu_v11_0_check_fw_status,
> .setup_pptable = navi10_setup_pptable,
> .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
> -   .populate_smc_tables = smu_v11_0_populate_smc_pptable,
>

Re: [PATCH 1/2] drm/amd/powerplay: drop redundant .set_min_dcefclk_deep_sleep API

2020-06-09 Thread Alex Deucher 
On Tue, Jun 9, 2020 at 6:10 AM Evan Quan  wrote:
>
> It has exactly the same functionality as .set_deep_sleep_dcefclk.
>
> Change-Id: Ib4d2d604ca014e194cb2b61ac770e4370ecad74d
> Signed-off-by: Evan Quan 
> ---
>  drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 11 +--
>  drivers/gpu/drm/amd/powerplay/arcturus_ppt.c   |  3 +--
>  drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h |  1 -
>  drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h  |  2 --
>  drivers/gpu/drm/amd/powerplay/navi10_ppt.c |  1 -
>  drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c |  3 +--
>  drivers/gpu/drm/amd/powerplay/smu_internal.h   |  4 ++--
>  drivers/gpu/drm/amd/powerplay/smu_v11_0.c  | 10 --
>  8 files changed, 9 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 
> b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> index 6beae3b496be..89dd12536d58 100644
> --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> @@ -1269,7 +1269,8 @@ static int smu_smc_hw_setup(struct smu_context *smu)
>  * Set min deep sleep dce fclk with bootup value from vbios via
>  * SetMinDeepSleepDcefclk MSG.
>  */
> -   ret = smu_set_min_dcef_deep_sleep(smu);
> +   ret = smu_set_min_dcef_deep_sleep(smu,
> + smu->smu_table.boot_values.dcefclk 
> / 100);
> if (ret)
> return ret;
>
> @@ -1584,9 +1585,8 @@ int smu_display_configuration_change(struct smu_context 
> *smu,
>
> mutex_lock(>mutex);
>
> -   if (smu->ppt_funcs->set_deep_sleep_dcefclk)
> -   smu->ppt_funcs->set_deep_sleep_dcefclk(smu,
> -   display_config->min_dcef_deep_sleep_set_clk / 
> 100);
> +   smu_set_min_dcef_deep_sleep(smu,
> +   
> display_config->min_dcef_deep_sleep_set_clk / 100);
>
> for (index = 0; index < 
> display_config->num_path_including_non_display; index++) {
> if (display_config->displays[index].controller_id != 0)
> @@ -2482,8 +2482,7 @@ int smu_set_deep_sleep_dcefclk(struct smu_context *smu, 
> int clk)
>
> mutex_lock(>mutex);
>
> -   if (smu->ppt_funcs->set_deep_sleep_dcefclk)
> -   ret = smu->ppt_funcs->set_deep_sleep_dcefclk(smu, clk);
> +   ret = smu_set_min_dcef_deep_sleep(smu, clk);
>
> mutex_unlock(>mutex);
>
> diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 
> b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
> index c104844b28f1..96c9a348f8b3 100644
> --- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
> @@ -2590,7 +2590,6 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
> .populate_smc_tables = smu_v11_0_populate_smc_pptable,
> .check_fw_version = smu_v11_0_check_fw_version,
> .write_pptable = smu_v11_0_write_pptable,
> -   .set_min_dcef_deep_sleep = NULL,
> .set_driver_table_location = smu_v11_0_set_driver_table_location,
> .set_tool_table_location = smu_v11_0_set_tool_table_location,
> .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
> @@ -2605,7 +2604,7 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
> .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
> .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
> .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
> -   .set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
> +   .set_deep_sleep_dcefclk = NULL,
> .display_clock_voltage_request = 
> smu_v11_0_display_clock_voltage_request,
> .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
> .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 
> b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> index 8eaa6338ad44..3420a58fad03 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> @@ -510,7 +510,6 @@ struct pptable_funcs {
> int (*powergate_sdma)(struct smu_context *smu, bool gate);
> int (*set_gfx_cgpg)(struct smu_context *smu, bool enable);
> int (*write_pptable)(struct smu_context *smu);
> -   int (*set_min_dcef_deep_sleep)(struct smu_context *smu);
> int (*set_driver_table_location)(struct smu_context *smu);
> int (*set_tool_table_location)(struct smu_context *smu);
> int (*notify_memory_pool_location)(struct smu_context *smu);
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h 
> b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
> index 2e9939beb128..9ccf62e99dcb 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
> @@ -170,8 +170,6 @@ int smu_v11_0_check_fw_version(struct smu_context *smu);
>
>  int

Re: [PATCH] drm/amd/amdgpu: Add SQ debug registers to GFX10 headers

2020-06-09 Thread Deucher, Alexander 
[AMD Official Use Only - Internal Distribution Only]

Might as well add it for gfx9 as well.  With that fixed:
Reviewed-by: Alex Deucher 

From: amd-gfx  on behalf of Tom St Denis 

Sent: Tuesday, June 9, 2020 1:59 PM
To: amd-gfx@lists.freedesktop.org 
Cc: StDenis, Tom 
Subject: [PATCH] drm/amd/amdgpu: Add SQ debug registers to GFX10 headers

Requested for UMR support.

Signed-off-by: Tom St Denis 
---
 .../include/asic_reg/gc/gc_10_1_0_offset.h|  1 +
 .../include/asic_reg/gc/gc_10_1_0_sh_mask.h   | 20 +++
 .../include/asic_reg/gc/gc_10_3_0_offset.h|  1 +
 .../include/asic_reg/gc/gc_10_3_0_sh_mask.h   | 19 ++
 4 files changed, 41 insertions(+)

diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h 
b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
index 075867d4b1da..791dc2b3d74a 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
@@ -11151,6 +11151,7 @@

 // addressBlock: sqind
 // base address: 0x0
+#define ixSQ_DEBUG_STS_LOCAL   
0x0008
 #define ixSQ_WAVE_MODE 
0x0101
 #define ixSQ_WAVE_STATUS   
0x0102
 #define ixSQ_WAVE_TRAPSTS  
0x0103
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h 
b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h
index 8b0b9a2a8fed..355e61bed291 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h
@@ -42546,6 +42546,26 @@


 // addressBlock: sqind
+//SQ_DEBUG_STS_LOCAL
+#define SQ_DEBUG_STS_LOCAL__BUSY_MASK  
   0x0001L
+#define SQ_DEBUG_STS_LOCAL__BUSY__SHIFT
   0x
+#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL_MASK
   0x03f0L
+#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL__SHIFT  
   0x0004
+#define SQ_DEBUG_STS_LOCAL__SQ_BUSY_MASK   
   0x1000L
+#define SQ_DEBUG_STS_LOCAL__SQ_BUSY__SHIFT 
   0x000C
+#define SQ_DEBUG_STS_LOCAL__IS_BUSY_MASK   
   0x2000L
+#define SQ_DEBUG_STS_LOCAL__IS_BUSY__SHIFT 
   0x000D
+#define SQ_DEBUG_STS_LOCAL__IB_BUSY_MASK   
   0x4000L
+#define SQ_DEBUG_STS_LOCAL__IB_BUSY__SHIFT 
   0x000E
+#define SQ_DEBUG_STS_LOCAL__ARB_BUSY_MASK  
   0x8000L
+#define SQ_DEBUG_STS_LOCAL__ARB_BUSY__SHIFT
   0x000F
+#define SQ_DEBUG_STS_LOCAL__EXP_BUSY_MASK  
   0x0001L
+#define SQ_DEBUG_STS_LOCAL__EXP_BUSY__SHIFT
   0x0010
+#define SQ_DEBUG_STS_LOCAL__BRMSG_BUSY_MASK
   0x0002L
+#define SQ_DEBUG_STS_LOCAL__BRMSG_BUSY__SHIFT  
   0x0011
+#define SQ_DEBUG_STS_LOCAL__VM_BUSY_MASK   
   0x0004L
+#define SQ_DEBUG_STS_LOCAL__VM_BUSY__SHIFT 
   0x0018
+
 //SQ_WAVE_MODE
 #define SQ_WAVE_MODE__FP_ROUND__SHIFT  
   0x0
 #define SQ_WAVE_MODE__FP_DENORM__SHIFT 
   0x4
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h 
b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
index 71c787d66132..a9a66371b75e 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
@@ -13277,6 +13277,7 @@

 // addressBlock: sqind
 // base address: 0x0
+#define ixSQ_DEBUG_STS_LOCAL   
0x0008
 #define ixSQ_WAVE_ACTIVE

[PATCH] drm/amd/amdgpu: Add SQ debug registers to GFX10 headers

2020-06-09 Thread Tom St Denis 
Requested for UMR support.

Signed-off-by: Tom St Denis 
---
 .../include/asic_reg/gc/gc_10_1_0_offset.h|  1 +
 .../include/asic_reg/gc/gc_10_1_0_sh_mask.h   | 20 +++
 .../include/asic_reg/gc/gc_10_3_0_offset.h|  1 +
 .../include/asic_reg/gc/gc_10_3_0_sh_mask.h   | 19 ++
 4 files changed, 41 insertions(+)

diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h 
b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
index 075867d4b1da..791dc2b3d74a 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
@@ -11151,6 +11151,7 @@
 
 // addressBlock: sqind
 // base address: 0x0
+#define ixSQ_DEBUG_STS_LOCAL   
0x0008
 #define ixSQ_WAVE_MODE 
0x0101
 #define ixSQ_WAVE_STATUS   
0x0102
 #define ixSQ_WAVE_TRAPSTS  
0x0103
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h 
b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h
index 8b0b9a2a8fed..355e61bed291 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h
@@ -42546,6 +42546,26 @@
 
 
 // addressBlock: sqind
+//SQ_DEBUG_STS_LOCAL
+#define SQ_DEBUG_STS_LOCAL__BUSY_MASK  
   0x0001L
+#define SQ_DEBUG_STS_LOCAL__BUSY__SHIFT
   0x
+#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL_MASK
   0x03f0L
+#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL__SHIFT  
   0x0004
+#define SQ_DEBUG_STS_LOCAL__SQ_BUSY_MASK   
   0x1000L
+#define SQ_DEBUG_STS_LOCAL__SQ_BUSY__SHIFT 
   0x000C
+#define SQ_DEBUG_STS_LOCAL__IS_BUSY_MASK   
   0x2000L
+#define SQ_DEBUG_STS_LOCAL__IS_BUSY__SHIFT 
   0x000D
+#define SQ_DEBUG_STS_LOCAL__IB_BUSY_MASK   
   0x4000L
+#define SQ_DEBUG_STS_LOCAL__IB_BUSY__SHIFT 
   0x000E
+#define SQ_DEBUG_STS_LOCAL__ARB_BUSY_MASK  
   0x8000L
+#define SQ_DEBUG_STS_LOCAL__ARB_BUSY__SHIFT
   0x000F
+#define SQ_DEBUG_STS_LOCAL__EXP_BUSY_MASK  
   0x0001L
+#define SQ_DEBUG_STS_LOCAL__EXP_BUSY__SHIFT
   0x0010
+#define SQ_DEBUG_STS_LOCAL__BRMSG_BUSY_MASK
   0x0002L
+#define SQ_DEBUG_STS_LOCAL__BRMSG_BUSY__SHIFT  
   0x0011
+#define SQ_DEBUG_STS_LOCAL__VM_BUSY_MASK   
   0x0004L
+#define SQ_DEBUG_STS_LOCAL__VM_BUSY__SHIFT 
   0x0018
+
 //SQ_WAVE_MODE
 #define SQ_WAVE_MODE__FP_ROUND__SHIFT  
   0x0
 #define SQ_WAVE_MODE__FP_DENORM__SHIFT 
   0x4
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h 
b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
index 71c787d66132..a9a66371b75e 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
@@ -13277,6 +13277,7 @@
 
 // addressBlock: sqind
 // base address: 0x0
+#define ixSQ_DEBUG_STS_LOCAL   
0x0008
 #define ixSQ_WAVE_ACTIVE   
0x000a
 #define ixSQ_WAVE_VALID_AND_IDLE   
0x000b
 #define ixSQ_WAVE_MODE 
0x0101
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h 
b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h
index

Re: [PATCH 1/6] drm/ttm: Add unampping of the entire device address space

2020-06-09 Thread Koenig, Christian 


Am 09.06.2020 18:37 schrieb "Grodzovsky, Andrey" :

On 6/5/20 2:40 PM, Christian König wrote:
> Am 05.06.20 um 16:29 schrieb Andrey Grodzovsky:
>>
>> On 5/11/20 2:45 AM, Christian König wrote:
>>> Am 09.05.20 um 20:51 schrieb Andrey Grodzovsky:
 Signed-off-by: Andrey Grodzovsky 
 ---
   drivers/gpu/drm/ttm/ttm_bo.c| 22 +-
   include/drm/ttm/ttm_bo_driver.h |  2 ++
   2 files changed, 23 insertions(+), 1 deletion(-)

 diff --git a/drivers/gpu/drm/ttm/ttm_bo.c
 b/drivers/gpu/drm/ttm/ttm_bo.c
 index c5b516f..eae61cc 100644
 --- a/drivers/gpu/drm/ttm/ttm_bo.c
 +++ b/drivers/gpu/drm/ttm/ttm_bo.c
 @@ -1750,9 +1750,29 @@ void ttm_bo_unmap_virtual(struct
 ttm_buffer_object *bo)
   ttm_bo_unmap_virtual_locked(bo);
   ttm_mem_io_unlock(man);
   }
 +EXPORT_SYMBOL(ttm_bo_unmap_virtual);
   +void ttm_bo_unmap_virtual_address_space(struct ttm_bo_device *bdev)
 +{
 +struct ttm_mem_type_manager *man;
 +int i;
   -EXPORT_SYMBOL(ttm_bo_unmap_virtual);
>>>
 +for (i = 0; i < TTM_NUM_MEM_TYPES; i++) {
 +man = >man[i];
 +if (man->has_type && man->use_type)
 +ttm_mem_io_lock(man, false);
 +}
>>>
>>> You should drop that it will just result in a deadlock warning for
>>> Nouveau and has no effect at all.
>>>
>>> Apart from that looks good to me,
>>> Christian.
>>
>>
>> As I am considering to re-include this in V2 of the patchsets, can
>> you clarify please why this will have no effect at all ?
>
> The locks are exclusive for Nouveau to allocate/free the io address
> space.
>
> Since we don't do this here we don't need the locks.
>
> Christian.


So basically calling unmap_mapping_range doesn't require any extra
locking around it and whatever locks are taken within the function
should be enough ?


I think so, yes.

Christian.


Andrey


>
>>
>> Andrey
>>
>>
>>>
 +
 +unmap_mapping_range(bdev->dev_mapping, 0, 0 , 1);
 +/*TODO What about ttm_mem_io_free_vm(bo) ? */
 +
 +for (i = TTM_NUM_MEM_TYPES - 1; i >= 0; i--) {
 +man = >man[i];
 +if (man->has_type && man->use_type)
 +ttm_mem_io_unlock(man);
 +}
 +}
 +EXPORT_SYMBOL(ttm_bo_unmap_virtual_address_space);
 int ttm_bo_wait(struct ttm_buffer_object *bo,
   bool interruptible, bool no_wait)
 diff --git a/include/drm/ttm/ttm_bo_driver.h
 b/include/drm/ttm/ttm_bo_driver.h
 index c9e0fd0..3133463 100644
 --- a/include/drm/ttm/ttm_bo_driver.h
 +++ b/include/drm/ttm/ttm_bo_driver.h
 @@ -600,6 +600,8 @@ int ttm_bo_device_init(struct ttm_bo_device *bdev,
*/
   void ttm_bo_unmap_virtual(struct ttm_buffer_object *bo);
   +void ttm_bo_unmap_virtual_address_space(struct ttm_bo_device
 *bdev);
 +
   /**
* ttm_bo_unmap_virtual
*
>>>
>

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Re: close() on some Intel CNP-LP PCI devices takes up to 2.7 s

2020-06-09 Thread Mika Westerberg 
On Tue, Jun 09, 2020 at 05:39:21PM +0200, Paul Menzel wrote:
> Dear Linux folks,
> 
> 
> On the Intel Cannon Point-LP laptop Dell Precision 3540 with a dedicated AMD
> graphics card (both graphics devices can be used) with Debian Sid/unstable
> with Linux 5.6.14, running lspci takes quite some time, and the screen even
> flickers a short moment before the result is displayed.
> 
> Tracing lspci with strace, shows that the close() function of the three
> devices takes from
> 
> •   00:1d.0 PCI bridge: Intel Corporation Cannon Point-LP PCI Express Root
> Port #9
> 
> •   04:00.0 System peripheral: Intel Corporation JHL6340 Thunderbolt 3 NHI
> (C step) [Alpine Ridge 2C 2016] (rev 02)
> 
> •   3b:00.0 Display controller: Advanced Micro Devices, Inc. [AMD/ATI] Lexa
> XT [Radeon PRO WX 3100]
> 
> takes from 270 ms to 2.5 s.
> 
> > 11:43:21.714391 openat(AT_FDCWD, 
> > "/sys/bus/pci/devices/:04:00.0/config", O_RDONLY) = 3
> > 11:43:21.714448 pread64(3, "\206\200\331\25\6\4\20\0\2\0\200\10 
> > \0\0\0\0\0\0\352\0\0\4\352\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0(\20\272\10\0\0\0\0\
> > 200\0\0\0\0\0\0\0\377\1\0\0", 64, 0) = 64
> > 11:43:24.487818 close(3)= 0
> 
> > 11:43:24.489508 openat(AT_FDCWD, 
> > "/sys/bus/pci/devices/:00:1d.0/config", O_RDONLY) = 3
> > 11:43:24.489598 pread64(3, 
> > "\206\200\260\235\7\4\20\0\360\0\4\6\20\0\201\0\0\0\0\0\0\0\0\0\0;;\0\0 
> >  \354 \354\1\300\21\320\0\0\0\0\0\0\0\0\0\0\0\0
> > @\0\0\0\0\0\0\0\377\1\22\0", 64, 0) = 64
> > 11:43:24.91 close(3)= 0
> 
> > 11:43:24.988544 openat(AT_FDCWD, 
> > "/sys/bus/pci/devices/:3b:00.0/config", O_RDONLY) = 3
> > 11:43:24.988584 pread64(3, 
> > "\2\20\205i\7\4\20\0\0\0\200\3\20\0\0\0\f\0\0\300\0\0\0\0\f\0\0\320\0\0\0\0\0010\0\0\0\0
> >  \354\0\0\0\0(\20\272\10\0\0$\354H\0\0\0\0\0\0\0\377\1\0\0", 64, 0) = 64
> > 11:43:25.252745 close(3)
> 
> Unfortunately, I forgot to collect the tree output, but hopefully the
> attached Linux messages and strace of lspci output will be enough for the
> start.
> 
> Please tell me, if you want me to create a bug report in the Linux bug
> tracker.

Can you try this commit?

  
https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git/commit/?h=pci/pm=ec411e02b7a2e785a4ed9ed283207cd14f48699d

It should be in the mainline already as well.

Note we still need to obey the delays required by the PCIe spec so 100ms
after the link is trained but this one should at least get it down from
1100ms.
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Re: [PATCH 1/6] drm/ttm: Add unampping of the entire device address space

2020-06-09 Thread Andrey Grodzovsky 


On 6/5/20 2:40 PM, Christian König wrote:

Am 05.06.20 um 16:29 schrieb Andrey Grodzovsky:


On 5/11/20 2:45 AM, Christian König wrote:

Am 09.05.20 um 20:51 schrieb Andrey Grodzovsky:

Signed-off-by: Andrey Grodzovsky 
---
  drivers/gpu/drm/ttm/ttm_bo.c    | 22 +-
  include/drm/ttm/ttm_bo_driver.h |  2 ++
  2 files changed, 23 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/ttm/ttm_bo.c 
b/drivers/gpu/drm/ttm/ttm_bo.c

index c5b516f..eae61cc 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -1750,9 +1750,29 @@ void ttm_bo_unmap_virtual(struct 
ttm_buffer_object *bo)

  ttm_bo_unmap_virtual_locked(bo);
  ttm_mem_io_unlock(man);
  }
+EXPORT_SYMBOL(ttm_bo_unmap_virtual);
  +void ttm_bo_unmap_virtual_address_space(struct ttm_bo_device *bdev)
+{
+    struct ttm_mem_type_manager *man;
+    int i;
  -EXPORT_SYMBOL(ttm_bo_unmap_virtual);



+    for (i = 0; i < TTM_NUM_MEM_TYPES; i++) {
+    man = >man[i];
+    if (man->has_type && man->use_type)
+    ttm_mem_io_lock(man, false);
+    }


You should drop that it will just result in a deadlock warning for 
Nouveau and has no effect at all.


Apart from that looks good to me,
Christian.



As I am considering to re-include this in V2 of the patchsets, can 
you clarify please why this will have no effect at all ?


The locks are exclusive for Nouveau to allocate/free the io address 
space.


Since we don't do this here we don't need the locks.

Christian.



So basically calling unmap_mapping_range doesn't require any extra 
locking around it and whatever locks are taken within the function 
should be enough ?


Andrey






Andrey





+
+    unmap_mapping_range(bdev->dev_mapping, 0, 0 , 1);
+    /*TODO What about ttm_mem_io_free_vm(bo) ? */
+
+    for (i = TTM_NUM_MEM_TYPES - 1; i >= 0; i--) {
+    man = >man[i];
+    if (man->has_type && man->use_type)
+    ttm_mem_io_unlock(man);
+    }
+}
+EXPORT_SYMBOL(ttm_bo_unmap_virtual_address_space);
    int ttm_bo_wait(struct ttm_buffer_object *bo,
  bool interruptible, bool no_wait)
diff --git a/include/drm/ttm/ttm_bo_driver.h 
b/include/drm/ttm/ttm_bo_driver.h

index c9e0fd0..3133463 100644
--- a/include/drm/ttm/ttm_bo_driver.h
+++ b/include/drm/ttm/ttm_bo_driver.h
@@ -600,6 +600,8 @@ int ttm_bo_device_init(struct ttm_bo_device *bdev,
   */
  void ttm_bo_unmap_virtual(struct ttm_buffer_object *bo);
  +void ttm_bo_unmap_virtual_address_space(struct ttm_bo_device 
*bdev);

+
  /**
   * ttm_bo_unmap_virtual
   *





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[PATCH v3 07/15] drm/amdgpu: Use PCI_IRQ_MSI_TYPES where appropriate

2020-06-09 Thread Piotr Stankiewicz 
Seeing as there is shorthand available to use when asking for any type
of interrupt, or any type of message signalled interrupt, leverage it.

Signed-off-by: Piotr Stankiewicz 
Reviewed-by: Andy Shevchenko 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 11 +--
 1 file changed, 1 insertion(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
index 0cc4c67f95f7..97141aa81f32 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
@@ -248,17 +248,8 @@ int amdgpu_irq_init(struct amdgpu_device *adev)
adev->irq.msi_enabled = false;
 
if (amdgpu_msi_ok(adev)) {
-   int nvec = pci_msix_vec_count(adev->pdev);
-   unsigned int flags;
-
-   if (nvec <= 0) {
-   flags = PCI_IRQ_MSI;
-   } else {
-   flags = PCI_IRQ_MSI | PCI_IRQ_MSIX;
-   }
/* we only need one vector */
-   nvec = pci_alloc_irq_vectors(adev->pdev, 1, 1, flags);
-   if (nvec > 0) {
+   if (pci_alloc_irq_vectors(adev->pdev, 1, 1, PCI_IRQ_MSI_TYPES) 
> 0) {
adev->irq.msi_enabled = true;
dev_dbg(adev->dev, "using MSI/MSI-X.\n");
}
-- 
2.17.2

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[PATCH v3 00/15] Forward MSI-X vector enable error code in pci_alloc_irq_vectors_affinity()

2020-06-09 Thread Piotr Stankiewicz 
The primary objective of this patch series is to change the behaviour
of pci_alloc_irq_vectors_affinity() such that it forwards the MSI-X enable
error code when appropriate. In the process, though, it was pointed out
that there are multiple places in the kernel which check/ask for message
signalled interrupts (MSI or MSI-X), which spawned the first patch adding
PCI_IRQ_MSI_TYPES. Finally the rest of the chain converts all users to
take advantage of PCI_IRQ_MSI_TYPES or PCI_IRQ_ALL_TYPES, as
appropriate.

Piotr Stankiewicz (15):
  PCI/MSI: Forward MSI-X vector enable error code in
pci_alloc_irq_vectors_affinity()
  PCI: Add macro for message signalled interrupt types
  PCI: Use PCI_IRQ_MSI_TYPES where appropriate
  ahci: Use PCI_IRQ_MSI_TYPES where appropriate
  crypto: inside-secure - Use PCI_IRQ_MSI_TYPES where appropriate
  dmaengine: dw-edma: Use PCI_IRQ_MSI_TYPES  where appropriate
  drm/amdgpu: Use PCI_IRQ_MSI_TYPES where appropriate
  IB/qib: Use PCI_IRQ_MSI_TYPES where appropriate
  media: ddbridge: Use PCI_IRQ_MSI_TYPES where appropriate
  vmw_vmci: Use PCI_IRQ_ALL_TYPES where appropriate
  mmc: sdhci: Use PCI_IRQ_MSI_TYPES where appropriate
  amd-xgbe: Use PCI_IRQ_MSI_TYPES where appropriate
  aquantia: atlantic: Use PCI_IRQ_ALL_TYPES where appropriate
  net: hns3: Use PCI_IRQ_MSI_TYPES where appropriate
  scsi: Use PCI_IRQ_MSI_TYPES and PCI_IRQ_ALL_TYPES where appropriate

 Documentation/PCI/msi-howto.rst   |  5 +++--
 drivers/ata/ahci.c|  2 +-
 drivers/crypto/inside-secure/safexcel.c   |  2 +-
 drivers/dma/dw-edma/dw-edma-pcie.c|  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c   | 11 +-
 drivers/infiniband/hw/qib/qib_pcie.c  |  6 +++--
 drivers/media/pci/ddbridge/ddbridge-main.c|  2 +-
 drivers/misc/vmw_vmci/vmci_guest.c|  3 +--
 drivers/mmc/host/sdhci-pci-gli.c  |  3 +--
 drivers/mmc/host/sdhci-pci-o2micro.c  |  3 +--
 drivers/net/ethernet/amd/xgbe/xgbe-pci.c  |  2 +-
 .../ethernet/aquantia/atlantic/aq_pci_func.c  |  4 +---
 .../hisilicon/hns3/hns3pf/hclge_main.c|  3 +--
 .../hisilicon/hns3/hns3vf/hclgevf_main.c  |  3 +--
 drivers/pci/msi.c | 22 ---
 drivers/pci/pcie/portdrv_core.c   |  4 ++--
 drivers/pci/switch/switchtec.c|  3 +--
 drivers/scsi/ipr.c|  5 +++--
 drivers/scsi/vmw_pvscsi.c |  2 +-
 include/linux/pci.h   |  4 ++--
 20 files changed, 37 insertions(+), 54 deletions(-)

-- 
2.17.2

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[PATCH v3 02/15] PCI: Add macro for message signalled interrupt types

2020-06-09 Thread Piotr Stankiewicz 
There are several places in the kernel which check/ask for MSI or MSI-X
interrupts. It would make sense to have a macro which defines all types
of message signalled interrupts, to use in such situations. Add
PCI_IRQ_MSI_TYPES, for this purpose.

Signed-off-by: Piotr Stankiewicz 
Suggested-by: Andy Shevchenko 
Reviewed-by: Andy Shevchenko 
Reviewed-by: Logan Gunthorpe 
---
 Documentation/PCI/msi-howto.rst | 5 +++--
 include/linux/pci.h | 4 ++--
 2 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/Documentation/PCI/msi-howto.rst b/Documentation/PCI/msi-howto.rst
index aa2046af69f7..2800ff5aa395 100644
--- a/Documentation/PCI/msi-howto.rst
+++ b/Documentation/PCI/msi-howto.rst
@@ -105,7 +105,8 @@ if it can't meet the minimum number of vectors.
 The flags argument is used to specify which type of interrupt can be used
 by the device and the driver (PCI_IRQ_LEGACY, PCI_IRQ_MSI, PCI_IRQ_MSIX).
 A convenient short-hand (PCI_IRQ_ALL_TYPES) is also available to ask for
-any possible kind of interrupt.  If the PCI_IRQ_AFFINITY flag is set,
+any possible kind of interrupt, and (PCI_IRQ_MSI_TYPES) to ask for message
+signalled interrupts (MSI or MSI-X).  If the PCI_IRQ_AFFINITY flag is set,
 pci_alloc_irq_vectors() will spread the interrupts around the available CPUs.
 
 To get the Linux IRQ numbers passed to request_irq() and free_irq() and the
@@ -160,7 +161,7 @@ the single MSI mode for a device.  It could be done by 
passing two 1s as
 Some devices might not support using legacy line interrupts, in which case
 the driver can specify that only MSI or MSI-X is acceptable::
 
-   nvec = pci_alloc_irq_vectors(pdev, 1, nvec, PCI_IRQ_MSI | PCI_IRQ_MSIX);
+   nvec = pci_alloc_irq_vectors(pdev, 1, nvec, PCI_IRQ_MSI_TYPES);
if (nvec < 0)
goto out_err;
 
diff --git a/include/linux/pci.h b/include/linux/pci.h
index c79d83304e52..a99094f17b21 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -1431,8 +1431,8 @@ int pci_set_vga_state(struct pci_dev *pdev, bool decode,
  */
 #define PCI_IRQ_VIRTUAL(1 << 4)
 
-#define PCI_IRQ_ALL_TYPES \
-   (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
+#define PCI_IRQ_MSI_TYPES  (PCI_IRQ_MSI | PCI_IRQ_MSIX)
+#define PCI_IRQ_ALL_TYPES  (PCI_IRQ_LEGACY | PCI_IRQ_MSI_TYPES)
 
 /* kmem_cache style wrapper around pci_alloc_consistent() */
 
-- 
2.17.2

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RE: [PATCH] drm/amd/amdgpu: handle return value of amdgpu_driver_load_kms

2020-06-09 Thread Chauhan, Madhav 
-Original Message-
From: amd-gfx  On Behalf Of Liu ChengZhe
Sent: Tuesday, June 9, 2020 2:50 PM
To: amd-gfx@lists.freedesktop.org
Cc: Liu, Cheng Zhe 
Subject: [PATCH] drm/amd/amdgpu: handle return value of amdgpu_driver_load_kms

[CAUTION: External Email]

if guest driver failed to enter full GPU access, amdgpu_driver_load_kms will 
unload kms and free dev->dev_private, drm_dev_register would access null 
pointer. Driver will enter an error state and can't be unloaded.

Signed-off-by: Liu ChengZhe 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 667aad1f15c0..9c81a3d0b546 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -1165,7 +1165,9 @@ static int amdgpu_pci_probe(struct pci_dev *pdev,

pci_set_drvdata(pdev, dev);

-   amdgpu_driver_load_kms(dev, ent->driver_data);
+   ret = amdgpu_driver_load_kms(dev, ent->driver_data);
+   if (ret)
+   goto err_pci;

Looks good to me. Reviewed-by: Madhav Chauhan 

 retry_init:
ret = drm_dev_register(dev, ent->driver_data);
--
2.25.1

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[PATCH] drm/amdgpu: remove distinction between explicit and implicit sync (v2)

2020-06-09 Thread Marek Olšák 
Hi,

This enables a full pipeline sync for implicit sync. It's Christian's patch
with the driver version bumped. With this, user mode drivers don't have to
wait for idle at the end of gfx IBs.

Any concerns?

Thanks,
Marek
From 2216e2db0994f1fdeb74353bd669f8981280188e Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Christian=20K=C3=B6nig?= 
Date: Wed, 27 May 2020 10:31:08 +0200
Subject: [PATCH] drm/amdgpu: remove distinction between explicit and implicit
 sync (v2)
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

According to Marek a pipeline sync should be inserted for implicit syncs well.

v2: bump the driver version

Signed-off-by: Christian König 
Tested-by: Marek Olšák 
Signed-off-by: Marek Olšák 
---
 .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c  |  8 ++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c|  4 +--
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c   |  3 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c|  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c   | 12 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_job.c   | 15 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c  | 31 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h  |  6 ++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c   |  2 +-
 9 files changed, 33 insertions(+), 50 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index 68e6e1bc8f3a..c408936e8f98 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -395,7 +395,7 @@ static int vm_update_pds(struct amdgpu_vm *vm, struct amdgpu_sync *sync)
 	if (ret)
 		return ret;
 
-	return amdgpu_sync_fence(sync, vm->last_update, false);
+	return amdgpu_sync_fence(sync, vm->last_update);
 }
 
 static uint64_t get_pte_flags(struct amdgpu_device *adev, struct kgd_mem *mem)
@@ -785,7 +785,7 @@ static int unmap_bo_from_gpuvm(struct amdgpu_device *adev,
 
 	amdgpu_vm_clear_freed(adev, vm, _va->last_pt_update);
 
-	amdgpu_sync_fence(sync, bo_va->last_pt_update, false);
+	amdgpu_sync_fence(sync, bo_va->last_pt_update);
 
 	return 0;
 }
@@ -804,7 +804,7 @@ static int update_gpuvm_pte(struct amdgpu_device *adev,
 		return ret;
 	}
 
-	return amdgpu_sync_fence(sync, bo_va->last_pt_update, false);
+	return amdgpu_sync_fence(sync, bo_va->last_pt_update);
 }
 
 static int map_bo_to_gpuvm(struct amdgpu_device *adev,
@@ -2102,7 +2102,7 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence **ef)
 			pr_debug("Memory eviction: Validate BOs failed. Try again\n");
 			goto validate_map_fail;
 		}
-		ret = amdgpu_sync_fence(_obj, bo->tbo.moving, false);
+		ret = amdgpu_sync_fence(_obj, bo->tbo.moving);
 		if (ret) {
 			pr_debug("Memory eviction: Sync BO fence failed. Try again\n");
 			goto validate_map_fail;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 19070226a945..ffbcaf4bfb8b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -992,7 +992,7 @@ static int amdgpu_cs_process_fence_dep(struct amdgpu_cs_parser *p,
 			dma_fence_put(old);
 		}
 
-		r = amdgpu_sync_fence(>job->sync, fence, true);
+		r = amdgpu_sync_fence(>job->sync, fence);
 		dma_fence_put(fence);
 		if (r)
 			return r;
@@ -1014,7 +1014,7 @@ static int amdgpu_syncobj_lookup_and_add_to_sync(struct amdgpu_cs_parser *p,
 		return r;
 	}
 
-	r = amdgpu_sync_fence(>job->sync, fence, true);
+	r = amdgpu_sync_fence(>job->sync, fence);
 	dma_fence_put(fence);
 
 	return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 499ddb0c75d2..a4576a81794a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -87,9 +87,10 @@
  * - 3.36.0 - Allow reading more status registers on si/cik
  * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness
  * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC
+ * - 3.39.0 - DMABUF implicit sync does a full pipeline sync
  */
 #define KMS_DRIVER_MAJOR	3
-#define KMS_DRIVER_MINOR	38
+#define KMS_DRIVER_MINOR	39
 #define KMS_DRIVER_PATCHLEVEL	0
 
 int amdgpu_vram_limit = 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index b91853fd66d3..4ffc32b78745 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -178,7 +178,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
 
 	need_ctx_switch = ring->current_ctx != fence_ctx;
 	if (ring->funcs->emit_pipeline_sync && job &&
-	((tmp = amdgpu_sync_get_fence(>sched_sync, NULL)) ||
+	((tmp = amdgpu_sync_get_fence(>sched_sync)) ||
 	 (amdgpu_sriov_vf(adev) && need_ctx_switch) ||
 	 amdgpu_vm_need_pipeline_sync(ring, job))) {
 		need_pipe_sync = true;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c

[PATCH 2/3] drm/amd/powerplay: revise the calling chain on sensor reading

2020-06-09 Thread Evan Quan 
Update the calling chain from "amdgpu_smu.c -> ${asic}_ppt.c ->
smu_v11/12_0.c -> amdgpu_smu.c (smu_common_read_sensor())" to "
"amdgpu_smu.c -> ${asic}_ppt.c -> smu_v11/12_0.c". This can help
to maintain clear code layers. More similar changes will be coming.

Change-Id: I95beba6c117b0cd3b0acea6158bf62240c6eac5a
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 81 ---
 .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h|  2 -
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c |  2 +-
 drivers/gpu/drm/amd/powerplay/smu_v12_0.c |  2 +-
 4 files changed, 35 insertions(+), 52 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 78263de02678..c032680c52b0 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -506,52 +506,6 @@ int smu_get_power_num_states(struct smu_context *smu,
return 0;
 }
 
-int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor,
-  void *data, uint32_t *size)
-{
-   struct smu_power_context *smu_power = >smu_power;
-   struct smu_power_gate *power_gate = _power->power_gate;
-   int ret = 0;
-
-   if(!data || !size)
-   return -EINVAL;
-
-   switch (sensor) {
-   case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
-   *((uint32_t *)data) = smu->pstate_sclk;
-   *size = 4;
-   break;
-   case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK:
-   *((uint32_t *)data) = smu->pstate_mclk;
-   *size = 4;
-   break;
-   case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
-   ret = smu_feature_get_enabled_mask(smu, (uint32_t *)data, 2);
-   *size = 8;
-   break;
-   case AMDGPU_PP_SENSOR_UVD_POWER:
-   *(uint32_t *)data = smu_feature_is_enabled(smu, 
SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0;
-   *size = 4;
-   break;
-   case AMDGPU_PP_SENSOR_VCE_POWER:
-   *(uint32_t *)data = smu_feature_is_enabled(smu, 
SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0;
-   *size = 4;
-   break;
-   case AMDGPU_PP_SENSOR_VCN_POWER_STATE:
-   *(uint32_t *)data = power_gate->vcn_gated ? 0 : 1;
-   *size = 4;
-   break;
-   default:
-   ret = -EINVAL;
-   break;
-   }
-
-   if (ret)
-   *size = 0;
-
-   return ret;
-}
-
 int smu_update_table(struct smu_context *smu, enum smu_table_id table_index, 
int argument,
 void *table_data, bool drv2smu)
 {
@@ -2338,10 +2292,41 @@ int smu_read_sensor(struct smu_context *smu,
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
return -EOPNOTSUPP;
 
+   if (!data || !size)
+   return -EINVAL;
+
mutex_lock(>mutex);
 
-   if (smu->ppt_funcs->read_sensor)
-   ret = smu->ppt_funcs->read_sensor(smu, sensor, data, size);
+   switch (sensor) {
+   case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
+   *((uint32_t *)data) = smu->pstate_sclk;
+   *size = 4;
+   break;
+   case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK:
+   *((uint32_t *)data) = smu->pstate_mclk;
+   *size = 4;
+   break;
+   case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
+   ret = smu_feature_get_enabled_mask(smu, (uint32_t *)data, 2);
+   *size = 8;
+   break;
+   case AMDGPU_PP_SENSOR_UVD_POWER:
+   *(uint32_t *)data = smu_feature_is_enabled(smu, 
SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0;
+   *size = 4;
+   break;
+   case AMDGPU_PP_SENSOR_VCE_POWER:
+   *(uint32_t *)data = smu_feature_is_enabled(smu, 
SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0;
+   *size = 4;
+   break;
+   case AMDGPU_PP_SENSOR_VCN_POWER_STATE:
+   *(uint32_t *)data = smu->smu_power.power_gate.vcn_gated ? 0 : 1;
+   *size = 4;
+   break;
+   default:
+   if (smu->ppt_funcs->read_sensor)
+   ret = smu->ppt_funcs->read_sensor(smu, sensor, data, 
size);
+   break;
+   }
 
mutex_unlock(>mutex);
 
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 0d1429fc791b..41164a8fbe8a 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -695,8 +695,6 @@ int smu_update_table(struct smu_context *smu, enum 
smu_table_id table_index, int
 
 bool is_support_sw_smu(struct amdgpu_device *adev);
 int smu_reset(struct smu_context *smu);
-int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor,
-  void *data, uint32_t *size);
 int smu_sys_get_pp_table(struct smu_context

[PATCH 3/3] drm/amd/powerplay: maximum code sharing on sensor reading

2020-06-09 Thread Evan Quan 
Move the common code to amdgpu_smu.c instead of having one
copy in both smu_v11_0.c and smu_v12_0.c.

Change-Id: Idc59c6f686139d034348a613f1a7b9213198312d
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 4 
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c  | 4 
 drivers/gpu/drm/amd/powerplay/smu_v12_0.c  | 4 
 3 files changed, 4 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index c032680c52b0..8415b383e7ae 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -2322,6 +2322,10 @@ int smu_read_sensor(struct smu_context *smu,
*(uint32_t *)data = smu->smu_power.power_gate.vcn_gated ? 0 : 1;
*size = 4;
break;
+   case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
+   *(uint32_t *)data = 0;
+   *size = 4;
+   break;
default:
if (smu->ppt_funcs->read_sensor)
ret = smu->ppt_funcs->read_sensor(smu, sensor, data, 
size);
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c 
b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 1a17d853afbd..993976452467 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -1193,10 +1193,6 @@ int smu_v11_0_read_sensor(struct smu_context *smu,
ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
*size = 4;
break;
-   case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
-   *(uint32_t *)data = 0;
-   *size = 4;
-   break;
default:
ret = -EOPNOTSUPP;
break;
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c 
b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
index ae1035575808..b03127273d56 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
@@ -221,10 +221,6 @@ int smu_v12_0_read_sensor(struct smu_context *smu,
ret = smu_get_current_clk_freq(smu, SMU_GFXCLK, (uint32_t 
*)data);
*size = 4;
break;
-   case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
-   *(uint32_t *)data = 0;
-   *size = 4;
-   break;
default:
ret = -EOPNOTSUPP;
break;
-- 
2.27.0

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[PATCH 1/3] drm/amd/powerplay: drop unnecessary SMU_MSG_GetDpmClockFreq check

2020-06-09 Thread Evan Quan 
Since SMU_MSG_GetDpmClockFreq is known to be supported for Vega20
and before ASICs only. For those ASICs supporting swSMU, it is not
supported.

Change-Id: I8ee71664baa32e40df5bb793550785120f3770c6
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 17 +++--
 1 file changed, 3 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c 
b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 9e3fee9e4aca..d10d15fc7492 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -1089,24 +1089,13 @@ int smu_v11_0_get_current_clk_freq(struct smu_context 
*smu,
 {
int ret = 0;
uint32_t freq = 0;
-   int asic_clk_id;
 
if (clk_id >= SMU_CLK_COUNT || !value)
return -EINVAL;
 
-   asic_clk_id = smu_clk_get_index(smu, clk_id);
-   if (asic_clk_id < 0)
-   return -EINVAL;
-
-   /* if don't has GetDpmClockFreq Message, try get current clock by 
SmuMetrics_t */
-   if (smu_msg_get_index(smu, SMU_MSG_GetDpmClockFreq) < 0)
-   ret =  smu_get_current_clk_freq_by_table(smu, clk_id, );
-   else {
-   ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetDpmClockFreq,
- (asic_clk_id << 16), );
-   if (ret)
-   return ret;
-   }
+   ret =  smu_get_current_clk_freq_by_table(smu, clk_id, );
+   if (ret)
+   return ret;
 
freq *= 100;
*value = freq;
-- 
2.27.0

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[PATCH 2/2] drm/amd/powerplay: drop unnecessary wrapper .populate_smc_tables

2020-06-09 Thread Evan Quan 
Since .populate_smc_tables is just a wrapper of .set_default_dpm_table.

Change-Id: I80e89146359d6cf5d80f1887878d371b41b41cb0
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 2 +-
 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c   | 1 -
 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 1 -
 drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h  | 2 --
 drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h  | 2 +-
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 1 -
 drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 2 +-
 drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c | 1 -
 drivers/gpu/drm/amd/powerplay/smu_internal.h   | 2 --
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c  | 9 -
 drivers/gpu/drm/amd/powerplay/smu_v12_0.c  | 2 +-
 11 files changed, 4 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 89dd12536d58..78263de02678 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -813,7 +813,7 @@ static int smu_late_init(void *handle)
 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each
 * type of clks.
 */
-   ret = smu_populate_smc_tables(smu);
+   ret = smu_set_default_dpm_table(smu);
if (ret) {
dev_err(adev->dev, "Failed to setup default dpm clock 
tables!\n");
return ret;
diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 
b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
index 96c9a348f8b3..ee492fc77414 100644
--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
@@ -2587,7 +2587,6 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
/* pptable related */
.setup_pptable = arcturus_setup_pptable,
.get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
-   .populate_smc_tables = smu_v11_0_populate_smc_pptable,
.check_fw_version = smu_v11_0_check_fw_version,
.write_pptable = smu_v11_0_write_pptable,
.set_driver_table_location = smu_v11_0_set_driver_table_location,
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 3420a58fad03..0d1429fc791b 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -505,7 +505,6 @@ struct pptable_funcs {
int (*check_fw_status)(struct smu_context *smu);
int (*setup_pptable)(struct smu_context *smu);
int (*get_vbios_bootup_values)(struct smu_context *smu);
-   int (*populate_smc_tables)(struct smu_context *smu);
int (*check_fw_version)(struct smu_context *smu);
int (*powergate_sdma)(struct smu_context *smu, bool gate);
int (*set_gfx_cgpg)(struct smu_context *smu, bool enable);
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h 
b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
index 9ccf62e99dcb..d6cd3d74dcfa 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
@@ -164,8 +164,6 @@ int smu_v11_0_setup_pptable(struct smu_context *smu);
 
 int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu);
 
-int smu_v11_0_populate_smc_pptable(struct smu_context *smu);
-
 int smu_v11_0_check_fw_version(struct smu_context *smu);
 
 int smu_v11_0_write_pptable(struct smu_context *smu);
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h 
b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
index 7fbebc1979cf..d29f75223987 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
@@ -72,7 +72,7 @@ int smu_v12_0_init_smc_tables(struct smu_context *smu);
 
 int smu_v12_0_fini_smc_tables(struct smu_context *smu);
 
-int smu_v12_0_populate_smc_tables(struct smu_context *smu);
+int smu_v12_0_set_default_dpm_tables(struct smu_context *smu);
 
 int smu_v12_0_get_enabled_mask(struct smu_context *smu,
  uint32_t *feature_mask, uint32_t num);
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c 
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index abbfcce6d9ad..ef04ab1eba94 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -2423,7 +2423,6 @@ static const struct pptable_funcs navi10_ppt_funcs = {
.check_fw_status = smu_v11_0_check_fw_status,
.setup_pptable = navi10_setup_pptable,
.get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
-   .populate_smc_tables = smu_v11_0_populate_smc_pptable,
.check_fw_version = smu_v11_0_check_fw_version,
.write_pptable = smu_v11_0_write_pptable,
.set_driver_table_location = smu_v11_0_set_driver_table_location,
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c

[PATCH 1/2] drm/amd/powerplay: drop redundant .set_min_dcefclk_deep_sleep API

2020-06-09 Thread Evan Quan 
It has exactly the same functionality as .set_deep_sleep_dcefclk.

Change-Id: Ib4d2d604ca014e194cb2b61ac770e4370ecad74d
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 11 +--
 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c   |  3 +--
 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h |  1 -
 drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h  |  2 --
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c |  1 -
 drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c |  3 +--
 drivers/gpu/drm/amd/powerplay/smu_internal.h   |  4 ++--
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c  | 10 --
 8 files changed, 9 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 6beae3b496be..89dd12536d58 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -1269,7 +1269,8 @@ static int smu_smc_hw_setup(struct smu_context *smu)
 * Set min deep sleep dce fclk with bootup value from vbios via
 * SetMinDeepSleepDcefclk MSG.
 */
-   ret = smu_set_min_dcef_deep_sleep(smu);
+   ret = smu_set_min_dcef_deep_sleep(smu,
+ smu->smu_table.boot_values.dcefclk / 
100);
if (ret)
return ret;
 
@@ -1584,9 +1585,8 @@ int smu_display_configuration_change(struct smu_context 
*smu,
 
mutex_lock(>mutex);
 
-   if (smu->ppt_funcs->set_deep_sleep_dcefclk)
-   smu->ppt_funcs->set_deep_sleep_dcefclk(smu,
-   display_config->min_dcef_deep_sleep_set_clk / 
100);
+   smu_set_min_dcef_deep_sleep(smu,
+   display_config->min_dcef_deep_sleep_set_clk 
/ 100);
 
for (index = 0; index < display_config->num_path_including_non_display; 
index++) {
if (display_config->displays[index].controller_id != 0)
@@ -2482,8 +2482,7 @@ int smu_set_deep_sleep_dcefclk(struct smu_context *smu, 
int clk)
 
mutex_lock(>mutex);
 
-   if (smu->ppt_funcs->set_deep_sleep_dcefclk)
-   ret = smu->ppt_funcs->set_deep_sleep_dcefclk(smu, clk);
+   ret = smu_set_min_dcef_deep_sleep(smu, clk);
 
mutex_unlock(>mutex);
 
diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 
b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
index c104844b28f1..96c9a348f8b3 100644
--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
@@ -2590,7 +2590,6 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
.populate_smc_tables = smu_v11_0_populate_smc_pptable,
.check_fw_version = smu_v11_0_check_fw_version,
.write_pptable = smu_v11_0_write_pptable,
-   .set_min_dcef_deep_sleep = NULL,
.set_driver_table_location = smu_v11_0_set_driver_table_location,
.set_tool_table_location = smu_v11_0_set_tool_table_location,
.notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
@@ -2605,7 +2604,7 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
.init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
.enable_thermal_alert = smu_v11_0_enable_thermal_alert,
.disable_thermal_alert = smu_v11_0_disable_thermal_alert,
-   .set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
+   .set_deep_sleep_dcefclk = NULL,
.display_clock_voltage_request = 
smu_v11_0_display_clock_voltage_request,
.get_fan_control_mode = smu_v11_0_get_fan_control_mode,
.set_fan_control_mode = smu_v11_0_set_fan_control_mode,
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 8eaa6338ad44..3420a58fad03 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -510,7 +510,6 @@ struct pptable_funcs {
int (*powergate_sdma)(struct smu_context *smu, bool gate);
int (*set_gfx_cgpg)(struct smu_context *smu, bool enable);
int (*write_pptable)(struct smu_context *smu);
-   int (*set_min_dcef_deep_sleep)(struct smu_context *smu);
int (*set_driver_table_location)(struct smu_context *smu);
int (*set_tool_table_location)(struct smu_context *smu);
int (*notify_memory_pool_location)(struct smu_context *smu);
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h 
b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
index 2e9939beb128..9ccf62e99dcb 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
@@ -170,8 +170,6 @@ int smu_v11_0_check_fw_version(struct smu_context *smu);
 
 int smu_v11_0_write_pptable(struct smu_context *smu);
 
-int smu_v11_0_set_min_dcef_deep_sleep(struct smu_context *smu);
-
 int smu_v11_0_set_driver_table_location(struct smu_context *smu);
 
 int smu_v11_0_set_tool_table_location(struct

Re: [PATCH] drm/amd/amdgpu: handle return value of amdgpu_driver_load_kms

2020-06-09 Thread Nirmoy 

Acked-by: Nirmoy Das 

On 6/9/20 11:20 AM, Liu ChengZhe wrote:

if guest driver failed to enter full GPU access, amdgpu_driver_load_kms
will unload kms and free dev->dev_private, drm_dev_register would access
null pointer. Driver will enter an error state and can't be unloaded.

Signed-off-by: Liu ChengZhe 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 4 +++-
  1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 667aad1f15c0..9c81a3d0b546 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -1165,7 +1165,9 @@ static int amdgpu_pci_probe(struct pci_dev *pdev,
  
  	pci_set_drvdata(pdev, dev);
  
-	amdgpu_driver_load_kms(dev, ent->driver_data);

+   ret = amdgpu_driver_load_kms(dev, ent->driver_data);
+   if (ret)
+   goto err_pci;
  
  retry_init:

ret = drm_dev_register(dev, ent->driver_data);

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[PATCH] drm/amd/amdgpu: handle return value of amdgpu_driver_load_kms

2020-06-09 Thread Liu ChengZhe 
if guest driver failed to enter full GPU access, amdgpu_driver_load_kms
will unload kms and free dev->dev_private, drm_dev_register would access
null pointer. Driver will enter an error state and can't be unloaded.

Signed-off-by: Liu ChengZhe 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 667aad1f15c0..9c81a3d0b546 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -1165,7 +1165,9 @@ static int amdgpu_pci_probe(struct pci_dev *pdev,
 
pci_set_drvdata(pdev, dev);
 
-   amdgpu_driver_load_kms(dev, ent->driver_data);
+   ret = amdgpu_driver_load_kms(dev, ent->driver_data);
+   if (ret)
+   goto err_pci;
 
 retry_init:
ret = drm_dev_register(dev, ent->driver_data);
-- 
2.25.1

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Re: [PATCH v5 06/13] drm/amd: Gate i2c transaction logs on drm_debug_syslog

2020-06-09 Thread Christian König 

Am 08.06.20 um 23:04 schrieb Sean Paul:

From: Sean Paul 

Since the logs protected by these checks specifically target syslog,
use the new drm_debug_syslog_enabled() call to avoid triggering
these prints when only trace is enabled.


Mhm, of hand that doesn't looks like something which belongs into the 
syslog in the first place. Maybe convert it into a trace point instead?




Signed-off-by: Sean Paul 


Acked-by: Christian König  either way.



Changes in v5:
-Added to the set
---
  drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c 
b/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c
index 9bffbab35041..9bc6baddd302 100644
--- a/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c
+++ b/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c
@@ -233,7 +233,7 @@ static uint32_t smu_v11_0_i2c_transmit(struct i2c_adapter 
*control,
DRM_DEBUG_DRIVER("I2C_Transmit(), address = %x, bytes = %d , data: ",
 (uint16_t)address, numbytes);
  
-	if (drm_debug_enabled(DRM_UT_DRIVER)) {

+   if (drm_debug_syslog_enabled(DRM_UT_DRIVER)) {
print_hex_dump(KERN_INFO, "data: ", DUMP_PREFIX_NONE,
   16, 1, data, numbytes, false);
}
@@ -387,7 +387,7 @@ static uint32_t smu_v11_0_i2c_receive(struct i2c_adapter 
*control,
DRM_DEBUG_DRIVER("I2C_Receive(), address = %x, bytes = %d, data :",
  (uint16_t)address, bytes_received);
  
-	if (drm_debug_enabled(DRM_UT_DRIVER)) {

+   if (drm_debug_syslog_enabled(DRM_UT_DRIVER)) {
print_hex_dump(KERN_INFO, "data: ", DUMP_PREFIX_NONE,
   16, 1, data, bytes_received, false);
}


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