RE: [PATCH] drm/amd/pm: update driver if file for sienna cichlid
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Jiansong Chen
-Original Message-
From: amd-gfx On Behalf Of Likun Gao
Sent: Tuesday, September 22, 2020 11:17 AM
To: amd-gfx@lists.freedesktop.org
Cc: Gao, Likun ; Feng, Kenneth ;
Zhang, Hawking
Subject: [PATCH] drm/amd/pm: update driver if file for sienna cichlid
From: Likun Gao
Update driver if file for sienna cichlid.
Signed-off-by: Likun Gao
Change-Id: I295edda90d156c4cea742e62fab696afb6cd1366
---
drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h | 4 ++--
drivers/gpu/drm/amd/pm/inc/smu_v11_0.h | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h
b/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h
index 11a6cf96fe0c..1275246769d9 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h
@@ -27,7 +27,7 @@
// *** IMPORTANT ***
// SMU TEAM: Always increment the interface version if // any structure is
changed in this file -#define SMU11_DRIVER_IF_VERSION 0x37
+#define SMU11_DRIVER_IF_VERSION 0x39
#define PPTABLE_Sienna_Cichlid_SMU_VERSION 6
@@ -962,7 +962,7 @@ typedef struct {
uint8_tFanLinearPwmPoints[NUM_OD_FAN_MAX_POINTS];
uint8_tFanLinearTempPoints[NUM_OD_FAN_MAX_POINTS];
uint16_t MaxOpTemp;// Degree Celcius
- uint16_t Padding_16[1];
+ int16_tVddGfxOffset; // in mV
uint8_tFanZeroRpmEnable;
uint8_tFanZeroRpmStopTemp;
uint8_tFanMode;
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
index 7ae83df83edb..03198d214bba 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
@@ -30,7 +30,7 @@
#define SMU11_DRIVER_IF_VERSION_NV10 0x36 #define
SMU11_DRIVER_IF_VERSION_NV12 0x36 #define SMU11_DRIVER_IF_VERSION_NV14 0x36
-#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x37
+#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x39
#define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0x5
/* MP Apertures */
--
2.25.1
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[PATCH] drm/amd/pm: update driver if file for sienna cichlid
From: Likun Gao
Update driver if file for sienna cichlid.
Signed-off-by: Likun Gao
Change-Id: I295edda90d156c4cea742e62fab696afb6cd1366
---
drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h | 4 ++--
drivers/gpu/drm/amd/pm/inc/smu_v11_0.h | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h
b/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h
index 11a6cf96fe0c..1275246769d9 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h
@@ -27,7 +27,7 @@
// *** IMPORTANT ***
// SMU TEAM: Always increment the interface version if
// any structure is changed in this file
-#define SMU11_DRIVER_IF_VERSION 0x37
+#define SMU11_DRIVER_IF_VERSION 0x39
#define PPTABLE_Sienna_Cichlid_SMU_VERSION 6
@@ -962,7 +962,7 @@ typedef struct {
uint8_tFanLinearPwmPoints[NUM_OD_FAN_MAX_POINTS];
uint8_tFanLinearTempPoints[NUM_OD_FAN_MAX_POINTS];
uint16_t MaxOpTemp;// Degree Celcius
- uint16_t Padding_16[1];
+ int16_tVddGfxOffset; // in mV
uint8_tFanZeroRpmEnable;
uint8_tFanZeroRpmStopTemp;
uint8_tFanMode;
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
index 7ae83df83edb..03198d214bba 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
@@ -30,7 +30,7 @@
#define SMU11_DRIVER_IF_VERSION_NV10 0x36
#define SMU11_DRIVER_IF_VERSION_NV12 0x36
#define SMU11_DRIVER_IF_VERSION_NV14 0x36
-#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x37
+#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x39
#define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0x5
/* MP Apertures */
--
2.25.1
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RE: [PATCH] drm/amdgpu: Fix L1 policy violations (PSP) on sienna cichlid SRIOV
[AMD Public Use]
Thanks Monk.
Take a look at this patch it almost exclude all the rlc callback function from
guest sriov sequence. That's why I would suggest we even don't initialize any
rlc callback function for sriov while check the function pointer before access
it.
Regarding CG/PG feature, if we don't need it in SRIOV guest, just remove the
corresponding mask for SRIOV. It's really not a good practice to add check in
every function.
Regards,
Hawking
-Original Message-
From: Liu, Monk
Sent: Tuesday, September 22, 2020 10:57
To: Liu, Monk ; Zhang, Hawking ;
Khaire, Rohit ; amd-gfx@lists.freedesktop.org
Cc: Xiao, Jack ; Xu, Feifei ; Wang,
Kevin(Yang) ; Li, Rong (Zero) ; Min,
Frank ; Yuan, Xiaojie
Subject: 回复: [PATCH] drm/amdgpu: Fix L1 policy violations (PSP) on sienna
cichlid SRIOV
I think the main problem is RLCG is not an independent IP block but embedded in
GFX block, so that make it hard to cut off from amdgpu for SRIOV
But I think we still have chance to introduce one more layer between GFX and
RLCG and redundant RLCG functions for SRIOV
(except the part that some L1 blocked registers are accessed through RLCG path
)
-邮件原件-
发件人: amd-gfx 代表 Liu, Monk
发送时间: 2020年9月22日 10:54
收件人: Zhang, Hawking ; Khaire, Rohit
; amd-gfx@lists.freedesktop.org
抄送: Xiao, Jack ; Xu, Feifei ; Wang,
Kevin(Yang) ; Li, Rong (Zero) ; Min,
Frank ; Yuan, Xiaojie
主题: 回复: [PATCH] drm/amdgpu: Fix L1 policy violations (PSP) on sienna cichlid
SRIOV
Yeah, Let's have a deep discussion regarding RLCG logic
-邮件原件-
发件人: Zhang, Hawking
发送时间: 2020年9月22日 10:04
收件人: Zhang, Hawking ; Khaire, Rohit
; amd-gfx@lists.freedesktop.org; Liu, Monk
抄送: Xiao, Jack ; Xu, Feifei ; Wang,
Kevin(Yang) ; Li, Rong (Zero) ; Min,
Frank ; Yuan, Xiaojie
主题: RE: [PATCH] drm/amdgpu: Fix L1 policy violations (PSP) on sienna cichlid
SRIOV
[AMD Public Use]
Add @Liu, Monk for a more reasonable approach if any.
Regards,
Hawking
-Original Message-
From: amd-gfx On Behalf Of Zhang,
Hawking
Sent: Tuesday, September 22, 2020 10:02
To: Khaire, Rohit ; amd-gfx@lists.freedesktop.org
Cc: Xiao, Jack ; Xu, Feifei ; Wang,
Kevin(Yang) ; Li, Rong (Zero) ; Min,
Frank ; Yuan, Xiaojie
Subject: RE: [PATCH] drm/amdgpu: Fix L1 policy violations (PSP) on sienna
cichlid SRIOV
[AMD Public Use]
This is really not a sustainable approach -- add amdgpu_sriov_vf(adev) check
for every callback function.
If RLC is not allowed to access from guest, we shall not initialize
gfx.rlc.funcs for sriov guest..., while check the function pointer before
invoke the function.
I think we really need to think about the approach we are using to support
sriov guest. I'm afraid, in current approach, more and more functions will have
to add amdgpu_sriov_vf(adev) check
Regards,
Hawking
-Original Message-
From: Khaire, Rohit
Sent: Tuesday, September 22, 2020 05:16
To: amd-gfx@lists.freedesktop.org
Cc: Xiao, Jack ; Zhang, Hawking ; Xu,
Feifei ; Wang, Kevin(Yang) ; Yuan,
Xiaojie ; Li, Rong (Zero) ; Min, Frank
Subject: RE: [PATCH] drm/amdgpu: Fix L1 policy violations (PSP) on sienna
cichlid SRIOV
[AMD Public Use]
Adding more reviewers to cc.
Rohit
-Original Message-
From: Khaire, Rohit
Sent: September 3, 2020 5:50 PM
To: amd-gfx@lists.freedesktop.org
Cc: Khaire, Rohit
Subject: [PATCH] drm/amdgpu: Fix L1 policy violations (PSP) on sienna cichlid
SRIOV
Signed-off-by: Rohit Khaire
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 49 --
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c | 64 +++-
drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 42
3 files changed, 95 insertions(+), 60 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index d502e30f67d9..4bafbd453e53 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4808,14 +4808,23 @@ static int gfx_v10_0_init_csb(struct amdgpu_device
*adev)
void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) {
- u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
+ u32 tmp;
+ /* For SRIOV, don't touch RLC_G */
+ if (amdgpu_sriov_vf(adev))
+ return;
+
+ tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
}
static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev) {
+ /* For SRIOV, don't touch RLC_G */
+ if (amdgpu_sriov_vf(adev))
+ return;
+
WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
udelay(50);
WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); @@ -4846,6
+4855,10 @@ static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device
*adev,
static void gfx_v10_0_rlc_start(struct amdgpu_device *adev) {
+ /* For SRIOV, don't touch RLC_G */
+ if (amdgpu_sriov_vf(adev))
+
[PATCH umr] Fix register name lookup for sdma POLL_REGMEM packet
POLL_REGMEM_ADDR_LO/HI are in byte but umr_reg_name() expects register address
in dword
Signed-off-by: Xiaojie Yuan
---
src/lib/ring_decode.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/lib/ring_decode.c b/src/lib/ring_decode.c
index a74229d..b5838d1 100644
--- a/src/lib/ring_decode.c
+++ b/src/lib/ring_decode.c
@@ -1904,10 +1904,10 @@ static void parse_next_sdma_pkt(struct umr_asic *asic,
struct umr_ring_decoder *
case 0: // WAIT_REG_MEM
switch (decoder->sdma.cur_word) {
case 1:
printf("POLL_REGMEM_ADDR_LO: %s0x%08lx%s", YELLOW, (unsigned long)ib, RST);
- if
(!(decoder->sdma.header_dw & (1UL << 31))) printf("(%s)", umr_reg_name(asic,
ib));
+ if
(!(decoder->sdma.header_dw & (1UL << 31))) printf("(%s)", umr_reg_name(asic, ib
>> 2));
break;
case 2:
printf("POLL_REGMEM_ADDR_HI: %s0x%08lx%s", YELLOW, (unsigned long)ib, RST);
- if
(!(decoder->sdma.header_dw & (1UL << 31))) printf("(%s)", umr_reg_name(asic,
ib));
+ if
(!(decoder->sdma.header_dw & (1UL << 31))) printf("(%s)", umr_reg_name(asic, ib
>> 2));
break;
case 3:
printf("POLL_REGMEM_ADDR_VALUE: %s0x%08lx%s", BLUE, (unsigned long)ib, RST);
break;
--
2.20.1
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RE: [PATCH 2/3] drm/amdgpu: add per device user friendly xgmi events for vega20
> -Original Message-
> From: Kasiviswanathan, Harish
> Sent: Monday, September 21, 2020 8:52 PM
> To: Kim, Jonathan ; amd-gfx@lists.freedesktop.org
> Subject: RE: [PATCH 2/3] drm/amdgpu: add per device user friendly xgmi
> events for vega20
>
> [AMD Official Use Only - Internal Distribution Only]
>
> Few comments inline.
>
> -Original Message-
> From: Kim, Jonathan
> Sent: Thursday, September 17, 2020 2:15 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Kasiviswanathan, Harish ; Kim,
> Jonathan ; Kim, Jonathan
>
> Subject: [PATCH 2/3] drm/amdgpu: add per device user friendly xgmi events
> for vega20
>
> Non-outbound data metrics are non useful so mark them as legacy.
> Bucket new perf counters into device and not device ip.
> Bind events to chip instead of IP.
> Report available event counters and not number of hw counter banks.
> Move DF public macros to private since not needed outside of IP version.
>
> v3: attr groups const array is global but attr groups are allocated per device
> which doesn't work and causes problems on memory allocation and de-
> allocation for pmu unregister. Switch to building const attr groups per pmu
> instead to simplify solution.
>
> v2: add comments on sysfs structure and formatting.
>
> Signed-off-by: Jonathan Kim
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 13 -
> drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c | 341
>
> drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.h | 6 +-
> drivers/gpu/drm/amd/amdgpu/df_v3_6.c| 72 +
> drivers/gpu/drm/amd/amdgpu/df_v3_6.h| 9 -
> 5 files changed, 304 insertions(+), 137 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 13f92dea182a..f43dfdd2716a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -1279,19 +1279,6 @@ bool amdgpu_device_load_pci_state(struct pci_dev
> *pdev);
>
> #include "amdgpu_object.h"
>
> -/* used by df_v3_6.c and amdgpu_pmu.c */
> -#define AMDGPU_PMU_ATTR(_name, _object)
> \
> -static ssize_t
> \
> -_name##_show(struct device *dev, \
> -struct device_attribute *attr, \
> -char *page) \
> -{\
> - BUILD_BUG_ON(sizeof(_object) >= PAGE_SIZE - 1);
> \
> - return sprintf(page, _object "\n"); \
> -}\
> - \
> -static struct device_attribute pmu_attr_##_name = __ATTR_RO(_name)
> -
> static inline bool amdgpu_is_tmz(struct amdgpu_device *adev) {
> return adev->gmc.tmz_enabled;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c
> index 1b0ec715c8ba..74fe8fbdc0d1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c
> @@ -27,9 +27,19 @@
> #include
> #include "amdgpu.h"
> #include "amdgpu_pmu.h"
> -#include "df_v3_6.h"
>
> #define PMU_NAME_SIZE 32
> +#define NUM_FORMATS_AMDGPU_PMU 4
> +#define NUM_FORMATS_DF_LEGACY3
> +#define NUM_EVENTS_DF_LEGACY 8
> +#define NUM_EVENTS_VEGA20_XGMI 2
> +#define NUM_EVENTS_VEGA20_MAXNUM_EVENTS_VEGA20_XGMI
> +
> +struct amdgpu_pmu_event_attribute {
> + struct device_attribute attr;
> + const char *event_str;
> + unsigned int type;
> +};
>
> /* record to keep track of pmu entry per pmu type per device */ struct
> amdgpu_pmu_entry { @@ -37,10 +47,74 @@ struct amdgpu_pmu_entry {
> struct amdgpu_device *adev;
> struct pmu pmu;
> unsigned int pmu_perf_type;
> + struct attribute_group fmt_attr_group;
> + struct amdgpu_pmu_event_attribute *fmt_attr;
> + struct attribute_group evt_attr_group;
> + struct amdgpu_pmu_event_attribute *evt_attr;
> };
>
> +static ssize_t amdgpu_pmu_event_show(struct device *dev,
> + struct device_attribute *attr, char *buf) {
> + struct amdgpu_pmu_event_attribute *amdgpu_pmu_attr;
> +
> + amdgpu_pmu_attr = container_of(attr, struct
> amdgpu_pmu_event_attribute,
> + attr);
> +
> + if (!amdgpu_pmu_attr->type)
> + return sprintf(buf, "%s\n", amdgpu_pmu_attr->event_str);
> +
> + return sprintf(buf, "%s,type=0x%x\n",
> + amdgpu_pmu_attr->event_str, amdgpu_pmu_attr-
> >type); }
> +
> static LIST_HEAD(amdgpu_pmu_list);
>
> +/*
> + * Event formatting is global to all amdgpu events under sysfs folder
> + * /sys/bus/event_source/devices/amdgpu_ where dev_num is the
> + * primary device index. Registered
回复: [PATCH] drm/amdgpu: Fix L1 policy violations (PSP) on sienna cichlid SRIOV
I think the main problem is RLCG is not an independent IP block but embedded in
GFX block, so that make it hard to cut off from amdgpu for SRIOV
But I think we still have chance to introduce one more layer between GFX and
RLCG and redundant RLCG functions for SRIOV
(except the part that some L1 blocked registers are accessed through RLCG path
)
-邮件原件-
发件人: amd-gfx 代表 Liu, Monk
发送时间: 2020年9月22日 10:54
收件人: Zhang, Hawking ; Khaire, Rohit
; amd-gfx@lists.freedesktop.org
抄送: Xiao, Jack ; Xu, Feifei ; Wang,
Kevin(Yang) ; Li, Rong (Zero) ; Min,
Frank ; Yuan, Xiaojie
主题: 回复: [PATCH] drm/amdgpu: Fix L1 policy violations (PSP) on sienna cichlid
SRIOV
Yeah, Let's have a deep discussion regarding RLCG logic
-邮件原件-
发件人: Zhang, Hawking
发送时间: 2020年9月22日 10:04
收件人: Zhang, Hawking ; Khaire, Rohit
; amd-gfx@lists.freedesktop.org; Liu, Monk
抄送: Xiao, Jack ; Xu, Feifei ; Wang,
Kevin(Yang) ; Li, Rong (Zero) ; Min,
Frank ; Yuan, Xiaojie
主题: RE: [PATCH] drm/amdgpu: Fix L1 policy violations (PSP) on sienna cichlid
SRIOV
[AMD Public Use]
Add @Liu, Monk for a more reasonable approach if any.
Regards,
Hawking
-Original Message-
From: amd-gfx On Behalf Of Zhang,
Hawking
Sent: Tuesday, September 22, 2020 10:02
To: Khaire, Rohit ; amd-gfx@lists.freedesktop.org
Cc: Xiao, Jack ; Xu, Feifei ; Wang,
Kevin(Yang) ; Li, Rong (Zero) ; Min,
Frank ; Yuan, Xiaojie
Subject: RE: [PATCH] drm/amdgpu: Fix L1 policy violations (PSP) on sienna
cichlid SRIOV
[AMD Public Use]
This is really not a sustainable approach -- add amdgpu_sriov_vf(adev) check
for every callback function.
If RLC is not allowed to access from guest, we shall not initialize
gfx.rlc.funcs for sriov guest..., while check the function pointer before
invoke the function.
I think we really need to think about the approach we are using to support
sriov guest. I'm afraid, in current approach, more and more functions will have
to add amdgpu_sriov_vf(adev) check
Regards,
Hawking
-Original Message-
From: Khaire, Rohit
Sent: Tuesday, September 22, 2020 05:16
To: amd-gfx@lists.freedesktop.org
Cc: Xiao, Jack ; Zhang, Hawking ; Xu,
Feifei ; Wang, Kevin(Yang) ; Yuan,
Xiaojie ; Li, Rong (Zero) ; Min, Frank
Subject: RE: [PATCH] drm/amdgpu: Fix L1 policy violations (PSP) on sienna
cichlid SRIOV
[AMD Public Use]
Adding more reviewers to cc.
Rohit
-Original Message-
From: Khaire, Rohit
Sent: September 3, 2020 5:50 PM
To: amd-gfx@lists.freedesktop.org
Cc: Khaire, Rohit
Subject: [PATCH] drm/amdgpu: Fix L1 policy violations (PSP) on sienna cichlid
SRIOV
Signed-off-by: Rohit Khaire
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 49 --
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c | 64 +++-
drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 42
3 files changed, 95 insertions(+), 60 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index d502e30f67d9..4bafbd453e53 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4808,14 +4808,23 @@ static int gfx_v10_0_init_csb(struct amdgpu_device
*adev)
void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) {
- u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
+ u32 tmp;
+ /* For SRIOV, don't touch RLC_G */
+ if (amdgpu_sriov_vf(adev))
+ return;
+
+ tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
}
static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev) {
+ /* For SRIOV, don't touch RLC_G */
+ if (amdgpu_sriov_vf(adev))
+ return;
+
WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
udelay(50);
WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); @@ -4846,6
+4855,10 @@ static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device
*adev,
static void gfx_v10_0_rlc_start(struct amdgpu_device *adev) {
+ /* For SRIOV, don't touch RLC_G */
+ if (amdgpu_sriov_vf(adev))
+ return;
+
/* TODO: enable rlc & smu handshake until smu
* and gfxoff feature works as expected */
if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) @@ -4859,6 +4872,10 @@
static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev) {
uint32_t tmp;
+ /* For SRIOV, don't touch RLC_G */
+ if (amdgpu_sriov_vf(adev))
+ return;
+
/* enable Save Restore Machine */
tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
@@ -4872,6 +4889,10 @@ static int gfx_v10_0_rlc_load_microcode(struct
amdgpu_device *adev)
const __le32 *fw_data;
unsigned i, fw_size;
+ /* For SRIOV, don't touch RLC_G */
+ if (amdgpu_sriov_vf(adev))
+ return;
+
if
回复: [PATCH] drm/amdgpu: Fix L1 policy violations (PSP) on sienna cichlid SRIOV
Yeah, Let's have a deep discussion regarding RLCG logic
-邮件原件-
发件人: Zhang, Hawking
发送时间: 2020年9月22日 10:04
收件人: Zhang, Hawking ; Khaire, Rohit
; amd-gfx@lists.freedesktop.org; Liu, Monk
抄送: Xiao, Jack ; Xu, Feifei ; Wang,
Kevin(Yang) ; Li, Rong (Zero) ; Min,
Frank ; Yuan, Xiaojie
主题: RE: [PATCH] drm/amdgpu: Fix L1 policy violations (PSP) on sienna cichlid
SRIOV
[AMD Public Use]
Add @Liu, Monk for a more reasonable approach if any.
Regards,
Hawking
-Original Message-
From: amd-gfx On Behalf Of Zhang,
Hawking
Sent: Tuesday, September 22, 2020 10:02
To: Khaire, Rohit ; amd-gfx@lists.freedesktop.org
Cc: Xiao, Jack ; Xu, Feifei ; Wang,
Kevin(Yang) ; Li, Rong (Zero) ; Min,
Frank ; Yuan, Xiaojie
Subject: RE: [PATCH] drm/amdgpu: Fix L1 policy violations (PSP) on sienna
cichlid SRIOV
[AMD Public Use]
This is really not a sustainable approach -- add amdgpu_sriov_vf(adev) check
for every callback function.
If RLC is not allowed to access from guest, we shall not initialize
gfx.rlc.funcs for sriov guest..., while check the function pointer before
invoke the function.
I think we really need to think about the approach we are using to support
sriov guest. I'm afraid, in current approach, more and more functions will have
to add amdgpu_sriov_vf(adev) check
Regards,
Hawking
-Original Message-
From: Khaire, Rohit
Sent: Tuesday, September 22, 2020 05:16
To: amd-gfx@lists.freedesktop.org
Cc: Xiao, Jack ; Zhang, Hawking ; Xu,
Feifei ; Wang, Kevin(Yang) ; Yuan,
Xiaojie ; Li, Rong (Zero) ; Min, Frank
Subject: RE: [PATCH] drm/amdgpu: Fix L1 policy violations (PSP) on sienna
cichlid SRIOV
[AMD Public Use]
Adding more reviewers to cc.
Rohit
-Original Message-
From: Khaire, Rohit
Sent: September 3, 2020 5:50 PM
To: amd-gfx@lists.freedesktop.org
Cc: Khaire, Rohit
Subject: [PATCH] drm/amdgpu: Fix L1 policy violations (PSP) on sienna cichlid
SRIOV
Signed-off-by: Rohit Khaire
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 49 --
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c | 64 +++-
drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 42
3 files changed, 95 insertions(+), 60 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index d502e30f67d9..4bafbd453e53 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4808,14 +4808,23 @@ static int gfx_v10_0_init_csb(struct amdgpu_device
*adev)
void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) {
- u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
+ u32 tmp;
+ /* For SRIOV, don't touch RLC_G */
+ if (amdgpu_sriov_vf(adev))
+ return;
+
+ tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
}
static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev) {
+ /* For SRIOV, don't touch RLC_G */
+ if (amdgpu_sriov_vf(adev))
+ return;
+
WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
udelay(50);
WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); @@ -4846,6
+4855,10 @@ static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device
*adev,
static void gfx_v10_0_rlc_start(struct amdgpu_device *adev) {
+ /* For SRIOV, don't touch RLC_G */
+ if (amdgpu_sriov_vf(adev))
+ return;
+
/* TODO: enable rlc & smu handshake until smu
* and gfxoff feature works as expected */
if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) @@ -4859,6 +4872,10 @@
static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev) {
uint32_t tmp;
+ /* For SRIOV, don't touch RLC_G */
+ if (amdgpu_sriov_vf(adev))
+ return;
+
/* enable Save Restore Machine */
tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
@@ -4872,6 +4889,10 @@ static int gfx_v10_0_rlc_load_microcode(struct
amdgpu_device *adev)
const __le32 *fw_data;
unsigned i, fw_size;
+ /* For SRIOV, don't touch RLC_G */
+ if (amdgpu_sriov_vf(adev))
+ return;
+
if (!adev->gfx.rlc_fw)
return -EINVAL;
@@ -4906,8 +4927,7 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device
*adev)
gfx_v10_0_init_csb(adev);
- if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
- gfx_v10_0_rlc_enable_srm(adev);
+ gfx_v10_0_rlc_enable_srm(adev);
} else {
if (amdgpu_sriov_vf(adev)) {
gfx_v10_0_init_csb(adev);
@@ -6990,7 +7010,6 @@ static int gfx_v10_0_hw_fini(void *handle)
if (amdgpu_gfx_disable_kcq(adev))
DRM_ERROR("KCQ disable failed\n");
if (amdgpu_sriov_vf(adev)) {
-
RE: [PATCH] drm/amdgpu: Fix L1 policy violations (PSP) on sienna cichlid SRIOV
[AMD Public Use]
If most bare metal sequence is bypassed from guest side, why we don't create
sriov specific ip block and initialize in set_ip_block phase. In such way, we
can have clean code base for both bare metal and sriov guest.
Now the amdgpu_sriov_vf is almost everywhere in amdgpu
Regards,
Hawking
-Original Message-
From: Zhang, Hawking
Sent: Tuesday, September 22, 2020 10:04
To: Zhang, Hawking ; Khaire, Rohit
; amd-gfx@lists.freedesktop.org; Liu, Monk
Cc: Xiao, Jack ; Xu, Feifei ; Wang,
Kevin(Yang) ; Li, Rong (Zero) ; Min,
Frank ; Yuan, Xiaojie
Subject: RE: [PATCH] drm/amdgpu: Fix L1 policy violations (PSP) on sienna
cichlid SRIOV
[AMD Public Use]
Add @Liu, Monk for a more reasonable approach if any.
Regards,
Hawking
-Original Message-
From: amd-gfx On Behalf Of Zhang,
Hawking
Sent: Tuesday, September 22, 2020 10:02
To: Khaire, Rohit ; amd-gfx@lists.freedesktop.org
Cc: Xiao, Jack ; Xu, Feifei ; Wang,
Kevin(Yang) ; Li, Rong (Zero) ; Min,
Frank ; Yuan, Xiaojie
Subject: RE: [PATCH] drm/amdgpu: Fix L1 policy violations (PSP) on sienna
cichlid SRIOV
[AMD Public Use]
This is really not a sustainable approach -- add amdgpu_sriov_vf(adev) check
for every callback function.
If RLC is not allowed to access from guest, we shall not initialize
gfx.rlc.funcs for sriov guest..., while check the function pointer before
invoke the function.
I think we really need to think about the approach we are using to support
sriov guest. I'm afraid, in current approach, more and more functions will have
to add amdgpu_sriov_vf(adev) check
Regards,
Hawking
-Original Message-
From: Khaire, Rohit
Sent: Tuesday, September 22, 2020 05:16
To: amd-gfx@lists.freedesktop.org
Cc: Xiao, Jack ; Zhang, Hawking ; Xu,
Feifei ; Wang, Kevin(Yang) ; Yuan,
Xiaojie ; Li, Rong (Zero) ; Min, Frank
Subject: RE: [PATCH] drm/amdgpu: Fix L1 policy violations (PSP) on sienna
cichlid SRIOV
[AMD Public Use]
Adding more reviewers to cc.
Rohit
-Original Message-
From: Khaire, Rohit
Sent: September 3, 2020 5:50 PM
To: amd-gfx@lists.freedesktop.org
Cc: Khaire, Rohit
Subject: [PATCH] drm/amdgpu: Fix L1 policy violations (PSP) on sienna cichlid
SRIOV
Signed-off-by: Rohit Khaire
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 49 --
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c | 64 +++-
drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 42
3 files changed, 95 insertions(+), 60 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index d502e30f67d9..4bafbd453e53 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4808,14 +4808,23 @@ static int gfx_v10_0_init_csb(struct amdgpu_device
*adev)
void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) {
- u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
+ u32 tmp;
+ /* For SRIOV, don't touch RLC_G */
+ if (amdgpu_sriov_vf(adev))
+ return;
+
+ tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
}
static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev) {
+ /* For SRIOV, don't touch RLC_G */
+ if (amdgpu_sriov_vf(adev))
+ return;
+
WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
udelay(50);
WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); @@ -4846,6
+4855,10 @@ static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device
*adev,
static void gfx_v10_0_rlc_start(struct amdgpu_device *adev) {
+ /* For SRIOV, don't touch RLC_G */
+ if (amdgpu_sriov_vf(adev))
+ return;
+
/* TODO: enable rlc & smu handshake until smu
* and gfxoff feature works as expected */
if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) @@ -4859,6 +4872,10 @@
static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev) {
uint32_t tmp;
+ /* For SRIOV, don't touch RLC_G */
+ if (amdgpu_sriov_vf(adev))
+ return;
+
/* enable Save Restore Machine */
tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
@@ -4872,6 +4889,10 @@ static int gfx_v10_0_rlc_load_microcode(struct
amdgpu_device *adev)
const __le32 *fw_data;
unsigned i, fw_size;
+ /* For SRIOV, don't touch RLC_G */
+ if (amdgpu_sriov_vf(adev))
+ return;
+
if (!adev->gfx.rlc_fw)
return -EINVAL;
@@ -4906,8 +4927,7 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device
*adev)
gfx_v10_0_init_csb(adev);
- if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
- gfx_v10_0_rlc_enable_srm(adev);
+ gfx_v10_0_rlc_enable_srm(adev);
} else {
if
RE: [PATCH] drm/amdgpu: Workaround RCC_DEV0_EPF0_STRAP0 access issue for SRIOV
[AMD Public Use]
You shall by pass get_rev_id function call, instead of adding the check in the
callback function.
For each hw generation, there could be several callback function implementation
depending on whether the mmRCC_DEV0_EPF0_STRAP0 can be re-used.
It's error prone if we just take the change in specific callback. There is no
guarantee people remember to add this check next time when working on the
implementation.
Regards,
Hawking
-Original Message-
From: Khaire, Rohit
Sent: Tuesday, September 22, 2020 04:55
To: amd-gfx@lists.freedesktop.org
Cc: Tuikov, Luben ; Koenig, Christian
; Deucher, Alexander ;
Xiao, Jack ; Zhang, Hawking ; Xu,
Feifei ; Wang, Kevin(Yang) ; Yuan,
Xiaojie ; Li, Rong (Zero) ; Min, Frank
; Khaire, Rohit
Subject: [PATCH] drm/amdgpu: Workaround RCC_DEV0_EPF0_STRAP0 access issue for
SRIOV
Signed-off-by: Rohit Khaire
---
drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
index 7429f30398b9..4f611cd68940 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
@@ -51,8 +51,19 @@ static void nbio_v2_3_remap_hdp_registers(struct
amdgpu_device *adev)
static u32 nbio_v2_3_get_rev_id(struct amdgpu_device *adev) {
- u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
+ u32 tmp;
+
+ if (amdgpu_sriov_vf(adev)) {
+ /* workaround on rev_id for sriov
+* guest vm gets 0x when reading RCC_DEV0_EPF0_STRAP0,
+* as a consequence, the rev_id and external_rev_id are wrong.
+*
+* workaround it by using PCI revision id.
+*/
+ return adev->pdev->revision;
+ }
+ tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
--
2.17.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH] drm/amdgpu: Fix SDMA RAP violations on Sienna Cichlid SRIOV
[AMD Public Use]
Similar as the RLC
If the engine is not allowed to access from the guest (or most bare metal
programming sequence is not allowed in guest environment), we shall consider to
disable it from high level, instead of adding amdgpu_sriov_vf(adev) everywhere.
Regards,
Hawking
-Original Message-
From: Khaire, Rohit
Sent: Tuesday, September 22, 2020 05:14
To: amd-gfx@lists.freedesktop.org
Cc: Tuikov, Luben ; Koenig, Christian
; Deucher, Alexander ;
Xiao, Jack ; Zhang, Hawking ; Xu,
Feifei ; Wang, Kevin(Yang) ; Yuan,
Xiaojie ; Li, Rong (Zero) ; Min, Frank
; Khaire, Rohit
Subject: [PATCH] drm/amdgpu: Fix SDMA RAP violations on Sienna Cichlid SRIOV
Signed-off-by: Rohit Khaire
---
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 128 ++---
1 file changed, 70 insertions(+), 58 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
index 34ccf376ee45..6fb5588fc0b6 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
@@ -541,7 +541,9 @@ static void sdma_v5_2_ctx_switch_enable(struct
amdgpu_device *adev, bool enable)
WREG32(sdma_v5_2_get_reg_offset(adev, i,
mmSDMA0_PHASE2_QUANTUM),
phase_quantum);
}
- WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL),
f32_cntl);
+ if (!amdgpu_sriov_vf(adev))
+ WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL),
+ f32_cntl);
}
}
@@ -559,6 +561,9 @@ static void sdma_v5_2_enable(struct amdgpu_device *adev,
bool enable)
u32 f32_cntl;
int i;
+ if (amdgpu_sriov_vf(adev))
+ return;
+
if (!enable) {
sdma_v5_2_gfx_stop(adev);
sdma_v5_2_rlc_stop(adev);
@@ -596,7 +601,9 @@ static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev)
ring = >sdma.instance[i].ring;
wb_offset = (ring->rptr_offs * 4);
- WREG32(sdma_v5_2_get_reg_offset(adev, i,
mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
+ if (!amdgpu_sriov_vf(adev))
+ WREG32(sdma_v5_2_get_reg_offset(adev, i,
+ mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
/* Set ring buffer size in dwords */
rb_bufsz = order_base_2(ring->ring_size / 4); @@ -621,13
+628,16 @@ static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev)
lower_32_bits(wptr_gpu_addr));
WREG32(sdma_v5_2_get_reg_offset(adev, i,
mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
upper_32_bits(wptr_gpu_addr));
- wptr_poll_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i,
-
mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
- wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
- SDMA0_GFX_RB_WPTR_POLL_CNTL,
- F32_POLL_ENABLE, 1);
- WREG32(sdma_v5_2_get_reg_offset(adev, i,
mmSDMA0_GFX_RB_WPTR_POLL_CNTL),
- wptr_poll_cntl);
+
+ if (!amdgpu_sriov_vf(adev)) {
+ wptr_poll_cntl = RREG32(sdma_v5_2_get_reg_offset(
+ adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
+ wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
+ SDMA0_GFX_RB_WPTR_POLL_CNTL,
+ F32_POLL_ENABLE, 1);
+ WREG32(sdma_v5_2_get_reg_offset(adev, i,
+ mmSDMA0_GFX_RB_WPTR_POLL_CNTL), wptr_poll_cntl);
+ }
/* set the wb address whether it's enabled or not */
WREG32(sdma_v5_2_get_reg_offset(adev, i,
mmSDMA0_GFX_RB_RPTR_ADDR_HI), @@ -673,30 +683,40 @@ static int
sdma_v5_2_gfx_resume(struct amdgpu_device *adev)
/* set minor_ptr_update to 0 after wptr programed */
WREG32(sdma_v5_2_get_reg_offset(adev, i,
mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
- /* set utc l1 enable flag always to 1 */
- temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
- temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
-
- /* enable MCBP */
- temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE,
1);
- WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
-
- /* Set up RESP_MODE to non-copy addresses */
- temp = RREG32(sdma_v5_2_get_reg_offset(adev, i,
mmSDMA0_UTCL1_CNTL));
- temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
- temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
- WREG32(sdma_v5_2_get_reg_offset(adev, i,
RE: [PATCH] drm/amdgpu: Fix L1 policy violations (PSP) on sienna cichlid SRIOV
[AMD Public Use]
Add @Liu, Monk for a more reasonable approach if any.
Regards,
Hawking
-Original Message-
From: amd-gfx On Behalf Of Zhang,
Hawking
Sent: Tuesday, September 22, 2020 10:02
To: Khaire, Rohit ; amd-gfx@lists.freedesktop.org
Cc: Xiao, Jack ; Xu, Feifei ; Wang,
Kevin(Yang) ; Li, Rong (Zero) ; Min,
Frank ; Yuan, Xiaojie
Subject: RE: [PATCH] drm/amdgpu: Fix L1 policy violations (PSP) on sienna
cichlid SRIOV
[AMD Public Use]
This is really not a sustainable approach -- add amdgpu_sriov_vf(adev) check
for every callback function.
If RLC is not allowed to access from guest, we shall not initialize
gfx.rlc.funcs for sriov guest..., while check the function pointer before
invoke the function.
I think we really need to think about the approach we are using to support
sriov guest. I'm afraid, in current approach, more and more functions will have
to add amdgpu_sriov_vf(adev) check
Regards,
Hawking
-Original Message-
From: Khaire, Rohit
Sent: Tuesday, September 22, 2020 05:16
To: amd-gfx@lists.freedesktop.org
Cc: Xiao, Jack ; Zhang, Hawking ; Xu,
Feifei ; Wang, Kevin(Yang) ; Yuan,
Xiaojie ; Li, Rong (Zero) ; Min, Frank
Subject: RE: [PATCH] drm/amdgpu: Fix L1 policy violations (PSP) on sienna
cichlid SRIOV
[AMD Public Use]
Adding more reviewers to cc.
Rohit
-Original Message-
From: Khaire, Rohit
Sent: September 3, 2020 5:50 PM
To: amd-gfx@lists.freedesktop.org
Cc: Khaire, Rohit
Subject: [PATCH] drm/amdgpu: Fix L1 policy violations (PSP) on sienna cichlid
SRIOV
Signed-off-by: Rohit Khaire
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 49 --
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c | 64 +++-
drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 42
3 files changed, 95 insertions(+), 60 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index d502e30f67d9..4bafbd453e53 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4808,14 +4808,23 @@ static int gfx_v10_0_init_csb(struct amdgpu_device
*adev)
void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) {
- u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
+ u32 tmp;
+ /* For SRIOV, don't touch RLC_G */
+ if (amdgpu_sriov_vf(adev))
+ return;
+
+ tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
}
static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev) {
+ /* For SRIOV, don't touch RLC_G */
+ if (amdgpu_sriov_vf(adev))
+ return;
+
WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
udelay(50);
WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); @@ -4846,6
+4855,10 @@ static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device
*adev,
static void gfx_v10_0_rlc_start(struct amdgpu_device *adev) {
+ /* For SRIOV, don't touch RLC_G */
+ if (amdgpu_sriov_vf(adev))
+ return;
+
/* TODO: enable rlc & smu handshake until smu
* and gfxoff feature works as expected */
if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) @@ -4859,6 +4872,10 @@
static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev) {
uint32_t tmp;
+ /* For SRIOV, don't touch RLC_G */
+ if (amdgpu_sriov_vf(adev))
+ return;
+
/* enable Save Restore Machine */
tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
@@ -4872,6 +4889,10 @@ static int gfx_v10_0_rlc_load_microcode(struct
amdgpu_device *adev)
const __le32 *fw_data;
unsigned i, fw_size;
+ /* For SRIOV, don't touch RLC_G */
+ if (amdgpu_sriov_vf(adev))
+ return;
+
if (!adev->gfx.rlc_fw)
return -EINVAL;
@@ -4906,8 +4927,7 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device
*adev)
gfx_v10_0_init_csb(adev);
- if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
- gfx_v10_0_rlc_enable_srm(adev);
+ gfx_v10_0_rlc_enable_srm(adev);
} else {
if (amdgpu_sriov_vf(adev)) {
gfx_v10_0_init_csb(adev);
@@ -6990,7 +7010,6 @@ static int gfx_v10_0_hw_fini(void *handle)
if (amdgpu_gfx_disable_kcq(adev))
DRM_ERROR("KCQ disable failed\n");
if (amdgpu_sriov_vf(adev)) {
- gfx_v10_0_cp_gfx_enable(adev, false);
/* Program KIQ position of RLC_CP_SCHEDULERS during destroy */
tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
tmp &= 0xff00;
@@ -7272,6 +7291,10 @@ static void
gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *ade {
uint32_t data, def;
+ /* For SRIOV, guest VM
RE: [PATCH] drm/amdgpu: Fix L1 policy violations (PSP) on sienna cichlid SRIOV
[AMD Public Use]
This is really not a sustainable approach -- add amdgpu_sriov_vf(adev) check
for every callback function.
If RLC is not allowed to access from guest, we shall not initialize
gfx.rlc.funcs for sriov guest..., while check the function pointer before
invoke the function.
I think we really need to think about the approach we are using to support
sriov guest. I'm afraid, in current approach, more and more functions will have
to add amdgpu_sriov_vf(adev) check
Regards,
Hawking
-Original Message-
From: Khaire, Rohit
Sent: Tuesday, September 22, 2020 05:16
To: amd-gfx@lists.freedesktop.org
Cc: Xiao, Jack ; Zhang, Hawking ; Xu,
Feifei ; Wang, Kevin(Yang) ; Yuan,
Xiaojie ; Li, Rong (Zero) ; Min, Frank
Subject: RE: [PATCH] drm/amdgpu: Fix L1 policy violations (PSP) on sienna
cichlid SRIOV
[AMD Public Use]
Adding more reviewers to cc.
Rohit
-Original Message-
From: Khaire, Rohit
Sent: September 3, 2020 5:50 PM
To: amd-gfx@lists.freedesktop.org
Cc: Khaire, Rohit
Subject: [PATCH] drm/amdgpu: Fix L1 policy violations (PSP) on sienna cichlid
SRIOV
Signed-off-by: Rohit Khaire
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 49 --
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c | 64 +++-
drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 42
3 files changed, 95 insertions(+), 60 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index d502e30f67d9..4bafbd453e53 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4808,14 +4808,23 @@ static int gfx_v10_0_init_csb(struct amdgpu_device
*adev)
void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) {
- u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
+ u32 tmp;
+ /* For SRIOV, don't touch RLC_G */
+ if (amdgpu_sriov_vf(adev))
+ return;
+
+ tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
}
static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev) {
+ /* For SRIOV, don't touch RLC_G */
+ if (amdgpu_sriov_vf(adev))
+ return;
+
WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
udelay(50);
WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); @@ -4846,6
+4855,10 @@ static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device
*adev,
static void gfx_v10_0_rlc_start(struct amdgpu_device *adev) {
+ /* For SRIOV, don't touch RLC_G */
+ if (amdgpu_sriov_vf(adev))
+ return;
+
/* TODO: enable rlc & smu handshake until smu
* and gfxoff feature works as expected */
if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) @@ -4859,6 +4872,10 @@
static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev) {
uint32_t tmp;
+ /* For SRIOV, don't touch RLC_G */
+ if (amdgpu_sriov_vf(adev))
+ return;
+
/* enable Save Restore Machine */
tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
@@ -4872,6 +4889,10 @@ static int gfx_v10_0_rlc_load_microcode(struct
amdgpu_device *adev)
const __le32 *fw_data;
unsigned i, fw_size;
+ /* For SRIOV, don't touch RLC_G */
+ if (amdgpu_sriov_vf(adev))
+ return;
+
if (!adev->gfx.rlc_fw)
return -EINVAL;
@@ -4906,8 +4927,7 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device
*adev)
gfx_v10_0_init_csb(adev);
- if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
- gfx_v10_0_rlc_enable_srm(adev);
+ gfx_v10_0_rlc_enable_srm(adev);
} else {
if (amdgpu_sriov_vf(adev)) {
gfx_v10_0_init_csb(adev);
@@ -6990,7 +7010,6 @@ static int gfx_v10_0_hw_fini(void *handle)
if (amdgpu_gfx_disable_kcq(adev))
DRM_ERROR("KCQ disable failed\n");
if (amdgpu_sriov_vf(adev)) {
- gfx_v10_0_cp_gfx_enable(adev, false);
/* Program KIQ position of RLC_CP_SCHEDULERS during destroy */
tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
tmp &= 0xff00;
@@ -7272,6 +7291,10 @@ static void
gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *ade {
uint32_t data, def;
+ /* For SRIOV, guest VM should not touch CGCG and PG stuff */
+ if (amdgpu_sriov_vf(adev))
+ return;
+
/* It is disabled by HW by default */
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
/* 0 - Disable some blocks' MGCG */
@@ -7339,6 +7362,10 @@ static void gfx_v10_0_update_3d_clock_gating(struct
amdgpu_device *adev, {
uint32_t data, def;
+ /* For SRIOV, guest VM should not touch
RE: [PATCH 2/3] drm/amdgpu: add per device user friendly xgmi events for vega20
[AMD Official Use Only - Internal Distribution Only]
Few comments inline.
-Original Message-
From: Kim, Jonathan
Sent: Thursday, September 17, 2020 2:15 PM
To: amd-gfx@lists.freedesktop.org
Cc: Kasiviswanathan, Harish ; Kim, Jonathan
; Kim, Jonathan
Subject: [PATCH 2/3] drm/amdgpu: add per device user friendly xgmi events for
vega20
Non-outbound data metrics are non useful so mark them as legacy.
Bucket new perf counters into device and not device ip.
Bind events to chip instead of IP.
Report available event counters and not number of hw counter banks.
Move DF public macros to private since not needed outside of IP version.
v3: attr groups const array is global but attr groups are allocated per
device which doesn't work and causes problems on memory allocation and
de-allocation for pmu unregister. Switch to building const attr groups
per pmu instead to simplify solution.
v2: add comments on sysfs structure and formatting.
Signed-off-by: Jonathan Kim
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 13 -
drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c | 341
drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.h | 6 +-
drivers/gpu/drm/amd/amdgpu/df_v3_6.c| 72 +
drivers/gpu/drm/amd/amdgpu/df_v3_6.h| 9 -
5 files changed, 304 insertions(+), 137 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 13f92dea182a..f43dfdd2716a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1279,19 +1279,6 @@ bool amdgpu_device_load_pci_state(struct pci_dev *pdev);
#include "amdgpu_object.h"
-/* used by df_v3_6.c and amdgpu_pmu.c */
-#define AMDGPU_PMU_ATTR(_name, _object)
\
-static ssize_t \
-_name##_show(struct device *dev, \
- struct device_attribute *attr, \
- char *page) \
-{ \
- BUILD_BUG_ON(sizeof(_object) >= PAGE_SIZE - 1); \
- return sprintf(page, _object "\n"); \
-} \
- \
-static struct device_attribute pmu_attr_##_name = __ATTR_RO(_name)
-
static inline bool amdgpu_is_tmz(struct amdgpu_device *adev)
{
return adev->gmc.tmz_enabled;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c
index 1b0ec715c8ba..74fe8fbdc0d1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c
@@ -27,9 +27,19 @@
#include
#include "amdgpu.h"
#include "amdgpu_pmu.h"
-#include "df_v3_6.h"
#define PMU_NAME_SIZE 32
+#define NUM_FORMATS_AMDGPU_PMU 4
+#define NUM_FORMATS_DF_LEGACY 3
+#define NUM_EVENTS_DF_LEGACY 8
+#define NUM_EVENTS_VEGA20_XGMI 2
+#define NUM_EVENTS_VEGA20_MAX NUM_EVENTS_VEGA20_XGMI
+
+struct amdgpu_pmu_event_attribute {
+ struct device_attribute attr;
+ const char *event_str;
+ unsigned int type;
+};
/* record to keep track of pmu entry per pmu type per device */
struct amdgpu_pmu_entry {
@@ -37,10 +47,74 @@ struct amdgpu_pmu_entry {
struct amdgpu_device *adev;
struct pmu pmu;
unsigned int pmu_perf_type;
+ struct attribute_group fmt_attr_group;
+ struct amdgpu_pmu_event_attribute *fmt_attr;
+ struct attribute_group evt_attr_group;
+ struct amdgpu_pmu_event_attribute *evt_attr;
};
+static ssize_t amdgpu_pmu_event_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct amdgpu_pmu_event_attribute *amdgpu_pmu_attr;
+
+ amdgpu_pmu_attr = container_of(attr, struct amdgpu_pmu_event_attribute,
+ attr);
+
+ if (!amdgpu_pmu_attr->type)
+ return sprintf(buf, "%s\n", amdgpu_pmu_attr->event_str);
+
+ return sprintf(buf, "%s,type=0x%x\n",
+ amdgpu_pmu_attr->event_str, amdgpu_pmu_attr->type);
+}
+
static LIST_HEAD(amdgpu_pmu_list);
+/*
+ * Event formatting is global to all amdgpu events under sysfs folder
+ * /sys/bus/event_source/devices/amdgpu_ where dev_num is the
+ * primary device index. Registered events can be found in subfolder "events"
+ * and formatting under subfolder "format".
+ *
+ * Formats "event", "instance", and "umask" are currently used by xGMI but can
+ * be for generalized for other IP usage. If format naming is insufficient
+ * for newly registered IP events, append to the list below and handle the
+ * perf events hardware configuration (see hwc->config) as required by the IP.
+ *
+ * Format
[PATCH] drm/amd/display: Fix dcn30_optc.o unknown argument with clang
[Why] Clang can't compile dcn30_optc.o with '-mpreferred-stack-boundary=4' [How] use '-mstack-alignment=4' if Clang is CC and '-mpreferred-stack-boundary=4' if CC is not Clang Signed-off-by: Anthony Benware --- drivers/gpu/drm/amd/display/dc/dcn30/Makefile | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/Makefile b/drivers/gpu/drm/amd/display/dc/dcn30/Makefile index 025637a83c3b..fcded5498393 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dcn30/Makefile @@ -31,7 +31,11 @@ DCN30 = dcn30_init.o dcn30_hubbub.o dcn30_hubp.o dcn30_dpp.o dcn30_optc.o \ dcn30_dio_link_encoder.o dcn30_resource.o +ifdef CONFIG_CC_IS_CLANG +CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_optc.o := -mhard-float -msse -mstack-alignment=4 +else CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_optc.o := -mhard-float -msse -mpreferred-stack-boundary=4 +endif CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_resource.o := -mhard-float -msse ifdef CONFIG_CC_IS_GCC -- 2.28.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdkfd: fix wanting in print statement
"warning" in print statement. Fixed locally.
On Mon, Sep 21, 2020 at 5:20 PM Alex Deucher wrote:
>
> drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_crat.c: In function
> ‘kfd_create_crat_image_virtual’:
> drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_crat.c:1391:12: warning: format ‘%d’
> expects argument of type ‘int’, but argument 3 has type ‘size_t’ {aka ‘long
> unsigned int’} [-Wformat=]
> 1391 | pr_debug("CRAT size is %d", dyn_size);
> |^
> ./include/linux/printk.h:297:21: note: in definition of macro ‘pr_fmt’
> 297 | #define pr_fmt(fmt) fmt
> | ^~~
> ./include/linux/dynamic_debug.h:143:2: note: in expansion of macro
> ‘__dynamic_func_call’
> 143 | __dynamic_func_call(__UNIQUE_ID(ddebug), fmt, func, ##__VA_ARGS__)
> | ^~~
> ./include/linux/dynamic_debug.h:153:2: note: in expansion of macro
> ‘_dynamic_func_call’
> 153 | _dynamic_func_call(fmt, __dynamic_pr_debug, \
> | ^~
> ./include/linux/printk.h:420:2: note: in expansion of macro ‘dynamic_pr_debug’
> 420 | dynamic_pr_debug(fmt, ##__VA_ARGS__)
> | ^~~~
> drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_crat.c:1391:3: note: in expansion of
> macro ‘pr_debug’
> 1391 | pr_debug("CRAT size is %d", dyn_size);
> | ^~~~
> drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_crat.c:1391:27: note: format string
> is defined here
> 1391 | pr_debug("CRAT size is %d", dyn_size);
> | ~^
> | |
> | int
> | %ld
>
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
> b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
> index c50e9f634d6c..d2981524dba0 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
> @@ -1388,7 +1388,7 @@ int kfd_create_crat_image_virtual(void **crat_image,
> size_t *size,
> if (!pcrat_image)
> return -ENOMEM;
> *size = dyn_size;
> - pr_debug("CRAT size is %d", dyn_size);
> + pr_debug("CRAT size is %ld", dyn_size);
> ret = kfd_create_vcrat_image_cpu(pcrat_image, size);
> break;
> case COMPUTE_UNIT_GPU:
> --
> 2.25.4
>
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdkfd: fix wanting in print statement
drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_crat.c: In function
‘kfd_create_crat_image_virtual’:
drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_crat.c:1391:12: warning: format ‘%d’
expects argument of type ‘int’, but argument 3 has type ‘size_t’ {aka ‘long
unsigned int’} [-Wformat=]
1391 | pr_debug("CRAT size is %d", dyn_size);
|^
./include/linux/printk.h:297:21: note: in definition of macro ‘pr_fmt’
297 | #define pr_fmt(fmt) fmt
| ^~~
./include/linux/dynamic_debug.h:143:2: note: in expansion of macro
‘__dynamic_func_call’
143 | __dynamic_func_call(__UNIQUE_ID(ddebug), fmt, func, ##__VA_ARGS__)
| ^~~
./include/linux/dynamic_debug.h:153:2: note: in expansion of macro
‘_dynamic_func_call’
153 | _dynamic_func_call(fmt, __dynamic_pr_debug, \
| ^~
./include/linux/printk.h:420:2: note: in expansion of macro ‘dynamic_pr_debug’
420 | dynamic_pr_debug(fmt, ##__VA_ARGS__)
| ^~~~
drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_crat.c:1391:3: note: in expansion of
macro ‘pr_debug’
1391 | pr_debug("CRAT size is %d", dyn_size);
| ^~~~
drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_crat.c:1391:27: note: format string is
defined here
1391 | pr_debug("CRAT size is %d", dyn_size);
| ~^
| |
| int
| %ld
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
index c50e9f634d6c..d2981524dba0 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
@@ -1388,7 +1388,7 @@ int kfd_create_crat_image_virtual(void **crat_image,
size_t *size,
if (!pcrat_image)
return -ENOMEM;
*size = dyn_size;
- pr_debug("CRAT size is %d", dyn_size);
+ pr_debug("CRAT size is %ld", dyn_size);
ret = kfd_create_vcrat_image_cpu(pcrat_image, size);
break;
case COMPUTE_UNIT_GPU:
--
2.25.4
___
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH] drm/amdgpu: Fix L1 policy violations (PSP) on sienna cichlid SRIOV
[AMD Public Use]
Adding more reviewers to cc.
Rohit
-Original Message-
From: Khaire, Rohit
Sent: September 3, 2020 5:50 PM
To: amd-gfx@lists.freedesktop.org
Cc: Khaire, Rohit
Subject: [PATCH] drm/amdgpu: Fix L1 policy violations (PSP) on sienna cichlid
SRIOV
Signed-off-by: Rohit Khaire
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 49 --
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c | 64 +++-
drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 42
3 files changed, 95 insertions(+), 60 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index d502e30f67d9..4bafbd453e53 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4808,14 +4808,23 @@ static int gfx_v10_0_init_csb(struct amdgpu_device
*adev)
void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) {
- u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
+ u32 tmp;
+ /* For SRIOV, don't touch RLC_G */
+ if (amdgpu_sriov_vf(adev))
+ return;
+
+ tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
}
static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev) {
+ /* For SRIOV, don't touch RLC_G */
+ if (amdgpu_sriov_vf(adev))
+ return;
+
WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
udelay(50);
WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); @@ -4846,6
+4855,10 @@ static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device
*adev,
static void gfx_v10_0_rlc_start(struct amdgpu_device *adev) {
+ /* For SRIOV, don't touch RLC_G */
+ if (amdgpu_sriov_vf(adev))
+ return;
+
/* TODO: enable rlc & smu handshake until smu
* and gfxoff feature works as expected */
if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) @@ -4859,6 +4872,10 @@
static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev) {
uint32_t tmp;
+ /* For SRIOV, don't touch RLC_G */
+ if (amdgpu_sriov_vf(adev))
+ return;
+
/* enable Save Restore Machine */
tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
@@ -4872,6 +4889,10 @@ static int gfx_v10_0_rlc_load_microcode(struct
amdgpu_device *adev)
const __le32 *fw_data;
unsigned i, fw_size;
+ /* For SRIOV, don't touch RLC_G */
+ if (amdgpu_sriov_vf(adev))
+ return;
+
if (!adev->gfx.rlc_fw)
return -EINVAL;
@@ -4906,8 +4927,7 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device
*adev)
gfx_v10_0_init_csb(adev);
- if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
- gfx_v10_0_rlc_enable_srm(adev);
+ gfx_v10_0_rlc_enable_srm(adev);
} else {
if (amdgpu_sriov_vf(adev)) {
gfx_v10_0_init_csb(adev);
@@ -6990,7 +7010,6 @@ static int gfx_v10_0_hw_fini(void *handle)
if (amdgpu_gfx_disable_kcq(adev))
DRM_ERROR("KCQ disable failed\n");
if (amdgpu_sriov_vf(adev)) {
- gfx_v10_0_cp_gfx_enable(adev, false);
/* Program KIQ position of RLC_CP_SCHEDULERS during destroy */
tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
tmp &= 0xff00;
@@ -7272,6 +7291,10 @@ static void
gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *ade {
uint32_t data, def;
+ /* For SRIOV, guest VM should not touch CGCG and PG stuff */
+ if (amdgpu_sriov_vf(adev))
+ return;
+
/* It is disabled by HW by default */
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
/* 0 - Disable some blocks' MGCG */
@@ -7339,6 +7362,10 @@ static void gfx_v10_0_update_3d_clock_gating(struct
amdgpu_device *adev, {
uint32_t data, def;
+ /* For SRIOV, guest VM should not touch CGCG and PG stuff */
+ if (amdgpu_sriov_vf(adev))
+ return;
+
/* Enable 3D CGCG/CGLS */
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
/* write cmd to clear cgcg/cgls ov */ @@ -7381,6 +7408,10 @@
static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device
*ade {
uint32_t def, data;
+ /* For SRIOV, guest VM should not touch CGCG and PG stuff */
+ if (amdgpu_sriov_vf(adev))
+ return;
+
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
/* unset CGCG override */
@@ -7422,6 +7453,10 @@ static void
gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade static
int
[PATCH] drm/amdgpu: Fix SDMA RAP violations on Sienna Cichlid SRIOV
Signed-off-by: Rohit Khaire
---
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 128 ++---
1 file changed, 70 insertions(+), 58 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
index 34ccf376ee45..6fb5588fc0b6 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
@@ -541,7 +541,9 @@ static void sdma_v5_2_ctx_switch_enable(struct
amdgpu_device *adev, bool enable)
WREG32(sdma_v5_2_get_reg_offset(adev, i,
mmSDMA0_PHASE2_QUANTUM),
phase_quantum);
}
- WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL),
f32_cntl);
+ if (!amdgpu_sriov_vf(adev))
+ WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL),
+ f32_cntl);
}
}
@@ -559,6 +561,9 @@ static void sdma_v5_2_enable(struct amdgpu_device *adev,
bool enable)
u32 f32_cntl;
int i;
+ if (amdgpu_sriov_vf(adev))
+ return;
+
if (!enable) {
sdma_v5_2_gfx_stop(adev);
sdma_v5_2_rlc_stop(adev);
@@ -596,7 +601,9 @@ static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev)
ring = >sdma.instance[i].ring;
wb_offset = (ring->rptr_offs * 4);
- WREG32(sdma_v5_2_get_reg_offset(adev, i,
mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
+ if (!amdgpu_sriov_vf(adev))
+ WREG32(sdma_v5_2_get_reg_offset(adev, i,
+ mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
/* Set ring buffer size in dwords */
rb_bufsz = order_base_2(ring->ring_size / 4);
@@ -621,13 +628,16 @@ static int sdma_v5_2_gfx_resume(struct amdgpu_device
*adev)
lower_32_bits(wptr_gpu_addr));
WREG32(sdma_v5_2_get_reg_offset(adev, i,
mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
upper_32_bits(wptr_gpu_addr));
- wptr_poll_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i,
-
mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
- wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
- SDMA0_GFX_RB_WPTR_POLL_CNTL,
- F32_POLL_ENABLE, 1);
- WREG32(sdma_v5_2_get_reg_offset(adev, i,
mmSDMA0_GFX_RB_WPTR_POLL_CNTL),
- wptr_poll_cntl);
+
+ if (!amdgpu_sriov_vf(adev)) {
+ wptr_poll_cntl = RREG32(sdma_v5_2_get_reg_offset(
+ adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
+ wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
+ SDMA0_GFX_RB_WPTR_POLL_CNTL,
+ F32_POLL_ENABLE, 1);
+ WREG32(sdma_v5_2_get_reg_offset(adev, i,
+ mmSDMA0_GFX_RB_WPTR_POLL_CNTL), wptr_poll_cntl);
+ }
/* set the wb address whether it's enabled or not */
WREG32(sdma_v5_2_get_reg_offset(adev, i,
mmSDMA0_GFX_RB_RPTR_ADDR_HI),
@@ -673,30 +683,40 @@ static int sdma_v5_2_gfx_resume(struct amdgpu_device
*adev)
/* set minor_ptr_update to 0 after wptr programed */
WREG32(sdma_v5_2_get_reg_offset(adev, i,
mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
- /* set utc l1 enable flag always to 1 */
- temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
- temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
-
- /* enable MCBP */
- temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE,
1);
- WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
-
- /* Set up RESP_MODE to non-copy addresses */
- temp = RREG32(sdma_v5_2_get_reg_offset(adev, i,
mmSDMA0_UTCL1_CNTL));
- temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
- temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
- WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL),
temp);
-
- /* program default cache read and write policy */
- temp = RREG32(sdma_v5_2_get_reg_offset(adev, i,
mmSDMA0_UTCL1_PAGE));
- /* clean read policy and write policy bits */
- temp &= 0xFF0FFF;
- temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) |
-(CACHE_WRITE_POLICY_L2__DEFAULT << 14) |
-0x0100);
- WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE),
temp);
-
if (!amdgpu_sriov_vf(adev)) {
+ /* set utc l1 enable flag always to 1 */
+ temp =
[PATCH] drm/amdgpu: Workaround RCC_DEV0_EPF0_STRAP0 access issue for SRIOV
Signed-off-by: Rohit Khaire
---
drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
index 7429f30398b9..4f611cd68940 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
@@ -51,8 +51,19 @@ static void nbio_v2_3_remap_hdp_registers(struct
amdgpu_device *adev)
static u32 nbio_v2_3_get_rev_id(struct amdgpu_device *adev)
{
- u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
+ u32 tmp;
+
+ if (amdgpu_sriov_vf(adev)) {
+ /* workaround on rev_id for sriov
+* guest vm gets 0x when reading RCC_DEV0_EPF0_STRAP0,
+* as a consequence, the rev_id and external_rev_id are wrong.
+*
+* workaround it by using PCI revision id.
+*/
+ return adev->pdev->revision;
+ }
+ tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
--
2.17.1
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[PATCH] drm/amdgpu: Workaround RCC_DEV0_EPF0_STRAP0 access issue for SRIOV
Signed-off-by: Rohit Khaire
---
drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
index 7429f30398b9..78cb48bafa4c 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
@@ -51,8 +51,20 @@ static void nbio_v2_3_remap_hdp_registers(struct
amdgpu_device *adev)
static u32 nbio_v2_3_get_rev_id(struct amdgpu_device *adev)
{
- u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
+ u32 tmp;
+
+ if (amdgpu_sriov_vf(adev)) {
+ /* workaround on rev_id for sriov
+* guest vm gets 0x when reading RCC_DEV0_EPF0_STRAP0,
+* as a consequence, the rev_id and external_rev_id are wrong.
+*
+* workaround it by hardcoding the rev_id to 0,
+*(which is the default value)
+*/
+ return adev->pdev->revision;
+ }
+ tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
--
2.17.1
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RE: [PATCH] drm/amdgpu: Workaround RCC_DEV0_EPF0_STRAP0 access issue for SRIOV
[AMD Public Use]
Hi Alex,
I discussed this with my team, we are fine with PCI_REVISION_ID for SRIOV.
I am resending my patch with the change you suggested.
Thanks
Rohit
-Original Message-
From: Alex Deucher
Sent: September 14, 2020 1:16 AM
To: Khaire, Rohit
Cc: amd-gfx list
Subject: Re: [PATCH] drm/amdgpu: Workaround RCC_DEV0_EPF0_STRAP0 access issue
for SRIOV
On Fri, Sep 11, 2020 at 6:03 PM Rohit Khaire wrote:
>
> Signed-off-by: Rohit Khaire
> ---
> drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c | 14 +-
> 1 file changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
> b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
> index 7429f30398b9..fdfa075e6d5a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
> @@ -51,8 +51,20 @@ static void nbio_v2_3_remap_hdp_registers(struct
> amdgpu_device *adev)
>
> static u32 nbio_v2_3_get_rev_id(struct amdgpu_device *adev) {
> - u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
> + u32 tmp;
>
> + /*
> +* On SRIOV VF RCC_DEV0_EPF0_STRAP is blocked.
> +* So we read rev_id from PCI config space.
> +*/
> + if (amdgpu_sriov_vf(adev)) {
> + pci_read_config_dword(adev->pdev, PCI_REVISION_ID, );
This is not going to do what you want. The pci revision id is not the
same as the ati rev id. If you actually want the pci revision id, we
already have it in adev->pdev->revision, no need to fetch it directly.
Alex
> + /* Revision ID is the least significant 8 bits */
> + tmp &= 0xFF;
> + return tmp;
> + }
> +
> + tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
> tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
> tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
>
> --
> 2.17.1
>
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Re: [PATCH v1 ] drm/amd/pm: Removed fixed clock in auto mode DPM
Applied with fixed up whitespace.
Thanks,
Alex
On Tue, Sep 15, 2020 at 3:45 AM Christian König
wrote:
>
> Am 15.09.20 um 09:18 schrieb Sudheesh Mavila:
> > SMU10_UMD_PSTATE_PEAK_FCLK value should not be used to set the DPM.
> >
> > Change suggested by evan.q...@amd.com
>
> Can't say much about the change itself, but the Commit message is
> indented and the indentation in the code doesn't look consistent either.
>
> Christian.
>
> >
> > Signed-off-by: Sudheesh Mavila
> > ---
> > drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 10 ++
> > 1 file changed, 6 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> > b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> > index c9cfe90a2947..081cb9b1b7c8 100644
> > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> > +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> > @@ -566,6 +566,8 @@ static int smu10_dpm_force_dpm_level(struct pp_hwmgr
> > *hwmgr,
> > struct smu10_hwmgr *data = hwmgr->backend;
> > uint32_t min_sclk = hwmgr->display_config->min_core_set_clock;
> > uint32_t min_mclk = hwmgr->display_config->min_mem_set_clock/100;
> > + uint32_t index_fclk = data->clock_vol_info.vdd_dep_on_fclk->count - 1;
> > + uint32_t index_socclk = data->clock_vol_info.vdd_dep_on_socclk->count
> > - 1;
> >
> > if (hwmgr->smu_version < 0x1E3700) {
> > pr_info("smu firmware version too old, can not set dpm
> > level\n");
> > @@ -679,13 +681,13 @@ static int smu10_dpm_force_dpm_level(struct pp_hwmgr
> > *hwmgr,
> > smum_send_msg_to_smc_with_parameter(hwmgr,
> >
> > PPSMC_MSG_SetHardMinFclkByFreq,
> >
> > hwmgr->display_config->num_display > 3 ?
> > - SMU10_UMD_PSTATE_PEAK_FCLK :
> > +
> > data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk :
> > min_mclk,
> > NULL);
> >
> > smum_send_msg_to_smc_with_parameter(hwmgr,
> >
> > PPSMC_MSG_SetHardMinSocclkByFreq,
> > - SMU10_UMD_PSTATE_MIN_SOCCLK,
> > +
> > data->clock_vol_info.vdd_dep_on_socclk->entries[0].clk,
> > NULL);
> > smum_send_msg_to_smc_with_parameter(hwmgr,
> > PPSMC_MSG_SetHardMinVcn,
> > @@ -698,11 +700,11 @@ static int smu10_dpm_force_dpm_level(struct pp_hwmgr
> > *hwmgr,
> > NULL);
> > smum_send_msg_to_smc_with_parameter(hwmgr,
> >
> > PPSMC_MSG_SetSoftMaxFclkByFreq,
> > - SMU10_UMD_PSTATE_PEAK_FCLK,
> > +
> > data->clock_vol_info.vdd_dep_on_fclk->entries[index_fclk].clk,
> > NULL);
> > smum_send_msg_to_smc_with_parameter(hwmgr,
> >
> > PPSMC_MSG_SetSoftMaxSocclkByFreq,
> > - SMU10_UMD_PSTATE_PEAK_SOCCLK,
> > +
> > data->clock_vol_info.vdd_dep_on_socclk->entries[index_socclk].clk,
> > NULL);
> > smum_send_msg_to_smc_with_parameter(hwmgr,
> > PPSMC_MSG_SetSoftMaxVcn,
>
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RE: [PATCH] drm/amdgpu: Add uid info to process BO list
[AMD Public Use] -Original Message- From: Christian König Sent: Tuesday, September 22, 2020 12:54 AM To: Chauhan, Madhav ; amd-gfx@lists.freedesktop.org Cc: Surampalli, Kishore ; Patel, Mihir ; Sharma, Shashank ; Deucher, Alexander ; Saleem, Athar Subject: Re: [PATCH] drm/amdgpu: Add uid info to process BO list Am 21.09.20 um 21:18 schrieb Madhav Chauhan: > UID is helpful while doing analysis of BO allocated by a process. Looks like a bit overkill to me, why not get the uid from the process info? Not sure if I got your point , but used the similar method implemented at drm level inside drm_debugfs.c. Thanks Regards, Madhav Christian. > > Signed-off-by: Madhav Chauhan > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 6 +- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c > index f4c2e2e75b8f..c1982349ec7b 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c > @@ -892,6 +892,7 @@ static int amdgpu_debugfs_gem_info(struct seq_file *m, > void *data) > struct drm_info_node *node = (struct drm_info_node *)m->private; > struct drm_device *dev = node->minor->dev; > struct drm_file *file; > + kuid_t uid; > int r; > > r = mutex_lock_interruptible(>filelist_mutex); > @@ -909,7 +910,10 @@ static int amdgpu_debugfs_gem_info(struct seq_file *m, > void *data) >*/ > rcu_read_lock(); > task = pid_task(file->pid, PIDTYPE_PID); > - seq_printf(m, "pid %8d command %s:\n", pid_nr(file->pid), > + uid = task ? __task_cred(task)->euid : GLOBAL_ROOT_UID; > + seq_printf(m, "pid %8d uid %5d command %s:\n", > +pid_nr(file->pid), > +from_kuid_munged(seq_user_ns(m), uid), > task ? task->comm : ""); > rcu_read_unlock(); > ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amd/display: optimize code runtime a bit
On Mon, Sep 21, 2020 at 9:14 AM Bernard Zhao wrote:
>
> Static function dal_ddc_i2c_payloads_destroy is only called
> in dal_ddc_service_query_ddc_data, the parameter is
> , there is no point NULL risk, so no need to check.
> This change is to make the code run a bit fast.
>
How about just getting rid of dal_ddc_i2c_payloads_destroy() and just
call dal_vector_destruct() directly.
Alex
> Signed-off-by: Bernard Zhao
> ---
> drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c | 3 ---
> 1 file changed, 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
> b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
> index b984eecca58b..6dcc666738fc 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
> @@ -150,9 +150,6 @@ static uint32_t dal_ddc_i2c_payloads_get_count(struct
> i2c_payloads *p)
>
> static void dal_ddc_i2c_payloads_destroy(struct i2c_payloads *p)
> {
> - if (!p)
> - return;
> -
> dal_vector_destruct(>payloads);
> }
>
> --
> 2.28.0
>
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Re: [PATCH -next] drm/amdgpu/gmc9: simplify the return expression of gmc_v9_0_suspend
Applied. Thanks!
Alex
On Mon, Sep 21, 2020 at 9:14 AM Liu Shixin wrote:
>
> Simplify the return expression.
>
> Signed-off-by: Liu Shixin
> ---
> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 7 +--
> 1 file changed, 1 insertion(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index 5400cac02087..cb9e9e5afa5a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -1683,14 +1683,9 @@ static int gmc_v9_0_hw_fini(void *handle)
>
> static int gmc_v9_0_suspend(void *handle)
> {
> - int r;
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> - r = gmc_v9_0_hw_fini(adev);
> - if (r)
> - return r;
> -
> - return 0;
> + return gmc_v9_0_hw_fini(adev);
> }
>
> static int gmc_v9_0_resume(void *handle)
> --
> 2.25.1
>
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Re: [PATCH -next] drm/amd/pm: simplify the return expression of smu_hw_fini
Applied. Thanks!
Alex
On Mon, Sep 21, 2020 at 9:14 AM Liu Shixin wrote:
>
> Simplify the return expression.
>
> Signed-off-by: Liu Shixin
> ---
> drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 7 +--
> 1 file changed, 1 insertion(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> index 5c4b74f964fc..3612841d40dc 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> @@ -1214,7 +1214,6 @@ static int smu_hw_fini(void *handle)
> {
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> struct smu_context *smu = >smu;
> - int ret = 0;
>
> if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
> return 0;
> @@ -1230,11 +1229,7 @@ static int smu_hw_fini(void *handle)
>
> adev->pm.dpm_enabled = false;
>
> - ret = smu_smc_hw_cleanup(smu);
> - if (ret)
> - return ret;
> -
> - return 0;
> + return smu_smc_hw_cleanup(smu);
> }
>
> int smu_reset(struct smu_context *smu)
> --
> 2.25.1
>
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Re: [PATCH -next] drm/amdgpu: simplify the return expression
Applied. Thanks!
Alex
On Mon, Sep 21, 2020 at 9:14 AM Qinglang Miao wrote:
>
> Simplify the return expression.
>
> Signed-off-by: Qinglang Miao
> ---
> drivers/gpu/drm/amd/amdgpu/cik_ih.c | 7 +--
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 10 ++
> 2 files changed, 3 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> index 401c99f0b..db953e95f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> @@ -316,14 +316,9 @@ static int cik_ih_sw_fini(void *handle)
>
> static int cik_ih_hw_init(void *handle)
> {
> - int r;
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> - r = cik_ih_irq_init(adev);
> - if (r)
> - return r;
> -
> - return 0;
> + return cik_ih_irq_init(adev);
> }
>
> static int cik_ih_hw_fini(void *handle)
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 20d8a03ca..56ed108b2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -2198,7 +2198,6 @@ static int gfx_v9_0_gpu_early_init(struct amdgpu_device
> *adev)
> static int gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int
> ring_id,
> int mec, int pipe, int queue)
> {
> - int r;
> unsigned irq_type;
> struct amdgpu_ring *ring = >gfx.compute_ring[ring_id];
> unsigned int hw_prio;
> @@ -2223,13 +,8 @@ static int gfx_v9_0_compute_ring_init(struct
> amdgpu_device *adev, int ring_id,
> hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev,
> ring->queue) ?
> AMDGPU_GFX_PIPE_PRIO_HIGH :
> AMDGPU_GFX_PIPE_PRIO_NORMAL;
> /* type-2 packets are deprecated on MEC, use type-3 instead */
> - r = amdgpu_ring_init(adev, ring, 1024,
> ->gfx.eop_irq, irq_type, hw_prio);
> - if (r)
> - return r;
> -
> -
> - return 0;
> + return amdgpu_ring_init(adev, ring, 1024,
> + >gfx.eop_irq, irq_type, hw_prio);
> }
>
> static int gfx_v9_0_sw_init(void *handle)
> --
> 2.23.0
>
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Re: [PATCH -next] drm/amdgpu/mes: simplify the return expression of mes_v10_1_ring_init
Applied. Thanks!
Alex
On Mon, Sep 21, 2020 at 9:14 AM Qinglang Miao wrote:
>
> Simplify the return expression.
>
> Signed-off-by: Qinglang Miao
> ---
> drivers/gpu/drm/amd/amdgpu/mes_v10_1.c | 7 +--
> 1 file changed, 1 insertion(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
> b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
> index 4b746584a..1c22d8393 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
> @@ -832,7 +832,6 @@ static int mes_v10_1_queue_init(struct amdgpu_device
> *adev)
> static int mes_v10_1_ring_init(struct amdgpu_device *adev)
> {
> struct amdgpu_ring *ring;
> - int r;
>
> ring = >mes.ring;
>
> @@ -849,11 +848,7 @@ static int mes_v10_1_ring_init(struct amdgpu_device
> *adev)
> ring->no_scheduler = true;
> sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe,
> ring->queue);
>
> - r = amdgpu_ring_init(adev, ring, 1024, NULL, 0,
> AMDGPU_RING_PRIO_DEFAULT);
> - if (r)
> - return r;
> -
> - return 0;
> + return amdgpu_ring_init(adev, ring, 1024, NULL, 0,
> AMDGPU_RING_PRIO_DEFAULT);
> }
>
> static int mes_v10_1_mqd_sw_init(struct amdgpu_device *adev)
> --
> 2.23.0
>
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Re: [PATCH] drm/amdgpu: Add uid info to process BO list
Am 21.09.20 um 21:18 schrieb Madhav Chauhan: UID is helpful while doing analysis of BO allocated by a process. Looks like a bit overkill to me, why not get the uid from the process info? Christian. Signed-off-by: Madhav Chauhan --- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index f4c2e2e75b8f..c1982349ec7b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -892,6 +892,7 @@ static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data) struct drm_info_node *node = (struct drm_info_node *)m->private; struct drm_device *dev = node->minor->dev; struct drm_file *file; + kuid_t uid; int r; r = mutex_lock_interruptible(>filelist_mutex); @@ -909,7 +910,10 @@ static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data) */ rcu_read_lock(); task = pid_task(file->pid, PIDTYPE_PID); - seq_printf(m, "pid %8d command %s:\n", pid_nr(file->pid), + uid = task ? __task_cred(task)->euid : GLOBAL_ROOT_UID; + seq_printf(m, "pid %8d uid %5d command %s:\n", + pid_nr(file->pid), + from_kuid_munged(seq_user_ns(m), uid), task ? task->comm : ""); rcu_read_unlock(); ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: Add uid info to process BO list
UID is helpful while doing analysis of BO allocated by a process. Signed-off-by: Madhav Chauhan --- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index f4c2e2e75b8f..c1982349ec7b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -892,6 +892,7 @@ static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data) struct drm_info_node *node = (struct drm_info_node *)m->private; struct drm_device *dev = node->minor->dev; struct drm_file *file; + kuid_t uid; int r; r = mutex_lock_interruptible(>filelist_mutex); @@ -909,7 +910,10 @@ static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data) */ rcu_read_lock(); task = pid_task(file->pid, PIDTYPE_PID); - seq_printf(m, "pid %8d command %s:\n", pid_nr(file->pid), + uid = task ? __task_cred(task)->euid : GLOBAL_ROOT_UID; + seq_printf(m, "pid %8d uid %5d command %s:\n", + pid_nr(file->pid), + from_kuid_munged(seq_user_ns(m), uid), task ? task->comm : ""); rcu_read_unlock(); -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amd/pm: correct the pmfw version check for Navi14
[AMD Public Use]
Reviewed-by: Alex Deucher
From: Quan, Evan
Sent: Sunday, September 20, 2020 10:47 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Quan, Evan
Subject: [PATCH] drm/amd/pm: correct the pmfw version check for Navi14
Otherwise, that will be always true for Navi14.
Change-Id: Ief94150d10e4987e405d97674d9ae4efe89246fb
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index e729337e84d0..b9e522ed499a 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -2279,13 +2279,14 @@ static int navi10_run_umc_cdr_workaround(struct
smu_context *smu)
}
/*
-* The messages below are only supported by 42.53.0 and later
-* PMFWs.
+* The messages below are only supported by Navi10 42.53.0 and later
+* PMFWs and Navi14 53.29.0 and later PMFWs.
* - PPSMC_MSG_SetDriverDummyTableDramAddrHigh
* - PPSMC_MSG_SetDriverDummyTableDramAddrLow
* - PPSMC_MSG_GetUMCFWWA
*/
- if (pmfw_version >= 0x2a3500) {
+ if (((adev->asic_type == CHIP_NAVI10) && (pmfw_version >= 0x2a3500)) ||
+ ((adev->asic_type == CHIP_NAVI14) && (pmfw_version >= 0x351D00))) {
ret = smu_cmn_send_smc_msg_with_param(smu,
SMU_MSG_GET_UMC_FW_WA,
0,
--
2.28.0
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Re: [PATCH 2/2] drm/amd/pm: drop redundant watermarks bitmap setting
[AMD Public Use]
Series is:
Reviewed-by: Alex Deucher
From: Quan, Evan
Sent: Sunday, September 20, 2020 10:49 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Quan, Evan
Subject: [PATCH 2/2] drm/amd/pm: drop redundant watermarks bitmap setting
As this is already set inside the implementation of
smu_set_watermarks_table().
Change-Id: I4d4d40855f0aad43f6d21d471b64f1c7e696f0e7
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 002bae81b856..ef10be599d37 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -1838,11 +1838,6 @@ int smu_set_watermarks_for_clock_ranges(struct
smu_context *smu,
ret = smu_set_watermarks_table(smu, clock_ranges);
- if (!(smu->watermarks_bitmap & WATERMARKS_EXIST)) {
- smu->watermarks_bitmap |= WATERMARKS_EXIST;
- smu->watermarks_bitmap &= ~WATERMARKS_LOADED;
- }
-
mutex_unlock(>mutex);
return ret;
--
2.28.0
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Re: XDC 2020 feedback and comments
On Mon, 21 Sep 2020 10:03:32 +0200 Samuel Iglesias Gonsálvez wrote: > Hi all, > > Huge thanks again to the entire team from Intel, for their great work > organizing XDC 2020, our first virtual conference! > > As usual we're looking for feedback on both XDC itself, and the CFP > process and program selection. Both about what was great and should be > kept for next year's edition, and where there's room for improvement. > > The board does keep some notes, for those interested in what we have > already: > > - XDC notes for prospective organizers: > https://www.x.org/wiki/Events/RFP/ > > - CFP notes: https://www.x.org/wiki/Events/PapersCommittee/ > > If you want to send in your comments in private, please send them to > the X.org Foundation board: bo...@foundation.x.org > > Cheers, > > Sam Hi Sam, I'd like to make a note about using some more privacy-friendly streaming platform. When I tried to watch the streams, instead of showing the video, youtube presented me with a GDPR dialog. While it was glitched and unskippable for me, just the fact that Google made it non-optional shows their disregard for my privacy (and, IMO, the letter of law, which mandates opt-in). Unfortunately, I wasn't able to evaluate the dialog's contents due to the glitch, but online reports suggest they are similarly ignorant. All in all, I only access youtube via youtube-dl any more, and that doesn't support streaming. When attending Akademy 2 weeks ago, they had a setup based on BigBlueButton that worked well without that sort of issues. Cheers, Dorota ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH v3] amdgpu: Add initial kernel documentation for the amd_ip_block_type structure
From: Ryan Taylor
Added IP block section to amdgpu.rst.
Added more documentation to amd_ip_funcs.
Created documentation for amd_ip_block_type.
v2: Provides a more detailed DOC section on IP blocks.
v3: Clarifies the IP block list. Adds info on IP block enumeration.
Signed-off-by: Ryan Taylor
Reviewed-by: Alex Deucher
---
Documentation/gpu/amdgpu.rst | 9 +++
drivers/gpu/drm/amd/include/amd_shared.h | 87 +---
2 files changed, 71 insertions(+), 25 deletions(-)
diff --git a/Documentation/gpu/amdgpu.rst b/Documentation/gpu/amdgpu.rst
index 29ca5f5feb35..57047dcb8d19 100644
--- a/Documentation/gpu/amdgpu.rst
+++ b/Documentation/gpu/amdgpu.rst
@@ -70,6 +70,15 @@ Interrupt Handling
.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
:internal:
+IP Blocks
+--
+
+.. kernel-doc:: drivers/gpu/drm/amd/include/amd_shared.h
+ :doc: IP Blocks
+
+.. kernel-doc:: drivers/gpu/drm/amd/include/amd_shared.h
+ :identifiers: amd_ip_block_type amd_ip_funcs
+
AMDGPU XGMI Support
===
diff --git a/drivers/gpu/drm/amd/include/amd_shared.h
b/drivers/gpu/drm/amd/include/amd_shared.h
index e98c84ef206f..6b8a40051f41 100644
--- a/drivers/gpu/drm/amd/include/amd_shared.h
+++ b/drivers/gpu/drm/amd/include/amd_shared.h
@@ -47,6 +47,40 @@ enum amd_apu_flags {
AMD_APU_IS_RENOIR = 0x0008UL,
};
+/**
+* DOC: IP Blocks
+*
+* GPUs are composed of IP (intellectual property) blocks. These
+* IP blocks provide various functionalities: display, graphics,
+* video decode, etc. The IP blocks that comprise a particular GPU
+* are listed in the GPU's respective SoC file. amdgpu_device.c
+* acquires the list of IP blocks for the GPU in use on initialization.
+* It can then operate on this list to perform standard driver operations
+* such as: init, fini, suspend, resume, etc.
+*
+*
+* IP block implementations are named using the following convention:
+* _v (E.g.: gfx_v6_0).
+*/
+
+/**
+* enum amd_ip_block_type - Used to classify IP blocks by functionality.
+*
+* @AMD_IP_BLOCK_TYPE_COMMON: GPU Family
+* @AMD_IP_BLOCK_TYPE_GMC: Graphics Memory Controller
+* @AMD_IP_BLOCK_TYPE_IH: Interrupt Handler
+* @AMD_IP_BLOCK_TYPE_SMC: System Management Controller
+* @AMD_IP_BLOCK_TYPE_PSP: Platform Security Processor
+* @AMD_IP_BLOCK_TYPE_DCE: Display and Compositing Engine
+* @AMD_IP_BLOCK_TYPE_GFX: Graphics and Compute Engine
+* @AMD_IP_BLOCK_TYPE_SDMA: System DMA Engine
+* @AMD_IP_BLOCK_TYPE_UVD: Unified Video Decoder
+* @AMD_IP_BLOCK_TYPE_VCE: Video Compression Engine
+* @AMD_IP_BLOCK_TYPE_ACP: Audio Co-Processor
+* @AMD_IP_BLOCK_TYPE_VCN: Video Core/Codec Next
+* @AMD_IP_BLOCK_TYPE_MES: Micro-Engine Scheduler
+* @AMD_IP_BLOCK_TYPE_JPEG: JPEG Engine
+*/
enum amd_ip_block_type {
AMD_IP_BLOCK_TYPE_COMMON,
AMD_IP_BLOCK_TYPE_GMC,
@@ -165,56 +199,59 @@ enum DC_DEBUG_MASK {
};
enum amd_dpm_forced_level;
+
/**
* struct amd_ip_funcs - general hooks for managing amdgpu IP Blocks
+ * @name: Name of IP block
+ * @early_init: sets up early driver state (pre sw_init),
+ * does not configure hw - Optional
+ * @late_init: sets up late driver/hw state (post hw_init) - Optional
+ * @sw_init: sets up driver state, does not configure hw
+ * @sw_fini: tears down driver state, does not configure hw
+ * @hw_init: sets up the hw state
+ * @hw_fini: tears down the hw state
+ * @late_fini: final cleanup
+ * @suspend: handles IP specific hw/sw changes for suspend
+ * @resume: handles IP specific hw/sw changes for resume
+ * @is_idle: returns current IP block idle status
+ * @wait_for_idle: poll for idle
+ * @check_soft_reset: check soft reset the IP block
+ * @pre_soft_reset: pre soft reset the IP block
+ * @soft_reset: soft reset the IP block
+ * @post_soft_reset: post soft reset the IP block
+ * @set_clockgating_state: enable/disable cg for the IP block
+ * @set_powergating_state: enable/disable pg for the IP block
+ * @get_clockgating_state: get current clockgating status
+ * @enable_umd_pstate: enable UMD powerstate
+ *
+ * These hooks provide an interface for controlling the operational state
+ * of IP blocks. After acquiring a list of IP blocks for the GPU in use,
+ * the driver can make chip-wide state changes by walking this list and
+ * making calls to hooks from each IP block. This list is ordered to ensure
+ * that the driver initializes the IP blocks in a safe sequence.
*/
struct amd_ip_funcs {
- /** @name: Name of IP block */
char *name;
- /**
-* @early_init:
-*
-* sets up early driver state (pre sw_init),
-* does not configure hw - Optional
-*/
int (*early_init)(void *handle);
- /** @late_init: sets up late driver/hw state (post hw_init) - Optional
*/
int (*late_init)(void *handle);
- /** @sw_init: sets up driver state, does not configure hw */
int (*sw_init)(void *handle);
- /** @sw_fini: tears down driver state, does not
Re: [PATCH] drm/amdkfd: Use kvmalloc instead of kmalloc for VCRAT
[AMD Public Use] Reviewed-by: Alex Deucher From: amd-gfx on behalf of Kent Russell Sent: Monday, September 21, 2020 10:27 AM To: amd-gfx@lists.freedesktop.org Cc: Russell, Kent Subject: [PATCH] drm/amdkfd: Use kvmalloc instead of kmalloc for VCRAT Since we're dynamically allocating the CPU VCRAT, use kvmalloc in case the allocation size is huge. Signed-off-by: Kent Russell --- drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c index 99182b8e9152..c50e9f634d6c 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c @@ -797,7 +797,8 @@ int kfd_create_crat_image_acpi(void **crat_image, size_t *size) return -ENODATA; } - pcrat_image = kmemdup(crat_table, crat_table->length, GFP_KERNEL); + pcrat_image = kvmalloc(crat_table->length, GFP_KERNEL); + memcpy(pcrat_image, crat_table, crat_table->length); if (!pcrat_image) return -ENOMEM; @@ -1383,7 +1384,7 @@ int kfd_create_crat_image_virtual(void **crat_image, size_t *size, num_nodes * (sizeof(struct crat_subtype_computeunit) + sizeof(struct crat_subtype_memory) + (num_nodes - 1) * sizeof(struct crat_subtype_iolink)); - pcrat_image = kmalloc(dyn_size, GFP_KERNEL); + pcrat_image = kvmalloc(dyn_size, GFP_KERNEL); if (!pcrat_image) return -ENOMEM; *size = dyn_size; @@ -1393,7 +1394,7 @@ int kfd_create_crat_image_virtual(void **crat_image, size_t *size, case COMPUTE_UNIT_GPU: if (!kdev) return -EINVAL; - pcrat_image = kmalloc(VCRAT_SIZE_FOR_GPU, GFP_KERNEL); + pcrat_image = kvmalloc(VCRAT_SIZE_FOR_GPU, GFP_KERNEL); if (!pcrat_image) return -ENOMEM; *size = VCRAT_SIZE_FOR_GPU; @@ -1412,7 +1413,7 @@ int kfd_create_crat_image_virtual(void **crat_image, size_t *size, if (!ret) *crat_image = pcrat_image; else - kfree(pcrat_image); + kvfree(pcrat_image); return ret; } -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfxdata=02%7C01%7Calexander.deucher%40amd.com%7C2c0550686c55482e784108d85e3a79b9%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637362952855598708sdata=juwKVfB3gvGU5TkLKf9KYPdy90sgT80810dh91hpZSw%3Dreserved=0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH AUTOSEL 5.4 13/15] drm/amdgpu/dc: Require primary plane to be enabled whenever the CRTC is
On 2020-09-21 4:40 p.m., Sasha Levin wrote: From: Michel Dänzer [ Upstream commit 2f228aab21bbc74e90e267a721215ec8be51daf7 ] Don't check drm_crtc_state::active for this either, per its documentation in include/drm/drm_crtc.h: * Hence drivers must not consult @active in their various * _mode_config_funcs.atomic_check callback to reject an atomic * commit. atomic_remove_fb disables the CRTC as needed for disabling the primary plane. This prevents at least the following problems if the primary plane gets disabled (e.g. due to destroying the FB assigned to the primary plane, as happens e.g. with mutter in Wayland mode): * The legacy cursor ioctl returned EINVAL for a non-0 cursor FB ID (which enables the cursor plane). * If the cursor plane was enabled, changing the legacy DPMS property value from off to on returned EINVAL. v2: * Minor changes to code comment and commit log, per review feedback. GitLab: https://gitlab.gnome.org/GNOME/mutter/-/issues/1108 GitLab: https://gitlab.gnome.org/GNOME/mutter/-/issues/1165 GitLab: https://gitlab.gnome.org/GNOME/mutter/-/issues/1344 Suggested-by: Daniel Vetter Acked-by: Daniel Vetter Reviewed-by: Nicholas Kazlauskas Signed-off-by: Michel Dänzer Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin I'm a bit nervous about this getting backported so far back so quickly. I'd prefer waiting for 5.9 final first at least. -- Earthling Michel Dänzer | https://redhat.com Libre software enthusiast | Mesa and X developer ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH AUTOSEL 5.8 13/20] drm/amd/display: Don't use DRM_ERROR() for DTM add topology
From: Bhawanpreet Lakha
[ Upstream commit 4cdd7b332ed139b1e37faeb82409a14490adb644 ]
[Why]
Previously we were only calling add_topology when hdcp was being enabled.
Now we call add_topology by default so the ERROR messages are printed if
the firmware is not loaded.
This error message is not relevant for normal display functionality so
no need to print a ERROR message.
[How]
Change DRM_ERROR to DRM_INFO
Signed-off-by: Bhawanpreet Lakha
Acked-by: Aurabindo Pillai
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
index fb1161dd7ea80..3a367a5968ae1 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
@@ -88,7 +88,7 @@ enum mod_hdcp_status mod_hdcp_add_display_to_topology(struct
mod_hdcp *hdcp,
enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
if (!psp->dtm_context.dtm_initialized) {
- DRM_ERROR("Failed to add display topology, DTM TA is not
initialized.");
+ DRM_INFO("Failed to add display topology, DTM TA is not
initialized.");
display->state = MOD_HDCP_DISPLAY_INACTIVE;
return MOD_HDCP_STATUS_FAILURE;
}
--
2.25.1
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[PATCH AUTOSEL 5.8 12/20] drm/amdkfd: fix a memory leak issue
From: Dennis Li [ Upstream commit 087d764159996ae378b08c0fdd557537adfd6899 ] In the resume stage of GPU recovery, start_cpsch will call pm_init which set pm->allocated as false, cause the next pm_release_ib has no chance to release ib memory. Add pm_release_ib in stop_cpsch which will be called in the suspend stage of GPU recovery. Reviewed-by: Felix Kuehling Signed-off-by: Dennis Li Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin --- drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index e9c4867abeffb..00b042a15373a 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -1177,6 +1177,8 @@ static int stop_cpsch(struct device_queue_manager *dqm) dqm->sched_running = false; dqm_unlock(dqm); + pm_release_ib(>packets); + kfd_gtt_sa_free(dqm->dev, dqm->fence_mem); pm_uninit(>packets, hanging); -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH AUTOSEL 4.19 7/9] drm/amdkfd: fix a memory leak issue
From: Dennis Li [ Upstream commit 087d764159996ae378b08c0fdd557537adfd6899 ] In the resume stage of GPU recovery, start_cpsch will call pm_init which set pm->allocated as false, cause the next pm_release_ib has no chance to release ib memory. Add pm_release_ib in stop_cpsch which will be called in the suspend stage of GPU recovery. Reviewed-by: Felix Kuehling Signed-off-by: Dennis Li Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin --- drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index 189212cb35475..bff39f561264e 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -1101,6 +1101,8 @@ static int stop_cpsch(struct device_queue_manager *dqm) unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0); dqm_unlock(dqm); + pm_release_ib(>packets); + kfd_gtt_sa_free(dqm->dev, dqm->fence_mem); pm_uninit(>packets); -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH AUTOSEL 5.8 16/20] drm/amd/display: Don't log hdcp module warnings in dmesg
From: Bhawanpreet Lakha
[ Upstream commit 875d369d8f75275d30e59421602d9366426abff7 ]
[Why]
DTM topology updates happens by default now. This results in DTM
warnings when hdcp is not even being enabled. This spams the dmesg
and doesn't effect normal display functionality so it is better to log it
using DRM_DEBUG_KMS()
[How]
Change the DRM_WARN() to DRM_DEBUG_KMS()
Signed-off-by: Bhawanpreet Lakha
Acked-by: Alex Deucher
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.h
b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.h
index d3192b9d0c3d8..47f8ee2832ff0 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.h
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.h
@@ -27,7 +27,7 @@
#define MOD_HDCP_LOG_H_
#ifdef CONFIG_DRM_AMD_DC_HDCP
-#define HDCP_LOG_ERR(hdcp, ...) DRM_WARN(__VA_ARGS__)
+#define HDCP_LOG_ERR(hdcp, ...) DRM_DEBUG_KMS(__VA_ARGS__)
#define HDCP_LOG_VER(hdcp, ...) DRM_DEBUG_KMS(__VA_ARGS__)
#define HDCP_LOG_FSM(hdcp, ...) DRM_DEBUG_KMS(__VA_ARGS__)
#define HDCP_LOG_TOP(hdcp, ...) pr_debug("[HDCP_TOP]:"__VA_ARGS__)
--
2.25.1
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[PATCH AUTOSEL 5.4 11/15] drm/amdkfd: fix a memory leak issue
From: Dennis Li [ Upstream commit 087d764159996ae378b08c0fdd557537adfd6899 ] In the resume stage of GPU recovery, start_cpsch will call pm_init which set pm->allocated as false, cause the next pm_release_ib has no chance to release ib memory. Add pm_release_ib in stop_cpsch which will be called in the suspend stage of GPU recovery. Reviewed-by: Felix Kuehling Signed-off-by: Dennis Li Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin --- drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index a2ed9c257cb0d..e9a2784400792 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -1075,6 +1075,8 @@ static int stop_cpsch(struct device_queue_manager *dqm) unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0); dqm_unlock(dqm); + pm_release_ib(>packets); + kfd_gtt_sa_free(dqm->dev, dqm->fence_mem); pm_uninit(>packets); -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH AUTOSEL 5.8 14/20] drm/amd/display: update nv1x stutter latencies
From: Jun Lei
[ Upstream commit c4790a8894232f39c25c7c546c06efe074e63384 ]
[why]
Recent characterization shows increased stutter latencies on some SKUs,
leading to underflow.
[how]
Update SOC params to account for this worst case latency.
Signed-off-by: Jun Lei
Acked-by: Aurabindo Pillai
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 2d9055eb3ce92..20bdabebbc434 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -409,8 +409,8 @@ struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv14_soc = {
},
},
.num_states = 5,
- .sr_exit_time_us = 8.6,
- .sr_enter_plus_exit_time_us = 10.9,
+ .sr_exit_time_us = 11.6,
+ .sr_enter_plus_exit_time_us = 13.9,
.urgent_latency_us = 4.0,
.urgent_latency_pixel_data_only_us = 4.0,
.urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
--
2.25.1
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[PATCH AUTOSEL 5.4 13/15] drm/amdgpu/dc: Require primary plane to be enabled whenever the CRTC is
From: Michel Dänzer
[ Upstream commit 2f228aab21bbc74e90e267a721215ec8be51daf7 ]
Don't check drm_crtc_state::active for this either, per its
documentation in include/drm/drm_crtc.h:
* Hence drivers must not consult @active in their various
* _mode_config_funcs.atomic_check callback to reject an atomic
* commit.
atomic_remove_fb disables the CRTC as needed for disabling the primary
plane.
This prevents at least the following problems if the primary plane gets
disabled (e.g. due to destroying the FB assigned to the primary plane,
as happens e.g. with mutter in Wayland mode):
* The legacy cursor ioctl returned EINVAL for a non-0 cursor FB ID
(which enables the cursor plane).
* If the cursor plane was enabled, changing the legacy DPMS property
value from off to on returned EINVAL.
v2:
* Minor changes to code comment and commit log, per review feedback.
GitLab: https://gitlab.gnome.org/GNOME/mutter/-/issues/1108
GitLab: https://gitlab.gnome.org/GNOME/mutter/-/issues/1165
GitLab: https://gitlab.gnome.org/GNOME/mutter/-/issues/1344
Suggested-by: Daniel Vetter
Acked-by: Daniel Vetter
Reviewed-by: Nicholas Kazlauskas
Signed-off-by: Michel Dänzer
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 32 ++-
1 file changed, 10 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 60e50181f6d39..2384aa018993d 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4299,19 +4299,6 @@ static void dm_crtc_helper_disable(struct drm_crtc *crtc)
{
}
-static bool does_crtc_have_active_cursor(struct drm_crtc_state *new_crtc_state)
-{
- struct drm_device *dev = new_crtc_state->crtc->dev;
- struct drm_plane *plane;
-
- drm_for_each_plane_mask(plane, dev, new_crtc_state->plane_mask) {
- if (plane->type == DRM_PLANE_TYPE_CURSOR)
- return true;
- }
-
- return false;
-}
-
static int count_crtc_active_planes(struct drm_crtc_state *new_crtc_state)
{
struct drm_atomic_state *state = new_crtc_state->state;
@@ -4391,19 +4378,20 @@ static int dm_crtc_helper_atomic_check(struct drm_crtc
*crtc,
return ret;
}
- /* In some use cases, like reset, no stream is attached */
- if (!dm_crtc_state->stream)
- return 0;
-
/*
-* We want at least one hardware plane enabled to use
-* the stream with a cursor enabled.
+* We require the primary plane to be enabled whenever the CRTC is,
otherwise
+* drm_mode_cursor_universal may end up trying to enable the cursor
plane while all other
+* planes are disabled, which is not supported by the hardware. And
there is legacy
+* userspace which stops using the HW cursor altogether in response to
the resulting EINVAL.
*/
- if (state->enable && state->active &&
- does_crtc_have_active_cursor(state) &&
- dm_crtc_state->active_planes == 0)
+ if (state->enable &&
+ !(state->plane_mask & drm_plane_mask(crtc->primary)))
return -EINVAL;
+ /* In some use cases, like reset, no stream is attached */
+ if (!dm_crtc_state->stream)
+ return 0;
+
if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)
return 0;
--
2.25.1
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[PATCH AUTOSEL 5.8 15/20] drm/amdgpu/dc: Require primary plane to be enabled whenever the CRTC is
From: Michel Dänzer
[ Upstream commit 2f228aab21bbc74e90e267a721215ec8be51daf7 ]
Don't check drm_crtc_state::active for this either, per its
documentation in include/drm/drm_crtc.h:
* Hence drivers must not consult @active in their various
* _mode_config_funcs.atomic_check callback to reject an atomic
* commit.
atomic_remove_fb disables the CRTC as needed for disabling the primary
plane.
This prevents at least the following problems if the primary plane gets
disabled (e.g. due to destroying the FB assigned to the primary plane,
as happens e.g. with mutter in Wayland mode):
* The legacy cursor ioctl returned EINVAL for a non-0 cursor FB ID
(which enables the cursor plane).
* If the cursor plane was enabled, changing the legacy DPMS property
value from off to on returned EINVAL.
v2:
* Minor changes to code comment and commit log, per review feedback.
GitLab: https://gitlab.gnome.org/GNOME/mutter/-/issues/1108
GitLab: https://gitlab.gnome.org/GNOME/mutter/-/issues/1165
GitLab: https://gitlab.gnome.org/GNOME/mutter/-/issues/1344
Suggested-by: Daniel Vetter
Acked-by: Daniel Vetter
Reviewed-by: Nicholas Kazlauskas
Signed-off-by: Michel Dänzer
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 32 ++-
1 file changed, 10 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 3f7eced92c0c8..7c1cc0ba30a55 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -5257,19 +5257,6 @@ static void dm_crtc_helper_disable(struct drm_crtc *crtc)
{
}
-static bool does_crtc_have_active_cursor(struct drm_crtc_state *new_crtc_state)
-{
- struct drm_device *dev = new_crtc_state->crtc->dev;
- struct drm_plane *plane;
-
- drm_for_each_plane_mask(plane, dev, new_crtc_state->plane_mask) {
- if (plane->type == DRM_PLANE_TYPE_CURSOR)
- return true;
- }
-
- return false;
-}
-
static int count_crtc_active_planes(struct drm_crtc_state *new_crtc_state)
{
struct drm_atomic_state *state = new_crtc_state->state;
@@ -5349,19 +5336,20 @@ static int dm_crtc_helper_atomic_check(struct drm_crtc
*crtc,
return ret;
}
- /* In some use cases, like reset, no stream is attached */
- if (!dm_crtc_state->stream)
- return 0;
-
/*
-* We want at least one hardware plane enabled to use
-* the stream with a cursor enabled.
+* We require the primary plane to be enabled whenever the CRTC is,
otherwise
+* drm_mode_cursor_universal may end up trying to enable the cursor
plane while all other
+* planes are disabled, which is not supported by the hardware. And
there is legacy
+* userspace which stops using the HW cursor altogether in response to
the resulting EINVAL.
*/
- if (state->enable && state->active &&
- does_crtc_have_active_cursor(state) &&
- dm_crtc_state->active_planes == 0)
+ if (state->enable &&
+ !(state->plane_mask & drm_plane_mask(crtc->primary)))
return -EINVAL;
+ /* In some use cases, like reset, no stream is attached */
+ if (!dm_crtc_state->stream)
+ return 0;
+
if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)
return 0;
--
2.25.1
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[PATCH AUTOSEL 5.4 12/15] drm/amd/display: update nv1x stutter latencies
From: Jun Lei
[ Upstream commit c4790a8894232f39c25c7c546c06efe074e63384 ]
[why]
Recent characterization shows increased stutter latencies on some SKUs,
leading to underflow.
[how]
Update SOC params to account for this worst case latency.
Signed-off-by: Jun Lei
Acked-by: Aurabindo Pillai
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 05b98eadc2899..46afd048c1ea3 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -340,8 +340,8 @@ struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv14_soc = {
},
},
.num_states = 5,
- .sr_exit_time_us = 8.6,
- .sr_enter_plus_exit_time_us = 10.9,
+ .sr_exit_time_us = 11.6,
+ .sr_enter_plus_exit_time_us = 13.9,
.urgent_latency_us = 4.0,
.urgent_latency_pixel_data_only_us = 4.0,
.urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
--
2.25.1
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RE: [PATCH V4 1/1] drm/amdgpu: update athub interrupt harvesting handle
[AMD Public Use]
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: Stanley.Yang
Sent: Monday, September 21, 2020 21:48
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Chen, Guchun ;
Clements, John ; Li, Dennis ; Zhou1,
Tao ; Yang, Stanley
Subject: [PATCH V4 1/1] drm/amdgpu: update athub interrupt harvesting handle
GCEA/MMHUB EA error should not result to DF freeze, this is fixed in next
generation, but for some reasons the GCEA/MMHUB EA error will result to DF
freeze in previous generation, diver should avoid to indicate GCEA/MMHUB EA
error as hw fatal error in kernel message by read GCEA/MMHUB err status
registers.
Changed from V1:
make query_ras_error_status function more general
make read mmhub er status register more friendly
Changed from V2:
move ras error status query function into do_recovery workqueue
Changed from V3:
remove useless code from V2, print GCEA error status
instance number
Signed-off-by: Stanley.Yang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 43 ++-
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c | 29 +
drivers/gpu/drm/amd/amdgpu/gfx_v9_4.h | 2 +
drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c | 29 +
.../amd/include/asic_reg/gc/gc_9_4_1_offset.h | 4 +-
8 files changed, 108 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index a611e78dd4ba..258498cbf1eb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -217,6 +217,7 @@ struct amdgpu_gfx_funcs {
int (*query_ras_error_count) (struct amdgpu_device *adev, void
*ras_error_status);
void (*reset_ras_error_count) (struct amdgpu_device *adev);
void (*init_spm_golden)(struct amdgpu_device *adev);
+ void (*query_ras_error_status) (struct amdgpu_device *adev);
};
struct sq_work {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h
index 0c43d7fe893c..1ae9bdae7311 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h
@@ -40,6 +40,7 @@ struct amdgpu_mmhub_funcs {
uint64_t page_table_base);
void (*update_power_gating)(struct amdgpu_device *adev,
bool enable);
+ void (*query_ras_error_status)(struct amdgpu_device *adev);
};
struct amdgpu_mmhub {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index e5ea14774c0c..40614ac9a111 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -1498,6 +1498,45 @@ static void amdgpu_ras_log_on_err_counter(struct
amdgpu_device *adev)
}
}
+/* Parse RdRspStatus and WrRspStatus */ void
+amdgpu_ras_error_status_query(struct amdgpu_device *adev,
+ struct ras_query_if *info)
+{
+ /*
+* Only two block need to query read/write
+* RspStatus at current state
+*/
+ switch (info->head.block) {
+ case AMDGPU_RAS_BLOCK__GFX:
+ if (adev->gfx.funcs->query_ras_error_status)
+ adev->gfx.funcs->query_ras_error_status(adev);
+ break;
+ case AMDGPU_RAS_BLOCK__MMHUB:
+ if (adev->mmhub.funcs->query_ras_error_status)
+ adev->mmhub.funcs->query_ras_error_status(adev);
+ break;
+ default:
+ break;
+ }
+}
+
+static void amdgpu_ras_query_err_status(struct amdgpu_device *adev) {
+ struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
+ struct ras_manager *obj;
+
+ if (!con)
+ return;
+
+ list_for_each_entry(obj, >head, node) {
+ struct ras_query_if info = {
+ .head = obj->head,
+ };
+
+ amdgpu_ras_error_status_query(adev, );
+ }
+}
+
/* recovery begin */
/* return 0 on success.
@@ -1568,8 +1607,10 @@ static void amdgpu_ras_do_recovery(struct work_struct
*work)
}
list_for_each_entry(remote_adev,
- device_list_handle, gmc.xgmi.head)
+ device_list_handle, gmc.xgmi.head) {
+ amdgpu_ras_query_err_status(remote_adev);
amdgpu_ras_log_on_err_counter(remote_adev);
+ }
amdgpu_put_xgmi_hive(hive);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index d898c9ff3526..adee0177654e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -2075,6 +2075,7 @@ static const
Re: [Mesa-dev] XDC 2020 feedback and comments
First off, I think you all did a fantastic job. I felt that things ran very smoothly and, as far as the talks themselves go, I think it went almost as smoothly as an in-person XDC. I'm really quite impressed. I do have a couple pieces of more nuanced feedback: 1. I think we were maybe a bit too scared of overloading jitsi. Having more people in the instance for questions might have made that portion go better. As it was, there was only one or two talks that had any live questions. That said, there are a few advantages to having things funneled through IRC, the most obvious of which being that people can ask their question mid-talk and have it handled at the end instead of having to remember it for 20 minutes. 2. I really miss the hallway track. On Thursday, after the conference, Bas, Connor, and I used jitsi to have a chat about ray-tracing. That was really fun and I wish I'd done something like that every day of XDC. Maybe it's my own fault for not setting up said chats but I think it could have been made more accessible (I had no idea how to fork off a jitsi instance) and/or encouraged somehow. --Jason On Mon, Sep 21, 2020 at 3:07 AM Samuel Iglesias Gonsálvez wrote: > > Hi all, > > Huge thanks again to the entire team from Intel, for their great work > organizing XDC 2020, our first virtual conference! > > As usual we're looking for feedback on both XDC itself, and the CFP > process and program selection. Both about what was great and should be > kept for next year's edition, and where there's room for improvement. > > The board does keep some notes, for those interested in what we have > already: > > - XDC notes for prospective organizers: > https://www.x.org/wiki/Events/RFP/ > > - CFP notes: https://www.x.org/wiki/Events/PapersCommittee/ > > If you want to send in your comments in private, please send them to > the X.org Foundation board: bo...@foundation.x.org > > Cheers, > > Sam > ___ > mesa-dev mailing list > mesa-...@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/mesa-dev ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdkfd: Use kvmalloc instead of kmalloc for VCRAT
Since we're dynamically allocating the CPU VCRAT, use kvmalloc in case the allocation size is huge. Signed-off-by: Kent Russell --- drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c index 99182b8e9152..c50e9f634d6c 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c @@ -797,7 +797,8 @@ int kfd_create_crat_image_acpi(void **crat_image, size_t *size) return -ENODATA; } - pcrat_image = kmemdup(crat_table, crat_table->length, GFP_KERNEL); + pcrat_image = kvmalloc(crat_table->length, GFP_KERNEL); + memcpy(pcrat_image, crat_table, crat_table->length); if (!pcrat_image) return -ENOMEM; @@ -1383,7 +1384,7 @@ int kfd_create_crat_image_virtual(void **crat_image, size_t *size, num_nodes * (sizeof(struct crat_subtype_computeunit) + sizeof(struct crat_subtype_memory) + (num_nodes - 1) * sizeof(struct crat_subtype_iolink)); - pcrat_image = kmalloc(dyn_size, GFP_KERNEL); + pcrat_image = kvmalloc(dyn_size, GFP_KERNEL); if (!pcrat_image) return -ENOMEM; *size = dyn_size; @@ -1393,7 +1394,7 @@ int kfd_create_crat_image_virtual(void **crat_image, size_t *size, case COMPUTE_UNIT_GPU: if (!kdev) return -EINVAL; - pcrat_image = kmalloc(VCRAT_SIZE_FOR_GPU, GFP_KERNEL); + pcrat_image = kvmalloc(VCRAT_SIZE_FOR_GPU, GFP_KERNEL); if (!pcrat_image) return -ENOMEM; *size = VCRAT_SIZE_FOR_GPU; @@ -1412,7 +1413,7 @@ int kfd_create_crat_image_virtual(void **crat_image, size_t *size, if (!ret) *crat_image = pcrat_image; else - kfree(pcrat_image); + kvfree(pcrat_image); return ret; } -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH V4 1/1] drm/amdgpu: update athub interrupt harvesting handle
GCEA/MMHUB EA error should not result to DF freeze, this is
fixed in next generation, but for some reasons the GCEA/MMHUB
EA error will result to DF freeze in previous generation,
diver should avoid to indicate GCEA/MMHUB EA error as hw fatal
error in kernel message by read GCEA/MMHUB err status registers.
Changed from V1:
make query_ras_error_status function more general
make read mmhub er status register more friendly
Changed from V2:
move ras error status query function into do_recovery workqueue
Changed from V3:
remove useless code from V2, print GCEA error status
instance number
Signed-off-by: Stanley.Yang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 43 ++-
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c | 29 +
drivers/gpu/drm/amd/amdgpu/gfx_v9_4.h | 2 +
drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c | 29 +
.../amd/include/asic_reg/gc/gc_9_4_1_offset.h | 4 +-
8 files changed, 108 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index a611e78dd4ba..258498cbf1eb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -217,6 +217,7 @@ struct amdgpu_gfx_funcs {
int (*query_ras_error_count) (struct amdgpu_device *adev, void
*ras_error_status);
void (*reset_ras_error_count) (struct amdgpu_device *adev);
void (*init_spm_golden)(struct amdgpu_device *adev);
+ void (*query_ras_error_status) (struct amdgpu_device *adev);
};
struct sq_work {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h
index 0c43d7fe893c..1ae9bdae7311 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h
@@ -40,6 +40,7 @@ struct amdgpu_mmhub_funcs {
uint64_t page_table_base);
void (*update_power_gating)(struct amdgpu_device *adev,
bool enable);
+ void (*query_ras_error_status)(struct amdgpu_device *adev);
};
struct amdgpu_mmhub {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index e5ea14774c0c..40614ac9a111 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -1498,6 +1498,45 @@ static void amdgpu_ras_log_on_err_counter(struct
amdgpu_device *adev)
}
}
+/* Parse RdRspStatus and WrRspStatus */
+void amdgpu_ras_error_status_query(struct amdgpu_device *adev,
+ struct ras_query_if *info)
+{
+ /*
+* Only two block need to query read/write
+* RspStatus at current state
+*/
+ switch (info->head.block) {
+ case AMDGPU_RAS_BLOCK__GFX:
+ if (adev->gfx.funcs->query_ras_error_status)
+ adev->gfx.funcs->query_ras_error_status(adev);
+ break;
+ case AMDGPU_RAS_BLOCK__MMHUB:
+ if (adev->mmhub.funcs->query_ras_error_status)
+ adev->mmhub.funcs->query_ras_error_status(adev);
+ break;
+ default:
+ break;
+ }
+}
+
+static void amdgpu_ras_query_err_status(struct amdgpu_device *adev)
+{
+ struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
+ struct ras_manager *obj;
+
+ if (!con)
+ return;
+
+ list_for_each_entry(obj, >head, node) {
+ struct ras_query_if info = {
+ .head = obj->head,
+ };
+
+ amdgpu_ras_error_status_query(adev, );
+ }
+}
+
/* recovery begin */
/* return 0 on success.
@@ -1568,8 +1607,10 @@ static void amdgpu_ras_do_recovery(struct work_struct
*work)
}
list_for_each_entry(remote_adev,
- device_list_handle, gmc.xgmi.head)
+ device_list_handle, gmc.xgmi.head) {
+ amdgpu_ras_query_err_status(remote_adev);
amdgpu_ras_log_on_err_counter(remote_adev);
+ }
amdgpu_put_xgmi_hive(hive);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index d898c9ff3526..adee0177654e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -2075,6 +2075,7 @@ static const struct amdgpu_gfx_funcs gfx_v9_4_gfx_funcs =
{
.ras_error_inject = _v9_4_ras_error_inject,
.query_ras_error_count = _v9_4_query_ras_error_count,
.reset_ras_error_count = _v9_4_reset_ras_error_count,
+ .query_ras_error_status = _v9_4_query_ras_error_status,
};
static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
diff
[PATCH -next] drm/amd/pm: simplify the return expression of smu_hw_fini
Simplify the return expression.
Signed-off-by: Liu Shixin
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 5c4b74f964fc..3612841d40dc 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -1214,7 +1214,6 @@ static int smu_hw_fini(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct smu_context *smu = >smu;
- int ret = 0;
if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
return 0;
@@ -1230,11 +1229,7 @@ static int smu_hw_fini(void *handle)
adev->pm.dpm_enabled = false;
- ret = smu_smc_hw_cleanup(smu);
- if (ret)
- return ret;
-
- return 0;
+ return smu_smc_hw_cleanup(smu);
}
int smu_reset(struct smu_context *smu)
--
2.25.1
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[PATCH] drm/amd/display: optimize code runtime a bit
Static function dal_ddc_i2c_payloads_destroy is only called
in dal_ddc_service_query_ddc_data, the parameter is
, there is no point NULL risk, so no need to check.
This change is to make the code run a bit fast.
Signed-off-by: Bernard Zhao
---
drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
index b984eecca58b..6dcc666738fc 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
@@ -150,9 +150,6 @@ static uint32_t dal_ddc_i2c_payloads_get_count(struct
i2c_payloads *p)
static void dal_ddc_i2c_payloads_destroy(struct i2c_payloads *p)
{
- if (!p)
- return;
-
dal_vector_destruct(>payloads);
}
--
2.28.0
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[PATCH -next] drm/amdgpu: simplify the return expression
Simplify the return expression.
Signed-off-by: Qinglang Miao
---
drivers/gpu/drm/amd/amdgpu/cik_ih.c | 7 +--
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 10 ++
2 files changed, 3 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
index 401c99f0b..db953e95f 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
@@ -316,14 +316,9 @@ static int cik_ih_sw_fini(void *handle)
static int cik_ih_hw_init(void *handle)
{
- int r;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- r = cik_ih_irq_init(adev);
- if (r)
- return r;
-
- return 0;
+ return cik_ih_irq_init(adev);
}
static int cik_ih_hw_fini(void *handle)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 20d8a03ca..56ed108b2 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -2198,7 +2198,6 @@ static int gfx_v9_0_gpu_early_init(struct amdgpu_device
*adev)
static int gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
int mec, int pipe, int queue)
{
- int r;
unsigned irq_type;
struct amdgpu_ring *ring = >gfx.compute_ring[ring_id];
unsigned int hw_prio;
@@ -2223,13 +,8 @@ static int gfx_v9_0_compute_ring_init(struct
amdgpu_device *adev, int ring_id,
hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue) ?
AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
/* type-2 packets are deprecated on MEC, use type-3 instead */
- r = amdgpu_ring_init(adev, ring, 1024,
->gfx.eop_irq, irq_type, hw_prio);
- if (r)
- return r;
-
-
- return 0;
+ return amdgpu_ring_init(adev, ring, 1024,
+ >gfx.eop_irq, irq_type, hw_prio);
}
static int gfx_v9_0_sw_init(void *handle)
--
2.23.0
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[PATCH -next] drm/amdgpu/mes: simplify the return expression of mes_v10_1_ring_init
Simplify the return expression.
Signed-off-by: Qinglang Miao
---
drivers/gpu/drm/amd/amdgpu/mes_v10_1.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
index 4b746584a..1c22d8393 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
@@ -832,7 +832,6 @@ static int mes_v10_1_queue_init(struct amdgpu_device *adev)
static int mes_v10_1_ring_init(struct amdgpu_device *adev)
{
struct amdgpu_ring *ring;
- int r;
ring = >mes.ring;
@@ -849,11 +848,7 @@ static int mes_v10_1_ring_init(struct amdgpu_device *adev)
ring->no_scheduler = true;
sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue);
- r = amdgpu_ring_init(adev, ring, 1024, NULL, 0,
AMDGPU_RING_PRIO_DEFAULT);
- if (r)
- return r;
-
- return 0;
+ return amdgpu_ring_init(adev, ring, 1024, NULL, 0,
AMDGPU_RING_PRIO_DEFAULT);
}
static int mes_v10_1_mqd_sw_init(struct amdgpu_device *adev)
--
2.23.0
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[PATCH -next] drm/amdgpu/gmc9: simplify the return expression of gmc_v9_0_suspend
Simplify the return expression.
Signed-off-by: Liu Shixin
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 5400cac02087..cb9e9e5afa5a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -1683,14 +1683,9 @@ static int gmc_v9_0_hw_fini(void *handle)
static int gmc_v9_0_suspend(void *handle)
{
- int r;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- r = gmc_v9_0_hw_fini(adev);
- if (r)
- return r;
-
- return 0;
+ return gmc_v9_0_hw_fini(adev);
}
static int gmc_v9_0_resume(void *handle)
--
2.25.1
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XDC 2020 feedback and comments
Hi all, Huge thanks again to the entire team from Intel, for their great work organizing XDC 2020, our first virtual conference! As usual we're looking for feedback on both XDC itself, and the CFP process and program selection. Both about what was great and should be kept for next year's edition, and where there's room for improvement. The board does keep some notes, for those interested in what we have already: - XDC notes for prospective organizers: https://www.x.org/wiki/Events/RFP/ - CFP notes: https://www.x.org/wiki/Events/PapersCommittee/ If you want to send in your comments in private, please send them to the X.org Foundation board: bo...@foundation.x.org Cheers, Sam signature.asc Description: This is a digitally signed message part ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amd/display: [FIX] update clock under two conditions
Hi
[This is an automated email]
This commit has been processed because it contains a "Fixes:" tag
fixing commit: .
The bot has tested the following trees: v5.8.10, v5.4.66, v4.19.146, v4.14.198,
v4.9.236, v4.4.236.
v5.8.10: Failed to apply! Possible dependencies:
598c13b21e25 ("drm/amd/display: update clock when non-seamless boot stream
exist")
b7efa4f5cdb4 ("drm/amd/display: Move call to disable DPG")
v5.4.66: Failed to apply! Possible dependencies:
3a4d180d4a9d ("drm/amd/display: Optimize clocks on clock change")
598c13b21e25 ("drm/amd/display: update clock when non-seamless boot stream
exist")
6b5d7730d226 ("drm/amd/display: Add wait for flip not pending on pipe
unlock")
7f7652ee8c8c ("drm/amd/display: enable single dp seamless boot")
9ae1b27f31d0 ("drm/amd/display: fix hotplug during display off")
b6e881c94741 ("drm/amd/display: update navi to use new surface programming
behaviour")
ccce745c28d6 ("drm/amd/display: Enable Seamless Boot Transition for
Multiple Streams")
ce10a0f39b19 ("drm/amd/display: use vbios message to call smu for dpm
level")
f2988e67144a ("drm/amd/display: optimize bandwidth after commit streams.")
v4.19.146: Failed to apply! Possible dependencies:
04a789bef315 ("drm/amd/display: add stream ID and otg instance in
dc_stream_state")
077d0b6ba211 ("drm/amd/display: Remove i2caux folder")
097578091327 ("drm/amd/display: Set gamma not working on MPO planes")
0cf5eb76e2b4 ("drm/amd/display: Add tracing to dc")
1e7e86c43f38 ("drm/amd/display: decouple front and backend pgm using
dpms_off as backend enable flag")
37cd85ce3322 ("drm/amd/display: Remove dc_stream_state->status")
56780940389a ("drm/amd/display: Remove redundant non-zero and overflow
check")
8c3db1284a01 ("drm/amdgpu: fill in
amdgpu_dm_remove_sink_from_freesync_module")
98e6436d3af5 ("drm/amd/display: Refactor FreeSync module")
9b93eb475aa9 ("drm/amd/display: move clk_mgr files to right place")
ad6756b4d773 ("drm/amd/display: Shift dc link aux to aux_payload")
ccce745c28d6 ("drm/amd/display: Enable Seamless Boot Transition for
Multiple Streams")
ceb3dbb4690d ("drm/amd/display: remove sink reference in dc_stream_state")
d82f99422b21 ("drm/amd/display: move edp fast boot optimization flag to
stream")
dc6c981d2027 ("drm/amd/display: Use DGAM ROM or RAM")
eae5ffa9bd7b ("drm/amd/display: Switch ddc to new aux interface")
fcee01b9f82d ("drm/amd/display: Add DCN2 clk mgr")
v4.14.198: Failed to apply! Possible dependencies:
1b0c0f9dc5ca ("drm/amdgpu: move userptr BOs to CPU domain during CS v2")
3fe89771cb0a ("drm/amdgpu: stop reserving the BO in the MMU callback v3")
4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
60de1c1740f3 ("drm/amdgpu: use a rw_semaphore for MMU notifiers")
9a18999640fa ("drm/amdgpu: move MMU notifier related defines to
amdgpu_mn.h")
9b93eb475aa9 ("drm/amd/display: move clk_mgr files to right place")
9cca0b8e5df0 ("drm/amdgpu: move amdgpu_cs_sysvm_access_required into
find_mapping")
a216ab09955d ("drm/amdgpu: fix userptr put_page handling")
b72cf4fca2bb ("drm/amdgpu: move taking mmap_sem into get_user_pages v2")
ca666a3c298f ("drm/amdgpu: stop using BO status for user pages")
ccce745c28d6 ("drm/amd/display: Enable Seamless Boot Transition for
Multiple Streams")
fcee01b9f82d ("drm/amd/display: Add DCN2 clk mgr")
v4.9.236: Failed to apply! Possible dependencies:
1cec20f0ea0e ("dma-buf: Restart reservation_object_wait_timeout_rcu() after
writes")
248a1d6f1ac4 ("drm/amd: fix include notation and remove -Iinclude/drm flag")
4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
78010cd9736e ("dma-buf/fence: add an lockdep_assert_held()")
9b93eb475aa9 ("drm/amd/display: move clk_mgr files to right place")
ccce745c28d6 ("drm/amd/display: Enable Seamless Boot Transition for
Multiple Streams")
f54d1867005c ("dma-buf: Rename struct fence to dma_fence")
fcee01b9f82d ("drm/amd/display: Add DCN2 clk mgr")
fedf54132d24 ("dma-buf: Restart reservation_object_get_fences_rcu() after
writes")
v4.4.236: Failed to apply! Possible dependencies:
0f477c6dea70 ("staging/android/sync: add sync_fence_create_dma")
1f7371b2a5fa ("drm/amd/powerplay: add basic powerplay framework")
248a1d6f1ac4 ("drm/amd: fix include notation and remove -Iinclude/drm flag")
288912cb95d1 ("drm/amdgpu: use $(src) in Makefile (v2)")
375fb53ec1be ("staging: android: replace explicit NULL comparison")
395dec6f6bc5 ("Documentation: add doc for sync_file_get_fence()")
4325198180e5 ("drm/amdgpu: remove GART page addr array")
4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
62304fb1fc08 ("dma-buf/sync_file: de-stage sync_file")
9b93eb475aa9 ("drm/amd/display: move clk_mgr files to right place")
a1d29476d666 ("drm/amdgpu: optionally enable GART debugfs file")
a8fe58cec351 ("drm/amd: add
Re: [PATCH v2] Revert "drm/radeon: handle PCIe root ports with addressing limitations"
Hi
[This is an automated email]
This commit has been processed because it contains a "Fixes:" tag
fixing commit: 33b3ad3788ab ("drm/radeon: handle PCIe root ports with
addressing limitations").
The bot has tested the following trees: v5.8.10, v5.4.66.
v5.8.10: Build OK!
v5.4.66: Failed to apply! Possible dependencies:
8b53e1cb2728 ("drm/radeon: switch to gem vma offset manager")
9d6f4484e81c ("drm/ttm: turn ttm_bo_device.vma_manager into a pointer")
NOTE: The patch will not be queued to stable trees until it is upstream.
How should we proceed with this patch?
--
Thanks
Sasha
___
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amd-gfx@lists.freedesktop.org
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Re: [PATCH 08/15] drm/amd/display: Increase timeout for DP Disable
Hi
[This is an automated email]
This commit has been processed because it contains a -stable tag.
The stable tag indicates that it's relevant for the following trees: all
The bot has tested the following trees: v5.8.10, v5.4.66, v4.19.146, v4.14.198,
v4.9.236, v4.4.236.
v5.8.10: Build OK!
v5.4.66: Build OK!
v4.19.146: Failed to apply! Possible dependencies:
3af91bb15093 ("drm/amd/display: Increase DP blank timeout from 30 ms to 50
ms")
v4.14.198: Failed to apply! Possible dependencies:
0c41891c81c0 ("drm/amd/display: Refactor stream encoder for HW review")
1b0c0f9dc5ca ("drm/amdgpu: move userptr BOs to CPU domain during CS v2")
3fe89771cb0a ("drm/amdgpu: stop reserving the BO in the MMU callback v3")
4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
587cdfe9463e ("drm/amd/display: Rename trasnform to dpp for dcn's")
5aff86c1b325 ("drm/amd/display: Implement input gamma LUT")
60de1c1740f3 ("drm/amdgpu: use a rw_semaphore for MMU notifiers")
70ccab604049 ("drm/amdgpu/display: Add core dc support for DCN")
9a18999640fa ("drm/amdgpu: move MMU notifier related defines to
amdgpu_mn.h")
9a70eba7f2c6 ("drm/amd/display: consolidate dce8-11.2 display clock code")
9cca0b8e5df0 ("drm/amdgpu: move amdgpu_cs_sysvm_access_required into
find_mapping")
a216ab09955d ("drm/amdgpu: fix userptr put_page handling")
b1a4eb992c17 ("drm/amd/display: enable diags compilation")
b51adc77e220 ("drm/amd/display: Only blank DCN when we have set_blank
implementation")
b72cf4fca2bb ("drm/amdgpu: move taking mmap_sem into get_user_pages v2")
ca666a3c298f ("drm/amdgpu: stop using BO status for user pages")
v4.9.236: Failed to apply! Possible dependencies:
0c41891c81c0 ("drm/amd/display: Refactor stream encoder for HW review")
1cec20f0ea0e ("dma-buf: Restart reservation_object_wait_timeout_rcu() after
writes")
248a1d6f1ac4 ("drm/amd: fix include notation and remove -Iinclude/drm flag")
4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
587cdfe9463e ("drm/amd/display: Rename trasnform to dpp for dcn's")
5aff86c1b325 ("drm/amd/display: Implement input gamma LUT")
70ccab604049 ("drm/amdgpu/display: Add core dc support for DCN")
78010cd9736e ("dma-buf/fence: add an lockdep_assert_held()")
9a70eba7f2c6 ("drm/amd/display: consolidate dce8-11.2 display clock code")
b1a4eb992c17 ("drm/amd/display: enable diags compilation")
b51adc77e220 ("drm/amd/display: Only blank DCN when we have set_blank
implementation")
f54d1867005c ("dma-buf: Rename struct fence to dma_fence")
fedf54132d24 ("dma-buf: Restart reservation_object_get_fences_rcu() after
writes")
v4.4.236: Failed to apply! Possible dependencies:
0c41891c81c0 ("drm/amd/display: Refactor stream encoder for HW review")
0f477c6dea70 ("staging/android/sync: add sync_fence_create_dma")
1f7371b2a5fa ("drm/amd/powerplay: add basic powerplay framework")
248a1d6f1ac4 ("drm/amd: fix include notation and remove -Iinclude/drm flag")
288912cb95d1 ("drm/amdgpu: use $(src) in Makefile (v2)")
375fb53ec1be ("staging: android: replace explicit NULL comparison")
395dec6f6bc5 ("Documentation: add doc for sync_file_get_fence()")
4325198180e5 ("drm/amdgpu: remove GART page addr array")
4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
587cdfe9463e ("drm/amd/display: Rename trasnform to dpp for dcn's")
5aff86c1b325 ("drm/amd/display: Implement input gamma LUT")
62304fb1fc08 ("dma-buf/sync_file: de-stage sync_file")
70ccab604049 ("drm/amdgpu/display: Add core dc support for DCN")
9a70eba7f2c6 ("drm/amd/display: consolidate dce8-11.2 display clock code")
a1d29476d666 ("drm/amdgpu: optionally enable GART debugfs file")
a8fe58cec351 ("drm/amd: add ACP driver support")
b1a4eb992c17 ("drm/amd/display: enable diags compilation")
b51adc77e220 ("drm/amd/display: Only blank DCN when we have set_blank
implementation")
b70f014d58b9 ("drm/amdgpu: change default sched jobs to 32")
c784c82a3fd6 ("Documentation: add Sync File doc")
d4cab38e153d ("staging/android: prepare sync_file for de-staging")
d7fdb0ae9d11 ("staging/android: rename sync_fence to sync_file")
f54d1867005c ("dma-buf: Rename struct fence to dma_fence")
fac8434dab96 ("Documentation: Fix some grammar mistakes in sync_file.txt")
fdba11f4079e ("drm/amdgpu: move all Kconfig options to amdgpu/Kconfig")
NOTE: The patch will not be queued to stable trees until it is upstream.
How should we proceed with this patch?
--
Thanks
Sasha
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 07/15] drm/amd/display: Fix ODM policy implementation
Hi
[This is an automated email]
This commit has been processed because it contains a -stable tag.
The stable tag indicates that it's relevant for the following trees: all
The bot has tested the following trees: v5.8.10, v5.4.66, v4.19.146, v4.14.198,
v4.9.236, v4.4.236.
v5.4.66: Failed to apply! Possible dependencies:
2b77dcc5e5aa ("drm/amd/display: rename core_dc to dc")
48af9b91b129 ("drm/amd/display: Don't allocate payloads if link lost")
4c1a1335dfe0 ("drm/amd/display: Driverside changes to support PSR in DMCUB")
7f7652ee8c8c ("drm/amd/display: enable single dp seamless boot")
904fb6e0f4e8 ("drm/amd/display: move panel power seq to new panel struct")
9ae1b27f31d0 ("drm/amd/display: fix hotplug during display off")
9dac88d8792a ("drm/amd/display: Add driver support for enabling PSR on
DMCUB")
ab4a4072f260 ("drm/amd/display: exit PSR during detection")
b739ab3a4fe6 ("drm/amd/display: Fix incorrect backlight register offset for
DCN")
d4252eee1f7c ("drm/amd/display: Add debugfs entry to force YUV420 output")
d462fcf5012b ("drm/amd/display: Update hdcp display config")
e0d08a40a63b ("drm/amd/display: Add debugfs entry for reading psr state")
e78a312f81c8 ("drm/amd/display: use requested_dispclk_khz instead of clk")
ef5a7d266e82 ("drm/amd/display: skip enable stream on disconnected display")
v4.19.146: Failed to apply! Possible dependencies:
1f6010a96273 ("drm/amd/display: Improve spelling, grammar, and formatting
of amdgpu_dm.c comments")
813d20dccf93 ("drm/amd/display: Fix multi-thread writing to 1 state")
8c3db1284a01 ("drm/amdgpu: fill in
amdgpu_dm_remove_sink_from_freesync_module")
904fb6e0f4e8 ("drm/amd/display: move panel power seq to new panel struct")
98e6436d3af5 ("drm/amd/display: Refactor FreeSync module")
a87fa9938749 ("drm/amd/display: Build stream update and plane updates in
dm")
a94d5569b232 ("drm/amd: Add DM DMCU support")
b739ab3a4fe6 ("drm/amd/display: Fix incorrect backlight register offset for
DCN")
b8592b48450b ("drm/amd/display: Initial documentation for AMDgpu DC")
dc88b4a684d2 ("drm/amd/display: make clk mgr soc specific")
eb3dc8978596 ("drm/amd/display: Use private obj helpers for
dm_atomic_state")
v4.14.198: Failed to apply! Possible dependencies:
1296423bf23c ("drm/amd/display: define DC_LOGGER for logger")
1b0c0f9dc5ca ("drm/amdgpu: move userptr BOs to CPU domain during CS v2")
3fe89771cb0a ("drm/amdgpu: stop reserving the BO in the MMU callback v3")
4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
60de1c1740f3 ("drm/amdgpu: use a rw_semaphore for MMU notifiers")
74c49c7ac14f ("drm/amdgpu/display: Add calcs code for DCN")
904fb6e0f4e8 ("drm/amd/display: move panel power seq to new panel struct")
9a18999640fa ("drm/amdgpu: move MMU notifier related defines to
amdgpu_mn.h")
9cca0b8e5df0 ("drm/amdgpu: move amdgpu_cs_sysvm_access_required into
find_mapping")
a216ab09955d ("drm/amdgpu: fix userptr put_page handling")
b72cf4fca2bb ("drm/amdgpu: move taking mmap_sem into get_user_pages v2")
b739ab3a4fe6 ("drm/amd/display: Fix incorrect backlight register offset for
DCN")
ca666a3c298f ("drm/amdgpu: stop using BO status for user pages")
dc88b4a684d2 ("drm/amd/display: make clk mgr soc specific")
f3efec54ed6a ("drm/amd/display: Allow option to use worst-case watermark")
v4.9.236: Failed to apply! Possible dependencies:
1296423bf23c ("drm/amd/display: define DC_LOGGER for logger")
1cec20f0ea0e ("dma-buf: Restart reservation_object_wait_timeout_rcu() after
writes")
248a1d6f1ac4 ("drm/amd: fix include notation and remove -Iinclude/drm flag")
4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
74c49c7ac14f ("drm/amdgpu/display: Add calcs code for DCN")
78010cd9736e ("dma-buf/fence: add an lockdep_assert_held()")
904fb6e0f4e8 ("drm/amd/display: move panel power seq to new panel struct")
b739ab3a4fe6 ("drm/amd/display: Fix incorrect backlight register offset for
DCN")
dc88b4a684d2 ("drm/amd/display: make clk mgr soc specific")
f3efec54ed6a ("drm/amd/display: Allow option to use worst-case watermark")
f54d1867005c ("dma-buf: Rename struct fence to dma_fence")
fedf54132d24 ("dma-buf: Restart reservation_object_get_fences_rcu() after
writes")
v4.4.236: Failed to apply! Possible dependencies:
0f477c6dea70 ("staging/android/sync: add sync_fence_create_dma")
1296423bf23c ("drm/amd/display: define DC_LOGGER for logger")
1f7371b2a5fa ("drm/amd/powerplay: add basic powerplay framework")
248a1d6f1ac4 ("drm/amd: fix include notation and remove -Iinclude/drm flag")
288912cb95d1 ("drm/amdgpu: use $(src) in Makefile (v2)")
375fb53ec1be ("staging: android: replace explicit NULL comparison")
395dec6f6bc5 ("Documentation: add doc for sync_file_get_fence()")
4325198180e5 ("drm/amdgpu: remove GART page addr array")
4562236b3bc0 ("drm/amd/dc:
Re: [PATCH 01/15] drm/amd/display: Fix incorrect backlight register offset for DCN
Hi
[This is an automated email]
This commit has been processed because it contains a -stable tag.
The stable tag indicates that it's relevant for the following trees: all
The bot has tested the following trees: v5.8.10, v5.4.66, v4.19.146, v4.14.198,
v4.9.236, v4.4.236.
v5.4.66: Failed to apply! Possible dependencies:
2b77dcc5e5aa ("drm/amd/display: rename core_dc to dc")
48af9b91b129 ("drm/amd/display: Don't allocate payloads if link lost")
4c1a1335dfe0 ("drm/amd/display: Driverside changes to support PSR in DMCUB")
7f7652ee8c8c ("drm/amd/display: enable single dp seamless boot")
904fb6e0f4e8 ("drm/amd/display: move panel power seq to new panel struct")
9ae1b27f31d0 ("drm/amd/display: fix hotplug during display off")
9dac88d8792a ("drm/amd/display: Add driver support for enabling PSR on
DMCUB")
ab4a4072f260 ("drm/amd/display: exit PSR during detection")
d4252eee1f7c ("drm/amd/display: Add debugfs entry to force YUV420 output")
d462fcf5012b ("drm/amd/display: Update hdcp display config")
e0d08a40a63b ("drm/amd/display: Add debugfs entry for reading psr state")
e78a312f81c8 ("drm/amd/display: use requested_dispclk_khz instead of clk")
ef5a7d266e82 ("drm/amd/display: skip enable stream on disconnected display")
v4.19.146: Failed to apply! Possible dependencies:
1f6010a96273 ("drm/amd/display: Improve spelling, grammar, and formatting
of amdgpu_dm.c comments")
813d20dccf93 ("drm/amd/display: Fix multi-thread writing to 1 state")
8c3db1284a01 ("drm/amdgpu: fill in
amdgpu_dm_remove_sink_from_freesync_module")
904fb6e0f4e8 ("drm/amd/display: move panel power seq to new panel struct")
98e6436d3af5 ("drm/amd/display: Refactor FreeSync module")
a87fa9938749 ("drm/amd/display: Build stream update and plane updates in
dm")
a94d5569b232 ("drm/amd: Add DM DMCU support")
b8592b48450b ("drm/amd/display: Initial documentation for AMDgpu DC")
dc88b4a684d2 ("drm/amd/display: make clk mgr soc specific")
eb3dc8978596 ("drm/amd/display: Use private obj helpers for
dm_atomic_state")
v4.14.198: Failed to apply! Possible dependencies:
1296423bf23c ("drm/amd/display: define DC_LOGGER for logger")
1b0c0f9dc5ca ("drm/amdgpu: move userptr BOs to CPU domain during CS v2")
3fe89771cb0a ("drm/amdgpu: stop reserving the BO in the MMU callback v3")
4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
60de1c1740f3 ("drm/amdgpu: use a rw_semaphore for MMU notifiers")
74c49c7ac14f ("drm/amdgpu/display: Add calcs code for DCN")
904fb6e0f4e8 ("drm/amd/display: move panel power seq to new panel struct")
9a18999640fa ("drm/amdgpu: move MMU notifier related defines to
amdgpu_mn.h")
9cca0b8e5df0 ("drm/amdgpu: move amdgpu_cs_sysvm_access_required into
find_mapping")
a216ab09955d ("drm/amdgpu: fix userptr put_page handling")
b72cf4fca2bb ("drm/amdgpu: move taking mmap_sem into get_user_pages v2")
ca666a3c298f ("drm/amdgpu: stop using BO status for user pages")
dc88b4a684d2 ("drm/amd/display: make clk mgr soc specific")
f3efec54ed6a ("drm/amd/display: Allow option to use worst-case watermark")
v4.9.236: Failed to apply! Possible dependencies:
1296423bf23c ("drm/amd/display: define DC_LOGGER for logger")
1cec20f0ea0e ("dma-buf: Restart reservation_object_wait_timeout_rcu() after
writes")
248a1d6f1ac4 ("drm/amd: fix include notation and remove -Iinclude/drm flag")
4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
74c49c7ac14f ("drm/amdgpu/display: Add calcs code for DCN")
78010cd9736e ("dma-buf/fence: add an lockdep_assert_held()")
904fb6e0f4e8 ("drm/amd/display: move panel power seq to new panel struct")
dc88b4a684d2 ("drm/amd/display: make clk mgr soc specific")
f3efec54ed6a ("drm/amd/display: Allow option to use worst-case watermark")
f54d1867005c ("dma-buf: Rename struct fence to dma_fence")
fedf54132d24 ("dma-buf: Restart reservation_object_get_fences_rcu() after
writes")
v4.4.236: Failed to apply! Possible dependencies:
0f477c6dea70 ("staging/android/sync: add sync_fence_create_dma")
1296423bf23c ("drm/amd/display: define DC_LOGGER for logger")
1f7371b2a5fa ("drm/amd/powerplay: add basic powerplay framework")
248a1d6f1ac4 ("drm/amd: fix include notation and remove -Iinclude/drm flag")
288912cb95d1 ("drm/amdgpu: use $(src) in Makefile (v2)")
375fb53ec1be ("staging: android: replace explicit NULL comparison")
395dec6f6bc5 ("Documentation: add doc for sync_file_get_fence()")
4325198180e5 ("drm/amdgpu: remove GART page addr array")
4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
62304fb1fc08 ("dma-buf/sync_file: de-stage sync_file")
74c49c7ac14f ("drm/amdgpu/display: Add calcs code for DCN")
904fb6e0f4e8 ("drm/amd/display: move panel power seq to new panel struct")
a1d29476d666 ("drm/amdgpu: optionally enable GART debugfs file")
a8fe58cec351 ("drm/amd: add ACP driver
Re: [Intel-gfx] [PATCH 0/4] managed drm_device, absolute final leftover bits
On Fri, Sep 18, 2020 at 01:12:21PM -0400, Rodrigo Vivi wrote: > On Fri, Sep 18, 2020 at 11:03:12AM -0400, Alex Deucher wrote: > > On Fri, Sep 18, 2020 at 9:25 AM Daniel Vetter > > wrote: > > > > > > Hi all, > > > > > > These are the leftovers of the leftovers of my initial drmm series to > > > manage drm_device. > > > > > > Changes: > > > - bugfixed i915 selftests > > > - patch from Luben to finalize the admgpu conversion > > > > > > Alex & i915 maintainers, pls ack for merging this all through > > > drm-misc-next since otherwise the final patch (and the resulting confusion > > > with outdated docs) is held up another round. > > > > Acked-by: Alex Deucher > > > Acked-by: Rodrigo Vivi Entire series merged into drm-misc-next. -Daniel > > > > > > > > > Cheers, Daniel > > > > > > Daniel Vetter (3): > > > drm/i915/selftest: Create mock_destroy_device > > > drm/i915/selftests: align more to real device lifetimes > > > drm/dev: Remove drm_dev_init > > > > > > Luben Tuikov (1): > > > drm/amdgpu: Convert to using devm_drm_dev_alloc() (v2) > > > > > > drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 16 ++ > > > drivers/gpu/drm/drm_drv.c | 41 ++-- > > > drivers/gpu/drm/drm_internal.h| 1 + > > > drivers/gpu/drm/drm_managed.c | 13 - > > > .../gpu/drm/i915/gem/selftests/huge_pages.c | 2 +- > > > .../drm/i915/gem/selftests/i915_gem_context.c | 2 +- > > > .../drm/i915/gem/selftests/i915_gem_dmabuf.c | 2 +- > > > .../drm/i915/gem/selftests/i915_gem_object.c | 2 +- > > > .../drm/i915/gem/selftests/i915_gem_phys.c| 2 +- > > > drivers/gpu/drm/i915/gt/selftest_timeline.c | 2 +- > > > .../gpu/drm/i915/selftests/i915_gem_evict.c | 2 +- > > > drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 2 +- > > > drivers/gpu/drm/i915/selftests/i915_request.c | 2 +- > > > drivers/gpu/drm/i915/selftests/i915_vma.c | 2 +- > > > .../drm/i915/selftests/intel_memory_region.c | 2 +- > > > .../gpu/drm/i915/selftests/mock_gem_device.c | 49 --- > > > .../gpu/drm/i915/selftests/mock_gem_device.h | 2 + > > > include/drm/drm_drv.h | 4 -- > > > 18 files changed, 51 insertions(+), 97 deletions(-) > > > > > > -- > > > 2.28.0 > > > > > > ___ > > > amd-gfx mailing list > > > amd-gfx@lists.freedesktop.org > > > https://lists.freedesktop.org/mailman/listinfo/amd-gfx > > ___ > > Intel-gfx mailing list > > intel-...@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH] drm/amdgpu/sriov: Enable the mcbp parameter for sriov
[AMD Official Use Only - Internal Distribution Only]
Hi Monk,
Just for debugging, we don't need to remove those amdgpu_sriov_vf, it won't
affect the mcbp disable.
Best wishes
Emily Deng
>-Original Message-
>From: Liu, Monk
>Sent: Monday, September 21, 2020 4:02 PM
>To: Deng, Emily ; amd-gfx@lists.freedesktop.org
>Cc: Deng, Emily
>Subject: RE: [PATCH] drm/amdgpu/sriov: Enable the mcbp parameter for sriov
>
>[AMD Official Use Only - Internal Distribution Only]
>
>Looks you missed many places, e.g.:
>
>866 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
> 867 bo_va = fpriv->csa_va;
> 868 BUG_ON(!bo_va);
> 869 r = amdgpu_vm_bo_update(adev, bo_va, false);
> 870 if (r)
> 871 return r;
> 872
> 873 r = amdgpu_sync_vm_fence(>job->sync, bo_va-
>>last_pt_update);
> 874 if (r)
> 875 return r;
> 876 }
>
>
> 949 if (chunk_ib->ip_type == AMDGPU_HW_IP_GFX &&
> 950 (amdgpu_mcbp || amdgpu_sriov_vf(adev))) {
> 951 if (chunk_ib->flags & AMDGPU_IB_FLAG_PREEMPT) {
> 952 if (chunk_ib->flags & AMDGPU_IB_FLAG_CE)
> 953 ce_preempt++;
> 954 else
> 955 de_preempt++;
> 956 }
> 957
> 958 /* each GFX command submit allows 0 or 1 IB preemptible for
> CE
>& DE */
> 959 if (ce_preempt > 1 || de_preempt > 1)
> 960 return -EINVAL;
> 961 }
>
>
> 2029 r = amdgpu_device_wb_init(adev);
> 2030 if (r) {
> 2031 DRM_ERROR("amdgpu_device_wb_init failed %d\n", r);
> 2032 goto init_failed;
> 2033 }
> 2034 adev->ip_blocks[i].status.hw = true;
> 2035
> 2036 /* right after GMC hw init, we create CSA */
> 2037 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
> 2038 r = amdgpu_allocate_static_csa(adev,
> >virt.csa_obj,
> 2039 AMDGPU_GEM_DOMAIN_VRAM,
> 2040 AMDGPU_CSA_SIZE);
> 2041 if (r) {
> 2042 DRM_ERROR("allocate CSA failed %d\n", r);
> 2043 goto init_failed;
> 2044 }
> 2045 }
> 2046 }
> 2047 }
>
>
> 4587 if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags &
>AMDGPU_IB_FLAG_PREEMPT)) {
> 4588 control |= INDIRECT_BUFFER_PRE_ENB(1);
> 4589
> 4590 if (flags & AMDGPU_IB_PREEMPTED)
> 4591 control |= INDIRECT_BUFFER_PRE_RESUME(1);
> 4592
> 4593 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)
> 4594 gfx_v10_0_ring_emit_de_meta(ring,
> 4595 (!amdgpu_sriov_vf(ring->adev) && flags &
>AMDGPU_IB_PREEMPTED) ? true : false);
> 4596 }
>
>
>
> 4742 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
> 4743 uint32_t flags)
> 4744 {
> 4745 uint32_t dw2 = 0;
> 4746
> 4747 if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev))
> 4748 gfx_v10_0_ring_emit_ce_meta(ring,
> 4749 (!amdgpu_sriov_vf(ring->adev) && flags &
>AMDGPU_IB_PREEMPTED) ? true : false);
> 4750
> 4751 dw2 |= 0x8000; /* set load_enable otherwise this package is just
>NOPs */
> 4752 if (flags & AMDGPU_HAVE_CTX_SWITCH) {
>
>72
> 73 /* don't enable OS preemption on SDMA under SRIOV */
> 74 if (amdgpu_sriov_vf(adev) || vmid == 0 || !amdgpu_mcbp)
> 75 return 0;
> 76
> 77 r = amdgpu_sdma_get_index_from_ring(ring, );
> 78
> 79 if (r || index > 31)
> 80 csa_mc_addr = 0;
>
>
>You need to change all the place refer to "amdgpu_mcbp", and remove the
>condition of " || amdgpu_srvio_vf()"
>
>_
>Monk Liu|GPU Virtualization Team |AMD
>
>
>-Original Message-
>From: amd-gfx On Behalf Of
>Emily.Deng
>Sent: Monday, September 21, 2020 3:55 PM
>To: amd-gfx@lists.freedesktop.org
>Cc: Deng, Emily
>Subject: [PATCH] drm/amdgpu/sriov: Enable the mcbp parameter for sriov
>
>For debug convenient, reuse mcbp parameter for sriov mcbp
>
>Signed-off-by: Emily.Deng
>Change-Id: If1222b2c050376feefb8fed4be58b4b87d36bd77
>---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 9 ++---
> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c| 5 +++--
> drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 3 ++-
> 3 files changed, 11 insertions(+), 6 deletions(-)
>
>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>index 5c2eb46e9b71..fcb6a41594db 100644
>--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>@@ -3197,15 +3197,18 @@ int amdgpu_device_init(struct amdgpu_device
>*adev,
>
> amdgpu_device_get_pcie_info(adev);
>
>-if (amdgpu_mcbp)
>-DRM_INFO("MCBP is enabled\n");
>-
> if (amdgpu_mes && adev->asic_type >=
RE: [PATCH] drm/amdgpu/sriov: Enable the mcbp parameter for sriov
[AMD Official Use Only - Internal Distribution Only]
Looks you missed many places, e.g.:
866 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
867 bo_va = fpriv->csa_va;
868 BUG_ON(!bo_va);
869 r = amdgpu_vm_bo_update(adev, bo_va, false);
870 if (r)
871 return r;
872
873 r = amdgpu_sync_vm_fence(>job->sync, bo_va->last_pt_update);
874 if (r)
875 return r;
876 }
949 if (chunk_ib->ip_type == AMDGPU_HW_IP_GFX &&
950 (amdgpu_mcbp || amdgpu_sriov_vf(adev))) {
951 if (chunk_ib->flags & AMDGPU_IB_FLAG_PREEMPT) {
952 if (chunk_ib->flags & AMDGPU_IB_FLAG_CE)
953 ce_preempt++;
954 else
955 de_preempt++;
956 }
957
958 /* each GFX command submit allows 0 or 1 IB preemptible for
CE & DE */
959 if (ce_preempt > 1 || de_preempt > 1)
960 return -EINVAL;
961 }
2029 r = amdgpu_device_wb_init(adev);
2030 if (r) {
2031 DRM_ERROR("amdgpu_device_wb_init failed %d\n", r);
2032 goto init_failed;
2033 }
2034 adev->ip_blocks[i].status.hw = true;
2035
2036 /* right after GMC hw init, we create CSA */
2037 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
2038 r = amdgpu_allocate_static_csa(adev, >virt.csa_obj,
2039 AMDGPU_GEM_DOMAIN_VRAM,
2040 AMDGPU_CSA_SIZE);
2041 if (r) {
2042 DRM_ERROR("allocate CSA failed %d\n", r);
2043 goto init_failed;
2044 }
2045 }
2046 }
2047 }
4587 if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags &
AMDGPU_IB_FLAG_PREEMPT)) {
4588 control |= INDIRECT_BUFFER_PRE_ENB(1);
4589
4590 if (flags & AMDGPU_IB_PREEMPTED)
4591 control |= INDIRECT_BUFFER_PRE_RESUME(1);
4592
4593 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)
4594 gfx_v10_0_ring_emit_de_meta(ring,
4595 (!amdgpu_sriov_vf(ring->adev) && flags &
AMDGPU_IB_PREEMPTED) ? true : false);
4596 }
4742 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
4743 uint32_t flags)
4744 {
4745 uint32_t dw2 = 0;
4746
4747 if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev))
4748 gfx_v10_0_ring_emit_ce_meta(ring,
4749 (!amdgpu_sriov_vf(ring->adev) && flags &
AMDGPU_IB_PREEMPTED) ? true : false);
4750
4751 dw2 |= 0x8000; /* set load_enable otherwise this package is just
NOPs */
4752 if (flags & AMDGPU_HAVE_CTX_SWITCH) {
72
73 /* don't enable OS preemption on SDMA under SRIOV */
74 if (amdgpu_sriov_vf(adev) || vmid == 0 || !amdgpu_mcbp)
75 return 0;
76
77 r = amdgpu_sdma_get_index_from_ring(ring, );
78
79 if (r || index > 31)
80 csa_mc_addr = 0;
You need to change all the place refer to "amdgpu_mcbp", and remove the
condition of " || amdgpu_srvio_vf()"
_
Monk Liu|GPU Virtualization Team |AMD
-Original Message-
From: amd-gfx On Behalf Of Emily.Deng
Sent: Monday, September 21, 2020 3:55 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deng, Emily
Subject: [PATCH] drm/amdgpu/sriov: Enable the mcbp parameter for sriov
For debug convenient, reuse mcbp parameter for sriov mcbp
Signed-off-by: Emily.Deng
Change-Id: If1222b2c050376feefb8fed4be58b4b87d36bd77
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 9 ++---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c| 5 +++--
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 3 ++-
3 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 5c2eb46e9b71..fcb6a41594db 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3197,15 +3197,18 @@ int amdgpu_device_init(struct amdgpu_device *adev,
amdgpu_device_get_pcie_info(adev);
-if (amdgpu_mcbp)
-DRM_INFO("MCBP is enabled\n");
-
if (amdgpu_mes && adev->asic_type >= CHIP_NAVI10)
adev->enable_mes = true;
/* detect hw virtualization here */
amdgpu_detect_virtualization(adev);
+if (amdgpu_mcbp == -1)
+amdgpu_mcbp = amdgpu_sriov_vf(adev) ? 1 : 0;
+
+if (amdgpu_mcbp)
+DRM_INFO("MCBP is enabled\n");
+
r = amdgpu_device_get_job_timeout_settings(adev);
if (r) {
dev_err(adev->dev, "invalid lockup_timeout parameter syntax\n"); diff --git
a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 8d658d2a16fe..976d4f8ee2f1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++
[PATCH] drm/amdgpu/sriov: Enable the mcbp parameter for sriov
For debug convenient, reuse mcbp parameter for sriov mcbp
Signed-off-by: Emily.Deng
Change-Id: If1222b2c050376feefb8fed4be58b4b87d36bd77
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 9 ++---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c| 5 +++--
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 3 ++-
3 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 5c2eb46e9b71..fcb6a41594db 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3197,15 +3197,18 @@ int amdgpu_device_init(struct amdgpu_device *adev,
amdgpu_device_get_pcie_info(adev);
- if (amdgpu_mcbp)
- DRM_INFO("MCBP is enabled\n");
-
if (amdgpu_mes && adev->asic_type >= CHIP_NAVI10)
adev->enable_mes = true;
/* detect hw virtualization here */
amdgpu_detect_virtualization(adev);
+ if (amdgpu_mcbp == -1)
+ amdgpu_mcbp = amdgpu_sriov_vf(adev) ? 1 : 0;
+
+ if (amdgpu_mcbp)
+ DRM_INFO("MCBP is enabled\n");
+
r = amdgpu_device_get_job_timeout_settings(adev);
if (r) {
dev_err(adev->dev, "invalid lockup_timeout parameter syntax\n");
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 8d658d2a16fe..976d4f8ee2f1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -144,7 +144,7 @@ uint amdgpu_smu_memory_pool_size = 0;
uint amdgpu_dc_feature_mask = 0;
uint amdgpu_dc_debug_mask = 0;
int amdgpu_async_gfx_ring = 1;
-int amdgpu_mcbp = 0;
+int amdgpu_mcbp = -1;
int amdgpu_discovery = -1;
int amdgpu_mes = 0;
int amdgpu_noretry;
@@ -575,9 +575,10 @@ module_param_named(async_gfx_ring, amdgpu_async_gfx_ring,
int, 0444);
* It is used to enable mid command buffer preemption. (0 = disabled
(default), 1 = enabled)
*/
MODULE_PARM_DESC(mcbp,
- "Enable Mid-command buffer preemption (0 = disabled (default), 1 =
enabled)");
+ "Enable Mid-command buffer preemption (-1 = auto (default), 0 =
disabled, 1 = enabled)");
module_param_named(mcbp, amdgpu_mcbp, int, 0444);
+
/**
* DOC: discovery (int)
* Allow driver to discover hardware IP information from IP Discovery table at
the top of VRAM.
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index 2f53fa0ae9a6..cffa45a9481d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -236,7 +236,8 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned
num_ibs,
for (i = 0; i < num_ibs; ++i) {
ib = [i];
-
+ if (!amdgpu_mcbp)
+ ib->flags &= ~AMDGPU_IB_FLAG_PREEMPT;
/* drop preamble IBs if we don't have a context switch */
if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) &&
skip_preamble &&
--
2.25.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH 1/2] drm/amdgpu/sriov: Add one parameter for mcbp debug
[AMD Official Use Only - Internal Distribution Only]
Hi Monk,
Good suggestion, will send out patch again.
Best wishes
Emily Deng
>-Original Message-
>From: Liu, Monk
>Sent: Monday, September 21, 2020 1:37 PM
>To: Deng, Emily ; amd-gfx@lists.freedesktop.org
>Cc: Deng, Emily
>Subject: RE: [PATCH 1/2] drm/amdgpu/sriov: Add one parameter for mcbp
>debug
>
>[AMD Official Use Only - Internal Distribution Only]
>
>Hi Emily
>
>There is already a amdgpu_mcbp parameter there, can you try to leverage that
>one ?
>
>e.g.:
>we refactor our driver's code and reduce the checking logic from "if
>(amdgpu_mcbp || amdgpu_sriov_vf(adev))" to something like
>"if( amdgpu_mcbp) "
>
>therefore:
>1) You need to force set "amdgpu_mcbp" to true in the driver's init stage once
>the "SRIOV" is detected *and* "amdgpu_mcbp" is not set to "0";
>2) for Bare-metal, we just leave "amdgpu_mcbp" as the value it was
>3) we interpret "amdgpu_mcbp" as:
>0: force disable, it will be "disable" for both BM and SRIOV
>1: force enable, auto (default), it will be "enable" for both BM and SRIOV
>
>This way if you can disable MCBP in both SRIOV and BM by that existed
>parameter instead of introducing a duplicated one ...
>
>_
>Monk Liu|GPU Virtualization Team |AMD
>
>
>-Original Message-
>From: amd-gfx On Behalf Of
>Emily.Deng
>Sent: Friday, September 18, 2020 11:27 AM
>To: amd-gfx@lists.freedesktop.org
>Cc: Deng, Emily
>Subject: [PATCH 1/2] drm/amdgpu/sriov: Add one parameter for mcbp debug
>
>For debug convenient, add sriov_mcbp parameter.
>
>Signed-off-by: Emily.Deng
>Change-Id: I84019eb4344e00d85b2ecc853145aabb312412fe
>---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 9 +
>drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 3 ++-
>drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 +-
> 4 files changed, 13 insertions(+), 2 deletions(-)
>
>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>index 13f92dea182a..a255fbf4d370 100644
>--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>@@ -183,6 +183,7 @@ extern uint amdgpu_ras_mask; extern int
>amdgpu_bad_page_threshold; extern int amdgpu_async_gfx_ring; extern int
>amdgpu_mcbp;
>+extern int amdgpu_sriov_mcbp;
> extern int amdgpu_discovery;
> extern int amdgpu_mes;
> extern int amdgpu_noretry;
>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>index 3f07d1475bd2..b0b2f0f7be94 100644
>--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>@@ -145,6 +145,7 @@ uint amdgpu_dc_feature_mask = 0; uint
>amdgpu_dc_debug_mask = 0; int amdgpu_async_gfx_ring = 1; int
>amdgpu_mcbp = 0;
>+int amdgpu_sriov_mcbp = 1;
> int amdgpu_discovery = -1;
> int amdgpu_mes = 0;
> int amdgpu_noretry;
>@@ -578,6 +579,14 @@ MODULE_PARM_DESC(mcbp, "Enable Mid-command
>buffer preemption (0 = disabled (default), 1 = enabled)");
>module_param_named(mcbp, amdgpu_mcbp, int, 0444);
>
>+/**
>+ * DOC: sriov_mcbp (int)
>+ * It is used to enable mid command buffer preemption. (0 = disabled, 1
>+= enabled(default)) */ MODULE_PARM_DESC(sriov_mcbp, "Enable sriov
>+Mid-command buffer preemption (0 = disabled (default), 1 = enabled)");
>+module_param_named(sriov_mcbp, amdgpu_sriov_mcbp, int, 0444);
>+
> /**
> * DOC: discovery (int)
> * Allow driver to discover hardware IP information from IP Discovery table at
>the top of VRAM.
>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
>b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
>index 2f53fa0ae9a6..ca0e17688bdf 100644
>--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
>+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
>@@ -236,7 +236,8 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring,
>unsigned num_ibs,
>
> for (i = 0; i < num_ibs; ++i) {
> ib = [i];
>-
>+if (!amdgpu_sriov_mcbp)
>+ib->flags &= ~AMDGPU_IB_FLAG_PREEMPT;
> /* drop preamble IBs if we don't have a context switch */ if ((ib->flags &
>AMDGPU_IB_FLAG_PREAMBLE) &&
> skip_preamble &&
>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>index d7f37cb92a97..156e76a5a6e0 100644
>--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>@@ -742,7 +742,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev,
>void *data, struct drm_file dev_info.ids_flags = 0; if (adev->flags &
>AMD_IS_APU) dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION; -if
>(amdgpu_mcbp || amdgpu_sriov_vf(adev))
>+if (amdgpu_mcbp || (amdgpu_sriov_vf(adev) && amdgpu_sriov_mcbp))
> dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION; if
>(amdgpu_is_tmz(adev)) dev_info.ids_flags |= AMDGPU_IDS_FLAGS_TMZ;
>--
>2.25.1
>
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