[PATCH 3/3] drm/amd/amdkfd: Surface files in Sysfs to allow users to get number of compute units that are in use.
[Why]
Allow user to know how many compute units (CU) are in use at any given
moment.
[How]
Surface files in Sysfs that allow user to determine the number of compute
units that are in use for a given process. One Sysfs file is used per
device.
Signed-off-by: Ramesh Errabolu
---
drivers/gpu/drm/amd/amdkfd/kfd_priv.h| 25 +
drivers/gpu/drm/amd/amdkfd/kfd_process.c | 68 +++-
2 files changed, 92 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
index 56f92cfff591..3df2b9936458 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
@@ -705,6 +705,31 @@ struct kfd_process_device {
struct kobject *kobj_stats;
unsigned int doorbell_index;
+
+ /*
+* @cu_occupancy: Reports occupancy of Compute Units (CU) of a process
+* that is associated with device encoded by "this" struct instance. The
+* value reflects CU usage by all of the waves launched by this process
+* on this device. A very important property of occupancy parameter is
+* that its value is a a snapshot of current use.
+*
+* Following is to be noted regarding how this parameter is reported:
+*
+* The number of waves that a CU can launch is limited by couple of
+* parameters. These are encoded by struct amdgpu_cu_info instance
+* that is part of every device definition. For GFX9 devices this
+* translates to 40 waves (simd_per_cu * max_waves_per_simd) when waves
+* do not use scratch memory and 32 waves (max_scratch_slots_per_cu)
+* when they use. This could change for future devices and therefore
+* this example should be considered as a guide.
+*
+* All CU's of a device are available for the process. This may not be
true
+* under certain conditions - e.g. CU masking.
+*
+* Finally number of CU's that are occupied by a process is affected
by both
+* number of CU's a device has along with number of other competing
processes
+*/
+ struct attribute attr_cu_occupancy;
};
#define qpd_to_pdd(x) container_of(x, struct kfd_process_device, qpd)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
index 17d909c86f50..26b716b5eb23 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
@@ -249,6 +249,52 @@ static void kfd_sdma_activity_worker(struct work_struct
*work)
}
}
+/**
+ * @kfd_get_cu_occupancy() - Collect number of waves in-flight on this device
+ * by current process. Translates acquired wave count into number of compute
units
+ * that are occupied.
+ *
+ * @atr: Handle of attribute that allows reporting of wave count. The attribute
+ * handle encapsulates GPU device it is associated with, thereby allowing
collection
+ * of waves in flight, etc
+ *
+ * @buffer: Handle of user provided buffer updated with wave count
+ *
+ * Return: Number of bytes written to user buffer or an error value
+ */
+static int kfd_get_cu_occupancy(struct attribute *attr, char *buffer)
+{
+ int cu_cnt;
+ int wave_cnt;
+ int max_waves_per_cu;
+ struct kfd_dev *dev = NULL;
+ struct kfd_process *proc = NULL;
+ struct kfd_process_device *pdd = NULL;
+
+ pdd = container_of(attr, struct kfd_process_device, attr_cu_occupancy);
+ dev = pdd->dev;
+ if (dev->kfd2kgd->get_cu_occupancy == NULL)
+ return -EINVAL;
+
+ cu_cnt = 0;
+ proc = pdd->process;
+ if (pdd->qpd.queue_count == 0) {
+ pr_debug("Gpu-Id: %d has no active queues for process %d\n",
+dev->id, proc->pasid);
+ return snprintf(buffer, PAGE_SIZE, "%d\n", cu_cnt);
+ }
+
+ /* Collect wave count from device if it supports */
+ wave_cnt = 0;
+ max_waves_per_cu = 0;
+ dev->kfd2kgd->get_cu_occupancy(dev->kgd, proc->pasid, _cnt,
+ _waves_per_cu);
+
+ /* Translate wave count to number of compute units */
+ cu_cnt = (wave_cnt + (max_waves_per_cu - 1)) / max_waves_per_cu;
+ return snprintf(buffer, PAGE_SIZE, "%d\n", cu_cnt);
+}
+
static ssize_t kfd_procfs_show(struct kobject *kobj, struct attribute *attr,
char *buffer)
{
@@ -344,6 +390,7 @@ static ssize_t kfd_procfs_queue_show(struct kobject *kobj,
return 0;
}
+
static ssize_t kfd_procfs_stats_show(struct kobject *kobj,
struct attribute *attr, char *buffer)
{
@@ -359,6 +406,10 @@ static ssize_t kfd_procfs_stats_show(struct kobject *kobj,
PAGE_SIZE,
"%llu\n",
jiffies64_to_msecs(evict_jiffies));
+
+ /* Sysfs handle that gets CU occupancy is
[PATCH 2/3] drm/amd/amdgpu: Define and implement a function that collects number of waves that are in flight.
[Why]
Allow user to know how many compute units (CU) are in use at any given
moment.
[How]
Read registers of SQ that give number of waves that are in flight
of various queues. Use this information to determine number of CU's
in use.
Signed-off-by: Ramesh Errabolu
---
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 176 +-
.../gpu/drm/amd/include/kgd_kfd_interface.h | 12 ++
2 files changed, 187 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
index e6aede725197..87d4c8855805 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
@@ -38,7 +38,7 @@
#include "soc15d.h"
#include "mmhub_v1_0.h"
#include "gfxhub_v1_0.h"
-
+#include "gfx_v9_0.h"
enum hqd_dequeue_request_type {
NO_ACTION = 0,
@@ -706,6 +706,179 @@ void kgd_gfx_v9_set_vm_context_page_table_base(struct
kgd_dev *kgd,
gfxhub_v1_0_setup_vm_pt_regs(adev, vmid, page_table_base);
}
+static void lock_spi_csq_mutexes(struct amdgpu_device *adev)
+{
+ mutex_lock(>srbm_mutex);
+ mutex_lock(>grbm_idx_mutex);
+
+}
+
+static void unlock_spi_csq_mutexes(struct amdgpu_device *adev)
+{
+ mutex_unlock(>grbm_idx_mutex);
+ mutex_unlock(>srbm_mutex);
+}
+
+/**
+ * @get_wave_count: Read device registers to get number of waves in flight for
+ * a particulare queue. The method also returns the VMID associated with the
+ * queue.
+ *
+ * @adev: Handle of device whose registers are to be read
+ * @queue_idx: Index of queue in the queue-map bit-field
+ * @wave_cnt: Output parameter updated with number of waves in flight
+ * @vmid: Output parameter updated with VMID of queue whose wave count
+ * is being collected
+ */
+static void get_wave_count(struct amdgpu_device *adev, int queue_idx,
+ int *wave_cnt, int *vmid)
+{
+ int pipe_idx;
+ int queue_slot;
+ unsigned int reg_val;
+
+ /*
+* Program GRBM with appropriate MEID, PIPEID, QUEUEID and VMID
+* parameters to read out waves in flight. Get VMID if there are
+* non-zero waves in flight.
+*/
+ *vmid = 0xFF;
+ *wave_cnt = 0;
+ pipe_idx = queue_idx / adev->gfx.mec.num_queue_per_pipe;
+ queue_slot = queue_idx % adev->gfx.mec.num_queue_per_pipe;
+ soc15_grbm_select(adev, 1, pipe_idx, queue_slot, 0);
+ reg_val = RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_CSQ_WF_ACTIVE_COUNT_0) +
+queue_slot);
+ *wave_cnt = reg_val & SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK;
+ if (*wave_cnt != 0)
+ *vmid = (RREG32_SOC15(GC, 0, mmCP_HQD_VMID) &
+CP_HQD_VMID__VMID_MASK) >> CP_HQD_VMID__VMID__SHIFT;
+}
+
+/**
+ * @kgd_gfx_v9_get_cu_occupancy: Reads relevant registers associated with each
+ * shader engine and aggregates the number of waves that are in fight for the
+ * process whose pasid is provided as a parameter. The process could have ZERO
+ * or more queues running and submitting waves to compute units.
+ *
+ * @kgd: Handle of device from which to get number of waves in flight
+ * @pasid: Identifies the process for which this query call is invoked
+ * @wave_cnt: Output parameter updated with number of waves in flight that
+ * belong to process with given pasid
+ * @max_waves_per_cu: Output parameter updated with maximum number of waves
+ * possible per Compute Unit
+ *
+ * @note: It's possible that the device has too many queues (oversubscription)
+ * in which case a VMID could be remapped to a different PASID. This could lead
+ * to in accurate wave count. Following is a high-level sequence:
+ *Time T1: vmid = getVmid(); vmid is associated with Pasid P1
+ *Time T2: passId = getPasId(vmid); vmid is associated with Pasid P2
+ * In the sequence above wave count obtained from time T1 will be incorrectly
+ * lost or added to total wave count.
+ *
+ * The registers that provide the waves in flight are:
+ *
+ * SPI_CSQ_WF_ACTIVE_STATUS - bit-map of queues per pipe. The bit is ON if a
+ * queue is slotted, OFF if there is no queue. A process could have ZERO or
+ * more queues slotted and submitting waves to be run on compute units. Even
+ * when there is a queue it is possible there could be zero wave fronts, this
+ * can happen when queue is waiting on top-of-pipe events - e.g. waitRegMem
+ * command
+ *
+ * For each bit that is ON from above:
+ *
+ *Read (SPI_CSQ_WF_ACTIVE_COUNT_0 + queue_idx) register. It provides the
+ *number of waves that are in flight for the queue at specified index. The
+ *index ranges from 0 to 7.
+ *
+ *If non-zero waves are in fligth, read CP_HQD_VMID register to obtain VMID
+ *of the wave(s).
+ *
+ *Determine if VMID from above step maps to pasid provided as parameter. If
+ *it matches agrregate the wave count. That the VMID will not match pasid
is
+ *a normal condition i.e. a
[PATCH 1/3] drm/amd/amdgpu: Prepare implementation to support reporting of CU usage
[Why]
Allow user to know number of compute units (CU) that are in use at any
given moment.
[How]
Read registers of SQ that give number of waves that are in flight
of various queues. Use this information to determine number of CU's
in use.
Signed-off-by: Ramesh Errabolu
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 11 ++-
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.h | 5 +
2 files changed, 7 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 346d8288f6ab..75a17a4007ef 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -49,6 +49,7 @@
#include "amdgpu_ras.h"
#include "gfx_v9_4.h"
+#include "gfx_v9_0.h"
#include "asic_reg/pwr/pwr_10_0_offset.h"
#include "asic_reg/pwr/pwr_10_0_sh_mask.h"
@@ -785,10 +786,9 @@ static void gfx_v9_0_set_ring_funcs(struct amdgpu_device
*adev);
static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev);
static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev);
static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev);
-static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
- struct amdgpu_cu_info *cu_info);
static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev);
-static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32
sh_num, u32 instance);
+static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
+ struct amdgpu_cu_info *cu_info);
static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring);
static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring);
static int gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev,
@@ -2397,7 +2397,8 @@ static void gfx_v9_0_tiling_mode_table_init(struct
amdgpu_device *adev)
/* TODO */
}
-static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32
sh_num, u32 instance)
+void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num,
+ u32 instance)
{
u32 data;
@@ -6924,7 +6925,7 @@ static u32 gfx_v9_0_get_cu_active_bitmap(struct
amdgpu_device *adev)
}
static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
-struct amdgpu_cu_info *cu_info)
+struct amdgpu_cu_info *cu_info)
{
int i, j, k, counter, active_cu_number = 0;
u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.h
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.h
index fa5a3fbaf6ab..37eba971acb1 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.h
@@ -26,9 +26,6 @@
extern const struct amdgpu_ip_block_version gfx_v9_0_ip_block;
-void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num);
-
-uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev);
-int gfx_v9_0_get_cu_info(struct amdgpu_device *adev, struct amdgpu_cu_info
*cu_info);
+void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num,
u32 instance);
#endif
--
2.27.0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amd/pm: fix screen flicker seen on Navi14 with 2*4K monitors
On Fri, Sep 25, 2020 at 5:13 PM Matt Coffin wrote:
>
> Thanks for the quick reply,
>
> Would it make sense, since there seem to be issues with both
> before/after initialization, to (temporarily?) add a module parameter
> for users so that they can switch between these two behaviors easily
> based on what works for them?
I'd rather work on a proper fix. module options tend to lead to more
problems than they solve as people tend blindly apply them.
Alex
>
> If so, if you can toss me a hint at what name for the param would make
> sense, I can take a crack at a patch for it, for debugging by the people
> in the issue on GitLab.
>
> Cheers, and thanks for the time,
> Matt
>
> GL issue for reference:
> https://gitlab.freedesktop.org/drm/amd/-/issues/1260
>
> On 9/25/20 3:09 PM, Alex Deucher wrote:
> > On Fri, Sep 25, 2020 at 5:05 PM Matt Coffin wrote:
> >>
> >> Sorry to bother you guys, but trying to learn about some of these
> >> things, and I'm tracking the issue this relates to pretty closely on
> >> GitLab.
> >>
> >> What does DAL stand for in this context?
> >
> > DAL is the name of the display team within AMD.
> >
> > Alex
> >
> >>
> >> Thanks in advance for the help,
> >> Matt
> >>
> >> On 9/24/20 9:38 PM, Quan, Evan wrote:
> >>> [AMD Official Use Only - Internal Distribution Only]
> >>>
> >>> That(postpone SOCCLK/UCLK enablement) will be revised and added back
> >>> after confirmed with DAL team.
> >>> For now, we just revert it to get around the screen flicker issue
> >>> introduced.
> >>>
> >>> BR
> >>> Evan
> >>> -Original Message-
> >>> From: Alex Deucher
> >>> Sent: Thursday, September 24, 2020 9:01 PM
> >>> To: Quan, Evan
> >>> Cc: amd-gfx list ; Deucher, Alexander
> >>>
> >>> Subject: Re: [PATCH] drm/amd/pm: fix screen flicker seen on Navi14 with
> >>> 2*4K monitors
> >>>
> >>> On Thu, Sep 24, 2020 at 6:10 AM Evan Quan wrote:
>
> Revert the guilty change introduced by the commit below:
> drm/amd/pm: postpone SOCCLK/UCLK enablement after DAL
> initialization(V2)
>
> Change-Id: I0cab619ffdf0f83b14ba5d2907e1b9c02a984e2f
> Signed-off-by: Evan Quan
> >>>
> >>> Won't this effectively disable the potential fix for multiple monitors at
> >>> boot time?
> >>>
> >>> Acked-by: Alex Deucher
> >>>
> ---
> .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 43 ++-
> 1 file changed, 12 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> index 1695b36dc23c..be44cb941e73 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> @@ -316,6 +316,18 @@ navi10_get_allowed_feature_mask(struct smu_context
> *smu,
> if (smu->dc_controlled_by_gpio)
> *(uint64_t *)feature_mask |=
> FEATURE_MASK(FEATURE_ACDC_BIT);
>
> + if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
> + *(uint64_t *)feature_mask |=
> + FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
> +
> + /* DPM UCLK enablement should be skipped for navi10 A0 secure
> board */
> + if (!(is_asic_secure(smu) &&
> +(adev->asic_type == CHIP_NAVI10) &&
> +(adev->rev_id == 0)) &&
> + (adev->pm.pp_feature & PP_MCLK_DPM_MASK))
> + *(uint64_t *)feature_mask |=
> FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
> + |
> FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
> + |
> + FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
> +
> /* DS SOCCLK enablement should be skipped for navi10 A0 secure
> board */
> if (is_asic_secure(smu) &&
> (adev->asic_type == CHIP_NAVI10) && @@ -2629,43 +2641,12
> @@ static int navi10_enable_mgpu_fan_boost(struct smu_context *smu)
>
> static int navi10_post_smu_init(struct smu_context *smu) {
> - struct smu_feature *feature = >smu_feature;
> struct amdgpu_device *adev = smu->adev;
> - uint64_t feature_mask = 0;
> int ret = 0;
>
> if (amdgpu_sriov_vf(adev))
> return 0;
>
> - /* For Naiv1x, enable these features only after DAL
> initialization */
> - if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
> - feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
> -
> - /* DPM UCLK enablement should be skipped for navi10 A0 secure
> board */
> - if (!(is_asic_secure(smu) &&
> -(adev->asic_type == CHIP_NAVI10) &&
> -(adev->rev_id == 0)) &&
> - (adev->pm.pp_feature & PP_MCLK_DPM_MASK))
> - feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
> -
Re: [PATCH] drm/amdgpu/dc: Pixel encoding DRM property and module parameter
On Tue, Sep 22, 2020 at 4:51 PM James Ettle wrote: > > On 22/09/2020 21:33, Alex Deucher wrote: > >> +/** > >> + * DOC: pixel_encoding (string) > >> + * Specify the initial pixel encoding used by a connector. > >> + */ > >> +static char amdgpu_pixel_encoding[MAX_INPUT]; > >> +MODULE_PARM_DESC(pixel_encoding, "Override pixel encoding"); > >> +module_param_string(pixel_encoding, amdgpu_pixel_encoding, > >> sizeof(amdgpu_pixel_encoding), 0444); > > > > You can drop this part. We don't need a module parameter if we have a > > kms property. > > > > Alex > > OK, but is there then an alternative means of setting the pixel encoding to > be used immediately on boot or when amdgpu loads? Also are there user tools > other than xrandr to change a KMS property, for Wayland and console users? You can force some things on the kernel command line, but I don't recall whether that includes kms properties or not. As for ways to change properties, the KMS API provides a way. those are exposed via randr when using X. When using wayland compositors, it depends on the compositor. Alex ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amd/pm: fix screen flicker seen on Navi14 with 2*4K monitors
Thanks for the quick reply,
Would it make sense, since there seem to be issues with both
before/after initialization, to (temporarily?) add a module parameter
for users so that they can switch between these two behaviors easily
based on what works for them?
If so, if you can toss me a hint at what name for the param would make
sense, I can take a crack at a patch for it, for debugging by the people
in the issue on GitLab.
Cheers, and thanks for the time,
Matt
GL issue for reference:
https://gitlab.freedesktop.org/drm/amd/-/issues/1260
On 9/25/20 3:09 PM, Alex Deucher wrote:
> On Fri, Sep 25, 2020 at 5:05 PM Matt Coffin wrote:
>>
>> Sorry to bother you guys, but trying to learn about some of these
>> things, and I'm tracking the issue this relates to pretty closely on GitLab.
>>
>> What does DAL stand for in this context?
>
> DAL is the name of the display team within AMD.
>
> Alex
>
>>
>> Thanks in advance for the help,
>> Matt
>>
>> On 9/24/20 9:38 PM, Quan, Evan wrote:
>>> [AMD Official Use Only - Internal Distribution Only]
>>>
>>> That(postpone SOCCLK/UCLK enablement) will be revised and added back after
>>> confirmed with DAL team.
>>> For now, we just revert it to get around the screen flicker issue
>>> introduced.
>>>
>>> BR
>>> Evan
>>> -Original Message-
>>> From: Alex Deucher
>>> Sent: Thursday, September 24, 2020 9:01 PM
>>> To: Quan, Evan
>>> Cc: amd-gfx list ; Deucher, Alexander
>>>
>>> Subject: Re: [PATCH] drm/amd/pm: fix screen flicker seen on Navi14 with
>>> 2*4K monitors
>>>
>>> On Thu, Sep 24, 2020 at 6:10 AM Evan Quan wrote:
Revert the guilty change introduced by the commit below:
drm/amd/pm: postpone SOCCLK/UCLK enablement after DAL
initialization(V2)
Change-Id: I0cab619ffdf0f83b14ba5d2907e1b9c02a984e2f
Signed-off-by: Evan Quan
>>>
>>> Won't this effectively disable the potential fix for multiple monitors at
>>> boot time?
>>>
>>> Acked-by: Alex Deucher
>>>
---
.../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 43 ++-
1 file changed, 12 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index 1695b36dc23c..be44cb941e73 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -316,6 +316,18 @@ navi10_get_allowed_feature_mask(struct smu_context
*smu,
if (smu->dc_controlled_by_gpio)
*(uint64_t *)feature_mask |=
FEATURE_MASK(FEATURE_ACDC_BIT);
+ if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
+ *(uint64_t *)feature_mask |=
+ FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
+
+ /* DPM UCLK enablement should be skipped for navi10 A0 secure
board */
+ if (!(is_asic_secure(smu) &&
+(adev->asic_type == CHIP_NAVI10) &&
+(adev->rev_id == 0)) &&
+ (adev->pm.pp_feature & PP_MCLK_DPM_MASK))
+ *(uint64_t *)feature_mask |=
FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
+ |
FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
+ |
+ FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
+
/* DS SOCCLK enablement should be skipped for navi10 A0 secure
board */
if (is_asic_secure(smu) &&
(adev->asic_type == CHIP_NAVI10) && @@ -2629,43 +2641,12
@@ static int navi10_enable_mgpu_fan_boost(struct smu_context *smu)
static int navi10_post_smu_init(struct smu_context *smu) {
- struct smu_feature *feature = >smu_feature;
struct amdgpu_device *adev = smu->adev;
- uint64_t feature_mask = 0;
int ret = 0;
if (amdgpu_sriov_vf(adev))
return 0;
- /* For Naiv1x, enable these features only after DAL initialization
*/
- if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
- feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
-
- /* DPM UCLK enablement should be skipped for navi10 A0 secure
board */
- if (!(is_asic_secure(smu) &&
-(adev->asic_type == CHIP_NAVI10) &&
-(adev->rev_id == 0)) &&
- (adev->pm.pp_feature & PP_MCLK_DPM_MASK))
- feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
- |
FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
- |
FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
-
- if (!feature_mask)
- return 0;
-
- bitmap_or(feature->allowed,
- feature->allowed,
- (unsigned long *)(_mask),
- SMU_FEATURE_MAX);
-
-
Re: [PATCH] drm/amd/pm: fix screen flicker seen on Navi14 with 2*4K monitors
On Fri, Sep 25, 2020 at 5:05 PM Matt Coffin wrote:
>
> Sorry to bother you guys, but trying to learn about some of these
> things, and I'm tracking the issue this relates to pretty closely on GitLab.
>
> What does DAL stand for in this context?
DAL is the name of the display team within AMD.
Alex
>
> Thanks in advance for the help,
> Matt
>
> On 9/24/20 9:38 PM, Quan, Evan wrote:
> > [AMD Official Use Only - Internal Distribution Only]
> >
> > That(postpone SOCCLK/UCLK enablement) will be revised and added back after
> > confirmed with DAL team.
> > For now, we just revert it to get around the screen flicker issue
> > introduced.
> >
> > BR
> > Evan
> > -Original Message-
> > From: Alex Deucher
> > Sent: Thursday, September 24, 2020 9:01 PM
> > To: Quan, Evan
> > Cc: amd-gfx list ; Deucher, Alexander
> >
> > Subject: Re: [PATCH] drm/amd/pm: fix screen flicker seen on Navi14 with
> > 2*4K monitors
> >
> > On Thu, Sep 24, 2020 at 6:10 AM Evan Quan wrote:
> >>
> >> Revert the guilty change introduced by the commit below:
> >> drm/amd/pm: postpone SOCCLK/UCLK enablement after DAL
> >> initialization(V2)
> >>
> >> Change-Id: I0cab619ffdf0f83b14ba5d2907e1b9c02a984e2f
> >> Signed-off-by: Evan Quan
> >
> > Won't this effectively disable the potential fix for multiple monitors at
> > boot time?
> >
> > Acked-by: Alex Deucher
> >
> >> ---
> >> .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 43 ++-
> >> 1 file changed, 12 insertions(+), 31 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> >> b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> >> index 1695b36dc23c..be44cb941e73 100644
> >> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> >> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> >> @@ -316,6 +316,18 @@ navi10_get_allowed_feature_mask(struct smu_context
> >> *smu,
> >> if (smu->dc_controlled_by_gpio)
> >> *(uint64_t *)feature_mask |=
> >> FEATURE_MASK(FEATURE_ACDC_BIT);
> >>
> >> + if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
> >> + *(uint64_t *)feature_mask |=
> >> + FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
> >> +
> >> + /* DPM UCLK enablement should be skipped for navi10 A0 secure
> >> board */
> >> + if (!(is_asic_secure(smu) &&
> >> +(adev->asic_type == CHIP_NAVI10) &&
> >> +(adev->rev_id == 0)) &&
> >> + (adev->pm.pp_feature & PP_MCLK_DPM_MASK))
> >> + *(uint64_t *)feature_mask |=
> >> FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
> >> + |
> >> FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
> >> + |
> >> + FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
> >> +
> >> /* DS SOCCLK enablement should be skipped for navi10 A0 secure
> >> board */
> >> if (is_asic_secure(smu) &&
> >> (adev->asic_type == CHIP_NAVI10) && @@ -2629,43 +2641,12
> >> @@ static int navi10_enable_mgpu_fan_boost(struct smu_context *smu)
> >>
> >> static int navi10_post_smu_init(struct smu_context *smu) {
> >> - struct smu_feature *feature = >smu_feature;
> >> struct amdgpu_device *adev = smu->adev;
> >> - uint64_t feature_mask = 0;
> >> int ret = 0;
> >>
> >> if (amdgpu_sriov_vf(adev))
> >> return 0;
> >>
> >> - /* For Naiv1x, enable these features only after DAL initialization
> >> */
> >> - if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
> >> - feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
> >> -
> >> - /* DPM UCLK enablement should be skipped for navi10 A0 secure
> >> board */
> >> - if (!(is_asic_secure(smu) &&
> >> -(adev->asic_type == CHIP_NAVI10) &&
> >> -(adev->rev_id == 0)) &&
> >> - (adev->pm.pp_feature & PP_MCLK_DPM_MASK))
> >> - feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
> >> - |
> >> FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
> >> - |
> >> FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
> >> -
> >> - if (!feature_mask)
> >> - return 0;
> >> -
> >> - bitmap_or(feature->allowed,
> >> - feature->allowed,
> >> - (unsigned long *)(_mask),
> >> - SMU_FEATURE_MAX);
> >> -
> >> - ret = smu_cmn_feature_update_enable_state(smu,
> >> - feature_mask,
> >> - true);
> >> - if (ret) {
> >> - dev_err(adev->dev, "Failed to post uclk/socclk dpm
> >> enablement!\n");
> >> - return ret;
> >> - }
> >> -
> >> ret = navi10_run_umc_cdr_workaround(smu);
> >> if (ret) {
> >> dev_err(adev->dev, "Failed to apply umc cdr
> >> workaround!\n");
> >> --
> >> 2.28.0
> >>
> >> ___
> >> amd-gfx
Re: [PATCH] drm/amd/pm: fix screen flicker seen on Navi14 with 2*4K monitors
Sorry to bother you guys, but trying to learn about some of these
things, and I'm tracking the issue this relates to pretty closely on GitLab.
What does DAL stand for in this context?
Thanks in advance for the help,
Matt
On 9/24/20 9:38 PM, Quan, Evan wrote:
> [AMD Official Use Only - Internal Distribution Only]
>
> That(postpone SOCCLK/UCLK enablement) will be revised and added back after
> confirmed with DAL team.
> For now, we just revert it to get around the screen flicker issue introduced.
>
> BR
> Evan
> -Original Message-
> From: Alex Deucher
> Sent: Thursday, September 24, 2020 9:01 PM
> To: Quan, Evan
> Cc: amd-gfx list ; Deucher, Alexander
>
> Subject: Re: [PATCH] drm/amd/pm: fix screen flicker seen on Navi14 with 2*4K
> monitors
>
> On Thu, Sep 24, 2020 at 6:10 AM Evan Quan wrote:
>>
>> Revert the guilty change introduced by the commit below:
>> drm/amd/pm: postpone SOCCLK/UCLK enablement after DAL
>> initialization(V2)
>>
>> Change-Id: I0cab619ffdf0f83b14ba5d2907e1b9c02a984e2f
>> Signed-off-by: Evan Quan
>
> Won't this effectively disable the potential fix for multiple monitors at
> boot time?
>
> Acked-by: Alex Deucher
>
>> ---
>> .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 43 ++-
>> 1 file changed, 12 insertions(+), 31 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
>> b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
>> index 1695b36dc23c..be44cb941e73 100644
>> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
>> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
>> @@ -316,6 +316,18 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
>> if (smu->dc_controlled_by_gpio)
>> *(uint64_t *)feature_mask |=
>> FEATURE_MASK(FEATURE_ACDC_BIT);
>>
>> + if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
>> + *(uint64_t *)feature_mask |=
>> + FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
>> +
>> + /* DPM UCLK enablement should be skipped for navi10 A0 secure board
>> */
>> + if (!(is_asic_secure(smu) &&
>> +(adev->asic_type == CHIP_NAVI10) &&
>> +(adev->rev_id == 0)) &&
>> + (adev->pm.pp_feature & PP_MCLK_DPM_MASK))
>> + *(uint64_t *)feature_mask |=
>> FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
>> + | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
>> + |
>> + FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
>> +
>> /* DS SOCCLK enablement should be skipped for navi10 A0 secure board
>> */
>> if (is_asic_secure(smu) &&
>> (adev->asic_type == CHIP_NAVI10) && @@ -2629,43 +2641,12
>> @@ static int navi10_enable_mgpu_fan_boost(struct smu_context *smu)
>>
>> static int navi10_post_smu_init(struct smu_context *smu) {
>> - struct smu_feature *feature = >smu_feature;
>> struct amdgpu_device *adev = smu->adev;
>> - uint64_t feature_mask = 0;
>> int ret = 0;
>>
>> if (amdgpu_sriov_vf(adev))
>> return 0;
>>
>> - /* For Naiv1x, enable these features only after DAL initialization */
>> - if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
>> - feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
>> -
>> - /* DPM UCLK enablement should be skipped for navi10 A0 secure board
>> */
>> - if (!(is_asic_secure(smu) &&
>> -(adev->asic_type == CHIP_NAVI10) &&
>> -(adev->rev_id == 0)) &&
>> - (adev->pm.pp_feature & PP_MCLK_DPM_MASK))
>> - feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
>> - | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
>> - | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
>> -
>> - if (!feature_mask)
>> - return 0;
>> -
>> - bitmap_or(feature->allowed,
>> - feature->allowed,
>> - (unsigned long *)(_mask),
>> - SMU_FEATURE_MAX);
>> -
>> - ret = smu_cmn_feature_update_enable_state(smu,
>> - feature_mask,
>> - true);
>> - if (ret) {
>> - dev_err(adev->dev, "Failed to post uclk/socclk dpm
>> enablement!\n");
>> - return ret;
>> - }
>> -
>> ret = navi10_run_umc_cdr_workaround(smu);
>> if (ret) {
>> dev_err(adev->dev, "Failed to apply umc cdr
>> workaround!\n");
>> --
>> 2.28.0
>>
>> ___
>> amd-gfx mailing list
>> amd-gfx@lists.freedesktop.org
>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flist
>> s.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfxdata=02%7C01%7Cev
>> an.quan%40amd.com%7C3899143b7990458f882c08d86089df67%7C3dd8961fe4884e6
>> 08e11a82d994e183d%7C0%7C0%7C637365492561293539sdata=J%2FM6YSLX6d%
>>
[PATCH 35/45] drm/amdgpu: add TOC firmware definition
From: Huang Rui
This patch is to add TOC firmware definition on uapi.
Signed-off-by: Huang Rui
Acked-by: Alex Deucher
Signed-off-by: Alex Deucher
---
include/uapi/drm/amdgpu_drm.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index d98d4e6f311b..64ae821b01ef 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -727,6 +727,8 @@ struct drm_amdgpu_cs_chunk_data {
#define AMDGPU_INFO_FW_TA 0x13
/* Subquery id: Query DMCUB firmware version */
#define AMDGPU_INFO_FW_DMCUB0x14
+ /* Subquery id: Query TOC firmware version */
+ #define AMDGPU_INFO_FW_TOC 0x15
/* number of bytes moved for TTM migration */
#define AMDGPU_INFO_NUM_BYTES_MOVED0x0f
--
2.25.4
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[PATCH 33/45] drm/amd/powerplay: add vangogh ppt into swSMU
From: Huang Rui This patch is to add vangogh ppt funcions into swSMU block. Signed-off-by: Huang Rui Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 4 drivers/gpu/drm/amd/pm/swsmu/smu11/Makefile | 1 + 2 files changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 5534125f1df3..d4cc2825d364 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -33,6 +33,7 @@ #include "navi10_ppt.h" #include "sienna_cichlid_ppt.h" #include "renoir_ppt.h" +#include "vangogh_ppt.h" #include "amd_pcie.h" /* @@ -401,6 +402,9 @@ static int smu_set_funcs(struct amdgpu_device *adev) case CHIP_RENOIR: renoir_set_ppt_funcs(smu); break; + case CHIP_VANGOGH: + vangogh_set_ppt_funcs(smu); + break; default: return -EINVAL; } diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/Makefile b/drivers/gpu/drm/amd/pm/swsmu/smu11/Makefile index f98d97192635..0138c982dfd3 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/Makefile +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/Makefile @@ -26,6 +26,7 @@ SMU11_MGR = arcturus_ppt.o \ navi10_ppt.o \ sienna_cichlid_ppt.o \ + vangogh_ppt.o \ smu_v11_0.o AMD_SWSMU_SMU11MGR = $(addprefix $(AMD_SWSMU_PATH)/smu11/,$(SMU11_MGR)) -- 2.25.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 37/45] drm/amdgpu: enable psp support for vangogh
From: Huang Rui
This patch is to enable psp support for vangogh
Signed-off-by: Huang Rui
Acked-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 3 +--
drivers/gpu/drm/amd/amdgpu/nv.c | 2 ++
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c| 5 +
4 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index c8cec7ab499d..574392fcd503 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -100,6 +100,7 @@ static int psp_early_init(void *handle)
case CHIP_NAVI12:
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ case CHIP_VANGOGH:
psp_v11_0_set_psp_funcs(psp);
psp->autoload_supported = true;
break;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index 3f791ca73ff7..676405171a4c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -391,12 +391,11 @@ amdgpu_ucode_get_load_type(struct amdgpu_device *adev,
int load_type)
case CHIP_NAVI12:
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ case CHIP_VANGOGH:
if (!load_type)
return AMDGPU_FW_LOAD_DIRECT;
else
return AMDGPU_FW_LOAD_PSP;
- case CHIP_VANGOGH:
- return AMDGPU_FW_LOAD_DIRECT;
default:
DRM_ERROR("Unknown firmware load type\n");
}
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 4fbf3f6640e6..568e33b7fda8 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -644,6 +644,8 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, _common_ip_block);
amdgpu_device_ip_block_add(adev, _v10_0_ip_block);
amdgpu_device_ip_block_add(adev, _ih_ip_block);
+ if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
+ amdgpu_device_ip_block_add(adev, _v11_0_ip_block);
amdgpu_device_ip_block_add(adev, _v11_0_ip_block);
if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
amdgpu_device_ip_block_add(adev, _virtual_ip_block);
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index f2d6b2518eee..d6ba6ea9a8fc 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -59,6 +59,8 @@ MODULE_FIRMWARE("amdgpu/sienna_cichlid_sos.bin");
MODULE_FIRMWARE("amdgpu/sienna_cichlid_ta.bin");
MODULE_FIRMWARE("amdgpu/navy_flounder_sos.bin");
MODULE_FIRMWARE("amdgpu/navy_flounder_ta.bin");
+MODULE_FIRMWARE("amdgpu/vangogh_asd.bin");
+MODULE_FIRMWARE("amdgpu/vangogh_toc.bin");
/* address block */
#define smnMP1_FIRMWARE_FLAGS 0x3010024
@@ -105,6 +107,9 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
case CHIP_NAVY_FLOUNDER:
chip_name = "navy_flounder";
break;
+ case CHIP_VANGOGH:
+ chip_name = "vangogh";
+ break;
default:
BUG();
}
--
2.25.4
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[PATCH 41/45] drm/amdgpu: add gfx power gating for gfx10
From: Huang Rui
This patch is to add power gating handle for gfx10.
Signed-off-by: Huang Rui
Acked-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 27 ++
1 file changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index fd29a6d7285b..f2849f180c91 100755
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -7583,6 +7583,30 @@ static bool gfx_v10_0_is_rlcg_access_range(struct
amdgpu_device *adev, u32 offse
return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0);
}
+static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)
+{
+ int data;
+
+ if (enable && (adev->cg_flags & AMD_PG_SUPPORT_GFX_PG)) {
+ data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
+ data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
+ WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data);
+ } else {
+ data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
+ data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
+ WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data);
+ }
+}
+
+static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable)
+{
+ amdgpu_gfx_rlc_enter_safe_mode(adev);
+
+ gfx_v10_cntl_power_gating(adev, enable);
+
+ amdgpu_gfx_rlc_exit_safe_mode(adev);
+}
+
static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
.is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
.set_safe_mode = gfx_v10_0_set_safe_mode,
@@ -7630,6 +7654,9 @@ static int gfx_v10_0_set_powergating_state(void *handle,
case CHIP_NAVY_FLOUNDER:
amdgpu_gfx_off_ctrl(adev, enable);
break;
+ case CHIP_VANGOGH:
+ gfx_v10_cntl_pg(adev, enable);
+ break;
default:
break;
}
--
2.25.4
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[PATCH 42/45] drm/amdgpu: enable gfx clock gating and power gating for vangogh
From: Huang Rui This patch is to enable the gfx cg and pg for vangogh. Signed-off-by: Huang Rui Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/nv.c | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index 4bd2e2f35fa4..67b6067f2bd3 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c @@ -919,8 +919,11 @@ static int nv_common_early_init(void *handle) break; case CHIP_VANGOGH: - adev->cg_flags = 0; - adev->pg_flags = 0; + adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG | + AMD_CG_SUPPORT_GFX_CGLS | + AMD_CG_SUPPORT_GFX_3D_CGCG | + AMD_CG_SUPPORT_GFX_3D_CGLS; + adev->pg_flags = AMD_PG_SUPPORT_GFX_PG; adev->external_rev_id = adev->rev_id + 0x01; break; default: -- 2.25.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 39/45] drm/amdgpu: IP discovery table is not ready yet for VG
Fallback to legacy path for now.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/nv.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 568e33b7fda8..4bd2e2f35fa4 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -484,6 +484,10 @@ static int nv_reg_base_init(struct amdgpu_device *adev)
{
int r;
+ /* IP discovery table is not available yet */
+ if (adev->asic_type == CHIP_VANGOGH)
+ goto legacy_init;
+
if (amdgpu_discovery) {
r = amdgpu_discovery_reg_base_init(adev);
if (r) {
--
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[PATCH 44/45] drm/amd/display: Add dcn3.01 support to DM
From: Roman Li
Update dm for vangogh support.
Signed-off-by: Roman Li
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 26 +++
1 file changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index e8177656e083..3cf4e08931bb 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -100,6 +100,10 @@ MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB);
#define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin"
MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB);
#endif
+#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
+#define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin"
+MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB);
+#endif
#define FIRMWARE_RAVEN_DMCU"amdgpu/raven_dmcu.bin"
MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
@@ -1135,6 +1139,9 @@ static int load_dmcu_fw(struct amdgpu_device *adev)
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+#endif
+#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
+ case CHIP_VANGOGH:
#endif
return 0;
case CHIP_NAVI12:
@@ -1242,6 +1249,12 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev)
fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB;
break;
#endif
+#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
+ case CHIP_VANGOGH:
+ dmub_asic = DMUB_ASIC_DCN301;
+ fw_name_dmub = FIRMWARE_VANGOGH_DMUB;
+ break;
+#endif
default:
/* ASIC doesn't support DMUB. */
@@ -3362,6 +3375,9 @@ static int amdgpu_dm_initialize_drm_device(struct
amdgpu_device *adev)
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+#endif
+#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
+ case CHIP_VANGOGH:
#endif
if (dcn10_register_irq_handlers(dm->adev)) {
DRM_ERROR("DM: Failed to initialize IRQ\n");
@@ -3609,6 +3625,13 @@ static int dm_early_init(void *handle)
adev->mode_info.num_hpd = 6;
adev->mode_info.num_dig = 6;
break;
+#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
+ case CHIP_VANGOGH:
+ adev->mode_info.num_crtc = 4;
+ adev->mode_info.num_hpd = 4;
+ adev->mode_info.num_dig = 4;
+ break;
+#endif
case CHIP_NAVI14:
adev->mode_info.num_crtc = 5;
adev->mode_info.num_hpd = 5;
@@ -3928,6 +3951,9 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev,
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
adev->asic_type == CHIP_SIENNA_CICHLID ||
adev->asic_type == CHIP_NAVY_FLOUNDER ||
+#endif
+#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
+ adev->asic_type == CHIP_VANGOGH ||
#endif
adev->asic_type == CHIP_RENOIR ||
adev->asic_type == CHIP_RAVEN) {
--
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[PATCH 29/45] drm/amdgpu/powerplay: add smu v11.5 smc header for vangogh
From: Xiaojian Du
This patch is to add smu v11.5 smc header for vangogh.
Signed-off-by: Xiaojian Du
Reviewed-by: Kevin Wang
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h | 86
1 file changed, 86 insertions(+)
create mode 100644 drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h
b/drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h
new file mode 100644
index ..55c1b151a68d
--- /dev/null
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h
@@ -0,0 +1,86 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef SMU_11_5_0_PPSMC_H
+#define SMU_11_5_0_PPSMC_H
+
+// SMU Response Codes:
+#define PPSMC_Result_OK 0x1
+#define PPSMC_Result_Failed 0xFF
+#define PPSMC_Result_UnknownCmd 0xFE
+#define PPSMC_Result_CmdRejectedPrereq 0xFD
+#define PPSMC_Result_CmdRejectedBusy 0xFC
+
+// Message Definitions:
+#define PPSMC_MSG_TestMessage 0x1
+#define PPSMC_MSG_GetSmuVersion 0x2
+#define PPSMC_MSG_GetDriverIfVersion 0x3
+#define PPSMC_MSG_EnableGfxOff 0x4
+#define PPSMC_MSG_DisableGfxOff 0x5
+#define PPSMC_MSG_PowerDownIspByTile 0x6 // ISP is power gated by default
+#define PPSMC_MSG_PowerUpIspByTile 0x7
+#define PPSMC_MSG_PowerDownVcn 0x8 // VCN is power gated by default
+#define PPSMC_MSG_PowerUpVcn 0x9
+#define PPSMC_MSG_spare 0xA
+#define PPSMC_MSG_SetHardMinVcn 0xB // For wireless display
+#define PPSMC_MSG_SetMinVideoGfxclkFreq0xC //Sets SoftMin for GFXCLK.
Arg is in MHz
+#define PPSMC_MSG_ActiveProcessNotify 0xD
+#define PPSMC_MSG_SetHardMinIspiclkByFreq 0xE
+#define PPSMC_MSG_SetHardMinIspxclkByFreq 0xF
+#define PPSMC_MSG_SetDriverDramAddrHigh 0x10
+#define PPSMC_MSG_SetDriverDramAddrLow 0x11
+#define PPSMC_MSG_TransferTableSmu2Dram 0x12
+#define PPSMC_MSG_TransferTableDram2Smu 0x13
+#define PPSMC_MSG_GfxDeviceDriverReset 0x14 //mode 2 reset during TDR
+#define PPSMC_MSG_GetEnabledSmuFeatures 0x15
+#define PPSMC_MSG_spare1 0x16
+#define PPSMC_MSG_SetHardMinSocclkByFreq 0x17
+#define PPSMC_MSG_SetMinVideoFclkFreq 0x18
+#define PPSMC_MSG_SetSoftMinVcn 0x19
+#define PPSMC_MSG_EnablePostCode 0x1A
+#define PPSMC_MSG_GetGfxclkFrequency 0x1B
+#define PPSMC_MSG_GetFclkFrequency 0x1C
+#define PPSMC_MSG_AllowGfxOff 0x1D
+#define PPSMC_MSG_DisallowGfxOff 0x1E
+#define PPSMC_MSG_SetSoftMaxGfxClk 0x1F
+#define PPSMC_MSG_SetHardMinGfxClk 0x20
+#define PPSMC_MSG_SetSoftMaxSocclkByFreq 0x21
+#define PPSMC_MSG_SetSoftMaxFclkByFreq 0x22
+#define PPSMC_MSG_SetSoftMaxVcn 0x23
+#define PPSMC_MSG_GpuChangeState 0x24 //FIXME AHOLLA - check how to do for VGM
+#define PPSMC_MSG_SetPowerLimitPercentage 0x25
+#define PPSMC_MSG_PowerDownJpeg 0x26
+#define PPSMC_MSG_PowerUpJpeg 0x27
+#define PPSMC_MSG_SetHardMinFclkByFreq 0x28
+#define PPSMC_MSG_SetSoftMinSocclkByFreq 0x29
+#define PPSMC_MSG_PowerUpCvip 0x2A
+#define PPSMC_MSG_PowerDownCvip 0x2B
+#define PPSMC_Message_Count 0x2C
+
+//Argument for PPSMC_MSG_GpuChangeState
+enum {
+ GpuChangeState_D0Entry = 1,
+ GpuChangeState_D3Entry,
+};
+
+#endif
--
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[PATCH 30/45] drm/amdgpu/powerplay: add vangogh asic name in smu v11 (v2)
From: Xiaojian Du This patch is to add vangogh asic name in smu v11. v2: drop smu firmware name (N/A for VG) Signed-off-by: Xiaojian Du Reviewed-by: Kevin Wang Reviewed-by: Huang Rui Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/inc/smu_v11_0.h | 1 + drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h index 03198d214bba..f57dc586649a 100644 --- a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h +++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h @@ -32,6 +32,7 @@ #define SMU11_DRIVER_IF_VERSION_NV14 0x36 #define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x39 #define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0x5 +#define SMU11_DRIVER_IF_VERSION_VANGOGH 0x01 /* MP Apertures */ #define MP0_Public 0x0380 diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c index d8ca6d968813..effa4391b577 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c @@ -244,6 +244,9 @@ int smu_v11_0_check_fw_version(struct smu_context *smu) case CHIP_NAVY_FLOUNDER: smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Navy_Flounder; break; + case CHIP_VANGOGH: + smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_VANGOGH; + break; default: dev_err(smu->adev->dev, "smu unsupported asic type:%d.\n", smu->adev->asic_type); smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_INV; -- 2.25.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 32/45] drm/amd/powerplay: partially enable swsmu for vangogh
From: Huang Rui This patch is to partially enable swSMU for vangogh for the moment. Signed-off-by: Huang Rui Acked-by: Alex Deucher Reviewed-by: Aaron Liu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 3010cb31324a..5534125f1df3 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -466,6 +466,9 @@ static int smu_late_init(void *handle) struct smu_context *smu = >smu; int ret = 0; + if (adev->asic_type == CHIP_VANGOGH) + return 0; + if (!smu->pm_enabled) return 0; @@ -1090,6 +1093,9 @@ static int smu_hw_init(void *handle) smu_set_gfx_cgpg(>smu, true); } + if (adev->asic_type == CHIP_VANGOGH) + return 0; + if (!smu->pm_enabled) return 0; -- 2.25.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 34/45] drm/amdgpu: add smu ip block for vangogh
From: Huang Rui This patch is to add ip block for vangogh. Signed-off-by: Huang Rui Acked-by: Alex Deucher Reviewed-by: Aaron Liu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/nv.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index 3ac89109ea3e..4fbf3f6640e6 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c @@ -644,6 +644,7 @@ int nv_set_ip_blocks(struct amdgpu_device *adev) amdgpu_device_ip_block_add(adev, _common_ip_block); amdgpu_device_ip_block_add(adev, _v10_0_ip_block); amdgpu_device_ip_block_add(adev, _ih_ip_block); + amdgpu_device_ip_block_add(adev, _v11_0_ip_block); if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) amdgpu_device_ip_block_add(adev, _virtual_ip_block); amdgpu_device_ip_block_add(adev, _v10_0_ip_block); -- 2.25.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 45/45] drm/amdgpu: add van gogh pci id
From: Huang Rui
Add Van Gogh PCI id support.
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 9ad1da52e6da..564336c2ee66 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -1088,6 +1088,9 @@ static const struct pci_device_id pciidlist[] = {
{0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
{0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
+ /* Van Gogh */
+ {0x1002, 0x163F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VANGOGH|AMD_IS_APU},
+
{0, 0, 0}
};
--
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[PATCH 31/45] drm/amdgpu/powerplay: add smu initialize funcitons for vangogh (v2)
From: Xiaojian Du
This patch is to add smu initialize functions for vangogh.
v2: squash in updates
Signed-off-by: Xiaojian Du
Reviewed-by: Kevin Wang
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 355 ++
.../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.h | 30 ++
2 files changed, 385 insertions(+)
create mode 100644 drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
create mode 100644 drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.h
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
new file mode 100644
index ..a06495126a8c
--- /dev/null
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
@@ -0,0 +1,355 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#define SWSMU_CODE_LAYER_L2
+
+#include "amdgpu.h"
+#include "amdgpu_smu.h"
+#include "smu_v11_0.h"
+#include "smu11_driver_if_vangogh.h"
+#include "vangogh_ppt.h"
+#include "smu_v11_5_ppsmc.h"
+#include "smu_v11_5_pmfw.h"
+#include "smu_cmn.h"
+
+/*
+ * DO NOT use these for err/warn/info/debug messages.
+ * Use dev_err, dev_warn, dev_info and dev_dbg instead.
+ * They are more MGPU friendly.
+ */
+#undef pr_err
+#undef pr_warn
+#undef pr_info
+#undef pr_debug
+
+#define FEATURE_MASK(feature) (1ULL << feature)
+#define SMC_DPM_FEATURE ( \
+ FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \
+ FEATURE_MASK(FEATURE_VCN_DPM_BIT)| \
+ FEATURE_MASK(FEATURE_FCLK_DPM_BIT) | \
+ FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT) | \
+ FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT) | \
+ FEATURE_MASK(FEATURE_LCLK_DPM_BIT) | \
+ FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT)| \
+ FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT)| \
+ FEATURE_MASK(FEATURE_GFX_DPM_BIT)| \
+ FEATURE_MASK(FEATURE_ISP_DPM_BIT)| \
+ FEATURE_MASK(FEATURE_A55_DPM_BIT)| \
+ FEATURE_MASK(FEATURE_CVIP_DSP_DPM_BIT))
+
+static struct cmn2asic_msg_mapping vangogh_message_map[SMU_MSG_MAX_COUNT] = {
+ MSG_MAP(TestMessage,PPSMC_MSG_TestMessage,
1),
+ MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion,
1),
+ MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion,
1),
+ MSG_MAP(AllowGfxOff,PPSMC_MSG_EnableGfxOff,
1),
+ MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisableGfxOff,
1),
+ MSG_MAP(PowerDownIspByTile, PPSMC_MSG_PowerDownIspByTile,
1),
+ MSG_MAP(PowerUpIspByTile, PPSMC_MSG_PowerUpIspByTile,
1),
+ MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn,
1),
+ MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn,
1),
+ MSG_MAP(Spare, PPSMC_MSG_spare,
1),
+ MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn,
1),
+ MSG_MAP(SetMinVideoGfxclkFreq,
PPSMC_MSG_SetMinVideoGfxclkFreq,1),
+ MSG_MAP(ActiveProcessNotify,PPSMC_MSG_ActiveProcessNotify,
1),
+ MSG_MAP(SetHardMinIspiclkByFreq,
PPSMC_MSG_SetHardMinIspiclkByFreq, 1),
+ MSG_MAP(SetHardMinIspxclkByFreq,
PPSMC_MSG_SetHardMinIspxclkByFreq, 1),
+ MSG_MAP(SetDriverDramAddrHigh,
PPSMC_MSG_SetDriverDramAddrHigh,1),
+ MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow,
1),
+ MSG_MAP(TransferTableSmu2Dram,
PPSMC_MSG_TransferTableSmu2Dram,1),
+ MSG_MAP(TransferTableDram2Smu,
PPSMC_MSG_TransferTableDram2Smu,1),
+ MSG_MAP(GfxDeviceDriverReset,
[PATCH 40/45] drm/amdgpu/mmhub2.3: print client id string for mmhub
Print the name of the client rather than the number. This
makes it easier to debug what block is causing the fault.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c | 49 ++---
1 file changed, 43 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
index b39dc2023b5f..3a248c8cd0b9 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
@@ -31,6 +31,30 @@
#include "soc15_common.h"
+static const char *mmhub_client_ids_vangogh[][2] = {
+ [0][0] = "MP0",
+ [1][0] = "MP1",
+ [2][0] = "DCEDMC",
+ [3][0] = "DCEVGA",
+ [13][0] = "UTCL2",
+ [26][0] = "OSS",
+ [27][0] = "HDP",
+ [28][0] = "VCN",
+ [29][0] = "VCNU",
+ [30][0] = "JPEG",
+ [0][1] = "MP0",
+ [1][1] = "MP1",
+ [2][1] = "DCEDMC",
+ [3][1] = "DCEVGA",
+ [4][1] = "DCEDWB",
+ [5][1] = "XDP",
+ [26][1] = "OSS",
+ [27][1] = "HDP",
+ [28][1] = "VCN",
+ [29][1] = "VCNU",
+ [30][1] = "JPEG",
+};
+
static uint32_t mmhub_v2_3_get_invalidate_req(unsigned int vmid,
uint32_t flush_type)
{
@@ -55,12 +79,27 @@ static void
mmhub_v2_3_print_l2_protection_fault_status(struct amdgpu_device *adev,
uint32_t status)
{
+ uint32_t cid, rw;
+ const char *mmhub_cid = NULL;
+
+ cid = REG_GET_FIELD(status,
+ MMVM_L2_PROTECTION_FAULT_STATUS, CID);
+ rw = REG_GET_FIELD(status,
+ MMVM_L2_PROTECTION_FAULT_STATUS, RW);
+
dev_err(adev->dev,
"MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
status);
- dev_err(adev->dev, "\t Faulty UTCL2 client ID: 0x%lx\n",
- REG_GET_FIELD(status,
- MMVM_L2_PROTECTION_FAULT_STATUS, CID));
+ switch (adev->asic_type) {
+ case CHIP_VANGOGH:
+ mmhub_cid = mmhub_client_ids_vangogh[cid][rw];
+ break;
+ default:
+ mmhub_cid = NULL;
+ break;
+ }
+ dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
+ mmhub_cid ? mmhub_cid : "unknown", cid);
dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
REG_GET_FIELD(status,
MMVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
@@ -73,9 +112,7 @@ mmhub_v2_3_print_l2_protection_fault_status(struct
amdgpu_device *adev,
dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
REG_GET_FIELD(status,
MMVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
- dev_err(adev->dev, "\t RW: 0x%lx\n",
- REG_GET_FIELD(status,
- MMVM_L2_PROTECTION_FAULT_STATUS, RW));
+ dev_err(adev->dev, "\t RW: 0x%x\n", rw);
}
static void mmhub_v2_3_setup_vm_pt_regs(struct amdgpu_device *adev,
--
2.25.4
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[PATCH 36/45] drm/amdgpu: add TOC firmware support for apu (v2)
From: Huang Rui
APU needs load toc firmware for gfx10 series on psp front door loading.
v2: rebase against latest code
Signed-off-by: Huang Rui
Acked-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 11
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 36 +
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 7 +
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 33 ---
4 files changed, 77 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index bd0d14419841..26caa8d43483 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -325,6 +325,10 @@ static int amdgpu_firmware_info(struct
drm_amdgpu_info_firmware *fw_info,
fw_info->ver = adev->dm.dmcub_fw_version;
fw_info->feature = 0;
break;
+ case AMDGPU_INFO_FW_TOC:
+ fw_info->ver = adev->psp.toc_fw_version;
+ fw_info->feature = adev->psp.toc_feature_version;
+ break;
default:
return -EINVAL;
}
@@ -1464,6 +1468,13 @@ static int amdgpu_debugfs_firmware_info(struct seq_file
*m, void *data)
seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n",
fw_info.feature, fw_info.ver);
+ /* TOC */
+ query_fw.fw_type = AMDGPU_INFO_FW_TOC;
+ ret = amdgpu_firmware_info(_info, _fw, adev);
+ if (ret)
+ return ret;
+ seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n",
+ fw_info.feature, fw_info.ver);
seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 18be544d8c1e..c8cec7ab499d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -2415,6 +2415,42 @@ int psp_init_asd_microcode(struct psp_context *psp,
return err;
}
+int psp_init_toc_microcode(struct psp_context *psp,
+ const char *chip_name)
+{
+ struct amdgpu_device *adev = psp->adev;
+ char fw_name[30];
+ const struct psp_firmware_header_v1_0 *toc_hdr;
+ int err = 0;
+
+ if (!chip_name) {
+ dev_err(adev->dev, "invalid chip name for toc microcode\n");
+ return -EINVAL;
+ }
+
+ snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name);
+ err = request_firmware(>psp.toc_fw, fw_name, adev->dev);
+ if (err)
+ goto out;
+
+ err = amdgpu_ucode_validate(adev->psp.toc_fw);
+ if (err)
+ goto out;
+
+ toc_hdr = (const struct psp_firmware_header_v1_0
*)adev->psp.toc_fw->data;
+ adev->psp.toc_fw_version = le32_to_cpu(toc_hdr->header.ucode_version);
+ adev->psp.toc_feature_version =
le32_to_cpu(toc_hdr->ucode_feature_version);
+ adev->psp.toc_bin_size = le32_to_cpu(toc_hdr->header.ucode_size_bytes);
+ adev->psp.toc_start_addr = (uint8_t *)toc_hdr +
+
le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes);
+ return 0;
+out:
+ dev_err(adev->dev, "fail to initialize toc microcode\n");
+ release_firmware(adev->psp.toc_fw);
+ adev->psp.toc_fw = NULL;
+ return err;
+}
+
int psp_init_sos_microcode(struct psp_context *psp,
const char *chip_name)
{
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index 919d2fb7427b..13f56618660a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -253,6 +253,11 @@ struct psp_context
uint32_tasd_ucode_size;
uint8_t *asd_start_addr;
+ /* toc firmware */
+ const struct firmware *toc_fw;
+ uint32_ttoc_fw_version;
+ uint32_ttoc_feature_version;
+
/* fence buffer */
struct amdgpu_bo*fence_buf_bo;
uint64_tfence_buf_mc_addr;
@@ -386,6 +391,8 @@ int psp_ring_cmd_submit(struct psp_context *psp,
int index);
int psp_init_asd_microcode(struct psp_context *psp,
const char *chip_name);
+int psp_init_toc_microcode(struct psp_context *psp,
+ const char *chip_name);
int psp_init_sos_microcode(struct psp_context *psp,
const char *chip_name);
int psp_init_ta_microcode(struct psp_context *psp,
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index 6c5d9612abcb..f2d6b2518eee 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -109,20 +109,16
[PATCH 38/45] drm/amdgpu: disable gfxoff on vangogh for the moment (v2)
From: Huang Rui GFXOFF will be enabled once it's verified on real asic. v2: move check into gfx10 module. Signed-off-by: Huang Rui Reviewed-by: Aaron Liu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 83183541865f..fd29a6d7285b 100755 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -3666,6 +3666,9 @@ static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev) if (!gfx_v10_0_navi10_gfxoff_should_enable(adev)) adev->pm.pp_feature &= ~PP_GFXOFF_MASK; break; + case CHIP_VANGOGH: + adev->pm.pp_feature &= ~PP_GFXOFF_MASK; + break; default: break; } -- 2.25.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 07/45] drm/amdgpu: skip sdma1 in nv_allowed_read_registers list for van gogh (v2)
From: Huang Rui
Van gogh only has one sdma.
v2: use num_instances rather than APU flag
Signed-off-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/nv.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 2077f897d6eb..8616d397da00 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -289,7 +289,8 @@ static int nv_read_register(struct amdgpu_device *adev, u32
se_num,
*value = 0;
for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) {
en = _allowed_read_registers[i];
- if (reg_offset !=
+ if ((i == 7 && (adev->sdma.num_instances == 1)) || /* some
asics don't have SDMA1 */
+ reg_offset !=
(adev->reg_offset[en->hwip][en->inst][en->seg] +
en->reg_offset))
continue;
--
2.25.4
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[PATCH 13/45] drm/amdgpu: get the correct vram type for van gogh
From: Huang Rui
This patch is to get the correct vram type from atombios for van gogh.
Signed-off-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | 4
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 1 +
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
index 17c010d0431f..e0e3a7e4774f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
@@ -149,6 +149,10 @@ static int convert_atom_mem_type_to_vram_type(struct
amdgpu_device *adev,
case LpDdr4MemType:
vram_type = AMDGPU_VRAM_TYPE_DDR4;
break;
+ case Ddr5MemType:
+ case LpDdr5MemType:
+ vram_type = AMDGPU_VRAM_TYPE_DDR5;
+ break;
default:
vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
break;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 92fbbfb16cff..2ce79bccfc30 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -1063,6 +1063,7 @@ static const char *amdgpu_vram_names[] = {
"DDR3",
"DDR4",
"GDDR6",
+ "DDR5"
};
/**
--
2.25.4
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[PATCH 26/45] drm/amdgpu/powerplay: add new smu messages and feature masks for vangogh (v2)
From: Xiaojian Du
This patch is to add new smu messages and feature masks for vangogh.
v2: squash in updates and typo fixes
Signed-off-by: Xiaojian Du
Reviewed-by: Kevin Wang
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/inc/smu_types.h | 53 +++---
1 file changed, 47 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_types.h
b/drivers/gpu/drm/amd/pm/inc/smu_types.h
index 35fc46d3c9c0..b1a18fbb7682 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_types.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_types.h
@@ -35,6 +35,7 @@
__SMU_DUMMY_MAP(EnableSmuFeaturesHigh),\
__SMU_DUMMY_MAP(DisableSmuFeaturesLow),\
__SMU_DUMMY_MAP(DisableSmuFeaturesHigh), \
+ __SMU_DUMMY_MAP(GetEnabledSmuFeatures), \
__SMU_DUMMY_MAP(GetEnabledSmuFeaturesLow), \
__SMU_DUMMY_MAP(GetEnabledSmuFeaturesHigh),\
__SMU_DUMMY_MAP(SetWorkloadMask), \
@@ -122,7 +123,7 @@
__SMU_DUMMY_MAP(GetVoltageByDpm), \
__SMU_DUMMY_MAP(GetVoltageByDpmOverdrive), \
__SMU_DUMMY_MAP(PowerUpVcn0), \
- __SMU_DUMMY_MAP(PowerDownVcn0), \
+ __SMU_DUMMY_MAP(PowerDownVcn0),\
__SMU_DUMMY_MAP(PowerUpVcn1), \
__SMU_DUMMY_MAP(PowerDownVcn1),\
__SMU_DUMMY_MAP(PowerUpGfx), \
@@ -165,18 +166,24 @@
__SMU_DUMMY_MAP(GpuChangeState), \
__SMU_DUMMY_MAP(SetPowerLimitPercentage), \
__SMU_DUMMY_MAP(ForceGfxContentSave), \
- __SMU_DUMMY_MAP(EnableTmdp48MHzRefclkPwrDown), \
+ __SMU_DUMMY_MAP(EnableTmdp48MHzRefclkPwrDown),\
__SMU_DUMMY_MAP(PowerGateAtHub), \
__SMU_DUMMY_MAP(SetSoftMinJpeg), \
__SMU_DUMMY_MAP(SetHardMinFclkByFreq),\
- __SMU_DUMMY_MAP(DFCstateControl), \
- __SMU_DUMMY_MAP(GmiPwrDnControl), \
- __SMU_DUMMY_MAP(DAL_DISABLE_DUMMY_PSTATE_CHANGE), \
+ __SMU_DUMMY_MAP(DFCstateControl), \
+ __SMU_DUMMY_MAP(GmiPwrDnControl), \
+ __SMU_DUMMY_MAP(DAL_DISABLE_DUMMY_PSTATE_CHANGE),\
__SMU_DUMMY_MAP(DAL_ENABLE_DUMMY_PSTATE_CHANGE), \
__SMU_DUMMY_MAP(SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_HIGH), \
__SMU_DUMMY_MAP(SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_LOW), \
__SMU_DUMMY_MAP(GET_UMC_FW_WA), \
__SMU_DUMMY_MAP(Mode1Reset), \
+ __SMU_DUMMY_MAP(Spare), \
+ __SMU_DUMMY_MAP(SetHardMinIspiclkByFreq),\
+ __SMU_DUMMY_MAP(SetHardMinIspxclkByFreq),\
+ __SMU_DUMMY_MAP(SetSoftMinSocclkByFreq), \
+ __SMU_DUMMY_MAP(PowerUpCvip),\
+ __SMU_DUMMY_MAP(PowerDownCvip), \
#undef __SMU_DUMMY_MAP
#define __SMU_DUMMY_MAP(type) SMU_MSG_##type
@@ -265,7 +272,41 @@ enum smu_clk_type {
__SMU_DUMMY_MAP(ATHUB_PG), \
__SMU_DUMMY_MAP(APCC_DFLL), \
__SMU_DUMMY_MAP(DPM_GFX_GPO),\
- __SMU_DUMMY_MAP(WAFL_CG),
+ __SMU_DUMMY_MAP(WAFL_CG),\
+ __SMU_DUMMY_MAP(CCLK_DPM), \
+ __SMU_DUMMY_MAP(FAN_CONTROLLER), \
+ __SMU_DUMMY_MAP(VCN_DPM), \
+ __SMU_DUMMY_MAP(FCLK_DPM), \
+ __SMU_DUMMY_MAP(SOCCLK_DPM), \
+ __SMU_DUMMY_MAP(MP0CLK_DPM), \
+ __SMU_DUMMY_MAP(LCLK_DPM), \
+ __SMU_DUMMY_MAP(SHUBCLK_DPM),\
+ __SMU_DUMMY_MAP(DCFCLK_DPM), \
+ __SMU_DUMMY_MAP(GFX_DPM), \
+ __SMU_DUMMY_MAP(DS_DCFCLK), \
+ __SMU_DUMMY_MAP(S0I2), \
+ __SMU_DUMMY_MAP(SMU_LOW_POWER), \
+ __SMU_DUMMY_MAP(GFX_DEM),\
+ __SMU_DUMMY_MAP(PSI), \
+ __SMU_DUMMY_MAP(PROCHOT),\
+ __SMU_DUMMY_MAP(CPUOFF),\
+ __SMU_DUMMY_MAP(STAPM), \
+ __SMU_DUMMY_MAP(S0I3), \
+ __SMU_DUMMY_MAP(DF_CSTATES), \
+ __SMU_DUMMY_MAP(PERF_LIMIT), \
+ __SMU_DUMMY_MAP(CORE_DLDO), \
+ __SMU_DUMMY_MAP(RSMU_LOW_POWER), \
+ __SMU_DUMMY_MAP(SMN_LOW_POWER), \
+ __SMU_DUMMY_MAP(THM_LOW_POWER), \
+ __SMU_DUMMY_MAP(SMUIO_LOW_POWER),\
+ __SMU_DUMMY_MAP(MP1_LOW_POWER), \
+ __SMU_DUMMY_MAP(DS_VCN), \
+ __SMU_DUMMY_MAP(CPPC),
[PATCH 27/45] drm/admgpu/powerplay: add smu v11.5 driver interface header for vangogh
From: Xiaojian Du
This patch is to add smu v11.5 driver interface header for vangogh.
Signed-off-by: Xiaojian Du
Reviewed-by: Kevin Wang
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
.../drm/amd/pm/inc/smu11_driver_if_vangogh.h | 239 ++
1 file changed, 239 insertions(+)
create mode 100644 drivers/gpu/drm/amd/pm/inc/smu11_driver_if_vangogh.h
diff --git a/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_vangogh.h
b/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_vangogh.h
new file mode 100644
index ..20f8c6f460b8
--- /dev/null
+++ b/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_vangogh.h
@@ -0,0 +1,239 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef __SMU11_DRIVER_IF_VANGOGH_H__
+#define __SMU11_DRIVER_IF_VANGOGH_H__
+
+// *** IMPORTANT ***
+// SMU TEAM: Always increment the interface version if
+// any structure is changed in this file
+#define SMU13_DRIVER_IF_VERSION 2
+
+typedef struct {
+ int32_t value;
+ uint32_t numFractionalBits;
+} FloatInIntFormat_t;
+
+typedef enum {
+ DSPCLK_DCFCLK = 0,
+ DSPCLK_DISPCLK,
+ DSPCLK_PIXCLK,
+ DSPCLK_PHYCLK,
+ DSPCLK_COUNT,
+} DSPCLK_e;
+
+typedef struct {
+ uint16_t Freq; // in MHz
+ uint16_t Vid; // min voltage in SVI2 VID
+} DisplayClockTable_t;
+
+typedef struct {
+ uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)
+ uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)
+ uint16_t MinMclk;
+ uint16_t MaxMclk;
+
+ uint8_t WmSetting;
+ uint8_t WmType; // Used for normal pstate change or memory retraining
+ uint8_t Padding[2];
+} WatermarkRowGeneric_t;
+
+#define NUM_WM_RANGES 4
+#define WM_PSTATE_CHG 0
+#define WM_RETRAINING 1
+
+typedef enum {
+ WM_SOCCLK = 0,
+ WM_DCFCLK,
+ WM_COUNT,
+} WM_CLOCK_e;
+
+typedef struct {
+ // Watermarks
+ WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
+
+ uint32_t MmHubPadding[7]; // SMU internal use
+} Watermarks_t;
+
+typedef enum {
+ CUSTOM_DPM_SETTING_GFXCLK,
+ CUSTOM_DPM_SETTING_CCLK,
+ CUSTOM_DPM_SETTING_FCLK_CCX,
+ CUSTOM_DPM_SETTING_FCLK_GFX,
+ CUSTOM_DPM_SETTING_FCLK_STALLS,
+ CUSTOM_DPM_SETTING_LCLK,
+ CUSTOM_DPM_SETTING_COUNT,
+} CUSTOM_DPM_SETTING_e;
+
+typedef struct {
+ uint8_t ActiveHystLimit;
+ uint8_t IdleHystLimit;
+ uint8_t FPS;
+ uint8_t MinActiveFreqType;
+ FloatInIntFormat_t MinActiveFreq;
+ FloatInIntFormat_t PD_Data_limit;
+ FloatInIntFormat_t PD_Data_time_constant;
+ FloatInIntFormat_t PD_Data_error_coeff;
+ FloatInIntFormat_t PD_Data_error_rate_coeff;
+} DpmActivityMonitorCoeffExt_t;
+
+typedef struct {
+ DpmActivityMonitorCoeffExt_t
DpmActivityMonitorCoeff[CUSTOM_DPM_SETTING_COUNT];
+} CustomDpmSettings_t;
+
+#define NUM_DCFCLK_DPM_LEVELS 6
+#define NUM_DISPCLK_DPM_LEVELS 6
+#define NUM_DPPCLK_DPM_LEVELS 6
+#define NUM_SOCCLK_DPM_LEVELS 8
+#define NUM_ISPICLK_DPM_LEVELS 6
+#define NUM_ISPXCLK_DPM_LEVELS 6
+#define NUM_VCN_DPM_LEVELS 8
+#define NUM_FCLK_DPM_LEVELS 4
+#define NUM_SOC_VOLTAGE_LEVELS 8
+
+typedef struct {
+ uint32_t fclk;
+ uint32_t memclk;
+ uint32_t voltage;
+} df_pstate_t;
+
+typedef struct {
+ uint32_t vclk;
+ uint32_t dclk;
+} vcn_clk_t;
+
+//Freq in MHz
+//Voltage in milli volts with 2 fractional bits
+
+typedef struct {
+ uint32_t DcfClocks[NUM_DCFCLK_DPM_LEVELS];
+ uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS];
+ uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS];
+ uint32_t SocClocks[NUM_SOCCLK_DPM_LEVELS];
+ uint32_t IspiClocks[NUM_ISPICLK_DPM_LEVELS];
+ uint32_t IspxClocks[NUM_ISPXCLK_DPM_LEVELS];
+ vcn_clk_t VcnClocks[NUM_VCN_DPM_LEVELS];
+
+ uint32_t SocVoltage[NUM_SOC_VOLTAGE_LEVELS];
+
+ df_pstate_t DfPstateTable[NUM_FCLK_DPM_LEVELS];
+
+ uint32_t MinGfxClk;
+ uint32_t MaxGfxClk;
+
+ uint8_t NumDfPstatesEnabled;
+ uint8_t NumDpmLevelsEnabled;
+ uint8_t spare[2];
+} DpmClocks_t;
+
+
+// Throttler
[PATCH 23/45] drm/amdgpu: enable vcn3.0 for van gogh
From: Thong Thai Same as other VCN 3.0 asics. Signed-off-by: Thong Thai Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 8 drivers/gpu/drm/amd/amdgpu/nv.c | 2 ++ 2 files changed, 10 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c index 495c3d7bb2b2..81102598cde7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c @@ -44,6 +44,7 @@ #define FIRMWARE_NAVI12"amdgpu/navi12_vcn.bin" #define FIRMWARE_SIENNA_CICHLID"amdgpu/sienna_cichlid_vcn.bin" #define FIRMWARE_NAVY_FLOUNDER "amdgpu/navy_flounder_vcn.bin" +#define FIRMWARE_VANGOGH "amdgpu/vangogh_vcn.bin" MODULE_FIRMWARE(FIRMWARE_RAVEN); MODULE_FIRMWARE(FIRMWARE_PICASSO); @@ -55,6 +56,7 @@ MODULE_FIRMWARE(FIRMWARE_NAVI14); MODULE_FIRMWARE(FIRMWARE_NAVI12); MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID); MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER); +MODULE_FIRMWARE(FIRMWARE_VANGOGH); static void amdgpu_vcn_idle_work_handler(struct work_struct *work); @@ -123,6 +125,12 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev) (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) adev->vcn.indirect_sram = true; break; + case CHIP_VANGOGH: + fw_name = FIRMWARE_VANGOGH; + if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && + (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) + adev->vcn.indirect_sram = true; + break; default: return -EINVAL; } diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index df94f72e017a..2711c5661a97 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c @@ -612,6 +612,8 @@ int nv_set_ip_blocks(struct amdgpu_device *adev) amdgpu_device_ip_block_add(adev, _virtual_ip_block); amdgpu_device_ip_block_add(adev, _v10_0_ip_block); amdgpu_device_ip_block_add(adev, _v5_2_ip_block); + amdgpu_device_ip_block_add(adev, _v3_0_ip_block); + amdgpu_device_ip_block_add(adev, _v3_0_ip_block); break; default: return -EINVAL; -- 2.25.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 22/45] drm/amdgpu: add mmhub v2.3 for vangogh (v4)
From: Huang Rui
There are too many register offset mismatch between mmhub v2.0 and v2.3.
E.X:
mmMM_ATC_L2_MISC_CG: 0x064a(v2.0) 0x06cd(v2.3)
mmMMVM_L2_PROTECTION_FAULT_CNTL: 0x0688(v2.0) 0x0708(v2.3)
mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32: 0x072b(v2.0) 0x0940(v2.3)
mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32: 0x072c(v2.0) 0x0941(v2.3)
mmMMVM_INVALIDATE_ENG0_REQ: 0x06e3(v2.0) 0x0a01(v2.3)
mmMMVM_INVALIDATE_ENG0_ACK: 0x06f5(v2.0) 0x0a02(v2.3)
mmMMVM_CONTEXT0_CNTL: 0x06c0(v2.0) 0x0740(v2.3)
mmMMVM_L2_PROTECTION_FAULT_STATUS: 0x068c(v2.0) 0x070c(v2.3)
mmMMVM_L2_PROTECTION_FAULT_CNTL: 0x0688(v2.0) 0x0708(v2.3)
mmMM_ATC_L2_MISC_CG: 0x064a(v2.0) 0x06cd(v2.3)
mmDAGB0_CNTL_MISC2: 0x0071(v2.0) 0x0096(v2.3)
...
Continuing using the same file mmhub v2.0 is not good choice, it will
introduce a lot of checking with ASIC types. And also easy to introduce the
issues that offset not align, this kind of issues are really hard to find. Van
Gogh's mmhub vm invalidation is actually caused by the offset mismatch as well.
So it would like to create a new file rather than stick to re-use orignal mmhub
v2.0 here.
v2: add missed translate_further programming.
v3: sync with latest code
v4: add missing callbacks
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/Makefile | 2 +-
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 10 +-
drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c | 552
drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.h | 28 ++
4 files changed, 590 insertions(+), 2 deletions(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.h
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
b/drivers/gpu/drm/amd/amdgpu/Makefile
index 7866e4666a43..7c7e34824c51 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -81,7 +81,7 @@ amdgpu-y += \
gmc_v7_0.o \
gmc_v8_0.o \
gfxhub_v1_0.o mmhub_v1_0.o gmc_v9_0.o gfxhub_v1_1.o mmhub_v9_4.o \
- gfxhub_v2_0.o mmhub_v2_0.o gmc_v10_0.o gfxhub_v2_1.o
+ gfxhub_v2_0.o mmhub_v2_0.o gmc_v10_0.o gfxhub_v2_1.o mmhub_v2_3.o
# add UMC block
amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index fa0a0c8a6b11..df14880cf97e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -46,6 +46,7 @@
#include "gfxhub_v2_0.h"
#include "gfxhub_v2_1.h"
#include "mmhub_v2_0.h"
+#include "mmhub_v2_3.h"
#include "athub_v2_0.h"
#include "athub_v2_1.h"
@@ -631,7 +632,14 @@ static void gmc_v10_0_set_umc_funcs(struct amdgpu_device
*adev)
static void gmc_v10_0_set_mmhub_funcs(struct amdgpu_device *adev)
{
- adev->mmhub.funcs = _v2_0_funcs;
+ switch (adev->asic_type) {
+ case CHIP_VANGOGH:
+ adev->mmhub.funcs = _v2_3_funcs;
+ break;
+ default:
+ adev->mmhub.funcs = _v2_0_funcs;
+ break;
+ }
}
static int gmc_v10_0_early_init(void *handle)
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
new file mode 100644
index ..b39dc2023b5f
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
@@ -0,0 +1,552 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include "amdgpu.h"
+#include "mmhub_v2_3.h"
+
+#include "mmhub/mmhub_2_3_0_offset.h"
+#include "mmhub/mmhub_2_3_0_sh_mask.h"
+#include "mmhub/mmhub_2_3_0_default.h"
+#include "navi10_enum.h"
+
+#include "soc15_common.h"
+
+static uint32_t mmhub_v2_3_get_invalidate_req(unsigned int vmid,
+ uint32_t flush_type)
+{
+ u32 req = 0;
+
+ /* invalidate using legacy mode on vmid*/
+ req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,
+
[PATCH 15/45] drm/amdgpu: set fw load type for van gogh
From: Huang Rui
This patch sets fw load type as direct for van gogh for the moment.
Will switch to psp when psp is ready.
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index 55fe19a2f332..3f791ca73ff7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -395,6 +395,8 @@ amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int
load_type)
return AMDGPU_FW_LOAD_DIRECT;
else
return AMDGPU_FW_LOAD_PSP;
+ case CHIP_VANGOGH:
+ return AMDGPU_FW_LOAD_DIRECT;
default:
DRM_ERROR("Unknown firmware load type\n");
}
--
2.25.4
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[PATCH 24/45] drm/amdgpu: add pcie port indirect read and write on nv
From: Huang Rui
This patch is to add pcie port indirect read/write callback for nv
series. They will be used for new asic.
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h | 2 ++
drivers/gpu/drm/amd/amdgpu/nv.c | 32
2 files changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
index edaac242ff85..483834a62436 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
@@ -53,6 +53,8 @@ struct amdgpu_nbio_funcs {
u32 (*get_hdp_flush_done_offset)(struct amdgpu_device *adev);
u32 (*get_pcie_index_offset)(struct amdgpu_device *adev);
u32 (*get_pcie_data_offset)(struct amdgpu_device *adev);
+ u32 (*get_pcie_port_index_offset)(struct amdgpu_device *adev);
+ u32 (*get_pcie_port_data_offset)(struct amdgpu_device *adev);
u32 (*get_rev_id)(struct amdgpu_device *adev);
void (*mc_access_enable)(struct amdgpu_device *adev, bool enable);
void (*hdp_flush)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 2711c5661a97..5b3b70a64a79 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -118,6 +118,21 @@ static u64 nv_pcie_rreg64(struct amdgpu_device *adev, u32
reg)
return r;
}
+static u32 nv_pcie_port_rreg(struct amdgpu_device *adev, u32 reg)
+{
+ unsigned long flags, address, data;
+ u32 r;
+ address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
+ data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
+
+ spin_lock_irqsave(>pcie_idx_lock, flags);
+ WREG32(address, reg * 4);
+ (void)RREG32(address);
+ r = RREG32(data);
+ spin_unlock_irqrestore(>pcie_idx_lock, flags);
+ return r;
+}
+
static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)
{
unsigned long flags, address, data;
@@ -140,6 +155,21 @@ static void nv_pcie_wreg64(struct amdgpu_device *adev, u32
reg, u64 v)
spin_unlock_irqrestore(>pcie_idx_lock, flags);
}
+static void nv_pcie_port_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
+{
+ unsigned long flags, address, data;
+
+ address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
+ data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
+
+ spin_lock_irqsave(>pcie_idx_lock, flags);
+ WREG32(address, reg * 4);
+ (void)RREG32(address);
+ WREG32(data, v);
+ (void)RREG32(data);
+ spin_unlock_irqrestore(>pcie_idx_lock, flags);
+}
+
static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg)
{
unsigned long flags, address, data;
@@ -746,6 +776,8 @@ static int nv_common_early_init(void *handle)
adev->pcie_wreg = _pcie_wreg;
adev->pcie_rreg64 = _pcie_rreg64;
adev->pcie_wreg64 = _pcie_wreg64;
+ adev->pciep_rreg = _pcie_port_rreg;
+ adev->pciep_wreg = _pcie_port_wreg;
/* TODO: will add them during VCN v2 implementation */
adev->uvd_ctx_rreg = NULL;
--
2.25.4
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[PATCH 21/45] drm/amdkfd: add Van Gogh KFD support
From: Huang Rui
This patch is to add GFX10 based APU Van Gogh KFD support. We will treat Van
Gogh as "dgpu" (bypass IOMMU v2).
Signed-off-by: Huang Rui
Acked-by: Alex Deucher
Reviewed-by: Yong Zhao
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 5 +
drivers/gpu/drm/amd/amdkfd/kfd_device.c | 20 +++
.../drm/amd/amdkfd/kfd_device_queue_manager.c | 1 +
drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c | 1 +
.../gpu/drm/amd/amdkfd/kfd_packet_manager.c | 1 +
drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 1 +
6 files changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
index d2981524dba0..0eeda7904c14 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
@@ -141,6 +141,7 @@ static struct kfd_gpu_cache_info carrizo_cache_info[] = {
#define renoir_cache_info carrizo_cache_info
/* TODO - check & update Navi10 cache details */
#define navi10_cache_info carrizo_cache_info
+#define vangogh_cache_info carrizo_cache_info
static void kfd_populated_cu_info_cpu(struct kfd_topology_device *dev,
struct crat_subtype_computeunit *cu)
@@ -683,6 +684,10 @@ static int kfd_fill_gpu_cache_info(struct kfd_dev *kdev,
pcache_info = navi10_cache_info;
num_of_cache_types = ARRAY_SIZE(navi10_cache_info);
break;
+ case CHIP_VANGOGH:
+ pcache_info = vangogh_cache_info;
+ num_of_cache_types = ARRAY_SIZE(vangogh_cache_info);
+ break;
default:
return -EINVAL;
}
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index 903170e59342..81751da79feb 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -76,6 +76,7 @@ static const struct kfd2kgd_calls *kfd2kgd_funcs[] = {
[CHIP_NAVI14] = _v10_kfd2kgd,
[CHIP_SIENNA_CICHLID] = _v10_3_kfd2kgd,
[CHIP_NAVY_FLOUNDER] = _v10_3_kfd2kgd,
+ [CHIP_VANGOGH] = _v10_3_kfd2kgd,
};
#ifdef KFD_SUPPORT_IOMMU_V2
@@ -498,6 +499,24 @@ static const struct kfd_device_info
navy_flounder_device_info = {
.num_sdma_queues_per_engine = 8,
};
+static const struct kfd_device_info vangogh_device_info = {
+ .asic_family = CHIP_VANGOGH,
+ .asic_name = "vangogh",
+ .max_pasid_bits = 16,
+ .max_no_of_hqd = 24,
+ .doorbell_size = 8,
+ .ih_ring_entry_size = 8 * sizeof(uint32_t),
+ .event_interrupt_class = _interrupt_class_v9,
+ .num_of_watch_points = 4,
+ .mqd_size_aligned = MQD_SIZE_ALIGNED,
+ .needs_iommu_device = false,
+ .supports_cwsr = true,
+ .needs_pci_atomics = false,
+ .num_sdma_engines = 1,
+ .num_xgmi_sdma_engines = 0,
+ .num_sdma_queues_per_engine = 2,
+};
+
/* For each entry, [0] is regular and [1] is virtualisation device. */
static const struct kfd_device_info *kfd_supported_devices[][2] = {
#ifdef KFD_SUPPORT_IOMMU_V2
@@ -522,6 +541,7 @@ static const struct kfd_device_info
*kfd_supported_devices[][2] = {
[CHIP_NAVI14] = {_device_info, NULL},
[CHIP_SIENNA_CICHLID] = {_cichlid_device_info,
_cichlid_device_info},
[CHIP_NAVY_FLOUNDER] = {_flounder_device_info,
_flounder_device_info},
+ [CHIP_VANGOGH] = {_device_info, NULL},
};
static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size,
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index 62504d5fa42b..7971bbe696d0 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -1925,6 +1925,7 @@ struct device_queue_manager
*device_queue_manager_init(struct kfd_dev *dev)
case CHIP_NAVI14:
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ case CHIP_VANGOGH:
device_queue_manager_init_v10_navi10(>asic_ops);
break;
default:
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
b/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
index 3c22909470f2..379457d1b250 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
@@ -417,6 +417,7 @@ int kfd_init_apertures(struct kfd_process *process)
case CHIP_NAVI14:
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ case CHIP_VANGOGH:
kfd_init_apertures_v9(pdd, id);
break;
default:
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
index 47ee40fbbd86..9beb2eabd56e 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
+++
[PATCH 05/45] drm/amdgpu: add vangogh_reg_base_init function for van gogh
From: Huang Rui
This patch adds vangogh_reg_base_init function to init the register base for
van gogh.
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/Makefile |2 +-
drivers/gpu/drm/amd/amdgpu/nv.h |1 +
drivers/gpu/drm/amd/amdgpu/vangogh_reg_init.c | 51 +
.../gpu/drm/amd/include/vangogh_ip_offset.h | 1516 +
4 files changed, 1569 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/vangogh_reg_init.c
create mode 100644 drivers/gpu/drm/amd/include/vangogh_ip_offset.h
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
b/drivers/gpu/drm/amd/amdgpu/Makefile
index 39976c7b100c..7866e4666a43 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -69,7 +69,7 @@ amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o
si_ih.o si_dma.o dce
amdgpu-y += \
vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o
vega10_reg_init.o \
vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o navi10_reg_init.o
navi14_reg_init.o \
- arct_reg_init.o navi12_reg_init.o mxgpu_nv.o sienna_cichlid_reg_init.o
+ arct_reg_init.o navi12_reg_init.o mxgpu_nv.o sienna_cichlid_reg_init.o
vangogh_reg_init.o
# add DF block
amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.h b/drivers/gpu/drm/amd/amdgpu/nv.h
index aeef50a6a54b..8a3bf476b18f 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.h
+++ b/drivers/gpu/drm/amd/amdgpu/nv.h
@@ -34,4 +34,5 @@ int navi10_reg_base_init(struct amdgpu_device *adev);
int navi14_reg_base_init(struct amdgpu_device *adev);
int navi12_reg_base_init(struct amdgpu_device *adev);
int sienna_cichlid_reg_base_init(struct amdgpu_device *adev);
+int vangogh_reg_base_init(struct amdgpu_device *adev);
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/vangogh_reg_init.c
b/drivers/gpu/drm/amd/amdgpu/vangogh_reg_init.c
new file mode 100644
index ..4c6c3b415e7b
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/vangogh_reg_init.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#include "amdgpu.h"
+#include "nv.h"
+
+#include "soc15_common.h"
+#include "soc15_hw_ip.h"
+#include "vangogh_ip_offset.h"
+
+int vangogh_reg_base_init(struct amdgpu_device *adev)
+{
+ /* HW has more IP blocks, only initialized the blocke needed by driver
*/
+ uint32_t i;
+ for (i = 0 ; i < MAX_INSTANCE ; ++i) {
+ adev->reg_offset[GC_HWIP][i] = (uint32_t
*)(&(GC_BASE.instance[i]));
+ adev->reg_offset[HDP_HWIP][i] = (uint32_t
*)(&(HDP_BASE.instance[i]));
+ adev->reg_offset[MMHUB_HWIP][i] = (uint32_t
*)(&(MMHUB_BASE.instance[i]));
+ adev->reg_offset[ATHUB_HWIP][i] = (uint32_t
*)(&(ATHUB_BASE.instance[i]));
+ adev->reg_offset[NBIO_HWIP][i] = (uint32_t
*)(&(NBIO_BASE.instance[i]));
+ adev->reg_offset[MP0_HWIP][i] = (uint32_t
*)(&(MP0_BASE.instance[i]));
+ adev->reg_offset[MP1_HWIP][i] = (uint32_t
*)(&(MP1_BASE.instance[i]));
+ adev->reg_offset[VCN_HWIP][i] = (uint32_t
*)(&(VCN_BASE.instance[i]));
+ adev->reg_offset[DF_HWIP][i] = (uint32_t
*)(&(DF_BASE.instance[i]));
+ adev->reg_offset[DCE_HWIP][i] = (uint32_t
*)(&(DCN_BASE.instance[i]));
+ adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t
*)(&(OSSSYS_BASE.instance[i]));
+ adev->reg_offset[SDMA0_HWIP][i] = (uint32_t
*)(&(GC_BASE.instance[i]));
+ adev->reg_offset[SMUIO_HWIP][i] = (uint32_t
*)(&(SMUIO_BASE.instance[i]));
+ adev->reg_offset[THM_HWIP][i] = (uint32_t
*)(&(THM_BASE.instance[i]));
+ }
+ return 0;
+}
diff --git a/drivers/gpu/drm/amd/include/vangogh_ip_offset.h
b/drivers/gpu/drm/amd/include/vangogh_ip_offset.h
new file
[PATCH 11/45] drm/amdgpu: update new memory types in atomfirmware header
From: Huang Rui
Add new nemory types in atomfirmware header.
Signed-off-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/include/atomfirmware.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h
b/drivers/gpu/drm/amd/include/atomfirmware.h
index 3e526c394f6c..0799a9ca0440 100644
--- a/drivers/gpu/drm/amd/include/atomfirmware.h
+++ b/drivers/gpu/drm/amd/include/atomfirmware.h
@@ -1367,6 +1367,11 @@ enum atom_dmi_t17_mem_type_def{
LpDdr2MemType,///< Assign 28 to
LPDDR2
LpDdr3MemType,///< Assign 29 to
LPDDR3
LpDdr4MemType,///< Assign 30 to
LPDDR4
+ GDdr6MemType, ///< Assign 31 to GDDR6
+ HbmMemType, ///< Assign 32 to HBM
+ Hbm2MemType, ///< Assign 33 to HBM2
+ Ddr5MemType, ///< Assign 34 to DDR5
+ LpDdr5MemType,///< Assign 35 to
LPDDR5
};
--
2.25.4
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[PATCH 14/45] drm/amdgpu: add gmc v10 supports for van gogh (v3)
From: Huang Rui
Add gfx memory controller support for van gogh.
v2: don't use dynamic invalidate eng allocation for van gogh.
v3: squash in other fixes
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 33 --
1 file changed, 26 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index 31359e519d69..fa0a0c8a6b11 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -677,7 +677,8 @@ static void gmc_v10_0_vram_gtt_location(struct
amdgpu_device *adev,
u64 base = 0;
if (adev->asic_type == CHIP_SIENNA_CICHLID ||
- adev->asic_type == CHIP_NAVY_FLOUNDER)
+ adev->asic_type == CHIP_NAVY_FLOUNDER ||
+ adev->asic_type == CHIP_VANGOGH)
base = gfxhub_v2_1_get_fb_location(adev);
else
base = gfxhub_v2_0_get_fb_location(adev);
@@ -690,7 +691,8 @@ static void gmc_v10_0_vram_gtt_location(struct
amdgpu_device *adev,
/* base offset of vram pages */
if (adev->asic_type == CHIP_SIENNA_CICHLID ||
- adev->asic_type == CHIP_NAVY_FLOUNDER)
+ adev->asic_type == CHIP_NAVY_FLOUNDER ||
+ adev->asic_type == CHIP_VANGOGH)
adev->vm_manager.vram_base_offset =
gfxhub_v2_1_get_mc_fb_offset(adev);
else
adev->vm_manager.vram_base_offset =
gfxhub_v2_0_get_mc_fb_offset(adev);
@@ -726,6 +728,13 @@ static int gmc_v10_0_mc_init(struct amdgpu_device *adev)
adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
+#ifdef CONFIG_X86_64
+ if (adev->flags & AMD_IS_APU) {
+ adev->gmc.aper_base = gfxhub_v2_1_get_mc_fb_offset(adev);
+ adev->gmc.aper_size = adev->gmc.real_vram_size;
+ }
+#endif
+
/* In case the PCI BAR is larger than the actual amount of vram */
adev->gmc.visible_vram_size = adev->gmc.aper_size;
if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
@@ -739,6 +748,7 @@ static int gmc_v10_0_mc_init(struct amdgpu_device *adev)
case CHIP_NAVI12:
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ case CHIP_VANGOGH:
default:
adev->gmc.gart_size = 512ULL << 20;
break;
@@ -778,7 +788,8 @@ static int gmc_v10_0_sw_init(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
if (adev->asic_type == CHIP_SIENNA_CICHLID ||
- adev->asic_type == CHIP_NAVY_FLOUNDER)
+ adev->asic_type == CHIP_NAVY_FLOUNDER ||
+ adev->asic_type == CHIP_VANGOGH)
gfxhub_v2_1_init(adev);
else
gfxhub_v2_0_init(adev);
@@ -787,7 +798,10 @@ static int gmc_v10_0_sw_init(void *handle)
spin_lock_init(>gmc.invalidate_lock);
- if (adev->asic_type == CHIP_SIENNA_CICHLID && amdgpu_emu_mode == 1) {
+ if ((adev->flags & AMD_IS_APU) && amdgpu_emu_mode == 1) {
+ adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4;
+ adev->gmc.vram_width = 64;
+ } else if (amdgpu_emu_mode == 1) {
adev->gmc.vram_type = AMDGPU_VRAM_TYPE_GDDR6;
adev->gmc.vram_width = 1 * 128; /* numchan * chansize */
} else {
@@ -805,6 +819,7 @@ static int gmc_v10_0_sw_init(void *handle)
case CHIP_NAVI12:
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ case CHIP_VANGOGH:
adev->num_vmhubs = 2;
/*
* To fulfill 4-level page support,
@@ -918,6 +933,7 @@ static void gmc_v10_0_init_golden_registers(struct
amdgpu_device *adev)
case CHIP_NAVI12:
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ case CHIP_VANGOGH:
break;
default:
break;
@@ -945,7 +961,8 @@ static int gmc_v10_0_gart_enable(struct amdgpu_device *adev)
return r;
if (adev->asic_type == CHIP_SIENNA_CICHLID ||
- adev->asic_type == CHIP_NAVY_FLOUNDER)
+ adev->asic_type == CHIP_NAVY_FLOUNDER ||
+ adev->asic_type == CHIP_VANGOGH)
r = gfxhub_v2_1_gart_enable(adev);
else
r = gfxhub_v2_0_gart_enable(adev);
@@ -970,7 +987,8 @@ static int gmc_v10_0_gart_enable(struct amdgpu_device *adev)
false : true;
if (adev->asic_type == CHIP_SIENNA_CICHLID ||
- adev->asic_type == CHIP_NAVY_FLOUNDER)
+ adev->asic_type == CHIP_NAVY_FLOUNDER ||
+ adev->asic_type == CHIP_VANGOGH)
gfxhub_v2_1_set_fault_enable_default(adev, value);
else
gfxhub_v2_0_set_fault_enable_default(adev, value);
@@ -1015,7 +1033,8
[PATCH 08/45] drm/amdgpu: add van gogh support for ih block
From: Huang Rui
This patch adds the support for van gogh ih block.
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
index 74b1e7dc49a9..ce4a974ab777 100644
--- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
@@ -314,6 +314,7 @@ static int navi10_ih_irq_init(struct amdgpu_device *adev)
switch (adev->asic_type) {
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ case CHIP_VANGOGH:
ih_chicken = RREG32_SOC15(OSSSYS, 0,
mmIH_CHICKEN_Sienna_Cichlid);
ih_chicken = REG_SET_FIELD(ih_chicken,
IH_CHICKEN,
MC_SPACE_GPA_ENABLE, 1);
--
2.25.4
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[PATCH 28/45] drm/amdgpu/powerplay: add smu v11.5 firmware header for vangogh (v2)
From: Xiaojian Du
This patch is to add smu v11.5 firmware header for vangogh
v2: squash in updates
Signed-off-by: Xiaojian Du
Reviewed-by: Kevin Wang
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/inc/smu_v11_5_pmfw.h | 120
1 file changed, 120 insertions(+)
create mode 100644 drivers/gpu/drm/amd/pm/inc/smu_v11_5_pmfw.h
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_5_pmfw.h
b/drivers/gpu/drm/amd/pm/inc/smu_v11_5_pmfw.h
new file mode 100644
index ..abf13abd3919
--- /dev/null
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_5_pmfw.h
@@ -0,0 +1,120 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __SMU_V11_5_0_PMFW_H__
+#define __SMU_V11_5_0_PMFW_H__
+
+#include "smu11_driver_if_vangogh.h"
+
+#pragma pack(push, 1)
+
+#define ENABLE_DEBUG_FEATURES
+
+// Feature Control Defines
+#define FEATURE_CCLK_DPM_BIT 0
+#define FEATURE_FAN_CONTROLLER_BIT 1
+#define FEATURE_DATA_CALCULATION_BIT 2
+#define FEATURE_PPT_BIT3
+#define FEATURE_TDC_BIT4
+#define FEATURE_THERMAL_BIT5
+#define FEATURE_FIT_BIT6
+#define FEATURE_EDC_BIT7
+#define FEATURE_PLL_POWER_DOWN_BIT 8
+#define FEATURE_ULV_BIT9
+#define FEATURE_VDDOFF_BIT10
+#define FEATURE_VCN_DPM_BIT 11
+#define FEATURE_CSTATE_BOOST_BIT 12
+#define FEATURE_FCLK_DPM_BIT 13
+#define FEATURE_SOCCLK_DPM_BIT14
+#define FEATURE_MP0CLK_DPM_BIT15
+#define FEATURE_LCLK_DPM_BIT 16
+#define FEATURE_SHUBCLK_DPM_BIT 17
+#define FEATURE_DCFCLK_DPM_BIT18
+#define FEATURE_GFX_DPM_BIT 19
+#define FEATURE_DS_GFXCLK_BIT 20
+#define FEATURE_DS_SOCCLK_BIT 21
+#define FEATURE_DS_LCLK_BIT 22
+#define FEATURE_DS_DCFCLK_BIT 23
+#define FEATURE_DS_SHUBCLK_BIT24
+#define FEATURE_GFX_TEMP_VMIN_BIT 25
+#define FEATURE_S0I2_BIT 26
+#define FEATURE_WHISPER_MODE_BIT 27
+#define FEATURE_DS_FCLK_BIT 28
+#define FEATURE_DS_SMNCLK_BIT 29
+#define FEATURE_DS_MP1CLK_BIT 30
+#define FEATURE_DS_MP0CLK_BIT 31
+#define FEATURE_SMU_LOW_POWER_BIT 32
+#define FEATURE_FUSE_PG_BIT 33
+#define FEATURE_GFX_DEM_BIT 34
+#define FEATURE_PSI_BIT 35
+#define FEATURE_PROCHOT_BIT 36
+#define FEATURE_CPUOFF_BIT37
+#define FEATURE_STAPM_BIT 38
+#define FEATURE_S0I3_BIT 39
+#define FEATURE_DF_CSTATES_BIT40
+#define FEATURE_PERF_LIMIT_BIT41
+#define FEATURE_CORE_DLDO_BIT 42
+#define FEATURE_RSMU_LOW_POWER_BIT43
+#define FEATURE_SMN_LOW_POWER_BIT 44
+#define FEATURE_THM_LOW_POWER_BIT 45
+#define FEATURE_SMUIO_LOW_POWER_BIT 46
+#define FEATURE_MP1_LOW_POWER_BIT 47
+#define FEATURE_DS_VCN_BIT48
+#define FEATURE_CPPC_BIT 49
+#define FEATURE_OS_CSTATES_BIT50
+#define FEATURE_ISP_DPM_BIT 51
+#define FEATURE_A55_DPM_BIT 52
+#define FEATURE_CVIP_DSP_DPM_BIT 53
+#define FEATURE_MSMU_LOW_POWER_BIT54
+#define FEATURE_SOC_VOLTAGE_MON_BIT 55
+#define FEATURE_ATHUB_PG_BIT 56
+#define FEATURE_ECO_DEEPCSTATE_BIT57
+#define FEATURE_CC6 58
+#define NUM_FEATURES 59
+
+typedef struct {
+ // MP1_EXT_SCRATCH0
+ uint32_t DpmHandlerID : 8;
+ uint32_t ActivityMonitorID: 8;
+ uint32_t DpmTimerID : 8;
+ uint32_t spare0 : 8;
+ // MP1_EXT_SCRATCH1
+ uint32_t GfxStatus: 2;
+ uint32_t GfxoffStatus : 8;
+ uint32_t CpuOff : 1;
+ uint32_t VddOff : 1;
+ uint32_t InUlv: 1;
+ uint32_t InS0i2 : 2;
+ uint32_t InWhisperMode: 1;
+ uint32_t
[PATCH 10/45] drm/amdgpu: add uapi to define van gogh memory type
From: Huang Rui
This patch adds van gogh memory type as DDR5.
Signed-off-by: Huang Rui
Signed-off-by: Alex Deucher
---
include/uapi/drm/amdgpu_drm.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index 8d416188ddb3..d98d4e6f311b 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -949,6 +949,7 @@ struct drm_amdgpu_info_firmware {
#define AMDGPU_VRAM_TYPE_DDR3 7
#define AMDGPU_VRAM_TYPE_DDR4 8
#define AMDGPU_VRAM_TYPE_GDDR6 9
+#define AMDGPU_VRAM_TYPE_DDR5 10
struct drm_amdgpu_info_device {
/** PCI Device ID */
--
2.25.4
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[PATCH 09/45] drm/amdgpu: use gpu virtual address for interrupt packet write space for vangogh
From: Huang Rui The interrupts are not stable while uses guest physical address (GPA) for interrupt packet write space even on direct loading case. Signed-off-by: Huang Rui Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c index ce4a974ab777..b66414998c90 100644 --- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c @@ -661,7 +661,10 @@ static int navi10_ih_sw_init(void *handle) /* use gpu virtual address for ih ring * until ih_checken is programmed to allow * use bus address for ih ring by psp bl */ - use_bus_addr = + if (adev->flags & AMD_IS_APU) + use_bus_addr = false; + else + use_bus_addr = (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) ? false : true; r = amdgpu_ih_ring_init(adev, >irq.ih, 256 * 1024, use_bus_addr); if (r) -- 2.25.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 19/45] drm/amdgpu: add sdma support for van gogh
From: Huang Rui
This patch adds the sdma v5.2 support for van gogh.
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
index 9f3952723c63..100d0a921ede 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
@@ -47,6 +47,8 @@
MODULE_FIRMWARE("amdgpu/sienna_cichlid_sdma.bin");
MODULE_FIRMWARE("amdgpu/navy_flounder_sdma.bin");
+MODULE_FIRMWARE("amdgpu/vangogh_sdma.bin");
+
#define SDMA1_REG_OFFSET 0x600
#define SDMA3_REG_OFFSET 0x400
#define SDMA0_HYP_DEC_REG_START 0x5880
@@ -87,6 +89,7 @@ static void sdma_v5_2_init_golden_registers(struct
amdgpu_device *adev)
switch (adev->asic_type) {
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ case CHIP_VANGOGH:
break;
default:
break;
@@ -160,6 +163,9 @@ static int sdma_v5_2_init_microcode(struct amdgpu_device
*adev)
case CHIP_NAVY_FLOUNDER:
chip_name = "navy_flounder";
break;
+ case CHIP_VANGOGH:
+ chip_name = "vangogh";
+ break;
default:
BUG();
}
@@ -1171,6 +1177,9 @@ static int sdma_v5_2_early_init(void *handle)
case CHIP_NAVY_FLOUNDER:
adev->sdma.num_instances = 2;
break;
+ case CHIP_VANGOGH:
+ adev->sdma.num_instances = 1;
+ break;
default:
break;
}
@@ -1567,6 +1576,7 @@ static int sdma_v5_2_set_clockgating_state(void *handle,
switch (adev->asic_type) {
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ case CHIP_VANGOGH:
sdma_v5_2_update_medium_grain_clock_gating(adev,
state == AMD_CG_STATE_GATE ? true : false);
sdma_v5_2_update_medium_grain_light_sleep(adev,
--
2.25.4
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[PATCH 25/45] drm/amdgpu: add nbio v7.2 for vangogh (v2)
From: Huang Rui
VanGogh uses nbio v7.2, and a couple of offsets are changed since nbio
v2.3 for navi series, so add new nbio v7.2 block.
v2: squash in fix for sdma and vcn instances
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/Makefile| 3 +-
drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c | 341 +
drivers/gpu/drm/amd/amdgpu/nbio_v7_2.h | 32 +++
drivers/gpu/drm/amd/amdgpu/nv.c| 10 +-
4 files changed, 383 insertions(+), 3 deletions(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/nbio_v7_2.h
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
b/drivers/gpu/drm/amd/amdgpu/Makefile
index 7c7e34824c51..60cff3b08eb3 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -69,7 +69,8 @@ amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o
si_ih.o si_dma.o dce
amdgpu-y += \
vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o
vega10_reg_init.o \
vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o navi10_reg_init.o
navi14_reg_init.o \
- arct_reg_init.o navi12_reg_init.o mxgpu_nv.o sienna_cichlid_reg_init.o
vangogh_reg_init.o
+ arct_reg_init.o navi12_reg_init.o mxgpu_nv.o sienna_cichlid_reg_init.o
vangogh_reg_init.o \
+ nbio_v7_2.o
# add DF block
amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c
b/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c
new file mode 100644
index ..aa36022670f9
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c
@@ -0,0 +1,341 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#include "amdgpu.h"
+#include "amdgpu_atombios.h"
+#include "nbio_v7_2.h"
+
+#include "nbio/nbio_7_2_0_offset.h"
+#include "nbio/nbio_7_2_0_sh_mask.h"
+#include
+
+static void nbio_v7_2_remap_hdp_registers(struct amdgpu_device *adev)
+{
+ WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL,
+ adev->rmmio_remap.reg_offset +
KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
+ WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL,
+ adev->rmmio_remap.reg_offset +
KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
+}
+
+static u32 nbio_v7_2_get_rev_id(struct amdgpu_device *adev)
+{
+ u32 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);
+
+ tmp &= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
+ tmp >>=
RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
+
+ return tmp;
+}
+
+static void nbio_v7_2_mc_access_enable(struct amdgpu_device *adev, bool enable)
+{
+ if (enable)
+ WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN,
+BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK |
+BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK);
+ else
+ WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 0);
+}
+
+static void nbio_v7_2_hdp_flush(struct amdgpu_device *adev,
+ struct amdgpu_ring *ring)
+{
+ if (!ring || !ring->funcs->emit_wreg)
+ WREG32_NO_KIQ((adev->rmmio_remap.reg_offset +
KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
+ else
+ amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset +
KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
+}
+
+static u32 nbio_v7_2_get_memsize(struct amdgpu_device *adev)
+{
+ return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE);
+}
+
+static void nbio_v7_2_sdma_doorbell_range(struct amdgpu_device *adev, int
instance,
+ bool use_doorbell, int doorbell_index,
+ int doorbell_size)
+{
+ u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_SDMA0_DOORBELL_RANGE);
+ u32 doorbell_range =
[PATCH 04/45] drm/amdgpu: add van gogh support for gpu_info and ip block setting
From: Huang Rui
This patch adds van gogh support for gpu_info firmware and ip block setting.
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index ecaa35ada79c..191d86c6c551 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -80,6 +80,7 @@ MODULE_FIRMWARE("amdgpu/renoir_gpu_info.bin");
MODULE_FIRMWARE("amdgpu/navi10_gpu_info.bin");
MODULE_FIRMWARE("amdgpu/navi14_gpu_info.bin");
MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin");
+MODULE_FIRMWARE("amdgpu/vangogh_gpu_info.bin");
#define AMDGPU_RESUME_MS 2000
@@ -1703,6 +1704,9 @@ static int amdgpu_device_parse_gpu_info_fw(struct
amdgpu_device *adev)
case CHIP_NAVI12:
chip_name = "navi12";
break;
+ case CHIP_VANGOGH:
+ chip_name = "vangogh";
+ break;
}
snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name);
@@ -1877,7 +1881,11 @@ static int amdgpu_device_ip_early_init(struct
amdgpu_device *adev)
case CHIP_NAVI12:
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
- adev->family = AMDGPU_FAMILY_NV;
+ case CHIP_VANGOGH:
+ if (adev->asic_type == CHIP_VANGOGH)
+ adev->family = AMDGPU_FAMILY_VGH;
+ else
+ adev->family = AMDGPU_FAMILY_NV;
r = nv_set_ip_blocks(adev);
if (r)
--
2.25.4
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[PATCH 06/45] drm/amdgpu: add nv common ip block support for van gogh
From: Huang Rui This patch adds common ip support for van gogh. Signed-off-by: Huang Rui Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/nv.c | 8 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index bc894cfba60c..2077f897d6eb 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c @@ -478,6 +478,9 @@ static int nv_reg_base_init(struct amdgpu_device *adev) case CHIP_NAVY_FLOUNDER: sienna_cichlid_reg_base_init(adev); break; + case CHIP_VANGOGH: + vangogh_reg_base_init(adev); + break; default: return -EINVAL; } @@ -858,6 +861,11 @@ static int nv_common_early_init(void *handle) adev->external_rev_id = adev->rev_id + 0x32; break; + case CHIP_VANGOGH: + adev->cg_flags = 0; + adev->pg_flags = 0; + adev->external_rev_id = adev->rev_id + 0x01; + break; default: /* FIXME: not supported yet */ return -EINVAL; -- 2.25.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 20/45] drm/amdgpu: set ip blocks for van gogh
From: Huang Rui Enable ip blocks for van gogh. Signed-off-by: Huang Rui Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/nv.c | 9 + 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index 8616d397da00..df94f72e017a 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c @@ -604,6 +604,15 @@ int nv_set_ip_blocks(struct amdgpu_device *adev) is_support_sw_smu(adev)) amdgpu_device_ip_block_add(adev, _v11_0_ip_block); break; + case CHIP_VANGOGH: + amdgpu_device_ip_block_add(adev, _common_ip_block); + amdgpu_device_ip_block_add(adev, _v10_0_ip_block); + amdgpu_device_ip_block_add(adev, _ih_ip_block); + if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) + amdgpu_device_ip_block_add(adev, _virtual_ip_block); + amdgpu_device_ip_block_add(adev, _v10_0_ip_block); + amdgpu_device_ip_block_add(adev, _v5_2_ip_block); + break; default: return -EINVAL; } -- 2.25.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 00/45] Add support for vangoh
This patch set adds initial support for vangoh, a new GPU from AMD. I did not send out the register header change due to size. The full patch set is available in git here: https://cgit.freedesktop.org/~agd5f/linux/log/?h=amd-staging-drm-next-vangogh Alex Deucher (3): drm/amdgpu/gfx10: add updated register offsets for VGH drm/amdgpu: IP discovery table is not ready yet for VG drm/amdgpu/mmhub2.3: print client id string for mmhub Huang Rui (32): drm/amdgpu: add vangogh asic header files (v2) drm/amdgpu: add van gogh asic_type enum (v2) drm/amdgpu: add uapi to define van gogh series drm/amdgpu: add van gogh support for gpu_info and ip block setting drm/amdgpu: add vangogh_reg_base_init function for van gogh drm/amdgpu: add nv common ip block support for van gogh drm/amdgpu: skip sdma1 in nv_allowed_read_registers list for van gogh (v2) drm/amdgpu: add van gogh support for ih block drm/amdgpu: use gpu virtual address for interrupt packet write space for vangogh drm/amdgpu: add uapi to define van gogh memory type drm/amdgpu: update new memory types in atomfirmware header drm/amdgpu: get the correct vram type for van gogh drm/amdgpu: add gmc v10 supports for van gogh (v3) drm/amdgpu: set fw load type for van gogh drm/amdgpu: add gfx support for van gogh (v2) drm/amdgpu: add gfx golden settings for vangogh (v3) drm/amdgpu: add sdma support for van gogh drm/amdgpu: set ip blocks for van gogh drm/amdkfd: add Van Gogh KFD support drm/amdgpu: add mmhub v2.3 for vangogh (v4) drm/amdgpu: add pcie port indirect read and write on nv drm/amdgpu: add nbio v7.2 for vangogh (v2) drm/amd/powerplay: partially enable swsmu for vangogh drm/amd/powerplay: add vangogh ppt into swSMU drm/amdgpu: add smu ip block for vangogh drm/amdgpu: add TOC firmware definition drm/amdgpu: add TOC firmware support for apu (v2) drm/amdgpu: enable psp support for vangogh drm/amdgpu: disable gfxoff on vangogh for the moment (v2) drm/amdgpu: add gfx power gating for gfx10 drm/amdgpu: enable gfx clock gating and power gating for vangogh drm/amdgpu: add van gogh pci id Roman Li (3): drm/amdgpu/atomfirmware: Add edp and integrated info v2.1 tables drm/amd/display: Add dcn3.01 support to DC drm/amd/display: Add dcn3.01 support to DM Thong Thai (1): drm/amdgpu: enable vcn3.0 for van gogh Xiaojian Du (6): drm/amdgpu/powerplay: add new smu messages and feature masks for vangogh (v2) drm/admgpu/powerplay: add smu v11.5 driver interface header for vangogh drm/amdgpu/powerplay: add smu v11.5 firmware header for vangogh (v2) drm/amdgpu/powerplay: add smu v11.5 smc header for vangogh drm/amdgpu/powerplay: add vangogh asic name in smu v11 (v2) drm/amdgpu/powerplay: add smu initialize funcitons for vangogh (v2) drivers/gpu/drm/amd/amdgpu/Makefile | 5 +- .../gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | 4 + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 11 +- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 + drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 11 + drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h | 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_object.c| 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 37 + drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 7 + drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 8 + drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c|109 +- drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c| 43 +- drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c |589 + drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.h | 28 + drivers/gpu/drm/amd/amdgpu/navi10_ih.c| 6 +- drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c|341 + drivers/gpu/drm/amd/amdgpu/nbio_v7_2.h| 32 + drivers/gpu/drm/amd/amdgpu/nv.c | 74 +- drivers/gpu/drm/amd/amdgpu/nv.h | 1 + drivers/gpu/drm/amd/amdgpu/psp_v11_0.c| 38 +- drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c| 10 + drivers/gpu/drm/amd/amdgpu/vangogh_reg_init.c | 51 + drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 5 + drivers/gpu/drm/amd/amdkfd/kfd_device.c | 20 + .../drm/amd/amdkfd/kfd_device_queue_manager.c | 1 + drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c | 1 + .../gpu/drm/amd/amdkfd/kfd_packet_manager.c | 1 + drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 1 + drivers/gpu/drm/amd/display/Kconfig | 9 + .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 26 + drivers/gpu/drm/amd/display/dc/Makefile | 4 + .../drm/amd/display/dc/bios/bios_parser2.c|187 + .../display/dc/bios/command_table_helper2.c | 6 +- .../gpu/drm/amd/display/dc/clk_mgr/Makefile | 10 + .../gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 21 +- .../display/dc/clk_mgr/dcn301/dcn301_smu.c|241 +
[PATCH 12/45] drm/amdgpu/atomfirmware: Add edp and integrated info v2.1 tables
From: Roman Li
Required for vangogh.
Signed-off-by: Roman Li
Reviewed-by: Alex Deucher
Reviewed-by: Harry Wentland
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/include/atomfirmware.h | 62 +-
1 file changed, 61 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h
b/drivers/gpu/drm/amd/include/atomfirmware.h
index 0799a9ca0440..4eb578b1baef 100644
--- a/drivers/gpu/drm/amd/include/atomfirmware.h
+++ b/drivers/gpu/drm/amd/include/atomfirmware.h
@@ -1304,11 +1304,71 @@ struct atom_integrated_system_info_v1_12
struct atom_hdmi_retimer_redriver_set dp3_retimer_set; //for DP3
struct atom_DCN_dpphy_dp_tuningset hbr_tuningset;//hbr 2.7G dp tuning set
struct atom_DCN_dpphy_dp_tuningset hbr2_tuningset; //hbr2 5.4G dp turnig
set
- struct atom_DCN_dpphy_dp_tuningset edp_tunings; //edp tuning set
+ struct atom_DCN_dpphy_dp_tuningset edp_tunings; //edp tuning set
struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK6_tuningset;
uint32_t reserved[63];
};
+
+#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
+
+struct edp_info_table
+{
+uint16_t edp_backlight_pwm_hz;
+uint16_t edp_ss_percentage;
+uint16_t edp_ss_rate_10hz;
+uint16_t reserved1;
+uint32_t reserved2;
+uint8_t edp_pwr_on_off_delay;
+uint8_t edp_pwr_on_vary_bl_to_blon;
+uint8_t edp_pwr_down_bloff_to_vary_bloff;
+uint8_t edp_panel_bpc;
+uint8_t edp_bootup_bl_level;
+uint8_t reserved3[3];
+uint32_t reserved4[3];
+};
+
+struct atom_integrated_system_info_v2_1
+{
+struct atom_common_table_header table_header;
+uint32_t vbios_misc; //enum of
atom_system_vbiosmisc_def
+uint32_t gpucapinfo; //enum of
atom_system_gpucapinf_def
+uint32_t system_config;
+uint32_t cpucapinfo;
+uint16_t gpuclk_ss_percentage; //unit of 0.001%, 1000
mean 1%
+uint16_t gpuclk_ss_type;
+uint16_t dpphy_override; // bit vector, enum of
atom_sysinfo_dpphy_override_def
+uint8_t memorytype; // enum of
atom_dmi_t17_mem_type_def, APU memory type indication.
+uint8_t umachannelnumber; // number of memory
channels
+uint8_t htc_hyst_limit;
+uint8_t htc_tmp_limit;
+uint8_t reserved1;
+uint8_t reserved2;
+struct edp_info_table edp1_info;
+struct edp_info_table edp2_info;
+uint32_t reserved3[8];
+struct atom_external_display_connection_info extdispconninfo;
+struct atom_DCN_dpphy_dvihdmi_tuningset TMDS_tuningset;
+struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK5_tuningset; //add clk6
+struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK6_tuningset;
+struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK8_tuningset;
+uint32_t reserved4[6];//reserve
2*sizeof(atom_DCN_dpphy_dvihdmi_tuningset)
+struct atom_DCN_dpphy_dp_tuningset rbr_tuningset;// rbr 1.62G
dp tuning set
+struct atom_DCN_dpphy_dp_tuningset hbr_tuningset;//hbr 2.7G dp
tuning set
+struct atom_DCN_dpphy_dp_tuningset hbr2_tuningset; //hbr2 5.4G dp
turnig set
+struct atom_DCN_dpphy_dp_tuningset hbr3_tuningset; // HBR3 dp tuning
set
+struct atom_DCN_dpphy_dp_tuningset edp_tunings; //edp tuning set
+uint32_t reserved5[28];//reserve 2*sizeof(atom_DCN_dpphy_dp_tuningset)
+struct atom_hdmi_retimer_redriver_set dp0_retimer_set; //for DP0
+struct atom_hdmi_retimer_redriver_set dp1_retimer_set; //for DP1
+struct atom_hdmi_retimer_redriver_set dp2_retimer_set; //for DP2
+struct atom_hdmi_retimer_redriver_set dp3_retimer_set; //for DP3
+uint32_t reserved6[30];// reserve size of(atom_camera_data) for
camera_info
+uint32_t reserved7[32];
+
+};
+#endif
+
// system_config
enum atom_system_vbiosmisc_def{
INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT = 0x01,
--
2.25.4
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[PATCH 16/45] drm/amdgpu: add gfx support for van gogh (v2)
From: Huang Rui
Add van gogh checks to gfx10 code.
v2: squash in fixes
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 29 +-
1 file changed, 28 insertions(+), 1 deletion(-)
mode change 100644 => 100755 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
old mode 100644
new mode 100755
index 17fb2efdadd3..19ab5783214c
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -152,6 +152,13 @@ MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin");
MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin");
MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin");
+MODULE_FIRMWARE("amdgpu/vangogh_ce.bin");
+MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin");
+MODULE_FIRMWARE("amdgpu/vangogh_me.bin");
+MODULE_FIRMWARE("amdgpu/vangogh_mec.bin");
+MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin");
+MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin");
+
static const struct soc15_reg_golden golden_settings_gc_10_1[] =
{
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x,
0x00400014),
@@ -3554,6 +3561,7 @@ static void gfx_v10_0_check_fw_write_wait(struct
amdgpu_device *adev)
break;
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ case CHIP_VANGOGH:
adev->gfx.cp_fw_write_wait = true;
break;
default:
@@ -3652,6 +3660,9 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device
*adev)
case CHIP_NAVY_FLOUNDER:
chip_name = "navy_flounder";
break;
+ case CHIP_VANGOGH:
+ chip_name = "vangogh";
+ break;
default:
BUG();
}
@@ -4186,6 +4197,7 @@ static void gfx_v10_0_gpu_early_init(struct amdgpu_device
*adev)
break;
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ case CHIP_VANGOGH:
adev->gfx.config.max_hw_contexts = 8;
adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
@@ -4309,6 +4321,7 @@ static int gfx_v10_0_sw_init(void *handle)
break;
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ case CHIP_VANGOGH:
adev->gfx.me.num_me = 1;
adev->gfx.me.num_pipe_per_me = 1;
adev->gfx.me.num_queue_per_pipe = 1;
@@ -4564,7 +4577,8 @@ static u32
gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *ade
/* for ASICs that integrates GFX v10.3
* pa_sc_tile_steering_override should be set to 0 */
if (adev->asic_type == CHIP_SIENNA_CICHLID ||
- adev->asic_type == CHIP_NAVY_FLOUNDER)
+ adev->asic_type == CHIP_NAVY_FLOUNDER ||
+ adev->asic_type == CHIP_VANGOGH)
return 0;
/* init num_sc */
@@ -5801,6 +5815,7 @@ static void gfx_v10_0_cp_gfx_set_doorbell(struct
amdgpu_device *adev,
switch (adev->asic_type) {
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ case CHIP_VANGOGH:
tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
DOORBELL_RANGE_LOWER_Sienna_Cichlid,
ring->doorbell_index);
WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
@@ -5934,6 +5949,7 @@ static void gfx_v10_0_cp_compute_enable(struct
amdgpu_device *adev, bool enable)
switch (adev->asic_type) {
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ case CHIP_VANGOGH:
WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0);
break;
default:
@@ -5944,6 +5960,7 @@ static void gfx_v10_0_cp_compute_enable(struct
amdgpu_device *adev, bool enable)
switch (adev->asic_type) {
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ case CHIP_VANGOGH:
WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid,
(CP_MEC_CNTL__MEC_ME1_HALT_MASK |
CP_MEC_CNTL__MEC_ME2_HALT_MASK));
@@ -6038,6 +6055,7 @@ static void gfx_v10_0_kiq_setting(struct amdgpu_ring
*ring)
switch (adev->asic_type) {
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
+ case CHIP_VANGOGH:
tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
tmp &= 0xff00;
tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
@@ -6758,6 +6776,8 @@ static bool gfx_v10_0_check_grbm_cam_remapping(struct
amdgpu_device *adev)
return false;
}
break;
+ case CHIP_VANGOGH:
+ return true;
[PATCH 18/45] drm/amdgpu/gfx10: add updated register offsets for VGH
Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 18 -- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 6999228cd6c0..83183541865f 100755 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -99,8 +99,22 @@ #define mmGCR_GENERAL_CNTL_Sienna_Cichlid 0x1580 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX 0 -#define mmSPI_CONFIG_CNTL_1_Vangogh0x2441 -#define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX 1 +#define mmSPI_CONFIG_CNTL_1_Vangogh 0x2441 +#define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX1 +#define mmVGT_TF_MEMORY_BASE_HI_Vangogh 0x2261 +#define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1 +#define mmVGT_HS_OFFCHIP_PARAM_Vangogh 0x224f +#define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX 1 +#define mmVGT_TF_RING_SIZE_Vangogh 0x224e +#define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX 1 +#define mmVGT_GSVS_RING_SIZE_Vangogh 0x2241 +#define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX1 +#define mmVGT_TF_MEMORY_BASE_Vangogh 0x2250 +#define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX1 +#define mmVGT_ESGS_RING_SIZE_Vangogh 0x2240 +#define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX1 +#define mmSPI_CONFIG_CNTL_Vangogh0x2440 +#define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX 1 #define mmCP_HYP_PFP_UCODE_ADDR0x5814 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1 -- 2.25.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 03/45] drm/amdgpu: add uapi to define van gogh series
From: Huang Rui
Add a flag to define van gogh series.
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
include/uapi/drm/amdgpu_drm.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index d3dadf10b13d..8d416188ddb3 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -1086,6 +1086,7 @@ struct drm_amdgpu_info_vce_clock_table {
#define AMDGPU_FAMILY_AI 141 /* Vega10 */
#define AMDGPU_FAMILY_RV 142 /* Raven */
#define AMDGPU_FAMILY_NV 143 /* Navi10 */
+#define AMDGPU_FAMILY_VGH 144 /* Van Gogh */
/*
* Definition of free sync enter and exit signals
--
2.25.4
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[PATCH 17/45] drm/amdgpu: add gfx golden settings for vangogh (v3)
From: Huang Rui
This patch is to add gfx golden settings for vangogh post si.
v2: squash in updates
v3: fix SPI register offset
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 36 +-
1 file changed, 35 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 19ab5783214c..6999228cd6c0 100755
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -99,6 +99,9 @@
#define mmGCR_GENERAL_CNTL_Sienna_Cichlid 0x1580
#define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX 0
+#define mmSPI_CONFIG_CNTL_1_Vangogh0x2441
+#define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX 1
+
#define mmCP_HYP_PFP_UCODE_ADDR0x5814
#define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1
#define mmCP_HYP_PFP_UCODE_DATA0x5815
@@ -3170,6 +3173,33 @@ static const struct soc15_reg_golden
golden_settings_gc_10_3_2[] =
SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x0fff,
0x03ff)
};
+static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] =
+{
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff,
0x3100),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff,
0x7e000100),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x00ff, 0x00e4),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x, 0x0200),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x, 0x0080),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f,
0x00b8),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x0142),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff1,
0x0500),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x00ff, 0x00e4),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x,
0x32103210),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x,
0x32103210),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0x,
0xfff3),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0x,
0xfff3),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ff, 0x00f80988),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17f, 0x0127),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER,
0x, 0x0800),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffbf,
0x0020),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0x,
0x00070103),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x17ff, 0x1000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7, 0x0103),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x, 0x0040),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x0fff,
0x00ff),
+};
+
#define DEFAULT_SH_MEM_CONFIG \
((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
(SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
@@ -3377,7 +3407,11 @@ static void gfx_v10_0_init_golden_registers(struct
amdgpu_device *adev)
golden_settings_gc_10_3_2,
(const
u32)ARRAY_SIZE(golden_settings_gc_10_3_2));
break;
-
+ case CHIP_VANGOGH:
+ soc15_program_register_sequence(adev,
+ golden_settings_gc_10_3_vangogh,
+ (const
u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh));
+ break;
default:
break;
}
--
2.25.4
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[PATCH 02/45] drm/amdgpu: add van gogh asic_type enum (v2)
From: Huang Rui
This patch adds van gogh to amd_asic_type enum and amdgpu_asic_name[].
v2: add missing comma
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 +
include/drm/amd_asic_type.h| 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 1fc216cac345..ecaa35ada79c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -114,6 +114,7 @@ const char *amdgpu_asic_name[] = {
"NAVI12",
"SIENNA_CICHLID",
"NAVY_FLOUNDER",
+ "VANGOGH",
"LAST",
};
diff --git a/include/drm/amd_asic_type.h b/include/drm/amd_asic_type.h
index 8712e14991ed..6d01cf04b77f 100644
--- a/include/drm/amd_asic_type.h
+++ b/include/drm/amd_asic_type.h
@@ -56,6 +56,7 @@ enum amd_asic_type {
CHIP_NAVI12,/* 27 */
CHIP_SIENNA_CICHLID,/* 28 */
CHIP_NAVY_FLOUNDER, /* 29 */
+ CHIP_VANGOGH, /* 30 */
CHIP_LAST,
};
--
2.25.4
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Re: [PATCH] drm/amdgpu: fix a warning in amdgpu_ras.c (v2)
Acked-by: Nirmoy Das On 9/25/20 9:23 PM, Alex Deucher wrote: drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c: In function ‘amdgpu_ras_fs_init’: drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:1284:2: warning: ignoring return value of ‘sysfs_create_group’, declared with attribute warn_unused_result [-Wunused-result] 1284 | sysfs_create_group(>dev->kobj, ); | ^~~~ v2: just print an error for sysfs group creation failure Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 49d10330bf64..8bf6a7c056bc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -1266,6 +1266,7 @@ static int amdgpu_ras_fs_init(struct amdgpu_device *adev) NULL, NULL, }; + int r; /* add features entry */ con->features_attr = dev_attr_features; @@ -1281,7 +1282,9 @@ static int amdgpu_ras_fs_init(struct amdgpu_device *adev) sysfs_bin_attr_init(bin_attrs[0]); } - sysfs_create_group(>dev->kobj, ); + r = sysfs_create_group(>dev->kobj, ); + if (r) + dev_err(adev->dev, "Failed to create RAS sysfs group!"); return 0; } ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu: fix a warning in amdgpu_ras.c (v2)
Reviewed-by: Luben Tuikov That's what I had in mind. No error--let the system survive as much as it can. Regards, Luben On 2020-09-25 15:23, Alex Deucher wrote: > drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c: In function ‘amdgpu_ras_fs_init’: > drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:1284:2: warning: ignoring return > value of ‘sysfs_create_group’, declared with attribute warn_unused_result > [-Wunused-result] > 1284 | sysfs_create_group(>dev->kobj, ); > | ^~~~ > > v2: just print an error for sysfs group creation failure > > Signed-off-by: Alex Deucher > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 5 - > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c > index 49d10330bf64..8bf6a7c056bc 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c > @@ -1266,6 +1266,7 @@ static int amdgpu_ras_fs_init(struct amdgpu_device > *adev) > NULL, > NULL, > }; > + int r; > > /* add features entry */ > con->features_attr = dev_attr_features; > @@ -1281,7 +1282,9 @@ static int amdgpu_ras_fs_init(struct amdgpu_device > *adev) > sysfs_bin_attr_init(bin_attrs[0]); > } > > - sysfs_create_group(>dev->kobj, ); > + r = sysfs_create_group(>dev->kobj, ); > + if (r) > + dev_err(adev->dev, "Failed to create RAS sysfs group!"); > > return 0; > } > ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu: fix a warning in amdgpu_ras.c
On 2020-09-25 15:01, Nirmoy wrote: > > On 9/25/20 7:36 PM, Luben Tuikov wrote: >> On 2020-09-25 11:00, Nirmoy wrote: >>> Acked-by: Nirmoy Das >>> >>> On 9/25/20 4:31 PM, Alex Deucher wrote: drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c: In function ‘amdgpu_ras_fs_init’: drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:1284:2: warning: ignoring return value of ‘sysfs_create_group’, declared with attribute warn_unused_result [-Wunused-result] 1284 | sysfs_create_group(>dev->kobj, ); | ^~~~ Signed-off-by: Alex Deucher --- Do we care whether this fails or not? >>> >>> I think we should. Failure in sysfs_create_group() means memory starved >>> >>> system or we are doing something in the driver code. >>> >>> IMO in both cases, we should error out. >> I disagree. We should try to bring up a display as much as possible. >> sysfs failing shouldn't necessarily bring down the system. >> The system should be as resilient as possible and try to survive >> as much as possible. > > > True, there is no use of printing error if we can't see that. > > > Alex, > > > We should then at least throw a warning and return void in > amdgpu_ras_fs_init(). I think Alex knows what the best course of action is, after my email. Plus we'll get a chance to review any and all patches, as they're posted here in this mailing list. Regards, Luben > > > Thanks, > > Nirmoy > > > >> >> If indeed we had had a memory starvation, other things would fail, >> before or after this sequence. And if those things are terminal, >> which sysfs is not, then let those other errors, such as no memory >> for BOs, bring the display bring-up down. >> >> Regards, >> Luben >> >> >>> >>> Nirmoy >>> drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 49d10330bf64..67724049a0fc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -1281,9 +1281,7 @@ static int amdgpu_ras_fs_init(struct amdgpu_device *adev) sysfs_bin_attr_init(bin_attrs[0]); } - sysfs_create_group(>dev->kobj, ); - - return 0; + return sysfs_create_group(>dev->kobj, ); } static int amdgpu_ras_fs_fini(struct amdgpu_device *adev) >>> ___ >>> amd-gfx mailing list >>> amd-gfx@lists.freedesktop.org >>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfxdata=02%7C01%7Cluben.tuikov%40amd.com%7Cd3a29eb3223b4b58ff6b08d86163c8a9%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637366428560245712sdata=bYWjk2k8IeEolG2wcJLA7J%2Bx2d%2FOSXNIOpLObk%2F3jSQ%3Dreserved=0 >>> ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: fix a warning in amdgpu_ras.c (v2)
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c: In function ‘amdgpu_ras_fs_init’: drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:1284:2: warning: ignoring return value of ‘sysfs_create_group’, declared with attribute warn_unused_result [-Wunused-result] 1284 | sysfs_create_group(>dev->kobj, ); | ^~~~ v2: just print an error for sysfs group creation failure Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 49d10330bf64..8bf6a7c056bc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -1266,6 +1266,7 @@ static int amdgpu_ras_fs_init(struct amdgpu_device *adev) NULL, NULL, }; + int r; /* add features entry */ con->features_attr = dev_attr_features; @@ -1281,7 +1282,9 @@ static int amdgpu_ras_fs_init(struct amdgpu_device *adev) sysfs_bin_attr_init(bin_attrs[0]); } - sysfs_create_group(>dev->kobj, ); + r = sysfs_create_group(>dev->kobj, ); + if (r) + dev_err(adev->dev, "Failed to create RAS sysfs group!"); return 0; } -- 2.25.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu: fix a warning in amdgpu_ras.c
On 9/25/20 7:36 PM, Luben Tuikov wrote: On 2020-09-25 11:00, Nirmoy wrote: Acked-by: Nirmoy Das On 9/25/20 4:31 PM, Alex Deucher wrote: drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c: In function ‘amdgpu_ras_fs_init’: drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:1284:2: warning: ignoring return value of ‘sysfs_create_group’, declared with attribute warn_unused_result [-Wunused-result] 1284 | sysfs_create_group(>dev->kobj, ); | ^~~~ Signed-off-by: Alex Deucher --- Do we care whether this fails or not? I think we should. Failure in sysfs_create_group() means memory starved system or we are doing something in the driver code. IMO in both cases, we should error out. I disagree. We should try to bring up a display as much as possible. sysfs failing shouldn't necessarily bring down the system. The system should be as resilient as possible and try to survive as much as possible. True, there is no use of printing error if we can't see that. Alex, We should then at least throw a warning and return void in amdgpu_ras_fs_init(). Thanks, Nirmoy If indeed we had had a memory starvation, other things would fail, before or after this sequence. And if those things are terminal, which sysfs is not, then let those other errors, such as no memory for BOs, bring the display bring-up down. Regards, Luben Nirmoy drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 49d10330bf64..67724049a0fc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -1281,9 +1281,7 @@ static int amdgpu_ras_fs_init(struct amdgpu_device *adev) sysfs_bin_attr_init(bin_attrs[0]); } - sysfs_create_group(>dev->kobj, ); - - return 0; + return sysfs_create_group(>dev->kobj, ); } static int amdgpu_ras_fs_fini(struct amdgpu_device *adev) ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfxdata=02%7C01%7Cluben.tuikov%40amd.com%7Cd3a29eb3223b4b58ff6b08d86163c8a9%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637366428560245712sdata=bYWjk2k8IeEolG2wcJLA7J%2Bx2d%2FOSXNIOpLObk%2F3jSQ%3Dreserved=0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH 7/9] drm/amd/display: Revert check for flip pending before locking pipes
[AMD Official Use Only - Internal Distribution Only] It's already un-reverted in latest. They could be squashed IMO. -Original Message- From: Michel Dänzer Sent: Friday, September 25, 2020 11:53 To: Siqueira, Rodrigo ; amd-gfx@lists.freedesktop.org Cc: Cyr, Aric ; Brol, Eryk ; Li, Sun peng (Leo) ; Wentland, Harry ; Zhuo, Qingqing ; Pillai, Aurabindo ; Lakha, Bhawanpreet Subject: Re: [PATCH 7/9] drm/amd/display: Revert check for flip pending before locking pipes On 2020-09-25 4:54 p.m., Rodrigo Siqueira wrote: > From: Aric Cyr > > This reverts commit e82d8eae9e81af243256f70bec593baed50b0bdb. Every revert should explain in the commit log why the change is being reverted. (Your future selves might thank you for that someday :) -- Earthling Michel Dänzer | https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fredhat.com%2Fdata=02%7C01%7CAric.Cyr%40amd.com%7Cff8318f7505f48ac4e6008d8616b1050%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637366459764467283sdata=eeKdB8NNb3tanvw5GToG7YbETY%2FYKnEJQXRsfuE6u5k%3Dreserved=0 Libre software enthusiast | Mesa and X developer ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu: fix a warning in amdgpu_ras.c
On 2020-09-25 11:00, Nirmoy wrote: > Acked-by: Nirmoy Das > > On 9/25/20 4:31 PM, Alex Deucher wrote: >> drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c: In function ‘amdgpu_ras_fs_init’: >> drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:1284:2: warning: ignoring return >> value of ‘sysfs_create_group’, declared with attribute warn_unused_result >> [-Wunused-result] >> 1284 | sysfs_create_group(>dev->kobj, ); >>| ^~~~ >> >> Signed-off-by: Alex Deucher >> --- >> >> Do we care whether this fails or not? > > > I think we should. Failure in sysfs_create_group() means memory starved > > system or we are doing something in the driver code. > > IMO in both cases, we should error out. I disagree. We should try to bring up a display as much as possible. sysfs failing shouldn't necessarily bring down the system. The system should be as resilient as possible and try to survive as much as possible. If indeed we had had a memory starvation, other things would fail, before or after this sequence. And if those things are terminal, which sysfs is not, then let those other errors, such as no memory for BOs, bring the display bring-up down. Regards, Luben > > > Nirmoy > >> >> drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 4 +--- >> 1 file changed, 1 insertion(+), 3 deletions(-) >> >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c >> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c >> index 49d10330bf64..67724049a0fc 100644 >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c >> @@ -1281,9 +1281,7 @@ static int amdgpu_ras_fs_init(struct amdgpu_device >> *adev) >> sysfs_bin_attr_init(bin_attrs[0]); >> } >> >> -sysfs_create_group(>dev->kobj, ); >> - >> -return 0; >> +return sysfs_create_group(>dev->kobj, ); >> } >> >> static int amdgpu_ras_fs_fini(struct amdgpu_device *adev) > ___ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfxdata=02%7C01%7Cluben.tuikov%40amd.com%7Cd3a29eb3223b4b58ff6b08d86163c8a9%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637366428560245712sdata=bYWjk2k8IeEolG2wcJLA7J%2Bx2d%2FOSXNIOpLObk%2F3jSQ%3Dreserved=0 > ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 7/9] drm/amd/display: Revert check for flip pending before locking pipes
On 2020-09-25 4:54 p.m., Rodrigo Siqueira wrote: From: Aric Cyr This reverts commit e82d8eae9e81af243256f70bec593baed50b0bdb. Every revert should explain in the commit log why the change is being reverted. (Your future selves might thank you for that someday :) -- Earthling Michel Dänzer | https://redhat.com Libre software enthusiast | Mesa and X developer ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: CONFIG_AMDGPU triggers full rebuild
Hi Christian Am 25.09.20 um 16:54 schrieb Christian König: > Maybe MMU notifiers? But honestly I don't know for sure. I checked. In my current config MMU_NOTIFIERS is y and DRM_AMDGPU is n. So it shouldn't have triggered the rebuilds, I guess. Anyway, thanks for trying to help. Best regards Thomas > > Christian. > > Am 25.09.20 um 16:29 schrieb Thomas Zimmermann: >> Hi, >> >> whenever I change the option CONFIG_AMDGPU, I have to rebuild the whole >> kernel. I guess it auto-selects some architecture-specific feature. That >> full rebuild might be avoidable if I could enable that feature permanently. >> >> Any ideas what this could be and how to avoid the full rebuilt? >> >> Best regards >> Thomas >> >> >> ___ >> amd-gfx mailing list >> amd-gfx@lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/amd-gfx > -- Thomas Zimmermann Graphics Driver Developer SUSE Software Solutions Germany GmbH Maxfeldstr. 5, 90409 Nürnberg, Germany (HRB 36809, AG Nürnberg) Geschäftsführer: Felix Imendörffer signature.asc Description: OpenPGP digital signature ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu: fix a warning in amdgpu_ras.c
Acked-by: Nirmoy Das On 9/25/20 4:31 PM, Alex Deucher wrote: drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c: In function ‘amdgpu_ras_fs_init’: drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:1284:2: warning: ignoring return value of ‘sysfs_create_group’, declared with attribute warn_unused_result [-Wunused-result] 1284 | sysfs_create_group(>dev->kobj, ); | ^~~~ Signed-off-by: Alex Deucher --- Do we care whether this fails or not? I think we should. Failure in sysfs_create_group() means memory starved system or we are doing something in the driver code. IMO in both cases, we should error out. Nirmoy drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 49d10330bf64..67724049a0fc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -1281,9 +1281,7 @@ static int amdgpu_ras_fs_init(struct amdgpu_device *adev) sysfs_bin_attr_init(bin_attrs[0]); } - sysfs_create_group(>dev->kobj, ); - - return 0; + return sysfs_create_group(>dev->kobj, ); } static int amdgpu_ras_fs_fini(struct amdgpu_device *adev) ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 0/9] DC Patches September 25, 2020
This DC patchset brings improvements in multiple areas. In summary, we highlight: * P-state refinements; * Improvements on DSC * Updates on NV1x Best Regards Alvin Lee (1): drm/amd/display: Update NV1x SR latency values Anthony Koo (1): drm/amd/display: [FW Promotion] Release 0.0.35 Aric Cyr (1): drm/amd/display: Revert check for flip pending before locking pipes Chiawen Huang (2): drm/amd/display: disable stream if pixel clock changed with link active drm/amd/display: disable stream if pixel clock changed with link active Eric Bernstein (1): drm/amd/display: Add dp_set_dsc_pps_info_packet to virtual stream encoder Joshua Aberback (1): drm/amd/display: Calc DLG from dummy p-state if full p-state unsupported Wesley Chalmers (1): drm/amd/display: Add debug param to force dio disable Wyatt Wood (1): drm/amd/display: Ensure all debug bits are passed to fw drivers/gpu/drm/amd/display/dc/core/dc.c | 74 +- .../drm/amd/display/dc/core/dc_link_hwss.c| 21 +-- drivers/gpu/drm/amd/display/dc/dc.h | 2 + drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 5 +- .../display/dc/dce110/dce110_hw_sequencer.c | 2 +- .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 12 +- .../amd/display/dc/dcn10/dcn10_hw_sequencer.h | 2 +- .../drm/amd/display/dc/dcn20/dcn20_resource.c | 4 +- .../drm/amd/display/dc/dcn30/dcn30_resource.c | 114 +-- .../drm/amd/display/dc/dcn30/dcn30_resource.h | 5 + .../gpu/drm/amd/display/dc/inc/core_types.h | 2 +- .../gpu/drm/amd/display/dc/inc/hw_sequencer.h | 2 +- .../dc/virtual/virtual_stream_encoder.c | 7 + .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 132 +- 14 files changed, 305 insertions(+), 79 deletions(-) -- 2.28.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 7/9] drm/amd/display: Revert check for flip pending before locking pipes
From: Aric Cyr
This reverts commit e82d8eae9e81af243256f70bec593baed50b0bdb.
Signed-off-by: Aric Cyr
Reviewed-by: Aric Cyr
Acked-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 11 +--
.../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c| 12 ++--
.../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h| 2 +-
drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h| 2 +-
4 files changed, 13 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index dc90d26e2663..76946a7d47ca 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2384,6 +2384,7 @@ static void commit_planes_for_stream(struct dc *dc,
enum surface_update_type update_type,
struct dc_state *context)
{
+ bool mpcc_disconnected = false;
int i, j;
struct pipe_ctx *top_pipe_to_program = NULL;
@@ -2414,8 +2415,14 @@ static void commit_planes_for_stream(struct dc *dc,
context_clock_trace(dc, context);
}
- if (update_type != UPDATE_TYPE_FAST &&
dc->hwss.interdependent_update_lock && dc->hwss.wait_for_pending_cleared)
- dc->hwss.disconnect_pipes(dc, context);
+ if (update_type != UPDATE_TYPE_FAST &&
dc->hwss.interdependent_update_lock &&
+ dc->hwss.disconnect_pipes && dc->hwss.wait_for_pending_cleared){
+ dc->hwss.interdependent_update_lock(dc, context, true);
+ mpcc_disconnected = dc->hwss.disconnect_pipes(dc, context);
+ dc->hwss.interdependent_update_lock(dc, context, false);
+ if (mpcc_disconnected)
+ dc->hwss.wait_for_pending_cleared(dc, context);
+ }
for (j = 0; j < dc->res_pool->pipe_count; j++) {
struct pipe_ctx *pipe_ctx = >res_ctx.pipe_ctx[j];
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 79fe9571cf5d..d0f3bf953d02 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2761,7 +2761,7 @@ static struct pipe_ctx *dcn10_find_top_pipe_for_stream(
return NULL;
}
-void dcn10_disconnect_pipes(
+bool dcn10_disconnect_pipes(
struct dc *dc,
struct dc_state *context)
{
@@ -2772,10 +2772,6 @@ void dcn10_disconnect_pipes(
bool mpcc_disconnected = false;
struct pipe_ctx *old_pipe;
struct pipe_ctx *new_pipe;
-
- dc->hwss.wait_for_pending_cleared(dc, context);
- dc->hwss.interdependent_update_lock(dc, context, true);
-
DC_LOGGER_INIT(dc->ctx->logger);
/* Set pipe update flags and lock pipes */
@@ -2878,11 +2874,7 @@ void dcn10_disconnect_pipes(
}
}
}
-
- dc->hwss.interdependent_update_lock(dc, context, false);
-
- if (mpcc_disconnected)
- dc->hwss.wait_for_pending_cleared(dc, context);
+ return mpcc_disconnected;
}
void dcn10_wait_for_pending_cleared(struct dc *dc,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
index 9a0f7a8a85cd..e5691e499023 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
@@ -194,7 +194,7 @@ void dcn10_get_surface_visual_confirm_color(
void dcn10_get_hdr_visual_confirm_color(
struct pipe_ctx *pipe_ctx,
struct tg_color *color);
-void dcn10_disconnect_pipes(
+bool dcn10_disconnect_pipes(
struct dc *dc,
struct dc_state *context);
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index f48ee24d42f9..64c1be818b0e 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -67,7 +67,7 @@ struct hw_sequencer_funcs {
int num_planes, struct dc_state *context);
void (*program_front_end_for_ctx)(struct dc *dc,
struct dc_state *context);
- void (*disconnect_pipes)(struct dc *dc,
+ bool (*disconnect_pipes)(struct dc *dc,
struct dc_state *context);
void (*wait_for_pending_cleared)(struct dc *dc,
struct dc_state *context);
--
2.28.0
___
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[PATCH 8/9] drm/amd/display: [FW Promotion] Release 0.0.35
From: Anthony Koo
[Header Changes]
- Definition for retaining ABM settings during disable
- Addition of some new AUX interface definitions
- Addition of some outbox definitions
Signed-off-by: Anthony Koo
Reviewed-by: Anthony Koo
Acked-by: Rodrigo Siqueira
---
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 132 +-
1 file changed, 126 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index 0051b1000264..d103ec1eaa73 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -36,10 +36,10 @@
/* Firmware versioning. */
#ifdef DMUB_EXPOSE_VERSION
-#define DMUB_FW_VERSION_GIT_HASH 0xf547f0b9d
+#define DMUB_FW_VERSION_GIT_HASH 0x9cf8f05fe
#define DMUB_FW_VERSION_MAJOR 0
#define DMUB_FW_VERSION_MINOR 0
-#define DMUB_FW_VERSION_REVISION 34
+#define DMUB_FW_VERSION_REVISION 35
#define DMUB_FW_VERSION_TEST 0
#define DMUB_FW_VERSION_VBIOS 0
#define DMUB_FW_VERSION_HOTFIX 0
@@ -57,6 +57,7 @@
#define SET_ABM_PIPE_GRADUALLY_DISABLE 0
#define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255
+#define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254
#define SET_ABM_PIPE_NORMAL 1
/* Maximum number of streams on any ASIC. */
@@ -69,10 +70,6 @@
#define PHYSICAL_ADDRESS_LOC union large_integer
#endif
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
#ifndef dmub_memcpy
#define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes))
#endif
@@ -81,6 +78,10 @@ extern "C" {
#define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes))
#endif
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
#ifndef dmub_udelay
#define dmub_udelay(microseconds) udelay(microseconds)
#endif
@@ -299,11 +300,15 @@ enum dmub_cmd_type {
DMUB_CMD__PSR = 64,
DMUB_CMD__ABM = 66,
DMUB_CMD__HW_LOCK = 69,
+ DMUB_CMD__DP_AUX_ACCESS = 70,
+ DMUB_CMD__OUTBOX1_ENABLE = 71,
DMUB_CMD__VBIOS = 128,
};
enum dmub_out_cmd_type {
DMUB_OUT_CMD__NULL = 0,
+ DMUB_OUT_CMD__DP_AUX_REPLY = 1,
+ DMUB_OUT_CMD__DP_HPD_NOTIFY = 2,
};
#pragma pack(push, 1)
@@ -461,6 +466,78 @@ struct dmub_rb_cmd_dpphy_init {
uint8_t reserved[60];
};
+enum dp_aux_request_action {
+ DP_AUX_REQ_ACTION_I2C_WRITE = 0x00,
+ DP_AUX_REQ_ACTION_I2C_READ = 0x10,
+ DP_AUX_REQ_ACTION_I2C_STATUS_REQ= 0x20,
+ DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40,
+ DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50,
+ DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT= 0x60,
+ DP_AUX_REQ_ACTION_DPCD_WRITE= 0x80,
+ DP_AUX_REQ_ACTION_DPCD_READ = 0x90
+};
+
+/* DP AUX command */
+struct aux_transaction_parameters {
+ uint8_t is_i2c_over_aux;
+ uint8_t action;
+ uint8_t length;
+ uint8_t pad;
+ uint32_t address;
+ uint8_t data[16];
+};
+
+struct dmub_cmd_dp_aux_control_data {
+ uint32_t handle;
+ uint8_t port_index;
+ uint8_t sw_crc_enabled;
+ uint16_t timeout;
+ struct aux_transaction_parameters dpaux;
+};
+
+struct dmub_rb_cmd_dp_aux_access {
+ struct dmub_cmd_header header;
+ struct dmub_cmd_dp_aux_control_data aux_control;
+};
+
+struct dmub_rb_cmd_outbox1_enable {
+ struct dmub_cmd_header header;
+ uint32_t enable;
+};
+
+/* DP AUX Reply command - OutBox Cmd */
+struct aux_reply_data {
+ uint8_t command;
+ uint8_t length;
+ uint8_t pad[2];
+ uint8_t data[16];
+};
+
+struct aux_reply_control_data {
+ uint32_t handle;
+ uint8_t phy_port_index;
+ uint8_t result;
+ uint16_t pad;
+};
+
+struct dmub_rb_cmd_dp_aux_reply {
+ struct dmub_cmd_header header;
+ struct aux_reply_control_data control;
+ struct aux_reply_data reply_data;
+};
+
+struct dp_hpd_data {
+ uint8_t phy_port_index;
+ uint8_t hpd_type;
+ uint8_t hpd_status;
+ uint8_t pad;
+};
+
+struct dmub_rb_cmd_dp_hpd_notify {
+ struct dmub_cmd_header header;
+ struct dp_hpd_data hpd_data;
+};
+
/*
* Command IDs should be treated as stable ABI.
* Do not reuse or modify IDs.
@@ -690,8 +767,15 @@ union dmub_rb_cmd {
struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level;
struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac;
struct dmub_rb_cmd_abm_init_config abm_init_config;
+ struct dmub_rb_cmd_dp_aux_access dp_aux_access;
+ struct dmub_rb_cmd_outbox1_enable outbox1_enable;
};
+union dmub_rb_out_cmd {
+ struct dmub_rb_cmd_common cmd_common;
+ struct dmub_rb_cmd_dp_aux_reply dp_aux_reply;
+ struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify;
+};
#pragma pack(pop)
@@ -764,6 +848,25 @@ static inline bool dmub_rb_push_front(struct dmub_rb *rb,
return true;
}
+static inline bool
[PATCH 5/9] drm/amd/display: Calc DLG from dummy p-state if full p-state unsupported
From: Joshua Aberback
[Why]
Currently, when full p-state changes are not supported, DLG parameters
are calculated for no p-state support at all. However, we are required
to always support dummy p-state changes, so we should instead calculate
DLG based on dummy p-state latency when full p-state is unsupported.
This behaviour already exists for DCN2.
[How]
- move DLG calculation inside WM calculation
- if p-state unsupported, do not recalculate for set A, instead copy from
set C, and perform DLG calculation with dummy p-state latency
Signed-off-by: Joshua Aberback
Reviewed-by: Jun Lei
Acked-by: Rodrigo Siqueira
---
.../drm/amd/display/dc/dcn30/dcn30_resource.c | 114 --
.../drm/amd/display/dc/dcn30/dcn30_resource.h | 5 +
.../gpu/drm/amd/display/dc/inc/core_types.h | 2 +-
3 files changed, 80 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
index dde87baf1370..7f3354b3512d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
@@ -2127,7 +2127,7 @@ static bool dcn30_internal_validate_bw(
return out;
}
-static void dcn30_calculate_wm(
+void dcn30_calculate_wm_and_dlg(
struct dc *dc, struct dc_state *context,
display_e2e_pipe_params_st *pipes,
int pipe_cnt,
@@ -2135,6 +2135,8 @@ static void dcn30_calculate_wm(
{
int i, pipe_idx;
double dcfclk =
context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
+ bool pstate_en =
context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]
!=
+ dm_dram_clock_change_unsupported;
if (context->bw_ctx.dml.soc.min_dcfclk > dcfclk)
dcfclk = context->bw_ctx.dml.soc.min_dcfclk;
@@ -2168,30 +2170,12 @@ static void dcn30_calculate_wm(
pipes[0].clks_cfg.voltage = vlevel;
pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
- /* Set C:
-* DCFCLK: Min Required
-* FCLK(proportional to UCLK): 1GHz or Max
-* pstate latency overriden to 5us
-*/
- if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) {
- context->bw_ctx.dml.soc.dram_clock_change_latency_us =
dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us;
- context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us =
dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us;
- context->bw_ctx.dml.soc.sr_exit_time_us =
dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us;
- }
- context->bw_ctx.bw.dcn.watermarks.c.urgent_ns =
get_wm_urgent(>bw_ctx.dml, pipes, pipe_cnt) * 1000;
-
context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns =
get_wm_stutter_enter_exit(>bw_ctx.dml, pipes, pipe_cnt) * 1000;
- context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns =
get_wm_stutter_exit(>bw_ctx.dml, pipes, pipe_cnt) * 1000;
- context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns =
get_wm_dram_clock_change(>bw_ctx.dml, pipes, pipe_cnt) * 1000;
- context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns =
get_wm_memory_trip(>bw_ctx.dml, pipes, pipe_cnt) * 1000;
- context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom =
get_fraction_of_urgent_bandwidth(>bw_ctx.dml, pipes, pipe_cnt) * 1000;
- context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip =
get_fraction_of_urgent_bandwidth_imm_flip(>bw_ctx.dml, pipes,
pipe_cnt) * 1000;
- context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns =
get_urgent_latency(>bw_ctx.dml, pipes, pipe_cnt) * 1000;
-
/* Set D:
* DCFCLK: Min Required
* FCLK(proportional to UCLK): 1GHz or Max
* sr_enter_exit = 4, sr_exit = 2us
*/
+ /*
if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].valid) {
context->bw_ctx.dml.soc.dram_clock_change_latency_us =
dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us;
context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us =
dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us;
@@ -2205,29 +2189,72 @@ static void dcn30_calculate_wm(
context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom =
get_fraction_of_urgent_bandwidth(>bw_ctx.dml, pipes, pipe_cnt) * 1000;
context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip =
get_fraction_of_urgent_bandwidth_imm_flip(>bw_ctx.dml, pipes,
pipe_cnt) * 1000;
context->bw_ctx.bw.dcn.watermarks.d.urgent_latency_ns =
get_urgent_latency(>bw_ctx.dml, pipes, pipe_cnt) * 1000;
+ */
- /* Set A:
+ /* Set C:
* DCFCLK: Min Required
* FCLK(proportional to UCLK): 1GHz or Max
-*
-* Set A calculated
[PATCH 2/9] drm/amd/display: Add dp_set_dsc_pps_info_packet to virtual stream encoder
From: Eric Bernstein
Signed-off-by: Eric Bernstein
Reviewed-by: Dmytro Laktyushkin
Acked-by: Rodrigo Siqueira
---
.../drm/amd/display/dc/core/dc_link_hwss.c| 21 ++-
.../dc/virtual/virtual_stream_encoder.c | 7 +++
2 files changed, 18 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
index dba338c88256..11a619befb42 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
@@ -493,13 +493,15 @@ void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool
enable)
OPTC_DSC_DISABLED, 0, 0);
/* disable DSC in stream encoder */
- if (dc_is_dp_signal(stream->signal) &&
!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
-
pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(
- pipe_ctx->stream_res.stream_enc,
- OPTC_DSC_DISABLED, 0, 0);
-
-
pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet(
- pipe_ctx->stream_res.stream_enc, false,
NULL);
+ if (dc_is_dp_signal(stream->signal)) {
+
+ if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+
pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(
+ pipe_ctx->stream_res.stream_enc,
+ OPTC_DSC_DISABLED, 0, 0);
+
pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet(
+
pipe_ctx->stream_res.stream_enc, false, NULL);
+ }
}
/* disable DSC block */
@@ -536,7 +538,6 @@ bool dp_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool
enable)
bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable)
{
struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;
- struct dc *dc = pipe_ctx->stream->ctx->dc;
struct dc_stream_state *stream = pipe_ctx->stream;
if (!pipe_ctx->stream->timing.flags.DSC || !dsc)
@@ -559,7 +560,7 @@ bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool
enable)
DC_LOG_DSC(" ");
dsc->funcs->dsc_get_packed_pps(dsc, _cfg,
_packed_pps[0]);
- if (dc_is_dp_signal(stream->signal) &&
!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+ if (dc_is_dp_signal(stream->signal)) {
DC_LOG_DSC("Setting stream encoder DSC PPS SDP for
engine %d\n", (int)pipe_ctx->stream_res.stream_enc->id);
pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet(
pipe_ctx->stream_res.stream_enc,
@@ -568,7 +569,7 @@ bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool
enable)
}
} else {
/* disable DSC PPS in stream encoder */
- if (dc_is_dp_signal(stream->signal) &&
!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+ if (dc_is_dp_signal(stream->signal)) {
pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet(
pipe_ctx->stream_res.stream_enc, false, NULL);
}
diff --git a/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c
b/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c
index f0a0d419e555..1053b165c139 100644
--- a/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c
@@ -99,6 +99,12 @@ static void virtual_setup_stereo_sync(
bool enable)
{}
+static void virtual_stream_encoder_set_dsc_pps_info_packet(
+ struct stream_encoder *enc,
+ bool enable,
+ uint8_t *dsc_packed_pps)
+{}
+
static const struct stream_encoder_funcs virtual_str_enc_funcs = {
.dp_set_odm_combine =
virtual_enc_dp_set_odm_combine,
@@ -128,6 +134,7 @@ static const struct stream_encoder_funcs
virtual_str_enc_funcs = {
.hdmi_reset_stream_attribute =
virtual_stream_encoder_reset_hdmi_stream_attribute,
.dig_connect_to_otg = virtual_dig_connect_to_otg,
.setup_stereo_sync = virtual_setup_stereo_sync,
+ .dp_set_dsc_pps_info_packet =
virtual_stream_encoder_set_dsc_pps_info_packet,
};
bool virtual_stream_encoder_construct(
--
2.28.0
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[PATCH 6/9] drm/amd/display: Add debug param to force dio disable
From: Wesley Chalmers
[WHY]
At the moment, some tests are failing because cur_link_settings is
invalid. As a workaround, add an option to force dio disable.
Signed-off-by: Wesley Chalmers
Reviewed-by: Martin Leung
Acked-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 2 ++
drivers/gpu/drm/amd/display/dc/dc.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 9fabe264cdea..dc90d26e2663 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -735,6 +735,8 @@ static bool dc_construct(struct dc *dc,
dc->clk_mgr->force_smu_not_present = init_params->force_smu_not_present;
#endif
+ dc->debug.force_ignore_link_settings =
init_params->force_ignore_link_settings;
+
if (dc->res_pool->funcs->update_bw_bounding_box)
dc->res_pool->funcs->update_bw_bounding_box(dc,
dc->clk_mgr->bw_params);
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 061ca15660ac..82fe0ab56e3a 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -503,6 +503,7 @@ struct dc_debug_options {
bool usbc_combo_phy_reset_wa;
bool disable_dsc;
bool enable_dram_clock_change_one_display_vactive;
+ bool force_ignore_link_settings;
};
struct dc_debug_data {
@@ -660,6 +661,7 @@ struct dc_init_data {
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
bool force_smu_not_present;
#endif
+ bool force_ignore_link_settings;
};
struct dc_callback_init {
--
2.28.0
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[PATCH 1/9] drm/amd/display: Update NV1x SR latency values
From: Alvin Lee
[Why]
HW team measurement requires updating values
[How]
Update bounding box values
Signed-off-by: Alvin Lee
Reviewed-by: Jun Lei
Acked-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 18b9465057ff..bf37a229a342 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -298,8 +298,8 @@ static struct _vcs_dpi_soc_bounding_box_st dcn2_0_soc = {
},
},
.num_states = 5,
- .sr_exit_time_us = 8.6,
- .sr_enter_plus_exit_time_us = 10.9,
+ .sr_exit_time_us = 11.6,
+ .sr_enter_plus_exit_time_us = 13.9,
.urgent_latency_us = 4.0,
.urgent_latency_pixel_data_only_us = 4.0,
.urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
--
2.28.0
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Re: CONFIG_AMDGPU triggers full rebuild
Maybe MMU notifiers? But honestly I don't know for sure. Christian. Am 25.09.20 um 16:29 schrieb Thomas Zimmermann: Hi, whenever I change the option CONFIG_AMDGPU, I have to rebuild the whole kernel. I guess it auto-selects some architecture-specific feature. That full rebuild might be avoidable if I could enable that feature permanently. Any ideas what this could be and how to avoid the full rebuilt? Best regards Thomas ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 3/9] drm/amd/display: Ensure all debug bits are passed to fw
From: Wyatt Wood [Why] Some debug bits are not being copied from driver to fw. [How] Copy debug bits properly. Signed-off-by: Wyatt Wood Reviewed-by: Anthony Koo Acked-by: Rodrigo Siqueira --- drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c index bf24f1029547..67af67ef2865 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c @@ -256,10 +256,11 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub, copy_settings_data->smu_optimizations_en= psr_context->allow_smu_optimizations; copy_settings_data->frame_delay = psr_context->frame_delay; copy_settings_data->frame_cap_ind = psr_context->psrFrameCaptureIndicationReq; + copy_settings_data->init_sdp_deadline = psr_context->sdpTransmitLineNumDeadline; + copy_settings_data->debug.u32All = 0; copy_settings_data->debug.bitfields.visual_confirm = dc->dc->debug.visual_confirm == VISUAL_CONFIRM_PSR ? true : false; - copy_settings_data->debug.bitfields.use_hw_lock_mgr = 1; - copy_settings_data->init_sdp_deadline = psr_context->sdpTransmitLineNumDeadline; + copy_settings_data->debug.bitfields.use_hw_lock_mgr = 1; dc_dmub_srv_cmd_queue(dc->dmub_srv, ); dc_dmub_srv_cmd_execute(dc->dmub_srv); -- 2.28.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 9/9] drm/amd/display: disable stream if pixel clock changed with link active
From: Chiawen Huang
[Why]
Vbios uses preferred timing to turn on edp but OS could use other
timing. If change pixel clock when link active, there is unexpected
garbage on monitor.
[How]
Once pixel clock changed, the driver needs to disable stream.
Signed-off-by: Chiawen Huang
Reviewed-by: Tony Cheng
Acked-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 76946a7d47ca..2a725a5fba40 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -864,7 +864,6 @@ static void disable_vbios_mode_if_required(
if (stream->link->local_sink &&
stream->link->local_sink->sink_signal ==
SIGNAL_TYPE_EDP) {
link = stream->link;
- break;
}
if (link != NULL) {
--
2.28.0
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[PATCH 4/9] drm/amd/display: disable stream if pixel clock changed with link active
From: Chiawen Huang
[Why]
Vbios uses preferred timing to turn on edp but OS could use other
timing. If change pixel clock when link active, there is unexpected
garbage on monitor.
[How]
Once pixel clock changed, the driver needs to disable stream.
Signed-off-by: Chiawen Huang
Reviewed-by: Tony Cheng
Acked-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 62 ++-
.../display/dc/dce110/dce110_hw_sequencer.c | 2 +-
2 files changed, 60 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 7e74ddc1c708..9fabe264cdea 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -842,6 +842,61 @@ static void disable_dangling_plane(struct dc *dc, struct
dc_state *context)
dc_release_state(current_ctx);
}
+static void disable_vbios_mode_if_required(
+ struct dc *dc,
+ struct dc_state *context)
+{
+ unsigned int i;
+
+ /* check if timing_changed, disable stream*/
+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ struct dc_stream_state *stream = NULL;
+ struct dc_link *link = NULL;
+ struct pipe_ctx *pipe = NULL;
+
+ pipe = >res_ctx.pipe_ctx[i];
+ stream = pipe->stream;
+ if (stream == NULL)
+ continue;
+
+ if (stream->link->local_sink &&
+ stream->link->local_sink->sink_signal ==
SIGNAL_TYPE_EDP) {
+ link = stream->link;
+ break;
+ }
+
+ if (link != NULL) {
+ unsigned int enc_inst, tg_inst = 0;
+ unsigned int pix_clk_100hz;
+
+ enc_inst =
link->link_enc->funcs->get_dig_frontend(link->link_enc);
+ if (enc_inst != ENGINE_ID_UNKNOWN) {
+ for (i = 0; i < dc->res_pool->stream_enc_count;
i++) {
+ if (dc->res_pool->stream_enc[i]->id ==
enc_inst) {
+ tg_inst =
dc->res_pool->stream_enc[i]->funcs->dig_source_otg(
+
dc->res_pool->stream_enc[i]);
+ break;
+ }
+ }
+
+
dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz(
+ dc->res_pool->dp_clock_source,
+ tg_inst, _clk_100hz);
+
+ if (link->link_status.link_active) {
+ uint32_t requested_pix_clk_100hz =
+
pipe->stream_res.pix_clk_params.requested_pix_clk_100hz;
+
+ if (pix_clk_100hz !=
requested_pix_clk_100hz) {
+ core_link_disable_stream(pipe);
+ pipe->stream->dpms_off = false;
+ }
+ }
+ }
+ }
+ }
+}
+
static void wait_for_no_pipes_pending(struct dc *dc, struct dc_state *context)
{
int i;
@@ -1278,13 +1333,14 @@ static enum dc_status dc_commit_state_no_check(struct
dc *dc, struct dc_state *c
for (i = 0; i < context->stream_count; i++)
dc_streams[i] = context->streams[i];
- if (!dcb->funcs->is_accelerated_mode(dcb))
+ if (!dcb->funcs->is_accelerated_mode(dcb)) {
+ disable_vbios_mode_if_required(dc, context);
dc->hwss.enable_accelerated_mode(dc, context);
+ }
- for (i = 0; i < context->stream_count; i++) {
+ for (i = 0; i < context->stream_count; i++)
if (context->streams[i]->apply_seamless_boot_optimization)
dc->optimize_seamless_boot_streams++;
- }
if (context->stream_count > dc->optimize_seamless_boot_streams ||
context->stream_count == 0)
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 27a1262a20f6..c73768ed250e 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1654,7 +1654,7 @@ void dce110_enable_accelerated_mode(struct dc *dc, struct
dc_state *context)
// enable fastboot if backend is enabled on eDP
if
(edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc)) {
/* Set optimization flag on eDP stream*/
- if (edp_stream) {
+ if (edp_stream
[PATCH] drm/amdgpu: fix a warning in amdgpu_ras.c
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c: In function ‘amdgpu_ras_fs_init’: drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:1284:2: warning: ignoring return value of ‘sysfs_create_group’, declared with attribute warn_unused_result [-Wunused-result] 1284 | sysfs_create_group(>dev->kobj, ); | ^~~~ Signed-off-by: Alex Deucher --- Do we care whether this fails or not? drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 49d10330bf64..67724049a0fc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -1281,9 +1281,7 @@ static int amdgpu_ras_fs_init(struct amdgpu_device *adev) sysfs_bin_attr_init(bin_attrs[0]); } - sysfs_create_group(>dev->kobj, ); - - return 0; + return sysfs_create_group(>dev->kobj, ); } static int amdgpu_ras_fs_fini(struct amdgpu_device *adev) -- 2.25.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
CONFIG_AMDGPU triggers full rebuild
Hi, whenever I change the option CONFIG_AMDGPU, I have to rebuild the whole kernel. I guess it auto-selects some architecture-specific feature. That full rebuild might be avoidable if I could enable that feature permanently. Any ideas what this could be and how to avoid the full rebuilt? Best regards Thomas -- Thomas Zimmermann Graphics Driver Developer SUSE Software Solutions Germany GmbH Maxfeldstr. 5, 90409 Nürnberg, Germany (HRB 36809, AG Nürnberg) Geschäftsführer: Felix Imendörffer signature.asc Description: OpenPGP digital signature ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: amd-staging-drm-next has a compilation issue
Thanks Alex,
I already tested the patch and everything looks fine from the
compilation perspective.
Best Regards
On 09/25, Alex Deucher wrote:
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwork.freedesktop.org%2Fpatch%2F392192%2Fdata=02%7C01%7CRodrigo.Siqueira%40amd.com%7Cb72ce334a3484dddab6c08d8615e65d2%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637366405348981954sdata=7kPoyo6sCqlkXBTJLbppjedOgcQnRT8ZmJICCCEXCM4%3Dreserved=0
>
> Alex
>
> On Fri, Sep 25, 2020 at 9:55 AM Rodrigo Siqueira
> wrote:
> >
> > Hi,
> >
> > When I tried to build the latest code from amd-staging-drm-next, I got
> > the following build failure:
> >
> > drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c: In function
> > ‘amdgpu_virt_init_data_exchange’:
> > drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c:586:10: error: ‘struct
> > amdgpu_device’ has no member named ‘fw_vram_usage’
> > 586 | if (adev->fw_vram_usage.va != NULL) {
> > | ^~
> > drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c:591:9: error: ‘struct
> > amdgpu_device’ has no member named ‘fw_vram_usage’
> > 591 |(adev->fw_vram_usage.va + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10));
> > | ^~
> > drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c:594:9: error: ‘struct
> > amdgpu_device’ has no member named ‘fw_vram_usage’
> > 594 |(adev->fw_vram_usage.va + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB << 10));
> > | ^~
> > make[4]: *** [scripts/Makefile.build:283:
> > drivers/gpu/drm/amd/amdgpu/amdgpu_virt.o] Error 1
> >
> > The latest commit that I tried:
> >
> > drm/amd/pm: fix screen flicker seen on Navi14 with 2*4K monitors
> >
> > Does anyone has seen this issue?
> >
> > Best Regards
> >
> > --
> > Rodrigo Siqueira
> > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fsiqueira.tech%2Fdata=02%7C01%7CRodrigo.Siqueira%40amd.com%7Cb72ce334a3484dddab6c08d8615e65d2%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637366405348981954sdata=w83BWszpGXMuId7GZJ3ecnJ8PCBOhpqDpTtKKSo4K0g%3Dreserved=0
> > ___
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org
> > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfxdata=02%7C01%7CRodrigo.Siqueira%40amd.com%7Cb72ce334a3484dddab6c08d8615e65d2%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637366405348981954sdata=S8kmcb7g4bTnhbaDRLdQ%2B%2BCqVL7%2FhSugc9BHyIGaDW4%3Dreserved=0
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Re: [PATCH] drm/amdgpu/virt: fix the build
Tested-by: Rodrigo Siqueira
On 09/24, Alex Deucher wrote:
> drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c: In function
> ‘amdgpu_virt_init_data_exchange’:
> drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c:586:10: error: ‘struct
> amdgpu_device’ has no member named ‘fw_vram_usage’
> 586 | if (adev->fw_vram_usage.va != NULL) {
> | ^~
> drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c:591:9: error: ‘struct amdgpu_device’
> has no member named ‘fw_vram_usage’
> 591 |(adev->fw_vram_usage.va + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10));
> | ^~
> drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c:594:9: error: ‘struct amdgpu_device’
> has no member named ‘fw_vram_usage’
> 594 |(adev->fw_vram_usage.va + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB << 10));
> | ^~
> make[4]: *** [scripts/Makefile.build:283:
> drivers/gpu/drm/amd/amdgpu/amdgpu_virt.o] Error 1
> make[4]: *** Waiting for unfinished jobs
> make[3]: *** [scripts/Makefile.build:500: drivers/gpu/drm/amd/amdgpu] Error 2
> make[3]: *** Waiting for unfinished jobs
> make[2]: *** [scripts/Makefile.build:500: drivers/gpu/drm] Error 2
> make[1]: *** [scripts/Makefile.build:500: drivers/gpu] Error 2
> make: *** [Makefile:1788: drivers] Error 2
>
> Cc: Bokun Zhang
> Fixes: 614e7ac92979 ("drm/amdgpu: Implement new guest side VF2PF message
> transaction")
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> index 1f1171812e35..836d784456e5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> @@ -583,15 +583,15 @@ void amdgpu_virt_init_data_exchange(struct
> amdgpu_device *adev)
> adev->virt.fw_reserve.p_vf2pf = NULL;
> adev->virt.vf2pf_update_interval_ms = 0;
>
> - if (adev->fw_vram_usage.va != NULL) {
> + if (adev->mman.fw_vram_usage_va != NULL) {
> adev->virt.vf2pf_update_interval_ms = 2000;
>
> adev->virt.fw_reserve.p_pf2vf =
> (struct amd_sriov_msg_pf2vf_info_header *)
> - (adev->fw_vram_usage.va +
> (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10));
> + (adev->mman.fw_vram_usage_va +
> (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10));
> adev->virt.fw_reserve.p_vf2pf =
> (struct amd_sriov_msg_vf2pf_info_header *)
> - (adev->fw_vram_usage.va +
> (AMD_SRIOV_MSG_VF2PF_OFFSET_KB << 10));
> + (adev->mman.fw_vram_usage_va +
> (AMD_SRIOV_MSG_VF2PF_OFFSET_KB << 10));
>
> amdgpu_virt_read_pf2vf_data(adev);
> amdgpu_virt_write_vf2pf_data(adev);
> --
> 2.25.4
>
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Re: amd-staging-drm-next has a compilation issue
https://patchwork.freedesktop.org/patch/392192/
Alex
On Fri, Sep 25, 2020 at 9:55 AM Rodrigo Siqueira
wrote:
>
> Hi,
>
> When I tried to build the latest code from amd-staging-drm-next, I got
> the following build failure:
>
> drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c: In function
> ‘amdgpu_virt_init_data_exchange’:
> drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c:586:10: error: ‘struct
> amdgpu_device’ has no member named ‘fw_vram_usage’
> 586 | if (adev->fw_vram_usage.va != NULL) {
> | ^~
> drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c:591:9: error: ‘struct amdgpu_device’
> has no member named ‘fw_vram_usage’
> 591 |(adev->fw_vram_usage.va + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10));
> | ^~
> drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c:594:9: error: ‘struct amdgpu_device’
> has no member named ‘fw_vram_usage’
> 594 |(adev->fw_vram_usage.va + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB << 10));
> | ^~
> make[4]: *** [scripts/Makefile.build:283:
> drivers/gpu/drm/amd/amdgpu/amdgpu_virt.o] Error 1
>
> The latest commit that I tried:
>
> drm/amd/pm: fix screen flicker seen on Navi14 with 2*4K monitors
>
> Does anyone has seen this issue?
>
> Best Regards
>
> --
> Rodrigo Siqueira
> https://siqueira.tech
> ___
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> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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amd-staging-drm-next has a compilation issue
Hi,
When I tried to build the latest code from amd-staging-drm-next, I got
the following build failure:
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c: In function
‘amdgpu_virt_init_data_exchange’:
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c:586:10: error: ‘struct amdgpu_device’
has no member named ‘fw_vram_usage’
586 | if (adev->fw_vram_usage.va != NULL) {
| ^~
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c:591:9: error: ‘struct amdgpu_device’
has no member named ‘fw_vram_usage’
591 |(adev->fw_vram_usage.va + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10));
| ^~
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c:594:9: error: ‘struct amdgpu_device’
has no member named ‘fw_vram_usage’
594 |(adev->fw_vram_usage.va + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB << 10));
| ^~
make[4]: *** [scripts/Makefile.build:283:
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.o] Error 1
The latest commit that I tried:
drm/amd/pm: fix screen flicker seen on Navi14 with 2*4K monitors
Does anyone has seen this issue?
Best Regards
--
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https://siqueira.tech
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RE: [PATCH] amdgpu/drm: cleanup navi10 ih logic about older ASIC
[AMD Public Use]
Hi Likun,
Let's take a step back to check with Alex S why he add the ASIC type check
here. I'm under impression there was a change to use navi10_ih block for
arcturus, but haven't followed up closely yet.
Regards,
Hawking
-Original Message-
From: Gao, Likun
Sent: Friday, September 25, 2020 16:56
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Gao, Likun
Subject: [PATCH] amdgpu/drm: cleanup navi10 ih logic about older ASIC
From: Likun Gao
The ASIC which is older than navi10 will not call into navi10_ih related
function, so cleanup the related code path.
Signed-off-by: Likun Gao
Change-Id: Idf73b73f1f4f19031260c220798e5fffbb2cecd2
---
drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 105 +++--
1 file changed, 9 insertions(+), 96 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
index 74b1e7dc49a9..92b5dc2931b6 100644
--- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
@@ -94,14 +94,7 @@ static void navi10_ih_enable_interrupts(struct amdgpu_device
*adev)
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1);
- if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) {
- if (psp_reg_program(>psp, PSP_REG_IH_RB_CNTL,
ih_rb_cntl)) {
- DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
- return;
- }
- } else {
- WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
- }
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
adev->irq.ih.enabled = true;
@@ -109,15 +102,7 @@ static void navi10_ih_enable_interrupts(struct
amdgpu_device *adev)
ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
RB_ENABLE, 1);
- if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) {
- if (psp_reg_program(>psp,
PSP_REG_IH_RB_CNTL_RING1,
- ih_rb_cntl)) {
- DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n");
- return;
- }
- } else {
- WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
- }
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
adev->irq.ih1.enabled = true;
}
@@ -125,15 +110,7 @@ static void navi10_ih_enable_interrupts(struct
amdgpu_device *adev)
ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,
RB_ENABLE, 1);
- if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) {
- if (psp_reg_program(>psp,
PSP_REG_IH_RB_CNTL_RING2,
- ih_rb_cntl)) {
- DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n");
- return;
- }
- } else {
- WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
- }
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
adev->irq.ih2.enabled = true;
}
}
@@ -151,14 +128,7 @@ static void navi10_ih_disable_interrupts(struct
amdgpu_device *adev)
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0);
- if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) {
- if (psp_reg_program(>psp, PSP_REG_IH_RB_CNTL,
ih_rb_cntl)) {
- DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
- return;
- }
- } else {
- WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
- }
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
/* set rptr, wptr to 0 */
WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); @@ -170,15 +140,7 @@ static
void navi10_ih_disable_interrupts(struct amdgpu_device *adev)
ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
RB_ENABLE, 0);
- if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) {
- if (psp_reg_program(>psp,
PSP_REG_IH_RB_CNTL_RING1,
- ih_rb_cntl)) {
- DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n");
- return;
- }
-
[PATCH] amdgpu/drm: cleanup navi10 ih logic about older ASIC
From: Likun Gao
The ASIC which is older than navi10 will not call into navi10_ih
related function, so cleanup the related code path.
Signed-off-by: Likun Gao
Change-Id: Idf73b73f1f4f19031260c220798e5fffbb2cecd2
---
drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 105 +++--
1 file changed, 9 insertions(+), 96 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
index 74b1e7dc49a9..92b5dc2931b6 100644
--- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
@@ -94,14 +94,7 @@ static void navi10_ih_enable_interrupts(struct amdgpu_device
*adev)
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1);
- if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) {
- if (psp_reg_program(>psp, PSP_REG_IH_RB_CNTL,
ih_rb_cntl)) {
- DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
- return;
- }
- } else {
- WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
- }
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
adev->irq.ih.enabled = true;
@@ -109,15 +102,7 @@ static void navi10_ih_enable_interrupts(struct
amdgpu_device *adev)
ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
RB_ENABLE, 1);
- if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) {
- if (psp_reg_program(>psp,
PSP_REG_IH_RB_CNTL_RING1,
- ih_rb_cntl)) {
- DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n");
- return;
- }
- } else {
- WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
- }
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
adev->irq.ih1.enabled = true;
}
@@ -125,15 +110,7 @@ static void navi10_ih_enable_interrupts(struct
amdgpu_device *adev)
ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,
RB_ENABLE, 1);
- if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) {
- if (psp_reg_program(>psp,
PSP_REG_IH_RB_CNTL_RING2,
- ih_rb_cntl)) {
- DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n");
- return;
- }
- } else {
- WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
- }
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
adev->irq.ih2.enabled = true;
}
}
@@ -151,14 +128,7 @@ static void navi10_ih_disable_interrupts(struct
amdgpu_device *adev)
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0);
- if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) {
- if (psp_reg_program(>psp, PSP_REG_IH_RB_CNTL,
ih_rb_cntl)) {
- DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
- return;
- }
- } else {
- WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
- }
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
/* set rptr, wptr to 0 */
WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0);
@@ -170,15 +140,7 @@ static void navi10_ih_disable_interrupts(struct
amdgpu_device *adev)
ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
RB_ENABLE, 0);
- if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) {
- if (psp_reg_program(>psp,
PSP_REG_IH_RB_CNTL_RING1,
- ih_rb_cntl)) {
- DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n");
- return;
- }
- } else {
- WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
- }
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
/* set rptr, wptr to 0 */
WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0);
WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0);
@@ -190,15 +152,7 @@ static void navi10_ih_disable_interrupts(struct
amdgpu_device *adev)
ih_rb_cntl =
Re: [PATCH v3 00/22] Convert all remaining drivers to GEM object functions
Hi Am 23.09.20 um 16:33 schrieb Christian König: > Feel free to add an Acked-by: Christian König > to all patches which I haven't explicitly reviewed. Done, thanks. > > I would say we should just push this to drm-misc-next now. It's merged now. Best regards Thomas > > Thanks for the nice cleanup, > Christian. > > Am 23.09.20 um 12:21 schrieb Thomas Zimmermann: >> The GEM and PRIME related callbacks in struct drm_driver are >> deprecated in >> favor of GEM object functions in struct drm_gem_object_funcs. This >> patchset >> converts the remaining drivers to object functions and removes most of >> the >> obsolete interfaces. >> >> Version 3 of this patchset mostly fixes drm_gem_prime_handle_to_fd and >> updates i.MX's dcss driver. The driver was missing from earlier versions >> and still needs review. >> >> Patches #1 to #6, #8 to #17 and #19 to #20 convert DRM drivers to GEM >> object >> functions, one by one. Each patch moves existing callbacks from struct >> drm_driver to an instance of struct drm_gem_object_funcs, and sets these >> funcs when the GEM object is initialized. The expection is >> .gem_prime_mmap. >> There are different ways of how drivers implement the callback, and >> moving >> it to GEM object functions requires a closer review for each. >> >> Patch #18 fixes virtgpu to use GEM object functions where possible. The >> driver recently introduced a function for one of the deprecated >> callbacks. >> >> Patches #7 and #20 convert i.MX's dcss and xlnx to CMA helper macros. >> There's >> no apparent reason why the drivers do the GEM setup on their's own. >> Using CMA >> helper macros adds GEM object functions implicitly. >> >> With most of the GEM and PRIME moved to GEM object functions, related >> code >> in struct drm_driver and in the DRM core/helpers is being removed by >> patch >> #22. >> >> Further testing is welcome. I tested the drivers for which I have HW >> available. These are gma500, i915, nouveau, radeon and vc4. The console, >> Weston and Xorg apparently work with the patches applied. >> >> v3: >> * restore default call to drm_gem_prime_export() in >> drm_gem_prime_handle_to_fd() >> * return -ENOSYS if get_sg_table is not set >> * drop all checks for obj->funcs >> * clean up TODO list and documentation >> v2: >> * moved code in amdgpu and radeon >> * made several functions static in various drivers >> * updated TODO-list item >> * fix virtgpu >> >> Thomas Zimmermann (22): >> drm/amdgpu: Introduce GEM object functions >> drm/armada: Introduce GEM object functions >> drm/etnaviv: Introduce GEM object functions >> drm/exynos: Introduce GEM object functions >> drm/gma500: Introduce GEM object functions >> drm/i915: Introduce GEM object functions >> drm/imx/dcss: Initialize DRM driver instance with CMA helper macro >> drm/mediatek: Introduce GEM object functions >> drm/msm: Introduce GEM object funcs >> drm/nouveau: Introduce GEM object functions >> drm/omapdrm: Introduce GEM object functions >> drm/pl111: Introduce GEM object functions >> drm/radeon: Introduce GEM object functions >> drm/rockchip: Convert to drm_gem_object_funcs >> drm/tegra: Introduce GEM object functions >> drm/vc4: Introduce GEM object functions >> drm/vgem: Introduce GEM object functions >> drm/virtgpu: Set PRIME export function in struct drm_gem_object_funcs >> drm/vkms: Introduce GEM object functions >> drm/xen: Introduce GEM object functions >> drm/xlnx: Initialize DRM driver instance with CMA helper macro >> drm: Remove obsolete GEM and PRIME callbacks from struct drm_driver >> >> Documentation/gpu/drm-mm.rst | 4 +- >> Documentation/gpu/todo.rst | 9 +- >> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 6 -- >> drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 23 +++-- >> drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h | 5 -- >> drivers/gpu/drm/armada/armada_drv.c | 3 - >> drivers/gpu/drm/armada/armada_gem.c | 12 ++- >> drivers/gpu/drm/armada/armada_gem.h | 2 - >> drivers/gpu/drm/drm_gem.c | 53 >> drivers/gpu/drm/drm_gem_cma_helper.c | 8 +- >> drivers/gpu/drm/drm_prime.c | 14 +-- >> drivers/gpu/drm/etnaviv/etnaviv_drv.c | 13 --- >> drivers/gpu/drm/etnaviv/etnaviv_drv.h | 1 - >> drivers/gpu/drm/etnaviv/etnaviv_gem.c | 19 - >> drivers/gpu/drm/exynos/exynos_drm_drv.c | 10 --- >> drivers/gpu/drm/exynos/exynos_drm_gem.c | 15 >> drivers/gpu/drm/gma500/framebuffer.c | 2 + >> drivers/gpu/drm/gma500/gem.c | 18 +++- >> drivers/gpu/drm/gma500/gem.h | 3 + >> drivers/gpu/drm/gma500/psb_drv.c | 9 -- >> drivers/gpu/drm/gma500/psb_drv.h | 2 - >> drivers/gpu/drm/i915/gem/i915_gem_object.c | 21 - >>
RE: [PATCH] drm/amdgpu/virt: fix the build
[AMD Official Use Only - Internal Distribution Only]
Reviewed-and-tested-by: Evan Quan
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: Friday, September 25, 2020 3:32 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Zhang, Bokun
Subject: [PATCH] drm/amdgpu/virt: fix the build
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c: In function
‘amdgpu_virt_init_data_exchange’:
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c:586:10: error: ‘struct amdgpu_device’
has no member named ‘fw_vram_usage’
586 | if (adev->fw_vram_usage.va != NULL) {
| ^~
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c:591:9: error: ‘struct amdgpu_device’
has no member named ‘fw_vram_usage’
591 |(adev->fw_vram_usage.va + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10));
| ^~
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c:594:9: error: ‘struct amdgpu_device’
has no member named ‘fw_vram_usage’
594 |(adev->fw_vram_usage.va + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB << 10));
| ^~
make[4]: *** [scripts/Makefile.build:283:
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.o] Error 1
make[4]: *** Waiting for unfinished jobs
make[3]: *** [scripts/Makefile.build:500: drivers/gpu/drm/amd/amdgpu] Error 2
make[3]: *** Waiting for unfinished jobs
make[2]: *** [scripts/Makefile.build:500: drivers/gpu/drm] Error 2
make[1]: *** [scripts/Makefile.build:500: drivers/gpu] Error 2
make: *** [Makefile:1788: drivers] Error 2
Cc: Bokun Zhang
Fixes: 614e7ac92979 ("drm/amdgpu: Implement new guest side VF2PF message
transaction")
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
index 1f1171812e35..836d784456e5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
@@ -583,15 +583,15 @@ void amdgpu_virt_init_data_exchange(struct amdgpu_device
*adev)
adev->virt.fw_reserve.p_vf2pf = NULL;
adev->virt.vf2pf_update_interval_ms = 0;
-if (adev->fw_vram_usage.va != NULL) {
+if (adev->mman.fw_vram_usage_va != NULL) {
adev->virt.vf2pf_update_interval_ms = 2000;
adev->virt.fw_reserve.p_pf2vf =
(struct amd_sriov_msg_pf2vf_info_header *)
-(adev->fw_vram_usage.va + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10));
+(adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10));
adev->virt.fw_reserve.p_vf2pf =
(struct amd_sriov_msg_vf2pf_info_header *)
-(adev->fw_vram_usage.va + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB << 10));
+(adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB << 10));
amdgpu_virt_read_pf2vf_data(adev);
amdgpu_virt_write_vf2pf_data(adev);
--
2.25.4
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