Re: [RFC PATCH 0/3] add ttm trace event support

[Christian König]

Not a bad start, but that needs quite some more work.

First of all please rebase on top of current drm-misc-next, a whole 
bunch of the stuff you want to trace here was already removed or is 
about to be removed.


Then concentrate on the necessary trace points, for example 
ttm:ttm_bo_device_init/release are overkill.


On the other hand I'm missing important events like pool shrink, tt 
swapout/swapin (ttm_bo_swapout can be dropped) and especially BO init.


I would separate the patches into one for each trace point. Not a must 
have, but it could make it easier to review and we can discuss for each 
one separately.


Thanks,
Christian.

Am 28.01.21 um 08:13 schrieb Kevin Wang:

the kernel ftrace can better help analyze the kernel running status.
add some trace events to support TTM.

add trace events list:

ttm:ttm_bo_add_mem_to_lru
ttm:ttm_bo_del_from_lru
ttm:ttm_bo_move_mem
ttm:ttm_bo_wait
ttm:ttm_bo_evict
ttm:ttm_bo_swapout
ttm:ttm_bo_device_init
ttm:ttm_bo_device_release
ttm:ttm_bo_init_reserved
ttm:ttm_bo_validate
ttm:ttm_bo_release
ttm:ttm_bo_mmap
ttm:ttm_bo_vm_fault
ttm:ttm_bo_vm_access
ttm:ttm_shrink
ttm:ttm_mem_global_reserve
ttm:ttm_mem_global_free

Kevin Wang (3):
   drm/ttm: add ttm bo trace event support
   drm/ttm: add ttm vm bo trace event support
   drm/ttm: add ttm mem trace event support

  drivers/gpu/drm/ttm/ttm_bo.c |  23 ++
  drivers/gpu/drm/ttm/ttm_bo_vm.c  |  12 +-
  drivers/gpu/drm/ttm/ttm_memory.c |   7 +
  drivers/gpu/drm/ttm/ttm_module.c |   3 +
  drivers/gpu/drm/ttm/ttm_trace.h  | 469 +++
  5 files changed, 512 insertions(+), 2 deletions(-)
  create mode 100644 drivers/gpu/drm/ttm/ttm_trace.h



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RE: [PATCH] drm/amdgpu/swsmu: use percent rather than rpm for manual fan control

[Quan, Evan]

[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Evan Quan 

-Original Message-
From: amd-gfx  On Behalf Of Alex Deucher
Sent: Thursday, January 28, 2021 6:41 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander 
Subject: [PATCH] drm/amdgpu/swsmu: use percent rather than rpm for manual fan 
control

On some boards the rpm interface apparently does not work at all
leading to the fan not spinning or spinning at strange speeds.
Both interfaces work properly on the boards I have.
Let's try and use the percent interface instead.

Bug: 
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgitlab.freedesktop.org%2Fdrm%2Famd%2F-%2Fissues%2F1408&data=04%7C01%7Cevan.quan%40amd.com%7Cc6a08573394046ec138808d8c314a9e7%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637473840813816002%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=bBwGsp2cAmmcsIgUXvecB6ziXRwgkxJzQu9IIbgR%2Fo0%3D&reserved=0
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h   | 12 +--
 drivers/gpu/drm/amd/pm/inc/smu_v11_0.h|  7 +-
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 35 
 .../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 26 --
 .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c   | 26 --
 .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c   | 26 --
 .../gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c| 89 +++
 7 files changed, 117 insertions(+), 104 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h 
b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
index 631a36a75ae3..44279c2afccb 100644
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
@@ -173,7 +173,7 @@ enum smu_memory_pool_size
 struct smu_user_dpm_profile {
 uint32_t fan_mode;
 uint32_t power_limit;
-uint32_t fan_speed_rpm;
+uint32_t fan_speed_percent;
 uint32_t flags;

 /* user clock state information */
@@ -472,7 +472,7 @@ struct smu_context
 struct work_struct interrupt_work;

 unsigned fan_max_rpm;
-unsigned manual_fan_speed_rpm;
+unsigned manual_fan_speed_percent;

 uint32_t gfx_default_hard_min_freq;
 uint32_t gfx_default_soft_max_freq;
@@ -648,9 +648,9 @@ struct pptable_funcs {
 bool (*is_dpm_running)(struct smu_context *smu);

 /**
- * @get_fan_speed_rpm: Get the current fan speed in RPM.
+ * @get_fan_speed_percent: Get the current fan speed in percent.
  */
-int (*get_fan_speed_rpm)(struct smu_context *smu, uint32_t *speed);
+int (*get_fan_speed_percent)(struct smu_context *smu, uint32_t *speed);

 /**
  * @set_watermarks_table: Configure and upload the watermarks tables to
@@ -951,9 +951,9 @@ struct pptable_funcs {
 int (*set_fan_control_mode)(struct smu_context *smu, uint32_t mode);

 /**
- * @set_fan_speed_rpm: Set a static fan speed in RPM.
+ * @set_fan_speed_percent: Set a static fan speed in percent.
  */
-int (*set_fan_speed_rpm)(struct smu_context *smu, uint32_t speed);
+int (*set_fan_speed_percent)(struct smu_context *smu, uint32_t speed);

 /**
  * @set_xgmi_pstate: Set inter-chip global memory interconnect pstate.
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h 
b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
index 102a0cf12d7a..c7d57e9555cc 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
@@ -203,11 +203,8 @@ int
 smu_v11_0_set_fan_control_mode(struct smu_context *smu,
uint32_t mode);

-int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
-   uint32_t speed);
-
-int smu_v11_0_get_fan_speed_rpm(struct smu_context *smu,
-uint32_t *speed);
+int smu_v11_0_set_fan_speed_percent(struct smu_context *smu,
+uint32_t speed);

 int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
  uint32_t pstate);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c 
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index f958b02f9317..1c7ac81fe417 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -368,8 +368,8 @@ static void smu_restore_dpm_user_profile(struct smu_context 
*smu)
 return;
 }

-if (!ret && smu->user_dpm_profile.fan_speed_rpm) {
-ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm);
+if (!ret && smu->user_dpm_profile.fan_speed_percent) {
+ret = smu_set_fan_speed_percent(smu, smu->user_dpm_profile.fan_speed_percent);
 if (ret)
 dev_err(smu->adev->dev, "Failed to set manual fan speed\n");
 }
@@ -2025,6 +2025,7 @@ int smu_set_gfx_cgpg(struct smu_context *smu, bool 
enabled)

 int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed)
 {
+u32 percent;
 int ret = 0;

 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
@@ -2032,10 +2033,11 @@ int smu_set_fan_speed_rpm(struct smu_context *smu, 
uint32_t speed)

 mutex_lock(&smu->mutex);

-if (smu->ppt_funcs->set_fan_speed_rpm) {
-ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed);
+if (smu->ppt_funcs->set_fan_speed_percent) {
+percent = speed * 100 / smu->fan_max_rpm;
+ret = smu->ppt_funcs->

[RFC PATCH 3/3] drm/ttm: add ttm mem trace event support

[Kevin Wang]

add ttm memory related trace event support

trace events:
ttm:ttm_shrink
ttm:ttm_mem_global_reserve
ttm:ttm_mem_global_free

Signed-off-by: Kevin Wang 
---
 drivers/gpu/drm/ttm/ttm_memory.c |  7 
 drivers/gpu/drm/ttm/ttm_trace.h  | 70 
 2 files changed, 77 insertions(+)

diff --git a/drivers/gpu/drm/ttm/ttm_memory.c b/drivers/gpu/drm/ttm/ttm_memory.c
index acd63b70d814..27470b1f1f13 100644
--- a/drivers/gpu/drm/ttm/ttm_memory.c
+++ b/drivers/gpu/drm/ttm/ttm_memory.c
@@ -39,6 +39,8 @@
 #include 
 #include 
 
+#include "ttm_trace.h"
+
 #define TTM_MEMORY_ALLOC_RETRIES 4
 
 struct ttm_mem_global ttm_mem_glob;
@@ -272,6 +274,7 @@ static void ttm_shrink(struct ttm_mem_global *glob, bool 
from_wq,
int ret;
 
spin_lock(&glob->lock);
+   trace_ttm_shrink(from_wq, extra, ctx);
 
while (ttm_zones_above_swap_target(glob, from_wq, extra)) {
spin_unlock(&glob->lock);
@@ -518,6 +521,8 @@ static void ttm_mem_global_free_zone(struct ttm_mem_global 
*glob,
zone->used_mem -= amount;
}
spin_unlock(&glob->lock);
+   trace_ttm_mem_global_free(single_zone->name, amount,
+ single_zone->used_mem, single_zone->max_mem);
 }
 
 void ttm_mem_global_free(struct ttm_mem_global *glob,
@@ -590,6 +595,8 @@ static int ttm_mem_global_reserve(struct ttm_mem_global 
*glob,
ret = 0;
 out_unlock:
spin_unlock(&glob->lock);
+   trace_ttm_mem_global_reserve(single_zone->name, amount,
+ single_zone->used_mem, single_zone->max_mem);
ttm_check_swapping(glob);
 
return ret;
diff --git a/drivers/gpu/drm/ttm/ttm_trace.h b/drivers/gpu/drm/ttm/ttm_trace.h
index 9f7cc34b243b..e25b8a2c423c 100644
--- a/drivers/gpu/drm/ttm/ttm_trace.h
+++ b/drivers/gpu/drm/ttm/ttm_trace.h
@@ -388,6 +388,76 @@ TRACE_EVENT(ttm_bo_vm_access,
  __entry->offset, __entry->len, __entry->mem_type)
 );
 
+TRACE_EVENT(ttm_shrink,
+   TP_PROTO(bool from_wq, uint64_t extra, struct ttm_operation_ctx 
*ctx),
+   TP_ARGS(from_wq, extra, ctx),
+   TP_STRUCT__entry(
+__field(bool, from_wq)
+__field(bool, interruptible)
+__field(bool, wait_gpu)
+__field(uint64_t, extra)
+),
+
+   TP_fast_assign(
+  __entry->from_wq = from_wq;
+  __entry->extra = extra;
+  __entry->interruptible= ctx->interruptible;
+  __entry->wait_gpu = !ctx->no_wait_gpu;
+  ),
+
+   TP_printk("ttm_shrink: from_wq=%s, interruptible=%s, wait_gpu=%s, 
extra=0x%llx(%lld)",
+ __entry->from_wq ? "true" : "false",
+ __entry->interruptible ? "true" : "false",
+ __entry->wait_gpu? "true" : "false",
+ __entry->extra, __entry->extra)
+);
+
+TRACE_EVENT(ttm_mem_global_reserve,
+   TP_PROTO(const char *zone_name, uint64_t amount,
+uint64_t used_mem, uint64_t max_mem),
+   TP_ARGS(zone_name, amount, used_mem, max_mem),
+   TP_STRUCT__entry(
+__string(zone, zone_name)
+__field(uint64_t, amount)
+__field(uint64_t, used_mem)
+__field(uint64_t, max_mem)
+),
+
+   TP_fast_assign(
+  __assign_str(zone, zone_name);
+  __entry->amount = amount;
+  __entry->used_mem = used_mem;
+  __entry->max_mem = max_mem;
+  ),
+
+   TP_printk("zone:%s, amount=%lld, used=%lld/%lld",
+ __get_str(zone), __entry->amount,
+ __entry->used_mem, __entry->max_mem)
+);
+
+TRACE_EVENT(ttm_mem_global_free,
+   TP_PROTO(const char *zone_name, uint64_t amount,
+uint64_t used_mem, uint64_t max_mem),
+   TP_ARGS(zone_name, amount, used_mem, max_mem),
+   TP_STRUCT__entry(
+__string(zone, zone_name)
+__field(uint64_t, amount)
+__field(uint64_t, used_mem)
+__field(uint64_t, max_mem)
+),
+
+   TP_fast_assign(
+  __assign_str(zone, zone_name);
+  __entry->amount = amount;
+  __entry->used_mem = used_mem;
+  __entry->max_mem = max_mem;
+  ),
+
+   TP_printk("zone:%s, amount=%lld, used=%lld/%lld",
+ __get_str(zone), __entry->amount,
+ __entry->used_mem, __entry->max_mem)
+);

[RFC PATCH 2/3] drm/ttm: add ttm vm bo trace event support

[Kevin Wang]

add ttm bo VM related trace event support

trace events:
ttm:ttm_bo_mmap
ttm:ttm_bo_vm_fault
ttm:ttm_bo_vm_access

Signed-off-by: Kevin Wang 
---
 drivers/gpu/drm/ttm/ttm_bo_vm.c | 12 -
 drivers/gpu/drm/ttm/ttm_trace.h | 78 +
 2 files changed, 88 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/ttm/ttm_bo_vm.c b/drivers/gpu/drm/ttm/ttm_bo_vm.c
index 01693e8f24b7..aece2024c1fd 100644
--- a/drivers/gpu/drm/ttm/ttm_bo_vm.c
+++ b/drivers/gpu/drm/ttm/ttm_bo_vm.c
@@ -42,6 +42,8 @@
 #include 
 #include 
 
+#include "ttm_trace.h"
+
 static vm_fault_t ttm_bo_vm_fault_idle(struct ttm_buffer_object *bo,
struct vm_fault *vmf)
 {
@@ -429,15 +431,17 @@ vm_fault_t ttm_bo_vm_fault(struct vm_fault *vmf)
 
ret = ttm_bo_vm_reserve(bo, vmf);
if (ret)
-   return ret;
+   goto out;
 
prot = vma->vm_page_prot;
ret = ttm_bo_vm_fault_reserved(vmf, prot, TTM_BO_VM_NUM_PREFAULT, 1);
if (ret == VM_FAULT_RETRY && !(vmf->flags & FAULT_FLAG_RETRY_NOWAIT))
-   return ret;
+   goto out;
 
dma_resv_unlock(bo->base.resv);
 
+out:
+   trace_ttm_bo_vm_fault(bo, vmf, ret);
return ret;
 }
 EXPORT_SYMBOL(ttm_bo_vm_fault);
@@ -516,6 +520,8 @@ int ttm_bo_vm_access(struct vm_area_struct *vma, unsigned 
long addr,
if (ret)
return ret;
 
+   trace_ttm_bo_vm_access(bo, !!write, offset, len);
+
switch (bo->mem.mem_type) {
case TTM_PL_SYSTEM:
if (unlikely(bo->ttm->page_flags & TTM_PAGE_FLAG_SWAPPED)) {
@@ -618,6 +624,7 @@ int ttm_bo_mmap(struct file *filp, struct vm_area_struct 
*vma,
goto out_unref;
 
ttm_bo_mmap_vma_setup(bo, vma);
+   trace_ttm_bo_mmap(bo, vma);
return 0;
 out_unref:
ttm_bo_put(bo);
@@ -629,6 +636,7 @@ int ttm_bo_mmap_obj(struct vm_area_struct *vma, struct 
ttm_buffer_object *bo)
 {
ttm_bo_get(bo);
ttm_bo_mmap_vma_setup(bo, vma);
+   trace_ttm_bo_mmap(bo, vma);
return 0;
 }
 EXPORT_SYMBOL(ttm_bo_mmap_obj);
diff --git a/drivers/gpu/drm/ttm/ttm_trace.h b/drivers/gpu/drm/ttm/ttm_trace.h
index 7c5e55725e8e..9f7cc34b243b 100644
--- a/drivers/gpu/drm/ttm/ttm_trace.h
+++ b/drivers/gpu/drm/ttm/ttm_trace.h
@@ -34,6 +34,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #define TTM_PLACEMENT_FLAGS_TRACE \
{ TTM_PL_FLAG_SYSTEM,   "SYSTEM"},\
@@ -310,6 +311,83 @@ TRACE_EVENT(ttm_bo_release,
TP_printk("bo:%p", __entry->bo)
 );
 
+TRACE_EVENT(ttm_bo_mmap,
+   TP_PROTO(struct ttm_buffer_object *bo, struct vm_area_struct *vma),
+   TP_ARGS(bo, vma),
+   TP_STRUCT__entry(
+__field(struct ttm_buffer_object *, bo)
+__field(unsigned long, vm_start)
+__field(unsigned long, vm_end)
+__field(unsigned long, vm_pgoff)
+__field(unsigned long, vm_flags)
+),
+
+   TP_fast_assign(
+  __entry->bo = bo;
+  __entry->vm_start = vma->vm_start;
+  __entry->vm_end = vma->vm_end;
+  __entry->vm_pgoff = vma->vm_pgoff;
+  __entry->vm_flags = vma->vm_flags;
+  ),
+
+   TP_printk("bo:%p, vm_start=%lx, vm_end=%lx, vm_pgoff=%lx, 
vm_flags=%s",
+ __entry->bo,
+ __entry->vm_start, __entry->vm_end, __entry->vm_pgoff,
+ show_vma_flags(__entry->vm_flags))
+);
+
+TRACE_EVENT(ttm_bo_vm_fault,
+   TP_PROTO(struct ttm_buffer_object *bo, struct vm_fault *vmf, int 
result),
+   TP_ARGS(bo, vmf, result),
+   TP_STRUCT__entry(
+__field(struct ttm_buffer_object *, bo)
+__field(struct vm_area_struct *, vma)
+__field(unsigned long, fault_address)
+__field(unsigned long, fault_pgoff)
+__field(int, result)
+__field(unsigned int, flags)
+),
+
+   TP_fast_assign(
+  __entry->bo = bo;
+  __entry->vma = vmf->vma;
+  __entry->fault_address = vmf->address;
+  __entry->fault_pgoff = vmf->pgoff;
+  __entry->flags = vmf->flags;
+  __entry->result = result;
+  ),
+
+   TP_printk("bo:%p, vma=%p, fault_address=%lx, fault_pgoff=%lx, 
fault_flags=%s %s",
+ __entry->bo, __entry->vma,
+ __entry->fault_address, __entry->fault_pgoff,
+ __entry->flags ? __print_flags(__entry->flags, "|", 
FAULT_FLAG_TRAC

[RFC PATCH 1/3] drm/ttm: add ttm bo trace event support

[Kevin Wang]

add ttm bo related trace event support

trace events:
ttm:ttm_bo_add_mem_to_lru
ttm:ttm_bo_del_from_lru
ttm:ttm_bo_move_mem
ttm:ttm_bo_wait
ttm:ttm_bo_evict
ttm:ttm_bo_swapout
ttm:ttm_bo_device_init
ttm:ttm_bo_device_release
ttm:ttm_bo_init_reserved
ttm:ttm_bo_validate
ttm:ttm_bo_release

Signed-off-by: Kevin Wang 
---
 drivers/gpu/drm/ttm/ttm_bo.c |  23 +++
 drivers/gpu/drm/ttm/ttm_module.c |   3 +
 drivers/gpu/drm/ttm/ttm_trace.h  | 321 +++
 3 files changed, 347 insertions(+)
 create mode 100644 drivers/gpu/drm/ttm/ttm_trace.h

diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index e3931e515906..074afd05aaa8 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -43,6 +43,8 @@
 #include 
 #include 
 
+#include "ttm_trace.h"
+
 static void ttm_bo_global_kobj_release(struct kobject *kobj);
 
 /**
@@ -143,6 +145,8 @@ static void ttm_bo_add_mem_to_lru(struct ttm_buffer_object 
*bo,
if (mem->placement & TTM_PL_FLAG_NO_EVICT)
return;
 
+   trace_ttm_bo_add_mem_to_lru(bo, mem);
+
man = ttm_manager_type(bdev, mem->mem_type);
list_add_tail(&bo->lru, &man->lru[bo->priority]);
 
@@ -167,6 +171,8 @@ static void ttm_bo_del_from_lru(struct ttm_buffer_object 
*bo)
notify = true;
}
 
+   trace_ttm_bo_del_from_lru(bo, notify);
+
if (notify && bdev->driver->del_from_lru_notify)
bdev->driver->del_from_lru_notify(bo);
 }
@@ -299,6 +305,8 @@ static int ttm_bo_handle_move_mem(struct ttm_buffer_object 
*bo,
}
}
 
+   trace_ttm_bo_move_mem(bo, mem, evict);
+
if (bdev->driver->move_notify)
bdev->driver->move_notify(bo, evict, mem);
 
@@ -542,6 +550,8 @@ static void ttm_bo_release(struct kref *kref)
size_t acc_size = bo->acc_size;
int ret;
 
+   trace_ttm_bo_release(bo);
+
if (!bo->deleted) {
ret = ttm_bo_individualize_resv(bo);
if (ret) {
@@ -668,6 +678,8 @@ static int ttm_bo_evict(struct ttm_buffer_object *bo,
ttm_resource_free(bo, &evict_mem);
goto out;
}
+
+   trace_ttm_bo_evict(bo, &evict_mem);
bo->evicted = true;
 out:
return ret;
@@ -1151,6 +1163,8 @@ int ttm_bo_validate(struct ttm_buffer_object *bo,
 
dma_resv_assert_held(bo->base.resv);
 
+   trace_ttm_bo_validate(bo);
+
/*
 * Remove the backing store if no placement is given.
 */
@@ -1263,6 +1277,8 @@ int ttm_bo_init_reserved(struct ttm_bo_device *bdev,
}
atomic_inc(&ttm_bo_glob.bo_count);
 
+   trace_ttm_bo_init_reserved(bo, size);
+
/*
 * For ttm_bo_type_device buffers, allocate
 * address space from the device.
@@ -1487,6 +1503,8 @@ int ttm_bo_device_release(struct ttm_bo_device *bdev)
if (!ret)
ttm_bo_global_release();
 
+   trace_ttm_bo_device_release(bdev);
+
return ret;
 }
 EXPORT_SYMBOL(ttm_bo_device_release);
@@ -1537,6 +1555,8 @@ int ttm_bo_device_init(struct ttm_bo_device *bdev,
list_add_tail(&bdev->device_list, &glob->device_list);
mutex_unlock(&ttm_global_mutex);
 
+   trace_ttm_bo_device_init(bdev);
+
return 0;
 }
 EXPORT_SYMBOL(ttm_bo_device_init);
@@ -1580,6 +1600,8 @@ int ttm_bo_wait(struct ttm_buffer_object *bo,
 
timeout = dma_resv_wait_timeout_rcu(bo->base.resv, true,
  interruptible, timeout);
+
+   trace_ttm_bo_wait(bo, interruptible, timeout);
if (timeout < 0)
return timeout;
 
@@ -1670,6 +1692,7 @@ int ttm_bo_swapout(struct ttm_bo_global *glob, struct 
ttm_operation_ctx *ctx)
 * anyone tries to access a ttm page.
 */
 
+   trace_ttm_bo_swapout(bo, i);
if (bo->bdev->driver->swap_notify)
bo->bdev->driver->swap_notify(bo);
 
diff --git a/drivers/gpu/drm/ttm/ttm_module.c b/drivers/gpu/drm/ttm/ttm_module.c
index 6ff40c041d79..8b70e8aebecb 100644
--- a/drivers/gpu/drm/ttm/ttm_module.c
+++ b/drivers/gpu/drm/ttm/ttm_module.c
@@ -35,6 +35,9 @@
 #include 
 #include 
 
+#define CREATE_TRACE_POINTS
+#include "ttm_trace.h"
+
 static DECLARE_WAIT_QUEUE_HEAD(exit_q);
 static atomic_t device_released;
 
diff --git a/drivers/gpu/drm/ttm/ttm_trace.h b/drivers/gpu/drm/ttm/ttm_trace.h
new file mode 100644
index ..7c5e55725e8e
--- /dev/null
+++ b/drivers/gpu/drm/ttm/ttm_trace.h
@@ -0,0 +1,321 @@
+/*
+ * Copyright 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is

[RFC PATCH 0/3] add ttm trace event support

[Kevin Wang]

the kernel ftrace can better help analyze the kernel running status.
add some trace events to support TTM.

add trace events list:

ttm:ttm_bo_add_mem_to_lru
ttm:ttm_bo_del_from_lru
ttm:ttm_bo_move_mem
ttm:ttm_bo_wait
ttm:ttm_bo_evict
ttm:ttm_bo_swapout
ttm:ttm_bo_device_init
ttm:ttm_bo_device_release
ttm:ttm_bo_init_reserved
ttm:ttm_bo_validate
ttm:ttm_bo_release
ttm:ttm_bo_mmap
ttm:ttm_bo_vm_fault
ttm:ttm_bo_vm_access
ttm:ttm_shrink
ttm:ttm_mem_global_reserve
ttm:ttm_mem_global_free

Kevin Wang (3):
  drm/ttm: add ttm bo trace event support
  drm/ttm: add ttm vm bo trace event support
  drm/ttm: add ttm mem trace event support

 drivers/gpu/drm/ttm/ttm_bo.c |  23 ++
 drivers/gpu/drm/ttm/ttm_bo_vm.c  |  12 +-
 drivers/gpu/drm/ttm/ttm_memory.c |   7 +
 drivers/gpu/drm/ttm/ttm_module.c |   3 +
 drivers/gpu/drm/ttm/ttm_trace.h  | 469 +++
 5 files changed, 512 insertions(+), 2 deletions(-)
 create mode 100644 drivers/gpu/drm/ttm/ttm_trace.h

-- 
2.17.1

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[PATCH] drm/amdkfd: dqm fence memory corruption

[Qu Huang]

Amdgpu driver uses 4-byte data type as DQM fence memory,
and transmits GPU address of fence memory to microcode
through query status PM4 message. However, query status
PM4 message definition and microcode processing are all
processed according to 8 bytes. Fence memory only allocates
4 bytes of memory, but microcode does write 8 bytes of memory,
so there is a memory corruption.

Signed-off-by: Qu Huang 
---
 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index e686ce2..8b38d0c 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -1161,7 +1161,7 @@ static int start_cpsch(struct device_queue_manager *dqm)
pr_debug("Allocating fence memory\n");
 
/* allocate fence memory on the gart */
-   retval = kfd_gtt_sa_allocate(dqm->dev, sizeof(*dqm->fence_addr),
+   retval = kfd_gtt_sa_allocate(dqm->dev, sizeof(uint64_t),
&dqm->fence_mem);
 
if (retval)
-- 
1.8.3.1

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RE: [PATCH] drm/amd/pm: Enable gfx DCS feature

[Feng, Kenneth]

[AMD Official Use Only - Internal Distribution Only]

Hi Alex,
Yes, SMU acts differently with regard to DCS when we set different workloads 
via the workload interface.
The mapping is as below.
Default, power saving, video, custom -> DCS is disabled in SMU firmware 
internally though it's enabled from driver.
3D fullscreen, VR -> FA DCS
Compute -> Async DCS

-Original Message-
From: Alex Deucher  
Sent: Thursday, January 28, 2021 1:49 AM
To: Feng, Kenneth 
Cc: amd-gfx list ; Zhou1, Tao 
Subject: Re: [PATCH] drm/amd/pm: Enable gfx DCS feature

[CAUTION: External Email]

On Wed, Jan 27, 2021 at 12:57 AM Feng, Kenneth  wrote:
>
> [AMD Official Use Only - Internal Distribution Only]
>
> Hi Alex,
> Actually the FA DCS is dependent on the workload type.
> FA DCS is applied only when there's 3D fullscreen workload or VR workload.
> So we need to disable it if there's a request from the sysfs/user to set the 
> workload type to 3D fullscreen or VR type because we don't have FA DCS so far.
> By removing this hunk is ok functionally, but the DCS will never kick in 
> though the DCS is enabled. That might be a little bit confusing.
> Thanks.

For clarity, does the SMU act differently with regard to DCS when you set 
different workloads via the workload interface or is this just using the 
assumption that at some point we might dynamically adjust the workload bits 
based on hints from userspace?

Alex


>
>
>
> -Original Message-
> From: Alex Deucher 
> Sent: Wednesday, January 27, 2021 12:55 PM
> To: Feng, Kenneth 
> Cc: amd-gfx list ; Zhou1, Tao 
> 
> Subject: Re: [PATCH] drm/amd/pm: Enable gfx DCS feature
>
> [CAUTION: External Email]
>
> On Tue, Jan 26, 2021 at 8:42 PM Kenneth Feng  wrote:
> >
> > Background:
> > Gfx Duty Cycle Scaling(DCS) is applied on the small power limit skus.
> > When the current/power/temperature exceeds the limit with the heavy 
> > workload, the gfx core can be shut off and powered on back and forth.
> > The ON time and OFF time is determined by the firmware according to 
> > the accumulated power credits.
> > This feature is different from gfxoff.Gfxoff is applied in the idle 
> > case and DCS is applied in the case with heavey workload.There are two 
> > types of DCS:
> > Async DCS and Frame-aligned DCS.Frame-aligned DCS is applied on 3D 
> > fullscreen and VR workload.
> > Since we only supports Async DCS now,disalbe DCS when the 3D 
> > fullscreen or the VR workload type is chosen.
> >
> > Verification:
> > The power is lowerer or the perf/watt is increased in the throttling case.
> > To be simplified, the entry/exit counter can be observed from the firmware.
> >
> > Signed-off-by: Kenneth Feng 
> > ---
> >  .../gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c  | 12
> > 
> >  1 file changed, 12 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > index 24f3c96a5e5e..436d94cbb166 100644
> > --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > @@ -261,6 +261,9 @@ sienna_cichlid_get_allowed_feature_mask(struct 
> > smu_context *smu,
> > *(uint64_t *)feature_mask |= 
> > FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT);
> > }
> >
> > +   if (adev->asic_type == CHIP_NAVY_FLOUNDER || adev->asic_type == 
> > CHIP_DIMGREY_CAVEFISH)
> > +   *(uint64_t *)feature_mask |= 
> > + FEATURE_MASK(FEATURE_GFX_DCS_BIT);
> > +
> > if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
> > *(uint64_t *)feature_mask |= 
> > FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
> > |
> > FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
> > @@ -1437,6 +1440,15 @@ static int 
> > sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *
> > smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
> > 1 << workload_type, NULL);
> >
> > +   /* have to disable dcs if it's the 3D fullscreen or VR workload 
> > type */
> > +   if (smu->adev->asic_type == CHIP_NAVY_FLOUNDER ||
> > +   smu->adev->asic_type == CHIP_DIMGREY_CAVEFISH) {
> > +   ret = smu_cmn_feature_set_enabled(smu, 
> > SMU_FEATURE_GFX_DCS_BIT, (workload_type ==
> > +   WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT || workload_type 
> > == WORKLOAD_PPLIB_VR_BIT) ? 0 : 1);
> > +   if (ret)
> > +   return ret;
> > +   }
> > +
>
> Since we don't support FA DCS yet, should we just drop this hunk for now?  I 
> think the workload profile stuff should be independent of FA DCS.  Also so we 
> want to add a ppfeaturemask flag to easily allow us to disable this at driver 
> load time?
>
> Alex
>
>
> > return ret;
> >  }
> >
> > --
> > 2.17.1
> >
> > ___
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org

RE: [PATCH] drm/amd/amdkfd: adjust dummy functions ' placement

[Yu, Lang]

[AMD Public Use]

Thanks for Felix's review, I will update soon.

Regards,
Yu Lang

-Original Message-
From: Kuehling, Felix  
Sent: Thursday, January 28, 2021 8:22 AM
To: Yu, Lang ; amd-gfx@lists.freedesktop.org
Cc: Huang, Ray ; Deucher, Alexander 

Subject: Re: [PATCH] drm/amd/amdkfd: adjust dummy functions ' placement

Am 2021-01-27 um 5:14 a.m. schrieb Lang Yu:
> Move all the dummy functions in amdgpu_amdkfd.c to amdgpu_amdkfd.h as 
> inline functions.
>
> Signed-off-by: Lang Yu 
> Suggested-by: Felix Kuehling 

Just a some nit-picking inline, other than that the patch is

Reviewed-by: Felix Kuehling 


> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c |  87   
> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 151 ++---
>  2 files changed, 130 insertions(+), 108 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> index db96d69eb45e..c5343a5eecbe 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> @@ -47,12 +47,8 @@ int amdgpu_amdkfd_init(void)
>   amdgpu_amdkfd_total_mem_size = si.totalram - si.totalhigh;
>   amdgpu_amdkfd_total_mem_size *= si.mem_unit;
>  
> -#ifdef CONFIG_HSA_AMD
>   ret = kgd2kfd_init();
>   amdgpu_amdkfd_gpuvm_init_mem_limits();
> -#else
> - ret = -ENOENT;
> -#endif
>   kfd_initialized = !ret;
>  
>   return ret;
> @@ -696,86 +692,3 @@ bool amdgpu_amdkfd_have_atomics_support(struct 
> kgd_dev *kgd)
>  
>   return adev->have_atomics_support;
>  }
> -
> -#ifndef CONFIG_HSA_AMD
> -bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm) 
> -{
> - return false;
> -}
> -
> -void amdgpu_amdkfd_unreserve_memory_limit(struct amdgpu_bo *bo) -{ -}
> -
> -int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo) -{
> - return 0;
> -}
> -
> -void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
> - struct amdgpu_vm *vm)
> -{
> -}
> -
> -struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence 
> *f) -{
> - return NULL;
> -}
> -
> -int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, struct mm_struct 
> *mm) -{
> - return 0;
> -}
> -
> -struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, struct pci_dev *pdev,
> -   unsigned int asic_type, bool vf)
> -{
> - return NULL;
> -}
> -
> -bool kgd2kfd_device_init(struct kfd_dev *kfd,
> -  struct drm_device *ddev,
> -  const struct kgd2kfd_shared_resources *gpu_resources)
> -{
> - return false;
> -}
> -
> -void kgd2kfd_device_exit(struct kfd_dev *kfd) -{ -}
> -
> -void kgd2kfd_exit(void)
> -{
> -}
> -
> -void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm) -{ -}
> -
> -int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm) -{
> - return 0;
> -}
> -
> -int kgd2kfd_pre_reset(struct kfd_dev *kfd) -{
> - return 0;
> -}
> -
> -int kgd2kfd_post_reset(struct kfd_dev *kfd) -{
> - return 0;
> -}
> -
> -void kgd2kfd_interrupt(struct kfd_dev *kfd, const void 
> *ih_ring_entry) -{ -}
> -
> -void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd) -{ -}
> -
> -void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint32_t 
> throttle_bitmask) -{ -} -#endif diff --git 
> a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
> index bc9f0e42e0a2..c3a51c0d54e9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
> @@ -94,11 +94,6 @@ enum kgd_engine_type {
>   KGD_ENGINE_MAX
>  };
>  
> -struct amdgpu_amdkfd_fence *amdgpu_amdkfd_fence_create(u64 context,
> -struct mm_struct *mm);
> -bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct 
> *mm); -struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct 
> dma_fence *f); -int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct 
> amdgpu_bo *bo);
>  
>  struct amdkfd_process_info {
>   /* List head of all VMs that belong to a KFD process */ @@ -132,8 
> +127,6 @@ void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev,  
> void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev);  void 
> amdgpu_amdkfd_device_init(struct amdgpu_device *adev);  void 
> amdgpu_amdkfd_device_fini(struct amdgpu_device *adev);
> -
> -int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, struct mm_struct 
> *mm);  int amdgpu_amdkfd_submit_ib(struct kgd_dev *kgd, enum kgd_engine_type 
> engine,
>   uint32_t vmid, uint64_t gpu_addr,
>   uint32_t *ib_cmd, uint32_t ib_len); @@ -153,6 
> +146,38 @@ void 
> amdgpu_amdkfd_gpu_reset(struct kgd_dev *kgd);  int 
> amdgpu_queue_mask_bit_to_set_resource_bit(struct amdgpu_device *adev,
>   int queue_bit);
>  
> +struct amdgpu_amdkfd_fence *amdgpu_amdkfd_fence_create(u64 context,
> +  

RE: [PATCH] drm/amd/pm: Enable gfx DCS feature

[Quan, Evan]

[AMD Official Use Only - Internal Distribution Only]

Hi Alex,

Yes, SMU acts differently with regard to DCS when you set different workloads 
via the workload interface. So, Kenneth seems right.
But I think the dcs feature disablement needs to be placed before 
SMU_MSG_SetWorkloadMask(some code as below). Otherwise, it seems the DCS mode 
switching happens first(during SMU_MSG_SetWorkloadMask) and the disablement 
comes afterwards.

+/* have to disable dcs if it's the 3D fullscreen or VR workload type */
+if (smu->adev->asic_type == CHIP_NAVY_FLOUNDER ||
+smu->adev->asic_type == CHIP_DIMGREY_CAVEFISH) {
+ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_DCS_BIT, (workload_type 
==
+WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT || workload_type == WORKLOAD_PPLIB_VR_BIT) ? 
0 : 1);
+if (ret)
+return ret;
+}
+
smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
 1 << workload_type, NULL);

BR
Evan
-Original Message-
From: amd-gfx  On Behalf Of Alex Deucher
Sent: Thursday, January 28, 2021 1:49 AM
To: Feng, Kenneth 
Cc: Zhou1, Tao ; amd-gfx list 
Subject: Re: [PATCH] drm/amd/pm: Enable gfx DCS feature

On Wed, Jan 27, 2021 at 12:57 AM Feng, Kenneth  wrote:
>
> [AMD Official Use Only - Internal Distribution Only]
>
> Hi Alex,
> Actually the FA DCS is dependent on the workload type.
> FA DCS is applied only when there's 3D fullscreen workload or VR workload.
> So we need to disable it if there's a request from the sysfs/user to set the 
> workload type to 3D fullscreen or VR type because we don't have FA DCS so far.
> By removing this hunk is ok functionally, but the DCS will never kick in 
> though the DCS is enabled. That might be a little bit confusing.
> Thanks.

For clarity, does the SMU act differently with regard to DCS when you set 
different workloads via the workload interface or is this just using the 
assumption that at some point we might dynamically adjust the workload bits 
based on hints from userspace?

Alex


>
>
>
> -Original Message-
> From: Alex Deucher 
> Sent: Wednesday, January 27, 2021 12:55 PM
> To: Feng, Kenneth 
> Cc: amd-gfx list ; Zhou1, Tao
> 
> Subject: Re: [PATCH] drm/amd/pm: Enable gfx DCS feature
>
> [CAUTION: External Email]
>
> On Tue, Jan 26, 2021 at 8:42 PM Kenneth Feng  wrote:
> >
> > Background:
> > Gfx Duty Cycle Scaling(DCS) is applied on the small power limit skus.
> > When the current/power/temperature exceeds the limit with the heavy
> > workload, the gfx core can be shut off and powered on back and forth.
> > The ON time and OFF time is determined by the firmware according to
> > the accumulated power credits.
> > This feature is different from gfxoff.Gfxoff is applied in the idle
> > case and DCS is applied in the case with heavey workload.There are two 
> > types of DCS:
> > Async DCS and Frame-aligned DCS.Frame-aligned DCS is applied on 3D
> > fullscreen and VR workload.
> > Since we only supports Async DCS now,disalbe DCS when the 3D
> > fullscreen or the VR workload type is chosen.
> >
> > Verification:
> > The power is lowerer or the perf/watt is increased in the throttling case.
> > To be simplified, the entry/exit counter can be observed from the firmware.
> >
> > Signed-off-by: Kenneth Feng 
> > ---
> >  .../gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c  | 12
> > 
> >  1 file changed, 12 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > index 24f3c96a5e5e..436d94cbb166 100644
> > --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > @@ -261,6 +261,9 @@ sienna_cichlid_get_allowed_feature_mask(struct 
> > smu_context *smu,
> > *(uint64_t *)feature_mask |= 
> > FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT);
> > }
> >
> > +   if (adev->asic_type == CHIP_NAVY_FLOUNDER || adev->asic_type == 
> > CHIP_DIMGREY_CAVEFISH)
> > +   *(uint64_t *)feature_mask |=
> > + FEATURE_MASK(FEATURE_GFX_DCS_BIT);
> > +
> > if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
> > *(uint64_t *)feature_mask |= 
> > FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
> > |
> > FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
> > @@ -1437,6 +1440,15 @@ static int 
> > sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *
> > smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
> > 1 << workload_type, NULL);
> >
> > +   /* have to disable dcs if it's the 3D fullscreen or VR workload 
> > type */
> > +   if (smu->adev->asic_type == CHIP_NAVY_FLOUNDER ||
> > +   smu->adev->asic_type == CHIP_DIMGREY_CAVEFISH) {
> > +   ret = smu_cmn_feature_set_enabled(smu, 
> > SMU_FEATURE_GFX_DCS_BIT, (workload_type ==
> > +   WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT || workload_type 
> > == WORKLOAD_PPLIB_VR_B

Re: [PATCH] drm/amd/amdkfd: adjust dummy functions ' placement

[Felix Kuehling]

Am 2021-01-27 um 5:14 a.m. schrieb Lang Yu:
> Move all the dummy functions in amdgpu_amdkfd.c to
> amdgpu_amdkfd.h as inline functions.
>
> Signed-off-by: Lang Yu 
> Suggested-by: Felix Kuehling 

Just a some nit-picking inline, other than that the patch is

Reviewed-by: Felix Kuehling 


> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c |  87 
>  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 151 ++---
>  2 files changed, 130 insertions(+), 108 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> index db96d69eb45e..c5343a5eecbe 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> @@ -47,12 +47,8 @@ int amdgpu_amdkfd_init(void)
>   amdgpu_amdkfd_total_mem_size = si.totalram - si.totalhigh;
>   amdgpu_amdkfd_total_mem_size *= si.mem_unit;
>  
> -#ifdef CONFIG_HSA_AMD
>   ret = kgd2kfd_init();
>   amdgpu_amdkfd_gpuvm_init_mem_limits();
> -#else
> - ret = -ENOENT;
> -#endif
>   kfd_initialized = !ret;
>  
>   return ret;
> @@ -696,86 +692,3 @@ bool amdgpu_amdkfd_have_atomics_support(struct kgd_dev 
> *kgd)
>  
>   return adev->have_atomics_support;
>  }
> -
> -#ifndef CONFIG_HSA_AMD
> -bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm)
> -{
> - return false;
> -}
> -
> -void amdgpu_amdkfd_unreserve_memory_limit(struct amdgpu_bo *bo)
> -{
> -}
> -
> -int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo)
> -{
> - return 0;
> -}
> -
> -void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
> - struct amdgpu_vm *vm)
> -{
> -}
> -
> -struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f)
> -{
> - return NULL;
> -}
> -
> -int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, struct mm_struct *mm)
> -{
> - return 0;
> -}
> -
> -struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, struct pci_dev *pdev,
> -   unsigned int asic_type, bool vf)
> -{
> - return NULL;
> -}
> -
> -bool kgd2kfd_device_init(struct kfd_dev *kfd,
> -  struct drm_device *ddev,
> -  const struct kgd2kfd_shared_resources *gpu_resources)
> -{
> - return false;
> -}
> -
> -void kgd2kfd_device_exit(struct kfd_dev *kfd)
> -{
> -}
> -
> -void kgd2kfd_exit(void)
> -{
> -}
> -
> -void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm)
> -{
> -}
> -
> -int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm)
> -{
> - return 0;
> -}
> -
> -int kgd2kfd_pre_reset(struct kfd_dev *kfd)
> -{
> - return 0;
> -}
> -
> -int kgd2kfd_post_reset(struct kfd_dev *kfd)
> -{
> - return 0;
> -}
> -
> -void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry)
> -{
> -}
> -
> -void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd)
> -{
> -}
> -
> -void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint32_t 
> throttle_bitmask)
> -{
> -}
> -#endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
> index bc9f0e42e0a2..c3a51c0d54e9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
> @@ -94,11 +94,6 @@ enum kgd_engine_type {
>   KGD_ENGINE_MAX
>  };
>  
> -struct amdgpu_amdkfd_fence *amdgpu_amdkfd_fence_create(u64 context,
> -struct mm_struct *mm);
> -bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm);
> -struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f);
> -int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo);
>  
>  struct amdkfd_process_info {
>   /* List head of all VMs that belong to a KFD process */
> @@ -132,8 +127,6 @@ void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev,
>  void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev);
>  void amdgpu_amdkfd_device_init(struct amdgpu_device *adev);
>  void amdgpu_amdkfd_device_fini(struct amdgpu_device *adev);
> -
> -int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, struct mm_struct *mm);
>  int amdgpu_amdkfd_submit_ib(struct kgd_dev *kgd, enum kgd_engine_type engine,
>   uint32_t vmid, uint64_t gpu_addr,
>   uint32_t *ib_cmd, uint32_t ib_len);
> @@ -153,6 +146,38 @@ void amdgpu_amdkfd_gpu_reset(struct kgd_dev *kgd);
>  int amdgpu_queue_mask_bit_to_set_resource_bit(struct amdgpu_device *adev,
>   int queue_bit);
>  
> +struct amdgpu_amdkfd_fence *amdgpu_amdkfd_fence_create(u64 context,
> +struct mm_struct *mm);
> +#if IS_ENABLED(CONFIG_HSA_AMD)
> +bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm);
> +struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f);
> +int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo);
> +int amd

[PATCH] drm/amdgpu/swsmu: use percent rather than rpm for manual fan control

[Alex Deucher]

On some boards the rpm interface apparently does not work at all
leading to the fan not spinning or spinning at strange speeds.
Both interfaces work properly on the boards I have.
Let's try and use the percent interface instead.

Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1408
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h   | 12 +--
 drivers/gpu/drm/amd/pm/inc/smu_v11_0.h|  7 +-
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 35 
 .../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 26 --
 .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c   | 26 --
 .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c   | 26 --
 .../gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c| 89 +++
 7 files changed, 117 insertions(+), 104 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h 
b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
index 631a36a75ae3..44279c2afccb 100644
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
@@ -173,7 +173,7 @@ enum smu_memory_pool_size
 struct smu_user_dpm_profile {
uint32_t fan_mode;
uint32_t power_limit;
-   uint32_t fan_speed_rpm;
+   uint32_t fan_speed_percent;
uint32_t flags;
 
/* user clock state information */
@@ -472,7 +472,7 @@ struct smu_context
struct work_struct interrupt_work;
 
unsigned fan_max_rpm;
-   unsigned manual_fan_speed_rpm;
+   unsigned manual_fan_speed_percent;
 
uint32_t gfx_default_hard_min_freq;
uint32_t gfx_default_soft_max_freq;
@@ -648,9 +648,9 @@ struct pptable_funcs {
bool (*is_dpm_running)(struct smu_context *smu);
 
/**
-* @get_fan_speed_rpm: Get the current fan speed in RPM.
+* @get_fan_speed_percent: Get the current fan speed in percent.
 */
-   int (*get_fan_speed_rpm)(struct smu_context *smu, uint32_t *speed);
+   int (*get_fan_speed_percent)(struct smu_context *smu, uint32_t *speed);
 
/**
 * @set_watermarks_table: Configure and upload the watermarks tables to
@@ -951,9 +951,9 @@ struct pptable_funcs {
int (*set_fan_control_mode)(struct smu_context *smu, uint32_t mode);
 
/**
-* @set_fan_speed_rpm: Set a static fan speed in RPM.
+* @set_fan_speed_percent: Set a static fan speed in percent.
 */
-   int (*set_fan_speed_rpm)(struct smu_context *smu, uint32_t speed);
+   int (*set_fan_speed_percent)(struct smu_context *smu, uint32_t speed);
 
/**
 * @set_xgmi_pstate: Set inter-chip global memory interconnect pstate.
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h 
b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
index 102a0cf12d7a..c7d57e9555cc 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
@@ -203,11 +203,8 @@ int
 smu_v11_0_set_fan_control_mode(struct smu_context *smu,
   uint32_t mode);
 
-int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
-  uint32_t speed);
-
-int smu_v11_0_get_fan_speed_rpm(struct smu_context *smu,
-   uint32_t *speed);
+int smu_v11_0_set_fan_speed_percent(struct smu_context *smu,
+   uint32_t speed);
 
 int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
 uint32_t pstate);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c 
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index f958b02f9317..1c7ac81fe417 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -368,8 +368,8 @@ static void smu_restore_dpm_user_profile(struct smu_context 
*smu)
return;
}
 
-   if (!ret && smu->user_dpm_profile.fan_speed_rpm) {
-   ret = smu_set_fan_speed_rpm(smu, 
smu->user_dpm_profile.fan_speed_rpm);
+   if (!ret && smu->user_dpm_profile.fan_speed_percent) {
+   ret = smu_set_fan_speed_percent(smu, 
smu->user_dpm_profile.fan_speed_percent);
if (ret)
dev_err(smu->adev->dev, "Failed to set manual 
fan speed\n");
}
@@ -2025,6 +2025,7 @@ int smu_set_gfx_cgpg(struct smu_context *smu, bool 
enabled)
 
 int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed)
 {
+   u32 percent;
int ret = 0;
 
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
@@ -2032,10 +2033,11 @@ int smu_set_fan_speed_rpm(struct smu_context *smu, 
uint32_t speed)
 
mutex_lock(&smu->mutex);
 
-   if (smu->ppt_funcs->set_fan_speed_rpm) {
-   ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed);
+   if (smu->ppt_funcs->set_fan_speed_percent) {
+   percent = speed * 100 / smu->fan_max_rpm;
+   ret = smu->ppt_funcs->set_fan_speed_percent(smu, percent);
if (

Re: [PATCH] drm/amdkfd: dqm fence memory corruption

[Felix Kuehling]

Am 2021-01-27 um 7:33 a.m. schrieb Qu Huang:
> Amdgpu driver uses 4-byte data type as DQM fence memory,
> and transmits GPU address of fence memory to microcode
> through query status PM4 message. However, query status
> PM4 message definition and microcode processing are all
> processed according to 8 bytes. Fence memory only allocates
> 4 bytes of memory, but microcode does write 8 bytes of memory,
> so there is a memory corruption.

Thank you for pointing out that discrepancy. That's a good catch!

I'd prefer to fix this properly by making dqm->fence_addr a u64 pointer.
We should probably also fix up the query_status and
amdkfd_fence_wait_timeout function interfaces to use a 64 bit fence
values everywhere to be consistent.

Regards,
  Felix


>
> Signed-off-by: Qu Huang 
> ---
>  drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c 
> b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> index e686ce2..8b38d0c 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> @@ -1161,7 +1161,7 @@ static int start_cpsch(struct device_queue_manager *dqm)
>   pr_debug("Allocating fence memory\n");
>  
>   /* allocate fence memory on the gart */
> - retval = kfd_gtt_sa_allocate(dqm->dev, sizeof(*dqm->fence_addr),
> + retval = kfd_gtt_sa_allocate(dqm->dev, sizeof(uint64_t),
>   &dqm->fence_mem);
>  
>   if (retval)
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Re: [PATCH] drm/amd/pm: Enable gfx DCS feature

[Alex Deucher]

On Wed, Jan 27, 2021 at 12:57 AM Feng, Kenneth  wrote:
>
> [AMD Official Use Only - Internal Distribution Only]
>
> Hi Alex,
> Actually the FA DCS is dependent on the workload type.
> FA DCS is applied only when there's 3D fullscreen workload or VR workload.
> So we need to disable it if there's a request from the sysfs/user to set the 
> workload type to 3D fullscreen or VR type because we don't have FA DCS so far.
> By removing this hunk is ok functionally, but the DCS will never kick in 
> though the DCS is enabled. That might be a little bit confusing.
> Thanks.

For clarity, does the SMU act differently with regard to DCS when you
set different workloads via the workload interface or is this just
using the assumption that at some point we might dynamically adjust
the workload bits based on hints from userspace?

Alex


>
>
>
> -Original Message-
> From: Alex Deucher 
> Sent: Wednesday, January 27, 2021 12:55 PM
> To: Feng, Kenneth 
> Cc: amd-gfx list ; Zhou1, Tao 
> 
> Subject: Re: [PATCH] drm/amd/pm: Enable gfx DCS feature
>
> [CAUTION: External Email]
>
> On Tue, Jan 26, 2021 at 8:42 PM Kenneth Feng  wrote:
> >
> > Background:
> > Gfx Duty Cycle Scaling(DCS) is applied on the small power limit skus.
> > When the current/power/temperature exceeds the limit with the heavy
> > workload, the gfx core can be shut off and powered on back and forth.
> > The ON time and OFF time is determined by the firmware according to
> > the accumulated power credits.
> > This feature is different from gfxoff.Gfxoff is applied in the idle
> > case and DCS is applied in the case with heavey workload.There are two 
> > types of DCS:
> > Async DCS and Frame-aligned DCS.Frame-aligned DCS is applied on 3D
> > fullscreen and VR workload.
> > Since we only supports Async DCS now,disalbe DCS when the 3D
> > fullscreen or the VR workload type is chosen.
> >
> > Verification:
> > The power is lowerer or the perf/watt is increased in the throttling case.
> > To be simplified, the entry/exit counter can be observed from the firmware.
> >
> > Signed-off-by: Kenneth Feng 
> > ---
> >  .../gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c  | 12
> > 
> >  1 file changed, 12 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > index 24f3c96a5e5e..436d94cbb166 100644
> > --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > @@ -261,6 +261,9 @@ sienna_cichlid_get_allowed_feature_mask(struct 
> > smu_context *smu,
> > *(uint64_t *)feature_mask |= 
> > FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT);
> > }
> >
> > +   if (adev->asic_type == CHIP_NAVY_FLOUNDER || adev->asic_type == 
> > CHIP_DIMGREY_CAVEFISH)
> > +   *(uint64_t *)feature_mask |=
> > + FEATURE_MASK(FEATURE_GFX_DCS_BIT);
> > +
> > if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
> > *(uint64_t *)feature_mask |= 
> > FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
> > |
> > FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
> > @@ -1437,6 +1440,15 @@ static int 
> > sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *
> > smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
> > 1 << workload_type, NULL);
> >
> > +   /* have to disable dcs if it's the 3D fullscreen or VR workload 
> > type */
> > +   if (smu->adev->asic_type == CHIP_NAVY_FLOUNDER ||
> > +   smu->adev->asic_type == CHIP_DIMGREY_CAVEFISH) {
> > +   ret = smu_cmn_feature_set_enabled(smu, 
> > SMU_FEATURE_GFX_DCS_BIT, (workload_type ==
> > +   WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT || workload_type 
> > == WORKLOAD_PPLIB_VR_BIT) ? 0 : 1);
> > +   if (ret)
> > +   return ret;
> > +   }
> > +
>
> Since we don't support FA DCS yet, should we just drop this hunk for now?  I 
> think the workload profile stuff should be independent of FA DCS.  Also so we 
> want to add a ppfeaturemask flag to easily allow us to disable this at driver 
> load time?
>
> Alex
>
>
> > return ret;
> >  }
> >
> > --
> > 2.17.1
> >
> > ___
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org
> > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flist
> > s.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=04%7C01%7Cke
> > nneth.feng%40amd.com%7C2f961319cdd141723c1808d8c27fb554%7C3dd8961fe488
> > 4e608e11a82d994e183d%7C0%7C0%7C637473201048667755%7CUnknown%7CTWFpbGZs
> > b3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D
> > %7C1000&sdata=2%2BC7%2FgINP5n9k2M6lXChHQj3scXU279dp6pR2SdRiq4%3D&a
> > mp;reserved=0
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Re: [PATCH] ACPI: Test for ACPI_SUCCESS rather than !ACPI_FAILURE

[Rafael J. Wysocki]

On Wed, Jan 27, 2021 at 5:06 PM Bjorn Helgaas  wrote:
>
> On Wed, Jan 27, 2021 at 04:44:02PM +0100, Rafael J. Wysocki wrote:
> > On Wed, Jan 27, 2021 at 4:16 PM Bjorn Helgaas  wrote:
> > >
> > > On Tue, Jan 26, 2021 at 02:23:17PM -0600, Bjorn Helgaas wrote:
> > > > From: Bjorn Helgaas 
> > > >
> > > > The double negative makes it hard to read "if (!ACPI_FAILURE(status))".
> > > > Replace it with "if (ACPI_SUCCESS(status))".
> > > >
> > > > Signed-off-by: Bjorn Helgaas 
> > > > ---
> > > >
> > > > This isn't really an ACPI patch, but I'm sending it to you, Rafael, 
> > > > since
> > > > it seems easier to just apply these all at once.  But I'd be happy to 
> > > > split
> > > > them up into individual patches if you'd rather.
> > >
> > > Thanks, everybody.  Rafael, I'll just merge this via my tree to avoid
> > > burdening you.
> >
> > It may conflict with some janitorial stuff I'm doing, though, so
> > unless you've already applied it, I'd prefer to take it via the ACPI
> > tree.
>
> No problem, it's all yours!

Applied as 5.12 material with the ACKs, thanks!
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Re: [PATCH] ACPI: Test for ACPI_SUCCESS rather than !ACPI_FAILURE

[Bjorn Helgaas]

On Wed, Jan 27, 2021 at 04:44:02PM +0100, Rafael J. Wysocki wrote:
> On Wed, Jan 27, 2021 at 4:16 PM Bjorn Helgaas  wrote:
> >
> > On Tue, Jan 26, 2021 at 02:23:17PM -0600, Bjorn Helgaas wrote:
> > > From: Bjorn Helgaas 
> > >
> > > The double negative makes it hard to read "if (!ACPI_FAILURE(status))".
> > > Replace it with "if (ACPI_SUCCESS(status))".
> > >
> > > Signed-off-by: Bjorn Helgaas 
> > > ---
> > >
> > > This isn't really an ACPI patch, but I'm sending it to you, Rafael, since
> > > it seems easier to just apply these all at once.  But I'd be happy to 
> > > split
> > > them up into individual patches if you'd rather.
> >
> > Thanks, everybody.  Rafael, I'll just merge this via my tree to avoid
> > burdening you.
> 
> It may conflict with some janitorial stuff I'm doing, though, so
> unless you've already applied it, I'd prefer to take it via the ACPI
> tree.

No problem, it's all yours!

Bjorn
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Re: [PATCH] ACPI: Test for ACPI_SUCCESS rather than !ACPI_FAILURE

[Rafael J. Wysocki]

On Wed, Jan 27, 2021 at 4:16 PM Bjorn Helgaas  wrote:
>
> On Tue, Jan 26, 2021 at 02:23:17PM -0600, Bjorn Helgaas wrote:
> > From: Bjorn Helgaas 
> >
> > The double negative makes it hard to read "if (!ACPI_FAILURE(status))".
> > Replace it with "if (ACPI_SUCCESS(status))".
> >
> > Signed-off-by: Bjorn Helgaas 
> > ---
> >
> > This isn't really an ACPI patch, but I'm sending it to you, Rafael, since
> > it seems easier to just apply these all at once.  But I'd be happy to split
> > them up into individual patches if you'd rather.
>
> Thanks, everybody.  Rafael, I'll just merge this via my tree to avoid
> burdening you.

It may conflict with some janitorial stuff I'm doing, though, so
unless you've already applied it, I'd prefer to take it via the ACPI
tree.

Cheers!
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RE: [PATCH 4/4] drm/amdgpu: bump driver version for new video codec INFO ioctl query

[Liu, Leo]

[AMD Official Use Only - Internal Distribution Only]

The series are:
Reviewed-by: Leo Liu 

-Original Message-
From: amd-gfx  On Behalf Of Alex Deucher
Sent: January 27, 2021 12:33 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander 
Subject: [PATCH 4/4] drm/amdgpu: bump driver version for new video codec INFO 
ioctl query

So mesa can check when to query the kernel vs use hardcoded codec bandwidth 
data.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index effa9062f541..021c2386778e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -90,9 +90,10 @@
  * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC
  * - 3.39.0 - DMABUF implicit sync does a full pipeline sync
  * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ
+ * - 3.41.0 - Add video codec query
  */
 #define KMS_DRIVER_MAJOR3
-#define KMS_DRIVER_MINOR40
+#define KMS_DRIVER_MINOR41
 #define KMS_DRIVER_PATCHLEVEL0

 int amdgpu_vram_limit;
--
2.29.2

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Re: [PATCH] ACPI: Test for ACPI_SUCCESS rather than !ACPI_FAILURE

[Bjorn Helgaas]

On Tue, Jan 26, 2021 at 02:23:17PM -0600, Bjorn Helgaas wrote:
> From: Bjorn Helgaas 
> 
> The double negative makes it hard to read "if (!ACPI_FAILURE(status))".
> Replace it with "if (ACPI_SUCCESS(status))".
> 
> Signed-off-by: Bjorn Helgaas 
> ---
> 
> This isn't really an ACPI patch, but I'm sending it to you, Rafael, since
> it seems easier to just apply these all at once.  But I'd be happy to split
> them up into individual patches if you'd rather.

Thanks, everybody.  Rafael, I'll just merge this via my tree to avoid
burdening you.

>  drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c | 4 ++--
>  drivers/gpu/drm/radeon/radeon_bios.c | 4 ++--
>  drivers/hwmon/acpi_power_meter.c | 4 ++--
>  drivers/platform/x86/asus-laptop.c   | 6 +++---
>  drivers/spi/spi.c| 2 +-
>  sound/pci/hda/hda_intel.c| 4 ++--
>  6 files changed, 12 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
> index 6333cada1e09..055f600eeed8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
> @@ -291,7 +291,7 @@ static bool amdgpu_atrm_get_bios(struct amdgpu_device 
> *adev)
>   continue;
>  
>   status = acpi_get_handle(dhandle, "ATRM", &atrm_handle);
> - if (!ACPI_FAILURE(status)) {
> + if (ACPI_SUCCESS(status)) {
>   found = true;
>   break;
>   }
> @@ -304,7 +304,7 @@ static bool amdgpu_atrm_get_bios(struct amdgpu_device 
> *adev)
>   continue;
>  
>   status = acpi_get_handle(dhandle, "ATRM", &atrm_handle);
> - if (!ACPI_FAILURE(status)) {
> + if (ACPI_SUCCESS(status)) {
>   found = true;
>   break;
>   }
> diff --git a/drivers/gpu/drm/radeon/radeon_bios.c 
> b/drivers/gpu/drm/radeon/radeon_bios.c
> index bb29cf02974d..43bbbfd6ade8 100644
> --- a/drivers/gpu/drm/radeon/radeon_bios.c
> +++ b/drivers/gpu/drm/radeon/radeon_bios.c
> @@ -205,7 +205,7 @@ static bool radeon_atrm_get_bios(struct radeon_device 
> *rdev)
>   continue;
>  
>   status = acpi_get_handle(dhandle, "ATRM", &atrm_handle);
> - if (!ACPI_FAILURE(status)) {
> + if (ACPI_SUCCESS(status)) {
>   found = true;
>   break;
>   }
> @@ -218,7 +218,7 @@ static bool radeon_atrm_get_bios(struct radeon_device 
> *rdev)
>   continue;
>  
>   status = acpi_get_handle(dhandle, "ATRM", &atrm_handle);
> - if (!ACPI_FAILURE(status)) {
> + if (ACPI_SUCCESS(status)) {
>   found = true;
>   break;
>   }
> diff --git a/drivers/hwmon/acpi_power_meter.c 
> b/drivers/hwmon/acpi_power_meter.c
> index 848718ab7312..7d3ddcba34ce 100644
> --- a/drivers/hwmon/acpi_power_meter.c
> +++ b/drivers/hwmon/acpi_power_meter.c
> @@ -161,7 +161,7 @@ static ssize_t set_avg_interval(struct device *dev,
>   mutex_lock(&resource->lock);
>   status = acpi_evaluate_integer(resource->acpi_dev->handle, "_PAI",
>  &args, &data);
> - if (!ACPI_FAILURE(status))
> + if (ACPI_SUCCESS(status))
>   resource->avg_interval = temp;
>   mutex_unlock(&resource->lock);
>  
> @@ -232,7 +232,7 @@ static ssize_t set_cap(struct device *dev, struct 
> device_attribute *devattr,
>   mutex_lock(&resource->lock);
>   status = acpi_evaluate_integer(resource->acpi_dev->handle, "_SHL",
>  &args, &data);
> - if (!ACPI_FAILURE(status))
> + if (ACPI_SUCCESS(status))
>   resource->cap = temp;
>   mutex_unlock(&resource->lock);
>  
> diff --git a/drivers/platform/x86/asus-laptop.c 
> b/drivers/platform/x86/asus-laptop.c
> index 0edafe687fa9..bfea656e910c 100644
> --- a/drivers/platform/x86/asus-laptop.c
> +++ b/drivers/platform/x86/asus-laptop.c
> @@ -861,7 +861,7 @@ static ssize_t infos_show(struct device *dev, struct 
> device_attribute *attr,
>* The significance of others is yet to be found.
>*/
>   rv = acpi_evaluate_integer(asus->handle, "SFUN", NULL, &temp);
> - if (!ACPI_FAILURE(rv))
> + if (ACPI_SUCCESS(rv))
>   len += sprintf(page + len, "SFUN value : %#x\n",
>  (uint) temp);
>   /*
> @@ -873,7 +873,7 @@ static ssize_t infos_show(struct device *dev, struct 
> device_attribute *attr,
>* takes several seconds to run on some systems.
>*/
>   rv = acpi_evaluate_integer(asus->handle, "HWRS", NULL, &temp);
> - if (!ACPI_FAILURE(rv))
> + if (ACPI_SUCCESS(rv))
>   len += sp

Re: [RFC PATCH 1/2] drm/amdgpu: add wave limit functionality for gfx8,9

[Christian König]

Am 27.01.21 um 15:56 schrieb Nirmoy Das:

Wave limiting can be use to load balance high priority
compute jobs along with gfx jobs. When enabled, this will reserve
70% of waves for compute jobs


Can this be changed on the fly? I was always assuming this must be 
something static.


Christian.



Signed-off-by: Nirmoy Das 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h |  1 +
  drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c| 16 
  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c| 18 ++
  3 files changed, 35 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 7112137689db..220eec886f23 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -197,6 +197,7 @@ struct amdgpu_ring_funcs {
void (*soft_recovery)(struct amdgpu_ring *ring, unsigned vmid);
int (*preempt_ib)(struct amdgpu_ring *ring);
void (*emit_mem_sync)(struct amdgpu_ring *ring);
+   void (*emit_wave_limit)(struct amdgpu_ring *ring, bool enable);
  };

  struct amdgpu_ring {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 37639214cbbb..ead2cae3927b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -6847,6 +6847,21 @@ static void gfx_v8_0_emit_mem_sync_compute(struct 
amdgpu_ring *ring)
amdgpu_ring_write(ring, 0x000A);/* poll interval */
  }

+#define mmSPI_WCL_PIPE_PERCENT_GFX_DEFAULT 0x07ff
+static void gfx_v8_0_emit_wave_limit(struct amdgpu_ring *ring, bool enable)
+{
+   struct amdgpu_device *adev = ring->adev;
+   uint32_t val;
+
+
+   /* mmSPI_WCL_PIPE_PERCENT_GFX is a 7 bit multiplier register to limit
+* number of gfx waves. Setting 5 bit will make sure gfx only gets
+* maximum 25% of gpu resources.
+*/
+   val = enable ? 0x1f : mmSPI_WCL_PIPE_PERCENT_GFX_DEFAULT;
+   gfx_v8_0_ring_emit_wreg(ring, mmSPI_WCL_PIPE_PERCENT_GFX, val);
+}
+
  static const struct amd_ip_funcs gfx_v8_0_ip_funcs = {
.name = "gfx_v8_0",
.early_init = gfx_v8_0_early_init,
@@ -6944,6 +6959,7 @@ static const struct amdgpu_ring_funcs 
gfx_v8_0_ring_funcs_compute = {
.pad_ib = amdgpu_ring_generic_pad_ib,
.emit_wreg = gfx_v8_0_ring_emit_wreg,
.emit_mem_sync = gfx_v8_0_emit_mem_sync_compute,
+   .emit_wave_limit = gfx_v8_0_emit_wave_limit,
  };

  static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_kiq = {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index a896e3d0fcf8..e94737d82915 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -52,6 +52,7 @@

  #include "asic_reg/pwr/pwr_10_0_offset.h"
  #include "asic_reg/pwr/pwr_10_0_sh_mask.h"
+#include "asic_reg/gc/gc_9_0_default.h"

  #define GFX9_NUM_GFX_RINGS 1
  #define GFX9_MEC_HPD_SIZE 4096
@@ -6670,6 +6671,22 @@ static void gfx_v9_0_emit_mem_sync(struct amdgpu_ring 
*ring)
amdgpu_ring_write(ring, 0x000A); /* POLL_INTERVAL */
  }

+static void gfx_v9_0_emit_wave_limit(struct amdgpu_ring *ring, bool enable)
+{
+   struct amdgpu_device *adev = ring->adev;
+   uint32_t val;
+
+
+   /* mmSPI_WCL_PIPE_PERCENT_GFX is a 7 bit multiplier register to limit
+* number of gfx waves. Setting 5 bit will make sure gfx only gets
+* maximum 25% of gpu resources.
+*/
+   val = enable ? 0x1f : mmSPI_WCL_PIPE_PERCENT_GFX_DEFAULT;
+   amdgpu_ring_emit_wreg(ring,
+ SOC15_REG_OFFSET(GC, 0, 
mmSPI_WCL_PIPE_PERCENT_GFX),
+ val);
+}
+
  static const struct amd_ip_funcs gfx_v9_0_ip_funcs = {
.name = "gfx_v9_0",
.early_init = gfx_v9_0_early_init,
@@ -6775,6 +6792,7 @@ static const struct amdgpu_ring_funcs 
gfx_v9_0_ring_funcs_compute = {
.emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
.emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
.emit_mem_sync = gfx_v9_0_emit_mem_sync,
+   .emit_wave_limit = gfx_v9_0_emit_wave_limit,
  };

  static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
--
2.30.0



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[RFC PATCH 2/2] drm/amdgpu: enable gfx wave limiting for high priority compute jobs

[Nirmoy Das]

Enable gfx wave limiting for gfx jobs before pushing high priority
compute jobs so that high priority compute jobs more resources
to finish early.

Signed-off-by: Nirmoy Das 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index 024d0a563a65..ee48989dfb4c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -195,6 +195,10 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned 
num_ibs,
if ((ib->flags & AMDGPU_IB_FLAG_EMIT_MEM_SYNC) && 
ring->funcs->emit_mem_sync)
ring->funcs->emit_mem_sync(ring);
 
+   if (ring->funcs->emit_wave_limit && job &&
+   job->base.s_priority >= DRM_SCHED_PRIORITY_HIGH)
+   ring->funcs->emit_wave_limit(ring, true);
+
if (ring->funcs->insert_start)
ring->funcs->insert_start(ring);
 
@@ -295,6 +299,11 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned 
num_ibs,
ring->current_ctx = fence_ctx;
if (vm && ring->funcs->emit_switch_buffer)
amdgpu_ring_emit_switch_buffer(ring);
+
+   if (ring->funcs->emit_wave_limit && job &&
+   job->base.s_priority >= DRM_SCHED_PRIORITY_HIGH)
+   ring->funcs->emit_wave_limit(ring, false);
+
amdgpu_ring_commit(ring);
return 0;
 }
-- 
2.30.0

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[RFC PATCH 1/2] drm/amdgpu: add wave limit functionality for gfx8,9

[Nirmoy Das]

Wave limiting can be use to load balance high priority
compute jobs along with gfx jobs. When enabled, this will reserve
70% of waves for compute jobs

Signed-off-by: Nirmoy Das 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h |  1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c| 16 
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c| 18 ++
 3 files changed, 35 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 7112137689db..220eec886f23 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -197,6 +197,7 @@ struct amdgpu_ring_funcs {
void (*soft_recovery)(struct amdgpu_ring *ring, unsigned vmid);
int (*preempt_ib)(struct amdgpu_ring *ring);
void (*emit_mem_sync)(struct amdgpu_ring *ring);
+   void (*emit_wave_limit)(struct amdgpu_ring *ring, bool enable);
 };

 struct amdgpu_ring {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 37639214cbbb..ead2cae3927b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -6847,6 +6847,21 @@ static void gfx_v8_0_emit_mem_sync_compute(struct 
amdgpu_ring *ring)
amdgpu_ring_write(ring, 0x000A);/* poll interval */
 }

+#define mmSPI_WCL_PIPE_PERCENT_GFX_DEFAULT 0x07ff
+static void gfx_v8_0_emit_wave_limit(struct amdgpu_ring *ring, bool enable)
+{
+   struct amdgpu_device *adev = ring->adev;
+   uint32_t val;
+
+
+   /* mmSPI_WCL_PIPE_PERCENT_GFX is a 7 bit multiplier register to limit
+* number of gfx waves. Setting 5 bit will make sure gfx only gets
+* maximum 25% of gpu resources.
+*/
+   val = enable ? 0x1f : mmSPI_WCL_PIPE_PERCENT_GFX_DEFAULT;
+   gfx_v8_0_ring_emit_wreg(ring, mmSPI_WCL_PIPE_PERCENT_GFX, val);
+}
+
 static const struct amd_ip_funcs gfx_v8_0_ip_funcs = {
.name = "gfx_v8_0",
.early_init = gfx_v8_0_early_init,
@@ -6944,6 +6959,7 @@ static const struct amdgpu_ring_funcs 
gfx_v8_0_ring_funcs_compute = {
.pad_ib = amdgpu_ring_generic_pad_ib,
.emit_wreg = gfx_v8_0_ring_emit_wreg,
.emit_mem_sync = gfx_v8_0_emit_mem_sync_compute,
+   .emit_wave_limit = gfx_v8_0_emit_wave_limit,
 };

 static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_kiq = {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index a896e3d0fcf8..e94737d82915 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -52,6 +52,7 @@

 #include "asic_reg/pwr/pwr_10_0_offset.h"
 #include "asic_reg/pwr/pwr_10_0_sh_mask.h"
+#include "asic_reg/gc/gc_9_0_default.h"

 #define GFX9_NUM_GFX_RINGS 1
 #define GFX9_MEC_HPD_SIZE 4096
@@ -6670,6 +6671,22 @@ static void gfx_v9_0_emit_mem_sync(struct amdgpu_ring 
*ring)
amdgpu_ring_write(ring, 0x000A); /* POLL_INTERVAL */
 }

+static void gfx_v9_0_emit_wave_limit(struct amdgpu_ring *ring, bool enable)
+{
+   struct amdgpu_device *adev = ring->adev;
+   uint32_t val;
+
+
+   /* mmSPI_WCL_PIPE_PERCENT_GFX is a 7 bit multiplier register to limit
+* number of gfx waves. Setting 5 bit will make sure gfx only gets
+* maximum 25% of gpu resources.
+*/
+   val = enable ? 0x1f : mmSPI_WCL_PIPE_PERCENT_GFX_DEFAULT;
+   amdgpu_ring_emit_wreg(ring,
+ SOC15_REG_OFFSET(GC, 0, 
mmSPI_WCL_PIPE_PERCENT_GFX),
+ val);
+}
+
 static const struct amd_ip_funcs gfx_v9_0_ip_funcs = {
.name = "gfx_v9_0",
.early_init = gfx_v9_0_early_init,
@@ -6775,6 +6792,7 @@ static const struct amdgpu_ring_funcs 
gfx_v9_0_ring_funcs_compute = {
.emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
.emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
.emit_mem_sync = gfx_v9_0_emit_mem_sync,
+   .emit_wave_limit = gfx_v9_0_emit_wave_limit,
 };

 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
--
2.30.0

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Re: [PATCH v4 01/14] drm/ttm: Remap all page faults to per process dummy page.

[Andrey Grodzovsky]

Hey Daniel, just a ping.

Andrey

On 1/25/21 10:28 AM, Andrey Grodzovsky wrote:


On 1/19/21 8:56 AM, Daniel Vetter wrote:

On Mon, Jan 18, 2021 at 04:01:10PM -0500, Andrey Grodzovsky wrote:

On device removal reroute all CPU mappings to dummy page.

v3:
Remove loop to find DRM file and instead access it
by vma->vm_file->private_data. Move dummy page installation
into a separate function.

v4:
Map the entire BOs VA space into on demand allocated dummy page
on the first fault for that BO.

Signed-off-by: Andrey Grodzovsky 
---
  drivers/gpu/drm/ttm/ttm_bo_vm.c | 82 
-

  include/drm/ttm/ttm_bo_api.h    |  2 +
  2 files changed, 83 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/ttm/ttm_bo_vm.c b/drivers/gpu/drm/ttm/ttm_bo_vm.c
index 6dc96cf..ed89da3 100644
--- a/drivers/gpu/drm/ttm/ttm_bo_vm.c
+++ b/drivers/gpu/drm/ttm/ttm_bo_vm.c
@@ -34,6 +34,8 @@
  #include 
  #include 
  #include 
+#include 
+#include 
  #include 
  #include 
  #include 
@@ -380,25 +382,103 @@ vm_fault_t ttm_bo_vm_fault_reserved(struct vm_fault 
*vmf,

  }
  EXPORT_SYMBOL(ttm_bo_vm_fault_reserved);
  +static void ttm_bo_release_dummy_page(struct drm_device *dev, void *res)
+{
+    struct page *dummy_page = (struct page *)res;
+
+    __free_page(dummy_page);
+}
+
+vm_fault_t ttm_bo_vm_dummy_page(struct vm_fault *vmf, pgprot_t prot)
+{
+    struct vm_area_struct *vma = vmf->vma;
+    struct ttm_buffer_object *bo = vma->vm_private_data;
+    struct ttm_bo_device *bdev = bo->bdev;
+    struct drm_device *ddev = bo->base.dev;
+    vm_fault_t ret = VM_FAULT_NOPAGE;
+    unsigned long address = vma->vm_start;
+    unsigned long num_prefault = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT;
+    unsigned long pfn;
+    struct page *page;
+    int i;
+
+    /*
+ * Wait for buffer data in transit, due to a pipelined
+ * move.
+ */
+    ret = ttm_bo_vm_fault_idle(bo, vmf);
+    if (unlikely(ret != 0))
+    return ret;
+
+    /* Allocate new dummy page to map all the VA range in this VMA to it*/
+    page = alloc_page(GFP_KERNEL | __GFP_ZERO);
+    if (!page)
+    return VM_FAULT_OOM;
+
+    pfn = page_to_pfn(page);
+
+    /*
+ * Prefault the entire VMA range right away to avoid further faults
+ */
+    for (i = 0; i < num_prefault; ++i) {
+
+    if (unlikely(address >= vma->vm_end))
+    break;
+
+    if (vma->vm_flags & VM_MIXEDMAP)
+    ret = vmf_insert_mixed_prot(vma, address,
+    __pfn_to_pfn_t(pfn, PFN_DEV),
+    prot);
+    else
+    ret = vmf_insert_pfn_prot(vma, address, pfn, prot);
+
+    /* Never error on prefaulted PTEs */
+    if (unlikely((ret & VM_FAULT_ERROR))) {
+    if (i == 0)
+    return VM_FAULT_NOPAGE;
+    else
+    break;
+    }
+
+    address += PAGE_SIZE;
+    }
+
+    /* Set the page to be freed using drmm release action */
+    if (drmm_add_action_or_reset(ddev, ttm_bo_release_dummy_page, page))
+    return VM_FAULT_OOM;
+
+    return ret;
+}
+EXPORT_SYMBOL(ttm_bo_vm_dummy_page);

I think we can lift this entire thing (once the ttm_bo_vm_fault_idle is
gone) to the drm level, since nothing ttm specific in here. Probably stuff
it into drm_gem.c (but really it's not even gem specific, it's fully
generic "replace this vma with dummy pages pls" function.



Once I started with this I noticed that drmm_add_action_or_reset depends
on struct drm_device *ddev = bo->base.dev  and bo is the private data
we embed at the TTM level when setting up the mapping and so this forces
to move drmm_add_action_or_reset out of this function to every client who uses
this function, and then you separate the logic of page allocation from it's 
release.

So I suggest we keep it as is.

Andrey




Aside from this nit I think the overall approach you have here is starting
to look good. Lots of work&polish, but imo we're getting there and can
start landing stuff soon.
-Daniel


+
  vm_fault_t ttm_bo_vm_fault(struct vm_fault *vmf)
  {
  struct vm_area_struct *vma = vmf->vma;
  pgprot_t prot;
  struct ttm_buffer_object *bo = vma->vm_private_data;
+    struct drm_device *ddev = bo->base.dev;
  vm_fault_t ret;
+    int idx;
    ret = ttm_bo_vm_reserve(bo, vmf);
  if (ret)
  return ret;
    prot = vma->vm_page_prot;
-    ret = ttm_bo_vm_fault_reserved(vmf, prot, TTM_BO_VM_NUM_PREFAULT, 1);
+    if (drm_dev_enter(ddev, &idx)) {
+    ret = ttm_bo_vm_fault_reserved(vmf, prot, TTM_BO_VM_NUM_PREFAULT, 1);
+    drm_dev_exit(idx);
+    } else {
+    ret = ttm_bo_vm_dummy_page(vmf, prot);
+    }
  if (ret == VM_FAULT_RETRY && !(vmf->flags & FAULT_FLAG_RETRY_NOWAIT))
  return ret;
    dma_resv_unlock(bo->base.resv);
    return ret;
+
+    return ret;
  }
  EXPORT_SYMBOL(ttm_bo_vm_fault);
  diff --git a/include/drm/ttm/ttm_bo_api.h b/include/drm/ttm/ttm_bo_api.h
index e17be32..12fb2

Re: [PATCH] drm/amd/display: Add DC feature flag to disable audio

[Christian König]

Am 27.01.21 um 13:23 schrieb Ernst Sjöstrand:

Just some additional thoughts...

The amdgpu driver already supports this as I mentioned, however only 
for the non-DC codepath.
"Set HDMI/DPAudio. Only affects non-DC display handling. The default 
is -1 (Enabled), set 0 to disabled it."


I've added this because I completely reverse engineered this roughly 10 
years ago without any hardware documentation.




Linux doesn't have a good infrastructure to disable sound cards afaik. 
If someone has 6 displays, do they really need 6 extra sound cards? 
Minor thing, I know.


Well yes, that is intentional :) In general the kernel should expose and 
manage all available hardware.


What you do with that in userspace is a completely different question.

Christian.



It was very easy to do, and didn't feel intrusive.
//E

Den ons 27 jan. 2021 kl 12:11 skrev Christian König 
>:


Am 26.01.21 um 17:15 schrieb Harry Wentland:
> On 2021-01-26 9:51 a.m., Ernst Sjöstrand wrote:
>> No problems with amdgpu, but when my headphone port is glitching I
>> often end up with some HDMI audio output selected instead.
>>
>
> Wouldn't this be better fixed in the audio management service, like
> PulseAudio? It sounds like it's not remembering your preferences
> correctly.

Yeah agree. A feature like this in a specific hardware driver is
justified if it prevents hangs or something similar.

But this just sounds like a problem in a higher level of the stack
which
should be fixed hardware driver independently.

Christian.

>
> Harry
>
>> It also cleans up the clutter in the audio selection list.
>>
>> //E
>>
>> Den tis 26 jan. 2021 kl 15:34 skrev Alex Deucher
>> mailto:alexdeuc...@gmail.com>
>>:
>>
>>     On Tue, Jan 26, 2021 at 9:32 AM Ernst Sjöstrand
mailto:ern...@gmail.com>
>>     >> wrote:
>>  >
>>  > With the pre-DC path you could set audio=0 to disable audio.
>>  > This adds a similar feature for the DC path with
>>  > amdgpu.dcfeaturemask=0x10.
>>  >
>>  > Signed-off-by: Ernst Sjöstrand mailto:ern...@gmail.com>
>>     >>
>>
>>     Is there a reason you want this?  I.e., is audio causing
problems
>>     for you?
>>
>>     Alex
>>
>>  > ---
>>  > drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +++
>>  > drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 7
---
>>  >  drivers/gpu/drm/amd/display/dc/dc.h        | 1 +
>>  >  drivers/gpu/drm/amd/include/amd_shared.h         | 1 +
>>  >  4 files changed, 9 insertions(+), 3 deletions(-)
>>  >
>>  > diff --git
a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>>  > index e490fc2486f7..322d9439b9c2 100644
>>  > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>>  > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>>  > @@ -1013,6 +1013,9 @@ static int amdgpu_dm_init(struct
>>     amdgpu_device *adev)
>>  >         if (amdgpu_dc_feature_mask &
>> DC_DISABLE_FRACTIONAL_PWM_MASK)
>>  >  init_data.flags.disable_fractional_pwm = true;
>>  >
>>  > +       if (amdgpu_dc_feature_mask & DC_DISABLE_AUDIO)
>>  > +  init_data.flags.disable_audio = true;
>>  > +
>>  >  init_data.flags.power_down_display_on_boot = true;
>>  >
>>  >         init_data.soc_bounding_box =
adev->dm.soc_bounding_box;
>>  > diff --git
a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
>> b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
>>  > index 68b65a090d17..4cc0d2308c98 100644
>>  > --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
>>  > +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
>>  > @@ -2141,9 +2141,10 @@ enum dc_status
>> resource_map_pool_resources(
>>  >                 true);
>>  >
>>  >         /* TODO: Add check if ASIC support and EDID audio */
>>  > -       if (!stream->converter_disable_audio &&
>>  > -  dc_is_audio_capable_signal(pipe_ctx->stream->signal) &&
>>  > -  stream->audio_info.mode_count &&
>>     stream->audio_info.flags.all) {
>>  > +       if (!dc->config.disable_audio &&
>>  > +  !stream->converter_disable_audio &&
>>  > +  dc_is_audio_capable_signal(pipe_ctx->stream->signal) &&
>>  > +  stream->audio_info.mode_count &&
>>     stream->audio_info.flags.all) {
>>  >  pipe_ctx->stream_res.audio =
>> find_first_free_audio(
>>  >                 &context->res_ctx, p

Re: [PATCH] drm/amd/display: Add DC feature flag to disable audio

[Ernst Sjöstrand]

Just some additional thoughts...

The amdgpu driver already supports this as I mentioned, however only for
the non-DC codepath.
"Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1
(Enabled), set 0 to disabled it."

Linux doesn't have a good infrastructure to disable sound cards afaik. If
someone has 6 displays, do they really need 6 extra sound cards? Minor
thing, I know.

It was very easy to do, and didn't feel intrusive.
//E

Den ons 27 jan. 2021 kl 12:11 skrev Christian König <
ckoenig.leichtzumer...@gmail.com>:

> Am 26.01.21 um 17:15 schrieb Harry Wentland:
> > On 2021-01-26 9:51 a.m., Ernst Sjöstrand wrote:
> >> No problems with amdgpu, but when my headphone port is glitching I
> >> often end up with some HDMI audio output selected instead.
> >>
> >
> > Wouldn't this be better fixed in the audio management service, like
> > PulseAudio? It sounds like it's not remembering your preferences
> > correctly.
>
> Yeah agree. A feature like this in a specific hardware driver is
> justified if it prevents hangs or something similar.
>
> But this just sounds like a problem in a higher level of the stack which
> should be fixed hardware driver independently.
>
> Christian.
>
> >
> > Harry
> >
> >> It also cleans up the clutter in the audio selection list.
> >>
> >> //E
> >>
> >> Den tis 26 jan. 2021 kl 15:34 skrev Alex Deucher
> >> mailto:alexdeuc...@gmail.com>>:
> >>
> >> On Tue, Jan 26, 2021 at 9:32 AM Ernst Sjöstrand  >> > wrote:
> >>  >
> >>  > With the pre-DC path you could set audio=0 to disable audio.
> >>  > This adds a similar feature for the DC path with
> >>  > amdgpu.dcfeaturemask=0x10.
> >>  >
> >>  > Signed-off-by: Ernst Sjöstrand  >> >
> >>
> >> Is there a reason you want this?  I.e., is audio causing problems
> >> for you?
> >>
> >> Alex
> >>
> >>  > ---
> >>  >  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +++
> >>  >  drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 7 ---
> >>  >  drivers/gpu/drm/amd/display/dc/dc.h   | 1 +
> >>  >  drivers/gpu/drm/amd/include/amd_shared.h  | 1 +
> >>  >  4 files changed, 9 insertions(+), 3 deletions(-)
> >>  >
> >>  > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> >> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> >>  > index e490fc2486f7..322d9439b9c2 100644
> >>  > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> >>  > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> >>  > @@ -1013,6 +1013,9 @@ static int amdgpu_dm_init(struct
> >> amdgpu_device *adev)
> >>  > if (amdgpu_dc_feature_mask &
> >> DC_DISABLE_FRACTIONAL_PWM_MASK)
> >>  > init_data.flags.disable_fractional_pwm = true;
> >>  >
> >>  > +   if (amdgpu_dc_feature_mask & DC_DISABLE_AUDIO)
> >>  > +   init_data.flags.disable_audio = true;
> >>  > +
> >>  > init_data.flags.power_down_display_on_boot = true;
> >>  >
> >>  > init_data.soc_bounding_box = adev->dm.soc_bounding_box;
> >>  > diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> >> b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> >>  > index 68b65a090d17..4cc0d2308c98 100644
> >>  > --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> >>  > +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> >>  > @@ -2141,9 +2141,10 @@ enum dc_status
> >> resource_map_pool_resources(
> >>  > true);
> >>  >
> >>  > /* TODO: Add check if ASIC support and EDID audio */
> >>  > -   if (!stream->converter_disable_audio &&
> >>  > -  dc_is_audio_capable_signal(pipe_ctx->stream->signal) &&
> >>  > -   stream->audio_info.mode_count &&
> >> stream->audio_info.flags.all) {
> >>  > +   if (!dc->config.disable_audio &&
> >>  > +   !stream->converter_disable_audio &&
> >>  > +  dc_is_audio_capable_signal(pipe_ctx->stream->signal) &&
> >>  > +   stream->audio_info.mode_count &&
> >> stream->audio_info.flags.all) {
> >>  > pipe_ctx->stream_res.audio =
> >> find_first_free_audio(
> >>  > &context->res_ctx, pool,
> >> pipe_ctx->stream_res.stream_enc->id, dc_ctx->dce_version);
> >>  >
> >>  > diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
> >> b/drivers/gpu/drm/amd/display/dc/dc.h
> >>  > index 71d46ade24e5..2ab6d770c66b 100644
> >>  > --- a/drivers/gpu/drm/amd/display/dc/dc.h
> >>  > +++ b/drivers/gpu/drm/amd/display/dc/dc.h
> >>  > @@ -297,6 +297,7 @@ struct dc_config {
> >>  > bool multi_mon_pp_mclk_switch;
> >>  > bool disable_dmcu;
> >>  > bool enable_4to1MPC;
> >>  > +   bool disable_audio;
> >>  >  #if defined(CONFIG_DRM_AMD_DC_DCN)
> >>  >  

Re: [PATCH] drm/amd/amdkfd: adjust dummy functions ' placement

[Huang Rui]

On Wed, Jan 27, 2021 at 06:14:03PM +0800, Yu, Lang wrote:
> Move all the dummy functions in amdgpu_amdkfd.c to
> amdgpu_amdkfd.h as inline functions.
> 
> Signed-off-by: Lang Yu 
> Suggested-by: Felix Kuehling 

Reviewed-by: Huang Rui 

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c |  87 
>  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 151 ++---
>  2 files changed, 130 insertions(+), 108 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> index db96d69eb45e..c5343a5eecbe 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> @@ -47,12 +47,8 @@ int amdgpu_amdkfd_init(void)
>   amdgpu_amdkfd_total_mem_size = si.totalram - si.totalhigh;
>   amdgpu_amdkfd_total_mem_size *= si.mem_unit;
>  
> -#ifdef CONFIG_HSA_AMD
>   ret = kgd2kfd_init();
>   amdgpu_amdkfd_gpuvm_init_mem_limits();
> -#else
> - ret = -ENOENT;
> -#endif
>   kfd_initialized = !ret;
>  
>   return ret;
> @@ -696,86 +692,3 @@ bool amdgpu_amdkfd_have_atomics_support(struct kgd_dev 
> *kgd)
>  
>   return adev->have_atomics_support;
>  }
> -
> -#ifndef CONFIG_HSA_AMD
> -bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm)
> -{
> - return false;
> -}
> -
> -void amdgpu_amdkfd_unreserve_memory_limit(struct amdgpu_bo *bo)
> -{
> -}
> -
> -int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo)
> -{
> - return 0;
> -}
> -
> -void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
> - struct amdgpu_vm *vm)
> -{
> -}
> -
> -struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f)
> -{
> - return NULL;
> -}
> -
> -int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, struct mm_struct *mm)
> -{
> - return 0;
> -}
> -
> -struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, struct pci_dev *pdev,
> -   unsigned int asic_type, bool vf)
> -{
> - return NULL;
> -}
> -
> -bool kgd2kfd_device_init(struct kfd_dev *kfd,
> -  struct drm_device *ddev,
> -  const struct kgd2kfd_shared_resources *gpu_resources)
> -{
> - return false;
> -}
> -
> -void kgd2kfd_device_exit(struct kfd_dev *kfd)
> -{
> -}
> -
> -void kgd2kfd_exit(void)
> -{
> -}
> -
> -void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm)
> -{
> -}
> -
> -int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm)
> -{
> - return 0;
> -}
> -
> -int kgd2kfd_pre_reset(struct kfd_dev *kfd)
> -{
> - return 0;
> -}
> -
> -int kgd2kfd_post_reset(struct kfd_dev *kfd)
> -{
> - return 0;
> -}
> -
> -void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry)
> -{
> -}
> -
> -void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd)
> -{
> -}
> -
> -void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint32_t 
> throttle_bitmask)
> -{
> -}
> -#endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
> index bc9f0e42e0a2..c3a51c0d54e9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
> @@ -94,11 +94,6 @@ enum kgd_engine_type {
>   KGD_ENGINE_MAX
>  };
>  
> -struct amdgpu_amdkfd_fence *amdgpu_amdkfd_fence_create(u64 context,
> -struct mm_struct *mm);
> -bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm);
> -struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f);
> -int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo);
>  
>  struct amdkfd_process_info {
>   /* List head of all VMs that belong to a KFD process */
> @@ -132,8 +127,6 @@ void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev,
>  void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev);
>  void amdgpu_amdkfd_device_init(struct amdgpu_device *adev);
>  void amdgpu_amdkfd_device_fini(struct amdgpu_device *adev);
> -
> -int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, struct mm_struct *mm);
>  int amdgpu_amdkfd_submit_ib(struct kgd_dev *kgd, enum kgd_engine_type engine,
>   uint32_t vmid, uint64_t gpu_addr,
>   uint32_t *ib_cmd, uint32_t ib_len);
> @@ -153,6 +146,38 @@ void amdgpu_amdkfd_gpu_reset(struct kgd_dev *kgd);
>  int amdgpu_queue_mask_bit_to_set_resource_bit(struct amdgpu_device *adev,
>   int queue_bit);
>  
> +struct amdgpu_amdkfd_fence *amdgpu_amdkfd_fence_create(u64 context,
> +struct mm_struct *mm);
> +#if IS_ENABLED(CONFIG_HSA_AMD)
> +bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm);
> +struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f);
> +int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo);
> +int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, struct

Re: [PATCH] ACPI: Test for ACPI_SUCCESS rather than !ACPI_FAILURE

[Mark Brown]

On Tue, Jan 26, 2021 at 02:23:17PM -0600, Bjorn Helgaas wrote:
> From: Bjorn Helgaas 
> 
> The double negative makes it hard to read "if (!ACPI_FAILURE(status))".
> Replace it with "if (ACPI_SUCCESS(status))".

Acked-by: Mark Brown 


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Re: [PATCH] drm/amd/display: Add DC feature flag to disable audio

[Christian König]

Am 26.01.21 um 17:15 schrieb Harry Wentland:

On 2021-01-26 9:51 a.m., Ernst Sjöstrand wrote:
No problems with amdgpu, but when my headphone port is glitching I 
often end up with some HDMI audio output selected instead.




Wouldn't this be better fixed in the audio management service, like 
PulseAudio? It sounds like it's not remembering your preferences 
correctly.


Yeah agree. A feature like this in a specific hardware driver is 
justified if it prevents hangs or something similar.


But this just sounds like a problem in a higher level of the stack which 
should be fixed hardware driver independently.


Christian.



Harry


It also cleans up the clutter in the audio selection list.

//E

Den tis 26 jan. 2021 kl 15:34 skrev Alex Deucher 
mailto:alexdeuc...@gmail.com>>:


    On Tue, Jan 26, 2021 at 9:32 AM Ernst Sjöstrand mailto:ern...@gmail.com>> wrote:
 >
 > With the pre-DC path you could set audio=0 to disable audio.
 > This adds a similar feature for the DC path with
 > amdgpu.dcfeaturemask=0x10.
 >
 > Signed-off-by: Ernst Sjöstrand mailto:ern...@gmail.com>>

    Is there a reason you want this?  I.e., is audio causing problems
    for you?

    Alex

 > ---
 >  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +++
 >  drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 7 ---
 >  drivers/gpu/drm/amd/display/dc/dc.h               | 1 +
 >  drivers/gpu/drm/amd/include/amd_shared.h          | 1 +
 >  4 files changed, 9 insertions(+), 3 deletions(-)
 >
 > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
    b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
 > index e490fc2486f7..322d9439b9c2 100644
 > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
 > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
 > @@ -1013,6 +1013,9 @@ static int amdgpu_dm_init(struct
    amdgpu_device *adev)
 >         if (amdgpu_dc_feature_mask & 
DC_DISABLE_FRACTIONAL_PWM_MASK)

 >                 init_data.flags.disable_fractional_pwm = true;
 >
 > +       if (amdgpu_dc_feature_mask & DC_DISABLE_AUDIO)
 > +               init_data.flags.disable_audio = true;
 > +
 >         init_data.flags.power_down_display_on_boot = true;
 >
 >         init_data.soc_bounding_box = adev->dm.soc_bounding_box;
 > diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
    b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
 > index 68b65a090d17..4cc0d2308c98 100644
 > --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
 > +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
 > @@ -2141,9 +2141,10 @@ enum dc_status 
resource_map_pool_resources(

 >                 true);
 >
 >         /* TODO: Add check if ASIC support and EDID audio */
 > -       if (!stream->converter_disable_audio &&
 > -  dc_is_audio_capable_signal(pipe_ctx->stream->signal) &&
 > -           stream->audio_info.mode_count &&
    stream->audio_info.flags.all) {
 > +       if (!dc->config.disable_audio &&
 > +               !stream->converter_disable_audio &&
 > +  dc_is_audio_capable_signal(pipe_ctx->stream->signal) &&
 > +               stream->audio_info.mode_count &&
    stream->audio_info.flags.all) {
 >                 pipe_ctx->stream_res.audio = 
find_first_free_audio(

 >                 &context->res_ctx, pool,
    pipe_ctx->stream_res.stream_enc->id, dc_ctx->dce_version);
 >
 > diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
    b/drivers/gpu/drm/amd/display/dc/dc.h
 > index 71d46ade24e5..2ab6d770c66b 100644
 > --- a/drivers/gpu/drm/amd/display/dc/dc.h
 > +++ b/drivers/gpu/drm/amd/display/dc/dc.h
 > @@ -297,6 +297,7 @@ struct dc_config {
 >         bool multi_mon_pp_mclk_switch;
 >         bool disable_dmcu;
 >         bool enable_4to1MPC;
 > +       bool disable_audio;
 >  #if defined(CONFIG_DRM_AMD_DC_DCN)
 >         bool clamp_min_dcfclk;
 >  #endif
 > diff --git a/drivers/gpu/drm/amd/include/amd_shared.h
    b/drivers/gpu/drm/amd/include/amd_shared.h
 > index 9676016a37ce..7202d816a97e 100644
 > --- a/drivers/gpu/drm/amd/include/amd_shared.h
 > +++ b/drivers/gpu/drm/amd/include/amd_shared.h
 > @@ -220,6 +220,7 @@ enum DC_FEATURE_MASK {
 >         DC_MULTI_MON_PP_MCLK_SWITCH_MASK = 0x2,
 >         DC_DISABLE_FRACTIONAL_PWM_MASK = 0x4,
 >         DC_PSR_MASK = 0x8,
 > +       DC_DISABLE_AUDIO = 0x10,
 >  };
 >
 >  enum DC_DEBUG_MASK {
 > --
 > 2.27.0
 >
 > ___
 > amd-gfx mailing list
 > amd-gfx@lists.freedesktop.org 


 > https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH] drm/amd/amdkfd: adjust dummy functions ' placement

[Lang Yu]

Move all the dummy functions in amdgpu_amdkfd.c to
amdgpu_amdkfd.h as inline functions.

Signed-off-by: Lang Yu 
Suggested-by: Felix Kuehling 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c |  87 
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 151 ++---
 2 files changed, 130 insertions(+), 108 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index db96d69eb45e..c5343a5eecbe 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -47,12 +47,8 @@ int amdgpu_amdkfd_init(void)
amdgpu_amdkfd_total_mem_size = si.totalram - si.totalhigh;
amdgpu_amdkfd_total_mem_size *= si.mem_unit;
 
-#ifdef CONFIG_HSA_AMD
ret = kgd2kfd_init();
amdgpu_amdkfd_gpuvm_init_mem_limits();
-#else
-   ret = -ENOENT;
-#endif
kfd_initialized = !ret;
 
return ret;
@@ -696,86 +692,3 @@ bool amdgpu_amdkfd_have_atomics_support(struct kgd_dev 
*kgd)
 
return adev->have_atomics_support;
 }
-
-#ifndef CONFIG_HSA_AMD
-bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm)
-{
-   return false;
-}
-
-void amdgpu_amdkfd_unreserve_memory_limit(struct amdgpu_bo *bo)
-{
-}
-
-int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo)
-{
-   return 0;
-}
-
-void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
-   struct amdgpu_vm *vm)
-{
-}
-
-struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f)
-{
-   return NULL;
-}
-
-int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, struct mm_struct *mm)
-{
-   return 0;
-}
-
-struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, struct pci_dev *pdev,
- unsigned int asic_type, bool vf)
-{
-   return NULL;
-}
-
-bool kgd2kfd_device_init(struct kfd_dev *kfd,
-struct drm_device *ddev,
-const struct kgd2kfd_shared_resources *gpu_resources)
-{
-   return false;
-}
-
-void kgd2kfd_device_exit(struct kfd_dev *kfd)
-{
-}
-
-void kgd2kfd_exit(void)
-{
-}
-
-void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm)
-{
-}
-
-int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm)
-{
-   return 0;
-}
-
-int kgd2kfd_pre_reset(struct kfd_dev *kfd)
-{
-   return 0;
-}
-
-int kgd2kfd_post_reset(struct kfd_dev *kfd)
-{
-   return 0;
-}
-
-void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry)
-{
-}
-
-void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd)
-{
-}
-
-void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint32_t throttle_bitmask)
-{
-}
-#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index bc9f0e42e0a2..c3a51c0d54e9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -94,11 +94,6 @@ enum kgd_engine_type {
KGD_ENGINE_MAX
 };
 
-struct amdgpu_amdkfd_fence *amdgpu_amdkfd_fence_create(u64 context,
-  struct mm_struct *mm);
-bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm);
-struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f);
-int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo);
 
 struct amdkfd_process_info {
/* List head of all VMs that belong to a KFD process */
@@ -132,8 +127,6 @@ void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev,
 void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev);
 void amdgpu_amdkfd_device_init(struct amdgpu_device *adev);
 void amdgpu_amdkfd_device_fini(struct amdgpu_device *adev);
-
-int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, struct mm_struct *mm);
 int amdgpu_amdkfd_submit_ib(struct kgd_dev *kgd, enum kgd_engine_type engine,
uint32_t vmid, uint64_t gpu_addr,
uint32_t *ib_cmd, uint32_t ib_len);
@@ -153,6 +146,38 @@ void amdgpu_amdkfd_gpu_reset(struct kgd_dev *kgd);
 int amdgpu_queue_mask_bit_to_set_resource_bit(struct amdgpu_device *adev,
int queue_bit);
 
+struct amdgpu_amdkfd_fence *amdgpu_amdkfd_fence_create(u64 context,
+  struct mm_struct *mm);
+#if IS_ENABLED(CONFIG_HSA_AMD)
+bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm);
+struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f);
+int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo);
+int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, struct mm_struct *mm);
+#else
+static inline
+bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm)
+{
+   return false;
+}
+
+static inline
+struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f)
+{
+   return NULL;
+}
+
+static inline
+int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo

RE: [PATCH v2] drm/amd/pm: Enable gfx DCS feature

[Lazar, Lijo]

[AMD Public Use]

Have some comments, please find inline <>

-Original Message-
From: amd-gfx  On Behalf Of Kenneth Feng
Sent: Wednesday, January 27, 2021 1:47 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao ; Feng, Kenneth 
Subject: [PATCH v2] drm/amd/pm: Enable gfx DCS feature

Background:
Gfx Duty Cycle Scaling(DCS) is applied on the small power limit skus.
When the current/power/temperature exceeds the limit with the heavy workload, 
the gfx core can be shut off and powered on back and forth.
The ON time and OFF time is determined by the firmware according to the 
accumulated power credits.
This feature is different from gfxoff.Gfxoff is applied in the idle case and 
DCS is applied in the case with heavey workload.There are two types of DCS:
Async DCS and Frame-aligned DCS.Frame-aligned DCS is applied on 3D fullscreen 
and VR workload.
Since we only supports Async DCS now,disalbe DCS when the 3D fullscreen or the 
VR workload type is chosen.

Verification:
The power is lowerer or the perf/watt is increased in the throttling case.
To be simplified, the entry/exit counter can be observed from the firmware.

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c  |  8 ++--
 drivers/gpu/drm/amd/include/amd_shared.h |  1 +
 .../gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c  | 12 
 3 files changed, 19 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 82c2fa8a67cd..186bbe139bde 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -131,8 +131,12 @@ uint amdgpu_pg_mask = 0x;  uint 
amdgpu_sdma_phase_quantum = 32;  char *amdgpu_disable_cu = NULL;  char 
*amdgpu_virtual_display = NULL;
-/* OverDrive(bit 14) disabled by default*/ -uint amdgpu_pp_feature_mask = 
0xbfff;
+
+/*
+ * OverDrive(bit 14) disabled by default
+ * GFX DCS(bit 19) disabled by default
+ */
+uint amdgpu_pp_feature_mask = 0xfff7bfff;

<> This  will cause a problem for other ASICS. This could be disabling feature 
bits which are no related.

 uint amdgpu_force_long_training;
 int amdgpu_job_hang_limit;
 int amdgpu_lbpw = -1;
diff --git a/drivers/gpu/drm/amd/include/amd_shared.h 
b/drivers/gpu/drm/amd/include/amd_shared.h
index 9676016a37ce..43ed6291b2b8 100644
--- a/drivers/gpu/drm/amd/include/amd_shared.h
+++ b/drivers/gpu/drm/amd/include/amd_shared.h
@@ -213,6 +213,7 @@ enum PP_FEATURE_MASK {
PP_ACG_MASK = 0x1,
PP_STUTTER_MODE = 0x2,
PP_AVFS_MASK = 0x4,
+   PP_GFX_DCS_MASK = 0x8,
 };
 
 enum DC_FEATURE_MASK {
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 24f3c96a5e5e..dffdcebc80e1 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -261,6 +261,9 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context 
*smu,
*(uint64_t *)feature_mask |= 
FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT);
}
 
+   if ((adev->pm.pp_feature & PP_GFX_DCS_MASK) && adev->asic_type > 
CHIP_SIENNA_CICHLID)
+   *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DCS_BIT);
+
if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
| 
FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
@@ -1437,6 +1440,15 @@ static int sienna_cichlid_set_power_profile_mode(struct 
smu_context *smu, long *
smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1 << workload_type, NULL);
 
+   /* have to disable dcs if it's the 3D fullscreen or VR workload type */
+   if ((smu->adev->pm.pp_feature & PP_GFX_DCS_MASK) &&
+   smu->adev->asic_type > CHIP_SIENNA_CICHLID) {
+   ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_DCS_BIT, 
(workload_type ==
+   WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT || workload_type == 
WORKLOAD_PPLIB_VR_BIT) ? 0 : 1);
+   if (ret)
+   return ret;
+   }

<> Is it guaranteed that power profile mode is set before running any 3D app? 
It seems optional and what happens if a 3D app is run without calling this?

Thanks,
Lijo

return ret;
 }
 
--
2.17.1

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RE: [PATCH v2] drm/amd/pm: Enable gfx DCS feature

[Zhou1, Tao]

[AMD Public Use]

Reviewed-by: Tao Zhou 

> -Original Message-
> From: Kenneth Feng 
> Sent: Wednesday, January 27, 2021 4:17 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhou1, Tao ; Feng, Kenneth
> 
> Subject: [PATCH v2] drm/amd/pm: Enable gfx DCS feature
> 
> Background:
> Gfx Duty Cycle Scaling(DCS) is applied on the small power limit skus.
> When the current/power/temperature exceeds the limit with the heavy
> workload, the gfx core can be shut off and powered on back and forth.
> The ON time and OFF time is determined by the firmware according to the
> accumulated power credits.
> This feature is different from gfxoff.Gfxoff is applied in the idle case and 
> DCS is
> applied in the case with heavey workload.There are two types of DCS:
> Async DCS and Frame-aligned DCS.Frame-aligned DCS is applied on 3D fullscreen
> and VR workload.
> Since we only supports Async DCS now,disalbe DCS when the 3D fullscreen or
> the VR workload type is chosen.
> 
> Verification:
> The power is lowerer or the perf/watt is increased in the throttling case.
> To be simplified, the entry/exit counter can be observed from the firmware.
> 
> Signed-off-by: Kenneth Feng 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c  |  8 ++--
>  drivers/gpu/drm/amd/include/amd_shared.h |  1 +
>  .../gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c  | 12 
>  3 files changed, 19 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index 82c2fa8a67cd..186bbe139bde 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -131,8 +131,12 @@ uint amdgpu_pg_mask = 0x;  uint
> amdgpu_sdma_phase_quantum = 32;  char *amdgpu_disable_cu = NULL;  char
> *amdgpu_virtual_display = NULL;
> -/* OverDrive(bit 14) disabled by default*/ -uint amdgpu_pp_feature_mask =
> 0xbfff;
> +
> +/*
> + * OverDrive(bit 14) disabled by default
> + * GFX DCS(bit 19) disabled by default
> + */
> +uint amdgpu_pp_feature_mask = 0xfff7bfff;
>  uint amdgpu_force_long_training;
>  int amdgpu_job_hang_limit;
>  int amdgpu_lbpw = -1;
> diff --git a/drivers/gpu/drm/amd/include/amd_shared.h
> b/drivers/gpu/drm/amd/include/amd_shared.h
> index 9676016a37ce..43ed6291b2b8 100644
> --- a/drivers/gpu/drm/amd/include/amd_shared.h
> +++ b/drivers/gpu/drm/amd/include/amd_shared.h
> @@ -213,6 +213,7 @@ enum PP_FEATURE_MASK {
>   PP_ACG_MASK = 0x1,
>   PP_STUTTER_MODE = 0x2,
>   PP_AVFS_MASK = 0x4,
> + PP_GFX_DCS_MASK = 0x8,
>  };
> 
>  enum DC_FEATURE_MASK {
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> index 24f3c96a5e5e..dffdcebc80e1 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> @@ -261,6 +261,9 @@ sienna_cichlid_get_allowed_feature_mask(struct
> smu_context *smu,
>   *(uint64_t *)feature_mask |=
> FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT);
>   }
> 
> + if ((adev->pm.pp_feature & PP_GFX_DCS_MASK) && adev->asic_type >
> CHIP_SIENNA_CICHLID)
> + *(uint64_t *)feature_mask |=
> FEATURE_MASK(FEATURE_GFX_DCS_BIT);
> +
>   if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
>   *(uint64_t *)feature_mask |=
> FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
>   |
> FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
> @@ -1437,6 +1440,15 @@ static int
> sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *
>   smu_cmn_send_smc_msg_with_param(smu,
> SMU_MSG_SetWorkloadMask,
>   1 << workload_type, NULL);
> 
> + /* have to disable dcs if it's the 3D fullscreen or VR workload type */
> + if ((smu->adev->pm.pp_feature & PP_GFX_DCS_MASK) &&
> + smu->adev->asic_type > CHIP_SIENNA_CICHLID) {
> + ret = smu_cmn_feature_set_enabled(smu,
> SMU_FEATURE_GFX_DCS_BIT, (workload_type ==
> + WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT ||
> workload_type == WORKLOAD_PPLIB_VR_BIT) ? 0 : 1);
> + if (ret)
> + return ret;
> + }
> +
>   return ret;
>  }
> 
> --
> 2.17.1
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[PATCH v2] drm/amd/pm: Enable gfx DCS feature

[Kenneth Feng]

Background:
Gfx Duty Cycle Scaling(DCS) is applied on the small power limit skus.
When the current/power/temperature exceeds the limit with the heavy workload,
the gfx core can be shut off and powered on back and forth.
The ON time and OFF time is determined by the firmware according to
the accumulated power credits.
This feature is different from gfxoff.Gfxoff is applied in the idle case
and DCS is applied in the case with heavey workload.There are two types of DCS:
Async DCS and Frame-aligned DCS.Frame-aligned DCS is applied on 3D fullscreen
and VR workload.
Since we only supports Async DCS now,disalbe DCS when the 3D fullscreen or
the VR workload type is chosen.

Verification:
The power is lowerer or the perf/watt is increased in the throttling case.
To be simplified, the entry/exit counter can be observed from the firmware.

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c  |  8 ++--
 drivers/gpu/drm/amd/include/amd_shared.h |  1 +
 .../gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c  | 12 
 3 files changed, 19 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 82c2fa8a67cd..186bbe139bde 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -131,8 +131,12 @@ uint amdgpu_pg_mask = 0x;
 uint amdgpu_sdma_phase_quantum = 32;
 char *amdgpu_disable_cu = NULL;
 char *amdgpu_virtual_display = NULL;
-/* OverDrive(bit 14) disabled by default*/
-uint amdgpu_pp_feature_mask = 0xbfff;
+
+/*
+ * OverDrive(bit 14) disabled by default
+ * GFX DCS(bit 19) disabled by default
+ */
+uint amdgpu_pp_feature_mask = 0xfff7bfff;
 uint amdgpu_force_long_training;
 int amdgpu_job_hang_limit;
 int amdgpu_lbpw = -1;
diff --git a/drivers/gpu/drm/amd/include/amd_shared.h 
b/drivers/gpu/drm/amd/include/amd_shared.h
index 9676016a37ce..43ed6291b2b8 100644
--- a/drivers/gpu/drm/amd/include/amd_shared.h
+++ b/drivers/gpu/drm/amd/include/amd_shared.h
@@ -213,6 +213,7 @@ enum PP_FEATURE_MASK {
PP_ACG_MASK = 0x1,
PP_STUTTER_MODE = 0x2,
PP_AVFS_MASK = 0x4,
+   PP_GFX_DCS_MASK = 0x8,
 };
 
 enum DC_FEATURE_MASK {
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 24f3c96a5e5e..dffdcebc80e1 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -261,6 +261,9 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context 
*smu,
*(uint64_t *)feature_mask |= 
FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT);
}
 
+   if ((adev->pm.pp_feature & PP_GFX_DCS_MASK) && adev->asic_type > 
CHIP_SIENNA_CICHLID)
+   *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DCS_BIT);
+
if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
| 
FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
@@ -1437,6 +1440,15 @@ static int sienna_cichlid_set_power_profile_mode(struct 
smu_context *smu, long *
smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1 << workload_type, NULL);
 
+   /* have to disable dcs if it's the 3D fullscreen or VR workload type */
+   if ((smu->adev->pm.pp_feature & PP_GFX_DCS_MASK) &&
+   smu->adev->asic_type > CHIP_SIENNA_CICHLID) {
+   ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_DCS_BIT, 
(workload_type ==
+   WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT || workload_type == 
WORKLOAD_PPLIB_VR_BIT) ? 0 : 1);
+   if (ret)
+   return ret;
+   }
+
return ret;
 }
 
-- 
2.17.1

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