RE: [PATCH] drm/amdgpu: add sdma 4_x interrupts printing

[Zhang, Hawking]

[AMD Public Use]

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: Feifei Xu  
Sent: Thursday, March 4, 2021 15:40
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Xu, Feifei 
Subject: [PATCH] drm/amdgpu: add sdma 4_x interrupts printing

Add VM_HOLE/DOORBELL_INVALID_BE/POLL_TIMEOUT/SRBMWRITE
interrupt info printing.

Signed-off-by: Feifei Xu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h |   5 +
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c   | 119 +++
 2 files changed, 124 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
index e5b8fb8e75c5..f8fb755e3aa6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
@@ -64,6 +64,11 @@ struct amdgpu_sdma {
struct amdgpu_irq_src   trap_irq;
struct amdgpu_irq_src   illegal_inst_irq;
struct amdgpu_irq_src   ecc_irq;
+   struct amdgpu_irq_src   vm_hole_irq;
+   struct amdgpu_irq_src   doorbell_invalid_irq;
+   struct amdgpu_irq_src   pool_timeout_irq;
+   struct amdgpu_irq_src   srbm_write_irq;
+
int num_instances;
uint32_tsrbm_soft_reset;
boolhas_page_queue;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 70d247841d14..bcf3d62e3cb8 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -1944,6 +1944,33 @@ static int sdma_v4_0_sw_init(void *handle)
return r;
}
 
+   /* SDMA VM_HOLE/DOORBELL_INV/POLL_TIMEOUT/SRBM_WRITE_PROTECTION event*/
+   for (i = 0; i < adev->sdma.num_instances; i++) {
+   r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
+ SDMA0_4_0__SRCID__SDMA_VM_HOLE,
+ &adev->sdma.vm_hole_irq);
+   if (r)
+   return r;
+
+   r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
+ SDMA0_4_0__SRCID__SDMA_DOORBELL_INVALID,
+ &adev->sdma.doorbell_invalid_irq);
+   if (r)
+   return r;
+
+   r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
+ SDMA0_4_0__SRCID__SDMA_POLL_TIMEOUT,
+ &adev->sdma.pool_timeout_irq);
+   if (r)
+   return r;
+
+   r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
+ SDMA0_4_0__SRCID__SDMA_SRBMWRITE,
+ &adev->sdma.srbm_write_irq);
+   if (r)
+   return r;
+   }
+
for (i = 0; i < adev->sdma.num_instances; i++) {
ring = &adev->sdma.instance[i].ring;
ring->ring_obj = NULL;
@@ -2198,6 +2225,72 @@ static int sdma_v4_0_set_ecc_irq_state(struct 
amdgpu_device *adev,
return 0;
 }
 
+static int sdma_v4_0_print_iv_entry(struct amdgpu_device *adev,
+ struct amdgpu_iv_entry *entry) {
+   int instance;
+   struct amdgpu_task_info task_info;
+   u64 addr;
+
+   instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
+   if (instance < 0 || instance >= adev->sdma.num_instances) {
+   dev_err(adev->dev, "sdma instance invalid %d\n", instance);
+   return -EINVAL;
+   }
+
+   addr = (u64)entry->src_data[0] << 12;
+   addr |= ((u64)entry->src_data[1] & 0xf) << 44;
+
+   memset(&task_info, 0, sizeof(struct amdgpu_task_info));
+   amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
+
+   dev_info(adev->dev,
+  "[sdma%d] address:0x%016llx src_id:%u ring:%u vmid:%u "
+  "pasid:%u, for process %s pid %d thread %s pid %d\n",
+  instance, addr, entry->src_id, entry->ring_id, entry->vmid,
+  entry->pasid, task_info.process_name, task_info.tgid,
+  task_info.task_name, task_info.pid);
+   return 0;
+}
+
+static int sdma_v4_0_process_vm_hole_irq(struct amdgpu_device *adev,
+ struct amdgpu_irq_src *source,
+ struct amdgpu_iv_entry *entry) {
+   dev_err(adev->dev, "MC or SEM address in VM hole\n");
+   sdma_v4_0_print_iv_entry(adev, entry);
+   return 0;
+}
+
+static int sdma_v4_0_process_doorbell_invalid_irq(struct amdgpu_device *adev,
+ struct amdgpu_irq_src *source,
+ struct amdgpu_iv_entry *entry) {
+   dev_err(adev->dev, "SDMA received a doorbell from BIF with byte_enable 
!=0xff\n");
+   sdma_v4_0_print_iv_entry(adev, entry);
+   ret

Re: [PATCH] drm/ttm: ioremap buffer according to TTM mem caching setting

[Christian König]

Hi Oak,

as far as I know some architectures like PowerPC/ARM/MIPS need that. And 
we at least officially support PowerPC and ARM and MIPS is best effort 
and shouldn't break if possible.


Thomas just recently had a whole bunch of DMA-buf patches to also fix 
that up for DMA-bufs vmap as well, previously we have just been casting 
away the __iomem and hoped that it always works.


Regards,
Christian.

Am 03.03.21 um 21:59 schrieb Zeng, Oak:


[AMD Official Use Only - Internal Distribution Only]


Hi Christian,

Can you explain why __iomem annotation is mandatory for amdgpu driver? 
If this is the case, we can’t switch to memremap. The only fix seems 
to me is add a #ifdef __x86_64__ to the ioremap_cache codes.


Regards,

Oak

*From:* Christian König 
*Sent:* Wednesday, March 3, 2021 5:46 AM
*To:* Zeng, Oak ; amd-gfx@lists.freedesktop.org; 
dri-de...@lists.freedesktop.org; Daniel Vetter ; Dave 
Airlie ; Thomas Hellström (Intel) 
; dan.j.willi...@intel.com
*Cc:* kbuild-...@lists.01.org; Kuehling, Felix 
; Kasiviswanathan, Harish 
; Deucher, Alexander 
; Huang, JinHuiEric 
; Koenig, Christian 
*Subject:* Re: [PATCH] drm/ttm: ioremap buffer according to TTM mem 
caching setting


Hi Oak,


config: parisc-randconfig-r012-20210302 (attached as .config)


It's not the Intel driver build which fails here, but the build bot is 
just hosted by Intel.


The problem is that the parisc architecture doesn't defines the 
ioremap_cache() function.


I've looked at using memremap() instead of ioremap_cache(). The 
problem is that we do support architectures with the TTM as well as 
amndgpu code where the __iomem annotation is mandatory and correct.


Regards,
Christian.

Am 02.03.21 um 23:45 schrieb Zeng, Oak:

[AMD Official Use Only - Internal Distribution Only]

Hi Daniel, Thomas, Dan,

Does below message mean the calling ioremap_cache failed intel’s
driver build? I can see both ioremap_cache and ioremap_wc are
defined in arch/x86/mm/ioremap.c – why ioremap_wc doesn’t break
intel driver’s build?

Are we supposed to use memremap (offset, size, MEMREMAP_WB) to
replace ioremap_cache? When I read here
https://lwn.net/Articles/653585/


I felt that ioremap_cache returns an address annotated with _iomem
while memremap returns an address without __iomem annotation. In
our use case, GPU memory is treated as UEFI SPM (specific purpose
memory). I am not very sure whether memremap (thus no __iomem
annotation) is the right thing to do. What I am sure is, we have
tested ioremap_cache and it works fine on AMD system.

I will send out a test patch replacing ioremap_cache with
ioremap_wc, to trigger Intel build robot to see whether it fails
Intel build. I suppose it will not fail Intel build.

Regards,

Oak

*From:* Christian König 

*Sent:* Tuesday, March 2, 2021 6:31 AM
*To:* amd-gfx@lists.freedesktop.org
;
dri-de...@lists.freedesktop.org
; Daniel Vetter
 ; Dave Airlie
 ; Thomas Hellström
(Intel)  
*Cc:* Zeng, Oak  ;
kbuild-...@lists.01.org ;
Kuehling, Felix 
; Kasiviswanathan, Harish

; Deucher, Alexander
 ;
Huang, JinHuiEric 
; Koenig, Christian
 
*Subject:* Re: [PATCH] drm/ttm: ioremap buffer according to TTM
mem caching setting

Hi guys,

adding the usual suspects direct. Does anybody of hand know how to
check if an architecture supports ioremap_cache()?

For now we only need this on X86, but I would feel better if we
don't use an #ifdef here.

Regards,
Christian.

Am 02.03.21 um 05:12 schrieb kernel test robot:

Hi Oak,

  


Thank you for the patch! Yet something to improve:

  


[auto build test ERROR on drm-intel/for-linux-next]

[also build test ERROR on drm-tip/drm-tip linus/master v5.12-rc1 
next-20210302]

[cannot apply to tegra-drm/drm/tegra/for-next 
drm-exynos/exynos-drm-next drm/drm-next]

[If your patch is applied to the wrong git tree, kindly drop us a note.

And when submitting patch, we suggest to use '--base' as documented in

RE: [PATCH] drm/amdgpu: add sdma 4_x interrupts printing

[Xu, Feifei]

[AMD Official Use Only - Internal Distribution Only]

1) Fix the hardcode as:
if (instance < 0 || instance >= adev->sdma.num_instances) {

2) Fix some coding style error/warning

Thanks,
Feifei

-Original Message-
From: Feifei Xu 
Sent: Thursday, March 4, 2021 3:40 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Xu, Feifei 
Subject: [PATCH] drm/amdgpu: add sdma 4_x interrupts printing

Add VM_HOLE/DOORBELL_INVALID_BE/POLL_TIMEOUT/SRBMWRITE
interrupt info printing.

Signed-off-by: Feifei Xu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h |   5 +
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c   | 119 +++
 2 files changed, 124 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
index e5b8fb8e75c5..f8fb755e3aa6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
@@ -64,6 +64,11 @@ struct amdgpu_sdma {
 struct amdgpu_irq_srctrap_irq;
 struct amdgpu_irq_srcillegal_inst_irq;
 struct amdgpu_irq_srcecc_irq;
+struct amdgpu_irq_srcvm_hole_irq;
+struct amdgpu_irq_srcdoorbell_invalid_irq;
+struct amdgpu_irq_srcpool_timeout_irq;
+struct amdgpu_irq_srcsrbm_write_irq;
+
 intnum_instances;
 uint32_tsrbm_soft_reset;
 boolhas_page_queue;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 70d247841d14..bcf3d62e3cb8 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -1944,6 +1944,33 @@ static int sdma_v4_0_sw_init(void *handle)
 return r;
 }

+/* SDMA VM_HOLE/DOORBELL_INV/POLL_TIMEOUT/SRBM_WRITE_PROTECTION event*/
+for (i = 0; i < adev->sdma.num_instances; i++) {
+r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
+  SDMA0_4_0__SRCID__SDMA_VM_HOLE,
+  &adev->sdma.vm_hole_irq);
+if (r)
+return r;
+
+r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
+  SDMA0_4_0__SRCID__SDMA_DOORBELL_INVALID,
+  &adev->sdma.doorbell_invalid_irq);
+if (r)
+return r;
+
+r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
+  SDMA0_4_0__SRCID__SDMA_POLL_TIMEOUT,
+  &adev->sdma.pool_timeout_irq);
+if (r)
+return r;
+
+r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
+  SDMA0_4_0__SRCID__SDMA_SRBMWRITE,
+  &adev->sdma.srbm_write_irq);
+if (r)
+return r;
+}
+
 for (i = 0; i < adev->sdma.num_instances; i++) {
 ring = &adev->sdma.instance[i].ring;
 ring->ring_obj = NULL;
@@ -2198,6 +2225,72 @@ static int sdma_v4_0_set_ecc_irq_state(struct 
amdgpu_device *adev,
 return 0;
 }

+static int sdma_v4_0_print_iv_entry(struct amdgpu_device *adev,
+  struct amdgpu_iv_entry *entry) {
+int instance;
+struct amdgpu_task_info task_info;
+u64 addr;
+
+instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
+if (instance < 0 || instance >= adev->sdma.num_instances) {
+dev_err(adev->dev, "sdma instance invalid %d\n", instance);
+return -EINVAL;
+}
+
+addr = (u64)entry->src_data[0] << 12;
+addr |= ((u64)entry->src_data[1] & 0xf) << 44;
+
+memset(&task_info, 0, sizeof(struct amdgpu_task_info));
+amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
+
+dev_info(adev->dev,
+   "[sdma%d] address:0x%016llx src_id:%u ring:%u vmid:%u "
+   "pasid:%u, for process %s pid %d thread %s pid %d\n",
+   instance, addr, entry->src_id, entry->ring_id, entry->vmid,
+   entry->pasid, task_info.process_name, task_info.tgid,
+   task_info.task_name, task_info.pid);
+return 0;
+}
+
+static int sdma_v4_0_process_vm_hole_irq(struct amdgpu_device *adev,
+  struct amdgpu_irq_src *source,
+  struct amdgpu_iv_entry *entry) {
+dev_err(adev->dev, "MC or SEM address in VM hole\n");
+sdma_v4_0_print_iv_entry(adev, entry);
+return 0;
+}
+
+static int sdma_v4_0_process_doorbell_invalid_irq(struct amdgpu_device *adev,
+  struct amdgpu_irq_src *source,
+  struct amdgpu_iv_entry *entry) {
+dev_err(adev->dev, "SDMA received a doorbell from BIF with byte_enable 
!=0xff\n");
+sdma_v4_0_print_iv_entry(adev, entry);
+return 0;
+}
+
+static int sdma_v4_0_process_pool_timeout_irq(struct amdgpu_device *adev,
+  struct amdgpu_irq_src *source,
+  struct amdgpu_iv_entry *entry) {
+dev_err(adev->dev,
+"Polling register/memory timeout executing POLL_REG/MEM with finite timer\n");
+sdma_v4_0_print_iv_entry(adev, entry);
+return 0;
+}
+
+static int sdma_v4_0_process_srbm_write_irq(struct amdgpu_device *adev,
+  struct amdgpu_irq_src *source,
+  struct amdgpu_iv_entry *entry) {
+dev_err(adev->dev,
+"SDMA gets an Register Write SRBM_WRITE command in non-privilege command 
buffer\n");
+sdma_v4_0_print_iv_entry(adev, entry);
+return 0;
+}
+
 static void sdma_v4_0_update_medium_grain_clock_gating(
 struct amdgpu_device *adev,
 bool enable)
@@ -2503,7 +2596,21 @@ static const struct amdgpu_irq_src_funcs 
sdma_v4_0_ecc_irq_funcs = {
 .process = amdgpu_sdma_process_ecc_irq,  };

+static const struct amdgpu_irq_src_funcs sdma_v4_0_vm_hole_irq_funcs = {
+.process = sdma_v4_0_process_vm_ho

[PATCH] drm/amdgpu: add sdma 4_x interrupts printing

[Feifei Xu]

Add VM_HOLE/DOORBELL_INVALID_BE/POLL_TIMEOUT/SRBMWRITE
interrupt info printing.

Signed-off-by: Feifei Xu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h |   5 +
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c   | 119 +++
 2 files changed, 124 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
index e5b8fb8e75c5..f8fb755e3aa6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
@@ -64,6 +64,11 @@ struct amdgpu_sdma {
struct amdgpu_irq_src   trap_irq;
struct amdgpu_irq_src   illegal_inst_irq;
struct amdgpu_irq_src   ecc_irq;
+   struct amdgpu_irq_src   vm_hole_irq;
+   struct amdgpu_irq_src   doorbell_invalid_irq;
+   struct amdgpu_irq_src   pool_timeout_irq;
+   struct amdgpu_irq_src   srbm_write_irq;
+
int num_instances;
uint32_tsrbm_soft_reset;
boolhas_page_queue;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 70d247841d14..bcf3d62e3cb8 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -1944,6 +1944,33 @@ static int sdma_v4_0_sw_init(void *handle)
return r;
}
 
+   /* SDMA VM_HOLE/DOORBELL_INV/POLL_TIMEOUT/SRBM_WRITE_PROTECTION event*/
+   for (i = 0; i < adev->sdma.num_instances; i++) {
+   r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
+ SDMA0_4_0__SRCID__SDMA_VM_HOLE,
+ &adev->sdma.vm_hole_irq);
+   if (r)
+   return r;
+
+   r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
+ SDMA0_4_0__SRCID__SDMA_DOORBELL_INVALID,
+ &adev->sdma.doorbell_invalid_irq);
+   if (r)
+   return r;
+
+   r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
+ SDMA0_4_0__SRCID__SDMA_POLL_TIMEOUT,
+ &adev->sdma.pool_timeout_irq);
+   if (r)
+   return r;
+
+   r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
+ SDMA0_4_0__SRCID__SDMA_SRBMWRITE,
+ &adev->sdma.srbm_write_irq);
+   if (r)
+   return r;
+   }
+
for (i = 0; i < adev->sdma.num_instances; i++) {
ring = &adev->sdma.instance[i].ring;
ring->ring_obj = NULL;
@@ -2198,6 +2225,72 @@ static int sdma_v4_0_set_ecc_irq_state(struct 
amdgpu_device *adev,
return 0;
 }
 
+static int sdma_v4_0_print_iv_entry(struct amdgpu_device *adev,
+ struct amdgpu_iv_entry *entry)
+{
+   int instance;
+   struct amdgpu_task_info task_info;
+   u64 addr;
+
+   instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
+   if (instance < 0 || instance >= adev->sdma.num_instances) {
+   dev_err(adev->dev, "sdma instance invalid %d\n", instance);
+   return -EINVAL;
+   }
+
+   addr = (u64)entry->src_data[0] << 12;
+   addr |= ((u64)entry->src_data[1] & 0xf) << 44;
+
+   memset(&task_info, 0, sizeof(struct amdgpu_task_info));
+   amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
+
+   dev_info(adev->dev,
+  "[sdma%d] address:0x%016llx src_id:%u ring:%u vmid:%u "
+  "pasid:%u, for process %s pid %d thread %s pid %d\n",
+  instance, addr, entry->src_id, entry->ring_id, entry->vmid,
+  entry->pasid, task_info.process_name, task_info.tgid,
+  task_info.task_name, task_info.pid);
+   return 0;
+}
+
+static int sdma_v4_0_process_vm_hole_irq(struct amdgpu_device *adev,
+ struct amdgpu_irq_src *source,
+ struct amdgpu_iv_entry *entry)
+{
+   dev_err(adev->dev, "MC or SEM address in VM hole\n");
+   sdma_v4_0_print_iv_entry(adev, entry);
+   return 0;
+}
+
+static int sdma_v4_0_process_doorbell_invalid_irq(struct amdgpu_device *adev,
+ struct amdgpu_irq_src *source,
+ struct amdgpu_iv_entry *entry)
+{
+   dev_err(adev->dev, "SDMA received a doorbell from BIF with byte_enable 
!=0xff\n");
+   sdma_v4_0_print_iv_entry(adev, entry);
+   return 0;
+}
+
+static int sdma_v4_0_process_pool_timeout_irq(struct amdgpu_device *adev,
+ struct amdgpu_irq_src *source,
+ struct amdgpu_iv_entry *entry)
+{
+   dev_err(adev->dev,
+

RE: [PATCH] drm/amdgpu: soc15 pcie gen4 support

[Lazar, Lijo]

[AMD Public Use]

This function is doing nothing, is it necessary to maintain it? Not sure, if 
pcie gen support needs to be enabled specifically in driver.

Thanks,
Lijo

-Original Message-
From: amd-gfx  On Behalf Of Chen, Guchun
Sent: Thursday, March 4, 2021 1:06 PM
To: Alex Deucher ; Xu, Feifei 
Cc: amd-gfx list ; Zhang, Hawking 

Subject: RE: [PATCH] drm/amdgpu: soc15 pcie gen4 support

[AMD Public Use]

How about module parameter check amdgpu_pcie_gen2 in soc15_pcie_gen4_enable? Is 
it necessary to modify it as well?

Regards,
Guchun

-Original Message-
From: amd-gfx  On Behalf Of Alex Deucher
Sent: Thursday, March 4, 2021 11:58 AM
To: Xu, Feifei 
Cc: amd-gfx list ; Zhang, Hawking 

Subject: Re: [PATCH] drm/amdgpu: soc15 pcie gen4 support

On Wed, Mar 3, 2021 at 10:46 PM Feifei Xu  wrote:
>
> Signed-off-by: Feifei Xu 

Acked-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/soc15.c | 9 +
>  1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c 
> b/drivers/gpu/drm/amd/amdgpu/soc15.c
> index 28b991904eaa..437cdc56bdc5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> @@ -569,7 +569,7 @@ static int soc15_set_vce_clocks(struct amdgpu_device 
> *adev, u32 evclk, u32 ecclk
> return 0;
>  }
>
> -static void soc15_pcie_gen3_enable(struct amdgpu_device *adev)
> +static void soc15_pcie_gen4_enable(struct amdgpu_device *adev)
>  {
> if (pci_is_root_bus(adev->pdev->bus))
> return;
> @@ -581,7 +581,8 @@ static void soc15_pcie_gen3_enable(struct amdgpu_device 
> *adev)
> return;
>
> if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
> -   CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
> +   CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 |
> +   
> + CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)))
> return;
>
> /* todo */
> @@ -1374,8 +1375,8 @@ static int soc15_common_hw_init(void *handle)  {
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> -   /* enable pcie gen2/3 link */
> -   soc15_pcie_gen3_enable(adev);
> +   /* enable pcie gen2/3/4 link */
> +   soc15_pcie_gen4_enable(adev);
> /* enable aspm */
> soc15_program_aspm(adev);
> /* setup nbio registers */
> --
> 2.25.1
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flist
> s.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=04%7C01%7Cgu
> chun.chen%40amd.com%7Ca2af451ebb4b43bcc27b08d8dec1b4b5%7C3dd8961fe4884
> e608e11a82d994e183d%7C0%7C0%7C637504270832366776%7CUnknown%7CTWFpbGZsb
> 3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%
> 7C1000&sdata=jaNGe06yp8RXKQxMm%2F%2FdR%2F6DMC4h8viG3KUW3Sz2s7Y%3D&
> amp;reserved=0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=04%7C01%7Clijo.lazar%40amd.com%7C8f330aec736c4dfe8b3d08d8dee01c35%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637504401425290833%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=9r5B6ckebE7FSvUHnZPKplh5c7fDMiK57U2RPnYSeM0%3D&reserved=0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=04%7C01%7Clijo.lazar%40amd.com%7C8f330aec736c4dfe8b3d08d8dee01c35%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637504401425290833%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=9r5B6ckebE7FSvUHnZPKplh5c7fDMiK57U2RPnYSeM0%3D&reserved=0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH] drm/amd/pm: remove duplicate XGMI feature mask

[Kevin Wang]

replace SMU feature XGMI with XGMI_DPM.
it will cause show to be incorrect in pp_features node.

Signed-off-by: Kevin Wang 
---
 drivers/gpu/drm/amd/pm/inc/smu_types.h| 1 -
 drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 2 +-
 2 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/inc/smu_types.h 
b/drivers/gpu/drm/amd/pm/inc/smu_types.h
index aa4822202587..f9f45b6764fa 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_types.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_types.h
@@ -282,7 +282,6 @@ enum smu_clk_type {
__SMU_DUMMY_MAP(DS_FCLK),   \
__SMU_DUMMY_MAP(DS_MP1CLK), \
__SMU_DUMMY_MAP(DS_MP0CLK), \
-   __SMU_DUMMY_MAP(XGMI),  \
__SMU_DUMMY_MAP(DPM_GFX_PACE),  \
__SMU_DUMMY_MAP(MEM_VDDCI_SCALING), \
__SMU_DUMMY_MAP(MEM_MVDD_SCALING),  \
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
index f76d1b8aeecc..8189457a3ae6 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
@@ -162,7 +162,7 @@ static const struct cmn2asic_mapping 
arcturus_feature_mask_map[SMU_FEATURE_COUNT
FEA_MAP(DPM_SOCCLK),
FEA_MAP(DPM_FCLK),
FEA_MAP(DPM_MP0CLK),
-   ARCTURUS_FEA_MAP(SMU_FEATURE_XGMI_BIT, FEATURE_DPM_XGMI_BIT),
+   FEA_MAP(DPM_XGMI),
FEA_MAP(DS_GFXCLK),
FEA_MAP(DS_SOCCLK),
FEA_MAP(DS_LCLK),
-- 
2.17.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

RE: [PATCH] drm/amdgpu: soc15 pcie gen4 support

[Chen, Guchun]

[AMD Public Use]

How about module parameter check amdgpu_pcie_gen2 in soc15_pcie_gen4_enable? Is 
it necessary to modify it as well?

Regards,
Guchun

-Original Message-
From: amd-gfx  On Behalf Of Alex Deucher
Sent: Thursday, March 4, 2021 11:58 AM
To: Xu, Feifei 
Cc: amd-gfx list ; Zhang, Hawking 

Subject: Re: [PATCH] drm/amdgpu: soc15 pcie gen4 support

On Wed, Mar 3, 2021 at 10:46 PM Feifei Xu  wrote:
>
> Signed-off-by: Feifei Xu 

Acked-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/soc15.c | 9 +
>  1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c 
> b/drivers/gpu/drm/amd/amdgpu/soc15.c
> index 28b991904eaa..437cdc56bdc5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> @@ -569,7 +569,7 @@ static int soc15_set_vce_clocks(struct amdgpu_device 
> *adev, u32 evclk, u32 ecclk
> return 0;
>  }
>
> -static void soc15_pcie_gen3_enable(struct amdgpu_device *adev)
> +static void soc15_pcie_gen4_enable(struct amdgpu_device *adev)
>  {
> if (pci_is_root_bus(adev->pdev->bus))
> return;
> @@ -581,7 +581,8 @@ static void soc15_pcie_gen3_enable(struct amdgpu_device 
> *adev)
> return;
>
> if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
> -   CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
> +   CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 |
> +   
> + CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)))
> return;
>
> /* todo */
> @@ -1374,8 +1375,8 @@ static int soc15_common_hw_init(void *handle)  {
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> -   /* enable pcie gen2/3 link */
> -   soc15_pcie_gen3_enable(adev);
> +   /* enable pcie gen2/3/4 link */
> +   soc15_pcie_gen4_enable(adev);
> /* enable aspm */
> soc15_program_aspm(adev);
> /* setup nbio registers */
> --
> 2.25.1
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flist
> s.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=04%7C01%7Cgu
> chun.chen%40amd.com%7Ca2af451ebb4b43bcc27b08d8dec1b4b5%7C3dd8961fe4884
> e608e11a82d994e183d%7C0%7C0%7C637504270832366776%7CUnknown%7CTWFpbGZsb
> 3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%
> 7C1000&sdata=jaNGe06yp8RXKQxMm%2F%2FdR%2F6DMC4h8viG3KUW3Sz2s7Y%3D&
> amp;reserved=0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=04%7C01%7Cguchun.chen%40amd.com%7Ca2af451ebb4b43bcc27b08d8dec1b4b5%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637504270832366776%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=jaNGe06yp8RXKQxMm%2F%2FdR%2F6DMC4h8viG3KUW3Sz2s7Y%3D&reserved=0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

RE: [PATCH] drm/amdgpu: simplify the sdma 4_x MGCG/MGLS logic.

[Zhang, Hawking]

[AMD Public Use]

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: amd-gfx  On Behalf Of Feifei Xu
Sent: Thursday, March 4, 2021 14:49
To: amd-gfx@lists.freedesktop.org
Cc: alexdeuc...@gmail.com; Xu, Feifei ; Lazar, Lijo 

Subject: [PATCH] drm/amdgpu: simplify the sdma 4_x MGCG/MGLS logic.

SDMA 4_x asics share the same MGCG/MGLS setting.

Signed-off-by: Feifei Xu 
---
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 20 
 1 file changed, 4 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 3bede8a70d7e..70d247841d14 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -2271,22 +2271,10 @@ static int sdma_v4_0_set_clockgating_state(void *handle,
if (amdgpu_sriov_vf(adev))
return 0;
 
-   switch (adev->asic_type) {
-   case CHIP_VEGA10:
-   case CHIP_VEGA12:
-   case CHIP_VEGA20:
-   case CHIP_RAVEN:
-   case CHIP_ARCTURUS:
-   case CHIP_RENOIR:
-   case CHIP_ALDEBARAN:
-   sdma_v4_0_update_medium_grain_clock_gating(adev,
-   state == AMD_CG_STATE_GATE);
-   sdma_v4_0_update_medium_grain_light_sleep(adev,
-   state == AMD_CG_STATE_GATE);
-   break;
-   default:
-   break;
-   }
+   sdma_v4_0_update_medium_grain_clock_gating(adev,
+   state == AMD_CG_STATE_GATE);
+   sdma_v4_0_update_medium_grain_light_sleep(adev,
+   state == AMD_CG_STATE_GATE);
return 0;
 }
 
-- 
2.25.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=04%7C01%7Chawking.zhang%40amd.com%7Cb242d7b4c7ef418c04e808d8ded9980c%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637504373431976237%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=Cix3f%2Bji1gZRCmqdSBiNiSTu9dcwqLQ%2FNcCrtNTuQ3Q%3D&reserved=0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

RE: [PATCH] drm/amdgpu: add sdma 4_x interrupts printing

[Xu, Feifei]

Thanks. Will modify like this:
if (instance < 0 || instance > adev->sdma.num_instances) {

Thanks,
Feifei

-Original Message-
From: Zhang, Hawking  
Sent: Thursday, March 4, 2021 2:54 PM
To: Xu, Feifei ; amd-gfx@lists.freedesktop.org
Cc: Xu, Feifei 
Subject: RE: [PATCH] drm/amdgpu: add sdma 4_x interrupts printing

[AMD Public Use]

+   if (instance < 0 || instance > 7){

Please check sdma.num_instances for the maximum instance, instead of hard coded 
to 7. The SDMA instance numbers vary from ASIC to ASIC.

With above fixed, the patch is

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: Feifei Xu  
Sent: Thursday, March 4, 2021 11:45
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Xu, Feifei 
Subject: [PATCH] drm/amdgpu: add sdma 4_x interrupts printing

Add VM_HOLE/DOORBELL_INVALID_BE/POLL_TIMEOUT/SRBMWRITE
interrupt info printing.

Signed-off-by: Feifei Xu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h |   5 +
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c   | 119 +++
 2 files changed, 124 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
index e5b8fb8e75c5..f8fb755e3aa6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
@@ -64,6 +64,11 @@ struct amdgpu_sdma {
struct amdgpu_irq_src   trap_irq;
struct amdgpu_irq_src   illegal_inst_irq;
struct amdgpu_irq_src   ecc_irq;
+   struct amdgpu_irq_src   vm_hole_irq;
+   struct amdgpu_irq_src   doorbell_invalid_irq;
+   struct amdgpu_irq_src   pool_timeout_irq;
+   struct amdgpu_irq_src   srbm_write_irq;
+
int num_instances;
uint32_tsrbm_soft_reset;
boolhas_page_queue;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 3bede8a70d7e..3305b8ec5025 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -1944,6 +1944,33 @@ static int sdma_v4_0_sw_init(void *handle)
return r;
}
 
+   /* SDMA VM_HOLE/DOORBELL_INV/POLL_TIMEOUT/SRBM_WRITE_PROTECTION event*/
+   for (i = 0; i < adev->sdma.num_instances; i++) {
+   r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
+ SDMA0_4_0__SRCID__SDMA_VM_HOLE,
+ &adev->sdma.vm_hole_irq);
+   if (r)
+   return r;
+
+   r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
+ SDMA0_4_0__SRCID__SDMA_DOORBELL_INVALID,
+ &adev->sdma.doorbell_invalid_irq);
+   if (r)
+   return r;
+
+   r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
+ SDMA0_4_0__SRCID__SDMA_POLL_TIMEOUT,
+ &adev->sdma.pool_timeout_irq);
+   if (r)
+   return r;
+
+   r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
+ SDMA0_4_0__SRCID__SDMA_SRBMWRITE,
+ &adev->sdma.srbm_write_irq);
+   if (r)
+   return r;
+   }
+
for (i = 0; i < adev->sdma.num_instances; i++) {
ring = &adev->sdma.instance[i].ring;
ring->ring_obj = NULL;
@@ -2198,6 +2225,72 @@ static int sdma_v4_0_set_ecc_irq_state(struct 
amdgpu_device *adev,
return 0;
 }
 
+static int sdma_v4_0_print_iv_entry(struct amdgpu_device *adev,
+ struct amdgpu_iv_entry *entry) {
+   int instance;
+   struct amdgpu_task_info task_info;
+   u64 addr;
+   instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
+   if (instance < 0 || instance > 7){
+   dev_err(adev->dev, "sdma instance invalid %d\n", instance);
+   return -EINVAL;
+   }
+
+   addr = (u64)entry->src_data[0] << 12;
+   addr |= ((u64)entry->src_data[1] & 0xf) << 44;
+
+   memset(&task_info, 0, sizeof(struct amdgpu_task_info));
+   amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
+
+   dev_info(adev->dev,
+  "[sdma%d] address:0x%016llx src_id:%u ring:%u vmid:%u "
+  "pasid:%u, for process %s pid %d thread %s pid %d\n",
+  instance, addr, entry->src_id, entry->ring_id, entry->vmid,
+  entry->pasid, task_info.process_name, task_info.tgid,
+  task_info.task_name, task_info.pid);
+   return 0;
+}
+
+static int sdma_v4_0_process_vm_hole_irq(struct amdgpu_device *adev,
+ struct amdgpu_irq_src *source,
+ struct amdgpu_iv_entry *entry) {
+

RE: [PATCH] drm/amdgpu: soc15 pcie gen4 support

[Zhang, Hawking]

[AMD Public Use]

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: Feifei Xu  
Sent: Thursday, March 4, 2021 11:47
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Xu, Feifei 
Subject: [PATCH] drm/amdgpu: soc15 pcie gen4 support

Signed-off-by: Feifei Xu 
---
 drivers/gpu/drm/amd/amdgpu/soc15.c | 9 +
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c 
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 28b991904eaa..437cdc56bdc5 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -569,7 +569,7 @@ static int soc15_set_vce_clocks(struct amdgpu_device *adev, 
u32 evclk, u32 ecclk
return 0;
 }
 
-static void soc15_pcie_gen3_enable(struct amdgpu_device *adev)
+static void soc15_pcie_gen4_enable(struct amdgpu_device *adev)
 {
if (pci_is_root_bus(adev->pdev->bus))
return;
@@ -581,7 +581,8 @@ static void soc15_pcie_gen3_enable(struct amdgpu_device 
*adev)
return;
 
if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
-   CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
+   CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 |
+   CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)))
return;
 
/* todo */
@@ -1374,8 +1375,8 @@ static int soc15_common_hw_init(void *handle)  {
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-   /* enable pcie gen2/3 link */
-   soc15_pcie_gen3_enable(adev);
+   /* enable pcie gen2/3/4 link */
+   soc15_pcie_gen4_enable(adev);
/* enable aspm */
soc15_program_aspm(adev);
/* setup nbio registers */
--
2.25.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

RE: [PATCH] drm/amdgpu: add sdma 4_x interrupts printing

[Zhang, Hawking]

[AMD Public Use]

+   if (instance < 0 || instance > 7){

Please check sdma.num_instances for the maximum instance, instead of hard coded 
to 7. The SDMA instance numbers vary from ASIC to ASIC.

With above fixed, the patch is

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: Feifei Xu  
Sent: Thursday, March 4, 2021 11:45
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Xu, Feifei 
Subject: [PATCH] drm/amdgpu: add sdma 4_x interrupts printing

Add VM_HOLE/DOORBELL_INVALID_BE/POLL_TIMEOUT/SRBMWRITE
interrupt info printing.

Signed-off-by: Feifei Xu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h |   5 +
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c   | 119 +++
 2 files changed, 124 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
index e5b8fb8e75c5..f8fb755e3aa6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
@@ -64,6 +64,11 @@ struct amdgpu_sdma {
struct amdgpu_irq_src   trap_irq;
struct amdgpu_irq_src   illegal_inst_irq;
struct amdgpu_irq_src   ecc_irq;
+   struct amdgpu_irq_src   vm_hole_irq;
+   struct amdgpu_irq_src   doorbell_invalid_irq;
+   struct amdgpu_irq_src   pool_timeout_irq;
+   struct amdgpu_irq_src   srbm_write_irq;
+
int num_instances;
uint32_tsrbm_soft_reset;
boolhas_page_queue;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 3bede8a70d7e..3305b8ec5025 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -1944,6 +1944,33 @@ static int sdma_v4_0_sw_init(void *handle)
return r;
}
 
+   /* SDMA VM_HOLE/DOORBELL_INV/POLL_TIMEOUT/SRBM_WRITE_PROTECTION event*/
+   for (i = 0; i < adev->sdma.num_instances; i++) {
+   r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
+ SDMA0_4_0__SRCID__SDMA_VM_HOLE,
+ &adev->sdma.vm_hole_irq);
+   if (r)
+   return r;
+
+   r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
+ SDMA0_4_0__SRCID__SDMA_DOORBELL_INVALID,
+ &adev->sdma.doorbell_invalid_irq);
+   if (r)
+   return r;
+
+   r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
+ SDMA0_4_0__SRCID__SDMA_POLL_TIMEOUT,
+ &adev->sdma.pool_timeout_irq);
+   if (r)
+   return r;
+
+   r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
+ SDMA0_4_0__SRCID__SDMA_SRBMWRITE,
+ &adev->sdma.srbm_write_irq);
+   if (r)
+   return r;
+   }
+
for (i = 0; i < adev->sdma.num_instances; i++) {
ring = &adev->sdma.instance[i].ring;
ring->ring_obj = NULL;
@@ -2198,6 +2225,72 @@ static int sdma_v4_0_set_ecc_irq_state(struct 
amdgpu_device *adev,
return 0;
 }
 
+static int sdma_v4_0_print_iv_entry(struct amdgpu_device *adev,
+ struct amdgpu_iv_entry *entry) {
+   int instance;
+   struct amdgpu_task_info task_info;
+   u64 addr;
+   instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
+   if (instance < 0 || instance > 7){
+   dev_err(adev->dev, "sdma instance invalid %d\n", instance);
+   return -EINVAL;
+   }
+
+   addr = (u64)entry->src_data[0] << 12;
+   addr |= ((u64)entry->src_data[1] & 0xf) << 44;
+
+   memset(&task_info, 0, sizeof(struct amdgpu_task_info));
+   amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
+
+   dev_info(adev->dev,
+  "[sdma%d] address:0x%016llx src_id:%u ring:%u vmid:%u "
+  "pasid:%u, for process %s pid %d thread %s pid %d\n",
+  instance, addr, entry->src_id, entry->ring_id, entry->vmid,
+  entry->pasid, task_info.process_name, task_info.tgid,
+  task_info.task_name, task_info.pid);
+   return 0;
+}
+
+static int sdma_v4_0_process_vm_hole_irq(struct amdgpu_device *adev,
+ struct amdgpu_irq_src *source,
+ struct amdgpu_iv_entry *entry) {
+   dev_err(adev->dev,"MC or SEM address in VM hole. \n");
+   sdma_v4_0_print_iv_entry(adev, entry);
+   return 0;
+}
+
+static int sdma_v4_0_process_doorbell_invalid_irq(struct amdgpu_device *adev,
+ struct amdgpu_irq_src *source,
+

[PATCH] drm/amdgpu: simplify the sdma 4_x MGCG/MGLS logic.

[Feifei Xu]

SDMA 4_x asics share the same MGCG/MGLS setting.

Signed-off-by: Feifei Xu 
---
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 20 
 1 file changed, 4 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 3bede8a70d7e..70d247841d14 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -2271,22 +2271,10 @@ static int sdma_v4_0_set_clockgating_state(void *handle,
if (amdgpu_sriov_vf(adev))
return 0;
 
-   switch (adev->asic_type) {
-   case CHIP_VEGA10:
-   case CHIP_VEGA12:
-   case CHIP_VEGA20:
-   case CHIP_RAVEN:
-   case CHIP_ARCTURUS:
-   case CHIP_RENOIR:
-   case CHIP_ALDEBARAN:
-   sdma_v4_0_update_medium_grain_clock_gating(adev,
-   state == AMD_CG_STATE_GATE);
-   sdma_v4_0_update_medium_grain_light_sleep(adev,
-   state == AMD_CG_STATE_GATE);
-   break;
-   default:
-   break;
-   }
+   sdma_v4_0_update_medium_grain_clock_gating(adev,
+   state == AMD_CG_STATE_GATE);
+   sdma_v4_0_update_medium_grain_light_sleep(adev,
+   state == AMD_CG_STATE_GATE);
return 0;
 }
 
-- 
2.25.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

RE: [PATCH] drm/amdgpu: simplify the sdma 4_x MGCG/MGLS logic.

[Xu, Feifei]

Thanks. Will modify to remove the check since all SDMA 4_x share the same 
setting logic.

Thanks,
Feifei

-Original Message-
From: Lazar, Lijo  
Sent: Thursday, March 4, 2021 1:37 PM
To: Alex Deucher ; Xu, Feifei 
Cc: amd-gfx list 
Subject: RE: [PATCH] drm/amdgpu: simplify the sdma 4_x MGCG/MGLS logic.

[AMD Public Use]

There shouldn't be any check based on ASIC type. If a check is required, it 
should be based on  AMD_CG_SUPPORT_SDMA_MGCG and AMD_CG_SUPPORT_SDMA_LS. We set 
the flags appropriately for each ASIC in soc15.

Thanks,
Lijo

-Original Message-
From: amd-gfx  On Behalf Of Alex Deucher
Sent: Thursday, March 4, 2021 10:50 AM
To: Xu, Feifei 
Cc: amd-gfx list 
Subject: Re: [PATCH] drm/amdgpu: simplify the sdma 4_x MGCG/MGLS logic.

On Wed, Mar 3, 2021 at 11:44 PM Xu, Feifei  wrote:
>
> [AMD Official Use Only - Internal Distribution Only]
>
> Thanks. The VegaM still need to be rule out.

VegaM is SDMA 3.x.

Alex

>
> Thanks,
> Feifei
>
> -Original Message-
> From: Alex Deucher 
> Sent: Thursday, March 4, 2021 12:12 PM
> To: Xu, Feifei 
> Cc: amd-gfx list 
> Subject: Re: [PATCH] drm/amdgpu: simplify the sdma 4_x MGCG/MGLS logic.
>
> On Wed, Mar 3, 2021 at 10:58 PM Feifei Xu  wrote:
> >
> > SDMA 4_x asics share the same MGCG/MGLS setting.
> >
> > Signed-off-by: Feifei Xu 
> > ---
> >  drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 12 +---
> >  1 file changed, 1 insertion(+), 11 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> > b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> > index 3bede8a70d7e..f46169c048fd 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> > @@ -2271,21 +2271,11 @@ static int sdma_v4_0_set_clockgating_state(void 
> > *handle,
> > if (amdgpu_sriov_vf(adev))
> > return 0;
> >
> > -   switch (adev->asic_type) {
> > -   case CHIP_VEGA10:
> > -   case CHIP_VEGA12:
> > -   case CHIP_VEGA20:
> > -   case CHIP_RAVEN:
> > -   case CHIP_ARCTURUS:
> > -   case CHIP_RENOIR:
> > -   case CHIP_ALDEBARAN:
> > +   if (adev->asic_type >= CHIP_VEGA10){
>
> Need a space between ) and {.  That said, do we even need to check the asic 
> type here at all?  I think this applies to all chips that have sdma4.
>
> Alex
>
> > sdma_v4_0_update_medium_grain_clock_gating(adev,
> > state == AMD_CG_STATE_GATE);
> > sdma_v4_0_update_medium_grain_light_sleep(adev,
> > state == AMD_CG_STATE_GATE);
> > -   break;
> > -   default:
> > -   break;
> > }
> > return 0;
> >  }
> > --
> > 2.25.1
> >
> > ___
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org
> > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fli
> > st 
> > s.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=04%7C01%7C
> > Fe
> > ifei.Xu%40amd.com%7C67eba26e9d7a4ea88e9b08d8dec3af22%7C3dd8961fe4884
> > e6 
> > 08e11a82d994e183d%7C0%7C0%7C637504279325196042%7CUnknown%7CTWFpbGZsb
> > 3d 
> > 8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%
> > 7C 
> > 1000&sdata=jUa2v%2BB6NICmTSr9Zdt0MQdjd1oIXYOzDYloTzUstz0%3D&
> > re
> > served=0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=04%7C01%7Clijo.lazar%40amd.com%7Cbfbac27bc87349944bb208d8decd3447%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637504320239632738%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=LJ5n33cyVrDmUCl%2FrJYUUtYP4RKP3tIiS1FKOSqdwyM%3D&reserved=0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

RE: [PATCH] drm/amdgpu: simplify the sdma 4_x MGCG/MGLS logic.

[Xu, Feifei]

[AMD Official Use Only - Internal Distribution Only]

OK. Thanks for pointing it out. I will modify to remove the check.

Thanks,
Feifei

-Original Message-
From: Alex Deucher 
Sent: Thursday, March 4, 2021 1:20 PM
To: Xu, Feifei 
Cc: amd-gfx list 
Subject: Re: [PATCH] drm/amdgpu: simplify the sdma 4_x MGCG/MGLS logic.

On Wed, Mar 3, 2021 at 11:44 PM Xu, Feifei  wrote:
>
> [AMD Official Use Only - Internal Distribution Only]
>
> Thanks. The VegaM still need to be rule out.

VegaM is SDMA 3.x.

Alex

>
> Thanks,
> Feifei
>
> -Original Message-
> From: Alex Deucher 
> Sent: Thursday, March 4, 2021 12:12 PM
> To: Xu, Feifei 
> Cc: amd-gfx list 
> Subject: Re: [PATCH] drm/amdgpu: simplify the sdma 4_x MGCG/MGLS logic.
>
> On Wed, Mar 3, 2021 at 10:58 PM Feifei Xu  wrote:
> >
> > SDMA 4_x asics share the same MGCG/MGLS setting.
> >
> > Signed-off-by: Feifei Xu 
> > ---
> >  drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 12 +---
> >  1 file changed, 1 insertion(+), 11 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> > b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> > index 3bede8a70d7e..f46169c048fd 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> > @@ -2271,21 +2271,11 @@ static int sdma_v4_0_set_clockgating_state(void 
> > *handle,
> > if (amdgpu_sriov_vf(adev))
> > return 0;
> >
> > -   switch (adev->asic_type) {
> > -   case CHIP_VEGA10:
> > -   case CHIP_VEGA12:
> > -   case CHIP_VEGA20:
> > -   case CHIP_RAVEN:
> > -   case CHIP_ARCTURUS:
> > -   case CHIP_RENOIR:
> > -   case CHIP_ALDEBARAN:
> > +   if (adev->asic_type >= CHIP_VEGA10){
>
> Need a space between ) and {.  That said, do we even need to check the asic 
> type here at all?  I think this applies to all chips that have sdma4.
>
> Alex
>
> > sdma_v4_0_update_medium_grain_clock_gating(adev,
> > state == AMD_CG_STATE_GATE);
> > sdma_v4_0_update_medium_grain_light_sleep(adev,
> > state == AMD_CG_STATE_GATE);
> > -   break;
> > -   default:
> > -   break;
> > }
> > return 0;
> >  }
> > --
> > 2.25.1
> >
> > ___
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org
> > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fli
> > st
> > s.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=04%7C01%7C
> > Fe
> > ifei.Xu%40amd.com%7C67eba26e9d7a4ea88e9b08d8dec3af22%7C3dd8961fe4884
> > e6
> > 08e11a82d994e183d%7C0%7C0%7C637504279325196042%7CUnknown%7CTWFpbGZsb
> > 3d
> > 8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%
> > 7C
> > 1000&sdata=jUa2v%2BB6NICmTSr9Zdt0MQdjd1oIXYOzDYloTzUstz0%3D&
> > re
> > served=0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

RE: [PATCH] drm/amdgpu: simplify the sdma 4_x MGCG/MGLS logic.

[Lazar, Lijo]

[AMD Public Use]

There shouldn't be any check based on ASIC type. If a check is required, it 
should be based on  AMD_CG_SUPPORT_SDMA_MGCG and AMD_CG_SUPPORT_SDMA_LS. We set 
the flags appropriately for each ASIC in soc15.

Thanks,
Lijo

-Original Message-
From: amd-gfx  On Behalf Of Alex Deucher
Sent: Thursday, March 4, 2021 10:50 AM
To: Xu, Feifei 
Cc: amd-gfx list 
Subject: Re: [PATCH] drm/amdgpu: simplify the sdma 4_x MGCG/MGLS logic.

On Wed, Mar 3, 2021 at 11:44 PM Xu, Feifei  wrote:
>
> [AMD Official Use Only - Internal Distribution Only]
>
> Thanks. The VegaM still need to be rule out.

VegaM is SDMA 3.x.

Alex

>
> Thanks,
> Feifei
>
> -Original Message-
> From: Alex Deucher 
> Sent: Thursday, March 4, 2021 12:12 PM
> To: Xu, Feifei 
> Cc: amd-gfx list 
> Subject: Re: [PATCH] drm/amdgpu: simplify the sdma 4_x MGCG/MGLS logic.
>
> On Wed, Mar 3, 2021 at 10:58 PM Feifei Xu  wrote:
> >
> > SDMA 4_x asics share the same MGCG/MGLS setting.
> >
> > Signed-off-by: Feifei Xu 
> > ---
> >  drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 12 +---
> >  1 file changed, 1 insertion(+), 11 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> > b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> > index 3bede8a70d7e..f46169c048fd 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> > @@ -2271,21 +2271,11 @@ static int sdma_v4_0_set_clockgating_state(void 
> > *handle,
> > if (amdgpu_sriov_vf(adev))
> > return 0;
> >
> > -   switch (adev->asic_type) {
> > -   case CHIP_VEGA10:
> > -   case CHIP_VEGA12:
> > -   case CHIP_VEGA20:
> > -   case CHIP_RAVEN:
> > -   case CHIP_ARCTURUS:
> > -   case CHIP_RENOIR:
> > -   case CHIP_ALDEBARAN:
> > +   if (adev->asic_type >= CHIP_VEGA10){
>
> Need a space between ) and {.  That said, do we even need to check the asic 
> type here at all?  I think this applies to all chips that have sdma4.
>
> Alex
>
> > sdma_v4_0_update_medium_grain_clock_gating(adev,
> > state == AMD_CG_STATE_GATE);
> > sdma_v4_0_update_medium_grain_light_sleep(adev,
> > state == AMD_CG_STATE_GATE);
> > -   break;
> > -   default:
> > -   break;
> > }
> > return 0;
> >  }
> > --
> > 2.25.1
> >
> > ___
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org
> > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fli
> > st 
> > s.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=04%7C01%7C
> > Fe
> > ifei.Xu%40amd.com%7C67eba26e9d7a4ea88e9b08d8dec3af22%7C3dd8961fe4884
> > e6 
> > 08e11a82d994e183d%7C0%7C0%7C637504279325196042%7CUnknown%7CTWFpbGZsb
> > 3d 
> > 8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%
> > 7C 
> > 1000&sdata=jUa2v%2BB6NICmTSr9Zdt0MQdjd1oIXYOzDYloTzUstz0%3D&
> > re
> > served=0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=04%7C01%7Clijo.lazar%40amd.com%7Cbfbac27bc87349944bb208d8decd3447%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637504320239632738%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=LJ5n33cyVrDmUCl%2FrJYUUtYP4RKP3tIiS1FKOSqdwyM%3D&reserved=0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm/amdgpu: simplify the sdma 4_x MGCG/MGLS logic.

[Alex Deucher]

On Wed, Mar 3, 2021 at 11:44 PM Xu, Feifei  wrote:
>
> [AMD Official Use Only - Internal Distribution Only]
>
> Thanks. The VegaM still need to be rule out.

VegaM is SDMA 3.x.

Alex

>
> Thanks,
> Feifei
>
> -Original Message-
> From: Alex Deucher 
> Sent: Thursday, March 4, 2021 12:12 PM
> To: Xu, Feifei 
> Cc: amd-gfx list 
> Subject: Re: [PATCH] drm/amdgpu: simplify the sdma 4_x MGCG/MGLS logic.
>
> On Wed, Mar 3, 2021 at 10:58 PM Feifei Xu  wrote:
> >
> > SDMA 4_x asics share the same MGCG/MGLS setting.
> >
> > Signed-off-by: Feifei Xu 
> > ---
> >  drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 12 +---
> >  1 file changed, 1 insertion(+), 11 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> > b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> > index 3bede8a70d7e..f46169c048fd 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> > @@ -2271,21 +2271,11 @@ static int sdma_v4_0_set_clockgating_state(void 
> > *handle,
> > if (amdgpu_sriov_vf(adev))
> > return 0;
> >
> > -   switch (adev->asic_type) {
> > -   case CHIP_VEGA10:
> > -   case CHIP_VEGA12:
> > -   case CHIP_VEGA20:
> > -   case CHIP_RAVEN:
> > -   case CHIP_ARCTURUS:
> > -   case CHIP_RENOIR:
> > -   case CHIP_ALDEBARAN:
> > +   if (adev->asic_type >= CHIP_VEGA10){
>
> Need a space between ) and {.  That said, do we even need to check the asic 
> type here at all?  I think this applies to all chips that have sdma4.
>
> Alex
>
> > sdma_v4_0_update_medium_grain_clock_gating(adev,
> > state == AMD_CG_STATE_GATE);
> > sdma_v4_0_update_medium_grain_light_sleep(adev,
> > state == AMD_CG_STATE_GATE);
> > -   break;
> > -   default:
> > -   break;
> > }
> > return 0;
> >  }
> > --
> > 2.25.1
> >
> > ___
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org
> > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flist
> > s.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=04%7C01%7CFe
> > ifei.Xu%40amd.com%7C67eba26e9d7a4ea88e9b08d8dec3af22%7C3dd8961fe4884e6
> > 08e11a82d994e183d%7C0%7C0%7C637504279325196042%7CUnknown%7CTWFpbGZsb3d
> > 8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C
> > 1000&sdata=jUa2v%2BB6NICmTSr9Zdt0MQdjd1oIXYOzDYloTzUstz0%3D&re
> > served=0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

RE: [PATCH] drm/amdgpu: simplify the sdma 4_x MGCG/MGLS logic.

[Xu, Feifei]

[AMD Official Use Only - Internal Distribution Only]

Modified the coding style error. And resend. Thanks.

Thanks,
Feifei

-Original Message-
From: Feifei Xu 
Sent: Thursday, March 4, 2021 12:54 PM
To: amd-gfx@lists.freedesktop.org; alexdeuc...@gmail.com
Cc: Deucher, Alexander ; Xu, Feifei 

Subject: [PATCH] drm/amdgpu: simplify the sdma 4_x MGCG/MGLS logic.

SDMA 4_x asics share the same MGCG/MGLS setting.

Signed-off-by: Feifei Xu 
---
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 12 +---
 1 file changed, 1 insertion(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 3bede8a70d7e..0280e8f589d1 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -2271,21 +2271,11 @@ static int sdma_v4_0_set_clockgating_state(void *handle,
 if (amdgpu_sriov_vf(adev))
 return 0;

-switch (adev->asic_type) {
-case CHIP_VEGA10:
-case CHIP_VEGA12:
-case CHIP_VEGA20:
-case CHIP_RAVEN:
-case CHIP_ARCTURUS:
-case CHIP_RENOIR:
-case CHIP_ALDEBARAN:
+if (adev->asic_type >= CHIP_VEGA10) {
 sdma_v4_0_update_medium_grain_clock_gating(adev,
 state == AMD_CG_STATE_GATE);
 sdma_v4_0_update_medium_grain_light_sleep(adev,
 state == AMD_CG_STATE_GATE);
-break;
-default:
-break;
 }
 return 0;
 }
--
2.25.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH] drm/amdgpu: simplify the sdma 4_x MGCG/MGLS logic.

[Feifei Xu]

SDMA 4_x asics share the same MGCG/MGLS setting.

Signed-off-by: Feifei Xu 
---
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 12 +---
 1 file changed, 1 insertion(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 3bede8a70d7e..0280e8f589d1 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -2271,21 +2271,11 @@ static int sdma_v4_0_set_clockgating_state(void *handle,
if (amdgpu_sriov_vf(adev))
return 0;
 
-   switch (adev->asic_type) {
-   case CHIP_VEGA10:
-   case CHIP_VEGA12:
-   case CHIP_VEGA20:
-   case CHIP_RAVEN:
-   case CHIP_ARCTURUS:
-   case CHIP_RENOIR:
-   case CHIP_ALDEBARAN:
+   if (adev->asic_type >= CHIP_VEGA10) {
sdma_v4_0_update_medium_grain_clock_gating(adev,
state == AMD_CG_STATE_GATE);
sdma_v4_0_update_medium_grain_light_sleep(adev,
state == AMD_CG_STATE_GATE);
-   break;
-   default:
-   break;
}
return 0;
 }
-- 
2.25.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

RE: [PATCH] drm/amdgpu: simplify the sdma 4_x MGCG/MGLS logic.

[Xu, Feifei]

[AMD Official Use Only - Internal Distribution Only]

Thanks. The VegaM still need to be rule out.

Thanks,
Feifei

-Original Message-
From: Alex Deucher 
Sent: Thursday, March 4, 2021 12:12 PM
To: Xu, Feifei 
Cc: amd-gfx list 
Subject: Re: [PATCH] drm/amdgpu: simplify the sdma 4_x MGCG/MGLS logic.

On Wed, Mar 3, 2021 at 10:58 PM Feifei Xu  wrote:
>
> SDMA 4_x asics share the same MGCG/MGLS setting.
>
> Signed-off-by: Feifei Xu 
> ---
>  drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 12 +---
>  1 file changed, 1 insertion(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> index 3bede8a70d7e..f46169c048fd 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> @@ -2271,21 +2271,11 @@ static int sdma_v4_0_set_clockgating_state(void 
> *handle,
> if (amdgpu_sriov_vf(adev))
> return 0;
>
> -   switch (adev->asic_type) {
> -   case CHIP_VEGA10:
> -   case CHIP_VEGA12:
> -   case CHIP_VEGA20:
> -   case CHIP_RAVEN:
> -   case CHIP_ARCTURUS:
> -   case CHIP_RENOIR:
> -   case CHIP_ALDEBARAN:
> +   if (adev->asic_type >= CHIP_VEGA10){

Need a space between ) and {.  That said, do we even need to check the asic 
type here at all?  I think this applies to all chips that have sdma4.

Alex

> sdma_v4_0_update_medium_grain_clock_gating(adev,
> state == AMD_CG_STATE_GATE);
> sdma_v4_0_update_medium_grain_light_sleep(adev,
> state == AMD_CG_STATE_GATE);
> -   break;
> -   default:
> -   break;
> }
> return 0;
>  }
> --
> 2.25.1
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flist
> s.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=04%7C01%7CFe
> ifei.Xu%40amd.com%7C67eba26e9d7a4ea88e9b08d8dec3af22%7C3dd8961fe4884e6
> 08e11a82d994e183d%7C0%7C0%7C637504279325196042%7CUnknown%7CTWFpbGZsb3d
> 8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C
> 1000&sdata=jUa2v%2BB6NICmTSr9Zdt0MQdjd1oIXYOzDYloTzUstz0%3D&re
> served=0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[pull] amdgpu drm-fixes-5.12

[Alex Deucher]

Hi Dave, Daniel,

Fixes for 5.12.

The following changes since commit ea3b4242bc9ca197762119382b37e125815bd67f:

  drm/amd/display: Fix system hang after multiple hotplugs (v3) (2021-02-24 
09:48:46 -0500)

are available in the Git repository at:

  https://gitlab.freedesktop.org/agd5f/linux.git 
tags/amd-drm-fixes-5.12-2021-03-03

for you to fetch changes up to 1aa46901ee51c1c5779b3b239ea0374a50c6d9ff:

  drm/amdgpu: fix parameter error of RREG32_PCIE() in amdgpu_regs_pcie 
(2021-03-03 23:05:16 -0500)


amd-drm-fixes-5.12-2021-03-03:

amdgpu:
- S0ix fix
- Handle new NV12 SKU
- Misc power fixes
- Display uninitialized value fix
- PCIE debugfs register access fix


Alex Deucher (4):
  drm/amdgpu: Only check for S0ix if AMD_PMC is configured
  drm/amdgpu/pm: make unsupported power profile messages debug
  drm/amdgpu/swsmu/vangogh: Only use RLCPowerNotify msg for disable
  drm/amdgpu: enable BACO runpm by default on sienna cichlid and navy 
flounder

Asher.Song (1):
  drm/amdgpu:disable VCN for Navi12 SKU

Colin Ian King (1):
  drm/amd/display: fix the return of the uninitialized value in ret

Evan Quan (1):
  drm/amd/pm: correct Arcturus mmTHM_BACO_CNTL register address

Kevin Wang (1):
  drm/amdgpu: fix parameter error of RREG32_PCIE() in amdgpu_regs_pcie

 drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c  |  3 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c   |  4 ++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c   |  2 --
 drivers/gpu/drm/amd/amdgpu/nv.c   |  6 --
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c |  2 +-
 drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c |  2 +-
 drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c| 15 ---
 drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c  |  6 +++---
 drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c   |  2 +-
 9 files changed, 26 insertions(+), 16 deletions(-)
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm/amdgpu: simplify the sdma 4_x MGCG/MGLS logic.

[Alex Deucher]

On Wed, Mar 3, 2021 at 10:58 PM Feifei Xu  wrote:
>
> SDMA 4_x asics share the same MGCG/MGLS setting.
>
> Signed-off-by: Feifei Xu 
> ---
>  drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 12 +---
>  1 file changed, 1 insertion(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 
> b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> index 3bede8a70d7e..f46169c048fd 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> @@ -2271,21 +2271,11 @@ static int sdma_v4_0_set_clockgating_state(void 
> *handle,
> if (amdgpu_sriov_vf(adev))
> return 0;
>
> -   switch (adev->asic_type) {
> -   case CHIP_VEGA10:
> -   case CHIP_VEGA12:
> -   case CHIP_VEGA20:
> -   case CHIP_RAVEN:
> -   case CHIP_ARCTURUS:
> -   case CHIP_RENOIR:
> -   case CHIP_ALDEBARAN:
> +   if (adev->asic_type >= CHIP_VEGA10){

Need a space between ) and {.  That said, do we even need to check the
asic type here at all?  I think this applies to all chips that have
sdma4.

Alex

> sdma_v4_0_update_medium_grain_clock_gating(adev,
> state == AMD_CG_STATE_GATE);
> sdma_v4_0_update_medium_grain_light_sleep(adev,
> state == AMD_CG_STATE_GATE);
> -   break;
> -   default:
> -   break;
> }
> return 0;
>  }
> --
> 2.25.1
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH] drm/amdgpu: simplify the sdma 4_x MGCG/MGLS logic.

[Feifei Xu]

SDMA 4_x asics share the same MGCG/MGLS setting.

Signed-off-by: Feifei Xu 
---
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 12 +---
 1 file changed, 1 insertion(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 3bede8a70d7e..f46169c048fd 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -2271,21 +2271,11 @@ static int sdma_v4_0_set_clockgating_state(void *handle,
if (amdgpu_sriov_vf(adev))
return 0;
 
-   switch (adev->asic_type) {
-   case CHIP_VEGA10:
-   case CHIP_VEGA12:
-   case CHIP_VEGA20:
-   case CHIP_RAVEN:
-   case CHIP_ARCTURUS:
-   case CHIP_RENOIR:
-   case CHIP_ALDEBARAN:
+   if (adev->asic_type >= CHIP_VEGA10){
sdma_v4_0_update_medium_grain_clock_gating(adev,
state == AMD_CG_STATE_GATE);
sdma_v4_0_update_medium_grain_light_sleep(adev,
state == AMD_CG_STATE_GATE);
-   break;
-   default:
-   break;
}
return 0;
 }
-- 
2.25.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm/amdgpu: soc15 pcie gen4 support

[Alex Deucher]

On Wed, Mar 3, 2021 at 10:46 PM Feifei Xu  wrote:
>
> Signed-off-by: Feifei Xu 

Acked-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/soc15.c | 9 +
>  1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c 
> b/drivers/gpu/drm/amd/amdgpu/soc15.c
> index 28b991904eaa..437cdc56bdc5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> @@ -569,7 +569,7 @@ static int soc15_set_vce_clocks(struct amdgpu_device 
> *adev, u32 evclk, u32 ecclk
> return 0;
>  }
>
> -static void soc15_pcie_gen3_enable(struct amdgpu_device *adev)
> +static void soc15_pcie_gen4_enable(struct amdgpu_device *adev)
>  {
> if (pci_is_root_bus(adev->pdev->bus))
> return;
> @@ -581,7 +581,8 @@ static void soc15_pcie_gen3_enable(struct amdgpu_device 
> *adev)
> return;
>
> if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
> -   CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
> +   CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 |
> +   CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)))
> return;
>
> /* todo */
> @@ -1374,8 +1375,8 @@ static int soc15_common_hw_init(void *handle)
>  {
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> -   /* enable pcie gen2/3 link */
> -   soc15_pcie_gen3_enable(adev);
> +   /* enable pcie gen2/3/4 link */
> +   soc15_pcie_gen4_enable(adev);
> /* enable aspm */
> soc15_program_aspm(adev);
> /* setup nbio registers */
> --
> 2.25.1
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH] drm/amdgpu: soc15 pcie gen4 support

[Feifei Xu]

Signed-off-by: Feifei Xu 
---
 drivers/gpu/drm/amd/amdgpu/soc15.c | 9 +
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c 
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 28b991904eaa..437cdc56bdc5 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -569,7 +569,7 @@ static int soc15_set_vce_clocks(struct amdgpu_device *adev, 
u32 evclk, u32 ecclk
return 0;
 }
 
-static void soc15_pcie_gen3_enable(struct amdgpu_device *adev)
+static void soc15_pcie_gen4_enable(struct amdgpu_device *adev)
 {
if (pci_is_root_bus(adev->pdev->bus))
return;
@@ -581,7 +581,8 @@ static void soc15_pcie_gen3_enable(struct amdgpu_device 
*adev)
return;
 
if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
-   CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
+   CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 |
+   CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)))
return;
 
/* todo */
@@ -1374,8 +1375,8 @@ static int soc15_common_hw_init(void *handle)
 {
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-   /* enable pcie gen2/3 link */
-   soc15_pcie_gen3_enable(adev);
+   /* enable pcie gen2/3/4 link */
+   soc15_pcie_gen4_enable(adev);
/* enable aspm */
soc15_program_aspm(adev);
/* setup nbio registers */
-- 
2.25.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH] drm/amdgpu: add sdma 4_x interrupts printing

[Feifei Xu]

Add VM_HOLE/DOORBELL_INVALID_BE/POLL_TIMEOUT/SRBMWRITE
interrupt info printing.

Signed-off-by: Feifei Xu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h |   5 +
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c   | 119 +++
 2 files changed, 124 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
index e5b8fb8e75c5..f8fb755e3aa6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
@@ -64,6 +64,11 @@ struct amdgpu_sdma {
struct amdgpu_irq_src   trap_irq;
struct amdgpu_irq_src   illegal_inst_irq;
struct amdgpu_irq_src   ecc_irq;
+   struct amdgpu_irq_src   vm_hole_irq;
+   struct amdgpu_irq_src   doorbell_invalid_irq;
+   struct amdgpu_irq_src   pool_timeout_irq;
+   struct amdgpu_irq_src   srbm_write_irq;
+
int num_instances;
uint32_tsrbm_soft_reset;
boolhas_page_queue;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 3bede8a70d7e..3305b8ec5025 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -1944,6 +1944,33 @@ static int sdma_v4_0_sw_init(void *handle)
return r;
}
 
+   /* SDMA VM_HOLE/DOORBELL_INV/POLL_TIMEOUT/SRBM_WRITE_PROTECTION event*/
+   for (i = 0; i < adev->sdma.num_instances; i++) {
+   r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
+ SDMA0_4_0__SRCID__SDMA_VM_HOLE,
+ &adev->sdma.vm_hole_irq);
+   if (r)
+   return r;
+
+   r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
+ SDMA0_4_0__SRCID__SDMA_DOORBELL_INVALID,
+ &adev->sdma.doorbell_invalid_irq);
+   if (r)
+   return r;
+
+   r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
+ SDMA0_4_0__SRCID__SDMA_POLL_TIMEOUT,
+ &adev->sdma.pool_timeout_irq);
+   if (r)
+   return r;
+
+   r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
+ SDMA0_4_0__SRCID__SDMA_SRBMWRITE,
+ &adev->sdma.srbm_write_irq);
+   if (r)
+   return r;
+   }
+
for (i = 0; i < adev->sdma.num_instances; i++) {
ring = &adev->sdma.instance[i].ring;
ring->ring_obj = NULL;
@@ -2198,6 +2225,72 @@ static int sdma_v4_0_set_ecc_irq_state(struct 
amdgpu_device *adev,
return 0;
 }
 
+static int sdma_v4_0_print_iv_entry(struct amdgpu_device *adev,
+ struct amdgpu_iv_entry *entry)
+{
+   int instance;
+   struct amdgpu_task_info task_info;
+   u64 addr;
+   instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
+   if (instance < 0 || instance > 7){
+   dev_err(adev->dev, "sdma instance invalid %d\n", instance);
+   return -EINVAL;
+   }
+
+   addr = (u64)entry->src_data[0] << 12;
+   addr |= ((u64)entry->src_data[1] & 0xf) << 44;
+
+   memset(&task_info, 0, sizeof(struct amdgpu_task_info));
+   amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
+
+   dev_info(adev->dev,
+  "[sdma%d] address:0x%016llx src_id:%u ring:%u vmid:%u "
+  "pasid:%u, for process %s pid %d thread %s pid %d\n",
+  instance, addr, entry->src_id, entry->ring_id, entry->vmid,
+  entry->pasid, task_info.process_name, task_info.tgid,
+  task_info.task_name, task_info.pid);
+   return 0;
+}
+
+static int sdma_v4_0_process_vm_hole_irq(struct amdgpu_device *adev,
+ struct amdgpu_irq_src *source,
+ struct amdgpu_iv_entry *entry)
+{
+   dev_err(adev->dev,"MC or SEM address in VM hole. \n");
+   sdma_v4_0_print_iv_entry(adev, entry);
+   return 0;
+}
+
+static int sdma_v4_0_process_doorbell_invalid_irq(struct amdgpu_device *adev,
+ struct amdgpu_irq_src *source,
+ struct amdgpu_iv_entry *entry)
+{
+   dev_err(adev->dev,
+   "SDMA received a doorbell from BIF with byte_enable != 0xff.  
\n");
+   sdma_v4_0_print_iv_entry(adev, entry);
+   return 0;
+}
+
+static int sdma_v4_0_process_pool_timeout_irq(struct amdgpu_device *adev,
+ struct amdgpu_irq_src *source,
+ struct amdgpu_iv_entry *entry)
+{
+   dev_err(adev->dev,
+  

[PATCH] MIPS: drm/radeon: A gray screen appears when going into hibernation(S4)

[wangjingyu]

Radeon Card:
  Caicos[Radeon HD 6450/7450/8450 /R5 230 OEM]

there is no gray screen when echo 4>/sys/module/drm/parameters/debug,
so the WREG32 function after DRM_DEBUG_KMS may have wrong when going
into hibernation.the delay of msleep(50) just can fix gray screen.

Signed-off-by: wangjingyu 
Signed-off-by: zhuyong 
---
 drivers/gpu/drm/radeon/radeon_display.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/radeon/radeon_display.c 
b/drivers/gpu/drm/radeon/radeon_display.c
index 652af7a134bd..1be50f949bb4 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -226,6 +226,8 @@ void radeon_crtc_load_lut(struct drm_crtc *crtc)
if (!crtc->enabled)
return;
 
+   sleep(50);
+
if (ASIC_IS_DCE5(rdev))
dce5_crtc_load_lut(crtc);
else if (ASIC_IS_DCE4(rdev))
-- 
2.11.0



___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

RE: [PATCH v2] drm/amd/pm/swsmu: clean up user profile function

[Quan, Evan]

[AMD Public Use]

Reviewed-by: Evan Quan 

-Original Message-
From: Paneer Selvam, Arunpravin  
Sent: Wednesday, March 3, 2021 10:09 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Lazar, Lijo 
; Quan, Evan ; Paneer Selvam, Arunpravin 

Subject: [PATCH v2] drm/amd/pm/swsmu: clean up user profile function

Remove unnecessary comments, enable restore mode using '|=' operator, fixes the 
alignment to improve the code readability.

v2: Move all restoration flag check to bitwise '&' operator

Signed-off-by: Arunpravin 
---
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 34 ---
 1 file changed, 12 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c 
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index f5d9590f2178..a64228157ff6 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -315,35 +315,25 @@ static void smu_set_user_clk_dependencies(struct 
smu_context *smu, enum smu_clk_
if (smu->adev->in_suspend)
return;
 
-   /*
-* mclk, fclk and socclk are interdependent
-* on each other
-*/
if (clk == SMU_MCLK) {
-   /* reset clock dependency */
smu->user_dpm_profile.clk_dependency = 0;
-   /* set mclk dependent clocks(fclk and socclk) */
smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | 
BIT(SMU_SOCCLK);
} else if (clk == SMU_FCLK) {
-   /* give priority to mclk, if mclk dependent clocks are set */
+   /* MCLK takes precedence over FCLK */
if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | 
BIT(SMU_SOCCLK)))
return;
 
-   /* reset clock dependency */
smu->user_dpm_profile.clk_dependency = 0;
-   /* set fclk dependent clocks(mclk and socclk) */
smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | 
BIT(SMU_SOCCLK);
} else if (clk == SMU_SOCCLK) {
-   /* give priority to mclk, if mclk dependent clocks are set */
+   /* MCLK takes precedence over SOCCLK */
if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | 
BIT(SMU_SOCCLK)))
return;
 
-   /* reset clock dependency */
smu->user_dpm_profile.clk_dependency = 0;
-   /* set socclk dependent clocks(mclk and fclk) */
smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | 
BIT(SMU_FCLK);
} else
-   /* add clk dependencies here, if any */
+   /* Add clk dependencies here, if any */
return;
 }
 
@@ -367,7 +357,7 @@ static void smu_restore_dpm_user_profile(struct smu_context 
*smu)
return;
 
/* Enable restore flag */
-   smu->user_dpm_profile.flags = SMU_DPM_USER_PROFILE_RESTORE;
+   smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE;
 
/* set the user dpm power limit */
if (smu->user_dpm_profile.power_limit) { @@ -390,8 +380,8 @@ static 
void smu_restore_dpm_user_profile(struct smu_context *smu)
ret = smu_force_smuclk_levels(smu, clk_type,

smu->user_dpm_profile.clk_mask[clk_type]);
if (ret)
-   dev_err(smu->adev->dev, "Failed to set 
clock type = %d\n",
-   clk_type);
+   dev_err(smu->adev->dev,
+   "Failed to set clock type = 
%d\n", clk_type);
}
}
}
@@ -1844,7 +1834,7 @@ static int smu_force_smuclk_levels(struct smu_context 
*smu,
 
if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) {
ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask);
-   if (!ret && smu->user_dpm_profile.flags != 
SMU_DPM_USER_PROFILE_RESTORE) {
+   if (!ret && !(smu->user_dpm_profile.flags & 
+SMU_DPM_USER_PROFILE_RESTORE)) {
smu->user_dpm_profile.clk_mask[clk_type] = mask;
smu_set_user_clk_dependencies(smu, clk_type);
}
@@ -2141,7 +2131,7 @@ int smu_set_fan_speed_rpm(void *handle, uint32_t speed)
if (smu->ppt_funcs->set_fan_speed_percent) {
percent = speed * 100 / smu->fan_max_rpm;
ret = smu->ppt_funcs->set_fan_speed_percent(smu, percent);
-   if (!ret && smu->user_dpm_profile.flags != 
SMU_DPM_USER_PROFILE_RESTORE)
+   if (!ret && !(smu->user_dpm_profile.flags & 
+SMU_DPM_USER_PROFILE_RESTORE))
smu->user_dpm_profile.fan_speed_percent = percent;
}
 
@@ -2212,7 +2202,7 @@ int smu_set_power_limit(void *handle, uint32_t limit)
 
if (smu->ppt_func

PROBLEM: random desktop freezes, kmsg errors "Failed to parse relocation -12" and "failed to pin new rbo buffer before flip"

[Lucas Werkmeister]

Hi all,

on Linux 5.11.1 and 5.11.2 (but not 5.10.16), my Gnome desktop (Radeon
R7 260X GPU) occasionally (usually after a few hours) freezes
completely; when it happens, I can still switch to a TTY (Ctrl+Alt+F3)
and back to the frozen desktop (Ctrl+Alt+F2), but I haven’t found a way
to “rescue” the desktop from the command line, and ultimately have to
reboot. When that happens, the journal is filled with many copies of
these kernel messages:

> [drm:radeon_cs_ioctl [radeon]] *ERROR* Failed to parse relocation -12!

> radeon :01:00.0: 641f4713 pin failed

> [drm:radeon_crtc_page_flip_target [radeon]] *ERROR* failed to pin new
> rbo buffer before flip

I have uploaded the kernel logs of one affected boot, in systemd journal
export format, at .

Keywords: drm, radeon, amd, graphics

Kernel version:
$ cat /proc/version
Linux version 5.11.2-arch1-1 (linux@archlinux) (gcc (GCC) 10.2.0, GNU ld
(GNU Binutils) 2.36.1) #1 SMP PREEMPT Fri, 26 Feb 2021 18:26:41 +

Kernel .config file (from /proc/config.gz):


Most recent kernel version which did not have the bug: 5.10.16 [though
this has a similar issue, where the desktop also freezes but then
unfreezes either on its own or when I switch to a TTY and back; I
haven’t reported this yet, and don’t know if it’s related or not]

I have not yet found a way to systematically reproduce this. It seems to
happen more frequently when there is more load on the system, or on the
graphics card (e.g. fullscreen video playback, desktop recording).

ver_linux output:

Linux theoden 5.11.2-arch1-1 #1 SMP PREEMPT Fri, 26 Feb 2021 18:26:41
+ x86_64 GNU/Linux

GNU C   10.2.0
GNU Make4.3
Binutils2.36.1
Util-linux  2.36.2
Mount   2.36.2
Module-init-tools   28
E2fsprogs   1.46.2
Jfsutils1.1.15
Reiserfsprogs   3.6.27
Xfsprogs5.10.0
Quota-tools 4.06
Bison   3.7.3
Flex2.6.4
Linux C++ Library   6.0.28
Linux C Library 2.33
Dynamic linker (ldd)2.33
Procps  3.3.17
Kbd 2.4.0
Console-tools   2.4.0
Sh-utils8.32
Udev247
Modules Loaded  ac97_bus aesni_intel agpgart amdgpu at24 cbc
cdrom cec coretemp crc16 crc32c_generic crc32c_intel crc32_pclmul
crct10dif_pclmul cryptd crypto_simd crypto_user dm_bio_prison dm_bufio
dm_cache dm_cache_smq dm_crypt dm_mod dm_persistent_data drm
drm_kms_helper drm_ttm_helper e1000e encrypted_keys ext4 fat fb_sys_fops
fuse ghash_clmulni_intel glue_helper gpu_sched i2c_algo_bit i2c_i801
i2c_smbus intel_cstate intel_pmc_bxt intel_powerclamp intel_rapl_common
intel_rapl_msr intel_uncore ip_tables irqbypass iTCO_vendor_support
iTCO_wdt jbd2 joydev kvm kvm_intel ledtrig_audio libcrc32c lpc_ich
mac_hid mbcache mc mei mei_hdcp mei_me mei_wdt mousedev nls_iso8859_1
pcspkr radeon rapl rfkill rng_core sg snd snd_compress snd_hda_codec
snd_hda_codec_generic snd_hda_codec_hdmi snd_hda_codec_realtek
snd_hda_core snd_hda_intel snd_hwdep snd_intel_dspcfg snd_pcm
snd_pcm_dmaengine snd_rawmidi snd_seq_device snd_soc_core snd_timer
snd_usb_audio snd_usbmidi_lib soundcore soundwire_bus soundwire_cadence
soundwire_generic_allocation soundwire_intel sr_mod syscopyarea
sysfillrect sysimgblt tpm trusted ttm uas usbhid usb_storage uvcvideo
vfat video videobuf2_common videobuf2_memops videobuf2_v4l2
videobuf2_vmalloc videodev x86_pkg_temp_thermal xhci_pci
xhci_pci_renesas x_tables

CPU: Intel i7-4771, full /proc/cpuinfo at

Graphics card: Radeon R7 260X/360, see below for lspci

/proc/modules: 
/proc/ioports: 
/proc/iomem: 
sudo lspci -vvv: 
/proc/scsi/scsi: 

I can’t think of any other relevant information at the moment, but I’ll
be happy to respond to any questions you have. If you come up with a
patch, I think I should be able to test it, though admittedly it’s been
a few years since I’ve built a kernel.

Cheers,
Lucas Werkmeister
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH] drm/ttm: ioremap buffer according to TTM mem caching setting

[Oak Zeng]

If tbo.mem.bus.caching is cached, buffer is intended to be mapped
as cached from CPU. Map it with ioremap_cache.

This wasn't necessary before as device memory was never mapped
as cached from CPU side. It becomes necessary for aldebaran as
device memory is mapped cached from CPU.

Signed-off-by: Oak Zeng 
Reviewed-by: Christian Konig 
---
 drivers/gpu/drm/ttm/ttm_bo_util.c | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c 
b/drivers/gpu/drm/ttm/ttm_bo_util.c
index 031e581..7c848e2 100644
--- a/drivers/gpu/drm/ttm/ttm_bo_util.c
+++ b/drivers/gpu/drm/ttm/ttm_bo_util.c
@@ -91,6 +91,10 @@ static int ttm_resource_ioremap(struct ttm_device *bdev,
 
if (mem->bus.caching == ttm_write_combined)
addr = ioremap_wc(mem->bus.offset, bus_size);
+#ifdef __x86_64__
+   else if (mem->bus.caching == ttm_cached)
+   addr = ioremap_cache(mem->bus.offset, bus_size);
+#endif
else
addr = ioremap(mem->bus.offset, bus_size);
if (!addr) {
@@ -372,6 +376,11 @@ static int ttm_bo_ioremap(struct ttm_buffer_object *bo,
if (mem->bus.caching == ttm_write_combined)
map->virtual = ioremap_wc(bo->mem.bus.offset + offset,
  size);
+#ifdef __x86_64__
+   else if (mem->bus.caching == ttm_cached)
+   map->virtual = ioremap_cache(bo->mem.bus.offset + 
offset,
+ size);
+#endif
else
map->virtual = ioremap(bo->mem.bus.offset + offset,
   size);
@@ -490,6 +499,11 @@ int ttm_bo_vmap(struct ttm_buffer_object *bo, struct 
dma_buf_map *map)
else if (mem->bus.caching == ttm_write_combined)
vaddr_iomem = ioremap_wc(mem->bus.offset,
 bo->base.size);
+   else if (mem->bus.caching == ttm_cached)
+#ifdef __x86_64__
+   vaddr_iomem = ioremap_cache(mem->bus.offset,
+ bo->base.size);
+#endif
else
vaddr_iomem = ioremap(mem->bus.offset, bo->base.size);
 
-- 
2.7.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

RE: [PATCH] drm/ttm: ioremap buffer according to TTM mem caching setting

[Zeng, Oak]

[AMD Official Use Only - Internal Distribution Only]

Hi Christian,

Can you explain why __iomem annotation is mandatory for amdgpu driver? If this 
is the case, we can't switch to memremap. The only fix seems to me is add a 
#ifdef __x86_64__ to the ioremap_cache codes.

Regards,
Oak

From: Christian König 
Sent: Wednesday, March 3, 2021 5:46 AM
To: Zeng, Oak ; amd-gfx@lists.freedesktop.org; 
dri-de...@lists.freedesktop.org; Daniel Vetter ; Dave Airlie 
; Thomas Hellström (Intel) ; 
dan.j.willi...@intel.com
Cc: kbuild-...@lists.01.org; Kuehling, Felix ; 
Kasiviswanathan, Harish ; Deucher, Alexander 
; Huang, JinHuiEric ; 
Koenig, Christian 
Subject: Re: [PATCH] drm/ttm: ioremap buffer according to TTM mem caching 
setting

Hi Oak,



config: parisc-randconfig-r012-20210302 (attached as .config)

It's not the Intel driver build which fails here, but the build bot is just 
hosted by Intel.

The problem is that the parisc architecture doesn't defines the ioremap_cache() 
function.

I've looked at using memremap() instead of ioremap_cache(). The problem is that 
we do support architectures with the TTM as well as amndgpu code where the 
__iomem annotation is mandatory and correct.

Regards,
Christian.
Am 02.03.21 um 23:45 schrieb Zeng, Oak:

[AMD Official Use Only - Internal Distribution Only]

Hi Daniel, Thomas, Dan,

Does below message mean the calling ioremap_cache failed intel's driver build? 
I can see both ioremap_cache and ioremap_wc are defined in 
arch/x86/mm/ioremap.c - why ioremap_wc doesn't break intel driver's build?

Are we supposed to use memremap (offset, size, MEMREMAP_WB) to replace 
ioremap_cache? When I read here 
https://lwn.net/Articles/653585/
 I felt that ioremap_cache returns an address annotated with _iomem while 
memremap returns an address without __iomem annotation. In our use case, GPU 
memory is treated as UEFI SPM (specific purpose memory). I am not very sure 
whether memremap (thus no __iomem annotation) is the right thing to do. What I 
am sure is, we have tested ioremap_cache and it works fine on AMD system.

I will send out a test patch replacing ioremap_cache with ioremap_wc, to 
trigger Intel build robot to see whether it fails Intel build. I suppose it 
will not fail Intel build.

Regards,
Oak

From: Christian König 

Sent: Tuesday, March 2, 2021 6:31 AM
To: amd-gfx@lists.freedesktop.org; 
dri-de...@lists.freedesktop.org; Daniel 
Vetter ; Dave Airlie 
; Thomas Hellström (Intel) 

Cc: Zeng, Oak ; 
kbuild-...@lists.01.org; Kuehling, Felix 
; Kasiviswanathan, 
Harish ; 
Deucher, Alexander 
; Huang, 
JinHuiEric ; Koenig, 
Christian 
Subject: Re: [PATCH] drm/ttm: ioremap buffer according to TTM mem caching 
setting

Hi guys,

adding the usual suspects direct. Does anybody of hand know how to check if an 
architecture supports ioremap_cache()?

For now we only need this on X86, but I would feel better if we don't use an 
#ifdef here.

Regards,
Christian.
Am 02.03.21 um 05:12 schrieb kernel test robot:

Hi Oak,



Thank you for the patch! Yet something to improve:



[auto build test ERROR on drm-intel/for-linux-next]

[also build test ERROR on drm-tip/drm-tip linus/master v5.12-rc1 next-20210302]

[cannot apply to tegra-drm/drm/tegra/for-next drm-exynos/exynos-drm-next 
drm/drm-next]

[If your patch is applied to the wrong git tree, kindly drop us a note.

And when submitting patch, we suggest to use '--base' as documented in

https://git-scm.com/docs/git-format-patch]



url:
https://github.com/0day-ci/linux/commits/Oak-Zeng/drm-ttm-ioremap-buffer-according-to-TTM-mem-caching-setting/20210302-064500

Re: [PATCH 3/6] amd/display: fail on cursor plane without an underlying plane

[Daniel Vetter]

On Wed, Mar 3, 2021 at 5:53 PM Michel Dänzer  wrote:
>
> On 2021-02-19 7:58 p.m., Simon Ser wrote:
> > Make sure there's an underlying pipe that can be used for the
> > cursor.
> >
> > Signed-off-by: Simon Ser 
> > Cc: Alex Deucher 
> > Cc: Harry Wentland 
> > Cc: Nicholas Kazlauskas 
> > ---
> >   drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 7 ++-
> >   1 file changed, 6 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
> > b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > index acbe1537e7cf..a5d6010405bf 100644
> > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > @@ -9226,9 +9226,14 @@ static int dm_check_crtc_cursor(struct 
> > drm_atomic_state *state,
> >   }
> >
> >   new_cursor_state = drm_atomic_get_new_plane_state(state, 
> > crtc->cursor);
> > - if (!new_cursor_state || !new_underlying_state || 
> > !new_cursor_state->fb)
> > + if (!new_cursor_state || !new_cursor_state->fb)
> >   return 0;
> >
> > + if (!new_underlying_state || !new_underlying_state->fb) {
> > + drm_dbg_atomic(crtc->dev, "Cursor plane can't be enabled 
> > without underlying plane\n");
> > + return -EINVAL;
> > + }
> > +
> >   cursor_scale_w = new_cursor_state->crtc_w * 1000 /
> >(new_cursor_state->src_w >> 16);
> >   cursor_scale_h = new_cursor_state->crtc_h * 1000 /
> >
>
> Houston, we have a problem I'm afraid. Adding Daniel.
>
>
> If the primary plane is enabled with a format which isn't compatible with the 
> HW cursor, and no overlay plane is enabled, the same issues as described in 
> b836a274b797 "drm/amdgpu/dc: Require primary plane to be enabled whenever the 
> CRTC is" can again occur:
>
>
> * The legacy cursor ioctl fails with EINVAL for a non-0 cursor FB ID
>
>(which enables the cursor plane).
>
> * If the cursor plane is enabled (e.g. using the legacy cursor ioctl
>during DPMS off), changing the legacy DPMS property
>   value from off to
>on fails with EINVAL.

atomic_check should still be run when the crtc is off, so the legacy
cursor ioctl should fail when dpms off in this case already. And then
the dpms on call should still succeed.

atomic_check should never have different state checks depending upon
crtc_state->active.

> Moreover, in the same scenario plus an overlay plane enabled with a HW cursor 
> compatible format, if the FB bound to the overlay plane is destroyed, the 
> common DRM code will attempt to disable the overlay plane, but 
> dm_check_crtc_cursor will reject that now. I can't remember exactly what the 
> result is, but AFAIR it's not pretty.

CRTC gets disabled instead. That's why we went with the "always
require primary plane" hack. I think the only solution here would be
to enable the primary plane (but not in userspace-visible state, so
this needs to be done in the dc derived state objects only) that scans
out black any time we're in such a situation with cursor with no
planes. At least assuming I'm understanding the hw constraints
correctly here. Otherwise I'm not really seeing how this would work
otherwise for userspace without some big surprises.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH][next] drm/radeon/si_dpm: Replace one-element array with flexible-array in struct SISLANDS_SMC_SWSTATE

[Gustavo A. R. Silva]

There is a regular need in the kernel to provide a way to declare having
a dynamically sized set of trailing elements in a structure. Kernel code
should always use “flexible array members”[1] for these cases. The older
style of one-element or zero-length arrays should no longer be used[2].

Refactor the code according to the use of a flexible-array member in
struct SISLANDS_SMC_SWSTATE, instead of a one-element array, and use
the struct_size() helper to calculate the size for the allocation.

Also, this helps with the ongoing efforts to enable -Warray-bounds by
fixing the following warnings:

drivers/gpu/drm/radeon/si_dpm.c: In function ‘si_convert_power_state_to_smc’:
drivers/gpu/drm/radeon/si_dpm.c:2350:20: warning: array subscript 1 is above 
array bounds of ‘SISLANDS_SMC_HW_PERFORMANCE_LEVEL[1]’ {aka ‘struct 
SISLANDS_SMC_HW_PERFORMANCE_LEVEL[1]’} [-Warray-bounds]
 2350 |   smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP 
* (max_sclk - min_sclk)) / max_sclk);
  |   ~^~~
drivers/gpu/drm/radeon/si_dpm.c:2351:20: warning: array subscript 1 is above 
array bounds of ‘SISLANDS_SMC_HW_PERFORMANCE_LEVEL[1]’ {aka ‘struct 
SISLANDS_SMC_HW_PERFORMANCE_LEVEL[1]’} [-Warray-bounds]
 2351 |   smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC;
  |   ~^~~
drivers/gpu/drm/radeon/si_dpm.c:2352:20: warning: array subscript 1 is above 
array bounds of ‘SISLANDS_SMC_HW_PERFORMANCE_LEVEL[1]’ {aka ‘struct 
SISLANDS_SMC_HW_PERFORMANCE_LEVEL[1]’} [-Warray-bounds]
 2352 |   smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC;
  |   ~^~~
drivers/gpu/drm/radeon/si_dpm.c:2353:20: warning: array subscript 1 is above 
array bounds of ‘SISLANDS_SMC_HW_PERFORMANCE_LEVEL[1]’ {aka ‘struct 
SISLANDS_SMC_HW_PERFORMANCE_LEVEL[1]’} [-Warray-bounds]
 2353 |   smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC;
  |   ~^~~
drivers/gpu/drm/radeon/si_dpm.c:2354:20: warning: array subscript 1 is above 
array bounds of ‘SISLANDS_SMC_HW_PERFORMANCE_LEVEL[1]’ {aka ‘struct 
SISLANDS_SMC_HW_PERFORMANCE_LEVEL[1]’} [-Warray-bounds]
 2354 |   smc_state->levels[i].dpm2.PwrEfficiencyRatio = 
cpu_to_be16(pwr_efficiency_ratio);
  |   ~^~~
drivers/gpu/drm/radeon/si_dpm.c:5105:20: warning: array subscript 1 is above 
array bounds of ‘SISLANDS_SMC_HW_PERFORMANCE_LEVEL[1]’ {aka ‘struct 
SISLANDS_SMC_HW_PERFORMANCE_LEVEL[1]’} [-Warray-bounds]
 5105 |   smc_state->levels[i + 1].aT = cpu_to_be32(a_t);
  |   ~^~~

[1] https://en.wikipedia.org/wiki/Flexible_array_member
[2] 
https://www.kernel.org/doc/html/v5.9/process/deprecated.html#zero-length-and-one-element-arrays

Link: https://github.com/KSPP/linux/issues/79
Link: https://github.com/KSPP/linux/issues/109
Build-tested-by: kernel test robot 
Link: https://lore.kernel.org/lkml/603f9a8f.adlrpmfzzsapzvyq%25...@intel.com/
Signed-off-by: Gustavo A. R. Silva 
---
 drivers/gpu/drm/radeon/si_dpm.c   |  5 ++---
 drivers/gpu/drm/radeon/sislands_smc.h | 10 +-
 2 files changed, 7 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/radeon/si_dpm.c b/drivers/gpu/drm/radeon/si_dpm.c
index 91bfc4762767..918609551804 100644
--- a/drivers/gpu/drm/radeon/si_dpm.c
+++ b/drivers/gpu/drm/radeon/si_dpm.c
@@ -5250,10 +5250,9 @@ static int si_upload_sw_state(struct radeon_device *rdev,
int ret;
u32 address = si_pi->state_table_start +
offsetof(SISLANDS_SMC_STATETABLE, driverState);
-   u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) +
-   ((new_state->performance_level_count - 1) *
-sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL));
SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState;
+   size_t state_size = struct_size(smc_state, levels,
+   new_state->performance_level_count);
 
memset(smc_state, 0, state_size);
 
diff --git a/drivers/gpu/drm/radeon/sislands_smc.h 
b/drivers/gpu/drm/radeon/sislands_smc.h
index 966e3a556011..fbd6589bdab9 100644
--- a/drivers/gpu/drm/radeon/sislands_smc.h
+++ b/drivers/gpu/drm/radeon/sislands_smc.h
@@ -182,11 +182,11 @@ typedef struct SISLANDS_SMC_HW_PERFORMANCE_LEVEL 
SISLANDS_SMC_HW_PERFORMANCE_LEV
 
 struct SISLANDS_SMC_SWSTATE
 {
-uint8_t flags;
-uint8_t levelCount;
-uint8_t padding2;
-uint8_t padding3;
-SISLANDS_SMC_HW_PERFORMANCE_LEVEL   levels[1];
+   uint8_t flags;
+   uint8_t levelCount;
+   uint8_t padding2;
+   uint8_t padding3;
+   SISLANDS_SMC_HW_PERFORMANCE_LEVEL   levels[];
 };
 
 typedef struct SISLANDS_SMC_SWSTATE SISLANDS_SMC_SWSTATE;
-- 
2.27.0

_

Re: [PATCH 3/6] amd/display: fail on cursor plane without an underlying plane

[Michel Dänzer]

On 2021-02-19 7:58 p.m., Simon Ser wrote:

Make sure there's an underlying pipe that can be used for the
cursor.

Signed-off-by: Simon Ser 
Cc: Alex Deucher 
Cc: Harry Wentland 
Cc: Nicholas Kazlauskas 
---
  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 7 ++-
  1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index acbe1537e7cf..a5d6010405bf 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -9226,9 +9226,14 @@ static int dm_check_crtc_cursor(struct drm_atomic_state 
*state,
}
  
  	new_cursor_state = drm_atomic_get_new_plane_state(state, crtc->cursor);

-   if (!new_cursor_state || !new_underlying_state || !new_cursor_state->fb)
+   if (!new_cursor_state || !new_cursor_state->fb)
return 0;
  
+	if (!new_underlying_state || !new_underlying_state->fb) {

+   drm_dbg_atomic(crtc->dev, "Cursor plane can't be enabled without 
underlying plane\n");
+   return -EINVAL;
+   }
+
cursor_scale_w = new_cursor_state->crtc_w * 1000 /
 (new_cursor_state->src_w >> 16);
cursor_scale_h = new_cursor_state->crtc_h * 1000 /



Houston, we have a problem I'm afraid. Adding Daniel.


If the primary plane is enabled with a format which isn't compatible with the HW cursor, 
and no overlay plane is enabled, the same issues as described in b836a274b797 
"drm/amdgpu/dc: Require primary plane to be enabled whenever the CRTC is" can 
again occur:


* The legacy cursor ioctl fails with EINVAL for a non-0 cursor FB ID

  (which enables the cursor plane).

* If the cursor plane is enabled (e.g. using the legacy cursor ioctl
  during DPMS off), changing the legacy DPMS property
 value from off to
  on fails with EINVAL.


Moreover, in the same scenario plus an overlay plane enabled with a HW cursor 
compatible format, if the FB bound to the overlay plane is destroyed, the 
common DRM code will attempt to disable the overlay plane, but 
dm_check_crtc_cursor will reject that now. I can't remember exactly what the 
result is, but AFAIR it's not pretty.


--
Earthling Michel Dänzer   |   https://redhat.com
Libre software enthusiast | Mesa and X developer
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

RE: [PATCH 1/1] drm/amdkfd: Use a new capability bit for SRAM ECC

[Russell, Kent]

[AMD Public Use]

Reviewed-by: Kent Russell 

> -Original Message-
> From: amd-gfx  On Behalf Of Felix 
> Kuehling
> Sent: Friday, February 26, 2021 5:46 PM
> To: amd-gfx@lists.freedesktop.org
> Subject: [PATCH 1/1] drm/amdkfd: Use a new capability bit for SRAM ECC
> 
> Existing, buggy user mode breaks when SRAM ECC is correctly reported as
> "enabled". To avoid breaking existing user mode, deprecate that bit and
> leave it as 0. Define a new bit to report the actual SRAM ECC mode that
> new, correct user mode can use in the future.
> 
> Fixes: 7ec177bdcfc1 ("drm/amdkfd: fix set kfd node ras properties value")
> Signed-off-by: Felix Kuehling 
> ---
>  drivers/gpu/drm/amd/amdkfd/kfd_topology.h | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h
> b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h
> index 416fd910e12e..b8b68087bd7a 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h
> @@ -47,13 +47,14 @@
>  #define HSA_CAP_DOORBELL_TYPE_2_00x2
>  #define HSA_CAP_AQL_QUEUE_DOUBLE_MAP 0x4000
> 
> -#define HSA_CAP_SRAM_EDCSUPPORTED0x0008
> +#define HSA_CAP_RESERVED_WAS_SRAM_EDCSUPPORTED   0x0008 /* Old buggy
> user mode depends on this being 0 */
>  #define HSA_CAP_MEM_EDCSUPPORTED 0x0010
>  #define HSA_CAP_RASEVENTNOTIFY   0x0020
>  #define HSA_CAP_ASIC_REVISION_MASK   0x03c0
>  #define HSA_CAP_ASIC_REVISION_SHIFT  22
> +#define HSA_CAP_SRAM_EDCSUPPORTED0x0400
> 
> -#define HSA_CAP_RESERVED 0xfc078000
> +#define HSA_CAP_RESERVED 0xf80f8000
> 
>  struct kfd_node_properties {
>   uint64_t hive_id;
> --
> 2.30.0
> 
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.or
> g%2Fmailman%2Flistinfo%2Famd-
> gfx&data=04%7C01%7Ckent.russell%40amd.com%7Cb8d46efc3f554cef4f7308d8daa85
> 3bb%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637499763789222071%7CUnk
> nown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXV
> CI6Mn0%3D%7C1000&sdata=ZhBBLDSK21I9o%2F1wsoFpWUlPtiezJ2rHHmIvJ51lsT4%3
> D&reserved=0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 10/53] drm/amd/display/dc/dce/dce_aux: Remove duplicate line causing 'field overwritten' issue

[Alex Deucher]

On Wed, Mar 3, 2021 at 8:44 AM Lee Jones  wrote:
>
> Fixes the following W=1 kernel build warning(s):
>
>  In file included from 
> drivers/gpu/drm/amd/amdgpu/../display/dc/dce112/dce112_resource.c:59:
>  
> drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dce/dce_11_2_sh_mask.h:10014:58:
>  warning: initialized field overwritten [-Woverride-init]
>  drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.h:214:16: note: in 
> expansion of macro ‘AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT’
>  drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.h:127:2: note: in 
> expansion of macro ‘AUX_SF’
>  drivers/gpu/drm/amd/amdgpu/../display/dc/dce112/dce112_resource.c:177:2: 
> note: in expansion of macro ‘DCE_AUX_MASK_SH_LIST’
>  
> drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dce/dce_11_2_sh_mask.h:10014:58:
>  note: (near initialization for ‘aux_shift.AUX_SW_AUTOINCREMENT_DISABLE’)
>  drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.h:214:16: note: in 
> expansion of macro ‘AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT’
>  drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.h:127:2: note: in 
> expansion of macro ‘AUX_SF’
>  drivers/gpu/drm/amd/amdgpu/../display/dc/dce112/dce112_resource.c:177:2: 
> note: in expansion of macro ‘DCE_AUX_MASK_SH_LIST’
>  
> drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dce/dce_11_2_sh_mask.h:10013:56:
>  warning: initialized field overwritten [-Woverride-init]
>  drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.h:214:16: note: in 
> expansion of macro ‘AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK’
>  drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.h:127:2: note: in 
> expansion of macro ‘AUX_SF’
>  drivers/gpu/drm/amd/amdgpu/../display/dc/dce112/dce112_resource.c:181:2: 
> note: in expansion of macro ‘DCE_AUX_MASK_SH_LIST’
>  
> drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dce/dce_11_2_sh_mask.h:10013:56:
>  note: (near initialization for ‘aux_mask.AUX_SW_AUTOINCREMENT_DISABLE’)
>  drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.h:214:16: note: in 
> expansion of macro ‘AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK’
>  drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.h:127:2: note: in 
> expansion of macro ‘AUX_SF’
>
> Cc: Harry Wentland 
> Cc: Leo Li 
> Cc: Alex Deucher 
> Cc: "Christian König" 
> Cc: David Airlie 
> Cc: Daniel Vetter 
> Cc: amd-gfx@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org
> Signed-off-by: Lee Jones 

Applied.  Thanks!

Alex

> ---
>  drivers/gpu/drm/amd/display/dc/dce/dce_aux.h | 1 -
>  1 file changed, 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h 
> b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
> index 775e24926380e..566b1bddd8cc6 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
> +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
> @@ -100,7 +100,6 @@ struct dce110_aux_registers {
> AUX_SF(AUX_SW_CONTROL, AUX_SW_GO, mask_sh),\
> AUX_SF(AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\
> AUX_SF(AUX_SW_DATA, AUX_SW_DATA_RW, mask_sh),\
> -   AUX_SF(AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\
> AUX_SF(AUX_SW_DATA, AUX_SW_INDEX, mask_sh),\
> AUX_SF(AUX_SW_DATA, AUX_SW_DATA, mask_sh),\
> AUX_SF(AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT, mask_sh),\
> --
> 2.27.0
>
> ___
> dri-devel mailing list
> dri-de...@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 07/53] drm/amd/display/dc/bios/command_table: Remove unused variable and associated comment

[Alex Deucher]

On Wed, Mar 3, 2021 at 8:43 AM Lee Jones  wrote:
>
> Fixes the following W=1 kernel build warning(s):
>
>  drivers/gpu/drm/amd/amdgpu/../display/dc/bios/command_table.c: In function 
> ‘adjust_display_pll_v2’:
>  drivers/gpu/drm/amd/amdgpu/../display/dc/bios/command_table.c:1462:11: 
> warning: unused variable ‘pixel_clock_10KHz_in’ [-Wunused-variable]
>
> Cc: Harry Wentland 
> Cc: Leo Li 
> Cc: Alex Deucher 
> Cc: "Christian König" 
> Cc: David Airlie 
> Cc: Daniel Vetter 
> Cc: Lee Jones 
> Cc: amd-gfx@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org
> Signed-off-by: Lee Jones 

Same comment as patch 4.


Alex

> ---
>  drivers/gpu/drm/amd/display/dc/bios/command_table.c | 4 
>  1 file changed, 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table.c 
> b/drivers/gpu/drm/amd/display/dc/bios/command_table.c
> index 9d3bc3a073821..e879ceb0c49ed 100644
> --- a/drivers/gpu/drm/amd/display/dc/bios/command_table.c
> +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table.c
> @@ -1518,10 +1518,6 @@ static enum bp_result adjust_display_pll_v2(
>  {
> enum bp_result result = BP_RESULT_FAILURE;
>
> -   /* We need to convert from KHz units into 10KHz units and then convert
> -* output pixel clock back 10KHz-->KHz */
> -   uint32_t pixel_clock_10KHz_in = bp_params->pixel_clock / 10;
> -
> bp->cmd_helper->encoder_id_to_atom(
> 
> dal_graphics_object_id_get_encoder_id(bp_params->encoder_object_id));
> bp->cmd_helper->encoder_mode_bp_to_atom(bp_params->signal_type, 
> false);
> --
> 2.27.0
>
> ___
> dri-devel mailing list
> dri-de...@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 04/53] drm/amd/display/dc/bios/command_table: Remove unused variable

[Alex Deucher]

On Wed, Mar 3, 2021 at 8:43 AM Lee Jones  wrote:
>
> None of the surrounding code was removed just in case even a small
> fraction of it was functional.
>
> Fixes the following W=1 kernel build warning(s):
>
>  drivers/gpu/drm/amd/amdgpu/../display/dc/bios/command_table.c: In function 
> ‘adjust_display_pll_v2’:
>  drivers/gpu/drm/amd/amdgpu/../display/dc/bios/command_table.c:1459:35: 
> warning: variable ‘params’ set but not used [-Wunused-but-set-variable]
>
> Cc: Harry Wentland 
> Cc: Leo Li 
> Cc: Alex Deucher 
> Cc: "Christian König" 
> Cc: David Airlie 
> Cc: Daniel Vetter 
> Cc: Qinglang Miao 
> Cc: amd-gfx@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org
> Signed-off-by: Lee Jones 

This function should be calling the atom cmd table with the
parameters.  Just sent a patch to fix this:
https://patchwork.freedesktop.org/patch/422833/

Alex

> ---
>  drivers/gpu/drm/amd/display/dc/bios/command_table.c | 12 +++-
>  1 file changed, 3 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table.c 
> b/drivers/gpu/drm/amd/display/dc/bios/command_table.c
> index afc10b954ffa7..9d3bc3a073821 100644
> --- a/drivers/gpu/drm/amd/display/dc/bios/command_table.c
> +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table.c
> @@ -1517,20 +1517,14 @@ static enum bp_result adjust_display_pll_v2(
> struct bp_adjust_pixel_clock_parameters *bp_params)
>  {
> enum bp_result result = BP_RESULT_FAILURE;
> -   ADJUST_DISPLAY_PLL_PS_ALLOCATION params = { 0 };
>
> /* We need to convert from KHz units into 10KHz units and then convert
>  * output pixel clock back 10KHz-->KHz */
> uint32_t pixel_clock_10KHz_in = bp_params->pixel_clock / 10;
>
> -   params.usPixelClock = cpu_to_le16((uint16_t)(pixel_clock_10KHz_in));
> -   params.ucTransmitterID =
> -   bp->cmd_helper->encoder_id_to_atom(
> -   dal_graphics_object_id_get_encoder_id(
> -   
> bp_params->encoder_object_id));
> -   params.ucEncodeMode =
> -   (uint8_t)bp->cmd_helper->encoder_mode_bp_to_atom(
> -   bp_params->signal_type, false);
> +   bp->cmd_helper->encoder_id_to_atom(
> +   
> dal_graphics_object_id_get_encoder_id(bp_params->encoder_object_id));
> +   bp->cmd_helper->encoder_mode_bp_to_atom(bp_params->signal_type, 
> false);
> return result;
>  }
>
> --
> 2.27.0
>
> ___
> dri-devel mailing list
> dri-de...@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH] drm/amdgpu/dc: fill in missing call to atom cmd table for pll adjust v2

[Alex Deucher]

We set up the parameters, but never called the atom table.

Signed-off-by: Alex Deucher 
---
 .../drm/amd/display/dc/bios/command_table.c   | 21 +++
 1 file changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table.c 
b/drivers/gpu/drm/amd/display/dc/bios/command_table.c
index afc10b954ffa..ad13e4e36d77 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table.c
@@ -1531,6 +1531,27 @@ static enum bp_result adjust_display_pll_v2(
params.ucEncodeMode =
(uint8_t)bp->cmd_helper->encoder_mode_bp_to_atom(
bp_params->signal_type, false);
+
+   if (EXEC_BIOS_CMD_TABLE(AdjustDisplayPll, params)) {
+   /* Convert output pixel clock back 10KHz-->KHz: multiply
+* original pixel clock in KHz by ratio
+* [output pxlClk/input pxlClk] */
+   uint64_t pixel_clk_10_khz_out =
+   (uint64_t)le16_to_cpu(params.usPixelClock);
+   uint64_t pixel_clk = (uint64_t)bp_params->pixel_clock;
+
+   if (pixel_clock_10KHz_in != 0) {
+   bp_params->adjusted_pixel_clock =
+   div_u64(pixel_clk * 
pixel_clk_10_khz_out,
+   pixel_clock_10KHz_in);
+   } else {
+   bp_params->adjusted_pixel_clock = 0;
+   BREAK_TO_DEBUGGER();
+   }
+
+   result = BP_RESULT_OK;
+   }
+
return result;
 }
 
-- 
2.29.2

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm/amd/display: Fix off by one in hdmi_14_process_transaction()

[Alex Deucher]

Applied.  Thanks!

Alex

On Tue, Mar 2, 2021 at 2:26 PM Lakha, Bhawanpreet
 wrote:
>
> [AMD Official Use Only - Internal Distribution Only]
>
>
> Thanks
>
> Reviewed-by: Bhawanpreet Lakha 
> 
> From: Dan Carpenter 
> Sent: March 2, 2021 6:15 AM
> To: Wentland, Harry ; Lakha, Bhawanpreet 
> 
> Cc: Li, Sun peng (Leo) ; Deucher, Alexander 
> ; Koenig, Christian ; 
> David Airlie ; Daniel Vetter ; Dan 
> Carpenter ; Lakha, Bhawanpreet 
> ; Siqueira, Rodrigo ; 
> Liu, Wenjing ; amd-gfx@lists.freedesktop.org 
> ; dri-de...@lists.freedesktop.org 
> ; kernel-janit...@vger.kernel.org 
> 
> Subject: [PATCH] drm/amd/display: Fix off by one in 
> hdmi_14_process_transaction()
>
> The hdcp_i2c_offsets[] array did not have an entry for
> HDCP_MESSAGE_ID_WRITE_CONTENT_STREAM_TYPE so it led to an off by one
> read overflow.  I added an entry and copied the 0x0 value for the offset
> from similar code in drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c.
>
> I also declared several of these arrays as having HDCP_MESSAGE_ID_MAX
> entries.  This doesn't change the code, but it's just a belt and
> suspenders approach to try future proof the code.
>
> Fixes: 4c283fdac08a ("drm/amd/display: Add HDCP module")
> Signed-off-by: Dan Carpenter 
> ---
> From static analysis, as mentioned in the commit message the offset
> is basically an educated guess.
>
> I reported this bug on Apr 16, 2020 but I guess we lost take of it.
>
>  drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c | 9 +
>  1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c 
> b/drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c
> index 5e384a8a83dc..51855a2624cf 100644
> --- a/drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c
> +++ b/drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c
> @@ -39,7 +39,7 @@
>  #define HDCP14_KSV_SIZE 5
>  #define HDCP14_MAX_KSV_FIFO_SIZE 127*HDCP14_KSV_SIZE
>
> -static const bool hdcp_cmd_is_read[] = {
> +static const bool hdcp_cmd_is_read[HDCP_MESSAGE_ID_MAX] = {
>  [HDCP_MESSAGE_ID_READ_BKSV] = true,
>  [HDCP_MESSAGE_ID_READ_RI_R0] = true,
>  [HDCP_MESSAGE_ID_READ_PJ] = true,
> @@ -75,7 +75,7 @@ static const bool hdcp_cmd_is_read[] = {
>  [HDCP_MESSAGE_ID_WRITE_CONTENT_STREAM_TYPE] = false
>  };
>
> -static const uint8_t hdcp_i2c_offsets[] = {
> +static const uint8_t hdcp_i2c_offsets[HDCP_MESSAGE_ID_MAX] = {
>  [HDCP_MESSAGE_ID_READ_BKSV] = 0x0,
>  [HDCP_MESSAGE_ID_READ_RI_R0] = 0x8,
>  [HDCP_MESSAGE_ID_READ_PJ] = 0xA,
> @@ -106,7 +106,8 @@ static const uint8_t hdcp_i2c_offsets[] = {
>  [HDCP_MESSAGE_ID_WRITE_REPEATER_AUTH_SEND_ACK] = 0x60,
>  [HDCP_MESSAGE_ID_WRITE_REPEATER_AUTH_STREAM_MANAGE] = 0x60,
>  [HDCP_MESSAGE_ID_READ_REPEATER_AUTH_STREAM_READY] = 0x80,
> -   [HDCP_MESSAGE_ID_READ_RXSTATUS] = 0x70
> +   [HDCP_MESSAGE_ID_READ_RXSTATUS] = 0x70,
> +   [HDCP_MESSAGE_ID_WRITE_CONTENT_STREAM_TYPE] = 0x0,
>  };
>
>  struct protection_properties {
> @@ -184,7 +185,7 @@ static const struct protection_properties 
> hdmi_14_protection = {
>  .process_transaction = hdmi_14_process_transaction
>  };
>
> -static const uint32_t hdcp_dpcd_addrs[] = {
> +static const uint32_t hdcp_dpcd_addrs[HDCP_MESSAGE_ID_MAX] = {
>  [HDCP_MESSAGE_ID_READ_BKSV] = 0x68000,
>  [HDCP_MESSAGE_ID_READ_RI_R0] = 0x68005,
>  [HDCP_MESSAGE_ID_READ_PJ] = 0x,
> --
> 2.30.1
>
> ___
> dri-devel mailing list
> dri-de...@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm/radeon: fix copy of uninitialized variable back to userspace

[Alex Deucher]

Applied.  Thanks!

Alex

On Wed, Mar 3, 2021 at 2:42 AM Christian König  wrote:
>
> Am 03.03.21 um 01:27 schrieb Colin King:
> > From: Colin Ian King 
> >
> > Currently the ioctl command RADEON_INFO_SI_BACKEND_ENABLED_MASK can
> > copy back uninitialised data in value_tmp that pointer *value points
> > to. This can occur when rdev->family is less than CHIP_BONAIRE and
> > less than CHIP_TAHITI.  Fix this by adding in a missing -EINVAL
> > so that no invalid value is copied back to userspace.
> >
> > Addresses-Coverity: ("Uninitialized scalar variable)
> > Cc: sta...@vger.kernel.org # 3.13+
> > Fixes: 439a1cfffe2c ("drm/radeon: expose render backend mask to the 
> > userspace")
> > Signed-off-by: Colin Ian King 
>
> Reviewed-by: Christian König 
>
> Let's hope that this doesn't break UAPI.
>
> Christian.
>
> > ---
> >   drivers/gpu/drm/radeon/radeon_kms.c | 1 +
> >   1 file changed, 1 insertion(+)
> >
> > diff --git a/drivers/gpu/drm/radeon/radeon_kms.c 
> > b/drivers/gpu/drm/radeon/radeon_kms.c
> > index 2479d6ab7a36..58876bb4ef2a 100644
> > --- a/drivers/gpu/drm/radeon/radeon_kms.c
> > +++ b/drivers/gpu/drm/radeon/radeon_kms.c
> > @@ -518,6 +518,7 @@ int radeon_info_ioctl(struct drm_device *dev, void 
> > *data, struct drm_file *filp)
> >   *value = rdev->config.si.backend_enable_mask;
> >   } else {
> >   DRM_DEBUG_KMS("BACKEND_ENABLED_MASK is si+ only!\n");
> > + return -EINVAL;
> >   }
> >   break;
> >   case RADEON_INFO_MAX_SCLK:
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH v3 0/3] Use kvmalloc_array for radeon and amdgpu CS chunks

[Alex Deucher]

Applied.  Thanks!

Alex

On Wed, Mar 3, 2021 at 6:30 AM Christian König  wrote:
>
> Reviewed-by: Christian König  for the entire
> series.
>
> Am 03.03.21 um 04:49 schrieb Chen Li:
> > When testing kernel with trinity, the kernel turned to tainted in that 
> > radeon CS require large memory and order is over MAX_ORDER.
> >
> > kvmalloc/kvmalloc_array should be used here in that it will fallback to 
> > vmalloc if necessary.
> >
> > Chen Li (3):
> >drm/radeon: Use kvmalloc for CS chunks
> >drm/amdgpu: Use kvmalloc for CS chunks
> >drm/amdgpu: correct DRM_ERROR for kvmalloc_array
> >
> > Changelog:
> >v1->v2:
> >  * also use kvmalloc in amdgpu
> >  * fix a DRM_ERROR message for kvmalloc_array.
> >v2->v3:
> >  * add missing kvfree for amdgpu CS
> >
> >   drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 14 +++---
> >   drivers/gpu/drm/radeon/radeon_cs.c |  8 
> >   2 files changed, 11 insertions(+), 11 deletions(-)
> >
> > --
> > 2.30.0
> >
> >
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm/amdgpu: Remove unnecessary conversion to bool

[Alex Deucher]

On Wed, Mar 3, 2021 at 4:18 AM Jiapeng Chong
 wrote:
>
> Fix the following coccicheck warnings:
>
> ./drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c:2252:40-45: WARNING: conversion
> to bool not needed here.
>
> Reported-by: Abaci Robot 
> Signed-off-by: Jiapeng Chong 

Applied.  Thanks!

Alex

> ---
>  drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 
> b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> index c8c22c1..00d3773 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> @@ -2249,7 +2249,7 @@ static int sdma_v4_0_set_powergating_state(void *handle,
> case CHIP_RAVEN:
> case CHIP_RENOIR:
> sdma_v4_1_update_power_gating(adev,
> -   state == AMD_PG_STATE_GATE ? true : false);
> +   state == AMD_PG_STATE_GATE);
> break;
> default:
> break;
> --
> 1.8.3.1
>
> ___
> dri-devel mailing list
> dri-de...@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH][next] drm/amd/display: remove redundant initialization of variable status

[Colin King]

From: Colin Ian King 

The variable status is being initialized with a value that is never read
and it is being updated later with a new value.  The initialization is
redundant and can be removed.

Addresses-Coverity: ("Unused value")
Signed-off-by: Colin Ian King 
---
 drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c 
b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
index 03741e170b61..15ed09b7a452 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
@@ -81,7 +81,7 @@ static void dmub_psr_get_state(struct dmub_psr *dmub, enum 
dc_psr_state *state)
 {
struct dmub_srv *srv = dmub->ctx->dmub_srv->dmub;
uint32_t raw_state;
-   enum dmub_status status = DMUB_STATUS_INVALID;
+   enum dmub_status status;
 
// Send gpint command and wait for ack
status = dmub_srv_send_gpint_command(srv, DMUB_GPINT__GET_PSR_STATE, 0, 
30);
-- 
2.30.0

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH] Revert "drm/amdgpu: Verify bo size can fit framebuffer size"

[Alex Deucher]

This reverts commit f9d2476012ddf26fab652ee0dff697260040924c.

This leads to a failure to init the framebuffer.

Signed-off-by: Alex Deucher 
Cc: Mark Yacoub 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 8 +++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c  | 3 +--
 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h| 1 -
 3 files changed, 4 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index 61684d543b8e..48cb33e5b382 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -872,14 +872,13 @@ static int amdgpu_display_get_fb_info(const struct 
amdgpu_framebuffer *amdgpu_fb
 
 int amdgpu_display_framebuffer_init(struct drm_device *dev,
struct amdgpu_framebuffer *rfb,
-   struct drm_file *file,
const struct drm_mode_fb_cmd2 *mode_cmd,
struct drm_gem_object *obj)
 {
int ret, i;
rfb->base.obj[0] = obj;
-   ret = drm_gem_fb_init_with_funcs(dev, &rfb->base, file, mode_cmd,
-&amdgpu_fb_funcs);
+   drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd);
+   ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs);
if (ret)
goto fail;
 
@@ -954,8 +953,7 @@ amdgpu_display_user_framebuffer_create(struct drm_device 
*dev,
return ERR_PTR(-ENOMEM);
}
 
-   ret = amdgpu_display_framebuffer_init(dev, amdgpu_fb, file_priv,
- mode_cmd, obj);
+   ret = amdgpu_display_framebuffer_init(dev, amdgpu_fb, mode_cmd, obj);
if (ret) {
kfree(amdgpu_fb);
drm_gem_object_put(obj);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
index 74aa80e11a80..51cd49c6f38f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
@@ -233,8 +233,7 @@ static int amdgpufb_create(struct drm_fb_helper *helper,
}
 
ret = amdgpu_display_framebuffer_init(adev_to_drm(adev), &rfbdev->rfb,
- helper->client.file, &mode_cmd,
- gobj);
+ &mode_cmd, gobj);
if (ret) {
DRM_ERROR("failed to initialize framebuffer %d\n", ret);
goto out;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
index 997b93674955..319cb19e1b99 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
@@ -604,7 +604,6 @@ int amdgpu_display_get_crtc_scanoutpos(struct drm_device 
*dev,
 
 int amdgpu_display_framebuffer_init(struct drm_device *dev,
struct amdgpu_framebuffer *rfb,
-   struct drm_file *file,
const struct drm_mode_fb_cmd2 *mode_cmd,
struct drm_gem_object *obj);
 
-- 
2.29.2

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: AMDGPU Linux 5.11.0 freezes (divide error)

[Alex Deucher]

On Wed, Mar 3, 2021 at 8:52 AM Jonas Zeiger  wrote:
>
> Hi all,
>
> I am experiencing random system freezes (about once per day) after updating 
> to Linux 5.11 (vanilla kernel).
>
> Only a manual power-cycle makes the system usable again afterwards.
>
> These freezes didn't occur on 5.10.x but I hadn't assigned "nohz_full=2-16" 
> and "cpuidle.governor=teo" back then.

Should be fixed with this patch I think:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=41401ac67791810dd880345962339aa1bedd3c0d

Alex

>
> Hardware:
>
> ThinkPad T14 (gen1)
> CPU: AMD Ryzen 7 PRO 4750U with Radeon Graphics
>
> Kernel cmdline:
>
> BOOT_IMAGE=/vmlinuz-5.11.0zlinux-svr-docker-wg root=/dev/nvme0n1p2 ro 
> nohz_full=2-16 cpuidle.governor=teo rootfstype=ext4 rootwait 
> ivrs_ioapic[4]=00:14.0 ivrs_ioapic[5]=00:00.2
>
> This is logged to the journal:
>
> kernel: divide error:  [#1] PREEMPT SMP
> kernel: CPU: 8 PID: 2914 Comm: Xorg Not tainted 5.11.0zlinux-svr-docker-wg #8
> kernel: Hardware name: LENOVO 20UD0013GE/20UD0013GE, BIOS R1BET58W(1.27 ) 
> 10/20/2020
> kernel: RIP: 0010:Calculate256BBlockSizes+0x50/0xc1 [amdgpu]
> kernel: Code: 83 ff 02 75 09 41 c7 00 04 00 00 00 eb 15 83 ff 08 75 09 41 c7 
> 00 10 00 00 00 eb 07 4>
> kernel: RSP: 0018:a35e815fb688 EFLAGS: 00010246
> kernel: RAX: 0100 RBX: 98afc1debaf8 RCX: 
> kernel: RDX:  RSI:  RDI: 0001
> kernel: RBP: 98afc1de2090 R08: 98afc1debab8 R09: 98afc1debad8
> kernel: R10: 0002 R11: 98afc1debb18 R12: 98a8d9ddd000
> kernel: R13:  R14: 98afc1de31c8 R15: 98afc1de2090
> kernel: FS:  7f41f3ff0a40() GS:98b35fa0() 
> knlGS:
> kernel: CS:  0010 DS:  ES:  CR0: 80050033
> kernel: CR2: 7f0486175000 CR3: 000116542000 CR4: 00350ee0
> kernel: Call Trace:
> kernel:  
> DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation+0xdb8/0x>
> kernel:  ? ModeSupportAndSystemConfiguration+0x77/0xe7 [amdgpu]
> kernel:  ? dcn_bw_ceil2+0x19/0x3b [amdgpu]
> kernel:  ? dml21_recalculate+0x59c/0x5b3 [amdgpu]
> kernel:  get_wm_urgent+0x9/0x13 [amdgpu]
> kernel:  dml21_rq_dlg_get_dlg_reg+0x6c/0x1804 [amdgpu]
> kernel:  ? dcn_bw_ceil2+0x19/0x3b [amdgpu]
> kernel:  ? 
> DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation+0x3e06>
> kernel:  dcn20_calculate_dlg_params+0x333/0x3af [amdgpu]
> kernel:  dcn21_validate_bandwidth+0x4cd/0x581 [amdgpu]
> kernel:  dc_validate_global_state+0x1a7/0x1c5 [amdgpu]
> kernel:  amdgpu_dm_atomic_check+0x84c/0xa00 [amdgpu]
> kernel:  ? __radix_tree_lookup+0x2a/0x91
> kernel:  drm_atomic_check_only+0x5bb/0x6b7
> kernel:  ? drm_mode_object_put+0x21/0x2d
> kernel:  ? drm_atomic_set_property+0x7b3/0x7c5
> kernel:  drm_atomic_commit+0xe/0x44
> kernel:  drm_mode_obj_set_property_ioctl+0x112/0x268
> kernel:  ? __fpu__restore_sig+0x21e/0x46d
> kernel:  ? drm_mode_obj_find_prop_id+0x23/0x23
> kernel:  drm_ioctl_kernel+0x7d/0xbc
> kernel:  drm_ioctl+0x1f2/0x2c9
> kernel:  ? drm_mode_obj_find_prop_id+0x23/0x23
> kernel:  ? rpm_resume+0x43e/0x450
> kernel:  amdgpu_drm_ioctl+0x45/0x71 [amdgpu]
> kernel:  vfs_ioctl+0x1a/0x28
> kernel:  __do_sys_ioctl+0x51/0x74
> kernel:  do_syscall_64+0x33/0x40
> kernel:  entry_SYSCALL_64_after_hwframe+0x44/0xa9
> kernel: RIP: 0033:0x7f41f445bcc7
> kernel: Code: 00 00 00 48 8b 05 c9 91 0c 00 64 c7 00 26 00 00 00 48 c7 c0 ff 
> ff ff ff c3 66 2e 0f 1>
> kernel: RSP: 002b:7ffd7b9f4db8 EFLAGS: 0246 ORIG_RAX: 0010
> kernel: RAX: ffda RBX: 7ffd7b9f4df0 RCX: 7f41f445bcc7
> kernel: RDX: 7ffd7b9f4df0 RSI: c01864ba RDI: 000f
> kernel: RBP: c01864ba R08: 0073 R09: 
> kernel: R10: 0fff R11: 0246 R12: 561f30685480
> kernel: R13: 000f R14:  R15: 0003
> kernel: Modules linked in: iwlmvm iwlwifi amdgpu drm_ttm_helper ttm mfd_core 
> gpu_sched r8169
> kernel: ---[ end trace 7e898fd18a4b26cd ]---
> kernel: [ cut here ]
> kernel: WARNING: CPU: 8 PID: 2914 at rcu_note_context_switch+0x3a/0x2d5
> kernel: Modules linked in: iwlmvm iwlwifi amdgpu drm_ttm_helper ttm mfd_core 
> gpu_sched r8169
> kernel: CPU: 8 PID: 2914 Comm: Xorg Tainted: G  D   
> 5.11.0zlinux-svr-docker-wg #8
> kernel: Hardware name: LENOVO 20UD0013GE/20UD0013GE, BIOS R1BET58W(1.27 ) 
> 10/20/2020
> kernel: RIP: 0010:rcu_note_context_switch+0x3a/0x2d5
> kernel: Code: 40 65 02 00 55 53 89 fb 65 4c 03 25 ff cb ed 68 48 8b 3d c8 af 
> b0 01 e8 3d cd ff ff 8>
> kernel: RSP: 0018:a35e815fb160 EFLAGS: 00010002
> kernel: RAX:  RBX:  RCX: 0002
> kernel: RDX: 0002 RSI: a35e815fb230 RDI: 9884fce6
> kernel: RBP: a35e815fb1c0 R08: 9884fce6 R09: 98a8

[PATCH v2] drm/amd/pm/swsmu: clean up user profile function

[Arunpravin]

Remove unnecessary comments, enable restore mode using
'|=' operator, fixes the alignment to improve the code
readability.

v2: Move all restoration flag check to bitwise '&' operator

Signed-off-by: Arunpravin 
---
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 34 ---
 1 file changed, 12 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c 
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index f5d9590f2178..a64228157ff6 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -315,35 +315,25 @@ static void smu_set_user_clk_dependencies(struct 
smu_context *smu, enum smu_clk_
if (smu->adev->in_suspend)
return;
 
-   /*
-* mclk, fclk and socclk are interdependent
-* on each other
-*/
if (clk == SMU_MCLK) {
-   /* reset clock dependency */
smu->user_dpm_profile.clk_dependency = 0;
-   /* set mclk dependent clocks(fclk and socclk) */
smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | 
BIT(SMU_SOCCLK);
} else if (clk == SMU_FCLK) {
-   /* give priority to mclk, if mclk dependent clocks are set */
+   /* MCLK takes precedence over FCLK */
if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | 
BIT(SMU_SOCCLK)))
return;
 
-   /* reset clock dependency */
smu->user_dpm_profile.clk_dependency = 0;
-   /* set fclk dependent clocks(mclk and socclk) */
smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | 
BIT(SMU_SOCCLK);
} else if (clk == SMU_SOCCLK) {
-   /* give priority to mclk, if mclk dependent clocks are set */
+   /* MCLK takes precedence over SOCCLK */
if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | 
BIT(SMU_SOCCLK)))
return;
 
-   /* reset clock dependency */
smu->user_dpm_profile.clk_dependency = 0;
-   /* set socclk dependent clocks(mclk and fclk) */
smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | 
BIT(SMU_FCLK);
} else
-   /* add clk dependencies here, if any */
+   /* Add clk dependencies here, if any */
return;
 }
 
@@ -367,7 +357,7 @@ static void smu_restore_dpm_user_profile(struct smu_context 
*smu)
return;
 
/* Enable restore flag */
-   smu->user_dpm_profile.flags = SMU_DPM_USER_PROFILE_RESTORE;
+   smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE;
 
/* set the user dpm power limit */
if (smu->user_dpm_profile.power_limit) {
@@ -390,8 +380,8 @@ static void smu_restore_dpm_user_profile(struct smu_context 
*smu)
ret = smu_force_smuclk_levels(smu, clk_type,

smu->user_dpm_profile.clk_mask[clk_type]);
if (ret)
-   dev_err(smu->adev->dev, "Failed to set 
clock type = %d\n",
-   clk_type);
+   dev_err(smu->adev->dev,
+   "Failed to set clock type = 
%d\n", clk_type);
}
}
}
@@ -1844,7 +1834,7 @@ static int smu_force_smuclk_levels(struct smu_context 
*smu,
 
if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) {
ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask);
-   if (!ret && smu->user_dpm_profile.flags != 
SMU_DPM_USER_PROFILE_RESTORE) {
+   if (!ret && !(smu->user_dpm_profile.flags & 
SMU_DPM_USER_PROFILE_RESTORE)) {
smu->user_dpm_profile.clk_mask[clk_type] = mask;
smu_set_user_clk_dependencies(smu, clk_type);
}
@@ -2141,7 +2131,7 @@ int smu_set_fan_speed_rpm(void *handle, uint32_t speed)
if (smu->ppt_funcs->set_fan_speed_percent) {
percent = speed * 100 / smu->fan_max_rpm;
ret = smu->ppt_funcs->set_fan_speed_percent(smu, percent);
-   if (!ret && smu->user_dpm_profile.flags != 
SMU_DPM_USER_PROFILE_RESTORE)
+   if (!ret && !(smu->user_dpm_profile.flags & 
SMU_DPM_USER_PROFILE_RESTORE))
smu->user_dpm_profile.fan_speed_percent = percent;
}
 
@@ -2212,7 +2202,7 @@ int smu_set_power_limit(void *handle, uint32_t limit)
 
if (smu->ppt_funcs->set_power_limit) {
ret = smu->ppt_funcs->set_power_limit(smu, limit);
-   if (!ret && smu->user_dpm_profile.flags != 
SMU_DPM_USER_PROFILE_RESTORE)
+   if (!ret && !(smu->user_dpm_profile.flags & 
SMU_DPM_USER_PROFILE_RESTORE))
smu->user_dpm_profile.power_limit = l

[PATCH 11/53] drm/amd/display/dc/dce80/dce80_resource: Make local functions static

[Lee Jones]

Fixes the following W=1 kernel build warning(s):

 drivers/gpu/drm/amd/amdgpu/../display/dc/dce80/dce80_resource.c:527:17: 
warning: no previous prototype for ‘dce80_aux_engine_create’ 
[-Wmissing-prototypes]
 drivers/gpu/drm/amd/amdgpu/../display/dc/dce80/dce80_resource.c:565:20: 
warning: no previous prototype for ‘dce80_i2c_hw_create’ [-Wmissing-prototypes]
 drivers/gpu/drm/amd/amdgpu/../display/dc/dce80/dce80_resource.c:581:20: 
warning: no previous prototype for ‘dce80_i2c_sw_create’ [-Wmissing-prototypes]
 drivers/gpu/drm/amd/amdgpu/../display/dc/dce80/dce80_resource.c:715:22: 
warning: no previous prototype for ‘dce80_link_encoder_create’ 
[-Wmissing-prototypes]
 drivers/gpu/drm/amd/amdgpu/../display/dc/dce80/dce80_resource.c:754:22: 
warning: no previous prototype for ‘dce80_clock_source_create’ 
[-Wmissing-prototypes]
 drivers/gpu/drm/amd/amdgpu/../display/dc/dce80/dce80_resource.c:778:6: 
warning: no previous prototype for ‘dce80_clock_source_destroy’ 
[-Wmissing-prototypes]
 drivers/gpu/drm/amd/amdgpu/../display/dc/dce80/dce80_resource.c:868:6: 
warning: no previous prototype for ‘dce80_validate_bandwidth’ 
[-Wmissing-prototypes]
 drivers/gpu/drm/amd/amdgpu/../display/dc/dce80/dce80_resource.c:913:16: 
warning: no previous prototype for ‘dce80_validate_global’ 
[-Wmissing-prototypes]

Cc: Harry Wentland 
Cc: Leo Li 
Cc: Alex Deucher 
Cc: "Christian König" 
Cc: David Airlie 
Cc: Daniel Vetter 
Cc: Anthony Koo 
Cc: amd-gfx@lists.freedesktop.org
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Lee Jones 
---
 .../drm/amd/display/dc/dce80/dce80_resource.c| 16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 
b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
index 612450f992782..725d92e40cd30 100644
--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
@@ -526,7 +526,7 @@ static struct output_pixel_processor *dce80_opp_create(
return &opp->base;
 }
 
-struct dce_aux *dce80_aux_engine_create(
+static struct dce_aux *dce80_aux_engine_create(
struct dc_context *ctx,
uint32_t inst)
 {
@@ -564,7 +564,7 @@ static const struct dce_i2c_mask i2c_masks = {
I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
 };
 
-struct dce_i2c_hw *dce80_i2c_hw_create(
+static struct dce_i2c_hw *dce80_i2c_hw_create(
struct dc_context *ctx,
uint32_t inst)
 {
@@ -580,7 +580,7 @@ struct dce_i2c_hw *dce80_i2c_hw_create(
return dce_i2c_hw;
 }
 
-struct dce_i2c_sw *dce80_i2c_sw_create(
+static struct dce_i2c_sw *dce80_i2c_sw_create(
struct dc_context *ctx)
 {
struct dce_i2c_sw *dce_i2c_sw =
@@ -714,7 +714,7 @@ static const struct encoder_feature_support 
link_enc_feature = {
.flags.bits.IS_TPS3_CAPABLE = true
 };
 
-struct link_encoder *dce80_link_encoder_create(
+static struct link_encoder *dce80_link_encoder_create(
const struct encoder_init_data *enc_init_data)
 {
struct dce110_link_encoder *enc110 =
@@ -753,7 +753,7 @@ static struct panel_cntl *dce80_panel_cntl_create(const 
struct panel_cntl_init_d
return &panel_cntl->base;
 }
 
-struct clock_source *dce80_clock_source_create(
+static struct clock_source *dce80_clock_source_create(
struct dc_context *ctx,
struct dc_bios *bios,
enum clock_source_id id,
@@ -777,7 +777,7 @@ struct clock_source *dce80_clock_source_create(
return NULL;
 }
 
-void dce80_clock_source_destroy(struct clock_source **clk_src)
+static void dce80_clock_source_destroy(struct clock_source **clk_src)
 {
kfree(TO_DCE110_CLK_SRC(*clk_src));
*clk_src = NULL;
@@ -867,7 +867,7 @@ static void dce80_resource_destruct(struct 
dce110_resource_pool *pool)
}
 }
 
-bool dce80_validate_bandwidth(
+static bool dce80_validate_bandwidth(
struct dc *dc,
struct dc_state *context,
bool fast_validate)
@@ -912,7 +912,7 @@ static bool dce80_validate_surface_sets(
return true;
 }
 
-enum dc_status dce80_validate_global(
+static enum dc_status dce80_validate_global(
struct dc *dc,
struct dc_state *context)
 {
-- 
2.27.0

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 09/53] drm/amd/display/dc/calcs/dce_calcs: Remove some large variables from the stack

[Lee Jones]

Fixes the following W=1 kernel build warning(s):

 drivers/gpu/drm/amd/amdgpu/../display/dc/calcs/dce_calcs.c: In function 
‘bw_calcs_init’:
 drivers/gpu/drm/amd/amdgpu/../display/dc/calcs/dce_calcs.c:2726:1: warning: 
the frame size of 1336 bytes is larger than 1024 bytes [-Wframe-larger-than=]

Cc: Harry Wentland 
Cc: Leo Li 
Cc: Alex Deucher 
Cc: "Christian König" 
Cc: David Airlie 
Cc: Daniel Vetter 
Cc: amd-gfx@lists.freedesktop.org
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Lee Jones 
---
 .../gpu/drm/amd/display/dc/calcs/dce_calcs.c  | 1122 +
 1 file changed, 567 insertions(+), 555 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 
b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
index 4f0474a3bbcad..53f5c170d9c97 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
@@ -2043,707 +2043,719 @@ void bw_calcs_init(struct bw_calcs_dceip *bw_dceip,
struct bw_calcs_vbios *bw_vbios,
struct hw_asic_id asic_id)
 {
-   struct bw_calcs_dceip dceip = { 0 };
-   struct bw_calcs_vbios vbios = { 0 };
+   struct bw_calcs_dceip *dceip;
+   struct bw_calcs_vbios *vbios;
 
enum bw_calcs_version version = bw_calcs_version_from_asic_id(asic_id);
 
-   dceip.version = version;
+   dceip = kzalloc(sizeof(dceip), GFP_KERNEL);
+   if (!dceip)
+   return;
+
+   vbios = kzalloc(sizeof(vbios), GFP_KERNEL);
+   if (!vbios) {
+   kfree(dceip);
+   return;
+   }
+
+   dceip->version = version;
 
switch (version) {
case BW_CALCS_VERSION_CARRIZO:
-   vbios.memory_type = bw_def_gddr5;
-   vbios.dram_channel_width_in_bits = 64;
-   vbios.number_of_dram_channels = asic_id.vram_width / 
vbios.dram_channel_width_in_bits;
-   vbios.number_of_dram_banks = 8;
-   vbios.high_yclk = bw_int_to_fixed(1600);
-   vbios.mid_yclk = bw_int_to_fixed(1600);
-   vbios.low_yclk = bw_frc_to_fixed(6, 100);
-   vbios.low_sclk = bw_int_to_fixed(200);
-   vbios.mid1_sclk = bw_int_to_fixed(300);
-   vbios.mid2_sclk = bw_int_to_fixed(300);
-   vbios.mid3_sclk = bw_int_to_fixed(300);
-   vbios.mid4_sclk = bw_int_to_fixed(300);
-   vbios.mid5_sclk = bw_int_to_fixed(300);
-   vbios.mid6_sclk = bw_int_to_fixed(300);
-   vbios.high_sclk = bw_frc_to_fixed(62609, 100);
-   vbios.low_voltage_max_dispclk = bw_int_to_fixed(352);
-   vbios.mid_voltage_max_dispclk = bw_int_to_fixed(467);
-   vbios.high_voltage_max_dispclk = bw_int_to_fixed(643);
-   vbios.low_voltage_max_phyclk = bw_int_to_fixed(540);
-   vbios.mid_voltage_max_phyclk = bw_int_to_fixed(810);
-   vbios.high_voltage_max_phyclk = bw_int_to_fixed(810);
-   vbios.data_return_bus_width = bw_int_to_fixed(32);
-   vbios.trc = bw_int_to_fixed(50);
-   vbios.dmifmc_urgent_latency = bw_int_to_fixed(4);
-   vbios.stutter_self_refresh_exit_latency = bw_frc_to_fixed(153, 
10);
-   vbios.stutter_self_refresh_entry_latency = bw_int_to_fixed(0);
-   vbios.nbp_state_change_latency = bw_frc_to_fixed(19649, 1000);
-   vbios.mcifwrmc_urgent_latency = bw_int_to_fixed(10);
-   vbios.scatter_gather_enable = true;
-   vbios.down_spread_percentage = bw_frc_to_fixed(5, 10);
-   vbios.cursor_width = 32;
-   vbios.average_compression_rate = 4;
-   vbios.number_of_request_slots_gmc_reserves_for_dmif_per_channel 
= 256;
-   vbios.blackout_duration = bw_int_to_fixed(0); /* us */
-   vbios.maximum_blackout_recovery_time = bw_int_to_fixed(0);
-
-   
dceip.max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation
 = 100;
-   
dceip.max_average_percent_of_ideal_drambw_display_can_use_in_normal_system_operation
 = 100;
-   dceip.percent_of_ideal_port_bw_received_after_urgent_latency = 
100;
-   dceip.large_cursor = false;
-   dceip.dmif_request_buffer_size = bw_int_to_fixed(768);
-   dceip.dmif_pipe_en_fbc_chunk_tracker = false;
-   dceip.cursor_max_outstanding_group_num = 1;
-   dceip.lines_interleaved_into_lb = 2;
-   dceip.chunk_width = 256;
-   dceip.number_of_graphics_pipes = 3;
-   dceip.number_of_underlay_pipes = 1;
-   dceip.low_power_tiling_mode = 0;
-   dceip.display_write_back_supported = false;
-   dceip.argb_compression_support = false;
-   dceip.underlay_vscaler_efficiency6_bit_per_component =
+   vbios->memory_type = bw_def_gddr5;
+   vbios->dram_channel_widt

[PATCH 10/53] drm/amd/display/dc/dce/dce_aux: Remove duplicate line causing 'field overwritten' issue

[Lee Jones]

Fixes the following W=1 kernel build warning(s):

 In file included from 
drivers/gpu/drm/amd/amdgpu/../display/dc/dce112/dce112_resource.c:59:
 
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dce/dce_11_2_sh_mask.h:10014:58: 
warning: initialized field overwritten [-Woverride-init]
 drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.h:214:16: note: in 
expansion of macro ‘AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT’
 drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.h:127:2: note: in 
expansion of macro ‘AUX_SF’
 drivers/gpu/drm/amd/amdgpu/../display/dc/dce112/dce112_resource.c:177:2: note: 
in expansion of macro ‘DCE_AUX_MASK_SH_LIST’
 
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dce/dce_11_2_sh_mask.h:10014:58: 
note: (near initialization for ‘aux_shift.AUX_SW_AUTOINCREMENT_DISABLE’)
 drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.h:214:16: note: in 
expansion of macro ‘AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT’
 drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.h:127:2: note: in 
expansion of macro ‘AUX_SF’
 drivers/gpu/drm/amd/amdgpu/../display/dc/dce112/dce112_resource.c:177:2: note: 
in expansion of macro ‘DCE_AUX_MASK_SH_LIST’
 
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dce/dce_11_2_sh_mask.h:10013:56: 
warning: initialized field overwritten [-Woverride-init]
 drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.h:214:16: note: in 
expansion of macro ‘AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK’
 drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.h:127:2: note: in 
expansion of macro ‘AUX_SF’
 drivers/gpu/drm/amd/amdgpu/../display/dc/dce112/dce112_resource.c:181:2: note: 
in expansion of macro ‘DCE_AUX_MASK_SH_LIST’
 
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dce/dce_11_2_sh_mask.h:10013:56: 
note: (near initialization for ‘aux_mask.AUX_SW_AUTOINCREMENT_DISABLE’)
 drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.h:214:16: note: in 
expansion of macro ‘AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK’
 drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.h:127:2: note: in 
expansion of macro ‘AUX_SF’

Cc: Harry Wentland 
Cc: Leo Li 
Cc: Alex Deucher 
Cc: "Christian König" 
Cc: David Airlie 
Cc: Daniel Vetter 
Cc: amd-gfx@lists.freedesktop.org
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Lee Jones 
---
 drivers/gpu/drm/amd/display/dc/dce/dce_aux.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h 
b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
index 775e24926380e..566b1bddd8cc6 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
@@ -100,7 +100,6 @@ struct dce110_aux_registers {
AUX_SF(AUX_SW_CONTROL, AUX_SW_GO, mask_sh),\
AUX_SF(AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\
AUX_SF(AUX_SW_DATA, AUX_SW_DATA_RW, mask_sh),\
-   AUX_SF(AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\
AUX_SF(AUX_SW_DATA, AUX_SW_INDEX, mask_sh),\
AUX_SF(AUX_SW_DATA, AUX_SW_DATA, mask_sh),\
AUX_SF(AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT, mask_sh),\
-- 
2.27.0

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

AMDGPU Linux 5.11.0 freezes (divide error)

[Jonas Zeiger]

Hi all,

I am experiencing random system freezes (about once per day) after updating to 
Linux 5.11 (vanilla kernel).

Only a manual power-cycle makes the system usable again afterwards.

These freezes didn't occur on 5.10.x but I hadn't assigned "nohz_full=2-16" and 
"cpuidle.governor=teo" back then.

Hardware:

ThinkPad T14 (gen1)
CPU: AMD Ryzen 7 PRO 4750U with Radeon Graphics

Kernel cmdline:

BOOT_IMAGE=/vmlinuz-5.11.0zlinux-svr-docker-wg root=/dev/nvme0n1p2 ro 
nohz_full=2-16 cpuidle.governor=teo rootfstype=ext4 rootwait 
ivrs_ioapic[4]=00:14.0 ivrs_ioapic[5]=00:00.2

This is logged to the journal:

kernel: divide error:  [#1] PREEMPT SMP
kernel: CPU: 8 PID: 2914 Comm: Xorg Not tainted 5.11.0zlinux-svr-docker-wg #8
kernel: Hardware name: LENOVO 20UD0013GE/20UD0013GE, BIOS R1BET58W(1.27 ) 
10/20/2020
kernel: RIP: 0010:Calculate256BBlockSizes+0x50/0xc1 [amdgpu]
kernel: Code: 83 ff 02 75 09 41 c7 00 04 00 00 00 eb 15 83 ff 08 75 09 41 c7 00 
10 00 00 00 eb 07 4>
kernel: RSP: 0018:a35e815fb688 EFLAGS: 00010246
kernel: RAX: 0100 RBX: 98afc1debaf8 RCX: 
kernel: RDX:  RSI:  RDI: 0001
kernel: RBP: 98afc1de2090 R08: 98afc1debab8 R09: 98afc1debad8
kernel: R10: 0002 R11: 98afc1debb18 R12: 98a8d9ddd000
kernel: R13:  R14: 98afc1de31c8 R15: 98afc1de2090
kernel: FS:  7f41f3ff0a40() GS:98b35fa0() 
knlGS:
kernel: CS:  0010 DS:  ES:  CR0: 80050033
kernel: CR2: 7f0486175000 CR3: 000116542000 CR4: 00350ee0
kernel: Call Trace:
kernel:  
DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation+0xdb8/0x>
kernel:  ? ModeSupportAndSystemConfiguration+0x77/0xe7 [amdgpu]
kernel:  ? dcn_bw_ceil2+0x19/0x3b [amdgpu]
kernel:  ? dml21_recalculate+0x59c/0x5b3 [amdgpu]
kernel:  get_wm_urgent+0x9/0x13 [amdgpu]
kernel:  dml21_rq_dlg_get_dlg_reg+0x6c/0x1804 [amdgpu]
kernel:  ? dcn_bw_ceil2+0x19/0x3b [amdgpu]
kernel:  ? 
DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation+0x3e06>
kernel:  dcn20_calculate_dlg_params+0x333/0x3af [amdgpu]
kernel:  dcn21_validate_bandwidth+0x4cd/0x581 [amdgpu]
kernel:  dc_validate_global_state+0x1a7/0x1c5 [amdgpu]
kernel:  amdgpu_dm_atomic_check+0x84c/0xa00 [amdgpu]
kernel:  ? __radix_tree_lookup+0x2a/0x91
kernel:  drm_atomic_check_only+0x5bb/0x6b7
kernel:  ? drm_mode_object_put+0x21/0x2d
kernel:  ? drm_atomic_set_property+0x7b3/0x7c5
kernel:  drm_atomic_commit+0xe/0x44
kernel:  drm_mode_obj_set_property_ioctl+0x112/0x268
kernel:  ? __fpu__restore_sig+0x21e/0x46d
kernel:  ? drm_mode_obj_find_prop_id+0x23/0x23
kernel:  drm_ioctl_kernel+0x7d/0xbc
kernel:  drm_ioctl+0x1f2/0x2c9
kernel:  ? drm_mode_obj_find_prop_id+0x23/0x23
kernel:  ? rpm_resume+0x43e/0x450
kernel:  amdgpu_drm_ioctl+0x45/0x71 [amdgpu]
kernel:  vfs_ioctl+0x1a/0x28
kernel:  __do_sys_ioctl+0x51/0x74
kernel:  do_syscall_64+0x33/0x40
kernel:  entry_SYSCALL_64_after_hwframe+0x44/0xa9
kernel: RIP: 0033:0x7f41f445bcc7
kernel: Code: 00 00 00 48 8b 05 c9 91 0c 00 64 c7 00 26 00 00 00 48 c7 c0 ff ff 
ff ff c3 66 2e 0f 1>
kernel: RSP: 002b:7ffd7b9f4db8 EFLAGS: 0246 ORIG_RAX: 0010
kernel: RAX: ffda RBX: 7ffd7b9f4df0 RCX: 7f41f445bcc7
kernel: RDX: 7ffd7b9f4df0 RSI: c01864ba RDI: 000f
kernel: RBP: c01864ba R08: 0073 R09: 
kernel: R10: 0fff R11: 0246 R12: 561f30685480
kernel: R13: 000f R14:  R15: 0003
kernel: Modules linked in: iwlmvm iwlwifi amdgpu drm_ttm_helper ttm mfd_core 
gpu_sched r8169
kernel: ---[ end trace 7e898fd18a4b26cd ]---
kernel: [ cut here ]
kernel: WARNING: CPU: 8 PID: 2914 at rcu_note_context_switch+0x3a/0x2d5
kernel: Modules linked in: iwlmvm iwlwifi amdgpu drm_ttm_helper ttm mfd_core 
gpu_sched r8169
kernel: CPU: 8 PID: 2914 Comm: Xorg Tainted: G  D   
5.11.0zlinux-svr-docker-wg #8
kernel: Hardware name: LENOVO 20UD0013GE/20UD0013GE, BIOS R1BET58W(1.27 ) 
10/20/2020
kernel: RIP: 0010:rcu_note_context_switch+0x3a/0x2d5
kernel: Code: 40 65 02 00 55 53 89 fb 65 4c 03 25 ff cb ed 68 48 8b 3d c8 af b0 
01 e8 3d cd ff ff 8>
kernel: RSP: 0018:a35e815fb160 EFLAGS: 00010002
kernel: RAX:  RBX:  RCX: 0002
kernel: RDX: 0002 RSI: a35e815fb230 RDI: 9884fce6
kernel: RBP: a35e815fb1c0 R08: 9884fce6 R09: 98a880060020
kernel: R10: 98a88006 R11: a35e815fb37b R12: 98b35fa26540
kernel: R13: 98a884cf6900 R14:  R15: 97ac8616
kernel: FS:  7f41f3ff0a40() GS:98b35fa0() 
knlGS:
kernel: CS:  0010 DS:  ES:  CR0: 80050033
kernel: CR2: 7f0486175000 CR3: 000116542000 CR4: 00350ee0
kernel: Call Trace:
kernel:  __sched

[RESEND 00/53] Rid GPU from W=1 warnings

[Lee Jones]

This is a resend.  All of these patches have been sent before.

The vmwgfx ones were even applied, but were dropped for some reason.

Lee Jones (53):
  drm/nouveau/nvkm/subdev/bios/init: Demote obvious abuse of kernel-doc
  drm/nouveau/dispnv50/disp: Remove unused variable 'ret'
  drm/msm/dp/dp_display: Remove unused variable 'hpd'
  drm/amd/display/dc/bios/command_table: Remove unused variable
  include: drm: drm_atomic: Make use of 'new_plane_state'
  drm/nouveau/nvkm/subdev/volt/gk20a: Demote non-conformant kernel-doc
headers
  drm/amd/display/dc/bios/command_table: Remove unused variable and
associated comment
  drm/amd/display/dc/calcs/dce_calcs: Move some large variables from the
stack to the heap
  drm/amd/display/dc/calcs/dce_calcs: Remove some large variables from
the stack
  drm/amd/display/dc/dce/dce_aux: Remove duplicate line causing 'field
overwritten' issue
  drm/amd/display/dc/dce80/dce80_resource: Make local functions static
  drm/nouveau/nvkm/engine/gr/gf100: Demote non-conformant kernel-doc
header
  drm/nouveau/nouveau_bo: Remove unused variables 'dev'
  drm/nouveau/nouveau_display: Remove set but unused variable 'width'
  drm/nouveau/dispnv04/crtc: Demote non-conforming kernel-doc headers
  drm/nouveau/dispnv50/disp: Remove unused variable 'ret' from function
returning void
  drm/nouveau/dispnv50/headc57d: Make local function 'headc57d_olut'
static
  drm/nouveau/nv50_display: Remove superfluous prototype for local
static functions
  drm/nouveau/dispnv50/disp: Include header containing our prototypes
  drm/nouveau/nouveau_ioc32: File headers are not good candidates for
kernel-doc
  drm/nouveau/nouveau_svm: Remove unused variable 'ret' from void
function
  drm/nouveau/nouveau_ioc32: Demote kernel-doc abuse to standard comment
block
  drm/vmwgfx/vmwgfx_execbuf: Fix some kernel-doc related issues
  drm/vmwgfx/vmwgfx_kms: Remove unused variable 'ret' from
'vmw_du_primary_plane_atomic_check()'
  drm/vmwgfx/vmwgfx_kms: Mark vmw_{cursor,primary}_plane_formats as
__maybe_unused
  drm/vmwgfx/vmwgfx_drv: Fix some kernel-doc misdemeanours
  drm/vmwgfx/vmwgfx_ioctl: Provide missing '@' sign required by
kernel-doc
  drm/vmwgfx/vmwgfx_resource: Fix worthy function headers demote some
others
  drm/vmwgfx/vmwgfx_ttm_buffer: Supply some missing parameter
descriptions
  drm/vmwgfx/vmwgfx_fifo: Demote non-conformant kernel-doc header
  drm/vmwgfx/vmwgfx_ldu: Supply descriptions for 'state' function
parameter
  drm/vmwgfx/vmwgfx_kms: Update worthy function headers and demote
others
  drm/vmwgfx/vmwgfx_overlay: Demote kernel-doc abuses to standard
comment blocks
  drm/vmwgfx/vmwgfx_fence: Add, remove and demote various documentation
params/headers
  drm/vmwgfx/vmwgfx_bo: Remove superfluous param description and supply
another
  drm/vmwgfx/vmwgfx_context: Demote kernel-doc abuses
  drm/vmwgfx/vmwgfx_scrn: Demote unworthy kernel-doc headers and update
others
  drm/vmwgfx/vmwgfx_surface: Fix some kernel-doc related issues
  drm/vmwgfx/vmwgfx_cmdbuf_res: Rename param description and remove
another
  drm/vmwgfx/vmwgfx_shader: Demote kernel-doc abuses and fix-up worthy
headers
  drm/vmwgfx/vmwgfx_cmdbuf: Fix a bunch of missing or incorrectly
formatted/named params
  drm/vmwgfx/vmwgfx_cmdbuf_res: Remove unused variable 'ret'
  drm/vmwgfx/vmwgfx_stdu: Add some missing param/member descriptions
  drm/vmwgfx/vmwgfx_cmdbuf: Fix misnaming of 'headers' should be plural
  drm/vmwgfx/vmwgfx_cotable: Fix a couple of simple documentation
problems
  drm/vmwgfx/vmwgfx_so: Add description for 'vmw_view's 'rcu' member
  drm/vmwgfx/vmwgfx_binding: Provide some missing param descriptions and
remove others
  drm/vmwgfx/vmwgfx_msg: Fix misspelling of 'msg'
  drm/vmwgfx/vmwgfx_blit: Add description for 'vmw_bo_cpu_blit's 'diff'
param
  drm/vmwgfx/vmwgfx_validation: Add some missing struct member/function
param descriptions
  drm/vmwgfx/ttm_object: Demote half-assed headers and fix-up another
  drm/vmwgfx/vmwgfx_thp: Add description for 'vmw_thp_manager's member
'manager'
  drm/vmwgfx/ttm_object: Reorder header to immediately precede its
struct

 .../drm/amd/display/dc/bios/command_table.c   |   16 +-
 .../gpu/drm/amd/display/dc/calcs/dce_calcs.c  | 1151 +
 drivers/gpu/drm/amd/display/dc/dce/dce_aux.h  |1 -
 .../drm/amd/display/dc/dce80/dce80_resource.c |   16 +-
 drivers/gpu/drm/msm/dp/dp_display.c   |3 -
 drivers/gpu/drm/nouveau/dispnv04/crtc.c   |4 +-
 drivers/gpu/drm/nouveau/dispnv50/disp.c   |   10 +-
 drivers/gpu/drm/nouveau/dispnv50/headc57d.c   |2 +-
 drivers/gpu/drm/nouveau/nouveau_bo.c  |4 -
 drivers/gpu/drm/nouveau/nouveau_display.c |8 +-
 drivers/gpu/drm/nouveau/nouveau_ioc32.c   |4 +-
 drivers/gpu/drm/nouveau/nouveau_svm.c |5 +-
 drivers/gpu/drm/nouveau/nv50_display.h|3 -
 .../gpu/drm/nouveau/nvkm/e

[PATCH 04/53] drm/amd/display/dc/bios/command_table: Remove unused variable

[Lee Jones]

None of the surrounding code was removed just in case even a small
fraction of it was functional.

Fixes the following W=1 kernel build warning(s):

 drivers/gpu/drm/amd/amdgpu/../display/dc/bios/command_table.c: In function 
‘adjust_display_pll_v2’:
 drivers/gpu/drm/amd/amdgpu/../display/dc/bios/command_table.c:1459:35: 
warning: variable ‘params’ set but not used [-Wunused-but-set-variable]

Cc: Harry Wentland 
Cc: Leo Li 
Cc: Alex Deucher 
Cc: "Christian König" 
Cc: David Airlie 
Cc: Daniel Vetter 
Cc: Qinglang Miao 
Cc: amd-gfx@lists.freedesktop.org
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Lee Jones 
---
 drivers/gpu/drm/amd/display/dc/bios/command_table.c | 12 +++-
 1 file changed, 3 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table.c 
b/drivers/gpu/drm/amd/display/dc/bios/command_table.c
index afc10b954ffa7..9d3bc3a073821 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table.c
@@ -1517,20 +1517,14 @@ static enum bp_result adjust_display_pll_v2(
struct bp_adjust_pixel_clock_parameters *bp_params)
 {
enum bp_result result = BP_RESULT_FAILURE;
-   ADJUST_DISPLAY_PLL_PS_ALLOCATION params = { 0 };
 
/* We need to convert from KHz units into 10KHz units and then convert
 * output pixel clock back 10KHz-->KHz */
uint32_t pixel_clock_10KHz_in = bp_params->pixel_clock / 10;
 
-   params.usPixelClock = cpu_to_le16((uint16_t)(pixel_clock_10KHz_in));
-   params.ucTransmitterID =
-   bp->cmd_helper->encoder_id_to_atom(
-   dal_graphics_object_id_get_encoder_id(
-   
bp_params->encoder_object_id));
-   params.ucEncodeMode =
-   (uint8_t)bp->cmd_helper->encoder_mode_bp_to_atom(
-   bp_params->signal_type, false);
+   bp->cmd_helper->encoder_id_to_atom(
+   
dal_graphics_object_id_get_encoder_id(bp_params->encoder_object_id));
+   bp->cmd_helper->encoder_mode_bp_to_atom(bp_params->signal_type, false);
return result;
 }
 
-- 
2.27.0

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 07/53] drm/amd/display/dc/bios/command_table: Remove unused variable and associated comment

[Lee Jones]

Fixes the following W=1 kernel build warning(s):

 drivers/gpu/drm/amd/amdgpu/../display/dc/bios/command_table.c: In function 
‘adjust_display_pll_v2’:
 drivers/gpu/drm/amd/amdgpu/../display/dc/bios/command_table.c:1462:11: 
warning: unused variable ‘pixel_clock_10KHz_in’ [-Wunused-variable]

Cc: Harry Wentland 
Cc: Leo Li 
Cc: Alex Deucher 
Cc: "Christian König" 
Cc: David Airlie 
Cc: Daniel Vetter 
Cc: Lee Jones 
Cc: amd-gfx@lists.freedesktop.org
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Lee Jones 
---
 drivers/gpu/drm/amd/display/dc/bios/command_table.c | 4 
 1 file changed, 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table.c 
b/drivers/gpu/drm/amd/display/dc/bios/command_table.c
index 9d3bc3a073821..e879ceb0c49ed 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table.c
@@ -1518,10 +1518,6 @@ static enum bp_result adjust_display_pll_v2(
 {
enum bp_result result = BP_RESULT_FAILURE;
 
-   /* We need to convert from KHz units into 10KHz units and then convert
-* output pixel clock back 10KHz-->KHz */
-   uint32_t pixel_clock_10KHz_in = bp_params->pixel_clock / 10;
-
bp->cmd_helper->encoder_id_to_atom(

dal_graphics_object_id_get_encoder_id(bp_params->encoder_object_id));
bp->cmd_helper->encoder_mode_bp_to_atom(bp_params->signal_type, false);
-- 
2.27.0

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 08/53] drm/amd/display/dc/calcs/dce_calcs: Move some large variables from the stack to the heap

[Lee Jones]

Fixes the following W=1 kernel build warning(s):

 drivers/gpu/drm/amd/amdgpu/../display/dc/calcs/dce_calcs.c: In function 
‘calculate_bandwidth’:
 drivers/gpu/drm/amd/amdgpu/../display/dc/calcs/dce_calcs.c:2016:1: warning: 
the frame size of 1216 bytes is larger than 1024 bytes [-Wframe-larger-than=]

Cc: Harry Wentland 
Cc: Leo Li 
Cc: Alex Deucher 
Cc: "Christian König" 
Cc: David Airlie 
Cc: Daniel Vetter 
Cc: Colin Ian King 
Cc: amd-gfx@lists.freedesktop.org
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Lee Jones 
---
 .../gpu/drm/amd/display/dc/calcs/dce_calcs.c  | 29 ---
 1 file changed, 25 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 
b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
index e633f8a51edb6..4f0474a3bbcad 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
@@ -98,16 +98,16 @@ static void calculate_bandwidth(
int32_t num_cursor_lines;
 
int32_t i, j, k;
-   struct bw_fixed yclk[3];
-   struct bw_fixed sclk[8];
+   struct bw_fixed *yclk;
+   struct bw_fixed *sclk;
bool d0_underlay_enable;
bool d1_underlay_enable;
bool fbc_enabled;
bool lpt_enabled;
enum bw_defines sclk_message;
enum bw_defines yclk_message;
-   enum bw_defines tiling_mode[maximum_number_of_surfaces];
-   enum bw_defines surface_type[maximum_number_of_surfaces];
+   enum bw_defines *tiling_mode;
+   enum bw_defines *surface_type;
enum bw_defines voltage;
enum bw_defines pipe_check;
enum bw_defines hsr_check;
@@ -122,6 +122,22 @@ static void calculate_bandwidth(
int32_t number_of_displays_enabled_with_margin = 0;
int32_t number_of_aligned_displays_with_no_margin = 0;
 
+   yclk = kcalloc(3, sizeof(*yclk), GFP_KERNEL);
+   if (!yclk)
+   return;
+
+   sclk = kcalloc(8, sizeof(*sclk), GFP_KERNEL);
+   if (!sclk)
+   return;
+
+   tiling_mode = kcalloc(maximum_number_of_surfaces, sizeof(*tiling_mode), 
GFP_KERNEL);
+   if (!tiling_mode)
+   return;
+
+   surface_type = kcalloc(maximum_number_of_surfaces, 
sizeof(*surface_type), GFP_KERNEL);
+   if (!surface_type)
+   return;
+
yclk[low] = vbios->low_yclk;
yclk[mid] = vbios->mid_yclk;
yclk[high] = vbios->high_yclk;
@@ -2013,6 +2029,11 @@ static void calculate_bandwidth(
}
}
}
+
+   kfree(tiling_mode);
+   kfree(surface_type);
+   kfree(yclk);
+   kfree(sclk);
 }
 
 
/***
-- 
2.27.0

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 08/53] drm/amd/display/dc/calcs/dce_calcs: Move some large variables from the stack to the heap

[Christian König]

Hi Lee,

I'm not an expert for the DC code base, but I think that this won't work.

This function is not allowed to sleep and the structures are a bit large 
to be allocated on the heap in an atomic context.


Regards,
Christian.

Am 03.03.21 um 14:42 schrieb Lee Jones:

Fixes the following W=1 kernel build warning(s):

  drivers/gpu/drm/amd/amdgpu/../display/dc/calcs/dce_calcs.c: In function 
‘calculate_bandwidth’:
  drivers/gpu/drm/amd/amdgpu/../display/dc/calcs/dce_calcs.c:2016:1: warning: 
the frame size of 1216 bytes is larger than 1024 bytes [-Wframe-larger-than=]

Cc: Harry Wentland 
Cc: Leo Li 
Cc: Alex Deucher 
Cc: "Christian König" 
Cc: David Airlie 
Cc: Daniel Vetter 
Cc: Colin Ian King 
Cc: amd-gfx@lists.freedesktop.org
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Lee Jones 
---
  .../gpu/drm/amd/display/dc/calcs/dce_calcs.c  | 29 ---
  1 file changed, 25 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 
b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
index e633f8a51edb6..4f0474a3bbcad 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
@@ -98,16 +98,16 @@ static void calculate_bandwidth(
int32_t num_cursor_lines;
  
  	int32_t i, j, k;

-   struct bw_fixed yclk[3];
-   struct bw_fixed sclk[8];
+   struct bw_fixed *yclk;
+   struct bw_fixed *sclk;
bool d0_underlay_enable;
bool d1_underlay_enable;
bool fbc_enabled;
bool lpt_enabled;
enum bw_defines sclk_message;
enum bw_defines yclk_message;
-   enum bw_defines tiling_mode[maximum_number_of_surfaces];
-   enum bw_defines surface_type[maximum_number_of_surfaces];
+   enum bw_defines *tiling_mode;
+   enum bw_defines *surface_type;
enum bw_defines voltage;
enum bw_defines pipe_check;
enum bw_defines hsr_check;
@@ -122,6 +122,22 @@ static void calculate_bandwidth(
int32_t number_of_displays_enabled_with_margin = 0;
int32_t number_of_aligned_displays_with_no_margin = 0;
  
+	yclk = kcalloc(3, sizeof(*yclk), GFP_KERNEL);

+   if (!yclk)
+   return;
+
+   sclk = kcalloc(8, sizeof(*sclk), GFP_KERNEL);
+   if (!sclk)
+   return;
+
+   tiling_mode = kcalloc(maximum_number_of_surfaces, sizeof(*tiling_mode), 
GFP_KERNEL);
+   if (!tiling_mode)
+   return;
+
+   surface_type = kcalloc(maximum_number_of_surfaces, 
sizeof(*surface_type), GFP_KERNEL);
+   if (!surface_type)
+   return;
+
yclk[low] = vbios->low_yclk;
yclk[mid] = vbios->mid_yclk;
yclk[high] = vbios->high_yclk;
@@ -2013,6 +2029,11 @@ static void calculate_bandwidth(
}
}
}
+
+   kfree(tiling_mode);
+   kfree(surface_type);
+   kfree(yclk);
+   kfree(sclk);
  }
  
  /***


___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH][next] drm/amdgpu/display: remove redundant continue statement

[Colin King]

From: Colin Ian King 

The continue statement in a for-loop is redudant and can be removed.
Clean up the code to address this.

Addresses-Coverity: ("Continue as no effect")
Fixes: b6f91fc183f7 ("drm/amdgpu/display: buffer INTERRUPT_LOW_IRQ_CONTEXT 
interrupt work")
Signed-off-by: Colin Ian King 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
index 8ce10d0973c5..d3c687d07ee6 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
@@ -520,9 +520,7 @@ static void amdgpu_dm_irq_schedule_work(struct 
amdgpu_device *adev,
return;
 
list_for_each_entry (handler_data, handler_list, list) {
-   if (!queue_work(system_highpri_wq, &handler_data->work)) {
-   continue;
-   } else {
+   if (queue_work(system_highpri_wq, &handler_data->work)) {
work_queued = true;
break;
}
-- 
2.30.0

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

re: drm/amd/display: Implement dmub trace event

[Colin Ian King]

Hi,

Static analysis on linux-next wit Coverity has found a potential null
pointer dereference in commit:

commit 70732504c53b2d3aae2cebc457515a304672d5bb
Author: Yongqiang Sun 
Date:   Fri Feb 19 14:50:23 2021 -0500

drm/amd/display: Implement dmub trace event

The analysis is as follows:

400 enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,
401  const struct dmub_srv_hw_params
*params)
402 {
403struct dmub_fb *inst_fb = params->fb[DMUB_WINDOW_0_INST_CONST];
404struct dmub_fb *stack_fb = params->fb[DMUB_WINDOW_1_STACK];
405struct dmub_fb *data_fb = params->fb[DMUB_WINDOW_2_BSS_DATA];
406struct dmub_fb *bios_fb = params->fb[DMUB_WINDOW_3_VBIOS];
407struct dmub_fb *mail_fb = params->fb[DMUB_WINDOW_4_MAILBOX];
408struct dmub_fb *tracebuff_fb =
params->fb[DMUB_WINDOW_5_TRACEBUFF];
409struct dmub_fb *fw_state_fb = params->fb[DMUB_WINDOW_6_FW_STATE];
410struct dmub_fb *scratch_mem_fb =
params->fb[DMUB_WINDOW_7_SCRATCH_MEM];
411
412struct dmub_rb_init_params rb_params, outbox0_rb_params;
413struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6;
414struct dmub_region inbox1, outbox1, outbox0;
415

   1. Condition !dmub->sw_init, taking false branch.

416if (!dmub->sw_init)
417return DMUB_STATUS_INVALID;
418
419dmub->fb_base = params->fb_base;
420dmub->fb_offset = params->fb_offset;
421dmub->psp_version = params->psp_version;
422

   2. Condition dmub->hw_funcs.reset, taking true branch.

423if (dmub->hw_funcs.reset)
424dmub->hw_funcs.reset(dmub);
425

   3. Condition inst_fb, taking true branch.
   4. Condition data_fb, taking true branch.

426if (inst_fb && data_fb) {
427cw0.offset.quad_part = inst_fb->gpu_addr;
428cw0.region.base = DMUB_CW0_BASE;
429cw0.region.top = cw0.region.base + inst_fb->size - 1;
430
431cw1.offset.quad_part = stack_fb->gpu_addr;
432cw1.region.base = DMUB_CW1_BASE;
433cw1.region.top = cw1.region.base + stack_fb->size - 1;
434

   5. Condition params->load_inst_const, taking true branch.
   6. Condition dmub->hw_funcs.backdoor_load, taking true branch.

435if (params->load_inst_const &&
dmub->hw_funcs.backdoor_load) {
436/**
437 * Read back all the instruction memory so we
don't hang the
438 * DMCUB when backdoor loading if the write from
x86 hasn't been
439 * flushed yet. This only occurs in backdoor loading.
440 */
441dmub_flush_buffer_mem(inst_fb);
442dmub->hw_funcs.backdoor_load(dmub, &cw0, &cw1);
443}
444
445}
446

   7. Condition inst_fb, taking true branch.
   8. Condition data_fb, taking true branch.
   9. Condition bios_fb, taking true branch.
   10. Condition mail_fb, taking true branch.
   11. Condition tracebuff_fb, taking false branch.
   12. var_compare_op: Comparing tracebuff_fb to null implies that
tracebuff_fb might be null.

447if (inst_fb && data_fb && bios_fb && mail_fb && tracebuff_fb &&
448fw_state_fb && scratch_mem_fb) {
449cw2.offset.quad_part = data_fb->gpu_addr;
450cw2.region.base = DMUB_CW0_BASE + inst_fb->size;
451cw2.region.top = cw2.region.base + data_fb->size;
452
453cw3.offset.quad_part = bios_fb->gpu_addr;
454cw3.region.base = DMUB_CW3_BASE;
455cw3.region.top = cw3.region.base + bios_fb->size;
456
457cw4.offset.quad_part = mail_fb->gpu_addr;
458cw4.region.base = DMUB_CW4_BASE;
459cw4.region.top = cw4.region.base + mail_fb->size;
460
461/**
462 * Doubled the mailbox region to accomodate inbox and
outbox.
463 * Note: Currently, currently total mailbox size is
16KB. It is split
464 * equally into 8KB between inbox and outbox. If this
config is
465 * changed, then uncached base address configuration
of outbox1
466 * has to be updated in funcs->setup_out_mailbox.
467 */
468inbox1.base = cw4.region.base;
469inbox1.top = cw4.region.base + DMUB_RB_SIZE;
470outbox1.base = inbox1.top;
471outbox1.top = cw4.region.top;
472
473cw5.offset.quad_part = tracebuff_fb->gpu_addr;
474cw5.region.base = DMUB_CW5_BASE;
475cw5.region.top = cw5.region.base + tracebuff_fb->size;
476
477outbox0.base = DMUB_REGION5_BASE +
TRACE_BUFFER_ENTRY_OFFSET;
478outbox0.top = outbox0.base + sizeof(struct
dmcub_trace_buf_entry) * PERF_TRACE_MAX_ENTRY;
479
480
481cw6.offset.quad_part = fw_state

[PATCH] drm/amdgpu: Remove unnecessary conversion to bool

[Jiapeng Chong]

Fix the following coccicheck warnings:

./drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c:2252:40-45: WARNING: conversion
to bool not needed here.

Reported-by: Abaci Robot 
Signed-off-by: Jiapeng Chong 
---
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index c8c22c1..00d3773 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -2249,7 +2249,7 @@ static int sdma_v4_0_set_powergating_state(void *handle,
case CHIP_RAVEN:
case CHIP_RENOIR:
sdma_v4_1_update_power_gating(adev,
-   state == AMD_PG_STATE_GATE ? true : false);
+   state == AMD_PG_STATE_GATE);
break;
default:
break;
-- 
1.8.3.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH v2 3/3] drm/amdgpu: drm/amdkfd: add amdgpu_kfd_bo struct

[Nirmoy]

On 3/3/21 1:04 PM, Christian König wrote:

Am 03.03.21 um 10:25 schrieb Nirmoy Das:

Implement a new struct based on amdgpu_bo base class
for BOs created by kfd device so that kfd related memeber
of amdgpu_bo can be moved there.


You should probably restructure which patch has which code in it here.

The first one adds the general infrastructure and makes the necessary 
modification to allow allocating BO structures with different 
structure size.


And the second then adds the amdgpu_kfd_bo structure so that the KFD 
can use it.



Thanks, I will split this into two.




You should also double check with Felix if we don't support importing 
BOs from elsewhere here and if that approach is correct.



Waiting for Felix to come back from vacation.


Nirmoy






Regards,
Christian.



v2: rename AMDGPU_GEM_USER_KFD -> AMDGPU_GEM_CREATE_KFD

Signed-off-by: Nirmoy Das 
---
  .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c  | 10 --
  drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c    |  3 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_object.c    | 32 ++-
  drivers/gpu/drm/amd/amdgpu/amdgpu_object.h    |  8 -
  4 files changed, 40 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

index 57798707cd5f..1f52ae4de609 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -1152,6 +1152,7 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
  struct sg_table *sg = NULL;
  uint64_t user_addr = 0;
  struct amdgpu_bo *bo;
+    struct amdgpu_kfd_bo *kbo;
  struct amdgpu_bo_param bp;
  u32 domain, alloc_domain;
  u64 alloc_flags;
@@ -1227,17 +1228,20 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
  bp.flags = alloc_flags;
  bp.type = bo_type;
  bp.resv = NULL;
-    ret = amdgpu_kfd_bo_create(adev, &bp, &bo);
+    ret = amdgpu_kfd_bo_create(adev, &bp, &kbo);
  if (ret) {
  pr_debug("Failed to create BO on domain %s. ret %d\n",
  domain_string(alloc_domain), ret);
  goto err_bo_create;
  }
+
+    bo = &kbo->bo;
  if (bo_type == ttm_bo_type_sg) {
  bo->tbo.sg = sg;
  bo->tbo.ttm->sg = sg;
  }
-    bo->kfd_bo = *mem;
+
+    kbo->kfd_bo = *mem;
  (*mem)->bo = bo;
  if (user_addr)
  bo->flags |= AMDGPU_AMDKFD_USERPTR_BO;
@@ -1261,7 +1265,7 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(

  allocate_init_user_pages_failed:
  remove_kgd_mem_from_kfd_bo_list(*mem, avm->process_info);
-    amdgpu_bo_unref(&bo);
+    amdgpu_kfd_bo_unref(&kbo);
  /* Don't unreserve system mem limit twice */
  goto err_reserve_limit;
  err_bo_create:
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c

index 1da67cf812b1..eaaf4940abcb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
@@ -102,6 +102,7 @@ static bool amdgpu_mn_invalidate_hsa(struct 
mmu_interval_notifier *mni,

   unsigned long cur_seq)
  {
  struct amdgpu_bo *bo = container_of(mni, struct amdgpu_bo, 
notifier);
+    struct amdgpu_kfd_bo *kbo = container_of(bo, struct 
amdgpu_kfd_bo, bo);

  struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);

  if (!mmu_notifier_range_blockable(range))
@@ -111,7 +112,7 @@ static bool amdgpu_mn_invalidate_hsa(struct 
mmu_interval_notifier *mni,


  mmu_interval_set_seq(mni, cur_seq);

-    amdgpu_amdkfd_evict_userptr(bo->kfd_bo, bo->notifier.mm);
+    amdgpu_amdkfd_evict_userptr(kbo->kfd_bo, bo->notifier.mm);
  mutex_unlock(&adev->notifier_lock);

  return true;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c

index 1b41b4870c99..787eb99119a2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -551,8 +551,10 @@ static int amdgpu_bo_do_create(struct 
amdgpu_device *adev,


  acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size,
 sizeof(struct amdgpu_bo));
+    if (bp->bo_ptr_size < sizeof(struct amdgpu_bo))
+    bp->bo_ptr_size = sizeof(struct amdgpu_bo);

-    bo = kzalloc(sizeof(struct amdgpu_bo), GFP_KERNEL);
+    bo = kzalloc(bp->bo_ptr_size, GFP_KERNEL);
  if (bo == NULL)
  return -ENOMEM;
  drm_gem_private_object_init(adev_to_drm(adev), &bo->tbo.base, 
size);

@@ -714,35 +716,37 @@ int amdgpu_bo_create(struct amdgpu_device *adev,

  int amdgpu_kfd_bo_create(struct amdgpu_device *adev,
   struct amdgpu_bo_param *bp,
- struct amdgpu_bo **bo_ptr)
+ struct amdgpu_kfd_bo **kfd_bo_ptr)
  {
+    struct amdgpu_bo *bo_ptr;
  u64 flags = bp->flags;
  int r;

  bp->flags = bp->flags & ~AMDGPU_GEM_CREATE_SHADOW;
  bp->flags = bp->flags | AMDGPU_GEM_CREATE_KFD;
-    r = amdgpu_bo_do_create(adev, bp, bo_ptr);
+    bp->bo_ptr_s

Re: [PATCH v2 2/3] drm/amdgpu: introduce kfd user flag for amdgpu_bo

[Christian König]

Am 03.03.21 um 13:41 schrieb Nirmoy:

[SNIP]



+ struct amdgpu_bo_param *bp,
+ struct amdgpu_bo **bo_ptr)
+{
+    u64 flags = bp->flags;
+    int r;
+
+    bp->flags = bp->flags & ~AMDGPU_GEM_CREATE_SHADOW;
+    bp->flags = bp->flags | AMDGPU_GEM_CREATE_KFD;
+    r = amdgpu_bo_do_create(adev, bp, bo_ptr);
+    if (r)
+    return r;
+
+    if ((flags & AMDGPU_GEM_CREATE_SHADOW) && !(adev->flags & 
AMD_IS_APU)) {

+    if (!bp->resv)
+ WARN_ON(dma_resv_lock((*bo_ptr)->tbo.base.resv,
+    NULL));
+
+    r = amdgpu_bo_create_shadow(adev, bp->size, *bo_ptr);
+
+    if (!bp->resv)
+    dma_resv_unlock((*bo_ptr)->tbo.base.resv);
+
+    if (r)
+    amdgpu_bo_unref(bo_ptr);
+    }


I don't think the KFD should ever have a reason to use the shadow 
buffer functionality.



This is interesting, I didn't know. I will remove 
amdgpu_bo_create_shadow().


Well the VM code is using the shadow stuff.







+
+    return r;
+}
+
+
  /**
   * amdgpu_bo_validate - validate an &amdgpu_bo buffer object
   * @bo: pointer to the buffer object
@@ -1309,7 +1355,7 @@ void amdgpu_bo_release_notify(struct 
ttm_buffer_object *bo)


  abo = ttm_to_amdgpu_bo(bo);

-    if (abo->kfd_bo)
+    if (abo->flags & AMDGPU_GEM_CREATE_KFD)
  amdgpu_amdkfd_unreserve_memory_limit(abo);

  /* We only remove the fence if the resv has individualized. */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h

index 8cd96c9330dd..665ee0015f06 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
@@ -245,6 +245,9 @@ void amdgpu_bo_placement_from_domain(struct 
amdgpu_bo *abo, u32 domain);

  int amdgpu_bo_create(struct amdgpu_device *adev,
   struct amdgpu_bo_param *bp,
   struct amdgpu_bo **bo_ptr);
+int amdgpu_kfd_bo_create(struct amdgpu_device *adev,
+ struct amdgpu_bo_param *bp,
+ struct amdgpu_bo **bo_ptr);
  int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
    unsigned long size, int align,
    u32 domain, struct amdgpu_bo **bo_ptr,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

index 7b2db779f313..030bec382f54 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -164,7 +164,7 @@ static int amdgpu_verify_access(struct 
ttm_buffer_object *bo, struct file *filp)

   * Don't verify access for KFD BOs. They don't have a GEM
   * object associated with them.
   */
-    if (abo->kfd_bo)
+    if (abo->flags & AMDGPU_GEM_CREATE_KFD)
  return 0;

  if (amdgpu_ttm_tt_get_usermm(bo->ttm))
diff --git a/include/uapi/drm/amdgpu_drm.h 
b/include/uapi/drm/amdgpu_drm.h

index 8b832f7458f2..f510e8302228 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -142,6 +142,11 @@ extern "C" {
   */
  #define AMDGPU_GEM_CREATE_ENCRYPTED    (1 << 10)

+/* Flag that the allocating BO's user is KFD. It should never be 
used by

+ * user space applications
+ */
+#define AMDGPU_GEM_CREATE_KFD    (1 << 20)


Why 20? 11 is the next one here.



I feel BO owner flag is different than others so wanted to reserve 
some bits for grouping.


I can assign it to 11 if that makes more sense.


We already have other flags which userspace is not allowed to use, so 
this is nothing special here.


Christian.




Thanks,

Nirmoy





Christian.


+
  struct drm_amdgpu_gem_create_in  {
  /** the requested memory size */
  __u64 bo_size;
--
2.30.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=04%7C01%7Cnirmoy.das%40amd.com%7C5c41ee9032df45e36f1508d8de3c0c57%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637503696776437773%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=1Lbaor5CuBUsnxr%2BQgB6zDYbRQVPWogth7gpIOhYRFI%3D&reserved=0 





___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH v2 2/3] drm/amdgpu: introduce kfd user flag for amdgpu_bo

[Nirmoy]

On 3/3/21 1:01 PM, Christian König wrote:

Am 03.03.21 um 10:25 schrieb Nirmoy Das:

Introduce a new flag for amdgpu_bo->flags to identify if
a BO is created by KFD.

v2: rename AMDGPU_GEM_USER_KFD -> AMDGPU_GEM_CREATE_KFD

Signed-off-by: Nirmoy Das 
---
  .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c  |  2 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c   |  3 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_object.c    | 48 ++-
  drivers/gpu/drm/amd/amdgpu/amdgpu_object.h    |  3 ++
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c   |  2 +-
  include/uapi/drm/amdgpu_drm.h |  5 ++
  6 files changed, 59 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

index 89d0e4f7c6a8..57798707cd5f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -1227,7 +1227,7 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
  bp.flags = alloc_flags;
  bp.type = bo_type;
  bp.resv = NULL;
-    ret = amdgpu_bo_create(adev, &bp, &bo);
+    ret = amdgpu_kfd_bo_create(adev, &bp, &bo);
  if (ret) {
  pr_debug("Failed to create BO on domain %s. ret %d\n",
  domain_string(alloc_domain), ret);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c

index 8e9b8a6e6ef0..e0ceeb32642c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -234,7 +234,8 @@ int amdgpu_gem_create_ioctl(struct drm_device 
*dev, void *data,

    AMDGPU_GEM_CREATE_VRAM_CLEARED |
    AMDGPU_GEM_CREATE_VM_ALWAYS_VALID |
    AMDGPU_GEM_CREATE_EXPLICIT_SYNC |
-  AMDGPU_GEM_CREATE_ENCRYPTED))
+  AMDGPU_GEM_CREATE_ENCRYPTED |
+  AMDGPU_GEM_CREATE_KFD))

  return -EINVAL;

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c

index 0bd22ed1dacf..1b41b4870c99 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -697,6 +697,52 @@ int amdgpu_bo_create(struct amdgpu_device *adev,
  return r;
  }

+/**
+ * amdgpu_kfd_bo_create - create an &amdgpu_bo buffer object with 
kfd user flag

+ * @adev: amdgpu device object
+ * @bp: parameters to be used for the buffer object
+ * @bo_ptr: pointer to the buffer object pointer
+ *
+ * Creates an &amdgpu_bo buffer object; and if requested, also 
creates a

+ * shadow object.
+ * Shadow object is used to backup the original buffer object, and 
is always

+ * in GTT.
+ *
+ * Returns:
+ * 0 for success or a negative error code on failure.
+ */
+
+int amdgpu_kfd_bo_create(struct amdgpu_device *adev,


Please name this amdgpu_bo_create_kfd instead.



Ok I will rename it.





+ struct amdgpu_bo_param *bp,
+ struct amdgpu_bo **bo_ptr)
+{
+    u64 flags = bp->flags;
+    int r;
+
+    bp->flags = bp->flags & ~AMDGPU_GEM_CREATE_SHADOW;
+    bp->flags = bp->flags | AMDGPU_GEM_CREATE_KFD;
+    r = amdgpu_bo_do_create(adev, bp, bo_ptr);
+    if (r)
+    return r;
+
+    if ((flags & AMDGPU_GEM_CREATE_SHADOW) && !(adev->flags & 
AMD_IS_APU)) {

+    if (!bp->resv)
+    WARN_ON(dma_resv_lock((*bo_ptr)->tbo.base.resv,
+    NULL));
+
+    r = amdgpu_bo_create_shadow(adev, bp->size, *bo_ptr);
+
+    if (!bp->resv)
+    dma_resv_unlock((*bo_ptr)->tbo.base.resv);
+
+    if (r)
+    amdgpu_bo_unref(bo_ptr);
+    }


I don't think the KFD should ever have a reason to use the shadow 
buffer functionality.



This is interesting, I didn't know. I will remove 
amdgpu_bo_create_shadow().






+
+    return r;
+}
+
+
  /**
   * amdgpu_bo_validate - validate an &amdgpu_bo buffer object
   * @bo: pointer to the buffer object
@@ -1309,7 +1355,7 @@ void amdgpu_bo_release_notify(struct 
ttm_buffer_object *bo)


  abo = ttm_to_amdgpu_bo(bo);

-    if (abo->kfd_bo)
+    if (abo->flags & AMDGPU_GEM_CREATE_KFD)
  amdgpu_amdkfd_unreserve_memory_limit(abo);

  /* We only remove the fence if the resv has individualized. */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h

index 8cd96c9330dd..665ee0015f06 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
@@ -245,6 +245,9 @@ void amdgpu_bo_placement_from_domain(struct 
amdgpu_bo *abo, u32 domain);

  int amdgpu_bo_create(struct amdgpu_device *adev,
   struct amdgpu_bo_param *bp,
   struct amdgpu_bo **bo_ptr);
+int amdgpu_kfd_bo_create(struct amdgpu_device *adev,
+ struct amdgpu_bo_param *bp,
+ struct amdgpu_bo **bo_ptr);
  int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
    unsigned long size, int align,
    u32 domain, struct amdgpu_b

Re: [PATCH v2 3/3] drm/amdgpu: drm/amdkfd: add amdgpu_kfd_bo struct

[Christian König]

Am 03.03.21 um 10:25 schrieb Nirmoy Das:

Implement a new struct based on amdgpu_bo base class
for BOs created by kfd device so that kfd related memeber
of amdgpu_bo can be moved there.


You should probably restructure which patch has which code in it here.

The first one adds the general infrastructure and makes the necessary 
modification to allow allocating BO structures with different structure 
size.


And the second then adds the amdgpu_kfd_bo structure so that the KFD can 
use it.


You should also double check with Felix if we don't support importing 
BOs from elsewhere here and if that approach is correct.


Regards,
Christian.



v2: rename AMDGPU_GEM_USER_KFD -> AMDGPU_GEM_CREATE_KFD

Signed-off-by: Nirmoy Das 
---
  .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c  | 10 --
  drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c|  3 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_object.c| 32 ++-
  drivers/gpu/drm/amd/amdgpu/amdgpu_object.h|  8 -
  4 files changed, 40 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index 57798707cd5f..1f52ae4de609 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -1152,6 +1152,7 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
struct sg_table *sg = NULL;
uint64_t user_addr = 0;
struct amdgpu_bo *bo;
+   struct amdgpu_kfd_bo *kbo;
struct amdgpu_bo_param bp;
u32 domain, alloc_domain;
u64 alloc_flags;
@@ -1227,17 +1228,20 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
bp.flags = alloc_flags;
bp.type = bo_type;
bp.resv = NULL;
-   ret = amdgpu_kfd_bo_create(adev, &bp, &bo);
+   ret = amdgpu_kfd_bo_create(adev, &bp, &kbo);
if (ret) {
pr_debug("Failed to create BO on domain %s. ret %d\n",
domain_string(alloc_domain), ret);
goto err_bo_create;
}
+
+   bo = &kbo->bo;
if (bo_type == ttm_bo_type_sg) {
bo->tbo.sg = sg;
bo->tbo.ttm->sg = sg;
}
-   bo->kfd_bo = *mem;
+
+   kbo->kfd_bo = *mem;
(*mem)->bo = bo;
if (user_addr)
bo->flags |= AMDGPU_AMDKFD_USERPTR_BO;
@@ -1261,7 +1265,7 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(

  allocate_init_user_pages_failed:
remove_kgd_mem_from_kfd_bo_list(*mem, avm->process_info);
-   amdgpu_bo_unref(&bo);
+   amdgpu_kfd_bo_unref(&kbo);
/* Don't unreserve system mem limit twice */
goto err_reserve_limit;
  err_bo_create:
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
index 1da67cf812b1..eaaf4940abcb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
@@ -102,6 +102,7 @@ static bool amdgpu_mn_invalidate_hsa(struct 
mmu_interval_notifier *mni,
 unsigned long cur_seq)
  {
struct amdgpu_bo *bo = container_of(mni, struct amdgpu_bo, notifier);
+   struct amdgpu_kfd_bo *kbo = container_of(bo, struct amdgpu_kfd_bo, bo);
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);

if (!mmu_notifier_range_blockable(range))
@@ -111,7 +112,7 @@ static bool amdgpu_mn_invalidate_hsa(struct 
mmu_interval_notifier *mni,

mmu_interval_set_seq(mni, cur_seq);

-   amdgpu_amdkfd_evict_userptr(bo->kfd_bo, bo->notifier.mm);
+   amdgpu_amdkfd_evict_userptr(kbo->kfd_bo, bo->notifier.mm);
mutex_unlock(&adev->notifier_lock);

return true;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 1b41b4870c99..787eb99119a2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -551,8 +551,10 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev,

acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size,
   sizeof(struct amdgpu_bo));
+   if (bp->bo_ptr_size < sizeof(struct amdgpu_bo))
+   bp->bo_ptr_size = sizeof(struct amdgpu_bo);

-   bo = kzalloc(sizeof(struct amdgpu_bo), GFP_KERNEL);
+   bo = kzalloc(bp->bo_ptr_size, GFP_KERNEL);
if (bo == NULL)
return -ENOMEM;
drm_gem_private_object_init(adev_to_drm(adev), &bo->tbo.base, size);
@@ -714,35 +716,37 @@ int amdgpu_bo_create(struct amdgpu_device *adev,

  int amdgpu_kfd_bo_create(struct amdgpu_device *adev,
 struct amdgpu_bo_param *bp,
-struct amdgpu_bo **bo_ptr)
+struct amdgpu_kfd_bo **kfd_bo_ptr)
  {
+   struct amdgpu_bo *bo_ptr;
u64 flags = bp->flags;
int r;

bp->flags = bp->flags & ~AMDGPU_GEM_CREATE_SHADOW;
bp->flags = bp->flags | AMDGPU_GEM_CREATE_KFD;

Re: [PATCH v2 2/3] drm/amdgpu: introduce kfd user flag for amdgpu_bo

[Christian König]

Am 03.03.21 um 10:25 schrieb Nirmoy Das:

Introduce a new flag for amdgpu_bo->flags to identify if
a BO is created by KFD.

v2: rename AMDGPU_GEM_USER_KFD -> AMDGPU_GEM_CREATE_KFD

Signed-off-by: Nirmoy Das 
---
  .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c  |  2 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c   |  3 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_object.c| 48 ++-
  drivers/gpu/drm/amd/amdgpu/amdgpu_object.h|  3 ++
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c   |  2 +-
  include/uapi/drm/amdgpu_drm.h |  5 ++
  6 files changed, 59 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index 89d0e4f7c6a8..57798707cd5f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -1227,7 +1227,7 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
bp.flags = alloc_flags;
bp.type = bo_type;
bp.resv = NULL;
-   ret = amdgpu_bo_create(adev, &bp, &bo);
+   ret = amdgpu_kfd_bo_create(adev, &bp, &bo);
if (ret) {
pr_debug("Failed to create BO on domain %s. ret %d\n",
domain_string(alloc_domain), ret);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 8e9b8a6e6ef0..e0ceeb32642c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -234,7 +234,8 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void 
*data,
  AMDGPU_GEM_CREATE_VRAM_CLEARED |
  AMDGPU_GEM_CREATE_VM_ALWAYS_VALID |
  AMDGPU_GEM_CREATE_EXPLICIT_SYNC |
- AMDGPU_GEM_CREATE_ENCRYPTED))
+ AMDGPU_GEM_CREATE_ENCRYPTED |
+ AMDGPU_GEM_CREATE_KFD))

return -EINVAL;

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 0bd22ed1dacf..1b41b4870c99 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -697,6 +697,52 @@ int amdgpu_bo_create(struct amdgpu_device *adev,
return r;
  }

+/**
+ * amdgpu_kfd_bo_create - create an &amdgpu_bo buffer object with kfd user flag
+ * @adev: amdgpu device object
+ * @bp: parameters to be used for the buffer object
+ * @bo_ptr: pointer to the buffer object pointer
+ *
+ * Creates an &amdgpu_bo buffer object; and if requested, also creates a
+ * shadow object.
+ * Shadow object is used to backup the original buffer object, and is always
+ * in GTT.
+ *
+ * Returns:
+ * 0 for success or a negative error code on failure.
+ */
+
+int amdgpu_kfd_bo_create(struct amdgpu_device *adev,


Please name this amdgpu_bo_create_kfd instead.


+struct amdgpu_bo_param *bp,
+struct amdgpu_bo **bo_ptr)
+{
+   u64 flags = bp->flags;
+   int r;
+
+   bp->flags = bp->flags & ~AMDGPU_GEM_CREATE_SHADOW;
+   bp->flags = bp->flags | AMDGPU_GEM_CREATE_KFD;
+   r = amdgpu_bo_do_create(adev, bp, bo_ptr);
+   if (r)
+   return r;
+
+   if ((flags & AMDGPU_GEM_CREATE_SHADOW) && !(adev->flags & AMD_IS_APU)) {
+   if (!bp->resv)
+   WARN_ON(dma_resv_lock((*bo_ptr)->tbo.base.resv,
+   NULL));
+
+   r = amdgpu_bo_create_shadow(adev, bp->size, *bo_ptr);
+
+   if (!bp->resv)
+   dma_resv_unlock((*bo_ptr)->tbo.base.resv);
+
+   if (r)
+   amdgpu_bo_unref(bo_ptr);
+   }


I don't think the KFD should ever have a reason to use the shadow buffer 
functionality.



+
+   return r;
+}
+
+
  /**
   * amdgpu_bo_validate - validate an &amdgpu_bo buffer object
   * @bo: pointer to the buffer object
@@ -1309,7 +1355,7 @@ void amdgpu_bo_release_notify(struct ttm_buffer_object 
*bo)

abo = ttm_to_amdgpu_bo(bo);

-   if (abo->kfd_bo)
+   if (abo->flags & AMDGPU_GEM_CREATE_KFD)
amdgpu_amdkfd_unreserve_memory_limit(abo);

/* We only remove the fence if the resv has individualized. */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
index 8cd96c9330dd..665ee0015f06 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
@@ -245,6 +245,9 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, 
u32 domain);
  int amdgpu_bo_create(struct amdgpu_device *adev,
 struct amdgpu_bo_param *bp,
 struct amdgpu_bo **bo_ptr);
+int amdgpu_kfd_bo_create(struct amdgpu_device *adev,
+struct amdgpu_bo_param *bp,
+struct amdgpu_bo **bo_ptr);
  int amdgpu_bo_create_reserved(struct amdgpu_device 

Re: [PATCH v3 0/3] Use kvmalloc_array for radeon and amdgpu CS chunks

[Christian König]

Reviewed-by: Christian König  for the entire 
series.


Am 03.03.21 um 04:49 schrieb Chen Li:

When testing kernel with trinity, the kernel turned to tainted in that radeon 
CS require large memory and order is over MAX_ORDER.

kvmalloc/kvmalloc_array should be used here in that it will fallback to vmalloc 
if necessary.

Chen Li (3):
   drm/radeon: Use kvmalloc for CS chunks
   drm/amdgpu: Use kvmalloc for CS chunks
   drm/amdgpu: correct DRM_ERROR for kvmalloc_array

Changelog:
   v1->v2:
 * also use kvmalloc in amdgpu
 * fix a DRM_ERROR message for kvmalloc_array.
   v2->v3:
 * add missing kvfree for amdgpu CS

  drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 14 +++---
  drivers/gpu/drm/radeon/radeon_cs.c |  8 
  2 files changed, 11 insertions(+), 11 deletions(-)

--
2.30.0




___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

RE: [PATCH] drm/amdgpu: enable one vf mode on sienna cichlid vf

[Liu, Monk]

[AMD Official Use Only - Internal Distribution Only]

Reviewed 

Thanks 

--
Monk Liu | Cloud-GPU Core team
--

-Original Message-
From: Horace Chen  
Sent: Wednesday, March 3, 2021 7:29 PM
To: amd-gfx@lists.freedesktop.org
Cc: Grodzovsky, Andrey ; Quan, Evan 
; Chen, Horace ; Tuikov, Luben 
; Koenig, Christian ; Deucher, 
Alexander ; Xiao, Jack ; Zhang, 
Hawking ; Liu, Monk ; Xu, Feifei 
; Wang, Kevin(Yang) ; Xiaojie Yuan 

Subject: [PATCH] drm/amdgpu: enable one vf mode on sienna cichlid vf

sienna cichlid needs one vf mode which allows vf to set and get clock status 
from guest vm. So now expose the required interface and allow some smu request 
on VF mode. Also since this asic blocked direct MMIO access, use KIQ to send 
SMU request under sriov vf.

OD use same command as getting pp table which is not allowed for  sienna 
cichlid, so remove OD feature under sriov vf.

Signed-off-by: Horace Chen 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c   |  2 ++
 drivers/gpu/drm/amd/pm/amdgpu_pm.c   |  2 +-
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c| 10 ++
 .../gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c  | 10 +-
 drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c   | 12 ++--
 5 files changed, 20 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 71805dfd9e25..a11760ec3924 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2043,6 +2043,8 @@ static int amdgpu_device_ip_early_init(struct 
amdgpu_device *adev)
adev->pm.pp_feature = amdgpu_pp_feature_mask;
if (amdgpu_sriov_vf(adev) || sched_policy == KFD_SCHED_POLICY_NO_HWS)
adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
+   if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_SIENNA_CICHLID)
+   adev->pm.pp_feature &= ~PP_OVERDRIVE_MASK;
 
for (i = 0; i < adev->num_ip_blocks; i++) {
if ((amdgpu_ip_block_mask & (1 << i)) == 0) { diff --git 
a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index 5f77e1c9ebd4..f2a64bd47f42 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -1750,7 +1750,7 @@ static ssize_t amdgpu_get_gpu_metrics(struct device *dev,
 
 static struct amdgpu_device_attr amdgpu_device_attrs[] = {
AMDGPU_DEVICE_ATTR_RW(power_dpm_state,  
ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
-   AMDGPU_DEVICE_ATTR_RW(power_dpm_force_performance_level,
ATTR_FLAG_BASIC),
+   AMDGPU_DEVICE_ATTR_RW(power_dpm_force_performance_level,
ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
AMDGPU_DEVICE_ATTR_RO(pp_num_states,
ATTR_FLAG_BASIC),
AMDGPU_DEVICE_ATTR_RO(pp_cur_state, 
ATTR_FLAG_BASIC),
AMDGPU_DEVICE_ATTR_RW(pp_force_state,   
ATTR_FLAG_BASIC),
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c 
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index f5d9590f2178..3d0a165bf563 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -653,10 +653,12 @@ static int smu_late_init(void *handle)
return ret;
}
 
-   ret = smu_set_default_od_settings(smu);
-   if (ret) {
-   dev_err(adev->dev, "Failed to setup default OD settings!\n");
-   return ret;
+   if (!amdgpu_sriov_vf(adev) || smu->od_enabled) {
+   ret = smu_set_default_od_settings(smu);
+   if (ret) {
+   dev_err(adev->dev, "Failed to setup default OD 
settings!\n");
+   return ret;
+   }
}
 
ret = smu_populate_umd_state_clk(smu); diff --git 
a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index c2d60d75be08..585db482c6d1 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -89,17 +89,17 @@ static struct cmn2asic_msg_mapping 
sienna_cichlid_message_map[SMU_MSG_MAX_COUNT]
MSG_MAP(GetEnabledSmuFeaturesHigh,  
PPSMC_MSG_GetRunningSmuFeaturesHigh,   1),
MSG_MAP(SetWorkloadMask,PPSMC_MSG_SetWorkloadMask,  
   1),
MSG_MAP(SetPptLimit,PPSMC_MSG_SetPptLimit,  
   0),
-   MSG_MAP(SetDriverDramAddrHigh,  
PPSMC_MSG_SetDriverDramAddrHigh,   0),
-   MSG_MAP(SetDriverDramAddrLow,   PPSMC_MSG_SetDriverDramAddrLow, 
   0),
+   MSG_MAP(SetDriverDramAddrHigh,  
PPSMC_MSG_SetDriverDramAddrHigh,   1),
+   MSG_MAP(SetDriverDramAddrLow,   PPSMC_MSG_SetDriverDramAddrLow, 
   1),
MSG_MAP(Se

RE: [PATCH] drm/amdgpu: enable one vf mode on sienna cichlid vf

[Chen, Horace]

[AMD Official Use Only - Internal Distribution Only]

Hi Alex,

Actually I think this can be a potential bug on bare metal, asics may not 
support overdrive but still need to set default od. If there is an SMU firmware 
which supports  PPSMC_MSG_TransferTableSmu2Dram but not support overdrive (just 
like sriov one vf mode), then the bug appears.

But since I don't have bare metal environment, I can let bare metal still run 
the old code path.

Thanks & Regards,
Horace.

-Original Message-
From: Alex Deucher 
Sent: Tuesday, March 2, 2021 12:03 AM
To: Liu, Monk 
Cc: Chen, Horace ; amd-gfx@lists.freedesktop.org; 
Grodzovsky, Andrey ; Xiao, Jack ; 
Xu, Feifei ; Wang, Kevin(Yang) ; 
Xiaojie Yuan ; Tuikov, Luben ; 
Deucher, Alexander ; Quan, Evan ; 
Koenig, Christian ; Zhang, Hawking 

Subject: Re: [PATCH] drm/amdgpu: enable one vf mode on sienna cichlid vf

On Mon, Mar 1, 2021 at 6:37 AM Liu, Monk  wrote:
>
> [AMD Official Use Only - Internal Distribution Only]
>
> Pls change "if (smu->od_enabled) {" to   " if 
> (amdgpu_sriov_vf() && smu->od_enabled) {"

Won't that break bare metal?

Alex

>
> With this addressed the patch is reviewed by me
>
> Thanks
>
> --
> Monk Liu | Cloud-GPU Core team
> --
>
> -Original Message-
> From: Horace Chen 
> Sent: Friday, February 26, 2021 2:31 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Grodzovsky, Andrey ; Quan, Evan 
> ; Chen, Horace ; Tuikov, Luben 
> ; Koenig, Christian ; 
> Deucher, Alexander ; Xiao, Jack 
> ; Zhang, Hawking ; Liu, Monk 
> ; Xu, Feifei ; Wang, Kevin(Yang) 
> ; Xiaojie Yuan 
> Subject: [PATCH] drm/amdgpu: enable one vf mode on sienna cichlid vf
>
> sienna cichlid needs one vf mode which allows vf to set and get clock status 
> from guest vm. So now expose the required interface and allow some smu 
> request on VF mode. Also since this asic blocked direct MMIO access, use KIQ 
> to send SMU request under sriov vf.
>
> OD use same command as getting pp table which is not allowed for  sienna 
> cichlid, so remove OD feature under sriov vf.
>
> Signed-off-by: Horace Chen 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c   |  2 ++
>  drivers/gpu/drm/amd/pm/amdgpu_pm.c   |  2 +-
>  drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c| 10 ++
>  .../gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c  | 10 +-
>  drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c   | 12 ++--
>  5 files changed, 20 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index f0f7ed42ee7f..dfbf2f2db0de 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -2043,6 +2043,8 @@ static int amdgpu_device_ip_early_init(struct 
> amdgpu_device *adev)
> adev->pm.pp_feature = amdgpu_pp_feature_mask;
> if (amdgpu_sriov_vf(adev) || sched_policy == KFD_SCHED_POLICY_NO_HWS)
> adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
> +   if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_SIENNA_CICHLID)
> +   adev->pm.pp_feature &= ~PP_OVERDRIVE_MASK;
>
> for (i = 0; i < adev->num_ip_blocks; i++) {
> if ((amdgpu_ip_block_mask & (1 << i)) == 0) { diff --git 
> a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> index b770dd634ab6..1866cbaf70c3 100644
> --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> @@ -2167,7 +2167,7 @@ static ssize_t amdgpu_get_gpu_metrics(struct device 
> *dev,
>
>  static struct amdgpu_device_attr amdgpu_device_attrs[] = {
> AMDGPU_DEVICE_ATTR_RW(power_dpm_state,  
> ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
> -   AMDGPU_DEVICE_ATTR_RW(power_dpm_force_performance_level,
> ATTR_FLAG_BASIC),
> +   AMDGPU_DEVICE_ATTR_RW(power_dpm_force_performance_level,
> ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
> AMDGPU_DEVICE_ATTR_RO(pp_num_states,
> ATTR_FLAG_BASIC),
> AMDGPU_DEVICE_ATTR_RO(pp_cur_state, 
> ATTR_FLAG_BASIC),
> AMDGPU_DEVICE_ATTR_RW(pp_force_state,   
> ATTR_FLAG_BASIC),
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c 
> b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> index d143ef1b460b..7033d52eb4d0 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> @@ -612,10 +612,12 @@ static int smu_late_init(void *handle)
> return ret;
> }
>
> -   ret = smu_set_default_od_settings(smu);
> -   if (ret) {
> -   dev_err(adev->dev, "Failed to setup default OD settings!\n");
> -   return ret;
> +   if (smu->od_enabled) {
> +   ret = smu_set_default_od_settings(smu);
> +   if (ret) {
>

Re: [PATCH] drm/ttm: ioremap buffer according to TTM mem caching setting

[Christian König]

Hi Oak,


config: parisc-randconfig-r012-20210302 (attached as .config)


It's not the Intel driver build which fails here, but the build bot is 
just hosted by Intel.


The problem is that the parisc architecture doesn't defines the 
ioremap_cache() function.


I've looked at using memremap() instead of ioremap_cache(). The problem 
is that we do support architectures with the TTM as well as amndgpu code 
where the __iomem annotation is mandatory and correct.


Regards,
Christian.

Am 02.03.21 um 23:45 schrieb Zeng, Oak:


[AMD Official Use Only - Internal Distribution Only]


Hi Daniel, Thomas, Dan,

Does below message mean the calling ioremap_cache failed intel’s 
driver build? I can see both ioremap_cache and ioremap_wc are defined 
in arch/x86/mm/ioremap.c – why ioremap_wc doesn’t break intel driver’s 
build?


Are we supposed to use memremap (offset, size, MEMREMAP_WB) to replace 
ioremap_cache? When I read here https://lwn.net/Articles/653585/ I 
felt that ioremap_cache returns an address annotated with _iomem while 
memremap returns an address without __iomem annotation. In our use 
case, GPU memory is treated as UEFI SPM (specific purpose memory). I 
am not very sure whether memremap (thus no __iomem annotation) is the 
right thing to do. What I am sure is, we have tested ioremap_cache and 
it works fine on AMD system.


I will send out a test patch replacing ioremap_cache with ioremap_wc, 
to trigger Intel build robot to see whether it fails Intel build. I 
suppose it will not fail Intel build.


Regards,

Oak

*From:* Christian König 
*Sent:* Tuesday, March 2, 2021 6:31 AM
*To:* amd-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org; 
Daniel Vetter ; Dave Airlie ; 
Thomas Hellström (Intel) 
*Cc:* Zeng, Oak ; kbuild-...@lists.01.org; Kuehling, 
Felix ; Kasiviswanathan, Harish 
; Deucher, Alexander 
; Huang, JinHuiEric 
; Koenig, Christian 
*Subject:* Re: [PATCH] drm/ttm: ioremap buffer according to TTM mem 
caching setting


Hi guys,

adding the usual suspects direct. Does anybody of hand know how to 
check if an architecture supports ioremap_cache()?


For now we only need this on X86, but I would feel better if we don't 
use an #ifdef here.


Regards,
Christian.

Am 02.03.21 um 05:12 schrieb kernel test robot:

Hi Oak,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on drm-intel/for-linux-next]

[also build test ERROR on drm-tip/drm-tip linus/master v5.12-rc1 
next-20210302]

[cannot apply to tegra-drm/drm/tegra/for-next drm-exynos/exynos-drm-next 
drm/drm-next]

[If your patch is applied to the wrong git tree, kindly drop us a note.

And when submitting patch, we suggest to use '--base' as documented in

https://git-scm.com/docs/git-format-patch  
]


url:https://github.com/0day-ci/linux/commits/Oak-Zeng/drm-ttm-ioremap-buffer-according-to-TTM-mem-caching-setting/20210302-064500
  


base:   git://anongit.freedesktop.org/drm-intel for-linux-next

config: parisc-randconfig-r012-20210302 (attached as .config)

compiler: hppa-linux-gcc (GCC) 9.3.0

reproduce (this is a W=1 build):

     wgethttps://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross  

  -O ~/bin/make.cross

     chmod +x ~/bin/make.cross

     #https://github.com/0day-ci/linux/commit/225bb3711439ec559dd72ae5af8e62d34ea60a64  

Re: [PATCH] drm/ttm: ioremap buffer according to TTM mem caching setting

[Christian König]

Hi Thomas,

Am 03.03.21 um 09:49 schrieb Thomas Zimmermann:

Hi

Am 01.03.21 um 23:43 schrieb Oak Zeng:

If tbo.mem.bus.caching is cached, buffer is intended to be mapped
as cached from CPU. Map it with ioremap_cache.


Just a question for my understanding: This is on-device memory? 
Accessing device memory is usually slow. If that memory can be mapped 
with CPU caching enabled, access will roughly be as fast as for system 
memory?


There is still a penalty associated with accessing it from the CPU, but 
it is much faster (both lower latency as well as throughput) as 
traditional device memory accessed over PCIe.


Regards,
Christian.



Best regards
Thomas



This wasn't necessary before as device memory was never mapped
as cached from CPU side. It becomes necessary for aldebaran as
device memory is mapped cached from CPU.

Signed-off-by: Oak Zeng 
Reviewed-by: Christian Konig 
---
  drivers/gpu/drm/ttm/ttm_bo_util.c | 8 
  1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c 
b/drivers/gpu/drm/ttm/ttm_bo_util.c

index 031e581..8c65a13 100644
--- a/drivers/gpu/drm/ttm/ttm_bo_util.c
+++ b/drivers/gpu/drm/ttm/ttm_bo_util.c
@@ -91,6 +91,8 @@ static int ttm_resource_ioremap(struct ttm_device 
*bdev,

    if (mem->bus.caching == ttm_write_combined)
  addr = ioremap_wc(mem->bus.offset, bus_size);
+    else if (mem->bus.caching == ttm_cached)
+    addr = ioremap_cache(mem->bus.offset, bus_size);
  else
  addr = ioremap(mem->bus.offset, bus_size);
  if (!addr) {
@@ -372,6 +374,9 @@ static int ttm_bo_ioremap(struct 
ttm_buffer_object *bo,

  if (mem->bus.caching == ttm_write_combined)
  map->virtual = ioremap_wc(bo->mem.bus.offset + offset,
    size);
+    else if (mem->bus.caching == ttm_cached)
+    map->virtual = ioremap_cache(bo->mem.bus.offset + offset,
+  size);
  else
  map->virtual = ioremap(bo->mem.bus.offset + offset,
 size);
@@ -490,6 +495,9 @@ int ttm_bo_vmap(struct ttm_buffer_object *bo, 
struct dma_buf_map *map)

  else if (mem->bus.caching == ttm_write_combined)
  vaddr_iomem = ioremap_wc(mem->bus.offset,
   bo->base.size);
+    else if (mem->bus.caching == ttm_cached)
+    vaddr_iomem = ioremap_cache(mem->bus.offset,
+  bo->base.size);
  else
  vaddr_iomem = ioremap(mem->bus.offset, bo->base.size);




___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx


___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH v2 2/3] drm/amdgpu: introduce kfd user flag for amdgpu_bo

[Nirmoy Das]

Introduce a new flag for amdgpu_bo->flags to identify if
a BO is created by KFD.

v2: rename AMDGPU_GEM_USER_KFD -> AMDGPU_GEM_CREATE_KFD

Signed-off-by: Nirmoy Das 
---
 .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c  |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c   |  3 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c| 48 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.h|  3 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c   |  2 +-
 include/uapi/drm/amdgpu_drm.h |  5 ++
 6 files changed, 59 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index 89d0e4f7c6a8..57798707cd5f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -1227,7 +1227,7 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
bp.flags = alloc_flags;
bp.type = bo_type;
bp.resv = NULL;
-   ret = amdgpu_bo_create(adev, &bp, &bo);
+   ret = amdgpu_kfd_bo_create(adev, &bp, &bo);
if (ret) {
pr_debug("Failed to create BO on domain %s. ret %d\n",
domain_string(alloc_domain), ret);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 8e9b8a6e6ef0..e0ceeb32642c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -234,7 +234,8 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void 
*data,
  AMDGPU_GEM_CREATE_VRAM_CLEARED |
  AMDGPU_GEM_CREATE_VM_ALWAYS_VALID |
  AMDGPU_GEM_CREATE_EXPLICIT_SYNC |
- AMDGPU_GEM_CREATE_ENCRYPTED))
+ AMDGPU_GEM_CREATE_ENCRYPTED |
+ AMDGPU_GEM_CREATE_KFD))

return -EINVAL;

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 0bd22ed1dacf..1b41b4870c99 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -697,6 +697,52 @@ int amdgpu_bo_create(struct amdgpu_device *adev,
return r;
 }

+/**
+ * amdgpu_kfd_bo_create - create an &amdgpu_bo buffer object with kfd user flag
+ * @adev: amdgpu device object
+ * @bp: parameters to be used for the buffer object
+ * @bo_ptr: pointer to the buffer object pointer
+ *
+ * Creates an &amdgpu_bo buffer object; and if requested, also creates a
+ * shadow object.
+ * Shadow object is used to backup the original buffer object, and is always
+ * in GTT.
+ *
+ * Returns:
+ * 0 for success or a negative error code on failure.
+ */
+
+int amdgpu_kfd_bo_create(struct amdgpu_device *adev,
+struct amdgpu_bo_param *bp,
+struct amdgpu_bo **bo_ptr)
+{
+   u64 flags = bp->flags;
+   int r;
+
+   bp->flags = bp->flags & ~AMDGPU_GEM_CREATE_SHADOW;
+   bp->flags = bp->flags | AMDGPU_GEM_CREATE_KFD;
+   r = amdgpu_bo_do_create(adev, bp, bo_ptr);
+   if (r)
+   return r;
+
+   if ((flags & AMDGPU_GEM_CREATE_SHADOW) && !(adev->flags & AMD_IS_APU)) {
+   if (!bp->resv)
+   WARN_ON(dma_resv_lock((*bo_ptr)->tbo.base.resv,
+   NULL));
+
+   r = amdgpu_bo_create_shadow(adev, bp->size, *bo_ptr);
+
+   if (!bp->resv)
+   dma_resv_unlock((*bo_ptr)->tbo.base.resv);
+
+   if (r)
+   amdgpu_bo_unref(bo_ptr);
+   }
+
+   return r;
+}
+
+
 /**
  * amdgpu_bo_validate - validate an &amdgpu_bo buffer object
  * @bo: pointer to the buffer object
@@ -1309,7 +1355,7 @@ void amdgpu_bo_release_notify(struct ttm_buffer_object 
*bo)

abo = ttm_to_amdgpu_bo(bo);

-   if (abo->kfd_bo)
+   if (abo->flags & AMDGPU_GEM_CREATE_KFD)
amdgpu_amdkfd_unreserve_memory_limit(abo);

/* We only remove the fence if the resv has individualized. */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
index 8cd96c9330dd..665ee0015f06 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
@@ -245,6 +245,9 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, 
u32 domain);
 int amdgpu_bo_create(struct amdgpu_device *adev,
 struct amdgpu_bo_param *bp,
 struct amdgpu_bo **bo_ptr);
+int amdgpu_kfd_bo_create(struct amdgpu_device *adev,
+struct amdgpu_bo_param *bp,
+struct amdgpu_bo **bo_ptr);
 int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
  unsigned long size, int align,
  u32 domain, struct amdgpu_bo **bo_ptr,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/

[PATCH v2 3/3] drm/amdgpu: drm/amdkfd: add amdgpu_kfd_bo struct

[Nirmoy Das]

Implement a new struct based on amdgpu_bo base class
for BOs created by kfd device so that kfd related memeber
of amdgpu_bo can be moved there.

v2: rename AMDGPU_GEM_USER_KFD -> AMDGPU_GEM_CREATE_KFD

Signed-off-by: Nirmoy Das 
---
 .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c  | 10 --
 drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c|  3 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c| 32 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.h|  8 -
 4 files changed, 40 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index 57798707cd5f..1f52ae4de609 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -1152,6 +1152,7 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
struct sg_table *sg = NULL;
uint64_t user_addr = 0;
struct amdgpu_bo *bo;
+   struct amdgpu_kfd_bo *kbo;
struct amdgpu_bo_param bp;
u32 domain, alloc_domain;
u64 alloc_flags;
@@ -1227,17 +1228,20 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
bp.flags = alloc_flags;
bp.type = bo_type;
bp.resv = NULL;
-   ret = amdgpu_kfd_bo_create(adev, &bp, &bo);
+   ret = amdgpu_kfd_bo_create(adev, &bp, &kbo);
if (ret) {
pr_debug("Failed to create BO on domain %s. ret %d\n",
domain_string(alloc_domain), ret);
goto err_bo_create;
}
+
+   bo = &kbo->bo;
if (bo_type == ttm_bo_type_sg) {
bo->tbo.sg = sg;
bo->tbo.ttm->sg = sg;
}
-   bo->kfd_bo = *mem;
+
+   kbo->kfd_bo = *mem;
(*mem)->bo = bo;
if (user_addr)
bo->flags |= AMDGPU_AMDKFD_USERPTR_BO;
@@ -1261,7 +1265,7 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(

 allocate_init_user_pages_failed:
remove_kgd_mem_from_kfd_bo_list(*mem, avm->process_info);
-   amdgpu_bo_unref(&bo);
+   amdgpu_kfd_bo_unref(&kbo);
/* Don't unreserve system mem limit twice */
goto err_reserve_limit;
 err_bo_create:
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
index 1da67cf812b1..eaaf4940abcb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
@@ -102,6 +102,7 @@ static bool amdgpu_mn_invalidate_hsa(struct 
mmu_interval_notifier *mni,
 unsigned long cur_seq)
 {
struct amdgpu_bo *bo = container_of(mni, struct amdgpu_bo, notifier);
+   struct amdgpu_kfd_bo *kbo = container_of(bo, struct amdgpu_kfd_bo, bo);
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);

if (!mmu_notifier_range_blockable(range))
@@ -111,7 +112,7 @@ static bool amdgpu_mn_invalidate_hsa(struct 
mmu_interval_notifier *mni,

mmu_interval_set_seq(mni, cur_seq);

-   amdgpu_amdkfd_evict_userptr(bo->kfd_bo, bo->notifier.mm);
+   amdgpu_amdkfd_evict_userptr(kbo->kfd_bo, bo->notifier.mm);
mutex_unlock(&adev->notifier_lock);

return true;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 1b41b4870c99..787eb99119a2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -551,8 +551,10 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev,

acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size,
   sizeof(struct amdgpu_bo));
+   if (bp->bo_ptr_size < sizeof(struct amdgpu_bo))
+   bp->bo_ptr_size = sizeof(struct amdgpu_bo);

-   bo = kzalloc(sizeof(struct amdgpu_bo), GFP_KERNEL);
+   bo = kzalloc(bp->bo_ptr_size, GFP_KERNEL);
if (bo == NULL)
return -ENOMEM;
drm_gem_private_object_init(adev_to_drm(adev), &bo->tbo.base, size);
@@ -714,35 +716,37 @@ int amdgpu_bo_create(struct amdgpu_device *adev,

 int amdgpu_kfd_bo_create(struct amdgpu_device *adev,
 struct amdgpu_bo_param *bp,
-struct amdgpu_bo **bo_ptr)
+struct amdgpu_kfd_bo **kfd_bo_ptr)
 {
+   struct amdgpu_bo *bo_ptr;
u64 flags = bp->flags;
int r;

bp->flags = bp->flags & ~AMDGPU_GEM_CREATE_SHADOW;
bp->flags = bp->flags | AMDGPU_GEM_CREATE_KFD;
-   r = amdgpu_bo_do_create(adev, bp, bo_ptr);
+   bp->bo_ptr_size = sizeof(struct amdgpu_kfd_bo);
+   r = amdgpu_bo_do_create(adev, bp, &bo_ptr);
if (r)
return r;

+   *kfd_bo_ptr = (struct amdgpu_kfd_bo *)bo_ptr;
if ((flags & AMDGPU_GEM_CREATE_SHADOW) && !(adev->flags & AMD_IS_APU)) {
if (!bp->resv)
-   WARN_ON(dma_resv_lock((*bo_ptr)->tbo.base.resv,
+   WARN_ON(dma_resv_lock((*kfd_bo_ptr)->bo.tbo.base.res

[PATCH 1/3] drm/amdgpu: drm/amdkfd: split amdgpu_mn_register

[Nirmoy Das]

Split amdgpu_mn_register() into two functions to avoid unnecessary
bo->kfd_bo check.

Signed-off-by: Nirmoy Das 
---
 .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c  |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c| 21 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h|  8 +++
 3 files changed, 26 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index 99ad4e1d0896..89d0e4f7c6a8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -571,7 +571,7 @@ static int init_user_pages(struct kgd_mem *mem, uint64_t 
user_addr)
goto out;
}
 
-   ret = amdgpu_mn_register(bo, user_addr);
+   ret = amdgpu_mn_register_hsa(bo, user_addr);
if (ret) {
pr_err("%s: Failed to register MMU notifier: %d\n",
   __func__, ret);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
index 828b5167ff12..1da67cf812b1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
@@ -132,15 +132,28 @@ static const struct mmu_interval_notifier_ops 
amdgpu_mn_hsa_ops = {
  */
 int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
 {
-   if (bo->kfd_bo)
-   return mmu_interval_notifier_insert(&bo->notifier, current->mm,
-   addr, amdgpu_bo_size(bo),
-   &amdgpu_mn_hsa_ops);
return mmu_interval_notifier_insert(&bo->notifier, current->mm, addr,
amdgpu_bo_size(bo),
&amdgpu_mn_gfx_ops);
 }
 
+/**
+ * amdgpu_mn_register_hsa - register a BO for notifier updates
+ *
+ * @bo: amdgpu buffer object
+ * @addr: userptr addr we should monitor
+ *
+ * Registers a mmu_notifier for the given kfd BO at the specified address.
+ * Returns 0 on success, -ERRNO if anything goes wrong.
+ */
+
+int amdgpu_mn_register_hsa(struct amdgpu_bo *bo, unsigned long addr)
+{
+   return mmu_interval_notifier_insert(&bo->notifier, current->mm, addr,
+   amdgpu_bo_size(bo),
+   &amdgpu_mn_hsa_ops);
+}
+
 /**
  * amdgpu_mn_unregister - unregister a BO for notifier updates
  *
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h
index a292238f75eb..565ee5a0a3ad 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h
@@ -32,6 +32,7 @@
 
 #if defined(CONFIG_HMM_MIRROR)
 int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr);
+int amdgpu_mn_register_hsa(struct amdgpu_bo *bo, unsigned long addr);
 void amdgpu_mn_unregister(struct amdgpu_bo *bo);
 #else
 static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
@@ -40,6 +41,13 @@ static inline int amdgpu_mn_register(struct amdgpu_bo *bo, 
unsigned long addr)
  "add CONFIG_ZONE_DEVICE=y in config file to fix this\n");
return -ENODEV;
 }
+
+static inline int amdgpu_mn_register_hsa(struct amdgpu_bo *bo, unsigned long 
addr)
+{
+   DRM_WARN_ONCE("HMM_MIRROR kernel config option is not enabled, "
+ "add CONFIG_ZONE_DEVICE=y in config file to fix this\n");
+   return -ENODEV;
+}
 static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
 #endif
 
-- 
2.30.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: lots of bugreports about a kernel-backtrace starting with amdgpu_dm_backlight_update_status

[Michel Dänzer]

On 2021-02-17 3:56 p.m., Hans de Goede wrote:

Hi All,

Fedora has a (opt-in) system to automatically collect backtraces from
software crashing on users systems.

This includes collecting kernel backtraces (including once triggered by
WARN macros) while looking a the top 10 of the most reported backtrace
during the last 2 weeks report from ABRT:
https://retrace.fedoraproject.org/faf/problems/

I noticed the following backtrace:
https://retrace.fedoraproject.org/faf/problems/13904/

which has been reported 16 times by Fedora users who have opted-in
during the last 14 days.


Given these numbers, the lack of response is puzzling. Adding some DC folks, in 
case they missed it before.



The ABRT symbol resolution points to amdgpu_dm_backlight_update_status:

1   
amdgpu_dm_backlight_update_status
amdgpu  0xb4
2   
amdgpu_dm_backlight_update_status
amdgpu  0xb4
3   
amdgpu_dm_backlight_update_status
amdgpu  0xb4
4   
amdgpu_dm_backlight_update_status
amdgpu  0xb4
5   
? amdgpu_dm_backlight_update_status
amdgpu  0xb4
6   
amdgpu_dm_backlight_update_status
amdgpu  0xb4
7   
amdgpu_dm_backlight_update_status
amdgpu  0xb4
8   
drm_sched_job_timedout
gpu_sched   drivers/gpu/drm/scheduler/sched_main.c  289


But the backtrace from dmesg points to something else:

RIP: 0010:dcn10_get_dig_frontend+0x76/0xb0 [amdgpu]
Code: 39 44 89 c0 48 83 c4 08 c3 41 b8 05 00 00 00 83 f8 20 74 ed 41 b8 06 00 00 00 
83 f8 40 74 e2 41 b8 04 00 00 00 83 f8 10 74 d7 <0f> 0b 41 b8 ff ff ff ff 48 83 
c4 08 44 89 c0 c3 45 31 c0 83 f8 01
RSP: 0018:a376c2dffca8 EFLAGS: 00210297
RAX:  RBX: 8ecf6b76 RCX: 0008
RDX:  RSI: 596f RDI: 8ecf6db2
RBP: 8ecf6a187000 R08:  R09: 8ecf6f88fc00
R10: 0001 R11: 0006 R12: 8ecf727ec200
R13: 0006 R14: 8ecf6f982800 R15: 8ecf6e749200
FS:  () GS:8ecf7e9c() knlGS:
CS:  0010 DS:  ES:  CR0: 80050033
CR2: 7fb5fb4a8000 CR3: 000356446000 CR4: 003506e0
Call Trace:
  dcn10_init_hw+0x6ed/0x930 [amdgpu]
  dc_set_power_state+0xf5/0x140 [amdgpu]
  dm_resume+0x328/0x500 [amdgpu]
  amdgpu_device_ip_resume_phase2+0x52/0xb0 [amdgpu]
  ? amdgpu_device_fw_loading+0x9f/0x110 [amdgpu]
  amdgpu_device_gpu_recover.cold+0x8c1/0xf62 [amdgpu]
  amdgpu_job_timedout+0x11c/0x140 [amdgpu]
  drm_sched_job_timedout+0x72/0xf0 [gpu_sched]
  process_one_work+0x1b4/0x370


There also is this bugzilla about this:
https://bugzilla.redhat.com/show_bug.cgi?id=1929746
from today


This one seems to have restricted access.



And a whole bunch of others:
https://bugzilla.redhat.com/buglist.cgi?quicksearch=amdgpu_dm_backlight_update_status


https://gitlab.freedesktop.org/drm/amd/-/issues/1337 looks related as well.


--
Earthling Michel Dänzer   |   https://redhat.com
Libre software enthusiast | Mesa and X developer
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm/ttm: ioremap buffer according to TTM mem caching setting

[Thomas Zimmermann]

Hi

Am 01.03.21 um 23:43 schrieb Oak Zeng:

If tbo.mem.bus.caching is cached, buffer is intended to be mapped
as cached from CPU. Map it with ioremap_cache.


Just a question for my understanding: This is on-device memory? 
Accessing device memory is usually slow. If that memory can be mapped 
with CPU caching enabled, access will roughly be as fast as for system 
memory?


Best regards
Thomas



This wasn't necessary before as device memory was never mapped
as cached from CPU side. It becomes necessary for aldebaran as
device memory is mapped cached from CPU.

Signed-off-by: Oak Zeng 
Reviewed-by: Christian Konig 
---
  drivers/gpu/drm/ttm/ttm_bo_util.c | 8 
  1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c 
b/drivers/gpu/drm/ttm/ttm_bo_util.c
index 031e581..8c65a13 100644
--- a/drivers/gpu/drm/ttm/ttm_bo_util.c
+++ b/drivers/gpu/drm/ttm/ttm_bo_util.c
@@ -91,6 +91,8 @@ static int ttm_resource_ioremap(struct ttm_device *bdev,
  
  		if (mem->bus.caching == ttm_write_combined)

addr = ioremap_wc(mem->bus.offset, bus_size);
+   else if (mem->bus.caching == ttm_cached)
+   addr = ioremap_cache(mem->bus.offset, bus_size);
else
addr = ioremap(mem->bus.offset, bus_size);
if (!addr) {
@@ -372,6 +374,9 @@ static int ttm_bo_ioremap(struct ttm_buffer_object *bo,
if (mem->bus.caching == ttm_write_combined)
map->virtual = ioremap_wc(bo->mem.bus.offset + offset,
  size);
+   else if (mem->bus.caching == ttm_cached)
+   map->virtual = ioremap_cache(bo->mem.bus.offset + 
offset,
+ size);
else
map->virtual = ioremap(bo->mem.bus.offset + offset,
   size);
@@ -490,6 +495,9 @@ int ttm_bo_vmap(struct ttm_buffer_object *bo, struct 
dma_buf_map *map)
else if (mem->bus.caching == ttm_write_combined)
vaddr_iomem = ioremap_wc(mem->bus.offset,
 bo->base.size);
+   else if (mem->bus.caching == ttm_cached)
+   vaddr_iomem = ioremap_cache(mem->bus.offset,
+ bo->base.size);
else
vaddr_iomem = ioremap(mem->bus.offset, bo->base.size);
  



--
Thomas Zimmermann
Graphics Driver Developer
SUSE Software Solutions Germany GmbH
Maxfeldstr. 5, 90409 Nürnberg, Germany
(HRB 36809, AG Nürnberg)
Geschäftsführer: Felix Imendörffer



OpenPGP_signature
Description: OpenPGP digital signature
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx