RE: [PATCH 2/2] drm/amd/pm: Use BACO reset arg 0 on XGMI configuration
[AMD Public Use]
Series is
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: amd-gfx On Behalf Of shaoyunl
Sent: Tuesday, March 16, 2021 00:01
To: amd-gfx@lists.freedesktop.org
Cc: Liu, Shaoyun
Subject: [PATCH 2/2] drm/amd/pm: Use BACO reset arg 0 on XGMI configuration
With arg 1 BACO reset, it will try to reload the SMU FW after reset.
This might failed if driver already in a pending reset status during probe
period.
Arg 0 reset will bring asic back to a clean state and driver will re-init
everythign including SMU FW
Signed-off-by: shaoyunl
Change-Id: I6df90d963e259dcf1df8fe3716cdf52681202162
---
drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
index 635bd5da2133..0d137af1a78a 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
@@ -1530,7 +1530,7 @@ int smu_v11_0_baco_set_state(struct smu_context *smu,
enum smu_baco_state state)
NULL);
break;
default:
- if (!ras || !ras->supported) {
+ if (!ras || !ras->supported ||
adev->gmc.xgmi.pending_reset) {
if (adev->asic_type == CHIP_ARCTURUS) {
data = RREG32_SOC15(THM, 0,
mmTHM_BACO_CNTL_ARCT);
data |= 0x8000;
--
2.17.1
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Re: [PATCH] drm/amd/pm: fix workload mismatch on vega10
[AMD Official Use Only - Internal Distribution Only] Reviewed-by: Kevin Wang Best Regards. Kevin From: amd-gfx on behalf of Kenneth Feng Sent: Tuesday, March 16, 2021 10:29 AM To: amd-gfx@lists.freedesktop.org Cc: Feng, Kenneth Subject: [PATCH] drm/amd/pm: fix workload mismatch on vega10 Workload number mapped to the correct one. This issue is only on vega10. Signed-off-by: Kenneth Feng --- drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c index f5a32654cde7..31c61ac3bd5e 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c @@ -5160,7 +5160,7 @@ static int vega10_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, ui out: smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetWorkloadMask, - 1 << power_profile_mode, + (!power_profile_mode) ? 0 : 1 << (power_profile_mode - 1), NULL); hwmgr->power_profile_mode = power_profile_mode; -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfxdata=04%7C01%7CKevin1.Wang%40amd.com%7C42f8a4ebbae1442d2b4a08d8e8236ae1%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637514586124157424%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000sdata=IsJaWeIqqZxzNcPL5wCOC1AvwDUoDHB%2BLRPkjdvPqng%3Dreserved=0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amd/pm: fix workload mismatch on vega10
Workload number mapped to the correct one. This issue is only on vega10. Signed-off-by: Kenneth Feng --- drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c index f5a32654cde7..31c61ac3bd5e 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c @@ -5160,7 +5160,7 @@ static int vega10_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, ui out: smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetWorkloadMask, - 1 << power_profile_mode, + (!power_profile_mode) ? 0 : 1 << (power_profile_mode - 1), NULL); hwmgr->power_profile_mode = power_profile_mode; -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdkfd: Fix UBSAN shift-out-of-bounds warning
On Sat, 2021-03-06 at 03:55 +, Jacob, Anson wrote:
> [AMD Public Use]
>
> Thanks Lyude for testing the patch.
>
> Are you referring to this issue [1] ?
>
> Is it reproducible after applying this patch as well ?
Yes I am - and yeah, if you're talking about the patch you originally asked me
to try then yes- I'm still able to reproduce it with that patch applied
>
> [1] https://gitlab.freedesktop.org/drm/amd/-/issues/1473
>
> -- Anson
> From: Lyude Paul
> Sent: Friday, March 5, 2021 6:08 PM
> To: Jacob, Anson ; amd-gfx@lists.freedesktop.org g...@lists.freedesktop.org>
> Cc: Deucher, Alexander ; Kuehling, Felix
>
> Subject: Re: [PATCH] drm/amdkfd: Fix UBSAN shift-out-of-bounds warning
> Tested-by: Lyude Paul
>
> That just leaves the KASAN error from read_indirect_azalia_reg, thanks for the
> fix!
>
> On Thu, 2021-03-04 at 15:08 -0500, Anson Jacob wrote:
> > If get_num_sdma_queues or get_num_xgmi_sdma_queues is 0, we end up
> > doing a shift operation where the number of bits shifted equals
> > number of bits in the operand. This behaviour is undefined.
> >
> > Set num_sdma_queues or num_xgmi_sdma_queues to ULLONG_MAX, if the
> > count is >= number of bits in the operand.
> >
> > Bug:
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgitlab.freedesktop.org%2Fdrm%2Famd%2F-%2Fissues%2F1472data=04%7C01%7Canson.jacob%40amd.com%7Ce9ea7130bcd945a194aa08d8e02ba9f8%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637505826204096667%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000sdata=GEyObPt%2FnEeU9Y7K2I30RS1TBMGbbUneQ6hWkR7pJLM%3Dreserved=0
> > Reported-by: Lyude Paul
> > Signed-off-by: Anson Jacob
> > Reviewed-by: Alex Deucher
> > Reviewed-by: Felix Kuehling
> > ---
> > .../drm/amd/amdkfd/kfd_device_queue_manager.c | 17 +++--
> > 1 file changed, 15 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> > b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> > index c37e9c4b1fb4..e7a3c496237f 100644
> > --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> > +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> > @@ -1128,6 +1128,9 @@ static int set_sched_resources(struct
> > device_queue_manager *dqm)
> >
> > static int initialize_cpsch(struct device_queue_manager *dqm)
> > {
> > + uint64_t num_sdma_queues;
> > + uint64_t num_xgmi_sdma_queues;
> > +
> > pr_debug("num of pipes: %d\n", get_pipes_per_mec(dqm));
> >
> > mutex_init(>lock_hidden);
> > @@ -1136,8 +1139,18 @@ static int initialize_cpsch(struct
> device_queue_manager
> > *dqm)
> > dqm->active_cp_queue_count = 0;
> > dqm->gws_queue_count = 0;
> > dqm->active_runlist = false;
> > - dqm->sdma_bitmap = ~0ULL >> (64 - get_num_sdma_queues(dqm));
> > - dqm->xgmi_sdma_bitmap = ~0ULL >> (64 -
> get_num_xgmi_sdma_queues(dqm));
> > +
> > + num_sdma_queues = get_num_sdma_queues(dqm);
> > + if (num_sdma_queues >= BITS_PER_TYPE(dqm->sdma_bitmap))
> > + dqm->sdma_bitmap = ULLONG_MAX;
> > + else
> > + dqm->sdma_bitmap = (BIT_ULL(num_sdma_queues) - 1);
> > +
> > + num_xgmi_sdma_queues = get_num_xgmi_sdma_queues(dqm);
> > + if (num_xgmi_sdma_queues >= BITS_PER_TYPE(dqm->xgmi_sdma_bitmap))
> > + dqm->xgmi_sdma_bitmap = ULLONG_MAX;
> > + else
> > + dqm->xgmi_sdma_bitmap = (BIT_ULL(num_xgmi_sdma_queues) - 1);
> >
> > INIT_WORK(>hw_exception_work, kfd_process_hw_exception);
> >
>
--
Sincerely,
Lyude Paul (she/her)
Software Engineer at Red Hat
Note: I deal with a lot of emails and have a lot of bugs on my plate. If you've
asked me a question, are waiting for a review/merge on a patch, etc. and I
haven't responded in a while, please feel free to send me another email to check
on my status. I don't bite!
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Re: [PATCH] drm/amdgpu/ttm: fix ifdefs for non-x86
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Oak Zeng
Regards,
Oak
On 2021-03-15, 3:39 PM, "amd-gfx on behalf of Alex Deucher"
wrote:
The else clause needs to be CONFIG_64BIT not CONFIG_X86.
Fixes: e98f250bddb5 ("drm/amdgpu: fix compile error on architecture s390")
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 158c987696ff..6d5cf0525325 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1731,12 +1731,14 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
/* Change the size here instead of the init above so only lpfn is affected
*/
amdgpu_ttm_set_buffer_funcs_status(adev, false);
+#ifdef CONFIG_64BIT
#ifdef CONFIG_X86
if (adev->gmc.xgmi.connected_to_cpu)
adev->mman.aper_base_kaddr = ioremap_cache(adev->gmc.aper_base,
adev->gmc.visible_vram_size);
else
+#endif
adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base,
adev->gmc.visible_vram_size);
#endif
--
2.30.2
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Re: [PATCH] drm/amdgpu/ttm: fix ifdefs for non-x86
Reviewed-by: Nirmoy Das
On 3/15/21 8:38 PM, Alex Deucher wrote:
The else clause needs to be CONFIG_64BIT not CONFIG_X86.
Fixes: e98f250bddb5 ("drm/amdgpu: fix compile error on architecture s390")
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 158c987696ff..6d5cf0525325 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1731,12 +1731,14 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
/* Change the size here instead of the init above so only lpfn is affected */
amdgpu_ttm_set_buffer_funcs_status(adev, false);
+#ifdef CONFIG_64BIT
#ifdef CONFIG_X86
if (adev->gmc.xgmi.connected_to_cpu)
adev->mman.aper_base_kaddr = ioremap_cache(adev->gmc.aper_base,
adev->gmc.visible_vram_size);
else
+#endif
adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base,
adev->gmc.visible_vram_size);
#endif
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RE: [PATCH 1/2] drm/amdgpu: fix compile error on architecture s390
[AMD Public Use] > -Original Message- > From: amd-gfx On Behalf Of > Deucher, Alexander > Sent: Monday, March 15, 2021 3:24 PM > To: Das, Nirmoy ; Zeng, Oak > ; amd-gfx@lists.freedesktop.org > Subject: RE: [PATCH 1/2] drm/amdgpu: fix compile error on architecture s390 > > [AMD Public Use] > > > -Original Message- > > From: Das, Nirmoy > > Sent: Monday, March 15, 2021 3:17 PM > > To: Deucher, Alexander ; Das, Nirmoy > > ; Zeng, Oak ; amd- > > g...@lists.freedesktop.org > > Subject: Re: [PATCH 1/2] drm/amdgpu: fix compile error on architecture > > s390 > > > > Hi Alex, > > > > On 3/15/21 7:46 PM, Deucher, Alexander wrote: > > > [AMD Public Use] > > > > > >> -Original Message- > > >> From: amd-gfx On Behalf Of > > >> Nirmoy > > >> Sent: Monday, March 15, 2021 2:43 PM > > >> To: Zeng, Oak ; amd-gfx@lists.freedesktop.org > > >> Subject: Re: [PATCH 1/2] drm/amdgpu: fix compile error on > > >> architecture s390 > > >> > > >> Wouldn't this restrict amdgpu for only x86 platform? > > > This particular case will only be x86. > > > > > > If I understand correctly, we map all the VRAM at startup to avoid > > > > mapping each BOs. Can't we do that for other Archs ? > > You are right. The else should be CONFIG_64BIT not CONFIG_X86. @Zeng, > Oak can you fix this up? Just sent out the fix. Alex > > Alex > > > > > > > > Nirmoy > > > > > > > > > > Alex > > > > > >> On 3/11/21 4:29 AM, Oak Zeng wrote: > > >>> ioremap_cache is not supported on some architecture such as s390. > > >>> Put the codes into a #ifdef to fix some compile error reported by > > >>> test robot. > > >>> > > >>> Signed-off-by: Oak Zeng > > >>> Reported-by: Kernel test robot > > >>> --- > > >>>drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +- > > >>>1 file changed, 1 insertion(+), 1 deletion(-) > > >>> > > >>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c > > >>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c > > >>> index 37751e7..1091585 100644 > > >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c > > >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c > > >>> @@ -1817,7 +1817,7 @@ int amdgpu_ttm_init(struct amdgpu_device > > >> *adev) > > >>> /* Change the size here instead of the init above so only lpfn > > >>> is > > >> affected */ > > >>> amdgpu_ttm_set_buffer_funcs_status(adev, false); -#ifdef > > >>> CONFIG_64BIT > > >>> +#ifdef CONFIG_X86 > > >>> if (adev->gmc.xgmi.connected_to_cpu) > > >>> adev->mman.aper_base_kaddr = > ioremap_cache(adev- > > gmc.aper_base, > > >>> adev->gmc.visible_vram_size); > > >> ___ > > >> amd-gfx mailing list > > >> amd-gfx@lists.freedesktop.org > > >> > > > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists. > > >> freedesktop.org%2Fmailman%2Flistinfo%2Famd- > > >> > > > gfxdata=04%7C01%7Calexander.deucher%40amd.com%7C6fab18a743 > > >> > > > c84b8abbd008d8e7e21e10%7C3dd8961fe4884e608e11a82d994e183d%7C0%7 > > >> > > > C0%7C637514305648085244%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4w > > >> > > > LjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000 > > >> > > > p;sdata=KLYRSc45rllptRvyiOF18qA9IFt5zAGXL1zsHasgdLs%3Dreserved > > >> =0 > ___ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists. > freedesktop.org%2Fmailman%2Flistinfo%2Famd- > gfxdata=04%7C01%7Calexander.deucher%40amd.com%7Cb8ba85a6c5 > 2449ad7ea908d8e7e7f43e%7C3dd8961fe4884e608e11a82d994e183d%7C0%7 > C0%7C637514330707623225%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4w > LjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000 > p;sdata=k0wrS%2BIRR7D%2B7%2FA4S%2B%2F3Hcrb6VWJueVibaFaKlStNic%3 > Dreserved=0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu/ttm: fix ifdefs for non-x86
The else clause needs to be CONFIG_64BIT not CONFIG_X86.
Fixes: e98f250bddb5 ("drm/amdgpu: fix compile error on architecture s390")
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 158c987696ff..6d5cf0525325 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1731,12 +1731,14 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
/* Change the size here instead of the init above so only lpfn is
affected */
amdgpu_ttm_set_buffer_funcs_status(adev, false);
+#ifdef CONFIG_64BIT
#ifdef CONFIG_X86
if (adev->gmc.xgmi.connected_to_cpu)
adev->mman.aper_base_kaddr = ioremap_cache(adev->gmc.aper_base,
adev->gmc.visible_vram_size);
else
+#endif
adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base,
adev->gmc.visible_vram_size);
#endif
--
2.30.2
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RE: [PATCH 1/2] drm/amdgpu: fix compile error on architecture s390
[AMD Public Use] > -Original Message- > From: Das, Nirmoy > Sent: Monday, March 15, 2021 3:17 PM > To: Deucher, Alexander ; Das, Nirmoy > ; Zeng, Oak ; amd- > g...@lists.freedesktop.org > Subject: Re: [PATCH 1/2] drm/amdgpu: fix compile error on architecture s390 > > Hi Alex, > > On 3/15/21 7:46 PM, Deucher, Alexander wrote: > > [AMD Public Use] > > > >> -Original Message- > >> From: amd-gfx On Behalf Of > >> Nirmoy > >> Sent: Monday, March 15, 2021 2:43 PM > >> To: Zeng, Oak ; amd-gfx@lists.freedesktop.org > >> Subject: Re: [PATCH 1/2] drm/amdgpu: fix compile error on > >> architecture s390 > >> > >> Wouldn't this restrict amdgpu for only x86 platform? > > This particular case will only be x86. > > > If I understand correctly, we map all the VRAM at startup to avoid > > mapping each BOs. Can't we do that for other Archs ? You are right. The else should be CONFIG_64BIT not CONFIG_X86. @Zeng, Oak can you fix this up? Alex > > > Nirmoy > > > > > > Alex > > > >> On 3/11/21 4:29 AM, Oak Zeng wrote: > >>> ioremap_cache is not supported on some architecture such as s390. > >>> Put the codes into a #ifdef to fix some compile error reported by > >>> test robot. > >>> > >>> Signed-off-by: Oak Zeng > >>> Reported-by: Kernel test robot > >>> --- > >>>drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +- > >>>1 file changed, 1 insertion(+), 1 deletion(-) > >>> > >>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c > >>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c > >>> index 37751e7..1091585 100644 > >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c > >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c > >>> @@ -1817,7 +1817,7 @@ int amdgpu_ttm_init(struct amdgpu_device > >> *adev) > >>> /* Change the size here instead of the init above so only lpfn > >>> is > >> affected */ > >>> amdgpu_ttm_set_buffer_funcs_status(adev, false); -#ifdef > >>> CONFIG_64BIT > >>> +#ifdef CONFIG_X86 > >>> if (adev->gmc.xgmi.connected_to_cpu) > >>> adev->mman.aper_base_kaddr = ioremap_cache(adev- > gmc.aper_base, > >>> adev->gmc.visible_vram_size); > >> ___ > >> amd-gfx mailing list > >> amd-gfx@lists.freedesktop.org > >> > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists. > >> freedesktop.org%2Fmailman%2Flistinfo%2Famd- > >> > gfxdata=04%7C01%7Calexander.deucher%40amd.com%7C6fab18a743 > >> > c84b8abbd008d8e7e21e10%7C3dd8961fe4884e608e11a82d994e183d%7C0%7 > >> > C0%7C637514305648085244%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4w > >> > LjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000 > >> > p;sdata=KLYRSc45rllptRvyiOF18qA9IFt5zAGXL1zsHasgdLs%3Dreserved > >> =0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 1/2] drm/amdgpu: fix compile error on architecture s390
Hi Alex, On 3/15/21 7:46 PM, Deucher, Alexander wrote: [AMD Public Use] -Original Message- From: amd-gfx On Behalf Of Nirmoy Sent: Monday, March 15, 2021 2:43 PM To: Zeng, Oak ; amd-gfx@lists.freedesktop.org Subject: Re: [PATCH 1/2] drm/amdgpu: fix compile error on architecture s390 Wouldn't this restrict amdgpu for only x86 platform? This particular case will only be x86. If I understand correctly, we map all the VRAM at startup to avoid mapping each BOs. Can't we do that for other Archs ? Nirmoy Alex On 3/11/21 4:29 AM, Oak Zeng wrote: ioremap_cache is not supported on some architecture such as s390. Put the codes into a #ifdef to fix some compile error reported by test robot. Signed-off-by: Oak Zeng Reported-by: Kernel test robot --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 37751e7..1091585 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -1817,7 +1817,7 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) /* Change the size here instead of the init above so only lpfn is affected */ amdgpu_ttm_set_buffer_funcs_status(adev, false); -#ifdef CONFIG_64BIT +#ifdef CONFIG_X86 if (adev->gmc.xgmi.connected_to_cpu) adev->mman.aper_base_kaddr = ioremap_cache(adev- gmc.aper_base, adev->gmc.visible_vram_size); ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists. freedesktop.org%2Fmailman%2Flistinfo%2Famd- gfxdata=04%7C01%7Calexander.deucher%40amd.com%7C6fab18a743 c84b8abbd008d8e7e21e10%7C3dd8961fe4884e608e11a82d994e183d%7C0%7 C0%7C637514305648085244%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4w LjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000 p;sdata=KLYRSc45rllptRvyiOF18qA9IFt5zAGXL1zsHasgdLs%3Dreserved =0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu/display: drop unused DCN3.01 functions
Reviewed-by: Nirmoy Das
On 3/15/21 8:12 PM, Alex Deucher wrote:
No longer used. Drop to avoid warnings.
Fixes: e0e33d4006aa ("[why] the dcn301_calculate_wm_and_dl() calculation exposed a
issue - switch to dcn30 version for now. still need to follow up with dcn301 watermark
updates version.")
Signed-off-by: Alex Deucher
Cc: Charles Sun
Cc: Nikola Cornij
---
.../amd/display/dc/dcn301/dcn301_resource.c | 94 ---
1 file changed, 94 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
index 22ffd7c64bde..c109d0cdab42 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
@@ -1621,100 +1621,6 @@ static void dcn301_update_bw_bounding_box(struct dc
*dc, struct clk_bw_params *b
dml_init_instance(>dml, _01_soc, _01_ip,
DML_PROJECT_DCN30);
}
-static void calculate_wm_set_for_vlevel(
- int vlevel,
- struct wm_range_table_entry *table_entry,
- struct dcn_watermarks *wm_set,
- struct display_mode_lib *dml,
- display_e2e_pipe_params_st *pipes,
- int pipe_cnt)
-{
- double dram_clock_change_latency_cached =
dml->soc.dram_clock_change_latency_us;
-
- ASSERT(vlevel < dml->soc.num_states);
- /* only pipe 0 is read for voltage and dcf/soc clocks */
- pipes[0].clks_cfg.voltage = vlevel;
- pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz;
- pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz;
-
- dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us;
- dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us;
- dml->soc.sr_enter_plus_exit_time_us =
table_entry->sr_enter_plus_exit_time_us;
-
- wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000;
- wm_set->cstate_pstate.cstate_enter_plus_exit_ns =
get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000;
- wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes,
pipe_cnt) * 1000;
- wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml,
pipes, pipe_cnt) * 1000;
- wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) *
1000;
- wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes,
pipe_cnt) * 1000;
- wm_set->frac_urg_bw_flip =
get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000;
- wm_set->urgent_latency_ns = get_urgent_latency(dml, pipes, pipe_cnt) *
1000;
- dml->soc.dram_clock_change_latency_us =
dram_clock_change_latency_cached;
-
-}
-
-static void dcn301_calculate_wm_and_dlg(
- struct dc *dc, struct dc_state *context,
- display_e2e_pipe_params_st *pipes,
- int pipe_cnt,
- int vlevel_req)
-{
- int i, pipe_idx;
- int vlevel, vlevel_max;
- struct wm_range_table_entry *table_entry;
- struct clk_bw_params *bw_params = dc->clk_mgr->bw_params;
-
- ASSERT(bw_params);
-
- vlevel_max = bw_params->clk_table.num_entries - 1;
-
- /* WM Set D */
- table_entry = _params->wm_table.entries[WM_D];
- if (table_entry->wm_type == WM_TYPE_RETRAINING)
- vlevel = 0;
- else
- vlevel = vlevel_max;
- calculate_wm_set_for_vlevel(vlevel, table_entry,
>bw_ctx.bw.dcn.watermarks.d,
- >bw_ctx.dml, pipes,
pipe_cnt);
- /* WM Set C */
- table_entry = _params->wm_table.entries[WM_C];
- vlevel = min(max(vlevel_req, 2), vlevel_max);
- calculate_wm_set_for_vlevel(vlevel, table_entry,
>bw_ctx.bw.dcn.watermarks.c,
- >bw_ctx.dml, pipes,
pipe_cnt);
- /* WM Set B */
- table_entry = _params->wm_table.entries[WM_B];
- vlevel = min(max(vlevel_req, 1), vlevel_max);
- calculate_wm_set_for_vlevel(vlevel, table_entry,
>bw_ctx.bw.dcn.watermarks.b,
- >bw_ctx.dml, pipes,
pipe_cnt);
-
- /* WM Set A */
- table_entry = _params->wm_table.entries[WM_A];
- vlevel = min(vlevel_req, vlevel_max);
- calculate_wm_set_for_vlevel(vlevel, table_entry,
>bw_ctx.bw.dcn.watermarks.a,
- >bw_ctx.dml, pipes,
pipe_cnt);
-
- for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
- if (!context->res_ctx.pipe_ctx[i].stream)
- continue;
-
- pipes[pipe_idx].clks_cfg.dispclk_mhz =
get_dispclk_calculated(>bw_ctx.dml, pipes, pipe_cnt);
- pipes[pipe_idx].clks_cfg.dppclk_mhz =
get_dppclk_calculated(>bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
-
- if (dc->config.forced_clocks) {
-
[PATCH] drm/amdgpu/display: drop unused DCN3.01 functions
No longer used. Drop to avoid warnings.
Fixes: e0e33d4006aa ("[why] the dcn301_calculate_wm_and_dl() calculation
exposed a issue - switch to dcn30 version for now. still need to follow up
with dcn301 watermark updates version.")
Signed-off-by: Alex Deucher
Cc: Charles Sun
Cc: Nikola Cornij
---
.../amd/display/dc/dcn301/dcn301_resource.c | 94 ---
1 file changed, 94 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
index 22ffd7c64bde..c109d0cdab42 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
@@ -1621,100 +1621,6 @@ static void dcn301_update_bw_bounding_box(struct dc
*dc, struct clk_bw_params *b
dml_init_instance(>dml, _01_soc, _01_ip,
DML_PROJECT_DCN30);
}
-static void calculate_wm_set_for_vlevel(
- int vlevel,
- struct wm_range_table_entry *table_entry,
- struct dcn_watermarks *wm_set,
- struct display_mode_lib *dml,
- display_e2e_pipe_params_st *pipes,
- int pipe_cnt)
-{
- double dram_clock_change_latency_cached =
dml->soc.dram_clock_change_latency_us;
-
- ASSERT(vlevel < dml->soc.num_states);
- /* only pipe 0 is read for voltage and dcf/soc clocks */
- pipes[0].clks_cfg.voltage = vlevel;
- pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz;
- pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz;
-
- dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us;
- dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us;
- dml->soc.sr_enter_plus_exit_time_us =
table_entry->sr_enter_plus_exit_time_us;
-
- wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000;
- wm_set->cstate_pstate.cstate_enter_plus_exit_ns =
get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000;
- wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes,
pipe_cnt) * 1000;
- wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml,
pipes, pipe_cnt) * 1000;
- wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) *
1000;
- wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes,
pipe_cnt) * 1000;
- wm_set->frac_urg_bw_flip =
get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000;
- wm_set->urgent_latency_ns = get_urgent_latency(dml, pipes, pipe_cnt) *
1000;
- dml->soc.dram_clock_change_latency_us =
dram_clock_change_latency_cached;
-
-}
-
-static void dcn301_calculate_wm_and_dlg(
- struct dc *dc, struct dc_state *context,
- display_e2e_pipe_params_st *pipes,
- int pipe_cnt,
- int vlevel_req)
-{
- int i, pipe_idx;
- int vlevel, vlevel_max;
- struct wm_range_table_entry *table_entry;
- struct clk_bw_params *bw_params = dc->clk_mgr->bw_params;
-
- ASSERT(bw_params);
-
- vlevel_max = bw_params->clk_table.num_entries - 1;
-
- /* WM Set D */
- table_entry = _params->wm_table.entries[WM_D];
- if (table_entry->wm_type == WM_TYPE_RETRAINING)
- vlevel = 0;
- else
- vlevel = vlevel_max;
- calculate_wm_set_for_vlevel(vlevel, table_entry,
>bw_ctx.bw.dcn.watermarks.d,
- >bw_ctx.dml, pipes,
pipe_cnt);
- /* WM Set C */
- table_entry = _params->wm_table.entries[WM_C];
- vlevel = min(max(vlevel_req, 2), vlevel_max);
- calculate_wm_set_for_vlevel(vlevel, table_entry,
>bw_ctx.bw.dcn.watermarks.c,
- >bw_ctx.dml, pipes,
pipe_cnt);
- /* WM Set B */
- table_entry = _params->wm_table.entries[WM_B];
- vlevel = min(max(vlevel_req, 1), vlevel_max);
- calculate_wm_set_for_vlevel(vlevel, table_entry,
>bw_ctx.bw.dcn.watermarks.b,
- >bw_ctx.dml, pipes,
pipe_cnt);
-
- /* WM Set A */
- table_entry = _params->wm_table.entries[WM_A];
- vlevel = min(vlevel_req, vlevel_max);
- calculate_wm_set_for_vlevel(vlevel, table_entry,
>bw_ctx.bw.dcn.watermarks.a,
- >bw_ctx.dml, pipes,
pipe_cnt);
-
- for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
- if (!context->res_ctx.pipe_ctx[i].stream)
- continue;
-
- pipes[pipe_idx].clks_cfg.dispclk_mhz =
get_dispclk_calculated(>bw_ctx.dml, pipes, pipe_cnt);
- pipes[pipe_idx].clks_cfg.dppclk_mhz =
get_dppclk_calculated(>bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
-
- if (dc->config.forced_clocks) {
- pipes[pipe_idx].clks_cfg.dispclk_mhz =
2021 X.Org Foundation Election Candidates
To all X.Org Foundation Members: The election for the X.Org Foundation Board of Directors will begin on 22 March 2021. We have 6 candidates who are running for 4 seats. They are (in alphabetical order): Samuel Iglesias Gonsálvez Manasi Navare Lyude Paul Rodrigo Siqueira Lucas Stach Daniel Vetter Attached below are the Personal Statements each candidate submitted for your consideration along with their Statements of Contribution that they submitted with the membership application. Please review each of the candidates' statements to help you decide whom to vote for during the upcoming election. If you have questions of the candidates, you should feel free to ask them here on the mailing list. The election committee will provide detailed instructions on how the voting system will work when the voting period begins. ** Election Schedule ** Nomination period Start: Mon 22nd February Nomination period End: Sun 7th March Publication of Candidates & start of Candidate QA: Mon 15th March Deadline of X.Org membership application or renewal: Thu 18th March Election Planned Start: Mon 22nd March anywhere on earth Election Planned End: Sun 4th April anywhere on earth ** Election Committee ** * Eric Anholt * Mark Filion * Keith Packard * Harry Wentland Thanks, Harry Wentland, on behalf of the X.Org elections committee ** Nominees ** ## Samuel Iglesias Gonsálvez __Current Affiliation:__ Igalia __Personal Statement:__ I have been contributing to Mesa and piglit for 7 years improving open-source drivers for both OpenGL and Vulkan. During my time on the board, I have become the XDC organization coordinator and the XDC CFP committee chair, due to my experience organizing the XDC 2018 in A Coruña, Spain. Thanks to these experiences, I have been deeply involved in the XDC organization process, where I have helped make a great and welcoming conference every year. If I am elected, I plan to continue leading both the XDC organization process and the XDC CFP committee. ## Manasi Navare __Current Affiliation:__ Intel __Statement of contribution:__ I am a lead contributor to Intel’s Open source graphics kernel driver i915 as well as to the Linux Kernel DRM subsystem. One of my most widely used contributions is the Display Port Compliance code in i915, DRM as well as in Xserver and IGT to make the entire graphics stack Display Port compliant and reward the end users with black screen free displays. I have also enabled features like Display stream compression across DRM and i915 as per VESA’s DSC specification for Display Port. Most recently I have been working with both the DRM and i915 community as well as the AMD developers to implement and enable adaptive sync feature for variable refresh rate on display drivers for enhanced gaming experience. I also have commit rights to several upstream projects like drm-intel, drm-misc and Intel GPU Tools. I have served on X.org board of directors for last 2 years organizing XDC conferences, being on Code of Conduct committee for X.org and Freedesktop and taking over the treasurer responsibility since September 2020. __Personal Statement:__ I have been a Linux Open Source contributor for last 7 years since I joined Intel's Open source technology center. My major contributions are in enabling display interfaces and develop display features in upcoming display specifications in i915 and Linux DRM subsystem. I have presented several talks at Linux Graphics conferences like Embedded Linux Conference, XDC and FOSDEM on several graphics display features like Display Port compliance and Display Stream Compression, Tiled display support, Adaptive Sync or Variable Refresh rate kernel support for gaming and I have been already actively involved in IRC discussions with DRM and i915 maintainers to constantly provide any solution on display port questions and work on improving the kernel documentation and code quality. I have served on the X.org board of directors since 2019 helping in XDC 2019 and XDC 2020 organization and for ensuring the Code of Conduct on the X.org community and during XDC events. I have previously mentored for the KMS project in Outreachy 2018 winter program as well as administered the Google summer of code 2019 program and will continue to do so whenever I get an opportunity. I joined the Code of Conduct Freedesktop committee as well to ensure it is followed on all the Freedesktop projects and open source channels. I have recently stepped up to take over the treasurer responsibility as part of the X.org board and working with all our sponsors to get the invoicing for the X.org events. If I get elected I would like to continue being a treasurer managing the XDC sponsorship and invoicing responsibilities as well as continue serving on the Code of conduct committee for X.org and Freedesktop. In addition to this I would like to help out on XDC event website organization and
RE: [PATCH 1/2] drm/amdgpu: fix compile error on architecture s390
[AMD Public Use] > -Original Message- > From: amd-gfx On Behalf Of > Nirmoy > Sent: Monday, March 15, 2021 2:43 PM > To: Zeng, Oak ; amd-gfx@lists.freedesktop.org > Subject: Re: [PATCH 1/2] drm/amdgpu: fix compile error on architecture s390 > > Wouldn't this restrict amdgpu for only x86 platform? This particular case will only be x86. Alex > > On 3/11/21 4:29 AM, Oak Zeng wrote: > > ioremap_cache is not supported on some architecture such as s390. Put > > the codes into a #ifdef to fix some compile error reported by test > > robot. > > > > Signed-off-by: Oak Zeng > > Reported-by: Kernel test robot > > --- > > drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c > > b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c > > index 37751e7..1091585 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c > > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c > > @@ -1817,7 +1817,7 @@ int amdgpu_ttm_init(struct amdgpu_device > *adev) > > > > /* Change the size here instead of the init above so only lpfn is > affected */ > > amdgpu_ttm_set_buffer_funcs_status(adev, false); -#ifdef > > CONFIG_64BIT > > +#ifdef CONFIG_X86 > > if (adev->gmc.xgmi.connected_to_cpu) > > adev->mman.aper_base_kaddr = ioremap_cache(adev- > >gmc.aper_base, > > adev->gmc.visible_vram_size); > ___ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists. > freedesktop.org%2Fmailman%2Flistinfo%2Famd- > gfxdata=04%7C01%7Calexander.deucher%40amd.com%7C6fab18a743 > c84b8abbd008d8e7e21e10%7C3dd8961fe4884e608e11a82d994e183d%7C0%7 > C0%7C637514305648085244%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4w > LjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000 > p;sdata=KLYRSc45rllptRvyiOF18qA9IFt5zAGXL1zsHasgdLs%3Dreserved > =0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 1/2] drm/amdgpu: fix compile error on architecture s390
Wouldn't this restrict amdgpu for only x86 platform? On 3/11/21 4:29 AM, Oak Zeng wrote: ioremap_cache is not supported on some architecture such as s390. Put the codes into a #ifdef to fix some compile error reported by test robot. Signed-off-by: Oak Zeng Reported-by: Kernel test robot --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 37751e7..1091585 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -1817,7 +1817,7 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) /* Change the size here instead of the init above so only lpfn is affected */ amdgpu_ttm_set_buffer_funcs_status(adev, false); -#ifdef CONFIG_64BIT +#ifdef CONFIG_X86 if (adev->gmc.xgmi.connected_to_cpu) adev->mman.aper_base_kaddr = ioremap_cache(adev->gmc.aper_base, adev->gmc.visible_vram_size); ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amd/display: Remove unnecessary conversion to bool
Applied. Thanks! Alex On Mon, Mar 15, 2021 at 4:22 AM Jiapeng Chong wrote: > > Fix the following coccicheck warnings: > > ./drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c:358:69-74: WARNING: > conversion to bool not needed here. > > Reported-by: Abaci Robot > Signed-off-by: Jiapeng Chong > --- > drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c > b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c > index 3e6f760..e153109 100644 > --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c > +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c > @@ -355,7 +355,7 @@ void mpc3_set_output_gamma( > next_mode = LUT_RAM_A; > > mpc3_power_on_ogam_lut(mpc, mpcc_id, true); > - mpc3_configure_ogam_lut(mpc, mpcc_id, next_mode == LUT_RAM_A ? > true:false); > + mpc3_configure_ogam_lut(mpc, mpcc_id, next_mode == LUT_RAM_A); > > if (next_mode == LUT_RAM_A) > mpc3_program_luta(mpc, mpcc_id, params); > -- > 1.8.3.1 > > ___ > dri-devel mailing list > dri-de...@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH V2] drm: amd: pm: Mundane typo fixes in the file amdgpu_pm.c
On Sun, Mar 14, 2021 at 11:22 PM Bhaskar Chowdhury wrote: > > > s/"an minimum"/"a minimum"/ > s/"an maxmum"/"a maximum"/ > > Signed-off-by: Bhaskar Chowdhury Applied. Thanks! Alex > --- > Changes from V1: > Randy's suggestion to adjust the subject line text > And missed out a spell too,which now included > > drivers/gpu/drm/amd/pm/amdgpu_pm.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c > b/drivers/gpu/drm/amd/pm/amdgpu_pm.c > index 5fa65f191a37..308249ae1a22 100644 > --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c > +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c > @@ -3315,9 +3315,9 @@ static ssize_t amdgpu_hwmon_show_mclk_label(struct > device *dev, > * > * - pwm1_max: pulse width modulation fan control maximum level (255) > * > - * - fan1_min: an minimum value Unit: revolution/min (RPM) > + * - fan1_min: a minimum value Unit: revolution/min (RPM) > * > - * - fan1_max: an maxmum value Unit: revolution/max (RPM) > + * - fan1_max: a maximum value Unit: revolution/max (RPM) > * > * - fan1_input: fan speed in RPM > * > -- > 2.30.2 > > ___ > dri-devel mailing list > dri-de...@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amd/display: remove redundant initialization of variable result
Applied. Thanks!
Alex
On Thu, Mar 11, 2021 at 11:34 AM Colin King wrote:
>
> From: Colin Ian King
>
> The variable result is being initialized with a value that is
> never read and it is being updated later with a new value. The
> initialization is redundant and can be removed.
>
> Addresses-Coverity: ("Unused value")
> Signed-off-by: Colin Ian King
> ---
> drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> index 099f43709060..47e6c33f73cb 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> @@ -4281,7 +4281,7 @@ void dp_set_panel_mode(struct dc_link *link, enum
> dp_panel_mode panel_mode)
>
> if (edp_config_set.bits.PANEL_MODE_EDP
> != panel_mode_edp) {
> - enum dc_status result = DC_ERROR_UNEXPECTED;
> + enum dc_status result;
>
> edp_config_set.bits.PANEL_MODE_EDP =
> panel_mode_edp;
> --
> 2.30.2
>
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Re: [PATCH][next] drm/amd/pm: Fix spelling mistake "disble" -> "disable"
Applied. Thanks! Alex On Fri, Mar 12, 2021 at 5:08 AM Colin King wrote: > > From: Colin Ian King > > There is a spelling mistake in an assert message. Fix it. > > Signed-off-by: Colin Ian King > --- > drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c > b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c > index 0d725b66fb78..7edafef095a3 100644 > --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c > +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c > @@ -1300,7 +1300,7 @@ static int smu7_start_dpm(struct pp_hwmgr *hwmgr) > (0 == smum_send_msg_to_smc(hwmgr, > PPSMC_MSG_PCIeDPM_Disable, > NULL)), > - "Failed to disble pcie DPM during DPM Start > Function!", > + "Failed to disable pcie DPM during DPM Start > Function!", > return -EINVAL); > } > > -- > 2.30.2 > > ___ > dri-devel mailing list > dri-de...@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 1/1] drm/amdgpu: make BO type check less restrictive
[AMD Official Use Only - Internal Distribution Only]
FWIW the patch seems to fix the issue I was seeing :-)
Tom
From: Koenig, Christian
Sent: Monday, March 15, 2021 11:22
To: Das, Nirmoy
Cc: amd-gfx@lists.freedesktop.org; StDenis, Tom
Subject: Re: [PATCH 1/1] drm/amdgpu: make BO type check less restrictive
Am 15.03.21 um 16:14 schrieb Nirmoy Das:
> BO with ttm_bo_type_sg type can also have tiling_flag and metadata.
> So so BO type check for only ttm_bo_type_kernel.
>
> Signed-off-by: Nirmoy Das
> Reported-by: Tom StDenis
At some point we should probably add a amdgpu_bo_is_user() helper
function, but for now that should work.
Reviewed-by: Christian König
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> index ac0e1cd83858..fdf23e439b42 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> @@ -1167,7 +1167,7 @@ int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo,
> u64 tiling_flags)
> struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
> struct amdgpu_bo_user *ubo;
>
> - BUG_ON(bo->tbo.type != ttm_bo_type_device);
> + BUG_ON(bo->tbo.type == ttm_bo_type_kernel);
> if (adev->family <= AMDGPU_FAMILY_CZ &&
> AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6)
> return -EINVAL;
> @@ -1189,7 +1189,7 @@ void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo,
> u64 *tiling_flags)
> {
> struct amdgpu_bo_user *ubo;
>
> - BUG_ON(bo->tbo.type != ttm_bo_type_device);
> + BUG_ON(bo->tbo.type == ttm_bo_type_kernel);
> dma_resv_assert_held(bo->tbo.base.resv);
> ubo = to_amdgpu_bo_user(bo);
>
> @@ -1216,7 +1216,7 @@ int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void
> *metadata,
> struct amdgpu_bo_user *ubo;
> void *buffer;
>
> - BUG_ON(bo->tbo.type != ttm_bo_type_device);
> + BUG_ON(bo->tbo.type == ttm_bo_type_kernel);
> ubo = to_amdgpu_bo_user(bo);
> if (!metadata_size) {
> if (ubo->metadata_size) {
> @@ -1266,7 +1266,7 @@ int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void
> *buffer,
> if (!buffer && !metadata_size)
> return -EINVAL;
>
> - BUG_ON(bo->tbo.type != ttm_bo_type_device);
> + BUG_ON(bo->tbo.type == ttm_bo_type_kernel);
> ubo = to_amdgpu_bo_user(bo);
> if (buffer) {
> if (buffer_size < ubo->metadata_size)
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[PATCH 2/2] drm/amd/pm: Use BACO reset arg 0 on XGMI configuration
With arg 1 BACO reset, it will try to reload the SMU FW after reset.
This might failed if driver already in a pending reset status during probe
period.
Arg 0 reset will bring asic back to a clean state and driver will re-init
everythign including SMU FW
Signed-off-by: shaoyunl
Change-Id: I6df90d963e259dcf1df8fe3716cdf52681202162
---
drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
index 635bd5da2133..0d137af1a78a 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
@@ -1530,7 +1530,7 @@ int smu_v11_0_baco_set_state(struct smu_context *smu,
enum smu_baco_state state)
NULL);
break;
default:
- if (!ras || !ras->supported) {
+ if (!ras || !ras->supported ||
adev->gmc.xgmi.pending_reset) {
if (adev->asic_type == CHIP_ARCTURUS) {
data = RREG32_SOC15(THM, 0,
mmTHM_BACO_CNTL_ARCT);
data |= 0x8000;
--
2.17.1
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[PATCH 1/2] drm/amdgpu: Keep pending_reset valid during smu reset the ASIC
SMU internal might need to check this pending_reset setting to decide the reset
method
Signed-off-by: shaoyunl
Change-Id: I8d88abf56d481e7443ac31baa2929826aec9e576
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index e0c4f70f96a4..7b3d9384b307 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -1359,8 +1359,8 @@ static void amdgpu_drv_delayed_reset_work_handler(struct
work_struct *work)
}
for (i = 0; i < mgpu_info.num_dgpu; i++) {
adev = mgpu_info.gpu_ins[i].adev;
- adev->gmc.xgmi.pending_reset = false;
flush_work(>xgmi_reset_work);
+ adev->gmc.xgmi.pending_reset = false;
}
/* reset function will rebuild the xgmi hive info , clear it now */
--
2.17.1
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Re: [PATCH] drm/amd/display: Free local data after use
Applied to amd-staging-drm-next. Thanks On 03/11, Victor Lu wrote: > Fixes the following memory leak in dc_link_construct(): > > unreferenced object 0xa03e81471400 (size 1024): > comm "amd_module_load", pid 2486, jiffies 4294946026 (age 10.544s) > hex dump (first 32 bytes): > 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > backtrace: > [<0bdf5c4a>] kmem_cache_alloc_trace+0x30a/0x4a0 > [] link_create+0xce/0xac0 [amdgpu] > [<2fb6c072>] dc_create+0x370/0x720 [amdgpu] > [<0094d1f3>] amdgpu_dm_init+0x18e/0x17a0 [amdgpu] > [ ] dm_hw_init+0x12/0x20 [amdgpu] > [ ] amdgpu_device_init+0x1463/0x1e60 [amdgpu] > [<32d3bb13>] amdgpu_driver_load_kms+0x5b/0x330 [amdgpu] > [ ] amdgpu_pci_probe+0x192/0x280 [amdgpu] > [ ] local_pci_probe+0x47/0xa0 > [<55dbbfa7>] pci_device_probe+0xe3/0x180 > [<815da970>] really_probe+0x1c4/0x4e0 > [ ] driver_probe_device+0x62/0x150 > [<0f9ecc61>] device_driver_attach+0x58/0x60 > [<0f65c843>] __driver_attach+0xd6/0x150 > [<2f5e3683>] bus_for_each_dev+0x6a/0xc0 > [ ] driver_attach+0x1e/0x20 > > Fixes: a8e30005b47a ("drm/amd/display/dc/core/dc_link: Move some local > data from the stack to the heap") > Signed-off-by: Victor Lu > --- > drivers/gpu/drm/amd/display/dc/core/dc_link.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c > b/drivers/gpu/drm/amd/display/dc/core/dc_link.c > index 9337e87a73e7..b60e0a4dc4bc 100644 > --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c > +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c > @@ -1615,6 +1615,7 @@ static bool dc_link_construct(struct dc_link *link, > link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED; > > DC_LOG_DC("BIOS object table - %s finished successfully.\n", __func__); > + kfree(info); > return true; > device_tag_fail: > link->link_enc->funcs->destroy(>link_enc); > -- > 2.25.1 > -- Rodrigo Siqueira https://siqueira.tech signature.asc Description: PGP signature ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amd/display: Free local data after use
Nice catch! Reviewed-by: Rodrigo Siqueira On 03/11, Victor Lu wrote: > Fixes the following memory leak in dc_link_construct(): > > unreferenced object 0xa03e81471400 (size 1024): > comm "amd_module_load", pid 2486, jiffies 4294946026 (age 10.544s) > hex dump (first 32 bytes): > 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > backtrace: > [<0bdf5c4a>] kmem_cache_alloc_trace+0x30a/0x4a0 > [] link_create+0xce/0xac0 [amdgpu] > [<2fb6c072>] dc_create+0x370/0x720 [amdgpu] > [<0094d1f3>] amdgpu_dm_init+0x18e/0x17a0 [amdgpu] > [ ] dm_hw_init+0x12/0x20 [amdgpu] > [ ] amdgpu_device_init+0x1463/0x1e60 [amdgpu] > [<32d3bb13>] amdgpu_driver_load_kms+0x5b/0x330 [amdgpu] > [ ] amdgpu_pci_probe+0x192/0x280 [amdgpu] > [ ] local_pci_probe+0x47/0xa0 > [<55dbbfa7>] pci_device_probe+0xe3/0x180 > [<815da970>] really_probe+0x1c4/0x4e0 > [ ] driver_probe_device+0x62/0x150 > [<0f9ecc61>] device_driver_attach+0x58/0x60 > [<0f65c843>] __driver_attach+0xd6/0x150 > [<2f5e3683>] bus_for_each_dev+0x6a/0xc0 > [ ] driver_attach+0x1e/0x20 > > Fixes: a8e30005b47a ("drm/amd/display/dc/core/dc_link: Move some local > data from the stack to the heap") > Signed-off-by: Victor Lu > --- > drivers/gpu/drm/amd/display/dc/core/dc_link.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c > b/drivers/gpu/drm/amd/display/dc/core/dc_link.c > index 9337e87a73e7..b60e0a4dc4bc 100644 > --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c > +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c > @@ -1615,6 +1615,7 @@ static bool dc_link_construct(struct dc_link *link, > link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED; > > DC_LOG_DC("BIOS object table - %s finished successfully.\n", __func__); > + kfree(info); > return true; > device_tag_fail: > link->link_enc->funcs->destroy(>link_enc); > -- > 2.25.1 > -- Rodrigo Siqueira https://siqueira.tech signature.asc Description: PGP signature ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu: drop legacy IO bar support
Am 15.03.21 um 16:17 schrieb Alex Deucher:
It was leftover from radeon where it was required for some
specific old hardware. It hasn't been required for ages
and the driver already falls back to MMIO when legacy IO
is not available. Legacy IO also seems to be problematic on
on some thunderbolt devices. Drop it.
Oh my, that stuff was still around?
And yes that is expected, there is probably no legacy IO space allocated
to the thunderbolt hardware.
Signed-off-by: Alex Deucher
Cc: Nicholas Johnson
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 7 ---
drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 43 ---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 57
drivers/gpu/drm/amd/amdgpu/atom.c| 4 +-
drivers/gpu/drm/amd/amdgpu/atom.h| 2 -
5 files changed, 2 insertions(+), 111 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index f69e6389bdc6..e738ebbe738a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -876,8 +876,6 @@ struct amdgpu_device {
spinlock_t audio_endpt_idx_lock;
amdgpu_block_rreg_t audio_endpt_rreg;
amdgpu_block_wreg_t audio_endpt_wreg;
- void __iomem*rio_mem;
- resource_size_t rio_mem_size;
struct amdgpu_doorbell doorbell;
/* clock/pll info */
@@ -1109,9 +1107,6 @@ void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t
value);
uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);
-u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
-void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
-
u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev,
u32 pcie_index, u32 pcie_data,
u32 reg_addr);
@@ -1202,8 +1197,6 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
} while (0)
#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false))
-#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
-#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
index 86add0f4ea4d..e05648a8a145 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
@@ -1905,40 +1905,6 @@ static uint32_t cail_reg_read(struct card_info *info,
uint32_t reg)
return r;
}
-/**
- * cail_ioreg_write - write IO register
- *
- * @info: atom card_info pointer
- * @reg: IO register offset
- * @val: value to write to the pll register
- *
- * Provides a IO register accessor for the atom interpreter (r4xx+).
- */
-static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t
val)
-{
- struct amdgpu_device *adev = drm_to_adev(info->dev);
-
- WREG32_IO(reg, val);
-}
-
-/**
- * cail_ioreg_read - read IO register
- *
- * @info: atom card_info pointer
- * @reg: IO register offset
- *
- * Provides an IO register accessor for the atom interpreter (r4xx+).
- * Returns the value of the IO register.
- */
-static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
-{
- struct amdgpu_device *adev = drm_to_adev(info->dev);
- uint32_t r;
-
- r = RREG32_IO(reg);
- return r;
-}
-
static ssize_t amdgpu_atombios_get_vbios_version(struct device *dev,
struct device_attribute *attr,
char *buf)
@@ -1998,15 +1964,6 @@ int amdgpu_atombios_init(struct amdgpu_device *adev)
atom_card_info->dev = adev_to_drm(adev);
atom_card_info->reg_read = cail_reg_read;
atom_card_info->reg_write = cail_reg_write;
- /* needed for iio ops */
- if (adev->rio_mem) {
- atom_card_info->ioreg_read = cail_ioreg_read;
- atom_card_info->ioreg_write = cail_ioreg_write;
- } else {
- DRM_DEBUG("PCI I/O BAR is not found. Using MMIO to access ATOM
BIOS\n");
- atom_card_info->ioreg_read = cail_reg_read;
- atom_card_info->ioreg_write = cail_reg_write;
- }
atom_card_info->mc_read = cail_mc_read;
atom_card_info->mc_write = cail_mc_write;
atom_card_info->pll_read = cail_pll_read;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index e04ec3c83485..112749549c00 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -466,49 +466,6 @@
Re: [PATCH 1/1] drm/amdgpu: make BO type check less restrictive
Am 15.03.21 um 16:14 schrieb Nirmoy Das:
BO with ttm_bo_type_sg type can also have tiling_flag and metadata.
So so BO type check for only ttm_bo_type_kernel.
Signed-off-by: Nirmoy Das
Reported-by: Tom StDenis
At some point we should probably add a amdgpu_bo_is_user() helper
function, but for now that should work.
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index ac0e1cd83858..fdf23e439b42 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -1167,7 +1167,7 @@ int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64
tiling_flags)
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
struct amdgpu_bo_user *ubo;
- BUG_ON(bo->tbo.type != ttm_bo_type_device);
+ BUG_ON(bo->tbo.type == ttm_bo_type_kernel);
if (adev->family <= AMDGPU_FAMILY_CZ &&
AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6)
return -EINVAL;
@@ -1189,7 +1189,7 @@ void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64
*tiling_flags)
{
struct amdgpu_bo_user *ubo;
- BUG_ON(bo->tbo.type != ttm_bo_type_device);
+ BUG_ON(bo->tbo.type == ttm_bo_type_kernel);
dma_resv_assert_held(bo->tbo.base.resv);
ubo = to_amdgpu_bo_user(bo);
@@ -1216,7 +1216,7 @@ int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata,
struct amdgpu_bo_user *ubo;
void *buffer;
- BUG_ON(bo->tbo.type != ttm_bo_type_device);
+ BUG_ON(bo->tbo.type == ttm_bo_type_kernel);
ubo = to_amdgpu_bo_user(bo);
if (!metadata_size) {
if (ubo->metadata_size) {
@@ -1266,7 +1266,7 @@ int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void
*buffer,
if (!buffer && !metadata_size)
return -EINVAL;
- BUG_ON(bo->tbo.type != ttm_bo_type_device);
+ BUG_ON(bo->tbo.type == ttm_bo_type_kernel);
ubo = to_amdgpu_bo_user(bo);
if (buffer) {
if (buffer_size < ubo->metadata_size)
___
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[PATCH] drm/amdgpu: drop legacy IO bar support
It was leftover from radeon where it was required for some
specific old hardware. It hasn't been required for ages
and the driver already falls back to MMIO when legacy IO
is not available. Legacy IO also seems to be problematic on
on some thunderbolt devices. Drop it.
Signed-off-by: Alex Deucher
Cc: Nicholas Johnson
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 7 ---
drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 43 ---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 57
drivers/gpu/drm/amd/amdgpu/atom.c| 4 +-
drivers/gpu/drm/amd/amdgpu/atom.h| 2 -
5 files changed, 2 insertions(+), 111 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index f69e6389bdc6..e738ebbe738a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -876,8 +876,6 @@ struct amdgpu_device {
spinlock_t audio_endpt_idx_lock;
amdgpu_block_rreg_t audio_endpt_rreg;
amdgpu_block_wreg_t audio_endpt_wreg;
- void __iomem*rio_mem;
- resource_size_t rio_mem_size;
struct amdgpu_doorbell doorbell;
/* clock/pll info */
@@ -1109,9 +1107,6 @@ void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t
value);
uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);
-u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
-void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
-
u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev,
u32 pcie_index, u32 pcie_data,
u32 reg_addr);
@@ -1202,8 +1197,6 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
} while (0)
#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n",
amdgpu_device_rreg((adev), (reg), false))
-#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
-#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
index 86add0f4ea4d..e05648a8a145 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
@@ -1905,40 +1905,6 @@ static uint32_t cail_reg_read(struct card_info *info,
uint32_t reg)
return r;
}
-/**
- * cail_ioreg_write - write IO register
- *
- * @info: atom card_info pointer
- * @reg: IO register offset
- * @val: value to write to the pll register
- *
- * Provides a IO register accessor for the atom interpreter (r4xx+).
- */
-static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t
val)
-{
- struct amdgpu_device *adev = drm_to_adev(info->dev);
-
- WREG32_IO(reg, val);
-}
-
-/**
- * cail_ioreg_read - read IO register
- *
- * @info: atom card_info pointer
- * @reg: IO register offset
- *
- * Provides an IO register accessor for the atom interpreter (r4xx+).
- * Returns the value of the IO register.
- */
-static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
-{
- struct amdgpu_device *adev = drm_to_adev(info->dev);
- uint32_t r;
-
- r = RREG32_IO(reg);
- return r;
-}
-
static ssize_t amdgpu_atombios_get_vbios_version(struct device *dev,
struct device_attribute *attr,
char *buf)
@@ -1998,15 +1964,6 @@ int amdgpu_atombios_init(struct amdgpu_device *adev)
atom_card_info->dev = adev_to_drm(adev);
atom_card_info->reg_read = cail_reg_read;
atom_card_info->reg_write = cail_reg_write;
- /* needed for iio ops */
- if (adev->rio_mem) {
- atom_card_info->ioreg_read = cail_ioreg_read;
- atom_card_info->ioreg_write = cail_ioreg_write;
- } else {
- DRM_DEBUG("PCI I/O BAR is not found. Using MMIO to access ATOM
BIOS\n");
- atom_card_info->ioreg_read = cail_reg_read;
- atom_card_info->ioreg_write = cail_reg_write;
- }
atom_card_info->mc_read = cail_mc_read;
atom_card_info->mc_write = cail_mc_write;
atom_card_info->pll_read = cail_pll_read;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index e04ec3c83485..112749549c00 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -466,49 +466,6 @@ void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
}
}
-/**
- * amdgpu_io_rreg - read an IO register
- *
- * @adev: amdgpu_device pointer
- * @reg: dword aligned register offset
- *
- * Returns the 32 bit value from the offset
[PATCH 1/1] drm/amdgpu: make BO type check less restrictive
BO with ttm_bo_type_sg type can also have tiling_flag and metadata.
So so BO type check for only ttm_bo_type_kernel.
Signed-off-by: Nirmoy Das
Reported-by: Tom StDenis
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index ac0e1cd83858..fdf23e439b42 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -1167,7 +1167,7 @@ int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64
tiling_flags)
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
struct amdgpu_bo_user *ubo;
- BUG_ON(bo->tbo.type != ttm_bo_type_device);
+ BUG_ON(bo->tbo.type == ttm_bo_type_kernel);
if (adev->family <= AMDGPU_FAMILY_CZ &&
AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6)
return -EINVAL;
@@ -1189,7 +1189,7 @@ void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64
*tiling_flags)
{
struct amdgpu_bo_user *ubo;
- BUG_ON(bo->tbo.type != ttm_bo_type_device);
+ BUG_ON(bo->tbo.type == ttm_bo_type_kernel);
dma_resv_assert_held(bo->tbo.base.resv);
ubo = to_amdgpu_bo_user(bo);
@@ -1216,7 +1216,7 @@ int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void
*metadata,
struct amdgpu_bo_user *ubo;
void *buffer;
- BUG_ON(bo->tbo.type != ttm_bo_type_device);
+ BUG_ON(bo->tbo.type == ttm_bo_type_kernel);
ubo = to_amdgpu_bo_user(bo);
if (!metadata_size) {
if (ubo->metadata_size) {
@@ -1266,7 +1266,7 @@ int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void
*buffer,
if (!buffer && !metadata_size)
return -EINVAL;
- BUG_ON(bo->tbo.type != ttm_bo_type_device);
+ BUG_ON(bo->tbo.type == ttm_bo_type_kernel);
ubo = to_amdgpu_bo_user(bo);
if (buffer) {
if (buffer_size < ubo->metadata_size)
--
2.30.1
___
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Re: [PATCH 1/1] amdgpu: use MMIO to init atombios if device is Thunderbolt / USB4 attached
On Mon, Mar 15, 2021 at 4:04 AM Nicholas Johnson
wrote:
>
> When using some Thunderbolt hosts using BIOS-assisted PCI enumeration
> with IO BAR assigned, we get an atombios timeout, such as:
>
> [drm:atom_op_jump [amdgpu]] *ERROR* atombios stuck in loop for more than
> 20secs aborting
> [drm:amdgpu_atom_execute_table_locked [amdgpu]] *ERROR* atombios stuck
> executing B456 (len 304, WS 4, PS 0) @ 0xB51B
> [drm:amdgpu_atom_execute_table_locked [amdgpu]] *ERROR* atombios stuck
> executing B104 (len 183, WS 0, PS 8) @ 0xB17E
> amdgpu :08:00.0: amdgpu: gpu post error!
> amdgpu :08:00.0: amdgpu: Fatal error during GPU init
> amdgpu: probe of :08:00.0 failed with error -22
>
> A workaround is to use MMIO to access ATOMBIOS when device is
> Thunderbolt / USB4 attached.
Missing your signed-off-by. Also, we can just remove the legacy IO
callbacks altogether. They are leftover from radeon and not required
at all on amdgpu.
Alex
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 8 ++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
> index 86add0f4e..5d16ec10d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
> @@ -1999,11 +1999,15 @@ int amdgpu_atombios_init(struct amdgpu_device *adev)
> atom_card_info->reg_read = cail_reg_read;
> atom_card_info->reg_write = cail_reg_write;
> /* needed for iio ops */
> - if (adev->rio_mem) {
> + if (adev->rio_mem && !pci_is_thunderbolt_attached(adev->pdev)) {
> atom_card_info->ioreg_read = cail_ioreg_read;
> atom_card_info->ioreg_write = cail_ioreg_write;
> } else {
> - DRM_DEBUG("PCI I/O BAR is not found. Using MMIO to access
> ATOM BIOS\n");
> + if (pci_is_thunderbolt_attached(adev->pdev))
> + DRM_DEBUG("Device is attached via Thunderbolt / USB4.
> Using MMIO to access ATOM BIOS\n");
> + else
> + DRM_DEBUG("PCI I/O BAR is not found. Using MMIO to
> access ATOM BIOS\n");
> +
> atom_card_info->ioreg_read = cail_reg_read;
> atom_card_info->ioreg_write = cail_reg_write;
> }
> --
> 2.30.2
>
> ___
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> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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RE: [PATCH 2/2] drm/amdgpu: Enable lightSBR for SMU on passthrough and XGMI configuration
[AMD Public Use] Reviewed-by: Hawking Zhang Regards, Hawking -Original Message- From: amd-gfx On Behalf Of shaoyunl Sent: Thursday, March 11, 2021 01:56 To: amd-gfx@lists.freedesktop.org Cc: Liu, Shaoyun Subject: [PATCH 2/2] drm/amdgpu: Enable lightSBR for SMU on passthrough and XGMI configuration SMU introduce the new interface to enable lightSBR mode, driver enable it on passthrough + XGMI configuration Signed-off-by: shaoyunl Change-Id: I59aef0559aba418b764e7cf716b0d98aca14fec5 --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 4640cafae619..31a1783f211a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -3630,6 +3630,10 @@ int amdgpu_device_init(struct amdgpu_device *adev, if (amdgpu_device_cache_pci_state(adev->pdev)) pci_restore_state(pdev); + /* Enable lightSBR on SMU in passthrough + xgmi configuration */ + if (amdgpu_passthrough(adev) && adev->gmc.xgmi.num_physical_nodes > 1) + smu_set_lightSBR(>smu, true); + if (adev->gmc.xgmi.pending_reset) queue_delayed_work(system_wq, _info.delayed_reset_work, msecs_to_jiffies(AMDGPU_RESUME_MS)); -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfxdata=04%7C01%7Chawking.zhang%40amd.com%7C04784f230da34296c57508d8e3edbae2%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637509957533562385%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000sdata=%2Bfx6ycEu2mX1unj7oi0bEvM0JMtMbFQ9u2J0UrxWQCI%3Dreserved=0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH 00/23] DC Patches March 15, 2021
[AMD Public Use] Hi all, This week this patchset was tested on a HP Envy 360, with Ryzen 5 4500U, on the following display types (via usb-c to dp/dvi/hdmi/vga): 4k 60z, 1440p 144hz, 1680*1050 60hz, internal eDP 1080p 60hz Tested on a Sapphire Pulse RX5700XT on the following display types (via DP): 4k60 60hz, 1440p 144hz, 1680x1050 60hz. Also tested on a Reference AMD RX6800 on the following display types (via DP): 4k60 60hz, 1440p 144hz. Also using a MST hub at 2x 4k 30hz on all systems. Thank you, Dan Wheeler Technologist | AMD SW Display O +(1) 905-882-2600 ext. 74665 -- 1 Commerce Valley Dr E, Thornhill, ON L3T 7X6 Facebook | Twitter | amd.com -Original Message- From: amd-gfx On Behalf Of Solomon Chiu Sent: March 14, 2021 9:40 PM To: amd-gfx@lists.freedesktop.org Cc: Brol, Eryk ; Chiu, Solomon ; Li, Sun peng (Leo) ; Wentland, Harry ; Zhuo, Qingqing ; Siqueira, Rodrigo ; Jacob, Anson ; Pillai, Aurabindo ; Lakha, Bhawanpreet ; R, Bindu Subject: [PATCH 00/23] DC Patches March 15, 2021 This DC patchset brings improvements in multiple areas. In summary, we highlight: * Add debug out when viewport too small * use max lb for latency hiding * System black screen hangs on driver load * Fix UBSAN warning for not a valid value for type '_Bool' * Fix for outbox1 ring buffer typecasting issue * Bypass sink detect when there are no eDPs connected * Increase precision for bpp in DSC calculations * Add changes for dsc bpp in 16ths and unify bw calculations * Correct algorithm for reversed gamma * Remove MPC gamut remap logic for DCN30 * Fix typo for helpers function name * Fix secure display lock problems * Fix no previous prototype warning * Separate caps for maximum RGB and YUV plane counts * Add debugfs to control DMUB trace buffer events * [FW Promotion] Release 0.0.56 * DCHUB underflow counter increasing in some scenarios * fix dml prefetch validation * fix dcn3+ bw validation soc param update sequence * add a func to disable accelerated mode * Fix potential memory leak Anson Jacob (1): drm/amd/display: Fix UBSAN warning for not a valid value for type '_Bool' Anthony Koo (1): drm/amd/display: [FW Promotion] Release 0.0.56 Aric Cyr (4): drm/amd/display: 3.2.126.1 drm/amd/display: System black screen hangs on driver load drm/amd/display: DCHUB underflow counter increasing in some scenarios drm/amd/display: 3.2.127 Atufa Khan (1): drm/amd/display: Separate caps for maximum RGB and YUV plane counts Calvin Hou (1): drm/amd/display: Correct algorithm for reversed gamma Dillon Varone (2): drm/amd/display: Add changes for dsc bpp in 16ths and unify bw calculations drm/amd/display: Remove MPC gamut remap logic for DCN30 Dmytro Laktyushkin (3): drm/amd/display: use max lb for latency hiding drm/amd/display: fix dml prefetch validation drm/amd/display: fix dcn3+ bw validation soc param update sequence Jake Wang (1): drm/amd/display: Bypass sink detect when there are no eDPs connected Jun Lei (1): drm/amd/display: Increase precision for bpp in DSC calculations Leo (Hanghong) Ma (2): drm/amd/display: Fix typo for helpers function name drm/amd/display: Add debugfs to control DMUB trace buffer events Meenakshikumar Somasundaram (1): drm/amd/display: Fix for outbox1 ring buffer typecasting issue Nikola Cornij (1): drm/amd/display: Add debug out when viewport too small Qingqing Zhuo (1): drm/amd/display: Fix potential memory leak Wayne Lin (2): drm/amd/display: Fix secure display lock problems drm/amd/display: Fix no previous prototype warning Yao Wang1 (1): drm/amd/display: add a func to disable accelerated mode .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 33 +- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 1 + .../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c | 10 +- .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 43 +- .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 2 +- .../amd/display/dc/bios/bios_parser_helper.c | 5 +- .../amd/display/dc/bios/bios_parser_helper.h | 2 +- .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 48 +- .../display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c | 4 +- drivers/gpu/drm/amd/display/dc/core/dc.c | 31 +- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 9 +- drivers/gpu/drm/amd/display/dc/dc.h | 12 +- drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 2 +- drivers/gpu/drm/amd/display/dc/dc_dsc.h | 9 +- drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 1 + .../display/dc/dce110/dce110_hw_sequencer.c | 2 +- .../amd/display/dc/dce110/dce110_resource.c | 2 + .../drm/amd/display/dc/dcn10/dcn10_resource.c | 6 +- .../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 34 +- .../drm/amd/display/dc/dcn20/dcn20_resource.c | 8 +- .../drm/amd/display/dc/dcn21/dcn21_resource.c | 11 +- .../amd/display/dc/dcn30/dcn30_cm_common.c| 26
Re: [PATCH 2/2] drm/amdkfd: Fix resource cursor initialization
Am 15.03.21 um 14:08 schrieb Felix Kuehling:
Am 2021-03-15 um 6:22 a.m. schrieb Christian König:
Am 13.03.21 um 03:43 schrieb Felix Kuehling:
Make sure the cur->size doesn't exceed cur->remaining. Otherwise the
first call to amdgpu_res_next will trigger the BUG_ON in that function.
Mhm the BUG_ON is correct since the function complains that we want to
move the cursor forward by more than originally expected.
The problem is rather that somebody is using cur->size which is the
size of the current segment as parameter for amdgpu_res_next().
Do you have a backtrace of this?
I didn't save the backtrace. The problem was in
amdgpu_vm_bo_update_mapping. num_entries is based on cursor.size and
later used in the amdpu_res_next call.
Yeah, found that in the meantime as well.
But I think that should be OK. If cursor.size is the current segment
size, it should not exceed cursor.remaining. Otherwise every user of the
cursor would have to check both cursor.size and cursor.remaining all the
time, which would be inconvenient. amdgpu_res_next ensures that with
cur->size = min(node->size << PAGE_SHIFT, cur->remaining). I think
amdgpu_res_first should do the same.
Ok, good point. Patch is Reviewed-by: Christian König
then.
Regards,
Christian.
Regards,
Felix
Thanks,
Christian.
Fixes: 3af0a018a728 ("drm/amdgpu: new resource cursor")
CC: Christian König
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h
index 1335e098510f..b49a61d07d60 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h
@@ -68,7 +68,7 @@ static inline void amdgpu_res_first(struct
ttm_resource *res,
start -= node++->size << PAGE_SHIFT;
cur->start = (node->start << PAGE_SHIFT) + start;
- cur->size = (node->size << PAGE_SHIFT) - start;
+ cur->size = min((node->size << PAGE_SHIFT) - start, size);
cur->remaining = size;
cur->node = node;
}
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Re: [PATCH 2/2] drm/amdkfd: Fix resource cursor initialization
Am 2021-03-15 um 6:22 a.m. schrieb Christian König:
> Am 13.03.21 um 03:43 schrieb Felix Kuehling:
>> Make sure the cur->size doesn't exceed cur->remaining. Otherwise the
>> first call to amdgpu_res_next will trigger the BUG_ON in that function.
>
> Mhm the BUG_ON is correct since the function complains that we want to
> move the cursor forward by more than originally expected.
>
> The problem is rather that somebody is using cur->size which is the
> size of the current segment as parameter for amdgpu_res_next().
>
> Do you have a backtrace of this?
I didn't save the backtrace. The problem was in
amdgpu_vm_bo_update_mapping. num_entries is based on cursor.size and
later used in the amdpu_res_next call.
But I think that should be OK. If cursor.size is the current segment
size, it should not exceed cursor.remaining. Otherwise every user of the
cursor would have to check both cursor.size and cursor.remaining all the
time, which would be inconvenient. amdgpu_res_next ensures that with
cur->size = min(node->size << PAGE_SHIFT, cur->remaining). I think
amdgpu_res_first should do the same.
Regards,
Felix
>
> Thanks,
> Christian.
>
>>
>> Fixes: 3af0a018a728 ("drm/amdgpu: new resource cursor")
>> CC: Christian König
>> Signed-off-by: Felix Kuehling
>> ---
>> drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h
>> index 1335e098510f..b49a61d07d60 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h
>> @@ -68,7 +68,7 @@ static inline void amdgpu_res_first(struct
>> ttm_resource *res,
>> start -= node++->size << PAGE_SHIFT;
>> cur->start = (node->start << PAGE_SHIFT) + start;
>> - cur->size = (node->size << PAGE_SHIFT) - start;
>> + cur->size = min((node->size << PAGE_SHIFT) - start, size);
>> cur->remaining = size;
>> cur->node = node;
>> }
>
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Re: slow boot with 7fef431be9c9 ("mm/page_alloc: place pages to tail in __free_pages_core()")
On 13.03.21 14:48, Mike Rapoport wrote: Hi, On Sat, Mar 13, 2021 at 10:05:23AM +0100, David Hildenbrand wrote: Am 13.03.2021 um 05:04 schrieb Liang, Liang (Leo) : Hi David, Which benchmark tool you prefer? Memtest86+ or else? Hi Leo, I think you want something that runs under Linux natively. I‘m planning on coding up a kernel module to walk all 4MB pages in the freelists and perform a stream benchmark individually. Then we might be able to identify the problematic range - if there is a problematic range :) My wild guess would be that the pages that are now at the head of free lists have wrong caching enabled. Might be worth checking in your test module. I hacked something up real quick: https://github.com/davidhildenbrand/kstream Only briefly tested inside a VM. The output looks something like [...] [ 8396.432225] [0x4580 - 0x45bf] 25322 MB/s / 38948 MB/s [ 8396.448749] [0x45c0 - 0x45ff] 24481 MB/s / 38946 MB/s [ 8396.465197] [0x4600 - 0x463f] 24892 MB/s / 39170 MB/s [ 8396.481552] [0x4640 - 0x467f] 25222 MB/s / 39156 MB/s [ 8396.498012] [0x4680 - 0x46bf] 24416 MB/s / 39159 MB/s [ 8396.514397] [0x46c0 - 0x46ff] 25469 MB/s / 38940 MB/s [ 8396.530849] [0x4700 - 0x473f] 24885 MB/s / 38734 MB/s [ 8396.547195] [0x4740 - 0x477f] 25458 MB/s / 38941 MB/s [...] The benchmark allocates one 4 MiB chunk at a time and runs a simplified STREAM benchmark a) without flushing caches b) flushing caches before every memory access. It would be great if you could run that with the *old behavior* kernel (IOW, without 7fef431be9c9), so we might still be lucky to catch the problematic area in the freelist. Let's see if that will indicate anything. -- Thanks, David / dhildenb ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amd/display: Remove unnecessary conversion to bool
Fix the following coccicheck warnings: ./drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c:358:69-74: WARNING: conversion to bool not needed here. Reported-by: Abaci Robot Signed-off-by: Jiapeng Chong --- drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c index 3e6f760..e153109 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c @@ -355,7 +355,7 @@ void mpc3_set_output_gamma( next_mode = LUT_RAM_A; mpc3_power_on_ogam_lut(mpc, mpcc_id, true); - mpc3_configure_ogam_lut(mpc, mpcc_id, next_mode == LUT_RAM_A ? true:false); + mpc3_configure_ogam_lut(mpc, mpcc_id, next_mode == LUT_RAM_A); if (next_mode == LUT_RAM_A) mpc3_program_luta(mpc, mpcc_id, params); -- 1.8.3.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: make sure to only process the remaining VM range
We should only map the remaining size here and not the whole segment.
Signed-off-by: Christian König
Fixes: 3af0a018a728 ("drm/amdgpu: new resource cursor")
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 318eeea577b5..ad1698bd6b24 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1646,7 +1646,8 @@ static int amdgpu_vm_bo_update_mapping(struct
amdgpu_device *adev,
while (cursor.remaining) {
uint64_t tmp, num_entries, addr;
- num_entries = cursor.size >> AMDGPU_GPU_PAGE_SHIFT;
+ num_entries = min(cursor.size, cursor.remaining)
+ >> AMDGPU_GPU_PAGE_SHIFT;
if (pages_addr) {
bool contiguous = true;
--
2.25.1
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[PATCH 23/23] drm/amd/display: Fix potential memory leak
From: Qingqing Zhuo
[Why]
vblank_workqueue is never released.
[How]
Free it upon dm finish.
Signed-off-by: Qingqing Zhuo
Reviewed-by: Nicholas Kazlauskas
Acked-by: Solomon Chiu
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 3db69f5bd6e9..41f19ec743d4 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1228,6 +1228,15 @@ static void amdgpu_dm_fini(struct amdgpu_device *adev)
if (adev->dm.dc)
dc_deinit_callbacks(adev->dm.dc);
#endif
+
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+ if (adev->dm.vblank_workqueue) {
+ adev->dm.vblank_workqueue->dm = NULL;
+ kfree(adev->dm.vblank_workqueue);
+ adev->dm.vblank_workqueue = NULL;
+ }
+#endif
+
if (adev->dm.dc->ctx->dmub_srv) {
dc_dmub_srv_destroy(>dm.dc->ctx->dmub_srv);
adev->dm.dc->ctx->dmub_srv = NULL;
--
2.29.0
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[PATCH 22/23] drm/amd/display: add a func to disable accelerated mode
From: Yao Wang1
[Why]
When driver disabled, we driver force the YCbCr420 to RGB,
which means some register will be changed, such as
RDPCS_PHY_DP_MPLLB_TX_CLK_DIV changed from 1 to 0
When driver re-enabled, OS will Set Mode YCbCr420 again,
which means the register RDPCS_PHY_DP_MPLLB_TX_CLK_DIV
should to be 1 again, but dmub fw can’t update the
register to 1 due to the mpll is not off
[How]
Adds an interface to disable accelerated mode bit,
which allows DM to decide to call during driver
disable/unload scenarios.
Signed-off-by: Yao Wang1
Reviewed-by: Anthony Koo
Acked-by: Solomon Chiu
---
.../amd/display/dc/bios/bios_parser_helper.c | 5 +++--
.../amd/display/dc/bios/bios_parser_helper.h | 2 +-
drivers/gpu/drm/amd/display/dc/core/dc.c | 18 ++
drivers/gpu/drm/amd/display/dc/dc.h| 6 ++
.../display/dc/dce110/dce110_hw_sequencer.c| 2 +-
5 files changed, 29 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c
b/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c
index fce46ab54c54..53d7513b5083 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c
@@ -64,9 +64,10 @@ bool bios_is_accelerated_mode(
void bios_set_scratch_acc_mode_change(
- struct dc_bios *bios)
+ struct dc_bios *bios,
+ uint32_t state)
{
- REG_UPDATE(BIOS_SCRATCH_6, S6_ACC_MODE, 1);
+ REG_UPDATE(BIOS_SCRATCH_6, S6_ACC_MODE, state);
}
diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.h
b/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.h
index 75a29e68fb27..e1b4a40a353d 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.h
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.h
@@ -32,7 +32,7 @@ uint8_t *bios_get_image(struct dc_bios *bp, uint32_t offset,
uint32_t size);
bool bios_is_accelerated_mode(struct dc_bios *bios);
-void bios_set_scratch_acc_mode_change(struct dc_bios *bios);
+void bios_set_scratch_acc_mode_change(struct dc_bios *bios, uint32_t state);
void bios_set_scratch_critical_state(struct dc_bios *bios, bool state);
uint32_t bios_get_vga_enabled_displays(struct dc_bios *bios);
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index dffd150180ec..8e6c815b55d2 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -41,6 +41,7 @@
#include "dc_bios_types.h"
#include "bios_parser_interface.h"
+#include "bios/bios_parser_helper.h"
#include "include/irq_service_interface.h"
#include "transform.h"
#include "dmcu.h"
@@ -3372,3 +3373,20 @@ bool dc_process_dmub_aux_transfer_async(struct dc *dc,
return true;
}
+
+/**
+ *
+ * Function: dc_disable_accelerated_mode
+ *
+ * @brief
+ * disable accelerated mode
+ *
+ * @param
+ * [in] dc: dc structure
+ *
+ *
+ */
+void dc_disable_accelerated_mode(struct dc *dc)
+{
+ bios_set_scratch_acc_mode_change(dc->ctx->dc_bios, 0);
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 352651c805ff..d163007e057c 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -1313,4 +1313,10 @@ bool dc_process_dmub_aux_transfer_async(struct dc *dc,
* DSC Interfaces
**/
#include "dc_dsc.h"
+
+/***
+ * Disable acc mode Interfaces
+
**/
+void dc_disable_accelerated_mode(struct dc *dc);
+
#endif /* DC_INTERFACE_H_ */
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 08047802d040..804092f81f85 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1750,7 +1750,7 @@ void dce110_enable_accelerated_mode(struct dc *dc, struct
dc_state *context)
if (edp_link_with_sink && !keep_edp_vdd_on)
dc->hwss.edp_power_control(edp_link_with_sink, false);
}
- bios_set_scratch_acc_mode_change(dc->ctx->dc_bios);
+ bios_set_scratch_acc_mode_change(dc->ctx->dc_bios, 1);
}
static uint32_t compute_pstate_blackout_duration(
--
2.29.0
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[PATCH 21/23] drm/amd/display: fix dcn3+ bw validation soc param update sequence
From: Dmytro Laktyushkin
SOC needs to be updated to the WM set A values before validation
happens.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Eric Bernstein
Acked-by: Solomon Chiu
---
.../drm/amd/display/dc/dcn30/dcn30_resource.c | 17 -
.../drm/amd/display/dc/dcn30/dcn30_resource.h | 1 +
.../drm/amd/display/dc/dcn301/dcn301_resource.c | 1 +
.../drm/amd/display/dc/dcn302/dcn302_resource.c | 1 +
drivers/gpu/drm/amd/display/dc/inc/core_types.h | 2 ++
5 files changed, 17 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
index deab48806fa2..263c2986682d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
@@ -1876,6 +1876,7 @@ static noinline bool dcn30_internal_validate_bw(
if (!pipes)
return false;
+ dc->res_pool->funcs->update_soc_for_wm_a(dc, context);
pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes,
fast_validate);
DC_FP_START();
@@ -2225,11 +2226,7 @@ static noinline void dcn30_calculate_wm_and_dlg_fp(
*
* Set A calculated last so that following calculations are
based on Set A
*/
- if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid) {
- context->bw_ctx.dml.soc.dram_clock_change_latency_us =
dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;
- context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us =
dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us;
- context->bw_ctx.dml.soc.sr_exit_time_us =
dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us;
- }
+ dc->res_pool->funcs->update_soc_for_wm_a(dc, context);
context->bw_ctx.bw.dcn.watermarks.a.urgent_ns =
get_wm_urgent(>bw_ctx.dml, pipes, pipe_cnt) * 1000;
context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns =
get_wm_stutter_enter_exit(>bw_ctx.dml, pipes, pipe_cnt) * 1000;
context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns =
get_wm_stutter_exit(>bw_ctx.dml, pipes, pipe_cnt) * 1000;
@@ -2272,6 +2269,15 @@ static noinline void dcn30_calculate_wm_and_dlg_fp(
dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;
}
+void dcn30_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)
+{
+ if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid) {
+ context->bw_ctx.dml.soc.dram_clock_change_latency_us =
dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;
+ context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us =
dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us;
+ context->bw_ctx.dml.soc.sr_exit_time_us =
dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us;
+ }
+}
+
void dcn30_calculate_wm_and_dlg(
struct dc *dc, struct dc_state *context,
display_e2e_pipe_params_st *pipes,
@@ -2496,6 +2502,7 @@ static const struct resource_funcs dcn30_res_pool_funcs =
{
.panel_cntl_create = dcn30_panel_cntl_create,
.validate_bandwidth = dcn30_validate_bandwidth,
.calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg,
+ .update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
.populate_dml_pipes = dcn30_populate_dml_pipes_from_context,
.acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
.add_stream_to_ctx = dcn30_add_stream_to_ctx,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.h
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.h
index 8ce7f6d39a20..b754b89beadf 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.h
@@ -60,6 +60,7 @@ void dcn30_calculate_wm_and_dlg(
display_e2e_pipe_params_st *pipes,
int pipe_cnt,
int vlevel);
+void dcn30_update_soc_for_wm_a(struct dc *dc, struct dc_state *context);
void dcn30_populate_dml_writeback_from_context(
struct dc *dc, struct resource_context *res_ctx,
display_e2e_pipe_params_st *pipes);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
index 5f29a4f85ef2..e41747c39e29 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
@@ -1721,6 +1721,7 @@ static struct resource_funcs dcn301_res_pool_funcs = {
.panel_cntl_create = dcn301_panel_cntl_create,
.validate_bandwidth = dcn30_validate_bandwidth,
[PATCH 20/23] drm/amd/display: fix dml prefetch validation
From: Dmytro Laktyushkin
Incorrect variable used, missing initialization during validation.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Eric Bernstein
Acked-by: Solomon Chiu
---
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c | 1 +
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
index 0f3f510fd83b..9729cf292e84 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
@@ -3437,6 +3437,7 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct
display_mode_lib *mode_l
mode_lib->vba.DCCEnabledInAnyPlane = true;
}
}
+ mode_lib->vba.UrgentLatency = mode_lib->vba.UrgentLatencyPixelDataOnly;
for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
locals->FabricAndDRAMBandwidthPerState[i] = dml_min(
mode_lib->vba.DRAMSpeedPerState[i] *
mode_lib->vba.NumberOfChannels
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
index 210c96cd5b03..51098c2c9854 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
@@ -3544,6 +3544,7 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct
display_mode_lib *mode
mode_lib->vba.DCCEnabledInAnyPlane = true;
}
}
+ mode_lib->vba.UrgentLatency = mode_lib->vba.UrgentLatencyPixelDataOnly;
for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
locals->FabricAndDRAMBandwidthPerState[i] = dml_min(
mode_lib->vba.DRAMSpeedPerState[i] *
mode_lib->vba.NumberOfChannels
--
2.29.0
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[PATCH 19/23] drm/amd/display: 3.2.127
From: Aric Cyr Signed-off-by: Aric Cyr Reviewed-by: Aric Cyr Acked-by: Solomon Chiu --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index d26472ef1572..352651c805ff 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -45,7 +45,7 @@ /* forward declaration */ struct aux_payload; -#define DC_VER "3.2.126.1" +#define DC_VER "3.2.127" #define MAX_SURFACES 3 #define MAX_PLANES 6 -- 2.29.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 18/23] drm/amd/display: DCHUB underflow counter increasing in some scenarios
From: Aric Cyr
[Why]
When unplugging a display, the underflow counter can be seen to
increase because PSTATE switch is allowed even when some planes are not
blanked.
[How]
Check that all planes are not active instead of all streams before
allowing PSTATE change.
Signed-off-by: Aric Cyr
Reviewed-by: Aric Cyr
Acked-by: Solomon Chiu
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
index c7e5a64e06af..81ea5d3a1947 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
@@ -252,6 +252,7 @@ static void dcn3_update_clocks(struct clk_mgr *clk_mgr_base,
bool force_reset = false;
bool update_uclk = false;
bool p_state_change_support;
+ int total_plane_count;
if (dc->work_arounds.skip_clock_update || !clk_mgr->smu_present)
return;
@@ -292,7 +293,8 @@ static void dcn3_update_clocks(struct clk_mgr *clk_mgr_base,
clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz;
clk_mgr_base->clks.prev_p_state_change_support =
clk_mgr_base->clks.p_state_change_support;
- p_state_change_support = new_clocks->p_state_change_support ||
(display_count == 0);
+ total_plane_count = clk_mgr_helper_get_active_plane_cnt(dc, context);
+ p_state_change_support = new_clocks->p_state_change_support ||
(total_plane_count == 0);
if (should_update_pstate_support(safe_to_lower, p_state_change_support,
clk_mgr_base->clks.p_state_change_support)) {
clk_mgr_base->clks.p_state_change_support =
p_state_change_support;
--
2.29.0
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[PATCH 17/23] drm/amd/display: [FW Promotion] Release 0.0.56
From: Anthony Koo
More updates to the comments to better describe the function of
different cmds and parameters in the dmub interface.
Signed-off-by: Anthony Koo
Reviewed-by: Aric Cyr
Acked-by: Solomon Chiu
---
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 668 ++
1 file changed, 526 insertions(+), 142 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index b6f4db3af5e8..f07b348f7c29 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -47,10 +47,10 @@
/* Firmware versioning. */
#ifdef DMUB_EXPOSE_VERSION
-#define DMUB_FW_VERSION_GIT_HASH 0x920aff8b2
+#define DMUB_FW_VERSION_GIT_HASH 0xc29b1734b
#define DMUB_FW_VERSION_MAJOR 0
#define DMUB_FW_VERSION_MINOR 0
-#define DMUB_FW_VERSION_REVISION 55
+#define DMUB_FW_VERSION_REVISION 56
#define DMUB_FW_VERSION_TEST 0
#define DMUB_FW_VERSION_VBIOS 0
#define DMUB_FW_VERSION_HOTFIX 0
@@ -120,14 +120,23 @@
/* Trace buffer offset for entry */
#define TRACE_BUFFER_ENTRY_OFFSET 16
+/**
+ * Physical framebuffer address location, 64-bit.
+ */
#ifndef PHYSICAL_ADDRESS_LOC
#define PHYSICAL_ADDRESS_LOC union large_integer
#endif
+/**
+ * OS/FW agnostic memcpy
+ */
#ifndef dmub_memcpy
#define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes))
#endif
+/**
+ * OS/FW agnostic memset
+ */
#ifndef dmub_memset
#define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes))
#endif
@@ -136,16 +145,22 @@
extern "C" {
#endif
+/**
+ * OS/FW agnostic udelay
+ */
#ifndef dmub_udelay
#define dmub_udelay(microseconds) udelay(microseconds)
#endif
+/**
+ * union dmub_addr - DMUB physical/virtual 64-bit address.
+ */
union dmub_addr {
struct {
- uint32_t low_part;
- uint32_t high_part;
- } u;
- uint64_t quad_part;
+ uint32_t low_part; /**< Lower 32 bits */
+ uint32_t high_part; /**< Upper 32 bits */
+ } u; /*<< Low/high bit access */
+ uint64_t quad_part; /*<< 64 bit address */
};
/**
@@ -187,11 +202,12 @@ struct dmub_feature_caps {
* Max PSR version supported by FW.
*/
uint8_t psr;
-
- /**
-* Reserved.
-*/
+#ifndef TRIM_FAMS
+ uint8_t fw_assisted_mclk_switch;
+ uint8_t reserved[6];
+#else
uint8_t reserved[7];
+#endif
};
#if defined(__cplusplus)
@@ -225,18 +241,20 @@ struct dmub_feature_caps {
* @dal_fw: 1 if the firmware is DAL
*/
struct dmub_fw_meta_info {
- uint32_t magic_value;
- uint32_t fw_region_size;
- uint32_t trace_buffer_size;
- uint32_t fw_version;
- uint8_t dal_fw;
- uint8_t reserved[3];
+ uint32_t magic_value; /**< magic value identifying DMUB firmware meta
info */
+ uint32_t fw_region_size; /**< size of the firmware state region */
+ uint32_t trace_buffer_size; /**< size of the tracebuffer region */
+ uint32_t fw_version; /**< the firmware version information */
+ uint8_t dal_fw; /**< 1 if the firmware is DAL */
+ uint8_t reserved[3]; /**< padding bits */
};
-/* Ensure that the structure remains 64 bytes. */
+/**
+ * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes
+ */
union dmub_fw_meta {
- struct dmub_fw_meta_info info;
- uint8_t reserved[64];
+ struct dmub_fw_meta_info info; /**< metadata info */
+ uint8_t reserved[64]; /**< padding bits */
};
#pragma pack(pop)
@@ -244,13 +262,19 @@ union dmub_fw_meta {
//==
//< DMUB Trace
Buffer>
//==
+/**
+ * dmub_trace_code_t - firmware trace code, 32-bits
+ */
typedef uint32_t dmub_trace_code_t;
+/**
+ * struct dmcub_trace_buf_entry - Firmware trace entry
+ */
struct dmcub_trace_buf_entry {
- dmub_trace_code_t trace_code;
- uint32_t tick_count;
- uint32_t param0;
- uint32_t param1;
+ dmub_trace_code_t trace_code; /**< trace code for the event */
+ uint32_t tick_count; /**< the tick count at time of trace */
+ uint32_t param0; /**< trace defined parameter 0 */
+ uint32_t param1; /**< trace defined parameter 1 */
};
//==
@@ -265,42 +289,49 @@ struct dmcub_trace_buf_entry {
* SCRATCH15: FW Boot Options register
*/
-/* Register bit definition for SCRATCH0 */
+/**
+ * union dmub_fw_boot_status - Status bit definitions for SCRATCH0.
+ */
union dmub_fw_boot_status {
struct {
- uint32_t dal_fw : 1;
- uint32_t mailbox_rdy : 1;
- uint32_t optimized_init_done : 1;
- uint32_t restore_required : 1;
- } bits;
-
[PATCH 16/23] drm/amd/display: Add debugfs to control DMUB trace buffer events
From: "Leo (Hanghong) Ma"
[Why]
We want to have a debugfs interface to enable or disable DMCUB
trace buffer events.
[How]
Add debugfs interface to enable or disable trace buffer events.
Signed-off-by: Leo (Hanghong) Ma
Reviewed-by: Harry Wentland
Acked-by: Solomon Chiu
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 1 +
.../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 37 +++
2 files changed, 38 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index be931efc772d..2c9eed78f6df 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -395,6 +395,7 @@ struct amdgpu_display_manager {
*/
struct amdgpu_encoder mst_encoders[AMDGPU_DM_MAX_CRTC];
bool force_timing_sync;
+ bool dmcub_trace_event_en;
/**
* @da_list:
*
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index b8644f49e0f2..927de7678a4f 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -34,6 +34,7 @@
#include "resource.h"
#include "dsc.h"
#include "dc_link_dp.h"
+#include "dc/dc_dmub_srv.h"
struct dmub_debugfs_trace_header {
uint32_t entry_count;
@@ -2490,6 +2491,39 @@ static int psr_get(void *data, u64 *val)
return 0;
}
+/*
+ * Set dmcub trace event IRQ enable or disable.
+ * Usage to enable dmcub trace event IRQ: echo 1 >
/sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en
+ * Usage to disable dmcub trace event IRQ: echo 0 >
/sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en
+ */
+static int dmcub_trace_event_state_set(void *data, u64 val)
+{
+ struct amdgpu_device *adev = data;
+
+ if (val == 1 || val == 0) {
+ dc_dmub_trace_event_control(adev->dm.dc, val);
+ adev->dm.dmcub_trace_event_en = (bool)val;
+ } else
+ return 0;
+
+ return 0;
+}
+
+/*
+ * The interface doesn't need get function, so it will return the
+ * value of zero
+ * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en
+ */
+static int dmcub_trace_event_state_get(void *data, u64 *val)
+{
+ struct amdgpu_device *adev = data;
+
+ *val = adev->dm.dmcub_trace_event_en;
+ return 0;
+}
+
+DEFINE_DEBUGFS_ATTRIBUTE(dmcub_trace_event_state_fops,
dmcub_trace_event_state_get,
+dmcub_trace_event_state_set, "%llu\n");
DEFINE_DEBUGFS_ATTRIBUTE(psr_fops, psr_get, NULL, "%llu\n");
@@ -2970,4 +3004,7 @@ void dtn_debugfs_init(struct amdgpu_device *adev)
debugfs_create_file_unsafe("amdgpu_dm_force_timing_sync", 0644, root,
adev, _timing_sync_ops);
+
+ debugfs_create_file_unsafe("amdgpu_dm_dmcub_trace_event_en", 0644, root,
+ adev, _trace_event_state_fops);
}
--
2.29.0
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[PATCH 15/23] drm/amd/display: Separate caps for maximum RGB and YUV plane counts
From: Atufa Khan
Not all ASICs have same plane capabilities so need to split them
out for proper support handling.
Signed-off-by: Atufa Khan
Reviewed-by: Aric Cyr
Acked-by: Solomon Chiu
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 ++
drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c | 2 ++
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 2 ++
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 ++
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 2 ++
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c | 2 ++
drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c | 2 ++
drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c | 2 ++
8 files changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 2088508dac1a..d26472ef1572 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -155,6 +155,8 @@ struct dc_caps {
uint32_t max_links;
uint32_t max_audios;
uint32_t max_slave_planes;
+ uint32_t max_slave_yuv_planes;
+ uint32_t max_slave_rgb_planes;
uint32_t max_planes;
uint32_t max_downscale_ratio;
uint32_t i2c_speed_in_khz;
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
index d7fcc5cccdce..ef56eab4e5da 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
@@ -1272,6 +1272,8 @@ static bool underlay_create(struct dc_context *ctx,
struct resource_pool *pool)
/* update the public caps to indicate an underlay is available */
ctx->dc->caps.max_slave_planes = 1;
+ ctx->dc->caps.max_slave_yuv_planes = 1;
+ ctx->dc->caps.max_slave_rgb_planes = 0;
return true;
}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index 33811953585b..d079f4e491e5 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -1422,6 +1422,8 @@ static bool dcn10_resource_construct(
dc->caps.max_cursor_size = 256;
dc->caps.min_horizontal_blanking_period = 80;
dc->caps.max_slave_planes = 1;
+ dc->caps.max_slave_yuv_planes = 1;
+ dc->caps.max_slave_rgb_planes = 0;
dc->caps.is_apu = true;
dc->caps.post_blend_color_processing = false;
dc->caps.extended_aux_timeout_support = false;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 9ae12a87d685..2307b3517821 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -3703,6 +3703,8 @@ static bool dcn20_resource_construct(
dc->caps.dmdata_alloc_size = 2048;
dc->caps.max_slave_planes = 1;
+ dc->caps.max_slave_yuv_planes = 1;
+ dc->caps.max_slave_rgb_planes = 1;
dc->caps.post_blend_color_processing = true;
dc->caps.force_dp_tps4_for_cp2520 = true;
dc->caps.extended_aux_timeout_support = true;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index bd8e4c0f92db..e62f931fc269 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -1982,6 +1982,8 @@ static bool dcn21_resource_construct(
dc->caps.dmdata_alloc_size = 2048;
dc->caps.max_slave_planes = 1;
+ dc->caps.max_slave_yuv_planes = 1;
+ dc->caps.max_slave_rgb_planes = 1;
dc->caps.post_blend_color_processing = true;
dc->caps.force_dp_tps4_for_cp2520 = true;
dc->caps.extended_aux_timeout_support = true;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
index a3ac7e275f3d..deab48806fa2 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
@@ -2568,6 +2568,8 @@ static bool dcn30_resource_construct(
dc->caps.cursor_cache_size = dc->caps.max_cursor_size *
dc->caps.max_cursor_size * 8;
dc->caps.max_slave_planes = 1;
+ dc->caps.max_slave_yuv_planes = 1;
+ dc->caps.max_slave_rgb_planes = 1;
dc->caps.post_blend_color_processing = true;
dc->caps.force_dp_tps4_for_cp2520 = true;
dc->caps.extended_aux_timeout_support = true;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
index 6358b2b266cf..5f29a4f85ef2 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
@@ -1766,6 +1766,8 @@ static bool
[PATCH 14/23] drm/amd/display: Fix no previous prototype warning
From: Wayne Lin
[Why]
Received compiling warning:
All warnings (new ones prefixed by >>):
>> drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:5574:5:
warning: no previous prototype for 'amdgpu_dm_crtc_late_register'
[-Wmissing-prototypes]
5574 | int amdgpu_dm_crtc_late_register(struct drm_crtc *crtc)
| ^~~~
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c: In
function 'dm_update_mst_vcpi_slots_for_dsc':
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:6405:46:
warning: variable 'old_con_state' set but not used
[-Wunused-but-set-variable]
6405 | struct drm_connector_state *new_con_state, *old_con_state;
| ^
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c: In
function 'amdgpu_dm_commit_cursors':
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:8006:44:
warning: variable 'new_plane_state' set but not used
[-Wunused-but-set-variable]
8006 | struct drm_plane_state *old_plane_state, *new_plane_state;
|^~~
vim +/amdgpu_dm_crtc_late_register +5574
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c
5572
5573 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
> 5574 int amdgpu_dm_crtc_late_register(struct drm_crtc *crtc)
5575 {
5576 crtc_debugfs_init(crtc);
5577
5578 return 0;
5579 }
5580 #endif
5581
[How]
Fix it with declaration as "static"
Reported-by: kernel test robot
Signed-off-by: Wayne Lin
Reviewed-by: Rodrigo Siqueira
Acked-by: Solomon Chiu
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index df060c354eb8..3db69f5bd6e9 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -5562,7 +5562,7 @@ dm_crtc_duplicate_state(struct drm_crtc *crtc)
}
#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
-int amdgpu_dm_crtc_late_register(struct drm_crtc *crtc)
+static int amdgpu_dm_crtc_late_register(struct drm_crtc *crtc)
{
crtc_debugfs_init(crtc);
--
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[PATCH 13/23] drm/amd/display: Fix secure display lock problems
From: Wayne Lin
[Why]
Find out few locks problems while doing secure display. They are
following few parts:
1. crc_rd_work_lock in amdgpu_dm_crtc_handle_crc_window_irq() should
also use spin_lock_irqsave instead of spin_lock_irq.
2. In crc_win_update_set(), crc_rd_work_lock should be grabbed after
obtaining lock event_lock. Otherwise, will cause deadlock by conflicting
the lock order in amdgpu_dm_crtc_handle_crc_window_irq()
3. flush_work() in crc_win_update_set() is no need and will cause
deadlock since amdgpu_dm_crtc_notify_ta_to_read() also tries to grab
lock crc_rd_work_lock.
[How]
Fix above problems.
Signed-off-by: Wayne Lin
Reviewed-by: Solomon Chiu
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c | 10 +-
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 6 ++
2 files changed, 7 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
index 3adbaf50a558..c6d6baab106e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
@@ -433,7 +433,7 @@ void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc
*crtc)
struct amdgpu_device *adev = NULL;
struct crc_rd_work *crc_rd_wrk = NULL;
struct crc_params *crc_window = NULL, tmp_window;
- unsigned long flags;
+ unsigned long flags1, flags2;
struct crtc_position position;
uint32_t v_blank;
uint32_t v_back_porch;
@@ -447,7 +447,7 @@ void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc
*crtc)
adev = drm_to_adev(crtc->dev);
drm_dev = crtc->dev;
- spin_lock_irqsave(_dev->event_lock, flags);
+ spin_lock_irqsave(_dev->event_lock, flags1);
stream_state = acrtc->dm_irq_params.stream;
cur_crc_src = acrtc->dm_irq_params.crc_src;
timing_out = _state->timing;
@@ -508,10 +508,10 @@ void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc
*crtc)
if
(acrtc->dm_irq_params.crc_window.skip_frame_cnt == 0) {
if (adev->dm.crc_rd_wrk) {
crc_rd_wrk =
adev->dm.crc_rd_wrk;
-
spin_lock_irq(_rd_wrk->crc_rd_work_lock);
+
spin_lock_irqsave(_rd_wrk->crc_rd_work_lock, flags2);
crc_rd_wrk->phy_inst =
stream_state->link->link_enc_hw_inst;
-
spin_unlock_irq(_rd_wrk->crc_rd_work_lock);
+
spin_unlock_irqrestore(_rd_wrk->crc_rd_work_lock, flags2);
schedule_work(_rd_wrk->notify_ta_work);
}
} else {
@@ -522,7 +522,7 @@ void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc
*crtc)
}
cleanup:
- spin_unlock_irqrestore(_dev->event_lock, flags);
+ spin_unlock_irqrestore(_dev->event_lock, flags1);
}
void amdgpu_dm_crtc_secure_display_resume(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index 6d839d3fb6a3..b8644f49e0f2 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -2695,14 +2695,12 @@ static int crc_win_update_set(void *data, u64 val)
struct crc_rd_work *crc_rd_wrk = adev->dm.crc_rd_wrk;
if (val) {
- spin_lock_irq(_rd_wrk->crc_rd_work_lock);
spin_lock_irq(_to_drm(adev)->event_lock);
+ spin_lock_irq(_rd_wrk->crc_rd_work_lock);
if (crc_rd_wrk && crc_rd_wrk->crtc) {
old_crtc = crc_rd_wrk->crtc;
old_acrtc = to_amdgpu_crtc(old_crtc);
- flush_work(>dm.crc_rd_wrk->notify_ta_work);
}
-
new_acrtc = to_amdgpu_crtc(new_crtc);
if (old_crtc && old_crtc != new_crtc) {
@@ -2720,8 +2718,8 @@ static int crc_win_update_set(void *data, u64 val)
new_acrtc->dm_irq_params.crc_window.skip_frame_cnt = 0;
crc_rd_wrk->crtc = new_crtc;
}
- spin_unlock_irq(_to_drm(adev)->event_lock);
spin_unlock_irq(_rd_wrk->crc_rd_work_lock);
+ spin_unlock_irq(_to_drm(adev)->event_lock);
}
return 0;
--
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[PATCH 12/23] drm/amd/display: Fix typo for helpers function name
From: "Leo (Hanghong) Ma"
[why]
Word "helper" was misspelled as "helpes" in
dm_helpes_dmub_outbox0_interrupt_control function.
[how]
Fix the spelling.
Signed-off-by: Leo (Hanghong) Ma
Reviewed-by: Yongqiang Sun
Acked-by: Solomon Chiu
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 2 +-
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 2 +-
drivers/gpu/drm/amd/display/dc/dm_helpers.h | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index b0e49d01c206..09bdffb3a09e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -698,7 +698,7 @@ void dm_helpers_free_gpu_mem(
}
}
-bool dm_helpes_dmub_outbox0_interrupt_control(struct dc_context *ctx, bool
enable)
+bool dm_helpers_dmub_outbox0_interrupt_control(struct dc_context *ctx, bool
enable)
{
// TODO
return true;
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
index 68453c29c617..6b72af2b3f4c 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
@@ -180,5 +180,5 @@ bool dc_dmub_srv_get_dmub_outbox0_msg(const struct dc *dc,
struct dmcub_trace_bu
void dc_dmub_trace_event_control(struct dc *dc, bool enable)
{
- dm_helpes_dmub_outbox0_interrupt_control(dc->ctx, enable);
+ dm_helpers_dmub_outbox0_interrupt_control(dc->ctx, enable);
}
diff --git a/drivers/gpu/drm/amd/display/dc/dm_helpers.h
b/drivers/gpu/drm/amd/display/dc/dm_helpers.h
index 65704f46c79b..f41db27c44de 100644
--- a/drivers/gpu/drm/amd/display/dc/dm_helpers.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_helpers.h
@@ -156,6 +156,6 @@ void dm_set_dcn_clocks(
struct dc_context *ctx,
struct dc_clocks *clks);
-bool dm_helpes_dmub_outbox0_interrupt_control(struct dc_context *ctx, bool
enable);
+bool dm_helpers_dmub_outbox0_interrupt_control(struct dc_context *ctx, bool
enable);
#endif /* __DM_HELPERS__ */
--
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[PATCH 11/23] drm/amd/display: Remove MPC gamut remap logic for DCN30
From: Dillon Varone
[Why?]
Should only reroute gamut remap to mpc unless 3D LUT is not used and all
planes are using the same src->dest.
[How?]
Remove DCN30 specific logic for rerouting gamut remap to mpc.
Signed-off-by: Dillon Varone
Reviewed-by: Krunoslav Kovac
Acked-by: Aric Cyr
Acked-by: Solomon Chiu
---
.../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 34 ++-
1 file changed, 2 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 0d3c7e42204f..6a10daec15cc 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1507,38 +1507,8 @@ static void dcn20_update_dchubp_dpp(
if (pipe_ctx->update_flags.bits.enable ||
pipe_ctx->update_flags.bits.opp_changed
|| pipe_ctx->stream->update_flags.bits.gamut_remap
|| pipe_ctx->stream->update_flags.bits.out_csc) {
- struct mpc *mpc =
pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
-
- if (mpc->funcs->set_gamut_remap) {
- int i;
- int mpcc_id = hubp->inst;
- struct mpc_grph_gamut_adjustment adjust;
- bool enable_remap_dpp = false;
-
- memset(, 0, sizeof(adjust));
- adjust.gamut_adjust_type =
GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
-
- /* save the enablement of gamut remap for dpp */
- enable_remap_dpp =
pipe_ctx->stream->gamut_remap_matrix.enable_remap;
-
- /* force bypass gamut remap for dpp/cm */
- pipe_ctx->stream->gamut_remap_matrix.enable_remap =
false;
- dc->hwss.program_gamut_remap(pipe_ctx);
-
- /* restore gamut remap flag and use this remap into mpc
*/
- pipe_ctx->stream->gamut_remap_matrix.enable_remap =
enable_remap_dpp;
-
- /* build remap matrix for top plane if enabled */
- if (enable_remap_dpp && pipe_ctx->top_pipe == NULL) {
- adjust.gamut_adjust_type =
GRAPHICS_GAMUT_ADJUST_TYPE_SW;
- for (i = 0; i <
CSC_TEMPERATURE_MATRIX_SIZE; i++)
- adjust.temperature_matrix[i] =
-
pipe_ctx->stream->gamut_remap_matrix.matrix[i];
- }
- mpc->funcs->set_gamut_remap(mpc, mpcc_id, );
- } else
- /* dpp/cm gamut remap*/
- dc->hwss.program_gamut_remap(pipe_ctx);
+ /* dpp/cm gamut remap*/
+ dc->hwss.program_gamut_remap(pipe_ctx);
/*call the dcn2 method which uses mpc csc*/
dc->hwss.program_output_csc(dc,
--
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[PATCH 10/23] drm/amd/display: Correct algorithm for reversed gamma
From: Calvin Hou
[Why]
DCN30 needs to correctly program reversed gamma curve, which DCN20
already has.
Also needs to fix a bug that 252-255 values are clipped.
[How]
Apply two fixes into DCN30.
Signed-off-by: Calvin Hou
Reviewed-by: Jun Lei
Reviewed-by: Krunoslav Kovac
Acked-by: Solomon Chiu
Acked-by: Vladimir Stempen
---
.../amd/display/dc/dcn30/dcn30_cm_common.c| 26 +--
1 file changed, 18 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c
index 41a1d0e9b7e2..e0df9b0065f9 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c
@@ -113,6 +113,7 @@ bool cm3_helper_translate_curve_to_hw_format(
struct pwl_result_data *rgb_resulted;
struct pwl_result_data *rgb;
struct pwl_result_data *rgb_plus_1;
+ struct pwl_result_data *rgb_minus_1;
struct fixed31_32 end_value;
int32_t region_start, region_end;
@@ -140,7 +141,7 @@ bool cm3_helper_translate_curve_to_hw_format(
region_start = -MAX_LOW_POINT;
region_end = NUMBER_REGIONS - MAX_LOW_POINT;
} else {
- /* 10 segments
+ /* 11 segments
* segment is from 2^-10 to 2^0
* There are less than 256 points, for optimization
*/
@@ -154,9 +155,10 @@ bool cm3_helper_translate_curve_to_hw_format(
seg_distr[7] = 4;
seg_distr[8] = 4;
seg_distr[9] = 4;
+ seg_distr[10] = 1;
region_start = -10;
- region_end = 0;
+ region_end = 1;
}
for (i = region_end - region_start; i < MAX_REGIONS_NUMBER ; i++)
@@ -189,6 +191,10 @@ bool cm3_helper_translate_curve_to_hw_format(
rgb_resulted[hw_points - 1].green =
output_tf->tf_pts.green[start_index];
rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index];
+ rgb_resulted[hw_points].red = rgb_resulted[hw_points - 1].red;
+ rgb_resulted[hw_points].green = rgb_resulted[hw_points - 1].green;
+ rgb_resulted[hw_points].blue = rgb_resulted[hw_points - 1].blue;
+
// All 3 color channels have same x
corner_points[0].red.x = dc_fixpt_pow(dc_fixpt_from_int(2),
dc_fixpt_from_int(region_start));
@@ -259,15 +265,18 @@ bool cm3_helper_translate_curve_to_hw_format(
rgb = rgb_resulted;
rgb_plus_1 = rgb_resulted + 1;
+ rgb_minus_1 = rgb;
i = 1;
while (i != hw_points + 1) {
- if (dc_fixpt_lt(rgb_plus_1->red, rgb->red))
- rgb_plus_1->red = rgb->red;
- if (dc_fixpt_lt(rgb_plus_1->green, rgb->green))
- rgb_plus_1->green = rgb->green;
- if (dc_fixpt_lt(rgb_plus_1->blue, rgb->blue))
- rgb_plus_1->blue = rgb->blue;
+ if (i >= hw_points - 1) {
+ if (dc_fixpt_lt(rgb_plus_1->red, rgb->red))
+ rgb_plus_1->red = dc_fixpt_add(rgb->red,
rgb_minus_1->delta_red);
+ if (dc_fixpt_lt(rgb_plus_1->green, rgb->green))
+ rgb_plus_1->green = dc_fixpt_add(rgb->green,
rgb_minus_1->delta_green);
+ if (dc_fixpt_lt(rgb_plus_1->blue, rgb->blue))
+ rgb_plus_1->blue = dc_fixpt_add(rgb->blue,
rgb_minus_1->delta_blue);
+ }
rgb->delta_red = dc_fixpt_sub(rgb_plus_1->red, rgb->red);
rgb->delta_green = dc_fixpt_sub(rgb_plus_1->green, rgb->green);
@@ -283,6 +292,7 @@ bool cm3_helper_translate_curve_to_hw_format(
}
++rgb_plus_1;
+ rgb_minus_1 = rgb;
++rgb;
++i;
}
--
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[PATCH 09/23] drm/amd/display: Add changes for dsc bpp in 16ths and unify bw calculations
From: Dillon Varone
[Why?]
Some code still expected bpp to be used in whole bits, not 16ths. dsc.c uses
redundant function now found in dc to calculate stream bandwidth from timing.
[How?]
Fix code to work with 16ths instead of whole bits for dsc bpp.
Refactor get_dsc_bandwidth to accept inputs in 16ths of a bit.
Use dc function to calculate bandwidth from timing, and make dsc bw calculation
a part of dsc.c.
Signed-off-by: Dillon Varone
Reviewed-by: Wenjing Liu
Acked-by: Solomon Chiu
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 9 +-
drivers/gpu/drm/amd/display/dc/dc_dsc.h | 9 +-
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 105 ++
3 files changed, 43 insertions(+), 80 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 9337e87a73e7..30263009851e 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -3497,19 +3497,16 @@ void dc_link_enable_hpd_filter(struct dc_link *link,
bool enable)
}
}
+uint32_t dc_dsc_stream_bandwidth_in_kbps(uint32_t pix_clk_100hz, uint32_t
bpp_x16);
+
uint32_t dc_bandwidth_in_kbps_from_timing(
const struct dc_crtc_timing *timing)
{
uint32_t bits_per_channel = 0;
uint32_t kbps;
- struct fixed31_32 link_bw_kbps;
if (timing->flags.DSC) {
- link_bw_kbps = dc_fixpt_from_int(timing->pix_clk_100hz);
- link_bw_kbps = dc_fixpt_div_int(link_bw_kbps, 160);
- link_bw_kbps = dc_fixpt_mul_int(link_bw_kbps,
timing->dsc_cfg.bits_per_pixel);
- kbps = dc_fixpt_ceil(link_bw_kbps);
- return kbps;
+ return dc_dsc_stream_bandwidth_in_kbps(timing->pix_clk_100hz,
timing->dsc_cfg.bits_per_pixel);
}
switch (timing->display_color_depth) {
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dsc.h
b/drivers/gpu/drm/amd/display/dc/dc_dsc.h
index ec55b77727d5..0c5d98524536 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dsc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dsc.h
@@ -51,6 +51,7 @@ struct dc_dsc_policy {
int min_slice_height; // Must not be less than 8
uint32_t max_target_bpp;
uint32_t min_target_bpp;
+ uint32_t preferred_bpp_x16;
bool enable_dsc_when_not_needed;
};
@@ -62,8 +63,8 @@ bool dc_dsc_parse_dsc_dpcd(const struct dc *dc,
bool dc_dsc_compute_bandwidth_range(
const struct display_stream_compressor *dsc,
uint32_t dsc_min_slice_height_override,
- uint32_t min_bpp,
- uint32_t max_bpp,
+ uint32_t min_bpp_x16,
+ uint32_t max_bpp_x16,
const struct dsc_dec_dpcd_caps *dsc_sink_caps,
const struct dc_crtc_timing *timing,
struct dc_dsc_bw_range *range);
@@ -77,8 +78,10 @@ bool dc_dsc_compute_config(
const struct dc_crtc_timing *timing,
struct dc_dsc_config *dsc_cfg);
+uint32_t dc_dsc_stream_bandwidth_in_kbps(uint32_t pix_clk_100hz, uint32_t
bpp_x16);
+
void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing,
- uint32_t max_target_bpp_limit_override,
+ uint32_t max_target_bpp_limit_override_x16,
struct dc_dsc_policy *policy);
void dc_dsc_policy_set_max_target_bpp_limit(uint32_t limit);
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
index c62d0eddc9c6..be57088d185d 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
@@ -37,59 +37,6 @@ static uint32_t dsc_policy_max_target_bpp_limit = 16;
/* default DSC policy enables DSC only when needed */
static bool dsc_policy_enable_dsc_when_not_needed;
-static uint32_t dc_dsc_bandwidth_in_kbps_from_timing(
- const struct dc_crtc_timing *timing)
-{
- uint32_t bits_per_channel = 0;
- uint32_t kbps;
-
- if (timing->flags.DSC) {
- kbps = (timing->pix_clk_100hz * timing->dsc_cfg.bits_per_pixel);
- kbps = kbps / 160 + ((kbps % 160) ? 1 : 0);
- return kbps;
- }
-
- switch (timing->display_color_depth) {
- case COLOR_DEPTH_666:
- bits_per_channel = 6;
- break;
- case COLOR_DEPTH_888:
- bits_per_channel = 8;
- break;
- case COLOR_DEPTH_101010:
- bits_per_channel = 10;
- break;
- case COLOR_DEPTH_121212:
- bits_per_channel = 12;
- break;
- case COLOR_DEPTH_141414:
- bits_per_channel = 14;
- break;
- case COLOR_DEPTH_161616:
- bits_per_channel = 16;
- break;
- default:
- break;
- }
-
- ASSERT(bits_per_channel != 0);
-
- kbps = timing->pix_clk_100hz / 10;
-
[PATCH 08/23] drm/amd/display: Increase precision for bpp in DSC calculations
From: Jun Lei
[Why?]
Many DSC variables and related functions use whole bits for bpp.
[How?]
Change variables and related functions to use 16ths of a bit for bpp.
Signed-off-by: Dillon Varone
Reviewed-by: Wenjing Liu
Acked-by: Solomon Chiu
---
drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
index 48d3ed97ead9..bcec019efa6f 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
@@ -770,6 +770,7 @@ struct dc_crtc_timing {
#endif
struct dc_crtc_timing_flags flags;
+ uint32_t dsc_fixed_bits_per_pixel_x16; /* DSC target bitrate in 1/16 of
bpp (e.g. 128 -> 8bpp) */
struct dc_dsc_config dsc_cfg;
};
--
2.29.0
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[PATCH 07/23] drm/amd/display: Bypass sink detect when there are no eDPs connected
From: Jake Wang
[How & Why]
Check DC config to determine if there are any eDPs connected. If there
are no eDPs connected, bypass sink detect when querying eDP presence.
Signed-off-by: Jake Wang
Reviewed-by: Nicholas Kazlauskas
Acked-by: Solomon Chiu
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 13 ++---
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 3dc49964ea7f..dffd150180ec 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1096,20 +1096,19 @@ static void detect_edp_presence(struct dc *dc)
{
struct dc_link *edp_links[MAX_NUM_EDP];
struct dc_link *edp_link = NULL;
+ enum dc_connection_type type;
int i;
int edp_num;
- bool edp_sink_present = true;
get_edp_links(dc, edp_links, _num);
if (!edp_num)
return;
- if (dc->config.edp_not_connected) {
- edp_sink_present = false;
- } else {
- enum dc_connection_type type;
- for (i = 0; i < edp_num; i++) {
- edp_link = edp_links[i];
+ for (i = 0; i < edp_num; i++) {
+ edp_link = edp_links[i];
+ if (dc->config.edp_not_connected) {
+ edp_link->edp_sink_present = false;
+ } else {
dc_link_detect_sink(edp_link, );
edp_link->edp_sink_present = (type !=
dc_connection_none);
}
--
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[PATCH 06/23] drm/amd/display: Fix for outbox1 ring buffer typecasting issue
From: Meenakshikumar Somasundaram [WHY] Compiler warning "pointer to integer of different size" reported on outbox1 ring buffer address typecasting. Reported-by: kernel test robot [HOW] Fixed the issue by typecasting with character pointer. Signed-off-by: Meenakshikumar Somasundaram Reviewed-by: Jun Lei Acked-by: Solomon Chiu --- drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c index 1ee2000ad099..8ba0a9e2da54 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c @@ -508,7 +508,7 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub, // Initialize outbox1 ring buffer rb_params.ctx = dmub; - rb_params.base_address = (void *) ((uint64_t) (mail_fb->cpu_addr) + DMUB_RB_SIZE); + rb_params.base_address = (void *) ((uint8_t *) (mail_fb->cpu_addr) + DMUB_RB_SIZE); rb_params.capacity = DMUB_RB_SIZE; dmub_rb_init(>outbox1_rb, _params); -- 2.29.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 05/23] drm/amd/display: Fix UBSAN warning for not a valid value for type '_Bool'
From: Anson Jacob
[Why]
dc_cursor_position do not initialise position.translate_by_source when
crtc or plane->state->fb is NULL. UBSAN caught this error in
dce110_set_cursor_position, as the value was garbage.
[How]
Initialise dc_cursor_position structure elements to 0 in handle_cursor_update
before calling get_cursor_position.
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1471
Reported-by: Lyude Paul
Signed-off-by: Anson Jacob
Reviewed-by: Aurabindo Jayamohanan Pillai
Acked-by: Solomon Chiu
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 7347a3dd66fc..df060c354eb8 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -7612,10 +7612,6 @@ static int get_cursor_position(struct drm_plane *plane,
struct drm_crtc *crtc,
int x, y;
int xorigin = 0, yorigin = 0;
- position->enable = false;
- position->x = 0;
- position->y = 0;
-
if (!crtc || !plane->state->fb)
return 0;
@@ -7662,7 +7658,7 @@ static void handle_cursor_update(struct drm_plane *plane,
struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state)
: NULL;
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
uint64_t address = afb ? afb->address : 0;
- struct dc_cursor_position position;
+ struct dc_cursor_position position = {0};
struct dc_cursor_attributes attributes;
int ret;
--
2.29.0
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[PATCH 04/23] drm/amd/display: System black screen hangs on driver load
From: Aric Cyr
This reverts commit bea6beb76a9f19a9a86d24d304f27b3cff5f1791
as it causes crash on driver load in some scenarios.
Signed-off-by: Aric Cyr
Reviewed-by: Martin Leung
Acked-by: Solomon Chiu
---
.../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 48 +--
drivers/gpu/drm/amd/display/dc/dc.h | 2 -
2 files changed, 2 insertions(+), 48 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
index 3946d12e9fb1..01b1853b7750 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
@@ -761,43 +761,6 @@ static struct wm_table ddr4_wm_table_rn = {
}
};
-static struct wm_table ddr4_1R_wm_table_rn = {
- .entries = {
- {
- .wm_inst = WM_A,
- .wm_type = WM_TYPE_PSTATE_CHG,
- .pstate_latency_us = 11.72,
- .sr_exit_time_us = 13.90,
- .sr_enter_plus_exit_time_us = 14.80,
- .valid = true,
- },
- {
- .wm_inst = WM_B,
- .wm_type = WM_TYPE_PSTATE_CHG,
- .pstate_latency_us = 11.72,
- .sr_exit_time_us = 13.90,
- .sr_enter_plus_exit_time_us = 14.80,
- .valid = true,
- },
- {
- .wm_inst = WM_C,
- .wm_type = WM_TYPE_PSTATE_CHG,
- .pstate_latency_us = 11.72,
- .sr_exit_time_us = 13.90,
- .sr_enter_plus_exit_time_us = 14.80,
- .valid = true,
- },
- {
- .wm_inst = WM_D,
- .wm_type = WM_TYPE_PSTATE_CHG,
- .pstate_latency_us = 11.72,
- .sr_exit_time_us = 13.90,
- .sr_enter_plus_exit_time_us = 14.80,
- .valid = true,
- },
- }
-};
-
static struct wm_table lpddr4_wm_table_rn = {
.entries = {
{
@@ -969,12 +932,8 @@ void rn_clk_mgr_construct(
} else {
if (is_green_sardine)
rn_bw_params.wm_table = ddr4_wm_table_gs;
- else {
- if (ctx->dc->config.is_single_rank_dimm)
- rn_bw_params.wm_table =
ddr4_1R_wm_table_rn;
- else
- rn_bw_params.wm_table =
ddr4_wm_table_rn;
- }
+ else
+ rn_bw_params.wm_table = ddr4_wm_table_rn;
}
/* Saved clocks configured at boot for debug purposes */
rn_dump_clk_registers(_mgr->base.boot_snapshot,
_mgr->base, _info);
@@ -992,9 +951,6 @@ void rn_clk_mgr_construct(
if (status == PP_SMU_RESULT_OK &&
ctx->dc_bios && ctx->dc_bios->integrated_info) {
rn_clk_mgr_helper_populate_bw_params
(clk_mgr->base.bw_params, _table, ctx->dc_bios->integrated_info);
- /* treat memory config as single channel if memory is
asymmetrics. */
- if (ctx->dc->config.is_asymmetric_memory)
- clk_mgr->base.bw_params->num_channels = 1;
}
}
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 153093abafbd..2088508dac1a 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -307,8 +307,6 @@ struct dc_config {
#endif
uint64_t vblank_alignment_dto_params;
uint8_t vblank_alignment_max_frame_time_diff;
- bool is_asymmetric_memory;
- bool is_single_rank_dimm;
};
enum visual_confirm {
--
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[PATCH 03/23] drm/amd/display: use max lb for latency hiding
From: Dmytro Laktyushkin
Enable max memory lb config to improve stutter efficiency and
latency hiding. Also increase max number of lb lines to be
used by dml since experiments have shown that there isnt a hard max
beyond what fits in lb.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Eric Bernstein
Acked-by: Solomon Chiu
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 4 +++-
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 6 --
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 9 ++---
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c | 4 +++-
drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c | 4 +++-
drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c | 4 +++-
6 files changed, 22 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index 90e912fef2b3..33811953585b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -82,7 +82,7 @@ const struct _vcs_dpi_ip_params_st dcn1_0_ip = {
.meta_chunk_size_kbytes = 2,
.writeback_chunk_size_kbytes = 2,
.line_buffer_size_bits = 589824,
- .max_line_buffer_lines = 12,
+ .max_line_buffer_lines = 32,
.IsLineBufferBppFixed = 0,
.LineBufferFixedBpp = -1,
.writeback_luma_buffer_size_kbytes = 12,
@@ -619,6 +619,7 @@ static const struct dc_debug_options debug_defaults_drv = {
.recovery_enabled = false, /*enable this by default after
testing.*/
.max_downscale_src_width = 3840,
.underflow_assert_delay_us = 0x,
+ .use_max_lb = true
};
static const struct dc_debug_options debug_defaults_diags = {
@@ -630,6 +631,7 @@ static const struct dc_debug_options debug_defaults_diags =
{
.disable_pplib_clock_request = true,
.disable_pplib_wm_range = true,
.underflow_assert_delay_us = 0x,
+ .use_max_lb = true
};
static void dcn10_dpp_destroy(struct dpp **dpp)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index a65efed63fbf..9ae12a87d685 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -112,7 +112,7 @@ struct _vcs_dpi_ip_params_st dcn2_0_ip = {
.is_line_buffer_bpp_fixed = 0,
.line_buffer_fixed_bpp = 0,
.dcc_supported = true,
- .max_line_buffer_lines = 12,
+ .max_line_buffer_lines = 32,
.writeback_luma_buffer_size_kbytes = 12,
.writeback_chroma_buffer_size_kbytes = 8,
.writeback_chroma_line_buffer_width_pixels = 4,
@@ -180,7 +180,7 @@ static struct _vcs_dpi_ip_params_st dcn2_0_nv14_ip = {
.is_line_buffer_bpp_fixed = 0,
.line_buffer_fixed_bpp = 0,
.dcc_supported = true,
- .max_line_buffer_lines = 12,
+ .max_line_buffer_lines = 32,
.writeback_luma_buffer_size_kbytes = 12,
.writeback_chroma_buffer_size_kbytes = 8,
.writeback_chroma_line_buffer_width_pixels = 4,
@@ -1075,6 +1075,7 @@ static const struct dc_debug_options debug_defaults_drv =
{
.scl_reset_length10 = true,
.sanity_checks = false,
.underflow_assert_delay_us = 0x,
+ .use_max_lb = true
};
static const struct dc_debug_options debug_defaults_diags = {
@@ -1091,6 +1092,7 @@ static const struct dc_debug_options debug_defaults_diags
= {
.scl_reset_length10 = true,
.underflow_assert_delay_us = 0x,
.enable_tri_buf = true,
+ .use_max_lb = true
};
void dcn20_dpp_destroy(struct dpp **dpp)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index 2c4e309d1836..bd8e4c0f92db 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -115,7 +115,7 @@ struct _vcs_dpi_ip_params_st dcn2_1_ip = {
.is_line_buffer_bpp_fixed = 0,
.line_buffer_fixed_bpp = 0,
.dcc_supported = true,
- .max_line_buffer_lines = 12,
+ .max_line_buffer_lines = 32,
.writeback_luma_buffer_size_kbytes = 12,
.writeback_chroma_buffer_size_kbytes = 8,
.writeback_chroma_line_buffer_width_pixels = 4,
@@ -882,7 +882,9 @@ static const struct dc_debug_options debug_defaults_drv = {
.scl_reset_length10 = true,
.sanity_checks = true,
.disable_48mhz_pwrdwn = false,
- .usbc_combo_phy_reset_wa = true
+ .usbc_combo_phy_reset_wa = true,
+ .dmub_command_table = true,
+ .use_max_lb = true
};
static const struct dc_debug_options
[PATCH 02/23] drm/amd/display: Add debug out when viewport too small
From: Nikola Cornij
[why] It helps debugging display setup issues
Signed-off-by: Nikola Cornij
Reviewed-by: Nicholas Kazlauskas
Acked-by: Solomon Chiu
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c| 16 ++--
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 2506e85a19b6..7347a3dd66fc 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -6656,13 +6656,17 @@ static int dm_plane_helper_check_state(struct
drm_plane_state *state,
else if (state->crtc_y + state->crtc_h >
new_crtc_state->mode.crtc_vdisplay)
viewport_height =
new_crtc_state->mode.crtc_vdisplay - state->crtc_y;
- /* If completely outside of screen, viewport_width
and/or viewport_height will be negative,
-* which is still OK to satisfy the condition below,
thereby also covering these cases
-* (when plane is completely outside of screen).
-* x2 for width is because of pipe-split.
-*/
- if (viewport_width < MIN_VIEWPORT_SIZE*2 ||
viewport_height < MIN_VIEWPORT_SIZE)
+ if (viewport_width < 0 || viewport_height < 0) {
+ DRM_DEBUG_ATOMIC("Plane completely outside of
screen\n");
+ return -EINVAL;
+ } else if (viewport_width < MIN_VIEWPORT_SIZE*2) { /*
x2 for width is because of pipe-split. */
+ DRM_DEBUG_ATOMIC("Viewport width %d smaller
than %d\n", viewport_width, MIN_VIEWPORT_SIZE*2);
+ return -EINVAL;
+ } else if (viewport_height < MIN_VIEWPORT_SIZE) {
+ DRM_DEBUG_ATOMIC("Viewport height %d smaller
than %d\n", viewport_height, MIN_VIEWPORT_SIZE);
return -EINVAL;
+ }
+
}
/* Get min/max allowed scaling factors from plane caps. */
--
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[PATCH 01/23] drm/amd/display: 3.2.126.1
From: Aric Cyr Bumping DC version for DMU FW fix Signed-off-by: Aric Cyr Reviewed-by: Aric Cyr Acked-by: Solomon Chiu --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index e0ee6d72b7f4..153093abafbd 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -45,7 +45,7 @@ /* forward declaration */ struct aux_payload; -#define DC_VER "3.2.126" +#define DC_VER "3.2.126.1" #define MAX_SURFACES 3 #define MAX_PLANES 6 -- 2.29.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 00/23] DC Patches March 15, 2021
This DC patchset brings improvements in multiple areas. In summary, we highlight: * Add debug out when viewport too small * use max lb for latency hiding * System black screen hangs on driver load * Fix UBSAN warning for not a valid value for type '_Bool' * Fix for outbox1 ring buffer typecasting issue * Bypass sink detect when there are no eDPs connected * Increase precision for bpp in DSC calculations * Add changes for dsc bpp in 16ths and unify bw calculations * Correct algorithm for reversed gamma * Remove MPC gamut remap logic for DCN30 * Fix typo for helpers function name * Fix secure display lock problems * Fix no previous prototype warning * Separate caps for maximum RGB and YUV plane counts * Add debugfs to control DMUB trace buffer events * [FW Promotion] Release 0.0.56 * DCHUB underflow counter increasing in some scenarios * fix dml prefetch validation * fix dcn3+ bw validation soc param update sequence * add a func to disable accelerated mode * Fix potential memory leak Anson Jacob (1): drm/amd/display: Fix UBSAN warning for not a valid value for type '_Bool' Anthony Koo (1): drm/amd/display: [FW Promotion] Release 0.0.56 Aric Cyr (4): drm/amd/display: 3.2.126.1 drm/amd/display: System black screen hangs on driver load drm/amd/display: DCHUB underflow counter increasing in some scenarios drm/amd/display: 3.2.127 Atufa Khan (1): drm/amd/display: Separate caps for maximum RGB and YUV plane counts Calvin Hou (1): drm/amd/display: Correct algorithm for reversed gamma Dillon Varone (2): drm/amd/display: Add changes for dsc bpp in 16ths and unify bw calculations drm/amd/display: Remove MPC gamut remap logic for DCN30 Dmytro Laktyushkin (3): drm/amd/display: use max lb for latency hiding drm/amd/display: fix dml prefetch validation drm/amd/display: fix dcn3+ bw validation soc param update sequence Jake Wang (1): drm/amd/display: Bypass sink detect when there are no eDPs connected Jun Lei (1): drm/amd/display: Increase precision for bpp in DSC calculations Leo (Hanghong) Ma (2): drm/amd/display: Fix typo for helpers function name drm/amd/display: Add debugfs to control DMUB trace buffer events Meenakshikumar Somasundaram (1): drm/amd/display: Fix for outbox1 ring buffer typecasting issue Nikola Cornij (1): drm/amd/display: Add debug out when viewport too small Qingqing Zhuo (1): drm/amd/display: Fix potential memory leak Wayne Lin (2): drm/amd/display: Fix secure display lock problems drm/amd/display: Fix no previous prototype warning Yao Wang1 (1): drm/amd/display: add a func to disable accelerated mode .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 33 +- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 1 + .../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c | 10 +- .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 43 +- .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 2 +- .../amd/display/dc/bios/bios_parser_helper.c | 5 +- .../amd/display/dc/bios/bios_parser_helper.h | 2 +- .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 48 +- .../display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c | 4 +- drivers/gpu/drm/amd/display/dc/core/dc.c | 31 +- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 9 +- drivers/gpu/drm/amd/display/dc/dc.h | 12 +- drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 2 +- drivers/gpu/drm/amd/display/dc/dc_dsc.h | 9 +- drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 1 + .../display/dc/dce110/dce110_hw_sequencer.c | 2 +- .../amd/display/dc/dce110/dce110_resource.c | 2 + .../drm/amd/display/dc/dcn10/dcn10_resource.c | 6 +- .../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 34 +- .../drm/amd/display/dc/dcn20/dcn20_resource.c | 8 +- .../drm/amd/display/dc/dcn21/dcn21_resource.c | 11 +- .../amd/display/dc/dcn30/dcn30_cm_common.c| 26 +- .../drm/amd/display/dc/dcn30/dcn30_resource.c | 23 +- .../drm/amd/display/dc/dcn30/dcn30_resource.h | 1 + .../amd/display/dc/dcn301/dcn301_resource.c | 7 +- .../amd/display/dc/dcn302/dcn302_resource.c | 7 +- drivers/gpu/drm/amd/display/dc/dm_helpers.h | 2 +- .../dc/dml/dcn20/display_mode_vba_20.c| 1 + .../dc/dml/dcn20/display_mode_vba_20v2.c | 1 + drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 105 +-- .../gpu/drm/amd/display/dc/inc/core_types.h | 2 + .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 668 ++ .../gpu/drm/amd/display/dmub/src/dmub_srv.c | 2 +- 33 files changed, 758 insertions(+), 362 deletions(-) -- 2.29.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 1/1] drm/amdgpu: wrap kiq ring ops with kiq spinlock
On 3/15/21 11:32 AM, Wang, Kevin(Yang) wrote:
[AMD Official Use Only - Internal Distribution Only]
Hi Das,
It seems more reasonable to put spin lock in ring structure, so that
KIQ ring can be treated like other normal ring.
We don't use locks for other rings though.
and do we have other paths to call kiq ring except for kernel
initialization? it seems the kfd and kgd will use kiq in one thread..
This patch is for consistency. It is not fixing any issue/bug.
Nirmoy
thanks.
Best Regards,
Kevin
*From:* amd-gfx on behalf of
Nirmoy Das
*Sent:* Saturday, March 13, 2021 1:08 AM
*To:* Koenig, Christian
*Cc:* Das, Nirmoy ; amd-gfx@lists.freedesktop.org
*Subject:* [PATCH 1/1] drm/amdgpu: wrap kiq ring ops with kiq spinlock
KIQ ring is being operated by kfd as well as amdgpu.
KFD is using kiq lock, we should the same from amdgpu side
as well.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index 1915b9b95106..892dc6b269fb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -462,20 +462,25 @@ int amdgpu_gfx_disable_kcq(struct amdgpu_device
*adev)
{
struct amdgpu_kiq *kiq = >gfx.kiq;
struct amdgpu_ring *kiq_ring = >ring;
- int i;
+ int i, r;
if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
return -EINVAL;
+ spin_lock(>gfx.kiq.ring_lock);
if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
- adev->gfx.num_compute_rings))
+ adev->gfx.num_compute_rings)) {
+ spin_unlock(>gfx.kiq.ring_lock);
return -ENOMEM;
+ }
for (i = 0; i < adev->gfx.num_compute_rings; i++)
kiq->pmf->kiq_unmap_queues(kiq_ring, >gfx.compute_ring[i],
RESET_QUEUES, 0, 0);
+ r = amdgpu_ring_test_helper(kiq_ring);
+ spin_unlock(>gfx.kiq.ring_lock);
- return amdgpu_ring_test_helper(kiq_ring);
+ return r;
}
int amdgpu_queue_mask_bit_to_set_resource_bit(struct amdgpu_device *adev,
@@ -518,12 +523,13 @@ int amdgpu_gfx_enable_kcq(struct amdgpu_device
*adev)
DRM_INFO("kiq ring mec %d pipe %d q %d\n", kiq_ring->me,
kiq_ring->pipe,
kiq_ring->queue);
-
+ spin_lock(>gfx.kiq.ring_lock);
r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
adev->gfx.num_compute_rings +
kiq->pmf->set_resources_size);
if (r) {
DRM_ERROR("Failed to lock KIQ (%d).\n", r);
+ spin_unlock(>gfx.kiq.ring_lock);
return r;
}
@@ -532,6 +538,7 @@ int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev)
kiq->pmf->kiq_map_queues(kiq_ring, >gfx.compute_ring[i]);
r = amdgpu_ring_test_helper(kiq_ring);
+ spin_unlock(>gfx.kiq.ring_lock);
if (r)
DRM_ERROR("KCQ enable failed\n");
--
2.30.1
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Re: [PATCH 1/1] drm/amdgpu: wrap kiq ring ops with kiq spinlock
[AMD Official Use Only - Internal Distribution Only]
Hi Das,
It seems more reasonable to put spin lock in ring structure, so that KIQ ring
can be treated like other normal ring.
and do we have other paths to call kiq ring except for kernel initialization?
it seems the kfd and kgd will use kiq in one thread..
thanks.
Best Regards,
Kevin
From: amd-gfx on behalf of Nirmoy Das
Sent: Saturday, March 13, 2021 1:08 AM
To: Koenig, Christian
Cc: Das, Nirmoy ; amd-gfx@lists.freedesktop.org
Subject: [PATCH 1/1] drm/amdgpu: wrap kiq ring ops with kiq spinlock
KIQ ring is being operated by kfd as well as amdgpu.
KFD is using kiq lock, we should the same from amdgpu side
as well.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index 1915b9b95106..892dc6b269fb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -462,20 +462,25 @@ int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev)
{
struct amdgpu_kiq *kiq = >gfx.kiq;
struct amdgpu_ring *kiq_ring = >ring;
- int i;
+ int i, r;
if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
return -EINVAL;
+ spin_lock(>gfx.kiq.ring_lock);
if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
- adev->gfx.num_compute_rings))
+ adev->gfx.num_compute_rings)) {
+ spin_unlock(>gfx.kiq.ring_lock);
return -ENOMEM;
+ }
for (i = 0; i < adev->gfx.num_compute_rings; i++)
kiq->pmf->kiq_unmap_queues(kiq_ring,
>gfx.compute_ring[i],
RESET_QUEUES, 0, 0);
+ r = amdgpu_ring_test_helper(kiq_ring);
+ spin_unlock(>gfx.kiq.ring_lock);
- return amdgpu_ring_test_helper(kiq_ring);
+ return r;
}
int amdgpu_queue_mask_bit_to_set_resource_bit(struct amdgpu_device *adev,
@@ -518,12 +523,13 @@ int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev)
DRM_INFO("kiq ring mec %d pipe %d q %d\n", kiq_ring->me,
kiq_ring->pipe,
kiq_ring->queue);
-
+ spin_lock(>gfx.kiq.ring_lock);
r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
adev->gfx.num_compute_rings +
kiq->pmf->set_resources_size);
if (r) {
DRM_ERROR("Failed to lock KIQ (%d).\n", r);
+ spin_unlock(>gfx.kiq.ring_lock);
return r;
}
@@ -532,6 +538,7 @@ int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev)
kiq->pmf->kiq_map_queues(kiq_ring, >gfx.compute_ring[i]);
r = amdgpu_ring_test_helper(kiq_ring);
+ spin_unlock(>gfx.kiq.ring_lock);
if (r)
DRM_ERROR("KCQ enable failed\n");
--
2.30.1
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Re: [PATCH 2/2] drm/amdkfd: Fix resource cursor initialization
Am 13.03.21 um 03:43 schrieb Felix Kuehling:
Make sure the cur->size doesn't exceed cur->remaining. Otherwise the
first call to amdgpu_res_next will trigger the BUG_ON in that function.
Mhm the BUG_ON is correct since the function complains that we want to
move the cursor forward by more than originally expected.
The problem is rather that somebody is using cur->size which is the size
of the current segment as parameter for amdgpu_res_next().
Do you have a backtrace of this?
Thanks,
Christian.
Fixes: 3af0a018a728 ("drm/amdgpu: new resource cursor")
CC: Christian König
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h
index 1335e098510f..b49a61d07d60 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h
@@ -68,7 +68,7 @@ static inline void amdgpu_res_first(struct ttm_resource *res,
start -= node++->size << PAGE_SHIFT;
cur->start = (node->start << PAGE_SHIFT) + start;
- cur->size = (node->size << PAGE_SHIFT) - start;
+ cur->size = min((node->size << PAGE_SHIFT) - start, size);
cur->remaining = size;
cur->node = node;
}
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Re: [PATCH 1/2] drm/amdkfd: Fix recursive lock warnings
Am 13.03.21 um 03:43 schrieb Felix Kuehling:
memalloc_nofs_save/restore are no longer sufficient to prevent recursive
lock warnings when holding locks that can be taken in MMU notifiers. Use
memalloc_noreclaim_save/restore instead.
Fixes: f920e413ff9c ("mm: track mmu notifiers in fs_reclaim_acquire/release")
Signed-off-by: Felix Kuehling
Reviewed-by: Christian König for this one.
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 318eeea577b5..bc3951b71079 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -93,13 +93,13 @@ struct amdgpu_prt_cb {
static inline void amdgpu_vm_eviction_lock(struct amdgpu_vm *vm)
{
mutex_lock(>eviction_lock);
- vm->saved_flags = memalloc_nofs_save();
+ vm->saved_flags = memalloc_noreclaim_save();
}
static inline int amdgpu_vm_eviction_trylock(struct amdgpu_vm *vm)
{
if (mutex_trylock(>eviction_lock)) {
- vm->saved_flags = memalloc_nofs_save();
+ vm->saved_flags = memalloc_noreclaim_save();
return 1;
}
return 0;
@@ -107,7 +107,7 @@ static inline int amdgpu_vm_eviction_trylock(struct
amdgpu_vm *vm)
static inline void amdgpu_vm_eviction_unlock(struct amdgpu_vm *vm)
{
- memalloc_nofs_restore(vm->saved_flags);
+ memalloc_noreclaim_restore(vm->saved_flags);
mutex_unlock(>eviction_lock);
}
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Re: [PATCH 1/1] drm/amdgpu: wrap kiq ring ops with kiq spinlock
Am 12.03.21 um 18:08 schrieb Nirmoy Das:
KIQ ring is being operated by kfd as well as amdgpu.
KFD is using kiq lock, we should the same from amdgpu side
as well.
Signed-off-by: Nirmoy Das
Acked-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index 1915b9b95106..892dc6b269fb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -462,20 +462,25 @@ int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev)
{
struct amdgpu_kiq *kiq = >gfx.kiq;
struct amdgpu_ring *kiq_ring = >ring;
- int i;
+ int i, r;
if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
return -EINVAL;
+ spin_lock(>gfx.kiq.ring_lock);
if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
- adev->gfx.num_compute_rings))
+ adev->gfx.num_compute_rings)) {
+ spin_unlock(>gfx.kiq.ring_lock);
return -ENOMEM;
+ }
for (i = 0; i < adev->gfx.num_compute_rings; i++)
kiq->pmf->kiq_unmap_queues(kiq_ring, >gfx.compute_ring[i],
RESET_QUEUES, 0, 0);
+ r = amdgpu_ring_test_helper(kiq_ring);
+ spin_unlock(>gfx.kiq.ring_lock);
- return amdgpu_ring_test_helper(kiq_ring);
+ return r;
}
int amdgpu_queue_mask_bit_to_set_resource_bit(struct amdgpu_device *adev,
@@ -518,12 +523,13 @@ int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev)
DRM_INFO("kiq ring mec %d pipe %d q %d\n", kiq_ring->me, kiq_ring->pipe,
kiq_ring->queue);
-
+ spin_lock(>gfx.kiq.ring_lock);
r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
adev->gfx.num_compute_rings +
kiq->pmf->set_resources_size);
if (r) {
DRM_ERROR("Failed to lock KIQ (%d).\n", r);
+ spin_unlock(>gfx.kiq.ring_lock);
return r;
}
@@ -532,6 +538,7 @@ int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev)
kiq->pmf->kiq_map_queues(kiq_ring, >gfx.compute_ring[i]);
r = amdgpu_ring_test_helper(kiq_ring);
+ spin_unlock(>gfx.kiq.ring_lock);
if (r)
DRM_ERROR("KCQ enable failed\n");
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RE: [PATCH v2] drm/amdgpu: Use dev_info if VFCT table not valid
[AMD Public Use]
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: Feifei Xu
Sent: Monday, March 15, 2021 17:11
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Lazar, Lijo
; Zhang, Hawking ; Xu, Feifei
Subject: [PATCH v2] drm/amdgpu: Use dev_info if VFCT table not valid
Some ASICs do not have GOP driver to copy vbios image into VFCT table. And it
will go to next check.
Signed-off-by: Feifei Xu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
index f454a6bd0ed6..a5e98d0142d7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
@@ -320,7 +320,7 @@ static bool amdgpu_atrm_get_bios(struct amdgpu_device *adev)
adev->bios = kmalloc(size, GFP_KERNEL);
if (!adev->bios) {
- DRM_ERROR("Unable to allocate bios\n");
+ dev_err(adev->dev, "Unable to allocate bios\n");
return false;
}
@@ -368,7 +368,7 @@ static bool amdgpu_acpi_vfct_bios(struct amdgpu_device
*adev)
return false;
tbl_size = hdr->length;
if (tbl_size < sizeof(UEFI_ACPI_VFCT)) {
- DRM_ERROR("ACPI VFCT table present but broken (too short
#1)\n");
+ dev_info(adev->dev, "ACPI VFCT table present but broken (too
short
+#1),skipping\n");
return false;
}
@@ -381,13 +381,13 @@ static bool amdgpu_acpi_vfct_bios(struct amdgpu_device
*adev)
offset += sizeof(VFCT_IMAGE_HEADER);
if (offset > tbl_size) {
- DRM_ERROR("ACPI VFCT image header truncated\n");
+ dev_info(adev->dev, "ACPI VFCT image header
truncated,skipping\n");
return false;
}
offset += vhdr->ImageLength;
if (offset > tbl_size) {
- DRM_ERROR("ACPI VFCT image truncated\n");
+ dev_info(adev->dev, "ACPI VFCT image
truncated,skipping\n");
return false;
}
@@ -410,7 +410,7 @@ static bool amdgpu_acpi_vfct_bios(struct amdgpu_device
*adev)
}
}
- DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n");
+ dev_info(adev->dev, "ACPI VFCT table present but broken (too short
+#2),skipping\n");
return false;
}
#else
@@ -457,7 +457,7 @@ bool amdgpu_get_bios(struct amdgpu_device *adev)
goto success;
}
- DRM_ERROR("Unable to locate a BIOS ROM\n");
+ dev_err(adev->dev, "Unable to locate a BIOS ROM\n");
return false;
success:
--
2.25.1
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[PATCH v2] drm/amdgpu: Use dev_info if VFCT table not valid
Some ASICs do not have GOP driver to copy vbios image into
VFCT table. And it will go to next check.
Signed-off-by: Feifei Xu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
index f454a6bd0ed6..a5e98d0142d7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
@@ -320,7 +320,7 @@ static bool amdgpu_atrm_get_bios(struct amdgpu_device *adev)
adev->bios = kmalloc(size, GFP_KERNEL);
if (!adev->bios) {
- DRM_ERROR("Unable to allocate bios\n");
+ dev_err(adev->dev, "Unable to allocate bios\n");
return false;
}
@@ -368,7 +368,7 @@ static bool amdgpu_acpi_vfct_bios(struct amdgpu_device
*adev)
return false;
tbl_size = hdr->length;
if (tbl_size < sizeof(UEFI_ACPI_VFCT)) {
- DRM_ERROR("ACPI VFCT table present but broken (too short
#1)\n");
+ dev_info(adev->dev, "ACPI VFCT table present but broken (too
short #1),skipping\n");
return false;
}
@@ -381,13 +381,13 @@ static bool amdgpu_acpi_vfct_bios(struct amdgpu_device
*adev)
offset += sizeof(VFCT_IMAGE_HEADER);
if (offset > tbl_size) {
- DRM_ERROR("ACPI VFCT image header truncated\n");
+ dev_info(adev->dev, "ACPI VFCT image header
truncated,skipping\n");
return false;
}
offset += vhdr->ImageLength;
if (offset > tbl_size) {
- DRM_ERROR("ACPI VFCT image truncated\n");
+ dev_info(adev->dev, "ACPI VFCT image
truncated,skipping\n");
return false;
}
@@ -410,7 +410,7 @@ static bool amdgpu_acpi_vfct_bios(struct amdgpu_device
*adev)
}
}
- DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n");
+ dev_info(adev->dev, "ACPI VFCT table present but broken (too short
#2),skipping\n");
return false;
}
#else
@@ -457,7 +457,7 @@ bool amdgpu_get_bios(struct amdgpu_device *adev)
goto success;
}
- DRM_ERROR("Unable to locate a BIOS ROM\n");
+ dev_err(adev->dev, "Unable to locate a BIOS ROM\n");
return false;
success:
--
2.25.1
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RE: [PATCH] drm/amdgpu: Use DRM_INFO if VFCT table not valid
OK. Will add in V2
Thanks,
Feifei
-Original Message-
From: Zhang, Hawking
Sent: Monday, March 15, 2021 3:28 PM
To: Xu, Feifei ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Lazar, Lijo
Subject: RE: [PATCH] drm/amdgpu: Use DRM_INFO if VFCT table not valid
[AMD Public Use]
Might be better switch to dev_err so in mGPU setup there is bdf along with the
warning/
Regards,
Hawking
-Original Message-
From: Xu, Feifei
Sent: Monday, March 15, 2021 15:11
To: Xu, Feifei ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Lazar, Lijo
; Zhang, Hawking
Subject: RE: [PATCH] drm/amdgpu: Use DRM_INFO if VFCT table not valid
[AMD Official Use Only - Internal Distribution Only]
Sorry, please ignore this one. I will draft a V2 to remove this one:
if (!adev->bios) {
-DRM_ERROR("Unable to allocate bios\n");
+DRM_INFO("Unable to allocate bios,skipping\n");
return false;
Thanks,
Feifei
-Original Message-
From: Feifei Xu
Sent: Monday, March 15, 2021 2:46 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Lazar, Lijo
; Zhang, Hawking ; Xu, Feifei
Subject: [PATCH] drm/amdgpu: Use DRM_INFO if VFCT table not valid
Some ASICs has no GOP driver to copy vbios image to VFCT table.
In this case, it will go to next check.
Signed-off-by: Feifei Xu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
index f454a6bd0ed6..dde27b26a735 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
@@ -320,7 +320,7 @@ static bool amdgpu_atrm_get_bios(struct amdgpu_device *adev)
adev->bios = kmalloc(size, GFP_KERNEL); if (!adev->bios) { -DRM_ERROR("Unable
to allocate bios\n");
+DRM_INFO("Unable to allocate bios,skipping\n");
return false;
}
@@ -368,7 +368,7 @@ static bool amdgpu_acpi_vfct_bios(struct amdgpu_device
*adev) return false; tbl_size = hdr->length; if (tbl_size <
sizeof(UEFI_ACPI_VFCT)) { -DRM_ERROR("ACPI VFCT table present but broken (too
short #1)\n");
+DRM_INFO("ACPI VFCT table present but broken (too short
+#1),skipping\n");
return false;
}
@@ -381,13 +381,13 @@ static bool amdgpu_acpi_vfct_bios(struct amdgpu_device
*adev)
offset += sizeof(VFCT_IMAGE_HEADER);
if (offset > tbl_size) {
-DRM_ERROR("ACPI VFCT image header truncated\n");
+DRM_INFO("ACPI VFCT image header truncated,skipping\n");
return false;
}
offset += vhdr->ImageLength;
if (offset > tbl_size) {
-DRM_ERROR("ACPI VFCT image truncated\n");
+DRM_INFO("ACPI VFCT image truncated,skipping\n");
return false;
}
@@ -410,7 +410,7 @@ static bool amdgpu_acpi_vfct_bios(struct amdgpu_device
*adev) } }
-DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n");
+DRM_INFO("ACPI VFCT table present but broken (too short
+#2),skipping\n");
return false;
}
#else
--
2.25.1
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Re: [PATCH] gpu: drm: amd: pm: Mundane typo fix in the file amdgpu_pm.c
On 3/14/21 6:57 PM, Bhaskar Chowdhury wrote: > > s/maxmum/maximum/ > > Signed-off-by: Bhaskar Chowdhury > --- > drivers/gpu/drm/amd/pm/amdgpu_pm.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c > b/drivers/gpu/drm/amd/pm/amdgpu_pm.c > index 7b6ef05a1d35..7af74d236600 100644 > --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c > +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c > @@ -3143,7 +3143,7 @@ static ssize_t amdgpu_hwmon_show_mclk_label(struct > device *dev, > * > * - fan1_min: an minimum value Unit: revolution/min (RPM) a minimum > * > - * - fan1_max: an maxmum value Unit: revolution/max (RPM) > + * - fan1_max: an maximum value Unit: revolution/max (RPM) a maximum > * > * - fan1_input: fan speed in RPM > * > -- and please follow the Subject: style: $ git log --online drivers/gpu/drm/amd/pm 48123d068fcb drm/amd/pm: correct the watermark settings for Polaris 50ceb1fe7acd drm/amd/pm: bug fix for pcie dpm 6efda1671312 drm/amd/pm: correct Arcturus mmTHM_BACO_CNTL register address 992ace410c32 drm/amdgpu/swsmu/vangogh: Only use RLCPowerNotify msg for disable e3746696e78f drm/amdgpu/pm: make unsupported power profile messages debug 7b3d19a76d68 drm/amd/pm/swsmu: Avoid using structure_size uninitialized in smu_cmn_init_soft_gpu_metrics d7ef887f2f8e drm/amd/pm: make the error log more clear for fine grain tuning function 6ef28889b413 drm/amd/pm: enable LCLK DS ae07970a0621 drm/amd/pm: add support for hwmon control of slow and fast PPT limit on vangogh 52d720b1a800 drm/amd/pm: modify the power limit level parameter from bool to enum type b36c1024dc32 drm/amd/pm: update the smu v11.5 smc header for vangogh de4b7cd8cb87 drm/amd/pm/swsmu: unify the init soft gpu metrics function 680602d6c2d6 drm/amd/pm: enable DCS 137aac26a2ed drm/amdgpu/smu12: fix power reporting on renoir 62826b86085d drm/amd/pm: enable ACDC feature c915ef890d5d drm/amdgpu: Prevent shift wrapping in amdgpu_read_mask() bb377febb10f drm/amd/pm: Disable GFXOFF when GFX DPM or PG disabled e487cb54db1b drm/amd/pm: remove some useless code for vangogh c9021a6e58c8 drm/amd/pm: fill in the data member of v2 gpu metrics table for vangogh 4954a76add70 drm/amdgpu/swsmu: use percent rather than rpm for manual fan control (v2) -- ~Randy ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: slow boot with 7fef431be9c9 ("mm/page_alloc: place pages to tail in __free_pages_core()")
Hi, On Sat, Mar 13, 2021 at 10:05:23AM +0100, David Hildenbrand wrote: > > Am 13.03.2021 um 05:04 schrieb Liang, Liang (Leo) : > > > > Hi David, > > > > Which benchmark tool you prefer? Memtest86+ or else? > > Hi Leo, > > I think you want something that runs under Linux natively. > > I‘m planning on coding up a kernel module to walk all 4MB pages in the > freelists and perform a stream benchmark individually. Then we might be > able to identify the problematic range - if there is a problematic range :) My wild guess would be that the pages that are now at the head of free lists have wrong caching enabled. Might be worth checking in your test module. > Guess I‘ll have it running by Monday and let you know. > > Cheers! -- Sincerely yours, Mike. ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH V2] drm: amd: pm: Mundane typo fixes in the file amdgpu_pm.c
On 3/14/21 8:21 PM, Bhaskar Chowdhury wrote: > > s/"an minimum"/"a minimum"/ > s/"an maxmum"/"a maximum"/ > > Signed-off-by: Bhaskar Chowdhury Acked-by: Randy Dunlap > --- > Changes from V1: > Randy's suggestion to adjust the subject line text > And missed out a spell too,which now included > > drivers/gpu/drm/amd/pm/amdgpu_pm.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c > b/drivers/gpu/drm/amd/pm/amdgpu_pm.c > index 5fa65f191a37..308249ae1a22 100644 > --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c > +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c > @@ -3315,9 +3315,9 @@ static ssize_t amdgpu_hwmon_show_mclk_label(struct > device *dev, > * > * - pwm1_max: pulse width modulation fan control maximum level (255) > * > - * - fan1_min: an minimum value Unit: revolution/min (RPM) > + * - fan1_min: a minimum value Unit: revolution/min (RPM) > * > - * - fan1_max: an maxmum value Unit: revolution/max (RPM) > + * - fan1_max: a maximum value Unit: revolution/max (RPM) > * > * - fan1_input: fan speed in RPM > * > -- -- ~Randy ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 1/1] amdgpu: use MMIO to init atombios if device is Thunderbolt / USB4 attached
When using some Thunderbolt hosts using BIOS-assisted PCI enumeration
with IO BAR assigned, we get an atombios timeout, such as:
[drm:atom_op_jump [amdgpu]] *ERROR* atombios stuck in loop for more than 20secs
aborting
[drm:amdgpu_atom_execute_table_locked [amdgpu]] *ERROR* atombios stuck
executing B456 (len 304, WS 4, PS 0) @ 0xB51B
[drm:amdgpu_atom_execute_table_locked [amdgpu]] *ERROR* atombios stuck
executing B104 (len 183, WS 0, PS 8) @ 0xB17E
amdgpu :08:00.0: amdgpu: gpu post error!
amdgpu :08:00.0: amdgpu: Fatal error during GPU init
amdgpu: probe of :08:00.0 failed with error -22
A workaround is to use MMIO to access ATOMBIOS when device is
Thunderbolt / USB4 attached.
---
drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
index 86add0f4e..5d16ec10d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
@@ -1999,11 +1999,15 @@ int amdgpu_atombios_init(struct amdgpu_device *adev)
atom_card_info->reg_read = cail_reg_read;
atom_card_info->reg_write = cail_reg_write;
/* needed for iio ops */
- if (adev->rio_mem) {
+ if (adev->rio_mem && !pci_is_thunderbolt_attached(adev->pdev)) {
atom_card_info->ioreg_read = cail_ioreg_read;
atom_card_info->ioreg_write = cail_ioreg_write;
} else {
- DRM_DEBUG("PCI I/O BAR is not found. Using MMIO to access ATOM
BIOS\n");
+ if (pci_is_thunderbolt_attached(adev->pdev))
+ DRM_DEBUG("Device is attached via Thunderbolt / USB4.
Using MMIO to access ATOM BIOS\n");
+ else
+ DRM_DEBUG("PCI I/O BAR is not found. Using MMIO to
access ATOM BIOS\n");
+
atom_card_info->ioreg_read = cail_reg_read;
atom_card_info->ioreg_write = cail_reg_write;
}
--
2.30.2
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[PATCH V2] drm: amd: pm: Mundane typo fixes in the file amdgpu_pm.c
s/"an minimum"/"a minimum"/ s/"an maxmum"/"a maximum"/ Signed-off-by: Bhaskar Chowdhury --- Changes from V1: Randy's suggestion to adjust the subject line text And missed out a spell too,which now included drivers/gpu/drm/amd/pm/amdgpu_pm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c index 5fa65f191a37..308249ae1a22 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c @@ -3315,9 +3315,9 @@ static ssize_t amdgpu_hwmon_show_mclk_label(struct device *dev, * * - pwm1_max: pulse width modulation fan control maximum level (255) * - * - fan1_min: an minimum value Unit: revolution/min (RPM) + * - fan1_min: a minimum value Unit: revolution/min (RPM) * - * - fan1_max: an maxmum value Unit: revolution/max (RPM) + * - fan1_max: a maximum value Unit: revolution/max (RPM) * * - fan1_input: fan speed in RPM * -- 2.30.2 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 0/1] Init atombios timeout when amdgpu is Thunderbolt / USB4 when IO BAR is assigned
Hi all, I am not certain why this happens, but when IO bar is assigned on Thunderbolt, the amdgpu init fails: [drm:atom_op_jump [amdgpu]] *ERROR* atombios stuck in loop for more than 20secs aborting [drm:amdgpu_atom_execute_table_locked [amdgpu]] *ERROR* atombios stuck executing B456 (len 304, WS 4, PS 0) @ 0xB51B [drm:amdgpu_atom_execute_table_locked [amdgpu]] *ERROR* atombios stuck executing B104 (len 183, WS 0, PS 8) @ 0xB17E amdgpu :08:00.0: amdgpu: gpu post error! amdgpu :08:00.0: amdgpu: Fatal error during GPU init amdgpu: probe of :08:00.0 failed with error -22 It seems to happen mostly when BIOS-assisted PCI enumeration is used (older Thunderbolt systems). I cannot rule it out with native enumeration, but generally native enumeration works, as the IO BAR is not assigned, due to limited IO resources. This patch is a simple fix against v5.12-rc2. I have experienced this issue for a long time, and have finally decided to do something about it. I do not see a downside to using MMIO, which is required to be assigned. Kind regards, Nicholas Johnson Nicholas Johnson (1): amdgpu: use MMIO to init atombios if device is Thunderbolt / USB4 attached drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) -- 2.30.2 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] powerpc: Fix missing declaration of [en/dis]able_kernel_vsx()
On Tue, 9 Mar 2021 08:39:39 + (UTC), Christophe Leroy wrote: > Add stub instances of enable_kernel_vsx() and disable_kernel_vsx() > when CONFIG_VSX is not set, to avoid following build failure. > > CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/calcs/dcn_calcs.o > In file included from > ./drivers/gpu/drm/amd/amdgpu/../display/dc/dm_services_types.h:29, > from > ./drivers/gpu/drm/amd/amdgpu/../display/dc/dm_services.h:37, > from > drivers/gpu/drm/amd/amdgpu/../display/dc/calcs/dcn_calcs.c:27: > drivers/gpu/drm/amd/amdgpu/../display/dc/calcs/dcn_calcs.c: In function > 'dcn_bw_apply_registry_override': > ./drivers/gpu/drm/amd/amdgpu/../display/dc/os_types.h:64:3: error: implicit > declaration of function 'enable_kernel_vsx'; did you mean 'enable_kernel_fp'? > [-Werror=implicit-function-declaration] >64 | enable_kernel_vsx(); \ > | ^ > drivers/gpu/drm/amd/amdgpu/../display/dc/calcs/dcn_calcs.c:640:2: note: in > expansion of macro 'DC_FP_START' > 640 | DC_FP_START(); > | ^~~ > ./drivers/gpu/drm/amd/amdgpu/../display/dc/os_types.h:75:3: error: implicit > declaration of function 'disable_kernel_vsx'; did you mean > 'disable_kernel_fp'? [-Werror=implicit-function-declaration] >75 | disable_kernel_vsx(); \ > | ^~ > drivers/gpu/drm/amd/amdgpu/../display/dc/calcs/dcn_calcs.c:676:2: note: in > expansion of macro 'DC_FP_END' > 676 | DC_FP_END(); > | ^ > cc1: some warnings being treated as errors > make[5]: *** [drivers/gpu/drm/amd/amdgpu/../display/dc/calcs/dcn_calcs.o] > Error 1 Applied to powerpc/fixes. [1/1] powerpc: Fix missing declaration of [en/dis]able_kernel_vsx() https://git.kernel.org/powerpc/c/bd73758803c2eedc037c2268b65a19542a832594 cheers ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] gpu: drm: amd: pm: Mundane typo fix in the file amdgpu_pm.c
s/maxmum/maximum/ Signed-off-by: Bhaskar Chowdhury --- drivers/gpu/drm/amd/pm/amdgpu_pm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c index 7b6ef05a1d35..7af74d236600 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c @@ -3143,7 +3143,7 @@ static ssize_t amdgpu_hwmon_show_mclk_label(struct device *dev, * * - fan1_min: an minimum value Unit: revolution/min (RPM) * - * - fan1_max: an maxmum value Unit: revolution/max (RPM) + * - fan1_max: an maximum value Unit: revolution/max (RPM) * * - fan1_input: fan speed in RPM * -- 2.30.2 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH] drm/amdgpu: Use DRM_INFO if VFCT table not valid
[AMD Public Use]
Might be better switch to dev_err so in mGPU setup there is bdf along with the
warning/
Regards,
Hawking
-Original Message-
From: Xu, Feifei
Sent: Monday, March 15, 2021 15:11
To: Xu, Feifei ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Lazar, Lijo
; Zhang, Hawking
Subject: RE: [PATCH] drm/amdgpu: Use DRM_INFO if VFCT table not valid
[AMD Official Use Only - Internal Distribution Only]
Sorry, please ignore this one. I will draft a V2 to remove this one:
if (!adev->bios) {
-DRM_ERROR("Unable to allocate bios\n");
+DRM_INFO("Unable to allocate bios,skipping\n");
return false;
Thanks,
Feifei
-Original Message-
From: Feifei Xu
Sent: Monday, March 15, 2021 2:46 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Lazar, Lijo
; Zhang, Hawking ; Xu, Feifei
Subject: [PATCH] drm/amdgpu: Use DRM_INFO if VFCT table not valid
Some ASICs has no GOP driver to copy vbios image to VFCT table.
In this case, it will go to next check.
Signed-off-by: Feifei Xu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
index f454a6bd0ed6..dde27b26a735 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
@@ -320,7 +320,7 @@ static bool amdgpu_atrm_get_bios(struct amdgpu_device *adev)
adev->bios = kmalloc(size, GFP_KERNEL); if (!adev->bios) { -DRM_ERROR("Unable
to allocate bios\n");
+DRM_INFO("Unable to allocate bios,skipping\n");
return false;
}
@@ -368,7 +368,7 @@ static bool amdgpu_acpi_vfct_bios(struct amdgpu_device
*adev) return false; tbl_size = hdr->length; if (tbl_size <
sizeof(UEFI_ACPI_VFCT)) { -DRM_ERROR("ACPI VFCT table present but broken (too
short #1)\n");
+DRM_INFO("ACPI VFCT table present but broken (too short
+#1),skipping\n");
return false;
}
@@ -381,13 +381,13 @@ static bool amdgpu_acpi_vfct_bios(struct amdgpu_device
*adev)
offset += sizeof(VFCT_IMAGE_HEADER);
if (offset > tbl_size) {
-DRM_ERROR("ACPI VFCT image header truncated\n");
+DRM_INFO("ACPI VFCT image header truncated,skipping\n");
return false;
}
offset += vhdr->ImageLength;
if (offset > tbl_size) {
-DRM_ERROR("ACPI VFCT image truncated\n");
+DRM_INFO("ACPI VFCT image truncated,skipping\n");
return false;
}
@@ -410,7 +410,7 @@ static bool amdgpu_acpi_vfct_bios(struct amdgpu_device
*adev) } }
-DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n");
+DRM_INFO("ACPI VFCT table present but broken (too short
+#2),skipping\n");
return false;
}
#else
--
2.25.1
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RE: [PATCH] drm/amdgpu: Use DRM_INFO if VFCT table not valid
[AMD Official Use Only - Internal Distribution Only]
Sorry, please ignore this one. I will draft a V2 to remove this one:
if (!adev->bios) {
-DRM_ERROR("Unable to allocate bios\n");
+DRM_INFO("Unable to allocate bios,skipping\n");
return false;
Thanks,
Feifei
-Original Message-
From: Feifei Xu
Sent: Monday, March 15, 2021 2:46 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Lazar, Lijo
; Zhang, Hawking ; Xu, Feifei
Subject: [PATCH] drm/amdgpu: Use DRM_INFO if VFCT table not valid
Some ASICs has no GOP driver to copy vbios image to VFCT table.
In this case, it will go to next check.
Signed-off-by: Feifei Xu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
index f454a6bd0ed6..dde27b26a735 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
@@ -320,7 +320,7 @@ static bool amdgpu_atrm_get_bios(struct amdgpu_device *adev)
adev->bios = kmalloc(size, GFP_KERNEL);
if (!adev->bios) {
-DRM_ERROR("Unable to allocate bios\n");
+DRM_INFO("Unable to allocate bios,skipping\n");
return false;
}
@@ -368,7 +368,7 @@ static bool amdgpu_acpi_vfct_bios(struct amdgpu_device
*adev)
return false;
tbl_size = hdr->length;
if (tbl_size < sizeof(UEFI_ACPI_VFCT)) {
-DRM_ERROR("ACPI VFCT table present but broken (too short #1)\n");
+DRM_INFO("ACPI VFCT table present but broken (too short #1),skipping\n");
return false;
}
@@ -381,13 +381,13 @@ static bool amdgpu_acpi_vfct_bios(struct amdgpu_device
*adev)
offset += sizeof(VFCT_IMAGE_HEADER);
if (offset > tbl_size) {
-DRM_ERROR("ACPI VFCT image header truncated\n");
+DRM_INFO("ACPI VFCT image header truncated,skipping\n");
return false;
}
offset += vhdr->ImageLength;
if (offset > tbl_size) {
-DRM_ERROR("ACPI VFCT image truncated\n");
+DRM_INFO("ACPI VFCT image truncated,skipping\n");
return false;
}
@@ -410,7 +410,7 @@ static bool amdgpu_acpi_vfct_bios(struct amdgpu_device
*adev)
}
}
-DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n");
+DRM_INFO("ACPI VFCT table present but broken (too short #2),skipping\n");
return false;
}
#else
--
2.25.1
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[PATCH] drm/amdgpu: Use DRM_INFO if VFCT table not valid
Some ASICs has no GOP driver to copy vbios image to VFCT table.
In this case, it will go to next check.
Signed-off-by: Feifei Xu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
index f454a6bd0ed6..dde27b26a735 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
@@ -320,7 +320,7 @@ static bool amdgpu_atrm_get_bios(struct amdgpu_device *adev)
adev->bios = kmalloc(size, GFP_KERNEL);
if (!adev->bios) {
- DRM_ERROR("Unable to allocate bios\n");
+ DRM_INFO("Unable to allocate bios,skipping\n");
return false;
}
@@ -368,7 +368,7 @@ static bool amdgpu_acpi_vfct_bios(struct amdgpu_device
*adev)
return false;
tbl_size = hdr->length;
if (tbl_size < sizeof(UEFI_ACPI_VFCT)) {
- DRM_ERROR("ACPI VFCT table present but broken (too short
#1)\n");
+ DRM_INFO("ACPI VFCT table present but broken (too short
#1),skipping\n");
return false;
}
@@ -381,13 +381,13 @@ static bool amdgpu_acpi_vfct_bios(struct amdgpu_device
*adev)
offset += sizeof(VFCT_IMAGE_HEADER);
if (offset > tbl_size) {
- DRM_ERROR("ACPI VFCT image header truncated\n");
+ DRM_INFO("ACPI VFCT image header truncated,skipping\n");
return false;
}
offset += vhdr->ImageLength;
if (offset > tbl_size) {
- DRM_ERROR("ACPI VFCT image truncated\n");
+ DRM_INFO("ACPI VFCT image truncated,skipping\n");
return false;
}
@@ -410,7 +410,7 @@ static bool amdgpu_acpi_vfct_bios(struct amdgpu_device
*adev)
}
}
- DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n");
+ DRM_INFO("ACPI VFCT table present but broken (too short
#2),skipping\n");
return false;
}
#else
--
2.25.1
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