[PATCH 14/14] drm/amd/display: 3.2.128

[Solomon Chiu]

From: Aric Cyr 

This version brings along following fixes:

- Populate socclk entries for dcn2.1
- hide VGH asic specific structs
- Add kernel doc to crc_rd_wrk field
- revert max lb lines change
- Log DMCUB trace buffer events
- Fix debugfs link_settings entry
- revert max lb use by default for n10
- Deallocate IRQ handlers on amdgpu_dm_irq_fini
- Fixed Clock Recovery Sequence
- Fix UBSAN: shift-out-of-bounds warning
- [FW Promotion] Release 0.0.57
- Change input parameter for set_drr
- Use pwrseq instance to determine eDP instance

Signed-off-by: Aric Cyr 
Reviewed-by: Aric Cyr 
Acked-by: Solomon Chiu 
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index d163007e057c..55f3c76823d8 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -45,7 +45,7 @@
 /* forward declaration */
 struct aux_payload;
 
-#define DC_VER "3.2.127"
+#define DC_VER "3.2.128"
 
 #define MAX_SURFACES 3
 #define MAX_PLANES 6
-- 
2.29.0

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[PATCH 13/14] drm/amd/display: Use pwrseq instance to determine eDP instance

[Solomon Chiu]

From: Jake Wang 

[Why & How]
Link index doesn't always correspond to the appropriate eDP instance.
We can assume lower link index is a lower eDP instance and set panel
control instance accordingly.

Signed-off-by: Jake Wang 
Reviewed-by: Nicholas Kazlauskas 
Acked-by: Qingqing Zhuo 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 10e34e411e06..e1e8a8bdf476 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1383,6 +1383,8 @@ static bool dc_link_construct(struct dc_link *link,
struct dc_bios *bios = init_params->dc->ctx->dc_bios;
const struct dc_vbios_funcs *bp_funcs = bios->funcs;
struct bp_disp_connector_caps_info disp_connect_caps_info = { 0 };
+   struct dc_link *edp_links[MAX_NUM_EDP];
+   int edp_num;
 
DC_LOGGER_INIT(dc_ctx->logger);
 
@@ -1506,7 +1508,11 @@ static bool dc_link_construct(struct dc_link *link,
(link->link_id.id == CONNECTOR_ID_EDP ||
link->link_id.id == CONNECTOR_ID_LVDS)) {
panel_cntl_init_data.ctx = dc_ctx;
-   panel_cntl_init_data.inst = link->link_index;
+   get_edp_links(panel_cntl_init_data.ctx->dc, edp_links, 
_num);
+   if ((edp_num > 1) && (link->link_index > 
edp_links[0]->link_index))
+   panel_cntl_init_data.inst = 1;
+   else
+   panel_cntl_init_data.inst = 0;
link->panel_cntl =
link->dc->res_pool->funcs->panel_cntl_create(

_cntl_init_data);
-- 
2.29.0

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[PATCH 12/14] drm/amd/display: Change input parameter for set_drr

[Solomon Chiu]

From: Alvin Lee 

[Why]
Change set_drr to pass in the entire dc_crtc_timing_adjust
structure instead of passing in the parameters individually.
This is to more easily pass in required parameters in the
adjust structure when it gets updated.

Signed-off-by: Alvin Lee 
Reviewed-by: Jun Lei 
Acked-by: Solomon Chiu 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c  | 10 ++---
 .../display/dc/dce110/dce110_hw_sequencer.c   |  9 ++---
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 14 +++
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.h |  3 +-
 .../gpu/drm/amd/display/dc/inc/hw_sequencer.h |  3 +-
 .../amd/display/modules/freesync/freesync.c   | 37 +--
 .../amd/display/modules/inc/mod_freesync.h|  7 +++-
 7 files changed, 49 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 8e6c815b55d2..d55c1dd6464c 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -304,7 +304,10 @@ bool dc_stream_adjust_vmin_vmax(struct dc *dc,
int i = 0;
bool ret = false;
 
-   stream->adjust = *adjust;
+   stream->adjust.v_total_max = adjust->v_total_max;
+   stream->adjust.v_total_mid = adjust->v_total_mid;
+   stream->adjust.v_total_mid_frame_num = adjust->v_total_mid_frame_num;
+   stream->adjust.v_total_min = adjust->v_total_min;
 
for (i = 0; i < MAX_PIPES; i++) {
struct pipe_ctx *pipe = >current_state->res_ctx.pipe_ctx[i];
@@ -312,10 +315,7 @@ bool dc_stream_adjust_vmin_vmax(struct dc *dc,
if (pipe->stream == stream && pipe->stream_res.tg) {
dc->hwss.set_drr(,
1,
-   adjust->v_total_min,
-   adjust->v_total_max,
-   adjust->v_total_mid,
-   adjust->v_total_mid_frame_num);
+   *adjust);
 
ret = true;
}
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 804092f81f85..873c6f2d2cd9 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1846,8 +1846,7 @@ void dce110_set_safe_displaymarks(
  
**/
 
 static void set_drr(struct pipe_ctx **pipe_ctx,
-   int num_pipes, unsigned int vmin, unsigned int vmax,
-   unsigned int vmid, unsigned int vmid_frame_number)
+   int num_pipes, struct dc_crtc_timing_adjust adjust)
 {
int i = 0;
struct drr_params params = {0};
@@ -1856,8 +1855,8 @@ static void set_drr(struct pipe_ctx **pipe_ctx,
// Note DRR trigger events are generated regardless of whether num 
frames met.
unsigned int num_frames = 2;
 
-   params.vertical_total_max = vmax;
-   params.vertical_total_min = vmin;
+   params.vertical_total_max = adjust.v_total_max;
+   params.vertical_total_min = adjust.v_total_min;
 
/* TODO: If multiple pipes are to be supported, you need
 * some GSL stuff. Static screen triggers may be programmed differently
@@ -1867,7 +1866,7 @@ static void set_drr(struct pipe_ctx **pipe_ctx,
pipe_ctx[i]->stream_res.tg->funcs->set_drr(
pipe_ctx[i]->stream_res.tg, );
 
-   if (vmax != 0 && vmin != 0)
+   if (adjust.v_total_max != 0 && adjust.v_total_min != 0)

pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control(
pipe_ctx[i]->stream_res.tg,
event_triggers, num_frames);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 9eb33eae0e81..e0aa88a7766b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -3271,8 +3271,7 @@ void dcn10_optimize_bandwidth(
 }
 
 void dcn10_set_drr(struct pipe_ctx **pipe_ctx,
-   int num_pipes, unsigned int vmin, unsigned int vmax,
-   unsigned int vmid, unsigned int vmid_frame_number)
+   int num_pipes, struct dc_crtc_timing_adjust adjust)
 {
int i = 0;
struct drr_params params = {0};
@@ -3281,11 +3280,10 @@ void dcn10_set_drr(struct pipe_ctx **pipe_ctx,
// Note DRR trigger events are generated regardless of whether num 
frames met.
unsigned int num_frames = 2;
 
-   params.vertical_total_max = vmax;
-   params.vertical_total_min = vmin;
-   params.vertical_total_mid = vmid;
-   params.vertical_total_mid_frame_num = 

[PATCH 11/14] drm/amd/display: [FW Promotion] Release 0.0.57

[Solomon Chiu]

From: Anthony Koo 

Signed-off-by: Anthony Koo 
Reviewed-by: Anthony Koo 
Acked-by: Solomon Chiu 
---
 drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h 
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index f07b348f7c29..09c62485a1f1 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -47,10 +47,10 @@
 
 /* Firmware versioning. */
 #ifdef DMUB_EXPOSE_VERSION
-#define DMUB_FW_VERSION_GIT_HASH 0xc29b1734b
+#define DMUB_FW_VERSION_GIT_HASH 0x899019e5c
 #define DMUB_FW_VERSION_MAJOR 0
 #define DMUB_FW_VERSION_MINOR 0
-#define DMUB_FW_VERSION_REVISION 56
+#define DMUB_FW_VERSION_REVISION 57
 #define DMUB_FW_VERSION_TEST 0
 #define DMUB_FW_VERSION_VBIOS 0
 #define DMUB_FW_VERSION_HOTFIX 0
-- 
2.29.0

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[PATCH 10/14] drm/amd/display: Fix UBSAN: shift-out-of-bounds warning

[Solomon Chiu]

From: Anson Jacob 

[Why]
On NAVI14 CONFIG_UBSAN reported shift-out-of-bounds at
display_rq_dlg_calc_20v2.c:304:38

rq_param->misc.rq_c.blk256_height is 0 when chroma(*_c) is invalid.
dml_log2 returns -1023 for log2(0), although log2(0) is undefined.

Which ended up as:
rq_param->dlg.rq_c.swath_height = 1 << -1023

[How]
Fix applied on all dml versions.
1. Ensure dml_log2 is only called if the argument is greater than 0.
2. Subtract req128_l/req128_c from log2_swath_height_l/log2_swath_height_c
   only when it is greater than 0.

Signed-off-by: Anson Jacob 
Reviewed-by: Dmytro Laktyushkin 
Reviewed-by: Jun Lei 
Acked-by: Solomon Chiu 
---
 .../dc/dml/dcn20/display_rq_dlg_calc_20.c | 28 +++
 .../dc/dml/dcn20/display_rq_dlg_calc_20v2.c   | 28 +++
 .../dc/dml/dcn21/display_rq_dlg_calc_21.c | 28 +++
 .../dc/dml/dcn30/display_rq_dlg_calc_30.c | 28 +++
 .../display/dc/dml/dml1_display_rq_dlg_calc.c | 28 +++
 5 files changed, 115 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
index 72423dc425dc..799bae229e67 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
@@ -293,13 +293,31 @@ static void handle_det_buf_split(struct display_mode_lib 
*mode_lib,
if (surf_linear) {
log2_swath_height_l = 0;
log2_swath_height_c = 0;
-   } else if (!surf_vert) {
-   log2_swath_height_l = 
dml_log2(rq_param->misc.rq_l.blk256_height) - req128_l;
-   log2_swath_height_c = 
dml_log2(rq_param->misc.rq_c.blk256_height) - req128_c;
} else {
-   log2_swath_height_l = 
dml_log2(rq_param->misc.rq_l.blk256_width) - req128_l;
-   log2_swath_height_c = 
dml_log2(rq_param->misc.rq_c.blk256_width) - req128_c;
+   unsigned int swath_height_l;
+   unsigned int swath_height_c;
+
+   if (!surf_vert) {
+   swath_height_l = rq_param->misc.rq_l.blk256_height;
+   swath_height_c = rq_param->misc.rq_c.blk256_height;
+   } else {
+   swath_height_l = rq_param->misc.rq_l.blk256_width;
+   swath_height_c = rq_param->misc.rq_c.blk256_width;
+   }
+
+   if (swath_height_l > 0)
+   log2_swath_height_l = dml_log2(swath_height_l);
+
+   if (req128_l && log2_swath_height_l > 0)
+   log2_swath_height_l -= 1;
+
+   if (swath_height_c > 0)
+   log2_swath_height_c = dml_log2(swath_height_c);
+
+   if (req128_c && log2_swath_height_c > 0)
+   log2_swath_height_c -= 1;
}
+
rq_param->dlg.rq_l.swath_height = 1 << log2_swath_height_l;
rq_param->dlg.rq_c.swath_height = 1 << log2_swath_height_c;
 
diff --git 
a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
index 9c78446c3a9d..6a6d5970d1d5 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
@@ -293,13 +293,31 @@ static void handle_det_buf_split(struct display_mode_lib 
*mode_lib,
if (surf_linear) {
log2_swath_height_l = 0;
log2_swath_height_c = 0;
-   } else if (!surf_vert) {
-   log2_swath_height_l = 
dml_log2(rq_param->misc.rq_l.blk256_height) - req128_l;
-   log2_swath_height_c = 
dml_log2(rq_param->misc.rq_c.blk256_height) - req128_c;
} else {
-   log2_swath_height_l = 
dml_log2(rq_param->misc.rq_l.blk256_width) - req128_l;
-   log2_swath_height_c = 
dml_log2(rq_param->misc.rq_c.blk256_width) - req128_c;
+   unsigned int swath_height_l;
+   unsigned int swath_height_c;
+
+   if (!surf_vert) {
+   swath_height_l = rq_param->misc.rq_l.blk256_height;
+   swath_height_c = rq_param->misc.rq_c.blk256_height;
+   } else {
+   swath_height_l = rq_param->misc.rq_l.blk256_width;
+   swath_height_c = rq_param->misc.rq_c.blk256_width;
+   }
+
+   if (swath_height_l > 0)
+   log2_swath_height_l = dml_log2(swath_height_l);
+
+   if (req128_l && log2_swath_height_l > 0)
+   log2_swath_height_l -= 1;
+
+   if (swath_height_c > 0)
+   log2_swath_height_c = dml_log2(swath_height_c);
+
+   if (req128_c && log2_swath_height_c > 0)
+   log2_swath_height_c -= 1;
}
+

[PATCH 09/14] drm/amd/display: Fixed Clock Recovery Sequence

[Solomon Chiu]

From: David Galiffi 

[Why]
When performing clock recovery, if a pre-emphasis adjustment is
requested, but voltage swing remains constant, the the retry counter
will not be reset. This can lead to prematurely failing link training.

[How]
Reset the clock recovery retry counter if an adjustment is requested
for either voltage swing or pre-emphasis.

Signed-off-by: Calvin Hou 
Signed-off-by: David Galiffi 
Reviewed-by: Jun Lei 
Acked-by: Solomon Chiu 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 10 ++
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 47e6c33f73cb..484d96f78ade 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -1098,11 +1098,13 @@ static enum link_training_result 
perform_clock_recovery_sequence(
if (is_max_vs_reached(lt_settings))
break;
 
-   /* 7. same voltage*/
-   /* Note: VS same for all lanes,
-   * so comparing first lane is sufficient*/
-   if (lt_settings->lane_settings[0].VOLTAGE_SWING ==
+   /* 7. same lane settings*/
+   /* Note: settings are the same for all lanes,
+* so comparing first lane is sufficient*/
+   if ((lt_settings->lane_settings[0].VOLTAGE_SWING ==
req_settings.lane_settings[0].VOLTAGE_SWING)
+   && (lt_settings->lane_settings[0].PRE_EMPHASIS ==
+   req_settings.lane_settings[0].PRE_EMPHASIS))
retries_cr++;
else
retries_cr = 0;
-- 
2.29.0

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[PATCH 08/14] drm/amd/display: Deallocate IRQ handlers on amdgpu_dm_irq_fini

[Solomon Chiu]

From: Victor Lu 

[why]
The amdgpu_dm IRQ handlers are not freed during the IRQ teardown.

[how]
Add function to deallocate IRQ handlers on amdgpu_dm_irq_fini step.

Signed-off-by: Victor Lu 
Reviewed-by: Roman Li 
Acked-by: Solomon Chiu 
---
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c | 51 +++
 1 file changed, 51 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
index ffd18cd90947..da2703a04e23 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
@@ -184,6 +184,55 @@ static struct list_head *remove_irq_handler(struct 
amdgpu_device *adev,
return hnd_list;
 }
 
+/**
+ * unregister_all_irq_handlers() - Cleans up handlers from the DM IRQ table
+ * @adev: The base driver device containing the DM device
+ *
+ * Go through low and high context IRQ tables and deallocate handlers.
+ */
+static void unregister_all_irq_handlers(struct amdgpu_device *adev)
+{
+   struct list_head *hnd_list_low;
+   struct list_head *hnd_list_high;
+   struct list_head *entry, *tmp;
+   struct amdgpu_dm_irq_handler_data *handler;
+   unsigned long irq_table_flags;
+   int i;
+
+   DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
+
+   for (i = 0; i < DAL_IRQ_SOURCES_NUMBER; i++) {
+   hnd_list_low = >dm.irq_handler_list_low_tab[i];
+   hnd_list_high = >dm.irq_handler_list_high_tab[i];
+
+   list_for_each_safe(entry, tmp, hnd_list_low) {
+
+   handler = list_entry(entry, struct 
amdgpu_dm_irq_handler_data,
+list);
+
+   if (handler == NULL || handler->handler == NULL)
+   continue;
+
+   list_del(>list);
+   kfree(handler);
+   }
+
+   list_for_each_safe(entry, tmp, hnd_list_high) {
+
+   handler = list_entry(entry, struct 
amdgpu_dm_irq_handler_data,
+list);
+
+   if (handler == NULL || handler->handler == NULL)
+   continue;
+
+   list_del(>list);
+   kfree(handler);
+   }
+   }
+
+   DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
+}
+
 static bool
 validate_irq_registration_params(struct dc_interrupt_params *int_params,
 void (*ih)(void *))
@@ -414,6 +463,8 @@ void amdgpu_dm_irq_fini(struct amdgpu_device *adev)
}
}
}
+   /* Deallocate handlers from the table. */
+   unregister_all_irq_handlers(adev);
 }
 
 int amdgpu_dm_irq_suspend(struct amdgpu_device *adev)
-- 
2.29.0

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[PATCH 06/14] drm/amd/display: Fix debugfs link_settings entry

[Solomon Chiu]

From: Fangzhi Zuo 

1. Catch invalid link_rate and link_count settings
2. Call dc interface to overwrite preferred link settings, and wait
until next stream update to apply the new settings.

Signed-off-by: Fangzhi Zuo 
Reviewed-by: Nicholas Kazlauskas 
Acked-by: Solomon Chiu 
---
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 15 ---
 1 file changed, 8 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index 927de7678a4f..f6f10a8c3e43 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -149,7 +149,7 @@ static int parse_write_buffer_into_params(char *wr_buf, 
uint32_t wr_buf_size,
  *
  * --- to get dp configuration
  *
- * cat link_settings
+ * cat /sys/kernel/debug/dri/0/DP-x/link_settings
  *
  * It will list current, verified, reported, preferred dp configuration.
  * current -- for current video mode
@@ -162,7 +162,7 @@ static int parse_write_buffer_into_params(char *wr_buf, 
uint32_t wr_buf_size,
  * echo> link_settings
  *
  * for example, to force to  2 lane, 2.7GHz,
- * echo 4 0xa > link_settings
+ * echo 4 0xa > /sys/kernel/debug/dri/0/DP-x/link_settings
  *
  * spread_spectrum could not be changed dynamically.
  *
@@ -170,7 +170,7 @@ static int parse_write_buffer_into_params(char *wr_buf, 
uint32_t wr_buf_size,
  * done. please check link settings after force operation to see if HW get
  * programming.
  *
- * cat link_settings
+ * cat /sys/kernel/debug/dri/0/DP-x/link_settings
  *
  * check current and preferred settings.
  *
@@ -254,7 +254,7 @@ static ssize_t dp_link_settings_write(struct file *f, const 
char __user *buf,
int max_param_num = 2;
uint8_t param_nums = 0;
long param[2];
-   bool valid_input = false;
+   bool valid_input = true;
 
if (size == 0)
return -EINVAL;
@@ -281,9 +281,9 @@ static ssize_t dp_link_settings_write(struct file *f, const 
char __user *buf,
case LANE_COUNT_ONE:
case LANE_COUNT_TWO:
case LANE_COUNT_FOUR:
-   valid_input = true;
break;
default:
+   valid_input = false;
break;
}
 
@@ -293,9 +293,9 @@ static ssize_t dp_link_settings_write(struct file *f, const 
char __user *buf,
case LINK_RATE_RBR2:
case LINK_RATE_HIGH2:
case LINK_RATE_HIGH3:
-   valid_input = true;
break;
default:
+   valid_input = false;
break;
}
 
@@ -309,10 +309,11 @@ static ssize_t dp_link_settings_write(struct file *f, 
const char __user *buf,
 * spread spectrum will not be changed
 */
prefer_link_settings.link_spread = link->cur_link_settings.link_spread;
+   prefer_link_settings.use_link_rate_set = false;
prefer_link_settings.lane_count = param[0];
prefer_link_settings.link_rate = param[1];
 
-   dc_link_set_preferred_link_settings(dc, _link_settings, link);
+   dc_link_set_preferred_training_settings(dc, _link_settings, 
NULL, link, true);
 
kfree(wr_buf);
return size;
-- 
2.29.0

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[PATCH 07/14] drm/amd/display: revert max lb use by default for n10

[Solomon Chiu]

From: Dmytro Laktyushkin 

This is causing a pstate change underflow regression for
unknown reason

Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Eric Bernstein 
Acked-by: Solomon Chiu 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 2 --
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 --
 2 files changed, 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index 0b1000d782a8..f962b905e79e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -619,7 +619,6 @@ static const struct dc_debug_options debug_defaults_drv = {
.recovery_enabled = false, /*enable this by default after 
testing.*/
.max_downscale_src_width = 3840,
.underflow_assert_delay_us = 0x,
-   .use_max_lb = true
 };
 
 static const struct dc_debug_options debug_defaults_diags = {
@@ -631,7 +630,6 @@ static const struct dc_debug_options debug_defaults_diags = 
{
.disable_pplib_clock_request = true,
.disable_pplib_wm_range = true,
.underflow_assert_delay_us = 0x,
-   .use_max_lb = true
 };
 
 static void dcn10_dpp_destroy(struct dpp **dpp)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index b8acad7acd94..28a3b4185424 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -1075,7 +1075,6 @@ static const struct dc_debug_options debug_defaults_drv = 
{
.scl_reset_length10 = true,
.sanity_checks = false,
.underflow_assert_delay_us = 0x,
-   .use_max_lb = true
 };
 
 static const struct dc_debug_options debug_defaults_diags = {
@@ -1092,7 +1091,6 @@ static const struct dc_debug_options debug_defaults_diags 
= {
.scl_reset_length10 = true,
.underflow_assert_delay_us = 0x,
.enable_tri_buf = true,
-   .use_max_lb = true
 };
 
 void dcn20_dpp_destroy(struct dpp **dpp)
-- 
2.29.0

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[PATCH 04/14] drm/amd/display: revert max lb lines change

[Solomon Chiu]

From: Dmytro Laktyushkin 

Some hardware revisions do have a max number of lines limitation
not honouring which can cause pstate switch underflow.

Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Eric Bernstein 
Acked-by: Solomon Chiu 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c   | 2 +-
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c   | 4 ++--
 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c   | 2 +-
 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c   | 2 +-
 drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c | 2 +-
 drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c | 2 +-
 6 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index d079f4e491e5..0b1000d782a8 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -82,7 +82,7 @@ const struct _vcs_dpi_ip_params_st dcn1_0_ip = {
.meta_chunk_size_kbytes = 2,
.writeback_chunk_size_kbytes = 2,
.line_buffer_size_bits = 589824,
-   .max_line_buffer_lines = 32,
+   .max_line_buffer_lines = 12,
.IsLineBufferBppFixed = 0,
.LineBufferFixedBpp = -1,
.writeback_luma_buffer_size_kbytes = 12,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 2307b3517821..b8acad7acd94 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -112,7 +112,7 @@ struct _vcs_dpi_ip_params_st dcn2_0_ip = {
.is_line_buffer_bpp_fixed = 0,
.line_buffer_fixed_bpp = 0,
.dcc_supported = true,
-   .max_line_buffer_lines = 32,
+   .max_line_buffer_lines = 12,
.writeback_luma_buffer_size_kbytes = 12,
.writeback_chroma_buffer_size_kbytes = 8,
.writeback_chroma_line_buffer_width_pixels = 4,
@@ -180,7 +180,7 @@ static struct _vcs_dpi_ip_params_st dcn2_0_nv14_ip = {
.is_line_buffer_bpp_fixed = 0,
.line_buffer_fixed_bpp = 0,
.dcc_supported = true,
-   .max_line_buffer_lines = 32,
+   .max_line_buffer_lines = 12,
.writeback_luma_buffer_size_kbytes = 12,
.writeback_chroma_buffer_size_kbytes = 8,
.writeback_chroma_line_buffer_width_pixels = 4,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index 7123151ed60f..8e3f1d0b4cc3 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -114,7 +114,7 @@ struct _vcs_dpi_ip_params_st dcn2_1_ip = {
.is_line_buffer_bpp_fixed = 0,
.line_buffer_fixed_bpp = 0,
.dcc_supported = true,
-   .max_line_buffer_lines = 32,
+   .max_line_buffer_lines = 12,
.writeback_luma_buffer_size_kbytes = 12,
.writeback_chroma_buffer_size_kbytes = 8,
.writeback_chroma_line_buffer_width_pixels = 4,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
index 263c2986682d..4a5fa23d8e7b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
@@ -120,7 +120,7 @@ struct _vcs_dpi_ip_params_st dcn3_0_ip = {
.dcc_supported = true,
.writeback_interface_buffer_size_kbytes = 90,
.writeback_line_buffer_buffer_size = 0,
-   .max_line_buffer_lines = 32,
+   .max_line_buffer_lines = 12,
.writeback_luma_buffer_size_kbytes = 12,  // 
writeback_line_buffer_buffer_size = 656640
.writeback_chroma_buffer_size_kbytes = 8,
.writeback_chroma_line_buffer_width_pixels = 4,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
index 0fbdfff87835..10c1884e3d30 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
@@ -116,7 +116,7 @@ struct _vcs_dpi_ip_params_st dcn3_01_ip = {
.dcc_supported = true,
.writeback_interface_buffer_size_kbytes = 90,
.writeback_line_buffer_buffer_size = 656640,
-   .max_line_buffer_lines = 32,
+   .max_line_buffer_lines = 12,
.writeback_luma_buffer_size_kbytes = 12,  // 
writeback_line_buffer_buffer_size = 656640
.writeback_chroma_buffer_size_kbytes = 8,
.writeback_chroma_line_buffer_width_pixels = 4,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
index 0723e29fd42e..a928c1d9a557 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
@@ -101,7 +101,7 @@ struct _vcs_dpi_ip_params_st dcn3_02_ip = {
 

[PATCH 03/14] drm/amd/display: Add kernel doc to crc_rd_wrk field

[Solomon Chiu]

From: Wayne Lin 

[Why]
Receive warning message below:

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:380: warning: Function
parameter or member 'crc_rd_wrk' not described in 'amdgpu_display_manager'

[How]
Add documentation for crc_rd_wrk.

Reported-by: Stephen Rothwell 
Signed-off-by: Wayne Lin 
Reviewed-by: Rodrigo Siqueira 
Acked-by: Solomon Chiu 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index 2c9eed78f6df..f7f0680c1fa1 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -385,6 +385,11 @@ struct amdgpu_display_manager {
 #endif
 
 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
+   /**
+* @crc_rd_wrk
+*
+* Work to be executed in a separate thread to communicate with PSP.
+*/
struct crc_rd_work *crc_rd_wrk;
 #endif
 
-- 
2.29.0

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[PATCH 05/14] drm/amd/display: Log DMCUB trace buffer events

[Solomon Chiu]

From: "Leo (Hanghong) Ma" 

[Why]
We want to log DMCUB trace buffer events as Linux kernel traces.

[How]
Register an IRQ handler for DMCUB outbox0 interrupt in amdgpu_dm,
and log the messages in the DMCUB tracebuffer to a new DMCUB
TRACE_EVENT as soon as we receive the outbox0 IRQ from DMCUB FW.

Signed-off-by: Leo (Hanghong) Ma 
Reviewed-by: Harry Wentland 
Acked-by: Solomon Chiu 
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 48 +++
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h |  9 
 .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 12 -
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c | 20 
 .../amd/display/amdgpu_dm/amdgpu_dm_trace.h   | 21 
 .../display/dc/irq/dcn21/irq_service_dcn21.c  | 32 -
 .../display/dc/irq/dcn30/irq_service_dcn30.c  | 32 -
 7 files changed, 170 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 8b464debc1ef..36100eeefb3b 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -908,6 +908,32 @@ static int dm_dmub_hw_init(struct amdgpu_device *adev)
return 0;
 }
 
+#define DMUB_TRACE_MAX_READ 64
+static void dm_dmub_trace_high_irq(void *interrupt_params)
+{
+   struct common_irq_params *irq_params = interrupt_params;
+   struct amdgpu_device *adev = irq_params->adev;
+   struct amdgpu_display_manager *dm = >dm;
+   struct dmcub_trace_buf_entry entry = { 0 };
+   uint32_t count = 0;
+
+   do {
+   if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, )) {
+   trace_amdgpu_dmub_trace_high_irq(entry.trace_code, 
entry.tick_count,
+   entry.param0, 
entry.param1);
+
+   DRM_DEBUG_DRIVER("trace_code:%u, tick_count:%u, 
param0:%u, param1:%u\n",
+entry.trace_code, entry.tick_count, 
entry.param0, entry.param1);
+   } else
+   break;
+
+   count++;
+
+   } while (count <= DMUB_TRACE_MAX_READ);
+
+   ASSERT(count <= DMUB_TRACE_MAX_READ);
+}
+
 #if defined(CONFIG_DRM_AMD_DC_DCN)
 static void mmhub_read_system_context(struct amdgpu_device *adev, struct 
dc_phy_addr_space_config *pa_config)
 {
@@ -3078,6 +3104,28 @@ static int dcn10_register_irq_handlers(struct 
amdgpu_device *adev)
 
}
 
+   if (dc->ctx->dmub_srv) {
+   i = DCN_1_0__SRCID__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INT;
+   r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, 
>dmub_trace_irq);
+
+   if (r) {
+   DRM_ERROR("Failed to add dmub trace irq id!\n");
+   return r;
+   }
+
+   int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
+   int_params.irq_source =
+   dc_interrupt_to_irq_source(dc, i, 0);
+
+   c_irq_params = >dm.dmub_trace_params[0];
+
+   c_irq_params->adev = adev;
+   c_irq_params->irq_src = int_params.irq_source;
+
+   amdgpu_dm_irq_register_interrupt(adev, _params,
+   dm_dmub_trace_high_irq, c_irq_params);
+   }
+
/* HPD */
r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, 
DCN_1_0__SRCID__DC_HPD1_INT,
>hpd_irq);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index f7f0680c1fa1..9d12f304b2ee 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -339,6 +339,15 @@ struct amdgpu_display_manager {
struct common_irq_params
vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1];
 
+   /**
+* @dmub_trace_params:
+*
+* DMUB trace event IRQ parameters, passed to registered handlers when
+* triggered.
+*/
+   struct common_irq_params
+   dmub_trace_params[1];
+
spinlock_t irq_handler_list_table_lock;
 
struct backlight_device *backlight_dev;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index 09bdffb3a09e..103e29905b57 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -700,6 +700,14 @@ void dm_helpers_free_gpu_mem(
 
 bool dm_helpers_dmub_outbox0_interrupt_control(struct dc_context *ctx, bool 
enable)
 {
-   // TODO
-   return true;
+   enum dc_irq_source irq_source;
+   bool ret;
+
+   irq_source = DC_IRQ_SOURCE_DMCUB_OUTBOX0;
+
+   ret = dc_interrupt_set(ctx->dc, irq_source, enable);
+
+   DRM_DEBUG_DRIVER("Dmub trace irq %sabling: r=%d\n",
+enable ? "en" : "dis", 

[PATCH 02/14] drm/amd/display: hide VGH asic specific structs

[Solomon Chiu]

From: Dmytro Laktyushkin 

The pmfw structs are specific to the asic and should not be
present in base clk_mgr struct

Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Eric Yang 
Acked-by: Solomon Chiu 
---
 .../gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c  | 116 +-
 .../display/dc/clk_mgr/dcn301/vg_clk_mgr.c| 101 +++
 .../display/dc/clk_mgr/dcn301/vg_clk_mgr.h|  28 ++---
 .../drm/amd/display/dc/dcn21/dcn21_resource.c |   1 -
 .../gpu/drm/amd/display/dc/inc/hw/clk_mgr.h   |   9 --
 5 files changed, 147 insertions(+), 108 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
index f7c728d4f50a..203150dd37f6 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
@@ -125,87 +125,135 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context 
*ctx, struct pp_smu_funcs *p
 {
struct hw_asic_id asic_id = ctx->asic_id;
 
-   struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), 
GFP_KERNEL);
-
-   if (clk_mgr == NULL) {
-   BREAK_TO_DEBUGGER();
-   return NULL;
-   }
-
switch (asic_id.chip_family) {
 #if defined(CONFIG_DRM_AMD_DC_SI)
-   case FAMILY_SI:
+   case FAMILY_SI: {
+   struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), 
GFP_KERNEL);
+
+   if (clk_mgr == NULL) {
+   BREAK_TO_DEBUGGER();
+   return NULL;
+   }
dce60_clk_mgr_construct(ctx, clk_mgr);
-   break;
+   dce_clk_mgr_construct(ctx, clk_mgr);
+   }
 #endif
case FAMILY_CI:
-   case FAMILY_KV:
+   case FAMILY_KV: {
+   struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), 
GFP_KERNEL);
+
+   if (clk_mgr == NULL) {
+   BREAK_TO_DEBUGGER();
+   return NULL;
+   }
dce_clk_mgr_construct(ctx, clk_mgr);
-   break;
-   case FAMILY_CZ:
+   return _mgr->base;
+   }
+   case FAMILY_CZ: {
+   struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), 
GFP_KERNEL);
+
+   if (clk_mgr == NULL) {
+   BREAK_TO_DEBUGGER();
+   return NULL;
+   }
dce110_clk_mgr_construct(ctx, clk_mgr);
-   break;
-   case FAMILY_VI:
+   return _mgr->base;
+   }
+   case FAMILY_VI: {
+   struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), 
GFP_KERNEL);
+
+   if (clk_mgr == NULL) {
+   BREAK_TO_DEBUGGER();
+   return NULL;
+   }
if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) ||
ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) {
dce_clk_mgr_construct(ctx, clk_mgr);
-   break;
+   return _mgr->base;
}
if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) ||

ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) ||

ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) {
dce112_clk_mgr_construct(ctx, clk_mgr);
-   break;
+   return _mgr->base;
}
if (ASIC_REV_IS_VEGAM(asic_id.hw_internal_rev)) {
dce112_clk_mgr_construct(ctx, clk_mgr);
-   break;
+   return _mgr->base;
+   }
+   return _mgr->base;
+   }
+   case FAMILY_AI: {
+   struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), 
GFP_KERNEL);
+
+   if (clk_mgr == NULL) {
+   BREAK_TO_DEBUGGER();
+   return NULL;
}
-   break;
-   case FAMILY_AI:
if (ASICREV_IS_VEGA20_P(asic_id.hw_internal_rev))
dce121_clk_mgr_construct(ctx, clk_mgr);
else
dce120_clk_mgr_construct(ctx, clk_mgr);
-   break;
-
+   return _mgr->base;
+   }
 #if defined(CONFIG_DRM_AMD_DC_DCN)
-   case FAMILY_RV:
+   case FAMILY_RV: {
+   struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), 
GFP_KERNEL);
+
+   if (clk_mgr == NULL) {
+   BREAK_TO_DEBUGGER();
+   return NULL;
+   }
+
if (ASICREV_IS_RENOIR(asic_id.hw_internal_rev)) {
rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
-   break;
+   return _mgr->base;
}
 
if (ASICREV_IS_GREEN_SARDINE(asic_id.hw_internal_rev)) {
   

[PATCH 01/14] drm/amd/display: Populate socclk entries for dcn2.1

[Solomon Chiu]

From: Roman Li 

[Why]
Dcn2.1 socclk entries in bandwidth params are not initialized.
They are not used now, but will be needed for dml validation.

[How]
Populate socclk bw params from dpm clock table

Signed-off-by: Roman Li 
Reviewed-by: Dmytro Laktyushkin 
Acked-by: Solomon Chiu 
---
 .../drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c   | 13 +
 1 file changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
index 01b1853b7750..887a54246bde 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
@@ -797,7 +797,18 @@ static struct wm_table lpddr4_wm_table_rn = {
},
}
 };
+static unsigned int find_socclk_for_voltage(struct dpm_clocks *clock_table, 
unsigned int voltage)
+{
+   int i;
+
+   for (i = 0; i < PP_SMU_NUM_SOCCLK_DPM_LEVELS; i++) {
+   if (clock_table->SocClocks[i].Vol == voltage)
+   return clock_table->SocClocks[i].Freq;
+   }
 
+   ASSERT(0);
+   return 0;
+}
 static unsigned int find_dcfclk_for_voltage(struct dpm_clocks *clock_table, 
unsigned int voltage)
 {
int i;
@@ -841,6 +852,8 @@ static void rn_clk_mgr_helper_populate_bw_params(struct 
clk_bw_params *bw_params
bw_params->clk_table.entries[i].memclk_mhz = 
clock_table->MemClocks[j].Freq;
bw_params->clk_table.entries[i].voltage = 
clock_table->FClocks[j].Vol;
bw_params->clk_table.entries[i].dcfclk_mhz = 
find_dcfclk_for_voltage(clock_table, clock_table->FClocks[j].Vol);
+   bw_params->clk_table.entries[i].socclk_mhz = 
find_socclk_for_voltage(clock_table,
+   
bw_params->clk_table.entries[i].voltage);
}
 
bw_params->vram_type = bios_info->memory_type;
-- 
2.29.0

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[PATCH 00/14] DC Patches March 22, 2021

[Solomon Chiu]

This DC patchset brings improvements in multiple areas. In summary, we 
highlight:
 
* Populate socclk entries for dcn2.1
* hide VGH asic specific structs
* Add kernel doc to crc_rd_wrk field
* revert max lb lines change
* Log DMCUB trace buffer events
* Fix debugfs link_settings entry
* revert max lb use by default for n10
* Deallocate IRQ handlers on amdgpu_dm_irq_fini
* Fixed Clock Recovery Sequence
* Fix UBSAN: shift-out-of-bounds warning
* [FW Promotion] Release 0.0.57
* Change input parameter for set_drr
* Use pwrseq instance to determine eDP instance


Alvin Lee (1):
  drm/amd/display: Change input parameter for set_drr

Anson Jacob (1):
  drm/amd/display: Fix UBSAN: shift-out-of-bounds warning

Anthony Koo (1):
  drm/amd/display: [FW Promotion] Release 0.0.57

Aric Cyr (1):
  drm/amd/display: 3.2.128

David Galiffi (1):
  drm/amd/display: Fixed Clock Recovery Sequence

Dmytro Laktyushkin (3):
  drm/amd/display: hide VGH asic specific structs
  drm/amd/display: revert max lb lines change
  drm/amd/display: revert max lb use by default for n10

Fangzhi Zuo (1):
  drm/amd/display: Fix debugfs link_settings entry

Jake Wang (1):
  drm/amd/display: Use pwrseq instance to determine eDP instance

Leo (Hanghong) Ma (1):
  drm/amd/display: Log DMCUB trace buffer events

Roman Li (1):
  drm/amd/display: Populate socclk entries for dcn2.1

Victor Lu (1):
  drm/amd/display: Deallocate IRQ handlers on amdgpu_dm_irq_fini

Wayne Lin (1):
  drm/amd/display: Add kernel doc to crc_rd_wrk field

 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  48 
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h |  14 +++
 .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c |  15 +--
 .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c |  12 +-
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c |  71 +++
 .../amd/display/amdgpu_dm/amdgpu_dm_trace.h   |  21 
 .../gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c  | 116 +-
 .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c |  13 ++
 .../display/dc/clk_mgr/dcn301/vg_clk_mgr.c| 101 +++
 .../display/dc/clk_mgr/dcn301/vg_clk_mgr.h|  28 ++---
 drivers/gpu/drm/amd/display/dc/core/dc.c  |  10 +-
 drivers/gpu/drm/amd/display/dc/core/dc_link.c |   8 +-
 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  |  10 +-
 drivers/gpu/drm/amd/display/dc/dc.h   |   2 +-
 .../display/dc/dce110/dce110_hw_sequencer.c   |   9 +-
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c |  14 +--
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.h |   3 +-
 .../drm/amd/display/dc/dcn10/dcn10_resource.c |   4 +-
 .../drm/amd/display/dc/dcn20/dcn20_resource.c |   6 +-
 .../drm/amd/display/dc/dcn21/dcn21_resource.c |   3 +-
 .../drm/amd/display/dc/dcn30/dcn30_resource.c |   2 +-
 .../amd/display/dc/dcn301/dcn301_resource.c   |   2 +-
 .../amd/display/dc/dcn302/dcn302_resource.c   |   2 +-
 .../dc/dml/dcn20/display_rq_dlg_calc_20.c |  28 -
 .../dc/dml/dcn20/display_rq_dlg_calc_20v2.c   |  28 -
 .../dc/dml/dcn21/display_rq_dlg_calc_21.c |  28 -
 .../dc/dml/dcn30/display_rq_dlg_calc_30.c |  28 -
 .../display/dc/dml/dml1_display_rq_dlg_calc.c |  28 -
 .../gpu/drm/amd/display/dc/inc/hw/clk_mgr.h   |   9 --
 .../gpu/drm/amd/display/dc/inc/hw_sequencer.h |   3 +-
 .../display/dc/irq/dcn21/irq_service_dcn21.c  |  32 -
 .../display/dc/irq/dcn30/irq_service_dcn30.c  |  32 -
 .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h   |   4 +-
 .../amd/display/modules/freesync/freesync.c   |  37 --
 .../amd/display/modules/inc/mod_freesync.h|   7 +-
 35 files changed, 581 insertions(+), 197 deletions(-)

-- 
2.29.0

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Re: [PATCH 1/5] drm/fourcc: Add 16 bpc fixed point framebuffer formats.

[Ville Syrjälä]

On Fri, Mar 19, 2021 at 10:45:10PM +0100, Mario Kleiner wrote:
> On Fri, Mar 19, 2021 at 10:16 PM Ville Syrjälä
>  wrote:
> >
> > On Fri, Mar 19, 2021 at 10:03:13PM +0100, Mario Kleiner wrote:
> > > These are 16 bits per color channel unsigned normalized formats.
> > > They are supported by at least AMD display hw, and suitable for
> > > direct scanout of Vulkan swapchain images in the format
> > > VK_FORMAT_R16G16B16A16_UNORM.
> > >
> > > Signed-off-by: Mario Kleiner 
> > > ---
> > >  drivers/gpu/drm/drm_fourcc.c  | 4 
> > >  include/uapi/drm/drm_fourcc.h | 7 +++
> > >  2 files changed, 11 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
> > > index 03262472059c..ce13d2be5d7b 100644
> > > --- a/drivers/gpu/drm/drm_fourcc.c
> > > +++ b/drivers/gpu/drm/drm_fourcc.c
> > > @@ -203,6 +203,10 @@ const struct drm_format_info *__drm_format_info(u32 
> > > format)
> > >   { .format = DRM_FORMAT_ARGB16161616F,   .depth = 0,  
> > > .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = 
> > > true },
> > >   { .format = DRM_FORMAT_ABGR16161616F,   .depth = 0,  
> > > .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = 
> > > true },
> > >   { .format = DRM_FORMAT_AXBXGXRX106106106106, .depth = 0, 
> > > .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = 
> > > true },
> > > + { .format = DRM_FORMAT_XRGB16161616,.depth = 0,  
> > > .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1 },
> > > + { .format = DRM_FORMAT_XBGR16161616,.depth = 0,  
> > > .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1 },
> > > + { .format = DRM_FORMAT_ARGB16161616,.depth = 0,  
> > > .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = 
> > > true },
> > > + { .format = DRM_FORMAT_ABGR16161616,.depth = 0,  
> > > .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = 
> > > true },
> > >   { .format = DRM_FORMAT_RGB888_A8,   .depth = 32, 
> > > .num_planes = 2, .cpp = { 3, 1, 0 }, .hsub = 1, .vsub = 1, .has_alpha = 
> > > true },
> > >   { .format = DRM_FORMAT_BGR888_A8,   .depth = 32, 
> > > .num_planes = 2, .cpp = { 3, 1, 0 }, .hsub = 1, .vsub = 1, .has_alpha = 
> > > true },
> > >   { .format = DRM_FORMAT_XRGB_A8, .depth = 32, 
> > > .num_planes = 2, .cpp = { 4, 1, 0 }, .hsub = 1, .vsub = 1, .has_alpha = 
> > > true },
> > > diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> > > index f76de49c768f..f7156322aba5 100644
> > > --- a/include/uapi/drm/drm_fourcc.h
> > > +++ b/include/uapi/drm/drm_fourcc.h
> > > @@ -168,6 +168,13 @@ extern "C" {
> > >  #define DRM_FORMAT_RGBA1010102   fourcc_code('R', 'A', '3', '0') /* 
> > > [31:0] R:G:B:A 10:10:10:2 little endian */
> > >  #define DRM_FORMAT_BGRA1010102   fourcc_code('B', 'A', '3', '0') /* 
> > > [31:0] B:G:R:A 10:10:10:2 little endian */
> > >
> > > +/* 64 bpp RGB */
> > > +#define DRM_FORMAT_XRGB16161616  fourcc_code('X', 'R', '4', '8') /* 
> > > [63:0] x:R:G:B 16:16:16:16 little endian */
> > > +#define DRM_FORMAT_XBGR16161616  fourcc_code('X', 'B', '4', '8') /* 
> > > [63:0] x:B:G:R 16:16:16:16 little endian */
> > > +
> > > +#define DRM_FORMAT_ARGB16161616  fourcc_code('A', 'R', '4', '8') /* 
> > > [63:0] A:R:G:B 16:16:16:16 little endian */
> > > +#define DRM_FORMAT_ABGR16161616  fourcc_code('A', 'B', '4', '8') /* 
> > > [63:0] A:B:G:R 16:16:16:16 little endian */
> >
> > These look reasonable enough to me. IIRC we should be able to expose
> > them on some recent Intel hw as well.
> >
> > Reviewed-by: Ville Syrjälä 
> >
> 
> Thanks Ville!
> 
> Indeed i looked over the Intel PRM's, and while fp16 support seems to
> be rather recent (Gen8? Gen9? Gen10? Can't remember atm.), iirc, I
> found references to rgb16 fixed point back to gen5 / Ironlake.

fp16 has been around since forever (gen4+)
uint16 is much more recent, IIRC is something ~glk+

> That
> would be pretty cool! The precision limit for the encoders on Intel is
> also 12 bpc atm., right?

Yes.

-- 
Ville Syrjälä
Intel
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Re: [PATCH] drm/amd/display: Allow idle optimization based on vblank.

[R, Bindu]

[AMD Official Use Only - Internal Distribution Only]

The Update patch has been submitted.

​Regards,
Bindu

From: Michel Dänzer 
Sent: Friday, March 19, 2021 6:31 AM
To: R, Bindu ; Lakha, Bhawanpreet ; 
amd-gfx@lists.freedesktop.org 
Cc: Deucher, Alexander ; Zhou1, Tao 
; Feng, Kenneth 
Subject: Re: [PATCH] drm/amd/display: Allow idle optimization based on vblank.

On 2021-03-19 1:44 a.m., R, Bindu wrote:
>
> ​Hi All,
>Thanks for the inputs, have updated the patch to include these changes.

Updated where? I can't find an updated patch.


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Re: [PATCH 1/5] drm/fourcc: Add 16 bpc fixed point framebuffer formats.

[Mario Kleiner]

On Fri, Mar 19, 2021 at 10:16 PM Ville Syrjälä
 wrote:
>
> On Fri, Mar 19, 2021 at 10:03:13PM +0100, Mario Kleiner wrote:
> > These are 16 bits per color channel unsigned normalized formats.
> > They are supported by at least AMD display hw, and suitable for
> > direct scanout of Vulkan swapchain images in the format
> > VK_FORMAT_R16G16B16A16_UNORM.
> >
> > Signed-off-by: Mario Kleiner 
> > ---
> >  drivers/gpu/drm/drm_fourcc.c  | 4 
> >  include/uapi/drm/drm_fourcc.h | 7 +++
> >  2 files changed, 11 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
> > index 03262472059c..ce13d2be5d7b 100644
> > --- a/drivers/gpu/drm/drm_fourcc.c
> > +++ b/drivers/gpu/drm/drm_fourcc.c
> > @@ -203,6 +203,10 @@ const struct drm_format_info *__drm_format_info(u32 
> > format)
> >   { .format = DRM_FORMAT_ARGB16161616F,   .depth = 0,  
> > .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = 
> > true },
> >   { .format = DRM_FORMAT_ABGR16161616F,   .depth = 0,  
> > .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = 
> > true },
> >   { .format = DRM_FORMAT_AXBXGXRX106106106106, .depth = 0, 
> > .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = 
> > true },
> > + { .format = DRM_FORMAT_XRGB16161616,.depth = 0,  
> > .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1 },
> > + { .format = DRM_FORMAT_XBGR16161616,.depth = 0,  
> > .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1 },
> > + { .format = DRM_FORMAT_ARGB16161616,.depth = 0,  
> > .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = 
> > true },
> > + { .format = DRM_FORMAT_ABGR16161616,.depth = 0,  
> > .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = 
> > true },
> >   { .format = DRM_FORMAT_RGB888_A8,   .depth = 32, 
> > .num_planes = 2, .cpp = { 3, 1, 0 }, .hsub = 1, .vsub = 1, .has_alpha = 
> > true },
> >   { .format = DRM_FORMAT_BGR888_A8,   .depth = 32, 
> > .num_planes = 2, .cpp = { 3, 1, 0 }, .hsub = 1, .vsub = 1, .has_alpha = 
> > true },
> >   { .format = DRM_FORMAT_XRGB_A8, .depth = 32, 
> > .num_planes = 2, .cpp = { 4, 1, 0 }, .hsub = 1, .vsub = 1, .has_alpha = 
> > true },
> > diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> > index f76de49c768f..f7156322aba5 100644
> > --- a/include/uapi/drm/drm_fourcc.h
> > +++ b/include/uapi/drm/drm_fourcc.h
> > @@ -168,6 +168,13 @@ extern "C" {
> >  #define DRM_FORMAT_RGBA1010102   fourcc_code('R', 'A', '3', '0') /* 
> > [31:0] R:G:B:A 10:10:10:2 little endian */
> >  #define DRM_FORMAT_BGRA1010102   fourcc_code('B', 'A', '3', '0') /* 
> > [31:0] B:G:R:A 10:10:10:2 little endian */
> >
> > +/* 64 bpp RGB */
> > +#define DRM_FORMAT_XRGB16161616  fourcc_code('X', 'R', '4', '8') /* 
> > [63:0] x:R:G:B 16:16:16:16 little endian */
> > +#define DRM_FORMAT_XBGR16161616  fourcc_code('X', 'B', '4', '8') /* 
> > [63:0] x:B:G:R 16:16:16:16 little endian */
> > +
> > +#define DRM_FORMAT_ARGB16161616  fourcc_code('A', 'R', '4', '8') /* 
> > [63:0] A:R:G:B 16:16:16:16 little endian */
> > +#define DRM_FORMAT_ABGR16161616  fourcc_code('A', 'B', '4', '8') /* 
> > [63:0] A:B:G:R 16:16:16:16 little endian */
>
> These look reasonable enough to me. IIRC we should be able to expose
> them on some recent Intel hw as well.
>
> Reviewed-by: Ville Syrjälä 
>

Thanks Ville!

Indeed i looked over the Intel PRM's, and while fp16 support seems to
be rather recent (Gen8? Gen9? Gen10? Can't remember atm.), iirc, I
found references to rgb16 fixed point back to gen5 / Ironlake. That
would be pretty cool! The precision limit for the encoders on Intel is
also 12 bpc atm., right?

-mario

> --
> Ville Syrjälä
> Intel
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Re: [PATCH] drm/amd/display: Set AMDGPU_DM_DEFAULT_MIN_BACKLIGHT to 0

[Alex Deucher]

On Fri, Mar 19, 2021 at 5:31 PM Evan Benn  wrote:
>
> On Sat, 20 Mar 2021 at 02:10, Harry Wentland  wrote:
> > On 2021-03-19 10:22 a.m., Alex Deucher wrote:
> > > On Fri, Mar 19, 2021 at 3:23 AM Evan Benn  wrote:
> > >>
> > >> AMDGPU_DM_DEFAULT_MIN_BACKLIGHT was set to the value of 12
> > >> to ensure no display backlight will flicker at low user brightness
> > >> settings. However this value is quite bright, so for devices that do not
> > >> implement the ACPI ATIF
> > >> ATIF_FUNCTION_QUERY_BRIGHTNESS_TRANSFER_CHARACTERISTICS
> > >> functionality the user cannot set the brightness to a low level even if
> > >> the display would support such a low PWM.
> > >>
> > >> This ATIF feature is not implemented on for example AMD grunt 
> > >> chromebooks.
> > >>
> > >> Signed-off-by: Evan Benn 
> > >>
> > >> ---
> > >> I could not find a justification for the reason for the value. It has
> > >> caused some noticable regression for users: 
> > >> https://bugzilla.kernel.org/show_bug.cgi?id=203439>>>
> > >> Maybe this can be either user controlled or userspace configured, but
> > >> preventing users from turning their backlight dim seems wrong.
> > >
> > > My understanding is that some panels flicker if you set the min to a
> > > value too low.  This was a safe minimum if the platform didn't specify
> > > it's own safe minimum.  I think we'd just be trading one bug for
> > > another (flickering vs not dim enough).  Maybe a whitelist or
> > > blacklist would be a better solution?
> > >
> >
> > Yeah, this is a NACK from me as-is for the reasons Alex described.
>
> Thanks Harry + Alex,
>
> I agree this solution is not the best.
>
> >
> > I agree a whitelist approach might be best.
>
> Do you have any idea what an allowlist could be keyed on?
> Is the flickering you observed here a function of the panel or the gpu
> or some other component?
> Maybe we could move the minimum level into the logic for that hardware.
>

Maybe the panel string from the EDID?  Either that or something from
dmi data?  Harry would probably have a better idea.

Alex

> >
> > Is this fix perhaps for OLED panels? If so we could use a different
> > min-value for OLED panels that don't do PWM, but use 12 for everything else.
>
> All the chromebooks I have worked with LCD + LED backlight have been
> fine with a backlight set to 0.
> We do have OLED panels too, but I'm not aware of what they do.
>
> > Harry
> >
> > > Alex
> > >
> > >
> > >>
> > >> Also reviewed here: 
> > >> https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/2748377>>>
> > >>   drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
> > >>   1 file changed, 1 insertion(+), 1 deletion(-)
> > >>
> > >> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
> > >> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > >> index 573cf17262da..0129bd69b94e 100644
> > >> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > >> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > >> @@ -3151,7 +3151,7 @@ static int amdgpu_dm_mode_config_init(struct 
> > >> amdgpu_device *adev)
> > >>  return 0;
> > >>   }
> > >>
> > >> -#define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
> > >> +#define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 0
> > >>   #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
> > >>   #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50
> > >>
> > >> --
> > >> 2.31.0.291.g576ba9dcdaf-goog
> > >>
> > >> ___
> > >> dri-devel mailing list
> > >> dri-de...@lists.freedesktop.org
> > >> https://lists.freedesktop.org/mailman/listinfo/dri-devel>> 
> > >> ___
> > > dri-devel mailing list
> > > dri-de...@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/dri-devel>>
> >
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Re: [PATCH] drm/amd/display: Set AMDGPU_DM_DEFAULT_MIN_BACKLIGHT to 0

[Evan Benn]

On Sat, 20 Mar 2021 at 02:10, Harry Wentland  wrote:
> On 2021-03-19 10:22 a.m., Alex Deucher wrote:
> > On Fri, Mar 19, 2021 at 3:23 AM Evan Benn  wrote:
> >>
> >> AMDGPU_DM_DEFAULT_MIN_BACKLIGHT was set to the value of 12
> >> to ensure no display backlight will flicker at low user brightness
> >> settings. However this value is quite bright, so for devices that do not
> >> implement the ACPI ATIF
> >> ATIF_FUNCTION_QUERY_BRIGHTNESS_TRANSFER_CHARACTERISTICS
> >> functionality the user cannot set the brightness to a low level even if
> >> the display would support such a low PWM.
> >>
> >> This ATIF feature is not implemented on for example AMD grunt chromebooks.
> >>
> >> Signed-off-by: Evan Benn 
> >>
> >> ---
> >> I could not find a justification for the reason for the value. It has
> >> caused some noticable regression for users: 
> >> https://bugzilla.kernel.org/show_bug.cgi?id=203439>>>
> >> Maybe this can be either user controlled or userspace configured, but
> >> preventing users from turning their backlight dim seems wrong.
> >
> > My understanding is that some panels flicker if you set the min to a
> > value too low.  This was a safe minimum if the platform didn't specify
> > it's own safe minimum.  I think we'd just be trading one bug for
> > another (flickering vs not dim enough).  Maybe a whitelist or
> > blacklist would be a better solution?
> >
>
> Yeah, this is a NACK from me as-is for the reasons Alex described.

Thanks Harry + Alex,

I agree this solution is not the best.

>
> I agree a whitelist approach might be best.

Do you have any idea what an allowlist could be keyed on?
Is the flickering you observed here a function of the panel or the gpu
or some other component?
Maybe we could move the minimum level into the logic for that hardware.

>
> Is this fix perhaps for OLED panels? If so we could use a different
> min-value for OLED panels that don't do PWM, but use 12 for everything else.

All the chromebooks I have worked with LCD + LED backlight have been
fine with a backlight set to 0.
We do have OLED panels too, but I'm not aware of what they do.

> Harry
>
> > Alex
> >
> >
> >>
> >> Also reviewed here: 
> >> https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/2748377>>>
> >>   drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
> >>   1 file changed, 1 insertion(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
> >> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> >> index 573cf17262da..0129bd69b94e 100644
> >> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> >> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> >> @@ -3151,7 +3151,7 @@ static int amdgpu_dm_mode_config_init(struct 
> >> amdgpu_device *adev)
> >>  return 0;
> >>   }
> >>
> >> -#define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
> >> +#define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 0
> >>   #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
> >>   #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50
> >>
> >> --
> >> 2.31.0.291.g576ba9dcdaf-goog
> >>
> >> ___
> >> dri-devel mailing list
> >> dri-de...@lists.freedesktop.org
> >> https://lists.freedesktop.org/mailman/listinfo/dri-devel>> 
> >> ___
> > dri-devel mailing list
> > dri-de...@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/dri-devel>>
>
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Re: [PATCH 5/8] drm/amdgpu: use the new cursor in amdgpu_ttm_access_memory

[Felix Kuehling]

This is causing a deadlock in amdgpu_ttm_access_memory during the 
PtraceAccess test in kfdtest. Unfortunately it doesn't get flagged by 
LOCKDEP. See the kernel log snippet below. I don't have a good 
explanation what's going on other than maybe some data structure corruption.


With this patch reverted the PtraceAccess test still fails, but it 
doesn't hang any more. If I also revert "use new cursor in 
amdgpu_ttm_io_mem_pfn" (which is used via amdgpu_find_mm_node in 
amdgpu_ttm_access_memory), Ptrace access starts working correctly. That 
tells me that there is some fundamental bug in the resource cursor 
implementation that's breaking several users.


Regards,
  Felix


[  129.446085] watchdog: BUG: soft lockup - CPU#8 stuck for 22s! [kfdtest:3588]
[  129.455379] Modules linked in: ip6table_filter ip6_tables iptable_filter 
amdgpu x86_pkg_temp_thermal drm_ttm_helper ttm iommu_v2 gpu_sched ip_tables 
x_tables
[  129.455428] irq event stamp: 75294000
[  129.455432] hardirqs last  enabled at (75293999): [] 
_raw_spin_unlock_irqrestore+0x2d/0x40
[  129.455447] hardirqs last disabled at (75294000): [] 
sysvec_apic_timer_interrupt+0xa/0xa0
[  129.455457] softirqs last  enabled at (75184000): [] 
__do_softirq+0x306/0x429
[  129.455467] softirqs last disabled at (75183995): [] 
asm_call_irq_on_stack+0xf/0x20
[  129.455477] CPU: 8 PID: 3588 Comm: kfdtest Not tainted 5.11.0-kfd-fkuehlin 
#194
[  129.455485] Hardware name: ASUS All Series/X99-E WS/USB 3.1, BIOS 3201 
06/17/2016
[  129.455490] RIP: 0010:_raw_spin_lock_irqsave+0xb/0x50
[  129.455498] Code: d2 31 f6 e8 e7 e9 31 ff 48 89 df 58 5b e9 7d 32 32 ff 0f 1f 00 
66 2e 0f 1f 84 00 00 00 00 00 0f 1f 44 00 00 55 48 89 fd 53 9c <5b> fa f6 c7 02 
74 05 e8 59 06 3e ff 65 ff 05 92 73 24 56 48 8d 7d
[  129.455505] RSP: 0018:a3eb407f3c58 EFLAGS: 0246
[  129.455513] RAX: 96466e2010a0 RBX: 96466e20 RCX: 
[  129.455519] RDX: a3eb407f3e70 RSI: 0190 RDI: 96466e2010a0
[  129.455524] RBP: 96466e2010a0 R08:  R09: 0001
[  129.455528] R10: a3eb407f3c60 R11: 96466e2010b8 R12: 0190
[  129.455533] R13: 0190 R14: a3eb407f3e70 R15: 0190
[  129.455538] FS:  7f5aad0f0740() GS:96467fc0() 
knlGS:
[  129.455544] CS:  0010 DS:  ES:  CR0: 80050033
[  129.455549] CR2: 563ea76ad0f0 CR3: 0007c6e92005 CR4: 001706e0
[  129.44] Call Trace:
[  129.455563]  amdgpu_device_vram_access+0xc1/0x200 [amdgpu]
[  129.455820]  ? _raw_spin_unlock_irqrestore+0x2d/0x40
[  129.455834]  amdgpu_ttm_access_memory+0x29e/0x320 [amdgpu]
[  129.456063]  ttm_bo_vm_access+0x1c8/0x3a0 [ttm]
[  129.456089]  __access_remote_vm+0x289/0x390
[  129.456112]  ptrace_access_vm+0x98/0xc0
[  129.456127]  generic_ptrace_peekdata+0x31/0x80
[  129.456138]  ptrace_request+0x13b/0x5d0
[  129.456155]  arch_ptrace+0x24f/0x2f0
[  129.456165]  __x64_sys_ptrace+0xc9/0x140
[  129.456177]  do_syscall_64+0x2d/0x40
[  129.456185]  entry_SYSCALL_64_after_hwframe+0x44/0xa9
[  129.456194] RIP: 0033:0x7f5aab861a3f
[  129.456199] Code: 48 89 44 24 18 48 8d 44 24 30 c7 44 24 10 18 00 00 00 8b 70 08 
48 8b 50 10 48 89 44 24 20 4c 0f 43 50 18 b8 65 00 00 00 0f 05 <48> 3d 00 f0 ff 
ff 77 41 48 85 c0 78 06 41 83 f8 02 76 1e 48 8b 4c
[  129.456205] RSP: 002b:7ffd27b68750 EFLAGS: 0293 ORIG_RAX: 
0065
[  129.456214] RAX: ffda RBX: 0001 RCX: 7f5aab861a3f
[  129.456219] RDX: 7f5aab30 RSI: 0dfa RDI: 0002
[  129.456224] RBP: 7ffd27b68870 R08: 0001 R09: 
[  129.456228] R10: 7ffd27b68758 R11: 0293 R12: 563ea764e2aa
[  129.456233] R13:  R14: 0021 R15: 

On 2021-03-08 8:40 a.m., Christian König wrote:

Separate the drm_mm_node walking from the actual handling.

Signed-off-by: Christian König 
Acked-by: Oak Zeng 
Tested-by: Nirmoy Das 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 67 +++--
  1 file changed, 18 insertions(+), 49 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 517611b709fa..2cbe4ace591f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -178,26 +178,6 @@ static int amdgpu_verify_access(struct ttm_buffer_object 
*bo, struct file *filp)
  filp->private_data);
  }
  
-/**

- * amdgpu_find_mm_node - Helper function finds the drm_mm_node corresponding to
- * @offset. It also modifies the offset to be within the drm_mm_node returned
- *
- * @mem: The region where the bo resides.
- * @offset: The offset that drm_mm_node is used for finding.
- *
- */
-static struct drm_mm_node *amdgpu_find_mm_node(struct ttm_resource *mem,
-  uint64_t *offset)
-{
-   

[pull] amdgpu, amdkfd, radeon drm-next-5.13

[Alex Deucher]

Hi Dave, Daniel,

New stuff for 5.13.

The following changes since commit 6e80fb8ab04f6c4f377e2fd422bdd1855beb7371:

  drm/amdgpu: Set reference clock to 100Mhz on Renoir (v2) (2021-02-18 16:43:09 
-0500)

are available in the Git repository at:

  https://gitlab.freedesktop.org/agd5f/linux.git 
tags/amd-drm-next-5.13-2021-03-19

for you to fetch changes up to 50487c677b9362a7df761f225b15f95a2157783d:

  drm/amdkfd: Bump KFD API version (2021-03-19 16:38:42 -0400)


amd-drm-next-5.13-2021-03-19:

amdgpu:
- Debugfs cleanup
- Various cleanups and spelling fixes
- Flexible array cleanups
- Initial AMD Freesync HDMI
- Display fixes
- 10bpc dithering improvements
- Display ASSR support
- Clean up and unify powerplay and swsmu interfaces
- Vangogh fixes
- Add SMU gfx busy queues for RV/PCO
- PCIE DPM fixes
- S0ix fixes
- GPU metrics data fixes
- DCN secure display support
- Backlight type override
- Add initial support for Aldebaran
- RAS fixes
- Prime fixes for A+A systems
- Reset fixes
- Initial resource cursor support
- Drop legacy IO BAR requirements
- Various power fixes

amdkfd:
- MMU notifier fixes
- APU fixes

radeon:
- Debugfs cleanups
- Flexible array cleanups

UAPI:
- amdgpu: Add a new INFO ioctl interface to query video capabilities
  rather than hardcoding them in userspace.  This allows us to provide
  fine grained asic capabilities (e.g., if a particular part is
  bandwidth limited, we can limit the capabilities).  Proposed userspace:
  https://gitlab.freedesktop.org/leoliu/drm/-/commits/info_video_caps
  https://gitlab.freedesktop.org/leoliu/mesa/-/commits/info_video_caps
- amdkfd: bump the driver version.  There was a problem with reporting
  some RAS features on older versions of the driver. Proposed userspace:
  
https://github.com/RadeonOpenCompute/ROCT-Thunk-Interface/commit/7cdd63475c36bb9f49bb960f90f9a8cdb7e80a21


Alex Deucher (21):
  drm/amdgpu: add asic callback for querying video codec info (v3)
  drm/amdgpu: add video decode/encode cap tables and asic callbacks (v3)
  drm/amdgpu: add INFO ioctl support for querying video caps (v4)
  drm/amdgpu: bump driver version for new video codec INFO ioctl query
  drm/amdgpu/codec: drop the internal codec index
  drm/amdgpu/pm: make unsupported power profile messages debug
  drm/amdgpu/swsmu/vangogh: Only use RLCPowerNotify msg for disable
  drm/amdgpu: Only check for S0ix if AMD_PMC is configured
  drm/amdgpu: enable BACO runpm by default on sienna cichlid and navy 
flounder
  drm/amdgpu: enable TMZ by default on Raven asics
  drm/amdgpu/dc: fill in missing call to atom cmd table for pll adjust v2
  drm/amdgpu/display: simplify backlight setting
  drm/amdgpu/display: don't assert in set backlight function
  drm/amdgpu/display: handle aux backlight in backlight_get_brightness
  drm/amdgpu: add mmhub client ids for aldebaran
  drm/amdgpu: fix S0ix handling when the CONFIG_AMD_PMC=m
  drm/amdgpu/powerplay/smu10: add support for gpu busy query (v2)
  drm/amdgpu/smu8: return an error rather than 50% if busy query fails
  drm/amdgpu: drop legacy IO bar support
  drm/amdgpu: drop extraneous hw_status update
  drm/amdgpu/display: properly guard dc_dsc_stream_bandwidth_in_kbps

Alex Sierra (4):
  drm/amdgpu: UTLC1 RB SDMA timeout on Aldebaran
  drm/amdgpu: enable 48-bit IH timestamp counter
  drm/amdgpu: update mmhub client ids for Aldebaran
  drm/amdgpu: use pd addr based on gart level page table

Amber Lin (1):
  drm/amdgpu: Aldebaran doesn't use semaphore

Anson Jacob (5):
  Revert "drm/amd/display: reuse current context instead of recreating one"
  drm/amdkfd: Fix UBSAN shift-out-of-bounds warning
  Revert "drm/amd/display: remove duplicate include in amdgpu_dm.c"
  drm/amd/display: remove duplicate include in amdgpu_dm.c
  drm/amd/display: Fix UBSAN warning for not a valid value for type '_Bool'

Anthony Koo (5):
  drm/amd/display: [FW Promotion] Release 0.0.52
  drm/amd/display: [FW Promotion] Release 0.0.53
  drm/amd/display: [FW Promotion] Release 0.0.54
  drm/amd/display: [FW Promotion] Release 0.0.55
  drm/amd/display: [FW Promotion] Release 0.0.56

Anthony Wang (2):
  drm/amd/display: disable seamless boot for DP MST
  drm/amd/display: enable audio on DP seamless boot

Aric Cyr (10):
  drm/amd/display: 3.2.123
  drm/amd/display: Don't optimize bandwidth before disabling planes
  drm/amd/display: reduce scope for local var
  drm/amd/display: 3.2.124
  drm/amd/display: 3.2.125
  drm/amd/display: 3.2.126
  drm/amd/display: 3.2.126.1
  drm/amd/display: System black screen hangs on driver load
  drm/amd/display: DCHUB underflow counter increasing in some scenarios
  drm/amd/display: 3.2.127

Arnd Bergmann (1):
  drm/amd/display: 

Re: [PATCH 1/5] drm/fourcc: Add 16 bpc fixed point framebuffer formats.

[Ville Syrjälä]

On Fri, Mar 19, 2021 at 10:03:13PM +0100, Mario Kleiner wrote:
> These are 16 bits per color channel unsigned normalized formats.
> They are supported by at least AMD display hw, and suitable for
> direct scanout of Vulkan swapchain images in the format
> VK_FORMAT_R16G16B16A16_UNORM.
> 
> Signed-off-by: Mario Kleiner 
> ---
>  drivers/gpu/drm/drm_fourcc.c  | 4 
>  include/uapi/drm/drm_fourcc.h | 7 +++
>  2 files changed, 11 insertions(+)
> 
> diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
> index 03262472059c..ce13d2be5d7b 100644
> --- a/drivers/gpu/drm/drm_fourcc.c
> +++ b/drivers/gpu/drm/drm_fourcc.c
> @@ -203,6 +203,10 @@ const struct drm_format_info *__drm_format_info(u32 
> format)
>   { .format = DRM_FORMAT_ARGB16161616F,   .depth = 0,  
> .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true 
> },
>   { .format = DRM_FORMAT_ABGR16161616F,   .depth = 0,  
> .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true 
> },
>   { .format = DRM_FORMAT_AXBXGXRX106106106106, .depth = 0, 
> .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true 
> },
> + { .format = DRM_FORMAT_XRGB16161616,.depth = 0,  
> .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1 },
> + { .format = DRM_FORMAT_XBGR16161616,.depth = 0,  
> .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1 },
> + { .format = DRM_FORMAT_ARGB16161616,.depth = 0,  
> .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true 
> },
> + { .format = DRM_FORMAT_ABGR16161616,.depth = 0,  
> .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true 
> },
>   { .format = DRM_FORMAT_RGB888_A8,   .depth = 32, 
> .num_planes = 2, .cpp = { 3, 1, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true 
> },
>   { .format = DRM_FORMAT_BGR888_A8,   .depth = 32, 
> .num_planes = 2, .cpp = { 3, 1, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true 
> },
>   { .format = DRM_FORMAT_XRGB_A8, .depth = 32, 
> .num_planes = 2, .cpp = { 4, 1, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true 
> },
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index f76de49c768f..f7156322aba5 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -168,6 +168,13 @@ extern "C" {
>  #define DRM_FORMAT_RGBA1010102   fourcc_code('R', 'A', '3', '0') /* 
> [31:0] R:G:B:A 10:10:10:2 little endian */
>  #define DRM_FORMAT_BGRA1010102   fourcc_code('B', 'A', '3', '0') /* 
> [31:0] B:G:R:A 10:10:10:2 little endian */
>  
> +/* 64 bpp RGB */
> +#define DRM_FORMAT_XRGB16161616  fourcc_code('X', 'R', '4', '8') /* 
> [63:0] x:R:G:B 16:16:16:16 little endian */
> +#define DRM_FORMAT_XBGR16161616  fourcc_code('X', 'B', '4', '8') /* 
> [63:0] x:B:G:R 16:16:16:16 little endian */
> +
> +#define DRM_FORMAT_ARGB16161616  fourcc_code('A', 'R', '4', '8') /* 
> [63:0] A:R:G:B 16:16:16:16 little endian */
> +#define DRM_FORMAT_ABGR16161616  fourcc_code('A', 'B', '4', '8') /* 
> [63:0] A:B:G:R 16:16:16:16 little endian */

These look reasonable enough to me. IIRC we should be able to expose
them on some recent Intel hw as well.

Reviewed-by: Ville Syrjälä 

-- 
Ville Syrjälä
Intel
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[PATCH 5/5] drm/amd/display: Enable support for 16 bpc fixed-point framebuffers.

[Mario Kleiner]

This is intended to enable direct high-precision scanout and pageflip
of Vulkan swapchain images in format VK_FORMAT_R16G16B16A16_UNORM.

Expose DRM_FORMAT_XRGB16161616, DRM_FORMAT_ARGB16161616,
DRM_FORMAT_XBGR16161616 and DRM_FORMAT_ABGR16161616 as 16 bpc
unsigned normalized formats. These allow to take full advantage
of the maximum precision of the display hardware, ie. currently
up to 12 bpc.

Searching through old AMD M56, M76 and RV630 hw programming docs
suggests that these 16 bpc formats are supported by all DCE and
DCN display engines, so we can expose the formats unconditionally.

Successfully tested on AMD Polaris11 DCE-11.2 an RavenRidge DCN-1.0
with a HDR-10 monitor over 10 bpc DP output with spatial dithering
enabled by the driver. Picture looks good, and my photometer
measurement procedure confirms an effective 12 bpc color
reproduction.

Signed-off-by: Mario Kleiner 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 94cd5ddd67ef..1a6e90e20f10 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4563,6 +4563,14 @@ fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
case DRM_FORMAT_ABGR16161616F:
plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F;
break;
+   case DRM_FORMAT_XRGB16161616:
+   case DRM_FORMAT_ARGB16161616:
+   plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616;
+   break;
+   case DRM_FORMAT_XBGR16161616:
+   case DRM_FORMAT_ABGR16161616:
+   plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616;
+   break;
default:
DRM_ERROR(
"Unsupported screen format %s\n",
@@ -6541,6 +6549,10 @@ static const uint32_t rgb_formats[] = {
DRM_FORMAT_XBGR2101010,
DRM_FORMAT_ARGB2101010,
DRM_FORMAT_ABGR2101010,
+   DRM_FORMAT_XRGB16161616,
+   DRM_FORMAT_XBGR16161616,
+   DRM_FORMAT_ARGB16161616,
+   DRM_FORMAT_ABGR16161616,
DRM_FORMAT_XBGR,
DRM_FORMAT_ABGR,
DRM_FORMAT_RGB565,
-- 
2.25.1

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[PATCH 4/5] drm/amd/display: Make assert in DCE's program_bit_depth_reduction more lenient.

[Mario Kleiner]

This is needed to avoid warnings with linebuffer depth 36 bpp.
Testing on a Polaris11, DCE-11.2 on a 10 bit HDR-10 monitor
showed no obvious problems, and this 12 bpc limit is consistent
with what other function in the DCE bit depth reduction path use.

Signed-off-by: Mario Kleiner 
---
 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
index 92b53a30d954..d9fd4ec60588 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
@@ -794,7 +794,7 @@ static void program_bit_depth_reduction(
enum dcp_out_trunc_round_mode trunc_mode;
bool spatial_dither_enable;
 
-   ASSERT(depth < COLOR_DEPTH_121212); /* Invalid clamp bit depth */
+   ASSERT(depth <= COLOR_DEPTH_121212); /* Invalid clamp bit depth */
 
spatial_dither_enable = bit_depth_params->flags.SPATIAL_DITHER_ENABLED;
/* Default to 12 bit truncation without rounding */
@@ -854,7 +854,7 @@ static void dce60_program_bit_depth_reduction(
enum dcp_out_trunc_round_mode trunc_mode;
bool spatial_dither_enable;
 
-   ASSERT(depth < COLOR_DEPTH_121212); /* Invalid clamp bit depth */
+   ASSERT(depth <= COLOR_DEPTH_121212); /* Invalid clamp bit depth */
 
spatial_dither_enable = bit_depth_params->flags.SPATIAL_DITHER_ENABLED;
/* Default to 12 bit truncation without rounding */
-- 
2.25.1

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[PATCH 3/5] drm/amd/display: Increase linebuffer pixel depth to 36bpp.

[Mario Kleiner]

Testing with the photometer shows that at least Raven Ridge DCN-1.0
does not achieve more than 10 bpc effective output precision with a
16 bpc unorm surface of type SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616,
unless linebuffer depth is increased from LB_PIXEL_DEPTH_30BPP to
LB_PIXEL_DEPTH_36BPP. Otherwise precision gets truncated somewhere
to 10 bpc effective depth.

Strangely this increase was not needed on Polaris11 DCE-11.2 during
testing to get 12 bpc effective precision. It also is not needed for
fp16 framebuffers.

Tested on DCN-1.0 and DCE-11.2.

Signed-off-by: Mario Kleiner 
---
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c  | 7 +--
 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c | 6 --
 drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c | 3 ++-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c   | 3 ++-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 2 +-
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c   | 3 ++-
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 2 +-
 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c   | 3 ++-
 8 files changed, 19 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index f1aed40b3124..51e91b546d69 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -1167,9 +1167,12 @@ bool resource_build_scaling_params(struct pipe_ctx 
*pipe_ctx)
 
/**
 * Setting line buffer pixel depth to 24bpp yields banding
-* on certain displays, such as the Sharp 4k
+* on certain displays, such as the Sharp 4k. 36bpp is needed
+* to support SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 and
+* SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616 with actual > 10 bpc
+* precision on at least DCN display engines.
 */
-   pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
+   pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_36BPP;
pipe_ctx->plane_res.scl_data.lb_params.alpha_en = 
plane_state->per_pixel_alpha;
 
pipe_ctx->plane_res.scl_data.recout.x += timing->h_border_left;
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
index 151dc7bf6d23..92b53a30d954 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
@@ -1647,7 +1647,8 @@ void dce_transform_construct(
xfm_dce->lb_pixel_depth_supported =
LB_PIXEL_DEPTH_18BPP |
LB_PIXEL_DEPTH_24BPP |
-   LB_PIXEL_DEPTH_30BPP;
+   LB_PIXEL_DEPTH_30BPP |
+   LB_PIXEL_DEPTH_36BPP;
 
xfm_dce->lb_bits_per_entry = LB_BITS_PER_ENTRY;
xfm_dce->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x6B0*/
@@ -1675,7 +1676,8 @@ void dce60_transform_construct(
xfm_dce->lb_pixel_depth_supported =
LB_PIXEL_DEPTH_18BPP |
LB_PIXEL_DEPTH_24BPP |
-   LB_PIXEL_DEPTH_30BPP;
+   LB_PIXEL_DEPTH_30BPP |
+   LB_PIXEL_DEPTH_36BPP;
 
xfm_dce->lb_bits_per_entry = LB_BITS_PER_ENTRY;
xfm_dce->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x6B0*/
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c
index 29438c6050db..45bca0db5e5e 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c
@@ -708,7 +708,8 @@ bool dce110_transform_v_construct(
xfm_dce->lb_pixel_depth_supported =
LB_PIXEL_DEPTH_18BPP |
LB_PIXEL_DEPTH_24BPP |
-   LB_PIXEL_DEPTH_30BPP;
+   LB_PIXEL_DEPTH_30BPP |
+   LB_PIXEL_DEPTH_36BPP;
 
xfm_dce->prescaler_on = true;
xfm_dce->lb_bits_per_entry = LB_BITS_PER_ENTRY;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
index a77e7bd3b8d5..91fdfcd8a14e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
@@ -568,7 +568,8 @@ void dpp1_construct(
dpp->lb_pixel_depth_supported =
LB_PIXEL_DEPTH_18BPP |
LB_PIXEL_DEPTH_24BPP |
-   LB_PIXEL_DEPTH_30BPP;
+   LB_PIXEL_DEPTH_30BPP |
+   LB_PIXEL_DEPTH_36BPP;
 
dpp->lb_bits_per_entry = LB_BITS_PER_ENTRY;
dpp->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x1404*/
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 

[PATCH 2/5] drm/amd/display: Add support for SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616.

[Mario Kleiner]

Add the necessary format definition, bandwidth and pixel size mappings,
prescaler setup, and pixelformat selection, following the logic
already present for SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616.

The new SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616 is implemented as the
old SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 format, but with swapped
red <-> green color channel, by use of the hardware xbar.

Please note that on the DCN 1/2/3 display engines, the pixelformat
in hubp and dpp setup for the old SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616
and the new SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616 was changed from
format id 22 to id 26. See amd/include/navi10_enum.h for the meaning
of the id's.

For format 22, the display engine read the framebuffer in 16 bpc format,
but truncated to the 12 bpc actually supported by later pipeline stages.
However, the engine took the 12 LSB of each color component for
truncation, which is incompatible with rendering at least under Vulkan,
where content is 16 bit wide, and a 12 MSB alignment would be appropriate,
if any. Format 20 for ARGB16161616_12MSB does work, but even better, we
can choose format 26 for ARGB16161616_UNORM, keeping all 16 bits around
until later stages of the display pipeline.

This allows to directly consume what the rendering hw produces under
Vulkan for swapchain format VK_FORMAT_R16G16B16A16_UNORM, as tested
with a patched version of the current AMD open-source amdvlk driver
which maps swapchain format VK_FORMAT_R16G16B16A16_UNORM onto
DRM_FORMAT_XBGR16161616.

The old id 22 would cause colorful pixeltrash to be displayed instead.

Tested under DCN-1.0 and DCE-11.2.

Signed-off-by: Mario Kleiner 
---
 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c| 2 ++
 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c| 2 ++
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c   | 2 ++
 drivers/gpu/drm/amd/display/dc/dc_hw_types.h| 2 ++
 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c  | 2 ++
 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 1 +
 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c  | 1 +
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c| 6 --
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c | 1 +
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c   | 4 +++-
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c| 3 ++-
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c | 1 +
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c   | 4 +++-
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c   | 1 +
 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c| 3 ++-
 15 files changed, 29 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 
b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
index e633f8a51edb..4e3664db7456 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
@@ -2827,6 +2827,7 @@ static void populate_initial_data(
data->bytes_per_pixel[num_displays + 4] = 4;
break;
case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
+   case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
data->bytes_per_pixel[num_displays + 4] = 8;
break;
@@ -2930,6 +2931,7 @@ static void populate_initial_data(
data->bytes_per_pixel[num_displays + 4] = 4;
break;
case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
+   case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
data->bytes_per_pixel[num_displays + 4] = 8;
break;
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 
b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index d4df4da5b81a..0e18df1283b6 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -236,6 +236,7 @@ static enum dcn_bw_defs tl_pixel_format_to_bw_defs(enum 
surface_pixel_format for
case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
return dcn_bw_rgb_sub_32;
case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
+   case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
return dcn_bw_rgb_sub_64;
@@ -375,6 +376,7 @@ static void pipe_ctx_to_e2e_pipe_params (
input->src.viewport_height_c   = input->src.viewport_height / 2;
break;
case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
+   case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:

[PATCH 1/5] drm/fourcc: Add 16 bpc fixed point framebuffer formats.

[Mario Kleiner]

These are 16 bits per color channel unsigned normalized formats.
They are supported by at least AMD display hw, and suitable for
direct scanout of Vulkan swapchain images in the format
VK_FORMAT_R16G16B16A16_UNORM.

Signed-off-by: Mario Kleiner 
---
 drivers/gpu/drm/drm_fourcc.c  | 4 
 include/uapi/drm/drm_fourcc.h | 7 +++
 2 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index 03262472059c..ce13d2be5d7b 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -203,6 +203,10 @@ const struct drm_format_info *__drm_format_info(u32 format)
{ .format = DRM_FORMAT_ARGB16161616F,   .depth = 0,  
.num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
{ .format = DRM_FORMAT_ABGR16161616F,   .depth = 0,  
.num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
{ .format = DRM_FORMAT_AXBXGXRX106106106106, .depth = 0, 
.num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
+   { .format = DRM_FORMAT_XRGB16161616,.depth = 0,  
.num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1 },
+   { .format = DRM_FORMAT_XBGR16161616,.depth = 0,  
.num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1 },
+   { .format = DRM_FORMAT_ARGB16161616,.depth = 0,  
.num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
+   { .format = DRM_FORMAT_ABGR16161616,.depth = 0,  
.num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
{ .format = DRM_FORMAT_RGB888_A8,   .depth = 32, 
.num_planes = 2, .cpp = { 3, 1, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
{ .format = DRM_FORMAT_BGR888_A8,   .depth = 32, 
.num_planes = 2, .cpp = { 3, 1, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
{ .format = DRM_FORMAT_XRGB_A8, .depth = 32, 
.num_planes = 2, .cpp = { 4, 1, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index f76de49c768f..f7156322aba5 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -168,6 +168,13 @@ extern "C" {
 #define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] 
R:G:B:A 10:10:10:2 little endian */
 #define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] 
B:G:R:A 10:10:10:2 little endian */
 
+/* 64 bpp RGB */
+#define DRM_FORMAT_XRGB16161616fourcc_code('X', 'R', '4', '8') /* 
[63:0] x:R:G:B 16:16:16:16 little endian */
+#define DRM_FORMAT_XBGR16161616fourcc_code('X', 'B', '4', '8') /* 
[63:0] x:B:G:R 16:16:16:16 little endian */
+
+#define DRM_FORMAT_ARGB16161616fourcc_code('A', 'R', '4', '8') /* 
[63:0] A:R:G:B 16:16:16:16 little endian */
+#define DRM_FORMAT_ABGR16161616fourcc_code('A', 'B', '4', '8') /* 
[63:0] A:B:G:R 16:16:16:16 little endian */
+
 /*
  * Floating point 64bpp RGB
  * IEEE 754-2008 binary16 half-precision float
-- 
2.25.1

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16 bpc fixed point (RGBA16) framebuffer support for core and AMD.

[Mario Kleiner]

Hi,

this patch series adds the fourcc's for 16 bit fixed point unorm
framebuffers to the core, and then an implementation for AMD gpu's
with DisplayCore.

This is intended to allow for pageflipping to, and direct scanout of,
Vulkan swapchain images in the format VK_FORMAT_R16G16B16A16_UNORM.
I have patched AMD's GPUOpen amdvlk OSS driver to enable this format
for swapchains, mapping to DRM_FORMAT_XBGR16161616:
Link: 
https://github.com/kleinerm/pal/commit/a25d4802074b13a8d5f7edc96ae45469ecbac3c4

My main motivation for this is squeezing every bit of precision
out of the hardware for scientific and medical research applications,
where fp16 in the unorm range is limited to ~11 bpc effective linear
precision in the upper half [0.5;1.0] of the unorm range, although
the hardware could do at least 12 bpc.

It has been successfully tested on AMD RavenRidge (DCN-1), and with
Polaris11 (DCE-11.2). Up to two displays were active on RavenRidge
(DP 2560x1440@144Hz + HDMI 2560x1440@120Hz), the maximum supported
on my hw, both running at 10 bpc DP output depth.

Up to three displays were active on the Polaris (DP 2560x1440@144Hz +
2560x1440@100Hz USB-C DP-altMode-to-HDMI converter + eDP 2880x1800@60Hz
Apple Retina panel), all running at 10 bpc output depth.

No malfunctions, visual artifacts or other oddities were observed
(apart from an adventureous mess of cables and adapters on my desk),
suggesting it works.

I used my automatic photometer measurement procedure to verify the
effective output precision of 10 bpc DP native signal + spatial
dithering in the gpu as enabled by the amdgpu driver. Results show
the expected 12 bpc precision i hoped for -- the current upper limit
for AMD display hw afaik.

So it seems to work in the way i hoped :).

Some open questions wrt. AMD DC, to be addressed in this patch series, or 
follow up
patches if neccessary:

- For the atomic check for plane scaling, the current patch will
apply the same hw limits as for other rgb fixed point fb's, e.g.,
for 8 bpc rgb8. Is this correct? Or would we need to use the fp16
limits, because this is also a 64 bpp format? Or something new
entirely?

- I haven't added the new fourcc to the DCC tables yet. Should i?

- I had to change an assert for DCE to allow 36bpp linebuffers (patch 4/5).
It looks to me as if that assert was inconsistent with other places
in the driver where COLOR_DEPTH121212 is supported, and looking at
the code, the change seems harmless. At least on DCE-11.2 the change
didn't cause any noticeable (by myself) or measurable (by my equipment)
problems on any of the 3 connected displays.

- Related to that change, while i needed to increase lb pixelsize to 36bpp
to get > 10 bpc effective precision on DCN, i didn't need to do that
on DCE. Also no change of lb pixelsize was needed on either DCN or DCe
to get > 10 bpc precision for fp16 framebuffers, so something seems to
behave differently for floating point 16 vs. fixed point 16. This all
seems to suggest one could leave lb pixelsize at the old 30 bpp value
on at least DCE-11.2 and still get the > 10 bpc precision if one wanted
to avoid the changes of patch 4/5.

Thanks,
-mario


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Re: [PATCH 2/3] drm/connector: Add helper to compare HDR metadata

[Harry Wentland]

On 2021-03-19 8:49 a.m., Maxime Ripard wrote:

All the drivers that support the HDR metadata property have a similar
function to compare the metadata from one connector state to the next,
and force a mode change if they differ.

All these functions run pretty much the same code, so let's turn it into
an helper that can be shared across those drivers.

Signed-off-by: Maxime Ripard 


Patches 1 & 2 are
Reviewed-by: Harry Wentland 

Harry


---
  .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 21 +-
  drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 17 +--
  drivers/gpu/drm/drm_connector.c   | 28 +++
  drivers/gpu/drm/i915/display/intel_atomic.c   | 13 +
  include/drm/drm_connector.h   |  2 ++
  5 files changed, 33 insertions(+), 48 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 06908a3cee0f..4eb5201e566a 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -5924,25 +5924,6 @@ static int fill_hdr_info_packet(const struct 
drm_connector_state *state,
return 0;
  }
  
-static bool

-is_hdr_metadata_different(const struct drm_connector_state *old_state,
- const struct drm_connector_state *new_state)
-{
-   struct drm_property_blob *old_blob = old_state->hdr_output_metadata;
-   struct drm_property_blob *new_blob = new_state->hdr_output_metadata;
-
-   if (old_blob != new_blob) {
-   if (old_blob && new_blob &&
-   old_blob->length == new_blob->length)
-   return memcmp(old_blob->data, new_blob->data,
- old_blob->length);
-
-   return true;
-   }
-
-   return false;
-}
-
  static int
  amdgpu_dm_connector_atomic_check(struct drm_connector *conn,
 struct drm_atomic_state *state)
@@ -5960,7 +5941,7 @@ amdgpu_dm_connector_atomic_check(struct drm_connector 
*conn,
if (!crtc)
return 0;
  
-	if (is_hdr_metadata_different(old_con_state, new_con_state)) {

+   if (!drm_connector_atomic_hdr_metadata_equal(old_con_state, 
new_con_state)) {
struct dc_info_packet hdr_infopacket;
  
  		ret = fill_hdr_info_packet(new_con_state, _infopacket);

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
index f24bbb840dbf..f871e33c2fc9 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
@@ -2395,21 +2395,6 @@ static int dw_hdmi_connector_get_modes(struct 
drm_connector *connector)
return ret;
  }
  
-static bool hdr_metadata_equal(const struct drm_connector_state *old_state,

-  const struct drm_connector_state *new_state)
-{
-   struct drm_property_blob *old_blob = old_state->hdr_output_metadata;
-   struct drm_property_blob *new_blob = new_state->hdr_output_metadata;
-
-   if (!old_blob || !new_blob)
-   return old_blob == new_blob;
-
-   if (old_blob->length != new_blob->length)
-   return false;
-
-   return !memcmp(old_blob->data, new_blob->data, old_blob->length);
-}
-
  static int dw_hdmi_connector_atomic_check(struct drm_connector *connector,
  struct drm_atomic_state *state)
  {
@@ -2423,7 +2408,7 @@ static int dw_hdmi_connector_atomic_check(struct 
drm_connector *connector,
if (!crtc)
return 0;
  
-	if (!hdr_metadata_equal(old_state, new_state)) {

+   if (!drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) {
crtc_state = drm_atomic_get_crtc_state(state, crtc);
if (IS_ERR(crtc_state))
return PTR_ERR(crtc_state);
diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index e25248e23e18..d781a3a1e9bf 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -2170,6 +2170,34 @@ int 
drm_connector_attach_hdr_output_metadata_property(struct drm_connector *conn
  }
  EXPORT_SYMBOL(drm_connector_attach_hdr_output_metadata_property);
  
+/**

+ * drm_connector_atomic_hdr_metadata_equal - checks if the hdr metadata changed
+ * @old_state: old connector state to compare
+ * @new_state: new connector state to compare
+ *
+ * This is used by HDR-enabled drivers to test whether the HDR metadata
+ * have changed between two different connector state (and thus probably
+ * requires a full blown mode change).
+ *
+ * Returns:
+ * True if the metadata are equal, False otherwise
+ */
+bool drm_connector_atomic_hdr_metadata_equal(struct drm_connector_state 
*old_state,
+struct drm_connector_state 
*new_state)
+{
+   struct drm_property_blob *old_blob = old_state->hdr_output_metadata;
+   

Re: [PATCH] drm/radeon/ttm: Fix memory leak userptr pages

[Felix Kuehling]

This caused a regression in kfdtest in a large-buffer stress test after 
memory allocation for user pages fails:


[17359.536303] amdgpu: init_user_pages: Failed to get user pages: -16
[17359.543746] BUG: kernel NULL pointer dereference, address: 
[17359.551494] #PF: supervisor read access in kernel mode
[17359.557375] #PF: error_code(0x) - not-present page
[17359.563247] PGD 0 P4D 0
[17359.566514] Oops:  [#1] SMP PTI
[17359.570728] CPU: 8 PID: 5944 Comm: kfdtest Not tainted 5.11.0-kfd-fkuehlin 
#193
[17359.578760] Hardware name: ASUS All Series/X99-E WS/USB 3.1, BIOS 3201 
06/17/2016
[17359.586971] RIP: 0010:amdgpu_ttm_backend_unbind+0x52/0x110 [amdgpu]
[17359.594075] Code: 48 39 c6 74 1b 8b 53 0c 48 8d bd 80 a1 ff ff e8 24 62 00 00 85 
c0 0f 85 ab 00 00 00 c6 43 54 00 5b 5d c3 48 8b 46 10 8b 4e 50 <48> 8b 30 48 85 
f6 74 ba 8b 50 0c 48 8b bf 80 a1 ff ff 83 e1 01 45
[17359.614340] RSP: 0018:a4764971fc98 EFLAGS: 00010206
[17359.620315] RAX:  RBX: 950e8d4edf00 RCX: 
[17359.628204] RDX:  RSI: 950e8d4edf00 RDI: 950eadec5e80
[17359.636084] RBP: 950eadec5e80 R08:  R09: 
[17359.643958] R10: 0246 R11: 0001 R12: 950c03377800
[17359.651833] R13: 950eadec5e80 R14: 950c03377858 R15: 
[17359.659701] FS:  7febb20cb740() GS:950ebfc0() 
knlGS:
[17359.668528] CS:  0010 DS:  ES:  CR0: 80050033
[17359.675012] CR2:  CR3: 0006d700e005 CR4: 001706e0
[17359.682883] Call Trace:
[17359.686063]  amdgpu_ttm_backend_destroy+0x12/0x70 [amdgpu]
[17359.692349]  ttm_bo_cleanup_memtype_use+0x37/0x60 [ttm]
[17359.698307]  ttm_bo_release+0x278/0x5e0 [ttm]
[17359.703385]  amdgpu_bo_unref+0x1a/0x30 [amdgpu]
[17359.708701]  amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu+0x7e5/0x910 [amdgpu]
[17359.716307]  kfd_ioctl_alloc_memory_of_gpu+0x11a/0x220 [amdgpu]
[17359.723036]  kfd_ioctl+0x223/0x400 [amdgpu]
[17359.728017]  ? kfd_dev_is_large_bar+0x90/0x90 [amdgpu]
[17359.734152]  __x64_sys_ioctl+0x8b/0xd0
[17359.738796]  do_syscall_64+0x2d/0x40
[17359.743259]  entry_SYSCALL_64_after_hwframe+0x44/0xa9
[17359.749205] RIP: 0033:0x7febb083b6d7
[17359.753681] Code: b3 66 90 48 8b 05 b1 47 2d 00 64 c7 00 26 00 00 00 48 c7 c0 ff 
ff ff ff c3 66 2e 0f 1f 84 00 00 00 00 00 b8 10 00 00 00 0f 05 <48> 3d 01 f0 ff 
ff 73 01 c3 48 8b 0d 81 47 2d 00 f7 d8 64 89 01 48
[17359.774340] RSP: 002b:7ffdb5522cd8 EFLAGS: 0202 ORIG_RAX: 
0010
[17359.782668] RAX: ffda RBX: 0001 RCX: 7febb083b6d7
[17359.790566] RDX: 7ffdb5522d60 RSI: c0284b16 RDI: 0003
[17359.798459] RBP: 7ffdb5522d10 R08: 7ffdb5522dd0 R09: c404
[17359.806352] R10:  R11: 0202 R12: 559416e4e2aa
[17359.814251] R13:  R14: 0021 R15: 
[17359.822140] Modules linked in: ip6table_filter ip6_tables iptable_filter 
amdgpu x86_pkg_temp_thermal drm_ttm_helper ttm iommu_v2 gpu_sched ip_tables 
x_tables
[17359.837776] CR2: 
[17359.841888] ---[ end trace a6f27d64475b28c8 ]---
[17359.847318] RIP: 0010:amdgpu_ttm_backend_unbind+0x52/0x110 [amdgpu]
[17359.854479] Code: 48 39 c6 74 1b 8b 53 0c 48 8d bd 80 a1 ff ff e8 24 62 00 00 85 
c0 0f 85 ab 00 00 00 c6 43 54 00 5b 5d c3 48 8b 46 10 8b 4e 50 <48> 8b 30 48 85 
f6 74 ba 8b 50 0c 48 8b bf 80 a1 ff ff 83 e1 01 45
[17359.874929] RSP: 0018:a4764971fc98 EFLAGS: 00010206
[17359.881014] RAX:  RBX: 950e8d4edf00 RCX: 
[17359.889007] RDX:  RSI: 950e8d4edf00 RDI: 950eadec5e80
[17359.897008] RBP: 950eadec5e80 R08:  R09: 
[17359.905020] R10: 0246 R11: 0001 R12: 950c03377800
[17359.913034] R13: 950eadec5e80 R14: 950c03377858 R15: 
[17359.921050] FS:  7febb20cb740() GS:950ebfc0() 
knlGS:
[17359.930047] CS:  0010 DS:  ES:  CR0: 80050033
[17359.936674] CR2:  CR3: 0006d700e005 CR4: 001706e0

Reverting this patch fixes the problem for me.

Regards,
  Felix

On 2021-03-18 10:57 p.m., Alex Deucher wrote:

Applied.  Thanks!

Alex

On Thu, Mar 18, 2021 at 5:00 AM Koenig, Christian
 wrote:

Reviewed-by: Christian König 

Von: Daniel Gomez 
Gesendet: Donnerstag, 18. März 2021 09:32
Cc: dag...@gmail.com ; Daniel Gomez ; Deucher, Alexander 
; Koenig, Christian ; David Airlie ; Daniel 
Vetter ; amd-gfx@lists.freedesktop.org ; dri-de...@lists.freedesktop.org 
; linux-ker...@vger.kernel.org 
Betreff: [PATCH] drm/radeon/ttm: Fix memory leak userptr pages

If userptr pages have been pinned but not bounded,
they remain uncleared.

Signed-off-by: Daniel Gomez 
---
  drivers/gpu/drm/radeon/radeon_ttm.c | 5 +++--
  1 file 

Re: [PATCH] drm/amdgpu/display: restore AUX_DPHY_TX_CONTROL for DCN2.x

[Harry Wentland]

On 2021-03-11 9:22 a.m., Alex Deucher wrote:

On Wed, Feb 17, 2021 at 11:53 AM Harry Wentland  wrote:


On 2021-02-16 12:28 p.m., Alex Deucher wrote:

Commit 098214999c8f added fetching of the AUX_DPHY register
values from the vbios, but it also changed the default values
in the case when there are no values in the vbios.  This causes
problems with displays with high refresh rates.  To fix this,
switch back to the original default value for AUX_DPHY_TX_CONTROL.


I don't see how this impacts displays with high refresh rates
specifically. This is a change that only affects our AUX pre-charge time
and was provided to us by the HW team. It does depend on another
register being programmed by the VBIOS/DMCUBFW at boot.

Before we revert this I would like confirmation that this is the root of
the problem.


Any updates on this?  Can we apply this in the meantime?



Sorry for the late response.

Looks like the other two patches I had were flaky, though I don't fully 
understand why. Let's just revert this change for NV1x (i.e. your change).


Reviewed-by: Harry Wentland 

Harry


Thanks,

Alex



Harry



Fixes: 098214999c8f ("drm/amd/display: Read VBIOS Golden Settings Tbl")
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1426 Signed-off-by: Alex 
Deucher 
Cc: Igor Kravchenko 
Cc: Aric Cyr 
Cc: Aurabindo Pillai 
---
   drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c | 3 +--
   1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c
index fa013496e26b..2f9bfaeaba8d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c
@@ -341,8 +341,7 @@ void enc2_hw_init(struct link_encoder *enc)
   } else {
   AUX_REG_WRITE(AUX_DPHY_RX_CONTROL0, 0x103d1110);

- AUX_REG_WRITE(AUX_DPHY_TX_CONTROL, 0x21c4d);
-
+ AUX_REG_WRITE(AUX_DPHY_TX_CONTROL, 0x21c7a);
   }

   //AUX_DPHY_TX_REF_CONTROL'AUX_TX_REF_DIV HW default is 0x32;



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Re: [PATCH 06/19] drm/amd/display/dc/calcs/dce_calcs: Move some large variables from the stack to the heap

[Alex Deucher]

On Fri, Mar 19, 2021 at 2:47 PM Christian König
 wrote:
>
>
>
> Am 19.03.21 um 19:26 schrieb Harry Wentland:
> > On 2021-03-19 2:13 p.m., Alex Deucher wrote:
> >> + Harry, Nick
> >>
> >> On Fri, Mar 19, 2021 at 4:24 AM Lee Jones  wrote:
> >>>
> >>> Fixes the following W=1 kernel build warning(s):
> >>>
> >>>   drivers/gpu/drm/amd/amdgpu/../display/dc/calcs/dce_calcs.c: In
> >>> function ‘calculate_bandwidth’:
> >>> drivers/gpu/drm/amd/amdgpu/../display/dc/calcs/dce_calcs.c:2016:1:
> >>> warning: the frame size of 1216 bytes is larger than 1024 bytes
> >>> [-Wframe-larger-than=]
> >>>
> >>> Cc: Harry Wentland 
> >>> Cc: Leo Li 
> >>> Cc: Alex Deucher 
> >>> Cc: "Christian König" 
> >>> Cc: David Airlie 
> >>> Cc: Daniel Vetter 
> >>> Cc: Colin Ian King 
> >>> Cc: amd-gfx@lists.freedesktop.org
> >>> Cc: dri-de...@lists.freedesktop.org
> >>> Signed-off-by: Lee Jones 
> >>> ---
> >>>   .../gpu/drm/amd/display/dc/calcs/dce_calcs.c  | 32
> >>> ---
> >>>   1 file changed, 28 insertions(+), 4 deletions(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
> >>> b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
> >>> index e633f8a51edb6..9d8f2505a61c2 100644
> >>> --- a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
> >>> +++ b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
> >>> @@ -98,16 +98,16 @@ static void calculate_bandwidth(
> >>>  int32_t num_cursor_lines;
> >>>
> >>>  int32_t i, j, k;
> >>> -   struct bw_fixed yclk[3];
> >>> -   struct bw_fixed sclk[8];
> >>> +   struct bw_fixed *yclk;
> >>> +   struct bw_fixed *sclk;
> >>>  bool d0_underlay_enable;
> >>>  bool d1_underlay_enable;
> >>>  bool fbc_enabled;
> >>>  bool lpt_enabled;
> >>>  enum bw_defines sclk_message;
> >>>  enum bw_defines yclk_message;
> >>> -   enum bw_defines tiling_mode[maximum_number_of_surfaces];
> >>> -   enum bw_defines surface_type[maximum_number_of_surfaces];
> >>> +   enum bw_defines *tiling_mode;
> >>> +   enum bw_defines *surface_type;
> >>>  enum bw_defines voltage;
> >>>  enum bw_defines pipe_check;
> >>>  enum bw_defines hsr_check;
> >>> @@ -122,6 +122,22 @@ static void calculate_bandwidth(
> >>>  int32_t number_of_displays_enabled_with_margin = 0;
> >>>  int32_t number_of_aligned_displays_with_no_margin = 0;
> >>>
> >>> +   yclk = kcalloc(3, sizeof(*yclk), GFP_KERNEL);
> >>> +   if (!yclk)
> >>> +   return;
> >>> +
> >>> +   sclk = kcalloc(8, sizeof(*sclk), GFP_KERNEL);
> >>> +   if (!sclk)
> >>> +   goto free_yclk;
> >>> +
> >>> +   tiling_mode = kcalloc(maximum_number_of_surfaces,
> >>> sizeof(*tiling_mode), GFP_KERNEL);
> >>> +   if (!tiling_mode)
> >>> +   goto free_sclk;
> >>> +
> >>> +   surface_type = kcalloc(maximum_number_of_surfaces,
> >>> sizeof(*surface_type), GFP_KERNEL);
> >>> +   if (!surface_type)
> >>> +   goto free_tiling_mode;
> >>> +
> >>
> >>
> >> Harry or Nick can correct me if I'm wrong, but for this patch and the
> >> next one, I think this can be called from an atomic context.
> >>
> >
> > From what I can see this doesn't seem the case. If I'm missing
> > something someone please correct me.
>
> Have you taken into account that using FP functions require atomic
> context as well?
>
> We had quite a bunch of problems with that and had to replace some
> GFP_KERNEL with GFP_ATOMIC in the DC code because of this.
>
> Could of course be that this code here isn't affected by that, but
> better save than sorry.

DCE hardware uses fixed point math so that should be ok.  It's just
the newer DCN hardware that requires FP.

Alex


>
> Christian.
>
> >
> > This and the next (06/19) patch are both
> > Reviewed-by: Harry Wentland 
> >
> > Harry
> >
> >> Alex
> >>
> >>>  yclk[low] = vbios->low_yclk;
> >>>  yclk[mid] = vbios->mid_yclk;
> >>>  yclk[high] = vbios->high_yclk;
> >>> @@ -2013,6 +2029,14 @@ static void calculate_bandwidth(
> >>>  }
> >>>  }
> >>>  }
> >>> +
> >>> +   kfree(surface_type);
> >>> +free_tiling_mode:
> >>> +   kfree(tiling_mode);
> >>> +free_yclk:
> >>> +   kfree(yclk);
> >>> +free_sclk:
> >>> +   kfree(sclk);
> >>>   }
> >>>
> >>> /***
> >>> --
> >>> 2.27.0
> >>>
> >>> ___
> >>> dri-devel mailing list
> >>> dri-de...@lists.freedesktop.org
> >>> https://lists.freedesktop.org/mailman/listinfo/dri-devel>
>
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[PATCH 1/1] drm/amdgpu: fix amdgpu_res_first()

[Nirmoy Das]

Fix size comparison in the resource cursor.

Signed-off-by: Nirmoy Das 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h
index b49a61d07d60..40f2adf305bc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h
@@ -64,7 +64,7 @@ static inline void amdgpu_res_first(struct ttm_resource *res,
BUG_ON(start + size > res->num_pages << PAGE_SHIFT);
 
node = res->mm_node;
-   while (start > node->size << PAGE_SHIFT)
+   while (start >= node->size << PAGE_SHIFT)
start -= node++->size << PAGE_SHIFT;
 
cur->start = (node->start << PAGE_SHIFT) + start;
-- 
2.30.1

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Re: [PATCH] drm/ttm: stop warning on TT shrinker failure

[Daniel Vetter]

On Fri, Mar 19, 2021 at 07:53:48PM +0100, Christian König wrote:
> Am 19.03.21 um 18:52 schrieb Daniel Vetter:
> > On Fri, Mar 19, 2021 at 03:08:57PM +0100, Christian König wrote:
> > > Don't print a warning when we fail to allocate a page for swapping things 
> > > out.
> > > 
> > > Also rely on memalloc_nofs_save/memalloc_nofs_restore instead of GFP_NOFS.
> > Uh this part doesn't make sense. Especially since you only do it for the
> > debugfs file, not in general. Which means you've just completely broken
> > the shrinker.
> 
> Are you sure? My impression is that GFP_NOFS should now work much more out
> of the box with the memalloc_nofs_save()/memalloc_nofs_restore().

Yeah, if you'd put it in the right place :-)

But also -mm folks are very clear that memalloc_no*() family is for dire
situation where there's really no other way out. For anything where you
know what you're doing, you really should use explicit gfp flags.

> > If this is just to paper over the seq_printf doing the wrong allocations,
> > then just move that out from under the fs_reclaim_acquire/release part.
> 
> No, that wasn't the problem.
> 
> We have just seen to many failures to allocate pages for swapout and I think
> that would improve this because in a lot of cases we can then immediately
> swap things out instead of having to rely on upper layers.

Yeah, you broke it. Now the real shrinker is running with GFP_KERNEL,
because your memalloc_no is only around the debugfs function. And ofc it's
much easier to allocate with GFP_KERNEL, right until you deadlock :-)

Shrinking is hard, there's no easy way out here.

Cheers, Daniel

> 
> Regards,
> Christian.
> 
> 
> > 
> > __GFP_NOWARN should be there indeed I think.
> > -Daniel
> > 
> > > Signed-off-by: Christian König 
> > > ---
> > >   drivers/gpu/drm/ttm/ttm_tt.c | 5 -
> > >   1 file changed, 4 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c
> > > index 2f0833c98d2c..86fa3e82dacc 100644
> > > --- a/drivers/gpu/drm/ttm/ttm_tt.c
> > > +++ b/drivers/gpu/drm/ttm/ttm_tt.c
> > > @@ -369,7 +369,7 @@ static unsigned long ttm_tt_shrinker_scan(struct 
> > > shrinker *shrink,
> > >   };
> > >   int ret;
> > > - ret = ttm_bo_swapout(, GFP_NOFS);
> > > + ret = ttm_bo_swapout(, GFP_KERNEL | __GFP_NOWARN);
> > >   return ret < 0 ? SHRINK_EMPTY : ret;
> > >   }
> > > @@ -389,10 +389,13 @@ static unsigned long ttm_tt_shrinker_count(struct 
> > > shrinker *shrink,
> > >   static int ttm_tt_debugfs_shrink_show(struct seq_file *m, void *data)
> > >   {
> > >   struct shrink_control sc = { .gfp_mask = GFP_KERNEL };
> > > + unsigned int flags;
> > >   fs_reclaim_acquire(GFP_KERNEL);
> > > + flags = memalloc_nofs_save();
> > >   seq_printf(m, "%lu/%lu\n", ttm_tt_shrinker_count(_shrinker, 
> > > ),
> > >  ttm_tt_shrinker_scan(_shrinker, ));
> > > + memalloc_nofs_restore(flags);
> > >   fs_reclaim_release(GFP_KERNEL);
> > >   return 0;
> > > -- 
> > > 2.25.1
> > > 
> > > ___
> > > dri-devel mailing list
> > > dri-de...@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/dri-devel
> 

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [PATCH 1/1] drm/amd/display: use GFP_ATOMIC in dcn20_resource_construct

[Harry Wentland]

On 2021-03-19 2:19 p.m., Nirmoy wrote:

ping.

On 3/17/21 11:52 AM, Nirmoy Das wrote:

Replace GFP_KERNEL with GFP_ATOMIC as dcn20_resource_construct()
can't sleep.

Partially fixes: https://bugzilla.kernel.org/show_bug.cgi?id=212311
as dcn20_resource_construct() also calls into SMU functions which does
mutex_lock().

Signed-off-by: Nirmoy Das 


Reviewed-by: Harry Wentland 

Harry


---
  drivers/gpu/drm/amd/display/dc/dce/dce_abm.c  |  2 +-
  drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c |  6 ++---
  .../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c |  2 +-
  .../drm/amd/display/dc/dcn20/dcn20_resource.c | 26 +--
  4 files changed, 18 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c

index 4e87e70237e3..874b132fe1d7 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
@@ -283,7 +283,7 @@ struct abm *dce_abm_create(
  const struct dce_abm_shift *abm_shift,
  const struct dce_abm_mask *abm_mask)
  {
-    struct dce_abm *abm_dce = kzalloc(sizeof(*abm_dce), GFP_KERNEL);
+    struct dce_abm *abm_dce = kzalloc(sizeof(*abm_dce), GFP_ATOMIC);
  if (abm_dce == NULL) {
  BREAK_TO_DEBUGGER();
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

index 4f864501e046..8cd841320ded 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
@@ -1133,7 +1133,7 @@ struct dmcu *dcn10_dmcu_create(
  const struct dce_dmcu_shift *dmcu_shift,
  const struct dce_dmcu_mask *dmcu_mask)
  {
-    struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_KERNEL);
+    struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_ATOMIC);
  if (dmcu_dce == NULL) {
  BREAK_TO_DEBUGGER();
@@ -1154,7 +1154,7 @@ struct dmcu *dcn20_dmcu_create(
  const struct dce_dmcu_shift *dmcu_shift,
  const struct dce_dmcu_mask *dmcu_mask)
  {
-    struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_KERNEL);
+    struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_ATOMIC);
  if (dmcu_dce == NULL) {
  BREAK_TO_DEBUGGER();
@@ -1175,7 +1175,7 @@ struct dmcu *dcn21_dmcu_create(
  const struct dce_dmcu_shift *dmcu_shift,
  const struct dce_dmcu_mask *dmcu_mask)
  {
-    struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_KERNEL);
+    struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_ATOMIC);
  if (dmcu_dce == NULL) {
  BREAK_TO_DEBUGGER();
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c

index 62cc2651e00c..8774406120fc 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c
@@ -112,7 +112,7 @@ struct dccg *dccg2_create(
  const struct dccg_shift *dccg_shift,
  const struct dccg_mask *dccg_mask)
  {
-    struct dcn_dccg *dccg_dcn = kzalloc(sizeof(*dccg_dcn), GFP_KERNEL);
+    struct dcn_dccg *dccg_dcn = kzalloc(sizeof(*dccg_dcn), GFP_ATOMIC);
  struct dccg *base;
  if (dccg_dcn == NULL) {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c

index 2307b3517821..25f8dd5db080 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -1106,7 +1106,7 @@ struct dpp *dcn20_dpp_create(
  uint32_t inst)
  {
  struct dcn20_dpp *dpp =
-    kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL);
+    kzalloc(sizeof(struct dcn20_dpp), GFP_ATOMIC);
  if (!dpp)
  return NULL;
@@ -1124,7 +1124,7 @@ struct input_pixel_processor *dcn20_ipp_create(
  struct dc_context *ctx, uint32_t inst)
  {
  struct dcn10_ipp *ipp =
-    kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL);
+    kzalloc(sizeof(struct dcn10_ipp), GFP_ATOMIC);
  if (!ipp) {
  BREAK_TO_DEBUGGER();
@@ -1141,7 +1141,7 @@ struct output_pixel_processor *dcn20_opp_create(
  struct dc_context *ctx, uint32_t inst)
  {
  struct dcn20_opp *opp =
-    kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
+    kzalloc(sizeof(struct dcn20_opp), GFP_ATOMIC);
  if (!opp) {
  BREAK_TO_DEBUGGER();
@@ -1158,7 +1158,7 @@ struct dce_aux *dcn20_aux_engine_create(
  uint32_t inst)
  {
  struct aux_engine_dce110 *aux_engine =
-    kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
+    kzalloc(sizeof(struct aux_engine_dce110), GFP_ATOMIC);
  if (!aux_engine)
  return NULL;
@@ -1196,7 +1196,7 @@ struct dce_i2c_hw *dcn20_i2c_hw_create(
  uint32_t inst)
  {
  struct dce_i2c_hw *dce_i2c_hw =
-    kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
+    kzalloc(sizeof(struct dce_i2c_hw), GFP_ATOMIC);
  if (!dce_i2c_hw)
  return NULL;
@@ -1209,7 +1209,7 @@ struct 

Re: [PATCH] drm/amdgpu/display: properly guard dc_dsc_stream_bandwidth_in_kbps

[Harry Wentland]

On 2021-03-19 2:18 p.m., Alex Deucher wrote:

Ping?

On Thu, Mar 18, 2021 at 10:18 PM Alex Deucher  wrote:


Move the function protoype to the right header and guard
the call with CONFIG_DRM_AMD_DC_DCN as DSC is only available
with DCN.

Fixes: a03f6c0e26b2 ("drm/amd/display: Add changes for dsc bpp in 16ths and unify bw 
calculations")
Signed-off-by: Alex Deucher 
Cc: Dillon Varone 
Cc: Stephen Rothwell 


Reviewed-by: Harry Wentland 

Harry


---
  drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 ++--
  drivers/gpu/drm/amd/display/dc/dc_dsc.h   | 2 ++
  2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 10e34e411e06..f9a33dc52c45 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -3498,17 +3498,17 @@ void dc_link_enable_hpd_filter(struct dc_link *link, 
bool enable)
 }
  }

-uint32_t dc_dsc_stream_bandwidth_in_kbps(uint32_t pix_clk_100hz, uint32_t 
bpp_x16);
-
  uint32_t dc_bandwidth_in_kbps_from_timing(
 const struct dc_crtc_timing *timing)
  {
 uint32_t bits_per_channel = 0;
 uint32_t kbps;

+#if defined(CONFIG_DRM_AMD_DC_DCN)
 if (timing->flags.DSC) {
 return dc_dsc_stream_bandwidth_in_kbps(timing->pix_clk_100hz, 
timing->dsc_cfg.bits_per_pixel);
 }
+#endif

 switch (timing->display_color_depth) {
 case COLOR_DEPTH_666:
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dsc.h 
b/drivers/gpu/drm/amd/display/dc/dc_dsc.h
index 0c5d98524536..c51d2d961b7a 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dsc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dsc.h
@@ -88,4 +88,6 @@ void dc_dsc_policy_set_max_target_bpp_limit(uint32_t limit);

  void dc_dsc_policy_set_enable_dsc_when_not_needed(bool enable);

+uint32_t dc_dsc_stream_bandwidth_in_kbps(uint32_t pix_clk_100hz, uint32_t 
bpp_x16);
+
  #endif
--
2.30.2

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Re: [PATCH] drm/ttm: stop warning on TT shrinker failure

[Christian König]

Am 19.03.21 um 18:52 schrieb Daniel Vetter:

On Fri, Mar 19, 2021 at 03:08:57PM +0100, Christian König wrote:

Don't print a warning when we fail to allocate a page for swapping things out.

Also rely on memalloc_nofs_save/memalloc_nofs_restore instead of GFP_NOFS.

Uh this part doesn't make sense. Especially since you only do it for the
debugfs file, not in general. Which means you've just completely broken
the shrinker.


Are you sure? My impression is that GFP_NOFS should now work much more 
out of the box with the memalloc_nofs_save()/memalloc_nofs_restore().



If this is just to paper over the seq_printf doing the wrong allocations,
then just move that out from under the fs_reclaim_acquire/release part.


No, that wasn't the problem.

We have just seen to many failures to allocate pages for swapout and I 
think that would improve this because in a lot of cases we can then 
immediately swap things out instead of having to rely on upper layers.


Regards,
Christian.




__GFP_NOWARN should be there indeed I think.
-Daniel


Signed-off-by: Christian König 
---
  drivers/gpu/drm/ttm/ttm_tt.c | 5 -
  1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c
index 2f0833c98d2c..86fa3e82dacc 100644
--- a/drivers/gpu/drm/ttm/ttm_tt.c
+++ b/drivers/gpu/drm/ttm/ttm_tt.c
@@ -369,7 +369,7 @@ static unsigned long ttm_tt_shrinker_scan(struct shrinker 
*shrink,
};
int ret;
  
-	ret = ttm_bo_swapout(, GFP_NOFS);

+   ret = ttm_bo_swapout(, GFP_KERNEL | __GFP_NOWARN);
return ret < 0 ? SHRINK_EMPTY : ret;
  }
  
@@ -389,10 +389,13 @@ static unsigned long ttm_tt_shrinker_count(struct shrinker *shrink,

  static int ttm_tt_debugfs_shrink_show(struct seq_file *m, void *data)
  {
struct shrink_control sc = { .gfp_mask = GFP_KERNEL };
+   unsigned int flags;
  
  	fs_reclaim_acquire(GFP_KERNEL);

+   flags = memalloc_nofs_save();
seq_printf(m, "%lu/%lu\n", ttm_tt_shrinker_count(_shrinker, ),
   ttm_tt_shrinker_scan(_shrinker, ));
+   memalloc_nofs_restore(flags);
fs_reclaim_release(GFP_KERNEL);
  
  	return 0;

--
2.25.1

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Re: [PATCH 06/19] drm/amd/display/dc/calcs/dce_calcs: Move some large variables from the stack to the heap

[Christian König]

Am 19.03.21 um 19:26 schrieb Harry Wentland:

On 2021-03-19 2:13 p.m., Alex Deucher wrote:

+ Harry, Nick

On Fri, Mar 19, 2021 at 4:24 AM Lee Jones  wrote:


Fixes the following W=1 kernel build warning(s):

  drivers/gpu/drm/amd/amdgpu/../display/dc/calcs/dce_calcs.c: In 
function ‘calculate_bandwidth’:
drivers/gpu/drm/amd/amdgpu/../display/dc/calcs/dce_calcs.c:2016:1: 
warning: the frame size of 1216 bytes is larger than 1024 bytes 
[-Wframe-larger-than=]


Cc: Harry Wentland 
Cc: Leo Li 
Cc: Alex Deucher 
Cc: "Christian König" 
Cc: David Airlie 
Cc: Daniel Vetter 
Cc: Colin Ian King 
Cc: amd-gfx@lists.freedesktop.org
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Lee Jones 
---
  .../gpu/drm/amd/display/dc/calcs/dce_calcs.c  | 32 
---

  1 file changed, 28 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 
b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c

index e633f8a51edb6..9d8f2505a61c2 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
@@ -98,16 +98,16 @@ static void calculate_bandwidth(
 int32_t num_cursor_lines;

 int32_t i, j, k;
-   struct bw_fixed yclk[3];
-   struct bw_fixed sclk[8];
+   struct bw_fixed *yclk;
+   struct bw_fixed *sclk;
 bool d0_underlay_enable;
 bool d1_underlay_enable;
 bool fbc_enabled;
 bool lpt_enabled;
 enum bw_defines sclk_message;
 enum bw_defines yclk_message;
-   enum bw_defines tiling_mode[maximum_number_of_surfaces];
-   enum bw_defines surface_type[maximum_number_of_surfaces];
+   enum bw_defines *tiling_mode;
+   enum bw_defines *surface_type;
 enum bw_defines voltage;
 enum bw_defines pipe_check;
 enum bw_defines hsr_check;
@@ -122,6 +122,22 @@ static void calculate_bandwidth(
 int32_t number_of_displays_enabled_with_margin = 0;
 int32_t number_of_aligned_displays_with_no_margin = 0;

+   yclk = kcalloc(3, sizeof(*yclk), GFP_KERNEL);
+   if (!yclk)
+   return;
+
+   sclk = kcalloc(8, sizeof(*sclk), GFP_KERNEL);
+   if (!sclk)
+   goto free_yclk;
+
+   tiling_mode = kcalloc(maximum_number_of_surfaces, 
sizeof(*tiling_mode), GFP_KERNEL);

+   if (!tiling_mode)
+   goto free_sclk;
+
+   surface_type = kcalloc(maximum_number_of_surfaces, 
sizeof(*surface_type), GFP_KERNEL);

+   if (!surface_type)
+   goto free_tiling_mode;
+



Harry or Nick can correct me if I'm wrong, but for this patch and the
next one, I think this can be called from an atomic context.



From what I can see this doesn't seem the case. If I'm missing 
something someone please correct me.


Have you taken into account that using FP functions require atomic 
context as well?


We had quite a bunch of problems with that and had to replace some 
GFP_KERNEL with GFP_ATOMIC in the DC code because of this.


Could of course be that this code here isn't affected by that, but 
better save than sorry.


Christian.



This and the next (06/19) patch are both
Reviewed-by: Harry Wentland 

Harry


Alex


 yclk[low] = vbios->low_yclk;
 yclk[mid] = vbios->mid_yclk;
 yclk[high] = vbios->high_yclk;
@@ -2013,6 +2029,14 @@ static void calculate_bandwidth(
 }
 }
 }
+
+   kfree(surface_type);
+free_tiling_mode:
+   kfree(tiling_mode);
+free_yclk:
+   kfree(yclk);
+free_sclk:
+   kfree(sclk);
  }

/***
--
2.27.0

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Re: [PATCH 06/19] drm/amd/display/dc/calcs/dce_calcs: Move some large variables from the stack to the heap

[Alex Deucher]

On Fri, Mar 19, 2021 at 2:26 PM Harry Wentland  wrote:
>
> On 2021-03-19 2:13 p.m., Alex Deucher wrote:
> > + Harry, Nick
> >
> > On Fri, Mar 19, 2021 at 4:24 AM Lee Jones  wrote:
> >>
> >> Fixes the following W=1 kernel build warning(s):
> >>
> >>   drivers/gpu/drm/amd/amdgpu/../display/dc/calcs/dce_calcs.c: In function 
> >> ‘calculate_bandwidth’:
> >>   drivers/gpu/drm/amd/amdgpu/../display/dc/calcs/dce_calcs.c:2016:1: 
> >> warning: the frame size of 1216 bytes is larger than 1024 bytes 
> >> [-Wframe-larger-than=]
> >>
> >> Cc: Harry Wentland 
> >> Cc: Leo Li 
> >> Cc: Alex Deucher 
> >> Cc: "Christian König" 
> >> Cc: David Airlie 
> >> Cc: Daniel Vetter 
> >> Cc: Colin Ian King 
> >> Cc: amd-gfx@lists.freedesktop.org
> >> Cc: dri-de...@lists.freedesktop.org
> >> Signed-off-by: Lee Jones 
> >> ---
> >>   .../gpu/drm/amd/display/dc/calcs/dce_calcs.c  | 32 ---
> >>   1 file changed, 28 insertions(+), 4 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 
> >> b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
> >> index e633f8a51edb6..9d8f2505a61c2 100644
> >> --- a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
> >> +++ b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
> >> @@ -98,16 +98,16 @@ static void calculate_bandwidth(
> >>  int32_t num_cursor_lines;
> >>
> >>  int32_t i, j, k;
> >> -   struct bw_fixed yclk[3];
> >> -   struct bw_fixed sclk[8];
> >> +   struct bw_fixed *yclk;
> >> +   struct bw_fixed *sclk;
> >>  bool d0_underlay_enable;
> >>  bool d1_underlay_enable;
> >>  bool fbc_enabled;
> >>  bool lpt_enabled;
> >>  enum bw_defines sclk_message;
> >>  enum bw_defines yclk_message;
> >> -   enum bw_defines tiling_mode[maximum_number_of_surfaces];
> >> -   enum bw_defines surface_type[maximum_number_of_surfaces];
> >> +   enum bw_defines *tiling_mode;
> >> +   enum bw_defines *surface_type;
> >>  enum bw_defines voltage;
> >>  enum bw_defines pipe_check;
> >>  enum bw_defines hsr_check;
> >> @@ -122,6 +122,22 @@ static void calculate_bandwidth(
> >>  int32_t number_of_displays_enabled_with_margin = 0;
> >>  int32_t number_of_aligned_displays_with_no_margin = 0;
> >>
> >> +   yclk = kcalloc(3, sizeof(*yclk), GFP_KERNEL);
> >> +   if (!yclk)
> >> +   return;
> >> +
> >> +   sclk = kcalloc(8, sizeof(*sclk), GFP_KERNEL);
> >> +   if (!sclk)
> >> +   goto free_yclk;
> >> +
> >> +   tiling_mode = kcalloc(maximum_number_of_surfaces, 
> >> sizeof(*tiling_mode), GFP_KERNEL);
> >> +   if (!tiling_mode)
> >> +   goto free_sclk;
> >> +
> >> +   surface_type = kcalloc(maximum_number_of_surfaces, 
> >> sizeof(*surface_type), GFP_KERNEL);
> >> +   if (!surface_type)
> >> +   goto free_tiling_mode;
> >> +
> >
> >
> > Harry or Nick can correct me if I'm wrong, but for this patch and the
> > next one, I think this can be called from an atomic context.
> >
>
>  From what I can see this doesn't seem the case. If I'm missing
> something someone please correct me.
>
> This and the next (06/19) patch are both
> Reviewed-by: Harry Wentland 

Thanks.  I've applied them.

Alex


>
> Harry
>
> > Alex
> >
> >>  yclk[low] = vbios->low_yclk;
> >>  yclk[mid] = vbios->mid_yclk;
> >>  yclk[high] = vbios->high_yclk;
> >> @@ -2013,6 +2029,14 @@ static void calculate_bandwidth(
> >>  }
> >>  }
> >>  }
> >> +
> >> +   kfree(surface_type);
> >> +free_tiling_mode:
> >> +   kfree(tiling_mode);
> >> +free_yclk:
> >> +   kfree(yclk);
> >> +free_sclk:
> >> +   kfree(sclk);
> >>   }
> >>
> >>   
> >> /***
> >> --
> >> 2.27.0
> >>
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Re: [PATCH] drm/amdgpu/powerplay/smu10: refactor AMDGPU_PP_SENSOR_GPU_LOAD

[Alex Deucher]

On Fri, Mar 19, 2021 at 3:04 AM Shirish S  wrote:
>
> refactor AMDGPU_PP_SENSOR_GPU_LOAD to ensure code consistency with other
> commands
>
> Signed-off-by: Shirish S 

Reviewed-by: Alex Deucher 

> ---
>  .../gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c| 13 ++---
>  1 file changed, 6 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c 
> b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
> index f5d59fa3a030..f5fe540cd536 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
> @@ -1297,19 +1297,18 @@ static int smu10_read_sensor(struct pp_hwmgr *hwmgr, 
> int idx,
> *size = 4;
> break;
> case AMDGPU_PP_SENSOR_GPU_LOAD:
> -   if (has_gfx_busy) {
> +   if (!has_gfx_busy)
> +   ret = -EOPNOTSUPP;
> +   else {
> ret = smum_send_msg_to_smc(hwmgr,
>PPSMC_MSG_GetGfxBusy,
>_percent);
> if (!ret)
> -   activity_percent = activity_percent > 100 ? 
> 100 : activity_percent;
> +   *((uint32_t *)value) = min(activity_percent, 
> (u32)100);
> else
> -   return -EIO;
> -   *((uint32_t *)value) = activity_percent;
> -   return 0;
> -   } else {
> -   return -EOPNOTSUPP;
> +   ret = -EIO;
> }
> +   break;
> default:
> ret = -EOPNOTSUPP;
> break;
> --
> 2.17.1
>
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Re: [PATCH 06/19] drm/amd/display/dc/calcs/dce_calcs: Move some large variables from the stack to the heap

[Harry Wentland]

On 2021-03-19 2:13 p.m., Alex Deucher wrote:

+ Harry, Nick

On Fri, Mar 19, 2021 at 4:24 AM Lee Jones  wrote:


Fixes the following W=1 kernel build warning(s):

  drivers/gpu/drm/amd/amdgpu/../display/dc/calcs/dce_calcs.c: In function 
‘calculate_bandwidth’:
  drivers/gpu/drm/amd/amdgpu/../display/dc/calcs/dce_calcs.c:2016:1: warning: 
the frame size of 1216 bytes is larger than 1024 bytes [-Wframe-larger-than=]

Cc: Harry Wentland 
Cc: Leo Li 
Cc: Alex Deucher 
Cc: "Christian König" 
Cc: David Airlie 
Cc: Daniel Vetter 
Cc: Colin Ian King 
Cc: amd-gfx@lists.freedesktop.org
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Lee Jones 
---
  .../gpu/drm/amd/display/dc/calcs/dce_calcs.c  | 32 ---
  1 file changed, 28 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 
b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
index e633f8a51edb6..9d8f2505a61c2 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
@@ -98,16 +98,16 @@ static void calculate_bandwidth(
 int32_t num_cursor_lines;

 int32_t i, j, k;
-   struct bw_fixed yclk[3];
-   struct bw_fixed sclk[8];
+   struct bw_fixed *yclk;
+   struct bw_fixed *sclk;
 bool d0_underlay_enable;
 bool d1_underlay_enable;
 bool fbc_enabled;
 bool lpt_enabled;
 enum bw_defines sclk_message;
 enum bw_defines yclk_message;
-   enum bw_defines tiling_mode[maximum_number_of_surfaces];
-   enum bw_defines surface_type[maximum_number_of_surfaces];
+   enum bw_defines *tiling_mode;
+   enum bw_defines *surface_type;
 enum bw_defines voltage;
 enum bw_defines pipe_check;
 enum bw_defines hsr_check;
@@ -122,6 +122,22 @@ static void calculate_bandwidth(
 int32_t number_of_displays_enabled_with_margin = 0;
 int32_t number_of_aligned_displays_with_no_margin = 0;

+   yclk = kcalloc(3, sizeof(*yclk), GFP_KERNEL);
+   if (!yclk)
+   return;
+
+   sclk = kcalloc(8, sizeof(*sclk), GFP_KERNEL);
+   if (!sclk)
+   goto free_yclk;
+
+   tiling_mode = kcalloc(maximum_number_of_surfaces, sizeof(*tiling_mode), 
GFP_KERNEL);
+   if (!tiling_mode)
+   goto free_sclk;
+
+   surface_type = kcalloc(maximum_number_of_surfaces, 
sizeof(*surface_type), GFP_KERNEL);
+   if (!surface_type)
+   goto free_tiling_mode;
+



Harry or Nick can correct me if I'm wrong, but for this patch and the
next one, I think this can be called from an atomic context.



From what I can see this doesn't seem the case. If I'm missing 
something someone please correct me.


This and the next (06/19) patch are both
Reviewed-by: Harry Wentland 

Harry


Alex


 yclk[low] = vbios->low_yclk;
 yclk[mid] = vbios->mid_yclk;
 yclk[high] = vbios->high_yclk;
@@ -2013,6 +2029,14 @@ static void calculate_bandwidth(
 }
 }
 }
+
+   kfree(surface_type);
+free_tiling_mode:
+   kfree(tiling_mode);
+free_yclk:
+   kfree(yclk);
+free_sclk:
+   kfree(sclk);
  }

  
/***
--
2.27.0

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Re: [PATCH 08/19] drm/amd/display/dc/dce80/dce80_resource: Make local functions static

[Harry Wentland]

On 2021-03-19 4:24 a.m., Lee Jones wrote:

Fixes the following W=1 kernel build warning(s):

  drivers/gpu/drm/amd/amdgpu/../display/dc/dce80/dce80_resource.c:527:17: 
warning: no previous prototype for ‘dce80_aux_engine_create’ 
[-Wmissing-prototypes]
  drivers/gpu/drm/amd/amdgpu/../display/dc/dce80/dce80_resource.c:565:20: 
warning: no previous prototype for ‘dce80_i2c_hw_create’ [-Wmissing-prototypes]
  drivers/gpu/drm/amd/amdgpu/../display/dc/dce80/dce80_resource.c:581:20: 
warning: no previous prototype for ‘dce80_i2c_sw_create’ [-Wmissing-prototypes]
  drivers/gpu/drm/amd/amdgpu/../display/dc/dce80/dce80_resource.c:715:22: 
warning: no previous prototype for ‘dce80_link_encoder_create’ 
[-Wmissing-prototypes]
  drivers/gpu/drm/amd/amdgpu/../display/dc/dce80/dce80_resource.c:754:22: 
warning: no previous prototype for ‘dce80_clock_source_create’ 
[-Wmissing-prototypes]
  drivers/gpu/drm/amd/amdgpu/../display/dc/dce80/dce80_resource.c:778:6: 
warning: no previous prototype for ‘dce80_clock_source_destroy’ 
[-Wmissing-prototypes]
  drivers/gpu/drm/amd/amdgpu/../display/dc/dce80/dce80_resource.c:868:6: 
warning: no previous prototype for ‘dce80_validate_bandwidth’ 
[-Wmissing-prototypes]
  drivers/gpu/drm/amd/amdgpu/../display/dc/dce80/dce80_resource.c:913:16: 
warning: no previous prototype for ‘dce80_validate_global’ 
[-Wmissing-prototypes]

Cc: Harry Wentland 
Cc: Leo Li 
Cc: Alex Deucher 
Cc: "Christian König" 
Cc: David Airlie 
Cc: Daniel Vetter 
Cc: Anthony Koo 
Cc: amd-gfx@lists.freedesktop.org
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Lee Jones 


Reviewed-by: Harry Wentland 

Harry


---
  .../drm/amd/display/dc/dce80/dce80_resource.c| 16 
  1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 
b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
index 612450f992782..725d92e40cd30 100644
--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
@@ -526,7 +526,7 @@ static struct output_pixel_processor *dce80_opp_create(
return >base;
  }
  
-struct dce_aux *dce80_aux_engine_create(

+static struct dce_aux *dce80_aux_engine_create(
struct dc_context *ctx,
uint32_t inst)
  {
@@ -564,7 +564,7 @@ static const struct dce_i2c_mask i2c_masks = {
I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
  };
  
-struct dce_i2c_hw *dce80_i2c_hw_create(

+static struct dce_i2c_hw *dce80_i2c_hw_create(
struct dc_context *ctx,
uint32_t inst)
  {
@@ -580,7 +580,7 @@ struct dce_i2c_hw *dce80_i2c_hw_create(
return dce_i2c_hw;
  }
  
-struct dce_i2c_sw *dce80_i2c_sw_create(

+static struct dce_i2c_sw *dce80_i2c_sw_create(
struct dc_context *ctx)
  {
struct dce_i2c_sw *dce_i2c_sw =
@@ -714,7 +714,7 @@ static const struct encoder_feature_support 
link_enc_feature = {
.flags.bits.IS_TPS3_CAPABLE = true
  };
  
-struct link_encoder *dce80_link_encoder_create(

+static struct link_encoder *dce80_link_encoder_create(
const struct encoder_init_data *enc_init_data)
  {
struct dce110_link_encoder *enc110 =
@@ -753,7 +753,7 @@ static struct panel_cntl *dce80_panel_cntl_create(const 
struct panel_cntl_init_d
return _cntl->base;
  }
  
-struct clock_source *dce80_clock_source_create(

+static struct clock_source *dce80_clock_source_create(
struct dc_context *ctx,
struct dc_bios *bios,
enum clock_source_id id,
@@ -777,7 +777,7 @@ struct clock_source *dce80_clock_source_create(
return NULL;
  }
  
-void dce80_clock_source_destroy(struct clock_source **clk_src)

+static void dce80_clock_source_destroy(struct clock_source **clk_src)
  {
kfree(TO_DCE110_CLK_SRC(*clk_src));
*clk_src = NULL;
@@ -867,7 +867,7 @@ static void dce80_resource_destruct(struct 
dce110_resource_pool *pool)
}
  }
  
-bool dce80_validate_bandwidth(

+static bool dce80_validate_bandwidth(
struct dc *dc,
struct dc_state *context,
bool fast_validate)
@@ -912,7 +912,7 @@ static bool dce80_validate_surface_sets(
return true;
  }
  
-enum dc_status dce80_validate_global(

+static enum dc_status dce80_validate_global(
struct dc *dc,
struct dc_state *context)
  {



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Re: [PATCH 08/19] drm/amd/display/dc/dce80/dce80_resource: Make local functions static

[Alex Deucher]

On Fri, Mar 19, 2021 at 4:24 AM Lee Jones  wrote:
>
> Fixes the following W=1 kernel build warning(s):
>
>  drivers/gpu/drm/amd/amdgpu/../display/dc/dce80/dce80_resource.c:527:17: 
> warning: no previous prototype for ‘dce80_aux_engine_create’ 
> [-Wmissing-prototypes]
>  drivers/gpu/drm/amd/amdgpu/../display/dc/dce80/dce80_resource.c:565:20: 
> warning: no previous prototype for ‘dce80_i2c_hw_create’ 
> [-Wmissing-prototypes]
>  drivers/gpu/drm/amd/amdgpu/../display/dc/dce80/dce80_resource.c:581:20: 
> warning: no previous prototype for ‘dce80_i2c_sw_create’ 
> [-Wmissing-prototypes]
>  drivers/gpu/drm/amd/amdgpu/../display/dc/dce80/dce80_resource.c:715:22: 
> warning: no previous prototype for ‘dce80_link_encoder_create’ 
> [-Wmissing-prototypes]
>  drivers/gpu/drm/amd/amdgpu/../display/dc/dce80/dce80_resource.c:754:22: 
> warning: no previous prototype for ‘dce80_clock_source_create’ 
> [-Wmissing-prototypes]
>  drivers/gpu/drm/amd/amdgpu/../display/dc/dce80/dce80_resource.c:778:6: 
> warning: no previous prototype for ‘dce80_clock_source_destroy’ 
> [-Wmissing-prototypes]
>  drivers/gpu/drm/amd/amdgpu/../display/dc/dce80/dce80_resource.c:868:6: 
> warning: no previous prototype for ‘dce80_validate_bandwidth’ 
> [-Wmissing-prototypes]
>  drivers/gpu/drm/amd/amdgpu/../display/dc/dce80/dce80_resource.c:913:16: 
> warning: no previous prototype for ‘dce80_validate_global’ 
> [-Wmissing-prototypes]
>
> Cc: Harry Wentland 
> Cc: Leo Li 
> Cc: Alex Deucher 
> Cc: "Christian König" 
> Cc: David Airlie 
> Cc: Daniel Vetter 
> Cc: Anthony Koo 
> Cc: amd-gfx@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org
> Signed-off-by: Lee Jones 

Applied.  Thanks!

Alex


> ---
>  .../drm/amd/display/dc/dce80/dce80_resource.c| 16 
>  1 file changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 
> b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
> index 612450f992782..725d92e40cd30 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
> @@ -526,7 +526,7 @@ static struct output_pixel_processor *dce80_opp_create(
> return >base;
>  }
>
> -struct dce_aux *dce80_aux_engine_create(
> +static struct dce_aux *dce80_aux_engine_create(
> struct dc_context *ctx,
> uint32_t inst)
>  {
> @@ -564,7 +564,7 @@ static const struct dce_i2c_mask i2c_masks = {
> I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
>  };
>
> -struct dce_i2c_hw *dce80_i2c_hw_create(
> +static struct dce_i2c_hw *dce80_i2c_hw_create(
> struct dc_context *ctx,
> uint32_t inst)
>  {
> @@ -580,7 +580,7 @@ struct dce_i2c_hw *dce80_i2c_hw_create(
> return dce_i2c_hw;
>  }
>
> -struct dce_i2c_sw *dce80_i2c_sw_create(
> +static struct dce_i2c_sw *dce80_i2c_sw_create(
> struct dc_context *ctx)
>  {
> struct dce_i2c_sw *dce_i2c_sw =
> @@ -714,7 +714,7 @@ static const struct encoder_feature_support 
> link_enc_feature = {
> .flags.bits.IS_TPS3_CAPABLE = true
>  };
>
> -struct link_encoder *dce80_link_encoder_create(
> +static struct link_encoder *dce80_link_encoder_create(
> const struct encoder_init_data *enc_init_data)
>  {
> struct dce110_link_encoder *enc110 =
> @@ -753,7 +753,7 @@ static struct panel_cntl *dce80_panel_cntl_create(const 
> struct panel_cntl_init_d
> return _cntl->base;
>  }
>
> -struct clock_source *dce80_clock_source_create(
> +static struct clock_source *dce80_clock_source_create(
> struct dc_context *ctx,
> struct dc_bios *bios,
> enum clock_source_id id,
> @@ -777,7 +777,7 @@ struct clock_source *dce80_clock_source_create(
> return NULL;
>  }
>
> -void dce80_clock_source_destroy(struct clock_source **clk_src)
> +static void dce80_clock_source_destroy(struct clock_source **clk_src)
>  {
> kfree(TO_DCE110_CLK_SRC(*clk_src));
> *clk_src = NULL;
> @@ -867,7 +867,7 @@ static void dce80_resource_destruct(struct 
> dce110_resource_pool *pool)
> }
>  }
>
> -bool dce80_validate_bandwidth(
> +static bool dce80_validate_bandwidth(
> struct dc *dc,
> struct dc_state *context,
> bool fast_validate)
> @@ -912,7 +912,7 @@ static bool dce80_validate_surface_sets(
> return true;
>  }
>
> -enum dc_status dce80_validate_global(
> +static enum dc_status dce80_validate_global(
> struct dc *dc,
> struct dc_state *context)
>  {
> --
> 2.27.0
>
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Re: [PATCH 1/1] drm/amd/display: use GFP_ATOMIC in dcn20_resource_construct

[Nirmoy]

ping.

On 3/17/21 11:52 AM, Nirmoy Das wrote:

Replace GFP_KERNEL with GFP_ATOMIC as dcn20_resource_construct()
can't sleep.

Partially fixes: https://bugzilla.kernel.org/show_bug.cgi?id=212311
as dcn20_resource_construct() also calls into SMU functions which does
mutex_lock().

Signed-off-by: Nirmoy Das 
---
  drivers/gpu/drm/amd/display/dc/dce/dce_abm.c  |  2 +-
  drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c |  6 ++---
  .../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c |  2 +-
  .../drm/amd/display/dc/dcn20/dcn20_resource.c | 26 +--
  4 files changed, 18 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
index 4e87e70237e3..874b132fe1d7 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
@@ -283,7 +283,7 @@ struct abm *dce_abm_create(
const struct dce_abm_shift *abm_shift,
const struct dce_abm_mask *abm_mask)
  {
-   struct dce_abm *abm_dce = kzalloc(sizeof(*abm_dce), GFP_KERNEL);
+   struct dce_abm *abm_dce = kzalloc(sizeof(*abm_dce), GFP_ATOMIC);
  
  	if (abm_dce == NULL) {

BREAK_TO_DEBUGGER();
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
index 4f864501e046..8cd841320ded 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
@@ -1133,7 +1133,7 @@ struct dmcu *dcn10_dmcu_create(
const struct dce_dmcu_shift *dmcu_shift,
const struct dce_dmcu_mask *dmcu_mask)
  {
-   struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_KERNEL);
+   struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_ATOMIC);
  
  	if (dmcu_dce == NULL) {

BREAK_TO_DEBUGGER();
@@ -1154,7 +1154,7 @@ struct dmcu *dcn20_dmcu_create(
const struct dce_dmcu_shift *dmcu_shift,
const struct dce_dmcu_mask *dmcu_mask)
  {
-   struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_KERNEL);
+   struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_ATOMIC);
  
  	if (dmcu_dce == NULL) {

BREAK_TO_DEBUGGER();
@@ -1175,7 +1175,7 @@ struct dmcu *dcn21_dmcu_create(
const struct dce_dmcu_shift *dmcu_shift,
const struct dce_dmcu_mask *dmcu_mask)
  {
-   struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_KERNEL);
+   struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_ATOMIC);
  
  	if (dmcu_dce == NULL) {

BREAK_TO_DEBUGGER();
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c
index 62cc2651e00c..8774406120fc 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c
@@ -112,7 +112,7 @@ struct dccg *dccg2_create(
const struct dccg_shift *dccg_shift,
const struct dccg_mask *dccg_mask)
  {
-   struct dcn_dccg *dccg_dcn = kzalloc(sizeof(*dccg_dcn), GFP_KERNEL);
+   struct dcn_dccg *dccg_dcn = kzalloc(sizeof(*dccg_dcn), GFP_ATOMIC);
struct dccg *base;
  
  	if (dccg_dcn == NULL) {

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 2307b3517821..25f8dd5db080 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -1106,7 +1106,7 @@ struct dpp *dcn20_dpp_create(
uint32_t inst)
  {
struct dcn20_dpp *dpp =
-   kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL);
+   kzalloc(sizeof(struct dcn20_dpp), GFP_ATOMIC);
  
  	if (!dpp)

return NULL;
@@ -1124,7 +1124,7 @@ struct input_pixel_processor *dcn20_ipp_create(
struct dc_context *ctx, uint32_t inst)
  {
struct dcn10_ipp *ipp =
-   kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL);
+   kzalloc(sizeof(struct dcn10_ipp), GFP_ATOMIC);
  
  	if (!ipp) {

BREAK_TO_DEBUGGER();
@@ -1141,7 +1141,7 @@ struct output_pixel_processor *dcn20_opp_create(
struct dc_context *ctx, uint32_t inst)
  {
struct dcn20_opp *opp =
-   kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
+   kzalloc(sizeof(struct dcn20_opp), GFP_ATOMIC);
  
  	if (!opp) {

BREAK_TO_DEBUGGER();
@@ -1158,7 +1158,7 @@ struct dce_aux *dcn20_aux_engine_create(
uint32_t inst)
  {
struct aux_engine_dce110 *aux_engine =
-   kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
+   kzalloc(sizeof(struct aux_engine_dce110), GFP_ATOMIC);
  
  	if (!aux_engine)

return NULL;
@@ -1196,7 +1196,7 @@ struct dce_i2c_hw *dcn20_i2c_hw_create(
uint32_t inst)
  {
struct dce_i2c_hw *dce_i2c_hw =
-   kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
+   

Re: [PATCH] drm/amdgpu/display: properly guard dc_dsc_stream_bandwidth_in_kbps

[Alex Deucher]

Ping?

On Thu, Mar 18, 2021 at 10:18 PM Alex Deucher  wrote:
>
> Move the function protoype to the right header and guard
> the call with CONFIG_DRM_AMD_DC_DCN as DSC is only available
> with DCN.
>
> Fixes: a03f6c0e26b2 ("drm/amd/display: Add changes for dsc bpp in 16ths and 
> unify bw calculations")
> Signed-off-by: Alex Deucher 
> Cc: Dillon Varone 
> Cc: Stephen Rothwell 
> ---
>  drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 ++--
>  drivers/gpu/drm/amd/display/dc/dc_dsc.h   | 2 ++
>  2 files changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
> b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> index 10e34e411e06..f9a33dc52c45 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> @@ -3498,17 +3498,17 @@ void dc_link_enable_hpd_filter(struct dc_link *link, 
> bool enable)
> }
>  }
>
> -uint32_t dc_dsc_stream_bandwidth_in_kbps(uint32_t pix_clk_100hz, uint32_t 
> bpp_x16);
> -
>  uint32_t dc_bandwidth_in_kbps_from_timing(
> const struct dc_crtc_timing *timing)
>  {
> uint32_t bits_per_channel = 0;
> uint32_t kbps;
>
> +#if defined(CONFIG_DRM_AMD_DC_DCN)
> if (timing->flags.DSC) {
> return dc_dsc_stream_bandwidth_in_kbps(timing->pix_clk_100hz, 
> timing->dsc_cfg.bits_per_pixel);
> }
> +#endif
>
> switch (timing->display_color_depth) {
> case COLOR_DEPTH_666:
> diff --git a/drivers/gpu/drm/amd/display/dc/dc_dsc.h 
> b/drivers/gpu/drm/amd/display/dc/dc_dsc.h
> index 0c5d98524536..c51d2d961b7a 100644
> --- a/drivers/gpu/drm/amd/display/dc/dc_dsc.h
> +++ b/drivers/gpu/drm/amd/display/dc/dc_dsc.h
> @@ -88,4 +88,6 @@ void dc_dsc_policy_set_max_target_bpp_limit(uint32_t limit);
>
>  void dc_dsc_policy_set_enable_dsc_when_not_needed(bool enable);
>
> +uint32_t dc_dsc_stream_bandwidth_in_kbps(uint32_t pix_clk_100hz, uint32_t 
> bpp_x16);
> +
>  #endif
> --
> 2.30.2
>
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Re: [PATCH 06/19] drm/amd/display/dc/calcs/dce_calcs: Move some large variables from the stack to the heap

[Alex Deucher]

+ Harry, Nick

On Fri, Mar 19, 2021 at 4:24 AM Lee Jones  wrote:
>
> Fixes the following W=1 kernel build warning(s):
>
>  drivers/gpu/drm/amd/amdgpu/../display/dc/calcs/dce_calcs.c: In function 
> ‘calculate_bandwidth’:
>  drivers/gpu/drm/amd/amdgpu/../display/dc/calcs/dce_calcs.c:2016:1: warning: 
> the frame size of 1216 bytes is larger than 1024 bytes [-Wframe-larger-than=]
>
> Cc: Harry Wentland 
> Cc: Leo Li 
> Cc: Alex Deucher 
> Cc: "Christian König" 
> Cc: David Airlie 
> Cc: Daniel Vetter 
> Cc: Colin Ian King 
> Cc: amd-gfx@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org
> Signed-off-by: Lee Jones 
> ---
>  .../gpu/drm/amd/display/dc/calcs/dce_calcs.c  | 32 ---
>  1 file changed, 28 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 
> b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
> index e633f8a51edb6..9d8f2505a61c2 100644
> --- a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
> +++ b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
> @@ -98,16 +98,16 @@ static void calculate_bandwidth(
> int32_t num_cursor_lines;
>
> int32_t i, j, k;
> -   struct bw_fixed yclk[3];
> -   struct bw_fixed sclk[8];
> +   struct bw_fixed *yclk;
> +   struct bw_fixed *sclk;
> bool d0_underlay_enable;
> bool d1_underlay_enable;
> bool fbc_enabled;
> bool lpt_enabled;
> enum bw_defines sclk_message;
> enum bw_defines yclk_message;
> -   enum bw_defines tiling_mode[maximum_number_of_surfaces];
> -   enum bw_defines surface_type[maximum_number_of_surfaces];
> +   enum bw_defines *tiling_mode;
> +   enum bw_defines *surface_type;
> enum bw_defines voltage;
> enum bw_defines pipe_check;
> enum bw_defines hsr_check;
> @@ -122,6 +122,22 @@ static void calculate_bandwidth(
> int32_t number_of_displays_enabled_with_margin = 0;
> int32_t number_of_aligned_displays_with_no_margin = 0;
>
> +   yclk = kcalloc(3, sizeof(*yclk), GFP_KERNEL);
> +   if (!yclk)
> +   return;
> +
> +   sclk = kcalloc(8, sizeof(*sclk), GFP_KERNEL);
> +   if (!sclk)
> +   goto free_yclk;
> +
> +   tiling_mode = kcalloc(maximum_number_of_surfaces, 
> sizeof(*tiling_mode), GFP_KERNEL);
> +   if (!tiling_mode)
> +   goto free_sclk;
> +
> +   surface_type = kcalloc(maximum_number_of_surfaces, 
> sizeof(*surface_type), GFP_KERNEL);
> +   if (!surface_type)
> +   goto free_tiling_mode;
> +


Harry or Nick can correct me if I'm wrong, but for this patch and the
next one, I think this can be called from an atomic context.

Alex

> yclk[low] = vbios->low_yclk;
> yclk[mid] = vbios->mid_yclk;
> yclk[high] = vbios->high_yclk;
> @@ -2013,6 +2029,14 @@ static void calculate_bandwidth(
> }
> }
> }
> +
> +   kfree(surface_type);
> +free_tiling_mode:
> +   kfree(tiling_mode);
> +free_yclk:
> +   kfree(yclk);
> +free_sclk:
> +   kfree(sclk);
>  }
>
>  
> /***
> --
> 2.27.0
>
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Re: [PATCH] PCI: quirks: Quirk PCI d3hot delay for AMD xhci

[Alex Deucher]

On Thu, Mar 18, 2021 at 2:36 PM Bjorn Helgaas  wrote:
>
> On Tue, Mar 16, 2021 at 03:28:51PM -0400, Alex Deucher wrote:
> > From: Marcin Bachry 
> >
> > Renoir needs a similar delay.
>
> See 
> https://lore.kernel.org/linux-pci/20210311125322.GA216@bjorn-Precision-5520/
>
> This is becoming a problem.  We shouldn't have to merge a quirk for
> every new device.  Either the devices are defective, and AMD should
> publish errata and have a plan for fixing them, or Linux is broken and
> we should fix that.
>
> There are quite a few mechanisms for controlling delays like this
> (Config Request Retry Status (PCIe r5.0, sec 2.3.1), Readiness
> Notifications (sec 6.23), ACPI _DSM for power-on delays (PCI Firmware
> Spec r3.3)), but most are for *reducing* delay, not for extending it.
>
> Linux supports CRS, but not all the others.  Maybe we're missing
> something we should support?
>
> How do you deal with these issues for Windows?  If it works on Windows
> without quirks, we should be able to make it work on Linux as well.

It works fine in windows.  Unfortunately, it's hard to tell what
windows does exactly since MS supplies the USB driver in that case.
Also, the extended delays are not necessary on our reference
platforms, these seem to only be an issue on some OEM platforms.  I
did confirm with the windows team that we use d3hot for USB on our
current platforms due to bios bugs, but this is fixed on upcoming
platforms.  Still digging for any more details.

>
> > Signed-off-by: Marcin Bachry 
> > Signed-off-by: Alex Deucher 
> > ---
> >  drivers/pci/quirks.c | 3 +++
> >  1 file changed, 3 insertions(+)
> >
> > diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
> > index 653660e3ba9e..36e5ec670fae 100644
> > --- a/drivers/pci/quirks.c
> > +++ b/drivers/pci/quirks.c
> > @@ -1904,6 +1904,9 @@ static void quirk_ryzen_xhci_d3hot(struct pci_dev 
> > *dev)
> >  }
> >  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e0, quirk_ryzen_xhci_d3hot);
> >  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e1, quirk_ryzen_xhci_d3hot);
> > +/* Renoir XHCI requires longer delay when transitioning from D0 to
> > + * D3hot */
>
> No need for "me too" comments that add no additional information.

Will drop that.

Alex

>
> > +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1639, quirk_ryzen_xhci_d3hot);
> >
> >  #ifdef CONFIG_X86_IO_APIC
> >  static int dmi_disable_ioapicreroute(const struct dmi_system_id *d)
> > --
> > 2.30.2
> >
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Re: [RESEND 00/53] Rid GPU from W=1 warnings

[Daniel Vetter]

On Fri, Mar 19, 2021 at 08:24:07AM +, Lee Jones wrote:
> On Thu, 18 Mar 2021, Daniel Vetter wrote:
> 
> > On Wed, Mar 17, 2021 at 9:32 PM Daniel Vetter  wrote:
> > >
> > > On Wed, Mar 17, 2021 at 9:17 AM Lee Jones  wrote:
> > > >
> > > > On Thu, 11 Mar 2021, Lee Jones wrote:
> > > >
> > > > > On Thu, 11 Mar 2021, Daniel Vetter wrote:
> > > > >
> > > > > > On Mon, Mar 08, 2021 at 09:19:32AM +, Lee Jones wrote:
> > > > > > > On Fri, 05 Mar 2021, Roland Scheidegger wrote:
> > > > > > >
> > > > > > > > The vmwgfx ones look all good to me, so for
> > > > > > > > 23-53: Reviewed-by: Roland Scheidegger 
> > > > > > > > That said, they were already signed off by Zack, so not sure 
> > > > > > > > what
> > > > > > > > happened here.
> > > > > > >
> > > > > > > Yes, they were accepted at one point, then dropped without a 
> > > > > > > reason.
> > > > > > >
> > > > > > > Since I rebased onto the latest -next, I had to pluck them back 
> > > > > > > out of
> > > > > > > a previous one.
> > > > > >
> > > > > > They should show up in linux-next again. We merge patches for next 
> > > > > > merge
> > > > > > window even during the current merge window, but need to make sure 
> > > > > > they
> > > > > > don't pollute linux-next. Occasionally the cut off is wrong so 
> > > > > > patches
> > > > > > show up, and then get pulled again.
> > > > > >
> > > > > > Unfortunately especially the 5.12 merge cycle was very wobbly due 
> > > > > > to some
> > > > > > confusion here. But your patches should all be in linux-next again 
> > > > > > (they
> > > > > > are queued up for 5.13 in drm-misc-next, I checked that).
> > > > > >
> > > > > > Sorry for the confusion here.
> > > > >
> > > > > Oh, I see.  Well so long as they don't get dropped, I'll be happy.
> > > > >
> > > > > Thanks for the explanation Daniel
> > > >
> > > > After rebasing today, all of my GPU patches have remained.  Would
> > > > someone be kind enough to check that everything is still in order
> > > > please?
> > >
> > > It's still broken somehow. I've kiced Maxime and Maarten again,
> > > they're also on this thread.
> > 
> > You're patches have made it into drm-next meanwhile, so they should
> > show up in linux-next through that tree at least. Except if that one
> > also has some trouble.
> 
> Thanks for letting me know.
> 
> I see some patches made it back in, others didn't.
> 
> I'll resend the stragglers - bear with.

The vmwgfx ones should all be back, the others I guess just werent ever
applied. I'll vacuum them all up if you resend. Apologies for the wobbly
ride.
-Daniel
-- 
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Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [PATCH] drm/ttm: stop warning on TT shrinker failure

[Daniel Vetter]

On Fri, Mar 19, 2021 at 03:08:57PM +0100, Christian König wrote:
> Don't print a warning when we fail to allocate a page for swapping things out.
> 
> Also rely on memalloc_nofs_save/memalloc_nofs_restore instead of GFP_NOFS.

Uh this part doesn't make sense. Especially since you only do it for the
debugfs file, not in general. Which means you've just completely broken
the shrinker.

If this is just to paper over the seq_printf doing the wrong allocations,
then just move that out from under the fs_reclaim_acquire/release part.

__GFP_NOWARN should be there indeed I think.
-Daniel

> 
> Signed-off-by: Christian König 
> ---
>  drivers/gpu/drm/ttm/ttm_tt.c | 5 -
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c
> index 2f0833c98d2c..86fa3e82dacc 100644
> --- a/drivers/gpu/drm/ttm/ttm_tt.c
> +++ b/drivers/gpu/drm/ttm/ttm_tt.c
> @@ -369,7 +369,7 @@ static unsigned long ttm_tt_shrinker_scan(struct shrinker 
> *shrink,
>   };
>   int ret;
>  
> - ret = ttm_bo_swapout(, GFP_NOFS);
> + ret = ttm_bo_swapout(, GFP_KERNEL | __GFP_NOWARN);
>   return ret < 0 ? SHRINK_EMPTY : ret;
>  }
>  
> @@ -389,10 +389,13 @@ static unsigned long ttm_tt_shrinker_count(struct 
> shrinker *shrink,
>  static int ttm_tt_debugfs_shrink_show(struct seq_file *m, void *data)
>  {
>   struct shrink_control sc = { .gfp_mask = GFP_KERNEL };
> + unsigned int flags;
>  
>   fs_reclaim_acquire(GFP_KERNEL);
> + flags = memalloc_nofs_save();
>   seq_printf(m, "%lu/%lu\n", ttm_tt_shrinker_count(_shrinker, ),
>  ttm_tt_shrinker_scan(_shrinker, ));
> + memalloc_nofs_restore(flags);
>   fs_reclaim_release(GFP_KERNEL);
>  
>   return 0;
> -- 
> 2.25.1
> 
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-- 
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Re: [PATCH] drm/ttm: stop warning on TT shrinker failure

[Deucher, Alexander]

[AMD Official Use Only - Internal Distribution Only]

+ Leo

From: amd-gfx  on behalf of Christian 
König 
Sent: Friday, March 19, 2021 10:08 AM
To: Liu, Leo ; amd-gfx@lists.freedesktop.org 
; dri-de...@lists.freedesktop.org 

Subject: [PATCH] drm/ttm: stop warning on TT shrinker failure

Don't print a warning when we fail to allocate a page for swapping things out.

Also rely on memalloc_nofs_save/memalloc_nofs_restore instead of GFP_NOFS.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/ttm/ttm_tt.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c
index 2f0833c98d2c..86fa3e82dacc 100644
--- a/drivers/gpu/drm/ttm/ttm_tt.c
+++ b/drivers/gpu/drm/ttm/ttm_tt.c
@@ -369,7 +369,7 @@ static unsigned long ttm_tt_shrinker_scan(struct shrinker 
*shrink,
 };
 int ret;

-   ret = ttm_bo_swapout(, GFP_NOFS);
+   ret = ttm_bo_swapout(, GFP_KERNEL | __GFP_NOWARN);
 return ret < 0 ? SHRINK_EMPTY : ret;
 }

@@ -389,10 +389,13 @@ static unsigned long ttm_tt_shrinker_count(struct 
shrinker *shrink,
 static int ttm_tt_debugfs_shrink_show(struct seq_file *m, void *data)
 {
 struct shrink_control sc = { .gfp_mask = GFP_KERNEL };
+   unsigned int flags;

 fs_reclaim_acquire(GFP_KERNEL);
+   flags = memalloc_nofs_save();
 seq_printf(m, "%lu/%lu\n", ttm_tt_shrinker_count(_shrinker, ),
ttm_tt_shrinker_scan(_shrinker, ));
+   memalloc_nofs_restore(flags);
 fs_reclaim_release(GFP_KERNEL);

 return 0;
--
2.25.1

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Re: [PATCH 2/2] drm/amdgpu: disable runpm if other reset method not runpm capable is chosen

[Deucher, Alexander]

[AMD Public Use]

Yeah, the reset method is independent of whether we can use BACO for runtime 
PM.  We can use BACO for power saving and use mode1 for reset.  Is there some 
issue I'm missing?

Alex


From: amd-gfx  on behalf of Lazar, Lijo 

Sent: Friday, March 19, 2021 7:27 AM
To: Quan, Evan ; amd-gfx@lists.freedesktop.org 

Cc: Quan, Evan 
Subject: RE: [PATCH 2/2] drm/amdgpu: disable runpm if other reset method not 
runpm capable is chosen

[AMD Public Use]



-Original Message-
From: amd-gfx  On Behalf Of Evan Quan
Sent: Friday, March 19, 2021 2:42 PM
To: amd-gfx@lists.freedesktop.org
Cc: Quan, Evan 
Subject: [PATCH 2/2] drm/amdgpu: disable runpm if other reset method not runpm 
capable is chosen

Otherwise, the runpm will be always enabled on a BACO capable target even the 
reset method was forced as like mode1.

Change-Id: If6bf55c533e91470c9c83383788466161608f68d
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +-  
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 ++
 drivers/gpu/drm/amd/amdgpu/cik.c| 2 +-
 drivers/gpu/drm/amd/amdgpu/nv.c | 2 +-
 drivers/gpu/drm/amd/amdgpu/si.c | 2 +-
 drivers/gpu/drm/amd/amdgpu/soc15.c  | 2 +-
 drivers/gpu/drm/amd/amdgpu/vi.c | 2 +-
 8 files changed, 9 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 963ecfd84347..be12dd2550b8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -589,6 +589,7 @@ struct amdgpu_allowed_register_entry {  };

 enum amd_reset_method {
+   AMD_RESET_METHOD_AUTO = -1,
 AMD_RESET_METHOD_LEGACY = 0,
 AMD_RESET_METHOD_MODE0,
 AMD_RESET_METHOD_MODE1,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 6a06234dbcad..78e5445b28b5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -168,7 +168,7 @@ int amdgpu_noretry = -1;  int amdgpu_force_asic_type = -1;  
int amdgpu_tmz = -1; /* auto */  uint amdgpu_freesync_vid_mode; -int 
amdgpu_reset_method = -1; /* auto */
+int amdgpu_reset_method = AMD_RESET_METHOD_AUTO; /* auto */
 int amdgpu_num_kcq = -1;

 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work); 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 8844f650b17f..49068ad698a6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -168,6 +168,8 @@ int amdgpu_driver_load_kms(struct amdgpu_device *adev, 
unsigned long flags)
 adev->runpm = true;
 dev_info(adev->dev, "Using BOCO for runtime pm\n");
 } else if (amdgpu_device_supports_baco(dev) &&
+  (amdgpu_reset_method == AMD_RESET_METHOD_AUTO ||
+   amdgpu_reset_method == AMD_RESET_METHOD_BACO) &&

< > Why to link runpm suspend method with reset method?

Thanks,
Lijo
(amdgpu_runtime_pm != 0)) {
 switch (adev->asic_type) {
 case CHIP_VEGA20:
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index c0fcc41ee574..e671871f4d28 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -1395,7 +1395,7 @@ cik_asic_reset_method(struct amdgpu_device *adev)
 amdgpu_reset_method == AMD_RESET_METHOD_BACO)
 return amdgpu_reset_method;

-   if (amdgpu_reset_method != -1)
+   if (amdgpu_reset_method != AMD_RESET_METHOD_AUTO)
 dev_warn(adev->dev, "Specified reset:%d isn't supported, using 
AUTO instead.\n",
   amdgpu_reset_method);

diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c 
index 2670ae00c2e5..1e751d415f15 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -529,7 +529,7 @@ nv_asic_reset_method(struct amdgpu_device *adev)
 amdgpu_reset_method == AMD_RESET_METHOD_PCI)
 return amdgpu_reset_method;

-   if (amdgpu_reset_method != -1)
+   if (amdgpu_reset_method != AMD_RESET_METHOD_AUTO)
 dev_warn(adev->dev, "Specified reset method:%d isn't 
supported, using AUTO instead.\n",
   amdgpu_reset_method);

diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c 
index 7cbc2bb03bc6..b9db761a7cc5 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -1420,7 +1420,7 @@ si_asic_reset_method(struct amdgpu_device *adev)
 if (amdgpu_reset_method == AMD_RESET_METHOD_PCI)
 return amdgpu_reset_method;
 else if (amdgpu_reset_method != AMD_RESET_METHOD_LEGACY &&
-amdgpu_reset_method != -1)
+

Re: [PATCH 2/2] drm/amd/pm: label these APIs used internally as static

[Deucher, Alexander]

[AMD Official Use Only - Internal Distribution Only]

Series is:
Reviewed-by: Alex Deucher 

From: amd-gfx  on behalf of Evan Quan 

Sent: Friday, March 19, 2021 2:53 AM
To: amd-gfx@lists.freedesktop.org 
Cc: Quan, Evan 
Subject: [PATCH 2/2] drm/amd/pm: label these APIs used internally as static

Also drop unnecessary header file and declarations.

Change-Id: I877b48c32c599534798e14e271c3e700b0d6ebf6
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c  |   1 -
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c|   1 -
 drivers/gpu/drm/amd/amdgpu/nv.c   |   1 -
 drivers/gpu/drm/amd/amdgpu/soc15.c|   1 -
 drivers/gpu/drm/amd/pm/amdgpu_pm.c|  10 +-
 drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h   |  61 +
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 159 +-
 7 files changed, 98 insertions(+), 136 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
index 33f748e5bbfc..1429c6897d3f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
@@ -24,7 +24,6 @@
 #include 
 #include "amdgpu.h"
 #include "amdgpu_xgmi.h"
-#include "amdgpu_smu.h"
 #include "amdgpu_ras.h"
 #include "soc15.h"
 #include "df/df_3_6_offset.h"
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index d780b9c0926f..9a65ff871a58 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -29,7 +29,6 @@
 #include "amdgpu.h"
 #include "amdgpu_gfx.h"
 #include "amdgpu_psp.h"
-#include "amdgpu_smu.h"
 #include "nv.h"
 #include "nvd.h"

diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index a31ef68ee2ab..e9cc3201054f 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -34,7 +34,6 @@
 #include "amdgpu_vce.h"
 #include "amdgpu_ucode.h"
 #include "amdgpu_psp.h"
-#include "amdgpu_smu.h"
 #include "atom.h"
 #include "amd_pcie.h"

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c 
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 3808402cd964..c354a11e2fd9 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -76,7 +76,6 @@
 #include "smuio_v13_0.h"
 #include "dce_virtual.h"
 #include "mxgpu_ai.h"
-#include "amdgpu_smu.h"
 #include "amdgpu_ras.h"
 #include "amdgpu_xgmi.h"
 #include 
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c 
b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index 74fa5fe89970..10c761b11ff7 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -27,7 +27,6 @@
 #include "amdgpu_drv.h"
 #include "amdgpu_pm.h"
 #include "amdgpu_dpm.h"
-#include "amdgpu_smu.h"
 #include "atom.h"
 #include 
 #include 
@@ -930,14 +929,7 @@ static ssize_t amdgpu_set_pp_features(struct device *dev,
 return ret;
 }

-   if (is_support_sw_smu(adev)) {
-   ret = smu_sys_set_pp_feature_mask(>smu, featuremask);
-   if (ret) {
-   pm_runtime_mark_last_busy(ddev->dev);
-   pm_runtime_put_autosuspend(ddev->dev);
-   return -EINVAL;
-   }
-   } else if (adev->powerplay.pp_funcs->set_ppfeature_status) {
+   if (adev->powerplay.pp_funcs->set_ppfeature_status) {
 ret = amdgpu_dpm_set_ppfeature_status(adev, featuremask);
 if (ret) {
 pm_runtime_mark_last_busy(ddev->dev);
diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h 
b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
index ca5a0a436cad..517f333fbc4b 100644
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
@@ -1281,50 +1281,22 @@ int smu_load_microcode(struct smu_context *smu);

 int smu_check_fw_status(struct smu_context *smu);

-int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled);
-
-int smu_set_fan_speed_rpm(void *handle, uint32_t speed);
-
 int smu_get_power_limit(struct smu_context *smu,
 uint32_t *limit,
 enum smu_ppt_limit_level limit_level);

-int smu_set_power_limit(void *handle, uint32_t limit);
-int smu_print_ppclk_levels(void *handle, enum pp_clock_type type, char *buf);
-
-int smu_od_edit_dpm_table(void *handle,
- enum PP_OD_DPM_TABLE_COMMAND type,
- long *input, uint32_t size);
-
-int smu_read_sensor(void *handle, int sensor, void *data, int *size);
-int smu_get_power_profile_mode(void *handle, char *buf);
-int smu_set_power_profile_mode(void *handle, long *param, uint32_t param_size);
-u32 smu_get_fan_control_mode(void *handle);
-int smu_set_fan_control_mode(struct smu_context *smu, int value);
-void smu_pp_set_fan_control_mode(void *handle, u32 value);
-int smu_get_fan_speed_percent(void *handle, u32 *speed);
-int smu_set_fan_speed_percent(void *handle, u32 speed);
-int smu_get_fan_speed_rpm(void 

Re: [PATCH] drm/amd/display: Set AMDGPU_DM_DEFAULT_MIN_BACKLIGHT to 0

[Harry Wentland]

On 2021-03-19 10:22 a.m., Alex Deucher wrote:

On Fri, Mar 19, 2021 at 3:23 AM Evan Benn  wrote:


AMDGPU_DM_DEFAULT_MIN_BACKLIGHT was set to the value of 12
to ensure no display backlight will flicker at low user brightness
settings. However this value is quite bright, so for devices that do not
implement the ACPI ATIF
ATIF_FUNCTION_QUERY_BRIGHTNESS_TRANSFER_CHARACTERISTICS
functionality the user cannot set the brightness to a low level even if
the display would support such a low PWM.

This ATIF feature is not implemented on for example AMD grunt chromebooks.

Signed-off-by: Evan Benn 

---
I could not find a justification for the reason for the value. It has
caused some noticable regression for users: 
https://bugzilla.kernel.org/show_bug.cgi?id=203439>>>
Maybe this can be either user controlled or userspace configured, but
preventing users from turning their backlight dim seems wrong.


My understanding is that some panels flicker if you set the min to a
value too low.  This was a safe minimum if the platform didn't specify
it's own safe minimum.  I think we'd just be trading one bug for
another (flickering vs not dim enough).  Maybe a whitelist or
blacklist would be a better solution?



Yeah, this is a NACK from me as-is for the reasons Alex described.

I agree a whitelist approach might be best.

Is this fix perhaps for OLED panels? If so we could use a different 
min-value for OLED panels that don't do PWM, but use 12 for everything else.


Harry


Alex




Also reviewed here: 
https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/2748377>>>
  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 573cf17262da..0129bd69b94e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -3151,7 +3151,7 @@ static int amdgpu_dm_mode_config_init(struct 
amdgpu_device *adev)
 return 0;
  }

-#define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
+#define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 0
  #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
  #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50

--
2.31.0.291.g576ba9dcdaf-goog

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Re: [PATCH 12/30] drm/bridge/analogix/anx6345: Cleanup on errors in anx6345_bridge_attach()

[Robert Foss]

Hey Lyude,

Thanks for the patch, it looks good to me.

Reviewed-by: Robert Foss 

On Fri, 19 Feb 2021 at 22:58, Lyude Paul  wrote:
>
> Another drive-by fix I found when fixing DP AUX adapter across the kernel
> tree - make sure we don't leak resources (and by proxy-AUX adapters) on
> failures in anx6345_bridge_attach() by unrolling on errors.
>
> Signed-off-by: Lyude Paul 
> ---
>  drivers/gpu/drm/bridge/analogix/analogix-anx6345.c | 11 ---
>  1 file changed, 8 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix-anx6345.c 
> b/drivers/gpu/drm/bridge/analogix/analogix-anx6345.c
> index 6258f16da0e8..aa6cda458eb9 100644
> --- a/drivers/gpu/drm/bridge/analogix/analogix-anx6345.c
> +++ b/drivers/gpu/drm/bridge/analogix/analogix-anx6345.c
> @@ -550,7 +550,7 @@ static int anx6345_bridge_attach(struct drm_bridge 
> *bridge,
>  DRM_MODE_CONNECTOR_eDP);
> if (err) {
> DRM_ERROR("Failed to initialize connector: %d\n", err);
> -   return err;
> +   goto aux_unregister;
> }
>
> drm_connector_helper_add(>connector,
> @@ -562,16 +562,21 @@ static int anx6345_bridge_attach(struct drm_bridge 
> *bridge,
>bridge->encoder);
> if (err) {
> DRM_ERROR("Failed to link up connector to encoder: %d\n", 
> err);
> -   return err;
> +   goto connector_cleanup;
> }
>
> err = drm_connector_register(>connector);
> if (err) {
> DRM_ERROR("Failed to register connector: %d\n", err);
> -   return err;
> +   goto connector_cleanup;
> }
>
> return 0;
> +connector_cleanup:
> +   drm_connector_cleanup(>connector);
> +aux_unregister:
> +   drm_dp_aux_unregister(>aux);
> +   return err;
>  }
>
>  static void anx6345_bridge_detach(struct drm_bridge *bridge)
> --
> 2.29.2
>
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Re: [PATCH 09/30] drm/bridge/analogix/anx78xx: Cleanup on error in anx78xx_bridge_attach()

[Robert Foss]

Hey Lyude,

Thanks for the patch, it looks good to me.

Reviewed-by: Robert Foss 

On Fri, 19 Feb 2021 at 22:56, Lyude Paul  wrote:
>
> Just another issue I noticed while correcting usages of
> drm_dp_aux_init()/drm_dp_aux_register() around the tree. If any of the
> steps in anx78xx_bridge_attach() fail, we end up leaking resources. So,
> let's fix that (and fix leaking a DP AUX adapter in the process) by
> unrolling on errors.
>
> Signed-off-by: Lyude Paul 
> ---
>  drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c | 11 ---
>  1 file changed, 8 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c 
> b/drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c
> index 338dd8531d4b..f20558618220 100644
> --- a/drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c
> +++ b/drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c
> @@ -918,7 +918,7 @@ static int anx78xx_bridge_attach(struct drm_bridge 
> *bridge,
>  DRM_MODE_CONNECTOR_DisplayPort);
> if (err) {
> DRM_ERROR("Failed to initialize connector: %d\n", err);
> -   return err;
> +   goto aux_unregister;
> }
>
> drm_connector_helper_add(>connector,
> @@ -930,16 +930,21 @@ static int anx78xx_bridge_attach(struct drm_bridge 
> *bridge,
>bridge->encoder);
> if (err) {
> DRM_ERROR("Failed to link up connector to encoder: %d\n", 
> err);
> -   return err;
> +   goto connector_cleanup;
> }
>
> err = drm_connector_register(>connector);
> if (err) {
> DRM_ERROR("Failed to register connector: %d\n", err);
> -   return err;
> +   goto connector_cleanup;
> }
>
> return 0;
> +connector_cleanup:
> +   drm_connector_cleanup(>connector);
> +aux_unregister:
> +   drm_dp_aux_unregister(>aux);
> +   return err;
>  }
>
>  static void anx78xx_bridge_detach(struct drm_bridge *bridge)
> --
> 2.29.2
>
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Re: [PATCH 10/30] drm/bridge/analogix/anx6345: Add missing drm_dp_aux_unregister() call

[Robert Foss]

Hey Lyude,

Thanks for the patch, it looks good to me.

Reviewed-by: Robert Foss 

On Fri, 19 Feb 2021 at 22:58, Lyude Paul  wrote:
>
> Another driver I found that seems to forget to unregister it's DP AUX
> device. Let's fix this by adding anx6345_bridge_detach().
>
> Signed-off-by: Lyude Paul 
> ---
>  drivers/gpu/drm/bridge/analogix/analogix-anx6345.c | 6 ++
>  1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix-anx6345.c 
> b/drivers/gpu/drm/bridge/analogix/analogix-anx6345.c
> index d9164fab044d..8e016ba7c54a 100644
> --- a/drivers/gpu/drm/bridge/analogix/analogix-anx6345.c
> +++ b/drivers/gpu/drm/bridge/analogix/analogix-anx6345.c
> @@ -574,6 +574,11 @@ static int anx6345_bridge_attach(struct drm_bridge 
> *bridge,
> return 0;
>  }
>
> +static void anx6345_bridge_detach(struct drm_bridge *bridge)
> +{
> +   drm_dp_aux_unregister(_to_anx6345(bridge)->aux);
> +}
> +
>  static enum drm_mode_status
>  anx6345_bridge_mode_valid(struct drm_bridge *bridge,
>   const struct drm_display_info *info,
> @@ -624,6 +629,7 @@ static void anx6345_bridge_enable(struct drm_bridge 
> *bridge)
>
>  static const struct drm_bridge_funcs anx6345_bridge_funcs = {
> .attach = anx6345_bridge_attach,
> +   .detach = anx6345_bridge_detach,
> .mode_valid = anx6345_bridge_mode_valid,
> .disable = anx6345_bridge_disable,
> .enable = anx6345_bridge_enable,
> --
> 2.29.2
>
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Re: [PATCH 13/30] drm/bridge/analogix/dp_core: Unregister DP AUX channel on error in analogix_dp_probe()

[Robert Foss]

Hey Lyude,

Thanks for the patch, it looks good to me.

Reviewed-by: Robert Foss 

On Fri, 19 Feb 2021 at 22:58, Lyude Paul  wrote:
>
> Just another drive-by fix I noticed while going through the tree to cleanup
> DP aux adapter registration - make sure we unregister the DP AUX dev if
> analogix_dp_probe() fails.
>
> Signed-off-by: Lyude Paul 
> ---
>  drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c 
> b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> index aa1bb86293fd..f115233b1cb9 100644
> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> @@ -1782,6 +1782,7 @@ int analogix_dp_bind(struct analogix_dp_device *dp, 
> struct drm_device *drm_dev)
>
>  err_disable_pm_runtime:
> pm_runtime_disable(dp->dev);
> +   drm_dp_aux_unregister(>aux);
>
> return ret;
>  }
> --
> 2.29.2
>
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Re: [PATCH 08/30] drm/bridge/analogix/anx78xx: Setup encoder before registering connector

[Robert Foss]

Hey Lyude,

Thanks for the patch, it looks good to me.

Reviewed-by: Robert Foss 

On Fri, 19 Feb 2021 at 22:56, Lyude Paul  wrote:
>
> Since encoder mappings for connectors are exposed to userspace, we should
> be attaching the encoder before exposing the connector to userspace. Just a
> drive-by fix for an issue I noticed while fixing up usages of
> drm_dp_aux_init()/drm_dp_aux_register() across the tree.
>
> Signed-off-by: Lyude Paul 
> ---
>  drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c | 12 ++--
>  1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c 
> b/drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c
> index ec4607dc01eb..338dd8531d4b 100644
> --- a/drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c
> +++ b/drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c
> @@ -924,12 +924,6 @@ static int anx78xx_bridge_attach(struct drm_bridge 
> *bridge,
> drm_connector_helper_add(>connector,
>  _connector_helper_funcs);
>
> -   err = drm_connector_register(>connector);
> -   if (err) {
> -   DRM_ERROR("Failed to register connector: %d\n", err);
> -   return err;
> -   }
> -
> anx78xx->connector.polled = DRM_CONNECTOR_POLL_HPD;
>
> err = drm_connector_attach_encoder(>connector,
> @@ -939,6 +933,12 @@ static int anx78xx_bridge_attach(struct drm_bridge 
> *bridge,
> return err;
> }
>
> +   err = drm_connector_register(>connector);
> +   if (err) {
> +   DRM_ERROR("Failed to register connector: %d\n", err);
> +   return err;
> +   }
> +
> return 0;
>  }
>
> --
> 2.29.2
>
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Re: [PATCH 11/30] drm/bridge/analogix/anx6345: Don't link encoder until after connector registration

[Robert Foss]

Hey Lyude,

Thanks for the patch, it looks good to me.

Reviewed-by: Robert Foss 

On Fri, 19 Feb 2021 at 22:58, Lyude Paul  wrote:
>
> Another case of linking an encoder to a connector after the connector's
> been registered. The proper place to do this is before connector
> registration, so let's fix that.
>
> Signed-off-by: Lyude Paul 
> ---
>  drivers/gpu/drm/bridge/analogix/analogix-anx6345.c | 12 ++--
>  1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix-anx6345.c 
> b/drivers/gpu/drm/bridge/analogix/analogix-anx6345.c
> index 8e016ba7c54a..6258f16da0e8 100644
> --- a/drivers/gpu/drm/bridge/analogix/analogix-anx6345.c
> +++ b/drivers/gpu/drm/bridge/analogix/analogix-anx6345.c
> @@ -556,12 +556,6 @@ static int anx6345_bridge_attach(struct drm_bridge 
> *bridge,
> drm_connector_helper_add(>connector,
>  _connector_helper_funcs);
>
> -   err = drm_connector_register(>connector);
> -   if (err) {
> -   DRM_ERROR("Failed to register connector: %d\n", err);
> -   return err;
> -   }
> -
> anx6345->connector.polled = DRM_CONNECTOR_POLL_HPD;
>
> err = drm_connector_attach_encoder(>connector,
> @@ -571,6 +565,12 @@ static int anx6345_bridge_attach(struct drm_bridge 
> *bridge,
> return err;
> }
>
> +   err = drm_connector_register(>connector);
> +   if (err) {
> +   DRM_ERROR("Failed to register connector: %d\n", err);
> +   return err;
> +   }
> +
> return 0;
>  }
>
> --
> 2.29.2
>
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Re: [PATCH 07/30] drm/bridge/analogix/anx78xx: Add missing drm_dp_aux_unregister() call

[Robert Foss]

Hey Lyude,

Thanks for the patch, it looks good to me.

Reviewed-by: Robert Foss 

On Fri, 19 Feb 2021 at 22:56, Lyude Paul  wrote:
>
> Surprisingly, this bridge actually registers it's AUX adapter at the
> correct time already. Nice job! However, it does forget to actually
> unregister the AUX adapter, so let's add a bridge function to handle that.
>
> Signed-off-by: Lyude Paul 
> ---
>  drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c | 6 ++
>  1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c 
> b/drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c
> index 81debd02c169..ec4607dc01eb 100644
> --- a/drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c
> +++ b/drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c
> @@ -942,6 +942,11 @@ static int anx78xx_bridge_attach(struct drm_bridge 
> *bridge,
> return 0;
>  }
>
> +static void anx78xx_bridge_detach(struct drm_bridge *bridge)
> +{
> +   drm_dp_aux_unregister(_to_anx78xx(bridge)->aux);
> +}
> +
>  static enum drm_mode_status
>  anx78xx_bridge_mode_valid(struct drm_bridge *bridge,
>   const struct drm_display_info *info,
> @@ -1013,6 +1018,7 @@ static void anx78xx_bridge_enable(struct drm_bridge 
> *bridge)
>
>  static const struct drm_bridge_funcs anx78xx_bridge_funcs = {
> .attach = anx78xx_bridge_attach,
> +   .detach = anx78xx_bridge_detach,
> .mode_valid = anx78xx_bridge_mode_valid,
> .disable = anx78xx_bridge_disable,
> .mode_set = anx78xx_bridge_mode_set,
> --
> 2.29.2
>
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Re: [PATCH 04/30] drm/bridge/tc358767: Don't register DP AUX channel until bridge is attached

[Robert Foss]

Hey Lyude,

This patch looks good to me.

Reviewed-by: Robert Foss 

On Fri, 19 Feb 2021 at 22:56, Lyude Paul  wrote:
>
> Since this is a bridge, we don't start out with a respective DRM device.
> Likewise this means we don't have a connector, which also means that we
> should be following drm_dp_aux_register()'s documentation advice and not
> call drm_dp_aux_register() until we have a matching connector. Instead,
> call drm_dp_aux_init() in tc_probe() and wait until tc_bridge_attach() to
> register our AUX channel. We also add tc_bridge_detach() to handle
> unregistering the AUX adapter once the bridge has been disconnected.
>
> Signed-off-by: Lyude Paul 
> ---
>  drivers/gpu/drm/bridge/tc358767.c | 20 +++-
>  1 file changed, 15 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/tc358767.c 
> b/drivers/gpu/drm/bridge/tc358767.c
> index 34a3e4e9f717..da89922721ed 100644
> --- a/drivers/gpu/drm/bridge/tc358767.c
> +++ b/drivers/gpu/drm/bridge/tc358767.c
> @@ -1414,11 +1414,15 @@ static int tc_bridge_attach(struct drm_bridge *bridge,
> if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
> return 0;
>
> +   ret = drm_dp_aux_register(>aux);
> +   if (ret < 0)
> +   return ret;
> +
> /* Create DP/eDP connector */
> drm_connector_helper_add(>connector, _connector_helper_funcs);
> ret = drm_connector_init(drm, >connector, _connector_funcs, 
> tc->bridge.type);
> if (ret)
> -   return ret;
> +   goto aux_unregister;
>
> /* Don't poll if don't have HPD connected */
> if (tc->hpd_pin >= 0) {
> @@ -1438,10 +1442,19 @@ static int tc_bridge_attach(struct drm_bridge *bridge,
> drm_connector_attach_encoder(>connector, tc->bridge.encoder);
>
> return 0;
> +aux_unregister:
> +   drm_dp_aux_unregister(>aux);
> +   return ret;
> +}
> +
> +static void tc_bridge_detach(struct drm_bridge *bridge)
> +{
> +   drm_dp_aux_unregister(_to_tc(bridge)->aux);
>  }
>
>  static const struct drm_bridge_funcs tc_bridge_funcs = {
> .attach = tc_bridge_attach,
> +   .detach = tc_bridge_detach,
> .mode_valid = tc_mode_valid,
> .mode_set = tc_bridge_mode_set,
> .enable = tc_bridge_enable,
> @@ -1680,9 +1693,7 @@ static int tc_probe(struct i2c_client *client, const 
> struct i2c_device_id *id)
> tc->aux.name = "TC358767 AUX i2c adapter";
> tc->aux.dev = tc->dev;
> tc->aux.transfer = tc_aux_transfer;
> -   ret = drm_dp_aux_register(>aux);
> -   if (ret)
> -   return ret;
> +   drm_dp_aux_init(>aux);
>
> tc->bridge.funcs = _bridge_funcs;
> if (tc->hpd_pin >= 0)
> @@ -1702,7 +1713,6 @@ static int tc_remove(struct i2c_client *client)
> struct tc_data *tc = i2c_get_clientdata(client);
>
> drm_bridge_remove(>bridge);
> -   drm_dp_aux_unregister(>aux);
>
> return 0;
>  }
> --
> 2.29.2
>
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[PATCH 1/3] drm/connector: Create a helper to attach the hdr_output_metadata property

[Maxime Ripard]

All the drivers that implement HDR output call pretty much the same
function to initialise the hdr_output_metadata property, and while the
creation of that property is in a helper, every driver uses the same
code to attach it.

Provide a helper for it as well

Signed-off-by: Maxime Ripard 
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  4 +---
 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c |  3 +--
 drivers/gpu/drm/drm_connector.c   | 21 +++
 drivers/gpu/drm/i915/display/intel_hdmi.c |  3 +--
 include/drm/drm_connector.h   |  1 +
 5 files changed, 25 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 22124f76d0b5..06908a3cee0f 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -7017,9 +7017,7 @@ void amdgpu_dm_connector_init_helper(struct 
amdgpu_display_manager *dm,
if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
connector_type == DRM_MODE_CONNECTOR_eDP) {
-   drm_object_attach_property(
-   >base.base,
-   dm->ddev->mode_config.hdr_output_metadata_property, 0);
+   
drm_connector_attach_hdr_output_metadata_property(>base);
 
if (!aconnector->mst_port)

drm_connector_attach_vrr_capable_property(>base);
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
index dda4fa9a1a08..f24bbb840dbf 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
@@ -2492,8 +2492,7 @@ static int dw_hdmi_connector_create(struct dw_hdmi *hdmi)
drm_connector_attach_max_bpc_property(connector, 8, 16);
 
if (hdmi->version >= 0x200a && hdmi->plat_data->use_drm_infoframe)
-   drm_object_attach_property(>base,
-   
connector->dev->mode_config.hdr_output_metadata_property, 0);
+   drm_connector_attach_hdr_output_metadata_property(connector);
 
drm_connector_attach_encoder(connector, hdmi->bridge.encoder);
 
diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index 98b6ec45ef96..e25248e23e18 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -2149,6 +2149,27 @@ int drm_connector_attach_max_bpc_property(struct 
drm_connector *connector,
 }
 EXPORT_SYMBOL(drm_connector_attach_max_bpc_property);
 
+/**
+ * drm_connector_attach_hdr_output_metadata_property - attach 
"HDR_OUTPUT_METADA" property
+ * @connector: connector to attach the property on.
+ *
+ * This is used to allow the userspace to send HDR Metadata to the
+ * driver.
+ *
+ * Returns:
+ * Zero on success, negative errno on failure.
+ */
+int drm_connector_attach_hdr_output_metadata_property(struct drm_connector 
*connector)
+{
+   struct drm_device *dev = connector->dev;
+   struct drm_property *prop = 
dev->mode_config.hdr_output_metadata_property;
+
+   drm_object_attach_property(>base, prop, 0);
+
+   return 0;
+}
+EXPORT_SYMBOL(drm_connector_attach_hdr_output_metadata_property);
+
 /**
  * drm_connector_set_vrr_capable_property - sets the variable refresh rate
  * capable property for a connector
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c 
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index c5959590562b..52c051efb7b7 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2958,8 +2958,7 @@ intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, 
struct drm_connector *c
drm_connector_attach_content_type_property(connector);
 
if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
-   drm_object_attach_property(>base,
-   
connector->dev->mode_config.hdr_output_metadata_property, 0);
+   drm_connector_attach_hdr_output_metadata_property(connector);
 
if (!HAS_GMCH(dev_priv))
drm_connector_attach_max_bpc_property(connector, 8, 12);
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index 1922b278ffad..32172dab8427 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -1671,6 +1671,7 @@ int drm_connector_attach_scaling_mode_property(struct 
drm_connector *connector,
   u32 scaling_mode_mask);
 int drm_connector_attach_vrr_capable_property(
struct drm_connector *connector);
+int drm_connector_attach_hdr_output_metadata_property(struct drm_connector 
*connector);
 int drm_mode_create_aspect_ratio_property(struct drm_device *dev);
 int drm_mode_create_hdmi_colorspace_property(struct drm_connector *connector);
 int drm_mode_create_dp_colorspace_property(struct drm_connector *connector);
-- 

Re: [PATCH 30/30] drm/dp_mst: Convert drm_dp_mst_topology.c to drm_err()/drm_dbg*()

[Robert Foss]

Hey Lyude,

Thanks for the patch

On Fri, 19 Feb 2021 at 23:03, Lyude Paul  wrote:
>
> And finally, convert all of the code in drm_dp_mst_topology.c over to using
> drm_err() and drm_dbg*(). Note that this refactor would have been a lot
> more complicated to have tried writing a coccinelle script for, so this
> whole thing was done by hand.
>
> Signed-off-by: Lyude Paul 
> ---
>  drivers/gpu/drm/drm_dp_mst_topology.c | 369 +-
>  1 file changed, 187 insertions(+), 182 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c 
> b/drivers/gpu/drm/drm_dp_mst_topology.c
> index fb66df39e0bb..f66232954689 100644
> --- a/drivers/gpu/drm/drm_dp_mst_topology.c
> +++ b/drivers/gpu/drm/drm_dp_mst_topology.c
> @@ -286,7 +286,8 @@ static void drm_dp_encode_sideband_msg_hdr(struct 
> drm_dp_sideband_msg_hdr *hdr,
> *len = idx;
>  }
>
> -static bool drm_dp_decode_sideband_msg_hdr(struct drm_dp_sideband_msg_hdr 
> *hdr,
> +static bool drm_dp_decode_sideband_msg_hdr(const struct 
> drm_dp_mst_topology_mgr *mgr,
> +  struct drm_dp_sideband_msg_hdr 
> *hdr,
>u8 *buf, int buflen, u8 *hdrlen)
>  {
> u8 crc4;
> @@ -303,7 +304,7 @@ static bool drm_dp_decode_sideband_msg_hdr(struct 
> drm_dp_sideband_msg_hdr *hdr,
> crc4 = drm_dp_msg_header_crc4(buf, (len * 2) - 1);
>
> if ((crc4 & 0xf) != (buf[len - 1] & 0xf)) {
> -   DRM_DEBUG_KMS("crc4 mismatch 0x%x 0x%x\n", crc4, buf[len - 
> 1]);
> +   drm_dbg_kms(mgr->dev, "crc4 mismatch 0x%x 0x%x\n", crc4, 
> buf[len - 1]);
> return false;
> }
>
> @@ -789,7 +790,8 @@ static bool drm_dp_sideband_append_payload(struct 
> drm_dp_sideband_msg_rx *msg,
> return true;
>  }
>
> -static bool drm_dp_sideband_parse_link_address(struct drm_dp_sideband_msg_rx 
> *raw,
> +static bool drm_dp_sideband_parse_link_address(const struct 
> drm_dp_mst_topology_mgr *mgr,
> +  struct drm_dp_sideband_msg_rx 
> *raw,
>struct 
> drm_dp_sideband_msg_reply_body *repmsg)
>  {
> int idx = 1;
> @@ -1014,7 +1016,8 @@ drm_dp_sideband_parse_query_stream_enc_status(
> return true;
>  }
>
> -static bool drm_dp_sideband_parse_reply(struct drm_dp_sideband_msg_rx *raw,
> +static bool drm_dp_sideband_parse_reply(const struct drm_dp_mst_topology_mgr 
> *mgr,
> +   struct drm_dp_sideband_msg_rx *raw,
> struct drm_dp_sideband_msg_reply_body 
> *msg)
>  {
> memset(msg, 0, sizeof(*msg));
> @@ -1030,7 +1033,7 @@ static bool drm_dp_sideband_parse_reply(struct 
> drm_dp_sideband_msg_rx *raw,
>
> switch (msg->req_type) {
> case DP_LINK_ADDRESS:
> -   return drm_dp_sideband_parse_link_address(raw, msg);
> +   return drm_dp_sideband_parse_link_address(mgr, raw, msg);
> case DP_QUERY_PAYLOAD:
> return drm_dp_sideband_parse_query_payload_ack(raw, msg);
> case DP_REMOTE_DPCD_READ:
> @@ -1053,14 +1056,16 @@ static bool drm_dp_sideband_parse_reply(struct 
> drm_dp_sideband_msg_rx *raw,
> case DP_QUERY_STREAM_ENC_STATUS:
> return drm_dp_sideband_parse_query_stream_enc_status(raw, 
> msg);
> default:
> -   DRM_ERROR("Got unknown reply 0x%02x (%s)\n", msg->req_type,
> - drm_dp_mst_req_type_str(msg->req_type));
> +   drm_err(mgr->dev, "Got unknown reply 0x%02x (%s)\n",
> +   msg->req_type, 
> drm_dp_mst_req_type_str(msg->req_type));
> return false;
> }
>  }
>
> -static bool drm_dp_sideband_parse_connection_status_notify(struct 
> drm_dp_sideband_msg_rx *raw,
> -  struct 
> drm_dp_sideband_msg_req_body *msg)
> +static bool
> +drm_dp_sideband_parse_connection_status_notify(const struct 
> drm_dp_mst_topology_mgr *mgr,
> +  struct drm_dp_sideband_msg_rx 
> *raw,
> +  struct 
> drm_dp_sideband_msg_req_body *msg)
>  {
> int idx = 1;
>
> @@ -1082,12 +1087,14 @@ static bool 
> drm_dp_sideband_parse_connection_status_notify(struct drm_dp_sideban
> idx++;
> return true;
>  fail_len:
> -   DRM_DEBUG_KMS("connection status reply parse length fail %d %d\n", 
> idx, raw->curlen);
> +   drm_dbg_kms(mgr->dev, "connection status reply parse length fail %d 
> %d\n",
> +   idx, raw->curlen);
> return false;
>  }
>
> -static bool drm_dp_sideband_parse_resource_status_notify(struct 
> drm_dp_sideband_msg_rx *raw,
> -  struct 
> drm_dp_sideband_msg_req_body *msg)
> +static bool drm_dp_sideband_parse_resource_status_notify(const 

Re: [RESEND 00/53] Rid GPU from W=1 warnings

[Lee Jones]

On Thu, 18 Mar 2021, Daniel Vetter wrote:

> On Wed, Mar 17, 2021 at 9:32 PM Daniel Vetter  wrote:
> >
> > On Wed, Mar 17, 2021 at 9:17 AM Lee Jones  wrote:
> > >
> > > On Thu, 11 Mar 2021, Lee Jones wrote:
> > >
> > > > On Thu, 11 Mar 2021, Daniel Vetter wrote:
> > > >
> > > > > On Mon, Mar 08, 2021 at 09:19:32AM +, Lee Jones wrote:
> > > > > > On Fri, 05 Mar 2021, Roland Scheidegger wrote:
> > > > > >
> > > > > > > The vmwgfx ones look all good to me, so for
> > > > > > > 23-53: Reviewed-by: Roland Scheidegger 
> > > > > > > That said, they were already signed off by Zack, so not sure what
> > > > > > > happened here.
> > > > > >
> > > > > > Yes, they were accepted at one point, then dropped without a reason.
> > > > > >
> > > > > > Since I rebased onto the latest -next, I had to pluck them back out 
> > > > > > of
> > > > > > a previous one.
> > > > >
> > > > > They should show up in linux-next again. We merge patches for next 
> > > > > merge
> > > > > window even during the current merge window, but need to make sure 
> > > > > they
> > > > > don't pollute linux-next. Occasionally the cut off is wrong so patches
> > > > > show up, and then get pulled again.
> > > > >
> > > > > Unfortunately especially the 5.12 merge cycle was very wobbly due to 
> > > > > some
> > > > > confusion here. But your patches should all be in linux-next again 
> > > > > (they
> > > > > are queued up for 5.13 in drm-misc-next, I checked that).
> > > > >
> > > > > Sorry for the confusion here.
> > > >
> > > > Oh, I see.  Well so long as they don't get dropped, I'll be happy.
> > > >
> > > > Thanks for the explanation Daniel
> > >
> > > After rebasing today, all of my GPU patches have remained.  Would
> > > someone be kind enough to check that everything is still in order
> > > please?
> >
> > It's still broken somehow. I've kiced Maxime and Maarten again,
> > they're also on this thread.
> 
> You're patches have made it into drm-next meanwhile, so they should
> show up in linux-next through that tree at least. Except if that one
> also has some trouble.

Thanks for letting me know.

I see some patches made it back in, others didn't.

I'll resend the stragglers - bear with.

-- 
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Senior Technical Lead - Developer Services
Linaro.org │ Open source software for Arm SoCs
Follow Linaro: Facebook | Twitter | Blog
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[RESEND 00/19] Rid GPU from W=1 warnings

[Lee Jones]

MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This is a resend of the remaining patches.

All of these patches have been sent before.

Lee Jones (19):
  drm/nouveau/nvkm/subdev/bios/init: Demote obvious abuse of kernel-doc
  drm/nouveau/dispnv50/disp: Remove unused variable 'ret'
  drm/msm/dp/dp_display: Remove unused variable 'hpd'
  include: drm: drm_atomic: Make use of 'new_plane_state'
  drm/nouveau/nvkm/subdev/volt/gk20a: Demote non-conformant kernel-doc
headers
  drm/amd/display/dc/calcs/dce_calcs: Move some large variables from the
stack to the heap
  drm/amd/display/dc/calcs/dce_calcs: Remove some large variables from
the stack
  drm/amd/display/dc/dce80/dce80_resource: Make local functions static
  drm/nouveau/nvkm/engine/gr/gf100: Demote non-conformant kernel-doc
header
  drm/nouveau/nouveau_bo: Remove unused variables 'dev'
  drm/nouveau/nouveau_display: Remove set but unused variable 'width'
  drm/nouveau/dispnv04/crtc: Demote non-conforming kernel-doc headers
  drm/nouveau/dispnv50/disp: Remove unused variable 'ret' from function
returning void
  drm/nouveau/dispnv50/headc57d: Make local function 'headc57d_olut'
static
  drm/nouveau/nv50_display: Remove superfluous prototype for local
static functions
  drm/nouveau/dispnv50/disp: Include header containing our prototypes
  drm/nouveau/nouveau_ioc32: File headers are not good candidates for
kernel-doc
  drm/nouveau/nouveau_svm: Remove unused variable 'ret' from void
function
  drm/nouveau/nouveau_ioc32: Demote kernel-doc abuse to standard comment
block

 .../gpu/drm/amd/display/dc/calcs/dce_calcs.c  | 1154 +
 .../drm/amd/display/dc/dce80/dce80_resource.c |   16 +-
 drivers/gpu/drm/msm/dp/dp_display.c   |3 -
 drivers/gpu/drm/nouveau/dispnv04/crtc.c   |4 +-
 drivers/gpu/drm/nouveau/dispnv50/disp.c   |   10 +-
 drivers/gpu/drm/nouveau/dispnv50/headc57d.c   |2 +-
 drivers/gpu/drm/nouveau/nouveau_bo.c  |4 -
 drivers/gpu/drm/nouveau/nouveau_display.c |8 +-
 drivers/gpu/drm/nouveau/nouveau_ioc32.c   |4 +-
 drivers/gpu/drm/nouveau/nouveau_svm.c |5 +-
 drivers/gpu/drm/nouveau/nv50_display.h|3 -
 .../gpu/drm/nouveau/nvkm/engine/gr/gf100.c|2 +-
 .../gpu/drm/nouveau/nvkm/subdev/bios/init.c   |  204 +--
 .../gpu/drm/nouveau/nvkm/subdev/volt/gk20a.c  |4 +-
 include/drm/drm_atomic.h  |3 +-
 15 files changed, 692 insertions(+), 734 deletions(-)

Cc: Alex Deucher 
Cc: amd-gfx@lists.freedesktop.org
Cc: Anthony Koo 
Cc: Ben Skeggs 
Cc: "Christian König" 
Cc: Colin Ian King 
Cc: Daniel Vetter 
Cc: David Airlie 
Cc: dri-de...@lists.freedesktop.org
Cc: freedr...@lists.freedesktop.org
Cc: Harry Wentland 
Cc: Jeremy Kolb 
Cc: Kuogee Hsieh 
Cc: Leo Li 
Cc: linaro-mm-...@lists.linaro.org
Cc: linux-arm-...@vger.kernel.org
Cc: linux-me...@vger.kernel.org
Cc: Lyude Paul 
Cc: Maarten Lankhorst 
Cc: Maxime Ripard 
Cc: nouv...@lists.freedesktop.org
Cc: Rob Clark 
Cc: Sean Paul 
Cc: Sumit Semwal 
Cc: Thomas Zimmermann 
-- 
2.27.0

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Re: [PATCH 18/30] drm/print: Fixup DRM_DEBUG_KMS_RATELIMITED()

[Robert Foss]

Hey Lyude,

Thanks for the patch,

On Fri, 19 Feb 2021 at 22:59, Lyude Paul  wrote:
>
> Since we're about to move drm_dp_helper.c over to drm_dbg_*(), we'll want
> to make sure that we can also add ratelimited versions of these macros in
> order to retain some of the previous debugging output behavior we had.
>
> However, as I was preparing to do this I noticed that the current
> rate limited macros we have are kind of bogus. It looks like when I wrote
> these, I didn't notice that we'd always be calling __ratelimit() even if
> the debugging message we'd be printing would normally be filtered out due
> to the relevant DRM debugging category being disabled.
>
> So, let's fix this by making sure to check drm_debug_enabled() in our
> ratelimited macros before calling __ratelimit(), and start using
> drm_dev_printk() in order to print debugging messages since that will save
> us from doing a redundant drm_debug_enabled() check. And while we're at it,
> let's move the code for this into another macro that we can reuse for
> defining new ratelimited DRM debug macros more easily.
>
> Signed-off-by: Lyude Paul 
> ---
>  include/drm/drm_print.h | 20 
>  1 file changed, 12 insertions(+), 8 deletions(-)
>
> diff --git a/include/drm/drm_print.h b/include/drm/drm_print.h
> index f32d179e139d..3a0c3fe4d292 100644
> --- a/include/drm/drm_print.h
> +++ b/include/drm/drm_print.h
> @@ -524,16 +524,20 @@ void __drm_err(const char *format, ...);
>  #define DRM_DEBUG_DP(fmt, ...) \
> __drm_dbg(DRM_UT_DP, fmt, ## __VA_ARGS__)
>
> -
> -#define DRM_DEBUG_KMS_RATELIMITED(fmt, ...)\
> -({ \
> -   static DEFINE_RATELIMIT_STATE(_rs,  \
> - DEFAULT_RATELIMIT_INTERVAL,   \
> - DEFAULT_RATELIMIT_BURST); \
> -   if (__ratelimit(&_rs))  \
> -   drm_dev_dbg(NULL, DRM_UT_KMS, fmt, ##__VA_ARGS__);  \
> +#define __DRM_DEFINE_DBG_RATELIMITED(category, drm, fmt, ...)
> \
> +({   
> \
> +   static DEFINE_RATELIMIT_STATE(rs_, DEFAULT_RATELIMIT_INTERVAL, 
> DEFAULT_RATELIMIT_BURST); \
> +   const struct drm_device *drm_ = (drm);
>\
> + 
> \
> +   if (drm_debug_enabled(DRM_UT_ ## category) && __ratelimit(_))  
>\
> +   drm_dev_printk(drm_ ? drm_->dev : NULL, KERN_DEBUG, fmt, ## 
> __VA_ARGS__);\
>  })

checkpatch --strict is unhappy about the tabs/spaces in this patch


ERROR: code indent should use tabs where possible
#48: FILE: include/drm/drm_print.h:531:
+
   \$

WARNING: please, no spaces at the start of a line
#48: FILE: include/drm/drm_print.h:531:
+
   \$


>
> +#define drm_dbg_kms_ratelimited(drm, fmt, ...) \
> +   __DRM_DEFINE_DBG_RATELIMITED(KMS, drm, fmt, ## __VA_ARGS__)
> +
> +#define DRM_DEBUG_KMS_RATELIMITED(fmt, ...) drm_dbg_kms_ratelimited(NULL, 
> fmt, ## __VA_ARGS__)
> +
>  /*
>   * struct drm_device based WARNs
>   *
> --
> 2.29.2
>
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[PATCH 06/19] drm/amd/display/dc/calcs/dce_calcs: Move some large variables from the stack to the heap

[Lee Jones]

Fixes the following W=1 kernel build warning(s):

 drivers/gpu/drm/amd/amdgpu/../display/dc/calcs/dce_calcs.c: In function 
‘calculate_bandwidth’:
 drivers/gpu/drm/amd/amdgpu/../display/dc/calcs/dce_calcs.c:2016:1: warning: 
the frame size of 1216 bytes is larger than 1024 bytes [-Wframe-larger-than=]

Cc: Harry Wentland 
Cc: Leo Li 
Cc: Alex Deucher 
Cc: "Christian König" 
Cc: David Airlie 
Cc: Daniel Vetter 
Cc: Colin Ian King 
Cc: amd-gfx@lists.freedesktop.org
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Lee Jones 
---
 .../gpu/drm/amd/display/dc/calcs/dce_calcs.c  | 32 ---
 1 file changed, 28 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 
b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
index e633f8a51edb6..9d8f2505a61c2 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
@@ -98,16 +98,16 @@ static void calculate_bandwidth(
int32_t num_cursor_lines;
 
int32_t i, j, k;
-   struct bw_fixed yclk[3];
-   struct bw_fixed sclk[8];
+   struct bw_fixed *yclk;
+   struct bw_fixed *sclk;
bool d0_underlay_enable;
bool d1_underlay_enable;
bool fbc_enabled;
bool lpt_enabled;
enum bw_defines sclk_message;
enum bw_defines yclk_message;
-   enum bw_defines tiling_mode[maximum_number_of_surfaces];
-   enum bw_defines surface_type[maximum_number_of_surfaces];
+   enum bw_defines *tiling_mode;
+   enum bw_defines *surface_type;
enum bw_defines voltage;
enum bw_defines pipe_check;
enum bw_defines hsr_check;
@@ -122,6 +122,22 @@ static void calculate_bandwidth(
int32_t number_of_displays_enabled_with_margin = 0;
int32_t number_of_aligned_displays_with_no_margin = 0;
 
+   yclk = kcalloc(3, sizeof(*yclk), GFP_KERNEL);
+   if (!yclk)
+   return;
+
+   sclk = kcalloc(8, sizeof(*sclk), GFP_KERNEL);
+   if (!sclk)
+   goto free_yclk;
+
+   tiling_mode = kcalloc(maximum_number_of_surfaces, sizeof(*tiling_mode), 
GFP_KERNEL);
+   if (!tiling_mode)
+   goto free_sclk;
+
+   surface_type = kcalloc(maximum_number_of_surfaces, 
sizeof(*surface_type), GFP_KERNEL);
+   if (!surface_type)
+   goto free_tiling_mode;
+
yclk[low] = vbios->low_yclk;
yclk[mid] = vbios->mid_yclk;
yclk[high] = vbios->high_yclk;
@@ -2013,6 +2029,14 @@ static void calculate_bandwidth(
}
}
}
+
+   kfree(surface_type);
+free_tiling_mode:
+   kfree(tiling_mode);
+free_yclk:
+   kfree(yclk);
+free_sclk:
+   kfree(sclk);
 }
 
 
/***
-- 
2.27.0

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[PATCH 08/19] drm/amd/display/dc/dce80/dce80_resource: Make local functions static

[Lee Jones]

Fixes the following W=1 kernel build warning(s):

 drivers/gpu/drm/amd/amdgpu/../display/dc/dce80/dce80_resource.c:527:17: 
warning: no previous prototype for ‘dce80_aux_engine_create’ 
[-Wmissing-prototypes]
 drivers/gpu/drm/amd/amdgpu/../display/dc/dce80/dce80_resource.c:565:20: 
warning: no previous prototype for ‘dce80_i2c_hw_create’ [-Wmissing-prototypes]
 drivers/gpu/drm/amd/amdgpu/../display/dc/dce80/dce80_resource.c:581:20: 
warning: no previous prototype for ‘dce80_i2c_sw_create’ [-Wmissing-prototypes]
 drivers/gpu/drm/amd/amdgpu/../display/dc/dce80/dce80_resource.c:715:22: 
warning: no previous prototype for ‘dce80_link_encoder_create’ 
[-Wmissing-prototypes]
 drivers/gpu/drm/amd/amdgpu/../display/dc/dce80/dce80_resource.c:754:22: 
warning: no previous prototype for ‘dce80_clock_source_create’ 
[-Wmissing-prototypes]
 drivers/gpu/drm/amd/amdgpu/../display/dc/dce80/dce80_resource.c:778:6: 
warning: no previous prototype for ‘dce80_clock_source_destroy’ 
[-Wmissing-prototypes]
 drivers/gpu/drm/amd/amdgpu/../display/dc/dce80/dce80_resource.c:868:6: 
warning: no previous prototype for ‘dce80_validate_bandwidth’ 
[-Wmissing-prototypes]
 drivers/gpu/drm/amd/amdgpu/../display/dc/dce80/dce80_resource.c:913:16: 
warning: no previous prototype for ‘dce80_validate_global’ 
[-Wmissing-prototypes]

Cc: Harry Wentland 
Cc: Leo Li 
Cc: Alex Deucher 
Cc: "Christian König" 
Cc: David Airlie 
Cc: Daniel Vetter 
Cc: Anthony Koo 
Cc: amd-gfx@lists.freedesktop.org
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Lee Jones 
---
 .../drm/amd/display/dc/dce80/dce80_resource.c| 16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 
b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
index 612450f992782..725d92e40cd30 100644
--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
@@ -526,7 +526,7 @@ static struct output_pixel_processor *dce80_opp_create(
return >base;
 }
 
-struct dce_aux *dce80_aux_engine_create(
+static struct dce_aux *dce80_aux_engine_create(
struct dc_context *ctx,
uint32_t inst)
 {
@@ -564,7 +564,7 @@ static const struct dce_i2c_mask i2c_masks = {
I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
 };
 
-struct dce_i2c_hw *dce80_i2c_hw_create(
+static struct dce_i2c_hw *dce80_i2c_hw_create(
struct dc_context *ctx,
uint32_t inst)
 {
@@ -580,7 +580,7 @@ struct dce_i2c_hw *dce80_i2c_hw_create(
return dce_i2c_hw;
 }
 
-struct dce_i2c_sw *dce80_i2c_sw_create(
+static struct dce_i2c_sw *dce80_i2c_sw_create(
struct dc_context *ctx)
 {
struct dce_i2c_sw *dce_i2c_sw =
@@ -714,7 +714,7 @@ static const struct encoder_feature_support 
link_enc_feature = {
.flags.bits.IS_TPS3_CAPABLE = true
 };
 
-struct link_encoder *dce80_link_encoder_create(
+static struct link_encoder *dce80_link_encoder_create(
const struct encoder_init_data *enc_init_data)
 {
struct dce110_link_encoder *enc110 =
@@ -753,7 +753,7 @@ static struct panel_cntl *dce80_panel_cntl_create(const 
struct panel_cntl_init_d
return _cntl->base;
 }
 
-struct clock_source *dce80_clock_source_create(
+static struct clock_source *dce80_clock_source_create(
struct dc_context *ctx,
struct dc_bios *bios,
enum clock_source_id id,
@@ -777,7 +777,7 @@ struct clock_source *dce80_clock_source_create(
return NULL;
 }
 
-void dce80_clock_source_destroy(struct clock_source **clk_src)
+static void dce80_clock_source_destroy(struct clock_source **clk_src)
 {
kfree(TO_DCE110_CLK_SRC(*clk_src));
*clk_src = NULL;
@@ -867,7 +867,7 @@ static void dce80_resource_destruct(struct 
dce110_resource_pool *pool)
}
 }
 
-bool dce80_validate_bandwidth(
+static bool dce80_validate_bandwidth(
struct dc *dc,
struct dc_state *context,
bool fast_validate)
@@ -912,7 +912,7 @@ static bool dce80_validate_surface_sets(
return true;
 }
 
-enum dc_status dce80_validate_global(
+static enum dc_status dce80_validate_global(
struct dc *dc,
struct dc_state *context)
 {
-- 
2.27.0

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 2/3] drm/connector: Add helper to compare HDR metadata

[Maxime Ripard]

All the drivers that support the HDR metadata property have a similar
function to compare the metadata from one connector state to the next,
and force a mode change if they differ.

All these functions run pretty much the same code, so let's turn it into
an helper that can be shared across those drivers.

Signed-off-by: Maxime Ripard 
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 21 +-
 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 17 +--
 drivers/gpu/drm/drm_connector.c   | 28 +++
 drivers/gpu/drm/i915/display/intel_atomic.c   | 13 +
 include/drm/drm_connector.h   |  2 ++
 5 files changed, 33 insertions(+), 48 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 06908a3cee0f..4eb5201e566a 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -5924,25 +5924,6 @@ static int fill_hdr_info_packet(const struct 
drm_connector_state *state,
return 0;
 }
 
-static bool
-is_hdr_metadata_different(const struct drm_connector_state *old_state,
- const struct drm_connector_state *new_state)
-{
-   struct drm_property_blob *old_blob = old_state->hdr_output_metadata;
-   struct drm_property_blob *new_blob = new_state->hdr_output_metadata;
-
-   if (old_blob != new_blob) {
-   if (old_blob && new_blob &&
-   old_blob->length == new_blob->length)
-   return memcmp(old_blob->data, new_blob->data,
- old_blob->length);
-
-   return true;
-   }
-
-   return false;
-}
-
 static int
 amdgpu_dm_connector_atomic_check(struct drm_connector *conn,
 struct drm_atomic_state *state)
@@ -5960,7 +5941,7 @@ amdgpu_dm_connector_atomic_check(struct drm_connector 
*conn,
if (!crtc)
return 0;
 
-   if (is_hdr_metadata_different(old_con_state, new_con_state)) {
+   if (!drm_connector_atomic_hdr_metadata_equal(old_con_state, 
new_con_state)) {
struct dc_info_packet hdr_infopacket;
 
ret = fill_hdr_info_packet(new_con_state, _infopacket);
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
index f24bbb840dbf..f871e33c2fc9 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
@@ -2395,21 +2395,6 @@ static int dw_hdmi_connector_get_modes(struct 
drm_connector *connector)
return ret;
 }
 
-static bool hdr_metadata_equal(const struct drm_connector_state *old_state,
-  const struct drm_connector_state *new_state)
-{
-   struct drm_property_blob *old_blob = old_state->hdr_output_metadata;
-   struct drm_property_blob *new_blob = new_state->hdr_output_metadata;
-
-   if (!old_blob || !new_blob)
-   return old_blob == new_blob;
-
-   if (old_blob->length != new_blob->length)
-   return false;
-
-   return !memcmp(old_blob->data, new_blob->data, old_blob->length);
-}
-
 static int dw_hdmi_connector_atomic_check(struct drm_connector *connector,
  struct drm_atomic_state *state)
 {
@@ -2423,7 +2408,7 @@ static int dw_hdmi_connector_atomic_check(struct 
drm_connector *connector,
if (!crtc)
return 0;
 
-   if (!hdr_metadata_equal(old_state, new_state)) {
+   if (!drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) {
crtc_state = drm_atomic_get_crtc_state(state, crtc);
if (IS_ERR(crtc_state))
return PTR_ERR(crtc_state);
diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index e25248e23e18..d781a3a1e9bf 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -2170,6 +2170,34 @@ int 
drm_connector_attach_hdr_output_metadata_property(struct drm_connector *conn
 }
 EXPORT_SYMBOL(drm_connector_attach_hdr_output_metadata_property);
 
+/**
+ * drm_connector_atomic_hdr_metadata_equal - checks if the hdr metadata changed
+ * @old_state: old connector state to compare
+ * @new_state: new connector state to compare
+ *
+ * This is used by HDR-enabled drivers to test whether the HDR metadata
+ * have changed between two different connector state (and thus probably
+ * requires a full blown mode change).
+ *
+ * Returns:
+ * True if the metadata are equal, False otherwise
+ */
+bool drm_connector_atomic_hdr_metadata_equal(struct drm_connector_state 
*old_state,
+struct drm_connector_state 
*new_state)
+{
+   struct drm_property_blob *old_blob = old_state->hdr_output_metadata;
+   struct drm_property_blob *new_blob = new_state->hdr_output_metadata;
+
+   if (!old_blob || !new_blob)

[PATCH 07/19] drm/amd/display/dc/calcs/dce_calcs: Remove some large variables from the stack

[Lee Jones]

Fixes the following W=1 kernel build warning(s):

 drivers/gpu/drm/amd/amdgpu/../display/dc/calcs/dce_calcs.c: In function 
‘bw_calcs_init’:
 drivers/gpu/drm/amd/amdgpu/../display/dc/calcs/dce_calcs.c:2726:1: warning: 
the frame size of 1336 bytes is larger than 1024 bytes [-Wframe-larger-than=]

Cc: Harry Wentland 
Cc: Leo Li 
Cc: Alex Deucher 
Cc: "Christian König" 
Cc: David Airlie 
Cc: Daniel Vetter 
Cc: amd-gfx@lists.freedesktop.org
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Lee Jones 
---
 .../gpu/drm/amd/display/dc/calcs/dce_calcs.c  | 1122 +
 1 file changed, 567 insertions(+), 555 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 
b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
index 9d8f2505a61c2..556ecfabc8d2a 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
@@ -2046,707 +2046,719 @@ void bw_calcs_init(struct bw_calcs_dceip *bw_dceip,
struct bw_calcs_vbios *bw_vbios,
struct hw_asic_id asic_id)
 {
-   struct bw_calcs_dceip dceip = { 0 };
-   struct bw_calcs_vbios vbios = { 0 };
+   struct bw_calcs_dceip *dceip;
+   struct bw_calcs_vbios *vbios;
 
enum bw_calcs_version version = bw_calcs_version_from_asic_id(asic_id);
 
-   dceip.version = version;
+   dceip = kzalloc(sizeof(dceip), GFP_KERNEL);
+   if (!dceip)
+   return;
+
+   vbios = kzalloc(sizeof(vbios), GFP_KERNEL);
+   if (!vbios) {
+   kfree(dceip);
+   return;
+   }
+
+   dceip->version = version;
 
switch (version) {
case BW_CALCS_VERSION_CARRIZO:
-   vbios.memory_type = bw_def_gddr5;
-   vbios.dram_channel_width_in_bits = 64;
-   vbios.number_of_dram_channels = asic_id.vram_width / 
vbios.dram_channel_width_in_bits;
-   vbios.number_of_dram_banks = 8;
-   vbios.high_yclk = bw_int_to_fixed(1600);
-   vbios.mid_yclk = bw_int_to_fixed(1600);
-   vbios.low_yclk = bw_frc_to_fixed(6, 100);
-   vbios.low_sclk = bw_int_to_fixed(200);
-   vbios.mid1_sclk = bw_int_to_fixed(300);
-   vbios.mid2_sclk = bw_int_to_fixed(300);
-   vbios.mid3_sclk = bw_int_to_fixed(300);
-   vbios.mid4_sclk = bw_int_to_fixed(300);
-   vbios.mid5_sclk = bw_int_to_fixed(300);
-   vbios.mid6_sclk = bw_int_to_fixed(300);
-   vbios.high_sclk = bw_frc_to_fixed(62609, 100);
-   vbios.low_voltage_max_dispclk = bw_int_to_fixed(352);
-   vbios.mid_voltage_max_dispclk = bw_int_to_fixed(467);
-   vbios.high_voltage_max_dispclk = bw_int_to_fixed(643);
-   vbios.low_voltage_max_phyclk = bw_int_to_fixed(540);
-   vbios.mid_voltage_max_phyclk = bw_int_to_fixed(810);
-   vbios.high_voltage_max_phyclk = bw_int_to_fixed(810);
-   vbios.data_return_bus_width = bw_int_to_fixed(32);
-   vbios.trc = bw_int_to_fixed(50);
-   vbios.dmifmc_urgent_latency = bw_int_to_fixed(4);
-   vbios.stutter_self_refresh_exit_latency = bw_frc_to_fixed(153, 
10);
-   vbios.stutter_self_refresh_entry_latency = bw_int_to_fixed(0);
-   vbios.nbp_state_change_latency = bw_frc_to_fixed(19649, 1000);
-   vbios.mcifwrmc_urgent_latency = bw_int_to_fixed(10);
-   vbios.scatter_gather_enable = true;
-   vbios.down_spread_percentage = bw_frc_to_fixed(5, 10);
-   vbios.cursor_width = 32;
-   vbios.average_compression_rate = 4;
-   vbios.number_of_request_slots_gmc_reserves_for_dmif_per_channel 
= 256;
-   vbios.blackout_duration = bw_int_to_fixed(0); /* us */
-   vbios.maximum_blackout_recovery_time = bw_int_to_fixed(0);
-
-   
dceip.max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation
 = 100;
-   
dceip.max_average_percent_of_ideal_drambw_display_can_use_in_normal_system_operation
 = 100;
-   dceip.percent_of_ideal_port_bw_received_after_urgent_latency = 
100;
-   dceip.large_cursor = false;
-   dceip.dmif_request_buffer_size = bw_int_to_fixed(768);
-   dceip.dmif_pipe_en_fbc_chunk_tracker = false;
-   dceip.cursor_max_outstanding_group_num = 1;
-   dceip.lines_interleaved_into_lb = 2;
-   dceip.chunk_width = 256;
-   dceip.number_of_graphics_pipes = 3;
-   dceip.number_of_underlay_pipes = 1;
-   dceip.low_power_tiling_mode = 0;
-   dceip.display_write_back_supported = false;
-   dceip.argb_compression_support = false;
-   dceip.underlay_vscaler_efficiency6_bit_per_component =
+   vbios->memory_type = bw_def_gddr5;
+   

[PATCH 3/3] drm/vc4: Add HDR metadata property to the VC5 HDMI connectors

[Maxime Ripard]

From: Dave Stevenson 

Now that we can export deeper colour depths, add in the signalling
for HDR metadata.

Signed-off-by: Dave Stevenson 
Signed-off-by: Maxime Ripard 
---
 drivers/gpu/drm/vc4/vc4_hdmi.c | 53 ++
 drivers/gpu/drm/vc4/vc4_hdmi.h |  3 ++
 2 files changed, 56 insertions(+)

diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index eee9751009c2..c8846cf9dd24 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -214,6 +214,31 @@ static int vc4_hdmi_connector_get_modes(struct 
drm_connector *connector)
return ret;
 }
 
+static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector,
+ struct drm_atomic_state *state)
+{
+   struct drm_connector_state *old_state =
+   drm_atomic_get_old_connector_state(state, connector);
+   struct drm_connector_state *new_state =
+   drm_atomic_get_new_connector_state(state, connector);
+   struct drm_crtc *crtc = new_state->crtc;
+
+   if (!crtc)
+   return 0;
+
+   if (!drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) {
+   struct drm_crtc_state *crtc_state;
+
+   crtc_state = drm_atomic_get_crtc_state(state, crtc);
+   if (IS_ERR(crtc_state))
+   return PTR_ERR(crtc_state);
+
+   crtc_state->mode_changed = true;
+   }
+
+   return 0;
+}
+
 static void vc4_hdmi_connector_reset(struct drm_connector *connector)
 {
struct vc4_hdmi_connector_state *old_state =
@@ -263,6 +288,7 @@ static const struct drm_connector_funcs 
vc4_hdmi_connector_funcs = {
 
 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs 
= {
.get_modes = vc4_hdmi_connector_get_modes,
+   .atomic_check = vc4_hdmi_connector_atomic_check,
 };
 
 static int vc4_hdmi_connector_init(struct drm_device *dev,
@@ -299,6 +325,9 @@ static int vc4_hdmi_connector_init(struct drm_device *dev,
connector->interlace_allowed = 1;
connector->doublescan_allowed = 0;
 
+   if (vc4_hdmi->variant->supports_hdr)
+   drm_connector_attach_hdr_output_metadata_property(connector);
+
drm_connector_attach_encoder(connector, encoder);
 
return 0;
@@ -432,6 +461,25 @@ static void vc4_hdmi_set_audio_infoframe(struct 
drm_encoder *encoder)
vc4_hdmi_write_infoframe(encoder, );
 }
 
+static void vc4_hdmi_set_hdr_infoframe(struct drm_encoder *encoder)
+{
+   struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
+   struct drm_connector *connector = _hdmi->connector;
+   struct drm_connector_state *conn_state = connector->state;
+   union hdmi_infoframe frame;
+
+   if (!vc4_hdmi->variant->supports_hdr)
+   return;
+
+   if (!conn_state->hdr_output_metadata)
+   return;
+
+   if (drm_hdmi_infoframe_set_hdr_metadata(, conn_state))
+   return;
+
+   vc4_hdmi_write_infoframe(encoder, );
+}
+
 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder)
 {
struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
@@ -444,6 +492,8 @@ static void vc4_hdmi_set_infoframes(struct drm_encoder 
*encoder)
 */
if (vc4_hdmi->audio.streaming)
vc4_hdmi_set_audio_infoframe(encoder);
+
+   vc4_hdmi_set_hdr_infoframe(encoder);
 }
 
 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder,
@@ -2101,6 +2151,7 @@ static const struct vc4_hdmi_variant bcm2835_variant = {
.phy_rng_enable = vc4_hdmi_phy_rng_enable,
.phy_rng_disable= vc4_hdmi_phy_rng_disable,
.channel_map= vc4_hdmi_channel_map,
+   .supports_hdr   = false,
 };
 
 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
@@ -2128,6 +2179,7 @@ static const struct vc4_hdmi_variant 
bcm2711_hdmi0_variant = {
.phy_rng_enable = vc5_hdmi_phy_rng_enable,
.phy_rng_disable= vc5_hdmi_phy_rng_disable,
.channel_map= vc5_hdmi_channel_map,
+   .supports_hdr   = true,
 };
 
 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
@@ -2155,6 +2207,7 @@ static const struct vc4_hdmi_variant 
bcm2711_hdmi1_variant = {
.phy_rng_enable = vc5_hdmi_phy_rng_enable,
.phy_rng_disable= vc5_hdmi_phy_rng_disable,
.channel_map= vc5_hdmi_channel_map,
+   .supports_hdr   = true,
 };
 
 static const struct of_device_id vc4_hdmi_dt_match[] = {
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.h b/drivers/gpu/drm/vc4/vc4_hdmi.h
index 3cebd1fd00fc..060bcaefbeb5 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.h
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.h
@@ -99,6 +99,9 @@ struct vc4_hdmi_variant {
 
/* Callback to get channel map */
u32 (*channel_map)(struct vc4_hdmi *vc4_hdmi, u32 channel_mask);
+
+   /* 

Re: [PATCH 27/30] drm/dp_mst: Pass drm_dp_mst_topology_mgr to drm_dp_get_vc_payload_bw()

[Robert Foss]

Hey Lyude,

Thanks for the patch.

On Fri, 19 Feb 2021 at 23:03, Lyude Paul  wrote:
>
> Since this is one of the few functions in drm_dp_mst_topology.c that
> doesn't have any way of getting access to a drm_device, let's pass the
> drm_dp_mst_topology_mgr down to this function so that it can use
> drm_dbg_kms().
>
> Signed-off-by: Lyude Paul 
> ---
>  drivers/gpu/drm/drm_dp_mst_topology.c   | 7 +--
>  drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 ++-
>  include/drm/drm_dp_mst_helper.h | 3 ++-
>  3 files changed, 9 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c 
> b/drivers/gpu/drm/drm_dp_mst_topology.c
> index cf4f2f85711e..fb66df39e0bb 100644
> --- a/drivers/gpu/drm/drm_dp_mst_topology.c
> +++ b/drivers/gpu/drm/drm_dp_mst_topology.c
> @@ -3631,6 +3631,7 @@ static int drm_dp_send_up_ack_reply(struct 
> drm_dp_mst_topology_mgr *mgr,
>
>  /**
>   * drm_dp_get_vc_payload_bw - get the VC payload BW for an MST link
> + * @mgr: The _dp_mst_topology_mgr to use
>   * @link_rate: link rate in 10kbits/s units
>   * @link_lane_count: lane count
>   *
> @@ -3639,7 +3640,8 @@ static int drm_dp_send_up_ack_reply(struct 
> drm_dp_mst_topology_mgr *mgr,
>   * convert the number of PBNs required for a given stream to the number of
>   * timeslots this stream requires in each MTP.
>   */
> -int drm_dp_get_vc_payload_bw(int link_rate, int link_lane_count)
> +int drm_dp_get_vc_payload_bw(const struct drm_dp_mst_topology_mgr *mgr,
> +int link_rate, int link_lane_count)
>  {
> if (link_rate == 0 || link_lane_count == 0)
> DRM_DEBUG_KMS("invalid link rate/lane count: (%d / %d)\n",
> @@ -3704,7 +3706,8 @@ int drm_dp_mst_topology_mgr_set_mst(struct 
> drm_dp_mst_topology_mgr *mgr, bool ms
> goto out_unlock;
> }
>
> -   mgr->pbn_div = 
> drm_dp_get_vc_payload_bw(drm_dp_bw_code_to_link_rate(mgr->dpcd[1]),
> +   mgr->pbn_div = drm_dp_get_vc_payload_bw(mgr,
> +   
> drm_dp_bw_code_to_link_rate(mgr->dpcd[1]),
> mgr->dpcd[2] & 
> DP_MAX_LANE_COUNT_MASK);
> if (mgr->pbn_div == 0) {
> ret = -EINVAL;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c 
> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 8e316146b6d1..60ca0fa32d15 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -70,7 +70,8 @@ static int intel_dp_mst_compute_link_config(struct 
> intel_encoder *encoder,
> slots = drm_dp_atomic_find_vcpi_slots(state, 
> _dp->mst_mgr,
>   connector->port,
>   crtc_state->pbn,
> - 
> drm_dp_get_vc_payload_bw(crtc_state->port_clock,
> + 
> drm_dp_get_vc_payload_bw(_dp->mst_mgr,
> + 
>  crtc_state->port_clock,
>   
>  crtc_state->lane_count));

checkpatch --strict is unhappy about this chunk

WARNING: line length of 102 exceeds 100 columns
#61: FILE: drivers/gpu/drm/i915/display/intel_dp_mst.c:73:
+   crtc_state->port_clock,

Maybe the results of drm_dp_get_vc_payload_bw() can be but in a
temporary variable.

> if (slots == -EDEADLK)
> return slots;
> diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h
> index bd1c39907b92..20dc705642bd 100644
> --- a/include/drm/drm_dp_mst_helper.h
> +++ b/include/drm/drm_dp_mst_helper.h
> @@ -783,7 +783,8 @@ drm_dp_mst_detect_port(struct drm_connector *connector,
>
>  struct edid *drm_dp_mst_get_edid(struct drm_connector *connector, struct 
> drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port);
>
> -int drm_dp_get_vc_payload_bw(int link_rate, int link_lane_count);
> +int drm_dp_get_vc_payload_bw(const struct drm_dp_mst_topology_mgr *mgr,
> +int link_rate, int link_lane_count);
>
>  int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc);
>
> --
> 2.29.2
>
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Re: [PATCH 28/30] drm/dp: Convert drm_dp_helper.c to using drm_err/drm_dbg_*()

[Robert Foss]

Hey Lyude,

Thanks for the patch.

On Fri, 19 Feb 2021 at 23:03, Lyude Paul  wrote:
>
> Now that we've added a back-pointer to drm_device to drm_dp_aux, made
> drm_dp_aux available to any functions in drm_dp_helper.c which need to
> print to the kernel log, and ensured all of our logging uses a consistent
> format, let's do the final step of the conversion and actually move
> everything over to using drm_err() and drm_dbg_*().
>
> This was done by using the following cocci script:
>
>   @@
>   expression list expr;
>   @@
>
>   (
>   - DRM_DEBUG_KMS(expr);
>   + drm_dbg_kms(aux->drm_dev, expr);
>   |
>   - DRM_DEBUG_DP(expr);
>   + drm_dbg_dp(aux->drm_dev, expr);
>   |
>   - DRM_DEBUG_ATOMIC(expr);
>   + drm_dbg_atomic(aux->drm_dev, expr);
>   |
>   - DRM_DEBUG_KMS_RATELIMITED(expr);
>   + drm_dbg_kms_ratelimited(aux->drm_dev, expr);
>   |
>   - DRM_ERROR(expr);
>   + drm_err(aux->drm_dev, expr);
>   )
>
> Followed by correcting the resulting line-wrapping in the results by hand.
>
> Signed-off-by: Lyude Paul 
> ---
>  drivers/gpu/drm/drm_dp_helper.c | 122 
>  1 file changed, 60 insertions(+), 62 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
> index b5e2671baf22..0a787ddf39fd 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -139,8 +139,8 @@ void drm_dp_link_train_clock_recovery_delay(const struct 
> drm_dp_aux *aux,
>  DP_TRAINING_AUX_RD_MASK;
>
> if (rd_interval > 4)
> -   DRM_DEBUG_KMS("%s: AUX interval %lu, out of range (max 4)\n",
> - aux->name, rd_interval);
> +   drm_dbg_kms(aux->drm_dev, "%s: AUX interval %lu, out of range 
> (max 4)\n",
> +   aux->name, rd_interval);
>
> if (rd_interval == 0 || dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
> rd_interval = 100;
> @@ -155,8 +155,8 @@ static void __drm_dp_link_train_channel_eq_delay(const 
> struct drm_dp_aux *aux,
>  unsigned long rd_interval)
>  {
> if (rd_interval > 4)
> -   DRM_DEBUG_KMS("%s: AUX interval %lu, out of range (max 4)\n",
> - aux->name, rd_interval);
> +   drm_dbg_kms(aux->drm_dev, "%s: AUX interval %lu, out of range 
> (max 4)\n",
> +   aux->name, rd_interval);
>
> if (rd_interval == 0)
> rd_interval = 400;
> @@ -220,11 +220,12 @@ drm_dp_dump_access(const struct drm_dp_aux *aux,
> const char *arrow = request == DP_AUX_NATIVE_READ ? "->" : "<-";
>
> if (ret > 0)
> -   DRM_DEBUG_DP("%s: 0x%05x AUX %s (ret=%3d) %*ph\n",
> -aux->name, offset, arrow, ret, min(ret, 20), 
> buffer);
> +   drm_dbg_dp(aux->drm_dev, "%s: 0x%05x AUX %s (ret=%3d) %*ph\n",
> +  aux->name, offset, arrow, ret, min(ret, 20),
> +  buffer);

checkpatch --strict is unhappy with this chunk

ERROR: code indent should use tabs where possible
#75: FILE: drivers/gpu/drm/drm_dp_helper.c:224:
+^I^I   aux->name, offset, arrow, ret, min(ret, 20),$

ERROR: code indent should use tabs where possible
#76: FILE: drivers/gpu/drm/drm_dp_helper.c:225:


> else
> -   DRM_DEBUG_DP("%s: 0x%05x AUX %s (ret=%3d)\n",
> -aux->name, offset, arrow, ret);
> +   drm_dbg_dp(aux->drm_dev, "%s: 0x%05x AUX %s (ret=%3d)\n",
> +  aux->name, offset, arrow, ret);

checkpatch --strict is unhappy with this chunk

ERROR: code indent should use tabs where possible
#81: FILE: drivers/gpu/drm/drm_dp_helper.c:228:
+^I^I   aux->name, offset, arrow, ret);$


>  }
>
>  /**
> @@ -287,8 +288,8 @@ static int drm_dp_dpcd_access(struct drm_dp_aux *aux, u8 
> request,
> err = ret;
> }
>
> -   DRM_DEBUG_KMS("%s: Too many retries, giving up. First error: %d\n",
> - aux->name, err);
> +   drm_dbg_kms(aux->drm_dev, "%s: Too many retries, giving up. First 
> error: %d\n",
> +   aux->name, err);
> ret = err;
>
>  unlock:
> @@ -524,44 +525,44 @@ bool drm_dp_send_real_edid_checksum(struct drm_dp_aux 
> *aux,
>
> if (drm_dp_dpcd_read(aux, DP_DEVICE_SERVICE_IRQ_VECTOR,
>  _test_req, 1) < 1) {
> -   DRM_ERROR("%s: DPCD failed read at register 0x%x\n",
> - aux->name, DP_DEVICE_SERVICE_IRQ_VECTOR);
> +   drm_err(aux->drm_dev, "%s: DPCD failed read at register 
> 0x%x\n",
> +   aux->name, DP_DEVICE_SERVICE_IRQ_VECTOR);
> return false;
> }
> auto_test_req &= DP_AUTOMATED_TEST_REQUEST;
>
> if (drm_dp_dpcd_read(aux, DP_TEST_REQUEST, _edid_read, 1) < 1) {
> -   DRM_ERROR("%s: 

Re: [PATCH] drm/amd/display: Set AMDGPU_DM_DEFAULT_MIN_BACKLIGHT to 0

[Alex Deucher]

On Fri, Mar 19, 2021 at 3:23 AM Evan Benn  wrote:
>
> AMDGPU_DM_DEFAULT_MIN_BACKLIGHT was set to the value of 12
> to ensure no display backlight will flicker at low user brightness
> settings. However this value is quite bright, so for devices that do not
> implement the ACPI ATIF
> ATIF_FUNCTION_QUERY_BRIGHTNESS_TRANSFER_CHARACTERISTICS
> functionality the user cannot set the brightness to a low level even if
> the display would support such a low PWM.
>
> This ATIF feature is not implemented on for example AMD grunt chromebooks.
>
> Signed-off-by: Evan Benn 
>
> ---
> I could not find a justification for the reason for the value. It has
> caused some noticable regression for users: 
> https://bugzilla.kernel.org/show_bug.cgi?id=203439
>
> Maybe this can be either user controlled or userspace configured, but
> preventing users from turning their backlight dim seems wrong.

My understanding is that some panels flicker if you set the min to a
value too low.  This was a safe minimum if the platform didn't specify
it's own safe minimum.  I think we'd just be trading one bug for
another (flickering vs not dim enough).  Maybe a whitelist or
blacklist would be a better solution?

Alex


>
> Also reviewed here: 
> https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/2748377
>
>  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 573cf17262da..0129bd69b94e 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -3151,7 +3151,7 @@ static int amdgpu_dm_mode_config_init(struct 
> amdgpu_device *adev)
> return 0;
>  }
>
> -#define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
> +#define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 0
>  #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
>  #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50
>
> --
> 2.31.0.291.g576ba9dcdaf-goog
>
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[PATCH] drm/ttm: stop warning on TT shrinker failure

[Christian König]

Don't print a warning when we fail to allocate a page for swapping things out.

Also rely on memalloc_nofs_save/memalloc_nofs_restore instead of GFP_NOFS.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/ttm/ttm_tt.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c
index 2f0833c98d2c..86fa3e82dacc 100644
--- a/drivers/gpu/drm/ttm/ttm_tt.c
+++ b/drivers/gpu/drm/ttm/ttm_tt.c
@@ -369,7 +369,7 @@ static unsigned long ttm_tt_shrinker_scan(struct shrinker 
*shrink,
};
int ret;
 
-   ret = ttm_bo_swapout(, GFP_NOFS);
+   ret = ttm_bo_swapout(, GFP_KERNEL | __GFP_NOWARN);
return ret < 0 ? SHRINK_EMPTY : ret;
 }
 
@@ -389,10 +389,13 @@ static unsigned long ttm_tt_shrinker_count(struct 
shrinker *shrink,
 static int ttm_tt_debugfs_shrink_show(struct seq_file *m, void *data)
 {
struct shrink_control sc = { .gfp_mask = GFP_KERNEL };
+   unsigned int flags;
 
fs_reclaim_acquire(GFP_KERNEL);
+   flags = memalloc_nofs_save();
seq_printf(m, "%lu/%lu\n", ttm_tt_shrinker_count(_shrinker, ),
   ttm_tt_shrinker_scan(_shrinker, ));
+   memalloc_nofs_restore(flags);
fs_reclaim_release(GFP_KERNEL);
 
return 0;
-- 
2.25.1

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Re: Amdgpu kernel oops and freezing on system suspend and hibernate

[Harvey]

Evan,

this is a laptop with RENOIR hardware (Ryzen 4800H) and a discrete GPU 
RX5500. There is an external monitor connected to the HDMI port (which 
is attached to the iGPU afaict).


I would be happy to test further and help in nailing this one ;)

Greetings
Harey


Am 19.03.21 um 03:10 schrieb Quan, Evan:

[AMD Public Use]

Hi Harvey,

Resuming after mode1 reset failed according to the error logs below.
Also according to the lspci output of last email, it happened for a Navi14 ASIC.
However, I cannot reproduce that on my desktop platform with 2 x Navi14 ASICs.

Mär 18 13:00:43 obelix kernel: amdgpu :03:00.0: amdgpu: MODE1 reset
Mär 18 13:00:43 obelix kernel: amdgpu :03:00.0: amdgpu: GPU psp
mode1 reset
Mär 18 13:00:43 obelix kernel: [drm] psp mode1 reset succeed

...
Mär 18 13:00:43 obelix kernel: [drm:psp_v11_0_ring_create [amdgpu]]
*ERROR* Failed to wait for sOS ready for ring creation
Mär 18 13:00:43 obelix kernel: [drm:psp_hw_start [amdgpu]] *ERROR* PSP
create ring failed!
Mär 18 13:00:43 obelix kernel: [drm:psp_resume [amdgpu]] *ERROR* PSP
resume failed
Mär 18 13:00:43 obelix kernel: [drm:amdgpu_device_fw_loading [amdgpu]]
*ERROR* resume of IP block  failed -62
Mär 18 13:00:43 obelix kernel: amdgpu :03:00.0: amdgpu:
amdgpu_device_ip_resume failed (-62).


Considering you seemed not running our latest driver according to the complaint 
blow. Maybe it's worth to try our latest driver(@Deucher, Alexander where 
Harvey can get our latest code?).
Mär 18 12:51:36 obelix kernel: amdgpu :03:00.0: amdgpu: smu driver
if version = 0x0036, smu fw if version = 0x0038, smu fw version
= 0x00352100 (53.33.0)

BR
Evan
-Original Message-
From: amd-gfx  On Behalf Of Harvey
Sent: Thursday, March 18, 2021 8:17 PM
To: amd-gfx@lists.freedesktop.org
Subject: Re: Amdgpu kernel oops and freezing on system suspend and hibernate

Alex,

I waited for kernel 5.11.7 to hit our repos yesterday evening and tested
again:

1. The suspend issue is gone - suspend and resume now work as expected.

2. System hibernation seems to be a different beast - still freezing

When invoking 'systemctl hibernate' the system does not power off (I
waited for 5 minutes) and I have to hard reset it to start up again. It
then tries to resume from the swap partition and comes back up with only
the external monitor connected to the HDMI port showing a picture and
the builtin screen of the laptop staying black. Nevertheless the system
is freezed and not responding, neither to mouse or keyboard. After
another hard reset I managed to get the following log from journalctl
(only cut the relevant part):

Mär 18 12:51:11 obelix NetworkManager[866]:   [1616068271.3466]
manager: sleep: sleep requested (sleeping: no  enabled: yes)
Mär 18 12:51:11 obelix NetworkManager[866]:   [1616068271.3473]
device (wlp4s0): state change: disconnected -> unmanaged (reason
'sleeping', sys-iface-state: 'managed')
Mär 18 12:51:11 obelix NetworkManager[866]:   [1616068271.3508]
device (wlp4s0): set-hw-addr: reset MAC address to 14:F6:D8:18:8C:EC
(unmanage)
Mär 18 12:51:11 obelix NetworkManager[866]:   [1616068271.3575]
device (p2p-dev-wlp4s0): state change: disconnected -> unmanaged (reason
'sleeping', sys-iface-state: 'managed')
Mär 18 12:51:11 obelix NetworkManager[866]:   [1616068271.3580]
manager: NetworkManager state is now ASLEEP
Mär 18 12:51:11 obelix wpa_supplicant[954]: nl80211: deinit
ifname=p2p-dev-wlp4s0 disabled_11b_rates=0
Mär 18 12:51:11 obelix wpa_supplicant[954]: nl80211: deinit
ifname=wlp4s0 disabled_11b_rates=0
Mär 18 12:51:12 obelix gsd-media-keys[1691]: Unable to get default sink
Mär 18 12:51:15 obelix gnome-shell[1496]:
../glib/gobject/gsignal.c:2732: instance '0x560b86c67b50' has no handler
with id '15070'
Mär 18 12:51:16 obelix gsd-usb-protect[1724]: Error calling USBGuard
DBus to change the protection after a screensaver event:
GDBus.Error:org.freedesktop.DBus.Error.ServiceUnknown: The name
org.usbguard1 was not provided by any .service files
Mär 18 12:51:16 obelix systemd[1]: Reached target Sleep.
Mär 18 12:51:16 obelix systemd[1]: Starting Suspend...
Mär 18 12:51:16 obelix systemd-sleep[2000]: Suspending system...
Mär 18 12:51:16 obelix kernel: PM: suspend entry (deep)
Mär 18 12:51:16 obelix kernel: Filesystems sync: 0.005 seconds
Mär 18 12:51:36 obelix kernel: Freezing user space processes ...
(elapsed 0.002 seconds) done.
Mär 18 12:51:36 obelix kernel: OOM killer disabled.
Mär 18 12:51:36 obelix kernel: Freezing remaining freezable tasks ...
(elapsed 0.001 seconds) done.
Mär 18 12:51:36 obelix kernel: printk: Suspending console(s) (use
no_console_suspend to debug)
Mär 18 12:51:36 obelix kernel: [drm] free PSP TMR buffer
Mär 18 12:51:36 obelix kernel: [drm] free PSP TMR buffer
Mär 18 12:51:36 obelix kernel: ACPI: EC: interrupt blocked
Mär 18 12:51:36 obelix kernel: ACPI: Preparing to enter system sleep
state S3
Mär 18 12:51:36 obelix kernel: ACPI: EC: event blocked
Mär 18 12:51:36 obelix kernel: ACPI: EC: EC stopped

[PATCH] drm/amdgpu: remove irq_src->data handling

[Christian König]

That is unused for quite some time now.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 5 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h | 1 -
 2 files changed, 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
index af026109421a..03412543427a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
@@ -382,11 +382,6 @@ void amdgpu_irq_fini(struct amdgpu_device *adev)
 
kfree(src->enabled_types);
src->enabled_types = NULL;
-   if (src->data) {
-   kfree(src->data);
-   kfree(src);
-   adev->irq.client[i].sources[j] = NULL;
-   }
}
kfree(adev->irq.client[i].sources);
adev->irq.client[i].sources = NULL;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
index ac527e5deae6..cf6116648322 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
@@ -62,7 +62,6 @@ struct amdgpu_irq_src {
unsignednum_types;
atomic_t*enabled_types;
const struct amdgpu_irq_src_funcs   *funcs;
-   void *data;
 };
 
 struct amdgpu_irq_client {
-- 
2.25.1

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Re: [PATCH] drm/amdgpu: Fix the page fault issue in amdgpu_irq_fini

[Christian König]

Am 19.03.21 um 02:38 schrieb Deng, Emily:

[AMD Official Use Only - Internal Distribution Only]


-Original Message-
From: Christian König 
Sent: Thursday, March 18, 2021 7:52 PM
To: Deng, Emily ; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu: Fix the page fault issue in amdgpu_irq_fini

Am 18.03.21 um 12:48 schrieb Emily Deng:

For some source, it will be shared by some client ID and source ID.
To fix the page fault issue, set all those to null.

Signed-off-by: Emily Deng 
---
   drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 16 +---
   1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
index af026109421a..623b1ac6231d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
@@ -359,7 +359,7 @@ int amdgpu_irq_init(struct amdgpu_device *adev)
*/
   void amdgpu_irq_fini(struct amdgpu_device *adev)
   {
-unsigned i, j;
+unsigned i, j, m, n;

   if (adev->irq.installed) {
   drm_irq_uninstall(adev_to_drm(adev));
@@ -380,12 +380,22 @@ void amdgpu_irq_fini(struct amdgpu_device

*adev)

   if (!src)
   continue;

-kfree(src->enabled_types);
+if (src->enabled_types)
+kfree(src->enabled_types);

A NULL check before kfree() is unecessary and will be complained about by the
static checkers.

Sorry, will remove this.

+
   src->enabled_types = NULL;
+

Unrelated white space change.

Sorry, will remove this also.

   if (src->data) {
   kfree(src->data);
   kfree(src);
-adev->irq.client[i].sources[j] = NULL;
+}
+
+for (m = 0; m < AMDGPU_IRQ_CLIENTID_MAX; ++m) {
+if (!adev->irq.client[m].sources)
+continue;
+for (n = 0; n < AMDGPU_MAX_IRQ_SRC_ID;

++n)

+if (adev->irq.client[m].sources[n] ==

src)

+adev->irq.client[m].sources[n]

= NULL;

Hui what? The memory you set to NULL here is freed on the line below.

Accessing it after that would be illegal, so why do you want to set it to NULL?

[Emily] It is in the loop "for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {", shouldn't have 
been freed in this loop. Only set " adev->irq.client[i].sources[j] = NULL;" is not enough,
as it maybe have other client ID and src ID will share the same src. Also need 
to set those to NULL.


No, that can't happen.

It is illegal to use a dynamic allocated source with multiple client ID 
and src ID. Where do you see that?


We could also probably completely remove this feature since it is unused 
as far as I know.


Thanks,
Christian.


Christian.


   }
   }
   kfree(adev->irq.client[i].sources);


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RE: [PATCH 2/2] drm/amdgpu: disable runpm if other reset method not runpm capable is chosen

[Lazar, Lijo]

[AMD Public Use]



-Original Message-
From: amd-gfx  On Behalf Of Evan Quan
Sent: Friday, March 19, 2021 2:42 PM
To: amd-gfx@lists.freedesktop.org
Cc: Quan, Evan 
Subject: [PATCH 2/2] drm/amdgpu: disable runpm if other reset method not runpm 
capable is chosen

Otherwise, the runpm will be always enabled on a BACO capable target even the 
reset method was forced as like mode1.

Change-Id: If6bf55c533e91470c9c83383788466161608f68d
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +-  
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 ++
 drivers/gpu/drm/amd/amdgpu/cik.c| 2 +-
 drivers/gpu/drm/amd/amdgpu/nv.c | 2 +-
 drivers/gpu/drm/amd/amdgpu/si.c | 2 +-
 drivers/gpu/drm/amd/amdgpu/soc15.c  | 2 +-
 drivers/gpu/drm/amd/amdgpu/vi.c | 2 +-
 8 files changed, 9 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 963ecfd84347..be12dd2550b8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -589,6 +589,7 @@ struct amdgpu_allowed_register_entry {  };
 
 enum amd_reset_method {
+   AMD_RESET_METHOD_AUTO = -1,
AMD_RESET_METHOD_LEGACY = 0,
AMD_RESET_METHOD_MODE0,
AMD_RESET_METHOD_MODE1,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 6a06234dbcad..78e5445b28b5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -168,7 +168,7 @@ int amdgpu_noretry = -1;  int amdgpu_force_asic_type = -1;  
int amdgpu_tmz = -1; /* auto */  uint amdgpu_freesync_vid_mode; -int 
amdgpu_reset_method = -1; /* auto */
+int amdgpu_reset_method = AMD_RESET_METHOD_AUTO; /* auto */
 int amdgpu_num_kcq = -1;
 
 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work); 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 8844f650b17f..49068ad698a6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -168,6 +168,8 @@ int amdgpu_driver_load_kms(struct amdgpu_device *adev, 
unsigned long flags)
adev->runpm = true;
dev_info(adev->dev, "Using BOCO for runtime pm\n");
} else if (amdgpu_device_supports_baco(dev) &&
+  (amdgpu_reset_method == AMD_RESET_METHOD_AUTO ||
+   amdgpu_reset_method == AMD_RESET_METHOD_BACO) &&

< > Why to link runpm suspend method with reset method?

Thanks,
Lijo
   (amdgpu_runtime_pm != 0)) {
switch (adev->asic_type) {
case CHIP_VEGA20:
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index c0fcc41ee574..e671871f4d28 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -1395,7 +1395,7 @@ cik_asic_reset_method(struct amdgpu_device *adev)
amdgpu_reset_method == AMD_RESET_METHOD_BACO)
return amdgpu_reset_method;
 
-   if (amdgpu_reset_method != -1)
+   if (amdgpu_reset_method != AMD_RESET_METHOD_AUTO)
dev_warn(adev->dev, "Specified reset:%d isn't supported, using 
AUTO instead.\n",
  amdgpu_reset_method);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c 
index 2670ae00c2e5..1e751d415f15 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -529,7 +529,7 @@ nv_asic_reset_method(struct amdgpu_device *adev)
amdgpu_reset_method == AMD_RESET_METHOD_PCI)
return amdgpu_reset_method;
 
-   if (amdgpu_reset_method != -1)
+   if (amdgpu_reset_method != AMD_RESET_METHOD_AUTO)
dev_warn(adev->dev, "Specified reset method:%d isn't supported, 
using AUTO instead.\n",
  amdgpu_reset_method);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c 
index 7cbc2bb03bc6..b9db761a7cc5 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -1420,7 +1420,7 @@ si_asic_reset_method(struct amdgpu_device *adev)
if (amdgpu_reset_method == AMD_RESET_METHOD_PCI)
return amdgpu_reset_method;
else if (amdgpu_reset_method != AMD_RESET_METHOD_LEGACY &&
-amdgpu_reset_method != -1)
+amdgpu_reset_method != AMD_RESET_METHOD_AUTO)
dev_warn(adev->dev, "Specified reset method:%d isn't supported, 
using AUTO instead.\n",
 amdgpu_reset_method);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c 
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index c354a11e2fd9..ad11f2e1f4db 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -689,7 +689,7 @@ soc15_asic_reset_method(struct amdgpu_device *adev)
 

RE: [PATCH 1/2] drm/amd/pm: drop redundant and unneeded BACO APIs

[Li, Dennis]

[AMD Official Use Only - Internal Distribution Only]

Hi, Evan,
  It is better to replace all nv_asic_supports_baco callings with 
amdgpu_dpm_is_baco_supported, and remove nv_asic_supports_baco function. 

>>> static bool nv_asic_supports_baco(struct amdgpu_device *adev)  {
>>> -   struct smu_context *smu = >smu;
>>>-
>>>-if (smu_baco_is_support(smu))
>>>-return true;
>>>-else
>>>-return false;
>>>+return amdgpu_dpm_is_baco_supported(adev);
>>>}

Best Regards
Dennis Li
-Original Message-
From: amd-gfx  On Behalf Of Evan Quan
Sent: Friday, March 19, 2021 5:12 PM
To: amd-gfx@lists.freedesktop.org
Cc: Quan, Evan 
Subject: [PATCH 1/2] drm/amd/pm: drop redundant and unneeded BACO APIs

Use other APIs which are with the same functionality but much more clean.

Change-Id: I5e9e0ab5d39b49b02434f18e12392b13931396be
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/amdgpu/nv.c   | 20 +
 drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h   |  9 ---
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 95 ---
 3 files changed, 3 insertions(+), 121 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c 
index e9cc3201054f..2670ae00c2e5 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -517,19 +517,12 @@ static int nv_asic_mode2_reset(struct amdgpu_device *adev)
 
 static bool nv_asic_supports_baco(struct amdgpu_device *adev)  {
-   struct smu_context *smu = >smu;
-
-   if (smu_baco_is_support(smu))
-   return true;
-   else
-   return false;
+   return amdgpu_dpm_is_baco_supported(adev);
 }
 
 static enum amd_reset_method
 nv_asic_reset_method(struct amdgpu_device *adev)  {
-   struct smu_context *smu = >smu;
-
if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
amdgpu_reset_method == AMD_RESET_METHOD_BACO || @@ -548,7 +541,7 @@ 
nv_asic_reset_method(struct amdgpu_device *adev)
case CHIP_DIMGREY_CAVEFISH:
return AMD_RESET_METHOD_MODE1;
default:
-   if (smu_baco_is_support(smu))
+   if (amdgpu_dpm_is_baco_supported(adev))
return AMD_RESET_METHOD_BACO;
else
return AMD_RESET_METHOD_MODE1;
@@ -558,7 +551,6 @@ nv_asic_reset_method(struct amdgpu_device *adev)  static 
int nv_asic_reset(struct amdgpu_device *adev)  {
int ret = 0;
-   struct smu_context *smu = >smu;
 
switch (nv_asic_reset_method(adev)) {
case AMD_RESET_METHOD_PCI:
@@ -567,13 +559,7 @@ static int nv_asic_reset(struct amdgpu_device *adev)
break;
case AMD_RESET_METHOD_BACO:
dev_info(adev->dev, "BACO reset\n");
-
-   ret = smu_baco_enter(smu);
-   if (ret)
-   return ret;
-   ret = smu_baco_exit(smu);
-   if (ret)
-   return ret;
+   ret = amdgpu_dpm_baco_reset(adev);
break;
case AMD_RESET_METHOD_MODE2:
dev_info(adev->dev, "MODE2 reset\n"); diff --git 
a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h 
b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
index 517f333fbc4b..02675155028d 100644
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
@@ -1285,15 +1285,6 @@ int smu_get_power_limit(struct smu_context *smu,
uint32_t *limit,
enum smu_ppt_limit_level limit_level);
 
-int smu_set_azalia_d3_pme(struct smu_context *smu);
-
-bool smu_baco_is_support(struct smu_context *smu);
-
-int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state *state);
-
-int smu_baco_enter(struct smu_context *smu); -int smu_baco_exit(struct 
smu_context *smu);
-
 bool smu_mode1_reset_is_support(struct smu_context *smu);  bool 
smu_mode2_reset_is_support(struct smu_context *smu);  int 
smu_mode1_reset(struct smu_context *smu); diff --git 
a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c 
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 4120d28f782b..1bb0c0966e3d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -2682,48 +2682,6 @@ static int smu_set_xgmi_pstate(void *handle,
return ret;
 }
 
-int smu_set_azalia_d3_pme(struct smu_context *smu) -{
-   int ret = 0;
-
-   if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
-   return -EOPNOTSUPP;
-
-   mutex_lock(>mutex);
-
-   if (smu->ppt_funcs->set_azalia_d3_pme)
-   ret = smu->ppt_funcs->set_azalia_d3_pme(smu);
-
-   mutex_unlock(>mutex);
-
-   return ret;
-}
-
-/*
- * On system suspending or resetting, the dpm_enabled
- * flag will be cleared. So that those SMU services which
- * are not supported will be gated.
- *
- * However, the baco/mode1 reset should still be granted

Re: [PATCH] drm/amd/display: Allow idle optimization based on vblank.

[Michel Dänzer]

On 2021-03-19 1:44 a.m., R, Bindu wrote:
> 
> ​Hi All,
>    Thanks for the inputs, have updated the patch to include these changes.

Updated where? I can't find an updated patch.


-- 
Earthling Michel Dänzer   |   https://redhat.com
Libre software enthusiast | Mesa and X developer
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 2/2] drm/amdgpu: disable runpm if other reset method not runpm capable is chosen

[Evan Quan]

Otherwise, the runpm will be always enabled on a BACO capable target
even the reset method was forced as like mode1.

Change-Id: If6bf55c533e91470c9c83383788466161608f68d
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 ++
 drivers/gpu/drm/amd/amdgpu/cik.c| 2 +-
 drivers/gpu/drm/amd/amdgpu/nv.c | 2 +-
 drivers/gpu/drm/amd/amdgpu/si.c | 2 +-
 drivers/gpu/drm/amd/amdgpu/soc15.c  | 2 +-
 drivers/gpu/drm/amd/amdgpu/vi.c | 2 +-
 8 files changed, 9 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 963ecfd84347..be12dd2550b8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -589,6 +589,7 @@ struct amdgpu_allowed_register_entry {
 };
 
 enum amd_reset_method {
+   AMD_RESET_METHOD_AUTO = -1,
AMD_RESET_METHOD_LEGACY = 0,
AMD_RESET_METHOD_MODE0,
AMD_RESET_METHOD_MODE1,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 6a06234dbcad..78e5445b28b5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -168,7 +168,7 @@ int amdgpu_noretry = -1;
 int amdgpu_force_asic_type = -1;
 int amdgpu_tmz = -1; /* auto */
 uint amdgpu_freesync_vid_mode;
-int amdgpu_reset_method = -1; /* auto */
+int amdgpu_reset_method = AMD_RESET_METHOD_AUTO; /* auto */
 int amdgpu_num_kcq = -1;
 
 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 8844f650b17f..49068ad698a6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -168,6 +168,8 @@ int amdgpu_driver_load_kms(struct amdgpu_device *adev, 
unsigned long flags)
adev->runpm = true;
dev_info(adev->dev, "Using BOCO for runtime pm\n");
} else if (amdgpu_device_supports_baco(dev) &&
+  (amdgpu_reset_method == AMD_RESET_METHOD_AUTO ||
+   amdgpu_reset_method == AMD_RESET_METHOD_BACO) &&
   (amdgpu_runtime_pm != 0)) {
switch (adev->asic_type) {
case CHIP_VEGA20:
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index c0fcc41ee574..e671871f4d28 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -1395,7 +1395,7 @@ cik_asic_reset_method(struct amdgpu_device *adev)
amdgpu_reset_method == AMD_RESET_METHOD_BACO)
return amdgpu_reset_method;
 
-   if (amdgpu_reset_method != -1)
+   if (amdgpu_reset_method != AMD_RESET_METHOD_AUTO)
dev_warn(adev->dev, "Specified reset:%d isn't supported, using 
AUTO instead.\n",
  amdgpu_reset_method);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 2670ae00c2e5..1e751d415f15 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -529,7 +529,7 @@ nv_asic_reset_method(struct amdgpu_device *adev)
amdgpu_reset_method == AMD_RESET_METHOD_PCI)
return amdgpu_reset_method;
 
-   if (amdgpu_reset_method != -1)
+   if (amdgpu_reset_method != AMD_RESET_METHOD_AUTO)
dev_warn(adev->dev, "Specified reset method:%d isn't supported, 
using AUTO instead.\n",
  amdgpu_reset_method);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index 7cbc2bb03bc6..b9db761a7cc5 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -1420,7 +1420,7 @@ si_asic_reset_method(struct amdgpu_device *adev)
if (amdgpu_reset_method == AMD_RESET_METHOD_PCI)
return amdgpu_reset_method;
else if (amdgpu_reset_method != AMD_RESET_METHOD_LEGACY &&
-amdgpu_reset_method != -1)
+amdgpu_reset_method != AMD_RESET_METHOD_AUTO)
dev_warn(adev->dev, "Specified reset method:%d isn't supported, 
using AUTO instead.\n",
 amdgpu_reset_method);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c 
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index c354a11e2fd9..ad11f2e1f4db 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -689,7 +689,7 @@ soc15_asic_reset_method(struct amdgpu_device *adev)
 return amdgpu_reset_method;
 }
 
-   if (amdgpu_reset_method != -1)
+   if (amdgpu_reset_method != AMD_RESET_METHOD_AUTO)
dev_warn(adev->dev, "Specified reset method:%d isn't supported, 
using AUTO instead.\n",
  amdgpu_reset_method);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c 

[PATCH 1/2] drm/amd/pm: drop redundant and unneeded BACO APIs

[Evan Quan]

Use other APIs which are with the same functionality but much
more clean.

Change-Id: I5e9e0ab5d39b49b02434f18e12392b13931396be
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/amdgpu/nv.c   | 20 +
 drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h   |  9 ---
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 95 ---
 3 files changed, 3 insertions(+), 121 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index e9cc3201054f..2670ae00c2e5 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -517,19 +517,12 @@ static int nv_asic_mode2_reset(struct amdgpu_device *adev)
 
 static bool nv_asic_supports_baco(struct amdgpu_device *adev)
 {
-   struct smu_context *smu = >smu;
-
-   if (smu_baco_is_support(smu))
-   return true;
-   else
-   return false;
+   return amdgpu_dpm_is_baco_supported(adev);
 }
 
 static enum amd_reset_method
 nv_asic_reset_method(struct amdgpu_device *adev)
 {
-   struct smu_context *smu = >smu;
-
if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
amdgpu_reset_method == AMD_RESET_METHOD_BACO ||
@@ -548,7 +541,7 @@ nv_asic_reset_method(struct amdgpu_device *adev)
case CHIP_DIMGREY_CAVEFISH:
return AMD_RESET_METHOD_MODE1;
default:
-   if (smu_baco_is_support(smu))
+   if (amdgpu_dpm_is_baco_supported(adev))
return AMD_RESET_METHOD_BACO;
else
return AMD_RESET_METHOD_MODE1;
@@ -558,7 +551,6 @@ nv_asic_reset_method(struct amdgpu_device *adev)
 static int nv_asic_reset(struct amdgpu_device *adev)
 {
int ret = 0;
-   struct smu_context *smu = >smu;
 
switch (nv_asic_reset_method(adev)) {
case AMD_RESET_METHOD_PCI:
@@ -567,13 +559,7 @@ static int nv_asic_reset(struct amdgpu_device *adev)
break;
case AMD_RESET_METHOD_BACO:
dev_info(adev->dev, "BACO reset\n");
-
-   ret = smu_baco_enter(smu);
-   if (ret)
-   return ret;
-   ret = smu_baco_exit(smu);
-   if (ret)
-   return ret;
+   ret = amdgpu_dpm_baco_reset(adev);
break;
case AMD_RESET_METHOD_MODE2:
dev_info(adev->dev, "MODE2 reset\n");
diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h 
b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
index 517f333fbc4b..02675155028d 100644
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
@@ -1285,15 +1285,6 @@ int smu_get_power_limit(struct smu_context *smu,
uint32_t *limit,
enum smu_ppt_limit_level limit_level);
 
-int smu_set_azalia_d3_pme(struct smu_context *smu);
-
-bool smu_baco_is_support(struct smu_context *smu);
-
-int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state *state);
-
-int smu_baco_enter(struct smu_context *smu);
-int smu_baco_exit(struct smu_context *smu);
-
 bool smu_mode1_reset_is_support(struct smu_context *smu);
 bool smu_mode2_reset_is_support(struct smu_context *smu);
 int smu_mode1_reset(struct smu_context *smu);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c 
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 4120d28f782b..1bb0c0966e3d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -2682,48 +2682,6 @@ static int smu_set_xgmi_pstate(void *handle,
return ret;
 }
 
-int smu_set_azalia_d3_pme(struct smu_context *smu)
-{
-   int ret = 0;
-
-   if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
-   return -EOPNOTSUPP;
-
-   mutex_lock(>mutex);
-
-   if (smu->ppt_funcs->set_azalia_d3_pme)
-   ret = smu->ppt_funcs->set_azalia_d3_pme(smu);
-
-   mutex_unlock(>mutex);
-
-   return ret;
-}
-
-/*
- * On system suspending or resetting, the dpm_enabled
- * flag will be cleared. So that those SMU services which
- * are not supported will be gated.
- *
- * However, the baco/mode1 reset should still be granted
- * as they are still supported and necessary.
- */
-bool smu_baco_is_support(struct smu_context *smu)
-{
-   bool ret = false;
-
-   if (!smu->pm_enabled)
-   return false;
-
-   mutex_lock(>mutex);
-
-   if (smu->ppt_funcs && smu->ppt_funcs->baco_is_support)
-   ret = smu->ppt_funcs->baco_is_support(smu);
-
-   mutex_unlock(>mutex);
-
-   return ret;
-}
-
 static int smu_get_baco_capability(void *handle, bool *cap)
 {
struct smu_context *smu = handle;
@@ -2744,59 +2702,6 @@ static int smu_get_baco_capability(void *handle, bool 
*cap)
return ret;
 }
 
-
-int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state *state)
-{
-   if 

RE: [PATCH] drm/amdgpu: Fix the page fault issue in amdgpu_irq_fini

[Li, Dennis]

[AMD Official Use Only - Internal Distribution Only]

Hi, Emily,
  What about refine struct amdgpu_irq_src with refcount? Your change could 
fix this issue, but it is unreadable. 

Best Regards
Dennis Li
-Original Message-
From: amd-gfx  On Behalf Of Deng, Emily
Sent: Friday, March 19, 2021 9:38 AM
To: Christian König ; 
amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH] drm/amdgpu: Fix the page fault issue in amdgpu_irq_fini

[AMD Official Use Only - Internal Distribution Only]

[AMD Official Use Only - Internal Distribution Only]

>-Original Message-
>From: Christian König 
>Sent: Thursday, March 18, 2021 7:52 PM
>To: Deng, Emily ; amd-gfx@lists.freedesktop.org
>Subject: Re: [PATCH] drm/amdgpu: Fix the page fault issue in 
>amdgpu_irq_fini
>
>Am 18.03.21 um 12:48 schrieb Emily Deng:
>> For some source, it will be shared by some client ID and source ID.
>> To fix the page fault issue, set all those to null.
>>
>> Signed-off-by: Emily Deng 
>> ---
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 16 +---
>>   1 file changed, 13 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
>> index af026109421a..623b1ac6231d 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
>> @@ -359,7 +359,7 @@ int amdgpu_irq_init(struct amdgpu_device *adev)
>>*/
>>   void amdgpu_irq_fini(struct amdgpu_device *adev)
>>   {
>> -unsigned i, j;
>> +unsigned i, j, m, n;
>>
>>   if (adev->irq.installed) {
>>   drm_irq_uninstall(adev_to_drm(adev));
>> @@ -380,12 +380,22 @@ void amdgpu_irq_fini(struct amdgpu_device
>*adev)
>>   if (!src)
>>   continue;
>>
>> -kfree(src->enabled_types);
>> +if (src->enabled_types)
>> +kfree(src->enabled_types);
>
>A NULL check before kfree() is unecessary and will be complained about 
>by the static checkers.
Sorry, will remove this.
>
>> +
>>   src->enabled_types = NULL;
>> +
>
>Unrelated white space change.
Sorry, will remove this also.
>
>>   if (src->data) {
>>   kfree(src->data);
>>   kfree(src);
>> -adev->irq.client[i].sources[j] = NULL;
>> +}
>> +
>> +for (m = 0; m < AMDGPU_IRQ_CLIENTID_MAX; ++m) { if 
>> +(!adev->irq.client[m].sources) continue; for (n = 0; n < 
>> +AMDGPU_MAX_IRQ_SRC_ID;
>++n)
>> +if (adev->irq.client[m].sources[n] ==
>src)
>> +adev->irq.client[m].sources[n]
>= NULL;
>
>Hui what? The memory you set to NULL here is freed on the line below.
>
>Accessing it after that would be illegal, so why do you want to set it to NULL?
[Emily] It is in the loop "for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {", 
shouldn't have been freed in this loop. Only set " 
adev->irq.client[i].sources[j] = NULL;" is not enough, as it maybe have other 
client ID and src ID will share the same src. Also need to set those to NULL.
>
>Christian.
>
>>   }
>>   }
>>   kfree(adev->irq.client[i].sources);

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[PATCH] drm/amd/display: Set AMDGPU_DM_DEFAULT_MIN_BACKLIGHT to 0

[Evan Benn]

AMDGPU_DM_DEFAULT_MIN_BACKLIGHT was set to the value of 12
to ensure no display backlight will flicker at low user brightness
settings. However this value is quite bright, so for devices that do not
implement the ACPI ATIF
ATIF_FUNCTION_QUERY_BRIGHTNESS_TRANSFER_CHARACTERISTICS
functionality the user cannot set the brightness to a low level even if
the display would support such a low PWM.

This ATIF feature is not implemented on for example AMD grunt chromebooks.

Signed-off-by: Evan Benn 

---
I could not find a justification for the reason for the value. It has
caused some noticable regression for users: 
https://bugzilla.kernel.org/show_bug.cgi?id=203439

Maybe this can be either user controlled or userspace configured, but
preventing users from turning their backlight dim seems wrong.

Also reviewed here: 
https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/2748377

 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 573cf17262da..0129bd69b94e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -3151,7 +3151,7 @@ static int amdgpu_dm_mode_config_init(struct 
amdgpu_device *adev)
return 0;
 }
 
-#define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
+#define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 0
 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
 #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50
 
-- 
2.31.0.291.g576ba9dcdaf-goog

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[PATCH] drm/amdgpu/powerplay/smu10: refactor AMDGPU_PP_SENSOR_GPU_LOAD

[Shirish S]

refactor AMDGPU_PP_SENSOR_GPU_LOAD to ensure code consistency with other
commands

Signed-off-by: Shirish S 
---
 .../gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c| 13 ++---
 1 file changed, 6 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c 
b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
index f5d59fa3a030..f5fe540cd536 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
@@ -1297,19 +1297,18 @@ static int smu10_read_sensor(struct pp_hwmgr *hwmgr, 
int idx,
*size = 4;
break;
case AMDGPU_PP_SENSOR_GPU_LOAD:
-   if (has_gfx_busy) {
+   if (!has_gfx_busy)
+   ret = -EOPNOTSUPP;
+   else {
ret = smum_send_msg_to_smc(hwmgr,
   PPSMC_MSG_GetGfxBusy,
   _percent);
if (!ret)
-   activity_percent = activity_percent > 100 ? 100 
: activity_percent;
+   *((uint32_t *)value) = min(activity_percent, 
(u32)100);
else
-   return -EIO;
-   *((uint32_t *)value) = activity_percent;
-   return 0;
-   } else {
-   return -EOPNOTSUPP;
+   ret = -EIO;
}
+   break;
default:
ret = -EOPNOTSUPP;
break;
-- 
2.17.1

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[PATCH 2/2] drm/amd/pm: label these APIs used internally as static

[Evan Quan]

Also drop unnecessary header file and declarations.

Change-Id: I877b48c32c599534798e14e271c3e700b0d6ebf6
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c  |   1 -
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c|   1 -
 drivers/gpu/drm/amd/amdgpu/nv.c   |   1 -
 drivers/gpu/drm/amd/amdgpu/soc15.c|   1 -
 drivers/gpu/drm/amd/pm/amdgpu_pm.c|  10 +-
 drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h   |  61 +
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 159 +-
 7 files changed, 98 insertions(+), 136 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
index 33f748e5bbfc..1429c6897d3f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
@@ -24,7 +24,6 @@
 #include 
 #include "amdgpu.h"
 #include "amdgpu_xgmi.h"
-#include "amdgpu_smu.h"
 #include "amdgpu_ras.h"
 #include "soc15.h"
 #include "df/df_3_6_offset.h"
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index d780b9c0926f..9a65ff871a58 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -29,7 +29,6 @@
 #include "amdgpu.h"
 #include "amdgpu_gfx.h"
 #include "amdgpu_psp.h"
-#include "amdgpu_smu.h"
 #include "nv.h"
 #include "nvd.h"
 
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index a31ef68ee2ab..e9cc3201054f 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -34,7 +34,6 @@
 #include "amdgpu_vce.h"
 #include "amdgpu_ucode.h"
 #include "amdgpu_psp.h"
-#include "amdgpu_smu.h"
 #include "atom.h"
 #include "amd_pcie.h"
 
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c 
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 3808402cd964..c354a11e2fd9 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -76,7 +76,6 @@
 #include "smuio_v13_0.h"
 #include "dce_virtual.h"
 #include "mxgpu_ai.h"
-#include "amdgpu_smu.h"
 #include "amdgpu_ras.h"
 #include "amdgpu_xgmi.h"
 #include 
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c 
b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index 74fa5fe89970..10c761b11ff7 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -27,7 +27,6 @@
 #include "amdgpu_drv.h"
 #include "amdgpu_pm.h"
 #include "amdgpu_dpm.h"
-#include "amdgpu_smu.h"
 #include "atom.h"
 #include 
 #include 
@@ -930,14 +929,7 @@ static ssize_t amdgpu_set_pp_features(struct device *dev,
return ret;
}
 
-   if (is_support_sw_smu(adev)) {
-   ret = smu_sys_set_pp_feature_mask(>smu, featuremask);
-   if (ret) {
-   pm_runtime_mark_last_busy(ddev->dev);
-   pm_runtime_put_autosuspend(ddev->dev);
-   return -EINVAL;
-   }
-   } else if (adev->powerplay.pp_funcs->set_ppfeature_status) {
+   if (adev->powerplay.pp_funcs->set_ppfeature_status) {
ret = amdgpu_dpm_set_ppfeature_status(adev, featuremask);
if (ret) {
pm_runtime_mark_last_busy(ddev->dev);
diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h 
b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
index ca5a0a436cad..517f333fbc4b 100644
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
@@ -1281,50 +1281,22 @@ int smu_load_microcode(struct smu_context *smu);
 
 int smu_check_fw_status(struct smu_context *smu);
 
-int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled);
-
-int smu_set_fan_speed_rpm(void *handle, uint32_t speed);
-
 int smu_get_power_limit(struct smu_context *smu,
uint32_t *limit,
enum smu_ppt_limit_level limit_level);
 
-int smu_set_power_limit(void *handle, uint32_t limit);
-int smu_print_ppclk_levels(void *handle, enum pp_clock_type type, char *buf);
-
-int smu_od_edit_dpm_table(void *handle,
- enum PP_OD_DPM_TABLE_COMMAND type,
- long *input, uint32_t size);
-
-int smu_read_sensor(void *handle, int sensor, void *data, int *size);
-int smu_get_power_profile_mode(void *handle, char *buf);
-int smu_set_power_profile_mode(void *handle, long *param, uint32_t param_size);
-u32 smu_get_fan_control_mode(void *handle);
-int smu_set_fan_control_mode(struct smu_context *smu, int value);
-void smu_pp_set_fan_control_mode(void *handle, u32 value);
-int smu_get_fan_speed_percent(void *handle, u32 *speed);
-int smu_set_fan_speed_percent(void *handle, u32 speed);
-int smu_get_fan_speed_rpm(void *handle, uint32_t *speed);
-
-int smu_set_xgmi_pstate(void *handle,
-   uint32_t pstate);
-
 int smu_set_azalia_d3_pme(struct smu_context *smu);
 
 bool smu_baco_is_support(struct smu_context *smu);
-int smu_get_baco_capability(void *handle, bool *cap);
 
 int smu_baco_get_state(struct smu_context *smu, enum 

[PATCH 1/2] drm/amd/pm: make DAL communicate with SMU through unified interfaces

[Evan Quan]

No need to have special handlings for swSMU supported ASICs.

Change-Id: I1ec552c6a2a4283cf6ab3acfe6c0753bfcca57a9
Signed-off-by: Evan Quan 
---
 .../amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c  | 134 +++---
 .../gpu/drm/amd/include/kgd_pp_interface.h|  14 ++
 drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h   |  27 
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c |  68 +++--
 4 files changed, 118 insertions(+), 125 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
index 607ec0999445..eba270121698 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
@@ -32,15 +32,12 @@
 #include "amdgpu_dm_irq.h"
 #include "amdgpu_pm.h"
 #include "dm_pp_smu.h"
-#include "amdgpu_smu.h"
-
 
 bool dm_pp_apply_display_requirements(
const struct dc_context *ctx,
const struct dm_pp_display_configuration *pp_display_cfg)
 {
struct amdgpu_device *adev = ctx->driver_context;
-   struct smu_context *smu = >smu;
int i;
 
if (adev->pm.dpm_enabled) {
@@ -106,9 +103,6 @@ bool dm_pp_apply_display_requirements(
adev->powerplay.pp_funcs->display_configuration_change(
adev->powerplay.pp_handle,
>pm.pm_display_cfg);
-   else if (adev->smu.ppt_funcs)
-   smu_display_configuration_change(smu,
-
>pm.pm_display_cfg);
 
amdgpu_pm_compute_clocks(adev);
}
@@ -148,36 +142,6 @@ static void get_default_clock_levels(
}
 }
 
-static enum smu_clk_type dc_to_smu_clock_type(
-   enum dm_pp_clock_type dm_pp_clk_type)
-{
-   enum smu_clk_type smu_clk_type = SMU_CLK_COUNT;
-
-   switch (dm_pp_clk_type) {
-   case DM_PP_CLOCK_TYPE_DISPLAY_CLK:
-   smu_clk_type = SMU_DISPCLK;
-   break;
-   case DM_PP_CLOCK_TYPE_ENGINE_CLK:
-   smu_clk_type = SMU_GFXCLK;
-   break;
-   case DM_PP_CLOCK_TYPE_MEMORY_CLK:
-   smu_clk_type = SMU_MCLK;
-   break;
-   case DM_PP_CLOCK_TYPE_DCEFCLK:
-   smu_clk_type = SMU_DCEFCLK;
-   break;
-   case DM_PP_CLOCK_TYPE_SOCCLK:
-   smu_clk_type = SMU_SOCCLK;
-   break;
-   default:
-   DRM_ERROR("DM_PPLIB: invalid clock type: %d!\n",
- dm_pp_clk_type);
-   break;
-   }
-
-   return smu_clk_type;
-}
-
 static enum amd_pp_clock_type dc_to_pp_clock_type(
enum dm_pp_clock_type dm_pp_clk_type)
 {
@@ -417,14 +381,8 @@ bool dm_pp_get_clock_levels_by_type_with_latency(
_clks);
if (ret)
return false;
-   } else if (adev->smu.ppt_funcs && 
adev->smu.ppt_funcs->get_clock_by_type_with_latency) {
-   if (smu_get_clock_by_type_with_latency(>smu,
-  
dc_to_smu_clock_type(clk_type),
-  _clks))
-   return false;
}
 
-
pp_to_dc_clock_levels_with_latency(_clks, clk_level_info, clk_type);
 
return true;
@@ -502,10 +460,6 @@ bool dm_pp_apply_clock_for_voltage_request(
ret = adev->powerplay.pp_funcs->display_clock_voltage_request(
adev->powerplay.pp_handle,
_clock_request);
-   else if (adev->smu.ppt_funcs &&
-adev->smu.ppt_funcs->display_clock_voltage_request)
-   ret = smu_display_clock_voltage_request(>smu,
-   _clock_request);
if (ret)
return false;
return true;
@@ -655,8 +609,11 @@ static enum pp_smu_status pp_nv_set_wm_ranges(struct 
pp_smu *pp,
 {
const struct dc_context *ctx = pp->dm;
struct amdgpu_device *adev = ctx->driver_context;
+   void *pp_handle = adev->powerplay.pp_handle;
+   const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 
-   smu_set_watermarks_for_clock_ranges(>smu, ranges);
+   if (pp_funcs && pp_funcs->set_watermarks_for_clocks_ranges)
+   pp_funcs->set_watermarks_for_clocks_ranges(pp_handle, ranges);
 
return PP_SMU_RESULT_OK;
 }
@@ -665,13 +622,14 @@ static enum pp_smu_status pp_nv_set_display_count(struct 
pp_smu *pp, int count)
 {
const struct dc_context *ctx = pp->dm;
struct amdgpu_device *adev = ctx->driver_context;
-   struct smu_context *smu = >smu;
+   void *pp_handle = adev->powerplay.pp_handle;
+   const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 
-   if (!smu->ppt_funcs)
+   if (!pp_funcs ||