Re: [PATCH v3 4/5] drm/amdgpu: address remove from fault filter
Am 2021-04-23 um 12:28 p.m. schrieb Christian König:
>
>
> Am 23.04.21 um 17:35 schrieb Philip Yang:
>> Add interface to remove address from fault filter ring by resetting
>> fault ring entry key, then future vm fault on the address will be
>> processed to recover.
>>
>> Use spinlock to protect fault hash ring access by interrupt handler and
>> interrupt scheduled deferred work for vg20.
>>
>> Signed-off-by: Philip Yang
>> ---
>> drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 66 +++--
>> drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 3 ++
>> drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 1 +
>> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 1 +
>> 4 files changed, 68 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
>> index c39ed9eb0987..91106b59389f 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
>> @@ -332,6 +332,17 @@ void amdgpu_gmc_agp_location(struct
>> amdgpu_device *adev, struct amdgpu_gmc *mc)
>> mc->agp_size >> 20, mc->agp_start, mc->agp_end);
>> }
>> +/**
>> + * fault_key - get 52bit hask key from vm fault address and pasid
>> + *
>> + * @addr: 48bit physical address
>> + * @pasid: 4 bit
>> + */
>> +static inline uint64_t fault_key(uint64_t addr, uint16_t pasid)
>
> Please prefix with amdgpu_gmc_
>
>> +{
>> + return addr << 4 | pasid;
>> +}
>> +
>> /**
>> * amdgpu_gmc_filter_faults - filter VM faults
>> *
>> @@ -349,15 +360,20 @@ bool amdgpu_gmc_filter_faults(struct
>> amdgpu_device *adev, uint64_t addr,
>> {
>> struct amdgpu_gmc *gmc = >gmc;
>> - uint64_t stamp, key = addr << 4 | pasid;
>> + uint64_t stamp, key = fault_key(addr, pasid);
>> struct amdgpu_gmc_fault *fault;
>> + unsigned long flags;
>> uint32_t hash;
>> /* If we don't have space left in the ring buffer return
>> immediately */
>> stamp = max(timestamp, AMDGPU_GMC_FAULT_TIMEOUT + 1) -
>> AMDGPU_GMC_FAULT_TIMEOUT;
>> - if (gmc->fault_ring[gmc->last_fault].timestamp >= stamp)
>> +
>> + spin_lock_irqsave(>fault_lock, flags);
>
> Uff the spinlock adds quite some overhead here. I'm still wondering if
> we can't somehow avoid this.
Does it? I guess the irqsave version has overhead because it needs to
disable and reenable interrupts. Other than that, spin locks should be
fairly low overhead, especially in the common (uncontested) case.
If we want to use atomic ops to update the key, it has to be a uint64_t,
not a bitfield. Maybe we could steal 8 bits for the "next" field from
the timestamp instead.
Regards,
Felix
>
> Christian.
>
>> + if (gmc->fault_ring[gmc->last_fault].timestamp >= stamp) {
>> + spin_unlock_irqrestore(>fault_lock, flags);
>> return true;
>> + }
>> /* Try to find the fault in the hash */
>> hash = hash_64(key, AMDGPU_GMC_FAULT_HASH_ORDER);
>> @@ -365,8 +381,10 @@ bool amdgpu_gmc_filter_faults(struct
>> amdgpu_device *adev, uint64_t addr,
>> while (fault->timestamp >= stamp) {
>> uint64_t tmp;
>> - if (fault->key == key)
>> + if (fault->key == key) {
>> + spin_unlock_irqrestore(>fault_lock, flags);
>> return true;
>> + }
>> tmp = fault->timestamp;
>> fault = >fault_ring[fault->next];
>> @@ -384,9 +402,51 @@ bool amdgpu_gmc_filter_faults(struct
>> amdgpu_device *adev, uint64_t addr,
>> /* And update the hash */
>> fault->next = gmc->fault_hash[hash].idx;
>> gmc->fault_hash[hash].idx = gmc->last_fault++;
>> + spin_unlock_irqrestore(>fault_lock, flags);
>> return false;
>> }
>> +/**
>> + * amdgpu_gmc_filter_faults_remove - remove address from VM faults
>> filter
>> + *
>> + * @adev: amdgpu device structure
>> + * @addr: address of the VM fault
>> + * @pasid: PASID of the process causing the fault
>> + *
>> + * Remove the address from fault filter, then future vm fault on
>> this address
>> + * will pass to retry fault handler to recover.
>> + */
>> +void amdgpu_gmc_filter_faults_remove(struct amdgpu_device *adev,
>> uint64_t addr,
>> + uint16_t pasid)
>> +{
>> + struct amdgpu_gmc *gmc = >gmc;
>> +
>> + uint64_t key = fault_key(addr, pasid);
>> + struct amdgpu_gmc_fault *fault;
>> + unsigned long flags;
>> + uint32_t hash;
>> +
>> + spin_lock_irqsave(>fault_lock, flags);
>> + hash = hash_64(key, AMDGPU_GMC_FAULT_HASH_ORDER);
>> + fault = >fault_ring[gmc->fault_hash[hash].idx];
>> + while (true) {
>> + uint64_t tmp;
>> +
>> + if (fault->key == key) {
>> + fault->key = fault_key(0, 0);
>> + break;
>> + }
>> +
>> + tmp = fault->timestamp;
>> + fault = >fault_ring[fault->next];
>> +
>> + /* Check if the entry was reused */
>> + if (fault->timestamp >= tmp)
>> + break;
>> + }
>> +
Re: [PATCH] drm/amdgpu: Added missing prototype
Am 2021-04-23 um 5:39 p.m. schrieb Souptick Joarder: > Kernel test robot throws below warning -> > >>> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c:125:5: warning: >>> no previous prototype for 'kgd_arcturus_hqd_sdma_load' >>> [-Wmissing-prototypes] > 125 | int kgd_arcturus_hqd_sdma_load(struct kgd_dev *kgd, void > *mqd, > >>> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c:227:6: warning: >>> no previous prototype for 'kgd_arcturus_hqd_sdma_is_occupied' >>> [-Wmissing-prototypes] > 227 | bool kgd_arcturus_hqd_sdma_is_occupied(struct kgd_dev *kgd, > void *mqd) > | ^ >>> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c:246:5: warning: >>> no previous prototype for 'kgd_arcturus_hqd_sdma_destroy' >>> [-Wmissing-prototypes] > 246 | int kgd_arcturus_hqd_sdma_destroy(struct kgd_dev *kgd, void > *mqd, > | ^ > > Added prototype for these functions. The prototypes are already defined in amdgpu_amdkfd_arcturus.h. I think we just need to add a #include in amdgpu_amdkfd_arcturus.c. Regards, Felix > > Reported-by: kernel test robot > Signed-off-by: Souptick Joarder > --- > drivers/gpu/drm/amd/amdgpu/amdgpu.h | 5 + > 1 file changed, 5 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h > b/drivers/gpu/drm/amd/amdgpu/amdgpu.h > index dc3a692..8fff0e7 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h > @@ -316,6 +316,11 @@ int amdgpu_device_ip_wait_for_idle(struct amdgpu_device > *adev, > enum amd_ip_block_type block_type); > bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, > enum amd_ip_block_type block_type); > +int kgd_arcturus_hqd_sdma_load(struct kgd_dev *kgd, void *mqd, > + uint32_t __user *wptr, struct mm_struct *mm); > +bool kgd_arcturus_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd); > +int kgd_arcturus_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd, > + unsigned int utimeout); > > #define AMDGPU_MAX_IP_NUM 16 > ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[pull] amdgpu, radeon drm-next-5.13
Hi Dave, Daniel, Fixes for 5.13. The following changes since commit af8352f1ff54c4fecf84e36315fd1928809a580b: Merge tag 'drm-msm-next-2021-04-11' of https://gitlab.freedesktop.org/drm/msm into drm-next (2021-04-13 23:35:54 +0200) are available in the Git repository at: https://gitlab.freedesktop.org/agd5f/linux.git tags/amd-drm-next-5.13-2021-04-23 for you to fetch changes up to 7845d80dda1fd998a34bb1a15ff9aba260a58f32: drm/amdgpu/gmc9: remove dummy read workaround for newer chips (2021-04-20 21:45:36 -0400) amd-drm-next-5.13-2021-04-23: amdgpu: - Fixes for Aldebaran - Display LTTPR fixes - eDP fixes - Fixes for Vangogh - RAS fixes - ASPM support - Renoir SMU fixes - Modifier fixes - Misc code cleanups - Freesync fixes radeon: - Misc code cleanups Alex Deucher (1): drm/amdgpu/gmc9: remove dummy read workaround for newer chips Anthony Koo (3): drm/amd/display: [FW Promotion] Release 0.0.60 drm/amd/display: [FW Promotion] Release 0.0.61 drm/amd/display: [FW Promotion] Release 0.0.62 Anthony Wang (3): drm/amd/display: Force vsync flip when reconfiguring MPCC drm/amd/display: Add DSC check to seamless boot validation drm/amd/display: disable seamless boot for external DP Aric Cyr (3): drm/amd/display: 3.2.131 drm/amd/display: Fix FreeSync when RGB MPO in use drm/amd/display: 3.2.132 Bing Guo (1): drm/amd/display: add helper for enabling mst stream features Dan Carpenter (2): drm/amdgpu: fix an error code in init_pmu_entry_by_type_and_add() drm/amd/pm: fix error code in smu_set_power_limit() David Galiffi (1): drm/amd/display: Fixed typo in function name. Dennis Li (2): drm/amdkfd: add edc error interrupt handle for poison propogate mode drm/amdgpu: fix a error injection failed issue Dillon Varone (2): drm/amd/display: Fix call to pass bpp in 16ths of a bit drm/amd/display: Report Proper Quantization Range in AVI Infoframe Dingchen (David) Zhang (2): drm/amd/display: update hdcp display using correct CP type. drm/amd/display: add handling for hdcp2 rx id list validation Eric Huang (1): drm/amdkfd: change MTYPEs for Aldebaran's HW requirement Felix Kuehling (1): drm/amdkfd: Remove legacy code not acquiring VMs Harry Wentland (1): drm/amd/display: Add debugfs to repress HPD and HPR_RX IRQs Hawking Zhang (3): drm/amdgpu: correct default gfx wdt timeout setting drm/amdgpu: only harvest gcea/mmea error status in arcturus drm/amdgpu: only harvest gcea/mmea error status in aldebaran Huang Rui (1): drm/amdgpu: enable tmz on renoir asics Hugo Hu (1): drm/amd/display: treat memory as a single-channel for asymmetric memory v2 Jack Zhang (1): drm/amd/sriov no need to config GECC for sriov Jake Wang (1): drm/amd/display: Added support for multiple eDP BL control Jiansong Chen (1): drm/amdgpu: fix GCR_GENERAL_CNTL offset for dimgrey_cavefish Jinzhou Su (2): drm/amdgpu: Add graphics cache rinse packet for sdma drm/amdgpu: Add mem sync flag for IB allocated by SA John Clements (3): drm/amdgpu: update mmhub 1.7 ras error reporting drm/amdgpu: update gfx 9.4.2 ras error reporting drm/amdgpu: resolve erroneous gfx_v9_4_2 prints Joseph Greathouse (1): drm/amdgpu: Copy MEC FW version to MEC2 if we skipped loading MEC2 Kenneth Feng (3): drm/amd/amdgpu: enable ASPM on navi1x drm/amd/amdgpu: enable ASPM on vega drm/amd/amdgpu: add ASPM support on polaris Kent Russell (1): drm/amdgpu: Ensure dcefclk isn't created on Aldebaran Lewis Huang (1): drm/amd/display: wait vblank when stream enabled and update dpp clock Lijo Lazar (2): drm/amd/pm: Use VBIOS PPTable for aldebaran drm/amd/pm: Show updated clocks on aldebaran Luben Tuikov (5): drm/amdgpu: Fix a bug for input with double sscanf drm/amdgpu: Fix a bug in checking the result of reserve page drm/amdgpu: Add bad_page_cnt_threshold to debugfs drm/amdgpu: Fix kernel-doc for the RAS sysfs interface drm/amdgpu: Add double-sscanf but invert Michael Strauss (4): drm/amd/display: Add debug flag to enable eDP ILR by default drm/amd/display: Disable boot optimizations if ILR optimzation is required drm/amd/display: Remove static property from decide_edp_link_settings drm/amd/display: Add link rate optimization logs for ILR Mike Hsieh (1): drm/amd/display: Fix DSC enable sequence Mikita Lipski (2): drm/amd/display: Remove unused flag from stream state drm/amd/display: Connect clock optimization function to dcn301 Mukul Joshi (2): drm/amdgpu: Reset RAS error count and status regs drm/amdgpu: Fix SDMA RAS error reporting on Aldebaran Nicholas Kazlauskas (2):
[PATCH] drm/amdgpu: Added missing prototype
Kernel test robot throws below warning -> >> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c:125:5: warning: >> no previous prototype for 'kgd_arcturus_hqd_sdma_load' >> [-Wmissing-prototypes] 125 | int kgd_arcturus_hqd_sdma_load(struct kgd_dev *kgd, void *mqd, >> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c:227:6: warning: >> no previous prototype for 'kgd_arcturus_hqd_sdma_is_occupied' >> [-Wmissing-prototypes] 227 | bool kgd_arcturus_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd) | ^ >> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c:246:5: warning: >> no previous prototype for 'kgd_arcturus_hqd_sdma_destroy' >> [-Wmissing-prototypes] 246 | int kgd_arcturus_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd, | ^ Added prototype for these functions. Reported-by: kernel test robot Signed-off-by: Souptick Joarder --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index dc3a692..8fff0e7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -316,6 +316,11 @@ int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, enum amd_ip_block_type block_type); bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, enum amd_ip_block_type block_type); +int kgd_arcturus_hqd_sdma_load(struct kgd_dev *kgd, void *mqd, + uint32_t __user *wptr, struct mm_struct *mm); +bool kgd_arcturus_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd); +int kgd_arcturus_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd, + unsigned int utimeout); #define AMDGPU_MAX_IP_NUM 16 -- 1.9.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH 2/2] drm/amdgpu/display: add documentation for dmcub_trace_event_en
[AMD Official Use Only - Internal Distribution Only]
Hi Alex,
Thanks for adding this.
Reviewed-by: Leo (Hanghong) Ma
Thanks,
-Leo
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: Friday, April 23, 2021 4:50 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH 2/2] drm/amdgpu/display: add documentation for
dmcub_trace_event_en
Was missing when this structure was updated.
Fixes: 4057828a1283 ("drm/amd/display: Add debugfs to control DMUB trace buffer
events")
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index d6a44b4fc472..fc13e8b6ea5c 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -168,6 +168,7 @@ struct dal_allocation {
* @compressor: Frame buffer compression buffer. See dm_compressor_info
* @force_timing_sync: set via debugfs. When set, indicates that all connected
*displays will be forced to synchronize.
+ * @dmcub_trace_event_en: enable dmcub trace events
*/
struct amdgpu_display_manager {
--
2.30.2
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Re: [PATCH] drm/amd/pm: Update energy_accumulator in gpu metrics
Reviewed-by: Alex Deucher On Fri, Apr 23, 2021 at 3:02 PM Harish Kasiviswanathan wrote: > > Signed-off-by: Harish Kasiviswanathan > --- > drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c > b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c > index dcbe3a72da09..1f02e4ee2909 100644 > --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c > @@ -1657,7 +1657,8 @@ static ssize_t aldebaran_get_gpu_metrics(struct > smu_context *smu, > gpu_metrics->average_mm_activity = 0; > > gpu_metrics->average_socket_power = metrics.AverageSocketPower; > - gpu_metrics->energy_accumulator = 0; > + gpu_metrics->energy_accumulator = metrics.EnergyAcc64bitHigh << 32 | > + metrics.EnergyAcc64bitLow; > > gpu_metrics->average_gfxclk_frequency = > metrics.AverageGfxclkFrequency; > gpu_metrics->average_socclk_frequency = > metrics.AverageSocclkFrequency; > -- > 2.25.1 > > ___ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amd/display: Remove condition which is always set to True
Kernel test robot throws below warning -> >> drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_debugfs.c:3015:53: >> warning: address of 'aconnector->mst_port->mst_mgr' will always >> evaluate to 'true' [-Wpointer-bool-conversion] if (!(aconnector->port && >mst_port->mst_mgr)) ~~ ~~^~~ Remove the condition which is always set to True. Reported-by: kernel test robot Signed-off-by: Souptick Joarder --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index 9a13f47..8f7df11 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -3012,7 +3012,7 @@ static int trigger_hpd_mst_set(void *data, u64 val) if (!aconnector->dc_link) continue; - if (!(aconnector->port && >mst_port->mst_mgr)) + if (!aconnector->port) continue; link = aconnector->dc_link; -- 1.9.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [Nouveau] [PATCH v4 02/17] drm/nouveau/kms/nv50-: Move AUX adapter reg to connector late register/early unregister
Some trivia, no comment on the real logic of the changes:
On Fri, Apr 23, 2021 at 2:43 PM Lyude Paul wrote:
>
> Since AUX adapters on nouveau have their respective DRM connectors as
> parents, we need to make sure that we register then after their connectors.
then -> them
>
> Signed-off-by: Lyude Paul
> ---
> drivers/gpu/drm/nouveau/nouveau_connector.c | 25 -
> 1 file changed, 20 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c
> b/drivers/gpu/drm/nouveau/nouveau_connector.c
> index 61e6d7412505..c04044be3d32 100644
> --- a/drivers/gpu/drm/nouveau/nouveau_connector.c
> +++ b/drivers/gpu/drm/nouveau/nouveau_connector.c
> @@ -401,7 +401,6 @@ nouveau_connector_destroy(struct drm_connector *connector)
> drm_connector_cleanup(connector);
> if (nv_connector->aux.transfer) {
> drm_dp_cec_unregister_connector(_connector->aux);
> - drm_dp_aux_unregister(_connector->aux);
> kfree(nv_connector->aux.name);
> }
> kfree(connector);
> @@ -905,13 +904,29 @@ nouveau_connector_late_register(struct drm_connector
> *connector)
> int ret;
>
> ret = nouveau_backlight_init(connector);
> + if (ret)
> + return ret;
>
> + if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
> + connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
> + ret = drm_dp_aux_register(_connector(connector)->aux);
> + if (ret)
> + goto backlight_fini;
> + }
> +
> + return 0;
> +backlight_fini:
> + nouveau_backlight_fini(connector);
> return ret;
> }
>
> static void
> nouveau_connector_early_unregister(struct drm_connector *connector)
> {
> + if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
> + connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort)
> + drm_dp_aux_unregister(_connector(connector)->aux);
> +
> nouveau_backlight_fini(connector);
> }
>
> @@ -1343,14 +1358,14 @@ nouveau_connector_create(struct drm_device *dev,
> snprintf(aux_name, sizeof(aux_name), "sor-%04x-%04x",
> dcbe->hasht, dcbe->hashm);
> nv_connector->aux.name = kstrdup(aux_name, GFP_KERNEL);
> - ret = drm_dp_aux_register(_connector->aux);
> + drm_dp_aux_init(_connector->aux);
> if (ret) {
> - NV_ERROR(drm, "failed to register aux channel\n");
> + NV_ERROR(drm, "Failed to init AUX adapter for
> sor-%04x-%04x: %d\n",
Maybe just use aux_name instead of rebuilding the string again?
> +dcbe->hasht, dcbe->hashm, ret);
> kfree(nv_connector);
> return ERR_PTR(ret);
> }
> - funcs = _connector_funcs;
> - break;
> + fallthrough;
> default:
> funcs = _connector_funcs;
> break;
> --
> 2.30.2
>
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[PATCH 1/2] drm/amdgpu/display: fix dal_allocation documentation
Add missing structure elements.
Fixes: 1ace37b873c2 ("drm/amdgpu/display: Implement functions to let DC
allocate GPU memory")
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index 77e338b3ab6b..d6a44b4fc472 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -135,6 +135,10 @@ struct amdgpu_dm_backlight_caps {
/**
* struct dal_allocation - Tracks mapped FB memory for SMU communication
+ * @list: list of dal allocations
+ * @bo: GPU buffer object
+ * @cpu_ptr: CPU virtual address of the GPU buffer object
+ * @gpu_addr: GPU virtual address of the GPU buffer object
*/
struct dal_allocation {
struct list_head list;
--
2.30.2
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[PATCH 2/2] drm/amdgpu/display: add documentation for dmcub_trace_event_en
Was missing when this structure was updated.
Fixes: 4057828a1283 ("drm/amd/display: Add debugfs to control DMUB trace buffer
events")
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index d6a44b4fc472..fc13e8b6ea5c 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -168,6 +168,7 @@ struct dal_allocation {
* @compressor: Frame buffer compression buffer. See dm_compressor_info
* @force_timing_sync: set via debugfs. When set, indicates that all connected
*displays will be forced to synchronize.
+ * @dmcub_trace_event_en: enable dmcub trace events
*/
struct amdgpu_display_manager {
--
2.30.2
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[PATCH] drm/dp_mst: Use the correct DPCD space in Synaptics quirk
[why]
Two conditions that were part of this fix did not go through:
1. DPCD revision has to be v1.4 and up
This was because wrong DPCD space was used to get the values
2. Downstream port must not be VGA converter
This was because for MST the topology manager AUX has to be used,
due to the way MST AUX reads are done.
[how]
- Use Extended Receiver Capability DPCD space if
DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT is set
- Use MST topology manager AUX to get port DPCD
Signed-off-by: Nikola Cornij
---
drivers/gpu/drm/drm_dp_mst_topology.c | 33 ---
1 file changed, 25 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c
b/drivers/gpu/drm/drm_dp_mst_topology.c
index de5124ce42cb..69fd16ce2cb3 100644
--- a/drivers/gpu/drm/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/drm_dp_mst_topology.c
@@ -5878,18 +5878,35 @@ struct drm_dp_aux *drm_dp_mst_dsc_aux_for_port(struct
drm_dp_mst_port *port)
return NULL;
if (drm_dp_has_quirk(, DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD) &&
- port->mgr->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14 &&
port->parent == port->mgr->mst_primary) {
- u8 downstreamport;
+ u8 training_aux_rd_interval = 0;
+ u8 dpcd_rev = 0;
+ unsigned int dpcd_caps_offset = 0;
- if (drm_dp_dpcd_read(>aux, DP_DOWNSTREAMPORT_PRESENT,
-, 1) < 0)
+ if (drm_dp_dpcd_read(port->mgr->aux,
DP_TRAINING_AUX_RD_INTERVAL,
+_aux_rd_interval, 1) < 1)
return NULL;
- if ((downstreamport & DP_DWN_STRM_PORT_PRESENT) &&
- ((downstreamport & DP_DWN_STRM_PORT_TYPE_MASK)
-!= DP_DWN_STRM_PORT_TYPE_ANALOG))
- return port->mgr->aux;
+ /* If DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT is set, the
Extended Receiver Capability field has to be used */
+ if (training_aux_rd_interval &
DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT)
+ dpcd_caps_offset = 0x02200;
+
+ if (drm_dp_dpcd_read(port->mgr->aux, dpcd_caps_offset +
DP_DPCD_REV,
+_rev, 1) < 1)
+ return NULL;
+
+ if (dpcd_rev >= DP_DPCD_REV_14) {
+ u8 downstreamport = 0;
+
+ if (drm_dp_dpcd_read(port->mgr->aux, dpcd_caps_offset +
DP_DOWNSTREAMPORT_PRESENT,
+, 1) < 1)
+ return NULL;
+
+ if ((downstreamport & DP_DWN_STRM_PORT_PRESENT) &&
+ ((downstreamport & DP_DWN_STRM_PORT_TYPE_MASK)
+!= DP_DWN_STRM_PORT_TYPE_ANALOG))
+ return port->mgr->aux;
+ }
}
/*
--
2.25.1
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RE: [PATCH 00/16] DC Patches April 23, 2021
[AMD Public Use] Hi all, This week this patchset was tested on the following systems: HP Envy 360, with Ryzen 5 4500U, on the following display types: eDP 1080p 60hz, 4k 60hz (via USB-C to DP/HDMI), 1440p 144hz (via USB-C to DP/HDMI), 1680*1050 60hz (via USB-C to DP and then DP to DVI/VGA) Sapphire Pulse RX5700XT on the following display types: 4k 60hz (via DP/HDMI), 1440p 144hz (via DP/HDMI), 1680*1050 60hz (via DP to DVI/VGA) Reference AMD RX6800 on the following display types: 4k 60hz (via DP/HDMI and USB-C to DP/HDMI), 1440p 144hz (via USB-C to DP/HDMI and USB-C to DP/HDMI), 1680*1050 60hz (via DP to DVI/VGA) Included testing using a Startech DP 1.4 MST hub at 2x 4k 60hz on all systems. Tested-by: Daniel Wheeler Thank you, Dan Wheeler Technologist | AMD SW Display-- 1 Commerce Valley Dr E, Thornhill, ON L3T 7X6 Facebook | Twitter | amd.com -Original Message- From: amd-gfx On Behalf Of Wayne Lin Sent: April 22, 2021 10:37 PM To: amd-gfx@lists.freedesktop.org Cc: Brol, Eryk ; Li, Sun peng (Leo) ; Wentland, Harry ; Zhuo, Qingqing ; Siqueira, Rodrigo ; Jacob, Anson ; Pillai, Aurabindo ; Lin, Wayne ; Lakha, Bhawanpreet ; R, Bindu Subject: [PATCH 00/16] DC Patches April 23, 2021 This DC patchset brings along following fixes: * [FW Promotion] Release 0.0.63 * fix HDCP reset sequence on reinitialize * Fix BSOD with NULL check * Added multi instance support for ABM * Revert wait vblank on update dpp clock * skip program clock when allow seamless boot * Add new DP_SEC registers for programming SDP Line number * Add SE_DCN3_REG_LIST for control SDP num * Add new case to get spread spectrum info * fix wrong statement in mst hpd debugfs * Clear MASTER_UPDATE_LOCK_DB_EN when disable doublebuffer lock * Expose internal display flag via debugfs * take max dsc stream bandwidth overhead into account * ddc resource data need to be initialized * avoid to authentication when DEVICE_COUNT=0 .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 22 +++- .../drm/amd/display/dc/bios/bios_parser2.c| 2 + .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 10 +- drivers/gpu/drm/amd/display/dc/core/dc.c | 15 +-- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 22 +++- drivers/gpu/drm/amd/display/dc/dc.h | 3 +- drivers/gpu/drm/amd/display/dc/dc_dsc.h | 5 +- drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c | 30 + .../drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +- .../drm/amd/display/dc/dcn21/dcn21_hwseq.c| 2 +- .../dc/dcn30/dcn30_dio_stream_encoder.h | 4 + .../gpu/drm/amd/display/dc/dcn30/dcn30_optc.c | 2 +- .../drm/amd/display/dc/dcn30/dcn30_resource.c | 2 +- drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 113 ++ drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c | 43 --- drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h | 2 - .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 88 -- .../gpu/drm/amd/display/modules/hdcp/hdcp.c | 1 - .../display/modules/hdcp/hdcp1_execution.c| 5 + .../display/modules/hdcp/hdcp2_execution.c| 5 + 20 files changed, 260 insertions(+), 118 deletions(-) -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfxdata=04%7C01%7Cdaniel.wheeler%40amd.com%7C494cc017f48448e2eaa108d90601092e%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637547423797664776%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000sdata=83RjQqvp8QA5E%2BiHR5jpy5PJaZOcIWDQ6tSkx6UxDPc%3Dreserved=0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amd/pm: Update energy_accumulator in gpu metrics
Signed-off-by: Harish Kasiviswanathan --- drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c index dcbe3a72da09..1f02e4ee2909 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c @@ -1657,7 +1657,8 @@ static ssize_t aldebaran_get_gpu_metrics(struct smu_context *smu, gpu_metrics->average_mm_activity = 0; gpu_metrics->average_socket_power = metrics.AverageSocketPower; - gpu_metrics->energy_accumulator = 0; + gpu_metrics->energy_accumulator = metrics.EnergyAcc64bitHigh << 32 | + metrics.EnergyAcc64bitLow; gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency; gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency; -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu: Register VGA clients after init can no longer fail
On Wed, Apr 21, 2021 at 1:43 PM Kai-Heng Feng
wrote:
>
> When an amdgpu device fails to init, it makes another VGA device cause
> kernel splat:
> kernel: amdgpu :08:00.0: amdgpu: amdgpu_device_ip_init failed
> kernel: amdgpu :08:00.0: amdgpu: Fatal error during GPU init
> kernel: amdgpu: probe of :08:00.0 failed with error -110
> ...
> kernel: amdgpu :01:00.0: vgaarb: changed VGA decodes:
> olddecodes=io+mem,decodes=none:owns=none
> kernel: BUG: kernel NULL pointer dereference, address: 0018
> kernel: #PF: supervisor read access in kernel mode
> kernel: #PF: error_code(0x) - not-present page
> kernel: PGD 0 P4D 0
> kernel: Oops: [#1] SMP NOPTI
> kernel: CPU: 6 PID: 1080 Comm: Xorg Tainted: GW 5.12.0-rc8+
> #12
> kernel: Hardware name: HP HP EliteDesk 805 G6/872B, BIOS S09 Ver. 02.02.00
> 12/30/2020
> kernel: RIP: 0010:amdgpu_device_vga_set_decode+0x13/0x30 [amdgpu]
> kernel: Code: 06 31 c0 c3 b8 ea ff ff ff 5d c3 66 2e 0f 1f 84 00 00 00 00 00
> 66 90 0f 1f 44 00 00 55 48 8b 87 90 06 00 00 48 89 e5 53 89 f3 <48> 8b 40 18
> 40 0f b6 f6 e8 40 58 39 fd 80 fb 01 5b 5d 19 c0 83 e0
> kernel: RSP: 0018:ae3c0246bd68 EFLAGS: 00010002
> kernel: RAX: RBX: RCX:
> kernel: RDX: 8dd1af5a8560 RSI: RDI: 8dce8c16
> kernel: RBP: ae3c0246bd70 R08: 8dd1af5985c0 R09: ae3c0246ba38
> kernel: R10: 0001 R11: 0001 R12: 0246
> kernel: R13: R14: 0003 R15: 8dce8149
> kernel: FS: 7f9303d8fa40() GS:8dd1af58()
> knlGS:
> kernel: CS: 0010 DS: ES: CR0: 80050033
> kernel: CR2: 0018 CR3: 000103cfa000 CR4: 00350ee0
> kernel: Call Trace:
> kernel: vga_arbiter_notify_clients.part.0+0x4a/0x80
> kernel: vga_get+0x17f/0x1c0
> kernel: vga_arb_write+0x121/0x6a0
> kernel: ? apparmor_file_permission+0x1c/0x20
> kernel: ? security_file_permission+0x30/0x180
> kernel: vfs_write+0xca/0x280
> kernel: ksys_write+0x67/0xe0
> kernel: __x64_sys_write+0x1a/0x20
> kernel: do_syscall_64+0x38/0x90
> kernel: entry_SYSCALL_64_after_hwframe+0x44/0xae
> kernel: RIP: 0033:0x7f93041e02f7
> kernel: Code: 75 05 48 83 c4 58 c3 e8 f7 33 ff ff 0f 1f 80 00 00 00 00 f3 0f
> 1e fa 64 8b 04 25 18 00 00 00 85 c0 75 10 b8 01 00 00 00 0f 05 <48> 3d 00 f0
> ff ff 77 51 c3 48 83 ec 28 48 89 54 24 18 48 89 74 24
> kernel: RSP: 002b:7fff60e49b28 EFLAGS: 0246 ORIG_RAX: 0001
> kernel: RAX: ffda RBX: 000b RCX: 7f93041e02f7
> kernel: RDX: 000b RSI: 7fff60e49b40 RDI: 000f
> kernel: RBP: 7fff60e49b40 R08: R09: 7fff60e499d0
> kernel: R10: 7f93049350b5 R11: 0246 R12: 56111d45e808
> kernel: R13: R14: 56111d45e7f8 R15: 56111d46c980
> kernel: Modules linked in: nls_iso8859_1 snd_hda_codec_realtek
> snd_hda_codec_generic ledtrig_audio snd_hda_codec_hdmi snd_hda_intel
> snd_intel_dspcfg snd_hda_codec snd_hwdep snd_hda_core snd_pcm snd_seq
> input_leds snd_seq_device snd_timer snd soundcore joydev kvm_amd serio_raw
> k10temp mac_hid hp_wmi ccp kvm sparse_keymap wmi_bmof ucsi_acpi efi_pstore
> typec_ucsi rapl typec video wmi sch_fq_codel parport_pc ppdev lp parport
> ip_tables x_tables autofs4 btrfs blake2b_generic zstd_compress raid10 raid456
> async_raid6_recov async_memcpy async_pq async_xor async_tx libcrc32c xor
> raid6_pq raid1 raid0 multipath linear dm_mirror dm_region_hash dm_log
> hid_generic usbhid hid amdgpu drm_ttm_helper ttm iommu_v2 gpu_sched
> i2c_algo_bit drm_kms_helper syscopyarea sysfillrect crct10dif_pclmul
> sysimgblt crc32_pclmul fb_sys_fops ghash_clmulni_intel cec rc_core
> aesni_intel crypto_simd psmouse cryptd r8169 i2c_piix4 drm ahci xhci_pci
> realtek libahci xhci_pci_renesas gpio_amdpt gpio_generic
> kernel: CR2: 0018
> kernel: ---[ end trace 76d04313d4214c51 ]---
>
> Commit 4192f7b57689 ("drm/amdgpu: unmap register bar on device init
> failure") makes amdgpu_driver_unload_kms() skips amdgpu_device_fini(),
> so the VGA clients remain registered. So when
> vga_arbiter_notify_clients() iterates over registered clients, it causes
> NULL pointer dereference.
>
> Since there's no reason to register VGA clients that early, so solve
> the issue by putting them after all the goto cleanups.
>
> Fixes: 4192f7b57689 ("drm/amdgpu: unmap register bar on device init failure")
> Signed-off-by: Kai-Heng Feng
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 26 +++---
> 1 file changed, 13 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index b4ad1c055c70..115a7699e11e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -3410,19
[PATCH v4 17/17] drm/dp_mst: Convert drm_dp_mst_topology.c to drm_err()/drm_dbg*()
And finally, convert all of the code in drm_dp_mst_topology.c over to using
drm_err() and drm_dbg*(). Note that this refactor would have been a lot
more complicated to have tried writing a coccinelle script for, so this
whole thing was done by hand.
v2:
* Fix line-wrapping in drm_dp_mst_atomic_check_mstb_bw_limit()
Signed-off-by: Lyude Paul
Cc: Robert Foss
Reviewed-by: Robert Foss
---
drivers/gpu/drm/drm_dp_mst_topology.c | 368 +-
1 file changed, 187 insertions(+), 181 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c
b/drivers/gpu/drm/drm_dp_mst_topology.c
index 9bac5bd050ab..5539a91b4031 100644
--- a/drivers/gpu/drm/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/drm_dp_mst_topology.c
@@ -286,7 +286,8 @@ static void drm_dp_encode_sideband_msg_hdr(struct
drm_dp_sideband_msg_hdr *hdr,
*len = idx;
}
-static bool drm_dp_decode_sideband_msg_hdr(struct drm_dp_sideband_msg_hdr *hdr,
+static bool drm_dp_decode_sideband_msg_hdr(const struct
drm_dp_mst_topology_mgr *mgr,
+ struct drm_dp_sideband_msg_hdr *hdr,
u8 *buf, int buflen, u8 *hdrlen)
{
u8 crc4;
@@ -303,7 +304,7 @@ static bool drm_dp_decode_sideband_msg_hdr(struct
drm_dp_sideband_msg_hdr *hdr,
crc4 = drm_dp_msg_header_crc4(buf, (len * 2) - 1);
if ((crc4 & 0xf) != (buf[len - 1] & 0xf)) {
- DRM_DEBUG_KMS("crc4 mismatch 0x%x 0x%x\n", crc4, buf[len - 1]);
+ drm_dbg_kms(mgr->dev, "crc4 mismatch 0x%x 0x%x\n", crc4,
buf[len - 1]);
return false;
}
@@ -789,7 +790,8 @@ static bool drm_dp_sideband_append_payload(struct
drm_dp_sideband_msg_rx *msg,
return true;
}
-static bool drm_dp_sideband_parse_link_address(struct drm_dp_sideband_msg_rx
*raw,
+static bool drm_dp_sideband_parse_link_address(const struct
drm_dp_mst_topology_mgr *mgr,
+ struct drm_dp_sideband_msg_rx
*raw,
struct
drm_dp_sideband_msg_reply_body *repmsg)
{
int idx = 1;
@@ -1014,7 +1016,8 @@ drm_dp_sideband_parse_query_stream_enc_status(
return true;
}
-static bool drm_dp_sideband_parse_reply(struct drm_dp_sideband_msg_rx *raw,
+static bool drm_dp_sideband_parse_reply(const struct drm_dp_mst_topology_mgr
*mgr,
+ struct drm_dp_sideband_msg_rx *raw,
struct drm_dp_sideband_msg_reply_body
*msg)
{
memset(msg, 0, sizeof(*msg));
@@ -1030,7 +1033,7 @@ static bool drm_dp_sideband_parse_reply(struct
drm_dp_sideband_msg_rx *raw,
switch (msg->req_type) {
case DP_LINK_ADDRESS:
- return drm_dp_sideband_parse_link_address(raw, msg);
+ return drm_dp_sideband_parse_link_address(mgr, raw, msg);
case DP_QUERY_PAYLOAD:
return drm_dp_sideband_parse_query_payload_ack(raw, msg);
case DP_REMOTE_DPCD_READ:
@@ -1053,14 +1056,16 @@ static bool drm_dp_sideband_parse_reply(struct
drm_dp_sideband_msg_rx *raw,
case DP_QUERY_STREAM_ENC_STATUS:
return drm_dp_sideband_parse_query_stream_enc_status(raw, msg);
default:
- DRM_ERROR("Got unknown reply 0x%02x (%s)\n", msg->req_type,
- drm_dp_mst_req_type_str(msg->req_type));
+ drm_err(mgr->dev, "Got unknown reply 0x%02x (%s)\n",
+ msg->req_type, drm_dp_mst_req_type_str(msg->req_type));
return false;
}
}
-static bool drm_dp_sideband_parse_connection_status_notify(struct
drm_dp_sideband_msg_rx *raw,
- struct
drm_dp_sideband_msg_req_body *msg)
+static bool
+drm_dp_sideband_parse_connection_status_notify(const struct
drm_dp_mst_topology_mgr *mgr,
+ struct drm_dp_sideband_msg_rx
*raw,
+ struct
drm_dp_sideband_msg_req_body *msg)
{
int idx = 1;
@@ -1082,12 +1087,14 @@ static bool
drm_dp_sideband_parse_connection_status_notify(struct drm_dp_sideban
idx++;
return true;
fail_len:
- DRM_DEBUG_KMS("connection status reply parse length fail %d %d\n", idx,
raw->curlen);
+ drm_dbg_kms(mgr->dev, "connection status reply parse length fail %d
%d\n",
+ idx, raw->curlen);
return false;
}
-static bool drm_dp_sideband_parse_resource_status_notify(struct
drm_dp_sideband_msg_rx *raw,
- struct
drm_dp_sideband_msg_req_body *msg)
+static bool drm_dp_sideband_parse_resource_status_notify(const struct
drm_dp_mst_topology_mgr *mgr,
+struct
drm_dp_sideband_msg_rx *raw,
+struct
[PATCH v4 15/17] drm/dp: Convert drm_dp_helper.c to using drm_err/drm_dbg_*()
Now that we've added a back-pointer to drm_device to drm_dp_aux, made
drm_dp_aux available to any functions in drm_dp_helper.c which need to
print to the kernel log, and ensured all of our logging uses a consistent
format, let's do the final step of the conversion and actually move
everything over to using drm_err() and drm_dbg_*().
This was done by using the following cocci script:
@@
expression list expr;
@@
(
- DRM_DEBUG_KMS(expr);
+ drm_dbg_kms(aux->drm_dev, expr);
|
- DRM_DEBUG_DP(expr);
+ drm_dbg_dp(aux->drm_dev, expr);
|
- DRM_DEBUG_ATOMIC(expr);
+ drm_dbg_atomic(aux->drm_dev, expr);
|
- DRM_DEBUG_KMS_RATELIMITED(expr);
+ drm_dbg_kms_ratelimited(aux->drm_dev, expr);
|
- DRM_ERROR(expr);
+ drm_err(aux->drm_dev, expr);
)
Followed by correcting the resulting line-wrapping in the results by hand.
v2:
* Fix indenting in drm_dp_dump_access
Signed-off-by: Lyude Paul
Cc: Robert Foss
Reviewed-by: Robert Foss
---
drivers/gpu/drm/drm_dp_helper.c | 121
1 file changed, 59 insertions(+), 62 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index b50e572b544d..cb56d74e9d38 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -139,8 +139,8 @@ void drm_dp_link_train_clock_recovery_delay(const struct
drm_dp_aux *aux,
DP_TRAINING_AUX_RD_MASK;
if (rd_interval > 4)
- DRM_DEBUG_KMS("%s: AUX interval %lu, out of range (max 4)\n",
- aux->name, rd_interval);
+ drm_dbg_kms(aux->drm_dev, "%s: AUX interval %lu, out of range
(max 4)\n",
+ aux->name, rd_interval);
if (rd_interval == 0 || dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
rd_interval = 100;
@@ -155,8 +155,8 @@ static void __drm_dp_link_train_channel_eq_delay(const
struct drm_dp_aux *aux,
unsigned long rd_interval)
{
if (rd_interval > 4)
- DRM_DEBUG_KMS("%s: AUX interval %lu, out of range (max 4)\n",
- aux->name, rd_interval);
+ drm_dbg_kms(aux->drm_dev, "%s: AUX interval %lu, out of range
(max 4)\n",
+ aux->name, rd_interval);
if (rd_interval == 0)
rd_interval = 400;
@@ -220,11 +220,11 @@ drm_dp_dump_access(const struct drm_dp_aux *aux,
const char *arrow = request == DP_AUX_NATIVE_READ ? "->" : "<-";
if (ret > 0)
- DRM_DEBUG_DP("%s: 0x%05x AUX %s (ret=%3d) %*ph\n",
-aux->name, offset, arrow, ret, min(ret, 20),
buffer);
+ drm_dbg_dp(aux->drm_dev, "%s: 0x%05x AUX %s (ret=%3d) %*ph\n",
+ aux->name, offset, arrow, ret, min(ret, 20), buffer);
else
- DRM_DEBUG_DP("%s: 0x%05x AUX %s (ret=%3d)\n",
-aux->name, offset, arrow, ret);
+ drm_dbg_dp(aux->drm_dev, "%s: 0x%05x AUX %s (ret=%3d)\n",
+ aux->name, offset, arrow, ret);
}
/**
@@ -287,8 +287,8 @@ static int drm_dp_dpcd_access(struct drm_dp_aux *aux, u8
request,
err = ret;
}
- DRM_DEBUG_KMS("%s: Too many retries, giving up. First error: %d\n",
- aux->name, err);
+ drm_dbg_kms(aux->drm_dev, "%s: Too many retries, giving up. First
error: %d\n",
+ aux->name, err);
ret = err;
unlock:
@@ -524,44 +524,44 @@ bool drm_dp_send_real_edid_checksum(struct drm_dp_aux
*aux,
if (drm_dp_dpcd_read(aux, DP_DEVICE_SERVICE_IRQ_VECTOR,
_test_req, 1) < 1) {
- DRM_ERROR("%s: DPCD failed read at register 0x%x\n",
- aux->name, DP_DEVICE_SERVICE_IRQ_VECTOR);
+ drm_err(aux->drm_dev, "%s: DPCD failed read at register 0x%x\n",
+ aux->name, DP_DEVICE_SERVICE_IRQ_VECTOR);
return false;
}
auto_test_req &= DP_AUTOMATED_TEST_REQUEST;
if (drm_dp_dpcd_read(aux, DP_TEST_REQUEST, _edid_read, 1) < 1) {
- DRM_ERROR("%s: DPCD failed read at register 0x%x\n",
- aux->name, DP_TEST_REQUEST);
+ drm_err(aux->drm_dev, "%s: DPCD failed read at register 0x%x\n",
+ aux->name, DP_TEST_REQUEST);
return false;
}
link_edid_read &= DP_TEST_LINK_EDID_READ;
if (!auto_test_req || !link_edid_read) {
- DRM_DEBUG_KMS("%s: Source DUT does not support
TEST_EDID_READ\n",
- aux->name);
+ drm_dbg_kms(aux->drm_dev, "%s: Source DUT does not support
TEST_EDID_READ\n",
+ aux->name);
return false;
}
if (drm_dp_dpcd_write(aux, DP_DEVICE_SERVICE_IRQ_VECTOR,
[PATCH v4 13/17] drm/dp_mst: Pass drm_dp_mst_topology_mgr to drm_dp_get_vc_payload_bw()
Since this is one of the few functions in drm_dp_mst_topology.c that
doesn't have any way of getting access to a drm_device, let's pass the
drm_dp_mst_topology_mgr down to this function so that it can use
drm_dbg_kms().
Signed-off-by: Lyude Paul
---
drivers/gpu/drm/drm_dp_mst_topology.c | 7 +--
drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 ++-
include/drm/drm_dp_mst_helper.h | 3 ++-
3 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c
b/drivers/gpu/drm/drm_dp_mst_topology.c
index 276f7f054d62..9bac5bd050ab 100644
--- a/drivers/gpu/drm/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/drm_dp_mst_topology.c
@@ -3638,6 +3638,7 @@ static int drm_dp_send_up_ack_reply(struct
drm_dp_mst_topology_mgr *mgr,
/**
* drm_dp_get_vc_payload_bw - get the VC payload BW for an MST link
+ * @mgr: The _dp_mst_topology_mgr to use
* @link_rate: link rate in 10kbits/s units
* @link_lane_count: lane count
*
@@ -3646,7 +3647,8 @@ static int drm_dp_send_up_ack_reply(struct
drm_dp_mst_topology_mgr *mgr,
* convert the number of PBNs required for a given stream to the number of
* timeslots this stream requires in each MTP.
*/
-int drm_dp_get_vc_payload_bw(int link_rate, int link_lane_count)
+int drm_dp_get_vc_payload_bw(const struct drm_dp_mst_topology_mgr *mgr,
+int link_rate, int link_lane_count)
{
if (link_rate == 0 || link_lane_count == 0)
DRM_DEBUG_KMS("invalid link rate/lane count: (%d / %d)\n",
@@ -3711,7 +3713,8 @@ int drm_dp_mst_topology_mgr_set_mst(struct
drm_dp_mst_topology_mgr *mgr, bool ms
goto out_unlock;
}
- mgr->pbn_div =
drm_dp_get_vc_payload_bw(drm_dp_bw_code_to_link_rate(mgr->dpcd[1]),
+ mgr->pbn_div = drm_dp_get_vc_payload_bw(mgr,
+
drm_dp_bw_code_to_link_rate(mgr->dpcd[1]),
mgr->dpcd[2] &
DP_MAX_LANE_COUNT_MASK);
if (mgr->pbn_div == 0) {
ret = -EINVAL;
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 180f97cd74cb..eb04b3cefda2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -70,7 +70,8 @@ static int intel_dp_mst_compute_link_config(struct
intel_encoder *encoder,
slots = drm_dp_atomic_find_vcpi_slots(state, _dp->mst_mgr,
connector->port,
crtc_state->pbn,
-
drm_dp_get_vc_payload_bw(crtc_state->port_clock,
+
drm_dp_get_vc_payload_bw(_dp->mst_mgr,
+
crtc_state->port_clock,
crtc_state->lane_count));
if (slots == -EDEADLK)
return slots;
diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h
index bd1c39907b92..20dc705642bd 100644
--- a/include/drm/drm_dp_mst_helper.h
+++ b/include/drm/drm_dp_mst_helper.h
@@ -783,7 +783,8 @@ drm_dp_mst_detect_port(struct drm_connector *connector,
struct edid *drm_dp_mst_get_edid(struct drm_connector *connector, struct
drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port);
-int drm_dp_get_vc_payload_bw(int link_rate, int link_lane_count);
+int drm_dp_get_vc_payload_bw(const struct drm_dp_mst_topology_mgr *mgr,
+int link_rate, int link_lane_count);
int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc);
--
2.30.2
___
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[PATCH v4 16/17] drm/dp_dual_mode: Convert drm_dp_dual_mode_helper.c to using drm_err/drm_dbg_kms()
Next step in the conversion, move everything in drm_dp_dual_mode_helper.c
over to using drm_err() and drm_dbg_kms(). This was done using the
following cocci script:
@@
expression list expr;
@@
(
- DRM_DEBUG_KMS(expr);
+ drm_dbg_kms(dev, expr);
|
- DRM_ERROR(expr);
+ drm_err(dev, expr);
)
And correcting the indentation of the resulting code by hand.
Signed-off-by: Lyude Paul
---
drivers/gpu/drm/drm_dp_dual_mode_helper.c | 45 +++
1 file changed, 21 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_dual_mode_helper.c
b/drivers/gpu/drm/drm_dp_dual_mode_helper.c
index dbf9b1fdec63..9faf49354cab 100644
--- a/drivers/gpu/drm/drm_dp_dual_mode_helper.c
+++ b/drivers/gpu/drm/drm_dp_dual_mode_helper.c
@@ -27,6 +27,7 @@
#include
#include
+#include
#include
#include
@@ -202,8 +203,8 @@ enum drm_dp_dual_mode_type drm_dp_dual_mode_detect(const
struct drm_device *dev,
*/
ret = drm_dp_dual_mode_read(adapter, DP_DUAL_MODE_HDMI_ID,
hdmi_id, sizeof(hdmi_id));
- DRM_DEBUG_KMS("DP dual mode HDMI ID: %*pE (err %zd)\n",
- ret ? 0 : (int)sizeof(hdmi_id), hdmi_id, ret);
+ drm_dbg_kms(dev, "DP dual mode HDMI ID: %*pE (err %zd)\n",
+ ret ? 0 : (int)sizeof(hdmi_id), hdmi_id, ret);
if (ret)
return DRM_DP_DUAL_MODE_UNKNOWN;
@@ -221,8 +222,7 @@ enum drm_dp_dual_mode_type drm_dp_dual_mode_detect(const
struct drm_device *dev,
*/
ret = drm_dp_dual_mode_read(adapter, DP_DUAL_MODE_ADAPTOR_ID,
_id, sizeof(adaptor_id));
- DRM_DEBUG_KMS("DP dual mode adaptor ID: %02x (err %zd)\n",
- adaptor_id, ret);
+ drm_dbg_kms(dev, "DP dual mode adaptor ID: %02x (err %zd)\n",
adaptor_id, ret);
if (ret == 0) {
if (is_lspcon_adaptor(hdmi_id, adaptor_id))
return DRM_DP_DUAL_MODE_LSPCON;
@@ -238,8 +238,7 @@ enum drm_dp_dual_mode_type drm_dp_dual_mode_detect(const
struct drm_device *dev,
* that we may have misdetected the type.
*/
if (!is_type1_adaptor(adaptor_id) && adaptor_id != hdmi_id[0])
- DRM_ERROR("Unexpected DP dual mode adaptor ID %02x\n",
- adaptor_id);
+ drm_err(dev, "Unexpected DP dual mode adaptor ID
%02x\n", adaptor_id);
}
@@ -286,7 +285,7 @@ int drm_dp_dual_mode_max_tmds_clock(const struct drm_device
*dev, enum drm_dp_du
ret = drm_dp_dual_mode_read(adapter, DP_DUAL_MODE_MAX_TMDS_CLOCK,
_tmds_clock, sizeof(max_tmds_clock));
if (ret || max_tmds_clock == 0x00 || max_tmds_clock == 0xff) {
- DRM_DEBUG_KMS("Failed to query max TMDS clock\n");
+ drm_dbg_kms(dev, "Failed to query max TMDS clock\n");
return 165000;
}
@@ -326,7 +325,7 @@ int drm_dp_dual_mode_get_tmds_output(const struct
drm_device *dev,
ret = drm_dp_dual_mode_read(adapter, DP_DUAL_MODE_TMDS_OEN,
_oen, sizeof(tmds_oen));
if (ret) {
- DRM_DEBUG_KMS("Failed to query state of TMDS output buffers\n");
+ drm_dbg_kms(dev, "Failed to query state of TMDS output
buffers\n");
return ret;
}
@@ -372,18 +371,17 @@ int drm_dp_dual_mode_set_tmds_output(const struct
drm_device *dev, enum drm_dp_d
ret = drm_dp_dual_mode_write(adapter, DP_DUAL_MODE_TMDS_OEN,
_oen, sizeof(tmds_oen));
if (ret) {
- DRM_DEBUG_KMS("Failed to %s TMDS output buffers (%d
attempts)\n",
- enable ? "enable" : "disable",
- retry + 1);
+ drm_dbg_kms(dev, "Failed to %s TMDS output buffers (%d
attempts)\n",
+ enable ? "enable" : "disable", retry + 1);
return ret;
}
ret = drm_dp_dual_mode_read(adapter, DP_DUAL_MODE_TMDS_OEN,
, sizeof(tmp));
if (ret) {
- DRM_DEBUG_KMS("I2C read failed during TMDS output
buffer %s (%d attempts)\n",
- enable ? "enabling" : "disabling",
- retry + 1);
+ drm_dbg_kms(dev,
+ "I2C read failed during TMDS output buffer
%s (%d attempts)\n",
+ enable ? "enabling" : "disabling", retry +
1);
return ret;
}
@@ -391,8 +389,8 @@ int drm_dp_dual_mode_set_tmds_output(const struct
drm_device *dev, enum drm_dp_d
return 0;
}
-
[PATCH v4 14/17] drm/print: Handle potentially NULL drm_devices in drm_dbg_*
While this shouldn't really be something that happens all that often, since we're going to be using the drm_dbg_* log helpers in DRM helpers it's technically possible that a driver could use an AUX adapter before it's been associated with it's respective drm_device. While drivers should take care to avoid this, there's likely going to be situations where it's difficult to workaround. And since other logging helpers in the kernel tend to be OK with NULL pointers (for instance, passing a NULL pointer to a "%s" argument for a printk-like function in the kernel doesn't break anything), we should do the same for ours. Signed-off-by: Lyude Paul --- include/drm/drm_print.h | 20 ++-- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/include/drm/drm_print.h b/include/drm/drm_print.h index a3c58c941bdc..9b66be54dd16 100644 --- a/include/drm/drm_print.h +++ b/include/drm/drm_print.h @@ -443,25 +443,25 @@ void drm_dev_dbg(const struct device *dev, enum drm_debug_category category, #define drm_dbg_core(drm, fmt, ...)\ - drm_dev_dbg((drm)->dev, DRM_UT_CORE, fmt, ##__VA_ARGS__) + drm_dev_dbg((drm) ? (drm)->dev : NULL, DRM_UT_CORE, fmt, ##__VA_ARGS__) #define drm_dbg(drm, fmt, ...) \ - drm_dev_dbg((drm)->dev, DRM_UT_DRIVER, fmt, ##__VA_ARGS__) + drm_dev_dbg((drm) ? (drm)->dev : NULL, DRM_UT_DRIVER, fmt, ##__VA_ARGS__) #define drm_dbg_kms(drm, fmt, ...) \ - drm_dev_dbg((drm)->dev, DRM_UT_KMS, fmt, ##__VA_ARGS__) + drm_dev_dbg((drm) ? (drm)->dev : NULL, DRM_UT_KMS, fmt, ##__VA_ARGS__) #define drm_dbg_prime(drm, fmt, ...) \ - drm_dev_dbg((drm)->dev, DRM_UT_PRIME, fmt, ##__VA_ARGS__) + drm_dev_dbg((drm) ? (drm)->dev : NULL, DRM_UT_PRIME, fmt, ##__VA_ARGS__) #define drm_dbg_atomic(drm, fmt, ...) \ - drm_dev_dbg((drm)->dev, DRM_UT_ATOMIC, fmt, ##__VA_ARGS__) + drm_dev_dbg((drm) ? (drm)->dev : NULL, DRM_UT_ATOMIC, fmt, ##__VA_ARGS__) #define drm_dbg_vbl(drm, fmt, ...) \ - drm_dev_dbg((drm)->dev, DRM_UT_VBL, fmt, ##__VA_ARGS__) + drm_dev_dbg((drm) ? (drm)->dev : NULL, DRM_UT_VBL, fmt, ##__VA_ARGS__) #define drm_dbg_state(drm, fmt, ...) \ - drm_dev_dbg((drm)->dev, DRM_UT_STATE, fmt, ##__VA_ARGS__) + drm_dev_dbg((drm) ? (drm)->dev : NULL, DRM_UT_STATE, fmt, ##__VA_ARGS__) #define drm_dbg_lease(drm, fmt, ...) \ - drm_dev_dbg((drm)->dev, DRM_UT_LEASE, fmt, ##__VA_ARGS__) + drm_dev_dbg((drm) ? (drm)->dev : NULL, DRM_UT_LEASE, fmt, ##__VA_ARGS__) #define drm_dbg_dp(drm, fmt, ...) \ - drm_dev_dbg((drm)->dev, DRM_UT_DP, fmt, ##__VA_ARGS__) + drm_dev_dbg((drm) ? (drm)->dev : NULL, DRM_UT_DP, fmt, ##__VA_ARGS__) #define drm_dbg_drmres(drm, fmt, ...) \ - drm_dev_dbg((drm)->dev, DRM_UT_DRMRES, fmt, ##__VA_ARGS__) + drm_dev_dbg((drm) ? (drm)->dev : NULL, DRM_UT_DRMRES, fmt, ##__VA_ARGS__) /* -- 2.30.2 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH v4 11/17] drm/dp_dual_mode: Pass drm_device to drm_dp_dual_mode_get_tmds_output()
Another function to pass drm_device * down to so we can start using the
drm_dbg_*() in the DRM DP helpers.
Signed-off-by: Lyude Paul
---
drivers/gpu/drm/drm_dp_dual_mode_helper.c | 5 +++--
include/drm/drm_dp_dual_mode_helper.h | 2 +-
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_dual_mode_helper.c
b/drivers/gpu/drm/drm_dp_dual_mode_helper.c
index 4a26b3e1f78f..c9c2952bcad2 100644
--- a/drivers/gpu/drm/drm_dp_dual_mode_helper.c
+++ b/drivers/gpu/drm/drm_dp_dual_mode_helper.c
@@ -296,6 +296,7 @@ EXPORT_SYMBOL(drm_dp_dual_mode_max_tmds_clock);
/**
* drm_dp_dual_mode_get_tmds_output - Get the state of the TMDS output buffers
in the DP dual mode adaptor
+ * @dev: _device to use
* @type: DP dual mode adaptor type
* @adapter: I2C adapter for the DDC bus
* @enabled: current state of the TMDS output buffers
@@ -310,8 +311,8 @@ EXPORT_SYMBOL(drm_dp_dual_mode_max_tmds_clock);
* Returns:
* 0 on success, negative error code on failure
*/
-int drm_dp_dual_mode_get_tmds_output(enum drm_dp_dual_mode_type type,
-struct i2c_adapter *adapter,
+int drm_dp_dual_mode_get_tmds_output(const struct drm_device *dev,
+enum drm_dp_dual_mode_type type, struct
i2c_adapter *adapter,
bool *enabled)
{
uint8_t tmds_oen;
diff --git a/include/drm/drm_dp_dual_mode_helper.h
b/include/drm/drm_dp_dual_mode_helper.h
index aabf9c951380..01eec9ff5962 100644
--- a/include/drm/drm_dp_dual_mode_helper.h
+++ b/include/drm/drm_dp_dual_mode_helper.h
@@ -108,7 +108,7 @@ enum drm_dp_dual_mode_type
drm_dp_dual_mode_detect(const struct drm_device *dev, struct i2c_adapter
*adapter);
int drm_dp_dual_mode_max_tmds_clock(const struct drm_device *dev, enum
drm_dp_dual_mode_type type,
struct i2c_adapter *adapter);
-int drm_dp_dual_mode_get_tmds_output(enum drm_dp_dual_mode_type type,
+int drm_dp_dual_mode_get_tmds_output(const struct drm_device *dev, enum
drm_dp_dual_mode_type type,
struct i2c_adapter *adapter, bool
*enabled);
int drm_dp_dual_mode_set_tmds_output(const struct drm_device *dev, enum
drm_dp_dual_mode_type type,
struct i2c_adapter *adapter, bool enable);
--
2.30.2
___
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[PATCH v4 10/17] drm/dp_dual_mode: Pass drm_device to drm_dp_dual_mode_max_tmds_clock()
Another function we need to pass drm_device down to in order to start using
drm_dbg_*().
Signed-off-by: Lyude Paul
---
drivers/gpu/drm/drm_dp_dual_mode_helper.c | 3 ++-
drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +-
include/drm/drm_dp_dual_mode_helper.h | 2 +-
3 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_dual_mode_helper.c
b/drivers/gpu/drm/drm_dp_dual_mode_helper.c
index a63d7de85309..4a26b3e1f78f 100644
--- a/drivers/gpu/drm/drm_dp_dual_mode_helper.c
+++ b/drivers/gpu/drm/drm_dp_dual_mode_helper.c
@@ -252,6 +252,7 @@ EXPORT_SYMBOL(drm_dp_dual_mode_detect);
/**
* drm_dp_dual_mode_max_tmds_clock - Max TMDS clock for DP dual mode adaptor
+ * @dev: _device to use
* @type: DP dual mode adaptor type
* @adapter: I2C adapter for the DDC bus
*
@@ -265,7 +266,7 @@ EXPORT_SYMBOL(drm_dp_dual_mode_detect);
* Returns:
* Maximum supported TMDS clock rate for the DP dual mode adaptor in kHz.
*/
-int drm_dp_dual_mode_max_tmds_clock(enum drm_dp_dual_mode_type type,
+int drm_dp_dual_mode_max_tmds_clock(const struct drm_device *dev, enum
drm_dp_dual_mode_type type,
struct i2c_adapter *adapter)
{
uint8_t max_tmds_clock;
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index fc3e7a9396b5..46de56af33db 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2256,7 +2256,7 @@ intel_hdmi_dp_dual_mode_detect(struct drm_connector
*connector, bool has_edid)
hdmi->dp_dual_mode.type = type;
hdmi->dp_dual_mode.max_tmds_clock =
- drm_dp_dual_mode_max_tmds_clock(type, adapter);
+ drm_dp_dual_mode_max_tmds_clock(_priv->drm, type, adapter);
drm_dbg_kms(_priv->drm,
"DP dual mode adaptor (%s) detected (max TMDS clock: %d
kHz)\n",
diff --git a/include/drm/drm_dp_dual_mode_helper.h
b/include/drm/drm_dp_dual_mode_helper.h
index 8cb0dcd98a99..aabf9c951380 100644
--- a/include/drm/drm_dp_dual_mode_helper.h
+++ b/include/drm/drm_dp_dual_mode_helper.h
@@ -106,7 +106,7 @@ enum drm_dp_dual_mode_type {
enum drm_dp_dual_mode_type
drm_dp_dual_mode_detect(const struct drm_device *dev, struct i2c_adapter
*adapter);
-int drm_dp_dual_mode_max_tmds_clock(enum drm_dp_dual_mode_type type,
+int drm_dp_dual_mode_max_tmds_clock(const struct drm_device *dev, enum
drm_dp_dual_mode_type type,
struct i2c_adapter *adapter);
int drm_dp_dual_mode_get_tmds_output(enum drm_dp_dual_mode_type type,
struct i2c_adapter *adapter, bool
*enabled);
--
2.30.2
___
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[PATCH v4 12/17] drm/dp_dual_mode: Pass drm_device to drm_lspcon_(get|set)_mode()
So that we can start using drm_dbg_*() throughout the DRM DP helpers.
Signed-off-by: Lyude Paul
---
drivers/gpu/drm/drm_dp_dual_mode_helper.c | 8 +---
drivers/gpu/drm/i915/display/intel_lspcon.c | 12 +++-
include/drm/drm_dp_dual_mode_helper.h | 4 ++--
3 files changed, 14 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_dual_mode_helper.c
b/drivers/gpu/drm/drm_dp_dual_mode_helper.c
index c9c2952bcad2..dbf9b1fdec63 100644
--- a/drivers/gpu/drm/drm_dp_dual_mode_helper.c
+++ b/drivers/gpu/drm/drm_dp_dual_mode_helper.c
@@ -430,6 +430,7 @@ EXPORT_SYMBOL(drm_dp_get_dual_mode_type_name);
/**
* drm_lspcon_get_mode: Get LSPCON's current mode of operation by
* reading offset (0x80, 0x41)
+ * @dev: _device to use
* @adapter: I2C-over-aux adapter
* @mode: current lspcon mode of operation output variable
*
@@ -437,7 +438,7 @@ EXPORT_SYMBOL(drm_dp_get_dual_mode_type_name);
* 0 on success, sets the current_mode value to appropriate mode
* -error on failure
*/
-int drm_lspcon_get_mode(struct i2c_adapter *adapter,
+int drm_lspcon_get_mode(const struct drm_device *dev, struct i2c_adapter
*adapter,
enum drm_lspcon_mode *mode)
{
u8 data;
@@ -477,13 +478,14 @@ EXPORT_SYMBOL(drm_lspcon_get_mode);
/**
* drm_lspcon_set_mode: Change LSPCON's mode of operation by
* writing offset (0x80, 0x40)
+ * @dev: _device to use
* @adapter: I2C-over-aux adapter
* @mode: required mode of operation
*
* Returns:
* 0 on success, -error on failure/timeout
*/
-int drm_lspcon_set_mode(struct i2c_adapter *adapter,
+int drm_lspcon_set_mode(const struct drm_device *dev, struct i2c_adapter
*adapter,
enum drm_lspcon_mode mode)
{
u8 data = 0;
@@ -508,7 +510,7 @@ int drm_lspcon_set_mode(struct i2c_adapter *adapter,
* so wait and retry until time out or done.
*/
do {
- ret = drm_lspcon_get_mode(adapter, _mode);
+ ret = drm_lspcon_get_mode(dev, adapter, _mode);
if (ret) {
DRM_ERROR("can't confirm LSPCON mode change\n");
return ret;
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c
b/drivers/gpu/drm/i915/display/intel_lspcon.c
index ca25044e7d1b..ec0048024746 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
@@ -139,10 +139,11 @@ void lspcon_detect_hdr_capability(struct intel_lspcon
*lspcon)
static enum drm_lspcon_mode lspcon_get_current_mode(struct intel_lspcon
*lspcon)
{
+ struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon);
enum drm_lspcon_mode current_mode;
- struct i2c_adapter *adapter = _to_intel_dp(lspcon)->aux.ddc;
+ struct i2c_adapter *adapter = _dp->aux.ddc;
- if (drm_lspcon_get_mode(adapter, _mode)) {
+ if (drm_lspcon_get_mode(intel_dp->aux.drm_dev, adapter, _mode))
{
DRM_DEBUG_KMS("Error reading LSPCON mode\n");
return DRM_LSPCON_MODE_INVALID;
}
@@ -175,11 +176,12 @@ static enum drm_lspcon_mode lspcon_wait_mode(struct
intel_lspcon *lspcon,
static int lspcon_change_mode(struct intel_lspcon *lspcon,
enum drm_lspcon_mode mode)
{
+ struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon);
int err;
enum drm_lspcon_mode current_mode;
- struct i2c_adapter *adapter = _to_intel_dp(lspcon)->aux.ddc;
+ struct i2c_adapter *adapter = _dp->aux.ddc;
- err = drm_lspcon_get_mode(adapter, _mode);
+ err = drm_lspcon_get_mode(intel_dp->aux.drm_dev, adapter,
_mode);
if (err) {
DRM_ERROR("Error reading LSPCON mode\n");
return err;
@@ -190,7 +192,7 @@ static int lspcon_change_mode(struct intel_lspcon *lspcon,
return 0;
}
- err = drm_lspcon_set_mode(adapter, mode);
+ err = drm_lspcon_set_mode(intel_dp->aux.drm_dev, adapter, mode);
if (err < 0) {
DRM_ERROR("LSPCON mode change failed\n");
return err;
diff --git a/include/drm/drm_dp_dual_mode_helper.h
b/include/drm/drm_dp_dual_mode_helper.h
index 01eec9ff5962..7ee482265087 100644
--- a/include/drm/drm_dp_dual_mode_helper.h
+++ b/include/drm/drm_dp_dual_mode_helper.h
@@ -114,8 +114,8 @@ int drm_dp_dual_mode_set_tmds_output(const struct
drm_device *dev, enum drm_dp_d
struct i2c_adapter *adapter, bool enable);
const char *drm_dp_get_dual_mode_type_name(enum drm_dp_dual_mode_type type);
-int drm_lspcon_get_mode(struct i2c_adapter *adapter,
+int drm_lspcon_get_mode(const struct drm_device *dev, struct i2c_adapter
*adapter,
enum drm_lspcon_mode *current_mode);
-int drm_lspcon_set_mode(struct i2c_adapter *adapter,
+int drm_lspcon_set_mode(const struct drm_device *dev, struct i2c_adapter
*adapter,
enum drm_lspcon_mode reqd_mode);
[PATCH v4 09/17] drm/dp_dual_mode: Pass drm_device to drm_dp_dual_mode_set_tmds_output()
Another function that we'll need to pass a drm_device (and not drm_dp_aux)
down to so that we can move over to using drm_dbg_*().
Signed-off-by: Lyude Paul
---
drivers/gpu/drm/drm_dp_dual_mode_helper.c | 3 ++-
drivers/gpu/drm/i915/display/intel_hdmi.c | 3 +--
include/drm/drm_dp_dual_mode_helper.h | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_dual_mode_helper.c
b/drivers/gpu/drm/drm_dp_dual_mode_helper.c
index 9ee75c568c37..a63d7de85309 100644
--- a/drivers/gpu/drm/drm_dp_dual_mode_helper.c
+++ b/drivers/gpu/drm/drm_dp_dual_mode_helper.c
@@ -336,6 +336,7 @@ EXPORT_SYMBOL(drm_dp_dual_mode_get_tmds_output);
/**
* drm_dp_dual_mode_set_tmds_output - Enable/disable TMDS output buffers in
the DP dual mode adaptor
+ * @dev: _device to use
* @type: DP dual mode adaptor type
* @adapter: I2C adapter for the DDC bus
* @enable: enable (as opposed to disable) the TMDS output buffers
@@ -349,7 +350,7 @@ EXPORT_SYMBOL(drm_dp_dual_mode_get_tmds_output);
* Returns:
* 0 on success, negative error code on failure
*/
-int drm_dp_dual_mode_set_tmds_output(enum drm_dp_dual_mode_type type,
+int drm_dp_dual_mode_set_tmds_output(const struct drm_device *dev, enum
drm_dp_dual_mode_type type,
struct i2c_adapter *adapter, bool enable)
{
uint8_t tmds_oen = enable ? 0 : DP_DUAL_MODE_TMDS_DISABLE;
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 08fb98dac169..fc3e7a9396b5 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -1251,8 +1251,7 @@ void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi
*hdmi, bool enable)
drm_dbg_kms(_priv->drm, "%s DP dual mode adaptor TMDS output\n",
enable ? "Enabling" : "Disabling");
- drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type,
-adapter, enable);
+ drm_dp_dual_mode_set_tmds_output(_priv->drm,
hdmi->dp_dual_mode.type, adapter, enable);
}
static int intel_hdmi_hdcp_read(struct intel_digital_port *dig_port,
diff --git a/include/drm/drm_dp_dual_mode_helper.h
b/include/drm/drm_dp_dual_mode_helper.h
index 23ce849152f3..8cb0dcd98a99 100644
--- a/include/drm/drm_dp_dual_mode_helper.h
+++ b/include/drm/drm_dp_dual_mode_helper.h
@@ -110,7 +110,7 @@ int drm_dp_dual_mode_max_tmds_clock(enum
drm_dp_dual_mode_type type,
struct i2c_adapter *adapter);
int drm_dp_dual_mode_get_tmds_output(enum drm_dp_dual_mode_type type,
struct i2c_adapter *adapter, bool
*enabled);
-int drm_dp_dual_mode_set_tmds_output(enum drm_dp_dual_mode_type type,
+int drm_dp_dual_mode_set_tmds_output(const struct drm_device *dev, enum
drm_dp_dual_mode_type type,
struct i2c_adapter *adapter, bool enable);
const char *drm_dp_get_dual_mode_type_name(enum drm_dp_dual_mode_type type);
--
2.30.2
___
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH v4 08/17] drm/dp_dual_mode: Pass drm_device to drm_dp_dual_mode_detect()
Since we're about to be using drm_dbg_*() throughout the DP helpers, we'll
need to be able to access the DRM device in the dual mode DP helpers as
well. Note however that since drm_dp_dual_mode_detect() can be called with
DDC adapters that aren't part of a drm_dp_aux struct, we need to pass down
the drm_device to these functions instead of using drm_dp_aux.
Signed-off-by: Lyude Paul
---
drivers/gpu/drm/drm_dp_dual_mode_helper.c | 4 +++-
drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +-
drivers/gpu/drm/i915/display/intel_lspcon.c | 5 +++--
include/drm/drm_dp_dual_mode_helper.h | 4 +++-
4 files changed, 10 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_dual_mode_helper.c
b/drivers/gpu/drm/drm_dp_dual_mode_helper.c
index 1c9ea9f7fdaf..9ee75c568c37 100644
--- a/drivers/gpu/drm/drm_dp_dual_mode_helper.c
+++ b/drivers/gpu/drm/drm_dp_dual_mode_helper.c
@@ -165,6 +165,7 @@ static bool is_lspcon_adaptor(const char
hdmi_id[DP_DUAL_MODE_HDMI_ID_LEN],
/**
* drm_dp_dual_mode_detect - Identify the DP dual mode adaptor
+ * @dev: _device to use
* @adapter: I2C adapter for the DDC bus
*
* Attempt to identify the type of the DP dual mode adaptor used.
@@ -178,7 +179,8 @@ static bool is_lspcon_adaptor(const char
hdmi_id[DP_DUAL_MODE_HDMI_ID_LEN],
* Returns:
* The type of the DP dual mode adaptor used
*/
-enum drm_dp_dual_mode_type drm_dp_dual_mode_detect(struct i2c_adapter *adapter)
+enum drm_dp_dual_mode_type drm_dp_dual_mode_detect(const struct drm_device
*dev,
+ struct i2c_adapter *adapter)
{
char hdmi_id[DP_DUAL_MODE_HDMI_ID_LEN] = {};
uint8_t adaptor_id = 0x00;
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 47a8f0a1c5e2..08fb98dac169 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2224,7 +2224,7 @@ intel_hdmi_dp_dual_mode_detect(struct drm_connector
*connector, bool has_edid)
enum port port = hdmi_to_dig_port(hdmi)->base.port;
struct i2c_adapter *adapter =
intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
- enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter);
+ enum drm_dp_dual_mode_type type =
drm_dp_dual_mode_detect(_priv->drm, adapter);
/*
* Type 1 DVI adaptors are not required to implement any
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c
b/drivers/gpu/drm/i915/display/intel_lspcon.c
index e4ff533e3a69..ca25044e7d1b 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
@@ -221,7 +221,8 @@ static bool lspcon_probe(struct intel_lspcon *lspcon)
{
int retry;
enum drm_dp_dual_mode_type adaptor_type;
- struct i2c_adapter *adapter = _to_intel_dp(lspcon)->aux.ddc;
+ struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon);
+ struct i2c_adapter *adapter = _dp->aux.ddc;
enum drm_lspcon_mode expected_mode;
expected_mode = lspcon_wake_native_aux_ch(lspcon) ?
@@ -232,7 +233,7 @@ static bool lspcon_probe(struct intel_lspcon *lspcon)
if (retry)
usleep_range(500, 1000);
- adaptor_type = drm_dp_dual_mode_detect(adapter);
+ adaptor_type = drm_dp_dual_mode_detect(intel_dp->aux.drm_dev,
adapter);
if (adaptor_type == DRM_DP_DUAL_MODE_LSPCON)
break;
}
diff --git a/include/drm/drm_dp_dual_mode_helper.h
b/include/drm/drm_dp_dual_mode_helper.h
index 4c42db81fcb4..23ce849152f3 100644
--- a/include/drm/drm_dp_dual_mode_helper.h
+++ b/include/drm/drm_dp_dual_mode_helper.h
@@ -62,6 +62,7 @@
#define DP_DUAL_MODE_LSPCON_CURRENT_MODE 0x41
#define DP_DUAL_MODE_LSPCON_MODE_PCON 0x1
+struct drm_device;
struct i2c_adapter;
ssize_t drm_dp_dual_mode_read(struct i2c_adapter *adapter,
@@ -103,7 +104,8 @@ enum drm_dp_dual_mode_type {
DRM_DP_DUAL_MODE_LSPCON,
};
-enum drm_dp_dual_mode_type drm_dp_dual_mode_detect(struct i2c_adapter
*adapter);
+enum drm_dp_dual_mode_type
+drm_dp_dual_mode_detect(const struct drm_device *dev, struct i2c_adapter
*adapter);
int drm_dp_dual_mode_max_tmds_clock(enum drm_dp_dual_mode_type type,
struct i2c_adapter *adapter);
int drm_dp_dual_mode_get_tmds_output(enum drm_dp_dual_mode_type type,
--
2.30.2
___
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[PATCH v4 06/17] drm/dp: Pass drm_dp_aux to drm_dp*_link_train_channel_eq_delay()
So that we can start using drm_dbg_*() for
drm_dp_link_train_channel_eq_delay() and
drm_dp_lttpr_link_train_channel_eq_delay().
Signed-off-by: Lyude Paul
Reviewed-by: Laurent Pinchart
---
drivers/gpu/drm/amd/amdgpu/atombios_dp.c | 2 +-
drivers/gpu/drm/drm_dp_helper.c| 14 +-
.../gpu/drm/i915/display/intel_dp_link_training.c | 4 ++--
drivers/gpu/drm/msm/dp/dp_ctrl.c | 4 ++--
drivers/gpu/drm/msm/edp/edp_ctrl.c | 4 ++--
drivers/gpu/drm/radeon/atombios_dp.c | 2 +-
drivers/gpu/drm/xlnx/zynqmp_dp.c | 2 +-
include/drm/drm_dp_helper.h| 6 --
8 files changed, 22 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
index 92d76f4cfdfc..f327becb022f 100644
--- a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
+++ b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
@@ -677,7 +677,7 @@ amdgpu_atombios_dp_link_train_ce(struct
amdgpu_atombios_dp_link_train_info *dp_i
dp_info->tries = 0;
channel_eq = false;
while (1) {
- drm_dp_link_train_channel_eq_delay(dp_info->dpcd);
+ drm_dp_link_train_channel_eq_delay(dp_info->aux, dp_info->dpcd);
if (drm_dp_dpcd_read_link_status(dp_info->aux,
dp_info->link_status) <= 0) {
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index f71b035a48b4..a2047dae3ab7 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -151,7 +151,8 @@ void drm_dp_link_train_clock_recovery_delay(const struct
drm_dp_aux *aux,
}
EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay);
-static void __drm_dp_link_train_channel_eq_delay(unsigned long rd_interval)
+static void __drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
+unsigned long rd_interval)
{
if (rd_interval > 4)
DRM_DEBUG_KMS("AUX interval %lu, out of range (max 4)\n",
@@ -165,9 +166,11 @@ static void __drm_dp_link_train_channel_eq_delay(unsigned
long rd_interval)
usleep_range(rd_interval, rd_interval * 2);
}
-void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
+void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
+ const u8 dpcd[DP_RECEIVER_CAP_SIZE])
{
- __drm_dp_link_train_channel_eq_delay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
+ __drm_dp_link_train_channel_eq_delay(aux,
+dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
DP_TRAINING_AUX_RD_MASK);
}
EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay);
@@ -183,13 +186,14 @@ static u8 dp_lttpr_phy_cap(const u8
phy_cap[DP_LTTPR_PHY_CAP_SIZE], int r)
return phy_cap[r - DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1];
}
-void drm_dp_lttpr_link_train_channel_eq_delay(const u8
phy_cap[DP_LTTPR_PHY_CAP_SIZE])
+void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
+ const u8
phy_cap[DP_LTTPR_PHY_CAP_SIZE])
{
u8 interval = dp_lttpr_phy_cap(phy_cap,
DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1) &
DP_TRAINING_AUX_RD_MASK;
- __drm_dp_link_train_channel_eq_delay(interval);
+ __drm_dp_link_train_channel_eq_delay(aux, interval);
}
EXPORT_SYMBOL(drm_dp_lttpr_link_train_channel_eq_delay);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 198ddb3c173a..6bf6f1ec13ed 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -665,11 +665,11 @@ intel_dp_link_training_channel_equalization_delay(struct
intel_dp *intel_dp,
enum drm_dp_phy dp_phy)
{
if (dp_phy == DP_PHY_DPRX) {
- drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
+ drm_dp_link_train_channel_eq_delay(_dp->aux,
intel_dp->dpcd);
} else {
const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy);
- drm_dp_lttpr_link_train_channel_eq_delay(phy_caps);
+ drm_dp_lttpr_link_train_channel_eq_delay(_dp->aux,
phy_caps);
}
}
diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c
index 264a9eae87d3..2cebd17a7289 100644
--- a/drivers/gpu/drm/msm/dp/dp_ctrl.c
+++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c
@@ -1184,7 +1184,7 @@ static int dp_ctrl_link_lane_down_shift(struct
dp_ctrl_private *ctrl)
static void dp_ctrl_clear_training_pattern(struct dp_ctrl_private *ctrl)
{
dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_DISABLE);
[PATCH v4 07/17] drm/dp: Always print aux channel name in logs
Since we're about to convert everything in drm_dp_helper.c over to using
drm_dbg_*(), let's also make our logging more consistent in drm_dp_helper.c
while we're at it to ensure that we always print the name of the AUX
channel in question.
Signed-off-by: Lyude Paul
---
drivers/gpu/drm/drm_dp_helper.c | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index a2047dae3ab7..b50e572b544d 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -139,8 +139,8 @@ void drm_dp_link_train_clock_recovery_delay(const struct
drm_dp_aux *aux,
DP_TRAINING_AUX_RD_MASK;
if (rd_interval > 4)
- DRM_DEBUG_KMS("AUX interval %lu, out of range (max 4)\n",
- rd_interval);
+ DRM_DEBUG_KMS("%s: AUX interval %lu, out of range (max 4)\n",
+ aux->name, rd_interval);
if (rd_interval == 0 || dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
rd_interval = 100;
@@ -155,8 +155,8 @@ static void __drm_dp_link_train_channel_eq_delay(const
struct drm_dp_aux *aux,
unsigned long rd_interval)
{
if (rd_interval > 4)
- DRM_DEBUG_KMS("AUX interval %lu, out of range (max 4)\n",
- rd_interval);
+ DRM_DEBUG_KMS("%s: AUX interval %lu, out of range (max 4)\n",
+ aux->name, rd_interval);
if (rd_interval == 0)
rd_interval = 400;
@@ -2781,7 +2781,7 @@ int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux)
if (ret < 0)
return ret;
if (!(buf & DP_PCON_ENABLE_SOURCE_CTL_MODE)) {
- DRM_DEBUG_KMS("PCON in Autonomous mode, can't enable FRL\n");
+ DRM_DEBUG_KMS("%s: PCON in Autonomous mode, can't enable
FRL\n", aux->name);
return -EINVAL;
}
buf |= DP_PCON_ENABLE_HDMI_LINK;
@@ -2876,7 +2876,8 @@ void drm_dp_pcon_hdmi_frl_link_error_count(struct
drm_dp_aux *aux,
num_error = 0;
}
- DRM_ERROR("More than %d errors since the last read for lane
%d", num_error, i);
+ DRM_ERROR("%s: More than %d errors since the last read for lane
%d",
+ aux->name, num_error, i);
}
}
EXPORT_SYMBOL(drm_dp_pcon_hdmi_frl_link_error_count);
--
2.30.2
___
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH v4 05/17] drm/dp: Pass drm_dp_aux to drm_dp_link_train_clock_recovery_delay()
So that we can start using drm_dbg_*() in
drm_dp_link_train_clock_recovery_delay().
Signed-off-by: Lyude Paul
Reviewed-by: Laurent Pinchart
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/amd/amdgpu/atombios_dp.c | 2 +-
drivers/gpu/drm/drm_dp_helper.c | 3 ++-
drivers/gpu/drm/i915/display/intel_dp_link_training.c | 2 +-
drivers/gpu/drm/msm/dp/dp_ctrl.c | 2 +-
drivers/gpu/drm/msm/edp/edp_ctrl.c| 2 +-
drivers/gpu/drm/radeon/atombios_dp.c | 2 +-
drivers/gpu/drm/xlnx/zynqmp_dp.c | 2 +-
include/drm/drm_dp_helper.h | 4 +++-
8 files changed, 11 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
index 062625a8a4ec..92d76f4cfdfc 100644
--- a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
+++ b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
@@ -612,7 +612,7 @@ amdgpu_atombios_dp_link_train_cr(struct
amdgpu_atombios_dp_link_train_info *dp_i
dp_info->tries = 0;
voltage = 0xff;
while (1) {
- drm_dp_link_train_clock_recovery_delay(dp_info->dpcd);
+ drm_dp_link_train_clock_recovery_delay(dp_info->aux,
dp_info->dpcd);
if (drm_dp_dpcd_read_link_status(dp_info->aux,
dp_info->link_status) <= 0) {
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 9f66153a3c55..f71b035a48b4 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -132,7 +132,8 @@ u8 drm_dp_get_adjust_request_post_cursor(const u8
link_status[DP_LINK_STATUS_SIZ
}
EXPORT_SYMBOL(drm_dp_get_adjust_request_post_cursor);
-void drm_dp_link_train_clock_recovery_delay(const u8
dpcd[DP_RECEIVER_CAP_SIZE])
+void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux,
+ const u8 dpcd[DP_RECEIVER_CAP_SIZE])
{
unsigned long rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
DP_TRAINING_AUX_RD_MASK;
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 591ddc4b876c..198ddb3c173a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -513,7 +513,7 @@ static void
intel_dp_link_training_clock_recovery_delay(struct intel_dp *intel_d
enum drm_dp_phy dp_phy)
{
if (dp_phy == DP_PHY_DPRX)
- drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
+ drm_dp_link_train_clock_recovery_delay(_dp->aux,
intel_dp->dpcd);
else
drm_dp_lttpr_link_train_clock_recovery_delay();
}
diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c
index 1390f3547fde..264a9eae87d3 100644
--- a/drivers/gpu/drm/msm/dp/dp_ctrl.c
+++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c
@@ -1103,7 +1103,7 @@ static int dp_ctrl_link_train_1(struct dp_ctrl_private
*ctrl,
tries = 0;
old_v_level = ctrl->link->phy_params.v_level;
for (tries = 0; tries < maximum_retries; tries++) {
- drm_dp_link_train_clock_recovery_delay(ctrl->panel->dpcd);
+ drm_dp_link_train_clock_recovery_delay(ctrl->aux,
ctrl->panel->dpcd);
ret = dp_ctrl_read_link_status(ctrl, link_status);
if (ret)
diff --git a/drivers/gpu/drm/msm/edp/edp_ctrl.c
b/drivers/gpu/drm/msm/edp/edp_ctrl.c
index 57af3d8b6699..6501598448b4 100644
--- a/drivers/gpu/drm/msm/edp/edp_ctrl.c
+++ b/drivers/gpu/drm/msm/edp/edp_ctrl.c
@@ -608,7 +608,7 @@ static int edp_start_link_train_1(struct edp_ctrl *ctrl)
tries = 0;
old_v_level = ctrl->v_level;
while (1) {
- drm_dp_link_train_clock_recovery_delay(ctrl->dpcd);
+ drm_dp_link_train_clock_recovery_delay(ctrl->drm_aux,
ctrl->dpcd);
rlen = drm_dp_dpcd_read_link_status(ctrl->drm_aux, link_status);
if (rlen < DP_LINK_STATUS_SIZE) {
diff --git a/drivers/gpu/drm/radeon/atombios_dp.c
b/drivers/gpu/drm/radeon/atombios_dp.c
index c50c504bad50..299b9d8da376 100644
--- a/drivers/gpu/drm/radeon/atombios_dp.c
+++ b/drivers/gpu/drm/radeon/atombios_dp.c
@@ -680,7 +680,7 @@ static int radeon_dp_link_train_cr(struct
radeon_dp_link_train_info *dp_info)
dp_info->tries = 0;
voltage = 0xff;
while (1) {
- drm_dp_link_train_clock_recovery_delay(dp_info->dpcd);
+ drm_dp_link_train_clock_recovery_delay(dp_info->aux,
dp_info->dpcd);
if (drm_dp_dpcd_read_link_status(dp_info->aux,
dp_info->link_status) <= 0) {
diff --git a/drivers/gpu/drm/xlnx/zynqmp_dp.c b/drivers/gpu/drm/xlnx/zynqmp_dp.c
[PATCH v4 03/17] drm/dp: Add backpointer to drm_device in drm_dp_aux
This is something that we've wanted for a while now: the ability to
actually look up the respective drm_device for a given drm_dp_aux struct.
This will also allow us to transition over to using the drm_dbg_*() helpers
for debug message printing, as we'll finally have a drm_device to reference
for doing so.
Note that there is one limitation with this - because some DP AUX adapters
exist as platform devices which are initialized independently of their
respective DRM devices, one cannot rely on drm_dp_aux->drm_dev to always be
non-NULL until drm_dp_aux_register() has been called. We make sure to point
this out in the documentation for struct drm_dp_aux.
v3:
* Add WARN_ON_ONCE() to drm_dp_aux_register() if drm_dev isn't filled out
Signed-off-by: Lyude Paul
Acked-by: Thierry Reding
---
drivers/gpu/drm/amd/amdgpu/atombios_dp.c | 2 ++
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 1 +
drivers/gpu/drm/bridge/analogix/analogix-anx6345.c | 1 +
drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c | 1 +
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 1 +
drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c | 1 +
drivers/gpu/drm/bridge/tc358767.c| 1 +
drivers/gpu/drm/bridge/ti-sn65dsi86.c| 1 +
drivers/gpu/drm/drm_dp_aux_dev.c | 6 ++
drivers/gpu/drm/drm_dp_helper.c | 2 ++
drivers/gpu/drm/drm_dp_mst_topology.c| 1 +
drivers/gpu/drm/i915/display/intel_dp_aux.c | 1 +
drivers/gpu/drm/msm/edp/edp.h| 3 +--
drivers/gpu/drm/msm/edp/edp_aux.c| 5 +++--
drivers/gpu/drm/msm/edp/edp_ctrl.c | 2 +-
drivers/gpu/drm/nouveau/nouveau_connector.c | 1 +
drivers/gpu/drm/radeon/atombios_dp.c | 1 +
drivers/gpu/drm/tegra/dpaux.c| 1 +
drivers/gpu/drm/xlnx/zynqmp_dp.c | 1 +
include/drm/drm_dp_helper.h | 9 -
20 files changed, 36 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
index a3ba9ca11e98..062625a8a4ec 100644
--- a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
+++ b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
@@ -188,6 +188,8 @@ void amdgpu_atombios_dp_aux_init(struct amdgpu_connector
*amdgpu_connector)
{
amdgpu_connector->ddc_bus->rec.hpd = amdgpu_connector->hpd.hpd;
amdgpu_connector->ddc_bus->aux.transfer =
amdgpu_atombios_dp_aux_transfer;
+ amdgpu_connector->ddc_bus->aux.drm_dev = amdgpu_connector->base.dev;
+
drm_dp_aux_init(_connector->ddc_bus->aux);
amdgpu_connector->ddc_bus->has_aux = true;
}
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 73cdb9fe981a..997567f6f0ba 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -433,6 +433,7 @@ void amdgpu_dm_initialize_dp_connector(struct
amdgpu_display_manager *dm,
kasprintf(GFP_KERNEL, "AMDGPU DM aux hw bus %d",
link_index);
aconnector->dm_dp_aux.aux.transfer = dm_dp_aux_transfer;
+ aconnector->dm_dp_aux.aux.drm_dev = dm->ddev;
aconnector->dm_dp_aux.ddc_service = aconnector->dc_link->ddc;
drm_dp_aux_init(>dm_dp_aux.aux);
diff --git a/drivers/gpu/drm/bridge/analogix/analogix-anx6345.c
b/drivers/gpu/drm/bridge/analogix/analogix-anx6345.c
index aa6cda458eb9..e33cd077595a 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix-anx6345.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix-anx6345.c
@@ -537,6 +537,7 @@ static int anx6345_bridge_attach(struct drm_bridge *bridge,
/* Register aux channel */
anx6345->aux.name = "DP-AUX";
anx6345->aux.dev = >client->dev;
+ anx6345->aux.drm_dev = bridge->dev;
anx6345->aux.transfer = anx6345_aux_transfer;
err = drm_dp_aux_register(>aux);
diff --git a/drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c
b/drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c
index f20558618220..5e6a0ed39199 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c
@@ -905,6 +905,7 @@ static int anx78xx_bridge_attach(struct drm_bridge *bridge,
/* Register aux channel */
anx78xx->aux.name = "DP-AUX";
anx78xx->aux.dev = >client->dev;
+ anx78xx->aux.drm_dev = bridge->dev;
anx78xx->aux.transfer = anx78xx_aux_transfer;
err = drm_dp_aux_register(>aux);
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index f115233b1cb9..550814ca2139 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++
[PATCH v4 04/17] drm/dp: Clarify DP AUX registration time
The docs we had for drm_dp_aux_init() and drm_dp_aux_register() were mostly
correct, except for the fact that they made the assumption that all AUX
devices were grandchildren of their respective DRM devices. This is the
case for most normal GPUs, but is almost never the case with SoCs and
display bridges. So, let's fix this documentation to clarify when the right
time to use drm_dp_aux_init() or drm_dp_aux_register() is.
Signed-off-by: Lyude Paul
---
drivers/gpu/drm/drm_dp_helper.c | 45 +++--
1 file changed, 32 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index ad73d7264743..9f66153a3c55 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -1728,10 +1728,18 @@ EXPORT_SYMBOL(drm_dp_remote_aux_init);
* drm_dp_aux_init() - minimally initialise an aux channel
* @aux: DisplayPort AUX channel
*
- * If you need to use the drm_dp_aux's i2c adapter prior to registering it
- * with the outside world, call drm_dp_aux_init() first. You must still
- * call drm_dp_aux_register() once the connector has been registered to
- * allow userspace access to the auxiliary DP channel.
+ * If you need to use the drm_dp_aux's i2c adapter prior to registering it with
+ * the outside world, call drm_dp_aux_init() first. For drivers which are
+ * grandparents to their AUX adapters (e.g. the AUX adapter is parented by a
+ * _connector), you must still call drm_dp_aux_register() once the
connector
+ * has been registered to allow userspace access to the auxiliary DP channel.
+ * Likewise, for such drivers you should also assign _dp_aux.drm_dev as
+ * early as possible so that the _device that corresponds to the AUX
adapter
+ * may be mentioned in debugging output from the DRM DP helpers.
+ *
+ * For devices which use a separate platform device for their AUX adapters,
this
+ * may be called as early as required by the driver.
+ *
*/
void drm_dp_aux_init(struct drm_dp_aux *aux)
{
@@ -1751,15 +1759,26 @@ EXPORT_SYMBOL(drm_dp_aux_init);
* drm_dp_aux_register() - initialise and register aux channel
* @aux: DisplayPort AUX channel
*
- * Automatically calls drm_dp_aux_init() if this hasn't been done yet.
- * This should only be called when the underlying drm_connector is
- * initialiazed already. Therefore the best place to call this is from
- * _connector_funcs.late_register. Not that drivers which don't follow this
- * will Oops when CONFIG_DRM_DP_AUX_CHARDEV is enabled.
- *
- * Drivers which need to use the aux channel before that point (e.g. at driver
- * load time, before drm_dev_register() has been called) need to call
- * drm_dp_aux_init().
+ * Automatically calls drm_dp_aux_init() if this hasn't been done yet. This
+ * should only be called once the parent of @aux, _dp_aux.dev, is
+ * initialized. For devices which are grandparents of their AUX channels,
+ * _dp_aux.dev will typically be the _connector which
+ * corresponds to @aux. For these devices, it's advised to call
+ * drm_dp_aux_register() in _connector_funcs.late_register, and likewise to
+ * call drm_dp_aux_unregister() in _connector_funcs.early_unregister.
+ * Functions which don't follow this will likely Oops when
+ * %CONFIG_DRM_DP_AUX_CHARDEV is enabled.
+ *
+ * For devices where the AUX channel is a device that exists independently of
+ * the _device that uses it, such as SoCs and bridge devices, it is
+ * recommended to call drm_dp_aux_register() after a _device has been
+ * assigned to _dp_aux.drm_dev, and likewise to call
+ * drm_dp_aux_unregister() once the _device should no longer be associated
+ * with the AUX channel (e.g. on bridge detach).
+ *
+ * Drivers which need to use the aux channel before either of the two points
+ * mentioned above need to call drm_dp_aux_init() in order to use the AUX
+ * channel before registration.
*
* Returns 0 on success or a negative error code on failure.
*/
--
2.30.2
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[PATCH v4 01/17] drm/bridge/cdns-mhdp8546: Register DP aux channel with userspace
Just adds some missing calls to
drm_dp_aux_register()/drm_dp_aux_unregister() for when we attach/detach the
bridge.
Signed-off-by: Lyude Paul
---
drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
index 01e95466502a..49e4c340f1de 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
@@ -1719,10 +1719,14 @@ static int cdns_mhdp_attach(struct drm_bridge *bridge,
dev_dbg(mhdp->dev, "%s\n", __func__);
+ ret = drm_dp_aux_register(>aux);
+ if (ret < 0)
+ return ret;
+
if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) {
ret = cdns_mhdp_connector_init(mhdp);
if (ret)
- return ret;
+ goto aux_unregister;
}
spin_lock(>start_lock);
@@ -1738,6 +1742,9 @@ static int cdns_mhdp_attach(struct drm_bridge *bridge,
mhdp->regs + CDNS_APB_INT_MASK);
return 0;
+aux_unregister:
+ drm_dp_aux_unregister(>aux);
+ return ret;
}
static void cdns_mhdp_configure_video(struct cdns_mhdp_device *mhdp,
@@ -2082,6 +2089,8 @@ static void cdns_mhdp_detach(struct drm_bridge *bridge)
dev_dbg(mhdp->dev, "%s\n", __func__);
+ drm_dp_aux_unregister(>aux);
+
spin_lock(>start_lock);
mhdp->bridge_attached = false;
--
2.30.2
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[PATCH v4 02/17] drm/nouveau/kms/nv50-: Move AUX adapter reg to connector late register/early unregister
Since AUX adapters on nouveau have their respective DRM connectors as
parents, we need to make sure that we register then after their connectors.
Signed-off-by: Lyude Paul
---
drivers/gpu/drm/nouveau/nouveau_connector.c | 25 -
1 file changed, 20 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c
b/drivers/gpu/drm/nouveau/nouveau_connector.c
index 61e6d7412505..c04044be3d32 100644
--- a/drivers/gpu/drm/nouveau/nouveau_connector.c
+++ b/drivers/gpu/drm/nouveau/nouveau_connector.c
@@ -401,7 +401,6 @@ nouveau_connector_destroy(struct drm_connector *connector)
drm_connector_cleanup(connector);
if (nv_connector->aux.transfer) {
drm_dp_cec_unregister_connector(_connector->aux);
- drm_dp_aux_unregister(_connector->aux);
kfree(nv_connector->aux.name);
}
kfree(connector);
@@ -905,13 +904,29 @@ nouveau_connector_late_register(struct drm_connector
*connector)
int ret;
ret = nouveau_backlight_init(connector);
+ if (ret)
+ return ret;
+ if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
+ connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
+ ret = drm_dp_aux_register(_connector(connector)->aux);
+ if (ret)
+ goto backlight_fini;
+ }
+
+ return 0;
+backlight_fini:
+ nouveau_backlight_fini(connector);
return ret;
}
static void
nouveau_connector_early_unregister(struct drm_connector *connector)
{
+ if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
+ connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort)
+ drm_dp_aux_unregister(_connector(connector)->aux);
+
nouveau_backlight_fini(connector);
}
@@ -1343,14 +1358,14 @@ nouveau_connector_create(struct drm_device *dev,
snprintf(aux_name, sizeof(aux_name), "sor-%04x-%04x",
dcbe->hasht, dcbe->hashm);
nv_connector->aux.name = kstrdup(aux_name, GFP_KERNEL);
- ret = drm_dp_aux_register(_connector->aux);
+ drm_dp_aux_init(_connector->aux);
if (ret) {
- NV_ERROR(drm, "failed to register aux channel\n");
+ NV_ERROR(drm, "Failed to init AUX adapter for
sor-%04x-%04x: %d\n",
+dcbe->hasht, dcbe->hashm, ret);
kfree(nv_connector);
return ERR_PTR(ret);
}
- funcs = _connector_funcs;
- break;
+ fallthrough;
default:
funcs = _connector_funcs;
break;
--
2.30.2
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[PATCH v4 00/17] drm: Use new DRM printk funcs (like drm_dbg_*()) in DP helpers
Since it's been asked quite a few times on some of the various DP related patch series I've submitted to use the new DRM printk helpers, and it technically wasn't really trivial to do this before due to the lack of a consistent way to find a drm_device for an AUX channel, this patch series aims to address this. In this series we: * (NEW! starting from V3) Make sure drm_dbg_*() and friends can handle NULL drm device pointers * Clean-up potentially erroneous usages of drm_dp_aux_init() and drm_dp_aux_register() so that actual AUX registration doesn't happen until we have an associated DRM device * Clean-up any obvious errors in drivers we find along the way * Add a backpointer to the respective drm_device for an AUX channel in drm_dp_aux.drm_dev, and hook it up in every driver with an AUX channel across the tree * Add a new ratelimited print helper we'll need for converting the DP helpers over to using the new DRM printk helpers * Fix any inconsistencies with logging in drm_dp_helper.c so we always have the aux channel name printed * Prepare the various DP helpers so they can find the correct drm_device to use for logging * And finally, convert all of the DP helpers over to using drm_dbg_*() and drm_err(). Major changes in v4: * Don't move i2c aux init into drm_dp_aux_init(), since I think I've found a much better solution to tegra's issues: https://patchwork.freedesktop.org/series/89420/ Lyude Paul (17): drm/bridge/cdns-mhdp8546: Register DP aux channel with userspace drm/nouveau/kms/nv50-: Move AUX adapter reg to connector late register/early unregister drm/dp: Add backpointer to drm_device in drm_dp_aux drm/dp: Clarify DP AUX registration time drm/dp: Pass drm_dp_aux to drm_dp_link_train_clock_recovery_delay() drm/dp: Pass drm_dp_aux to drm_dp*_link_train_channel_eq_delay() drm/dp: Always print aux channel name in logs drm/dp_dual_mode: Pass drm_device to drm_dp_dual_mode_detect() drm/dp_dual_mode: Pass drm_device to drm_dp_dual_mode_set_tmds_output() drm/dp_dual_mode: Pass drm_device to drm_dp_dual_mode_max_tmds_clock() drm/dp_dual_mode: Pass drm_device to drm_dp_dual_mode_get_tmds_output() drm/dp_dual_mode: Pass drm_device to drm_lspcon_(get|set)_mode() drm/dp_mst: Pass drm_dp_mst_topology_mgr to drm_dp_get_vc_payload_bw() drm/print: Handle potentially NULL drm_devices in drm_dbg_* drm/dp: Convert drm_dp_helper.c to using drm_err/drm_dbg_*() drm/dp_dual_mode: Convert drm_dp_dual_mode_helper.c to using drm_err/drm_dbg_kms() drm/dp_mst: Convert drm_dp_mst_topology.c to drm_err()/drm_dbg*() drivers/gpu/drm/amd/amdgpu/atombios_dp.c | 6 +- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 1 + .../drm/bridge/analogix/analogix-anx6345.c| 1 + .../drm/bridge/analogix/analogix-anx78xx.c| 1 + .../drm/bridge/analogix/analogix_dp_core.c| 1 + .../drm/bridge/cadence/cdns-mhdp8546-core.c | 12 +- drivers/gpu/drm/bridge/tc358767.c | 1 + drivers/gpu/drm/bridge/ti-sn65dsi86.c | 1 + drivers/gpu/drm/drm_dp_aux_dev.c | 6 + drivers/gpu/drm/drm_dp_dual_mode_helper.c | 68 ++-- drivers/gpu/drm/drm_dp_helper.c | 184 + drivers/gpu/drm/drm_dp_mst_topology.c | 376 +- drivers/gpu/drm/i915/display/intel_dp_aux.c | 1 + .../drm/i915/display/intel_dp_link_training.c | 6 +- drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 +- drivers/gpu/drm/i915/display/intel_hdmi.c | 7 +- drivers/gpu/drm/i915/display/intel_lspcon.c | 17 +- drivers/gpu/drm/msm/dp/dp_ctrl.c | 6 +- drivers/gpu/drm/msm/edp/edp.h | 3 +- drivers/gpu/drm/msm/edp/edp_aux.c | 5 +- drivers/gpu/drm/msm/edp/edp_ctrl.c| 8 +- drivers/gpu/drm/nouveau/nouveau_connector.c | 26 +- drivers/gpu/drm/radeon/atombios_dp.c | 5 +- drivers/gpu/drm/tegra/dpaux.c | 1 + drivers/gpu/drm/xlnx/zynqmp_dp.c | 5 +- include/drm/drm_dp_dual_mode_helper.h | 14 +- include/drm/drm_dp_helper.h | 19 +- include/drm/drm_dp_mst_helper.h | 3 +- include/drm/drm_print.h | 20 +- 29 files changed, 453 insertions(+), 354 deletions(-) -- 2.30.2 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH v1] drm/amd/dc: Fix a missing check bug in dm_dp_mst_detect()
Applied. Thanks!
Alex
On Thu, Apr 8, 2021 at 9:01 PM wrote:
>
> From: Yingjie Wang
>
> In dm_dp_mst_detect(), We should check whether or not @connector
> has been unregistered from userspace. If the connector is unregistered,
> we should return disconnected status.
>
> Fixes: 4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
> Signed-off-by: Yingjie Wang
> ---
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> index 8ab0b9060d2b..103dfd0e9b65 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> @@ -271,6 +271,9 @@ dm_dp_mst_detect(struct drm_connector *connector,
> struct amdgpu_dm_connector *aconnector =
> to_amdgpu_dm_connector(connector);
> struct amdgpu_dm_connector *master = aconnector->mst_port;
>
> + if (drm_connector_is_unregistered(connector))
> + return connector_status_disconnected;
> +
> return drm_dp_mst_detect_port(connector, ctx, >mst_mgr,
> aconnector->port);
> }
> --
> 2.7.4
>
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Re: [PATCH v3 03/20] drm/dp: Move i2c init to drm_dp_aux_init, add __must_check and fini
On Fri, 2021-04-23 at 14:39 +0200, Thierry Reding wrote: > > I'm curious: how is a DP AUX adapter reference count going to solve the > issue of potentially registering devices too early (i.e. before the DRM > is registered)? > > Is it because registering too early could cause a reference count > problem if somebody get a hold of the DP AUX adapter before the parent > DRM device is around? Well currently the problem is that we kind of want to avoid setting up the i2c adapter before the DRM driver is registered with userspace, but it's not really possible to do that if we need the core device struct for the ddc adapter initialized so that tegra can call get_device() on it in drivers/gpu/drm/tegra/sor.c. So my thought is instead of calling get_device() on the ddc adapter that the AUX channel provides, why not just call it on the actual platform device that implements the AUX channel instead? I think this should work pretty nicely while still preventing the platform device for the AUX channel from disappearing before the SOR has disappeared. > > Thierry -- Cheers, Lyude Paul (she/her) Software Engineer at Red Hat ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH v3 4/5] drm/amdgpu: address remove from fault filter
Am 23.04.21 um 17:35 schrieb Philip Yang:
Add interface to remove address from fault filter ring by resetting
fault ring entry key, then future vm fault on the address will be
processed to recover.
Use spinlock to protect fault hash ring access by interrupt handler and
interrupt scheduled deferred work for vg20.
Signed-off-by: Philip Yang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 66 +++--
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 3 ++
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 1 +
4 files changed, 68 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index c39ed9eb0987..91106b59389f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
@@ -332,6 +332,17 @@ void amdgpu_gmc_agp_location(struct amdgpu_device *adev,
struct amdgpu_gmc *mc)
mc->agp_size >> 20, mc->agp_start, mc->agp_end);
}
+/**
+ * fault_key - get 52bit hask key from vm fault address and pasid
+ *
+ * @addr: 48bit physical address
+ * @pasid: 4 bit
+ */
+static inline uint64_t fault_key(uint64_t addr, uint16_t pasid)
Please prefix with amdgpu_gmc_
+{
+ return addr << 4 | pasid;
+}
+
/**
* amdgpu_gmc_filter_faults - filter VM faults
*
@@ -349,15 +360,20 @@ bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev,
uint64_t addr,
{
struct amdgpu_gmc *gmc = >gmc;
- uint64_t stamp, key = addr << 4 | pasid;
+ uint64_t stamp, key = fault_key(addr, pasid);
struct amdgpu_gmc_fault *fault;
+ unsigned long flags;
uint32_t hash;
/* If we don't have space left in the ring buffer return immediately */
stamp = max(timestamp, AMDGPU_GMC_FAULT_TIMEOUT + 1) -
AMDGPU_GMC_FAULT_TIMEOUT;
- if (gmc->fault_ring[gmc->last_fault].timestamp >= stamp)
+
+ spin_lock_irqsave(>fault_lock, flags);
Uff the spinlock adds quite some overhead here. I'm still wondering if
we can't somehow avoid this.
Christian.
+ if (gmc->fault_ring[gmc->last_fault].timestamp >= stamp) {
+ spin_unlock_irqrestore(>fault_lock, flags);
return true;
+ }
/* Try to find the fault in the hash */
hash = hash_64(key, AMDGPU_GMC_FAULT_HASH_ORDER);
@@ -365,8 +381,10 @@ bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev,
uint64_t addr,
while (fault->timestamp >= stamp) {
uint64_t tmp;
- if (fault->key == key)
+ if (fault->key == key) {
+ spin_unlock_irqrestore(>fault_lock, flags);
return true;
+ }
tmp = fault->timestamp;
fault = >fault_ring[fault->next];
@@ -384,9 +402,51 @@ bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev,
uint64_t addr,
/* And update the hash */
fault->next = gmc->fault_hash[hash].idx;
gmc->fault_hash[hash].idx = gmc->last_fault++;
+ spin_unlock_irqrestore(>fault_lock, flags);
return false;
}
+/**
+ * amdgpu_gmc_filter_faults_remove - remove address from VM faults filter
+ *
+ * @adev: amdgpu device structure
+ * @addr: address of the VM fault
+ * @pasid: PASID of the process causing the fault
+ *
+ * Remove the address from fault filter, then future vm fault on this address
+ * will pass to retry fault handler to recover.
+ */
+void amdgpu_gmc_filter_faults_remove(struct amdgpu_device *adev, uint64_t addr,
+uint16_t pasid)
+{
+ struct amdgpu_gmc *gmc = >gmc;
+
+ uint64_t key = fault_key(addr, pasid);
+ struct amdgpu_gmc_fault *fault;
+ unsigned long flags;
+ uint32_t hash;
+
+ spin_lock_irqsave(>fault_lock, flags);
+ hash = hash_64(key, AMDGPU_GMC_FAULT_HASH_ORDER);
+ fault = >fault_ring[gmc->fault_hash[hash].idx];
+ while (true) {
+ uint64_t tmp;
+
+ if (fault->key == key) {
+ fault->key = fault_key(0, 0);
+ break;
+ }
+
+ tmp = fault->timestamp;
+ fault = >fault_ring[fault->next];
+
+ /* Check if the entry was reused */
+ if (fault->timestamp >= tmp)
+ break;
+ }
+ spin_unlock_irqrestore(>fault_lock, flags);
+}
+
int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev)
{
int r;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
index 9d11c02a3938..0aae3bd01bf2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
@@ -246,6 +246,7 @@ struct amdgpu_gmc {
uint64_tidx:AMDGPU_GMC_FAULT_RING_ORDER;
} fault_hash[AMDGPU_GMC_FAULT_HASH_SIZE];
uint64_tlast_fault:AMDGPU_GMC_FAULT_RING_ORDER;
+
[PATCH 2/2] drm/amd/amdgpu: Add dwc quirk for Stoney/CZ platforms
Add a quirk DW_I2S_QUIRK_STOP_ON_SHUTDOWN for Stoney/CZ
platforms.
For CZ/StoneyRidge platforms, ACP DMA between ACP SRAM and
I2S FIFO should be stopped before stopping I2S Controller DMA.
When DMA is progressing and stop request received, while DMA
transfer ongoing between ACP SRAM and I2S FIFO, Stopping I2S DMA
prior to ACP DMA stop resulting ACP DMA channel stop failure.
ACP DMA driver can't fix this issue due to design constraint.
By setting this quirk, I2S DMA gets stopped after ACP DMA stop
which will fix the ACP DMA stop failure.
Signed-off-by: Vijendar Mukunda
---
drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 38 +++--
1 file changed, 13 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
index b8655ff..6866b73 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
@@ -245,42 +245,30 @@ static int acp_hw_init(void *handle)
goto failure;
}
- switch (adev->asic_type) {
- case CHIP_STONEY:
- i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET |
- DW_I2S_QUIRK_16BIT_IDX_OVERRIDE;
- break;
- default:
- i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET;
- }
+ i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET |
+ DW_I2S_QUIRK_STOP_ON_SHUTDOWN;
+ if (adev->asic_type == CHIP_STONEY)
+ i2s_pdata[0].quirks |= DW_I2S_QUIRK_16BIT_IDX_OVERRIDE;
+
i2s_pdata[0].cap = DWC_I2S_PLAY;
i2s_pdata[0].snd_rates = SNDRV_PCM_RATE_8000_96000;
i2s_pdata[0].i2s_reg_comp1 = ACP_I2S_COMP1_PLAY_REG_OFFSET;
i2s_pdata[0].i2s_reg_comp2 = ACP_I2S_COMP2_PLAY_REG_OFFSET;
- switch (adev->asic_type) {
- case CHIP_STONEY:
- i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET |
- DW_I2S_QUIRK_COMP_PARAM1 |
- DW_I2S_QUIRK_16BIT_IDX_OVERRIDE;
- break;
- default:
- i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET |
- DW_I2S_QUIRK_COMP_PARAM1;
- }
+ i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET |
+ DW_I2S_QUIRK_COMP_PARAM1 |
+ DW_I2S_QUIRK_STOP_ON_SHUTDOWN;
+ if (adev->asic_type == CHIP_STONEY)
+ i2s_pdata[1].quirks |= DW_I2S_QUIRK_16BIT_IDX_OVERRIDE;
i2s_pdata[1].cap = DWC_I2S_RECORD;
i2s_pdata[1].snd_rates = SNDRV_PCM_RATE_8000_96000;
i2s_pdata[1].i2s_reg_comp1 = ACP_I2S_COMP1_CAP_REG_OFFSET;
i2s_pdata[1].i2s_reg_comp2 = ACP_I2S_COMP2_CAP_REG_OFFSET;
- i2s_pdata[2].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET;
- switch (adev->asic_type) {
- case CHIP_STONEY:
+ i2s_pdata[2].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET |
+ DW_I2S_QUIRK_STOP_ON_SHUTDOWN;
+ if (adev->asic_type == CHIP_STONEY)
i2s_pdata[2].quirks |= DW_I2S_QUIRK_16BIT_IDX_OVERRIDE;
- break;
- default:
- break;
- }
i2s_pdata[2].cap = DWC_I2S_PLAY | DWC_I2S_RECORD;
i2s_pdata[2].snd_rates = SNDRV_PCM_RATE_8000_96000;
--
2.7.4
___
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[PATCH 5/5] drm/amdkfd: enable subsequent retry fault
After draining the stale retry fault, or failed to validate the range
to recover, have to remove the fault address from fault filter ring, to
be able to handle subsequent retry interrupt on same address. Otherwise
the retry fault will not be processed to recover until timeout passed.
Signed-off-by: Philip Yang
Reviewed-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
index 6490f016aa6e..5ed7dda2d14f 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
@@ -2363,8 +2363,10 @@ svm_range_restore_pages(struct amdgpu_device *adev,
unsigned int pasid,
mutex_lock(>migrate_mutex);
- if (svm_range_skip_recover(prange))
+ if (svm_range_skip_recover(prange)) {
+ amdgpu_gmc_filter_faults_remove(adev, addr, pasid);
goto out_unlock_range;
+ }
timestamp = ktime_to_us(ktime_get()) - prange->validate_timestamp;
/* skip duplicate vm fault on different pages of same range */
@@ -2426,6 +2428,7 @@ svm_range_restore_pages(struct amdgpu_device *adev,
unsigned int pasid,
if (r == -EAGAIN) {
pr_debug("recover vm fault later\n");
+ amdgpu_gmc_filter_faults_remove(adev, addr, pasid);
r = 0;
}
return r;
--
2.17.1
___
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[PATCH v3 4/5] drm/amdgpu: address remove from fault filter
Add interface to remove address from fault filter ring by resetting
fault ring entry key, then future vm fault on the address will be
processed to recover.
Use spinlock to protect fault hash ring access by interrupt handler and
interrupt scheduled deferred work for vg20.
Signed-off-by: Philip Yang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 66 +++--
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 3 ++
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 1 +
4 files changed, 68 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index c39ed9eb0987..91106b59389f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
@@ -332,6 +332,17 @@ void amdgpu_gmc_agp_location(struct amdgpu_device *adev,
struct amdgpu_gmc *mc)
mc->agp_size >> 20, mc->agp_start, mc->agp_end);
}
+/**
+ * fault_key - get 52bit hask key from vm fault address and pasid
+ *
+ * @addr: 48bit physical address
+ * @pasid: 4 bit
+ */
+static inline uint64_t fault_key(uint64_t addr, uint16_t pasid)
+{
+ return addr << 4 | pasid;
+}
+
/**
* amdgpu_gmc_filter_faults - filter VM faults
*
@@ -349,15 +360,20 @@ bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev,
uint64_t addr,
{
struct amdgpu_gmc *gmc = >gmc;
- uint64_t stamp, key = addr << 4 | pasid;
+ uint64_t stamp, key = fault_key(addr, pasid);
struct amdgpu_gmc_fault *fault;
+ unsigned long flags;
uint32_t hash;
/* If we don't have space left in the ring buffer return immediately */
stamp = max(timestamp, AMDGPU_GMC_FAULT_TIMEOUT + 1) -
AMDGPU_GMC_FAULT_TIMEOUT;
- if (gmc->fault_ring[gmc->last_fault].timestamp >= stamp)
+
+ spin_lock_irqsave(>fault_lock, flags);
+ if (gmc->fault_ring[gmc->last_fault].timestamp >= stamp) {
+ spin_unlock_irqrestore(>fault_lock, flags);
return true;
+ }
/* Try to find the fault in the hash */
hash = hash_64(key, AMDGPU_GMC_FAULT_HASH_ORDER);
@@ -365,8 +381,10 @@ bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev,
uint64_t addr,
while (fault->timestamp >= stamp) {
uint64_t tmp;
- if (fault->key == key)
+ if (fault->key == key) {
+ spin_unlock_irqrestore(>fault_lock, flags);
return true;
+ }
tmp = fault->timestamp;
fault = >fault_ring[fault->next];
@@ -384,9 +402,51 @@ bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev,
uint64_t addr,
/* And update the hash */
fault->next = gmc->fault_hash[hash].idx;
gmc->fault_hash[hash].idx = gmc->last_fault++;
+ spin_unlock_irqrestore(>fault_lock, flags);
return false;
}
+/**
+ * amdgpu_gmc_filter_faults_remove - remove address from VM faults filter
+ *
+ * @adev: amdgpu device structure
+ * @addr: address of the VM fault
+ * @pasid: PASID of the process causing the fault
+ *
+ * Remove the address from fault filter, then future vm fault on this address
+ * will pass to retry fault handler to recover.
+ */
+void amdgpu_gmc_filter_faults_remove(struct amdgpu_device *adev, uint64_t addr,
+uint16_t pasid)
+{
+ struct amdgpu_gmc *gmc = >gmc;
+
+ uint64_t key = fault_key(addr, pasid);
+ struct amdgpu_gmc_fault *fault;
+ unsigned long flags;
+ uint32_t hash;
+
+ spin_lock_irqsave(>fault_lock, flags);
+ hash = hash_64(key, AMDGPU_GMC_FAULT_HASH_ORDER);
+ fault = >fault_ring[gmc->fault_hash[hash].idx];
+ while (true) {
+ uint64_t tmp;
+
+ if (fault->key == key) {
+ fault->key = fault_key(0, 0);
+ break;
+ }
+
+ tmp = fault->timestamp;
+ fault = >fault_ring[fault->next];
+
+ /* Check if the entry was reused */
+ if (fault->timestamp >= tmp)
+ break;
+ }
+ spin_unlock_irqrestore(>fault_lock, flags);
+}
+
int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev)
{
int r;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
index 9d11c02a3938..0aae3bd01bf2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
@@ -246,6 +246,7 @@ struct amdgpu_gmc {
uint64_tidx:AMDGPU_GMC_FAULT_RING_ORDER;
} fault_hash[AMDGPU_GMC_FAULT_HASH_SIZE];
uint64_tlast_fault:AMDGPU_GMC_FAULT_RING_ORDER;
+ spinlock_t fault_lock;
bool tmz_enabled;
@@ -318,6 +319,8 @@ void amdgpu_gmc_agp_location(struct amdgpu_device *adev,
struct
Re: [PATCH v2 1/2] drm/amdgpu: address remove from fault filter
On 2021-04-23 2:03 a.m., Felix Kuehling
wrote:
Am 2021-04-22 um 10:03 p.m. schrieb Philip Yang:
Add interface to remove address from fault filter ring by resetting
fault ring entry of the fault address timestamp to 0, then future vm
fault on the address will be processed to recover.
Use spinlock to protect fault hash ring access by interrupt handler and
interrupt scheduled deferred work for vg20.
This needs a better explanation. When you say Vega20, I think you're
referring to the lack of HW IH rerouting. In that case
amdgpu_gmc_filter_faults runs in interrupt context before delegating the
IH entries to the SW IH ring.
yes, Vega20 uses ih_soft ring, I need add drain retry fault from
ih_soft ring for Vega20.
On GPUs that support IH rerouting, amdgpu_gmc_filter_faults runs in the
same thread as the page fault handling, so there is no risk of
concurrently accessing the fault ring assuming that
amdgpu_gmc_filter_faults_remove is only called from the page fault handler.
Christian had an idea to do this without a lock, by using cmpxchg. I
guess that idea didn't work out?
cmpxchg cannot use for 52bit fault->key, which share same
uint64_t with 8bit fault->next. This is compilation error:
/home/yangp/git/compute_staging/kernel/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c:435:22:
error: cannot take address of bit-field ‘key’
if (atomic_cmpxchg(>key, key, 0) == key)
Vega20 interrupt handler and deferred work access fault hash
table and fault ring, not just fault->key, so I decide to use
spinlock.
Signed-off-by: Philip Yang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 66 +++--
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 3 ++
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 1 +
4 files changed, 68 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index c39ed9eb0987..801ea0623453 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
@@ -332,6 +332,17 @@ void amdgpu_gmc_agp_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc)
mc->agp_size >> 20, mc->agp_start, mc->agp_end);
}
+/**
+ * fault_key - get 52bit hask key from vm fault address and pasid
+ *
+ * @addr: 48bit physical address
+ * @pasid: 4 bit
+ */
+static inline uint64_t fault_key(uint64_t addr, uint16_t pasid)
+{
+ return addr << 4 | pasid;
+}
+
/**
* amdgpu_gmc_filter_faults - filter VM faults
*
@@ -349,15 +360,20 @@ bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev, uint64_t addr,
{
struct amdgpu_gmc *gmc = >gmc;
- uint64_t stamp, key = addr << 4 | pasid;
+ uint64_t stamp, key = fault_key(addr, pasid);
struct amdgpu_gmc_fault *fault;
+ unsigned long flags;
uint32_t hash;
/* If we don't have space left in the ring buffer return immediately */
stamp = max(timestamp, AMDGPU_GMC_FAULT_TIMEOUT + 1) -
AMDGPU_GMC_FAULT_TIMEOUT;
- if (gmc->fault_ring[gmc->last_fault].timestamp >= stamp)
+
+ spin_lock_irqsave(>fault_lock, flags);
+ if (gmc->fault_ring[gmc->last_fault].timestamp >= stamp) {
+ spin_unlock_irqrestore(>fault_lock, flags);
return true;
+ }
/* Try to find the fault in the hash */
hash = hash_64(key, AMDGPU_GMC_FAULT_HASH_ORDER);
@@ -365,8 +381,10 @@ bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev, uint64_t addr,
while (fault->timestamp >= stamp) {
uint64_t tmp;
- if (fault->key == key)
+ if (fault->key == key) {
+ spin_unlock_irqrestore(>fault_lock, flags);
return true;
+ }
tmp = fault->timestamp;
fault = >fault_ring[fault->next];
@@ -384,9 +402,51 @@ bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev, uint64_t addr,
/* And update the hash */
fault->next = gmc->fault_hash[hash].idx;
gmc->fault_hash[hash].idx = gmc->last_fault++;
+ spin_unlock_irqrestore(>fault_lock, flags);
return false;
}
+/**
+ * amdgpu_gmc_filter_faults_remove - remove address from VM faults filter
+ *
+ * @adev: amdgpu device structure
+ * @addr: address of the VM fault
+ * @pasid: PASID of the process causing the fault
+ *
+ * Remove the address from fault filter, then future vm fault on this address
+ * will pass to retry fault handler to recover.
+ */
+void amdgpu_gmc_filter_faults_remove(struct amdgpu_device *adev, uint64_t addr,
+ uint16_t pasid)
+{
+ struct amdgpu_gmc *gmc = >gmc;
+
+ uint64_t key = fault_key(addr, pasid);
+ struct amdgpu_gmc_fault *fault;
+ unsigned long flags;
+ uint32_t hash;
+
+ spin_lock_irqsave(>fault_lock, flags);
+ hash = hash_64(key, AMDGPU_GMC_FAULT_HASH_ORDER);
+ fault = >fault_ring[gmc->fault_hash[hash].idx];
+ while (true) {
+ uint64_t tmp;
+
+ if (fault->key == key) {
+ fault->timestamp = 0;
Setting the timestamp to 0 breaks the chain of interrupts with the
Re: [PATCH v3 03/20] drm/dp: Move i2c init to drm_dp_aux_init, add __must_check and fini
On Thu, Apr 22, 2021 at 01:18:09PM -0400, Lyude Paul wrote: > On Tue, 2021-04-20 at 02:16 +0300, Ville Syrjälä wrote: > > > > The init vs. register split is intentional. Registering the thing > > and allowing userspace access to it before the rest of the driver > > is ready isn't particularly great. For a while now we've tried to > > move towards an architecture where the driver is fully initialzied > > before anything gets exposed to userspace. > > Yeah-thank you for pointing this out. Thierry - do you think there's an > alternate solution we could go with in Tegra to fix the get_device() issue > that wouldn't require us trying to expose the i2c adapter early? I suppose we could do it in a hackish way that grabs a reference to the I2C adapter only upon registration. We can't do that for the regular I2C DDC case where the I2C controller is an external one because by the time we get to registration it could've gone again. This would make both code paths asymmetric, so I'd prefer not to do it. Perhaps it could serve as an stop-gap solution until something better is in place, though. Thierry signature.asc Description: PGP signature ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH v3 03/20] drm/dp: Move i2c init to drm_dp_aux_init, add __must_check and fini
On Fri, Apr 23, 2021 at 12:11:06AM -0400, Lyude Paul wrote: > On Thu, 2021-04-22 at 18:33 -0400, Lyude Paul wrote: > > OK - talked with Ville a bit on this and did some of my own research, I > > actually think that moving i2c to drm_dp_aux_init() is the right decision > > for > > the time being. The reasoning behind this being that as shown by my previous > > work of fixing drivers that call drm_dp_aux_register() too early - it seems > > like there's already been drivers that have been working just fine with > > setting up the i2c device before DRM registration. > > > > In the future, it'd probably be better if we can split up i2c_add_adapter() > > into an init and register function - but we'll have to talk with the i2c > > maintainers to see if this is acceptable w/ them > > Actually - I think adding the ability to refcount dp aux adapters might be a > better solution so I'm going to try that! I'm curious: how is a DP AUX adapter reference count going to solve the issue of potentially registering devices too early (i.e. before the DRM is registered)? Is it because registering too early could cause a reference count problem if somebody get a hold of the DP AUX adapter before the parent DRM device is around? Thierry signature.asc Description: PGP signature ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 31/40] drm/amd/amdgpu/amdgpu_gart: Correct a couple of function names in the docs
On Tue, 20 Apr 2021, Alex Deucher wrote: > Applied. thanks! Lovely. Thanks for these Alex. -- Lee Jones [李琼斯] Senior Technical Lead - Developer Services Linaro.org │ Open source software for Arm SoCs Follow Linaro: Facebook | Twitter | Blog ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH v3 03/20] drm/dp: Move i2c init to drm_dp_aux_init, add __must_check and fini
On Thu, Apr 22, 2021 at 06:33:44PM -0400, Lyude Paul wrote: > OK - talked with Ville a bit on this and did some of my own research, I > actually think that moving i2c to drm_dp_aux_init() is the right decision for > the time being. The reasoning behind this being that as shown by my previous > work of fixing drivers that call drm_dp_aux_register() too early - it seems > like there's already been drivers that have been working just fine with > setting up the i2c device before DRM registration. > > In the future, it'd probably be better if we can split up i2c_add_adapter() > into an init and register function - but we'll have to talk with the i2c > maintainers to see if this is acceptable w/ them Yeah, that sounds like a better long-term solution. We could leave i2c_add_adapter() in place, since it's already half-way split up into some initialization code and i2c_register_adapter(), so it shouldn't be all that difficult to split out an i2c_init_adapter() so that outside users can do the split setup. Thierry signature.asc Description: PGP signature ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH v2] drm/amd/display: Reject non-zero src_y and src_x for video planes
On 2021-04-23 10:18 a.m., Christian König wrote: Good that this has been found. Just a curious guess, but have you guys checked if the src_x and src_y are a multiple of 2? That was one of my first guesses but I still observed the hang after forcing src_x and src_y to be multiples of 2. Might cause problems to try to access a subsampled surface if the coordinates doesn't make much sense. Anyway patch is Acked-by: Christian König Thanks, Harry Regards, Christian. Am 23.04.21 um 16:09 schrieb Harry Wentland: [Why] This hasn't been well tested and leads to complete system hangs on DCN1 based systems, possibly others. The system hang can be reproduced by gesturing the video on the YouTube Android app on ChromeOS into full screen. [How] Reject atomic commits with non-zero drm_plane_state.src_x or src_y values. v2: - Add code comment describing the reason we're rejecting non-zero src_x and src_y - Drop gerrit Change-Id - Add stable CC - Based on amd-staging-drm-next Signed-off-by: Harry Wentland Cc: sta...@vger.kernel.org Cc: nicholas.kazlaus...@amd.com Cc: amd-gfx@lists.freedesktop.org Cc: alexander.deuc...@amd.com Cc: roman...@amd.com Cc: hersenxs...@amd.com Cc: danny.w...@amd.com Reviewed-by: Nicholas Kazlauskas --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 17 + 1 file changed, 17 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index be1769d29742..b12469043e6b 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4089,6 +4089,23 @@ static int fill_dc_scaling_info(const struct drm_plane_state *state, scaling_info->src_rect.x = state->src_x >> 16; scaling_info->src_rect.y = state->src_y >> 16; + /* + * For reasons we don't (yet) fully understand a non-zero + * src_y coordinate into an NV12 buffer can cause a + * system hang. To avoid hangs (and maybe be overly cautious) + * let's reject both non-zero src_x and src_y. + * + * We currently know of only one use-case to reproduce a + * scenario with non-zero src_x and src_y for NV12, which + * is to gesture the YouTube Android app into full screen + * on ChromeOS. + */ + if (state->fb && + state->fb->format->format == DRM_FORMAT_NV12 && + (scaling_info->src_rect.x != 0 || + scaling_info->src_rect.y != 0)) + return -EINVAL; + scaling_info->src_rect.width = state->src_w >> 16; if (scaling_info->src_rect.width == 0) return -EINVAL; ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH v2] drm/amd/display: Reject non-zero src_y and src_x for video planes
Good that this has been found. Just a curious guess, but have you guys checked if the src_x and src_y are a multiple of 2? Might cause problems to try to access a subsampled surface if the coordinates doesn't make much sense. Anyway patch is Acked-by: Christian König Regards, Christian. Am 23.04.21 um 16:09 schrieb Harry Wentland: [Why] This hasn't been well tested and leads to complete system hangs on DCN1 based systems, possibly others. The system hang can be reproduced by gesturing the video on the YouTube Android app on ChromeOS into full screen. [How] Reject atomic commits with non-zero drm_plane_state.src_x or src_y values. v2: - Add code comment describing the reason we're rejecting non-zero src_x and src_y - Drop gerrit Change-Id - Add stable CC - Based on amd-staging-drm-next Signed-off-by: Harry Wentland Cc: sta...@vger.kernel.org Cc: nicholas.kazlaus...@amd.com Cc: amd-gfx@lists.freedesktop.org Cc: alexander.deuc...@amd.com Cc: roman...@amd.com Cc: hersenxs...@amd.com Cc: danny.w...@amd.com Reviewed-by: Nicholas Kazlauskas --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 17 + 1 file changed, 17 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index be1769d29742..b12469043e6b 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4089,6 +4089,23 @@ static int fill_dc_scaling_info(const struct drm_plane_state *state, scaling_info->src_rect.x = state->src_x >> 16; scaling_info->src_rect.y = state->src_y >> 16; + /* +* For reasons we don't (yet) fully understand a non-zero +* src_y coordinate into an NV12 buffer can cause a +* system hang. To avoid hangs (and maybe be overly cautious) +* let's reject both non-zero src_x and src_y. +* +* We currently know of only one use-case to reproduce a +* scenario with non-zero src_x and src_y for NV12, which +* is to gesture the YouTube Android app into full screen +* on ChromeOS. +*/ + if (state->fb && + state->fb->format->format == DRM_FORMAT_NV12 && + (scaling_info->src_rect.x != 0 || +scaling_info->src_rect.y != 0)) + return -EINVAL; + scaling_info->src_rect.width = state->src_w >> 16; if (scaling_info->src_rect.width == 0) return -EINVAL; ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH v3] drm/amd/display: Reject non-zero src_y and src_x for video planes
[AMD Official Use Only - Internal Distribution Only] Reviewed-by: Hersen Wu -Original Message- From: Harry Wentland Sent: Friday, April 23, 2021 10:12 AM To: amd-gfx@lists.freedesktop.org Cc: Wentland, Harry ; sta...@vger.kernel.org; Kazlauskas, Nicholas ; Deucher, Alexander ; Li, Roman ; Wu, Hersen ; Wang, Danny Subject: [PATCH v3] drm/amd/display: Reject non-zero src_y and src_x for video planes [Why] This hasn't been well tested and leads to complete system hangs on DCN1 based systems, possibly others. The system hang can be reproduced by gesturing the video on the YouTube Android app on ChromeOS into full screen. [How] Reject atomic commits with non-zero drm_plane_state.src_x or src_y values. v2: - Add code comment describing the reason we're rejecting non-zero src_x and src_y - Drop gerrit Change-Id - Add stable CC - Based on amd-staging-drm-next v3: removed trailing whitespace Signed-off-by: Harry Wentland Cc: sta...@vger.kernel.org Cc: nicholas.kazlaus...@amd.com Cc: amd-gfx@lists.freedesktop.org Cc: alexander.deuc...@amd.com Cc: roman...@amd.com Cc: hersenxs...@amd.com Cc: danny.w...@amd.com Reviewed-by: Nicholas Kazlauskas --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 17 + 1 file changed, 17 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index be1769d29742..aeedc5a3fb36 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4089,6 +4089,23 @@ static int fill_dc_scaling_info(const struct drm_plane_state *state, scaling_info->src_rect.x = state->src_x >> 16; scaling_info->src_rect.y = state->src_y >> 16; + /* +* For reasons we don't (yet) fully understand a non-zero +* src_y coordinate into an NV12 buffer can cause a +* system hang. To avoid hangs (and maybe be overly cautious) +* let's reject both non-zero src_x and src_y. +* +* We currently know of only one use-case to reproduce a +* scenario with non-zero src_x and src_y for NV12, which +* is to gesture the YouTube Android app into full screen +* on ChromeOS. +*/ + if (state->fb && + state->fb->format->format == DRM_FORMAT_NV12 && + (scaling_info->src_rect.x != 0 || +scaling_info->src_rect.y != 0)) + return -EINVAL; + scaling_info->src_rect.width = state->src_w >> 16; if (scaling_info->src_rect.width == 0) return -EINVAL; -- 2.31.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH v3] drm/amd/display: Reject non-zero src_y and src_x for video planes
[Why] This hasn't been well tested and leads to complete system hangs on DCN1 based systems, possibly others. The system hang can be reproduced by gesturing the video on the YouTube Android app on ChromeOS into full screen. [How] Reject atomic commits with non-zero drm_plane_state.src_x or src_y values. v2: - Add code comment describing the reason we're rejecting non-zero src_x and src_y - Drop gerrit Change-Id - Add stable CC - Based on amd-staging-drm-next v3: removed trailing whitespace Signed-off-by: Harry Wentland Cc: sta...@vger.kernel.org Cc: nicholas.kazlaus...@amd.com Cc: amd-gfx@lists.freedesktop.org Cc: alexander.deuc...@amd.com Cc: roman...@amd.com Cc: hersenxs...@amd.com Cc: danny.w...@amd.com Reviewed-by: Nicholas Kazlauskas --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 17 + 1 file changed, 17 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index be1769d29742..aeedc5a3fb36 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4089,6 +4089,23 @@ static int fill_dc_scaling_info(const struct drm_plane_state *state, scaling_info->src_rect.x = state->src_x >> 16; scaling_info->src_rect.y = state->src_y >> 16; + /* +* For reasons we don't (yet) fully understand a non-zero +* src_y coordinate into an NV12 buffer can cause a +* system hang. To avoid hangs (and maybe be overly cautious) +* let's reject both non-zero src_x and src_y. +* +* We currently know of only one use-case to reproduce a +* scenario with non-zero src_x and src_y for NV12, which +* is to gesture the YouTube Android app into full screen +* on ChromeOS. +*/ + if (state->fb && + state->fb->format->format == DRM_FORMAT_NV12 && + (scaling_info->src_rect.x != 0 || +scaling_info->src_rect.y != 0)) + return -EINVAL; + scaling_info->src_rect.width = state->src_w >> 16; if (scaling_info->src_rect.width == 0) return -EINVAL; -- 2.31.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH v2] drm/amd/display: Reject non-zero src_y and src_x for video planes
[Why] This hasn't been well tested and leads to complete system hangs on DCN1 based systems, possibly others. The system hang can be reproduced by gesturing the video on the YouTube Android app on ChromeOS into full screen. [How] Reject atomic commits with non-zero drm_plane_state.src_x or src_y values. v2: - Add code comment describing the reason we're rejecting non-zero src_x and src_y - Drop gerrit Change-Id - Add stable CC - Based on amd-staging-drm-next Signed-off-by: Harry Wentland Cc: sta...@vger.kernel.org Cc: nicholas.kazlaus...@amd.com Cc: amd-gfx@lists.freedesktop.org Cc: alexander.deuc...@amd.com Cc: roman...@amd.com Cc: hersenxs...@amd.com Cc: danny.w...@amd.com Reviewed-by: Nicholas Kazlauskas --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 17 + 1 file changed, 17 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index be1769d29742..b12469043e6b 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4089,6 +4089,23 @@ static int fill_dc_scaling_info(const struct drm_plane_state *state, scaling_info->src_rect.x = state->src_x >> 16; scaling_info->src_rect.y = state->src_y >> 16; + /* +* For reasons we don't (yet) fully understand a non-zero +* src_y coordinate into an NV12 buffer can cause a +* system hang. To avoid hangs (and maybe be overly cautious) +* let's reject both non-zero src_x and src_y. +* +* We currently know of only one use-case to reproduce a +* scenario with non-zero src_x and src_y for NV12, which +* is to gesture the YouTube Android app into full screen +* on ChromeOS. +*/ + if (state->fb && + state->fb->format->format == DRM_FORMAT_NV12 && + (scaling_info->src_rect.x != 0 || +scaling_info->src_rect.y != 0)) + return -EINVAL; + scaling_info->src_rect.width = state->src_w >> 16; if (scaling_info->src_rect.width == 0) return -EINVAL; -- 2.31.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu: fix concurrent VM flushes on Vega/Navi v2
Reviewed-by: James Zhu
Tested-by: James Zhu
James
On 2021-04-23 5:29 a.m., Christian König wrote:
Starting with Vega the hardware supports concurrent flushes
of VMID which can be used to implement per process VMID
allocation.
But concurrent flushes are mutual exclusive with back to
back VMID allocations, fix this to avoid a VMID used in
two ways at the same time.
v2: don't set ring to NULL
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c | 19 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 6 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 1 +
3 files changed, 18 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
index 94b069630db3..b4971e90b98c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
@@ -215,7 +215,11 @@ static int amdgpu_vmid_grab_idle(struct amdgpu_vm *vm,
/* Check if we have an idle VMID */
i = 0;
list_for_each_entry((*idle), _mgr->ids_lru, list) {
- fences[i] = amdgpu_sync_peek_fence(&(*idle)->active, ring);
+ /* Don't use per engine and per process VMID at the same time */
+ struct amdgpu_ring *r = adev->vm_manager.concurrent_flush ?
+ NULL : ring;
+
+ fences[i] = amdgpu_sync_peek_fence(&(*idle)->active, r);
if (!fences[i])
break;
++i;
@@ -281,7 +285,7 @@ static int amdgpu_vmid_grab_reserved(struct amdgpu_vm *vm,
if (updates && (*id)->flushed_updates &&
updates->context == (*id)->flushed_updates->context &&
!dma_fence_is_later(updates, (*id)->flushed_updates))
- updates = NULL;
+ updates = NULL;
if ((*id)->owner != vm->immediate.fence_context ||
job->vm_pd_addr != (*id)->pd_gpu_addr ||
@@ -290,6 +294,10 @@ static int amdgpu_vmid_grab_reserved(struct amdgpu_vm *vm,
!dma_fence_is_signaled((*id)->last_flush))) {
struct dma_fence *tmp;
+ /* Don't use per engine and per process VMID at the same time */
+ if (adev->vm_manager.concurrent_flush)
+ ring = NULL;
+
/* to prevent one context starved by another context */
(*id)->pd_gpu_addr = 0;
tmp = amdgpu_sync_peek_fence(&(*id)->active, ring);
@@ -365,12 +373,7 @@ static int amdgpu_vmid_grab_used(struct amdgpu_vm *vm,
if (updates && (!flushed || dma_fence_is_later(updates,
flushed)))
needs_flush = true;
- /* Concurrent flushes are only possible starting with Vega10 and
-* are broken on Navi10 and Navi14.
-*/
- if (needs_flush && (adev->asic_type < CHIP_VEGA10 ||
- adev->asic_type == CHIP_NAVI10 ||
- adev->asic_type == CHIP_NAVI14))
+ if (needs_flush && !adev->vm_manager.concurrent_flush)
continue;
/* Good, we can use this VMID. Remember this submission as
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index f95bcda8463f..adc4481b05fb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -3149,6 +3149,12 @@ void amdgpu_vm_manager_init(struct amdgpu_device *adev)
{
unsigned i;
+ /* Concurrent flushes are only possible starting with Vega10 and
+* are broken on Navi10 and Navi14.
+*/
+ adev->vm_manager.concurrent_flush = !(adev->asic_type < CHIP_VEGA10 ||
+ adev->asic_type == CHIP_NAVI10 ||
+ adev->asic_type == CHIP_NAVI14);
amdgpu_vmid_mgr_init(adev);
adev->vm_manager.fence_context =
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 848e175e99ff..163763f8b418 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -331,6 +331,7 @@ struct amdgpu_vm_manager {
/* Handling of VMIDs */
struct amdgpu_vmid_mgr id_mgr[AMDGPU_MAX_VMHUBS];
unsigned intfirst_kfd_vmid;
+ boolconcurrent_flush;
/* Handling of VM fences */
u64 fence_context;
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 2/2] drm/amdgpu: Add show_fdinfo() interface
Am 23.04.21 um 12:55 schrieb Roy Sun:
Tracking devices, process info and fence info using
/proc/pid/fdinfo
Signed-off-by: David M Nieto
Signed-off-by: Roy Sun
---
drivers/gpu/drm/amd/amdgpu/Makefile| 2 +
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c| 61 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h| 5 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c| 5 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c | 98 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.h | 43 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 20 +
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 2 +
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 45 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 2 +
11 files changed, 282 insertions(+), 2 deletions(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.h
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
b/drivers/gpu/drm/amd/amdgpu/Makefile
index ee85e8aba636..d216b7ecb5d1 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -58,6 +58,8 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
amdgpu_umc.o smu_v11_0_i2c.o amdgpu_fru_eeprom.o amdgpu_rap.o \
amdgpu_fw_attestation.o amdgpu_securedisplay.o
+amdgpu-$(CONFIG_PROC_FS) += amdgpu_fdinfo.o
+
amdgpu-$(CONFIG_PERF_EVENTS) += amdgpu_pmu.o
# add asic specific block
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 125b25a5ce5b..3365feae15e1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -107,6 +107,7 @@
#include "amdgpu_gfxhub.h"
#include "amdgpu_df.h"
#include "amdgpu_smuio.h"
+#include "amdgpu_fdinfo.h"
#define MAX_GPU_INSTANCE 16
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index 0350205c4897..01fe60fedcbe 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -651,3 +651,64 @@ void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr)
idr_destroy(>ctx_handles);
mutex_destroy(>lock);
}
+
+void amdgpu_ctx_fence_time(struct amdgpu_ctx *ctx, struct amdgpu_ctx_entity
*centity,
+ ktime_t *total, ktime_t *max)
+{
+ ktime_t now, t1;
+ uint32_t i;
+
+ now = ktime_get();
+ for (i = 0; i < amdgpu_sched_jobs; i++) {
+ struct dma_fence *fence;
+ struct drm_sched_fence *s_fence;
+
+ spin_lock(>ring_lock);
+ fence = dma_fence_get(centity->fences[i]);
+ spin_unlock(>ring_lock);
+ if (!fence)
+ continue;
+ s_fence = to_drm_sched_fence(fence);
+ if (!dma_fence_is_signaled(_fence->scheduled))
+ continue;
+ t1 = s_fence->scheduled.timestamp;
+ if (t1 >= now)
+ continue;
+ if (dma_fence_is_signaled(_fence->finished) &&
+ s_fence->finished.timestamp < now)
+ *total += ktime_sub(s_fence->finished.timestamp, t1);
+ else
+ *total += ktime_sub(now, t1);
+ t1 = ktime_sub(now, t1);
+ dma_fence_put(fence);
+ *max = max(t1, *max);
+ }
+}
+
+ktime_t amdgpu_ctx_mgr_fence_usage(struct amdgpu_ctx_mgr *mgr, uint32_t hwip,
+ uint32_t idx, uint64_t *elapsed)
+{
+ struct idr *idp;
+ struct amdgpu_ctx *ctx;
+ uint32_t id;
+ struct amdgpu_ctx_entity *centity;
+ ktime_t total = 0, max = 0;
+
+ if (idx >= AMDGPU_MAX_ENTITY_NUM)
+ return 0;
+ idp = >ctx_handles;
+ mutex_lock(>lock);
+ idr_for_each_entry(idp, ctx, id) {
+ if (!ctx->entities[hwip][idx])
+ continue;
+
+ centity = ctx->entities[hwip][idx];
+ amdgpu_ctx_fence_time(ctx, centity, , );
+ }
+
+ mutex_unlock(>lock);
+ if (elapsed)
+ *elapsed = max;
+
+ return total;
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
index f54e10314661..10dcf59a5c6b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
@@ -87,5 +87,8 @@ void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
void amdgpu_ctx_mgr_entity_fini(struct amdgpu_ctx_mgr *mgr);
long amdgpu_ctx_mgr_entity_flush(struct amdgpu_ctx_mgr *mgr, long timeout);
void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
-
+ktime_t amdgpu_ctx_mgr_fence_usage(struct amdgpu_ctx_mgr *mgr, uint32_t hwip,
+ uint32_t idx, uint64_t *elapsed);
+void amdgpu_ctx_fence_time(struct amdgpu_ctx *ctx, struct amdgpu_ctx_entity
*centity,
+ ktime_t
Re: [PATCH 1/6] drm/amdgpu: expose amdgpu_bo_create_shadow()
Reviewed-by: Christian König for the series.
Am 23.04.21 um 13:17 schrieb Nirmoy Das:
Exposed amdgpu_bo_create_shadow() will be needed
for amdgpu_vm handling.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 3 +++
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 1345f7eba011..9cdeb20fb6cd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -625,9 +625,9 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev,
return r;
}
-static int amdgpu_bo_create_shadow(struct amdgpu_device *adev,
- unsigned long size,
- struct amdgpu_bo *bo)
+int amdgpu_bo_create_shadow(struct amdgpu_device *adev,
+ unsigned long size,
+ struct amdgpu_bo *bo)
{
struct amdgpu_bo_param bp;
int r;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
index 973c88bdf37b..e0ec48d6a3fd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
@@ -271,6 +271,9 @@ int amdgpu_bo_create_user(struct amdgpu_device *adev,
struct amdgpu_bo_user **ubo_ptr);
void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,
void **cpu_addr);
+int amdgpu_bo_create_shadow(struct amdgpu_device *adev,
+ unsigned long size,
+ struct amdgpu_bo *bo);
int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr);
void *amdgpu_bo_kptr(struct amdgpu_bo *bo);
void amdgpu_bo_kunmap(struct amdgpu_bo *bo);
___
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[PATCH 6/6] drm/amdgpu: remove AMDGPU_GEM_CREATE_SHADOW flag
Remove unused AMDGPU_GEM_CREATE_SHADOW flag.
Userspace is never allowed to use this.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 5 +
include/uapi/drm/amdgpu_drm.h | 2 --
2 files changed, 1 insertion(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 39f88e4a8eb5..da6d4ee0a132 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -649,8 +649,7 @@ int amdgpu_bo_create_shadow(struct amdgpu_device *adev,
memset(, 0, sizeof(bp));
bp.size = size;
bp.domain = AMDGPU_GEM_DOMAIN_GTT;
- bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC |
- AMDGPU_GEM_CREATE_SHADOW;
+ bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
bp.type = ttm_bo_type_kernel;
bp.resv = bo->tbo.base.resv;
bp.bo_ptr_size = sizeof(struct amdgpu_bo);
@@ -685,7 +684,6 @@ int amdgpu_bo_create_user(struct amdgpu_device *adev,
struct amdgpu_bo *bo_ptr;
int r;
- bp->flags = bp->flags & ~AMDGPU_GEM_CREATE_SHADOW;
bp->bo_ptr_size = sizeof(struct amdgpu_bo_user);
r = amdgpu_bo_create(adev, bp, _ptr);
if (r)
@@ -1559,7 +1557,6 @@ u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo,
struct seq_file *m)
amdgpu_bo_print_flag(m, bo, NO_CPU_ACCESS);
amdgpu_bo_print_flag(m, bo, CPU_GTT_USWC);
amdgpu_bo_print_flag(m, bo, VRAM_CLEARED);
- amdgpu_bo_print_flag(m, bo, SHADOW);
amdgpu_bo_print_flag(m, bo, VRAM_CONTIGUOUS);
amdgpu_bo_print_flag(m, bo, VM_ALWAYS_VALID);
amdgpu_bo_print_flag(m, bo, EXPLICIT_SYNC);
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index 8b832f7458f2..9169df7fadee 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -119,8 +119,6 @@ extern "C" {
#define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2)
/* Flag that the memory should be in VRAM and cleared */
#define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3)
-/* Flag that create shadow bo(GTT) while allocating vram bo */
-#define AMDGPU_GEM_CREATE_SHADOW (1 << 4)
/* Flag that allocating the BO should use linear VRAM */
#define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5)
/* Flag that BO is always valid in this VM */
--
2.31.1
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[PATCH 5/6] drm/amdgpu: cleanup amdgpu_bo_create()
Remove shadow bo related code as vm code is creating shadow bo
using proper API. Without shadow bo code, amdgpu_bo_create() is basically
a wrapper around amdgpu_bo_do_create(). So rename amdgpu_bo_do_create()
to amdgpu_bo_create().
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 61 +-
1 file changed, 14 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 9cdeb20fb6cd..39f88e4a8eb5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -515,7 +515,18 @@ bool amdgpu_bo_support_uswc(u64 bo_flags)
#endif
}
-static int amdgpu_bo_do_create(struct amdgpu_device *adev,
+/**
+ * amdgpu_bo_create - create an _bo buffer object
+ * @adev: amdgpu device object
+ * @bp: parameters to be used for the buffer object
+ * @bo_ptr: pointer to the buffer object pointer
+ *
+ * Creates an _bo buffer object.
+ *
+ * Returns:
+ * 0 for success or a negative error code on failure.
+ */
+int amdgpu_bo_create(struct amdgpu_device *adev,
struct amdgpu_bo_param *bp,
struct amdgpu_bo **bo_ptr)
{
@@ -644,7 +655,7 @@ int amdgpu_bo_create_shadow(struct amdgpu_device *adev,
bp.resv = bo->tbo.base.resv;
bp.bo_ptr_size = sizeof(struct amdgpu_bo);
- r = amdgpu_bo_do_create(adev, , >shadow);
+ r = amdgpu_bo_create(adev, , >shadow);
if (!r) {
bo->shadow->parent = amdgpu_bo_ref(bo);
mutex_lock(>shadow_list_lock);
@@ -655,50 +666,6 @@ int amdgpu_bo_create_shadow(struct amdgpu_device *adev,
return r;
}
-/**
- * amdgpu_bo_create - create an _bo buffer object
- * @adev: amdgpu device object
- * @bp: parameters to be used for the buffer object
- * @bo_ptr: pointer to the buffer object pointer
- *
- * Creates an _bo buffer object; and if requested, also creates a
- * shadow object.
- * Shadow object is used to backup the original buffer object, and is always
- * in GTT.
- *
- * Returns:
- * 0 for success or a negative error code on failure.
- */
-int amdgpu_bo_create(struct amdgpu_device *adev,
-struct amdgpu_bo_param *bp,
-struct amdgpu_bo **bo_ptr)
-{
- u64 flags = bp->flags;
- int r;
-
- bp->flags = bp->flags & ~AMDGPU_GEM_CREATE_SHADOW;
-
- r = amdgpu_bo_do_create(adev, bp, bo_ptr);
- if (r)
- return r;
-
- if ((flags & AMDGPU_GEM_CREATE_SHADOW) && !(adev->flags & AMD_IS_APU)) {
- if (!bp->resv)
- WARN_ON(dma_resv_lock((*bo_ptr)->tbo.base.resv,
- NULL));
-
- r = amdgpu_bo_create_shadow(adev, bp->size, *bo_ptr);
-
- if (!bp->resv)
- dma_resv_unlock((*bo_ptr)->tbo.base.resv);
-
- if (r)
- amdgpu_bo_unref(bo_ptr);
- }
-
- return r;
-}
-
/**
* amdgpu_bo_create_user - create an _bo_user buffer object
* @adev: amdgpu device object
@@ -720,7 +687,7 @@ int amdgpu_bo_create_user(struct amdgpu_device *adev,
bp->flags = bp->flags & ~AMDGPU_GEM_CREATE_SHADOW;
bp->bo_ptr_size = sizeof(struct amdgpu_bo_user);
- r = amdgpu_bo_do_create(adev, bp, _ptr);
+ r = amdgpu_bo_create(adev, bp, _ptr);
if (r)
return r;
--
2.31.1
___
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[PATCH 3/6] drm/amdgpu: remove unused vm context flags
Remove unused AMDGPU_VM_CONTEXT_GFX and AMDGPU_VM_CONTEXT_COMPUTE flags. Signed-off-by: Nirmoy Das Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h index 7f07acae447b..6a9dcedfcf89 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h @@ -121,9 +121,6 @@ struct amdgpu_bo_list_entry; /* max vmids dedicated for process */ #define AMDGPU_VM_MAX_RESERVED_VMID1 -#define AMDGPU_VM_CONTEXT_GFX 0 -#define AMDGPU_VM_CONTEXT_COMPUTE 1 - /* See vm_update_mode */ #define AMDGPU_VM_USE_CPU_FOR_GFX (1 << 0) #define AMDGPU_VM_USE_CPU_FOR_COMPUTE (1 << 1) -- 2.31.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 4/6] create shadow bo using amdgpu_bo_create_shadow()
Shadow BOs are only needed for vm code so call amdgpu_bo_create_shadow()
directly instead of depending on amdgpu_bo_create().
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 69 +-
1 file changed, 45 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 577148a4ffaa..9a864a391170 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -850,35 +850,60 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
}
/**
- * amdgpu_vm_bo_param - fill in parameters for PD/PT allocation
+ * amdgpu_vm_pt_create - create bo for PD/PT
*
* @adev: amdgpu_device pointer
* @vm: requesting vm
* @level: the page table level
* @immediate: use a immediate update
- * @bp: resulting BO allocation parameters
+ * @bo: pointer to the buffer object pointer
*/
-static void amdgpu_vm_bo_param(struct amdgpu_device *adev, struct amdgpu_vm
*vm,
+static int amdgpu_vm_pt_create(struct amdgpu_device *adev,
+ struct amdgpu_vm *vm,
int level, bool immediate,
- struct amdgpu_bo_param *bp)
+ struct amdgpu_bo **bo)
{
- memset(bp, 0, sizeof(*bp));
+ struct amdgpu_bo_param bp;
+ int r;
- bp->size = amdgpu_vm_bo_size(adev, level);
- bp->byte_align = AMDGPU_GPU_PAGE_SIZE;
- bp->domain = AMDGPU_GEM_DOMAIN_VRAM;
- bp->domain = amdgpu_bo_get_preferred_pin_domain(adev, bp->domain);
- bp->flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
+ memset(, 0, sizeof(bp));
+
+ bp.size = amdgpu_vm_bo_size(adev, level);
+ bp.byte_align = AMDGPU_GPU_PAGE_SIZE;
+ bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
+ bp.domain = amdgpu_bo_get_preferred_pin_domain(adev, bp.domain);
+ bp.flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
AMDGPU_GEM_CREATE_CPU_GTT_USWC;
- bp->bo_ptr_size = sizeof(struct amdgpu_bo);
+ bp.bo_ptr_size = sizeof(struct amdgpu_bo);
if (vm->use_cpu_for_update)
- bp->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
- else if (!vm->root.base.bo || vm->root.base.bo->shadow)
- bp->flags |= AMDGPU_GEM_CREATE_SHADOW;
- bp->type = ttm_bo_type_kernel;
- bp->no_wait_gpu = immediate;
+ bp.flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
+
+ bp.type = ttm_bo_type_kernel;
+ bp.no_wait_gpu = immediate;
if (vm->root.base.bo)
- bp->resv = vm->root.base.bo->tbo.base.resv;
+ bp.resv = vm->root.base.bo->tbo.base.resv;
+
+ r = amdgpu_bo_create(adev, , bo);
+ if (r)
+ return r;
+
+ if (vm->is_compute_context && (adev->flags & AMD_IS_APU))
+ return 0;
+
+ if (!bp.resv)
+ WARN_ON(dma_resv_lock((*bo)->tbo.base.resv,
+ NULL));
+ r = amdgpu_bo_create_shadow(adev, bp.size, *bo);
+
+ if (!bp.resv)
+ dma_resv_unlock((*bo)->tbo.base.resv);
+
+ if (r) {
+ amdgpu_bo_unref(bo);
+ return r;
+ }
+
+ return 0;
}
/**
@@ -901,7 +926,6 @@ static int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
bool immediate)
{
struct amdgpu_vm_pt *entry = cursor->entry;
- struct amdgpu_bo_param bp;
struct amdgpu_bo *pt;
int r;
@@ -919,9 +943,7 @@ static int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
if (entry->base.bo)
return 0;
- amdgpu_vm_bo_param(adev, vm, cursor->level, immediate, );
-
- r = amdgpu_bo_create(adev, , );
+ r = amdgpu_vm_pt_create(adev, vm, cursor->level, immediate, );
if (r)
return r;
@@ -2784,7 +2806,6 @@ long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long
timeout)
*/
int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, u32 pasid)
{
- struct amdgpu_bo_param bp;
struct amdgpu_bo *root;
int r, i;
@@ -2835,8 +2856,8 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct
amdgpu_vm *vm, u32 pasid)
mutex_init(>eviction_lock);
vm->evicting = false;
- amdgpu_vm_bo_param(adev, vm, adev->vm_manager.root_level, false, );
- r = amdgpu_bo_create(adev, , );
+ r = amdgpu_vm_pt_create(adev, vm, adev->vm_manager.root_level,
+ false, );
if (r)
goto error_free_delayed;
--
2.31.1
___
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[PATCH 2/6] drm/amdgpu: cleanup amdgpu_vm_init()
Currently only way to create compute vm is through
amdgpu_vm_make_compute(). So vm_context isn't required
anymore for amdgpu_vm_init().
Signed-off-by: Nirmoy Das
Reviewed-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 3 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 16 +++-
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 3 +--
3 files changed, 6 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 39ee88d29cca..07e8a7c28561 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -1114,7 +1114,8 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct
drm_file *file_priv)
dev_warn(adev->dev, "No more PASIDs available!");
pasid = 0;
}
- r = amdgpu_vm_init(adev, >vm, AMDGPU_VM_CONTEXT_GFX, pasid);
+
+ r = amdgpu_vm_init(adev, >vm, pasid);
if (r)
goto error_pasid;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index f95bcda8463f..577148a4ffaa 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -2782,8 +2782,7 @@ long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long
timeout)
* Returns:
* 0 for success, error for failure.
*/
-int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
- int vm_context, u32 pasid)
+int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, u32 pasid)
{
struct amdgpu_bo_param bp;
struct amdgpu_bo *root;
@@ -2817,16 +2816,9 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct
amdgpu_vm *vm,
vm->pte_support_ats = false;
vm->is_compute_context = false;
- if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE) {
- vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
- AMDGPU_VM_USE_CPU_FOR_COMPUTE);
+ vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
+ AMDGPU_VM_USE_CPU_FOR_GFX);
- if (adev->asic_type == CHIP_RAVEN)
- vm->pte_support_ats = true;
- } else {
- vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
- AMDGPU_VM_USE_CPU_FOR_GFX);
- }
DRM_DEBUG_DRIVER("VM update mode is %s\n",
vm->use_cpu_for_update ? "CPU" : "SDMA");
WARN_ONCE((vm->use_cpu_for_update &&
@@ -2844,8 +2836,6 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct
amdgpu_vm *vm,
vm->evicting = false;
amdgpu_vm_bo_param(adev, vm, adev->vm_manager.root_level, false, );
- if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE)
- bp.flags &= ~AMDGPU_GEM_CREATE_SHADOW;
r = amdgpu_bo_create(adev, , );
if (r)
goto error_free_delayed;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 848e175e99ff..7f07acae447b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -379,8 +379,7 @@ void amdgpu_vm_manager_init(struct amdgpu_device *adev);
void amdgpu_vm_manager_fini(struct amdgpu_device *adev);
long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout);
-int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
- int vm_context, u32 pasid);
+int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, u32
pasid);
int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm,
u32 pasid);
void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm
*vm);
void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
--
2.31.1
___
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[PATCH 1/6] drm/amdgpu: expose amdgpu_bo_create_shadow()
Exposed amdgpu_bo_create_shadow() will be needed
for amdgpu_vm handling.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 3 +++
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 1345f7eba011..9cdeb20fb6cd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -625,9 +625,9 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev,
return r;
}
-static int amdgpu_bo_create_shadow(struct amdgpu_device *adev,
- unsigned long size,
- struct amdgpu_bo *bo)
+int amdgpu_bo_create_shadow(struct amdgpu_device *adev,
+ unsigned long size,
+ struct amdgpu_bo *bo)
{
struct amdgpu_bo_param bp;
int r;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
index 973c88bdf37b..e0ec48d6a3fd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
@@ -271,6 +271,9 @@ int amdgpu_bo_create_user(struct amdgpu_device *adev,
struct amdgpu_bo_user **ubo_ptr);
void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,
void **cpu_addr);
+int amdgpu_bo_create_shadow(struct amdgpu_device *adev,
+ unsigned long size,
+ struct amdgpu_bo *bo);
int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr);
void *amdgpu_bo_kptr(struct amdgpu_bo *bo);
void amdgpu_bo_kunmap(struct amdgpu_bo *bo);
--
2.31.1
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Re: [PATCH 1/2] drm/scheduler: Change scheduled fence track
[AMD Official Use Only - Internal Distribution Only]
From: amd-gfx on behalf of Roy Sun
Sent: Friday, April 23, 2021 6:55 PM
To: amd-gfx@lists.freedesktop.org
Cc: Sun, Roy ; Nieto, David M
Subject: [PATCH 1/2] drm/scheduler: Change scheduled fence track
Update the timestamp of scheduled fence on HW
completion of the previous fences
This allow more accurate tracking of the fence
execution in HW
Signed-off-by: David M Nieto
Signed-off-by: Roy Sun
---
drivers/gpu/drm/scheduler/sched_main.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/scheduler/sched_main.c
b/drivers/gpu/drm/scheduler/sched_main.c
index 92d8de24d0a1..dc05a20a8ef2 100644
--- a/drivers/gpu/drm/scheduler/sched_main.c
+++ b/drivers/gpu/drm/scheduler/sched_main.c
@@ -515,7 +515,7 @@ void drm_sched_resubmit_jobs(struct drm_gpu_scheduler
*sched)
EXPORT_SYMBOL(drm_sched_resubmit_jobs);
/**
- * drm_sched_resubmit_jobs_ext - helper to relunch certain number of jobs from
mirror ring list
+ * drm_sched_resubmit_jobs_ext - helper to relaunch certain number of jobs
from pending list
*
* @sched: scheduler instance
* @max: job numbers to relaunch
@@ -671,7 +671,7 @@ drm_sched_select_entity(struct drm_gpu_scheduler *sched)
static struct drm_sched_job *
drm_sched_get_cleanup_job(struct drm_gpu_scheduler *sched)
{
- struct drm_sched_job *job;
+ struct drm_sched_job *job, *next;
/*
* Don't destroy jobs while the timeout worker is running OR thread
@@ -690,6 +690,13 @@ drm_sched_get_cleanup_job(struct drm_gpu_scheduler *sched)
if (job && dma_fence_is_signaled(>s_fence->finished)) {
/* remove job from pending_list */
list_del_init(>list);
+ /* account for the next fence in the queue */
+ next = list_first_entry_or_null(>pending_list,
+ struct drm_sched_job, list);
+ if (next) {
+ next->s_fence->scheduled.timestamp =
+ job->s_fence->finished.timestamp;
+ }
1. the timestamp maybe is invalid, we'd better check
DMA_FENCE_FLAG_TIMESTAMP_BIT before use it .
2. when hw_submission > 2, do we need to check rest jobs? not only next.
Thanks,
Kevin.
} else {
job = NULL;
/* queue timeout for next job */
--
2.31.1
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[PATCH 1/2] drm/scheduler: Change scheduled fence track
Update the timestamp of scheduled fence on HW
completion of the previous fences
This allow more accurate tracking of the fence
execution in HW
Signed-off-by: David M Nieto
Signed-off-by: Roy Sun
---
drivers/gpu/drm/scheduler/sched_main.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/scheduler/sched_main.c
b/drivers/gpu/drm/scheduler/sched_main.c
index 92d8de24d0a1..dc05a20a8ef2 100644
--- a/drivers/gpu/drm/scheduler/sched_main.c
+++ b/drivers/gpu/drm/scheduler/sched_main.c
@@ -515,7 +515,7 @@ void drm_sched_resubmit_jobs(struct drm_gpu_scheduler
*sched)
EXPORT_SYMBOL(drm_sched_resubmit_jobs);
/**
- * drm_sched_resubmit_jobs_ext - helper to relunch certain number of jobs from
mirror ring list
+ * drm_sched_resubmit_jobs_ext - helper to relaunch certain number of jobs
from pending list
*
* @sched: scheduler instance
* @max: job numbers to relaunch
@@ -671,7 +671,7 @@ drm_sched_select_entity(struct drm_gpu_scheduler *sched)
static struct drm_sched_job *
drm_sched_get_cleanup_job(struct drm_gpu_scheduler *sched)
{
- struct drm_sched_job *job;
+ struct drm_sched_job *job, *next;
/*
* Don't destroy jobs while the timeout worker is running OR thread
@@ -690,6 +690,13 @@ drm_sched_get_cleanup_job(struct drm_gpu_scheduler *sched)
if (job && dma_fence_is_signaled(>s_fence->finished)) {
/* remove job from pending_list */
list_del_init(>list);
+ /* account for the next fence in the queue */
+ next = list_first_entry_or_null(>pending_list,
+ struct drm_sched_job, list);
+ if (next) {
+ next->s_fence->scheduled.timestamp =
+ job->s_fence->finished.timestamp;
+ }
} else {
job = NULL;
/* queue timeout for next job */
--
2.31.1
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[PATCH 2/2] drm/amdgpu: Add show_fdinfo() interface
Tracking devices, process info and fence info using
/proc/pid/fdinfo
Signed-off-by: David M Nieto
Signed-off-by: Roy Sun
---
drivers/gpu/drm/amd/amdgpu/Makefile| 2 +
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c| 61 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h| 5 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c| 5 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c | 98 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.h | 43 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 20 +
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 2 +
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 45 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 2 +
11 files changed, 282 insertions(+), 2 deletions(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.h
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
b/drivers/gpu/drm/amd/amdgpu/Makefile
index ee85e8aba636..d216b7ecb5d1 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -58,6 +58,8 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
amdgpu_umc.o smu_v11_0_i2c.o amdgpu_fru_eeprom.o amdgpu_rap.o \
amdgpu_fw_attestation.o amdgpu_securedisplay.o
+amdgpu-$(CONFIG_PROC_FS) += amdgpu_fdinfo.o
+
amdgpu-$(CONFIG_PERF_EVENTS) += amdgpu_pmu.o
# add asic specific block
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 125b25a5ce5b..3365feae15e1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -107,6 +107,7 @@
#include "amdgpu_gfxhub.h"
#include "amdgpu_df.h"
#include "amdgpu_smuio.h"
+#include "amdgpu_fdinfo.h"
#define MAX_GPU_INSTANCE 16
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index 0350205c4897..01fe60fedcbe 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -651,3 +651,64 @@ void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr)
idr_destroy(>ctx_handles);
mutex_destroy(>lock);
}
+
+void amdgpu_ctx_fence_time(struct amdgpu_ctx *ctx, struct amdgpu_ctx_entity
*centity,
+ ktime_t *total, ktime_t *max)
+{
+ ktime_t now, t1;
+ uint32_t i;
+
+ now = ktime_get();
+ for (i = 0; i < amdgpu_sched_jobs; i++) {
+ struct dma_fence *fence;
+ struct drm_sched_fence *s_fence;
+
+ spin_lock(>ring_lock);
+ fence = dma_fence_get(centity->fences[i]);
+ spin_unlock(>ring_lock);
+ if (!fence)
+ continue;
+ s_fence = to_drm_sched_fence(fence);
+ if (!dma_fence_is_signaled(_fence->scheduled))
+ continue;
+ t1 = s_fence->scheduled.timestamp;
+ if (t1 >= now)
+ continue;
+ if (dma_fence_is_signaled(_fence->finished) &&
+ s_fence->finished.timestamp < now)
+ *total += ktime_sub(s_fence->finished.timestamp, t1);
+ else
+ *total += ktime_sub(now, t1);
+ t1 = ktime_sub(now, t1);
+ dma_fence_put(fence);
+ *max = max(t1, *max);
+ }
+}
+
+ktime_t amdgpu_ctx_mgr_fence_usage(struct amdgpu_ctx_mgr *mgr, uint32_t hwip,
+ uint32_t idx, uint64_t *elapsed)
+{
+ struct idr *idp;
+ struct amdgpu_ctx *ctx;
+ uint32_t id;
+ struct amdgpu_ctx_entity *centity;
+ ktime_t total = 0, max = 0;
+
+ if (idx >= AMDGPU_MAX_ENTITY_NUM)
+ return 0;
+ idp = >ctx_handles;
+ mutex_lock(>lock);
+ idr_for_each_entry(idp, ctx, id) {
+ if (!ctx->entities[hwip][idx])
+ continue;
+
+ centity = ctx->entities[hwip][idx];
+ amdgpu_ctx_fence_time(ctx, centity, , );
+ }
+
+ mutex_unlock(>lock);
+ if (elapsed)
+ *elapsed = max;
+
+ return total;
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
index f54e10314661..10dcf59a5c6b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
@@ -87,5 +87,8 @@ void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
void amdgpu_ctx_mgr_entity_fini(struct amdgpu_ctx_mgr *mgr);
long amdgpu_ctx_mgr_entity_flush(struct amdgpu_ctx_mgr *mgr, long timeout);
void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
-
+ktime_t amdgpu_ctx_mgr_fence_usage(struct amdgpu_ctx_mgr *mgr, uint32_t hwip,
+ uint32_t idx, uint64_t *elapsed);
+void amdgpu_ctx_fence_time(struct amdgpu_ctx *ctx, struct amdgpu_ctx_entity
*centity,
+ ktime_t *total, ktime_t *max);
#endif
diff --git
Re: [PATCH 2/2] drm/amdgpu: Add show_fdinfo() interface
Am 23.04.21 um 11:19 schrieb Roy Sun:
Tracking devices, process info and fence info using
/proc/pid/fdinfo
Signed-off-by: David M Nieto
Signed-off-by: Roy Sun
---
drivers/gpu/drm/amd/amdgpu/Makefile| 2 +
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c| 61 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h| 5 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c| 5 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c | 96 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.h | 43 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 20 +
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 2 +
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 45 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 2 +
11 files changed, 280 insertions(+), 2 deletions(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.h
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
b/drivers/gpu/drm/amd/amdgpu/Makefile
index ee85e8aba636..d216b7ecb5d1 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -58,6 +58,8 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
amdgpu_umc.o smu_v11_0_i2c.o amdgpu_fru_eeprom.o amdgpu_rap.o \
amdgpu_fw_attestation.o amdgpu_securedisplay.o
+amdgpu-$(CONFIG_PROC_FS) += amdgpu_fdinfo.o
+
amdgpu-$(CONFIG_PERF_EVENTS) += amdgpu_pmu.o
# add asic specific block
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 125b25a5ce5b..3365feae15e1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -107,6 +107,7 @@
#include "amdgpu_gfxhub.h"
#include "amdgpu_df.h"
#include "amdgpu_smuio.h"
+#include "amdgpu_fdinfo.h"
#define MAX_GPU_INSTANCE 16
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index 0350205c4897..01fe60fedcbe 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -651,3 +651,64 @@ void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr)
idr_destroy(>ctx_handles);
mutex_destroy(>lock);
}
+
+void amdgpu_ctx_fence_time(struct amdgpu_ctx *ctx, struct amdgpu_ctx_entity
*centity,
+ ktime_t *total, ktime_t *max)
+{
+ ktime_t now, t1;
+ uint32_t i;
+
+ now = ktime_get();
+ for (i = 0; i < amdgpu_sched_jobs; i++) {
+ struct dma_fence *fence;
+ struct drm_sched_fence *s_fence;
+
+ spin_lock(>ring_lock);
+ fence = dma_fence_get(centity->fences[i]);
+ spin_unlock(>ring_lock);
+ if (!fence)
+ continue;
+ s_fence = to_drm_sched_fence(fence);
+ if (!dma_fence_is_signaled(_fence->scheduled))
+ continue;
+ t1 = s_fence->scheduled.timestamp;
+ if (t1 >= now)
+ continue;
+ if (dma_fence_is_signaled(_fence->finished) &&
+ s_fence->finished.timestamp < now)
+ *total += ktime_sub(s_fence->finished.timestamp, t1);
+ else
+ *total += ktime_sub(now, t1);
+ t1 = ktime_sub(now, t1);
+ dma_fence_put(fence);
+ *max = max(t1, *max);
+ }
+}
+
+ktime_t amdgpu_ctx_mgr_fence_usage(struct amdgpu_ctx_mgr *mgr, uint32_t hwip,
+ uint32_t idx, uint64_t *elapsed)
+{
+ struct idr *idp;
+ struct amdgpu_ctx *ctx;
+ uint32_t id;
+ struct amdgpu_ctx_entity *centity;
+ ktime_t total = 0, max = 0;
+
+ if (idx >= AMDGPU_MAX_ENTITY_NUM)
+ return 0;
+ idp = >ctx_handles;
+ mutex_lock(>lock);
+ idr_for_each_entry(idp, ctx, id) {
+ if (!ctx->entities[hwip][idx])
+ continue;
+
+ centity = ctx->entities[hwip][idx];
+ amdgpu_ctx_fence_time(ctx, centity, , );
+ }
+
+ mutex_unlock(>lock);
+ if (elapsed)
+ *elapsed = max;
+
+ return total;
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
index f54e10314661..10dcf59a5c6b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
@@ -87,5 +87,8 @@ void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
void amdgpu_ctx_mgr_entity_fini(struct amdgpu_ctx_mgr *mgr);
long amdgpu_ctx_mgr_entity_flush(struct amdgpu_ctx_mgr *mgr, long timeout);
void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
-
+ktime_t amdgpu_ctx_mgr_fence_usage(struct amdgpu_ctx_mgr *mgr, uint32_t hwip,
+ uint32_t idx, uint64_t *elapsed);
+void amdgpu_ctx_fence_time(struct amdgpu_ctx *ctx, struct amdgpu_ctx_entity
*centity,
+
Re: [PATCH 4/6] create shadow bo using amdgpu_bo_create_shadow()
On 4/23/21 9:55 AM, Christian König wrote:
Am 22.04.21 um 17:40 schrieb Nirmoy Das:
Shadow BOs are only needed for vm code so call amdgpu_bo_create_shadow()
directly instead of depending on amdgpu_bo_create().
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 70 +-
1 file changed, 47 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 577148a4ffaa..bb5506ff80dd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -850,35 +850,63 @@ static int amdgpu_vm_clear_bo(struct
amdgpu_device *adev,
}
/**
- * amdgpu_vm_bo_param - fill in parameters for PD/PT allocation
+ * amdgpu_vm_pt_create - create bo for PD/PT
*
* @adev: amdgpu_device pointer
* @vm: requesting vm
* @level: the page table level
* @immediate: use a immediate update
- * @bp: resulting BO allocation parameters
+ * @bo: pointer to the buffer object pointer
*/
-static void amdgpu_vm_bo_param(struct amdgpu_device *adev, struct
amdgpu_vm *vm,
+static int amdgpu_vm_pt_create(struct amdgpu_device *adev,
+ struct amdgpu_vm *vm,
int level, bool immediate,
- struct amdgpu_bo_param *bp)
+ struct amdgpu_bo **bo)
{
- memset(bp, 0, sizeof(*bp));
+ struct amdgpu_bo_param bp;
+ bool create_shadow = false;
As far as I can see this variable is only set and never used.
Please clean that up, apart from that looks good to me.
Sorry I missed that :/ . Re-sending!
Christian.
+ int r;
- bp->size = amdgpu_vm_bo_size(adev, level);
- bp->byte_align = AMDGPU_GPU_PAGE_SIZE;
- bp->domain = AMDGPU_GEM_DOMAIN_VRAM;
- bp->domain = amdgpu_bo_get_preferred_pin_domain(adev, bp->domain);
- bp->flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
+ memset(, 0, sizeof(bp));
+
+ bp.size = amdgpu_vm_bo_size(adev, level);
+ bp.byte_align = AMDGPU_GPU_PAGE_SIZE;
+ bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
+ bp.domain = amdgpu_bo_get_preferred_pin_domain(adev, bp.domain);
+ bp.flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
AMDGPU_GEM_CREATE_CPU_GTT_USWC;
- bp->bo_ptr_size = sizeof(struct amdgpu_bo);
+ bp.bo_ptr_size = sizeof(struct amdgpu_bo);
if (vm->use_cpu_for_update)
- bp->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
+ bp.flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
else if (!vm->root.base.bo || vm->root.base.bo->shadow)
- bp->flags |= AMDGPU_GEM_CREATE_SHADOW;
- bp->type = ttm_bo_type_kernel;
- bp->no_wait_gpu = immediate;
+ create_shadow = true;
+
+ bp.type = ttm_bo_type_kernel;
+ bp.no_wait_gpu = immediate;
if (vm->root.base.bo)
- bp->resv = vm->root.base.bo->tbo.base.resv;
+ bp.resv = vm->root.base.bo->tbo.base.resv;
+
+ r = amdgpu_bo_create(adev, , bo);
+ if (r)
+ return r;
+
+ if (vm->is_compute_context && (adev->flags & AMD_IS_APU))
+ return 0;
+
+ if (!bp.resv)
+ WARN_ON(dma_resv_lock((*bo)->tbo.base.resv,
+ NULL));
+ r = amdgpu_bo_create_shadow(adev, bp.size, *bo);
+
+ if (!bp.resv)
+ dma_resv_unlock((*bo)->tbo.base.resv);
+
+ if (r) {
+ amdgpu_bo_unref(bo);
+ return r;
+ }
+
+ return 0;
}
/**
@@ -901,7 +929,6 @@ static int amdgpu_vm_alloc_pts(struct
amdgpu_device *adev,
bool immediate)
{
struct amdgpu_vm_pt *entry = cursor->entry;
- struct amdgpu_bo_param bp;
struct amdgpu_bo *pt;
int r;
@@ -919,9 +946,7 @@ static int amdgpu_vm_alloc_pts(struct
amdgpu_device *adev,
if (entry->base.bo)
return 0;
- amdgpu_vm_bo_param(adev, vm, cursor->level, immediate, );
-
- r = amdgpu_bo_create(adev, , );
+ r = amdgpu_vm_pt_create(adev, vm, cursor->level, immediate, );
if (r)
return r;
@@ -2784,7 +2809,6 @@ long amdgpu_vm_wait_idle(struct amdgpu_vm
*vm, long timeout)
*/
int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm
*vm, u32 pasid)
{
- struct amdgpu_bo_param bp;
struct amdgpu_bo *root;
int r, i;
@@ -2835,8 +2859,8 @@ int amdgpu_vm_init(struct amdgpu_device
*adev, struct amdgpu_vm *vm, u32 pasid)
mutex_init(>eviction_lock);
vm->evicting = false;
- amdgpu_vm_bo_param(adev, vm, adev->vm_manager.root_level,
false, );
- r = amdgpu_bo_create(adev, , );
+ r = amdgpu_vm_pt_create(adev, vm, adev->vm_manager.root_level,
+ false, );
if (r)
goto error_free_delayed;
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[PATCH] drm/amdgpu: fix concurrent VM flushes on Vega/Navi v2
Starting with Vega the hardware supports concurrent flushes
of VMID which can be used to implement per process VMID
allocation.
But concurrent flushes are mutual exclusive with back to
back VMID allocations, fix this to avoid a VMID used in
two ways at the same time.
v2: don't set ring to NULL
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c | 19 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 6 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 1 +
3 files changed, 18 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
index 94b069630db3..b4971e90b98c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
@@ -215,7 +215,11 @@ static int amdgpu_vmid_grab_idle(struct amdgpu_vm *vm,
/* Check if we have an idle VMID */
i = 0;
list_for_each_entry((*idle), _mgr->ids_lru, list) {
- fences[i] = amdgpu_sync_peek_fence(&(*idle)->active, ring);
+ /* Don't use per engine and per process VMID at the same time */
+ struct amdgpu_ring *r = adev->vm_manager.concurrent_flush ?
+ NULL : ring;
+
+ fences[i] = amdgpu_sync_peek_fence(&(*idle)->active, r);
if (!fences[i])
break;
++i;
@@ -281,7 +285,7 @@ static int amdgpu_vmid_grab_reserved(struct amdgpu_vm *vm,
if (updates && (*id)->flushed_updates &&
updates->context == (*id)->flushed_updates->context &&
!dma_fence_is_later(updates, (*id)->flushed_updates))
- updates = NULL;
+ updates = NULL;
if ((*id)->owner != vm->immediate.fence_context ||
job->vm_pd_addr != (*id)->pd_gpu_addr ||
@@ -290,6 +294,10 @@ static int amdgpu_vmid_grab_reserved(struct amdgpu_vm *vm,
!dma_fence_is_signaled((*id)->last_flush))) {
struct dma_fence *tmp;
+ /* Don't use per engine and per process VMID at the same time */
+ if (adev->vm_manager.concurrent_flush)
+ ring = NULL;
+
/* to prevent one context starved by another context */
(*id)->pd_gpu_addr = 0;
tmp = amdgpu_sync_peek_fence(&(*id)->active, ring);
@@ -365,12 +373,7 @@ static int amdgpu_vmid_grab_used(struct amdgpu_vm *vm,
if (updates && (!flushed || dma_fence_is_later(updates,
flushed)))
needs_flush = true;
- /* Concurrent flushes are only possible starting with Vega10 and
-* are broken on Navi10 and Navi14.
-*/
- if (needs_flush && (adev->asic_type < CHIP_VEGA10 ||
- adev->asic_type == CHIP_NAVI10 ||
- adev->asic_type == CHIP_NAVI14))
+ if (needs_flush && !adev->vm_manager.concurrent_flush)
continue;
/* Good, we can use this VMID. Remember this submission as
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index f95bcda8463f..adc4481b05fb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -3149,6 +3149,12 @@ void amdgpu_vm_manager_init(struct amdgpu_device *adev)
{
unsigned i;
+ /* Concurrent flushes are only possible starting with Vega10 and
+* are broken on Navi10 and Navi14.
+*/
+ adev->vm_manager.concurrent_flush = !(adev->asic_type < CHIP_VEGA10 ||
+ adev->asic_type == CHIP_NAVI10 ||
+ adev->asic_type == CHIP_NAVI14);
amdgpu_vmid_mgr_init(adev);
adev->vm_manager.fence_context =
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 848e175e99ff..163763f8b418 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -331,6 +331,7 @@ struct amdgpu_vm_manager {
/* Handling of VMIDs */
struct amdgpu_vmid_mgr id_mgr[AMDGPU_MAX_VMHUBS];
unsigned intfirst_kfd_vmid;
+ boolconcurrent_flush;
/* Handling of VM fences */
u64 fence_context;
--
2.25.1
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[PATCH 2/2] drm/amdgpu: Add show_fdinfo() interface
Tracking devices, process info and fence info using
/proc/pid/fdinfo
Signed-off-by: David M Nieto
Signed-off-by: Roy Sun
---
drivers/gpu/drm/amd/amdgpu/Makefile| 2 +
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c| 61 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h| 5 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c| 5 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c | 96 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.h | 43 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 20 +
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 2 +
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 45 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 2 +
11 files changed, 280 insertions(+), 2 deletions(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.h
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
b/drivers/gpu/drm/amd/amdgpu/Makefile
index ee85e8aba636..d216b7ecb5d1 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -58,6 +58,8 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
amdgpu_umc.o smu_v11_0_i2c.o amdgpu_fru_eeprom.o amdgpu_rap.o \
amdgpu_fw_attestation.o amdgpu_securedisplay.o
+amdgpu-$(CONFIG_PROC_FS) += amdgpu_fdinfo.o
+
amdgpu-$(CONFIG_PERF_EVENTS) += amdgpu_pmu.o
# add asic specific block
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 125b25a5ce5b..3365feae15e1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -107,6 +107,7 @@
#include "amdgpu_gfxhub.h"
#include "amdgpu_df.h"
#include "amdgpu_smuio.h"
+#include "amdgpu_fdinfo.h"
#define MAX_GPU_INSTANCE 16
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index 0350205c4897..01fe60fedcbe 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -651,3 +651,64 @@ void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr)
idr_destroy(>ctx_handles);
mutex_destroy(>lock);
}
+
+void amdgpu_ctx_fence_time(struct amdgpu_ctx *ctx, struct amdgpu_ctx_entity
*centity,
+ ktime_t *total, ktime_t *max)
+{
+ ktime_t now, t1;
+ uint32_t i;
+
+ now = ktime_get();
+ for (i = 0; i < amdgpu_sched_jobs; i++) {
+ struct dma_fence *fence;
+ struct drm_sched_fence *s_fence;
+
+ spin_lock(>ring_lock);
+ fence = dma_fence_get(centity->fences[i]);
+ spin_unlock(>ring_lock);
+ if (!fence)
+ continue;
+ s_fence = to_drm_sched_fence(fence);
+ if (!dma_fence_is_signaled(_fence->scheduled))
+ continue;
+ t1 = s_fence->scheduled.timestamp;
+ if (t1 >= now)
+ continue;
+ if (dma_fence_is_signaled(_fence->finished) &&
+ s_fence->finished.timestamp < now)
+ *total += ktime_sub(s_fence->finished.timestamp, t1);
+ else
+ *total += ktime_sub(now, t1);
+ t1 = ktime_sub(now, t1);
+ dma_fence_put(fence);
+ *max = max(t1, *max);
+ }
+}
+
+ktime_t amdgpu_ctx_mgr_fence_usage(struct amdgpu_ctx_mgr *mgr, uint32_t hwip,
+ uint32_t idx, uint64_t *elapsed)
+{
+ struct idr *idp;
+ struct amdgpu_ctx *ctx;
+ uint32_t id;
+ struct amdgpu_ctx_entity *centity;
+ ktime_t total = 0, max = 0;
+
+ if (idx >= AMDGPU_MAX_ENTITY_NUM)
+ return 0;
+ idp = >ctx_handles;
+ mutex_lock(>lock);
+ idr_for_each_entry(idp, ctx, id) {
+ if (!ctx->entities[hwip][idx])
+ continue;
+
+ centity = ctx->entities[hwip][idx];
+ amdgpu_ctx_fence_time(ctx, centity, , );
+ }
+
+ mutex_unlock(>lock);
+ if (elapsed)
+ *elapsed = max;
+
+ return total;
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
index f54e10314661..10dcf59a5c6b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
@@ -87,5 +87,8 @@ void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
void amdgpu_ctx_mgr_entity_fini(struct amdgpu_ctx_mgr *mgr);
long amdgpu_ctx_mgr_entity_flush(struct amdgpu_ctx_mgr *mgr, long timeout);
void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
-
+ktime_t amdgpu_ctx_mgr_fence_usage(struct amdgpu_ctx_mgr *mgr, uint32_t hwip,
+ uint32_t idx, uint64_t *elapsed);
+void amdgpu_ctx_fence_time(struct amdgpu_ctx *ctx, struct amdgpu_ctx_entity
*centity,
+ ktime_t *total, ktime_t *max);
#endif
diff --git
[PATCH 1/2] drm/scheduler: Change scheduled fence track
Update the timestamp of scheduled fence on HW
completion of the previous fences
This allow more accurate tracking of the fence
execution in HW
Signed-off-by: David M Nieto
Signed-off-by: Roy Sun
---
This is the patch that just return the memory size.
drivers/gpu/drm/scheduler/sched_main.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/scheduler/sched_main.c
b/drivers/gpu/drm/scheduler/sched_main.c
index 92d8de24d0a1..dc05a20a8ef2 100644
--- a/drivers/gpu/drm/scheduler/sched_main.c
+++ b/drivers/gpu/drm/scheduler/sched_main.c
@@ -515,7 +515,7 @@ void drm_sched_resubmit_jobs(struct drm_gpu_scheduler
*sched)
EXPORT_SYMBOL(drm_sched_resubmit_jobs);
/**
- * drm_sched_resubmit_jobs_ext - helper to relunch certain number of jobs from
mirror ring list
+ * drm_sched_resubmit_jobs_ext - helper to relaunch certain number of jobs
from pending list
*
* @sched: scheduler instance
* @max: job numbers to relaunch
@@ -671,7 +671,7 @@ drm_sched_select_entity(struct drm_gpu_scheduler *sched)
static struct drm_sched_job *
drm_sched_get_cleanup_job(struct drm_gpu_scheduler *sched)
{
- struct drm_sched_job *job;
+ struct drm_sched_job *job, *next;
/*
* Don't destroy jobs while the timeout worker is running OR thread
@@ -690,6 +690,13 @@ drm_sched_get_cleanup_job(struct drm_gpu_scheduler *sched)
if (job && dma_fence_is_signaled(>s_fence->finished)) {
/* remove job from pending_list */
list_del_init(>list);
+ /* account for the next fence in the queue */
+ next = list_first_entry_or_null(>pending_list,
+ struct drm_sched_job, list);
+ if (next) {
+ next->s_fence->scheduled.timestamp =
+ job->s_fence->finished.timestamp;
+ }
} else {
job = NULL;
/* queue timeout for next job */
--
2.31.1
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Re: [PATCH] drm/amdgpu: Enable SDMA LS for Vangogh
On Fri, Apr 23, 2021 at 04:30:10PM +0800, Su, Jinzhou (Joe) wrote:
> Add flags AMD_CG_SUPPORT_SDMA_LS for Vangogh.
> Start to open sdma ls from firmware version 70.
>
> Signed-off-by: Jinzhou Su
Reviewed-by: Huang Rui
> ---
> drivers/gpu/drm/amd/amdgpu/nv.c| 1 +
> drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 4
> 2 files changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
> index 9c4f232e81c0..82a380be8368 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nv.c
> @@ -1121,6 +1121,7 @@ static int nv_common_early_init(void *handle)
> AMD_CG_SUPPORT_GFX_FGCG |
> AMD_CG_SUPPORT_VCN_MGCG |
> AMD_CG_SUPPORT_SDMA_MGCG |
> + AMD_CG_SUPPORT_SDMA_LS |
> AMD_CG_SUPPORT_JPEG_MGCG;
> adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
> AMD_PG_SUPPORT_VCN |
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> index 4ba7fce4c0b4..7c4e0586e26d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> @@ -1593,6 +1593,10 @@ static void
> sdma_v5_2_update_medium_grain_light_sleep(struct amdgpu_device *adev
> int i;
>
> for (i = 0; i < adev->sdma.num_instances; i++) {
> +
> + if (adev->sdma.instance[i].fw_version < 70 && adev->asic_type
> == CHIP_VANGOGH)
> + adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_LS;
> +
> if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
> /* Enable sdma mem light sleep */
> def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i,
> mmSDMA0_POWER_CNTL));
> --
> 2.27.0
>
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[PATCH] drm/amdgpu: Enable SDMA LS for Vangogh
Add flags AMD_CG_SUPPORT_SDMA_LS for Vangogh.
Start to open sdma ls from firmware version 70.
Signed-off-by: Jinzhou Su
---
drivers/gpu/drm/amd/amdgpu/nv.c| 1 +
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 4
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 9c4f232e81c0..82a380be8368 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -1121,6 +1121,7 @@ static int nv_common_early_init(void *handle)
AMD_CG_SUPPORT_GFX_FGCG |
AMD_CG_SUPPORT_VCN_MGCG |
AMD_CG_SUPPORT_SDMA_MGCG |
+ AMD_CG_SUPPORT_SDMA_LS |
AMD_CG_SUPPORT_JPEG_MGCG;
adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
AMD_PG_SUPPORT_VCN |
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
index 4ba7fce4c0b4..7c4e0586e26d 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
@@ -1593,6 +1593,10 @@ static void
sdma_v5_2_update_medium_grain_light_sleep(struct amdgpu_device *adev
int i;
for (i = 0; i < adev->sdma.num_instances; i++) {
+
+ if (adev->sdma.instance[i].fw_version < 70 && adev->asic_type
== CHIP_VANGOGH)
+ adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_LS;
+
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
/* Enable sdma mem light sleep */
def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i,
mmSDMA0_POWER_CNTL));
--
2.27.0
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Re: [PATCH 6/6] drm/amdgpu: remove AMDGPU_GEM_CREATE_SHADOW flag
Am 22.04.21 um 17:40 schrieb Nirmoy Das:
Remove unused AMDGPU_GEM_CREATE_SHADOW flag.
Please add "Userspace as never allowed to use this." to the commit message.
Christian.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 5 +
include/uapi/drm/amdgpu_drm.h | 2 --
2 files changed, 1 insertion(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 39f88e4a8eb5..da6d4ee0a132 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -649,8 +649,7 @@ int amdgpu_bo_create_shadow(struct amdgpu_device *adev,
memset(, 0, sizeof(bp));
bp.size = size;
bp.domain = AMDGPU_GEM_DOMAIN_GTT;
- bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC |
- AMDGPU_GEM_CREATE_SHADOW;
+ bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
bp.type = ttm_bo_type_kernel;
bp.resv = bo->tbo.base.resv;
bp.bo_ptr_size = sizeof(struct amdgpu_bo);
@@ -685,7 +684,6 @@ int amdgpu_bo_create_user(struct amdgpu_device *adev,
struct amdgpu_bo *bo_ptr;
int r;
- bp->flags = bp->flags & ~AMDGPU_GEM_CREATE_SHADOW;
bp->bo_ptr_size = sizeof(struct amdgpu_bo_user);
r = amdgpu_bo_create(adev, bp, _ptr);
if (r)
@@ -1559,7 +1557,6 @@ u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo,
struct seq_file *m)
amdgpu_bo_print_flag(m, bo, NO_CPU_ACCESS);
amdgpu_bo_print_flag(m, bo, CPU_GTT_USWC);
amdgpu_bo_print_flag(m, bo, VRAM_CLEARED);
- amdgpu_bo_print_flag(m, bo, SHADOW);
amdgpu_bo_print_flag(m, bo, VRAM_CONTIGUOUS);
amdgpu_bo_print_flag(m, bo, VM_ALWAYS_VALID);
amdgpu_bo_print_flag(m, bo, EXPLICIT_SYNC);
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index 8b832f7458f2..9169df7fadee 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -119,8 +119,6 @@ extern "C" {
#define AMDGPU_GEM_CREATE_CPU_GTT_USWC(1 << 2)
/* Flag that the memory should be in VRAM and cleared */
#define AMDGPU_GEM_CREATE_VRAM_CLEARED(1 << 3)
-/* Flag that create shadow bo(GTT) while allocating vram bo */
-#define AMDGPU_GEM_CREATE_SHADOW (1 << 4)
/* Flag that allocating the BO should use linear VRAM */
#define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5)
/* Flag that BO is always valid in this VM */
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Re: [PATCH 4/6] create shadow bo using amdgpu_bo_create_shadow()
Am 22.04.21 um 17:40 schrieb Nirmoy Das:
Shadow BOs are only needed for vm code so call amdgpu_bo_create_shadow()
directly instead of depending on amdgpu_bo_create().
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 70 +-
1 file changed, 47 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 577148a4ffaa..bb5506ff80dd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -850,35 +850,63 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
}
/**
- * amdgpu_vm_bo_param - fill in parameters for PD/PT allocation
+ * amdgpu_vm_pt_create - create bo for PD/PT
*
* @adev: amdgpu_device pointer
* @vm: requesting vm
* @level: the page table level
* @immediate: use a immediate update
- * @bp: resulting BO allocation parameters
+ * @bo: pointer to the buffer object pointer
*/
-static void amdgpu_vm_bo_param(struct amdgpu_device *adev, struct amdgpu_vm
*vm,
+static int amdgpu_vm_pt_create(struct amdgpu_device *adev,
+ struct amdgpu_vm *vm,
int level, bool immediate,
- struct amdgpu_bo_param *bp)
+ struct amdgpu_bo **bo)
{
- memset(bp, 0, sizeof(*bp));
+ struct amdgpu_bo_param bp;
+ bool create_shadow = false;
As far as I can see this variable is only set and never used.
Please clean that up, apart from that looks good to me.
Christian.
+ int r;
- bp->size = amdgpu_vm_bo_size(adev, level);
- bp->byte_align = AMDGPU_GPU_PAGE_SIZE;
- bp->domain = AMDGPU_GEM_DOMAIN_VRAM;
- bp->domain = amdgpu_bo_get_preferred_pin_domain(adev, bp->domain);
- bp->flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
+ memset(, 0, sizeof(bp));
+
+ bp.size = amdgpu_vm_bo_size(adev, level);
+ bp.byte_align = AMDGPU_GPU_PAGE_SIZE;
+ bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
+ bp.domain = amdgpu_bo_get_preferred_pin_domain(adev, bp.domain);
+ bp.flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
AMDGPU_GEM_CREATE_CPU_GTT_USWC;
- bp->bo_ptr_size = sizeof(struct amdgpu_bo);
+ bp.bo_ptr_size = sizeof(struct amdgpu_bo);
if (vm->use_cpu_for_update)
- bp->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
+ bp.flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
else if (!vm->root.base.bo || vm->root.base.bo->shadow)
- bp->flags |= AMDGPU_GEM_CREATE_SHADOW;
- bp->type = ttm_bo_type_kernel;
- bp->no_wait_gpu = immediate;
+ create_shadow = true;
+
+ bp.type = ttm_bo_type_kernel;
+ bp.no_wait_gpu = immediate;
if (vm->root.base.bo)
- bp->resv = vm->root.base.bo->tbo.base.resv;
+ bp.resv = vm->root.base.bo->tbo.base.resv;
+
+ r = amdgpu_bo_create(adev, , bo);
+ if (r)
+ return r;
+
+ if (vm->is_compute_context && (adev->flags & AMD_IS_APU))
+ return 0;
+
+ if (!bp.resv)
+ WARN_ON(dma_resv_lock((*bo)->tbo.base.resv,
+ NULL));
+ r = amdgpu_bo_create_shadow(adev, bp.size, *bo);
+
+ if (!bp.resv)
+ dma_resv_unlock((*bo)->tbo.base.resv);
+
+ if (r) {
+ amdgpu_bo_unref(bo);
+ return r;
+ }
+
+ return 0;
}
/**
@@ -901,7 +929,6 @@ static int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
bool immediate)
{
struct amdgpu_vm_pt *entry = cursor->entry;
- struct amdgpu_bo_param bp;
struct amdgpu_bo *pt;
int r;
@@ -919,9 +946,7 @@ static int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
if (entry->base.bo)
return 0;
- amdgpu_vm_bo_param(adev, vm, cursor->level, immediate, );
-
- r = amdgpu_bo_create(adev, , );
+ r = amdgpu_vm_pt_create(adev, vm, cursor->level, immediate, );
if (r)
return r;
@@ -2784,7 +2809,6 @@ long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout)
*/
int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, u32
pasid)
{
- struct amdgpu_bo_param bp;
struct amdgpu_bo *root;
int r, i;
@@ -2835,8 +2859,8 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, u32 pasid)
mutex_init(>eviction_lock);
vm->evicting = false;
- amdgpu_vm_bo_param(adev, vm, adev->vm_manager.root_level, false, );
- r = amdgpu_bo_create(adev, , );
+ r = amdgpu_vm_pt_create(adev, vm, adev->vm_manager.root_level,
+ false, );
if (r)
goto error_free_delayed;
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
Re: [PATCH v2 04/10] drm/amdgpu: Simplify AQL queue mapping
Am 2021-04-22 um 9:33 p.m. schrieb Zeng, Oak:
> Regards,
> Oak
>
>
>
> On 2021-04-21, 9:31 PM, "amd-gfx on behalf of Felix Kuehling"
>
> wrote:
>
> Do AQL queue double-mapping with a single attach call. That will make it
> easier to create per-GPU BOs later, to be shared between the two BO VA
> mappings on the same GPU.
>
> Freeing the attachments is not necessary if map_to_gpu fails. These will
> be
> cleaned up when the kdg_mem object is destroyed in
> amdgpu_amdkfd_gpuvm_free_memory_of_gpu.
>
> Signed-off-by: Felix Kuehling
> ---
> .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 103 --
> 1 file changed, 48 insertions(+), 55 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> index 34c9a2d0028e..fbd7e786b54e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> @@ -486,70 +486,76 @@ static uint64_t get_pte_flags(struct amdgpu_device
> *adev, struct kgd_mem *mem)
> * 4a. Validate new page tables and directories
> */
> static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem
> *mem,
> - struct amdgpu_vm *vm, bool is_aql,
> - struct kfd_mem_attachment **p_attachment)
> + struct amdgpu_vm *vm, bool is_aql)
> {
> unsigned long bo_size = mem->bo->tbo.base.size;
> uint64_t va = mem->va;
> - struct kfd_mem_attachment *attachment;
> - struct amdgpu_bo *bo;
> - int ret;
> + struct kfd_mem_attachment *attachment[2] = {NULL, NULL};
> + struct amdgpu_bo *bo[2] = {NULL, NULL};
> + int i, ret;
>
> if (!va) {
> pr_err("Invalid VA when adding BO to VM\n");
> return -EINVAL;
> }
>
> - if (is_aql)
> - va += bo_size;
> -
> - attachment = kzalloc(sizeof(*attachment), GFP_KERNEL);
> - if (!attachment)
> - return -ENOMEM;
> + for (i = 0; i <= is_aql; i++) {
> + attachment[i] = kzalloc(sizeof(*attachment[i]), GFP_KERNEL);
> + if (unlikely(!attachment[i])) {
> + ret = -ENOMEM;
> + goto unwind;
> + }
>
> - pr_debug("\t add VA 0x%llx - 0x%llx to vm %p\n", va,
> - va + bo_size, vm);
> + pr_debug("\t add VA 0x%llx - 0x%llx to vm %p\n", va,
> + va + bo_size, vm);
>
> - /* FIXME: For now all attachments use the same BO. This is incorrect
> - * because one BO can only have one DMA mapping for one GPU. We need
> - * one BO per GPU, e.g. a DMABuf import with dynamic attachment. This
> - * will be addressed one BO-type at a time in subsequent patches.
> - */
> - bo = mem->bo;
> - drm_gem_object_get(>tbo.base);
> + /* FIXME: For now all attachments use the same BO. This is
> + * incorrect because one BO can only have one DMA mapping
> + * for one GPU. We need one BO per GPU, e.g. a DMABuf
> + * import with dynamic attachment. This will be addressed
> + * one BO-type at a time in subsequent patches.
> + */
> + bo[i] = mem->bo;
> + drm_gem_object_get([i]->tbo.base);
>
> - /* Add BO to VM internal data structures*/
> - attachment->bo_va = amdgpu_vm_bo_add(adev, vm, bo);
> - if (!attachment->bo_va) {
> - ret = -EINVAL;
> - pr_err("Failed to add BO object to VM. ret == %d\n",
> - ret);
> - goto err_vmadd;
> - }
> + /* Add BO to VM internal data structures */
> + attachment[i]->bo_va = amdgpu_vm_bo_add(adev, vm, bo[i]);
> Just for discussion. Are we allowed to add one bo twice to a vm? When I
> looked at amdgpu_vm_bo_base_init (called by amdgpu_vm_bo_add), line:
> bo->vm_bo = base;
> when you add the same bo to vm the second time, bo->vm_bo will be
> overwritten. I am not sure whether this will cause an issue later.
> This is not introduced by your code. The original code (calling
> kfd_mem_attach twice for aql) has the same problem.
If you just add one more line of context, you'll see that bo->vm_bo is
the start of a single linked list of struct amdgpu_vm_bo_base. So adding
a BO to a VM multiple times just extends that single-linked list:
base->next = bo->vm_bo;
bo->vm_bo = base;
Regards,
Felix
> + if (unlikely(!attachment[i]->bo_va)) {
> + ret = -ENOMEM;
> + pr_err("Failed to add BO object to VM. ret == %d\n",
> +ret);
> + goto unwind;
> + }
>
> - attachment->va = va;
> - attachment->pte_flags = get_pte_flags(adev, mem);
> - attachment->adev = adev;
> - list_add(>list, >attachments);
> +
Re: [PATCH v2 1/2] drm/amdgpu: address remove from fault filter
Am 2021-04-22 um 10:03 p.m. schrieb Philip Yang:
> Add interface to remove address from fault filter ring by resetting
> fault ring entry of the fault address timestamp to 0, then future vm
> fault on the address will be processed to recover.
>
> Use spinlock to protect fault hash ring access by interrupt handler and
> interrupt scheduled deferred work for vg20.
This needs a better explanation. When you say Vega20, I think you're
referring to the lack of HW IH rerouting. In that case
amdgpu_gmc_filter_faults runs in interrupt context before delegating the
IH entries to the SW IH ring.
On GPUs that support IH rerouting, amdgpu_gmc_filter_faults runs in the
same thread as the page fault handling, so there is no risk of
concurrently accessing the fault ring assuming that
amdgpu_gmc_filter_faults_remove is only called from the page fault handler.
Christian had an idea to do this without a lock, by using cmpxchg. I
guess that idea didn't work out?
>
> Signed-off-by: Philip Yang
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 66 +++--
> drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 3 ++
> drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 1 +
> 4 files changed, 68 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> index c39ed9eb0987..801ea0623453 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> @@ -332,6 +332,17 @@ void amdgpu_gmc_agp_location(struct amdgpu_device *adev,
> struct amdgpu_gmc *mc)
> mc->agp_size >> 20, mc->agp_start, mc->agp_end);
> }
>
> +/**
> + * fault_key - get 52bit hask key from vm fault address and pasid
> + *
> + * @addr: 48bit physical address
> + * @pasid: 4 bit
> + */
> +static inline uint64_t fault_key(uint64_t addr, uint16_t pasid)
> +{
> + return addr << 4 | pasid;
> +}
> +
> /**
> * amdgpu_gmc_filter_faults - filter VM faults
> *
> @@ -349,15 +360,20 @@ bool amdgpu_gmc_filter_faults(struct amdgpu_device
> *adev, uint64_t addr,
> {
> struct amdgpu_gmc *gmc = >gmc;
>
> - uint64_t stamp, key = addr << 4 | pasid;
> + uint64_t stamp, key = fault_key(addr, pasid);
> struct amdgpu_gmc_fault *fault;
> + unsigned long flags;
> uint32_t hash;
>
> /* If we don't have space left in the ring buffer return immediately */
> stamp = max(timestamp, AMDGPU_GMC_FAULT_TIMEOUT + 1) -
> AMDGPU_GMC_FAULT_TIMEOUT;
> - if (gmc->fault_ring[gmc->last_fault].timestamp >= stamp)
> +
> + spin_lock_irqsave(>fault_lock, flags);
> + if (gmc->fault_ring[gmc->last_fault].timestamp >= stamp) {
> + spin_unlock_irqrestore(>fault_lock, flags);
> return true;
> + }
>
> /* Try to find the fault in the hash */
> hash = hash_64(key, AMDGPU_GMC_FAULT_HASH_ORDER);
> @@ -365,8 +381,10 @@ bool amdgpu_gmc_filter_faults(struct amdgpu_device
> *adev, uint64_t addr,
> while (fault->timestamp >= stamp) {
> uint64_t tmp;
>
> - if (fault->key == key)
> + if (fault->key == key) {
> + spin_unlock_irqrestore(>fault_lock, flags);
> return true;
> + }
>
> tmp = fault->timestamp;
> fault = >fault_ring[fault->next];
> @@ -384,9 +402,51 @@ bool amdgpu_gmc_filter_faults(struct amdgpu_device
> *adev, uint64_t addr,
> /* And update the hash */
> fault->next = gmc->fault_hash[hash].idx;
> gmc->fault_hash[hash].idx = gmc->last_fault++;
> + spin_unlock_irqrestore(>fault_lock, flags);
> return false;
> }
>
> +/**
> + * amdgpu_gmc_filter_faults_remove - remove address from VM faults filter
> + *
> + * @adev: amdgpu device structure
> + * @addr: address of the VM fault
> + * @pasid: PASID of the process causing the fault
> + *
> + * Remove the address from fault filter, then future vm fault on this address
> + * will pass to retry fault handler to recover.
> + */
> +void amdgpu_gmc_filter_faults_remove(struct amdgpu_device *adev, uint64_t
> addr,
> + uint16_t pasid)
> +{
> + struct amdgpu_gmc *gmc = >gmc;
> +
> + uint64_t key = fault_key(addr, pasid);
> + struct amdgpu_gmc_fault *fault;
> + unsigned long flags;
> + uint32_t hash;
> +
> + spin_lock_irqsave(>fault_lock, flags);
> + hash = hash_64(key, AMDGPU_GMC_FAULT_HASH_ORDER);
> + fault = >fault_ring[gmc->fault_hash[hash].idx];
> + while (true) {
> + uint64_t tmp;
> +
> + if (fault->key == key) {
> + fault->timestamp = 0;
Setting the timestamp to 0 breaks the chain of interrupts with the same
hash. As you can see in amdgpu_gmc_filter_faults, it uses a closed hash
algorithm that looks for the entry with the correct key until it hits a
time stamp that's too old. So
