RE: [PATCH] drm/amdgpu: Add vbios info ioctl interface

[Gu, JiaWei (Will)]

[Public]

Hi all,

Then the struct looks like:

> +struct drm_amdgpu_info_vbios {
> + __u8 name[64];
> + __u8 vbios_pn[64];
> + __u32 version;
> + __u8 vbios_ver_str[32];
> + __u8 date[32];
> +};

Sample output:

vbios name : NAVI12 A0 XT D30501 8GB EVAL 1150e/334m HYN/SAM
vbios pn : 113-D3050100-104
vbios version : 285409288
vbios ver_str : 017.003.000.008.016956
vbios date : 2021/05/03 23:32

Please help double confirm that we're all fine with it and there's no need to 
add & remove anything.

Best regards,
Jiawei

From: Nieto, David M 
Sent: Tuesday, May 18, 2021 12:40 PM
To: Gu, JiaWei (Will) ; Koenig, Christian 
; amd-gfx@lists.freedesktop.org; mar...@gmail.com; 
Deucher, Alexander 
Cc: Deng, Emily 
Subject: Re: [PATCH] drm/amdgpu: Add vbios info ioctl interface


[Public]

Yes, let's remove that too,

Thanks,

David

From: Gu, JiaWei (Will) mailto:jiawei...@amd.com>>
Sent: Monday, May 17, 2021 8:07 PM
To: Nieto, David M mailto:david.ni...@amd.com>>; Koenig, 
Christian mailto:christian.koe...@amd.com>>; 
amd-gfx@lists.freedesktop.org 
mailto:amd-gfx@lists.freedesktop.org>>; 
mar...@gmail.com 
mailto:mar...@gmail.com>>; Deucher, Alexander 
mailto:alexander.deuc...@amd.com>>
Cc: Deng, Emily mailto:emily.d...@amd.com>>
Subject: RE: [PATCH] drm/amdgpu: Add vbios info ioctl interface


[AMD Official Use Only - Internal Distribution Only]



OK let's remove serial.



dbdf comes from this:

vbios_info.dbdf = PCI_DEVID(adev->pdev->bus->number, adev->pdev->devfn);



I think we can remove dbdf as well.



Best regards,

Jiawei



From: Nieto, David M mailto:david.ni...@amd.com>>
Sent: Tuesday, May 18, 2021 10:45 AM
To: Gu, JiaWei (Will) mailto:jiawei...@amd.com>>; Koenig, 
Christian mailto:christian.koe...@amd.com>>; 
amd-gfx@lists.freedesktop.org; 
mar...@gmail.com; Deucher, Alexander 
mailto:alexander.deuc...@amd.com>>
Cc: Deng, Emily mailto:emily.d...@amd.com>>
Subject: Re: [PATCH] drm/amdgpu: Add vbios info ioctl interface



[AMD Official Use Only - Internal Distribution Only]



The serial number is ASIC information, not VBIOS information, and it is still 
available as a sysfs node... I don't think we should put it there.



Not sure what dbdf stands for.



From: Gu, JiaWei (Will) mailto:jiawei...@amd.com>>
Sent: Monday, May 17, 2021 7:11 PM
To: Koenig, Christian 
mailto:christian.koe...@amd.com>>; 
amd-gfx@lists.freedesktop.org 
mailto:amd-gfx@lists.freedesktop.org>>; Nieto, 
David M mailto:david.ni...@amd.com>>; 
mar...@gmail.com 
mailto:mar...@gmail.com>>; Deucher, Alexander 
mailto:alexander.deuc...@amd.com>>
Cc: Deng, Emily mailto:emily.d...@amd.com>>
Subject: RE: [PATCH] drm/amdgpu: Add vbios info ioctl interface



[AMD Official Use Only - Internal Distribution Only]

So I guess the dbdf is also needed to be removed?
And how about serial?

> +struct drm_amdgpu_info_vbios {
> + __u8 name[64];
> + __u32 dbdf; // do we need this?
> + __u8 vbios_pn[64];
> + __u32 version;
> + __u8 vbios_ver_str[32];
> + __u8 date[32];
> + __u64 serial; // do we need this?
> +};

Best regards,
Jiawei

-Original Message-
From: Koenig, Christian 
mailto:christian.koe...@amd.com>>
Sent: Monday, May 17, 2021 8:26 PM
To: Gu, JiaWei (Will) mailto:jiawei...@amd.com>>; 
amd-gfx@lists.freedesktop.org; Nieto, 
David M mailto:david.ni...@amd.com>>; 
mar...@gmail.com; Deucher, Alexander 
mailto:alexander.deuc...@amd.com>>
Cc: Deng, Emily mailto:emily.d...@amd.com>>
Subject: Re: [PATCH] drm/amdgpu: Add vbios info ioctl interface

I'm not very familiar with the technical background why we have the fields here 
once more.

But of hand we should at least remove everything which is also available from 
the PCI information.

E.g. dev_id, rev_id, sub_dev_id, sub_ved_id.

Regards,
Christian.

Am 17.05.21 um 14:17 schrieb Gu, JiaWei (Will):
> [AMD Official Use Only - Internal Distribution Only]
>
> Hi all,
>
> Thanks Christian's suggestion.
> I reverted the previous patches and squash them into this single one.
>
> As this patch shows, the current uapi change looks like this:
>
> +struct drm_amdgpu_info_vbios {
> + __u8 name[64];
> + __u32 dbdf;
> + __u8 vbios_pn[64];
> + __u32 version;
> + __u8 vbios_ver_str[32];
> + __u8 date[32];
> + __u64 serial;
> + __u32 dev_id;
> + __u32 rev_id;
> + __u32 sub_dev_id;
> + __u32 sub_ved_id;
> +};
>
> As we know there's some redundant info in this struct.
> Please feel free to give any comments or suggestion about what it should & 
> shouldn't include.
>
> Best regards,
> Jiawei
>
> -Original Message-
> From: Jiawei Gu mailto:jiawei...@amd.com>>
> Sent: Monday, May 17, 2021 8:08 PM
> 

Re: [PATCH] drm/amdgpu: Add vbios info ioctl interface

[Nieto, David M]

[Public]

Yes, let's remove that too,

Thanks,

David

From: Gu, JiaWei (Will) 
Sent: Monday, May 17, 2021 8:07 PM
To: Nieto, David M ; Koenig, Christian 
; amd-gfx@lists.freedesktop.org 
; mar...@gmail.com ; Deucher, 
Alexander 
Cc: Deng, Emily 
Subject: RE: [PATCH] drm/amdgpu: Add vbios info ioctl interface


[AMD Official Use Only - Internal Distribution Only]



OK let’s remove serial.



dbdf comes from this:

vbios_info.dbdf = PCI_DEVID(adev->pdev->bus->number, adev->pdev->devfn);



I think we can remove dbdf as well.



Best regards,

Jiawei



From: Nieto, David M 
Sent: Tuesday, May 18, 2021 10:45 AM
To: Gu, JiaWei (Will) ; Koenig, Christian 
; amd-gfx@lists.freedesktop.org; mar...@gmail.com; 
Deucher, Alexander 
Cc: Deng, Emily 
Subject: Re: [PATCH] drm/amdgpu: Add vbios info ioctl interface



[AMD Official Use Only - Internal Distribution Only]



The serial number is ASIC information, not VBIOS information, and it is still 
available as a sysfs node... I don't think we should put it there.



Not sure what dbdf stands for.



From: Gu, JiaWei (Will) mailto:jiawei...@amd.com>>
Sent: Monday, May 17, 2021 7:11 PM
To: Koenig, Christian 
mailto:christian.koe...@amd.com>>; 
amd-gfx@lists.freedesktop.org 
mailto:amd-gfx@lists.freedesktop.org>>; Nieto, 
David M mailto:david.ni...@amd.com>>; 
mar...@gmail.com 
mailto:mar...@gmail.com>>; Deucher, Alexander 
mailto:alexander.deuc...@amd.com>>
Cc: Deng, Emily mailto:emily.d...@amd.com>>
Subject: RE: [PATCH] drm/amdgpu: Add vbios info ioctl interface



[AMD Official Use Only - Internal Distribution Only]

So I guess the dbdf is also needed to be removed?
And how about serial?

> +struct drm_amdgpu_info_vbios {
> + __u8 name[64];
> + __u32 dbdf; // do we need this?
> + __u8 vbios_pn[64];
> + __u32 version;
> + __u8 vbios_ver_str[32];
> + __u8 date[32];
> + __u64 serial; // do we need this?
> +};

Best regards,
Jiawei

-Original Message-
From: Koenig, Christian 
mailto:christian.koe...@amd.com>>
Sent: Monday, May 17, 2021 8:26 PM
To: Gu, JiaWei (Will) mailto:jiawei...@amd.com>>; 
amd-gfx@lists.freedesktop.org; Nieto, 
David M mailto:david.ni...@amd.com>>; 
mar...@gmail.com; Deucher, Alexander 
mailto:alexander.deuc...@amd.com>>
Cc: Deng, Emily mailto:emily.d...@amd.com>>
Subject: Re: [PATCH] drm/amdgpu: Add vbios info ioctl interface

I'm not very familiar with the technical background why we have the fields here 
once more.

But of hand we should at least remove everything which is also available from 
the PCI information.

E.g. dev_id, rev_id, sub_dev_id, sub_ved_id.

Regards,
Christian.

Am 17.05.21 um 14:17 schrieb Gu, JiaWei (Will):
> [AMD Official Use Only - Internal Distribution Only]
>
> Hi all,
>
> Thanks Christian's suggestion.
> I reverted the previous patches and squash them into this single one.
>
> As this patch shows, the current uapi change looks like this:
>
> +struct drm_amdgpu_info_vbios {
> + __u8 name[64];
> + __u32 dbdf;
> + __u8 vbios_pn[64];
> + __u32 version;
> + __u8 vbios_ver_str[32];
> + __u8 date[32];
> + __u64 serial;
> + __u32 dev_id;
> + __u32 rev_id;
> + __u32 sub_dev_id;
> + __u32 sub_ved_id;
> +};
>
> As we know there's some redundant info in this struct.
> Please feel free to give any comments or suggestion about what it should & 
> shouldn't include.
>
> Best regards,
> Jiawei
>
> -Original Message-
> From: Jiawei Gu mailto:jiawei...@amd.com>>
> Sent: Monday, May 17, 2021 8:08 PM
> To: amd-gfx@lists.freedesktop.org; 
> Koenig, Christian
> mailto:christian.koe...@amd.com>>; Nieto, David M 
> mailto:david.ni...@amd.com>>;
> mar...@gmail.com; Deucher, Alexander 
> mailto:alexander.deuc...@amd.com>>
> Cc: Deng, Emily mailto:emily.d...@amd.com>>; Gu, JiaWei 
> (Will)
> mailto:jiawei...@amd.com>>
> Subject: [PATCH] drm/amdgpu: Add vbios info ioctl interface
>
> Add AMDGPU_INFO_VBIOS_INFO subquery id for detailed vbios info.
>
> Provides a way for the user application to get the VBIOS information without 
> having to parse the binary.
> It is useful for the user to be able to display in a simple way the VBIOS 
> version in their system if they happen to encounter an issue.
>
> V2:
> Use numeric serial.
> Parse and expose vbios version string.
>
> Signed-off-by: Jiawei Gu mailto:jiawei...@amd.com>>
> Acked-by: Christian König 
> mailto:christian.koe...@amd.com>>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c|  21 +++
>   drivers/gpu/drm/amd/amdgpu/atom.c  | 174 +
>   drivers/gpu/drm/amd/amdgpu/atom.h  |  12 ++
>   drivers/gpu/drm/amd/include/atomfirmware.h |   5 +
>   include/uapi/drm/amdgpu_drm.h  |  16 ++
>   5 files changed, 228 

[PATCH 2/3] drm/amdgpu/pm: add new fields for Navi1x

[David M Nieto]

Fill voltage fields in metrics table

Signed-off-by: David M Nieto 
---
 .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c   | 62 ++-
 1 file changed, 45 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index ac13042672ea..9339fd24ae8c 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -505,7 +505,7 @@ static int navi10_tables_init(struct smu_context *smu)
goto err0_out;
smu_table->metrics_time = 0;
 
-   smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_1);
+   smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
smu_table->gpu_metrics_table = 
kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
if (!smu_table->gpu_metrics_table)
goto err1_out;
@@ -2627,10 +2627,11 @@ static ssize_t navi10_get_legacy_gpu_metrics(struct 
smu_context *smu,
 void **table)
 {
struct smu_table_context *smu_table = >smu_table;
-   struct gpu_metrics_v1_1 *gpu_metrics =
-   (struct gpu_metrics_v1_1 *)smu_table->gpu_metrics_table;
+   struct gpu_metrics_v1_3 *gpu_metrics =
+   (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
SmuMetrics_legacy_t metrics;
int ret = 0;
+   int freq = 0, dpm = 0;
 
mutex_lock(>metrics_lock);
 
@@ -2646,7 +2647,7 @@ static ssize_t navi10_get_legacy_gpu_metrics(struct 
smu_context *smu,
 
mutex_unlock(>metrics_lock);
 
-   smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 1);
+   smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
 
gpu_metrics->temperature_edge = metrics.TemperatureEdge;
gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
@@ -2681,19 +2682,26 @@ static ssize_t navi10_get_legacy_gpu_metrics(struct 
smu_context *smu,
 
gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
 
+   gpu_metrics->voltage_gfx = (155000 - 625 * 
metrics.CurrGfxVoltageOffset) / 100;
+   gpu_metrics->voltage_mem = (155000 - 625 * metrics.CurrMemVidOffset) / 
100;
+   gpu_metrics->voltage_soc = (155000 - 625 * 
metrics.CurrSocVoltageOffset) / 100;
+
*table = (void *)gpu_metrics;
 
-   return sizeof(struct gpu_metrics_v1_1);
+   return sizeof(struct gpu_metrics_v1_3);
+out:
+   return ret;
 }
 
 static ssize_t navi10_get_gpu_metrics(struct smu_context *smu,
  void **table)
 {
struct smu_table_context *smu_table = >smu_table;
-   struct gpu_metrics_v1_1 *gpu_metrics =
-   (struct gpu_metrics_v1_1 *)smu_table->gpu_metrics_table;
+   struct gpu_metrics_v1_3 *gpu_metrics =
+   (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
SmuMetrics_t metrics;
int ret = 0;
+   int freq = 0, dpm = 0;
 
mutex_lock(>metrics_lock);
 
@@ -2709,7 +2717,7 @@ static ssize_t navi10_get_gpu_metrics(struct smu_context 
*smu,
 
mutex_unlock(>metrics_lock);
 
-   smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 1);
+   smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
 
gpu_metrics->temperature_edge = metrics.TemperatureEdge;
gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
@@ -2746,19 +2754,26 @@ static ssize_t navi10_get_gpu_metrics(struct 
smu_context *smu,
 
gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
 
+   gpu_metrics->voltage_gfx = (155000 - 625 * 
metrics.CurrGfxVoltageOffset) / 100;
+   gpu_metrics->voltage_mem = (155000 - 625 * metrics.CurrMemVidOffset) / 
100;
+   gpu_metrics->voltage_soc = (155000 - 625 * 
metrics.CurrSocVoltageOffset) / 100;
+
*table = (void *)gpu_metrics;
 
-   return sizeof(struct gpu_metrics_v1_1);
+   return sizeof(struct gpu_metrics_v1_3);
+out:
+   return ret;
 }
 
 static ssize_t navi12_get_legacy_gpu_metrics(struct smu_context *smu,
 void **table)
 {
struct smu_table_context *smu_table = >smu_table;
-   struct gpu_metrics_v1_1 *gpu_metrics =
-   (struct gpu_metrics_v1_1 *)smu_table->gpu_metrics_table;
+   struct gpu_metrics_v1_3 *gpu_metrics =
+   (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
SmuMetrics_NV12_legacy_t metrics;
int ret = 0;
+   int freq = 0, dpm = 0;
 
mutex_lock(>metrics_lock);
 
@@ -2774,7 +2789,7 @@ static ssize_t navi12_get_legacy_gpu_metrics(struct 
smu_context *smu,
 
mutex_unlock(>metrics_lock);
 
-   smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 1);
+   smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
 
gpu_metrics->temperature_edge = metrics.TemperatureEdge;
gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
@@ -2814,19 +2829,26 @@ static ssize_t 

[PATCH 3/3] drm/amdgpu/pm: display vcn pp dpm

[David M Nieto]

Enable displaying DPM levels for VCN clocks
in swsmu supported ASICs

Signed-off-by: David M Nieto 
---
 .../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 46 ++
 .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c   |  4 ++
 .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c   |  8 
 .../gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c   | 38 +++
 .../drm/amd/pm/swsmu/smu13/aldebaran_ppt.c| 48 +++
 5 files changed, 144 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
index 77693bf0840c..1735a96dd307 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
@@ -822,6 +822,52 @@ static int arcturus_print_clk_levels(struct smu_context 
*smu,
now) ? "*" : ""));
break;
 
+   case SMU_VCLK:
+   ret = arcturus_get_current_clk_freq_by_table(smu, SMU_VCLK, 
);
+   if (ret) {
+   dev_err(smu->adev->dev, "Attempt to get current vclk 
Failed!");
+   return ret;
+   }
+
+   single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
+   ret = arcturus_get_clk_table(smu, , single_dpm_table);
+   if (ret) {
+   dev_err(smu->adev->dev, "Attempt to get vclk levels 
Failed!");
+   return ret;
+   }
+
+   for (i = 0; i < single_dpm_table->count; i++)
+   size += sprintf(buf + size, "%d: %uMhz %s\n",
+   i, single_dpm_table->dpm_levels[i].value,
+   (clocks.num_levels == 1) ? "*" :
+   (arcturus_freqs_in_same_level(
+   clocks.data[i].clocks_in_khz / 1000,
+   now) ? "*" : ""));
+   break;
+
+   case SMU_DCLK:
+   ret = arcturus_get_current_clk_freq_by_table(smu, SMU_DCLK, 
);
+   if (ret) {
+   dev_err(smu->adev->dev, "Attempt to get current dclk 
Failed!");
+   return ret;
+   }
+
+   single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
+   ret = arcturus_get_clk_table(smu, , single_dpm_table);
+   if (ret) {
+   dev_err(smu->adev->dev, "Attempt to get dclk levels 
Failed!");
+   return ret;
+   }
+
+   for (i = 0; i < single_dpm_table->count; i++)
+   size += sprintf(buf + size, "%d: %uMhz %s\n",
+   i, single_dpm_table->dpm_levels[i].value,
+   (clocks.num_levels == 1) ? "*" :
+   (arcturus_freqs_in_same_level(
+   clocks.data[i].clocks_in_khz / 1000,
+   now) ? "*" : ""));
+   break;
+
case SMU_PCIE:
gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index 9339fd24ae8c..2e801f2e42a9 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -1273,6 +1273,8 @@ static int navi10_print_clk_levels(struct smu_context 
*smu,
case SMU_MCLK:
case SMU_UCLK:
case SMU_FCLK:
+   case SMU_VCLK:
+   case SMU_DCLK:
case SMU_DCEFCLK:
ret = navi10_get_current_clk_freq_by_table(smu, clk_type, 
_value);
if (ret)
@@ -1444,6 +1446,8 @@ static int navi10_force_clk_levels(struct smu_context 
*smu,
case SMU_MCLK:
case SMU_UCLK:
case SMU_FCLK:
+   case SMU_VCLK:
+   case SMU_DCLK:
/* There is only 2 levels for fine grained DPM */
if (navi10_is_support_fine_grained_dpm(smu, clk_type)) {
soft_max_level = (soft_max_level >= 1 ? 1 : 0);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 0c40a54c46d7..6da6d08d8858 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -987,6 +987,10 @@ static int sienna_cichlid_print_clk_levels(struct 
smu_context *smu,
case SMU_MCLK:
case SMU_UCLK:
case SMU_FCLK:
+   case SMU_VCLK:
+   case SMU_VCLK1:
+   case SMU_DCLK:
+   case SMU_DCLK1:
case SMU_DCEFCLK:
ret = sienna_cichlid_get_current_clk_freq_by_table(smu, 
clk_type, _value);
if (ret)
@@ -1150,6 +1154,10 @@ static int sienna_cichlid_force_clk_levels(struct 
smu_context *smu,
 

[PATCH 1/3] drm/amdgpu/pm: Update metrics table

[David M Nieto]

expand metrics table with voltages and frequency ranges

Signed-off-by: David M Nieto 
---
 .../gpu/drm/amd/include/kgd_pp_interface.h| 69 +++
 drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c|  3 +
 2 files changed, 72 insertions(+)

diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h 
b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index e2d13131a432..b1cd52a9d684 100644
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -536,6 +536,75 @@ struct gpu_metrics_v1_2 {
uint64_tfirmware_timestamp;
 };
 
+struct gpu_metrics_v1_3 {
+   struct metrics_table_header common_header;
+
+   /* Temperature */
+   uint16_ttemperature_edge;
+   uint16_ttemperature_hotspot;
+   uint16_ttemperature_mem;
+   uint16_ttemperature_vrgfx;
+   uint16_ttemperature_vrsoc;
+   uint16_ttemperature_vrmem;
+
+   /* Utilization */
+   uint16_taverage_gfx_activity;
+   uint16_taverage_umc_activity; // memory 
controller
+   uint16_taverage_mm_activity; // UVD or VCN
+
+   /* Power/Energy */
+   uint16_taverage_socket_power;
+   uint64_tenergy_accumulator;
+
+   /* Driver attached timestamp (in ns) */
+   uint64_tsystem_clock_counter;
+
+   /* Average clocks */
+   uint16_taverage_gfxclk_frequency;
+   uint16_taverage_socclk_frequency;
+   uint16_taverage_uclk_frequency;
+   uint16_taverage_vclk0_frequency;
+   uint16_taverage_dclk0_frequency;
+   uint16_taverage_vclk1_frequency;
+   uint16_taverage_dclk1_frequency;
+
+   /* Current clocks */
+   uint16_tcurrent_gfxclk;
+   uint16_tcurrent_socclk;
+   uint16_tcurrent_uclk;
+   uint16_tcurrent_vclk0;
+   uint16_tcurrent_dclk0;
+   uint16_tcurrent_vclk1;
+   uint16_tcurrent_dclk1;
+
+   /* Throttle status */
+   uint32_tthrottle_status;
+
+   /* Fans */
+   uint16_tcurrent_fan_speed;
+
+   /* Link width/speed */
+   uint16_tpcie_link_width;
+   uint16_tpcie_link_speed; // in 0.1 GT/s
+
+   uint16_tpadding;
+
+   uint32_tgfx_activity_acc;
+   uint32_tmem_activity_acc;
+
+   uint16_ttemperature_hbm[NUM_HBM_INSTANCES];
+
+   /* PMFW attached timestamp (10ns resolution) */
+   uint64_tfirmware_timestamp;
+
+   /* Voltage (mV) */
+   uint16_tvoltage_soc;
+   uint16_tvoltage_gfx;
+   uint16_tvoltage_mem;
+
+   uint16_tpadding1;
+};
+
 /*
  * gpu_metrics_v2_0 is not recommended as it's not naturally aligned.
  * Use gpu_metrics_v2_1 or later instead.
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
index 0934e5b3aa17..0ceb7329838c 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
@@ -764,6 +764,9 @@ void smu_cmn_init_soft_gpu_metrics(void *table, uint8_t 
frev, uint8_t crev)
case METRICS_VERSION(1, 2):
structure_size = sizeof(struct gpu_metrics_v1_2);
break;
+   case METRICS_VERSION(1, 3):
+   structure_size = sizeof(struct gpu_metrics_v1_3);
+   break;
case METRICS_VERSION(2, 0):
structure_size = sizeof(struct gpu_metrics_v2_0);
break;
-- 
2.17.1

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RE: [PATCH] drm/amdgpu: Add vbios info ioctl interface

[Gu, JiaWei (Will)]

[AMD Official Use Only - Internal Distribution Only]

OK let's remove serial.

dbdf comes from this:
vbios_info.dbdf = PCI_DEVID(adev->pdev->bus->number, adev->pdev->devfn);

I think we can remove dbdf as well.

Best regards,
Jiawei

From: Nieto, David M 
Sent: Tuesday, May 18, 2021 10:45 AM
To: Gu, JiaWei (Will) ; Koenig, Christian 
; amd-gfx@lists.freedesktop.org; mar...@gmail.com; 
Deucher, Alexander 
Cc: Deng, Emily 
Subject: Re: [PATCH] drm/amdgpu: Add vbios info ioctl interface


[AMD Official Use Only - Internal Distribution Only]

The serial number is ASIC information, not VBIOS information, and it is still 
available as a sysfs node... I don't think we should put it there.

Not sure what dbdf stands for.

From: Gu, JiaWei (Will) mailto:jiawei...@amd.com>>
Sent: Monday, May 17, 2021 7:11 PM
To: Koenig, Christian 
mailto:christian.koe...@amd.com>>; 
amd-gfx@lists.freedesktop.org 
mailto:amd-gfx@lists.freedesktop.org>>; Nieto, 
David M mailto:david.ni...@amd.com>>; 
mar...@gmail.com 
mailto:mar...@gmail.com>>; Deucher, Alexander 
mailto:alexander.deuc...@amd.com>>
Cc: Deng, Emily mailto:emily.d...@amd.com>>
Subject: RE: [PATCH] drm/amdgpu: Add vbios info ioctl interface

[AMD Official Use Only - Internal Distribution Only]

So I guess the dbdf is also needed to be removed?
And how about serial?

> +struct drm_amdgpu_info_vbios {
> + __u8 name[64];
> + __u32 dbdf; // do we need this?
> + __u8 vbios_pn[64];
> + __u32 version;
> + __u8 vbios_ver_str[32];
> + __u8 date[32];
> + __u64 serial; // do we need this?
> +};

Best regards,
Jiawei

-Original Message-
From: Koenig, Christian 
mailto:christian.koe...@amd.com>>
Sent: Monday, May 17, 2021 8:26 PM
To: Gu, JiaWei (Will) mailto:jiawei...@amd.com>>; 
amd-gfx@lists.freedesktop.org; Nieto, 
David M mailto:david.ni...@amd.com>>; 
mar...@gmail.com; Deucher, Alexander 
mailto:alexander.deuc...@amd.com>>
Cc: Deng, Emily mailto:emily.d...@amd.com>>
Subject: Re: [PATCH] drm/amdgpu: Add vbios info ioctl interface

I'm not very familiar with the technical background why we have the fields here 
once more.

But of hand we should at least remove everything which is also available from 
the PCI information.

E.g. dev_id, rev_id, sub_dev_id, sub_ved_id.

Regards,
Christian.

Am 17.05.21 um 14:17 schrieb Gu, JiaWei (Will):
> [AMD Official Use Only - Internal Distribution Only]
>
> Hi all,
>
> Thanks Christian's suggestion.
> I reverted the previous patches and squash them into this single one.
>
> As this patch shows, the current uapi change looks like this:
>
> +struct drm_amdgpu_info_vbios {
> + __u8 name[64];
> + __u32 dbdf;
> + __u8 vbios_pn[64];
> + __u32 version;
> + __u8 vbios_ver_str[32];
> + __u8 date[32];
> + __u64 serial;
> + __u32 dev_id;
> + __u32 rev_id;
> + __u32 sub_dev_id;
> + __u32 sub_ved_id;
> +};
>
> As we know there's some redundant info in this struct.
> Please feel free to give any comments or suggestion about what it should & 
> shouldn't include.
>
> Best regards,
> Jiawei
>
> -Original Message-
> From: Jiawei Gu mailto:jiawei...@amd.com>>
> Sent: Monday, May 17, 2021 8:08 PM
> To: amd-gfx@lists.freedesktop.org; 
> Koenig, Christian
> mailto:christian.koe...@amd.com>>; Nieto, David M 
> mailto:david.ni...@amd.com>>;
> mar...@gmail.com; Deucher, Alexander 
> mailto:alexander.deuc...@amd.com>>
> Cc: Deng, Emily mailto:emily.d...@amd.com>>; Gu, JiaWei 
> (Will)
> mailto:jiawei...@amd.com>>
> Subject: [PATCH] drm/amdgpu: Add vbios info ioctl interface
>
> Add AMDGPU_INFO_VBIOS_INFO subquery id for detailed vbios info.
>
> Provides a way for the user application to get the VBIOS information without 
> having to parse the binary.
> It is useful for the user to be able to display in a simple way the VBIOS 
> version in their system if they happen to encounter an issue.
>
> V2:
> Use numeric serial.
> Parse and expose vbios version string.
>
> Signed-off-by: Jiawei Gu mailto:jiawei...@amd.com>>
> Acked-by: Christian König 
> mailto:christian.koe...@amd.com>>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c|  21 +++
>   drivers/gpu/drm/amd/amdgpu/atom.c  | 174 +
>   drivers/gpu/drm/amd/amdgpu/atom.h  |  12 ++
>   drivers/gpu/drm/amd/include/atomfirmware.h |   5 +
>   include/uapi/drm/amdgpu_drm.h  |  16 ++
>   5 files changed, 228 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> index 8d12e474745a..30e4fed3de22 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> @@ -861,6 +861,27 @@ int amdgpu_info_ioctl(struct drm_device *dev, void 
> *data, struct drm_file *filp)
>

[PATCH] drm/amdgpu: Fix a use-after-free

[xinhui pan]

looks like we forget to set ttm->sg to NULL.
Hit panic below

[ 1235.844104] general protection fault, probably for non-canonical address 
0x6b6b6b6b6b6b7b4b:  [#1] SMP DEBUG_PAGEALLOC NOPTI
[ 1235.862186] CPU: 5 PID: 25180 Comm: kfdtest Tainted: GW 
5.11.0+ #114
[ 1235.870633] Hardware name: System manufacturer System Product Name/PRIME 
Z390-A, BIOS 1401 11/26/2019
[ 1235.880689] RIP: 0010:__sg_free_table+0x55/0x90
[ 1235.885654] Code: 39 c6 77 1c 41 c7 46 0c 00 00 00 00 85 d2 74 46 49 c7 06 
00 00 00 00 5b 41 5c 41 5d 41 5e 5d c3 8d 48 ff 49 89 c8 48 c1 e1 05 <48> 8b 1c 
0f 44 29 c6 41 89 76 0c 48 83 e3 f8
[ 1235.906084] RSP: :ad1c430cfbd0 EFLAGS: 00010202
[ 1235.911671] RAX: 0080 RBX: 93e266d2e6d8 RCX: 0fe0
[ 1235.919393] RDX:  RSI: a56b6b6b RDI: 6b6b6b6b6b6b6b6b
[ 1235.927190] RBP: ad1c430cfbf0 R08: 007f R09: 0001
[ 1235.934970] R10: 0001 R11: 0001 R12: 0080
[ 1235.942766] R13: 9e7fe9f0 R14: 93e20c3488b0 R15: 93e270bc8b20
[ 1235.950563] FS:  7f5013ca63c0() GS:93f07520() 
knlGS:
[ 1235.959404] CS:  0010 DS:  ES:  CR0: 80050033
[ 1235.965683] CR2: 7ff44b08faff CR3: 00020f84e002 CR4: 003706e0
[ 1235.973472] DR0:  DR1:  DR2: 
[ 1235.981269] DR3:  DR6: fffe0ff0 DR7: 0400
[ 1235.989074] Call Trace:
[ 1235.991751]  sg_free_table+0x17/0x20
[ 1235.995667]  amdgpu_ttm_backend_unbind.cold+0x4d/0xf7 [amdgpu]
[ 1236.002288]  amdgpu_ttm_backend_destroy+0x29/0x130 [amdgpu]
[ 1236.008464]  ttm_tt_destroy+0x1e/0x30 [ttm]
[ 1236.013066]  ttm_bo_cleanup_memtype_use+0x51/0xa0 [ttm]
[ 1236.018783]  ttm_bo_release+0x262/0xa50 [ttm]
[ 1236.023547]  ttm_bo_put+0x82/0xd0 [ttm]
[ 1236.027766]  amdgpu_bo_unref+0x26/0x50 [amdgpu]
[ 1236.032809]  amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu+0x7aa/0xd90 [amdgpu]
[ 1236.040400]  kfd_ioctl_alloc_memory_of_gpu+0xe2/0x330 [amdgpu]
[ 1236.046912]  kfd_ioctl+0x463/0x690 [amdgpu]
[ 1236.051632]  ? kfd_dev_is_large_bar+0xf0/0xf0 [amdgpu]
[ 1236.057360]  __x64_sys_ioctl+0x91/0xc0
[ 1236.061457]  do_syscall_64+0x38/0x90
[ 1236.065383]  entry_SYSCALL_64_after_hwframe+0x44/0xa9
[ 1236.070920] RIP: 0033:0x7f5013dbe50b

Signed-off-by: xinhui pan 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 89cd93b24404..754f9847497d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1158,6 +1158,7 @@ static void amdgpu_ttm_tt_unpopulate(struct ttm_device 
*bdev,
if (gtt && gtt->userptr) {
amdgpu_ttm_tt_set_user_pages(ttm, NULL);
kfree(ttm->sg);
+   ttm->sg = NULL;
ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
return;
}
-- 
2.25.1

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RE: [PATCH] drm/amd/pm: correct MGpuFanBoost setting

[Feng, Kenneth]

[AMD Official Use Only]

Reviewed-by: Kenneth Feng 

-Original Message-
From: Quan, Evan  
Sent: Tuesday, May 18, 2021 10:05 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Feng, Kenneth 
; Quan, Evan 
Subject: [PATCH] drm/amd/pm: correct MGpuFanBoost setting

No MGpuFanBoost setting for those ASICs which do not support it.
Otherwise, it may breaks their fan control feature.

Change-Id: Ifa9c87ac537a07937a0f0f6a670f21368eb29218
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c|  9 +
 .../gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c| 10 ++
 2 files changed, 19 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index d2063b1e7936..f16c76038f13 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -2936,6 +2936,8 @@ static ssize_t navi1x_get_gpu_metrics(struct smu_context 
*smu,
 
 static int navi10_enable_mgpu_fan_boost(struct smu_context *smu)  {
+   struct smu_table_context *table_context = >smu_table;
+   PPTable_t *smc_pptable = table_context->driver_pptable;
struct amdgpu_device *adev = smu->adev;
uint32_t param = 0;
 
@@ -2943,6 +2945,13 @@ static int navi10_enable_mgpu_fan_boost(struct 
smu_context *smu)
if (adev->asic_type == CHIP_NAVI12)
return 0;
 
+   /*
+* Skip the MGpuFanBoost setting for those ASICs
+* which do not support it
+*/
+   if (!smc_pptable->MGpuFanBoostLimitRpm)
+   return 0;
+
/* Workaround for WS SKU */
if (adev->pdev->device == 0x7312 &&
adev->pdev->revision == 0)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 3c3a7f9233e0..159cd698323e 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -3201,6 +3201,16 @@ static ssize_t sienna_cichlid_get_gpu_metrics(struct 
smu_context *smu,
 
 static int sienna_cichlid_enable_mgpu_fan_boost(struct smu_context *smu)  {
+   struct smu_table_context *table_context = >smu_table;
+   PPTable_t *smc_pptable = table_context->driver_pptable;
+
+   /*
+* Skip the MGpuFanBoost setting for those ASICs
+* which do not support it
+*/
+   if (!smc_pptable->MGpuFanBoostLimitRpm)
+   return 0;
+
return smu_cmn_send_smc_msg_with_param(smu,
   SMU_MSG_SetMGpuFanBoostLimitRpm,
   0,
--
2.29.0
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RE: [PATCH 1/2] drm/amdgpu: update gc golden setting for Navi12

[Feng, Kenneth]

[AMD Official Use Only]

Series are Reviewed-by: Kenneth Feng 


-Original Message-
From: Chen, Guchun  
Sent: Tuesday, May 18, 2021 10:01 AM
To: amd-gfx@lists.freedesktop.org; Deucher, Alexander 
; Zhang, Hawking ; Feng, 
Kenneth ; Chen, Jiansong (Simon) ; 
Xiao, Jack ; Quan, Evan 
Cc: Chen, Guchun 
Subject: [PATCH 1/2] drm/amdgpu: update gc golden setting for Navi12

Current golden setting is out of date.

Signed-off-by: Guchun Chen 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 2a3427e5020f..7edd0c0eed8e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -1399,9 +1399,10 @@ static const struct soc15_reg_golden 
golden_settings_gc_10_1_2[] =
SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x, 0x2000),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0x, 0x0420),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x, 0x0200),
-   SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x, 0x0480),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x, 0x0490),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x, 
0x003f),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0x, 
0x03860204),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 
+0x0044),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0, 
0x0500),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x7fff, 
0x01fe),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x, 
0xe4e4e4e4), @@ -1419,12 +1420,13 @@ static const struct soc15_reg_golden 
golden_settings_gc_10_1_2[] =
SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x0820, 
0x0820),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0xff0f, 
0x),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0x, 0x3101),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f, 
+0x00070104),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0x, 
0x),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x0133, 0x0130),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0x, 
0x),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7, 0x0103),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
-   SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x, 0x0080)
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x, 0x00c0)
 };
 
 static bool gfx_v10_is_rlcg_rw(struct amdgpu_device *adev, u32 offset, 
uint32_t *flag, bool write)
--
2.17.1
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Re: [PATCH] drm/amdgpu: Add vbios info ioctl interface

[Nieto, David M]

[AMD Official Use Only - Internal Distribution Only]

The serial number is ASIC information, not VBIOS information, and it is still 
available as a sysfs node... I don't think we should put it there.

Not sure what dbdf stands for.

From: Gu, JiaWei (Will) 
Sent: Monday, May 17, 2021 7:11 PM
To: Koenig, Christian ; amd-gfx@lists.freedesktop.org 
; Nieto, David M ; 
mar...@gmail.com ; Deucher, Alexander 

Cc: Deng, Emily 
Subject: RE: [PATCH] drm/amdgpu: Add vbios info ioctl interface

[AMD Official Use Only - Internal Distribution Only]

So I guess the dbdf is also needed to be removed?
And how about serial?

> +struct drm_amdgpu_info_vbios {
> + __u8 name[64];
> + __u32 dbdf; // do we need this?
> + __u8 vbios_pn[64];
> + __u32 version;
> + __u8 vbios_ver_str[32];
> + __u8 date[32];
> + __u64 serial; // do we need this?
> +};

Best regards,
Jiawei

-Original Message-
From: Koenig, Christian 
Sent: Monday, May 17, 2021 8:26 PM
To: Gu, JiaWei (Will) ; amd-gfx@lists.freedesktop.org; 
Nieto, David M ; mar...@gmail.com; Deucher, Alexander 

Cc: Deng, Emily 
Subject: Re: [PATCH] drm/amdgpu: Add vbios info ioctl interface

I'm not very familiar with the technical background why we have the fields here 
once more.

But of hand we should at least remove everything which is also available from 
the PCI information.

E.g. dev_id, rev_id, sub_dev_id, sub_ved_id.

Regards,
Christian.

Am 17.05.21 um 14:17 schrieb Gu, JiaWei (Will):
> [AMD Official Use Only - Internal Distribution Only]
>
> Hi all,
>
> Thanks Christian's suggestion.
> I reverted the previous patches and squash them into this single one.
>
> As this patch shows, the current uapi change looks like this:
>
> +struct drm_amdgpu_info_vbios {
> + __u8 name[64];
> + __u32 dbdf;
> + __u8 vbios_pn[64];
> + __u32 version;
> + __u8 vbios_ver_str[32];
> + __u8 date[32];
> + __u64 serial;
> + __u32 dev_id;
> + __u32 rev_id;
> + __u32 sub_dev_id;
> + __u32 sub_ved_id;
> +};
>
> As we know there's some redundant info in this struct.
> Please feel free to give any comments or suggestion about what it should & 
> shouldn't include.
>
> Best regards,
> Jiawei
>
> -Original Message-
> From: Jiawei Gu 
> Sent: Monday, May 17, 2021 8:08 PM
> To: amd-gfx@lists.freedesktop.org; Koenig, Christian
> ; Nieto, David M ;
> mar...@gmail.com; Deucher, Alexander 
> Cc: Deng, Emily ; Gu, JiaWei (Will)
> 
> Subject: [PATCH] drm/amdgpu: Add vbios info ioctl interface
>
> Add AMDGPU_INFO_VBIOS_INFO subquery id for detailed vbios info.
>
> Provides a way for the user application to get the VBIOS information without 
> having to parse the binary.
> It is useful for the user to be able to display in a simple way the VBIOS 
> version in their system if they happen to encounter an issue.
>
> V2:
> Use numeric serial.
> Parse and expose vbios version string.
>
> Signed-off-by: Jiawei Gu 
> Acked-by: Christian König 
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c|  21 +++
>   drivers/gpu/drm/amd/amdgpu/atom.c  | 174 +
>   drivers/gpu/drm/amd/amdgpu/atom.h  |  12 ++
>   drivers/gpu/drm/amd/include/atomfirmware.h |   5 +
>   include/uapi/drm/amdgpu_drm.h  |  16 ++
>   5 files changed, 228 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> index 8d12e474745a..30e4fed3de22 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> @@ -861,6 +861,27 @@ int amdgpu_info_ioctl(struct drm_device *dev, void 
> *data, struct drm_file *filp)
>min((size_t)size, 
> (size_t)(bios_size - bios_offset)))
>? -EFAULT : 0;
>}
> + case AMDGPU_INFO_VBIOS_INFO: {
> + struct drm_amdgpu_info_vbios vbios_info = {};
> + struct atom_context *atom_context;
> +
> + atom_context = adev->mode_info.atom_context;
> + memcpy(vbios_info.name, atom_context->name, 
> sizeof(atom_context->name));
> + vbios_info.dbdf = PCI_DEVID(adev->pdev->bus->number, 
> adev->pdev->devfn);
> + memcpy(vbios_info.vbios_pn, atom_context->vbios_pn, 
> sizeof(atom_context->vbios_pn));
> + vbios_info.version = atom_context->version;
> + memcpy(vbios_info.vbios_ver_str, 
> atom_context->vbios_ver_str,
> + 
> sizeof(atom_context->vbios_ver_str));
> + memcpy(vbios_info.date, atom_context->date, 
> sizeof(atom_context->date));
> + vbios_info.serial = adev->unique_id;
> + vbios_info.dev_id = adev->pdev->device;
> + vbios_info.rev_id = adev->pdev->revision;
> + 

RE: [PATCH] drm/amdgpu: Add vbios info ioctl interface

[Gu, JiaWei (Will)]

[AMD Official Use Only - Internal Distribution Only]

So I guess the dbdf is also needed to be removed?
And how about serial?

> +struct drm_amdgpu_info_vbios {
> + __u8 name[64];
> + __u32 dbdf; // do we need this?
> + __u8 vbios_pn[64];
> + __u32 version;
> + __u8 vbios_ver_str[32];
> + __u8 date[32];
> + __u64 serial; // do we need this?
> +};

Best regards,
Jiawei

-Original Message-
From: Koenig, Christian  
Sent: Monday, May 17, 2021 8:26 PM
To: Gu, JiaWei (Will) ; amd-gfx@lists.freedesktop.org; 
Nieto, David M ; mar...@gmail.com; Deucher, Alexander 

Cc: Deng, Emily 
Subject: Re: [PATCH] drm/amdgpu: Add vbios info ioctl interface

I'm not very familiar with the technical background why we have the fields here 
once more.

But of hand we should at least remove everything which is also available from 
the PCI information.

E.g. dev_id, rev_id, sub_dev_id, sub_ved_id.

Regards,
Christian.

Am 17.05.21 um 14:17 schrieb Gu, JiaWei (Will):
> [AMD Official Use Only - Internal Distribution Only]
>
> Hi all,
>
> Thanks Christian's suggestion.
> I reverted the previous patches and squash them into this single one.
>
> As this patch shows, the current uapi change looks like this:
>
> +struct drm_amdgpu_info_vbios {
> + __u8 name[64];
> + __u32 dbdf;
> + __u8 vbios_pn[64];
> + __u32 version;
> + __u8 vbios_ver_str[32];
> + __u8 date[32];
> + __u64 serial;
> + __u32 dev_id;
> + __u32 rev_id;
> + __u32 sub_dev_id;
> + __u32 sub_ved_id;
> +};
>
> As we know there's some redundant info in this struct.
> Please feel free to give any comments or suggestion about what it should & 
> shouldn't include.
>
> Best regards,
> Jiawei
>
> -Original Message-
> From: Jiawei Gu 
> Sent: Monday, May 17, 2021 8:08 PM
> To: amd-gfx@lists.freedesktop.org; Koenig, Christian 
> ; Nieto, David M ; 
> mar...@gmail.com; Deucher, Alexander 
> Cc: Deng, Emily ; Gu, JiaWei (Will) 
> 
> Subject: [PATCH] drm/amdgpu: Add vbios info ioctl interface
>
> Add AMDGPU_INFO_VBIOS_INFO subquery id for detailed vbios info.
>
> Provides a way for the user application to get the VBIOS information without 
> having to parse the binary.
> It is useful for the user to be able to display in a simple way the VBIOS 
> version in their system if they happen to encounter an issue.
>
> V2:
> Use numeric serial.
> Parse and expose vbios version string.
>
> Signed-off-by: Jiawei Gu 
> Acked-by: Christian König 
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c|  21 +++
>   drivers/gpu/drm/amd/amdgpu/atom.c  | 174 +
>   drivers/gpu/drm/amd/amdgpu/atom.h  |  12 ++
>   drivers/gpu/drm/amd/include/atomfirmware.h |   5 +
>   include/uapi/drm/amdgpu_drm.h  |  16 ++
>   5 files changed, 228 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> index 8d12e474745a..30e4fed3de22 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> @@ -861,6 +861,27 @@ int amdgpu_info_ioctl(struct drm_device *dev, void 
> *data, struct drm_file *filp)
>   min((size_t)size, 
> (size_t)(bios_size - bios_offset)))
>   ? -EFAULT : 0;
>   }
> + case AMDGPU_INFO_VBIOS_INFO: {
> + struct drm_amdgpu_info_vbios vbios_info = {};
> + struct atom_context *atom_context;
> +
> + atom_context = adev->mode_info.atom_context;
> + memcpy(vbios_info.name, atom_context->name, 
> sizeof(atom_context->name));
> + vbios_info.dbdf = PCI_DEVID(adev->pdev->bus->number, 
> adev->pdev->devfn);
> + memcpy(vbios_info.vbios_pn, atom_context->vbios_pn, 
> sizeof(atom_context->vbios_pn));
> + vbios_info.version = atom_context->version;
> + memcpy(vbios_info.vbios_ver_str, 
> atom_context->vbios_ver_str,
> + 
> sizeof(atom_context->vbios_ver_str));
> + memcpy(vbios_info.date, atom_context->date, 
> sizeof(atom_context->date));
> + vbios_info.serial = adev->unique_id;
> + vbios_info.dev_id = adev->pdev->device;
> + vbios_info.rev_id = adev->pdev->revision;
> + vbios_info.sub_dev_id = atom_context->sub_dev_id;
> + vbios_info.sub_ved_id = atom_context->sub_ved_id;
> +
> + return copy_to_user(out, _info,
> + min((size_t)size, 
> sizeof(vbios_info))) ? -EFAULT : 0;
> + }
>   default:
>   DRM_DEBUG_KMS("Invalid request %d\n",
>   info->vbios_info.type);
> diff --git a/drivers/gpu/drm/amd/amdgpu/atom.c 
> 

[PATCH] drm/amd/pm: correct MGpuFanBoost setting

[Evan Quan]

No MGpuFanBoost setting for those ASICs which do not support it.
Otherwise, it may breaks their fan control feature.

Change-Id: Ifa9c87ac537a07937a0f0f6a670f21368eb29218
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c|  9 +
 .../gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c| 10 ++
 2 files changed, 19 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index d2063b1e7936..f16c76038f13 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -2936,6 +2936,8 @@ static ssize_t navi1x_get_gpu_metrics(struct smu_context 
*smu,
 
 static int navi10_enable_mgpu_fan_boost(struct smu_context *smu)
 {
+   struct smu_table_context *table_context = >smu_table;
+   PPTable_t *smc_pptable = table_context->driver_pptable;
struct amdgpu_device *adev = smu->adev;
uint32_t param = 0;
 
@@ -2943,6 +2945,13 @@ static int navi10_enable_mgpu_fan_boost(struct 
smu_context *smu)
if (adev->asic_type == CHIP_NAVI12)
return 0;
 
+   /*
+* Skip the MGpuFanBoost setting for those ASICs
+* which do not support it
+*/
+   if (!smc_pptable->MGpuFanBoostLimitRpm)
+   return 0;
+
/* Workaround for WS SKU */
if (adev->pdev->device == 0x7312 &&
adev->pdev->revision == 0)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 3c3a7f9233e0..159cd698323e 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -3201,6 +3201,16 @@ static ssize_t sienna_cichlid_get_gpu_metrics(struct 
smu_context *smu,
 
 static int sienna_cichlid_enable_mgpu_fan_boost(struct smu_context *smu)
 {
+   struct smu_table_context *table_context = >smu_table;
+   PPTable_t *smc_pptable = table_context->driver_pptable;
+
+   /*
+* Skip the MGpuFanBoost setting for those ASICs
+* which do not support it
+*/
+   if (!smc_pptable->MGpuFanBoostLimitRpm)
+   return 0;
+
return smu_cmn_send_smc_msg_with_param(smu,
   SMU_MSG_SetMGpuFanBoostLimitRpm,
   0,
-- 
2.29.0

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[PATCH 2/2] drm/amdgpu: update sdma golden setting for Navi12

[Guchun Chen]

Current golden setting is out of date.

Signed-off-by: Guchun Chen 
---
 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
index 04c68a79eca4..75d7310f8439 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
@@ -123,6 +123,10 @@ static const struct soc15_reg_golden 
golden_settings_sdma_nv14[] = {
 
 static const struct soc15_reg_golden golden_settings_sdma_nv12[] = {
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 
0xfff7, 0x00403000),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG, 0x001877ff, 
0x0044),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x001877ff, 
0x0044),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG, 0x001877ff, 
0x0044),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x001877ff, 
0x0044),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 
0xfff7, 0x00403000),
 };
 
-- 
2.17.1

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[PATCH 1/2] drm/amdgpu: update gc golden setting for Navi12

[Guchun Chen]

Current golden setting is out of date.

Signed-off-by: Guchun Chen 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 2a3427e5020f..7edd0c0eed8e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -1399,9 +1399,10 @@ static const struct soc15_reg_golden 
golden_settings_gc_10_1_2[] =
SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x, 0x2000),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0x, 0x0420),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x, 0x0200),
-   SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x, 0x0480),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x, 0x0490),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x, 
0x003f),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0x, 
0x03860204),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x0044),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0, 
0x0500),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x7fff, 
0x01fe),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x, 0xe4e4e4e4),
@@ -1419,12 +1420,13 @@ static const struct soc15_reg_golden 
golden_settings_gc_10_1_2[] =
SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x0820, 
0x0820),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0xff0f, 
0x),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0x, 0x3101),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f, 
0x00070104),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0x, 
0x),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x0133, 0x0130),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0x, 
0x),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7, 0x0103),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
-   SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x, 0x0080)
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x, 0x00c0)
 };
 
 static bool gfx_v10_is_rlcg_rw(struct amdgpu_device *adev, u32 offset, 
uint32_t *flag, bool write)
-- 
2.17.1

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[PATCH] drm/amdgpu: add cancel_delayed_work_sync before power gate

[James Zhu]

Add cancel_delayed_work_sync before set power gating state
to avoid race condition issue when power gating.

Signed-off-by: James Zhu 
---
 drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 19 +--
 1 file changed, 13 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c 
b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index 779e585..360dff2 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -388,6 +388,19 @@ static int vcn_v3_0_hw_fini(void *handle)
continue;
 
ring = >vcn.inst[i].ring_dec;
+   ring->sched.ready = false;
+
+   for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
+   ring = >vcn.inst[i].ring_enc[j];
+   ring->sched.ready = false;
+   }
+   }
+
+   cancel_delayed_work_sync(>vcn.idle_work);
+
+   for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+   if (adev->vcn.harvest_config & (1 << i))
+   continue;
 
if (!amdgpu_sriov_vf(adev)) {
if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
@@ -396,12 +409,6 @@ static int vcn_v3_0_hw_fini(void *handle)
vcn_v3_0_set_powergating_state(adev, 
AMD_PG_STATE_GATE);
}
}
-   ring->sched.ready = false;
-
-   for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
-   ring = >vcn.inst[i].ring_enc[j];
-   ring->sched.ready = false;
-   }
}
 
return 0;
-- 
2.7.4

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Re: [PATCH] drm/amdgpu: Expose rfc4122 compliant UUID

[Nieto, David M]

[AMD Official Use Only]

It is for unique identification of the GPU in system management applications, 
the 64 bit asic number is only available in Vega10 and later and not compliant 
with RFC4122.

David

From: Christian König 
Sent: Sunday, May 16, 2021 11:52 PM
To: Gu, JiaWei (Will) ; amd-gfx@lists.freedesktop.org 

Cc: Deng, Emily ; Nieto, David M 
Subject: Re: [PATCH] drm/amdgpu: Expose rfc4122 compliant UUID

Am 17.05.21 um 07:54 schrieb Jiawei Gu:
> Introduce an RFC 4122 compliant UUID for the GPUs derived
> from the unique GPU serial number (from Vega10) on gpus.
> Where this serial number is not available, use a compliant
> random UUID.
>
> For virtualization, the unique ID is passed by the host driver
> in the PF2VF structure.

The question is why this is useful.

>
> Signed-off-by: Jiawei Gu 
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu.h | 36 
>   drivers/gpu/drm/amd/amdgpu/amdgpu_device.c  | 96 +
>   drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c|  4 +
>   drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h |  4 +-
>   drivers/gpu/drm/amd/amdgpu/nv.c |  5 ++
>   drivers/gpu/drm/amd/amdgpu/nv.h |  3 +
>   6 files changed, 146 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 3147c1c935c8..ad6d4b55be6c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -802,6 +802,40 @@ struct amd_powerplay {
>  (rid == 0x01) || \
>  (rid == 0x10
>
> +union amdgpu_uuid_info {
> + struct {
> + union {
> + struct {
> + uint32_t did: 16;
> + uint32_t fcn: 8;
> + uint32_t asic_7 : 8;
> + };

Bitfields are not allowed in structures used for communication with
hardware or uAPI.

Regards,
Christian.

> + uint32_t time_low;
> + };
> +
> + struct {
> + uint32_t time_mid  : 16;
> + uint32_t time_high : 12;
> + uint32_t version   : 4;
> + };
> +
> + struct {
> + struct {
> + uint8_t clk_seq_hi : 6;
> + uint8_t variant: 2;
> + };
> + union {
> + uint8_t clk_seq_low;
> + uint8_t asic_6;
> + };
> + uint16_t asic_4;
> + };
> +
> + uint32_t asic_0;
> + };
> + char as_char[16];
> +};
> +
>   #define AMDGPU_RESET_MAGIC_NUM 64
>   #define AMDGPU_MAX_DF_PERFMONS 4
>   struct amdgpu_device {
> @@ -1074,6 +1108,8 @@ struct amdgpu_device {
>charproduct_name[32];
>charserial[20];
>
> + union amdgpu_uuid_info uuid_info;
> +
>struct amdgpu_autodump  autodump;
>
>atomic_tthrottling_logging_enabled;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 7c6c435e5d02..079841e1cb52 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -37,6 +37,7 @@
>   #include 
>   #include 
>   #include 
> +#include 
>   #include "amdgpu.h"
>   #include "amdgpu_trace.h"
>   #include "amdgpu_i2c.h"
> @@ -3239,11 +3240,104 @@ static int 
> amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev)
>return ret;
>   }
>
> +static bool amdgpu_is_uuid_info_empty(union amdgpu_uuid_info *uuid_info)
> +{
> + return (uuid_info->time_low== 0 &&
> + uuid_info->time_mid== 0 &&
> + uuid_info->time_high   == 0 &&
> + uuid_info->version == 0 &&
> + uuid_info->clk_seq_hi  == 0 &&
> + uuid_info->variant == 0 &&
> + uuid_info->clk_seq_low == 0 &&
> + uuid_info->asic_4  == 0 &&
> + uuid_info->asic_0  == 0);
> +}
> +
> +static void amdgpu_gen_uuid_info(union amdgpu_uuid_info *uuid_info,
> + uint64_t serial, uint16_t did, uint8_t idx)
> +{
> + uint16_t clk_seq = 0;
> +
> + /* Step1: insert clk_seq */
> + uuid_info->clk_seq_low = (uint8_t)clk_seq;
> + uuid_info->clk_seq_hi  = (uint8_t)(clk_seq >> 8) & 0x3F;
> +
> + /* Step2: insert did */
> + uuid_info->did = did;
> +
> + /* Step3: insert vf idx */
> + uuid_info->fcn = idx;
> +
> + /* Step4: insert serial */
> + uuid_info->asic_0 = (uint32_t)serial;
> + uuid_info->asic_4 = (uint16_t)(serial >> 4 * 8) & 0x;
> + 

Re: [PATCH 1/2] drm/amdgpu: enhance amdgpu_vcn_suspend

[James Zhu]

On 2021-05-17 3:43 p.m., Christian König wrote:

Am 17.05.21 um 16:57 schrieb James Zhu:

During vcn suspends, stop ring continue to receive new requests,
and try to wait for all vcn jobs to finish gracefully.

Signed-off-by: James Zhu 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 20 +++-
  1 file changed, 19 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c

index 2016459..7e9f5cb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -275,9 +275,27 @@ int amdgpu_vcn_suspend(struct amdgpu_device *adev)
  {
  unsigned size;
  void *ptr;
+    int retry_max = 6;
  int i;
  -    cancel_delayed_work_sync(>vcn.idle_work);
+    for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+    if (adev->vcn.harvest_config & (1 << i))
+    continue;
+    ring = >vcn.inst[i].ring_dec;
+    ring->sched.ready = false;
+
+    for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
+    ring = >vcn.inst[i].ring_enc[j];
+    ring->sched.ready = false;
+    }
+    }
+
+    while (retry_max--) {
+    if (cancel_delayed_work_sync(>vcn.idle_work)) {
+    dev_warn(adev->dev, "Waiting for left VCN job(s) to 
finish gracefully ...");

+    mdelay(5);
+    }
+    }


Ok that just makes no sense at all.

A cancel_delayed_work_sync() call is final, you never need to call it 
more than once.



yeah, I am preparing a new patch. Thanks! James

Christian.


    for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
  if (adev->vcn.harvest_config & (1 << i))



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Re: [PATCH 2/2] drm/amdgpu/pm: add new fields for Navi1x

[Nieto, David M]

[AMD Public Use]

I dont think the pp_nodes expose the vclk dclk nodes, but it might be better to 
rework this patch to expose those instead, and just add the voltages...

From: Lazar, Lijo 
Sent: Sunday, May 16, 2021 11:28 PM
To: Nieto, David M ; amd-gfx@lists.freedesktop.org 

Cc: Nieto, David M 
Subject: RE: [PATCH 2/2] drm/amdgpu/pm: add new fields for Navi1x

[AMD Public Use]

Metrics table carries dynamic state information of the ASIC. There are other 
pp_* nodes which carry static information about min/max and levels supported 
and that is a one-time query. Why there is a need to put everything in metrics 
data?

Thanks,
Lijo

-Original Message-
From: amd-gfx  On Behalf Of David M Nieto
Sent: Saturday, May 15, 2021 2:32 AM
To: amd-gfx@lists.freedesktop.org
Cc: Nieto, David M 
Subject: [PATCH 2/2] drm/amdgpu/pm: add new fields for Navi1x

Fill voltage and frequency ranges fields

Signed-off-by: David M Nieto 
Change-Id: I07f926dea46e80a96e1c972ba9dbc804b812d503
---
 .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c   | 434 +-
 1 file changed, 417 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index ac13042672ea..a412fa9a95ec 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -505,7 +505,7 @@ static int navi10_tables_init(struct smu_context *smu)
 goto err0_out;
 smu_table->metrics_time = 0;

-   smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_1);
+   smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
 smu_table->gpu_metrics_table = 
kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
 if (!smu_table->gpu_metrics_table)
 goto err1_out;
@@ -2627,10 +2627,11 @@ static ssize_t navi10_get_legacy_gpu_metrics(struct 
smu_context *smu,
  void **table)
 {
 struct smu_table_context *smu_table = >smu_table;
-   struct gpu_metrics_v1_1 *gpu_metrics =
-   (struct gpu_metrics_v1_1 *)smu_table->gpu_metrics_table;
+   struct gpu_metrics_v1_3 *gpu_metrics =
+   (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
 SmuMetrics_legacy_t metrics;
 int ret = 0;
+   int freq = 0, dpm = 0;

 mutex_lock(>metrics_lock);

@@ -2646,7 +2647,7 @@ static ssize_t navi10_get_legacy_gpu_metrics(struct 
smu_context *smu,

 mutex_unlock(>metrics_lock);

-   smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 1);
+   smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);

 gpu_metrics->temperature_edge = metrics.TemperatureEdge;
 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; @@ 
-2681,19 +2682,119 @@ static ssize_t navi10_get_legacy_gpu_metrics(struct 
smu_context *smu,

 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();

+   gpu_metrics->voltage_gfx = (155000 - 625 * 
metrics.CurrGfxVoltageOffset) / 100;
+   gpu_metrics->voltage_mem = (155000 - 625 * metrics.CurrMemVidOffset) / 
100;
+   gpu_metrics->voltage_soc = (155000 - 625 *
+metrics.CurrSocVoltageOffset) / 100;
+
+   gpu_metrics->max_socket_power = smu->power_limit;
+
+   /* Frequency and DPM ranges */
+
+   ret = smu_v11_0_get_dpm_freq_by_index(smu, SMU_GFXCLK, 0, );
+   if (ret)
+   goto out;
+   gpu_metrics->min_gfxclk_frequency = freq;
+
+   ret = smu_v11_0_get_dpm_freq_by_index(smu, SMU_SOCCLK, 0, );
+   if (ret)
+   goto out;
+   gpu_metrics->min_socclk_frequency = freq;
+
+   ret = smu_v11_0_get_dpm_freq_by_index(smu, SMU_UCLK, 0, );
+   if (ret)
+   goto out;
+   gpu_metrics->min_uclk_frequency = freq;
+
+   ret = smu_v11_0_get_dpm_freq_by_index(smu, SMU_VCLK, 0, );
+   if (ret)
+   goto out;
+   gpu_metrics->min_vclk0_frequency = freq;
+
+   ret = smu_v11_0_get_dpm_freq_by_index(smu, SMU_DCLK, 0, );
+   if (ret)
+   goto out;
+   gpu_metrics->min_dclk0_frequency = freq;
+
+   ret = smu_v11_0_get_dpm_level_count(smu, SMU_GFXCLK, );
+   if (ret)
+   goto out;
+   gpu_metrics->max_gfxclk_dpm = dpm;
+
+   ret = smu_v11_0_get_dpm_freq_by_index(smu, SMU_GFXCLK,
+   gpu_metrics->max_gfxclk_dpm - 1, );
+   if (ret)
+   goto out;
+
+   gpu_metrics->max_gfxclk_frequency = freq;
+
+   ret = smu_v11_0_get_dpm_level_count(smu, SMU_SOCCLK, );
+   if (ret)
+   goto out;
+
+   gpu_metrics->max_socclk_dpm = dpm;
+
+   ret = smu_v11_0_get_dpm_freq_by_index(smu, SMU_SOCCLK,
+   gpu_metrics->max_socclk_dpm - 1, );
+   if (ret)
+   goto out;
+
+   gpu_metrics->max_socclk_frequency = freq;
+
+   ret = smu_v11_0_get_dpm_level_count(smu, 

Re: [PATCH v7 12/16] drm/amdgpu: Fix hang on device removal.

[Christian König]

Ok, then putting that on my TODO list for tomorrow.

I've already found a problem with how we finish of fences, going to 
write more on this tomorrow.


Christian.

Am 17.05.21 um 21:46 schrieb Andrey Grodzovsky:

Yep, you can take a look.

Andrey

On 2021-05-17 3:39 p.m., Christian König wrote:

You need to note who you are pinging here.

I'm still assuming you wait for feedback from Daniel. Or should I 
take a look?


Christian.

Am 17.05.21 um 16:40 schrieb Andrey Grodzovsky:

Ping

Andrey

On 2021-05-14 10:42 a.m., Andrey Grodzovsky wrote:

Ping

Andrey

On 2021-05-12 10:26 a.m., Andrey Grodzovsky wrote:

If removing while commands in flight you cannot wait to flush the
HW fences on a ring since the device is gone.

Signed-off-by: Andrey Grodzovsky 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 16 ++--
  1 file changed, 10 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c

index 1ffb36bd0b19..fa03702ecbfb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
@@ -36,6 +36,7 @@
  #include 
  #include 
+#include 
  #include "amdgpu.h"
  #include "amdgpu_trace.h"
@@ -525,8 +526,7 @@ int amdgpu_fence_driver_init(struct 
amdgpu_device *adev)

   */
  void amdgpu_fence_driver_fini_hw(struct amdgpu_device *adev)
  {
-    unsigned i, j;
-    int r;
+    int i, r;
  for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
  struct amdgpu_ring *ring = adev->rings[i];
@@ -535,11 +535,15 @@ void amdgpu_fence_driver_fini_hw(struct 
amdgpu_device *adev)

  continue;
  if (!ring->no_scheduler)
  drm_sched_fini(>sched);
-    r = amdgpu_fence_wait_empty(ring);
-    if (r) {
-    /* no need to trigger GPU reset as we are unloading */
+    /* You can't wait for HW to signal if it's gone */
+    if (!drm_dev_is_unplugged(>ddev))
+    r = amdgpu_fence_wait_empty(ring);
+    else
+    r = -ENODEV;
+    /* no need to trigger GPU reset as we are unloading */
+    if (r)
  amdgpu_fence_driver_force_completion(ring);
-    }
+
  if (ring->fence_drv.irq_src)
  amdgpu_irq_put(adev, ring->fence_drv.irq_src,
 ring->fence_drv.irq_type);





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Re: [PATCH v7 12/16] drm/amdgpu: Fix hang on device removal.

[Andrey Grodzovsky]

Yep, you can take a look.

Andrey

On 2021-05-17 3:39 p.m., Christian König wrote:

You need to note who you are pinging here.

I'm still assuming you wait for feedback from Daniel. Or should I take a 
look?


Christian.

Am 17.05.21 um 16:40 schrieb Andrey Grodzovsky:

Ping

Andrey

On 2021-05-14 10:42 a.m., Andrey Grodzovsky wrote:

Ping

Andrey

On 2021-05-12 10:26 a.m., Andrey Grodzovsky wrote:

If removing while commands in flight you cannot wait to flush the
HW fences on a ring since the device is gone.

Signed-off-by: Andrey Grodzovsky 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 16 ++--
  1 file changed, 10 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c

index 1ffb36bd0b19..fa03702ecbfb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
@@ -36,6 +36,7 @@
  #include 
  #include 
+#include 
  #include "amdgpu.h"
  #include "amdgpu_trace.h"
@@ -525,8 +526,7 @@ int amdgpu_fence_driver_init(struct 
amdgpu_device *adev)

   */
  void amdgpu_fence_driver_fini_hw(struct amdgpu_device *adev)
  {
-    unsigned i, j;
-    int r;
+    int i, r;
  for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
  struct amdgpu_ring *ring = adev->rings[i];
@@ -535,11 +535,15 @@ void amdgpu_fence_driver_fini_hw(struct 
amdgpu_device *adev)

  continue;
  if (!ring->no_scheduler)
  drm_sched_fini(>sched);
-    r = amdgpu_fence_wait_empty(ring);
-    if (r) {
-    /* no need to trigger GPU reset as we are unloading */
+    /* You can't wait for HW to signal if it's gone */
+    if (!drm_dev_is_unplugged(>ddev))
+    r = amdgpu_fence_wait_empty(ring);
+    else
+    r = -ENODEV;
+    /* no need to trigger GPU reset as we are unloading */
+    if (r)
  amdgpu_fence_driver_force_completion(ring);
-    }
+
  if (ring->fence_drv.irq_src)
  amdgpu_irq_put(adev, ring->fence_drv.irq_src,
 ring->fence_drv.irq_type);




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Re: [PATCH 1/2] drm/amdgpu: enhance amdgpu_vcn_suspend

[Christian König]

Am 17.05.21 um 16:57 schrieb James Zhu:

During vcn suspends, stop ring continue to receive new requests,
and try to wait for all vcn jobs to finish gracefully.

Signed-off-by: James Zhu 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 20 +++-
  1 file changed, 19 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 2016459..7e9f5cb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -275,9 +275,27 @@ int amdgpu_vcn_suspend(struct amdgpu_device *adev)
  {
unsigned size;
void *ptr;
+   int retry_max = 6;
int i;
  
-	cancel_delayed_work_sync(>vcn.idle_work);

+   for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+   if (adev->vcn.harvest_config & (1 << i))
+   continue;
+   ring = >vcn.inst[i].ring_dec;
+   ring->sched.ready = false;
+
+   for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
+   ring = >vcn.inst[i].ring_enc[j];
+   ring->sched.ready = false;
+   }
+   }
+
+   while (retry_max--) {
+   if (cancel_delayed_work_sync(>vcn.idle_work)) {
+   dev_warn(adev->dev, "Waiting for left VCN job(s) to finish 
gracefully ...");
+   mdelay(5);
+   }
+   }


Ok that just makes no sense at all.

A cancel_delayed_work_sync() call is final, you never need to call it 
more than once.


Christian.

  
  	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {

if (adev->vcn.harvest_config & (1 << i))


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Re: [PATCH v7 12/16] drm/amdgpu: Fix hang on device removal.

[Christian König]

You need to note who you are pinging here.

I'm still assuming you wait for feedback from Daniel. Or should I take a 
look?


Christian.

Am 17.05.21 um 16:40 schrieb Andrey Grodzovsky:

Ping

Andrey

On 2021-05-14 10:42 a.m., Andrey Grodzovsky wrote:

Ping

Andrey

On 2021-05-12 10:26 a.m., Andrey Grodzovsky wrote:

If removing while commands in flight you cannot wait to flush the
HW fences on a ring since the device is gone.

Signed-off-by: Andrey Grodzovsky 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 16 ++--
  1 file changed, 10 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c

index 1ffb36bd0b19..fa03702ecbfb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
@@ -36,6 +36,7 @@
  #include 
  #include 
+#include 
  #include "amdgpu.h"
  #include "amdgpu_trace.h"
@@ -525,8 +526,7 @@ int amdgpu_fence_driver_init(struct 
amdgpu_device *adev)

   */
  void amdgpu_fence_driver_fini_hw(struct amdgpu_device *adev)
  {
-    unsigned i, j;
-    int r;
+    int i, r;
  for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
  struct amdgpu_ring *ring = adev->rings[i];
@@ -535,11 +535,15 @@ void amdgpu_fence_driver_fini_hw(struct 
amdgpu_device *adev)

  continue;
  if (!ring->no_scheduler)
  drm_sched_fini(>sched);
-    r = amdgpu_fence_wait_empty(ring);
-    if (r) {
-    /* no need to trigger GPU reset as we are unloading */
+    /* You can't wait for HW to signal if it's gone */
+    if (!drm_dev_is_unplugged(>ddev))
+    r = amdgpu_fence_wait_empty(ring);
+    else
+    r = -ENODEV;
+    /* no need to trigger GPU reset as we are unloading */
+    if (r)
  amdgpu_fence_driver_force_completion(ring);
-    }
+
  if (ring->fence_drv.irq_src)
  amdgpu_irq_put(adev, ring->fence_drv.irq_src,
 ring->fence_drv.irq_type);



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Re: [RFC PATCH 0/3] A drm_plane API to support HDR planes

[Vitaly Prosyak]

On 2021-05-17 12:48 p.m., Sebastian Wick wrote:

On 2021-05-17 10:57, Pekka Paalanen wrote:

On Fri, 14 May 2021 17:05:11 -0400
Harry Wentland  wrote:


On 2021-04-27 10:50 a.m., Pekka Paalanen wrote:
> On Mon, 26 Apr 2021 13:38:49 -0400
> Harry Wentland  wrote:


...


>> ## Mastering Luminances
>>
>> Now we are able to use the PQ 2084 EOTF to define the luminance of
>> pixels in absolute terms. Unfortunately we're again presented with
>> physical limitations of the display technologies on the market 
today.

>> Here are a few examples of luminance ranges of displays.
>>
>> | Display  | Luminance range in nits |
>> |  | --- |
>> | Typical PC display   | 0.3 - 200 |
>> | Excellent LCD HDTV   | 0.3 - 400 |
>> | HDR LCD w/ local dimming | 0.05 - 1,500 |
>>
>> Since no display can currently show the full 0.0005 to 10,000 nits
>> luminance range the display will need to tonemap the HDR content, 
i.e

>> to fit the content within a display's capabilities. To assist with
>> tonemapping HDR content is usually accompanied with a metadata that
>> describes (among other things) the minimum and maximum mastering
>> luminance, i.e. the maximum and minimum luminance of the display 
that

>> was used to master the HDR content.
>>
>> The HDR metadata is currently defined on the drm_connector via the
>> hdr_output_metadata blob property.
>>
>> It might be useful to define per-plane hdr metadata, as different
>> planes might have been mastered differently.
>
> I don't think this would directly help with the dynamic range 
blending

> problem. You still need to establish the mapping between the optical
> values from two different EOTFs and dynamic ranges. Or can you know
> which optical values match the mastering display maximum and minimum
> luminances for not-PQ?
>

My understanding of this is probably best illustrated by this example:

Assume HDR was mastered on a display with a maximum white level of 500
nits and played back on a display that supports a max white level of 
400
nits. If you know the mastering white level of 500 you know that 
this is
the maximum value you need to compress down to 400 nits, allowing 
you to

use the full extent of the 400 nits panel.


Right, but in the kernel, where do you get these nits values from?

hdr_output_metadata blob is infoframe data to the monitor. I think this
should be independent of the metadata used for color transformations in
the display pipeline before the monitor.

EDID may tell us the monitor HDR metadata, but again what is used in
the color transformations should be independent, because EDIDs lie,
lighting environments change, and users have different preferences.

What about black levels?

Do you want to do black level adjustment?

How exactly should the compression work?

Where do you map the mid-tones?

What if the end user wants something different?


I suspect that this is not about tone mapping at all. The use cases
listed always have the display in PQ mode and just assume that no
content exceeds the PQ limitations. Then you can simply bring all
content to the color space with a matrix multiplication and then map the
linear light content somewhere into the PQ range. Tone mapping is
performed in the display only.

From a generic wayland compositor point of view this is uninteresting.

It a compositor's decision to provide or not the metadata property to 
the kernel. The metadata can be available from one or multiple clients 
or most likely not available at all.


Compositors may put a display in HDR10 ( when PQ 2084 INV EOTF and TM 
occurs in display ) or NATIVE mode and do not attach any metadata to the 
connector and do TM in compositor.


It is all about user preference or compositor design, or a combination 
of both options.




I completely agree with what you said below though. I would even argue
that all generic KMS abstract pipeline elements must have a well defined
place in the pipeline and follow an exact specified formula.




If you do not know the mastering luminance is 500 nits you would
have to compress 10,000 nits down to 400 (assuming PQ), losing quite
a bit of the full 400 nits available as you'll need room to map the 500
to 10,000 nits range which in reality is completely unused. You 
might end

up with mapping 500 nits to 350 nits, instead of mapping it to 400.


The quality of the result depends on the compression (tone-mapping)
algorithm. I believe no-one will ever do a simple linear compression of
ranges.

Instead, you probably do something smooth in the black end, keep
mid-tones roughly as they are, and the again do a smooth saturation to
some "reasonable" level that goes well with the monitor in the current
lighting environment without introducing coloring artifacts, and just
clip the huge overshoot of the full PQ-range.

There are many big and small decisions to be made in how to map
out-of-gamut or out-of-brightness values into the displayable range,
and no 

[PATCH] drm/amdgpu: Unmap all MMIO mappings

[Andrey Grodzovsky]

Access to those must be prevented post pci_remove

v6: Drop BOs list, unampping VRAM BAR is enough.
v8:
Add condition of xgmi.connected_to_cpu to MTTR
handling and remove MTTR handling from the old place.

Signed-off-by: Andrey Grodzovsky 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 26 +++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c |  4 
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c|  4 
 3 files changed, 23 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index f7cca25c0fa0..8b50315d1fe1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3666,6 +3666,27 @@ int amdgpu_device_init(struct amdgpu_device *adev,
return r;
 }
 
+static void amdgpu_device_unmap_mmio(struct amdgpu_device *adev)
+{
+   /* Clear all CPU mappings pointing to this device */
+   unmap_mapping_range(adev->ddev.anon_inode->i_mapping, 0, 0, 1);
+
+   /* Unmap all mapped bars - Doorbell, registers and VRAM */
+   amdgpu_device_doorbell_fini(adev);
+
+   iounmap(adev->rmmio);
+   adev->rmmio = NULL;
+   if (adev->mman.aper_base_kaddr)
+   iounmap(adev->mman.aper_base_kaddr);
+   adev->mman.aper_base_kaddr = NULL;
+
+   /* Memory manager related */
+   if (!adev->gmc.xgmi.connected_to_cpu) {
+   arch_phys_wc_del(adev->gmc.vram_mtrr);
+   arch_io_free_memtype_wc(adev->gmc.aper_base, 
adev->gmc.aper_size);
+   }
+}
+
 /**
  * amdgpu_device_fini - tear down the driver
  *
@@ -3712,6 +3733,8 @@ void amdgpu_device_fini_hw(struct amdgpu_device *adev)
amdgpu_device_ip_fini_early(adev);
 
amdgpu_gart_dummy_page_fini(adev);
+
+   amdgpu_device_unmap_mmio(adev);
 }
 
 void amdgpu_device_fini_sw(struct amdgpu_device *adev)
@@ -3739,9 +3762,6 @@ void amdgpu_device_fini_sw(struct amdgpu_device *adev)
}
if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
vga_client_register(adev->pdev, NULL, NULL, NULL);
-   iounmap(adev->rmmio);
-   adev->rmmio = NULL;
-   amdgpu_device_doorbell_fini(adev);
 
if (IS_ENABLED(CONFIG_PERF_EVENTS))
amdgpu_pmu_fini(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 0adffcace326..8eabe3c9ad17 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -1107,10 +1107,6 @@ int amdgpu_bo_init(struct amdgpu_device *adev)
 void amdgpu_bo_fini(struct amdgpu_device *adev)
 {
amdgpu_ttm_fini(adev);
-   if (!adev->gmc.xgmi.connected_to_cpu) {
-   arch_phys_wc_del(adev->gmc.vram_mtrr);
-   arch_io_free_memtype_wc(adev->gmc.aper_base, 
adev->gmc.aper_size);
-   }
 }
 
 /**
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 0d54e70278ca..58ad2fecc9e3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1841,10 +1841,6 @@ void amdgpu_ttm_fini(struct amdgpu_device *adev)
amdgpu_bo_free_kernel(>mman.discovery_memory, NULL, NULL);
amdgpu_ttm_fw_reserve_vram_fini(adev);
 
-   if (adev->mman.aper_base_kaddr)
-   iounmap(adev->mman.aper_base_kaddr);
-   adev->mman.aper_base_kaddr = NULL;
-
amdgpu_vram_mgr_fini(adev);
amdgpu_gtt_mgr_fini(adev);
ttm_range_man_fini(>mman.bdev, AMDGPU_PL_GDS);
-- 
2.25.1

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Re: [PATCH v7 16/16] drm/amdgpu: Unmap all MMIO mappings

[Andrey Grodzovsky]

On 2021-05-17 2:56 p.m., Alex Deucher wrote:

On Mon, May 17, 2021 at 2:46 PM Andrey Grodzovsky
 wrote:




On 2021-05-17 1:43 p.m., Alex Deucher wrote:

On Wed, May 12, 2021 at 10:27 AM Andrey Grodzovsky
 wrote:


Access to those must be prevented post pci_remove

v6: Drop BOs list, unampping VRAM BAR is enough.

Signed-off-by: Andrey Grodzovsky 
---
   drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 24 +++---
   drivers/gpu/drm/amd/amdgpu/amdgpu_object.c |  1 +
   drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c|  4 
   3 files changed, 22 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index f7cca25c0fa0..73cbc3c7453f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3666,6 +3666,25 @@ int amdgpu_device_init(struct amdgpu_device *adev,
  return r;
   }

+static void amdgpu_device_unmap_mmio(struct amdgpu_device *adev)
+{
+   /* Clear all CPU mappings pointing to this device */
+   unmap_mapping_range(adev->ddev.anon_inode->i_mapping, 0, 0, 1);
+
+   /* Unmap all mapped bars - Doorbell, registers and VRAM */
+   amdgpu_device_doorbell_fini(adev);
+
+   iounmap(adev->rmmio);
+   adev->rmmio = NULL;
+   if (adev->mman.aper_base_kaddr)
+   iounmap(adev->mman.aper_base_kaddr);
+   adev->mman.aper_base_kaddr = NULL;
+
+   /* Memory manager related */


I think we need:
if (!adev->gmc.xgmi.connected_to_cpu) {
around these two to mirror amdgpu_bo_fini().

Alex


I am working of off drm-misc-next and here amdgpu_xgmi
doesn't have connected_to_cpu yet.


Ah, right.  Ok.  Do we need to remove the code from bo_fini() if we
handle it here now?

Alex


My bad, I was on older kernel due to fixing internal
ticket last week, in latest drm-misc-next there is
connected_to_cpu and so I fixed everything as you asked.
Will resend in a moment.

Andrey






Andrey




+   arch_phys_wc_del(adev->gmc.vram_mtrr);
+   arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size);
+}
+
   /**
* amdgpu_device_fini - tear down the driver
*
@@ -3712,6 +3731,8 @@ void amdgpu_device_fini_hw(struct amdgpu_device *adev)
  amdgpu_device_ip_fini_early(adev);

  amdgpu_gart_dummy_page_fini(adev);
+
+   amdgpu_device_unmap_mmio(adev);
   }

   void amdgpu_device_fini_sw(struct amdgpu_device *adev)
@@ -3739,9 +3760,6 @@ void amdgpu_device_fini_sw(struct amdgpu_device *adev)
  }
  if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
  vga_client_register(adev->pdev, NULL, NULL, NULL);
-   iounmap(adev->rmmio);
-   adev->rmmio = NULL;
-   amdgpu_device_doorbell_fini(adev);

  if (IS_ENABLED(CONFIG_PERF_EVENTS))
  amdgpu_pmu_fini(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 0adffcace326..882fb49f3c41 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -533,6 +533,7 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev,
  return -ENOMEM;
  drm_gem_private_object_init(adev_to_drm(adev), >tbo.base, size);
  INIT_LIST_HEAD(>shadow_list);
+
  bo->vm_bo = NULL;
  bo->preferred_domains = bp->preferred_domain ? bp->preferred_domain :
  bp->domain;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 0d54e70278ca..58ad2fecc9e3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1841,10 +1841,6 @@ void amdgpu_ttm_fini(struct amdgpu_device *adev)
  amdgpu_bo_free_kernel(>mman.discovery_memory, NULL, NULL);
  amdgpu_ttm_fw_reserve_vram_fini(adev);

-   if (adev->mman.aper_base_kaddr)
-   iounmap(adev->mman.aper_base_kaddr);
-   adev->mman.aper_base_kaddr = NULL;
-
  amdgpu_vram_mgr_fini(adev);
  amdgpu_gtt_mgr_fini(adev);
  ttm_range_man_fini(>mman.bdev, AMDGPU_PL_GDS);
--
2.25.1


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[PATCH 2/2] drm/amdgpu/display/dc: drop un used variables

[Alex Deucher]

Unused so remove them.

Fixes: 5791d219561cb6 ("drm/amd/display: Refactor and add visual confirm for HW 
Flip Queue")
Signed-off-by: Alex Deucher 
Cc: Wyatt Wood 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 1 -
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c| 1 -
 2 files changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 85a947015945..81803463ca9b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2521,7 +2521,6 @@ void dcn10_update_visual_confirm_color(struct dc *dc, 
struct pipe_ctx *pipe_ctx,
 
 void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
 {
-   struct dce_hwseq *hws = dc->hwseq;
struct hubp *hubp = pipe_ctx->plane_res.hubp;
struct mpcc_blnd_cfg blnd_cfg = {{0}};
bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha && 
pipe_ctx->bottom_pipe;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 558821e5ed2f..25de15158801 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -2286,7 +2286,6 @@ void dcn20_update_visual_confirm_color(struct dc *dc, 
struct pipe_ctx *pipe_ctx,
 
 void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
 {
-   struct dce_hwseq *hws = dc->hwseq;
struct hubp *hubp = pipe_ctx->plane_res.hubp;
struct mpcc_blnd_cfg blnd_cfg = { {0} };
bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha;
-- 
2.31.1

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[PATCH 1/2] drm/amdgpu/display: revert random whitespace changes

[Alex Deucher]

Commit 458ef68e972878 ("drm/amd/display: Add get_current_time interface to 
dmub_srv")
introduced a bunch of random whitespace changes which lead
to compiler warnings.  Revert those changes to fix the warning
and keep the code readable.  No intended functional change.

Fixes: 458ef68e972878 ("drm/amd/display: Add get_current_time interface to 
dmub_srv")
Signed-off-by: Alex Deucher 
Cc: Wyatt Wood 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c  | 36 +--
 .../gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c |  8 ++---
 drivers/gpu/drm/amd/display/dc/dm_services.h  |  1 +
 3 files changed, 23 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index b4aa20250301..ef157b83bacd 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2636,14 +2636,14 @@ static void commit_planes_for_stream(struct dc *dc,

top_pipe_to_program->stream_res.tg);
}
 
-   if ((update_type != UPDATE_TYPE_FAST) && 
dc->hwss.interdependent_update_lock)
-   dc->hwss.interdependent_update_lock(dc, context, true);
-   else
-   /* Lock the top pipe while updating plane addrs, since 
freesync requires
-*  plane addr update event triggers to be synchronized.
-*  top_pipe_to_program is expected to never be NULL
-*/
-   dc->hwss.pipe_control_lock(dc, top_pipe_to_program, 
true);
+   if ((update_type != UPDATE_TYPE_FAST) && 
dc->hwss.interdependent_update_lock)
+   dc->hwss.interdependent_update_lock(dc, context, true);
+   else
+   /* Lock the top pipe while updating plane addrs, since freesync 
requires
+*  plane addr update event triggers to be synchronized.
+*  top_pipe_to_program is expected to never be NULL
+*/
+   dc->hwss.pipe_control_lock(dc, top_pipe_to_program, true);
 
// Stream updates
if (stream_update)
@@ -2659,10 +2659,10 @@ static void commit_planes_for_stream(struct dc *dc,
if (dc->hwss.program_front_end_for_ctx)
dc->hwss.program_front_end_for_ctx(dc, context);
 
-   if ((update_type != UPDATE_TYPE_FAST) && 
dc->hwss.interdependent_update_lock)
-   dc->hwss.interdependent_update_lock(dc, 
context, false);
-   else
-   dc->hwss.pipe_control_lock(dc, 
top_pipe_to_program, false);
+   if ((update_type != UPDATE_TYPE_FAST) && 
dc->hwss.interdependent_update_lock)
+   dc->hwss.interdependent_update_lock(dc, context, false);
+   else
+   dc->hwss.pipe_control_lock(dc, top_pipe_to_program, 
false);
dc->hwss.post_unlock_program_front_end(dc, context);
return;
}
@@ -2789,10 +2789,10 @@ static void commit_planes_for_stream(struct dc *dc,
 
}
 
-   if ((update_type != UPDATE_TYPE_FAST) && 
dc->hwss.interdependent_update_lock)
-   dc->hwss.interdependent_update_lock(dc, context, false);
-   else
-   dc->hwss.pipe_control_lock(dc, top_pipe_to_program, 
false);
+   if ((update_type != UPDATE_TYPE_FAST) && 
dc->hwss.interdependent_update_lock)
+   dc->hwss.interdependent_update_lock(dc, context, false);
+   else
+   dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
 
if ((update_type != UPDATE_TYPE_FAST) && 
stream->update_flags.bits.dsc_changed)
if 
(top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) {
@@ -2838,8 +2838,8 @@ static void commit_planes_for_stream(struct dc *dc,
pipe_ctx->plane_state->skip_manual_trigger)
continue;
 
-   if 
(pipe_ctx->stream_res.tg->funcs->program_manual_trigger)
-   
pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg);
+   if (pipe_ctx->stream_res.tg->funcs->program_manual_trigger)
+   
pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg);
}
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c 
b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
index e7c56df8f762..b0c9180b808f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
@@ -795,10 +795,10 @@ bool hubp21_program_surface_flip_and_addr(
flip_regs.tmz_surface = address->tmz_surface;
flip_regs.immediate = flip_immediate;
 
-   if (hubp->ctx->dc->debug.enable_dmcub_surface_flip && 
address->type == 

Re: [PATCH v7 16/16] drm/amdgpu: Unmap all MMIO mappings

[Alex Deucher]

On Mon, May 17, 2021 at 2:46 PM Andrey Grodzovsky
 wrote:
>
>
>
> On 2021-05-17 1:43 p.m., Alex Deucher wrote:
> > On Wed, May 12, 2021 at 10:27 AM Andrey Grodzovsky
> >  wrote:
> >>
> >> Access to those must be prevented post pci_remove
> >>
> >> v6: Drop BOs list, unampping VRAM BAR is enough.
> >>
> >> Signed-off-by: Andrey Grodzovsky 
> >> ---
> >>   drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 24 +++---
> >>   drivers/gpu/drm/amd/amdgpu/amdgpu_object.c |  1 +
> >>   drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c|  4 
> >>   3 files changed, 22 insertions(+), 7 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
> >> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> >> index f7cca25c0fa0..73cbc3c7453f 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> >> @@ -3666,6 +3666,25 @@ int amdgpu_device_init(struct amdgpu_device *adev,
> >>  return r;
> >>   }
> >>
> >> +static void amdgpu_device_unmap_mmio(struct amdgpu_device *adev)
> >> +{
> >> +   /* Clear all CPU mappings pointing to this device */
> >> +   unmap_mapping_range(adev->ddev.anon_inode->i_mapping, 0, 0, 1);
> >> +
> >> +   /* Unmap all mapped bars - Doorbell, registers and VRAM */
> >> +   amdgpu_device_doorbell_fini(adev);
> >> +
> >> +   iounmap(adev->rmmio);
> >> +   adev->rmmio = NULL;
> >> +   if (adev->mman.aper_base_kaddr)
> >> +   iounmap(adev->mman.aper_base_kaddr);
> >> +   adev->mman.aper_base_kaddr = NULL;
> >> +
> >> +   /* Memory manager related */
> >
> > I think we need:
> > if (!adev->gmc.xgmi.connected_to_cpu) {
> > around these two to mirror amdgpu_bo_fini().
> >
> > Alex
>
> I am working of off drm-misc-next and here amdgpu_xgmi
> doesn't have connected_to_cpu yet.

Ah, right.  Ok.  Do we need to remove the code from bo_fini() if we
handle it here now?

Alex


>
> Andrey
>
> >
> >> +   arch_phys_wc_del(adev->gmc.vram_mtrr);
> >> +   arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size);
> >> +}
> >> +
> >>   /**
> >>* amdgpu_device_fini - tear down the driver
> >>*
> >> @@ -3712,6 +3731,8 @@ void amdgpu_device_fini_hw(struct amdgpu_device 
> >> *adev)
> >>  amdgpu_device_ip_fini_early(adev);
> >>
> >>  amdgpu_gart_dummy_page_fini(adev);
> >> +
> >> +   amdgpu_device_unmap_mmio(adev);
> >>   }
> >>
> >>   void amdgpu_device_fini_sw(struct amdgpu_device *adev)
> >> @@ -3739,9 +3760,6 @@ void amdgpu_device_fini_sw(struct amdgpu_device 
> >> *adev)
> >>  }
> >>  if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
> >>  vga_client_register(adev->pdev, NULL, NULL, NULL);
> >> -   iounmap(adev->rmmio);
> >> -   adev->rmmio = NULL;
> >> -   amdgpu_device_doorbell_fini(adev);
> >>
> >>  if (IS_ENABLED(CONFIG_PERF_EVENTS))
> >>  amdgpu_pmu_fini(adev);
> >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
> >> b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> >> index 0adffcace326..882fb49f3c41 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> >> @@ -533,6 +533,7 @@ static int amdgpu_bo_do_create(struct amdgpu_device 
> >> *adev,
> >>  return -ENOMEM;
> >>  drm_gem_private_object_init(adev_to_drm(adev), >tbo.base, 
> >> size);
> >>  INIT_LIST_HEAD(>shadow_list);
> >> +
> >>  bo->vm_bo = NULL;
> >>  bo->preferred_domains = bp->preferred_domain ? 
> >> bp->preferred_domain :
> >>  bp->domain;
> >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
> >> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> >> index 0d54e70278ca..58ad2fecc9e3 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> >> @@ -1841,10 +1841,6 @@ void amdgpu_ttm_fini(struct amdgpu_device *adev)
> >>  amdgpu_bo_free_kernel(>mman.discovery_memory, NULL, NULL);
> >>  amdgpu_ttm_fw_reserve_vram_fini(adev);
> >>
> >> -   if (adev->mman.aper_base_kaddr)
> >> -   iounmap(adev->mman.aper_base_kaddr);
> >> -   adev->mman.aper_base_kaddr = NULL;
> >> -
> >>  amdgpu_vram_mgr_fini(adev);
> >>  amdgpu_gtt_mgr_fini(adev);
> >>  ttm_range_man_fini(>mman.bdev, AMDGPU_PL_GDS);
> >> --
> >> 2.25.1
> >>
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Re: [PATCH v7 16/16] drm/amdgpu: Unmap all MMIO mappings

[Andrey Grodzovsky]

On 2021-05-17 1:43 p.m., Alex Deucher wrote:

On Wed, May 12, 2021 at 10:27 AM Andrey Grodzovsky
 wrote:


Access to those must be prevented post pci_remove

v6: Drop BOs list, unampping VRAM BAR is enough.

Signed-off-by: Andrey Grodzovsky 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 24 +++---
  drivers/gpu/drm/amd/amdgpu/amdgpu_object.c |  1 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c|  4 
  3 files changed, 22 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index f7cca25c0fa0..73cbc3c7453f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3666,6 +3666,25 @@ int amdgpu_device_init(struct amdgpu_device *adev,
 return r;
  }

+static void amdgpu_device_unmap_mmio(struct amdgpu_device *adev)
+{
+   /* Clear all CPU mappings pointing to this device */
+   unmap_mapping_range(adev->ddev.anon_inode->i_mapping, 0, 0, 1);
+
+   /* Unmap all mapped bars - Doorbell, registers and VRAM */
+   amdgpu_device_doorbell_fini(adev);
+
+   iounmap(adev->rmmio);
+   adev->rmmio = NULL;
+   if (adev->mman.aper_base_kaddr)
+   iounmap(adev->mman.aper_base_kaddr);
+   adev->mman.aper_base_kaddr = NULL;
+
+   /* Memory manager related */


I think we need:
if (!adev->gmc.xgmi.connected_to_cpu) {
around these two to mirror amdgpu_bo_fini().

Alex


I am working of off drm-misc-next and here amdgpu_xgmi
doesn't have connected_to_cpu yet.

Andrey




+   arch_phys_wc_del(adev->gmc.vram_mtrr);
+   arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size);
+}
+
  /**
   * amdgpu_device_fini - tear down the driver
   *
@@ -3712,6 +3731,8 @@ void amdgpu_device_fini_hw(struct amdgpu_device *adev)
 amdgpu_device_ip_fini_early(adev);

 amdgpu_gart_dummy_page_fini(adev);
+
+   amdgpu_device_unmap_mmio(adev);
  }

  void amdgpu_device_fini_sw(struct amdgpu_device *adev)
@@ -3739,9 +3760,6 @@ void amdgpu_device_fini_sw(struct amdgpu_device *adev)
 }
 if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
 vga_client_register(adev->pdev, NULL, NULL, NULL);
-   iounmap(adev->rmmio);
-   adev->rmmio = NULL;
-   amdgpu_device_doorbell_fini(adev);

 if (IS_ENABLED(CONFIG_PERF_EVENTS))
 amdgpu_pmu_fini(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 0adffcace326..882fb49f3c41 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -533,6 +533,7 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev,
 return -ENOMEM;
 drm_gem_private_object_init(adev_to_drm(adev), >tbo.base, size);
 INIT_LIST_HEAD(>shadow_list);
+
 bo->vm_bo = NULL;
 bo->preferred_domains = bp->preferred_domain ? bp->preferred_domain :
 bp->domain;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 0d54e70278ca..58ad2fecc9e3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1841,10 +1841,6 @@ void amdgpu_ttm_fini(struct amdgpu_device *adev)
 amdgpu_bo_free_kernel(>mman.discovery_memory, NULL, NULL);
 amdgpu_ttm_fw_reserve_vram_fini(adev);

-   if (adev->mman.aper_base_kaddr)
-   iounmap(adev->mman.aper_base_kaddr);
-   adev->mman.aper_base_kaddr = NULL;
-
 amdgpu_vram_mgr_fini(adev);
 amdgpu_gtt_mgr_fini(adev);
 ttm_range_man_fini(>mman.bdev, AMDGPU_PL_GDS);
--
2.25.1


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Re: [PATCH v2 1/2] drm/amdgpu: enhance amdgpu_vcn_suspend

[Leo Liu]

To be accurate, the Bo is mapped to engine cache window, and the runtime 
of engine stacks, so we should save it before the poweroff.



On 2021-05-17 2:15 p.m., Leo Liu wrote:


The saved data are from the engine cache, it's the runtime of engine 
before suspend, it might be different after you have the engine 
powered off.



Regards,

Leo



On 2021-05-17 2:11 p.m., Zhu, James wrote:


[AMD Official Use Only - Internal Distribution Only]


save_bo needn't ungate vcn,  it just keeps data in memory.

Thanks & Best Regards!


James Zhu


*From:* Liu, Leo 
*Sent:* Monday, May 17, 2021 2:07 PM
*To:* Zhu, James ; Zhu, James ; 
amd-gfx@lists.freedesktop.org 

*Subject:* Re: [PATCH v2 1/2] drm/amdgpu: enhance amdgpu_vcn_suspend

Definitely, we need to move cancel_delayed_work_sync moved to before 
power gate.


Should "save_bo" be step 4 before power gate ?

Regards,

Leo


On 2021-05-17 1:59 p.m., James Zhu wrote:


Then we forgot the proposal I provided before.

I think the below seq may fixed the race condition issue that we are 
facing.


1. stop scheduling new jobs

    for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
        if (adev->vcn.harvest_config & (1 << i))
            continue;

        ring = >vcn.inst[i].ring_dec;
        ring->sched.ready = false;

        for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
            ring = >vcn.inst[i].ring_enc[j];
            ring->sched.ready = false;
        }
    }

2. cancel_delayed_work_sync(>vcn.idle_work);

3. SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1,
     UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);

4. amdgpu_device_ip_set_powergating_state(adev, 
AMD_IP_BLOCK_TYPE_VCN,   AMD_PG_STATE_GATE);


5.  saved_bo

Best Regards!

James

On 2021-05-17 1:43 p.m., Leo Liu wrote:


On 2021-05-17 12:54 p.m., James Zhu wrote:
I am wondering if there are still some jobs kept in the queue, it 
is lucky to check


Yes it's possible, in this case delayed handler is set, so 
cancelling once is enough.





UVD_POWER_STATUS done, but after, fw start a new job that list in 
the queue.


To handle this situation perfectly, we need add mechanism to 
suspend fw first.


I think that should be handled by the sequence from 
vcn_v3_0_stop_dpg_mode().





Another case, if it is unlucky, that  vcn fw hung at that time, 
UVD_POWER_STATUS


always keeps busy.   then it needs force powering gate the vcn hw 
after certain time waiting.


Yep, we still need to gate VCN power after certain timeout.


Regards,

Leo





Best Regards!

James

On 2021-05-17 12:34 p.m., Leo Liu wrote:


On 2021-05-17 11:52 a.m., James Zhu wrote:

During vcn suspends, stop ring continue to receive new requests,
and try to wait for all vcn jobs to finish gracefully.

v2: Forced powering gate vcn hardware after few wainting retry.

Signed-off-by: James Zhu  


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 22 
+-

  1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c

index 2016459..9f3a6e7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -275,9 +275,29 @@ int amdgpu_vcn_suspend(struct amdgpu_device 
*adev)

  {
  unsigned size;
  void *ptr;
+    int retry_max = 6;
  int i;
  - cancel_delayed_work_sync(>vcn.idle_work);
+    for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+    if (adev->vcn.harvest_config & (1 << i))
+    continue;
+    ring = >vcn.inst[i].ring_dec;
+    ring->sched.ready = false;
+
+    for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
+    ring = >vcn.inst[i].ring_enc[j];
+    ring->sched.ready = false;
+    }
+    }
+
+    while (retry_max-- && 
cancel_delayed_work_sync(>vcn.idle_work))

+    mdelay(5);


I think it's possible to have one pending job unprocessed with 
VCN when suspend sequence getting here, but it shouldn't be more 
than one, cancel_delayed_work_sync probably return false after 
the first time, so calling cancel_delayed_work_sync once should 
be enough here. we probably need to wait longer from:


SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1,
        UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);

to make sure the unprocessed job get done.


Regards,

Leo



+    if (!retry_max && !amdgpu_sriov_vf(adev)) {
+    if (RREG32_SOC15(VCN, i, mmUVD_STATUS)) {
+    dev_warn(adev->dev, "Forced powering gate vcn 
hardware!");
+    vcn_v3_0_set_powergating_state(adev, 
AMD_PG_STATE_GATE);

+    }
+    }
    for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
  if (adev->vcn.harvest_config & (1 << i))


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Re: [PATCH v2 1/2] drm/amdgpu: enhance amdgpu_vcn_suspend

[Leo Liu]

The saved data are from the engine cache, it's the runtime of engine 
before suspend, it might be different after you have the engine powered off.



Regards,

Leo



On 2021-05-17 2:11 p.m., Zhu, James wrote:


[AMD Official Use Only - Internal Distribution Only]


save_bo needn't ungate vcn,  it just keeps data in memory.

Thanks & Best Regards!


James Zhu


*From:* Liu, Leo 
*Sent:* Monday, May 17, 2021 2:07 PM
*To:* Zhu, James ; Zhu, James ; 
amd-gfx@lists.freedesktop.org 

*Subject:* Re: [PATCH v2 1/2] drm/amdgpu: enhance amdgpu_vcn_suspend

Definitely, we need to move cancel_delayed_work_sync moved to before 
power gate.


Should "save_bo" be step 4 before power gate ?

Regards,

Leo


On 2021-05-17 1:59 p.m., James Zhu wrote:


Then we forgot the proposal I provided before.

I think the below seq may fixed the race condition issue that we are 
facing.


1. stop scheduling new jobs

    for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
        if (adev->vcn.harvest_config & (1 << i))
            continue;

        ring = >vcn.inst[i].ring_dec;
        ring->sched.ready = false;

        for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
            ring = >vcn.inst[i].ring_enc[j];
            ring->sched.ready = false;
        }
    }

2. cancel_delayed_work_sync(>vcn.idle_work);

3. SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1,
     UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);

4. amdgpu_device_ip_set_powergating_state(adev, 
AMD_IP_BLOCK_TYPE_VCN,   AMD_PG_STATE_GATE);


5.  saved_bo

Best Regards!

James

On 2021-05-17 1:43 p.m., Leo Liu wrote:


On 2021-05-17 12:54 p.m., James Zhu wrote:
I am wondering if there are still some jobs kept in the queue, it 
is lucky to check


Yes it's possible, in this case delayed handler is set, so 
cancelling once is enough.





UVD_POWER_STATUS done, but after, fw start a new job that list in 
the queue.


To handle this situation perfectly, we need add mechanism to 
suspend fw first.


I think that should be handled by the sequence from 
vcn_v3_0_stop_dpg_mode().





Another case, if it is unlucky, that  vcn fw hung at that time, 
UVD_POWER_STATUS


always keeps busy.   then it needs force powering gate the vcn hw 
after certain time waiting.


Yep, we still need to gate VCN power after certain timeout.


Regards,

Leo





Best Regards!

James

On 2021-05-17 12:34 p.m., Leo Liu wrote:


On 2021-05-17 11:52 a.m., James Zhu wrote:

During vcn suspends, stop ring continue to receive new requests,
and try to wait for all vcn jobs to finish gracefully.

v2: Forced powering gate vcn hardware after few wainting retry.

Signed-off-by: James Zhu  


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 22 
+-

  1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c

index 2016459..9f3a6e7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -275,9 +275,29 @@ int amdgpu_vcn_suspend(struct amdgpu_device 
*adev)

  {
  unsigned size;
  void *ptr;
+    int retry_max = 6;
  int i;
  - cancel_delayed_work_sync(>vcn.idle_work);
+    for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+    if (adev->vcn.harvest_config & (1 << i))
+    continue;
+    ring = >vcn.inst[i].ring_dec;
+    ring->sched.ready = false;
+
+    for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
+    ring = >vcn.inst[i].ring_enc[j];
+    ring->sched.ready = false;
+    }
+    }
+
+    while (retry_max-- && 
cancel_delayed_work_sync(>vcn.idle_work))

+    mdelay(5);


I think it's possible to have one pending job unprocessed with VCN 
when suspend sequence getting here, but it shouldn't be more than 
one, cancel_delayed_work_sync probably return false after the 
first time, so calling cancel_delayed_work_sync once should be 
enough here. we probably need to wait longer from:


SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1,
        UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);

to make sure the unprocessed job get done.


Regards,

Leo



+    if (!retry_max && !amdgpu_sriov_vf(adev)) {
+    if (RREG32_SOC15(VCN, i, mmUVD_STATUS)) {
+    dev_warn(adev->dev, "Forced powering gate vcn 
hardware!");
+    vcn_v3_0_set_powergating_state(adev, 
AMD_PG_STATE_GATE);

+    }
+    }
    for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
  if (adev->vcn.harvest_config & (1 << i))
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Re: [PATCH v2 1/2] drm/amdgpu: enhance amdgpu_vcn_suspend

[Zhu, James]

[AMD Official Use Only - Internal Distribution Only]

save_bo needn't ungate vcn,  it just keeps data in memory.


Thanks & Best Regards!


James Zhu


From: Liu, Leo 
Sent: Monday, May 17, 2021 2:07 PM
To: Zhu, James ; Zhu, James ; 
amd-gfx@lists.freedesktop.org 
Subject: Re: [PATCH v2 1/2] drm/amdgpu: enhance amdgpu_vcn_suspend


Definitely, we need to move cancel_delayed_work_sync moved to before power gate.

Should "save_bo" be step 4 before power gate ?

Regards,

Leo


On 2021-05-17 1:59 p.m., James Zhu wrote:

Then we forgot the proposal I provided before.

I think the below seq may fixed the race condition issue that we are facing.

1. stop scheduling new jobs

for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
if (adev->vcn.harvest_config & (1 << i))
continue;

ring = >vcn.inst[i].ring_dec;
ring->sched.ready = false;

for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
ring = >vcn.inst[i].ring_enc[j];
ring->sched.ready = false;
}
}

2.cancel_delayed_work_sync(>vcn.idle_work);

3.SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1,
 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);

4.amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,   
AMD_PG_STATE_GATE);

5.  saved_bo

Best Regards!

James

On 2021-05-17 1:43 p.m., Leo Liu wrote:

On 2021-05-17 12:54 p.m., James Zhu wrote:
I am wondering if there are still some jobs kept in the queue, it is lucky to 
check

Yes it's possible, in this case delayed handler is set, so cancelling once is 
enough.



UVD_POWER_STATUS done, but after, fw start a new job that list in the queue.

To handle this situation perfectly, we need add mechanism to suspend fw first.

I think that should be handled by the sequence from vcn_v3_0_stop_dpg_mode().



Another case, if it is unlucky, that  vcn fw hung at that time, UVD_POWER_STATUS

always keeps busy.   then it needs force powering gate the vcn hw after certain 
time waiting.

Yep, we still need to gate VCN power after certain timeout.


Regards,

Leo




Best Regards!

James

On 2021-05-17 12:34 p.m., Leo Liu wrote:

On 2021-05-17 11:52 a.m., James Zhu wrote:
During vcn suspends, stop ring continue to receive new requests,
and try to wait for all vcn jobs to finish gracefully.

v2: Forced powering gate vcn hardware after few wainting retry.

Signed-off-by: James Zhu 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 22 +-
  1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 2016459..9f3a6e7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -275,9 +275,29 @@ int amdgpu_vcn_suspend(struct amdgpu_device *adev)
  {
  unsigned size;
  void *ptr;
+int retry_max = 6;
  int i;
  -cancel_delayed_work_sync(>vcn.idle_work);
+for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+if (adev->vcn.harvest_config & (1 << i))
+continue;
+ring = >vcn.inst[i].ring_dec;
+ring->sched.ready = false;
+
+for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
+ring = >vcn.inst[i].ring_enc[j];
+ring->sched.ready = false;
+}
+}
+
+while (retry_max-- && cancel_delayed_work_sync(>vcn.idle_work))
+mdelay(5);

I think it's possible to have one pending job unprocessed with VCN when suspend 
sequence getting here, but it shouldn't be more than one, 
cancel_delayed_work_sync probably return false after the first time, so calling 
cancel_delayed_work_sync once should be enough here. we probably need to wait 
longer from:

SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1,
UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);

to make sure the unprocessed job get done.


Regards,

Leo


+if (!retry_max && !amdgpu_sriov_vf(adev)) {
+if (RREG32_SOC15(VCN, i, mmUVD_STATUS)) {
+dev_warn(adev->dev, "Forced powering gate vcn hardware!");
+vcn_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
+}
+}
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
  if (adev->vcn.harvest_config & (1 << i))
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Re: [PATCH v2 1/2] drm/amdgpu: enhance amdgpu_vcn_suspend

[Leo Liu]

Definitely, we need to move cancel_delayed_work_sync moved to before 
power gate.


Should "save_bo" be step 4 before power gate ?

Regards,

Leo


On 2021-05-17 1:59 p.m., James Zhu wrote:


Then we forgot the proposal I provided before.

I think the below seq may fixed the race condition issue that we are 
facing.


1. stop scheduling new jobs

    for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
        if (adev->vcn.harvest_config & (1 << i))
            continue;

        ring = >vcn.inst[i].ring_dec;
        ring->sched.ready = false;

        for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
            ring = >vcn.inst[i].ring_enc[j];
            ring->sched.ready = false;
        }
    }

2.    cancel_delayed_work_sync(>vcn.idle_work);

3. SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1,
     UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);

4. amdgpu_device_ip_set_powergating_state(adev, 
AMD_IP_BLOCK_TYPE_VCN,   AMD_PG_STATE_GATE);


5.  saved_bo

Best Regards!

James

On 2021-05-17 1:43 p.m., Leo Liu wrote:


On 2021-05-17 12:54 p.m., James Zhu wrote:
I am wondering if there are still some jobs kept in the queue, it is 
lucky to check


Yes it's possible, in this case delayed handler is set, so cancelling 
once is enough.





UVD_POWER_STATUS done, but after, fw start a new job that list in 
the queue.


To handle this situation perfectly, we need add mechanism to suspend 
fw first.


I think that should be handled by the sequence from 
vcn_v3_0_stop_dpg_mode().





Another case, if it is unlucky, that  vcn fw hung at that time, 
UVD_POWER_STATUS


always keeps busy.   then it needs force powering gate the vcn hw 
after certain time waiting.


Yep, we still need to gate VCN power after certain timeout.


Regards,

Leo





Best Regards!

James

On 2021-05-17 12:34 p.m., Leo Liu wrote:


On 2021-05-17 11:52 a.m., James Zhu wrote:

During vcn suspends, stop ring continue to receive new requests,
and try to wait for all vcn jobs to finish gracefully.

v2: Forced powering gate vcn hardware after few wainting retry.

Signed-off-by: James Zhu 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 22 +-
  1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c

index 2016459..9f3a6e7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -275,9 +275,29 @@ int amdgpu_vcn_suspend(struct amdgpu_device 
*adev)

  {
  unsigned size;
  void *ptr;
+    int retry_max = 6;
  int i;
  - cancel_delayed_work_sync(>vcn.idle_work);
+    for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+    if (adev->vcn.harvest_config & (1 << i))
+    continue;
+    ring = >vcn.inst[i].ring_dec;
+    ring->sched.ready = false;
+
+    for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
+    ring = >vcn.inst[i].ring_enc[j];
+    ring->sched.ready = false;
+    }
+    }
+
+    while (retry_max-- && 
cancel_delayed_work_sync(>vcn.idle_work))

+    mdelay(5);


I think it's possible to have one pending job unprocessed with VCN 
when suspend sequence getting here, but it shouldn't be more than 
one, cancel_delayed_work_sync probably return false after the first 
time, so calling cancel_delayed_work_sync once should be enough 
here. we probably need to wait longer from:


SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1,
        UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);

to make sure the unprocessed job get done.


Regards,

Leo



+    if (!retry_max && !amdgpu_sriov_vf(adev)) {
+    if (RREG32_SOC15(VCN, i, mmUVD_STATUS)) {
+    dev_warn(adev->dev, "Forced powering gate vcn 
hardware!");

+    vcn_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
+    }
+    }
    for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
  if (adev->vcn.harvest_config & (1 << i))
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Re: [PATCH v2 1/2] drm/amdgpu: enhance amdgpu_vcn_suspend

[James Zhu]

Then we forgot the proposal I provided before.

I think the below seq may fixed the race condition issue that we are facing.

1. stop scheduling new jobs

    for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
        if (adev->vcn.harvest_config & (1 << i))
            continue;

        ring = >vcn.inst[i].ring_dec;
        ring->sched.ready = false;

        for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
            ring = >vcn.inst[i].ring_enc[j];
            ring->sched.ready = false;
        }
    }

2.    cancel_delayed_work_sync(>vcn.idle_work);

3. SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1,
     UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);

4. amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,   
AMD_PG_STATE_GATE);


5.  saved_bo

Best Regards!

James

On 2021-05-17 1:43 p.m., Leo Liu wrote:


On 2021-05-17 12:54 p.m., James Zhu wrote:
I am wondering if there are still some jobs kept in the queue, it is 
lucky to check


Yes it's possible, in this case delayed handler is set, so cancelling 
once is enough.





UVD_POWER_STATUS done, but after, fw start a new job that list in the 
queue.


To handle this situation perfectly, we need add mechanism to suspend 
fw first.


I think that should be handled by the sequence from 
vcn_v3_0_stop_dpg_mode().





Another case, if it is unlucky, that  vcn fw hung at that time, 
UVD_POWER_STATUS


always keeps busy.   then it needs force powering gate the vcn hw 
after certain time waiting.


Yep, we still need to gate VCN power after certain timeout.


Regards,

Leo





Best Regards!

James

On 2021-05-17 12:34 p.m., Leo Liu wrote:


On 2021-05-17 11:52 a.m., James Zhu wrote:

During vcn suspends, stop ring continue to receive new requests,
and try to wait for all vcn jobs to finish gracefully.

v2: Forced powering gate vcn hardware after few wainting retry.

Signed-off-by: James Zhu 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 22 +-
  1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c

index 2016459..9f3a6e7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -275,9 +275,29 @@ int amdgpu_vcn_suspend(struct amdgpu_device 
*adev)

  {
  unsigned size;
  void *ptr;
+    int retry_max = 6;
  int i;
  - cancel_delayed_work_sync(>vcn.idle_work);
+    for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+    if (adev->vcn.harvest_config & (1 << i))
+    continue;
+    ring = >vcn.inst[i].ring_dec;
+    ring->sched.ready = false;
+
+    for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
+    ring = >vcn.inst[i].ring_enc[j];
+    ring->sched.ready = false;
+    }
+    }
+
+    while (retry_max-- && 
cancel_delayed_work_sync(>vcn.idle_work))

+    mdelay(5);


I think it's possible to have one pending job unprocessed with VCN 
when suspend sequence getting here, but it shouldn't be more than 
one, cancel_delayed_work_sync probably return false after the first 
time, so calling cancel_delayed_work_sync once should be enough 
here. we probably need to wait longer from:


SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1,
        UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);

to make sure the unprocessed job get done.


Regards,

Leo



+    if (!retry_max && !amdgpu_sriov_vf(adev)) {
+    if (RREG32_SOC15(VCN, i, mmUVD_STATUS)) {
+    dev_warn(adev->dev, "Forced powering gate vcn 
hardware!");

+    vcn_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
+    }
+    }
    for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
  if (adev->vcn.harvest_config & (1 << i))
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Re: [PATCH v7 16/16] drm/amdgpu: Unmap all MMIO mappings

[Alex Deucher]

On Wed, May 12, 2021 at 10:27 AM Andrey Grodzovsky
 wrote:
>
> Access to those must be prevented post pci_remove
>
> v6: Drop BOs list, unampping VRAM BAR is enough.
>
> Signed-off-by: Andrey Grodzovsky 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 24 +++---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_object.c |  1 +
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c|  4 
>  3 files changed, 22 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index f7cca25c0fa0..73cbc3c7453f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -3666,6 +3666,25 @@ int amdgpu_device_init(struct amdgpu_device *adev,
> return r;
>  }
>
> +static void amdgpu_device_unmap_mmio(struct amdgpu_device *adev)
> +{
> +   /* Clear all CPU mappings pointing to this device */
> +   unmap_mapping_range(adev->ddev.anon_inode->i_mapping, 0, 0, 1);
> +
> +   /* Unmap all mapped bars - Doorbell, registers and VRAM */
> +   amdgpu_device_doorbell_fini(adev);
> +
> +   iounmap(adev->rmmio);
> +   adev->rmmio = NULL;
> +   if (adev->mman.aper_base_kaddr)
> +   iounmap(adev->mman.aper_base_kaddr);
> +   adev->mman.aper_base_kaddr = NULL;
> +
> +   /* Memory manager related */

I think we need:
if (!adev->gmc.xgmi.connected_to_cpu) {
around these two to mirror amdgpu_bo_fini().

Alex

> +   arch_phys_wc_del(adev->gmc.vram_mtrr);
> +   arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size);
> +}
> +
>  /**
>   * amdgpu_device_fini - tear down the driver
>   *
> @@ -3712,6 +3731,8 @@ void amdgpu_device_fini_hw(struct amdgpu_device *adev)
> amdgpu_device_ip_fini_early(adev);
>
> amdgpu_gart_dummy_page_fini(adev);
> +
> +   amdgpu_device_unmap_mmio(adev);
>  }
>
>  void amdgpu_device_fini_sw(struct amdgpu_device *adev)
> @@ -3739,9 +3760,6 @@ void amdgpu_device_fini_sw(struct amdgpu_device *adev)
> }
> if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
> vga_client_register(adev->pdev, NULL, NULL, NULL);
> -   iounmap(adev->rmmio);
> -   adev->rmmio = NULL;
> -   amdgpu_device_doorbell_fini(adev);
>
> if (IS_ENABLED(CONFIG_PERF_EVENTS))
> amdgpu_pmu_fini(adev);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> index 0adffcace326..882fb49f3c41 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> @@ -533,6 +533,7 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev,
> return -ENOMEM;
> drm_gem_private_object_init(adev_to_drm(adev), >tbo.base, size);
> INIT_LIST_HEAD(>shadow_list);
> +
> bo->vm_bo = NULL;
> bo->preferred_domains = bp->preferred_domain ? bp->preferred_domain :
> bp->domain;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index 0d54e70278ca..58ad2fecc9e3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -1841,10 +1841,6 @@ void amdgpu_ttm_fini(struct amdgpu_device *adev)
> amdgpu_bo_free_kernel(>mman.discovery_memory, NULL, NULL);
> amdgpu_ttm_fw_reserve_vram_fini(adev);
>
> -   if (adev->mman.aper_base_kaddr)
> -   iounmap(adev->mman.aper_base_kaddr);
> -   adev->mman.aper_base_kaddr = NULL;
> -
> amdgpu_vram_mgr_fini(adev);
> amdgpu_gtt_mgr_fini(adev);
> ttm_range_man_fini(>mman.bdev, AMDGPU_PL_GDS);
> --
> 2.25.1
>
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Re: [PATCH v2 1/2] drm/amdgpu: enhance amdgpu_vcn_suspend

[Leo Liu]

On 2021-05-17 12:54 p.m., James Zhu wrote:
I am wondering if there are still some jobs kept in the queue, it is 
lucky to check


Yes it's possible, in this case delayed handler is set, so cancelling 
once is enough.





UVD_POWER_STATUS done, but after, fw start a new job that list in the 
queue.


To handle this situation perfectly, we need add mechanism to suspend 
fw first.


I think that should be handled by the sequence from 
vcn_v3_0_stop_dpg_mode().





Another case, if it is unlucky, that  vcn fw hung at that time, 
UVD_POWER_STATUS


always keeps busy.   then it needs force powering gate the vcn hw 
after certain time waiting.


Yep, we still need to gate VCN power after certain timeout.


Regards,

Leo





Best Regards!

James

On 2021-05-17 12:34 p.m., Leo Liu wrote:


On 2021-05-17 11:52 a.m., James Zhu wrote:

During vcn suspends, stop ring continue to receive new requests,
and try to wait for all vcn jobs to finish gracefully.

v2: Forced powering gate vcn hardware after few wainting retry.

Signed-off-by: James Zhu 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 22 +-
  1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c

index 2016459..9f3a6e7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -275,9 +275,29 @@ int amdgpu_vcn_suspend(struct amdgpu_device *adev)
  {
  unsigned size;
  void *ptr;
+    int retry_max = 6;
  int i;
  -    cancel_delayed_work_sync(>vcn.idle_work);
+    for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+    if (adev->vcn.harvest_config & (1 << i))
+    continue;
+    ring = >vcn.inst[i].ring_dec;
+    ring->sched.ready = false;
+
+    for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
+    ring = >vcn.inst[i].ring_enc[j];
+    ring->sched.ready = false;
+    }
+    }
+
+    while (retry_max-- && 
cancel_delayed_work_sync(>vcn.idle_work))

+    mdelay(5);


I think it's possible to have one pending job unprocessed with VCN 
when suspend sequence getting here, but it shouldn't be more than 
one, cancel_delayed_work_sync probably return false after the first 
time, so calling cancel_delayed_work_sync once should be enough here. 
we probably need to wait longer from:


SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1,
        UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);

to make sure the unprocessed job get done.


Regards,

Leo



+    if (!retry_max && !amdgpu_sriov_vf(adev)) {
+    if (RREG32_SOC15(VCN, i, mmUVD_STATUS)) {
+    dev_warn(adev->dev, "Forced powering gate vcn hardware!");
+    vcn_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
+    }
+    }
    for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
  if (adev->vcn.harvest_config & (1 << i))

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Re: [PATCH v7 12/16] drm/amdgpu: Fix hang on device removal.

[Alex Deucher]

Reviewed-by: Alex Deucher 

On Mon, May 17, 2021 at 10:40 AM Andrey Grodzovsky
 wrote:
>
> Ping
>
> Andrey
>
> On 2021-05-14 10:42 a.m., Andrey Grodzovsky wrote:
> > Ping
> >
> > Andrey
> >
> > On 2021-05-12 10:26 a.m., Andrey Grodzovsky wrote:
> >> If removing while commands in flight you cannot wait to flush the
> >> HW fences on a ring since the device is gone.
> >>
> >> Signed-off-by: Andrey Grodzovsky 
> >> ---
> >>   drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 16 ++--
> >>   1 file changed, 10 insertions(+), 6 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
> >> b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
> >> index 1ffb36bd0b19..fa03702ecbfb 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
> >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
> >> @@ -36,6 +36,7 @@
> >>   #include 
> >>   #include 
> >> +#include 
> >>   #include "amdgpu.h"
> >>   #include "amdgpu_trace.h"
> >> @@ -525,8 +526,7 @@ int amdgpu_fence_driver_init(struct amdgpu_device
> >> *adev)
> >>*/
> >>   void amdgpu_fence_driver_fini_hw(struct amdgpu_device *adev)
> >>   {
> >> -unsigned i, j;
> >> -int r;
> >> +int i, r;
> >>   for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
> >>   struct amdgpu_ring *ring = adev->rings[i];
> >> @@ -535,11 +535,15 @@ void amdgpu_fence_driver_fini_hw(struct
> >> amdgpu_device *adev)
> >>   continue;
> >>   if (!ring->no_scheduler)
> >>   drm_sched_fini(>sched);
> >> -r = amdgpu_fence_wait_empty(ring);
> >> -if (r) {
> >> -/* no need to trigger GPU reset as we are unloading */
> >> +/* You can't wait for HW to signal if it's gone */
> >> +if (!drm_dev_is_unplugged(>ddev))
> >> +r = amdgpu_fence_wait_empty(ring);
> >> +else
> >> +r = -ENODEV;
> >> +/* no need to trigger GPU reset as we are unloading */
> >> +if (r)
> >>   amdgpu_fence_driver_force_completion(ring);
> >> -}
> >> +
> >>   if (ring->fence_drv.irq_src)
> >>   amdgpu_irq_put(adev, ring->fence_drv.irq_src,
> >>  ring->fence_drv.irq_type);
> >>
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Re: [PATCH 1/2] drm/amdgpu/display: add helper functions to get/set backlight (v2)

[Alex Deucher]

Ping on this series.

Alex

On Tue, May 11, 2021 at 11:44 AM Alex Deucher  wrote:
>
> And cache the value.  These can be used by the backlight callbacks
> and modesetting functions.
>
> v2: rebase on latest backlight changes.
>
> Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1337
> Signed-off-by: Alex Deucher 
> ---
>  .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 42 ++-
>  .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h |  7 
>  2 files changed, 38 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 5df187a6e25f..167c8759fbc9 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -3467,26 +3467,28 @@ static u32 convert_brightness_to_user(const struct 
> amdgpu_dm_backlight_caps *cap
>  max - min);
>  }
>
> -static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
> +static int amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm,
> +u32 user_brightness)
>  {
> -   struct amdgpu_display_manager *dm = bl_get_data(bd);
> struct amdgpu_dm_backlight_caps caps;
> struct dc_link *link[AMDGPU_DM_MAX_NUM_EDP];
> -   u32 brightness;
> +   u32 brightness[AMDGPU_DM_MAX_NUM_EDP];
> bool rc;
> int i;
>
> amdgpu_dm_update_backlight_caps(dm);
> caps = dm->backlight_caps;
>
> -   for (i = 0; i < dm->num_of_edps; i++)
> +   for (i = 0; i < dm->num_of_edps; i++) {
> +   dm->brightness[i] = user_brightness;
> +   brightness[i] = convert_brightness_from_user(, 
> dm->brightness[i]);
> link[i] = (struct dc_link *)dm->backlight_link[i];
> +   }
>
> -   brightness = convert_brightness_from_user(, 
> bd->props.brightness);
> -   // Change brightness based on AUX property
> +   /* Change brightness based on AUX property */
> if (caps.aux_support) {
> for (i = 0; i < dm->num_of_edps; i++) {
> -   rc = dc_link_set_backlight_level_nits(link[i], true, 
> brightness,
> +   rc = dc_link_set_backlight_level_nits(link[i], true, 
> brightness[i],
> AUX_BL_DEFAULT_TRANSITION_TIME_MS);
> if (!rc) {
> DRM_ERROR("DM: Failed to update backlight via 
> AUX on eDP[%d]\n", i);
> @@ -3495,7 +3497,7 @@ static int amdgpu_dm_backlight_update_status(struct 
> backlight_device *bd)
> }
> } else {
> for (i = 0; i < dm->num_of_edps; i++) {
> -   rc = 
> dc_link_set_backlight_level(dm->backlight_link[i], brightness, 0);
> +   rc = 
> dc_link_set_backlight_level(dm->backlight_link[i], brightness[i], 0);
> if (!rc) {
> DRM_ERROR("DM: Failed to update backlight on 
> eDP[%d]\n", i);
> break;
> @@ -3506,9 +3508,17 @@ static int amdgpu_dm_backlight_update_status(struct 
> backlight_device *bd)
> return rc ? 0 : 1;
>  }
>
> -static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
> +static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
>  {
> struct amdgpu_display_manager *dm = bl_get_data(bd);
> +
> +   amdgpu_dm_backlight_set_level(dm, bd->props.brightness);
> +
> +   return 0;
> +}
> +
> +static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm)
> +{
> struct amdgpu_dm_backlight_caps caps;
>
> amdgpu_dm_update_backlight_caps(dm);
> @@ -3521,17 +3531,24 @@ static int amdgpu_dm_backlight_get_brightness(struct 
> backlight_device *bd)
>
> rc = dc_link_get_backlight_level_nits(link, , );
> if (!rc)
> -   return bd->props.brightness;
> +   return dm->brightness[0];
> return convert_brightness_to_user(, avg);
> } else {
> int ret = dc_link_get_backlight_level(dm->backlight_link[0]);
>
> if (ret == DC_ERROR_UNEXPECTED)
> -   return bd->props.brightness;
> +   return dm->brightness[0];
> return convert_brightness_to_user(, ret);
> }
>  }
>
> +static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
> +{
> +   struct amdgpu_display_manager *dm = bl_get_data(bd);
> +
> +   return amdgpu_dm_backlight_get_level(dm);
> +}
> +
>  static const struct backlight_ops amdgpu_dm_backlight_ops = {
> .options = BL_CORE_SUSPENDRESUME,
> .get_brightness = amdgpu_dm_backlight_get_brightness,
> @@ -3543,8 +3560,11 @@ amdgpu_dm_register_backlight_device(struct 
> amdgpu_display_manager *dm)
>  {
> char 

Re: [RFC PATCH v2 1/6] drm/doc: Color Management and HDR10 RFC

[Sebastian Wick]

On 2021-05-14 23:07, Harry Wentland wrote:

Use the new DRM RFC doc section to capture the RFC previously only
described in the cover letter at
https://patchwork.freedesktop.org/series/89506/

Update the RFC based on feedback received:
 * don't use color_encoding property to define color space
 * expand on reason for SDR luminance definition
 * define input/output transfer functions for luminance space 
transforms,

   rather than defining the luminance space of an input directly

Signed-off-by: Harry Wentland 
---
 Documentation/gpu/rfc/hdr-wide-gamut.rst | 416 +++
 Documentation/gpu/rfc/index.rst  |   4 +
 2 files changed, 420 insertions(+)
 create mode 100644 Documentation/gpu/rfc/hdr-wide-gamut.rst

diff --git a/Documentation/gpu/rfc/hdr-wide-gamut.rst
b/Documentation/gpu/rfc/hdr-wide-gamut.rst
new file mode 100644
index ..132898668eac
--- /dev/null
+++ b/Documentation/gpu/rfc/hdr-wide-gamut.rst
@@ -0,0 +1,416 @@
+==
+HDR & Wide Color Gamut Support
+==
+
+.. role:: wy-text-strike
+
+ToDo
+
+
+* :wy-text-strike:`Reformat as RST kerneldoc` - done
+* :wy-text-strike:`Don't use color_encoding for color_space 
definitions` - done
+* :wy-text-strike:`Update SDR luminance description and reasoning` - 
done

+* :wy-text-strike:`Clarify 3D LUT required for some color space
transformations` - done
+* :wy-text-strike:`Highlight need for named color space and EOTF
definitions` - done
+* :wy-text-strike:`Define transfer function API` - done
+* :wy-text-strike:`Draft upstream plan` - done
+* Reference to wayland and/or Chrome plans
+* Sketch view of HW pipeline for couple of HW implementations
+
+
+Upstream Plan
+=
+
+* Reach consensus on DRM/KMS API
+* Implement support in amdgpu
+* Implement IGT tests
+* Add API support to Weston, ChromiumOS, or other canonical
open-source project interested in HDR
+* Merge user-space
+* Merge kernel patches
+
+
+Introduction
+
+
+We are looking to enable HDR support for a couple of single-plane and
+multi-plane scenarios. To do this effectively we recommend new 
interfaces

+to drm_plane. Below I'll give a bit of background on HDR and why we
+propose these interfaces.
+
+
+Overview and background
+===
+
+Defining a pixel's luminance
+
+
+The luminance space of pixels in a framebuffer/plane presented to the
+display is not well defined in the DRM/KMS APIs. It is usually assumed 
to
+be in a 2.2 or 2.4 gamma space and has no mapping to an absolute 
luminance

+value; it is interpreted in relative terms.
+
+Luminance can be measured and described in absolute terms as candela
+per meter squared, or cd/m2, or nits. Even though a pixel value can be
+mapped to luminance in a linear fashion to do so without losing a lot 
of

+detail requires 16-bpc color depth. The reason for this is that human
+perception can distinguish roughly between a 0.5-1% luminance delta. A
+linear representation is suboptimal, wasting precision in the 
highlights

+and losing precision in the shadows.
+
+A gamma curve is a decent approximation to a human's perception of
+luminance, but the PQ (perceptual quantizer) function [1] improves on
+it. It also defines the luminance values in absolute terms, with the
+highest value being 10,000 nits and the lowest 0.0005 nits.
+
+Using a content that's defined in PQ space we can approximate the real
+world in a much better way.
+
+Here are some examples of real-life objects and their approximate
+luminance values:
+
+.. flat-table::
+   :header-rows: 1
+
+   * - Object
+ - Luminance in nits
+
+   *  - Fluorescent light
+  - 10,000
+
+   *  - Highlights
+  - 1,000 - sunlight
+
+   *  - White Objects
+  - 250 - 1,000
+
+   *  - Typical Objects
+  - 1 - 250
+
+   *  - Shadows
+  - 0.01 - 1
+
+   *  - Ultra Blacks
+  - 0 - 0.0005
+
+Transfer functions
+--
+
+Traditionally we used the terms gamma and de-gamma to describe the
+encoding of a pixel's luminance value and the operation to transfer 
from

+a linear luminance space to the non-linear space used to encode the
+pixels. Since some newer encodings don't use a gamma curve I suggest
+we refer to non-linear encodings using the terms EOTF, and OETF[2], or
+simply as transfer function in general.
+
+The EOTF (Electro-Optical Transfer Function) describes how to transfer
+from an electrical signal to an optical signal. This was traditionally
+done by the de-gamma function.
+
+The OETF (Opto Electronic Transfer Function) describes how to transfer
+from an optical signal to an electronic signal. This was traditionally
+done by the gamma function.
+
+More generally we can name the transfer function describing the 
transform
+between scanout and blending space as the **input transfer function**, 
and
+the transfer function describing the transform from blending space to 
the

+output space as **output transfer 

Re: [PATCH] drm/amd/amdgpu: fix refcount leak

[Alex Deucher]

On Mon, May 17, 2021 at 4:47 AM Christian König
 wrote:
>
> Am 17.05.21 um 10:26 schrieb Jingwen Chen:
> > [Why]
> > the gem object rfb->base.obj[0] is get according to num_planes
> > in amdgpufb_create, but is not put according to num_planes
> >
> > [How]
> > put rfb->base.obj[0] in amdgpu_fbdev_destroy according to num_planes
> >
> > Signed-off-by: Jingwen Chen 
>
> Looks sane to me, but Alex might want to take a look as well.
>
> Acked-by: Christian König 

Looks good to me as well.

Reviewed-by: Alex Deucher 

>
> > ---
> >   drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 3 +++
> >   1 file changed, 3 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c 
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
> > index 4f10c4529840..09b048647523 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
> > @@ -288,10 +288,13 @@ static int amdgpufb_create(struct drm_fb_helper 
> > *helper,
> >   static int amdgpu_fbdev_destroy(struct drm_device *dev, struct 
> > amdgpu_fbdev *rfbdev)
> >   {
> >   struct amdgpu_framebuffer *rfb = >rfb;
> > + int i;
> >
> >   drm_fb_helper_unregister_fbi(>helper);
> >
> >   if (rfb->base.obj[0]) {
> > + for (i = 0; i < rfb->base.format->num_planes; i++)
> > + drm_gem_object_put(rfb->base.obj[0]);
> >   amdgpufb_destroy_pinned_object(rfb->base.obj[0]);
> >   rfb->base.obj[0] = NULL;
> >   drm_framebuffer_unregister_private(>base);
>
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Re: [trivial PATCH] drm/amd/display: Fix typo of format termination newline

[Alex Deucher]

On Sat, May 15, 2021 at 1:01 PM Joe Perches  wrote:
>
> /n should be \n
>
> Signed-off-by: Joe Perches 

Applied.  Thanks!

Alex

> ---
>  drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c   | 2 +-
>  drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c | 2 +-
>  drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c | 2 +-
>  3 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c 
> b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
> index 45f96221a094..b38fee783277 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
> @@ -1724,7 +1724,7 @@ static bool init_soc_bounding_box(struct dc *dc,
> DC_LOGGER_INIT(dc->ctx->logger);
>
> if (!is_soc_bounding_box_valid(dc)) {
> -   DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__);
> +   DC_LOG_ERROR("%s: not valid soc bounding box\n", __func__);
> return false;
> }
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c 
> b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
> index 5b54b7fc5105..3bf66c994dd5 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
> @@ -1497,7 +1497,7 @@ static bool init_soc_bounding_box(struct dc *dc,
> DC_LOGGER_INIT(dc->ctx->logger);
>
> if (!is_soc_bounding_box_valid(dc)) {
> -   DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__);
> +   DC_LOG_ERROR("%s: not valid soc bounding box\n", __func__);
> return false;
> }
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c 
> b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
> index fc2dea243d1b..84c61128423e 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
> @@ -1093,7 +1093,7 @@ static bool init_soc_bounding_box(struct dc *dc,  
> struct resource_pool *pool)
> DC_LOGGER_INIT(dc->ctx->logger);
>
> if (!is_soc_bounding_box_valid(dc)) {
> -   DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__);
> +   DC_LOG_ERROR("%s: not valid soc bounding box\n", __func__);
> return false;
> }
>
>
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Re: [RFC PATCH 0/3] A drm_plane API to support HDR planes

[Sebastian Wick]

On 2021-05-17 10:57, Pekka Paalanen wrote:

On Fri, 14 May 2021 17:05:11 -0400
Harry Wentland  wrote:


On 2021-04-27 10:50 a.m., Pekka Paalanen wrote:
> On Mon, 26 Apr 2021 13:38:49 -0400
> Harry Wentland  wrote:


...


>> ## Mastering Luminances
>>
>> Now we are able to use the PQ 2084 EOTF to define the luminance of
>> pixels in absolute terms. Unfortunately we're again presented with
>> physical limitations of the display technologies on the market today.
>> Here are a few examples of luminance ranges of displays.
>>
>> | Display  | Luminance range in nits |
>> |  | --- |
>> | Typical PC display   | 0.3 - 200   |
>> | Excellent LCD HDTV   | 0.3 - 400   |
>> | HDR LCD w/ local dimming | 0.05 - 1,500|
>>
>> Since no display can currently show the full 0.0005 to 10,000 nits
>> luminance range the display will need to tonemap the HDR content, i.e
>> to fit the content within a display's capabilities. To assist with
>> tonemapping HDR content is usually accompanied with a metadata that
>> describes (among other things) the minimum and maximum mastering
>> luminance, i.e. the maximum and minimum luminance of the display that
>> was used to master the HDR content.
>>
>> The HDR metadata is currently defined on the drm_connector via the
>> hdr_output_metadata blob property.
>>
>> It might be useful to define per-plane hdr metadata, as different
>> planes might have been mastered differently.
>
> I don't think this would directly help with the dynamic range blending
> problem. You still need to establish the mapping between the optical
> values from two different EOTFs and dynamic ranges. Or can you know
> which optical values match the mastering display maximum and minimum
> luminances for not-PQ?
>

My understanding of this is probably best illustrated by this example:

Assume HDR was mastered on a display with a maximum white level of 500
nits and played back on a display that supports a max white level of 
400
nits. If you know the mastering white level of 500 you know that this 
is
the maximum value you need to compress down to 400 nits, allowing you 
to

use the full extent of the 400 nits panel.


Right, but in the kernel, where do you get these nits values from?

hdr_output_metadata blob is infoframe data to the monitor. I think this
should be independent of the metadata used for color transformations in
the display pipeline before the monitor.

EDID may tell us the monitor HDR metadata, but again what is used in
the color transformations should be independent, because EDIDs lie,
lighting environments change, and users have different preferences.

What about black levels?

Do you want to do black level adjustment?

How exactly should the compression work?

Where do you map the mid-tones?

What if the end user wants something different?


I suspect that this is not about tone mapping at all. The use cases
listed always have the display in PQ mode and just assume that no
content exceeds the PQ limitations. Then you can simply bring all
content to the color space with a matrix multiplication and then map the
linear light content somewhere into the PQ range. Tone mapping is
performed in the display only.

From a generic wayland compositor point of view this is uninteresting.

I completely agree with what you said below though. I would even argue
that all generic KMS abstract pipeline elements must have a well defined
place in the pipeline and follow an exact specified formula.




If you do not know the mastering luminance is 500 nits you would
have to compress 10,000 nits down to 400 (assuming PQ), losing quite
a bit of the full 400 nits available as you'll need room to map the 
500
to 10,000 nits range which in reality is completely unused. You might 
end

up with mapping 500 nits to 350 nits, instead of mapping it to 400.


The quality of the result depends on the compression (tone-mapping)
algorithm. I believe no-one will ever do a simple linear compression of
ranges.

Instead, you probably do something smooth in the black end, keep
mid-tones roughly as they are, and the again do a smooth saturation to
some "reasonable" level that goes well with the monitor in the current
lighting environment without introducing coloring artifacts, and just
clip the huge overshoot of the full PQ-range.

There are many big and small decisions to be made in how to map
out-of-gamut or out-of-brightness values into the displayable range,
and no algorithm fits all use cases. I believe this is why e.g. ICC
has several different "render intents", some of which are so vaguely
defined that they are practically undefined - just like what "a good
picture" means. You have essentially three dimensions: luminance, hue,
and saturation. Which one will you sacrifice, shift or emphasize and to
what degree to fit the square content peg into the round display hole?

A naive example: Let's say content has 300 nits red. Your display can

Re: [PATCH v2 1/2] drm/amdgpu: enhance amdgpu_vcn_suspend

[James Zhu]

I am wondering if there are still some jobs kept in the queue, it is 
lucky to check


UVD_POWER_STATUS done, but after, fw start a new job that list in the queue.

To handle this situation perfectly, we need add mechanism to suspend fw 
first.


Another case, if it is unlucky, that  vcn fw hung at that time, 
UVD_POWER_STATUS


always keeps busy.   then it needs force powering gate the vcn hw after 
certain time waiting.


Best Regards!

James

On 2021-05-17 12:34 p.m., Leo Liu wrote:


On 2021-05-17 11:52 a.m., James Zhu wrote:

During vcn suspends, stop ring continue to receive new requests,
and try to wait for all vcn jobs to finish gracefully.

v2: Forced powering gate vcn hardware after few wainting retry.

Signed-off-by: James Zhu 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 22 +-
  1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c

index 2016459..9f3a6e7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -275,9 +275,29 @@ int amdgpu_vcn_suspend(struct amdgpu_device *adev)
  {
  unsigned size;
  void *ptr;
+    int retry_max = 6;
  int i;
  -    cancel_delayed_work_sync(>vcn.idle_work);
+    for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+    if (adev->vcn.harvest_config & (1 << i))
+    continue;
+    ring = >vcn.inst[i].ring_dec;
+    ring->sched.ready = false;
+
+    for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
+    ring = >vcn.inst[i].ring_enc[j];
+    ring->sched.ready = false;
+    }
+    }
+
+    while (retry_max-- && 
cancel_delayed_work_sync(>vcn.idle_work))

+    mdelay(5);


I think it's possible to have one pending job unprocessed with VCN 
when suspend sequence getting here, but it shouldn't be more than one, 
cancel_delayed_work_sync probably return false after the first time, 
so calling cancel_delayed_work_sync once should be enough here. we 
probably need to wait longer from:


SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1,
        UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);

to make sure the unprocessed job get done.


Regards,

Leo



+    if (!retry_max && !amdgpu_sriov_vf(adev)) {
+    if (RREG32_SOC15(VCN, i, mmUVD_STATUS)) {
+    dev_warn(adev->dev, "Forced powering gate vcn hardware!");
+    vcn_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
+    }
+    }
    for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
  if (adev->vcn.harvest_config & (1 << i))

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Re: [PATCH v2 1/2] drm/amdgpu: enhance amdgpu_vcn_suspend

[Leo Liu]

On 2021-05-17 11:52 a.m., James Zhu wrote:

During vcn suspends, stop ring continue to receive new requests,
and try to wait for all vcn jobs to finish gracefully.

v2: Forced powering gate vcn hardware after few wainting retry.

Signed-off-by: James Zhu 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 22 +-
  1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 2016459..9f3a6e7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -275,9 +275,29 @@ int amdgpu_vcn_suspend(struct amdgpu_device *adev)
  {
unsigned size;
void *ptr;
+   int retry_max = 6;
int i;
  
-	cancel_delayed_work_sync(>vcn.idle_work);

+   for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+   if (adev->vcn.harvest_config & (1 << i))
+   continue;
+   ring = >vcn.inst[i].ring_dec;
+   ring->sched.ready = false;
+
+   for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
+   ring = >vcn.inst[i].ring_enc[j];
+   ring->sched.ready = false;
+   }
+   }
+
+   while (retry_max-- && cancel_delayed_work_sync(>vcn.idle_work))
+   mdelay(5);


I think it's possible to have one pending job unprocessed with VCN when 
suspend sequence getting here, but it shouldn't be more than one, 
cancel_delayed_work_sync probably return false after the first time, so 
calling cancel_delayed_work_sync once should be enough here. we probably 
need to wait longer from:


SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1,
        UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);

to make sure the unprocessed job get done.


Regards,

Leo



+   if (!retry_max && !amdgpu_sriov_vf(adev)) {
+   if (RREG32_SOC15(VCN, i, mmUVD_STATUS)) {
+   dev_warn(adev->dev, "Forced powering gate vcn 
hardware!");
+   vcn_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
+   }
+   }
  
  	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {

if (adev->vcn.harvest_config & (1 << i))

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[PATCH v2 1/2] drm/amdgpu: enhance amdgpu_vcn_suspend

[James Zhu]

During vcn suspends, stop ring continue to receive new requests,
and try to wait for all vcn jobs to finish gracefully.

v2: Forced powering gate vcn hardware after few wainting retry.

Signed-off-by: James Zhu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 22 +-
 1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 2016459..9f3a6e7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -275,9 +275,29 @@ int amdgpu_vcn_suspend(struct amdgpu_device *adev)
 {
unsigned size;
void *ptr;
+   int retry_max = 6;
int i;
 
-   cancel_delayed_work_sync(>vcn.idle_work);
+   for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+   if (adev->vcn.harvest_config & (1 << i))
+   continue;
+   ring = >vcn.inst[i].ring_dec;
+   ring->sched.ready = false;
+
+   for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
+   ring = >vcn.inst[i].ring_enc[j];
+   ring->sched.ready = false;
+   }
+   }
+
+   while (retry_max-- && cancel_delayed_work_sync(>vcn.idle_work))
+   mdelay(5);
+   if (!retry_max && !amdgpu_sriov_vf(adev)) {
+   if (RREG32_SOC15(VCN, i, mmUVD_STATUS)) {
+   dev_warn(adev->dev, "Forced powering gate vcn 
hardware!");
+   vcn_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
+   }
+   }
 
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
if (adev->vcn.harvest_config & (1 << i))
-- 
2.7.4

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[PATCH 2/2] drm/amdgpu: remove unsued vcn_v3_0_hw_fini

[James Zhu]

Removed unsued vcn_v3_0_hw_fini when enhanced
common amdgpu_vicn_suspend is applied.

Signed-off-by: James Zhu 
---
 drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 4 
 1 file changed, 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c 
b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index cf165ab..e7505ec 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -411,10 +411,6 @@ static int vcn_v3_0_suspend(void *handle)
int r;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-   r = vcn_v3_0_hw_fini(adev);
-   if (r)
-   return r;
-
r = amdgpu_vcn_suspend(adev);
 
return r;
-- 
2.7.4

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[PATCH 1/2] drm/amdgpu: enhance amdgpu_vcn_suspend

[James Zhu]

During vcn suspends, stop ring continue to receive new requests,
and try to wait for all vcn jobs to finish gracefully.

Signed-off-by: James Zhu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 20 +++-
 1 file changed, 19 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 2016459..7e9f5cb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -275,9 +275,27 @@ int amdgpu_vcn_suspend(struct amdgpu_device *adev)
 {
unsigned size;
void *ptr;
+   int retry_max = 6;
int i;
 
-   cancel_delayed_work_sync(>vcn.idle_work);
+   for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+   if (adev->vcn.harvest_config & (1 << i))
+   continue;
+   ring = >vcn.inst[i].ring_dec;
+   ring->sched.ready = false;
+
+   for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
+   ring = >vcn.inst[i].ring_enc[j];
+   ring->sched.ready = false;
+   }
+   }
+
+   while (retry_max--) {
+   if (cancel_delayed_work_sync(>vcn.idle_work)) {
+   dev_warn(adev->dev, "Waiting for left VCN job(s) to 
finish gracefully ...");
+   mdelay(5);
+   }
+   }
 
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
if (adev->vcn.harvest_config & (1 << i))
-- 
2.7.4

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RE: [PATCH v5 01/10] drm/amdgpu: Indirect register access for Navi12 sriov

[Zhou, Peng Ju]

[AMD Official Use Only - Internal Distribution Only]

Hi Alex
About your comment:
"I think patches 1-4, 16 need to be squashed together to avoid breaking the 
build.  Please also provide a description of how the new macros work in the 
patch description.  Describe how the reworked macros properly handle sending GC 
and MMHUB accesses via the RLC rather than via some other mechanism.  It's 
really hard to follow the macro logic."

I squashed patches 1-4, 16 and add more detail description in the patch 
description.
Can you help to review the patch series?


-- 
BW
Pengju Zhou



> -Original Message-
> From: Peng Ju Zhou 
> Sent: Monday, May 17, 2021 10:39 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhou, Peng Ju 
> Subject: [PATCH v5 01/10] drm/amdgpu: Indirect register access for Navi12
> sriov
> 
> This patch series are used for GC/MMHUB(part)/IH_RB_CNTL indirect access
> in the SRIOV environment.
> 
> There are 4 bits, controlled by host, to control if
> GC/MMHUB(part)/IH_RB_CNTL indirect access enabled.
> (one bit is master bit controls other 3 bits)
> 
> For GC registers, changing all the register access from MMIO to RLC and use
> RLC as the default access method in the full access time.
> 
> For partial MMHUB registers, changing their access from MMIO to RLC in the
> full access time, the remaining registers keep the original access method.
> 
> For IH_RB_CNTL register, changing it's access from MMIO to PSP.
> 
> Signed-off-by: Peng Ju Zhou 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h|  1 +
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  2 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h|  4 +-
>  drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 78 +--
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c  |  9 ++-
>  drivers/gpu/drm/amd/amdgpu/soc15_common.h  | 87 +--
> ---
>  6 files changed, 97 insertions(+), 84 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 3147c1c935c8..4e0c90e52ab6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -1147,6 +1147,7 @@ int emu_soc_asic_init(struct amdgpu_device
> *adev);
>   * Registers read & write functions.
>   */
>  #define AMDGPU_REGS_NO_KIQ(1<<1)
> +#define AMDGPU_REGS_RLC  (1<<2)
> 
>  #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg),
> AMDGPU_REGS_NO_KIQ)  #define WREG32_NO_KIQ(reg, v)
> amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) diff --git
> a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 7c6c435e5d02..a2392bbe1e21 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -490,7 +490,7 @@ void amdgpu_mm_wreg_mmio_rlc(struct
> amdgpu_device *adev,
>   adev->gfx.rlc.funcs &&
>   adev->gfx.rlc.funcs->is_rlcg_access_range) {
>   if (adev->gfx.rlc.funcs->is_rlcg_access_range(adev, reg))
> - return adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, v, 0);
> + return adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, v, 0,
> 0);
>   } else {
>   writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
>   }
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
> index 4fc2ce8ce8ab..7a4775ab6804 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
> @@ -127,8 +127,8 @@ struct amdgpu_rlc_funcs {
>   void (*reset)(struct amdgpu_device *adev);
>   void (*start)(struct amdgpu_device *adev);
>   void (*update_spm_vmid)(struct amdgpu_device *adev, unsigned
> vmid);
> - void (*rlcg_wreg)(struct amdgpu_device *adev, u32 offset, u32 v, u32
> flag);
> - u32 (*rlcg_rreg)(struct amdgpu_device *adev, u32 offset, u32 flag);
> + void (*rlcg_wreg)(struct amdgpu_device *adev, u32 offset, u32 v, u32
> acc_flags, u32 hwip);
> + u32 (*rlcg_rreg)(struct amdgpu_device *adev, u32 offset, u32
> +acc_flags, u32 hwip);
>   bool (*is_rlcg_access_range)(struct amdgpu_device *adev, uint32_t
> reg);  };
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index 2a3427e5020f..7c5c1ff7d97e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -1427,38 +1427,36 @@ static const struct soc15_reg_golden
> golden_settings_gc_10_1_2[] =
>   SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x,
> 0x0080)  };
> 
> -static bool gfx_v10_is_rlcg_rw(struct amdgpu_device *adev, u32 offset,
> uint32_t *flag, bool write) -{
> - /* always programed by rlcg, only for gc */
> - if (offset == SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI) ||
> - offset == SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO) ||
> - offset == SOC15_REG_OFFSET(GC, 

Re: [PATCH] drm/amdgpu: Handle IOMMU enabled case.

[Felix Kuehling]

Am 2021-05-17 um 10:38 a.m. schrieb Andrey Grodzovsky:
> Problem:
> Handle all DMA IOMMU group related dependencies before the
> group is removed. Those manifest themself in that when IOMMU
> enabled DMA map/unmap is dependent on the presence of IOMMU
> group the device belongs to but, this group is released once
> the device is removed from PCI topology.
>
> Fix:
> Expedite all such unmap operations to pci remove driver callback.
>
> v5: Drop IOMMU notifier and switch to lockless call to ttm_tt_unpopulate
> v6: Drop the BO unamp list
> v7:
> Drop amdgpu_gart_fini
> In amdgpu_ih_ring_fini do uncinditional  check (!ih->ring)
> to avoid freeing uniniitalized rings.
> Call amdgpu_ih_ring_fini unconditionally.
> v8: Add deatiled explanation
>
> Signed-off-by: Andrey Grodzovsky 

This patch is

Reviewed-by: Felix Kuehling 


> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  4 ++--
>  drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c   | 14 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h   |  2 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c |  6 --
>  drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c|  5 +
>  drivers/gpu/drm/amd/amdgpu/cik_ih.c|  1 -
>  drivers/gpu/drm/amd/amdgpu/cz_ih.c |  1 -
>  drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c |  1 -
>  drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c  |  1 -
>  drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c  |  1 -
>  drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c  |  1 -
>  drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c  |  1 -
>  drivers/gpu/drm/amd/amdgpu/iceland_ih.c|  1 -
>  drivers/gpu/drm/amd/amdgpu/navi10_ih.c |  4 
>  drivers/gpu/drm/amd/amdgpu/si_ih.c |  1 -
>  drivers/gpu/drm/amd/amdgpu/tonga_ih.c  |  1 -
>  drivers/gpu/drm/amd/amdgpu/vega10_ih.c |  4 
>  drivers/gpu/drm/amd/amdgpu/vega20_ih.c |  4 
>  18 files changed, 13 insertions(+), 40 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 18598eda18f6..a0bff4713672 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -3256,7 +3256,6 @@ static const struct attribute *amdgpu_dev_attributes[] 
> = {
>   NULL
>  };
>  
> -
>  /**
>   * amdgpu_device_init - initialize the driver
>   *
> @@ -3698,12 +3697,13 @@ void amdgpu_device_fini_hw(struct amdgpu_device *adev)
>   amdgpu_ucode_sysfs_fini(adev);
>   sysfs_remove_files(>dev->kobj, amdgpu_dev_attributes);
>  
> -
>   amdgpu_fbdev_fini(adev);
>  
>   amdgpu_irq_fini_hw(adev);
>  
>   amdgpu_device_ip_fini_early(adev);
> +
> + amdgpu_gart_dummy_page_fini(adev);
>  }
>  
>  void amdgpu_device_fini_sw(struct amdgpu_device *adev)
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
> index c5a9a4fb10d2..6460cf723f0a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
> @@ -92,7 +92,7 @@ static int amdgpu_gart_dummy_page_init(struct amdgpu_device 
> *adev)
>   *
>   * Frees the dummy page used by the driver (all asics).
>   */
> -static void amdgpu_gart_dummy_page_fini(struct amdgpu_device *adev)
> +void amdgpu_gart_dummy_page_fini(struct amdgpu_device *adev)
>  {
>   if (!adev->dummy_page_addr)
>   return;
> @@ -365,15 +365,3 @@ int amdgpu_gart_init(struct amdgpu_device *adev)
>  
>   return 0;
>  }
> -
> -/**
> - * amdgpu_gart_fini - tear down the driver info for managing the gart
> - *
> - * @adev: amdgpu_device pointer
> - *
> - * Tear down the gart driver info and free the dummy page (all asics).
> - */
> -void amdgpu_gart_fini(struct amdgpu_device *adev)
> -{
> - amdgpu_gart_dummy_page_fini(adev);
> -}
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h
> index a25fe97b0196..030b9d4c736a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h
> @@ -57,7 +57,7 @@ void amdgpu_gart_table_vram_free(struct amdgpu_device 
> *adev);
>  int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev);
>  void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev);
>  int amdgpu_gart_init(struct amdgpu_device *adev);
> -void amdgpu_gart_fini(struct amdgpu_device *adev);
> +void amdgpu_gart_dummy_page_fini(struct amdgpu_device *adev);
>  int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
>  int pages);
>  int amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset,
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
> index faaa6aa2faaf..433469ace6f4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
> @@ -115,9 +115,11 @@ int amdgpu_ih_ring_init(struct amdgpu_device *adev, 
> struct amdgpu_ih_ring *ih,
>   */
>  void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring 
> *ih)
>  

Re: [PATCH v7 16/16] drm/amdgpu: Unmap all MMIO mappings

[Andrey Grodzovsky]

Ping

Andrey

On 2021-05-14 10:42 a.m., Andrey Grodzovsky wrote:

Ping

Andrey

On 2021-05-12 10:26 a.m., Andrey Grodzovsky wrote:

Access to those must be prevented post pci_remove

v6: Drop BOs list, unampping VRAM BAR is enough.

Signed-off-by: Andrey Grodzovsky 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 24 +++---
  drivers/gpu/drm/amd/amdgpu/amdgpu_object.c |  1 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c    |  4 
  3 files changed, 22 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

index f7cca25c0fa0..73cbc3c7453f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3666,6 +3666,25 @@ int amdgpu_device_init(struct amdgpu_device *adev,
  return r;
  }
+static void amdgpu_device_unmap_mmio(struct amdgpu_device *adev)
+{
+    /* Clear all CPU mappings pointing to this device */
+    unmap_mapping_range(adev->ddev.anon_inode->i_mapping, 0, 0, 1);
+
+    /* Unmap all mapped bars - Doorbell, registers and VRAM */
+    amdgpu_device_doorbell_fini(adev);
+
+    iounmap(adev->rmmio);
+    adev->rmmio = NULL;
+    if (adev->mman.aper_base_kaddr)
+    iounmap(adev->mman.aper_base_kaddr);
+    adev->mman.aper_base_kaddr = NULL;
+
+    /* Memory manager related */
+    arch_phys_wc_del(adev->gmc.vram_mtrr);
+    arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size);
+}
+
  /**
   * amdgpu_device_fini - tear down the driver
   *
@@ -3712,6 +3731,8 @@ void amdgpu_device_fini_hw(struct amdgpu_device 
*adev)

  amdgpu_device_ip_fini_early(adev);
  amdgpu_gart_dummy_page_fini(adev);
+
+    amdgpu_device_unmap_mmio(adev);
  }
  void amdgpu_device_fini_sw(struct amdgpu_device *adev)
@@ -3739,9 +3760,6 @@ void amdgpu_device_fini_sw(struct amdgpu_device 
*adev)

  }
  if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
  vga_client_register(adev->pdev, NULL, NULL, NULL);
-    iounmap(adev->rmmio);
-    adev->rmmio = NULL;
-    amdgpu_device_doorbell_fini(adev);
  if (IS_ENABLED(CONFIG_PERF_EVENTS))
  amdgpu_pmu_fini(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c

index 0adffcace326..882fb49f3c41 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -533,6 +533,7 @@ static int amdgpu_bo_do_create(struct 
amdgpu_device *adev,

  return -ENOMEM;
  drm_gem_private_object_init(adev_to_drm(adev), >tbo.base, 
size);

  INIT_LIST_HEAD(>shadow_list);
+
  bo->vm_bo = NULL;
  bo->preferred_domains = bp->preferred_domain ? 
bp->preferred_domain :

  bp->domain;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

index 0d54e70278ca..58ad2fecc9e3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1841,10 +1841,6 @@ void amdgpu_ttm_fini(struct amdgpu_device *adev)
  amdgpu_bo_free_kernel(>mman.discovery_memory, NULL, NULL);
  amdgpu_ttm_fw_reserve_vram_fini(adev);
-    if (adev->mman.aper_base_kaddr)
-    iounmap(adev->mman.aper_base_kaddr);
-    adev->mman.aper_base_kaddr = NULL;
-
  amdgpu_vram_mgr_fini(adev);
  amdgpu_gtt_mgr_fini(adev);
  ttm_range_man_fini(>mman.bdev, AMDGPU_PL_GDS);


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Re: [PATCH v7 12/16] drm/amdgpu: Fix hang on device removal.

[Andrey Grodzovsky]

Ping

Andrey

On 2021-05-14 10:42 a.m., Andrey Grodzovsky wrote:

Ping

Andrey

On 2021-05-12 10:26 a.m., Andrey Grodzovsky wrote:

If removing while commands in flight you cannot wait to flush the
HW fences on a ring since the device is gone.

Signed-off-by: Andrey Grodzovsky 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 16 ++--
  1 file changed, 10 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c

index 1ffb36bd0b19..fa03702ecbfb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
@@ -36,6 +36,7 @@
  #include 
  #include 
+#include 
  #include "amdgpu.h"
  #include "amdgpu_trace.h"
@@ -525,8 +526,7 @@ int amdgpu_fence_driver_init(struct amdgpu_device 
*adev)

   */
  void amdgpu_fence_driver_fini_hw(struct amdgpu_device *adev)
  {
-    unsigned i, j;
-    int r;
+    int i, r;
  for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
  struct amdgpu_ring *ring = adev->rings[i];
@@ -535,11 +535,15 @@ void amdgpu_fence_driver_fini_hw(struct 
amdgpu_device *adev)

  continue;
  if (!ring->no_scheduler)
  drm_sched_fini(>sched);
-    r = amdgpu_fence_wait_empty(ring);
-    if (r) {
-    /* no need to trigger GPU reset as we are unloading */
+    /* You can't wait for HW to signal if it's gone */
+    if (!drm_dev_is_unplugged(>ddev))
+    r = amdgpu_fence_wait_empty(ring);
+    else
+    r = -ENODEV;
+    /* no need to trigger GPU reset as we are unloading */
+    if (r)
  amdgpu_fence_driver_force_completion(ring);
-    }
+
  if (ring->fence_drv.irq_src)
  amdgpu_irq_put(adev, ring->fence_drv.irq_src,
 ring->fence_drv.irq_type);


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[PATCH] drm/amdgpu: Handle IOMMU enabled case.

[Andrey Grodzovsky]

Problem:
Handle all DMA IOMMU group related dependencies before the
group is removed. Those manifest themself in that when IOMMU
enabled DMA map/unmap is dependent on the presence of IOMMU
group the device belongs to but, this group is released once
the device is removed from PCI topology.

Fix:
Expedite all such unmap operations to pci remove driver callback.

v5: Drop IOMMU notifier and switch to lockless call to ttm_tt_unpopulate
v6: Drop the BO unamp list
v7:
Drop amdgpu_gart_fini
In amdgpu_ih_ring_fini do uncinditional  check (!ih->ring)
to avoid freeing uniniitalized rings.
Call amdgpu_ih_ring_fini unconditionally.
v8: Add deatiled explanation

Signed-off-by: Andrey Grodzovsky 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  4 ++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c   | 14 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h   |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c |  6 --
 drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c|  5 +
 drivers/gpu/drm/amd/amdgpu/cik_ih.c|  1 -
 drivers/gpu/drm/amd/amdgpu/cz_ih.c |  1 -
 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c |  1 -
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c  |  1 -
 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c  |  1 -
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c  |  1 -
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c  |  1 -
 drivers/gpu/drm/amd/amdgpu/iceland_ih.c|  1 -
 drivers/gpu/drm/amd/amdgpu/navi10_ih.c |  4 
 drivers/gpu/drm/amd/amdgpu/si_ih.c |  1 -
 drivers/gpu/drm/amd/amdgpu/tonga_ih.c  |  1 -
 drivers/gpu/drm/amd/amdgpu/vega10_ih.c |  4 
 drivers/gpu/drm/amd/amdgpu/vega20_ih.c |  4 
 18 files changed, 13 insertions(+), 40 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 18598eda18f6..a0bff4713672 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3256,7 +3256,6 @@ static const struct attribute *amdgpu_dev_attributes[] = {
NULL
 };
 
-
 /**
  * amdgpu_device_init - initialize the driver
  *
@@ -3698,12 +3697,13 @@ void amdgpu_device_fini_hw(struct amdgpu_device *adev)
amdgpu_ucode_sysfs_fini(adev);
sysfs_remove_files(>dev->kobj, amdgpu_dev_attributes);
 
-
amdgpu_fbdev_fini(adev);
 
amdgpu_irq_fini_hw(adev);
 
amdgpu_device_ip_fini_early(adev);
+
+   amdgpu_gart_dummy_page_fini(adev);
 }
 
 void amdgpu_device_fini_sw(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
index c5a9a4fb10d2..6460cf723f0a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
@@ -92,7 +92,7 @@ static int amdgpu_gart_dummy_page_init(struct amdgpu_device 
*adev)
  *
  * Frees the dummy page used by the driver (all asics).
  */
-static void amdgpu_gart_dummy_page_fini(struct amdgpu_device *adev)
+void amdgpu_gart_dummy_page_fini(struct amdgpu_device *adev)
 {
if (!adev->dummy_page_addr)
return;
@@ -365,15 +365,3 @@ int amdgpu_gart_init(struct amdgpu_device *adev)
 
return 0;
 }
-
-/**
- * amdgpu_gart_fini - tear down the driver info for managing the gart
- *
- * @adev: amdgpu_device pointer
- *
- * Tear down the gart driver info and free the dummy page (all asics).
- */
-void amdgpu_gart_fini(struct amdgpu_device *adev)
-{
-   amdgpu_gart_dummy_page_fini(adev);
-}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h
index a25fe97b0196..030b9d4c736a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h
@@ -57,7 +57,7 @@ void amdgpu_gart_table_vram_free(struct amdgpu_device *adev);
 int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev);
 void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev);
 int amdgpu_gart_init(struct amdgpu_device *adev);
-void amdgpu_gart_fini(struct amdgpu_device *adev);
+void amdgpu_gart_dummy_page_fini(struct amdgpu_device *adev);
 int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
   int pages);
 int amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
index faaa6aa2faaf..433469ace6f4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
@@ -115,9 +115,11 @@ int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct 
amdgpu_ih_ring *ih,
  */
 void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih)
 {
+
+   if (!ih->ring)
+   return;
+
if (ih->use_bus_addr) {
-   if (!ih->ring)
-   return;
 
/* add 8 bytes for the rptr/wptr shadows and
 * add them to the end of the ring allocation.
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c 

Re: [PATCH 1/3] drm/amdkfd: classify and map mixed svm range pages in GPU

[Felix Kuehling]

Am 2021-05-17 um 9:44 a.m. schrieb Felix Kuehling:
> A few more comments inline. Sorry I took so long.
>
> Am 2021-05-12 um 1:34 p.m. schrieb Alex Sierra:
>
>> [Why]
>> svm ranges can have mixed pages from device or system memory.
>> A good example is, after a prange has been allocated in VRAM and a
>> copy-on-write is triggered by a fork. This invalidates some pages
>> inside the prange. Endding up in mixed pages.
>>
>> [How]
>> By classifying each page inside a prange, based on its type. Device or
>> system memory, during dma mapping call. If page corresponds
>> to VRAM domain, a flag is set to its dma_addr entry for each GPU.
>> Then, at the GPU page table mapping. All group of contiguous pages within
>> the same type are mapped with their proper pte flags.
>>
>> v2:
>> Instead of using ttm_res to calculate vram pfns in the svm_range. It is now
>> done by setting the vram real physical address into drm_addr array.
>> This makes more flexible VRAM management, plus removes the need to have
>> a BO reference in the svm_range.
>>
>> Signed-off-by: Alex Sierra 
>> ---
>>  drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 71 ++--
>>  drivers/gpu/drm/amd/amdkfd/kfd_svm.h |  1 +
>>  2 files changed, 46 insertions(+), 26 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c 
>> b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
>> index 2b4318646a75..0ab10cb24205 100644
>> --- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
>> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
>> @@ -119,11 +119,12 @@ static void svm_range_remove_notifier(struct svm_range 
>> *prange)
>>  }
>>  
>>  static int
>> -svm_range_dma_map_dev(struct device *dev, dma_addr_t **dma_addr,
>> +svm_range_dma_map_dev(struct amdgpu_device *adev, dma_addr_t **dma_addr,
>>unsigned long *hmm_pfns, uint64_t npages)
>>  {
>>  enum dma_data_direction dir = DMA_BIDIRECTIONAL;
>>  dma_addr_t *addr = *dma_addr;
>> +struct device *dev = adev->dev;
>>  struct page *page;
>>  int i, r;
>>  
>> @@ -141,6 +142,14 @@ svm_range_dma_map_dev(struct device *dev, dma_addr_t 
>> **dma_addr,
>>  dma_unmap_page(dev, addr[i], PAGE_SIZE, dir);
>>  
>>  page = hmm_pfn_to_page(hmm_pfns[i]);
>> +if (is_zone_device_page(page)) {
>> +addr[i] = (hmm_pfns[i] << PAGE_SHIFT) +
>> +   adev->vm_manager.vram_base_offset -
>> +   adev->kfd.dev->pgmap.range.start;
>> +addr[i] |= SVM_RANGE_VRAM_DOMAIN;
>> +pr_debug("vram address detected: 0x%llx\n", addr[i]);
>> +continue;
>> +}
>>  addr[i] = dma_map_page(dev, page, 0, PAGE_SIZE, dir);
>>  r = dma_mapping_error(dev, addr[i]);
>>  if (r) {
>> @@ -175,7 +184,7 @@ svm_range_dma_map(struct svm_range *prange, unsigned 
>> long *bitmap,
>>  }
>>  adev = (struct amdgpu_device *)pdd->dev->kgd;
>>  
>> -r = svm_range_dma_map_dev(adev->dev, >dma_addr[gpuidx],
>> +r = svm_range_dma_map_dev(adev, >dma_addr[gpuidx],
>>hmm_pfns, prange->npages);
>>  if (r)
>>  break;
>> @@ -1003,21 +1012,22 @@ svm_range_split_by_granularity(struct kfd_process 
>> *p, struct mm_struct *mm,
>>  }
>>  
>>  static uint64_t
>> -svm_range_get_pte_flags(struct amdgpu_device *adev, struct svm_range 
>> *prange)
>> +svm_range_get_pte_flags(struct amdgpu_device *adev, struct svm_range 
>> *prange,
>> +int domain)
>>  {
>>  struct amdgpu_device *bo_adev;
>>  uint32_t flags = prange->flags;
>>  uint32_t mapping_flags = 0;
>>  uint64_t pte_flags;
>> -bool snoop = !prange->ttm_res;
>> +bool snoop = !!domain;
> This is a bit obscure and it assumes that SVM_RANGE_VRAM_DOMAIN is 0.
> And it's not actually correct. Make this
>
> bool snoop = (domain != SVM_RANGE_VRAM_DOMAIN);
>
>
>>  bool coherent = flags & KFD_IOCTL_SVM_FLAG_COHERENT;
>>  
>> -if (prange->svm_bo && prange->ttm_res)
>> +if (domain == SVM_RANGE_VRAM_DOMAIN)
>>  bo_adev = amdgpu_ttm_adev(prange->svm_bo->bo->tbo.bdev);
>>  
>>  switch (adev->asic_type) {
>>  case CHIP_ARCTURUS:
>> -if (prange->svm_bo && prange->ttm_res) {
>> +if (domain == SVM_RANGE_VRAM_DOMAIN) {
>>  if (bo_adev == adev) {
>>  mapping_flags |= coherent ?
>>  AMDGPU_VM_MTYPE_CC : AMDGPU_VM_MTYPE_RW;
>> @@ -1032,7 +1042,7 @@ svm_range_get_pte_flags(struct amdgpu_device *adev, 
>> struct svm_range *prange)
>>  }
>>  break;
>>  case CHIP_ALDEBARAN:
>> -if (prange->svm_bo && prange->ttm_res) {
>> +if (domain == SVM_RANGE_VRAM_DOMAIN) {
>>  if (bo_adev == adev) {
>>  mapping_flags |= coherent ?

[PATCH v5 09/10] drm/amdgpu: Use PSP to program IH_RB_CNTL* registers

[Peng Ju Zhou]

use psp to program IH_RB_CNTL* if indirect access
for ih enabled in SRIOV environment.

Signed-off-by: Victor 
Signed-off-by: Peng Ju Zhou 
---
 drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 19 +--
 drivers/gpu/drm/amd/amdgpu/nv.c|  2 +-
 2 files changed, 18 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c 
b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
index f4e4040bbd25..2e69cf8db072 100644
--- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
@@ -151,7 +151,14 @@ static int navi10_ih_toggle_ring_interrupts(struct 
amdgpu_device *adev,
/* enable_intr field is only valid in ring0 */
if (ih == >irq.ih)
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 
0));
-   WREG32(ih_regs->ih_rb_cntl, tmp);
+   if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
+   if (psp_reg_program(>psp, ih_regs->psp_reg_id, tmp)) {
+   DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
+   return -ETIMEDOUT;
+   }
+   } else {
+   WREG32(ih_regs->ih_rb_cntl, tmp);
+   }
 
if (enable) {
ih->enabled = true;
@@ -261,7 +268,15 @@ static int navi10_ih_enable_ring(struct amdgpu_device 
*adev,
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0);
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1);
}
-   WREG32(ih_regs->ih_rb_cntl, tmp);
+
+   if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
+   if (psp_reg_program(>psp, ih_regs->psp_reg_id, tmp)) {
+   DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
+   return -ETIMEDOUT;
+   }
+   } else {
+   WREG32(ih_regs->ih_rb_cntl, tmp);
+   }
 
if (ih == >irq.ih) {
/* set the ih ring 0 writeback address whether it's enabled or 
not */
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index a9ad28fb55b3..b9c9c4d4606c 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -845,8 +845,8 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
case CHIP_NAVI12:
amdgpu_device_ip_block_add(adev, _common_ip_block);
amdgpu_device_ip_block_add(adev, _v10_0_ip_block);
-   amdgpu_device_ip_block_add(adev, _ih_ip_block);
amdgpu_device_ip_block_add(adev, _v11_0_ip_block);
+   amdgpu_device_ip_block_add(adev, _ih_ip_block);
if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
amdgpu_device_ip_block_add(adev, _v11_0_ip_block);
if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
-- 
2.17.1

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[PATCH v5 10/10] drm/amdgpu: Skip the program of MMMC_VM_AGP_* in SRIOV

[Peng Ju Zhou]

KMD should not program these registers, the value were
defined in the host, so skip them in the SRIOV environment.

Signed-off-by: Peng Ju Zhou 
---
 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 
b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
index e24225b3d42a..422d106a650b 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
@@ -197,12 +197,12 @@ static void mmhub_v2_0_init_system_aperture_regs(struct 
amdgpu_device *adev)
uint64_t value;
uint32_t tmp;
 
-   /* Program the AGP BAR */
-   WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_BASE, 0);
-   WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 
24);
-   WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
-
if (!amdgpu_sriov_vf(adev)) {
+   /* Program the AGP BAR */
+   WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_BASE, 0);
+   WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_BOT, 
adev->gmc.agp_start >> 24);
+   WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_TOP, adev->gmc.agp_end 
>> 24);
+
/* Program the system aperture low logical page number. */
WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 
18);
-- 
2.17.1

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[PATCH v5 08/10] drm/amdgpu: Modify MMHUB register access from MMIO to RLCG in file mmhub_v2*

[Peng Ju Zhou]

From: pengzhou 

In SRIOV environment, KMD should access GC registers
with RLCG if GC indirect access flag enabled.

Signed-off-by: pengzhou 
---
 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 37 +
 1 file changed, 19 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 
b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
index ac76081b91d5..e24225b3d42a 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
@@ -29,6 +29,7 @@
 #include "mmhub/mmhub_2_0_0_default.h"
 #include "navi10_enum.h"
 
+#include "gc/gc_10_1_0_offset.h"
 #include "soc15_common.h"
 
 #define mmMM_ATC_L2_MISC_CG_Sienna_Cichlid  0x064d
@@ -165,11 +166,11 @@ static void mmhub_v2_0_setup_vm_pt_regs(struct 
amdgpu_device *adev, uint32_t vmi
 {
struct amdgpu_vmhub *hub = >vmhub[AMDGPU_MMHUB_0];
 
-   WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
+   WREG32_SOC15_OFFSET_RLC(MMHUB, 0, 
mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
hub->ctx_addr_distance * vmid,
lower_32_bits(page_table_base));
 
-   WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
+   WREG32_SOC15_OFFSET_RLC(MMHUB, 0, 
mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
hub->ctx_addr_distance * vmid,
upper_32_bits(page_table_base));
 }
@@ -180,14 +181,14 @@ static void mmhub_v2_0_init_gart_aperture_regs(struct 
amdgpu_device *adev)
 
mmhub_v2_0_setup_vm_pt_regs(adev, 0, pt_base);
 
-   WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
+   WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
 (u32)(adev->gmc.gart_start >> 12));
-   WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
+   WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
 (u32)(adev->gmc.gart_start >> 44));
 
-   WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
+   WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
 (u32)(adev->gmc.gart_end >> 12));
-   WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
+   WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
 (u32)(adev->gmc.gart_end >> 44));
 }
 
@@ -197,9 +198,9 @@ static void mmhub_v2_0_init_system_aperture_regs(struct 
amdgpu_device *adev)
uint32_t tmp;
 
/* Program the AGP BAR */
-   WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BASE, 0);
-   WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
-   WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
+   WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_BASE, 0);
+   WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 
24);
+   WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
 
if (!amdgpu_sriov_vf(adev)) {
/* Program the system aperture low logical page number. */
@@ -308,7 +309,7 @@ static void mmhub_v2_0_enable_system_domain(struct 
amdgpu_device *adev)
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL,
RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
-   WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL, tmp);
+   WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_CNTL, tmp);
 }
 
 static void mmhub_v2_0_disable_identity_aperture(struct amdgpu_device *adev)
@@ -370,16 +371,16 @@ static void mmhub_v2_0_setup_vmid_config(struct 
amdgpu_device *adev)
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
!adev->gmc.noretry);
-   WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL,
+   WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT1_CNTL,
i * hub->ctx_distance, tmp);
-   WREG32_SOC15_OFFSET(MMHUB, 0, 
mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
+   WREG32_SOC15_OFFSET_RLC(MMHUB, 0, 
mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
i * hub->ctx_addr_distance, 0);
-   WREG32_SOC15_OFFSET(MMHUB, 0, 
mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
+   WREG32_SOC15_OFFSET_RLC(MMHUB, 0, 
mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
i * hub->ctx_addr_distance, 0);
-   WREG32_SOC15_OFFSET(MMHUB, 0, 
mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
+   WREG32_SOC15_OFFSET_RLC(MMHUB, 0, 
mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
i * hub->ctx_addr_distance,
lower_32_bits(adev->vm_manager.max_pfn - 
1));
-

[PATCH v5 07/10] drm/amdgpu: Modify GC register access from MMIO to RLCG in file amdgpu_gmc.c

[Peng Ju Zhou]

In SRIOV environment, KMD should access GC registers
with RLCG if GC indirect access flag enabled.

Signed-off-by: Peng Ju Zhou 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c |  9 +++--
 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c  | 25 +
 2 files changed, 24 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index a129ecc73869..3313d43bb94a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
@@ -629,13 +629,18 @@ void amdgpu_gmc_set_vm_fault_masks(struct amdgpu_device 
*adev, int hub_type,
for (i = 0; i < 16; i++) {
reg = hub->vm_context0_cntl + hub->ctx_distance * i;
 
-   tmp = RREG32(reg);
+   tmp = (hub_type == AMDGPU_GFXHUB_0) ?
+   RREG32_SOC15_IP(GC, reg) :
+   RREG32_SOC15_IP(MMHUB, reg);
+
if (enable)
tmp |= hub->vm_cntx_cntl_vm_fault;
else
tmp &= ~hub->vm_cntx_cntl_vm_fault;
 
-   WREG32(reg, tmp);
+   (hub_type == AMDGPU_GFXHUB_0) ?
+   WREG32_SOC15_IP(GC, reg, tmp) :
+   WREG32_SOC15_IP(MMHUB, reg, tmp);
}
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index c134af6b0ca0..52eba885289d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -229,6 +229,10 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device 
*adev, uint32_t vmid,
/* Use register 17 for GART */
const unsigned eng = 17;
unsigned int i;
+   unsigned char hub_ip = 0;
+
+   hub_ip = (vmhub == AMDGPU_GFXHUB_0) ?
+  GC_HWIP : MMHUB_HWIP;
 
spin_lock(>gmc.invalidate_lock);
/*
@@ -242,8 +246,9 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device 
*adev, uint32_t vmid,
if (use_semaphore) {
for (i = 0; i < adev->usec_timeout; i++) {
/* a read return value of 1 means semaphore acuqire */
-   tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem +
-   hub->eng_distance * eng);
+   tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem +
+hub->eng_distance * eng, hub_ip);
+
if (tmp & 0x1)
break;
udelay(1);
@@ -253,7 +258,9 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device 
*adev, uint32_t vmid,
DRM_ERROR("Timeout waiting for sem acquire in VM 
flush!\n");
}
 
-   WREG32_NO_KIQ(hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req);
+   WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req +
+ hub->eng_distance * eng,
+ inv_req, hub_ip);
 
/*
 * Issue a dummy read to wait for the ACK register to be cleared
@@ -261,12 +268,14 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device 
*adev, uint32_t vmid,
 */
if ((vmhub == AMDGPU_GFXHUB_0) &&
(adev->asic_type < CHIP_SIENNA_CICHLID))
-   RREG32_NO_KIQ(hub->vm_inv_eng0_req + hub->eng_distance * eng);
+   RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req +
+ hub->eng_distance * eng, hub_ip);
 
/* Wait for ACK with a delay.*/
for (i = 0; i < adev->usec_timeout; i++) {
-   tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack +
-   hub->eng_distance * eng);
+   tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_ack +
+ hub->eng_distance * eng, hub_ip);
+
tmp &= 1 << vmid;
if (tmp)
break;
@@ -280,8 +289,8 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device 
*adev, uint32_t vmid,
 * add semaphore release after invalidation,
 * write with 0 means semaphore release
 */
-   WREG32_NO_KIQ(hub->vm_inv_eng0_sem +
- hub->eng_distance * eng, 0);
+   WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem +
+ hub->eng_distance * eng, 0, hub_ip);
 
spin_unlock(>gmc.invalidate_lock);
 
-- 
2.17.1

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[PATCH v5 06/10] drm/amdgpu: Modify GC register access from MMIO to RLCG in file nv.c

[Peng Ju Zhou]

In SRIOV environment, KMD should access GC registers
with RLCG if GC indirect access flag enabled.

Signed-off-by: Peng Ju Zhou 
---
 drivers/gpu/drm/amd/amdgpu/nv.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 32c34470404c..a9ad28fb55b3 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -466,7 +466,7 @@ void nv_grbm_select(struct amdgpu_device *adev,
grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, 
queue);
 
-   WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl);
+   WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl);
 }
 
 static void nv_vga_set_state(struct amdgpu_device *adev, bool state)
-- 
2.17.1

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[PATCH v5 05/10] drm/amdgpu: Modify GC register access from MMIO to RLCG in file sdma_v5*

[Peng Ju Zhou]

In SRIOV environment, KMD should access GC registers
with RLCG if GC indirect access flag enabled.

Signed-off-by: Peng Ju Zhou 
---
 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 78 ++
 1 file changed, 42 insertions(+), 36 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
index 04c68a79eca4..e5dded824afa 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
@@ -324,9 +324,9 @@ static uint64_t sdma_v5_0_ring_get_wptr(struct amdgpu_ring 
*ring)
wptr = READ_ONCE(*((u64 *)>wb.wb[ring->wptr_offs]));
DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
} else {
-   wptr = RREG32(sdma_v5_0_get_reg_offset(adev, ring->me, 
mmSDMA0_GFX_RB_WPTR_HI));
+   wptr = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, 
ring->me, mmSDMA0_GFX_RB_WPTR_HI));
wptr = wptr << 32;
-   wptr |= RREG32(sdma_v5_0_get_reg_offset(adev, ring->me, 
mmSDMA0_GFX_RB_WPTR));
+   wptr |= RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, 
ring->me, mmSDMA0_GFX_RB_WPTR));
DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", 
ring->me, wptr);
}
 
@@ -367,9 +367,9 @@ static void sdma_v5_0_ring_set_wptr(struct amdgpu_ring 
*ring)
lower_32_bits(ring->wptr << 2),
ring->me,
upper_32_bits(ring->wptr << 2));
-   WREG32(sdma_v5_0_get_reg_offset(adev, ring->me, 
mmSDMA0_GFX_RB_WPTR),
+   WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, 
mmSDMA0_GFX_RB_WPTR),
lower_32_bits(ring->wptr << 2));
-   WREG32(sdma_v5_0_get_reg_offset(adev, ring->me, 
mmSDMA0_GFX_RB_WPTR_HI),
+   WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, 
mmSDMA0_GFX_RB_WPTR_HI),
upper_32_bits(ring->wptr << 2));
}
 }
@@ -545,12 +545,12 @@ static void sdma_v5_0_gfx_stop(struct amdgpu_device *adev)
amdgpu_ttm_set_buffer_funcs_status(adev, false);
 
for (i = 0; i < adev->sdma.num_instances; i++) {
-   rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, 
mmSDMA0_GFX_RB_CNTL));
+   rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, 
mmSDMA0_GFX_RB_CNTL));
rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 
0);
-   WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), 
rb_cntl);
-   ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, 
mmSDMA0_GFX_IB_CNTL));
+   WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, 
mmSDMA0_GFX_RB_CNTL), rb_cntl);
+   ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, 
mmSDMA0_GFX_IB_CNTL));
ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 
0);
-   WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), 
ib_cntl);
+   WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, 
mmSDMA0_GFX_IB_CNTL), ib_cntl);
}
 }
 
@@ -611,11 +611,11 @@ static void sdma_v5_0_ctx_switch_enable(struct 
amdgpu_device *adev, bool enable)
}
 
if (enable && amdgpu_sdma_phase_quantum) {
-   WREG32(sdma_v5_0_get_reg_offset(adev, i, 
mmSDMA0_PHASE0_QUANTUM),
+   WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, 
mmSDMA0_PHASE0_QUANTUM),
   phase_quantum);
-   WREG32(sdma_v5_0_get_reg_offset(adev, i, 
mmSDMA0_PHASE1_QUANTUM),
+   WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, 
mmSDMA0_PHASE1_QUANTUM),
   phase_quantum);
-   WREG32(sdma_v5_0_get_reg_offset(adev, i, 
mmSDMA0_PHASE2_QUANTUM),
+   WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, 
mmSDMA0_PHASE2_QUANTUM),
   phase_quantum);
}
if (!amdgpu_sriov_vf(adev))
@@ -682,58 +682,63 @@ static int sdma_v5_0_gfx_resume(struct amdgpu_device 
*adev)
 
/* Set ring buffer size in dwords */
rb_bufsz = order_base_2(ring->ring_size / 4);
-   rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, 
mmSDMA0_GFX_RB_CNTL));
+   rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, 
mmSDMA0_GFX_RB_CNTL));
rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, 
rb_bufsz);
 #ifdef __BIG_ENDIAN
rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 
RB_SWAP_ENABLE, 1);
rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
RPTR_WRITEBACK_SWAP_ENABLE, 1);
 #endif
-   WREG32(sdma_v5_0_get_reg_offset(adev, i, 

[PATCH v5 03/10] drm/amdgpu: Modify GC register access from MMIO to RLCG in file kfd_v10*

[Peng Ju Zhou]

In SRIOV environment, KMD should access GC registers
with RLCG if GC indirect access flag enabled.

Signed-off-by: Peng Ju Zhou 
---
 .../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c| 42 +--
 1 file changed, 21 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
index 62aa1a6f64ed..491acdf92f73 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
@@ -96,8 +96,8 @@ static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, 
uint32_t vmid,
 
lock_srbm(kgd, 0, 0, 0, vmid);
 
-   WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), sh_mem_config);
-   WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases);
+   WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config);
+   WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
/* APE1 no longer exists on GFX9 */
 
unlock_srbm(kgd);
@@ -161,7 +161,7 @@ static int kgd_init_interrupts(struct kgd_dev *kgd, 
uint32_t pipe_id)
 
lock_srbm(kgd, mec, pipe, 0, 0);
 
-   WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL),
+   WREG32_SOC15(GC, 0, mmCPC_INT_CNTL,
CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK |
CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK);
 
@@ -239,13 +239,13 @@ static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, 
uint32_t pipe_id,
 
for (reg = hqd_base;
 reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++)
-   WREG32(reg, mqd_hqd[reg - hqd_base]);
+   WREG32_SOC15_IP(GC, reg, mqd_hqd[reg - hqd_base]);
 
 
/* Activate doorbell logic before triggering WPTR poll. */
data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control,
 CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
-   WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), data);
+   WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, data);
 
if (wptr) {
/* Don't read wptr with get_user because the user
@@ -274,27 +274,27 @@ static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, 
uint32_t pipe_id,
guessed_wptr += m->cp_hqd_pq_wptr_lo & ~(queue_size - 1);
guessed_wptr += (uint64_t)m->cp_hqd_pq_wptr_hi << 32;
 
-   WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO),
+   WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
   lower_32_bits(guessed_wptr));
-   WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI),
+   WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
   upper_32_bits(guessed_wptr));
-   WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR),
+   WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
   lower_32_bits((uint64_t)wptr));
-   WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI),
+   WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
   upper_32_bits((uint64_t)wptr));
pr_debug("%s setting CP_PQ_WPTR_POLL_CNTL1 to %x\n", __func__,
 (uint32_t)get_queue_mask(adev, pipe_id, queue_id));
-   WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1),
+   WREG32_SOC15(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1,
   (uint32_t)get_queue_mask(adev, pipe_id, queue_id));
}
 
/* Start the EOP fetcher */
-   WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_RPTR),
+   WREG32_SOC15(GC, 0, mmCP_HQD_EOP_RPTR,
   REG_SET_FIELD(m->cp_hqd_eop_rptr,
 CP_HQD_EOP_RPTR, INIT_FETCHER, 1));
 
data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);
-   WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE), data);
+   WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, data);
 
release_queue(kgd);
 
@@ -365,7 +365,7 @@ static int kgd_hqd_dump(struct kgd_dev *kgd,
if (WARN_ON_ONCE(i >= HQD_N_REGS))  \
break;  \
(*dump)[i][0] = (addr) << 2;\
-   (*dump)[i++][1] = RREG32(addr); \
+   (*dump)[i++][1] = RREG32_SOC15_IP(GC, addr);\
} while (0)
 
*dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL);
@@ -497,13 +497,13 @@ static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, 
uint64_t queue_address,
uint32_t low, high;
 
acquire_queue(kgd, pipe_id, queue_id);
-   act = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE));
+   act = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE);
if (act) {
low = lower_32_bits(queue_address >> 8);
high = upper_32_bits(queue_address >> 8);
 
-   if (low == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE)) &&
-  high == 

[PATCH v5 04/10] drm/amdgpu: Modify GC register access from MMIO to RLCG in file soc15.c

[Peng Ju Zhou]

In SRIOV environment, KMD should access GC registers
with RLCG if GC indirect access flag enabled.

Signed-off-by: Peng Ju Zhou 
---
 drivers/gpu/drm/amd/amdgpu/soc15.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c 
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 080e715799d4..50f6574e1d35 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -632,7 +632,9 @@ void soc15_program_register_sequence(struct amdgpu_device 
*adev,
if (entry->and_mask == 0x) {
tmp = entry->or_mask;
} else {
-   tmp = RREG32(reg);
+   tmp = (entry->hwip == GC_HWIP) ?
+   RREG32_SOC15_IP(GC, reg) : RREG32(reg);
+
tmp &= ~(entry->and_mask);
tmp |= (entry->or_mask & entry->and_mask);
}
@@ -643,7 +645,8 @@ void soc15_program_register_sequence(struct amdgpu_device 
*adev,
reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG))
WREG32_RLC(reg, tmp);
else
-   WREG32(reg, tmp);
+   (entry->hwip == GC_HWIP) ?
+   WREG32_SOC15_IP(GC, reg, tmp) : WREG32(reg, 
tmp);
 
}
 
-- 
2.17.1

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[PATCH v5 01/10] drm/amdgpu: Indirect register access for Navi12 sriov

[Peng Ju Zhou]

This patch series are used for GC/MMHUB(part)/IH_RB_CNTL
indirect access in the SRIOV environment.

There are 4 bits, controlled by host, to control
if GC/MMHUB(part)/IH_RB_CNTL indirect access enabled.
(one bit is master bit controls other 3 bits)

For GC registers, changing all the register access from MMIO to
RLC and use RLC as the default access method in the full access time.

For partial MMHUB registers, changing their access from MMIO to
RLC in the full access time, the remaining registers
keep the original access method.

For IH_RB_CNTL register, changing it's access from MMIO to PSP.

Signed-off-by: Peng Ju Zhou 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h|  1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h|  4 +-
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 78 +--
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c  |  9 ++-
 drivers/gpu/drm/amd/amdgpu/soc15_common.h  | 87 +-
 6 files changed, 97 insertions(+), 84 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 3147c1c935c8..4e0c90e52ab6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1147,6 +1147,7 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
  * Registers read & write functions.
  */
 #define AMDGPU_REGS_NO_KIQ(1<<1)
+#define AMDGPU_REGS_RLC(1<<2)
 
 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), 
AMDGPU_REGS_NO_KIQ)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 7c6c435e5d02..a2392bbe1e21 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -490,7 +490,7 @@ void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
adev->gfx.rlc.funcs &&
adev->gfx.rlc.funcs->is_rlcg_access_range) {
if (adev->gfx.rlc.funcs->is_rlcg_access_range(adev, reg))
-   return adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, v, 0);
+   return adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, v, 0, 
0);
} else {
writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
index 4fc2ce8ce8ab..7a4775ab6804 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
@@ -127,8 +127,8 @@ struct amdgpu_rlc_funcs {
void (*reset)(struct amdgpu_device *adev);
void (*start)(struct amdgpu_device *adev);
void (*update_spm_vmid)(struct amdgpu_device *adev, unsigned vmid);
-   void (*rlcg_wreg)(struct amdgpu_device *adev, u32 offset, u32 v, u32 
flag);
-   u32 (*rlcg_rreg)(struct amdgpu_device *adev, u32 offset, u32 flag);
+   void (*rlcg_wreg)(struct amdgpu_device *adev, u32 offset, u32 v, u32 
acc_flags, u32 hwip);
+   u32 (*rlcg_rreg)(struct amdgpu_device *adev, u32 offset, u32 acc_flags, 
u32 hwip);
bool (*is_rlcg_access_range)(struct amdgpu_device *adev, uint32_t reg);
 };
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 2a3427e5020f..7c5c1ff7d97e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -1427,38 +1427,36 @@ static const struct soc15_reg_golden 
golden_settings_gc_10_1_2[] =
SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x, 0x0080)
 };
 
-static bool gfx_v10_is_rlcg_rw(struct amdgpu_device *adev, u32 offset, 
uint32_t *flag, bool write)
-{
-   /* always programed by rlcg, only for gc */
-   if (offset == SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI) ||
-   offset == SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO) ||
-   offset == SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH) ||
-   offset == SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL) ||
-   offset == SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX) ||
-   offset == SOC15_REG_OFFSET(GC, 0, mmCP_ME_CNTL)) {
-   if (!amdgpu_sriov_reg_indirect_gc(adev))
-   *flag = GFX_RLCG_GC_WRITE_OLD;
-   else
-   *flag = write ? GFX_RLCG_GC_WRITE : GFX_RLCG_GC_READ;
+static bool gfx_v10_get_rlcg_flag(struct amdgpu_device *adev, u32 acc_flags, 
u32 hwip,
+int write, u32 *rlcg_flag)
+{
+   switch (hwip) {
+   case GC_HWIP:
+   if (amdgpu_sriov_reg_indirect_gc(adev)) {
+   *rlcg_flag = write ? GFX_RLCG_GC_WRITE : 
GFX_RLCG_GC_READ;
 
-   return true;
-   }
+   return true;
+   /* only in new version, AMDGPU_REGS_NO_KIQ and AMDGPU_REGS_RLC 
enabled simultaneously */
+   } else if ((acc_flags & AMDGPU_REGS_RLC) && 

[PATCH v5 02/10] drm/amdgpu: Modify GC register access from MMIO to RLCG in file gfx_v10*

[Peng Ju Zhou]

In SRIOV environment, KMD should access GC registers
with RLCG if GC indirect access flag enabled.

Signed-off-by: Peng Ju Zhou 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 32 +-
 1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 7c5c1ff7d97e..952a2f0f2f4e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -5178,10 +5178,10 @@ static void gfx_v10_0_rlc_enable_srm(struct 
amdgpu_device *adev)
uint32_t tmp;
 
/* enable Save Restore Machine */
-   tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
+   tmp = RREG32_SOC15(GC, 0, mmRLC_SRM_CNTL);
tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
-   WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
+   WREG32_SOC15(GC, 0, mmRLC_SRM_CNTL, tmp);
 }
 
 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev)
@@ -7876,12 +7876,12 @@ static int gfx_v10_0_update_gfx_clock_gating(struct 
amdgpu_device *adev,
 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned 
vmid)
 {
u32 reg, data;
-
+   /* not for *_SOC15 */
reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);
if (amdgpu_sriov_is_pp_one_vf(adev))
data = RREG32_NO_KIQ(reg);
else
-   data = RREG32(reg);
+   data = RREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL);
 
data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << 
RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
@@ -8621,16 +8621,16 @@ gfx_v10_0_set_gfx_eop_interrupt_state(struct 
amdgpu_device *adev,
 
switch (state) {
case AMDGPU_IRQ_STATE_DISABLE:
-   cp_int_cntl = RREG32(cp_int_cntl_reg);
+   cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
TIME_STAMP_INT_ENABLE, 0);
-   WREG32(cp_int_cntl_reg, cp_int_cntl);
+   WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
break;
case AMDGPU_IRQ_STATE_ENABLE:
-   cp_int_cntl = RREG32(cp_int_cntl_reg);
+   cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
TIME_STAMP_INT_ENABLE, 1);
-   WREG32(cp_int_cntl_reg, cp_int_cntl);
+   WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
break;
default:
break;
@@ -8674,16 +8674,16 @@ static void 
gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev
 
switch (state) {
case AMDGPU_IRQ_STATE_DISABLE:
-   mec_int_cntl = RREG32(mec_int_cntl_reg);
+   mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
mec_int_cntl = REG_SET_FIELD(mec_int_cntl, 
CP_ME1_PIPE0_INT_CNTL,
 TIME_STAMP_INT_ENABLE, 0);
-   WREG32(mec_int_cntl_reg, mec_int_cntl);
+   WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
break;
case AMDGPU_IRQ_STATE_ENABLE:
-   mec_int_cntl = RREG32(mec_int_cntl_reg);
+   mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
mec_int_cntl = REG_SET_FIELD(mec_int_cntl, 
CP_ME1_PIPE0_INT_CNTL,
 TIME_STAMP_INT_ENABLE, 1);
-   WREG32(mec_int_cntl_reg, mec_int_cntl);
+   WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
break;
default:
break;
@@ -8879,20 +8879,20 @@ static int gfx_v10_0_kiq_set_interrupt_state(struct 
amdgpu_device *adev,
GENERIC2_INT_ENABLE, 0);
WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
 
-   tmp = RREG32(target);
+   tmp = RREG32_SOC15_IP(GC, target);
tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
GENERIC2_INT_ENABLE, 0);
-   WREG32(target, tmp);
+   WREG32_SOC15_IP(GC, target, tmp);
} else {
tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
GENERIC2_INT_ENABLE, 1);
WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
 
-   tmp = RREG32(target);
+   tmp = RREG32_SOC15_IP(GC, target);
tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
GENERIC2_INT_ENABLE, 1);
-

Re: [PATCH 3/3] drm/amdkfd: add invalid pages debug at vram migration

[Felix Kuehling]

Am 2021-05-12 um 1:34 p.m. schrieb Alex Sierra:

> This is for debug purposes only.
> It conditionally generates partial migrations to test mixed
> CPU/GPU memory domain pages in a prange easily.
>
> Signed-off-by: Alex Sierra 
> ---
>  drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 14 ++
>  1 file changed, 14 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c 
> b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
> index e1cc844b2f4e..4c6e340393fb 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
> @@ -403,6 +403,20 @@ svm_migrate_copy_to_vram(struct amdgpu_device *adev, 
> struct svm_range *prange,
>   }
>   }
>  
> +#ifdef DEBUG_FORCE_MIXED_DOMAINS
> + for (i = 0, j = 0; i < npages; i += 4, j++) {
> + if (j & 1)
> + continue;
> + svm_migrate_put_vram_page(adev, dst[i]);
> + migrate->dst[i] = 0;
> + svm_migrate_put_vram_page(adev, dst[i + 1]);
> + migrate->dst[i + 1] = 0;
> + svm_migrate_put_vram_page(adev, dst[i + 2]);
> + migrate->dst[i + 2] = 0;
> + svm_migrate_put_vram_page(adev, dst[i + 3]);
> + migrate->dst[i + 3] = 0;
> + }
> +#endif

You're doing this at the end of svm_migrate_copy_to_vram. If you did it
in the beginning, you could also check that svm_migrate_copy_to_vram
itself is behaving correctly for partial migrations.

Regards,
  Felix


>  out:
>   return r;
>  }
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Re: New uAPI for color management proposal and feedback request

[Werner Sembach]

Am 12.05.21 um 14:06 schrieb Werner Sembach:
> Hello,
>
> In addition to the existing "max bpc", and "Broadcast RGB/output_csc" drm 
> properties I propose 4 new properties:
> "preferred pixel encoding", "active color depth", "active color range", and 
> "active pixel encoding"

As an alternative/additional to the feedback channels: Maybe the kernel should 
not only communicate resolutions and
refresh rates of available modes, but also color capabilities.

I tested with a monitor, for example, that had several 4k@60Hz modes/timings 
offered by the edid, but only some of them
supported YCbCr 420.

>
> Motivation:
>
> Current monitors have a variety pixel encodings available: RGB, YCbCr 4:4:4, 
> YCbCr 4:2:2, YCbCr 4:2:0.
>
> In addition they might be full or limited RGB range and the monitors accept 
> different bit depths.
>
> Currently the kernel driver for AMD and Intel GPUs automatically configure 
> the color settings automatically with little
> to no influence of the user. However there are several real world scenarios 
> where the user might disagree with the
> default chosen by the drivers and wants to set his or her own preference.
>
> Some examples:
>
> 1. While RGB and YCbCr 4:4:4 in theory carry the same amount of color 
> information, some screens might look better on one
> than the other because of bad internal conversion. The driver currently 
> however has a fixed default that is chosen if
> available (RGB for Intel and YCbCr 4:4:4 for AMD). The only way to change 
> this currently is by editing and overloading
> the edid reported by the monitor to the kernel.
>
> 2. RGB and YCbCr 4:4:4 need a higher port clock then YCbCr 4:2:0. Some 
> hardware might report that it supports the higher
> port clock, but because of bad shielding on the PC, the cable, or the monitor 
> the screen cuts out every few seconds when
> RGB or YCbCr 4:4:4 encoding is used, while YCbCr 4:2:0 might just work fine 
> without changing hardware. The drivers
> currently however always default to the "best available" option even if it 
> might be broken.
>
> 3. Some screens natively only supporting 8-bit color, simulate 10-Bit color 
> by rapidly switching between 2 adjacent
> colors. They advertise themselves to the kernel as 10-bit monitors but the 
> user might not like the "fake" 10-bit effect
> and prefer running at the native 8-bit per color.
>
> 4. Some screens are falsely classified as full RGB range wile they actually 
> use limited RGB range. This results in
> washed out colors in dark and bright scenes. A user override can be helpful 
> to manually fix this issue when it occurs.
>
> There already exist several requests, discussion, and patches regarding the 
> thematic:
>
> - https://gitlab.freedesktop.org/drm/amd/-/issues/476
>
> - https://gitlab.freedesktop.org/drm/amd/-/issues/1548
>
> - https://lkml.org/lkml/2021/5/7/695
>
> - https://lkml.org/lkml/2021/5/11/416
>
>
> Current State:
>
> I only know bits about the Intel i915 and AMD amdgpu driver. I don't know how 
> other driver handle color management
>
> - "max bpc", global setting applied by both i915 (only on dp i think?) and 
> amdgpu. Default value is "8". For every
> resolution + frequency combination the highest possible even number between 6 
> and max_bpc is chosen. If the range
> doesn't contain a valid mode the resolution + frequency combination is 
> discarded (but I guess that would be a very
> special edge case, if existent at all, when 6 doesn't work but 10 would 
> work). Intel HDMI code always checks 8, 12, and
> 10 and does not check the max_bpc setting.
>
> - "Broadcast RGB" for i915 and "output_csc" for the old radeon driver (not 
> amdgpu), overwrites the kernel chosen color
> range setting (full or limited). If I recall correctly Intel HDMI code 
> defaults to full unless this property is set,
> Intel dp code tries to probe the monitor to find out what to use. amdgpu has 
> no corresponding setting (I don't know how
> it's decided there).
>
> - RGB pixel encoding can be forced by overloading a Monitors edid with one 
> that tells the kernel that only RGB is
> possible. That doesn't work for YCbCr 4:4:4 however because of the edid 
> specification. Forcing YCbCr 4:2:0 would
> theoretically also be possible this way. amdgpu has a debugfs switch 
> "force_ycbcr_420" which makes the driver default to
> YCbCr 4:2:0 on all monitors if possible.
>
>
> Proposed Solution:
>
> 1. Add a new uAPI property "preferred pixel encoding", as a per port setting.
>
>     - An amdgpu specific implementation was already shared here: 
> https://gitlab.freedesktop.org/drm/amd/-/issues/476
>
>     - It also writes back the actually used encoding if the one requested was 
> not possible, overwriting the requested
> value in the process. I think it would be better to have this feedback 
> channel as a different, read-only property.
>
>     - Make this solution vendor agnostic by putting it in the 
> drm_connector_state struct next do max_bpc
> 

Re: [PATCH] ACPI: PM: s2idle: Add missing LPS0 functions for AMD

[Rafael J. Wysocki]

On Wed, May 5, 2021 at 3:21 PM Alex Deucher  wrote:
>
> These are supposedly not required for AMD platforms,
> but at least some HP laptops seem to require it to
> properly turn off the keyboard backlight.
>
> Based on a patch from Marcin Bachry .
>
> Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1230
> Reviewed-by: Hans de Goede 
> Signed-off-by: Alex Deucher 
> Cc: Marcin Bachry 
> Cc: Mario Limonciello 
> ---
>
> Resend with updated subject.
>
>  drivers/acpi/x86/s2idle.c | 4 
>  1 file changed, 4 insertions(+)
>
> diff --git a/drivers/acpi/x86/s2idle.c b/drivers/acpi/x86/s2idle.c
> index 2b69536cdccb..2d7ddb8a8cb6 100644
> --- a/drivers/acpi/x86/s2idle.c
> +++ b/drivers/acpi/x86/s2idle.c
> @@ -42,6 +42,8 @@ static const struct acpi_device_id lps0_device_ids[] = {
>
>  /* AMD */
>  #define ACPI_LPS0_DSM_UUID_AMD  "e3f32452-febc-43ce-9039-932122d37721"
> +#define ACPI_LPS0_ENTRY_AMD 2
> +#define ACPI_LPS0_EXIT_AMD  3
>  #define ACPI_LPS0_SCREEN_OFF_AMD4
>  #define ACPI_LPS0_SCREEN_ON_AMD 5
>
> @@ -408,6 +410,7 @@ int acpi_s2idle_prepare_late(void)
>
> if (acpi_s2idle_vendor_amd()) {
> acpi_sleep_run_lps0_dsm(ACPI_LPS0_SCREEN_OFF_AMD);
> +   acpi_sleep_run_lps0_dsm(ACPI_LPS0_ENTRY_AMD);
> } else {
> acpi_sleep_run_lps0_dsm(ACPI_LPS0_SCREEN_OFF);
> acpi_sleep_run_lps0_dsm(ACPI_LPS0_ENTRY);
> @@ -422,6 +425,7 @@ void acpi_s2idle_restore_early(void)
> return;
>
> if (acpi_s2idle_vendor_amd()) {
> +   acpi_sleep_run_lps0_dsm(ACPI_LPS0_EXIT_AMD);
> acpi_sleep_run_lps0_dsm(ACPI_LPS0_SCREEN_ON_AMD);
> } else {
> acpi_sleep_run_lps0_dsm(ACPI_LPS0_EXIT);
> --

Applied as 5.14 material, thanks!
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Re: [PATCH 2/3] drm/amdkfd: skip invalid pages during migrations

[Felix Kuehling]

Am 2021-05-12 um 1:34 p.m. schrieb Alex Sierra:
> Invalid pages can be the result of pages that have been migrated
> already due to copy-on-write procedure or pages that were never
> migrated to VRAM in first place. This is not an issue anymore,
> as pranges now support mixed memory domains (CPU/GPU).
>
> Signed-off-by: Alex Sierra 

Reviewed-by: Felix Kuehling 


> ---
>  drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 36 +++-
>  1 file changed, 17 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c 
> b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
> index b298aa8dea4d..e1cc844b2f4e 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
> @@ -419,7 +419,6 @@ svm_migrate_vma_to_vram(struct amdgpu_device *adev, 
> struct svm_range *prange,
>   size_t size;
>   void *buf;
>   int r = -ENOMEM;
> - int retry = 0;
>  
>   memset(, 0, sizeof(migrate));
>   migrate.vma = vma;
> @@ -438,7 +437,6 @@ svm_migrate_vma_to_vram(struct amdgpu_device *adev, 
> struct svm_range *prange,
>   migrate.dst = migrate.src + npages;
>   scratch = (dma_addr_t *)(migrate.dst + npages);
>  
> -retry:
>   r = migrate_vma_setup();
>   if (r) {
>   pr_debug("failed %d prepare migrate svms 0x%p [0x%lx 0x%lx]\n",
> @@ -446,17 +444,9 @@ svm_migrate_vma_to_vram(struct amdgpu_device *adev, 
> struct svm_range *prange,
>   goto out_free;
>   }
>   if (migrate.cpages != npages) {
> - pr_debug("collect 0x%lx/0x%llx pages, retry\n", migrate.cpages,
> + pr_debug("Partial migration. 0x%lx/0x%llx pages can be 
> migrated\n",
> +  migrate.cpages,
>npages);
> - migrate_vma_finalize();
> - if (retry++ >= 3) {
> - r = -ENOMEM;
> - pr_debug("failed %d migrate svms 0x%p [0x%lx 0x%lx]\n",
> -  r, prange->svms, prange->start, prange->last);
> - goto out_free;
> - }
> -
> - goto retry;
>   }
>  
>   if (migrate.cpages) {
> @@ -547,9 +537,8 @@ static void svm_migrate_page_free(struct page *page)
>  static int
>  svm_migrate_copy_to_ram(struct amdgpu_device *adev, struct svm_range *prange,
>   struct migrate_vma *migrate, struct dma_fence **mfence,
> - dma_addr_t *scratch)
> + dma_addr_t *scratch, uint64_t npages)
>  {
> - uint64_t npages = migrate->cpages;
>   struct device *dev = adev->dev;
>   uint64_t *src;
>   dma_addr_t *dst;
> @@ -566,15 +555,23 @@ svm_migrate_copy_to_ram(struct amdgpu_device *adev, 
> struct svm_range *prange,
>   src = (uint64_t *)(scratch + npages);
>   dst = scratch;
>  
> - for (i = 0, j = 0; i < npages; i++, j++, addr += PAGE_SIZE) {
> + for (i = 0, j = 0; i < npages; i++, addr += PAGE_SIZE) {
>   struct page *spage;
>  
>   spage = migrate_pfn_to_page(migrate->src[i]);
>   if (!spage) {
> - pr_debug("failed get spage svms 0x%p [0x%lx 0x%lx]\n",
> + pr_debug("invalid page. Could be in CPU already svms 
> 0x%p [0x%lx 0x%lx]\n",
>prange->svms, prange->start, prange->last);
> - r = -ENOMEM;
> - goto out_oom;
> + if (j) {
> + r = svm_migrate_copy_memory_gart(adev, dst + i 
> - j,
> +  src + i - j, j,
> +  
> FROM_VRAM_TO_RAM,
> +  mfence);
> + if (r)
> + goto out_oom;
> + j = 0;
> + }
> + continue;
>   }
>   src[i] = svm_migrate_addr(adev, spage);
>   if (i > 0 && src[i] != src[i - 1] + PAGE_SIZE) {
> @@ -607,6 +604,7 @@ svm_migrate_copy_to_ram(struct amdgpu_device *adev, 
> struct svm_range *prange,
>  
>   migrate->dst[i] = migrate_pfn(page_to_pfn(dpage));
>   migrate->dst[i] |= MIGRATE_PFN_LOCKED;
> + j++;
>   }
>  
>   r = svm_migrate_copy_memory_gart(adev, dst + i - j, src + i - j, j,
> @@ -664,7 +662,7 @@ svm_migrate_vma_to_ram(struct amdgpu_device *adev, struct 
> svm_range *prange,
>  
>   if (migrate.cpages) {
>   r = svm_migrate_copy_to_ram(adev, prange, , ,
> - scratch);
> + scratch, npages);
>   migrate_vma_pages();
>   svm_migrate_copy_done(adev, mfence);
>   migrate_vma_finalize();
___
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Re: [PATCH 1/3] drm/amdkfd: classify and map mixed svm range pages in GPU

[Felix Kuehling]

A few more comments inline. Sorry I took so long.

Am 2021-05-12 um 1:34 p.m. schrieb Alex Sierra:

> [Why]
> svm ranges can have mixed pages from device or system memory.
> A good example is, after a prange has been allocated in VRAM and a
> copy-on-write is triggered by a fork. This invalidates some pages
> inside the prange. Endding up in mixed pages.
>
> [How]
> By classifying each page inside a prange, based on its type. Device or
> system memory, during dma mapping call. If page corresponds
> to VRAM domain, a flag is set to its dma_addr entry for each GPU.
> Then, at the GPU page table mapping. All group of contiguous pages within
> the same type are mapped with their proper pte flags.
>
> v2:
> Instead of using ttm_res to calculate vram pfns in the svm_range. It is now
> done by setting the vram real physical address into drm_addr array.
> This makes more flexible VRAM management, plus removes the need to have
> a BO reference in the svm_range.
>
> Signed-off-by: Alex Sierra 
> ---
>  drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 71 ++--
>  drivers/gpu/drm/amd/amdkfd/kfd_svm.h |  1 +
>  2 files changed, 46 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c 
> b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
> index 2b4318646a75..0ab10cb24205 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
> @@ -119,11 +119,12 @@ static void svm_range_remove_notifier(struct svm_range 
> *prange)
>  }
>  
>  static int
> -svm_range_dma_map_dev(struct device *dev, dma_addr_t **dma_addr,
> +svm_range_dma_map_dev(struct amdgpu_device *adev, dma_addr_t **dma_addr,
> unsigned long *hmm_pfns, uint64_t npages)
>  {
>   enum dma_data_direction dir = DMA_BIDIRECTIONAL;
>   dma_addr_t *addr = *dma_addr;
> + struct device *dev = adev->dev;
>   struct page *page;
>   int i, r;
>  
> @@ -141,6 +142,14 @@ svm_range_dma_map_dev(struct device *dev, dma_addr_t 
> **dma_addr,
>   dma_unmap_page(dev, addr[i], PAGE_SIZE, dir);
>  
>   page = hmm_pfn_to_page(hmm_pfns[i]);
> + if (is_zone_device_page(page)) {
> + addr[i] = (hmm_pfns[i] << PAGE_SHIFT) +
> +adev->vm_manager.vram_base_offset -
> +adev->kfd.dev->pgmap.range.start;
> + addr[i] |= SVM_RANGE_VRAM_DOMAIN;
> + pr_debug("vram address detected: 0x%llx\n", addr[i]);
> + continue;
> + }
>   addr[i] = dma_map_page(dev, page, 0, PAGE_SIZE, dir);
>   r = dma_mapping_error(dev, addr[i]);
>   if (r) {
> @@ -175,7 +184,7 @@ svm_range_dma_map(struct svm_range *prange, unsigned long 
> *bitmap,
>   }
>   adev = (struct amdgpu_device *)pdd->dev->kgd;
>  
> - r = svm_range_dma_map_dev(adev->dev, >dma_addr[gpuidx],
> + r = svm_range_dma_map_dev(adev, >dma_addr[gpuidx],
> hmm_pfns, prange->npages);
>   if (r)
>   break;
> @@ -1003,21 +1012,22 @@ svm_range_split_by_granularity(struct kfd_process *p, 
> struct mm_struct *mm,
>  }
>  
>  static uint64_t
> -svm_range_get_pte_flags(struct amdgpu_device *adev, struct svm_range *prange)
> +svm_range_get_pte_flags(struct amdgpu_device *adev, struct svm_range *prange,
> + int domain)
>  {
>   struct amdgpu_device *bo_adev;
>   uint32_t flags = prange->flags;
>   uint32_t mapping_flags = 0;
>   uint64_t pte_flags;
> - bool snoop = !prange->ttm_res;
> + bool snoop = !!domain;

This is a bit obscure and it assumes that SVM_RANGE_VRAM_DOMAIN is 0.
And it's not actually correct. Make this

bool snoop = (domain != SVM_RANGE_VRAM_DOMAIN);


>   bool coherent = flags & KFD_IOCTL_SVM_FLAG_COHERENT;
>  
> - if (prange->svm_bo && prange->ttm_res)
> + if (domain == SVM_RANGE_VRAM_DOMAIN)
>   bo_adev = amdgpu_ttm_adev(prange->svm_bo->bo->tbo.bdev);
>  
>   switch (adev->asic_type) {
>   case CHIP_ARCTURUS:
> - if (prange->svm_bo && prange->ttm_res) {
> + if (domain == SVM_RANGE_VRAM_DOMAIN) {
>   if (bo_adev == adev) {
>   mapping_flags |= coherent ?
>   AMDGPU_VM_MTYPE_CC : AMDGPU_VM_MTYPE_RW;
> @@ -1032,7 +1042,7 @@ svm_range_get_pte_flags(struct amdgpu_device *adev, 
> struct svm_range *prange)
>   }
>   break;
>   case CHIP_ALDEBARAN:
> - if (prange->svm_bo && prange->ttm_res) {
> + if (domain == SVM_RANGE_VRAM_DOMAIN) {
>   if (bo_adev == adev) {
>   mapping_flags |= coherent ?
>   AMDGPU_VM_MTYPE_CC : AMDGPU_VM_MTYPE_RW;
> @@ -1061,14 +1071,14 @@ 

Re: [5.13-rc1][bug] often hangs for no reason

[Borislav Petkov]

On Mon, May 17, 2021 at 03:27:23AM +0500, Mikhail Gavrilov wrote:
> Hi folks.
> 5.13-rc1 after 5.13-rc0 is a disaster because it hangs and hangs again
> after reboot.
> All hang's have in common is that they all happens in
> smp_call_function_many_cond function (I compared all trace [1], [2],
> [3], [4], [5])
> I do not know if this is a known problem or not, so I'm reporting here.

Looks like some splat, lockdep probably, in amdgpu when it gets loaded.
Maybe locking's botched although the beginning of the splats is missing
for whatever reason...

Adding them to Cc in case they have a better idea.

> Full logs here:
> [1] https://pastebin.com/u7SkKGDT
> [2] https://pastebin.com/fNae4dSL
> [3] https://pastebin.com/jEDMjQDy
> [4] https://pastebin.com/vEMhWGgE
> [5] https://pastebin.com/fvWx5ctR
> 

-- 
Regards/Gruss,
Boris.

https://people.kernel.org/tglx/notes-about-netiquette
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[PATCH] drm/amdgpu: fix PM reference leak in amdgpu_debugfs_gfxoff_rea()

[Yu Kuai]

pm_runtime_get_sync will increment pm usage counter even it failed.
Forgetting to putting operation will result in reference leak here.
Fix it by replacing it with pm_runtime_resume_and_get to keep usage
counter balanced.

Reported-by: Hulk Robot 
Signed-off-by: Yu Kuai 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index bcaf271b39bf..eb7f9d20dad7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -1058,7 +1058,7 @@ static ssize_t amdgpu_debugfs_gfxoff_read(struct file *f, 
char __user *buf,
if (size & 0x3 || *pos & 0x3)
return -EINVAL;
 
-   r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
+   r = pm_runtime_resume_and_get(adev_to_drm(adev)->dev);
if (r < 0)
return r;
 
-- 
2.25.4

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Re: [PATCH] drm/amdgpu: Add vbios info ioctl interface

[Christian König]

I'm not very familiar with the technical background why we have the 
fields here once more.


But of hand we should at least remove everything which is also available 
from the PCI information.


E.g. dev_id, rev_id, sub_dev_id, sub_ved_id.

Regards,
Christian.

Am 17.05.21 um 14:17 schrieb Gu, JiaWei (Will):

[AMD Official Use Only - Internal Distribution Only]

Hi all,

Thanks Christian's suggestion.
I reverted the previous patches and squash them into this single one.

As this patch shows, the current uapi change looks like this:

+struct drm_amdgpu_info_vbios {
+   __u8 name[64];
+   __u32 dbdf;
+   __u8 vbios_pn[64];
+   __u32 version;
+   __u8 vbios_ver_str[32];
+   __u8 date[32];
+   __u64 serial;
+   __u32 dev_id;
+   __u32 rev_id;
+   __u32 sub_dev_id;
+   __u32 sub_ved_id;
+};

As we know there's some redundant info in this struct.
Please feel free to give any comments or suggestion about what it should & 
shouldn't include.

Best regards,
Jiawei

-Original Message-
From: Jiawei Gu 
Sent: Monday, May 17, 2021 8:08 PM
To: amd-gfx@lists.freedesktop.org; Koenig, Christian ; Nieto, 
David M ; mar...@gmail.com; Deucher, Alexander 

Cc: Deng, Emily ; Gu, JiaWei (Will) 
Subject: [PATCH] drm/amdgpu: Add vbios info ioctl interface

Add AMDGPU_INFO_VBIOS_INFO subquery id for detailed vbios info.

Provides a way for the user application to get the VBIOS information without 
having to parse the binary.
It is useful for the user to be able to display in a simple way the VBIOS 
version in their system if they happen to encounter an issue.

V2:
Use numeric serial.
Parse and expose vbios version string.

Signed-off-by: Jiawei Gu 
Acked-by: Christian König 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c|  21 +++
  drivers/gpu/drm/amd/amdgpu/atom.c  | 174 +
  drivers/gpu/drm/amd/amdgpu/atom.h  |  12 ++
  drivers/gpu/drm/amd/include/atomfirmware.h |   5 +
  include/uapi/drm/amdgpu_drm.h  |  16 ++
  5 files changed, 228 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 8d12e474745a..30e4fed3de22 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -861,6 +861,27 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, 
struct drm_file *filp)
min((size_t)size, 
(size_t)(bios_size - bios_offset)))
? -EFAULT : 0;
}
+   case AMDGPU_INFO_VBIOS_INFO: {
+   struct drm_amdgpu_info_vbios vbios_info = {};
+   struct atom_context *atom_context;
+
+   atom_context = adev->mode_info.atom_context;
+   memcpy(vbios_info.name, atom_context->name, 
sizeof(atom_context->name));
+   vbios_info.dbdf = PCI_DEVID(adev->pdev->bus->number, 
adev->pdev->devfn);
+   memcpy(vbios_info.vbios_pn, atom_context->vbios_pn, 
sizeof(atom_context->vbios_pn));
+   vbios_info.version = atom_context->version;
+   memcpy(vbios_info.vbios_ver_str, 
atom_context->vbios_ver_str,
+   
sizeof(atom_context->vbios_ver_str));
+   memcpy(vbios_info.date, atom_context->date, 
sizeof(atom_context->date));
+   vbios_info.serial = adev->unique_id;
+   vbios_info.dev_id = adev->pdev->device;
+   vbios_info.rev_id = adev->pdev->revision;
+   vbios_info.sub_dev_id = atom_context->sub_dev_id;
+   vbios_info.sub_ved_id = atom_context->sub_ved_id;
+
+   return copy_to_user(out, _info,
+   min((size_t)size, 
sizeof(vbios_info))) ? -EFAULT : 0;
+   }
default:
DRM_DEBUG_KMS("Invalid request %d\n",
info->vbios_info.type);
diff --git a/drivers/gpu/drm/amd/amdgpu/atom.c 
b/drivers/gpu/drm/amd/amdgpu/atom.c
index 3dcb8b32f48b..542b2c2414e4 100644
--- a/drivers/gpu/drm/amd/amdgpu/atom.c
+++ b/drivers/gpu/drm/amd/amdgpu/atom.c
@@ -31,6 +31,7 @@
  
  #define ATOM_DEBUG
  
+#include "atomfirmware.h"

  #include "atom.h"
  #include "atom-names.h"
  #include "atom-bits.h"
@@ -1299,12 +1300,168 @@ static void atom_index_iio(struct atom_context *ctx, 
int base)
}
  }
  
+static void atom_get_vbios_name(struct atom_context *ctx) {

+   unsigned char *p_rom;
+   unsigned char str_num;
+   unsigned short off_to_vbios_str;
+   unsigned char *c_ptr;
+   int name_size;
+   int i;
+
+   const char *na = "--N/A--";
+   char *back;
+
+   p_rom = ctx->bios;
+
+   str_num = *(p_rom + OFFSET_TO_GET_ATOMBIOS_NUMBER_OF_STRINGS);
+   if (str_num != 0) 

RE: [PATCH] drm/amdgpu: Add vbios info ioctl interface

[Gu, JiaWei (Will)]

[AMD Official Use Only - Internal Distribution Only]

Hi all,

Thanks Christian's suggestion.
I reverted the previous patches and squash them into this single one.

As this patch shows, the current uapi change looks like this:

+struct drm_amdgpu_info_vbios {
+   __u8 name[64];
+   __u32 dbdf;
+   __u8 vbios_pn[64];
+   __u32 version;
+   __u8 vbios_ver_str[32];
+   __u8 date[32];
+   __u64 serial;
+   __u32 dev_id;
+   __u32 rev_id;
+   __u32 sub_dev_id;
+   __u32 sub_ved_id;
+};

As we know there's some redundant info in this struct.
Please feel free to give any comments or suggestion about what it should & 
shouldn't include.

Best regards,
Jiawei

-Original Message-
From: Jiawei Gu  
Sent: Monday, May 17, 2021 8:08 PM
To: amd-gfx@lists.freedesktop.org; Koenig, Christian 
; Nieto, David M ; 
mar...@gmail.com; Deucher, Alexander 
Cc: Deng, Emily ; Gu, JiaWei (Will) 
Subject: [PATCH] drm/amdgpu: Add vbios info ioctl interface

Add AMDGPU_INFO_VBIOS_INFO subquery id for detailed vbios info.

Provides a way for the user application to get the VBIOS information without 
having to parse the binary.
It is useful for the user to be able to display in a simple way the VBIOS 
version in their system if they happen to encounter an issue.

V2:
Use numeric serial.
Parse and expose vbios version string.

Signed-off-by: Jiawei Gu 
Acked-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c|  21 +++
 drivers/gpu/drm/amd/amdgpu/atom.c  | 174 +
 drivers/gpu/drm/amd/amdgpu/atom.h  |  12 ++
 drivers/gpu/drm/amd/include/atomfirmware.h |   5 +
 include/uapi/drm/amdgpu_drm.h  |  16 ++
 5 files changed, 228 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 8d12e474745a..30e4fed3de22 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -861,6 +861,27 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, 
struct drm_file *filp)
min((size_t)size, 
(size_t)(bios_size - bios_offset)))
? -EFAULT : 0;
}
+   case AMDGPU_INFO_VBIOS_INFO: {
+   struct drm_amdgpu_info_vbios vbios_info = {};
+   struct atom_context *atom_context;
+
+   atom_context = adev->mode_info.atom_context;
+   memcpy(vbios_info.name, atom_context->name, 
sizeof(atom_context->name));
+   vbios_info.dbdf = PCI_DEVID(adev->pdev->bus->number, 
adev->pdev->devfn);
+   memcpy(vbios_info.vbios_pn, atom_context->vbios_pn, 
sizeof(atom_context->vbios_pn));
+   vbios_info.version = atom_context->version;
+   memcpy(vbios_info.vbios_ver_str, 
atom_context->vbios_ver_str,
+   
sizeof(atom_context->vbios_ver_str));
+   memcpy(vbios_info.date, atom_context->date, 
sizeof(atom_context->date));
+   vbios_info.serial = adev->unique_id;
+   vbios_info.dev_id = adev->pdev->device;
+   vbios_info.rev_id = adev->pdev->revision;
+   vbios_info.sub_dev_id = atom_context->sub_dev_id;
+   vbios_info.sub_ved_id = atom_context->sub_ved_id;
+
+   return copy_to_user(out, _info,
+   min((size_t)size, 
sizeof(vbios_info))) ? -EFAULT : 0;
+   }
default:
DRM_DEBUG_KMS("Invalid request %d\n",
info->vbios_info.type);
diff --git a/drivers/gpu/drm/amd/amdgpu/atom.c 
b/drivers/gpu/drm/amd/amdgpu/atom.c
index 3dcb8b32f48b..542b2c2414e4 100644
--- a/drivers/gpu/drm/amd/amdgpu/atom.c
+++ b/drivers/gpu/drm/amd/amdgpu/atom.c
@@ -31,6 +31,7 @@
 
 #define ATOM_DEBUG
 
+#include "atomfirmware.h"
 #include "atom.h"
 #include "atom-names.h"
 #include "atom-bits.h"
@@ -1299,12 +1300,168 @@ static void atom_index_iio(struct atom_context *ctx, 
int base)
}
 }
 
+static void atom_get_vbios_name(struct atom_context *ctx) {
+   unsigned char *p_rom;
+   unsigned char str_num;
+   unsigned short off_to_vbios_str;
+   unsigned char *c_ptr;
+   int name_size;
+   int i;
+
+   const char *na = "--N/A--";
+   char *back;
+
+   p_rom = ctx->bios;
+
+   str_num = *(p_rom + OFFSET_TO_GET_ATOMBIOS_NUMBER_OF_STRINGS);
+   if (str_num != 0) {
+   off_to_vbios_str =
+   *(unsigned short *)(p_rom + 
OFFSET_TO_GET_ATOMBIOS_STRING_START);
+
+   c_ptr = (unsigned char *)(p_rom + off_to_vbios_str);
+   } else {
+   /* do not know where to find name */
+   memcpy(ctx->name, na, 7);
+   

[PATCH] drm/amdgpu: Add vbios info ioctl interface

[Jiawei Gu]

Add AMDGPU_INFO_VBIOS_INFO subquery id for detailed vbios info.

Provides a way for the user application to get the VBIOS
information without having to parse the binary.
It is useful for the user to be able to display in a simple way the VBIOS
version in their system if they happen to encounter an issue.

V2:
Use numeric serial.
Parse and expose vbios version string.

Signed-off-by: Jiawei Gu 
Acked-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c|  21 +++
 drivers/gpu/drm/amd/amdgpu/atom.c  | 174 +
 drivers/gpu/drm/amd/amdgpu/atom.h  |  12 ++
 drivers/gpu/drm/amd/include/atomfirmware.h |   5 +
 include/uapi/drm/amdgpu_drm.h  |  16 ++
 5 files changed, 228 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 8d12e474745a..30e4fed3de22 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -861,6 +861,27 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, 
struct drm_file *filp)
min((size_t)size, 
(size_t)(bios_size - bios_offset)))
? -EFAULT : 0;
}
+   case AMDGPU_INFO_VBIOS_INFO: {
+   struct drm_amdgpu_info_vbios vbios_info = {};
+   struct atom_context *atom_context;
+
+   atom_context = adev->mode_info.atom_context;
+   memcpy(vbios_info.name, atom_context->name, 
sizeof(atom_context->name));
+   vbios_info.dbdf = PCI_DEVID(adev->pdev->bus->number, 
adev->pdev->devfn);
+   memcpy(vbios_info.vbios_pn, atom_context->vbios_pn, 
sizeof(atom_context->vbios_pn));
+   vbios_info.version = atom_context->version;
+   memcpy(vbios_info.vbios_ver_str, 
atom_context->vbios_ver_str,
+   
sizeof(atom_context->vbios_ver_str));
+   memcpy(vbios_info.date, atom_context->date, 
sizeof(atom_context->date));
+   vbios_info.serial = adev->unique_id;
+   vbios_info.dev_id = adev->pdev->device;
+   vbios_info.rev_id = adev->pdev->revision;
+   vbios_info.sub_dev_id = atom_context->sub_dev_id;
+   vbios_info.sub_ved_id = atom_context->sub_ved_id;
+
+   return copy_to_user(out, _info,
+   min((size_t)size, 
sizeof(vbios_info))) ? -EFAULT : 0;
+   }
default:
DRM_DEBUG_KMS("Invalid request %d\n",
info->vbios_info.type);
diff --git a/drivers/gpu/drm/amd/amdgpu/atom.c 
b/drivers/gpu/drm/amd/amdgpu/atom.c
index 3dcb8b32f48b..542b2c2414e4 100644
--- a/drivers/gpu/drm/amd/amdgpu/atom.c
+++ b/drivers/gpu/drm/amd/amdgpu/atom.c
@@ -31,6 +31,7 @@
 
 #define ATOM_DEBUG
 
+#include "atomfirmware.h"
 #include "atom.h"
 #include "atom-names.h"
 #include "atom-bits.h"
@@ -1299,12 +1300,168 @@ static void atom_index_iio(struct atom_context *ctx, 
int base)
}
 }
 
+static void atom_get_vbios_name(struct atom_context *ctx)
+{
+   unsigned char *p_rom;
+   unsigned char str_num;
+   unsigned short off_to_vbios_str;
+   unsigned char *c_ptr;
+   int name_size;
+   int i;
+
+   const char *na = "--N/A--";
+   char *back;
+
+   p_rom = ctx->bios;
+
+   str_num = *(p_rom + OFFSET_TO_GET_ATOMBIOS_NUMBER_OF_STRINGS);
+   if (str_num != 0) {
+   off_to_vbios_str =
+   *(unsigned short *)(p_rom + 
OFFSET_TO_GET_ATOMBIOS_STRING_START);
+
+   c_ptr = (unsigned char *)(p_rom + off_to_vbios_str);
+   } else {
+   /* do not know where to find name */
+   memcpy(ctx->name, na, 7);
+   ctx->name[7] = 0;
+   return;
+   }
+
+   /*
+* skip the atombios strings, usually 4
+* 1st is P/N, 2nd is ASIC, 3rd is PCI type, 4th is Memory type
+*/
+   for (i = 0; i < str_num; i++) {
+   while (*c_ptr != 0)
+   c_ptr++;
+   c_ptr++;
+   }
+
+   /* skip the following 2 chars: 0x0D 0x0A */
+   c_ptr += 2;
+
+   name_size = strnlen(c_ptr, STRLEN_LONG - 1);
+   memcpy(ctx->name, c_ptr, name_size);
+   back = ctx->name + name_size;
+   while ((*--back) == ' ')
+   ;
+   *(back + 1) = '\0';
+}
+
+static void atom_get_vbios_date(struct atom_context *ctx)
+{
+   unsigned char *p_rom;
+   unsigned char *date_in_rom;
+
+   p_rom = ctx->bios;
+
+   date_in_rom = p_rom + OFFSET_TO_VBIOS_DATE;
+
+   ctx->date[0] = '2';
+   ctx->date[1] = '0';
+   ctx->date[2] = date_in_rom[6];
+   ctx->date[3] = date_in_rom[7];
+   

Re: [PATCH] drm/amdgpu: Revert vbios info ioctl patches

[Christian König]

Am 17.05.21 um 13:38 schrieb Jiawei Gu:

Revert "drm/amdgpu: Add vbios info ioctl interface"
Revert "drm/amdgpu: Field type update in drm_amdgpu_info_vbios"

This reverts commits:
d75a789ace808b738081322f27dcb1abe5cc9aa9.
50c70d479041e2d8a6a22b2ee4d76cfea1327576.

Reason for revert: Step back to update uapi in a single patch

Signed-off-by: Jiawei Gu 


Reviewed-by: Christian König 


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c|  19 ---
  drivers/gpu/drm/amd/amdgpu/atom.c  | 158 -
  drivers/gpu/drm/amd/amdgpu/atom.h  |  11 --
  drivers/gpu/drm/amd/include/atomfirmware.h |   4 -
  include/uapi/drm/amdgpu_drm.h  |  15 --
  5 files changed, 207 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index e1008a79b441..8d12e474745a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -861,25 +861,6 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, 
struct drm_file *filp)
min((size_t)size, 
(size_t)(bios_size - bios_offset)))
? -EFAULT : 0;
}
-   case AMDGPU_INFO_VBIOS_INFO: {
-   struct drm_amdgpu_info_vbios vbios_info = {};
-   struct atom_context *atom_context;
-
-   atom_context = adev->mode_info.atom_context;
-   memcpy(vbios_info.name, atom_context->name, 
sizeof(atom_context->name));
-   vbios_info.dbdf = PCI_DEVID(adev->pdev->bus->number, 
adev->pdev->devfn);
-   memcpy(vbios_info.vbios_pn, atom_context->vbios_pn, 
sizeof(atom_context->vbios_pn));
-   vbios_info.version = atom_context->version;
-   memcpy(vbios_info.date, atom_context->date, 
sizeof(atom_context->date));
-   vbios_info.serial = adev->unique_id;
-   vbios_info.dev_id = adev->pdev->device;
-   vbios_info.rev_id = adev->pdev->revision;
-   vbios_info.sub_dev_id = atom_context->sub_dev_id;
-   vbios_info.sub_ved_id = atom_context->sub_ved_id;
-
-   return copy_to_user(out, _info,
-   min((size_t)size, 
sizeof(vbios_info))) ? -EFAULT : 0;
-   }
default:
DRM_DEBUG_KMS("Invalid request %d\n",
info->vbios_info.type);
diff --git a/drivers/gpu/drm/amd/amdgpu/atom.c 
b/drivers/gpu/drm/amd/amdgpu/atom.c
index 0e2f0ea13b40..3dcb8b32f48b 100644
--- a/drivers/gpu/drm/amd/amdgpu/atom.c
+++ b/drivers/gpu/drm/amd/amdgpu/atom.c
@@ -31,7 +31,6 @@
  
  #define ATOM_DEBUG
  
-#include "atomfirmware.h"

  #include "atom.h"
  #include "atom-names.h"
  #include "atom-bits.h"
@@ -1300,153 +1299,12 @@ static void atom_index_iio(struct atom_context *ctx, 
int base)
}
  }
  
-static void atom_get_vbios_name(struct atom_context *ctx)

-{
-   unsigned char *p_rom;
-   unsigned char str_num;
-   unsigned short off_to_vbios_str;
-   unsigned char *c_ptr;
-   int name_size;
-   int i;
-
-   const char *na = "--N/A--";
-   char *back;
-
-   p_rom = ctx->bios;
-
-   str_num = *(p_rom + OFFSET_TO_GET_ATOMBIOS_NUMBER_OF_STRINGS);
-   if (str_num != 0) {
-   off_to_vbios_str =
-   *(unsigned short *)(p_rom + 
OFFSET_TO_GET_ATOMBIOS_STRING_START);
-
-   c_ptr = (unsigned char *)(p_rom + off_to_vbios_str);
-   } else {
-   /* do not know where to find name */
-   memcpy(ctx->name, na, 7);
-   ctx->name[7] = 0;
-   return;
-   }
-
-   /*
-* skip the atombios strings, usually 4
-* 1st is P/N, 2nd is ASIC, 3rd is PCI type, 4th is Memory type
-*/
-   for (i = 0; i < str_num; i++) {
-   while (*c_ptr != 0)
-   c_ptr++;
-   c_ptr++;
-   }
-
-   /* skip the following 2 chars: 0x0D 0x0A */
-   c_ptr += 2;
-
-   name_size = strnlen(c_ptr, STRLEN_LONG - 1);
-   memcpy(ctx->name, c_ptr, name_size);
-   back = ctx->name + name_size;
-   while ((*--back) == ' ')
-   ;
-   *(back + 1) = '\0';
-}
-
-static void atom_get_vbios_date(struct atom_context *ctx)
-{
-   unsigned char *p_rom;
-   unsigned char *date_in_rom;
-
-   p_rom = ctx->bios;
-
-   date_in_rom = p_rom + OFFSET_TO_VBIOS_DATE;
-
-   ctx->date[0] = '2';
-   ctx->date[1] = '0';
-   ctx->date[2] = date_in_rom[6];
-   ctx->date[3] = date_in_rom[7];
-   ctx->date[4] = '/';
-   ctx->date[5] = date_in_rom[0];
-   ctx->date[6] = date_in_rom[1];
-   ctx->date[7] = '/';
-   ctx->date[8] = date_in_rom[3];
-   ctx->date[9] = 

[PATCH] drm/amdgpu: Revert vbios info ioctl patches

[Jiawei Gu]

Revert "drm/amdgpu: Add vbios info ioctl interface"
Revert "drm/amdgpu: Field type update in drm_amdgpu_info_vbios"

This reverts commits:
d75a789ace808b738081322f27dcb1abe5cc9aa9.
50c70d479041e2d8a6a22b2ee4d76cfea1327576.

Reason for revert: Step back to update uapi in a single patch

Signed-off-by: Jiawei Gu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c|  19 ---
 drivers/gpu/drm/amd/amdgpu/atom.c  | 158 -
 drivers/gpu/drm/amd/amdgpu/atom.h  |  11 --
 drivers/gpu/drm/amd/include/atomfirmware.h |   4 -
 include/uapi/drm/amdgpu_drm.h  |  15 --
 5 files changed, 207 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index e1008a79b441..8d12e474745a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -861,25 +861,6 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, 
struct drm_file *filp)
min((size_t)size, 
(size_t)(bios_size - bios_offset)))
? -EFAULT : 0;
}
-   case AMDGPU_INFO_VBIOS_INFO: {
-   struct drm_amdgpu_info_vbios vbios_info = {};
-   struct atom_context *atom_context;
-
-   atom_context = adev->mode_info.atom_context;
-   memcpy(vbios_info.name, atom_context->name, 
sizeof(atom_context->name));
-   vbios_info.dbdf = PCI_DEVID(adev->pdev->bus->number, 
adev->pdev->devfn);
-   memcpy(vbios_info.vbios_pn, atom_context->vbios_pn, 
sizeof(atom_context->vbios_pn));
-   vbios_info.version = atom_context->version;
-   memcpy(vbios_info.date, atom_context->date, 
sizeof(atom_context->date));
-   vbios_info.serial = adev->unique_id;
-   vbios_info.dev_id = adev->pdev->device;
-   vbios_info.rev_id = adev->pdev->revision;
-   vbios_info.sub_dev_id = atom_context->sub_dev_id;
-   vbios_info.sub_ved_id = atom_context->sub_ved_id;
-
-   return copy_to_user(out, _info,
-   min((size_t)size, 
sizeof(vbios_info))) ? -EFAULT : 0;
-   }
default:
DRM_DEBUG_KMS("Invalid request %d\n",
info->vbios_info.type);
diff --git a/drivers/gpu/drm/amd/amdgpu/atom.c 
b/drivers/gpu/drm/amd/amdgpu/atom.c
index 0e2f0ea13b40..3dcb8b32f48b 100644
--- a/drivers/gpu/drm/amd/amdgpu/atom.c
+++ b/drivers/gpu/drm/amd/amdgpu/atom.c
@@ -31,7 +31,6 @@
 
 #define ATOM_DEBUG
 
-#include "atomfirmware.h"
 #include "atom.h"
 #include "atom-names.h"
 #include "atom-bits.h"
@@ -1300,153 +1299,12 @@ static void atom_index_iio(struct atom_context *ctx, 
int base)
}
 }
 
-static void atom_get_vbios_name(struct atom_context *ctx)
-{
-   unsigned char *p_rom;
-   unsigned char str_num;
-   unsigned short off_to_vbios_str;
-   unsigned char *c_ptr;
-   int name_size;
-   int i;
-
-   const char *na = "--N/A--";
-   char *back;
-
-   p_rom = ctx->bios;
-
-   str_num = *(p_rom + OFFSET_TO_GET_ATOMBIOS_NUMBER_OF_STRINGS);
-   if (str_num != 0) {
-   off_to_vbios_str =
-   *(unsigned short *)(p_rom + 
OFFSET_TO_GET_ATOMBIOS_STRING_START);
-
-   c_ptr = (unsigned char *)(p_rom + off_to_vbios_str);
-   } else {
-   /* do not know where to find name */
-   memcpy(ctx->name, na, 7);
-   ctx->name[7] = 0;
-   return;
-   }
-
-   /*
-* skip the atombios strings, usually 4
-* 1st is P/N, 2nd is ASIC, 3rd is PCI type, 4th is Memory type
-*/
-   for (i = 0; i < str_num; i++) {
-   while (*c_ptr != 0)
-   c_ptr++;
-   c_ptr++;
-   }
-
-   /* skip the following 2 chars: 0x0D 0x0A */
-   c_ptr += 2;
-
-   name_size = strnlen(c_ptr, STRLEN_LONG - 1);
-   memcpy(ctx->name, c_ptr, name_size);
-   back = ctx->name + name_size;
-   while ((*--back) == ' ')
-   ;
-   *(back + 1) = '\0';
-}
-
-static void atom_get_vbios_date(struct atom_context *ctx)
-{
-   unsigned char *p_rom;
-   unsigned char *date_in_rom;
-
-   p_rom = ctx->bios;
-
-   date_in_rom = p_rom + OFFSET_TO_VBIOS_DATE;
-
-   ctx->date[0] = '2';
-   ctx->date[1] = '0';
-   ctx->date[2] = date_in_rom[6];
-   ctx->date[3] = date_in_rom[7];
-   ctx->date[4] = '/';
-   ctx->date[5] = date_in_rom[0];
-   ctx->date[6] = date_in_rom[1];
-   ctx->date[7] = '/';
-   ctx->date[8] = date_in_rom[3];
-   ctx->date[9] = date_in_rom[4];
-   ctx->date[10] = ' ';
-   ctx->date[11] = date_in_rom[9];
-   

Re: [PATCH] drm/amd/amdgpu: fix a potential deadlock in gpu reset

[Christian König]

Am 17.05.21 um 12:52 schrieb Lang Yu:

When amdgpu_ib_ring_tests failed, the reset logic called
amdgpu_device_ip_suspend twice, then deadlock occurred.

Deadlock log:
[  805.655192] amdgpu :04:00.0: amdgpu: ib ring test failed (-110).
[  806.011571] [drm] Register(0) [mmUVD_POWER_STATUS] failed to reach value 
0x0001 != 0x0002
[  806.280139] [drm] Register(0) [mmUVD_POWER_STATUS] failed to reach value 
0x0001 != 0x0002
[  806.290952] [drm] free PSP TMR buffer

[  806.319406] 
[  806.320315] WARNING: possible recursive locking detected
[  806.321225] 5.11.0-custom #1 Tainted: GW  OEL
[  806.322135] 
[  806.323043] cat/2593 is trying to acquire lock:
[  806.323825] 888136b1cdc8 (>dm.dc_lock){+.+.}-{3:3}, at: 
dm_suspend+0xb8/0x1d0 [amdgpu]
[  806.325668]
but task is already holding lock:
[  806.326664] 888136b1cdc8 (>dm.dc_lock){+.+.}-{3:3}, at: 
dm_suspend+0xb8/0x1d0 [amdgpu]
[  806.328430]
other info that might help us debug this:
[  806.329539]  Possible unsafe locking scenario:

[  806.330549]CPU0
[  806.330983]
[  806.331416]   lock(>dm.dc_lock);
[  806.332086]   lock(>dm.dc_lock);
[  806.332738]
 *** DEADLOCK ***

[  806.333747]  May be due to missing lock nesting notation

[  806.334899] 3 locks held by cat/2593:
[  806.335537]  #0: 888100d3f1b8 (>mutex){+.+.}-{3:3}, at: 
simple_attr_read+0x4e/0x110
[  806.337009]  #1: 888136b1fd78 (>reset_sem){}-{3:3}, at: 
amdgpu_device_lock_adev+0x42/0x94 [amdgpu]
[  806.339018]  #2: 888136b1cdc8 (>dm.dc_lock){+.+.}-{3:3}, at: 
dm_suspend+0xb8/0x1d0 [amdgpu]
[  806.340869]
stack backtrace:
[  806.341621] CPU: 6 PID: 2593 Comm: cat Tainted: GW  OEL
5.11.0-custom #1
[  806.342921] Hardware name: AMD Celadon-CZN/Celadon-CZN, BIOS 
WLD0C23N_Weekly_20_12_2 12/23/2020
[  806.344413] Call Trace:
[  806.344849]  dump_stack+0x93/0xbd
[  806.345435]  __lock_acquire.cold+0x18a/0x2cf
[  806.346179]  lock_acquire+0xca/0x390
[  806.346807]  ? dm_suspend+0xb8/0x1d0 [amdgpu]
[  806.347813]  __mutex_lock+0x9b/0x930
[  806.348454]  ? dm_suspend+0xb8/0x1d0 [amdgpu]
[  806.349434]  ? amdgpu_device_indirect_rreg+0x58/0x70 [amdgpu]
[  806.350581]  ? _raw_spin_unlock_irqrestore+0x47/0x50
[  806.351437]  ? dm_suspend+0xb8/0x1d0 [amdgpu]
[  806.352437]  ? rcu_read_lock_sched_held+0x4f/0x80
[  806.353252]  ? rcu_read_lock_sched_held+0x4f/0x80
[  806.354064]  mutex_lock_nested+0x1b/0x20
[  806.354747]  ? mutex_lock_nested+0x1b/0x20
[  806.355457]  dm_suspend+0xb8/0x1d0 [amdgpu]
[  806.356427]  ? soc15_common_set_clockgating_state+0x17d/0x19 [amdgpu]
[  806.357736]  amdgpu_device_ip_suspend_phase1+0x78/0xd0 [amdgpu]
[  806.360394]  amdgpu_device_ip_suspend+0x21/0x70 [amdgpu]
[  806.362926]  amdgpu_device_pre_asic_reset+0xb3/0x270 [amdgpu]
[  806.365560]  amdgpu_device_gpu_recover.cold+0x679/0x8eb [amdgpu]
[  806.368331]  ? __pm_runtime_resume+0x60/0x80
[  806.370509]  gpu_recover_get+0x2e/0x60 [amdgpu]
[  806.372887]  simple_attr_read+0x6d/0x110
[  806.374966]  debugfs_attr_read+0x49/0x70
[  806.377046]  full_proxy_read+0x5f/0x90
[  806.379054]  vfs_read+0xa3/0x190
[  806.380969]  ksys_read+0x70/0xf0
[  806.382833]  __x64_sys_read+0x1a/0x20
[  806.384803]  do_syscall_64+0x38/0x90
[  806.386743]  entry_SYSCALL_64_after_hwframe+0x44/0xa9
[  806.388946] RIP: 0033:0x7fb084ea1142
[  806.390914] Code: c0 e9 c2 fe ff ff 50 48 8d 3d 3a ca 0a 00 e8 f5 19 02 00 0f 1f 
44 00 00 f3 0f 1e fa 64 8b 04 25 18 00 00 00 85 c0 75 10 0f 05 <48> 3d 00 f0 ff 
ff 77 56 c3 0f 1f 44 00 00 48 83 ec 28 48 89 54 24
[  806.395496] RSP: 002b:7fffde50ee08 EFLAGS: 0246 ORIG_RAX: 

[  806.398298] RAX: ffda RBX: 0002 RCX: 7fb084ea1142
[  806.401063] RDX: 0002 RSI: 7fb0844ff000 RDI: 0003
[  806.403793] RBP: 7fb0844ff000 R08: 7fb0844fe010 R09: 
[  806.406516] R10: 0022 R11: 0246 R12: 555d3d3b51f0
[  806.409246] R13: 0003 R14: 0002 R15: 0002


I think we should shorten the backtrace here a bit.



Signed-off-by: Lang Yu 


Looks sane to me, but Andrey should probably also take a look.

Acked-by: Christian König 


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 -
  1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 7c6c435e5d02..ff341154394e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -4476,7 +4476,6 @@ int amdgpu_do_asic_reset(struct list_head 
*device_list_handle,
r = amdgpu_ib_ring_tests(tmp_adev);
if (r) {
dev_err(tmp_adev->dev, "ib ring test failed 
(%d).\n", r);
-  

[PATCH] drm/amd/amdgpu: fix a potential deadlock in gpu reset

[Lang Yu]

When amdgpu_ib_ring_tests failed, the reset logic called
amdgpu_device_ip_suspend twice, then deadlock occurred.

Deadlock log:
[  805.655192] amdgpu :04:00.0: amdgpu: ib ring test failed (-110).
[  806.011571] [drm] Register(0) [mmUVD_POWER_STATUS] failed to reach value 
0x0001 != 0x0002
[  806.280139] [drm] Register(0) [mmUVD_POWER_STATUS] failed to reach value 
0x0001 != 0x0002
[  806.290952] [drm] free PSP TMR buffer

[  806.319406] 
[  806.320315] WARNING: possible recursive locking detected
[  806.321225] 5.11.0-custom #1 Tainted: GW  OEL
[  806.322135] 
[  806.323043] cat/2593 is trying to acquire lock:
[  806.323825] 888136b1cdc8 (>dm.dc_lock){+.+.}-{3:3}, at: 
dm_suspend+0xb8/0x1d0 [amdgpu]
[  806.325668]
   but task is already holding lock:
[  806.326664] 888136b1cdc8 (>dm.dc_lock){+.+.}-{3:3}, at: 
dm_suspend+0xb8/0x1d0 [amdgpu]
[  806.328430]
   other info that might help us debug this:
[  806.329539]  Possible unsafe locking scenario:

[  806.330549]CPU0
[  806.330983]
[  806.331416]   lock(>dm.dc_lock);
[  806.332086]   lock(>dm.dc_lock);
[  806.332738]
*** DEADLOCK ***

[  806.333747]  May be due to missing lock nesting notation

[  806.334899] 3 locks held by cat/2593:
[  806.335537]  #0: 888100d3f1b8 (>mutex){+.+.}-{3:3}, at: 
simple_attr_read+0x4e/0x110
[  806.337009]  #1: 888136b1fd78 (>reset_sem){}-{3:3}, at: 
amdgpu_device_lock_adev+0x42/0x94 [amdgpu]
[  806.339018]  #2: 888136b1cdc8 (>dm.dc_lock){+.+.}-{3:3}, at: 
dm_suspend+0xb8/0x1d0 [amdgpu]
[  806.340869]
   stack backtrace:
[  806.341621] CPU: 6 PID: 2593 Comm: cat Tainted: GW  OEL
5.11.0-custom #1
[  806.342921] Hardware name: AMD Celadon-CZN/Celadon-CZN, BIOS 
WLD0C23N_Weekly_20_12_2 12/23/2020
[  806.344413] Call Trace:
[  806.344849]  dump_stack+0x93/0xbd
[  806.345435]  __lock_acquire.cold+0x18a/0x2cf
[  806.346179]  lock_acquire+0xca/0x390
[  806.346807]  ? dm_suspend+0xb8/0x1d0 [amdgpu]
[  806.347813]  __mutex_lock+0x9b/0x930
[  806.348454]  ? dm_suspend+0xb8/0x1d0 [amdgpu]
[  806.349434]  ? amdgpu_device_indirect_rreg+0x58/0x70 [amdgpu]
[  806.350581]  ? _raw_spin_unlock_irqrestore+0x47/0x50
[  806.351437]  ? dm_suspend+0xb8/0x1d0 [amdgpu]
[  806.352437]  ? rcu_read_lock_sched_held+0x4f/0x80
[  806.353252]  ? rcu_read_lock_sched_held+0x4f/0x80
[  806.354064]  mutex_lock_nested+0x1b/0x20
[  806.354747]  ? mutex_lock_nested+0x1b/0x20
[  806.355457]  dm_suspend+0xb8/0x1d0 [amdgpu]
[  806.356427]  ? soc15_common_set_clockgating_state+0x17d/0x19 [amdgpu]
[  806.357736]  amdgpu_device_ip_suspend_phase1+0x78/0xd0 [amdgpu]
[  806.360394]  amdgpu_device_ip_suspend+0x21/0x70 [amdgpu]
[  806.362926]  amdgpu_device_pre_asic_reset+0xb3/0x270 [amdgpu]
[  806.365560]  amdgpu_device_gpu_recover.cold+0x679/0x8eb [amdgpu]
[  806.368331]  ? __pm_runtime_resume+0x60/0x80
[  806.370509]  gpu_recover_get+0x2e/0x60 [amdgpu]
[  806.372887]  simple_attr_read+0x6d/0x110
[  806.374966]  debugfs_attr_read+0x49/0x70
[  806.377046]  full_proxy_read+0x5f/0x90
[  806.379054]  vfs_read+0xa3/0x190
[  806.380969]  ksys_read+0x70/0xf0
[  806.382833]  __x64_sys_read+0x1a/0x20
[  806.384803]  do_syscall_64+0x38/0x90
[  806.386743]  entry_SYSCALL_64_after_hwframe+0x44/0xa9
[  806.388946] RIP: 0033:0x7fb084ea1142
[  806.390914] Code: c0 e9 c2 fe ff ff 50 48 8d 3d 3a ca 0a 00 e8 f5 19 02 00 
0f 1f 44 00 00 f3 0f 1e fa 64 8b 04 25 18 00 00 00 85 c0 75 10 0f 05 <48> 3d 00 
f0 ff ff 77 56 c3 0f 1f 44 00 00 48 83 ec 28 48 89 54 24
[  806.395496] RSP: 002b:7fffde50ee08 EFLAGS: 0246 ORIG_RAX: 

[  806.398298] RAX: ffda RBX: 0002 RCX: 7fb084ea1142
[  806.401063] RDX: 0002 RSI: 7fb0844ff000 RDI: 0003
[  806.403793] RBP: 7fb0844ff000 R08: 7fb0844fe010 R09: 
[  806.406516] R10: 0022 R11: 0246 R12: 555d3d3b51f0
[  806.409246] R13: 0003 R14: 0002 R15: 0002

Signed-off-by: Lang Yu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 7c6c435e5d02..ff341154394e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -4476,7 +4476,6 @@ int amdgpu_do_asic_reset(struct list_head 
*device_list_handle,
r = amdgpu_ib_ring_tests(tmp_adev);
if (r) {
dev_err(tmp_adev->dev, "ib ring test failed 
(%d).\n", r);
-   r = amdgpu_device_ip_suspend(tmp_adev);
need_full_reset = true;
r = -EAGAIN;
goto end;
-- 
2.25.1

Re: [PATCH] drm/amdgpu: Add vbios version string

[Christian König]

Hi Jiawei,

yes agree and additional to that we need to go a step back here.

First of all once uAPI headers are added you are not allowed to change 
them again.


So this iterative approach where more and more fields to the structure 
is really a NO-GO.


Instead please revert all patches already pushed amd-staging-drm-next 
and then squash together all patches and send the result to the mailing 
list for discussion.


This way we can review and verify the uAPI as a whole and not in 
individual steps.


Regards,
Christian.

Am 17.05.21 um 12:28 schrieb Gu, JiaWei (Will):

[AMD Official Use Only - Internal Distribution Only]

Hi all,

I know the vbios ioctl discussion is not settled down yet.
Please just regard this patch as a proposal to include vbios version string 
info into discussion.

Best regards,
Jiawei

-Original Message-
From: Jiawei Gu 
Sent: Monday, May 17, 2021 6:22 PM
To: amd-gfx@lists.freedesktop.org; Koenig, Christian ; Nieto, 
David M ; mar...@gmail.com; Deucher, Alexander 

Cc: Deng, Emily ; Gu, JiaWei (Will) 
Subject: [PATCH] drm/amdgpu: Add vbios version string

Expose XXX.XXX.XXX.XXX.XX vbios version string in AMDGPU_INFO_VBIOS_INFO 
ioctl

Signed-off-by: Jiawei Gu 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c|  2 ++
  drivers/gpu/drm/amd/amdgpu/atom.c  | 16 
  drivers/gpu/drm/amd/amdgpu/atom.h  |  1 +
  drivers/gpu/drm/amd/include/atomfirmware.h |  1 +
  include/uapi/drm/amdgpu_drm.h  |  1 +
  5 files changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index e1008a79b441..30e4fed3de22 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -870,6 +870,8 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, 
struct drm_file *filp)
vbios_info.dbdf = PCI_DEVID(adev->pdev->bus->number, 
adev->pdev->devfn);
memcpy(vbios_info.vbios_pn, atom_context->vbios_pn, 
sizeof(atom_context->vbios_pn));
vbios_info.version = atom_context->version;
+   memcpy(vbios_info.vbios_ver_str, 
atom_context->vbios_ver_str,
+   
sizeof(atom_context->vbios_ver_str));
memcpy(vbios_info.date, atom_context->date, 
sizeof(atom_context->date));
vbios_info.serial = adev->unique_id;
vbios_info.dev_id = adev->pdev->device; diff --git 
a/drivers/gpu/drm/amd/amdgpu/atom.c b/drivers/gpu/drm/amd/amdgpu/atom.c
index 0e2f0ea13b40..542b2c2414e4 100644
--- a/drivers/gpu/drm/amd/amdgpu/atom.c
+++ b/drivers/gpu/drm/amd/amdgpu/atom.c
@@ -1438,6 +1438,21 @@ static void atom_get_vbios_pn(struct atom_context *ctx)
}
  }
  
+static void atom_get_vbios_version(struct atom_context *ctx) {

+   unsigned char *vbios_ver;
+
+   /* find anchor ATOMBIOSBK-AMD */
+   vbios_ver = atom_find_str_in_rom(ctx, BIOS_VERSION_PREFIX, 3, 1024, 64);
+   if (vbios_ver != NULL) {
+   /* skip ATOMBIOSBK-AMD VER */
+   vbios_ver += 18;
+   memcpy(ctx->vbios_ver_str, vbios_ver, STRLEN_NORMAL);
+   } else {
+   ctx->vbios_ver_str[0] = '\0';
+   }
+}
+
  struct atom_context *amdgpu_atom_parse(struct card_info *card, void *bios)  {
int base;
@@ -1511,6 +1526,7 @@ struct atom_context *amdgpu_atom_parse(struct card_info 
*card, void *bios)
atom_get_vbios_name(ctx);
atom_get_vbios_pn(ctx);
atom_get_vbios_date(ctx);
+   atom_get_vbios_version(ctx);
  
  	return ctx;

  }
diff --git a/drivers/gpu/drm/amd/amdgpu/atom.h 
b/drivers/gpu/drm/amd/amdgpu/atom.h
index c729f7ceba4f..6463ce6e756d 100644
--- a/drivers/gpu/drm/amd/amdgpu/atom.h
+++ b/drivers/gpu/drm/amd/amdgpu/atom.h
@@ -148,6 +148,7 @@ struct atom_context {
uint8_t name[STRLEN_LONG];
uint8_t vbios_pn[STRLEN_LONG];
uint32_t version;
+   uint8_t vbios_ver_str[STRLEN_NORMAL];
uint8_t date[STRLEN_NORMAL];
uint32_t sub_dev_id;
uint32_t sub_ved_id;
diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h 
b/drivers/gpu/drm/amd/include/atomfirmware.h
index 14d0d7d58255..28deecc2f990 100644
--- a/drivers/gpu/drm/amd/include/atomfirmware.h
+++ b/drivers/gpu/drm/amd/include/atomfirmware.h
@@ -198,6 +198,7 @@ enum atom_dp_vs_preemph_def{  };
  
  #define BIOS_ATOM_PREFIX   "ATOMBIOS"

+#define BIOS_VERSION_PREFIX  "ATOMBIOSBK-AMD"
  #define BIOS_STRING_LENGTH 43
  
  /*

diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h 
index 2d9e84658bbc..e0f98ca9a755 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -956,6 +956,7 @@ struct drm_amdgpu_info_vbios {
__u32 dbdf;
__u8 vbios_pn[64];
__u32 version;
+   __u8 vbios_ver_str[32];
__u8 date[32];
__u64 serial;
__u32 dev_id;

RE: [PATCH] drm/amdgpu: Add vbios version string

[Gu, JiaWei (Will)]

[AMD Official Use Only - Internal Distribution Only]

Hi all,

I know the vbios ioctl discussion is not settled down yet.
Please just regard this patch as a proposal to include vbios version string 
info into discussion.

Best regards,
Jiawei

-Original Message-
From: Jiawei Gu  
Sent: Monday, May 17, 2021 6:22 PM
To: amd-gfx@lists.freedesktop.org; Koenig, Christian 
; Nieto, David M ; 
mar...@gmail.com; Deucher, Alexander 
Cc: Deng, Emily ; Gu, JiaWei (Will) 
Subject: [PATCH] drm/amdgpu: Add vbios version string

Expose XXX.XXX.XXX.XXX.XX vbios version string in AMDGPU_INFO_VBIOS_INFO 
ioctl

Signed-off-by: Jiawei Gu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c|  2 ++
 drivers/gpu/drm/amd/amdgpu/atom.c  | 16 
 drivers/gpu/drm/amd/amdgpu/atom.h  |  1 +
 drivers/gpu/drm/amd/include/atomfirmware.h |  1 +
 include/uapi/drm/amdgpu_drm.h  |  1 +
 5 files changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index e1008a79b441..30e4fed3de22 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -870,6 +870,8 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, 
struct drm_file *filp)
vbios_info.dbdf = PCI_DEVID(adev->pdev->bus->number, 
adev->pdev->devfn);
memcpy(vbios_info.vbios_pn, atom_context->vbios_pn, 
sizeof(atom_context->vbios_pn));
vbios_info.version = atom_context->version;
+   memcpy(vbios_info.vbios_ver_str, 
atom_context->vbios_ver_str,
+   
sizeof(atom_context->vbios_ver_str));
memcpy(vbios_info.date, atom_context->date, 
sizeof(atom_context->date));
vbios_info.serial = adev->unique_id;
vbios_info.dev_id = adev->pdev->device; diff --git 
a/drivers/gpu/drm/amd/amdgpu/atom.c b/drivers/gpu/drm/amd/amdgpu/atom.c
index 0e2f0ea13b40..542b2c2414e4 100644
--- a/drivers/gpu/drm/amd/amdgpu/atom.c
+++ b/drivers/gpu/drm/amd/amdgpu/atom.c
@@ -1438,6 +1438,21 @@ static void atom_get_vbios_pn(struct atom_context *ctx)
}
 }
 
+static void atom_get_vbios_version(struct atom_context *ctx) {
+   unsigned char *vbios_ver;
+
+   /* find anchor ATOMBIOSBK-AMD */
+   vbios_ver = atom_find_str_in_rom(ctx, BIOS_VERSION_PREFIX, 3, 1024, 64);
+   if (vbios_ver != NULL) {
+   /* skip ATOMBIOSBK-AMD VER */
+   vbios_ver += 18;
+   memcpy(ctx->vbios_ver_str, vbios_ver, STRLEN_NORMAL);
+   } else {
+   ctx->vbios_ver_str[0] = '\0';
+   }
+}
+
 struct atom_context *amdgpu_atom_parse(struct card_info *card, void *bios)  {
int base;
@@ -1511,6 +1526,7 @@ struct atom_context *amdgpu_atom_parse(struct card_info 
*card, void *bios)
atom_get_vbios_name(ctx);
atom_get_vbios_pn(ctx);
atom_get_vbios_date(ctx);
+   atom_get_vbios_version(ctx);
 
return ctx;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/atom.h 
b/drivers/gpu/drm/amd/amdgpu/atom.h
index c729f7ceba4f..6463ce6e756d 100644
--- a/drivers/gpu/drm/amd/amdgpu/atom.h
+++ b/drivers/gpu/drm/amd/amdgpu/atom.h
@@ -148,6 +148,7 @@ struct atom_context {
uint8_t name[STRLEN_LONG];
uint8_t vbios_pn[STRLEN_LONG];
uint32_t version;
+   uint8_t vbios_ver_str[STRLEN_NORMAL];
uint8_t date[STRLEN_NORMAL];
uint32_t sub_dev_id;
uint32_t sub_ved_id;
diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h 
b/drivers/gpu/drm/amd/include/atomfirmware.h
index 14d0d7d58255..28deecc2f990 100644
--- a/drivers/gpu/drm/amd/include/atomfirmware.h
+++ b/drivers/gpu/drm/amd/include/atomfirmware.h
@@ -198,6 +198,7 @@ enum atom_dp_vs_preemph_def{  };
 
 #define BIOS_ATOM_PREFIX   "ATOMBIOS"
+#define BIOS_VERSION_PREFIX  "ATOMBIOSBK-AMD"
 #define BIOS_STRING_LENGTH 43
 
 /*
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h 
index 2d9e84658bbc..e0f98ca9a755 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -956,6 +956,7 @@ struct drm_amdgpu_info_vbios {
__u32 dbdf;
__u8 vbios_pn[64];
__u32 version;
+   __u8 vbios_ver_str[32];
__u8 date[32];
__u64 serial;
__u32 dev_id;
--
2.17.1
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[PATCH] drm/amdgpu: Add vbios version string

[Jiawei Gu]

Expose XXX.XXX.XXX.XXX.XX vbios version string in
AMDGPU_INFO_VBIOS_INFO ioctl

Signed-off-by: Jiawei Gu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c|  2 ++
 drivers/gpu/drm/amd/amdgpu/atom.c  | 16 
 drivers/gpu/drm/amd/amdgpu/atom.h  |  1 +
 drivers/gpu/drm/amd/include/atomfirmware.h |  1 +
 include/uapi/drm/amdgpu_drm.h  |  1 +
 5 files changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index e1008a79b441..30e4fed3de22 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -870,6 +870,8 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, 
struct drm_file *filp)
vbios_info.dbdf = PCI_DEVID(adev->pdev->bus->number, 
adev->pdev->devfn);
memcpy(vbios_info.vbios_pn, atom_context->vbios_pn, 
sizeof(atom_context->vbios_pn));
vbios_info.version = atom_context->version;
+   memcpy(vbios_info.vbios_ver_str, 
atom_context->vbios_ver_str,
+   
sizeof(atom_context->vbios_ver_str));
memcpy(vbios_info.date, atom_context->date, 
sizeof(atom_context->date));
vbios_info.serial = adev->unique_id;
vbios_info.dev_id = adev->pdev->device;
diff --git a/drivers/gpu/drm/amd/amdgpu/atom.c 
b/drivers/gpu/drm/amd/amdgpu/atom.c
index 0e2f0ea13b40..542b2c2414e4 100644
--- a/drivers/gpu/drm/amd/amdgpu/atom.c
+++ b/drivers/gpu/drm/amd/amdgpu/atom.c
@@ -1438,6 +1438,21 @@ static void atom_get_vbios_pn(struct atom_context *ctx)
}
 }
 
+static void atom_get_vbios_version(struct atom_context *ctx)
+{
+   unsigned char *vbios_ver;
+
+   /* find anchor ATOMBIOSBK-AMD */
+   vbios_ver = atom_find_str_in_rom(ctx, BIOS_VERSION_PREFIX, 3, 1024, 64);
+   if (vbios_ver != NULL) {
+   /* skip ATOMBIOSBK-AMD VER */
+   vbios_ver += 18;
+   memcpy(ctx->vbios_ver_str, vbios_ver, STRLEN_NORMAL);
+   } else {
+   ctx->vbios_ver_str[0] = '\0';
+   }
+}
+
 struct atom_context *amdgpu_atom_parse(struct card_info *card, void *bios)
 {
int base;
@@ -1511,6 +1526,7 @@ struct atom_context *amdgpu_atom_parse(struct card_info 
*card, void *bios)
atom_get_vbios_name(ctx);
atom_get_vbios_pn(ctx);
atom_get_vbios_date(ctx);
+   atom_get_vbios_version(ctx);
 
return ctx;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/atom.h 
b/drivers/gpu/drm/amd/amdgpu/atom.h
index c729f7ceba4f..6463ce6e756d 100644
--- a/drivers/gpu/drm/amd/amdgpu/atom.h
+++ b/drivers/gpu/drm/amd/amdgpu/atom.h
@@ -148,6 +148,7 @@ struct atom_context {
uint8_t name[STRLEN_LONG];
uint8_t vbios_pn[STRLEN_LONG];
uint32_t version;
+   uint8_t vbios_ver_str[STRLEN_NORMAL];
uint8_t date[STRLEN_NORMAL];
uint32_t sub_dev_id;
uint32_t sub_ved_id;
diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h 
b/drivers/gpu/drm/amd/include/atomfirmware.h
index 14d0d7d58255..28deecc2f990 100644
--- a/drivers/gpu/drm/amd/include/atomfirmware.h
+++ b/drivers/gpu/drm/amd/include/atomfirmware.h
@@ -198,6 +198,7 @@ enum atom_dp_vs_preemph_def{
 };
 
 #define BIOS_ATOM_PREFIX   "ATOMBIOS"
+#define BIOS_VERSION_PREFIX  "ATOMBIOSBK-AMD"
 #define BIOS_STRING_LENGTH 43
 
 /*
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index 2d9e84658bbc..e0f98ca9a755 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -956,6 +956,7 @@ struct drm_amdgpu_info_vbios {
__u32 dbdf;
__u8 vbios_pn[64];
__u32 version;
+   __u8 vbios_ver_str[32];
__u8 date[32];
__u64 serial;
__u32 dev_id;
-- 
2.17.1

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Re: [PATCH v2 2/3] drm/amd/pm: Fix showing incorrect frequencies on aldebaran

[Wang, Kevin(Yang)]

[AMD Public Use]

ok, it is fine for me,
and some code blocks need to have a blank line to match kernel coding style.
with that fixes,  Series is

Reviewed-by: Kevin Wang 

Best Regards,
Kevin

From: Lazar, Lijo 
Sent: Monday, May 17, 2021 5:04 PM
To: Wang, Kevin(Yang) ; amd-gfx@lists.freedesktop.org 

Cc: Zhang, Hawking ; Chen, Guchun ; 
Feng, Kenneth 
Subject: RE: [PATCH v2 2/3] drm/amd/pm: Fix showing incorrect frequencies on 
aldebaran


[AMD Public Use]



Hi Kevin,



This case is for determinism mode  - there it uses the max frequency passed and 
min_clk is the default min clock.



Thanks,

Lijo



From: Wang, Kevin(Yang) 
Sent: Monday, May 17, 2021 2:32 PM
To: Lazar, Lijo ; amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Chen, Guchun ; 
Feng, Kenneth 
Subject: Re: [PATCH v2 2/3] drm/amd/pm: Fix showing incorrect frequencies on 
aldebaran



[AMD Public Use]



Hi Lijo,



+ 
pstate_table->gfxclk_pstate.curr.min = min_clk;

+ 
pstate_table->gfxclk_pstate.curr.max = max;



min_clk and max,

it seems it is coding error, is right?



Best Regards,

Kevin



From: Lazar, Lijo mailto:lijo.la...@amd.com>>
Sent: Monday, May 17, 2021 4:39 PM
To: amd-gfx@lists.freedesktop.org 
mailto:amd-gfx@lists.freedesktop.org>>
Cc: Zhang, Hawking mailto:hawking.zh...@amd.com>>; Wang, 
Kevin(Yang) mailto:kevin1.w...@amd.com>>; Chen, Guchun 
mailto:guchun.c...@amd.com>>; Feng, Kenneth 
mailto:kenneth.f...@amd.com>>
Subject: [PATCH v2 2/3] drm/amd/pm: Fix showing incorrect frequencies on 
aldebaran



[AMD Public Use]



v1: Use the current and custom pstate frequencies to track the current and

user-set min/max values in manual and determinism mode. Previously, only

actual_* value was used to track the currrent and user requested value.

The value will get reassigned whenever user requests a new value with

pp_od_clk_voltage node. Hence it will show incorrect values when user

requests an invalid value or tries a partial request without committing

the values. Separating out to custom and current variable fixes such

issues.



v2: Remove redundant if-else check



Signed-off-by: Lijo Lazar lijo.la...@amd.com

---

.../drm/amd/pm/swsmu/smu13/aldebaran_ppt.c| 65 ---

.../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c|  6 ++

2 files changed, 46 insertions(+), 25 deletions(-)



diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

index 5d04a1dfdfd8..d27ed2954705 100644

--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

@@ -78,8 +78,6 @@

 #define smnPCIE_ESM_CTRL 0x111003D0

-#define CLOCK_VALID (1 << 31)

-

static const struct cmn2asic_msg_mapping 
aldebaran_message_map[SMU_MSG_MAX_COUNT] = {

   MSG_MAP(TestMessage, 
 PPSMC_MSG_TestMessage,  0),

   MSG_MAP(GetSmuVersion,   
  PPSMC_MSG_GetSmuVersion, 1),

@@ -455,12 +453,18 @@ static int aldebaran_populate_umd_state_clk(struct 
smu_context *smu)

pstate_table->gfxclk_pstate.min = gfx_table->min;

   pstate_table->gfxclk_pstate.peak = gfx_table->max;

+ pstate_table->gfxclk_pstate.curr.min = gfx_table->min;

+ pstate_table->gfxclk_pstate.curr.max = gfx_table->max;

pstate_table->uclk_pstate.min = mem_table->min;

   pstate_table->uclk_pstate.peak = mem_table->max;

+ pstate_table->uclk_pstate.curr.min = mem_table->min;

+ pstate_table->uclk_pstate.curr.max = mem_table->max;

pstate_table->socclk_pstate.min = soc_table->min;

   pstate_table->socclk_pstate.peak = soc_table->max;

+ pstate_table->socclk_pstate.curr.min = soc_table->min;

+ pstate_table->socclk_pstate.curr.max = soc_table->max;

if (gfx_table->count > ALDEBARAN_UMD_PSTATE_GFXCLK_LEVEL &&

   mem_table->count > ALDEBARAN_UMD_PSTATE_MCLK_LEVEL &&

@@ -669,6 +673,7 @@ static int aldebaran_print_clk_levels(struct smu_context 
*smu,

{

   int i, now, size = 0;

   int ret = 0;

+ struct smu_umd_pstate_table *pstate_table = >pstate_table;

   struct pp_clock_levels_with_latency clocks;

   struct smu_13_0_dpm_table *single_dpm_table;

   struct smu_dpm_context *smu_dpm = >smu_dpm;

@@ -703,12 +708,8 @@ static int aldebaran_print_clk_levels(struct smu_context 
*smu,

display_levels = clocks.num_levels;

-   

RE: [PATCH v2 2/3] drm/amd/pm: Fix showing incorrect frequencies on aldebaran

[Lazar, Lijo]

[AMD Public Use]

Hi Kevin,

This case is for determinism mode  - there it uses the max frequency passed and 
min_clk is the default min clock.

Thanks,
Lijo

From: Wang, Kevin(Yang) 
Sent: Monday, May 17, 2021 2:32 PM
To: Lazar, Lijo ; amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Chen, Guchun ; 
Feng, Kenneth 
Subject: Re: [PATCH v2 2/3] drm/amd/pm: Fix showing incorrect frequencies on 
aldebaran


[AMD Public Use]


Hi Lijo,



+ 
pstate_table->gfxclk_pstate.curr.min = min_clk;

+ 
pstate_table->gfxclk_pstate.curr.max = max;



min_clk and max,

it seems it is coding error, is right?



Best Regards,

Kevin


From: Lazar, Lijo mailto:lijo.la...@amd.com>>
Sent: Monday, May 17, 2021 4:39 PM
To: amd-gfx@lists.freedesktop.org 
mailto:amd-gfx@lists.freedesktop.org>>
Cc: Zhang, Hawking mailto:hawking.zh...@amd.com>>; Wang, 
Kevin(Yang) mailto:kevin1.w...@amd.com>>; Chen, Guchun 
mailto:guchun.c...@amd.com>>; Feng, Kenneth 
mailto:kenneth.f...@amd.com>>
Subject: [PATCH v2 2/3] drm/amd/pm: Fix showing incorrect frequencies on 
aldebaran


[AMD Public Use]


v1: Use the current and custom pstate frequencies to track the current and

user-set min/max values in manual and determinism mode. Previously, only

actual_* value was used to track the currrent and user requested value.

The value will get reassigned whenever user requests a new value with

pp_od_clk_voltage node. Hence it will show incorrect values when user

requests an invalid value or tries a partial request without committing

the values. Separating out to custom and current variable fixes such

issues.



v2: Remove redundant if-else check



Signed-off-by: Lijo Lazar lijo.la...@amd.com

---

.../drm/amd/pm/swsmu/smu13/aldebaran_ppt.c| 65 ---

.../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c|  6 ++

2 files changed, 46 insertions(+), 25 deletions(-)



diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

index 5d04a1dfdfd8..d27ed2954705 100644

--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

@@ -78,8 +78,6 @@

 #define smnPCIE_ESM_CTRL 0x111003D0

-#define CLOCK_VALID (1 << 31)

-

static const struct cmn2asic_msg_mapping 
aldebaran_message_map[SMU_MSG_MAX_COUNT] = {

   MSG_MAP(TestMessage, 
 PPSMC_MSG_TestMessage,  0),

   MSG_MAP(GetSmuVersion,   
  PPSMC_MSG_GetSmuVersion, 1),

@@ -455,12 +453,18 @@ static int aldebaran_populate_umd_state_clk(struct 
smu_context *smu)

pstate_table->gfxclk_pstate.min = gfx_table->min;

   pstate_table->gfxclk_pstate.peak = gfx_table->max;

+ pstate_table->gfxclk_pstate.curr.min = gfx_table->min;

+ pstate_table->gfxclk_pstate.curr.max = gfx_table->max;

pstate_table->uclk_pstate.min = mem_table->min;

   pstate_table->uclk_pstate.peak = mem_table->max;

+ pstate_table->uclk_pstate.curr.min = mem_table->min;

+ pstate_table->uclk_pstate.curr.max = mem_table->max;

pstate_table->socclk_pstate.min = soc_table->min;

   pstate_table->socclk_pstate.peak = soc_table->max;

+ pstate_table->socclk_pstate.curr.min = soc_table->min;

+ pstate_table->socclk_pstate.curr.max = soc_table->max;

if (gfx_table->count > ALDEBARAN_UMD_PSTATE_GFXCLK_LEVEL &&

   mem_table->count > ALDEBARAN_UMD_PSTATE_MCLK_LEVEL &&

@@ -669,6 +673,7 @@ static int aldebaran_print_clk_levels(struct smu_context 
*smu,

{

   int i, now, size = 0;

   int ret = 0;

+ struct smu_umd_pstate_table *pstate_table = >pstate_table;

   struct pp_clock_levels_with_latency clocks;

   struct smu_13_0_dpm_table *single_dpm_table;

   struct smu_dpm_context *smu_dpm = >smu_dpm;

@@ -703,12 +708,8 @@ static int aldebaran_print_clk_levels(struct smu_context 
*smu,

display_levels = clocks.num_levels;

-  min_clk = smu->gfx_actual_hard_min_freq & 
CLOCK_VALID ?

-
smu->gfx_actual_hard_min_freq & ~CLOCK_VALID :

-
single_dpm_table->dpm_levels[0].value;

-  max_clk = smu->gfx_actual_soft_max_freq & 
CLOCK_VALID ?

-
smu->gfx_actual_soft_max_freq & 

Re: [PATCH v2 2/3] drm/amd/pm: Fix showing incorrect frequencies on aldebaran

[Wang, Kevin(Yang)]

[AMD Public Use]


Hi Lijo,


+ 
pstate_table->gfxclk_pstate.curr.min = min_clk;

+ 
pstate_table->gfxclk_pstate.curr.max = max;


min_clk and max,

it seems it is coding error, is right?


Best Regards,

Kevin


From: Lazar, Lijo 
Sent: Monday, May 17, 2021 4:39 PM
To: amd-gfx@lists.freedesktop.org 
Cc: Zhang, Hawking ; Wang, Kevin(Yang) 
; Chen, Guchun ; Feng, Kenneth 

Subject: [PATCH v2 2/3] drm/amd/pm: Fix showing incorrect frequencies on 
aldebaran


[AMD Public Use]


v1: Use the current and custom pstate frequencies to track the current and

user-set min/max values in manual and determinism mode. Previously, only

actual_* value was used to track the currrent and user requested value.

The value will get reassigned whenever user requests a new value with

pp_od_clk_voltage node. Hence it will show incorrect values when user

requests an invalid value or tries a partial request without committing

the values. Separating out to custom and current variable fixes such

issues.



v2: Remove redundant if-else check



Signed-off-by: Lijo Lazar lijo.la...@amd.com

---

.../drm/amd/pm/swsmu/smu13/aldebaran_ppt.c| 65 ---

.../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c|  6 ++

2 files changed, 46 insertions(+), 25 deletions(-)



diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

index 5d04a1dfdfd8..d27ed2954705 100644

--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

@@ -78,8 +78,6 @@

 #define smnPCIE_ESM_CTRL 0x111003D0

-#define CLOCK_VALID (1 << 31)

-

static const struct cmn2asic_msg_mapping 
aldebaran_message_map[SMU_MSG_MAX_COUNT] = {

   MSG_MAP(TestMessage, 
 PPSMC_MSG_TestMessage,  0),

   MSG_MAP(GetSmuVersion,   
  PPSMC_MSG_GetSmuVersion, 1),

@@ -455,12 +453,18 @@ static int aldebaran_populate_umd_state_clk(struct 
smu_context *smu)

pstate_table->gfxclk_pstate.min = gfx_table->min;

   pstate_table->gfxclk_pstate.peak = gfx_table->max;

+ pstate_table->gfxclk_pstate.curr.min = gfx_table->min;

+ pstate_table->gfxclk_pstate.curr.max = gfx_table->max;

pstate_table->uclk_pstate.min = mem_table->min;

   pstate_table->uclk_pstate.peak = mem_table->max;

+ pstate_table->uclk_pstate.curr.min = mem_table->min;

+ pstate_table->uclk_pstate.curr.max = mem_table->max;

pstate_table->socclk_pstate.min = soc_table->min;

   pstate_table->socclk_pstate.peak = soc_table->max;

+ pstate_table->socclk_pstate.curr.min = soc_table->min;

+ pstate_table->socclk_pstate.curr.max = soc_table->max;

if (gfx_table->count > ALDEBARAN_UMD_PSTATE_GFXCLK_LEVEL &&

   mem_table->count > ALDEBARAN_UMD_PSTATE_MCLK_LEVEL &&

@@ -669,6 +673,7 @@ static int aldebaran_print_clk_levels(struct smu_context 
*smu,

{

   int i, now, size = 0;

   int ret = 0;

+ struct smu_umd_pstate_table *pstate_table = >pstate_table;

   struct pp_clock_levels_with_latency clocks;

   struct smu_13_0_dpm_table *single_dpm_table;

   struct smu_dpm_context *smu_dpm = >smu_dpm;

@@ -703,12 +708,8 @@ static int aldebaran_print_clk_levels(struct smu_context 
*smu,

display_levels = clocks.num_levels;

-  min_clk = smu->gfx_actual_hard_min_freq & 
CLOCK_VALID ?

-
smu->gfx_actual_hard_min_freq & ~CLOCK_VALID :

-
single_dpm_table->dpm_levels[0].value;

-  max_clk = smu->gfx_actual_soft_max_freq & 
CLOCK_VALID ?

-
smu->gfx_actual_soft_max_freq & ~CLOCK_VALID :

-
single_dpm_table->dpm_levels[1].value;

+ min_clk = pstate_table->gfxclk_pstate.curr.min;

+ max_clk = pstate_table->gfxclk_pstate.curr.max;

freq_values[0] = min_clk;

   freq_values[1] = max_clk;

@@ -1134,9 +1135,6 @@ static int aldebaran_set_performance_level(struct 
smu_context *smu,

   && (level != 
AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM))

   

Re: [RFC PATCH 0/3] A drm_plane API to support HDR planes

[Pekka Paalanen]

On Fri, 14 May 2021 17:05:11 -0400
Harry Wentland  wrote:

> On 2021-04-27 10:50 a.m., Pekka Paalanen wrote:
> > On Mon, 26 Apr 2021 13:38:49 -0400
> > Harry Wentland  wrote:

...

> >> ## Mastering Luminances
> >>
> >> Now we are able to use the PQ 2084 EOTF to define the luminance of
> >> pixels in absolute terms. Unfortunately we're again presented with
> >> physical limitations of the display technologies on the market today.
> >> Here are a few examples of luminance ranges of displays.
> >>
> >> | Display  | Luminance range in nits |
> >> |  | --- |
> >> | Typical PC display   | 0.3 - 200   |
> >> | Excellent LCD HDTV   | 0.3 - 400   |
> >> | HDR LCD w/ local dimming | 0.05 - 1,500|
> >>
> >> Since no display can currently show the full 0.0005 to 10,000 nits
> >> luminance range the display will need to tonemap the HDR content, i.e
> >> to fit the content within a display's capabilities. To assist with
> >> tonemapping HDR content is usually accompanied with a metadata that
> >> describes (among other things) the minimum and maximum mastering
> >> luminance, i.e. the maximum and minimum luminance of the display that
> >> was used to master the HDR content.
> >>
> >> The HDR metadata is currently defined on the drm_connector via the
> >> hdr_output_metadata blob property.
> >>
> >> It might be useful to define per-plane hdr metadata, as different
> >> planes might have been mastered differently.  
> > 
> > I don't think this would directly help with the dynamic range blending
> > problem. You still need to establish the mapping between the optical
> > values from two different EOTFs and dynamic ranges. Or can you know
> > which optical values match the mastering display maximum and minimum
> > luminances for not-PQ?
> >   
> 
> My understanding of this is probably best illustrated by this example:
> 
> Assume HDR was mastered on a display with a maximum white level of 500
> nits and played back on a display that supports a max white level of 400
> nits. If you know the mastering white level of 500 you know that this is
> the maximum value you need to compress down to 400 nits, allowing you to
> use the full extent of the 400 nits panel.

Right, but in the kernel, where do you get these nits values from?

hdr_output_metadata blob is infoframe data to the monitor. I think this
should be independent of the metadata used for color transformations in
the display pipeline before the monitor.

EDID may tell us the monitor HDR metadata, but again what is used in
the color transformations should be independent, because EDIDs lie,
lighting environments change, and users have different preferences.

What about black levels?

Do you want to do black level adjustment?

How exactly should the compression work?

Where do you map the mid-tones?

What if the end user wants something different?

> If you do not know the mastering luminance is 500 nits you would
> have to compress 10,000 nits down to 400 (assuming PQ), losing quite
> a bit of the full 400 nits available as you'll need room to map the 500
> to 10,000 nits range which in reality is completely unused. You might end
> up with mapping 500 nits to 350 nits, instead of mapping it to 400.

The quality of the result depends on the compression (tone-mapping)
algorithm. I believe no-one will ever do a simple linear compression of
ranges.

Instead, you probably do something smooth in the black end, keep
mid-tones roughly as they are, and the again do a smooth saturation to
some "reasonable" level that goes well with the monitor in the current
lighting environment without introducing coloring artifacts, and just
clip the huge overshoot of the full PQ-range.

There are many big and small decisions to be made in how to map
out-of-gamut or out-of-brightness values into the displayable range,
and no algorithm fits all use cases. I believe this is why e.g. ICC
has several different "render intents", some of which are so vaguely
defined that they are practically undefined - just like what "a good
picture" means. You have essentially three dimensions: luminance, hue,
and saturation. Which one will you sacrifice, shift or emphasize and to
what degree to fit the square content peg into the round display hole?

A naive example: Let's say content has 300 nits red. Your display can
show max 400 nits white or max 180 nits red, and anything in between.
What will you show?

The problem is, that if UAPI does not define exactly what happens, then
taking advantage of these hardware capabilities means you have no idea
what happens to your content. This may be fine for closed systems, where
the software has been carefully built for the specific hardware
revision and the use cases of the complete system have been
pre-defined, so that it can assume what should and will happen. But
should that be exposed as a generic UAPI, when generic userspace has no
chance of knowing what it will do?

Re: [PATCH] drm/amd/amdgpu: fix refcount leak

[Christian König]

Am 17.05.21 um 10:26 schrieb Jingwen Chen:

[Why]
the gem object rfb->base.obj[0] is get according to num_planes
in amdgpufb_create, but is not put according to num_planes

[How]
put rfb->base.obj[0] in amdgpu_fbdev_destroy according to num_planes

Signed-off-by: Jingwen Chen 


Looks sane to me, but Alex might want to take a look as well.

Acked-by: Christian König 


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 3 +++
  1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
index 4f10c4529840..09b048647523 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
@@ -288,10 +288,13 @@ static int amdgpufb_create(struct drm_fb_helper *helper,
  static int amdgpu_fbdev_destroy(struct drm_device *dev, struct amdgpu_fbdev 
*rfbdev)
  {
struct amdgpu_framebuffer *rfb = >rfb;
+   int i;
  
  	drm_fb_helper_unregister_fbi(>helper);
  
  	if (rfb->base.obj[0]) {

+   for (i = 0; i < rfb->base.format->num_planes; i++)
+   drm_gem_object_put(rfb->base.obj[0]);
amdgpufb_destroy_pinned_object(rfb->base.obj[0]);
rfb->base.obj[0] = NULL;
drm_framebuffer_unregister_private(>base);


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[PATCH v2 3/3] drm/amd/pm: Reset max GFX clock after disabling determinism

[Lazar, Lijo]

[AMD Public Use]

When determinism mode is disabled on aldebaran, max GFX clock will
be reset to default max frequency value.

Signed-off-by: Lijo Lazar lijo.la...@amd.com
---
drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
index d27ed2954705..34afea71f1b3 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
@@ -1129,12 +1129,17 @@ static int aldebaran_set_performance_level(struct 
smu_context *smu,

  enum amd_dpm_forced_level level)
{
   struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
+ struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
+ struct smu_13_0_dpm_table *gfx_table =
+ _context->dpm_tables.gfx_table;
+ struct smu_umd_pstate_table *pstate_table = >pstate_table;
/* Disable determinism if switching to another mode */
-  if ((smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)
-  && (level != 
AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM))
+ if ((smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) 
&&
+ (level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) {
   smu_cmn_send_smc_msg(smu, 
SMU_MSG_DisableDeterminism, NULL);
-
+ pstate_table->gfxclk_pstate.curr.max = 
gfx_table->max;
+ }
switch (level) {
--
2.17.1

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[PATCH v2 2/3] drm/amd/pm: Fix showing incorrect frequencies on aldebaran

[Lazar, Lijo]

[AMD Public Use]

v1: Use the current and custom pstate frequencies to track the current and
user-set min/max values in manual and determinism mode. Previously, only
actual_* value was used to track the currrent and user requested value.
The value will get reassigned whenever user requests a new value with
pp_od_clk_voltage node. Hence it will show incorrect values when user
requests an invalid value or tries a partial request without committing
the values. Separating out to custom and current variable fixes such
issues.

v2: Remove redundant if-else check

Signed-off-by: Lijo Lazar lijo.la...@amd.com
---
.../drm/amd/pm/swsmu/smu13/aldebaran_ppt.c| 65 ---
.../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c|  6 ++
2 files changed, 46 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
index 5d04a1dfdfd8..d27ed2954705 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
@@ -78,8 +78,6 @@
 #define smnPCIE_ESM_CTRL 0x111003D0
-#define CLOCK_VALID (1 << 31)
-
static const struct cmn2asic_msg_mapping 
aldebaran_message_map[SMU_MSG_MAX_COUNT] = {
   MSG_MAP(TestMessage, 
 PPSMC_MSG_TestMessage,  0),
   MSG_MAP(GetSmuVersion,   
  PPSMC_MSG_GetSmuVersion, 1),
@@ -455,12 +453,18 @@ static int aldebaran_populate_umd_state_clk(struct 
smu_context *smu)
pstate_table->gfxclk_pstate.min = gfx_table->min;
   pstate_table->gfxclk_pstate.peak = gfx_table->max;
+ pstate_table->gfxclk_pstate.curr.min = gfx_table->min;
+ pstate_table->gfxclk_pstate.curr.max = gfx_table->max;
pstate_table->uclk_pstate.min = mem_table->min;
   pstate_table->uclk_pstate.peak = mem_table->max;
+ pstate_table->uclk_pstate.curr.min = mem_table->min;
+ pstate_table->uclk_pstate.curr.max = mem_table->max;
pstate_table->socclk_pstate.min = soc_table->min;
   pstate_table->socclk_pstate.peak = soc_table->max;
+ pstate_table->socclk_pstate.curr.min = soc_table->min;
+ pstate_table->socclk_pstate.curr.max = soc_table->max;
if (gfx_table->count > ALDEBARAN_UMD_PSTATE_GFXCLK_LEVEL &&
   mem_table->count > ALDEBARAN_UMD_PSTATE_MCLK_LEVEL &&
@@ -669,6 +673,7 @@ static int aldebaran_print_clk_levels(struct smu_context 
*smu,
{
   int i, now, size = 0;
   int ret = 0;
+ struct smu_umd_pstate_table *pstate_table = >pstate_table;
   struct pp_clock_levels_with_latency clocks;
   struct smu_13_0_dpm_table *single_dpm_table;
   struct smu_dpm_context *smu_dpm = >smu_dpm;
@@ -703,12 +708,8 @@ static int aldebaran_print_clk_levels(struct smu_context 
*smu,
display_levels = clocks.num_levels;
-  min_clk = smu->gfx_actual_hard_min_freq & 
CLOCK_VALID ?
-
smu->gfx_actual_hard_min_freq & ~CLOCK_VALID :
-
single_dpm_table->dpm_levels[0].value;
-  max_clk = smu->gfx_actual_soft_max_freq & 
CLOCK_VALID ?
-
smu->gfx_actual_soft_max_freq & ~CLOCK_VALID :
-
single_dpm_table->dpm_levels[1].value;
+ min_clk = pstate_table->gfxclk_pstate.curr.min;
+ max_clk = pstate_table->gfxclk_pstate.curr.max;
freq_values[0] = min_clk;
   freq_values[1] = max_clk;
@@ -1134,9 +1135,6 @@ static int aldebaran_set_performance_level(struct 
smu_context *smu,
   && (level != 
AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM))
   smu_cmn_send_smc_msg(smu, 
SMU_MSG_DisableDeterminism, NULL);
-  /* Reset user min/max gfx clock */
-  smu->gfx_actual_hard_min_freq = 0;
-  smu->gfx_actual_soft_max_freq = 0;
switch (level) {
@@ -1163,6 +1161,7 @@ static int aldebaran_set_soft_freq_limited_range(struct 
smu_context *smu,
{
   struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
   struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
+ struct smu_umd_pstate_table *pstate_table = >pstate_table;
   struct amdgpu_device *adev = smu->adev;
   uint32_t min_clk;
   uint32_t max_clk;
@@ 

[PATCH v2 1/3] drm/amd/pm: Add custom/current freq to pstates

[Lazar, Lijo]

[AMD Public Use]

Add custom member for user requested custom frequency, level mask
or min/max frequencies. Add curr member to keep track of the current
active values.

Signed-off-by: Lijo Lazar 
---
 drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 8 
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h 
b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
index 8bb224f6c762..76d670bd6440 100644
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
@@ -392,10 +392,18 @@ struct smu_baco_context
bool platform_support;
 };
 
+struct smu_freq_info {
+   uint32_t min;
+   uint32_t max;
+   uint32_t freq_level;
+};
+
 struct pstates_clk_freq {
uint32_tmin;
uint32_tstandard;
uint32_tpeak;
+   struct smu_freq_infocustom;
+   struct smu_freq_infocurr;
 };
 
 struct smu_umd_pstate_table {
-- 
2.17.1
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Re: [RFC PATCH 1/3] drm/color: Add RGB Color encodings

[Pekka Paalanen]

On Fri, 14 May 2021 17:04:51 -0400
Harry Wentland  wrote:

> On 2021-04-30 8:53 p.m., Sebastian Wick wrote:
> > On 2021-04-26 20:56, Harry Wentland wrote:  

...

> >> Another reason I'm proposing to define the color space (and gamma) of
> >> a plane is to make this explicit. Up until the color space and gamma
> >> of a plane or framebuffer are not well defined, which leads to drivers
> >> assuming the color space and gamma of a buffer (for blending and other
> >> purposes) and might lead to sub-optimal outcomes.  
> > 
> > Blending only is "correct" with linear light so that property of the
> > color space is important. However, why does the kernel have to be
> > involved here? As long as user space knows that for correct blending the
> > data must represent linear light and knows when in the pipeline blending
> > happens it can make sure that the data at that point in the pipeline
> > contains linear light.
> >   
> 
> The only reason the kernel needs to be involved is to take full advantage
> of the available HW without requiring KMS clients to be aware of
> the difference in display HW.

Can you explain in more tangible examples, why you think so, please?

Is it because hardware does not fit the KMS UAPI model of the abstract
pixel pipeline?

Or is it because you have fixed-function hardware elements that you can
only make use of when userspace uses an enum-based UAPI?

I would totally agree that the driver does not want to be analysing LUT
entries to decipher if it could use a fixed-function element or not. It
would introduce uncertainty in the UAPI. So fixed-function elements
would need their own properties, but I don't know if that is feasible
as generic UAPI or if it should be driver-specific (and so left unused
by generic userspace).


Thanks,
pq


pgpcRsBDhLORZ.pgp
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[PATCH] drm/amd/amdgpu: fix refcount leak

[Jingwen Chen]

[Why]
the gem object rfb->base.obj[0] is get according to num_planes
in amdgpufb_create, but is not put according to num_planes

[How]
put rfb->base.obj[0] in amdgpu_fbdev_destroy according to num_planes

Signed-off-by: Jingwen Chen 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
index 4f10c4529840..09b048647523 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
@@ -288,10 +288,13 @@ static int amdgpufb_create(struct drm_fb_helper *helper,
 static int amdgpu_fbdev_destroy(struct drm_device *dev, struct amdgpu_fbdev 
*rfbdev)
 {
struct amdgpu_framebuffer *rfb = >rfb;
+   int i;
 
drm_fb_helper_unregister_fbi(>helper);
 
if (rfb->base.obj[0]) {
+   for (i = 0; i < rfb->base.format->num_planes; i++)
+   drm_gem_object_put(rfb->base.obj[0]);
amdgpufb_destroy_pinned_object(rfb->base.obj[0]);
rfb->base.obj[0] = NULL;
drm_framebuffer_unregister_private(>base);
-- 
2.25.1

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回复: [PATCH] drm/amdgpu: fix PM reference leak in amdgpu_debugfs_gfxoff_rea()

[Pan, Xinhui]

[AMD Official Use Only]

thanks Kuai.
But code below matches the other code block in this file.

r = pm_runtime_get_sync(dev->dev);
if (r < 0) {
pm_runtime_put_autosuspend(dev->dev);
return r;
}


发件人: Yu Kuai 
发送时间: 2021年5月17日 16:16
收件人: Deucher, Alexander; Koenig, Christian; Pan, Xinhui; airl...@linux.ie; 
dan...@ffwll.ch
抄送: amd-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org; 
linux-ker...@vger.kernel.org; yuku...@huawei.com; yi.zh...@huawei.com
主题: [PATCH] drm/amdgpu: fix PM reference leak in amdgpu_debugfs_gfxoff_rea()

pm_runtime_get_sync will increment pm usage counter even it failed.
Forgetting to putting operation will result in reference leak here.
Fix it by replacing it with pm_runtime_resume_and_get to keep usage
counter balanced.

Reported-by: Hulk Robot 
Signed-off-by: Yu Kuai 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index bcaf271b39bf..eb7f9d20dad7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -1058,7 +1058,7 @@ static ssize_t amdgpu_debugfs_gfxoff_read(struct file *f, 
char __user *buf,
if (size & 0x3 || *pos & 0x3)
return -EINVAL;

-   r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
+   r = pm_runtime_resume_and_get(adev_to_drm(adev)->dev);
if (r < 0)
return r;

--
2.25.4

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RE: [PATCH] drm/amdgpu: disable 3DCGCG on picasso/raven1 to avoid compute hang

[Zhu, Changfeng]

[AMD Official Use Only - Internal Distribution Only]

Hi Ray and Alex,

I have confirmed it can enable the additional compute queues with this patch:

[   41.823013] This is ring mec 1, pipe 0, queue 0, value 1
[   41.823028] This is ring mec 1, pipe 1, queue 0, value 1
[   41.823042] This is ring mec 1, pipe 2, queue 0, value 1
[   41.823057] This is ring mec 1, pipe 3, queue 0, value 1
[   41.823071] This is ring mec 1, pipe 0, queue 1, value 1
[   41.823086] This is ring mec 1, pipe 1, queue 1, value 1
[   41.823101] This is ring mec 1, pipe 2, queue 1, value 1
[   41.823115] This is ring mec 1, pipe 3, queue 1, value 1

BR,
Changfeng.


-Original Message-
From: Huang, Ray  
Sent: Monday, May 17, 2021 2:27 PM
To: Alex Deucher ; Zhu, Changfeng 
Cc: amd-gfx list 
Subject: Re: [PATCH] drm/amdgpu: disable 3DCGCG on picasso/raven1 to avoid 
compute hang

On Fri, May 14, 2021 at 10:13:55PM +0800, Alex Deucher wrote:
> On Fri, May 14, 2021 at 4:20 AM  wrote:
> >
> > From: changzhu 
> >
> > From: Changfeng 
> >
> > There is problem with 3DCGCG firmware and it will cause compute test 
> > hang on picasso/raven1. It needs to disable 3DCGCG in driver to 
> > avoid compute hang.
> >
> > Change-Id: Ic7d3c7922b2b32f7ac5193d6a4869cbc5b3baa87
> > Signed-off-by: Changfeng 
> 
> Reviewed-by: Alex Deucher 
> 
> WIth this applied, can we re-enable the additional compute queues?
> 

I think so.

Changfeng, could you please confirm this on all raven series?

Patch is Reviewed-by: Huang Rui 

> Alex
> 
> > ---
> >  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 10 +++---
> >  drivers/gpu/drm/amd/amdgpu/soc15.c|  2 --
> >  2 files changed, 7 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
> > b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > index 22608c45f07c..feaa5e4a5538 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > @@ -4947,7 +4947,7 @@ static void gfx_v9_0_update_3d_clock_gating(struct 
> > amdgpu_device *adev,
> > amdgpu_gfx_rlc_enter_safe_mode(adev);
> >
> > /* Enable 3D CGCG/CGLS */
> > -   if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
> > +   if (enable) {
> > /* write cmd to clear cgcg/cgls ov */
> > def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
> > /* unset CGCG override */ @@ -4959,8 +4959,12 @@ 
> > static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,
> > /* enable 3Dcgcg FSM(0x363f) */
> > def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
> >
> > -   data = (0x36 << 
> > RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
> > -   RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
> > +   if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
> > +   data = (0x36 << 
> > RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
> > +   RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
> > +   else
> > +   data = 0x0 << 
> > + RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT;
> > +
> > if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
> > data |= (0x000F << 
> > RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
> > RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
> > diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c 
> > b/drivers/gpu/drm/amd/amdgpu/soc15.c
> > index 4b660b2d1c22..080e715799d4 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> > @@ -1393,7 +1393,6 @@ static int soc15_common_early_init(void *handle)
> > adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
> > AMD_CG_SUPPORT_GFX_MGLS |
> > AMD_CG_SUPPORT_GFX_CP_LS |
> > -   AMD_CG_SUPPORT_GFX_3D_CGCG |
> > AMD_CG_SUPPORT_GFX_3D_CGLS |
> > AMD_CG_SUPPORT_GFX_CGCG |
> > AMD_CG_SUPPORT_GFX_CGLS | @@ -1413,7 
> > +1412,6 @@ static int soc15_common_early_init(void *handle)
> > AMD_CG_SUPPORT_GFX_MGLS |
> > AMD_CG_SUPPORT_GFX_RLC_LS |
> > AMD_CG_SUPPORT_GFX_CP_LS |
> > -   AMD_CG_SUPPORT_GFX_3D_CGCG |
> > AMD_CG_SUPPORT_GFX_3D_CGLS |
> > AMD_CG_SUPPORT_GFX_CGCG |
> > AMD_CG_SUPPORT_GFX_CGLS |
> > --
> > 2.17.1
> >
> > ___
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> > amd-gfx@lists.freedesktop.org
> > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fli
> > sts.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfxdata=04%7C01%
> > 

[trivial PATCH] drm/amd/display: Fix typo of format termination newline

[Joe Perches]

/n should be \n

Signed-off-by: Joe Perches 
---
 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c   | 2 +-
 drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c | 2 +-
 drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
index 45f96221a094..b38fee783277 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
@@ -1724,7 +1724,7 @@ static bool init_soc_bounding_box(struct dc *dc,
DC_LOGGER_INIT(dc->ctx->logger);
 
if (!is_soc_bounding_box_valid(dc)) {
-   DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__);
+   DC_LOG_ERROR("%s: not valid soc bounding box\n", __func__);
return false;
}
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
index 5b54b7fc5105..3bf66c994dd5 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
@@ -1497,7 +1497,7 @@ static bool init_soc_bounding_box(struct dc *dc,
DC_LOGGER_INIT(dc->ctx->logger);
 
if (!is_soc_bounding_box_valid(dc)) {
-   DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__);
+   DC_LOG_ERROR("%s: not valid soc bounding box\n", __func__);
return false;
}
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
index fc2dea243d1b..84c61128423e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
@@ -1093,7 +1093,7 @@ static bool init_soc_bounding_box(struct dc *dc,  struct 
resource_pool *pool)
DC_LOGGER_INIT(dc->ctx->logger);
 
if (!is_soc_bounding_box_valid(dc)) {
-   DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__);
+   DC_LOG_ERROR("%s: not valid soc bounding box\n", __func__);
return false;
}
 

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Re: [PATCH] drm/amdgpu: optimize to drop preamble IB for old GPUs

[Christian König]

Yes and exactly that is the total mess I was talking about :)

The backend should be given clear orders which it act on. In other words 
"load_global_*", "load_ce_ram" etc...


The middle layer in amdgpu_ib_schedule()  then decides based of the 
flags if the what orders the backend should execute.


If you want to do this right I would suggest that you clean it up 
thoughtfully.


If you want to just get it working for now I suggest to adjust the 
skip_preamble variable in amdgpu_ib_schedule() and make sure that we 
never skip a preamble when gfxoff is enabled.


Regards,
Christian.

Am 17.05.21 um 09:20 schrieb Chen, Jiansong (Simon):

[AMD Official Use Only]

Does't the below code in gfx_v8_ring_emit_cntxcntl do almost the same thing as 
dropping the preamble ib. I cannot understand why bother to duplicate the 
optimization and cause a mess
In the common code.
 /* set load_ce_ram if preamble presented */
 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
 dw2 |= 0x1000;
 } else {
 /* still load_ce_ram if this is the first time preamble 
presented
  * although there is no context switch happens.
  */
 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
 dw2 |= 0x1000;
 }

-Original Message-
From: Christian König 
Sent: Monday, May 17, 2021 2:56 PM
To: Chen, Jiansong (Simon) ; Koenig, Christian 
; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu: optimize to drop preamble IB for old GPUs

Am 17.05.21 um 08:51 schrieb Chen, Jiansong (Simon):

[AMD Official Use Only]

Doesn't  current solution always enable the optimization in a safe and more 
clear way?

No, we also need this for gfx8 where gfxoff is currently not implemented.

Additional to that we mix common frontend handling into the backend with this 
approach.

But you could clean up the code in amdgpu_ib_schedule() quite a bit.

Regards,
Christian.


1. for gfx8/9/10 we use load_ce_ram in context_control to control the 
optimization.
2. for gfx6/7, we directly drop the preamble ib.

Regards,
Jiansong
-Original Message-
From: Koenig, Christian 
Sent: Monday, May 17, 2021 2:42 PM
To: Chen, Jiansong (Simon) ;
amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu: optimize to drop preamble IB for old
GPUs

Well NAK, as discussed checking the global flag is more flexible since it will 
still enable the preamble drop when gfxoff is disabled.

Christian.

Am 17.05.21 um 06:39 schrieb Jiansong Chen:

The optimization is safe for old GPUs and can help performance.

Signed-off-by: Jiansong Chen 
Change-Id: Id3b1250f1fe46dddbe8498894fb97e9753b7cafe
---
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 6 ++
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 6 ++
2 files changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index 3a8d52a54873..c915cc439484 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -1873,6 +1873,12 @@ static void gfx_v6_0_ring_emit_ib(struct amdgpu_ring 
*ring,
amdgpu_ring_write(ring, 0);
}

+ /* drop the CE preamble IB for the same context */
+ if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) &&
+ !(flags & AMDGPU_HAVE_CTX_SWITCH) &&
+ !(flags & AMDGPU_PREAMBLE_IB_PRESENT_FIRST))
+ return;
+
if (ib->flags & AMDGPU_IB_FLAG_CE)
header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
else
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index c35fdd2ef2d4..6d9ccae48024 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -2269,6 +2269,12 @@ static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring 
*ring,
amdgpu_ring_write(ring, 0);
}

+ /* drop the CE preamble IB for the same context */
+ if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) &&
+ !(flags & AMDGPU_HAVE_CTX_SWITCH) &&
+ !(flags & AMDGPU_PREAMBLE_IB_PRESENT_FIRST))
+ return;
+
if (ib->flags & AMDGPU_IB_FLAG_CE)
header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
else

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RE: [PATCH] drm/amdgpu: optimize to drop preamble IB for old GPUs

[Chen, Jiansong (Simon)]

[AMD Official Use Only]

Does't the below code in gfx_v8_ring_emit_cntxcntl do almost the same thing as 
dropping the preamble ib. I cannot understand why bother to duplicate the 
optimization and cause a mess
In the common code.
/* set load_ce_ram if preamble presented */
if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
dw2 |= 0x1000;
} else {
/* still load_ce_ram if this is the first time preamble 
presented
 * although there is no context switch happens.
 */
if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
dw2 |= 0x1000;
}

-Original Message-
From: Christian König 
Sent: Monday, May 17, 2021 2:56 PM
To: Chen, Jiansong (Simon) ; Koenig, Christian 
; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu: optimize to drop preamble IB for old GPUs

Am 17.05.21 um 08:51 schrieb Chen, Jiansong (Simon):
> [AMD Official Use Only]
>
> Doesn't  current solution always enable the optimization in a safe and more 
> clear way?

No, we also need this for gfx8 where gfxoff is currently not implemented.

Additional to that we mix common frontend handling into the backend with this 
approach.

But you could clean up the code in amdgpu_ib_schedule() quite a bit.

Regards,
Christian.

> 1. for gfx8/9/10 we use load_ce_ram in context_control to control the 
> optimization.
> 2. for gfx6/7, we directly drop the preamble ib.
>
> Regards,
> Jiansong
> -Original Message-
> From: Koenig, Christian 
> Sent: Monday, May 17, 2021 2:42 PM
> To: Chen, Jiansong (Simon) ;
> amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH] drm/amdgpu: optimize to drop preamble IB for old
> GPUs
>
> Well NAK, as discussed checking the global flag is more flexible since it 
> will still enable the preamble drop when gfxoff is disabled.
>
> Christian.
>
> Am 17.05.21 um 06:39 schrieb Jiansong Chen:
>> The optimization is safe for old GPUs and can help performance.
>>
>> Signed-off-by: Jiansong Chen 
>> Change-Id: Id3b1250f1fe46dddbe8498894fb97e9753b7cafe
>> ---
>>drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 6 ++
>>drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 6 ++
>>2 files changed, 12 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
>> index 3a8d52a54873..c915cc439484 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
>> @@ -1873,6 +1873,12 @@ static void gfx_v6_0_ring_emit_ib(struct amdgpu_ring 
>> *ring,
>>amdgpu_ring_write(ring, 0);
>>}
>>
>> + /* drop the CE preamble IB for the same context */
>> + if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) &&
>> + !(flags & AMDGPU_HAVE_CTX_SWITCH) &&
>> + !(flags & AMDGPU_PREAMBLE_IB_PRESENT_FIRST))
>> + return;
>> +
>>if (ib->flags & AMDGPU_IB_FLAG_CE)
>>header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
>>else
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
>> index c35fdd2ef2d4..6d9ccae48024 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
>> @@ -2269,6 +2269,12 @@ static void gfx_v7_0_ring_emit_ib_gfx(struct 
>> amdgpu_ring *ring,
>>amdgpu_ring_write(ring, 0);
>>}
>>
>> + /* drop the CE preamble IB for the same context */
>> + if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) &&
>> + !(flags & AMDGPU_HAVE_CTX_SWITCH) &&
>> + !(flags & AMDGPU_PREAMBLE_IB_PRESENT_FIRST))
>> + return;
>> +
>>if (ib->flags & AMDGPU_IB_FLAG_CE)
>>header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
>>else
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Re: [PATCH] drm/amd/amdgpu: destroy pinned gem obj according to refcount

[Christian König]

Am 17.05.21 um 09:11 schrieb Jingwen Chen:

[Why]
the fb gem object is get for 4 times when amdgpu_display_framebuffer_init,
while this object is put for less than 4 times. This can lead to warning trace
when unloading amdgpu

[How]
put gem object according to refcount in amdgpufb_destroy_pinned_object


WOW, that is a really big NAK.

Please instead fix the refcount leak.

Christian.



Warning trace attached:
[324584.505752] amdgpu :00:07.0: amdgpu: amdgpu: finishing device.
[324584.510737] [drm] clean up the vf2pf work item
[324584.532205] [drm] free PSP TMR buffer
[324584.591206] [ cut here ]
[324584.591449] WARNING: CPU: 1 PID: 5800 at 
/var/lib/dkms/amdgpu/5.11.11.119-1259830/build/include/drm/ttm/ttm_resource.h:196
 amdgpu_vram_mgr_fini+0x72/0x150 [amdgpu]
[324584.591450] Modules linked in: amdgpu(OE-) amd_iommu_v2 amdttm(OE) 
amd_sched(OE) amdkcl(OE) drm_kms_helper drm i2c_algo_bit fb_sys_fops 
syscopyarea sysfillrect sysimgblt intel_rapl_msr intel_rapl_common kvm 
irqbypass snd_hda_codec_generic ledtrig_audio snd_hda_intel snd_intel_dspcfg 
crct10dif_pclmul snd_hda_codec crc32_pclmul ghash_clmulni_intel snd_hda_core 
snd_hwdep snd_pcm aesni_intel aes_x86_64 crypto_simd snd_seq_midi cryptd 
snd_seq_midi_event glue_helper snd_rawmidi snd_seq input_leds snd_seq_device 
serio_raw snd_timer snd mac_hid soundcore qemu_fw_cfg sch_fq_codel binfmt_misc 
parport_pc ppdev lp parport ip_tables x_tables autofs4 8139too psmouse floppy 
8139cp mii i2c_piix4 pata_acpi [last unloaded: amd_iommu_v2]
[324584.591479] CPU: 1 PID: 5800 Comm: modprobe Tainted: GW  OE 
5.3.0-61-generic #55~18.04.1-Ubuntu
[324584.591480] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 
1.10.2-1ubuntu1 04/01/2014
[324584.591538] RIP: 0010:amdgpu_vram_mgr_fini+0x72/0x150 [amdgpu]
[324584.591540] Code: 00 00 41 c6 84 24 40 5d 00 00 00 4c 89 f6 e8 85 9d fa ff 85 c0 
74 17 5b 41 5c 41 5d 41 5e 41 5f 5d c3 4c 89 ff e8 51 d3 a9 dc <0f> 0b eb c3 4d 
8d b4 24 90 5e 00 00 4d 8d ac 24 98 5e 00 00 4c 89
[324584.591541] RSP: 0018:9ce444e7fce8 EFLAGS: 00010282
[324584.591542] RAX: 0024 RBX: 8e86b02c5d60 RCX: 

[324584.591543] RDX:  RSI: 8e86b7a97448 RDI: 
8e86b7a97448
[324584.591543] RBP: 9ce444e7fd10 R08: 0405 R09: 
0004
[324584.591544] R10: 9ce444e7fcd0 R11: 0001 R12: 
8e86b02c
[324584.591544] R13: 8e86b02c5da0 R14: 8e86b02c5d40 R15: 
c0c702a8
[324584.591545] FS:  7fea6fac0540() GS:8e86b7a8() 
knlGS:
[324584.591546] CS:  0010 DS:  ES:  CR0: 80050033
[324584.591547] CR2: 55b9092b6048 CR3: 00022f962004 CR4: 
003606e0
[324584.591550] DR0:  DR1:  DR2: 

[324584.591550] DR3:  DR6: fffe0ff0 DR7: 
0400
[324584.591551] Call Trace:
[324584.591605]  amdgpu_ttm_fini+0xc7/0x230 [amdgpu]
[324584.591657]  amdgpu_bo_fini+0x12/0x40 [amdgpu]
[324584.591717]  gmc_v10_0_sw_fini+0x32/0x40 [amdgpu]
[324584.591767]  amdgpu_device_fini+0x373/0x560 [amdgpu]
[324584.591831]  amdgpu_driver_unload_kms+0x43/0x70 [amdgpu]
[324584.591879]  amdgpu_pci_remove+0x3b/0x60 [amdgpu]
[324584.591950]  pci_device_remove+0x3e/0xc0
[324584.591981]  device_release_driver_internal+0xe0/0x1b0
[324584.591982]  driver_detach+0x49/0x90
[324584.591984]  bus_remove_driver+0x59/0xd0
[324584.591985]  driver_unregister+0x2c/0x40
[324584.591986]  pci_unregister_driver+0x22/0xa0
[324584.592071]  amdgpu_exit+0x15/0x629 [amdgpu]
[324584.592121]  __x64_sys_delete_module+0x146/0x290
[324584.592148]  do_syscall_64+0x5a/0x130
[324584.592165]  entry_SYSCALL_64_after_hwframe+0x44/0xa9
[324584.592183] RIP: 0033:0x7fea6f5e4047
[324584.592185] Code: 73 01 c3 48 8b 0d 41 8e 2c 00 f7 d8 64 89 01 48 83 c8 ff c3 66 
2e 0f 1f 84 00 00 00 00 00 0f 1f 44 00 00 b8 b0 00 00 00 0f 05 <48> 3d 01 f0 ff 
ff 73 01 c3 48 8b 0d 11 8e 2c 00 f7 d8 64 89 01 48
[324584.592186] RSP: 002b:7ffdfa3d75a8 EFLAGS: 0206 ORIG_RAX: 
00b0
[324584.592187] RAX: ffda RBX: 55b9092ae120 RCX: 
7fea6f5e4047
[324584.592187] RDX:  RSI: 0800 RDI: 
55b9092ae188
[324584.592188] RBP: 55b9092ae120 R08: 7ffdfa3d6551 R09: 

[324584.592188] R10: 7fea6f660c40 R11: 0206 R12: 
55b9092ae188
[324584.592189] R13: 0001 R14: 55b9092ae188 R15: 
7ffdfa3d8990
[324584.592190] ---[ end trace 4ea03bb6309ad6c3 ]---

Signed-off-by: Jingwen Chen 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 7 +--
  1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
index 4f10c4529840..afdc2c48c060 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
@@ -106,7 +106,7 @@ int 

[PATCH] drm/amd/amdgpu: destroy pinned gem obj according to refcount

[Jingwen Chen]

[Why]
the fb gem object is get for 4 times when amdgpu_display_framebuffer_init,
while this object is put for less than 4 times. This can lead to warning trace
when unloading amdgpu

[How]
put gem object according to refcount in amdgpufb_destroy_pinned_object

Warning trace attached:
[324584.505752] amdgpu :00:07.0: amdgpu: amdgpu: finishing device.
[324584.510737] [drm] clean up the vf2pf work item
[324584.532205] [drm] free PSP TMR buffer
[324584.591206] [ cut here ]
[324584.591449] WARNING: CPU: 1 PID: 5800 at 
/var/lib/dkms/amdgpu/5.11.11.119-1259830/build/include/drm/ttm/ttm_resource.h:196
 amdgpu_vram_mgr_fini+0x72/0x150 [amdgpu]
[324584.591450] Modules linked in: amdgpu(OE-) amd_iommu_v2 amdttm(OE) 
amd_sched(OE) amdkcl(OE) drm_kms_helper drm i2c_algo_bit fb_sys_fops 
syscopyarea sysfillrect sysimgblt intel_rapl_msr intel_rapl_common kvm 
irqbypass snd_hda_codec_generic ledtrig_audio snd_hda_intel snd_intel_dspcfg 
crct10dif_pclmul snd_hda_codec crc32_pclmul ghash_clmulni_intel snd_hda_core 
snd_hwdep snd_pcm aesni_intel aes_x86_64 crypto_simd snd_seq_midi cryptd 
snd_seq_midi_event glue_helper snd_rawmidi snd_seq input_leds snd_seq_device 
serio_raw snd_timer snd mac_hid soundcore qemu_fw_cfg sch_fq_codel binfmt_misc 
parport_pc ppdev lp parport ip_tables x_tables autofs4 8139too psmouse floppy 
8139cp mii i2c_piix4 pata_acpi [last unloaded: amd_iommu_v2]
[324584.591479] CPU: 1 PID: 5800 Comm: modprobe Tainted: GW  OE 
5.3.0-61-generic #55~18.04.1-Ubuntu
[324584.591480] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 
1.10.2-1ubuntu1 04/01/2014
[324584.591538] RIP: 0010:amdgpu_vram_mgr_fini+0x72/0x150 [amdgpu]
[324584.591540] Code: 00 00 41 c6 84 24 40 5d 00 00 00 4c 89 f6 e8 85 9d fa ff 
85 c0 74 17 5b 41 5c 41 5d 41 5e 41 5f 5d c3 4c 89 ff e8 51 d3 a9 dc <0f> 0b eb 
c3 4d 8d b4 24 90 5e 00 00 4d 8d ac 24 98 5e 00 00 4c 89
[324584.591541] RSP: 0018:9ce444e7fce8 EFLAGS: 00010282
[324584.591542] RAX: 0024 RBX: 8e86b02c5d60 RCX: 

[324584.591543] RDX:  RSI: 8e86b7a97448 RDI: 
8e86b7a97448
[324584.591543] RBP: 9ce444e7fd10 R08: 0405 R09: 
0004
[324584.591544] R10: 9ce444e7fcd0 R11: 0001 R12: 
8e86b02c
[324584.591544] R13: 8e86b02c5da0 R14: 8e86b02c5d40 R15: 
c0c702a8
[324584.591545] FS:  7fea6fac0540() GS:8e86b7a8() 
knlGS:
[324584.591546] CS:  0010 DS:  ES:  CR0: 80050033
[324584.591547] CR2: 55b9092b6048 CR3: 00022f962004 CR4: 
003606e0
[324584.591550] DR0:  DR1:  DR2: 

[324584.591550] DR3:  DR6: fffe0ff0 DR7: 
0400
[324584.591551] Call Trace:
[324584.591605]  amdgpu_ttm_fini+0xc7/0x230 [amdgpu]
[324584.591657]  amdgpu_bo_fini+0x12/0x40 [amdgpu]
[324584.591717]  gmc_v10_0_sw_fini+0x32/0x40 [amdgpu]
[324584.591767]  amdgpu_device_fini+0x373/0x560 [amdgpu]
[324584.591831]  amdgpu_driver_unload_kms+0x43/0x70 [amdgpu]
[324584.591879]  amdgpu_pci_remove+0x3b/0x60 [amdgpu]
[324584.591950]  pci_device_remove+0x3e/0xc0
[324584.591981]  device_release_driver_internal+0xe0/0x1b0
[324584.591982]  driver_detach+0x49/0x90
[324584.591984]  bus_remove_driver+0x59/0xd0
[324584.591985]  driver_unregister+0x2c/0x40
[324584.591986]  pci_unregister_driver+0x22/0xa0
[324584.592071]  amdgpu_exit+0x15/0x629 [amdgpu]
[324584.592121]  __x64_sys_delete_module+0x146/0x290
[324584.592148]  do_syscall_64+0x5a/0x130
[324584.592165]  entry_SYSCALL_64_after_hwframe+0x44/0xa9
[324584.592183] RIP: 0033:0x7fea6f5e4047
[324584.592185] Code: 73 01 c3 48 8b 0d 41 8e 2c 00 f7 d8 64 89 01 48 83 c8 ff 
c3 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 44 00 00 b8 b0 00 00 00 0f 05 <48> 3d 01 
f0 ff ff 73 01 c3 48 8b 0d 11 8e 2c 00 f7 d8 64 89 01 48
[324584.592186] RSP: 002b:7ffdfa3d75a8 EFLAGS: 0206 ORIG_RAX: 
00b0
[324584.592187] RAX: ffda RBX: 55b9092ae120 RCX: 
7fea6f5e4047
[324584.592187] RDX:  RSI: 0800 RDI: 
55b9092ae188
[324584.592188] RBP: 55b9092ae120 R08: 7ffdfa3d6551 R09: 

[324584.592188] R10: 7fea6f660c40 R11: 0206 R12: 
55b9092ae188
[324584.592189] R13: 0001 R14: 55b9092ae188 R15: 
7ffdfa3d8990
[324584.592190] ---[ end trace 4ea03bb6309ad6c3 ]---

Signed-off-by: Jingwen Chen 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
index 4f10c4529840..afdc2c48c060 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
@@ -106,7 +106,7 @@ int amdgpu_align_pitch(struct amdgpu_device *adev, int 
width, int cpp, bool tile
 static void amdgpufb_destroy_pinned_object(struct drm_gem_object *gobj)
 {
  

Re: [PATCH] drm/amdgpu: optimize to drop preamble IB for old GPUs

[Christian König]

Am 17.05.21 um 08:51 schrieb Chen, Jiansong (Simon):

[AMD Official Use Only]

Doesn't  current solution always enable the optimization in a safe and more 
clear way?


No, we also need this for gfx8 where gfxoff is currently not implemented.

Additional to that we mix common frontend handling into the backend with 
this approach.


But you could clean up the code in amdgpu_ib_schedule() quite a bit.

Regards,
Christian.


1. for gfx8/9/10 we use load_ce_ram in context_control to control the 
optimization.
2. for gfx6/7, we directly drop the preamble ib.

Regards,
Jiansong
-Original Message-
From: Koenig, Christian 
Sent: Monday, May 17, 2021 2:42 PM
To: Chen, Jiansong (Simon) ; 
amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu: optimize to drop preamble IB for old GPUs

Well NAK, as discussed checking the global flag is more flexible since it will 
still enable the preamble drop when gfxoff is disabled.

Christian.

Am 17.05.21 um 06:39 schrieb Jiansong Chen:

The optimization is safe for old GPUs and can help performance.

Signed-off-by: Jiansong Chen 
Change-Id: Id3b1250f1fe46dddbe8498894fb97e9753b7cafe
---
   drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 6 ++
   drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 6 ++
   2 files changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index 3a8d52a54873..c915cc439484 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -1873,6 +1873,12 @@ static void gfx_v6_0_ring_emit_ib(struct amdgpu_ring 
*ring,
   amdgpu_ring_write(ring, 0);
   }

+ /* drop the CE preamble IB for the same context */
+ if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) &&
+ !(flags & AMDGPU_HAVE_CTX_SWITCH) &&
+ !(flags & AMDGPU_PREAMBLE_IB_PRESENT_FIRST))
+ return;
+
   if (ib->flags & AMDGPU_IB_FLAG_CE)
   header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
   else
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index c35fdd2ef2d4..6d9ccae48024 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -2269,6 +2269,12 @@ static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring 
*ring,
   amdgpu_ring_write(ring, 0);
   }

+ /* drop the CE preamble IB for the same context */
+ if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) &&
+ !(flags & AMDGPU_HAVE_CTX_SWITCH) &&
+ !(flags & AMDGPU_PREAMBLE_IB_PRESENT_FIRST))
+ return;
+
   if (ib->flags & AMDGPU_IB_FLAG_CE)
   header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
   else

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx


___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm/amdgpu: Expose rfc4122 compliant UUID

[Christian König]

Am 17.05.21 um 07:54 schrieb Jiawei Gu:

Introduce an RFC 4122 compliant UUID for the GPUs derived
from the unique GPU serial number (from Vega10) on gpus.
Where this serial number is not available, use a compliant
random UUID.

For virtualization, the unique ID is passed by the host driver
in the PF2VF structure.


The question is why this is useful.



Signed-off-by: Jiawei Gu 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu.h | 36 
  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c  | 96 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c|  4 +
  drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h |  4 +-
  drivers/gpu/drm/amd/amdgpu/nv.c |  5 ++
  drivers/gpu/drm/amd/amdgpu/nv.h |  3 +
  6 files changed, 146 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 3147c1c935c8..ad6d4b55be6c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -802,6 +802,40 @@ struct amd_powerplay {
  (rid == 0x01) || \
  (rid == 0x10
  
+union amdgpu_uuid_info {

+   struct {
+   union {
+   struct {
+   uint32_t did: 16;
+   uint32_t fcn: 8;
+   uint32_t asic_7 : 8;
+   };


Bitfields are not allowed in structures used for communication with 
hardware or uAPI.


Regards,
Christian.


+   uint32_t time_low;
+   };
+
+   struct {
+   uint32_t time_mid  : 16;
+   uint32_t time_high : 12;
+   uint32_t version   : 4;
+   };
+
+   struct {
+   struct {
+   uint8_t clk_seq_hi : 6;
+   uint8_t variant: 2;
+   };
+   union {
+   uint8_t clk_seq_low;
+   uint8_t asic_6;
+   };
+   uint16_t asic_4;
+   };
+
+   uint32_t asic_0;
+   };
+   char as_char[16];
+};
+
  #define AMDGPU_RESET_MAGIC_NUM 64
  #define AMDGPU_MAX_DF_PERFMONS 4
  struct amdgpu_device {
@@ -1074,6 +1108,8 @@ struct amdgpu_device {
charproduct_name[32];
charserial[20];
  
+	union amdgpu_uuid_info uuid_info;

+
struct amdgpu_autodump  autodump;
  
  	atomic_t			throttling_logging_enabled;

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 7c6c435e5d02..079841e1cb52 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -37,6 +37,7 @@
  #include 
  #include 
  #include 
+#include 
  #include "amdgpu.h"
  #include "amdgpu_trace.h"
  #include "amdgpu_i2c.h"
@@ -3239,11 +3240,104 @@ static int 
amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev)
return ret;
  }
  
+static bool amdgpu_is_uuid_info_empty(union amdgpu_uuid_info *uuid_info)

+{
+   return (uuid_info->time_low== 0 &&
+   uuid_info->time_mid== 0 &&
+   uuid_info->time_high   == 0 &&
+   uuid_info->version == 0 &&
+   uuid_info->clk_seq_hi  == 0 &&
+   uuid_info->variant == 0 &&
+   uuid_info->clk_seq_low == 0 &&
+   uuid_info->asic_4  == 0 &&
+   uuid_info->asic_0  == 0);
+}
+
+static void amdgpu_gen_uuid_info(union amdgpu_uuid_info *uuid_info,
+   uint64_t serial, uint16_t did, uint8_t idx)
+{
+   uint16_t clk_seq = 0;
+
+   /* Step1: insert clk_seq */
+   uuid_info->clk_seq_low = (uint8_t)clk_seq;
+   uuid_info->clk_seq_hi  = (uint8_t)(clk_seq >> 8) & 0x3F;
+
+   /* Step2: insert did */
+   uuid_info->did = did;
+
+   /* Step3: insert vf idx */
+   uuid_info->fcn = idx;
+
+   /* Step4: insert serial */
+   uuid_info->asic_0 = (uint32_t)serial;
+   uuid_info->asic_4 = (uint16_t)(serial >> 4 * 8) & 0x;
+   uuid_info->asic_6 = (uint8_t)(serial >> 6 * 8) & 0xFF;
+   uuid_info->asic_7 = (uint8_t)(serial >> 7 * 8) & 0xFF;
+
+   /* Step5: insert version */
+   uuid_info->version = 1;
+   /* Step6: insert variant */
+   uuid_info->variant = 2;
+}
+
+/* byte reverse random uuid */
+static void amdgpu_gen_uuid_random(union amdgpu_uuid_info *uuid_info)
+{
+   char b0, b1;
+   int i;
+
+   generate_random_uuid(uuid_info->as_char);
+   for (i = 0; i < 8; i++) {
+   b0 = uuid_info->as_char[i];
+   b1 = uuid_info->as_char[16-i];
+

RE: [PATCH] drm/amdgpu: optimize to drop preamble IB for old GPUs

[Chen, Jiansong (Simon)]

[AMD Official Use Only]

Doesn't  current solution always enable the optimization in a safe and more 
clear way?
1. for gfx8/9/10 we use load_ce_ram in context_control to control the 
optimization.
2. for gfx6/7, we directly drop the preamble ib.

Regards,
Jiansong
-Original Message-
From: Koenig, Christian 
Sent: Monday, May 17, 2021 2:42 PM
To: Chen, Jiansong (Simon) ; 
amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu: optimize to drop preamble IB for old GPUs

Well NAK, as discussed checking the global flag is more flexible since it will 
still enable the preamble drop when gfxoff is disabled.

Christian.

Am 17.05.21 um 06:39 schrieb Jiansong Chen:
> The optimization is safe for old GPUs and can help performance.
>
> Signed-off-by: Jiansong Chen 
> Change-Id: Id3b1250f1fe46dddbe8498894fb97e9753b7cafe
> ---
>   drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 6 ++
>   drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 6 ++
>   2 files changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> index 3a8d52a54873..c915cc439484 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> @@ -1873,6 +1873,12 @@ static void gfx_v6_0_ring_emit_ib(struct amdgpu_ring 
> *ring,
>   amdgpu_ring_write(ring, 0);
>   }
>
> + /* drop the CE preamble IB for the same context */
> + if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) &&
> + !(flags & AMDGPU_HAVE_CTX_SWITCH) &&
> + !(flags & AMDGPU_PREAMBLE_IB_PRESENT_FIRST))
> + return;
> +
>   if (ib->flags & AMDGPU_IB_FLAG_CE)
>   header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
>   else
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> index c35fdd2ef2d4..6d9ccae48024 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> @@ -2269,6 +2269,12 @@ static void gfx_v7_0_ring_emit_ib_gfx(struct 
> amdgpu_ring *ring,
>   amdgpu_ring_write(ring, 0);
>   }
>
> + /* drop the CE preamble IB for the same context */
> + if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) &&
> + !(flags & AMDGPU_HAVE_CTX_SWITCH) &&
> + !(flags & AMDGPU_PREAMBLE_IB_PRESENT_FIRST))
> + return;
> +
>   if (ib->flags & AMDGPU_IB_FLAG_CE)
>   header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
>   else

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