Re: [PATCH] drm/amdgpu: Fix a BUG_ON due to resv trylock fails

[Felix Kuehling]

When the BO gets individualized, there is an assumption that nobody is
accessing it any more. See this comment in ttm_bo_individualize_resv:

/* This works because the BO is about to be destroyed and nobody
 * reference it any more. The only tricky case is the trylock on
 * the resv object while holding the lru_lock.
 */

That is violated when the BO is still being swapped out at this stage.
You can kind of paper that over by taking the LRU lock. But there are
probably other race conditions going on when the reservation gets
swapped by "individualize" during an eviction.

I think to avoid all that TTM needs to make sure that the BO is no
longer on the LRU list when it gets individualized.

Regards,
  Felix


Am 2021-05-21 um 10:11 p.m. schrieb xinhui pan:
> The reservation object might be locked again by evict/swap after
> individualized. The race is like below.
> cpu 0   cpu 1
> BO releaseBO evict or swap
>   lock lru_lock
> ttm_bo_individualize_resv {resv = &_resv}
> ttm_bo_evict_swapout_allowable
> dma_resv_trylock(resv)
> ->release_notify() {BUG_ON(!trylock(resv))}
> if (!ttm_bo_get_unless_zero))
> dma_resv_unlock(resv)
>   unlock lru_lock
> To fix it simply, let's acquire lru_lock before resv trylock to avoid
> the race above.
>
> Signed-off-by: xinhui pan 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> index 928e8d57cd08..8f6da0034db9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> @@ -318,7 +318,9 @@ int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct 
> amdgpu_bo *bo)
>   ef = container_of(dma_fence_get(&info->eviction_fence->base),
>   struct amdgpu_amdkfd_fence, base);
>  
> + spin_lock(&bo->tbo.bdev->lru_lock);
>   BUG_ON(!dma_resv_trylock(bo->tbo.base.resv));
> + spin_unlock(&bo->tbo.bdev->lru_lock);
>   ret = amdgpu_amdkfd_remove_eviction_fence(bo, ef);
>   dma_resv_unlock(bo->tbo.base.resv);
>  
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[PATCH] drm/amdgpu: Fix a BUG_ON due to resv trylock fails

[xinhui pan]

The reservation object might be locked again by evict/swap after
individualized. The race is like below.
cpu 0   cpu 1
BO release  BO evict or swap
lock lru_lock
ttm_bo_individualize_resv {resv = &_resv}
ttm_bo_evict_swapout_allowable
dma_resv_trylock(resv)
->release_notify() {BUG_ON(!trylock(resv))}
if (!ttm_bo_get_unless_zero))
dma_resv_unlock(resv)
unlock lru_lock
To fix it simply, let's acquire lru_lock before resv trylock to avoid
the race above.

Signed-off-by: xinhui pan 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index 928e8d57cd08..8f6da0034db9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -318,7 +318,9 @@ int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct 
amdgpu_bo *bo)
ef = container_of(dma_fence_get(&info->eviction_fence->base),
struct amdgpu_amdkfd_fence, base);
 
+   spin_lock(&bo->tbo.bdev->lru_lock);
BUG_ON(!dma_resv_trylock(bo->tbo.base.resv));
+   spin_unlock(&bo->tbo.bdev->lru_lock);
ret = amdgpu_amdkfd_remove_eviction_fence(bo, ef);
dma_resv_unlock(bo->tbo.base.resv);
 
-- 
2.25.1

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回复: [PATCH] drm/amdgpu: Use dma_resv_lock instead in BO release_notify

[Pan, Xinhui]

[AMD Official Use Only]

Oh, sorry for that. I notice the lockdep warning too.
I just think we use trylock elsewhere because we hold the lru_lock mostly.
So I think we can do something like below. Let me verify it later.

@@ -318,7 +318,9 @@ int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct 
amdgpu_bo *bo)
ef = container_of(dma_fence_get(&info->eviction_fence->base),
struct amdgpu_amdkfd_fence, base);

+   spin_lock(&bo->tbo.bdev->lru_lock);
BUG_ON(!dma_resv_trylock(bo->tbo.base.resv));
+   spin_unlock(&bo->tbo.bdev->lru_lock);
ret = amdgpu_amdkfd_remove_eviction_fence(bo, ef);
dma_resv_unlock(bo->tbo.base.resv);



发件人: Kuehling, Felix 
发送时间: 2021年5月22日 2:24
收件人: Pan, Xinhui; amd-gfx@lists.freedesktop.org
抄送: Deucher, Alexander; Koenig, Christian
主题: Re: [PATCH] drm/amdgpu: Use dma_resv_lock instead in BO release_notify


Am 2021-05-21 um 1:26 a.m. schrieb xinhui pan:
> The reservation object might be locked again by evict/swap after
> individualized. The race is like below.
> cpu 0 cpu 1
> BO releaseBO evict or swap
> ttm_bo_individualize_resv {resv = &_resv}
>   ttm_bo_evict_swapout_allowable
>   dma_resv_trylock(resv)
> ->release_notify() {BUG_ON(!trylock(resv))}
>   if (!ttm_bo_get_unless_zero))
>   dma_resv_unlock(resv)
> Actually this is not a bug if trylock fails. So use dma_resv_lock
> instead.

Please test this with LOCKDEP enabled. I believe the trylock here was
needed to avoid potential deadlocks. Maybe Christian can fill in more
details.

Regards,
  Felix


>
> Signed-off-by: xinhui pan 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> index 928e8d57cd08..beacb46265f8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> @@ -318,7 +318,7 @@ int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct 
> amdgpu_bo *bo)
>   ef = container_of(dma_fence_get(&info->eviction_fence->base),
>   struct amdgpu_amdkfd_fence, base);
>
> - BUG_ON(!dma_resv_trylock(bo->tbo.base.resv));
> + dma_resv_lock(bo->tbo.base.resv, NULL);
>   ret = amdgpu_amdkfd_remove_eviction_fence(bo, ef);
>   dma_resv_unlock(bo->tbo.base.resv);
>
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Re: [PATCH] drm/amd/amdkfd: Drop unnecessary NULL check after container_of

[Felix Kuehling]

Am 2021-05-21 um 11:02 a.m. schrieb Guenter Roeck:
> The first parameter passed to container_of() is the pointer to the work
> structure passed to the worker and never NULL. The NULL check on the
> result of container_of() is therefore unnecessary and misleading.
> Remove it.
>
> This change was made automatically with the following Coccinelle script.
>
> @@
> type t;
> identifier v;
> statement s;
> @@
>
> <+...
> (
>   t v = container_of(...);
> |
>   v = container_of(...);
> )
>   ...
>   when != v
> - if (\( !v \| v == NULL \) ) s
> ...+>
>
> Signed-off-by: Guenter Roeck 

Thank you. The patch looks good to me. I caught a few such pointless
checks in code review but must have missed this one. I'll apply your
patch to amd-staging-drm-next. The patch is

Reviewed-by: Felix Kuehling 


> ---
>  drivers/gpu/drm/amd/amdkfd/kfd_process.c | 2 --
>  1 file changed, 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c 
> b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
> index 5b6c5669c03d..2f8d352e0069 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
> @@ -110,8 +110,6 @@ static void kfd_sdma_activity_worker(struct work_struct 
> *work)
>  
>   workarea = container_of(work, struct kfd_sdma_activity_handler_workarea,
>   sdma_activity_work);
> - if (!workarea)
> - return;
>  
>   pdd = workarea->pdd;
>   if (!pdd)
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RE: [PATCH 2/6] drm/amd/pm: Add arcturus throttler translation

[Sider, Graham]

Right, that all makes sense. I'm fine with either of these options. Thanks for 
the insights -- I'll give this a bit more thought and get back to you.

Best,
Graham

-Original Message-
From: Alex Deucher  
Sent: Friday, May 21, 2021 5:50 PM
To: Sider, Graham 
Cc: amd-gfx list ; Kasiviswanathan, Harish 
; Sakhnovitch, Elena (Elen) 

Subject: Re: [PATCH 2/6] drm/amd/pm: Add arcturus throttler translation

[CAUTION: External Email]

On Fri, May 21, 2021 at 5:47 PM Alex Deucher  wrote:
>
> On Fri, May 21, 2021 at 5:32 PM Sider, Graham  wrote:
> >
> > Would this be referring to tools that may parse 
> > /sys/class/.../device/gpu_metrics or the actual gpu_metrics_vX_Y structs? 
> > For the latter, if there are tools that parse dependent on version vX_Y, I 
> > agree that we would not want to break those.
> >
> > Since most ASICs are using different version currently, we would have to 
> > create a duplicate struct for each gpu_metrics version currently being 
> > used, unless I'm misunderstanding. I'm not sure if this is what you had in 
> > mind - let me know.
> >
>
> Just update them all to the latest version.  The newer ones are just 
> supersets of the previous versions.  I think a newer revision just 
> went in in the last day or two for some additional new data, you can 
> probably just piggy back on that since the code is not upstream yet.

Another option would be to leave the current throttle status as is, and add a 
new one that provides the standardized format.  Not sure if there is much value 
in having both though.  That said, we could increase the size of the new one to 
64 bits to accommodate future throttle status bits.

Alex

>
> Alex
>
>
> > Best,
> > Graham
> >
> > -Original Message-
> > From: Alex Deucher 
> > Sent: Friday, May 21, 2021 4:15 PM
> > To: Sider, Graham 
> > Cc: amd-gfx list ; Kasiviswanathan, 
> > Harish ; Sakhnovitch, Elena (Elen) 
> > 
> > Subject: Re: [PATCH 2/6] drm/amd/pm: Add arcturus throttler 
> > translation
> >
> > [CAUTION: External Email]
> >
> > On Fri, May 21, 2021 at 1:39 PM Sider, Graham  wrote:
> > >
> > > Hi Alex,
> > >
> > > Are you referring to bumping the gpu_metrics_vX_Y version number? 
> > > Different ASICs are currently using different version numbers already, so 
> > > I'm not sure how feasible this might be (e.g. arcturus ==  
> > > gpu_metrics_v1_1, navi1x == gpu_metrics_v1_3, vangogh == 
> > > gpu_metrics_v2_1).
> > >
> > > Technically speaking no new fields have been added to any of the 
> > > gpu_metrics versions, just a change in representation in the 
> > > throttle_status field. Let me know your thoughts on this.
> > >
> >
> > I don't know if we have any existing tools out there that parse this data, 
> > but if so, they would interpret it incorrectly after this change.  If we 
> > bump the version, at least the tools will know how to handle it.
> >
> > Alex
> >
> >
> > > Best,
> > > Graham
> > >
> > > -Original Message-
> > > From: Alex Deucher 
> > > Sent: Friday, May 21, 2021 10:27 AM
> > > To: Sider, Graham 
> > > Cc: amd-gfx list ; Kasiviswanathan, 
> > > Harish ; Sakhnovitch, Elena (Elen) 
> > > 
> > > Subject: Re: [PATCH 2/6] drm/amd/pm: Add arcturus throttler 
> > > translation
> > >
> > > [CAUTION: External Email]
> > >
> > > General comment on the patch series, do you want to bump the metrics 
> > > table version since the meaning of the throttler status has changed?
> > >
> > > Alex
> > >
> > > On Thu, May 20, 2021 at 10:30 AM Graham Sider  
> > > wrote:
> > > >
> > > > Perform dependent to independent throttle status translation for 
> > > > arcturus.
> > > > ---
> > > >  .../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 62
> > > > ---
> > > >  1 file changed, 53 insertions(+), 9 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> > > > b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> > > > index 1735a96dd307..7c01c0bf2073 100644
> > > > --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> > > > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> > > > @@ -540,6 +540,49 @@ static int arcturus_freqs_in_same_level(int32_t 
> > > > frequency1,
> > > > return (abs(frequency1 - frequency2) <= EPSILON);  }
> > > >
> > > > +static uint32_t arcturus_get_indep_throttler_status(
> > > > +   unsigned long
> > > > +dep_throttler_status) {
> > > > +   unsigned long indep_throttler_status = 0;
> > > > +
> > > > +   __assign_bit(INDEP_THROTTLER_TEMP_EDGE_BIT, 
> > > > &indep_throttler_status,
> > > > + test_bit(THROTTLER_TEMP_EDGE_BIT, 
> > > > &dep_throttler_status));
> > > > +   __assign_bit(INDEP_THROTTLER_TEMP_HOTSPOT_BIT, 
> > > > &indep_throttler_status,
> > > > + test_bit(THROTTLER_TEMP_HOTSPOT_BIT, 
> > > > &dep_throttler_status));
> > > > +   __assign_bit(INDEP_THROTTLER_TEMP_MEM_BIT, 
> > > > &indep_throttler_status,
> > > > + test_bit(THR

Re: [PATCH 2/6] drm/amd/pm: Add arcturus throttler translation

[Alex Deucher]

On Fri, May 21, 2021 at 5:47 PM Alex Deucher  wrote:
>
> On Fri, May 21, 2021 at 5:32 PM Sider, Graham  wrote:
> >
> > Would this be referring to tools that may parse 
> > /sys/class/.../device/gpu_metrics or the actual gpu_metrics_vX_Y structs? 
> > For the latter, if there are tools that parse dependent on version vX_Y, I 
> > agree that we would not want to break those.
> >
> > Since most ASICs are using different version currently, we would have to 
> > create a duplicate struct for each gpu_metrics version currently being 
> > used, unless I'm misunderstanding. I'm not sure if this is what you had in 
> > mind - let me know.
> >
>
> Just update them all to the latest version.  The newer ones are just
> supersets of the previous versions.  I think a newer revision just
> went in in the last day or two for some additional new data, you can
> probably just piggy back on that since the code is not upstream yet.

Another option would be to leave the current throttle status as is,
and add a new one that provides the standardized format.  Not sure if
there is much value in having both though.  That said, we could
increase the size of the new one to 64 bits to accommodate future
throttle status bits.

Alex

>
> Alex
>
>
> > Best,
> > Graham
> >
> > -Original Message-
> > From: Alex Deucher 
> > Sent: Friday, May 21, 2021 4:15 PM
> > To: Sider, Graham 
> > Cc: amd-gfx list ; Kasiviswanathan, Harish 
> > ; Sakhnovitch, Elena (Elen) 
> > 
> > Subject: Re: [PATCH 2/6] drm/amd/pm: Add arcturus throttler translation
> >
> > [CAUTION: External Email]
> >
> > On Fri, May 21, 2021 at 1:39 PM Sider, Graham  wrote:
> > >
> > > Hi Alex,
> > >
> > > Are you referring to bumping the gpu_metrics_vX_Y version number? 
> > > Different ASICs are currently using different version numbers already, so 
> > > I'm not sure how feasible this might be (e.g. arcturus ==  
> > > gpu_metrics_v1_1, navi1x == gpu_metrics_v1_3, vangogh == 
> > > gpu_metrics_v2_1).
> > >
> > > Technically speaking no new fields have been added to any of the 
> > > gpu_metrics versions, just a change in representation in the 
> > > throttle_status field. Let me know your thoughts on this.
> > >
> >
> > I don't know if we have any existing tools out there that parse this data, 
> > but if so, they would interpret it incorrectly after this change.  If we 
> > bump the version, at least the tools will know how to handle it.
> >
> > Alex
> >
> >
> > > Best,
> > > Graham
> > >
> > > -Original Message-
> > > From: Alex Deucher 
> > > Sent: Friday, May 21, 2021 10:27 AM
> > > To: Sider, Graham 
> > > Cc: amd-gfx list ; Kasiviswanathan,
> > > Harish ; Sakhnovitch, Elena (Elen)
> > > 
> > > Subject: Re: [PATCH 2/6] drm/amd/pm: Add arcturus throttler
> > > translation
> > >
> > > [CAUTION: External Email]
> > >
> > > General comment on the patch series, do you want to bump the metrics 
> > > table version since the meaning of the throttler status has changed?
> > >
> > > Alex
> > >
> > > On Thu, May 20, 2021 at 10:30 AM Graham Sider  
> > > wrote:
> > > >
> > > > Perform dependent to independent throttle status translation for
> > > > arcturus.
> > > > ---
> > > >  .../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 62
> > > > ---
> > > >  1 file changed, 53 insertions(+), 9 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> > > > b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> > > > index 1735a96dd307..7c01c0bf2073 100644
> > > > --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> > > > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> > > > @@ -540,6 +540,49 @@ static int arcturus_freqs_in_same_level(int32_t 
> > > > frequency1,
> > > > return (abs(frequency1 - frequency2) <= EPSILON);  }
> > > >
> > > > +static uint32_t arcturus_get_indep_throttler_status(
> > > > +   unsigned long
> > > > +dep_throttler_status) {
> > > > +   unsigned long indep_throttler_status = 0;
> > > > +
> > > > +   __assign_bit(INDEP_THROTTLER_TEMP_EDGE_BIT, 
> > > > &indep_throttler_status,
> > > > + test_bit(THROTTLER_TEMP_EDGE_BIT, 
> > > > &dep_throttler_status));
> > > > +   __assign_bit(INDEP_THROTTLER_TEMP_HOTSPOT_BIT, 
> > > > &indep_throttler_status,
> > > > + test_bit(THROTTLER_TEMP_HOTSPOT_BIT, 
> > > > &dep_throttler_status));
> > > > +   __assign_bit(INDEP_THROTTLER_TEMP_MEM_BIT, 
> > > > &indep_throttler_status,
> > > > + test_bit(THROTTLER_TEMP_MEM_BIT, 
> > > > &dep_throttler_status));
> > > > +   __assign_bit(INDEP_THROTTLER_TEMP_VR_GFX_BIT, 
> > > > &indep_throttler_status,
> > > > + test_bit(THROTTLER_TEMP_VR_GFX_BIT, 
> > > > &dep_throttler_status));
> > > > +   __assign_bit(INDEP_THROTTLER_TEMP_VR_MEM_BIT, 
> > > > &indep_throttler_status,
> > > > + test_bit(THROTTLER_TEMP_VR_MEM_BIT, 
> > > > &dep_throttler_status));
> > > > +   __

Re: [PATCH 2/6] drm/amd/pm: Add arcturus throttler translation

[Alex Deucher]

On Fri, May 21, 2021 at 5:32 PM Sider, Graham  wrote:
>
> Would this be referring to tools that may parse 
> /sys/class/.../device/gpu_metrics or the actual gpu_metrics_vX_Y structs? For 
> the latter, if there are tools that parse dependent on version vX_Y, I agree 
> that we would not want to break those.
>
> Since most ASICs are using different version currently, we would have to 
> create a duplicate struct for each gpu_metrics version currently being used, 
> unless I'm misunderstanding. I'm not sure if this is what you had in mind - 
> let me know.
>

Just update them all to the latest version.  The newer ones are just
supersets of the previous versions.  I think a newer revision just
went in in the last day or two for some additional new data, you can
probably just piggy back on that since the code is not upstream yet.

Alex


> Best,
> Graham
>
> -Original Message-
> From: Alex Deucher 
> Sent: Friday, May 21, 2021 4:15 PM
> To: Sider, Graham 
> Cc: amd-gfx list ; Kasiviswanathan, Harish 
> ; Sakhnovitch, Elena (Elen) 
> 
> Subject: Re: [PATCH 2/6] drm/amd/pm: Add arcturus throttler translation
>
> [CAUTION: External Email]
>
> On Fri, May 21, 2021 at 1:39 PM Sider, Graham  wrote:
> >
> > Hi Alex,
> >
> > Are you referring to bumping the gpu_metrics_vX_Y version number? Different 
> > ASICs are currently using different version numbers already, so I'm not 
> > sure how feasible this might be (e.g. arcturus ==  gpu_metrics_v1_1, navi1x 
> > == gpu_metrics_v1_3, vangogh == gpu_metrics_v2_1).
> >
> > Technically speaking no new fields have been added to any of the 
> > gpu_metrics versions, just a change in representation in the 
> > throttle_status field. Let me know your thoughts on this.
> >
>
> I don't know if we have any existing tools out there that parse this data, 
> but if so, they would interpret it incorrectly after this change.  If we bump 
> the version, at least the tools will know how to handle it.
>
> Alex
>
>
> > Best,
> > Graham
> >
> > -Original Message-
> > From: Alex Deucher 
> > Sent: Friday, May 21, 2021 10:27 AM
> > To: Sider, Graham 
> > Cc: amd-gfx list ; Kasiviswanathan,
> > Harish ; Sakhnovitch, Elena (Elen)
> > 
> > Subject: Re: [PATCH 2/6] drm/amd/pm: Add arcturus throttler
> > translation
> >
> > [CAUTION: External Email]
> >
> > General comment on the patch series, do you want to bump the metrics table 
> > version since the meaning of the throttler status has changed?
> >
> > Alex
> >
> > On Thu, May 20, 2021 at 10:30 AM Graham Sider  wrote:
> > >
> > > Perform dependent to independent throttle status translation for
> > > arcturus.
> > > ---
> > >  .../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 62
> > > ---
> > >  1 file changed, 53 insertions(+), 9 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> > > b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> > > index 1735a96dd307..7c01c0bf2073 100644
> > > --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> > > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> > > @@ -540,6 +540,49 @@ static int arcturus_freqs_in_same_level(int32_t 
> > > frequency1,
> > > return (abs(frequency1 - frequency2) <= EPSILON);  }
> > >
> > > +static uint32_t arcturus_get_indep_throttler_status(
> > > +   unsigned long
> > > +dep_throttler_status) {
> > > +   unsigned long indep_throttler_status = 0;
> > > +
> > > +   __assign_bit(INDEP_THROTTLER_TEMP_EDGE_BIT, 
> > > &indep_throttler_status,
> > > + test_bit(THROTTLER_TEMP_EDGE_BIT, 
> > > &dep_throttler_status));
> > > +   __assign_bit(INDEP_THROTTLER_TEMP_HOTSPOT_BIT, 
> > > &indep_throttler_status,
> > > + test_bit(THROTTLER_TEMP_HOTSPOT_BIT, 
> > > &dep_throttler_status));
> > > +   __assign_bit(INDEP_THROTTLER_TEMP_MEM_BIT, 
> > > &indep_throttler_status,
> > > + test_bit(THROTTLER_TEMP_MEM_BIT, 
> > > &dep_throttler_status));
> > > +   __assign_bit(INDEP_THROTTLER_TEMP_VR_GFX_BIT, 
> > > &indep_throttler_status,
> > > + test_bit(THROTTLER_TEMP_VR_GFX_BIT, 
> > > &dep_throttler_status));
> > > +   __assign_bit(INDEP_THROTTLER_TEMP_VR_MEM_BIT, 
> > > &indep_throttler_status,
> > > + test_bit(THROTTLER_TEMP_VR_MEM_BIT, 
> > > &dep_throttler_status));
> > > +   __assign_bit(INDEP_THROTTLER_TEMP_VR_SOC_BIT, 
> > > &indep_throttler_status,
> > > + test_bit(THROTTLER_TEMP_VR_SOC_BIT, 
> > > &dep_throttler_status));
> > > +   __assign_bit(INDEP_THROTTLER_TDC_GFX_BIT, &indep_throttler_status,
> > > + test_bit(THROTTLER_TDC_GFX_BIT, &dep_throttler_status));
> > > +   __assign_bit(INDEP_THROTTLER_TDC_SOC_BIT, &indep_throttler_status,
> > > + test_bit(THROTTLER_TDC_SOC_BIT, &dep_throttler_status));
> > > +   __assign_bit(INDEP_THROTTLER_PPT0_BIT, &indep_throttler_status,
> > > + test_bit(

RE: [PATCH 2/6] drm/amd/pm: Add arcturus throttler translation

[Sider, Graham]

Would this be referring to tools that may parse 
/sys/class/.../device/gpu_metrics or the actual gpu_metrics_vX_Y structs? For 
the latter, if there are tools that parse dependent on version vX_Y, I agree 
that we would not want to break those.

Since most ASICs are using different version currently, we would have to create 
a duplicate struct for each gpu_metrics version currently being used, unless 
I'm misunderstanding. I'm not sure if this is what you had in mind - let me 
know.

Best,
Graham

-Original Message-
From: Alex Deucher  
Sent: Friday, May 21, 2021 4:15 PM
To: Sider, Graham 
Cc: amd-gfx list ; Kasiviswanathan, Harish 
; Sakhnovitch, Elena (Elen) 

Subject: Re: [PATCH 2/6] drm/amd/pm: Add arcturus throttler translation

[CAUTION: External Email]

On Fri, May 21, 2021 at 1:39 PM Sider, Graham  wrote:
>
> Hi Alex,
>
> Are you referring to bumping the gpu_metrics_vX_Y version number? Different 
> ASICs are currently using different version numbers already, so I'm not sure 
> how feasible this might be (e.g. arcturus ==  gpu_metrics_v1_1, navi1x == 
> gpu_metrics_v1_3, vangogh == gpu_metrics_v2_1).
>
> Technically speaking no new fields have been added to any of the gpu_metrics 
> versions, just a change in representation in the throttle_status field. Let 
> me know your thoughts on this.
>

I don't know if we have any existing tools out there that parse this data, but 
if so, they would interpret it incorrectly after this change.  If we bump the 
version, at least the tools will know how to handle it.

Alex


> Best,
> Graham
>
> -Original Message-
> From: Alex Deucher 
> Sent: Friday, May 21, 2021 10:27 AM
> To: Sider, Graham 
> Cc: amd-gfx list ; Kasiviswanathan, 
> Harish ; Sakhnovitch, Elena (Elen) 
> 
> Subject: Re: [PATCH 2/6] drm/amd/pm: Add arcturus throttler 
> translation
>
> [CAUTION: External Email]
>
> General comment on the patch series, do you want to bump the metrics table 
> version since the meaning of the throttler status has changed?
>
> Alex
>
> On Thu, May 20, 2021 at 10:30 AM Graham Sider  wrote:
> >
> > Perform dependent to independent throttle status translation for 
> > arcturus.
> > ---
> >  .../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 62
> > ---
> >  1 file changed, 53 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> > b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> > index 1735a96dd307..7c01c0bf2073 100644
> > --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> > @@ -540,6 +540,49 @@ static int arcturus_freqs_in_same_level(int32_t 
> > frequency1,
> > return (abs(frequency1 - frequency2) <= EPSILON);  }
> >
> > +static uint32_t arcturus_get_indep_throttler_status(
> > +   unsigned long
> > +dep_throttler_status) {
> > +   unsigned long indep_throttler_status = 0;
> > +
> > +   __assign_bit(INDEP_THROTTLER_TEMP_EDGE_BIT, &indep_throttler_status,
> > + test_bit(THROTTLER_TEMP_EDGE_BIT, &dep_throttler_status));
> > +   __assign_bit(INDEP_THROTTLER_TEMP_HOTSPOT_BIT, 
> > &indep_throttler_status,
> > + test_bit(THROTTLER_TEMP_HOTSPOT_BIT, 
> > &dep_throttler_status));
> > +   __assign_bit(INDEP_THROTTLER_TEMP_MEM_BIT, &indep_throttler_status,
> > + test_bit(THROTTLER_TEMP_MEM_BIT, &dep_throttler_status));
> > +   __assign_bit(INDEP_THROTTLER_TEMP_VR_GFX_BIT, 
> > &indep_throttler_status,
> > + test_bit(THROTTLER_TEMP_VR_GFX_BIT, 
> > &dep_throttler_status));
> > +   __assign_bit(INDEP_THROTTLER_TEMP_VR_MEM_BIT, 
> > &indep_throttler_status,
> > + test_bit(THROTTLER_TEMP_VR_MEM_BIT, 
> > &dep_throttler_status));
> > +   __assign_bit(INDEP_THROTTLER_TEMP_VR_SOC_BIT, 
> > &indep_throttler_status,
> > + test_bit(THROTTLER_TEMP_VR_SOC_BIT, 
> > &dep_throttler_status));
> > +   __assign_bit(INDEP_THROTTLER_TDC_GFX_BIT, &indep_throttler_status,
> > + test_bit(THROTTLER_TDC_GFX_BIT, &dep_throttler_status));
> > +   __assign_bit(INDEP_THROTTLER_TDC_SOC_BIT, &indep_throttler_status,
> > + test_bit(THROTTLER_TDC_SOC_BIT, &dep_throttler_status));
> > +   __assign_bit(INDEP_THROTTLER_PPT0_BIT, &indep_throttler_status,
> > + test_bit(THROTTLER_PPT0_BIT, &dep_throttler_status));
> > +   __assign_bit(INDEP_THROTTLER_PPT1_BIT, &indep_throttler_status,
> > + test_bit(THROTTLER_PPT1_BIT, &dep_throttler_status));
> > +   __assign_bit(INDEP_THROTTLER_PPT2_BIT, &indep_throttler_status,
> > + test_bit(THROTTLER_PPT2_BIT, &dep_throttler_status));
> > +   __assign_bit(INDEP_THROTTLER_PPT3_BIT, &indep_throttler_status,
> > + test_bit(THROTTLER_PPT3_BIT, &dep_throttler_status));
> > +   __assign_bit(INDEP_THROTTLER_PPM_BIT, &indep_throttler_status,
> > +

[PATCH 3/3] drm/amdgpu: Use delayed work to collect RAS error counters

[Luben Tuikov]

On Context Query2 IOCTL return the correctable and
uncorrectable errors in O(1) fashion, from cached
values, and schedule a delayed work function to
calculate and cache them for the next such IOCTL.

Cc: Alexander Deucher 
Cc: Christian König 
Cc: John Clements 
Cc: Hawking Zhang 
Signed-off-by: Luben Tuikov 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 32 +++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 38 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h |  5 
 3 files changed, 73 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index bb0cfe871aba..4e95d255960b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -331,10 +331,13 @@ static int amdgpu_ctx_query(struct amdgpu_device *adev,
return 0;
 }
 
+#define AMDGPU_RAS_COUNTE_DELAY_MS 3000
+
 static int amdgpu_ctx_query2(struct amdgpu_device *adev,
-   struct amdgpu_fpriv *fpriv, uint32_t id,
-   union drm_amdgpu_ctx_out *out)
+struct amdgpu_fpriv *fpriv, uint32_t id,
+union drm_amdgpu_ctx_out *out)
 {
+   struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
struct amdgpu_ctx *ctx;
struct amdgpu_ctx_mgr *mgr;
 
@@ -361,6 +364,31 @@ static int amdgpu_ctx_query2(struct amdgpu_device *adev,
if (atomic_read(&ctx->guilty))
out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_GUILTY;
 
+   if (adev->ras_enabled && con) {
+   /* Return the cached values in O(1),
+* and schedule delayed work to cache
+* new vaues.
+*/
+   int ce_count, ue_count;
+
+   ce_count = atomic_read(&con->ras_ce_count);
+   ue_count = atomic_read(&con->ras_ue_count);
+
+   if (ce_count != ctx->ras_counter_ce) {
+   ctx->ras_counter_ce = ce_count;
+   out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RAS_CE;
+   }
+
+   if (ue_count != ctx->ras_counter_ue) {
+   ctx->ras_counter_ue = ue_count;
+   out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RAS_UE;
+   }
+
+   if (!delayed_work_pending(&con->ras_counte_delay_work))
+   schedule_delayed_work(&con->ras_counte_delay_work,
+ msecs_to_jiffies(AMDGPU_RAS_COUNTE_DELAY_MS));
+   }
+
mutex_unlock(&mgr->lock);
return 0;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index ed3c43e8b0b5..80f576098318 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -27,6 +27,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "amdgpu.h"
 #include "amdgpu_ras.h"
@@ -2116,6 +2117,30 @@ static void amdgpu_ras_check_supported(struct 
amdgpu_device *adev)
adev->ras_hw_enabled & amdgpu_ras_mask;
 }
 
+static void amdgpu_ras_counte_dw(struct work_struct *work)
+{
+   struct amdgpu_ras *con = container_of(work, struct amdgpu_ras,
+ ras_counte_delay_work.work);
+   struct amdgpu_device *adev = con->adev;
+   struct drm_device *dev = &adev->ddev;
+   unsigned long ce_count, ue_count;
+   int res;
+
+   res = pm_runtime_get_sync(dev->dev);
+   if (res < 0)
+   goto Out;
+
+   /* Cache new values.
+*/
+   amdgpu_ras_query_error_count(adev, &ce_count, &ue_count);
+   atomic_set(&con->ras_ce_count, ce_count);
+   atomic_set(&con->ras_ue_count, ue_count);
+
+   pm_runtime_mark_last_busy(dev->dev);
+Out:
+   pm_runtime_put_autosuspend(dev->dev);
+}
+
 int amdgpu_ras_init(struct amdgpu_device *adev)
 {
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
@@ -2130,6 +2155,11 @@ int amdgpu_ras_init(struct amdgpu_device *adev)
if (!con)
return -ENOMEM;
 
+   con->adev = adev;
+   INIT_DELAYED_WORK(&con->ras_counte_delay_work, amdgpu_ras_counte_dw);
+   atomic_set(&con->ras_ce_count, 0);
+   atomic_set(&con->ras_ue_count, 0);
+
con->objs = (struct ras_manager *)(con + 1);
 
amdgpu_ras_set_context(adev, con);
@@ -2233,6 +2263,8 @@ int amdgpu_ras_late_init(struct amdgpu_device *adev,
 struct ras_fs_if *fs_info,
 struct ras_ih_if *ih_info)
 {
+   struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
+   unsigned long ue_count, ce_count;
int r;
 
/* disable RAS feature per IP block if it is not supported */
@@ -2273,6 +2305,12 @@ int amdgpu_ras_late_init(struct amdgpu_device *adev,
if (r)
goto sysfs;
 
+   /* Those are the cached values at init.
+*/
+   amdgpu_ras_query_error_count(adev, &ce_count, &ue_

[PATCH 2/3] drm/amdgpu: Fix RAS function interface

[Luben Tuikov]

The correctable and uncorrectable errors
are calculated at each invocation of this
function. Therefore, it is highly inefficient to
return just one of them based on a Boolean
input. If the caller wants both, twice the work
would be done. (And this work is O(n^3) on
Vega20.)

Fix this "interface" to simply return what it had
calculated--both values. Let the caller choose
what it wants to record, inspect, use.

Cc: Alexander Deucher 
Cc: John Clements 
Cc: Hawking Zhang 
Signed-off-by: Luben Tuikov 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 23 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h |  5 +++--
 2 files changed, 18 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index e3a4c3a7635a..ed3c43e8b0b5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -1043,29 +1043,36 @@ int amdgpu_ras_error_inject(struct amdgpu_device *adev,
 }
 
 /* get the total error counts on all IPs */
-unsigned long amdgpu_ras_query_error_count(struct amdgpu_device *adev,
-   bool is_ce)
+void amdgpu_ras_query_error_count(struct amdgpu_device *adev,
+ unsigned long *ce_count,
+ unsigned long *ue_count)
 {
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
struct ras_manager *obj;
-   struct ras_err_data data = {0, 0};
+   unsigned long ce, ue;
 
if (!adev->ras_enabled || !con)
-   return 0;
+   return;
 
+   ce = 0;
+   ue = 0;
list_for_each_entry(obj, &con->head, node) {
struct ras_query_if info = {
.head = obj->head,
};
 
if (amdgpu_ras_query_error_status(adev, &info))
-   return 0;
+   return;
 
-   data.ce_count += info.ce_count;
-   data.ue_count += info.ue_count;
+   ce += info.ce_count;
+   ue += info.ue_count;
}
 
-   return is_ce ? data.ce_count : data.ue_count;
+   if (ce_count)
+   *ce_count = ce;
+
+   if (ue_count)
+   *ue_count = ue;
 }
 /* query/inject/cure end */
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
index bfa40c8ecc94..10fca0393106 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
@@ -485,8 +485,9 @@ int amdgpu_ras_request_reset_on_boot(struct amdgpu_device 
*adev,
 void amdgpu_ras_resume(struct amdgpu_device *adev);
 void amdgpu_ras_suspend(struct amdgpu_device *adev);
 
-unsigned long amdgpu_ras_query_error_count(struct amdgpu_device *adev,
-   bool is_ce);
+void amdgpu_ras_query_error_count(struct amdgpu_device *adev,
+ unsigned long *ce_count,
+ unsigned long *ue_count);
 
 /* error handling functions */
 int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
-- 
2.31.1.527.g2d677e5b15

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[PATCH 1/3] drm/amdgpu: Don't query CE and UE errors

[Luben Tuikov]

On QUERY2 IOCTL don't query counts of correctable
and uncorrectable errors, since when RAS is
enabled and supported on Vega20 server boards,
this takes insurmountably long time, in O(n^3),
which slows the system down to the point of it
being unusable when we have GUI up.

Fixes: ae363a212b14 ("drm/amdgpu: Add a new flag to AMDGPU_CTX_OP_QUERY_STATE2")
Cc: Alexander Deucher 
Cc: sta...@vger.kernel.org
Signed-off-by: Luben Tuikov 
Reviewed-by: Alexander Deucher 
Reviewed-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 16 
 1 file changed, 16 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index fc83445fbc40..bb0cfe871aba 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -337,7 +337,6 @@ static int amdgpu_ctx_query2(struct amdgpu_device *adev,
 {
struct amdgpu_ctx *ctx;
struct amdgpu_ctx_mgr *mgr;
-   unsigned long ras_counter;
 
if (!fpriv)
return -EINVAL;
@@ -362,21 +361,6 @@ static int amdgpu_ctx_query2(struct amdgpu_device *adev,
if (atomic_read(&ctx->guilty))
out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_GUILTY;
 
-   /*query ue count*/
-   ras_counter = amdgpu_ras_query_error_count(adev, false);
-   /*ras counter is monotonic increasing*/
-   if (ras_counter != ctx->ras_counter_ue) {
-   out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RAS_UE;
-   ctx->ras_counter_ue = ras_counter;
-   }
-
-   /*query ce count*/
-   ras_counter = amdgpu_ras_query_error_count(adev, true);
-   if (ras_counter != ctx->ras_counter_ce) {
-   out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RAS_CE;
-   ctx->ras_counter_ce = ras_counter;
-   }
-
mutex_unlock(&mgr->lock);
return 0;
 }
-- 
2.31.1.527.g2d677e5b15

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Re: [PATCH] drm/amd/amdkfd: Drop unnecessary NULL check after container_of

[Alex Deucher]

Applied.  Thanks!

Alex

On Fri, May 21, 2021 at 11:02 AM Guenter Roeck  wrote:
>
> The first parameter passed to container_of() is the pointer to the work
> structure passed to the worker and never NULL. The NULL check on the
> result of container_of() is therefore unnecessary and misleading.
> Remove it.
>
> This change was made automatically with the following Coccinelle script.
>
> @@
> type t;
> identifier v;
> statement s;
> @@
>
> <+...
> (
>   t v = container_of(...);
> |
>   v = container_of(...);
> )
>   ...
>   when != v
> - if (\( !v \| v == NULL \) ) s
> ...+>
>
> Signed-off-by: Guenter Roeck 
> ---
>  drivers/gpu/drm/amd/amdkfd/kfd_process.c | 2 --
>  1 file changed, 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c 
> b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
> index 5b6c5669c03d..2f8d352e0069 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
> @@ -110,8 +110,6 @@ static void kfd_sdma_activity_worker(struct work_struct 
> *work)
>
> workarea = container_of(work, struct 
> kfd_sdma_activity_handler_workarea,
> sdma_activity_work);
> -   if (!workarea)
> -   return;
>
> pdd = workarea->pdd;
> if (!pdd)
> --
> 2.25.1
>
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Re: [PATCH] drm/amdgpu: Fix inconsistent indenting

[Alex Deucher]

Applied.  Thanks!

Alex

On Fri, May 21, 2021 at 9:35 AM Christian König
 wrote:
>
> Am 21.05.21 um 11:50 schrieb Jiapeng Chong:
> > Eliminate the follow smatch warning:
> >
> > drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c:449
> > sdma_v5_0_ring_emit_mem_sync() warn: inconsistent indenting.
> >
> > Reported-by: Abaci Robot 
> > Signed-off-by: Jiapeng Chong 
>
> Reviewed-by: Christian König 
>
> > ---
> >   drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 13 ++---
> >   1 file changed, 6 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 
> > b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> > index 75d7310..c45e1b0 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> > @@ -440,20 +440,19 @@ static void sdma_v5_0_ring_emit_ib(struct amdgpu_ring 
> > *ring,
> >*/
> >   static void sdma_v5_0_ring_emit_mem_sync(struct amdgpu_ring *ring)
> >   {
> > -uint32_t gcr_cntl =
> > - SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV |
> > - SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | 
> > SDMA_GCR_GLK_INV |
> > - SDMA_GCR_GLI_INV(1);
> > + uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | 
> > SDMA_GCR_GLM_INV |
> > + SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | 
> > SDMA_GCR_GLK_INV |
> > + SDMA_GCR_GLI_INV(1);
> >
> >   /* flush entire cache L0/L1/L2, this can be optimized by performance 
> > requirement */
> >   amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ));
> >   amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0));
> >   amdgpu_ring_write(ring, 
> > SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) |
> > - SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0));
> > +   SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0));
> >   amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) |
> > - SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl 
> > >> 16));
> > +   
> > SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16));
> >   amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) |
> > - SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0));
> > +   SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0));
> >   }
> >
> >   /**
>
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Re: [PATCH v2 2/2] drm/amdgpu: Fix crash when hot unplug in BACO.

[Alex Deucher]

On Fri, May 21, 2021 at 4:41 PM Andrey Grodzovsky
 wrote:
>
> Problem:
> When device goes into sleep state due to prolonged

s/sleep state/runtime suspend/

> innactivity (e.g. BACO sleep) and then hot unplugged,

inactivity

> PCI core will try to wake up the device as part of
> unplug process. Since the device is gone all HW
> programming during rpm resume fails leading
> to a bad SW state later during pci remove handling.
>
> Fix:
> Use a flag we use for PCIe error recovery to avoid
> accessing registres. This allows to succefully complete

successfully

> rpm resume sequence and finish pci remove.
>
> v2: Renamed HW access block flag
>
> Link: https://gitlab.freedesktop.org/drm/amd/-/issues/1081
> Signed-off-by: Andrey Grodzovsky 

With the above comments fixed, the series is:
Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 5 +
>  1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index d8db5929cdd9..b9d221fcb66d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -1555,6 +1555,11 @@ static int amdgpu_pmops_runtime_resume(struct device 
> *dev)
> if (!adev->runpm)
> return -EINVAL;
>
> +   /* Avoids registers access if device is physically gone */
> +   if (!pci_device_is_present(adev->pdev))
> +   adev->no_hw_access = true;
> +
> +
> if (amdgpu_device_supports_px(drm_dev)) {
> drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
>
> --
> 2.25.1
>
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[PATCH v2 2/2] drm/amdgpu: Fix crash when hot unplug in BACO.

[Andrey Grodzovsky]

Problem:
When device goes into sleep state due to prolonged
innactivity (e.g. BACO sleep) and then hot unplugged,
PCI core will try to wake up the device as part of
unplug process. Since the device is gone all HW
programming during rpm resume fails leading
to a bad SW state later during pci remove handling.

Fix:
Use a flag we use for PCIe error recovery to avoid
accessing registres. This allows to succefully complete
rpm resume sequence and finish pci remove.

v2: Renamed HW access block flag

Link: https://gitlab.freedesktop.org/drm/amd/-/issues/1081
Signed-off-by: Andrey Grodzovsky 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index d8db5929cdd9..b9d221fcb66d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -1555,6 +1555,11 @@ static int amdgpu_pmops_runtime_resume(struct device 
*dev)
if (!adev->runpm)
return -EINVAL;
 
+   /* Avoids registers access if device is physically gone */
+   if (!pci_device_is_present(adev->pdev))
+   adev->no_hw_access = true;
+
+
if (amdgpu_device_supports_px(drm_dev)) {
drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 
-- 
2.25.1

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[PATCH v2 1/2] drm/amdgpu: Rename flag which prevents HW access

[Andrey Grodzovsky]

Make it's name not feature but function descriptive.

Signed-off-by: Andrey Grodzovsky 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h| 2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 +++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c| 4 ++--
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-
 drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 2 +-
 5 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index d830a541ba89..d0e557cb5f1d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1076,7 +1076,7 @@ struct amdgpu_device {
struct ratelimit_state  throttling_logging_rs;
uint32_tras_features;
 
-   boolin_pci_err_recovery;
+   boolno_hw_access;
struct pci_saved_state  *pci_state;
 
struct amdgpu_reset_control *reset_cntl;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index bf5055642b82..60e945471a54 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -340,7 +340,7 @@ void amdgpu_device_vram_access(struct amdgpu_device *adev, 
loff_t pos,
 /* Check if hw access should be skipped because of hotplug or device error */
 bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev)
 {
-   if (adev->in_pci_err_recovery)
+   if (adev->no_hw_access)
return true;
 
 #ifdef CONFIG_LOCKDEP
@@ -5335,9 +5335,9 @@ pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev 
*pdev)
set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags);
 
-   adev->in_pci_err_recovery = true;
+   adev->no_hw_access = true;
r = amdgpu_device_pre_asic_reset(adev, &reset_context);
-   adev->in_pci_err_recovery = false;
+   adev->no_hw_access = false;
if (r)
goto out;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index baa7d9778583..ce1577687ac2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -232,7 +232,7 @@ int psp_wait_for(struct psp_context *psp, uint32_t 
reg_index,
int i;
struct amdgpu_device *adev = psp->adev;
 
-   if (psp->adev->in_pci_err_recovery)
+   if (psp->adev->no_hw_access)
return 0;
 
for (i = 0; i < adev->usec_timeout; i++) {
@@ -261,7 +261,7 @@ psp_cmd_submit_buf(struct psp_context *psp,
bool ras_intr = false;
bool skip_unsupport = false;
 
-   if (psp->adev->in_pci_err_recovery)
+   if (psp->adev->no_hw_access)
return 0;
 
if (!drm_dev_enter(&psp->adev->ddev, &idx))
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 2408ed4c7d84..540fedf787c8 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -7332,7 +7332,7 @@ static int gfx_v10_0_hw_fini(void *handle)
amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
 
-   if (!adev->in_pci_err_recovery) {
+   if (!adev->no_hw_access) {
 #ifndef BRING_UP_DEBUG
if (amdgpu_async_gfx_ring) {
r = gfx_v10_0_kiq_disable_kgq(adev);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
index dc7d2e71aa6f..9526b46582c8 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
@@ -126,7 +126,7 @@ int smu_cmn_send_smc_msg_with_param(struct smu_context *smu,
struct amdgpu_device *adev = smu->adev;
int ret = 0, index = 0;
 
-   if (smu->adev->in_pci_err_recovery)
+   if (smu->adev->no_hw_access)
return 0;
 
index = smu_cmn_to_asic_specific_index(smu,
-- 
2.25.1

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Re: [PATCH] drm/amdgpu: Fix crash when hot unplug in BACO.

[Andrey Grodzovsky]

Will do.

Andrey

On 2021-05-21 4:18 p.m., Alex Deucher wrote:

On Fri, May 21, 2021 at 4:14 PM Andrey Grodzovsky
 wrote:

Problem:
When device goes into sleep state due to prolonged
innactivity (e.g. BACO sleep) and then hot unplugged,
PCI core will try to wake up the device as part of
unplug process. Since the device is gone all HW
programming during rpm resume fails leading
to a bad SW state later during pci remove handling.

Fix:
Use a flag we use for PCIe error recovery to avoid
accessing registres. This allows to succefully complete
rpm resume sequence and finish pci remove.

Might make sense to create a preliminary patch to change the name of
this flag to something like no_hw_access since it's not specific to
pci error handling.

Alex


P.S Must use pci_device_is_present and not drm_dev_enter/exit
here since rpm resume happens before PCI remove and so the
unplug flag is not set yet.

Link: 
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgitlab.freedesktop.org%2Fdrm%2Famd%2F-%2Fissues%2F1081&data=04%7C01%7Candrey.grodzovsky%40amd.com%7C2a0ec02245b64de0139808d91c959987%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637572251118922092%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=egcYBxBU%2BkIqbEdypVueXQcWb%2Bqe%2BKCC30Mw%2FjgR6ag%3D&reserved=0
Signed-off-by: Andrey Grodzovsky 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 5 +
  1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index d8db5929cdd9..ab95ebf56636 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -1555,6 +1555,11 @@ static int amdgpu_pmops_runtime_resume(struct device 
*dev)
 if (!adev->runpm)
 return -EINVAL;

+   /* Avoids registers access if device is physically gone */
+   if (!pci_device_is_present(adev->pdev))
+   adev->in_pci_err_recovery = true;
+
+
 if (amdgpu_device_supports_px(drm_dev)) {
 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;

--
2.25.1


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Re: [PATCH] drm/amdgpu: Fix crash when hot unplug in BACO.

[Alex Deucher]

On Fri, May 21, 2021 at 4:14 PM Andrey Grodzovsky
 wrote:
>
> Problem:
> When device goes into sleep state due to prolonged
> innactivity (e.g. BACO sleep) and then hot unplugged,
> PCI core will try to wake up the device as part of
> unplug process. Since the device is gone all HW
> programming during rpm resume fails leading
> to a bad SW state later during pci remove handling.
>
> Fix:
> Use a flag we use for PCIe error recovery to avoid
> accessing registres. This allows to succefully complete
> rpm resume sequence and finish pci remove.

Might make sense to create a preliminary patch to change the name of
this flag to something like no_hw_access since it's not specific to
pci error handling.

Alex

>
> P.S Must use pci_device_is_present and not drm_dev_enter/exit
> here since rpm resume happens before PCI remove and so the
> unplug flag is not set yet.
>
> Link: https://gitlab.freedesktop.org/drm/amd/-/issues/1081
> Signed-off-by: Andrey Grodzovsky 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 5 +
>  1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index d8db5929cdd9..ab95ebf56636 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -1555,6 +1555,11 @@ static int amdgpu_pmops_runtime_resume(struct device 
> *dev)
> if (!adev->runpm)
> return -EINVAL;
>
> +   /* Avoids registers access if device is physically gone */
> +   if (!pci_device_is_present(adev->pdev))
> +   adev->in_pci_err_recovery = true;
> +
> +
> if (amdgpu_device_supports_px(drm_dev)) {
> drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
>
> --
> 2.25.1
>
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Re: [PATCH 2/6] drm/amd/pm: Add arcturus throttler translation

[Alex Deucher]

On Fri, May 21, 2021 at 1:39 PM Sider, Graham  wrote:
>
> Hi Alex,
>
> Are you referring to bumping the gpu_metrics_vX_Y version number? Different 
> ASICs are currently using different version numbers already, so I'm not sure 
> how feasible this might be (e.g. arcturus ==  gpu_metrics_v1_1, navi1x == 
> gpu_metrics_v1_3, vangogh == gpu_metrics_v2_1).
>
> Technically speaking no new fields have been added to any of the gpu_metrics 
> versions, just a change in representation in the throttle_status field. Let 
> me know your thoughts on this.
>

I don't know if we have any existing tools out there that parse this
data, but if so, they would interpret it incorrectly after this
change.  If we bump the version, at least the tools will know how to
handle it.

Alex


> Best,
> Graham
>
> -Original Message-
> From: Alex Deucher 
> Sent: Friday, May 21, 2021 10:27 AM
> To: Sider, Graham 
> Cc: amd-gfx list ; Kasiviswanathan, Harish 
> ; Sakhnovitch, Elena (Elen) 
> 
> Subject: Re: [PATCH 2/6] drm/amd/pm: Add arcturus throttler translation
>
> [CAUTION: External Email]
>
> General comment on the patch series, do you want to bump the metrics table 
> version since the meaning of the throttler status has changed?
>
> Alex
>
> On Thu, May 20, 2021 at 10:30 AM Graham Sider  wrote:
> >
> > Perform dependent to independent throttle status translation for
> > arcturus.
> > ---
> >  .../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 62
> > ---
> >  1 file changed, 53 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> > b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> > index 1735a96dd307..7c01c0bf2073 100644
> > --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> > @@ -540,6 +540,49 @@ static int arcturus_freqs_in_same_level(int32_t 
> > frequency1,
> > return (abs(frequency1 - frequency2) <= EPSILON);  }
> >
> > +static uint32_t arcturus_get_indep_throttler_status(
> > +   unsigned long
> > +dep_throttler_status) {
> > +   unsigned long indep_throttler_status = 0;
> > +
> > +   __assign_bit(INDEP_THROTTLER_TEMP_EDGE_BIT, &indep_throttler_status,
> > + test_bit(THROTTLER_TEMP_EDGE_BIT, &dep_throttler_status));
> > +   __assign_bit(INDEP_THROTTLER_TEMP_HOTSPOT_BIT, 
> > &indep_throttler_status,
> > + test_bit(THROTTLER_TEMP_HOTSPOT_BIT, 
> > &dep_throttler_status));
> > +   __assign_bit(INDEP_THROTTLER_TEMP_MEM_BIT, &indep_throttler_status,
> > + test_bit(THROTTLER_TEMP_MEM_BIT, &dep_throttler_status));
> > +   __assign_bit(INDEP_THROTTLER_TEMP_VR_GFX_BIT, 
> > &indep_throttler_status,
> > + test_bit(THROTTLER_TEMP_VR_GFX_BIT, 
> > &dep_throttler_status));
> > +   __assign_bit(INDEP_THROTTLER_TEMP_VR_MEM_BIT, 
> > &indep_throttler_status,
> > + test_bit(THROTTLER_TEMP_VR_MEM_BIT, 
> > &dep_throttler_status));
> > +   __assign_bit(INDEP_THROTTLER_TEMP_VR_SOC_BIT, 
> > &indep_throttler_status,
> > + test_bit(THROTTLER_TEMP_VR_SOC_BIT, 
> > &dep_throttler_status));
> > +   __assign_bit(INDEP_THROTTLER_TDC_GFX_BIT, &indep_throttler_status,
> > + test_bit(THROTTLER_TDC_GFX_BIT, &dep_throttler_status));
> > +   __assign_bit(INDEP_THROTTLER_TDC_SOC_BIT, &indep_throttler_status,
> > + test_bit(THROTTLER_TDC_SOC_BIT, &dep_throttler_status));
> > +   __assign_bit(INDEP_THROTTLER_PPT0_BIT, &indep_throttler_status,
> > + test_bit(THROTTLER_PPT0_BIT, &dep_throttler_status));
> > +   __assign_bit(INDEP_THROTTLER_PPT1_BIT, &indep_throttler_status,
> > + test_bit(THROTTLER_PPT1_BIT, &dep_throttler_status));
> > +   __assign_bit(INDEP_THROTTLER_PPT2_BIT, &indep_throttler_status,
> > + test_bit(THROTTLER_PPT2_BIT, &dep_throttler_status));
> > +   __assign_bit(INDEP_THROTTLER_PPT3_BIT, &indep_throttler_status,
> > + test_bit(THROTTLER_PPT3_BIT, &dep_throttler_status));
> > +   __assign_bit(INDEP_THROTTLER_PPM_BIT, &indep_throttler_status,
> > + test_bit(THROTTLER_PPM_BIT, &dep_throttler_status));
> > +   __assign_bit(INDEP_THROTTLER_FIT_BIT, &indep_throttler_status,
> > + test_bit(THROTTLER_FIT_BIT, &dep_throttler_status));
> > +   __assign_bit(INDEP_THROTTLER_APCC_BIT, &indep_throttler_status,
> > + test_bit(THROTTLER_APCC_BIT, &dep_throttler_status));
> > +   __assign_bit(INDEP_THROTTLER_VRHOT0_BIT, &indep_throttler_status,
> > + test_bit(THROTTLER_VRHOT0_BIT, &dep_throttler_status));
> > +   __assign_bit(INDEP_THROTTLER_VRHOT1_BIT, &indep_throttler_status,
> > + test_bit(THROTTLER_VRHOT1_BIT,
> > + &dep_throttler_status));
> > +
> > +   return (uint32_t)indep_throttler_status; }
> > +
> >  static int arcturus_get

[PATCH] drm/amdgpu: Fix crash when hot unplug in BACO.

[Andrey Grodzovsky]

Problem:
When device goes into sleep state due to prolonged
innactivity (e.g. BACO sleep) and then hot unplugged,
PCI core will try to wake up the device as part of
unplug process. Since the device is gone all HW
programming during rpm resume fails leading
to a bad SW state later during pci remove handling.

Fix:
Use a flag we use for PCIe error recovery to avoid
accessing registres. This allows to succefully complete
rpm resume sequence and finish pci remove.

P.S Must use pci_device_is_present and not drm_dev_enter/exit
here since rpm resume happens before PCI remove and so the 
unplug flag is not set yet.

Link: https://gitlab.freedesktop.org/drm/amd/-/issues/1081
Signed-off-by: Andrey Grodzovsky 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index d8db5929cdd9..ab95ebf56636 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -1555,6 +1555,11 @@ static int amdgpu_pmops_runtime_resume(struct device 
*dev)
if (!adev->runpm)
return -EINVAL;
 
+   /* Avoids registers access if device is physically gone */
+   if (!pci_device_is_present(adev->pdev))
+   adev->in_pci_err_recovery = true;
+
+
if (amdgpu_device_supports_px(drm_dev)) {
drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 
-- 
2.25.1

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Re: [PATCH] drm/amdkfd: use resource cursor in svm_migrate_copy_to_vram

[philip yang]

  
This simply the logic, several comments inline.
Thanks,

Philip

On 2021-05-21 9:52 a.m., Christian
  König wrote:


  Access to the mm_node is now forbidden. So instead of hand wiring that
use the cursor functionality.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 76 +++-
 1 file changed, 9 insertions(+), 67 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
index fd8f544f0de2..cb28d1e660af 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
@@ -29,6 +29,7 @@
 #include "amdgpu_object.h"
 #include "amdgpu_vm.h"
 #include "amdgpu_mn.h"
+#include "amdgpu_res_cursor.h"
 #include "kfd_priv.h"
 #include "kfd_svm.h"
 #include "kfd_migrate.h"
@@ -205,34 +206,6 @@ svm_migrate_copy_done(struct amdgpu_device *adev, struct dma_fence *mfence)
 	return r;
 }
 
-static uint64_t
-svm_migrate_node_physical_addr(struct amdgpu_device *adev,
-			   struct drm_mm_node **mm_node, uint64_t *offset)
-{
-	struct drm_mm_node *node = *mm_node;
-	uint64_t pos = *offset;
-
-	if (node->start == AMDGPU_BO_INVALID_OFFSET) {
-		pr_debug("drm node is not validated\n");
-		return 0;
-	}
-
-	pr_debug("vram node start 0x%llx npages 0x%llx\n", node->start,
-		 node->size);
-
-	if (pos >= node->size) {
-		do  {
-			pos -= node->size;
-			node++;
-		} while (pos >= node->size);
-
-		*mm_node = node;
-		*offset = pos;
-	}
-
-	return (node->start + pos) << PAGE_SHIFT;
-}
-
 unsigned long
 svm_migrate_addr_to_pfn(struct amdgpu_device *adev, unsigned long addr)
 {
@@ -297,11 +270,9 @@ svm_migrate_copy_to_vram(struct amdgpu_device *adev, struct svm_range *prange,
 {
 	uint64_t npages = migrate->cpages;
 	struct device *dev = adev->dev;
-	struct drm_mm_node *node;
+	struct amdgpu_res_cursor cursor;
 	dma_addr_t *src;
 	uint64_t *dst;
-	uint64_t vram_addr;
-	uint64_t offset;
 	uint64_t i, j;
 	int r;
 
@@ -317,19 +288,12 @@ svm_migrate_copy_to_vram(struct amdgpu_device *adev, struct svm_range *prange,
 		goto out;
 	}
 
-	node = prange->ttm_res->mm_node;
-	offset = prange->offset;
-	vram_addr = svm_migrate_node_physical_addr(adev, &node, &offset);
-	if (!vram_addr) {

The prange->ttm_res valid check is not needed because we already
check svm_range_vram_node_new return value

  
-		WARN_ONCE(1, "vram node address is 0\n");
-		r = -ENOMEM;
-		goto out;
-	}
-
+	amdgpu_res_first(prange->ttm_res, prange->offset, npages << PAGE_SHIFT,

prange->offset<< PAGE_SHIFT
amdgpu_res_first takes start and size in bytes, prange->offset
  use page aligned offset



  
+			 &cursor);
 	for (i = j = 0; i < npages; i++) {
 		struct page *spage;
 
-		dst[i] = vram_addr + (j << PAGE_SHIFT);
+		dst[i] = cursor.start + (j << PAGE_SHIFT);
 		migrate->dst[i] = svm_migrate_addr_to_pfn(adev, dst[i]);
 		svm_migrate_get_vram_page(prange, migrate->dst[i]);
 
@@ -354,18 +318,10 @@ svm_migrate_copy_to_vram(struct amdgpu_device *adev, struct svm_range *prange,
 		mfence);
 if (r)
 	goto out_free_vram_pages;
-offset += j;
-vram_addr = (node->start + offset) << PAGE_SHIFT;
+amdgpu_res_next(&cursor, j << PAGE_SHIFT);
 j = 0;
 			} else {
-offset++;
-vram_addr += PAGE_SIZE;
-			}
-			if (offset >= node->size) {
-node++;
-pr_debug("next node size 0x%llx\n", node->size);
-vram_addr = node->start << PAGE_SHIFT;
-offset = 0;
+amdgpu_res_next(&cursor, PAGE_SIZE);
 			}
 			continue;
 		}
@@ -373,22 +329,8 @@ svm_migrate_copy_to_vram(struct amdgpu_device *adev, struct svm_range *prange,
 		pr_debug("dma mapping src to 0x%llx, page_to_pfn 0x%lx\n",
 			 src[i] >> PAGE_SHIFT, page_to_pfn(spage));
 
-		if (j + offset >= node->size - 1 && i < npages - 1) {
-			r = svm_migrate_copy_memory_gart(adev, src + i - j,
-			 dst + i - j, j + 1,
-			 FROM_RAM_TO_VRAM,
-			 mfence);
-			if (r)
-goto out_free_vram_pages;
-
-			node++;
-			pr_debug("next node size 0x%llx\n", node->size);
-			vram_addr = node->start << PAGE_SHIFT;
-			offset = 0;
-			j = 0;
-		} else {
-			j++;
-		}
+		amdgpu_res_next(&cursor, PAGE_SIZE);
+		j++;

Here to handle cross mm_node case.
if (j >= cursor->size - 1 && i < npages - 1) {
    r = svm_migrate_copy_memory_gart(adev, src + i - j,

                                dst + i - j, j + 1,

			FROM_RAM_TO_VRAM,
			 mfence);
if (r)
	goto out_free_vram_pages;

amdgpu_res_next(&cursor, (j + 1) * PAGE_SIZE);
j= 0;
} else {
   j++;
}



 

  
 	}


   
 	r = svm_migrate_copy_memory_gart(adev, src + i - j, dst + i - j, j,


  

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Re: [PATCH] drm/amdgpu: Use dma_resv_lock instead in BO release_notify

[Christian König]

Am 21.05.21 um 20:24 schrieb Felix Kuehling:

Am 2021-05-21 um 1:26 a.m. schrieb xinhui pan:

The reservation object might be locked again by evict/swap after
individualized. The race is like below.
cpu 0   cpu 1
BO release  BO evict or swap
ttm_bo_individualize_resv {resv = &_resv}
ttm_bo_evict_swapout_allowable
dma_resv_trylock(resv)
->release_notify() {BUG_ON(!trylock(resv))}
if (!ttm_bo_get_unless_zero))
dma_resv_unlock(resv)
Actually this is not a bug if trylock fails. So use dma_resv_lock
instead.

Please test this with LOCKDEP enabled. I believe the trylock here was
needed to avoid potential deadlocks. Maybe Christian can fill in more
details.


Unfortunately I don't remember why trylock was needed here either.

But yes, testing with lockdep enabled is a really good idea.

Regards,
Christian.



Regards,
   Felix



Signed-off-by: xinhui pan 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index 928e8d57cd08..beacb46265f8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -318,7 +318,7 @@ int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct 
amdgpu_bo *bo)
ef = container_of(dma_fence_get(&info->eviction_fence->base),
struct amdgpu_amdkfd_fence, base);
  
-	BUG_ON(!dma_resv_trylock(bo->tbo.base.resv));

+   dma_resv_lock(bo->tbo.base.resv, NULL);
ret = amdgpu_amdkfd_remove_eviction_fence(bo, ef);
dma_resv_unlock(bo->tbo.base.resv);
  


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Re: [PATCH] drm/amdgpu: Use dma_resv_lock instead in BO release_notify

[Felix Kuehling]

Am 2021-05-21 um 1:26 a.m. schrieb xinhui pan:
> The reservation object might be locked again by evict/swap after
> individualized. The race is like below.
> cpu 0 cpu 1
> BO releaseBO evict or swap
> ttm_bo_individualize_resv {resv = &_resv}
>   ttm_bo_evict_swapout_allowable
>   dma_resv_trylock(resv)
> ->release_notify() {BUG_ON(!trylock(resv))}
>   if (!ttm_bo_get_unless_zero))
>   dma_resv_unlock(resv)
> Actually this is not a bug if trylock fails. So use dma_resv_lock
> instead.

Please test this with LOCKDEP enabled. I believe the trylock here was
needed to avoid potential deadlocks. Maybe Christian can fill in more
details.

Regards,
  Felix


>
> Signed-off-by: xinhui pan 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> index 928e8d57cd08..beacb46265f8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> @@ -318,7 +318,7 @@ int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct 
> amdgpu_bo *bo)
>   ef = container_of(dma_fence_get(&info->eviction_fence->base),
>   struct amdgpu_amdkfd_fence, base);
>  
> - BUG_ON(!dma_resv_trylock(bo->tbo.base.resv));
> + dma_resv_lock(bo->tbo.base.resv, NULL);
>   ret = amdgpu_amdkfd_remove_eviction_fence(bo, ef);
>   dma_resv_unlock(bo->tbo.base.resv);
>  
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RE: [PATCH 2/6] drm/amd/pm: Add arcturus throttler translation

[Sider, Graham]

Hi Alex,

Are you referring to bumping the gpu_metrics_vX_Y version number? Different 
ASICs are currently using different version numbers already, so I'm not sure 
how feasible this might be (e.g. arcturus ==  gpu_metrics_v1_1, navi1x == 
gpu_metrics_v1_3, vangogh == gpu_metrics_v2_1).

Technically speaking no new fields have been added to any of the gpu_metrics 
versions, just a change in representation in the throttle_status field. Let me 
know your thoughts on this.

Best,
Graham

-Original Message-
From: Alex Deucher  
Sent: Friday, May 21, 2021 10:27 AM
To: Sider, Graham 
Cc: amd-gfx list ; Kasiviswanathan, Harish 
; Sakhnovitch, Elena (Elen) 

Subject: Re: [PATCH 2/6] drm/amd/pm: Add arcturus throttler translation

[CAUTION: External Email]

General comment on the patch series, do you want to bump the metrics table 
version since the meaning of the throttler status has changed?

Alex

On Thu, May 20, 2021 at 10:30 AM Graham Sider  wrote:
>
> Perform dependent to independent throttle status translation for 
> arcturus.
> ---
>  .../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 62 
> ---
>  1 file changed, 53 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c 
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> index 1735a96dd307..7c01c0bf2073 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> @@ -540,6 +540,49 @@ static int arcturus_freqs_in_same_level(int32_t 
> frequency1,
> return (abs(frequency1 - frequency2) <= EPSILON);  }
>
> +static uint32_t arcturus_get_indep_throttler_status(
> +   unsigned long 
> +dep_throttler_status) {
> +   unsigned long indep_throttler_status = 0;
> +
> +   __assign_bit(INDEP_THROTTLER_TEMP_EDGE_BIT, &indep_throttler_status,
> + test_bit(THROTTLER_TEMP_EDGE_BIT, &dep_throttler_status));
> +   __assign_bit(INDEP_THROTTLER_TEMP_HOTSPOT_BIT, 
> &indep_throttler_status,
> + test_bit(THROTTLER_TEMP_HOTSPOT_BIT, 
> &dep_throttler_status));
> +   __assign_bit(INDEP_THROTTLER_TEMP_MEM_BIT, &indep_throttler_status,
> + test_bit(THROTTLER_TEMP_MEM_BIT, &dep_throttler_status));
> +   __assign_bit(INDEP_THROTTLER_TEMP_VR_GFX_BIT, &indep_throttler_status,
> + test_bit(THROTTLER_TEMP_VR_GFX_BIT, &dep_throttler_status));
> +   __assign_bit(INDEP_THROTTLER_TEMP_VR_MEM_BIT, &indep_throttler_status,
> + test_bit(THROTTLER_TEMP_VR_MEM_BIT, &dep_throttler_status));
> +   __assign_bit(INDEP_THROTTLER_TEMP_VR_SOC_BIT, &indep_throttler_status,
> + test_bit(THROTTLER_TEMP_VR_SOC_BIT, &dep_throttler_status));
> +   __assign_bit(INDEP_THROTTLER_TDC_GFX_BIT, &indep_throttler_status,
> + test_bit(THROTTLER_TDC_GFX_BIT, &dep_throttler_status));
> +   __assign_bit(INDEP_THROTTLER_TDC_SOC_BIT, &indep_throttler_status,
> + test_bit(THROTTLER_TDC_SOC_BIT, &dep_throttler_status));
> +   __assign_bit(INDEP_THROTTLER_PPT0_BIT, &indep_throttler_status,
> + test_bit(THROTTLER_PPT0_BIT, &dep_throttler_status));
> +   __assign_bit(INDEP_THROTTLER_PPT1_BIT, &indep_throttler_status,
> + test_bit(THROTTLER_PPT1_BIT, &dep_throttler_status));
> +   __assign_bit(INDEP_THROTTLER_PPT2_BIT, &indep_throttler_status,
> + test_bit(THROTTLER_PPT2_BIT, &dep_throttler_status));
> +   __assign_bit(INDEP_THROTTLER_PPT3_BIT, &indep_throttler_status,
> + test_bit(THROTTLER_PPT3_BIT, &dep_throttler_status));
> +   __assign_bit(INDEP_THROTTLER_PPM_BIT, &indep_throttler_status,
> + test_bit(THROTTLER_PPM_BIT, &dep_throttler_status));
> +   __assign_bit(INDEP_THROTTLER_FIT_BIT, &indep_throttler_status,
> + test_bit(THROTTLER_FIT_BIT, &dep_throttler_status));
> +   __assign_bit(INDEP_THROTTLER_APCC_BIT, &indep_throttler_status,
> + test_bit(THROTTLER_APCC_BIT, &dep_throttler_status));
> +   __assign_bit(INDEP_THROTTLER_VRHOT0_BIT, &indep_throttler_status,
> + test_bit(THROTTLER_VRHOT0_BIT, &dep_throttler_status));
> +   __assign_bit(INDEP_THROTTLER_VRHOT1_BIT, &indep_throttler_status,
> + test_bit(THROTTLER_VRHOT1_BIT, 
> + &dep_throttler_status));
> +
> +   return (uint32_t)indep_throttler_status; }
> +
>  static int arcturus_get_smu_metrics_data(struct smu_context *smu,
>  MetricsMember_t member,
>  uint32_t *value) @@ -629,7 
> +672,7 @@ static int arcturus_get_smu_metrics_data(struct smu_context *smu,
> SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
> break;
> case METRICS_THROTTLER_STATUS:
> -   *value = metrics->ThrottlerStatus;
> +   *value = 
> + arcturu

[PATCH 14/15] drm/amd/display: 3.2.137

[Qingqing Zhuo]

From: Aric Cyr 

DC version 3.2.137 brings improvements in multiple areas.
In summary, we highlight:

- Updates on DP configurations and clock recovery API
- Improvements on DSC, link training sequence, etc.
- Fixes on memory leak, ODM scaling, etc.

Signed-off-by: Aric Cyr 
Reviewed-by: Aric Cyr 
Acked-by: Qingqing Zhuo 
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 7da5e7a2e88d..1b923172244e 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -45,7 +45,7 @@
 /* forward declaration */
 struct aux_payload;
 
-#define DC_VER "3.2.136"
+#define DC_VER "3.2.137"
 
 #define MAX_SURFACES 3
 #define MAX_PLANES 6
-- 
2.25.1

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[PATCH 15/15] Revert "drm/amd/display: Refactor and add visual confirm for HW Flip Queue"

[Qingqing Zhuo]

This reverts commit 5791d219561cb661c991332a4f0bca6a8c8db080.

Recent visual confirm changes are regressing the driver, causing a
black screen on boot in some green sardine configs, or visual confirm
is not updated at all.

Signed-off-by: Qingqing Zhuo 
Acked-by: Qingqing Zhuo 
---
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 31 +++
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.h |  6 
 .../gpu/drm/amd/display/dc/dcn10/dcn10_init.c |  1 -
 .../gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c  |  5 ---
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 28 ++---
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.h|  5 ---
 .../gpu/drm/amd/display/dc/dcn20/dcn20_init.c |  1 -
 .../gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c  |  2 +-
 .../gpu/drm/amd/display/dc/dcn21/dcn21_init.c |  1 -
 .../gpu/drm/amd/display/dc/dcn30/dcn30_init.c |  1 -
 .../gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c  |  2 +-
 .../drm/amd/display/dc/dcn301/dcn301_init.c   |  1 -
 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h   |  3 --
 .../gpu/drm/amd/display/dc/inc/hw_sequencer.h |  4 ---
 14 files changed, 23 insertions(+), 68 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 85a947015945..8f11e2b58cd7 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2502,23 +2502,6 @@ static void dcn10_update_dpp(struct dpp *dpp, struct 
dc_plane_state *plane_state
dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);
 }
 
-void dcn10_update_visual_confirm_color(struct dc *dc, struct pipe_ctx 
*pipe_ctx, struct tg_color *color, int mpcc_id)
-{
-   struct dce_hwseq *hws = dc->hwseq;
-   struct mpc *mpc = dc->res_pool->mpc;
-
-   if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR)
-   hws->funcs.get_hdr_visual_confirm_color(pipe_ctx, color);
-   else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE)
-   hws->funcs.get_surface_visual_confirm_color(pipe_ctx, color);
-   else
-   color_space_to_black_color(
-   dc, pipe_ctx->stream->output_color_space, 
color);
-
-   if (mpc->funcs->set_bg_color)
-   mpc->funcs->set_bg_color(mpc, color, mpcc_id);
-}
-
 void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
 {
struct dce_hwseq *hws = dc->hwseq;
@@ -2530,6 +2513,18 @@ void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx 
*pipe_ctx)
struct mpc *mpc = dc->res_pool->mpc;
struct mpc_tree *mpc_tree_params = 
&(pipe_ctx->stream_res.opp->mpc_tree_params);
 
+   if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) {
+   hws->funcs.get_hdr_visual_confirm_color(
+   pipe_ctx, &blnd_cfg.black_color);
+   } else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) {
+   hws->funcs.get_surface_visual_confirm_color(
+   pipe_ctx, &blnd_cfg.black_color);
+   } else {
+   color_space_to_black_color(
+   dc, pipe_ctx->stream->output_color_space,
+   &blnd_cfg.black_color);
+   }
+
if (per_pixel_alpha)
blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA;
else
@@ -2561,8 +2556,6 @@ void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx 
*pipe_ctx)
 */
mpcc_id = hubp->inst;
 
-   dc->hwss.update_visual_confirm_color(dc, pipe_ctx, 
&blnd_cfg.black_color, mpcc_id);
-
/* If there is no full update, don't need to touch MPC tree*/
if (!pipe_ctx->plane_state->update_flags.bits.full_update) {
mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
index 478180b96d8d..c9bdffe5989b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
@@ -206,10 +206,4 @@ void dcn10_verify_allow_pstate_change_high(struct dc *dc);
 
 void dcn10_get_dcc_en_bits(struct dc *dc, int *dcc_en_bits);
 
-void dcn10_update_visual_confirm_color(
-   struct dc *dc,
-   struct pipe_ctx *pipe_ctx,
-   struct tg_color *color,
-   int mpcc_id);
-
 #endif /* __DC_HWSS_DCN10_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c
index 4ff3ebc25438..680ca53455a2 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c
@@ -82,7 +82,6 @@ static const struct hw_sequencer_funcs dcn10_funcs = {
.set_abm_immediate_disable = dce110_set_abm_immediate_disable,
.set_pipe = dce110_set_pipe,
.get_dcc_en_bits = dcn10_get_

[PATCH 13/15] drm/amd/display: fix odm scaling

[Qingqing Zhuo]

From: Dmytro Laktyushkin 

There are two issues with scaling calculations, odm recout
calculation and matching viewport to actual recout.

This change fixes both issues. Odm recout calculation via
special casing and viewport matching issue by reworking
the viewport calcualtion to use scaling ratios and recout
to derrive the required offset and size.

Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Jun Lei 
Acked-by: Qingqing Zhuo 
---
 .../gpu/drm/amd/display/dc/core/dc_resource.c | 568 +++---
 drivers/gpu/drm/amd/display/dc/dc_types.h |   5 -
 .../drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c |  12 +-
 .../drm/amd/display/dc/dcn20/dcn20_resource.c |  14 +-
 .../amd/display/dc/dml/display_mode_structs.h |   2 +
 .../drm/amd/display/dc/dml/display_mode_vba.c |  13 +
 .../gpu/drm/amd/display/dc/inc/hw/transform.h |   4 -
 7 files changed, 232 insertions(+), 386 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 8a158a192ec0..aea7d4cbb62c 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -701,124 +701,23 @@ static void calculate_split_count_and_index(struct 
pipe_ctx *pipe_ctx, int *spli
}
 }
 
-static void calculate_viewport(struct pipe_ctx *pipe_ctx)
+/*
+ * This is a preliminary vp size calculation to allow us to check taps support.
+ * The result is completely overridden afterwards.
+ */
+static void calculate_viewport_size(struct pipe_ctx *pipe_ctx)
 {
-   const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
-   const struct dc_stream_state *stream = pipe_ctx->stream;
struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
-   struct rect surf_src = plane_state->src_rect;
-   struct rect clip, dest;
-   int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
-   || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
-   int split_count = 0;
-   int split_idx = 0;
-   bool orthogonal_rotation, flip_y_start, flip_x_start;
-
-   calculate_split_count_and_index(pipe_ctx, &split_count, &split_idx);
 
-   if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE ||
-   stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) {
-   split_count = 0;
-   split_idx = 0;
-   }
-
-   /* The actual clip is an intersection between stream
-* source and surface clip
-*/
-   dest = plane_state->dst_rect;
-   clip.x = stream->src.x > plane_state->clip_rect.x ?
-   stream->src.x : plane_state->clip_rect.x;
-
-   clip.width = stream->src.x + stream->src.width <
-   plane_state->clip_rect.x + plane_state->clip_rect.width 
?
-   stream->src.x + stream->src.width - clip.x :
-   plane_state->clip_rect.x + plane_state->clip_rect.width 
- clip.x ;
-
-   clip.y = stream->src.y > plane_state->clip_rect.y ?
-   stream->src.y : plane_state->clip_rect.y;
-
-   clip.height = stream->src.y + stream->src.height <
-   plane_state->clip_rect.y + 
plane_state->clip_rect.height ?
-   stream->src.y + stream->src.height - clip.y :
-   plane_state->clip_rect.y + 
plane_state->clip_rect.height - clip.y ;
-
-   /*
-* Need to calculate how scan origin is shifted in vp space
-* to correctly rotate clip and dst
-*/
-   get_vp_scan_direction(
-   plane_state->rotation,
-   plane_state->horizontal_mirror,
-   &orthogonal_rotation,
-   &flip_y_start,
-   &flip_x_start);
-
-   if (orthogonal_rotation) {
-   swap(clip.x, clip.y);
-   swap(clip.width, clip.height);
-   swap(dest.x, dest.y);
-   swap(dest.width, dest.height);
-   }
-   if (flip_x_start) {
-   clip.x = dest.x + dest.width - clip.x - clip.width;
-   dest.x = 0;
-   }
-   if (flip_y_start) {
-   clip.y = dest.y + dest.height - clip.y - clip.height;
-   dest.y = 0;
-   }
-
-   /* offset = surf_src.ofs + (clip.ofs - surface->dst_rect.ofs) * 
scl_ratio
-* num_pixels = clip.num_pix * scl_ratio
-*/
-   data->viewport.x = surf_src.x + (clip.x - dest.x) * surf_src.width / 
dest.width;
-   data->viewport.width = clip.width * surf_src.width / dest.width;
-
-   data->viewport.y = surf_src.y + (clip.y - dest.y) * surf_src.height / 
dest.height;
-   data->viewport.height = clip.height * surf_src.height / dest.height;
-
-   /* Handle split */
-   if (split_count) {
-   /* extra pixels in the division remainder need to go to pipes 
after
-* the extra pixel index minus one(epimo) defined here as:
-   

[PATCH 02/15] drm/amd/display: disable desktop VRR when using older flip model

[Qingqing Zhuo]

From: hvanzyll 

[WHY]
OS uses older flip model which does not work with desktop
VRR causing memory allocations at the wrong IRQ level.

[HOW]
Checks added to flip model to verify model is 2.2 or greater when
doing any of the desktop VRR checks for full updates. This
prevents full updates when VRR changes until a mode change.

Signed-off-by: Harry VanZyllDeJong 
Reviewed-by: Jun Lei 
Acked-by: Qingqing Zhuo 
---
 drivers/gpu/drm/amd/display/dc/dc_stream.h|  3 ++
 .../amd/display/modules/freesync/freesync.c   | 29 ---
 2 files changed, 22 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h 
b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index 13dae7238a58..0ab1a33dae84 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -179,6 +179,9 @@ struct dc_stream_state {
 
bool use_vsc_sdp_for_colorimetry;
bool ignore_msa_timing_param;
+
+   bool freesync_on_desktop;
+
bool converter_disable_audio;
uint8_t qs_bit;
uint8_t qy_bit;
diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c 
b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
index 3f4f44b44e6a..b99aa232bd8b 100644
--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
@@ -516,7 +516,8 @@ bool mod_freesync_get_v_position(struct mod_freesync 
*mod_freesync,
 }
 
 static void build_vrr_infopacket_data_v1(const struct mod_vrr_params *vrr,
-   struct dc_info_packet *infopacket)
+   struct dc_info_packet *infopacket,
+   bool freesync_on_desktop)
 {
/* PB1 = 0x1A (24bit AMD IEEE OUI (0x1A) - Byte 0) */
infopacket->sb[1] = 0x1A;
@@ -542,10 +543,16 @@ static void build_vrr_infopacket_data_v1(const struct 
mod_vrr_params *vrr,
vrr->state != VRR_STATE_UNSUPPORTED)
infopacket->sb[6] |= 0x02;
 
-   /* PB6 = [Bit 2 = FreeSync Active] */
-   if (vrr->state != VRR_STATE_DISABLED &&
+   if (freesync_on_desktop) {
+   /* PB6 = [Bit 2 = FreeSync Active] */
+   if (vrr->state != VRR_STATE_DISABLED &&
vrr->state != VRR_STATE_UNSUPPORTED)
-   infopacket->sb[6] |= 0x04;
+   infopacket->sb[6] |= 0x04;
+   } else {
+   if (vrr->state == VRR_STATE_ACTIVE_VARIABLE ||
+   vrr->state == VRR_STATE_ACTIVE_FIXED)
+   infopacket->sb[6] |= 0x04;
+   }
 
// For v1 & 2 infoframes program nominal if non-fs mode, otherwise full 
range
/* PB7 = FreeSync Minimum refresh rate (Hz) */
@@ -824,13 +831,14 @@ static void build_vrr_infopacket_checksum(unsigned int 
*payload_size,
 
 static void build_vrr_infopacket_v1(enum signal_type signal,
const struct mod_vrr_params *vrr,
-   struct dc_info_packet *infopacket)
+   struct dc_info_packet *infopacket,
+   bool freesync_on_desktop)
 {
/* SPD info packet for FreeSync */
unsigned int payload_size = 0;
 
build_vrr_infopacket_header_v1(signal, infopacket, &payload_size);
-   build_vrr_infopacket_data_v1(vrr, infopacket);
+   build_vrr_infopacket_data_v1(vrr, infopacket, freesync_on_desktop);
build_vrr_infopacket_checksum(&payload_size, infopacket);
 
infopacket->valid = true;
@@ -839,12 +847,13 @@ static void build_vrr_infopacket_v1(enum signal_type 
signal,
 static void build_vrr_infopacket_v2(enum signal_type signal,
const struct mod_vrr_params *vrr,
enum color_transfer_func app_tf,
-   struct dc_info_packet *infopacket)
+   struct dc_info_packet *infopacket,
+   bool freesync_on_desktop)
 {
unsigned int payload_size = 0;
 
build_vrr_infopacket_header_v2(signal, infopacket, &payload_size);
-   build_vrr_infopacket_data_v1(vrr, infopacket);
+   build_vrr_infopacket_data_v1(vrr, infopacket, freesync_on_desktop);
 
build_vrr_infopacket_fs2_data(app_tf, infopacket);
 
@@ -953,12 +962,12 @@ void mod_freesync_build_vrr_infopacket(struct 
mod_freesync *mod_freesync,
 #endif
break;
case PACKET_TYPE_FS_V2:
-   build_vrr_infopacket_v2(stream->signal, vrr, app_tf, 
infopacket);
+   build_vrr_infopacket_v2(stream->signal, vrr, app_tf, 
infopacket, stream->freesync_on_desktop);
break;
case PACKET_TYPE_VRR:
case PACKET_TYPE_FS_V1:
default:
-   build_vrr_infopacket_v1(stream->signal, vrr, infopacket);
+   build_vrr_infopacket_v1(stream->signal, vrr, infopacket, 
stream->freesync_on_desktop);
}
 
if (true == pack_sdp_v1_3 &&
-- 
2.25.1

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[PATCH 09/15] drm/amd/display: add exit training mode and update channel coding in LT

[Qingqing Zhuo]

From: Wenjing Liu 

[why]
As recommended by DP specs, source needs to make sure
DPRX exits previous LT mode before configuring new LT params
Nofity what channel coding mode we will use for current link training.

Signed-off-by: Wenjing Liu 
Reviewed-by: Jun Lei 
Acked-by: Qingqing Zhuo 
---
 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 73 ++-
 drivers/gpu/drm/amd/display/dc/dc_link.h  |  2 +-
 .../amd/display/include/link_service_types.h  |  1 +
 3 files changed, 58 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index d9b538e193c4..60aa4876300b 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -1324,6 +1324,11 @@ static inline void decide_8b_10b_training_settings(
lt_settings->enhanced_framing = *overrides->enhanced_framing;
else
lt_settings->enhanced_framing = 1;
+
+   if (link->preferred_training_settings.fec_enable != NULL)
+   lt_settings->should_set_fec_ready = 
*link->preferred_training_settings.fec_enable;
+   else
+   lt_settings->should_set_fec_ready = true;
 }
 
 void dp_decide_training_settings(
@@ -1614,29 +1619,68 @@ enum dc_status dpcd_configure_lttpr_mode(struct dc_link 
*link, struct link_train
return status;
 }
 
+static void dpcd_exit_training_mode(struct dc_link *link)
+{
+   const uint8_t clear_pattern = 0;
+
+   /* clear training pattern set */
+   core_link_write_dpcd(
+   link,
+   DP_TRAINING_PATTERN_SET,
+   &clear_pattern,
+   sizeof(clear_pattern));
+   DC_LOG_HW_LINK_TRAINING("%s\n %x pattern = %x\n",
+   __func__,
+   DP_TRAINING_PATTERN_SET,
+   clear_pattern);
+}
+
+enum dc_status dpcd_configure_channel_coding(struct dc_link *link,
+   struct link_training_settings *lt_settings)
+{
+   enum dp_link_encoding encoding =
+   dp_get_link_encoding_format(
+   <_settings->link_settings);
+   enum dc_status status;
+
+   status = core_link_write_dpcd(
+   link,
+   DP_MAIN_LINK_CHANNEL_CODING_SET,
+   (uint8_t *) &encoding,
+   1);
+   DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X MAIN_LINK_CHANNEL_CODING_SET = 
%x\n",
+   __func__,
+   DP_MAIN_LINK_CHANNEL_CODING_SET,
+   encoding);
+
+   return status;
+}
+
 enum link_training_result dc_link_dp_perform_link_training(
struct dc_link *link,
-   const struct dc_link_settings *link_setting,
+   const struct dc_link_settings *link_settings,
bool skip_video_pattern)
 {
enum link_training_result status = LINK_TRAINING_SUCCESS;
struct link_training_settings lt_settings;
 
-   bool fec_enable;
-   uint8_t repeater_cnt;
-   uint8_t repeater_id;
+   /* reset previous training states */
+   dpcd_exit_training_mode(link);
 
+   /* decide training settings */
dp_decide_training_settings(
link,
-   link_setting,
+   link_settings,
&link->preferred_training_settings,
<_settings);
+   dpcd_configure_lttpr_mode(link, <_settings);
+   dp_set_fec_ready(link, lt_settings.should_set_fec_ready);
+   dpcd_configure_channel_coding(link, <_settings);
 
-   /* Configure lttpr mode */
-   if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT)
-   configure_lttpr_mode_non_transparent(link, <_settings);
-   else if (link->lttpr_mode == LTTPR_MODE_TRANSPARENT)
-   configure_lttpr_mode_transparent(link);
+   /* enter training mode:
+* Per DP specs starting from here, DPTX device shall not issue
+* Non-LT AUX transactions inside training mode.
+*/
 
if (link->ctx->dc->work_arounds.lt_early_cr_pattern)
start_clock_recovery_pattern_early(link, <_settings, DPRX);
@@ -1644,14 +1688,9 @@ enum link_training_result 
dc_link_dp_perform_link_training(
/* 1. set link rate, lane count and spread. */
dpcd_set_link_settings(link, <_settings);
 
-   if (link->preferred_training_settings.fec_enable != NULL)
-   fec_enable = *link->preferred_training_settings.fec_enable;
-   else
-   fec_enable = true;
-
-   dp_set_fec_ready(link, fec_enable);
-
if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {
+   uint8_t repeater_cnt;
+   uint8_t repeater_id;
 
/* 2. perform link training (set link training done
 *  to 

[PATCH 11/15] drm/amd/display: Add Log for SST DSC Determination Policy

[Qingqing Zhuo]

From: Fangzhi Zuo 

[Why & How]
To facilitate DSC debugging purpose

Signed-off-by: Fangzhi Zuo 
Reviewed-by: Nicholas Kazlauskas 
Acked-by: Qingqing Zhuo 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index c582c424460a..ac8dc341d956 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -5791,8 +5791,10 @@ create_stream_for_sink(struct amdgpu_dm_connector 
*aconnector,
  0,
  link_bandwidth_kbps,
  &stream->timing,
- &stream->timing.dsc_cfg))
+ &stream->timing.dsc_cfg)) {
stream->timing.flags.DSC = 1;
+   DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from 
SST RX\n", __func__, drm_connector->name);
+   }
/* Overwrite the stream flag if DSC is enabled through 
debugfs */
if (aconnector->dsc_settings.dsc_force_enable == 
DSC_CLK_FORCE_ENABLE)
stream->timing.flags.DSC = 1;
-- 
2.25.1

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[PATCH 10/15] drm/amd/display: isolate 8b 10b link training sequence into its own function

[Qingqing Zhuo]

From: Wenjing Liu 

[how]
1. move 8b 10 link trianing into its own function
2. make link status check after a link success link as part of
dp transition to video idle sequence.

Signed-off-by: Wenjing Liu 
Reviewed-by: Jun Lei 
Acked-by: Qingqing Zhuo 
---
 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 118 +-
 1 file changed, 62 insertions(+), 56 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 60aa4876300b..15f089e4fa1f 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -1170,8 +1170,16 @@ static inline enum link_training_result 
dp_transition_to_video_idle(
 * TPS4 must be used instead of POST_LT_ADJ_REQ.
 */
if (link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED != 1 ||
-   lt_settings->pattern_for_eq == 
DP_TRAINING_PATTERN_SEQUENCE_4)
+   lt_settings->pattern_for_eq == 
DP_TRAINING_PATTERN_SEQUENCE_4) {
+   /* delay 5ms after Main Link output idle pattern and then check
+* DPCD 0202h.
+*/
+   if (link->connector_signal != SIGNAL_TYPE_EDP && status == 
LINK_TRAINING_SUCCESS) {
+   msleep(5);
+   status = dp_check_link_loss_status(link, lt_settings);
+   }
return status;
+   }
 
if (status == LINK_TRAINING_SUCCESS &&
perform_post_lt_adj_req_sequence(link, lt_settings) == false)
@@ -1621,18 +1629,9 @@ enum dc_status dpcd_configure_lttpr_mode(struct dc_link 
*link, struct link_train
 
 static void dpcd_exit_training_mode(struct dc_link *link)
 {
-   const uint8_t clear_pattern = 0;
 
/* clear training pattern set */
-   core_link_write_dpcd(
-   link,
-   DP_TRAINING_PATTERN_SET,
-   &clear_pattern,
-   sizeof(clear_pattern));
-   DC_LOG_HW_LINK_TRAINING("%s\n %x pattern = %x\n",
-   __func__,
-   DP_TRAINING_PATTERN_SET,
-   clear_pattern);
+   dpcd_set_training_pattern(link, DP_TRAINING_PATTERN_VIDEOIDLE);
 }
 
 enum dc_status dpcd_configure_channel_coding(struct dc_link *link,
@@ -1656,41 +1655,22 @@ enum dc_status dpcd_configure_channel_coding(struct 
dc_link *link,
return status;
 }
 
-enum link_training_result dc_link_dp_perform_link_training(
-   struct dc_link *link,
-   const struct dc_link_settings *link_settings,
-   bool skip_video_pattern)
+static enum link_training_result dp_perform_8b_10b_link_training(
+   struct dc_link *link,
+   struct link_training_settings *lt_settings)
 {
enum link_training_result status = LINK_TRAINING_SUCCESS;
-   struct link_training_settings lt_settings;
 
-   /* reset previous training states */
-   dpcd_exit_training_mode(link);
-
-   /* decide training settings */
-   dp_decide_training_settings(
-   link,
-   link_settings,
-   &link->preferred_training_settings,
-   <_settings);
-   dpcd_configure_lttpr_mode(link, <_settings);
-   dp_set_fec_ready(link, lt_settings.should_set_fec_ready);
-   dpcd_configure_channel_coding(link, <_settings);
-
-   /* enter training mode:
-* Per DP specs starting from here, DPTX device shall not issue
-* Non-LT AUX transactions inside training mode.
-*/
+   uint8_t repeater_cnt;
+   uint8_t repeater_id;
 
if (link->ctx->dc->work_arounds.lt_early_cr_pattern)
-   start_clock_recovery_pattern_early(link, <_settings, DPRX);
+   start_clock_recovery_pattern_early(link, lt_settings, DPRX);
 
/* 1. set link rate, lane count and spread. */
-   dpcd_set_link_settings(link, <_settings);
+   dpcd_set_link_settings(link, lt_settings);
 
if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {
-   uint8_t repeater_cnt;
-   uint8_t repeater_id;
 
/* 2. perform link training (set link training done
 *  to false is done as well)
@@ -1699,13 +1679,13 @@ enum link_training_result 
dc_link_dp_perform_link_training(
 
for (repeater_id = repeater_cnt; (repeater_id > 0 && status == 
LINK_TRAINING_SUCCESS);
repeater_id--) {
-   status = perform_clock_recovery_sequence(link, 
<_settings, repeater_id);
+   status = perform_clock_recovery_sequence(link, 
lt_settings, repeater_id);
 
if (status != LINK_TRAINING_SUCCESS)
break;
 
status = perform_channel_equalization_sequence(link,
-   <_settings,
+   

[PATCH 05/15] drm/amd/display: Expand DP module clock recovery API.

[Qingqing Zhuo]

From: Jimmy Kizito 

[Why & How]
Add functionality useful for DP clock recovery phase of link training to
public interface.

Signed-off-by: Jimmy Kizito 
Reviewed-by: Jun Lei 
Acked-by: Qingqing Zhuo 
---
 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 79 +--
 .../gpu/drm/amd/display/dc/inc/dc_link_dp.h   | 49 
 2 files changed, 85 insertions(+), 43 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 5812412382c0..d9b538e193c4 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -25,8 +25,6 @@ static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA";
link->ctx->logger
 #define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */
 
-#define DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE   0x50
-
/* maximum pre emphasis level allowed for each voltage swing level*/
static const enum dc_pre_emphasis
voltage_swing_to_pre_emphasis[] = { PRE_EMPHASIS_LEVEL3,
@@ -39,14 +37,6 @@ enum {
POST_LT_ADJ_REQ_TIMEOUT = 200
 };
 
-enum {
-   LINK_TRAINING_MAX_RETRY_COUNT = 5,
-   /* to avoid infinite loop where-in the receiver
-* switches between different VS
-*/
-   LINK_TRAINING_MAX_CR_RETRY = 100
-};
-
 static bool decide_fallback_link_setting(
struct dc_link_settings initial_link_settings,
struct dc_link_settings *current_link_setting,
@@ -97,7 +87,7 @@ static uint32_t get_eq_training_aux_rd_interval(
return wait_in_micro_secs;
 }
 
-static void wait_for_training_aux_rd_interval(
+void dp_wait_for_training_aux_rd_interval(
struct dc_link *link,
uint32_t wait_in_micro_secs)
 {
@@ -108,7 +98,7 @@ static void wait_for_training_aux_rd_interval(
wait_in_micro_secs);
 }
 
-static enum dpcd_training_patterns
+enum dpcd_training_patterns
dc_dp_training_pattern_to_dpcd_training_pattern(
struct dc_link *link,
enum dc_dp_training_pattern pattern)
@@ -284,7 +274,7 @@ enum dc_status dpcd_set_link_settings(
return status;
 }
 
-static uint8_t dc_dp_initialize_scrambling_data_symbols(
+uint8_t dc_dp_initialize_scrambling_data_symbols(
struct dc_link *link,
enum dc_dp_training_pattern pattern)
 {
@@ -433,7 +423,7 @@ static void dpcd_set_lt_pattern_and_lane_settings(
link->cur_lane_setting = lt_settings->lane_settings[0];
 }
 
-static bool is_cr_done(enum dc_lane_count ln_count,
+bool dp_is_cr_done(enum dc_lane_count ln_count,
union lane_status *dpcd_lane_status)
 {
uint32_t lane;
@@ -472,7 +462,7 @@ static inline bool is_interlane_aligned(union 
lane_align_status_updated align_st
return align_status.bits.INTERLANE_ALIGN_DONE == 1;
 }
 
-static void update_drive_settings(
+void dp_update_drive_settings(
struct link_training_settings *dest,
struct link_training_settings src)
 {
@@ -616,7 +606,7 @@ static void find_max_drive_settings(
 
 }
 
-static void get_lane_status_and_drive_settings(
+enum dc_status dp_get_lane_status_and_drive_settings(
struct dc_link *link,
const struct link_training_settings *link_training_setting,
union lane_status *ln_status,
@@ -631,6 +621,7 @@ static void get_lane_status_and_drive_settings(
union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
struct link_training_settings request_settings = { {0} };
uint32_t lane;
+   enum dc_status status;
 
memset(req_settings, '\0', sizeof(struct link_training_settings));
 
@@ -641,7 +632,7 @@ static void get_lane_status_and_drive_settings(
lane_adjust_offset = 3;
}
 
-   core_link_read_dpcd(
+   status = core_link_read_dpcd(
link,
lane01_status_address,
(uint8_t *)(dpcd_buf),
@@ -729,9 +720,10 @@ static void get_lane_status_and_drive_settings(
 * read DpcdAddress_AdjustRequestPostCursor2 = 0x020C
 */
 
+   return status;
 }
 
-static void dpcd_set_lane_settings(
+enum dc_status dpcd_set_lane_settings(
struct dc_link *link,
const struct link_training_settings *link_training_setting,
uint32_t offset)
@@ -739,6 +731,7 @@ static void dpcd_set_lane_settings(
union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = {{{0}}};
uint32_t lane;
unsigned int lane0_set_address;
+   enum dc_status status;
 
lane0_set_address = DP_TRAINING_LANE0_SET;
 
@@ -766,7 +759,7 @@ static void dpcd_set_lane_settings(
PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
}
 
-   core_link_write_dpcd(link,
+   status = core_link_write_dpcd(link,
lane0_set_address,
(uint8_t *)(dpcd_lane),
link_training_setting->link_settings.lane_count);
@@ -812,9 +805,10 @@ static void dpcd_set_lane_setting

[PATCH 12/15] drm/amd/display: Refactor SST DSC Determination Policy

[Qingqing Zhuo]

From: Fangzhi Zuo 

[Why & How]
SST dsc determination policy becomes bigger when more scenarios
are introduced. Take it out to make it clean and readable.

Signed-off-by: Fangzhi Zuo 
Reviewed-by: Nicholas Kazlauskas 
Acked-by: Qingqing Zhuo 
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 105 +++---
 1 file changed, 63 insertions(+), 42 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index ac8dc341d956..f0703fe22c68 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -5577,6 +5577,65 @@ static void dm_enable_per_frame_crtc_master_sync(struct 
dc_state *context)
}
 }
 
+static void update_dsc_caps(struct amdgpu_dm_connector *aconnector,
+   struct dc_sink *sink, 
struct dc_stream_state *stream,
+   struct 
dsc_dec_dpcd_caps *dsc_caps)
+{
+   stream->timing.flags.DSC = 0;
+
+   if (aconnector->dc_link && sink->sink_signal == 
SIGNAL_TYPE_DISPLAY_PORT) {
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+   dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
+ 
aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
+ 
aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
+ dsc_caps);
+#endif
+   }
+}
+
+static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector,
+   
struct dc_sink *sink, struct dc_stream_state *stream,
+   
struct dsc_dec_dpcd_caps *dsc_caps)
+{
+   struct drm_connector *drm_connector = &aconnector->base;
+   uint32_t link_bandwidth_kbps;
+
+   link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
+   
dc_link_get_link_cap(aconnector->dc_link));
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+   /* Set DSC policy according to dsc_clock_en */
+   dc_dsc_policy_set_enable_dsc_when_not_needed(
+   aconnector->dsc_settings.dsc_force_enable == 
DSC_CLK_FORCE_ENABLE);
+
+   if (aconnector->dc_link && sink->sink_signal == 
SIGNAL_TYPE_DISPLAY_PORT) {
+
+   if 
(dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
+   dsc_caps,
+   
aconnector->dc_link->ctx->dc->debug.dsc_min_slice_height_override,
+   0,
+   link_bandwidth_kbps,
+   &stream->timing,
+   &stream->timing.dsc_cfg)) {
+   stream->timing.flags.DSC = 1;
+   DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from SST 
RX\n", __func__, drm_connector->name);
+   }
+   }
+
+   /* Overwrite the stream flag if DSC is enabled through debugfs */
+   if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE)
+   stream->timing.flags.DSC = 1;
+
+   if (stream->timing.flags.DSC && 
aconnector->dsc_settings.dsc_num_slices_h)
+   stream->timing.dsc_cfg.num_slices_h = 
aconnector->dsc_settings.dsc_num_slices_h;
+
+   if (stream->timing.flags.DSC && 
aconnector->dsc_settings.dsc_num_slices_v)
+   stream->timing.dsc_cfg.num_slices_v = 
aconnector->dsc_settings.dsc_num_slices_v;
+
+   if (stream->timing.flags.DSC && 
aconnector->dsc_settings.dsc_bits_per_pixel)
+   stream->timing.dsc_cfg.bits_per_pixel = 
aconnector->dsc_settings.dsc_bits_per_pixel;
+#endif
+}
+
 static struct drm_display_mode *
 get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector,
  bool use_probed_modes)
@@ -5678,7 +5737,6 @@ create_stream_for_sink(struct amdgpu_dm_connector 
*aconnector,
int preferred_refresh = 0;
 #if defined(CONFIG_DRM_AMD_DC_DCN)
struct dsc_dec_dpcd_caps dsc_caps;
-   uint32_t link_bandwidth_kbps;
 #endif
struct dc_sink *sink = NULL;
 
@@ -5769,47 +5827,10 @@ create_stream_for_sink(struct amdgpu_dm_connector 
*aconnector,
stream, &mode, &aconnector->base, con_state, old_stream,
requested_bpc);
 
-   stream->timing.flags.DSC = 0;
-
-   if (aconnector->dc_link && sink->sink_signal == 
SIGNAL_TYPE_DISPLAY_PORT) {
-#if defined(CONFIG_DRM_AMD_DC_DCN)
-   dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
- 
aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
- 
aconnector->d

[PATCH 06/15] drm/amd/display: Remove redundant safeguards for dmub-srv destroy()

[Qingqing Zhuo]

From: Roman Li 

[Why]
dc_dmub_srv_destroy() has internal null-check and null assignment.
No need to duplicate them externally.

[How]
Remove redundant safeguards.

Signed-off-by: Lang Yu 
Signed-off-by: Roman Li 
Reviewed-by: Nicholas Kazlauskas 
Acked-by: Qingqing Zhuo 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 +
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 40d119354509..9be4ebb5fac4 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1329,10 +1329,7 @@ static void amdgpu_dm_fini(struct amdgpu_device *adev)
}
 #endif
 
-   if (adev->dm.dc->ctx->dmub_srv) {
-   dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);
-   adev->dm.dc->ctx->dmub_srv = NULL;
-   }
+   dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);
 
if (dc_enable_dmub_notifications(adev->dm.dc)) {
kfree(adev->dm.dmub_notify);
-- 
2.25.1

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[PATCH 07/15] drm/amd/display: Fix potential memory leak in DMUB hw_init

[Qingqing Zhuo]

From: Roman Li 

[Why]
On resume we perform DMUB hw_init which allocates memory:
dm_resume->dm_dmub_hw_init->dc_dmub_srv_create->kzalloc
That results in memory leak in suspend/resume scenarios.

[How]
Allocate memory for the DC wrapper to DMUB only if it was not
allocated before.
No need to reallocate it on suspend/resume.

Signed-off-by: Lang Yu 
Signed-off-by: Roman Li 
Reviewed-by: Nicholas Kazlauskas 
Acked-by: Qingqing Zhuo 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 9be4ebb5fac4..c582c424460a 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -981,7 +981,8 @@ static int dm_dmub_hw_init(struct amdgpu_device *adev)
abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
}
 
-   adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv);
+   if (!adev->dm.dc->ctx->dmub_srv)
+   adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, 
dmub_srv);
if (!adev->dm.dc->ctx->dmub_srv) {
DRM_ERROR("Couldn't allocate DC DMUB server!\n");
return -ENOMEM;
@@ -2003,7 +2004,6 @@ static int dm_suspend(void *handle)
 
amdgpu_dm_irq_suspend(adev);
 
-
dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
 
return 0;
-- 
2.25.1

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[PATCH 08/15] drm/amd/display: Implement INBOX0 usage in driver

[Qingqing Zhuo]

From: Alvin Lee 

[Why]
Start using INBOX0 for HW Lock command

[How]
- Implement initial interface for INBOX0 HW lock message

Signed-off-by: Alvin Lee 
Reviewed-by: Jun Lei 
Acked-by: Qingqing Zhuo 
---
 drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c  | 9 +
 drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h  | 2 ++
 drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c | 8 
 drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h | 3 +++
 drivers/gpu/drm/amd/display/dmub/dmub_srv.h   | 1 +
 5 files changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c 
b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
index c5dc3a947020..4b2854d1d981 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
@@ -110,6 +110,15 @@ void dc_dmub_srv_wait_idle(struct dc_dmub_srv *dc_dmub_srv)
DC_ERROR("Error waiting for DMUB idle: status=%d\n", status);
 }
 
+void dc_dmub_srv_send_inbox0_cmd(struct dc_dmub_srv *dmub_srv,
+   union dmub_inbox0_data_register data)
+{
+   struct dmub_srv *dmub = dmub_srv->dmub;
+   if (dmub->hw_funcs.send_inbox0_cmd)
+   dmub->hw_funcs.send_inbox0_cmd(dmub, data);
+   // TODO: Add wait command -- poll register for ACK
+}
+
 bool dc_dmub_srv_cmd_with_reply_data(struct dc_dmub_srv *dc_dmub_srv, union 
dmub_rb_cmd *cmd)
 {
struct dmub_srv *dmub;
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h 
b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
index 338f776990db..f615e3a76d01 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
@@ -66,4 +66,6 @@ bool dc_dmub_srv_get_dmub_outbox0_msg(const struct dc *dc, 
struct dmcub_trace_bu
 
 void dc_dmub_trace_event_control(struct dc *dc, bool enable);
 
+void dc_dmub_srv_send_inbox0_cmd(struct dc_dmub_srv *dmub_srv, union 
dmub_inbox0_data_register data);
+
 #endif /* _DMUB_DC_SRV_H_ */
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c 
b/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c
index c97ee5abc0ef..9baf8ca0a920 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c
@@ -52,6 +52,14 @@ void dmub_hw_lock_mgr_cmd(struct dc_dmub_srv *dmub_srv,
dc_dmub_srv_wait_idle(dmub_srv);
 }
 
+void dmub_hw_lock_mgr_inbox0_cmd(struct dc_dmub_srv *dmub_srv,
+   union dmub_inbox0_cmd_lock_hw hw_lock_cmd)
+{
+   union dmub_inbox0_data_register data = { 0 };
+   data.inbox0_cmd_lock_hw = hw_lock_cmd;
+   dc_dmub_srv_send_inbox0_cmd(dmub_srv, data);
+}
+
 bool should_use_dmub_lock(struct dc_link *link)
 {
return false;
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h 
b/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h
index bc5906347493..5a72b168fb4a 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h
@@ -34,6 +34,9 @@ void dmub_hw_lock_mgr_cmd(struct dc_dmub_srv *dmub_srv,
union dmub_hw_lock_flags *hw_locks,
struct dmub_hw_lock_inst_flags *inst_flags);
 
+void dmub_hw_lock_mgr_inbox0_cmd(struct dc_dmub_srv *dmub_srv,
+   union dmub_inbox0_cmd_lock_hw hw_lock_cmd);
+
 bool should_use_dmub_lock(struct dc_link *link);
 
 #endif /*_DMUB_HW_LOCK_MGR_H_ */
diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h 
b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
index 79ff68c13902..ed58abc5b3f9 100644
--- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
+++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
@@ -324,6 +324,7 @@ struct dmub_srv_hw_funcs {
 
uint32_t (*get_gpint_response)(struct dmub_srv *dmub);
 
+   void (*send_inbox0_cmd)(struct dmub_srv *dmub, union 
dmub_inbox0_data_register data);
uint32_t (*get_current_time)(struct dmub_srv *dmub);
 };
 
-- 
2.25.1

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[PATCH 04/15] drm/amd/display: Update DP link configuration.

[Qingqing Zhuo]

From: Jimmy Kizito 

[Why & How]
- Update application of training settings for links whose encoders are
assigned dynamically.
- Add functionality useful for DP link configuration to public
interface.

Signed-off-by: Jimmy Kizito 
Reviewed-by: Jun Lei 
Acked-by: Qingqing Zhuo 
---
 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 91 ++-
 .../gpu/drm/amd/display/dc/inc/dc_link_dp.h   | 17 +++-
 2 files changed, 83 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 9e08410bfdfd..5812412382c0 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -206,11 +206,12 @@ static enum dc_dp_training_pattern 
decide_eq_training_pattern(struct dc_link *li
return DP_TRAINING_PATTERN_SEQUENCE_2;
 }
 
-static void dpcd_set_link_settings(
+enum dc_status dpcd_set_link_settings(
struct dc_link *link,
const struct link_training_settings *lt_settings)
 {
uint8_t rate;
+   enum dc_status status;
 
union down_spread_ctrl downspread = { {0} };
union lane_count_set lane_count_set = { {0} };
@@ -225,15 +226,16 @@ static void dpcd_set_link_settings(
lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
 
 
-   if (lt_settings->pattern_for_eq < DP_TRAINING_PATTERN_SEQUENCE_4) {
+   if (link->ep_type == DISPLAY_ENDPOINT_PHY &&
+   lt_settings->pattern_for_eq < 
DP_TRAINING_PATTERN_SEQUENCE_4) {
lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED =

link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED;
}
 
-   core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
+   status = core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
&downspread.raw, sizeof(downspread));
 
-   core_link_write_dpcd(link, DP_LANE_COUNT_SET,
+   status = core_link_write_dpcd(link, DP_LANE_COUNT_SET,
&lane_count_set.raw, 1);
 
if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 &&
@@ -249,12 +251,12 @@ static void dpcd_set_link_settings(
core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES,
supported_link_rates, 
sizeof(supported_link_rates));
}
-   core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
-   core_link_write_dpcd(link, DP_LINK_RATE_SET,
+   status = core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
+   status = core_link_write_dpcd(link, DP_LINK_RATE_SET,
<_settings->link_settings.link_rate_set, 1);
} else {
rate = (uint8_t) (lt_settings->link_settings.link_rate);
-   core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
+   status = core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
}
 
if (rate) {
@@ -278,6 +280,8 @@ static void dpcd_set_link_settings(
DP_DOWNSPREAD_CTRL,
lt_settings->link_settings.link_spread);
}
+
+   return status;
 }
 
 static uint8_t dc_dp_initialize_scrambling_data_symbols(
@@ -1329,7 +1333,7 @@ static inline void decide_8b_10b_training_settings(
lt_settings->enhanced_framing = 1;
 }
 
-static void decide_training_settings(
+void dp_decide_training_settings(
struct dc_link *link,
const struct dc_link_settings *link_settings,
const struct dc_link_training_overrides *overrides,
@@ -1365,18 +1369,18 @@ uint8_t dp_convert_to_count(uint8_t 
lttpr_repeater_count)
return 0; // invalid value
 }
 
-static void configure_lttpr_mode_transparent(struct dc_link *link)
+enum dc_status configure_lttpr_mode_transparent(struct dc_link *link)
 {
uint8_t repeater_mode = DP_PHY_REPEATER_MODE_TRANSPARENT;
 
DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Transparent Mode\n", 
__func__);
-   core_link_write_dpcd(link,
+   return core_link_write_dpcd(link,
DP_PHY_REPEATER_MODE,
(uint8_t *)&repeater_mode,
sizeof(repeater_mode));
 }
 
-static void configure_lttpr_mode_non_transparent(
+enum dc_status configure_lttpr_mode_non_transparent(
struct dc_link *link,
const struct link_training_settings *lt_settings)
 {
@@ -1431,6 +1435,8 @@ static void configure_lttpr_mode_non_transparent(
}
}
}
+
+   return result;
 }
 
 static void repeater_training_done(struct dc_link *link, uint32_t offset)
@@ -1564,7 +1570,7 @@ bool dc_link_dp_perform_link_training_skip_aux(
 {
struct link_training_settings lt_settings;
 
-   decide_training_settings(
+   dp_decide_training_settings(
link,
link_setting,
&l

[PATCH 01/15] drm/amd/display: Added support for individual control for multiple back-light instances.

[Qingqing Zhuo]

From: Jake Wang 

[Why & How]
Added support for individual control for multiple back-light instances.

Signed-off-by: Jake Wang 
Reviewed-by: Anthony Koo 
Acked-by: Qingqing Zhuo 
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 26 +++
 drivers/gpu/drm/amd/display/dc/dc_link.h  | 17 
 drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c | 10 +++
 drivers/gpu/drm/amd/display/dc/inc/hw/abm.h   |  3 ++-
 .../amd/display/modules/power/power_helpers.c | 15 ++-
 .../amd/display/modules/power/power_helpers.h |  3 ++-
 6 files changed, 47 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 8cd270f12918..40d119354509 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1709,7 +1709,6 @@ static int dm_late_init(void *handle)
unsigned int linear_lut[16];
int i;
struct dmcu *dmcu = NULL;
-   bool ret = true;
 
dmcu = adev->dm.dc->res_pool->dmcu;
 
@@ -1726,18 +1725,23 @@ static int dm_late_init(void *handle)
 * 0x x 0.01 = 0x28F
 */
params.min_abm_backlight = 0x28F;
-
/* In the case where abm is implemented on dmcub,
-* dmcu object will be null.
-* ABM 2.4 and up are implemented on dmcub.
-*/
-   if (dmcu)
-   ret = dmcu_load_iram(dmcu, params);
-   else if (adev->dm.dc->ctx->dmub_srv)
-   ret = dmub_init_abm_config(adev->dm.dc->res_pool, params);
+   * dmcu object will be null.
+   * ABM 2.4 and up are implemented on dmcub.
+   */
+   if (dmcu) {
+   if (!dmcu_load_iram(dmcu, params))
+   return -EINVAL;
+   } else if (adev->dm.dc->ctx->dmub_srv) {
+   struct dc_link *edp_links[MAX_NUM_EDP];
+   int edp_num;
 
-   if (!ret)
-   return -EINVAL;
+   get_edp_links(adev->dm.dc, edp_links, &edp_num);
+   for (i = 0; i < edp_num; i++) {
+   if (!dmub_init_abm_config(adev->dm.dc->res_pool, 
params, i))
+   return -EINVAL;
+   }
+   }
 
return detect_mst_link_for_all_connectors(adev_to_drm(adev));
 }
diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h 
b/drivers/gpu/drm/amd/display/dc/dc_link.h
index c871923e7db0..c617e9ae68a3 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_link.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
@@ -216,6 +216,23 @@ static inline void get_edp_links(const struct dc *dc,
}
 }
 
+static inline bool dc_get_edp_link_panel_inst(const struct dc *dc,
+   const struct dc_link *link,
+   unsigned int *inst_out)
+{
+   struct dc_link *edp_links[MAX_NUM_EDP];
+   int edp_num;
+
+   if (link->connector_signal != SIGNAL_TYPE_EDP)
+   return false;
+   get_edp_links(dc, edp_links, &edp_num);
+   if ((edp_num > 1) && (link->link_index > edp_links[0]->link_index))
+   *inst_out = 1;
+   else
+   *inst_out = 0;
+   return true;
+}
+
 /* Set backlight level of an embedded panel (eDP, LVDS).
  * backlight_pwm_u16_16 is unsigned 32 bit with 16 bit integer
  * and 16 bit fractional, where 1.0 is max backlight value.
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c 
b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
index 6939ca2e8212..54a1408c8015 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
@@ -172,16 +172,12 @@ static bool dmub_abm_set_level(struct abm *abm, uint32_t 
level)
 
 static bool dmub_abm_init_config(struct abm *abm,
const char *src,
-   unsigned int bytes)
+   unsigned int bytes,
+   unsigned int inst)
 {
union dmub_rb_cmd cmd;
struct dc_context *dc = abm->ctx;
-   uint32_t edp_id_count = dc->dc_edp_id_count;
-   int i;
-   uint8_t panel_mask = 0;
-
-   for (i = 0; i < edp_id_count; i++)
-   panel_mask |= 0x01 << i;
+   uint8_t panel_mask = 0x01 << inst;
 
// TODO: Optimize by only reading back final 4 bytes
dmub_flush_buffer_mem(&dc->dmub_srv->dmub->scratch_mem_fb);
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h 
b/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h
index e8ce8c85adf1..142753644377 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h
@@ -52,7 +52,8 @@ struct abm_funcs {
unsigned int (*get_target_backlight)(struct abm *abm);
bool (*init_abm_config)(struct abm *abm,
const char *src,
-   unsigned int bytes);
+   unsigned int bytes,
+   unsigned int inst);
 };
 
 #endif
diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c 
b/drivers/gpu/drm/amd/displ

[PATCH 03/15] drm/amd/display: Retrieve DSC Branch Decoder Caps

[Qingqing Zhuo]

From: Fangzhi Zuo 

DSC extended branch decoder caps 0xA0 ~ 0xA2 is read from dsc_aux.
The dsc_aux is returned from drm dsc determination policy with the
right DSC capable MST branch device for decoding.

The values are all zero if DSC decoding at a MST BU with virtual DPCD;
The values are meaningful when DSC decoding at a MST BU without
virtual DPCD or at a DSC capable MST endpoint.

Signed-off-by: Fangzhi Zuo 
Reviewed-by: Nicholas Kazlauskas 
Acked-by: Qingqing Zhuo 
---
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c| 10 --
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index f3a9bc828b91..0fca1e842552 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -160,6 +160,8 @@ static bool validate_dsc_caps_on_connector(struct 
amdgpu_dm_connector *aconnecto
struct dc_sink *dc_sink = aconnector->dc_sink;
struct drm_dp_mst_port *port = aconnector->port;
u8 dsc_caps[16] = { 0 };
+   u8 dsc_branch_dec_caps_raw[3] = { 0 };  // DSC branch decoder caps 0xA0 
~ 0xA2
+   u8 *dsc_branch_dec_caps = NULL;
 
aconnector->dsc_aux = drm_dp_mst_dsc_aux_for_port(port);
 #if defined(CONFIG_HP_HOOK_WORKAROUND)
@@ -182,9 +184,13 @@ static bool validate_dsc_caps_on_connector(struct 
amdgpu_dm_connector *aconnecto
if (drm_dp_dpcd_read(aconnector->dsc_aux, DP_DSC_SUPPORT, dsc_caps, 16) 
< 0)
return false;
 
+   if (drm_dp_dpcd_read(aconnector->dsc_aux,
+   DP_DSC_BRANCH_OVERALL_THROUGHPUT_0, 
dsc_branch_dec_caps_raw, 3) == 3)
+   dsc_branch_dec_caps = dsc_branch_dec_caps_raw;
+
if (!dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
-  dsc_caps, NULL,
-  &dc_sink->dsc_caps.dsc_dec_caps))
+ dsc_caps, dsc_branch_dec_caps,
+ &dc_sink->dsc_caps.dsc_dec_caps))
return false;
 
return true;
-- 
2.25.1

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[PATCH 00/15] DC Patches May 24th, 2021

[Qingqing Zhuo]

This DC patchset brings improvements in multiple areas.
In summary, we highlight:

  - DC 3.2.137
  - Updates on DP configurations and clock recovery API
  - Improvements on DSC, link training sequence, etc.
  - Fixes on memory leak, ODM scaling, etc.

---

Alvin Lee (1):
  drm/amd/display: Implement INBOX0 usage in driver

Aric Cyr (1):
  drm/amd/display: 3.2.137

Dmytro Laktyushkin (1):
  drm/amd/display: fix odm scaling

Fangzhi Zuo (3):
  drm/amd/display: Retrieve DSC Branch Decoder Caps
  drm/amd/display: Add Log for SST DSC Determination Policy
  drm/amd/display: Refactor SST DSC Determination Policy

Jake Wang (1):
  drm/amd/display: Added support for individual control for multiple
back-light instances.

Jimmy Kizito (2):
  drm/amd/display: Update DP link configuration.
  drm/amd/display: Expand DP module clock recovery API.

Qingqing Zhuo (1):
  Revert "drm/amd/display: Refactor and add visual confirm for HW Flip
Queue"

Roman Li (2):
  drm/amd/display: Remove redundant safeguards for dmub-srv destroy()
  drm/amd/display: Fix potential memory leak in DMUB hw_init

Wenjing Liu (2):
  drm/amd/display: add exit training mode and update channel coding in
LT
  drm/amd/display: isolate 8b 10b link training sequence into its own
function

hvanzyll (1):
  drm/amd/display: disable desktop VRR when using older flip model

 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 138 +++--
 .../display/amdgpu_dm/amdgpu_dm_mst_types.c   |  10 +-
 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 307 ++
 .../gpu/drm/amd/display/dc/core/dc_resource.c | 568 +++---
 drivers/gpu/drm/amd/display/dc/dc.h   |   2 +-
 drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c  |   9 +
 drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h  |   2 +
 drivers/gpu/drm/amd/display/dc/dc_link.h  |  19 +-
 drivers/gpu/drm/amd/display/dc/dc_stream.h|   3 +
 drivers/gpu/drm/amd/display/dc/dc_types.h |   5 -
 drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c |  10 +-
 .../drm/amd/display/dc/dce/dmub_hw_lock_mgr.c |   8 +
 .../drm/amd/display/dc/dce/dmub_hw_lock_mgr.h |   3 +
 .../drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c |  12 +-
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c |  31 +-
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.h |   6 -
 .../gpu/drm/amd/display/dc/dcn10/dcn10_init.c |   1 -
 .../gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c  |   5 -
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.c|  28 +-
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.h|   5 -
 .../gpu/drm/amd/display/dc/dcn20/dcn20_init.c |   1 -
 .../gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c  |   2 +-
 .../drm/amd/display/dc/dcn20/dcn20_resource.c |  14 +-
 .../gpu/drm/amd/display/dc/dcn21/dcn21_init.c |   1 -
 .../gpu/drm/amd/display/dc/dcn30/dcn30_init.c |   1 -
 .../gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c  |   2 +-
 .../drm/amd/display/dc/dcn301/dcn301_init.c   |   1 -
 .../amd/display/dc/dml/display_mode_structs.h |   2 +
 .../drm/amd/display/dc/dml/display_mode_vba.c |  13 +
 .../gpu/drm/amd/display/dc/inc/dc_link_dp.h   |  66 +-
 drivers/gpu/drm/amd/display/dc/inc/hw/abm.h   |   3 +-
 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h   |   3 -
 .../gpu/drm/amd/display/dc/inc/hw/transform.h |   4 -
 .../gpu/drm/amd/display/dc/inc/hw_sequencer.h |   4 -
 drivers/gpu/drm/amd/display/dmub/dmub_srv.h   |   1 +
 .../amd/display/include/link_service_types.h  |   1 +
 .../amd/display/modules/freesync/freesync.c   |  29 +-
 .../amd/display/modules/power/power_helpers.c |  15 +-
 .../amd/display/modules/power/power_helpers.h |   3 +-
 39 files changed, 683 insertions(+), 655 deletions(-)

-- 
2.25.1

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Re: [PATCH] drm/amdgpu/display: make backlight setting failure messages debug

[Kazlauskas, Nicholas]

On 2021-05-21 12:08 a.m., Alex Deucher wrote:

Avoid spamming the log.  The backlight controller on DCN chips
gets powered down when the display is off, so if you attempt to
set the backlight level when the display is off, you'll get this
message.  This isn't a problem as we cache the requested backlight
level if it's adjusted when the display is off and set it again
during modeset.

Signed-off-by: Alex Deucher 
Cc: nicholas.c...@amd.com
Cc: harry.wentl...@amd.com


Reviewed-by: Nicholas Kazlauskas 

Regards,
Nicholas Kazlauskas


---
  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index b8026c1baf36..c1f7456aeaa0 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -3506,7 +3506,7 @@ static int amdgpu_dm_backlight_set_level(struct 
amdgpu_display_manager *dm,
rc = dc_link_set_backlight_level_nits(link[i], true, 
brightness[i],
AUX_BL_DEFAULT_TRANSITION_TIME_MS);
if (!rc) {
-   DRM_ERROR("DM: Failed to update backlight via AUX on 
eDP[%d]\n", i);
+   DRM_DEBUG("DM: Failed to update backlight via AUX on 
eDP[%d]\n", i);
break;
}
}
@@ -3514,7 +3514,7 @@ static int amdgpu_dm_backlight_set_level(struct 
amdgpu_display_manager *dm,
for (i = 0; i < dm->num_of_edps; i++) {
rc = dc_link_set_backlight_level(dm->backlight_link[i], 
brightness[i], 0);
if (!rc) {
-   DRM_ERROR("DM: Failed to update backlight on 
eDP[%d]\n", i);
+   DRM_DEBUG("DM: Failed to update backlight on 
eDP[%d]\n", i);
break;
}
}



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Re: [PATCH 1/7] drm/amdgpu: add amdgpu_bo_vm bo type

[Nirmoy]

On 5/21/21 4:54 PM, Alex Deucher wrote:

On Fri, May 21, 2021 at 8:46 AM Nirmoy Das  wrote:

Add new BO subcalss that will be used by amdgpu vm code.

s/subcalss/subclass/



Thanks, Alex!



Alex


Signed-off-by: Nirmoy Das 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 32 ++
  drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 10 +++
  2 files changed, 42 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 745fcf3ea450..61b1edcb490a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -692,6 +692,38 @@ int amdgpu_bo_create_user(struct amdgpu_device *adev,
 *ubo_ptr = to_amdgpu_bo_user(bo_ptr);
 return r;
  }
+
+/**
+ * amdgpu_bo_create_vm - create an &amdgpu_bo_vm buffer object
+ * @adev: amdgpu device object
+ * @bp: parameters to be used for the buffer object
+ * @vmbo_ptr: pointer to the buffer object pointer
+ *
+ * Create a BO to be for GPUVM.
+ *
+ * Returns:
+ * 0 for success or a negative error code on failure.
+ */
+
+int amdgpu_bo_create_vm(struct amdgpu_device *adev,
+   struct amdgpu_bo_param *bp,
+   struct amdgpu_bo_vm **vmbo_ptr)
+{
+   struct amdgpu_bo *bo_ptr;
+   int r;
+
+   /* bo_ptr_size will be determined by the caller and it depends on
+* num of amdgpu_vm_pt entries.
+*/
+   BUG_ON(bp->bo_ptr_size < sizeof(struct amdgpu_bo_vm));
+   r = amdgpu_bo_create(adev, bp, &bo_ptr);
+   if (r)
+   return r;
+
+   *vmbo_ptr = to_amdgpu_bo_vm(bo_ptr);
+   return r;
+}
+
  /**
   * amdgpu_bo_validate - validate an &amdgpu_bo buffer object
   * @bo: pointer to the buffer object
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
index 11480c5a2716..a7fbf5f7051e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
@@ -44,6 +44,7 @@
  #define AMDGPU_AMDKFD_CREATE_SVM_BO(1ULL << 62)

  #define to_amdgpu_bo_user(abo) container_of((abo), struct amdgpu_bo_user, bo)
+#define to_amdgpu_bo_vm(abo) container_of((abo), struct amdgpu_bo_vm, bo)

  struct amdgpu_bo_param {
 unsigned long   size;
@@ -125,6 +126,12 @@ struct amdgpu_bo_user {

  };

+struct amdgpu_bo_vm {
+   struct amdgpu_bobo;
+   struct amdgpu_bo*shadow;
+   struct amdgpu_vm_pt entries[];
+};
+
  static inline struct amdgpu_bo *ttm_to_amdgpu_bo(struct ttm_buffer_object 
*tbo)
  {
 return container_of(tbo, struct amdgpu_bo, tbo);
@@ -272,6 +279,9 @@ int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev,
  int amdgpu_bo_create_user(struct amdgpu_device *adev,
   struct amdgpu_bo_param *bp,
   struct amdgpu_bo_user **ubo_ptr);
+int amdgpu_bo_create_vm(struct amdgpu_device *adev,
+   struct amdgpu_bo_param *bp,
+   struct amdgpu_bo_vm **ubo_ptr);
  void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,
void **cpu_addr);
  int amdgpu_bo_create_shadow(struct amdgpu_device *adev,
--
2.31.1

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[PATCH] drm/amd/amdkfd: Drop unnecessary NULL check after container_of

[Guenter Roeck]

The first parameter passed to container_of() is the pointer to the work
structure passed to the worker and never NULL. The NULL check on the
result of container_of() is therefore unnecessary and misleading.
Remove it.

This change was made automatically with the following Coccinelle script.

@@
type t;
identifier v;
statement s;
@@

<+...
(
  t v = container_of(...);
|
  v = container_of(...);
)
  ...
  when != v
- if (\( !v \| v == NULL \) ) s
...+>

Signed-off-by: Guenter Roeck 
---
 drivers/gpu/drm/amd/amdkfd/kfd_process.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
index 5b6c5669c03d..2f8d352e0069 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
@@ -110,8 +110,6 @@ static void kfd_sdma_activity_worker(struct work_struct 
*work)
 
workarea = container_of(work, struct kfd_sdma_activity_handler_workarea,
sdma_activity_work);
-   if (!workarea)
-   return;
 
pdd = workarea->pdd;
if (!pdd)
-- 
2.25.1

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Re: [PATCH 1/7] drm/amdgpu: add amdgpu_bo_vm bo type

[Alex Deucher]

On Fri, May 21, 2021 at 8:46 AM Nirmoy Das  wrote:
>
> Add new BO subcalss that will be used by amdgpu vm code.

s/subcalss/subclass/

Alex

>
> Signed-off-by: Nirmoy Das 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 32 ++
>  drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 10 +++
>  2 files changed, 42 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> index 745fcf3ea450..61b1edcb490a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> @@ -692,6 +692,38 @@ int amdgpu_bo_create_user(struct amdgpu_device *adev,
> *ubo_ptr = to_amdgpu_bo_user(bo_ptr);
> return r;
>  }
> +
> +/**
> + * amdgpu_bo_create_vm - create an &amdgpu_bo_vm buffer object
> + * @adev: amdgpu device object
> + * @bp: parameters to be used for the buffer object
> + * @vmbo_ptr: pointer to the buffer object pointer
> + *
> + * Create a BO to be for GPUVM.
> + *
> + * Returns:
> + * 0 for success or a negative error code on failure.
> + */
> +
> +int amdgpu_bo_create_vm(struct amdgpu_device *adev,
> +   struct amdgpu_bo_param *bp,
> +   struct amdgpu_bo_vm **vmbo_ptr)
> +{
> +   struct amdgpu_bo *bo_ptr;
> +   int r;
> +
> +   /* bo_ptr_size will be determined by the caller and it depends on
> +* num of amdgpu_vm_pt entries.
> +*/
> +   BUG_ON(bp->bo_ptr_size < sizeof(struct amdgpu_bo_vm));
> +   r = amdgpu_bo_create(adev, bp, &bo_ptr);
> +   if (r)
> +   return r;
> +
> +   *vmbo_ptr = to_amdgpu_bo_vm(bo_ptr);
> +   return r;
> +}
> +
>  /**
>   * amdgpu_bo_validate - validate an &amdgpu_bo buffer object
>   * @bo: pointer to the buffer object
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
> index 11480c5a2716..a7fbf5f7051e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
> @@ -44,6 +44,7 @@
>  #define AMDGPU_AMDKFD_CREATE_SVM_BO(1ULL << 62)
>
>  #define to_amdgpu_bo_user(abo) container_of((abo), struct amdgpu_bo_user, bo)
> +#define to_amdgpu_bo_vm(abo) container_of((abo), struct amdgpu_bo_vm, bo)
>
>  struct amdgpu_bo_param {
> unsigned long   size;
> @@ -125,6 +126,12 @@ struct amdgpu_bo_user {
>
>  };
>
> +struct amdgpu_bo_vm {
> +   struct amdgpu_bobo;
> +   struct amdgpu_bo*shadow;
> +   struct amdgpu_vm_pt entries[];
> +};
> +
>  static inline struct amdgpu_bo *ttm_to_amdgpu_bo(struct ttm_buffer_object 
> *tbo)
>  {
> return container_of(tbo, struct amdgpu_bo, tbo);
> @@ -272,6 +279,9 @@ int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev,
>  int amdgpu_bo_create_user(struct amdgpu_device *adev,
>   struct amdgpu_bo_param *bp,
>   struct amdgpu_bo_user **ubo_ptr);
> +int amdgpu_bo_create_vm(struct amdgpu_device *adev,
> +   struct amdgpu_bo_param *bp,
> +   struct amdgpu_bo_vm **ubo_ptr);
>  void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,
>void **cpu_addr);
>  int amdgpu_bo_create_shadow(struct amdgpu_device *adev,
> --
> 2.31.1
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 2/6] drm/amd/pm: Add arcturus throttler translation

[Alex Deucher]

General comment on the patch series, do you want to bump the metrics
table version since the meaning of the throttler status has changed?

Alex

On Thu, May 20, 2021 at 10:30 AM Graham Sider  wrote:
>
> Perform dependent to independent throttle status translation for
> arcturus.
> ---
>  .../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 62 ---
>  1 file changed, 53 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c 
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> index 1735a96dd307..7c01c0bf2073 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> @@ -540,6 +540,49 @@ static int arcturus_freqs_in_same_level(int32_t 
> frequency1,
> return (abs(frequency1 - frequency2) <= EPSILON);
>  }
>
> +static uint32_t arcturus_get_indep_throttler_status(
> +   unsigned long dep_throttler_status)
> +{
> +   unsigned long indep_throttler_status = 0;
> +
> +   __assign_bit(INDEP_THROTTLER_TEMP_EDGE_BIT, &indep_throttler_status,
> + test_bit(THROTTLER_TEMP_EDGE_BIT, &dep_throttler_status));
> +   __assign_bit(INDEP_THROTTLER_TEMP_HOTSPOT_BIT, 
> &indep_throttler_status,
> + test_bit(THROTTLER_TEMP_HOTSPOT_BIT, 
> &dep_throttler_status));
> +   __assign_bit(INDEP_THROTTLER_TEMP_MEM_BIT, &indep_throttler_status,
> + test_bit(THROTTLER_TEMP_MEM_BIT, &dep_throttler_status));
> +   __assign_bit(INDEP_THROTTLER_TEMP_VR_GFX_BIT, &indep_throttler_status,
> + test_bit(THROTTLER_TEMP_VR_GFX_BIT, &dep_throttler_status));
> +   __assign_bit(INDEP_THROTTLER_TEMP_VR_MEM_BIT, &indep_throttler_status,
> + test_bit(THROTTLER_TEMP_VR_MEM_BIT, &dep_throttler_status));
> +   __assign_bit(INDEP_THROTTLER_TEMP_VR_SOC_BIT, &indep_throttler_status,
> + test_bit(THROTTLER_TEMP_VR_SOC_BIT, &dep_throttler_status));
> +   __assign_bit(INDEP_THROTTLER_TDC_GFX_BIT, &indep_throttler_status,
> + test_bit(THROTTLER_TDC_GFX_BIT, &dep_throttler_status));
> +   __assign_bit(INDEP_THROTTLER_TDC_SOC_BIT, &indep_throttler_status,
> + test_bit(THROTTLER_TDC_SOC_BIT, &dep_throttler_status));
> +   __assign_bit(INDEP_THROTTLER_PPT0_BIT, &indep_throttler_status,
> + test_bit(THROTTLER_PPT0_BIT, &dep_throttler_status));
> +   __assign_bit(INDEP_THROTTLER_PPT1_BIT, &indep_throttler_status,
> + test_bit(THROTTLER_PPT1_BIT, &dep_throttler_status));
> +   __assign_bit(INDEP_THROTTLER_PPT2_BIT, &indep_throttler_status,
> + test_bit(THROTTLER_PPT2_BIT, &dep_throttler_status));
> +   __assign_bit(INDEP_THROTTLER_PPT3_BIT, &indep_throttler_status,
> + test_bit(THROTTLER_PPT3_BIT, &dep_throttler_status));
> +   __assign_bit(INDEP_THROTTLER_PPM_BIT, &indep_throttler_status,
> + test_bit(THROTTLER_PPM_BIT, &dep_throttler_status));
> +   __assign_bit(INDEP_THROTTLER_FIT_BIT, &indep_throttler_status,
> + test_bit(THROTTLER_FIT_BIT, &dep_throttler_status));
> +   __assign_bit(INDEP_THROTTLER_APCC_BIT, &indep_throttler_status,
> + test_bit(THROTTLER_APCC_BIT, &dep_throttler_status));
> +   __assign_bit(INDEP_THROTTLER_VRHOT0_BIT, &indep_throttler_status,
> + test_bit(THROTTLER_VRHOT0_BIT, &dep_throttler_status));
> +   __assign_bit(INDEP_THROTTLER_VRHOT1_BIT, &indep_throttler_status,
> + test_bit(THROTTLER_VRHOT1_BIT, &dep_throttler_status));
> +
> +   return (uint32_t)indep_throttler_status;
> +}
> +
>  static int arcturus_get_smu_metrics_data(struct smu_context *smu,
>  MetricsMember_t member,
>  uint32_t *value)
> @@ -629,7 +672,7 @@ static int arcturus_get_smu_metrics_data(struct 
> smu_context *smu,
> SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
> break;
> case METRICS_THROTTLER_STATUS:
> -   *value = metrics->ThrottlerStatus;
> +   *value = 
> arcturus_get_indep_throttler_status(metrics->ThrottlerStatus);
> break;
> case METRICS_CURR_FANSPEED:
> *value = metrics->CurrFanSpeed;
> @@ -2213,13 +2256,13 @@ static const struct throttling_logging_label {
> uint32_t feature_mask;
> const char *label;
>  } logging_label[] = {
> -   {(1U << THROTTLER_TEMP_HOTSPOT_BIT), "GPU"},
> -   {(1U << THROTTLER_TEMP_MEM_BIT), "HBM"},
> -   {(1U << THROTTLER_TEMP_VR_GFX_BIT), "VR of GFX rail"},
> -   {(1U << THROTTLER_TEMP_VR_MEM_BIT), "VR of HBM rail"},
> -   {(1U << THROTTLER_TEMP_VR_SOC_BIT), "VR of SOC rail"},
> -   {(1U << THROTTLER_VRHOT0_BIT), "VR0 HOT"},
> -   {(1U << THROTTLER_VRHOT1_BIT), "VR1 HOT"},
> +   {(1U << INDEP_THROTTLER_TEM

RE: [PATCH 2/6] drm/amd/pm: Add arcturus throttler translation

[Kasiviswanathan, Harish]

[AMD Official Use Only]

Hi Graham,

This patch series looks good. Please add "Signed-off-by" to all the commit 
messages. 
One additional comment inline below.

-Original Message-
From: Sider, Graham  
Sent: Thursday, May 20, 2021 10:29 AM
To: amd-gfx@lists.freedesktop.org
Cc: Kasiviswanathan, Harish ; Sakhnovitch, 
Elena (Elen) ; Sider, Graham 
Subject: [PATCH 2/6] drm/amd/pm: Add arcturus throttler translation

Perform dependent to independent throttle status translation for
arcturus.
---
 .../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 62 ---
 1 file changed, 53 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
index 1735a96dd307..7c01c0bf2073 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
@@ -540,6 +540,49 @@ static int arcturus_freqs_in_same_level(int32_t frequency1,
return (abs(frequency1 - frequency2) <= EPSILON);
 }
 
+static uint32_t arcturus_get_indep_throttler_status(
+   unsigned long dep_throttler_status)
+{
+   unsigned long indep_throttler_status = 0;
+

[HK] You can a simple optimization here. During most of the time 
throttler_status would be 0.  So if (dep_throttler_status == 0) you could just 
return here. You can add this to other commits too.

+   __assign_bit(INDEP_THROTTLER_TEMP_EDGE_BIT, &indep_throttler_status,
+ test_bit(THROTTLER_TEMP_EDGE_BIT, &dep_throttler_status));
+   __assign_bit(INDEP_THROTTLER_TEMP_HOTSPOT_BIT, &indep_throttler_status,
+ test_bit(THROTTLER_TEMP_HOTSPOT_BIT, &dep_throttler_status));
+   __assign_bit(INDEP_THROTTLER_TEMP_MEM_BIT, &indep_throttler_status,
+ test_bit(THROTTLER_TEMP_MEM_BIT, &dep_throttler_status));
+   __assign_bit(INDEP_THROTTLER_TEMP_VR_GFX_BIT, &indep_throttler_status,
+ test_bit(THROTTLER_TEMP_VR_GFX_BIT, &dep_throttler_status));
+   __assign_bit(INDEP_THROTTLER_TEMP_VR_MEM_BIT, &indep_throttler_status,
+ test_bit(THROTTLER_TEMP_VR_MEM_BIT, &dep_throttler_status));
+   __assign_bit(INDEP_THROTTLER_TEMP_VR_SOC_BIT, &indep_throttler_status,
+ test_bit(THROTTLER_TEMP_VR_SOC_BIT, &dep_throttler_status));
+   __assign_bit(INDEP_THROTTLER_TDC_GFX_BIT, &indep_throttler_status,
+ test_bit(THROTTLER_TDC_GFX_BIT, &dep_throttler_status));
+   __assign_bit(INDEP_THROTTLER_TDC_SOC_BIT, &indep_throttler_status,
+ test_bit(THROTTLER_TDC_SOC_BIT, &dep_throttler_status));
+   __assign_bit(INDEP_THROTTLER_PPT0_BIT, &indep_throttler_status,
+ test_bit(THROTTLER_PPT0_BIT, &dep_throttler_status));
+   __assign_bit(INDEP_THROTTLER_PPT1_BIT, &indep_throttler_status,
+ test_bit(THROTTLER_PPT1_BIT, &dep_throttler_status));
+   __assign_bit(INDEP_THROTTLER_PPT2_BIT, &indep_throttler_status,
+ test_bit(THROTTLER_PPT2_BIT, &dep_throttler_status));
+   __assign_bit(INDEP_THROTTLER_PPT3_BIT, &indep_throttler_status,
+ test_bit(THROTTLER_PPT3_BIT, &dep_throttler_status));
+   __assign_bit(INDEP_THROTTLER_PPM_BIT, &indep_throttler_status,
+ test_bit(THROTTLER_PPM_BIT, &dep_throttler_status));
+   __assign_bit(INDEP_THROTTLER_FIT_BIT, &indep_throttler_status,
+ test_bit(THROTTLER_FIT_BIT, &dep_throttler_status));
+   __assign_bit(INDEP_THROTTLER_APCC_BIT, &indep_throttler_status,
+ test_bit(THROTTLER_APCC_BIT, &dep_throttler_status));
+   __assign_bit(INDEP_THROTTLER_VRHOT0_BIT, &indep_throttler_status,
+ test_bit(THROTTLER_VRHOT0_BIT, &dep_throttler_status));
+   __assign_bit(INDEP_THROTTLER_VRHOT1_BIT, &indep_throttler_status,
+ test_bit(THROTTLER_VRHOT1_BIT, &dep_throttler_status));
+
+   return (uint32_t)indep_throttler_status;
+}
+
 static int arcturus_get_smu_metrics_data(struct smu_context *smu,
 MetricsMember_t member,
 uint32_t *value)
@@ -629,7 +672,7 @@ static int arcturus_get_smu_metrics_data(struct smu_context 
*smu,
SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
break;
case METRICS_THROTTLER_STATUS:
-   *value = metrics->ThrottlerStatus;
+   *value = 
arcturus_get_indep_throttler_status(metrics->ThrottlerStatus);
break;
case METRICS_CURR_FANSPEED:
*value = metrics->CurrFanSpeed;
@@ -2213,13 +2256,13 @@ static const struct throttling_logging_label {
uint32_t feature_mask;
const char *label;
 } logging_label[] = {
-   {(1U << THROTTLER_TEMP_HOTSPOT_BIT), "GPU"},
-   {(1U << THROTTLER_TEMP_MEM_BIT), "HBM"},
-   {(1U << THROTTLER_TEMP_VR_GFX_BIT), "VR of GFX rail"},
-   {(1U

Re: [PATCH v5 09/10] drm/amdgpu: Use PSP to program IH_RB_CNTL* registers

[Alex Deucher]

On Fri, May 21, 2021 at 6:07 AM Deng, Emily  wrote:
>
> Hi Pengju,
>  You'd better only switch for sriov.

Either verify that this doesn't break bare metal, or do something like
we do on sienna cichlid.  E.g.,
if (!amdgpu_sriov_vf(adev)) {
amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
if (likely(adev->firmware.load_type ==
AMDGPU_FW_LOAD_PSP))
amdgpu_device_ip_block_add(adev,
&psp_v11_0_ip_block);
} else {
if (likely(adev->firmware.load_type ==
AMDGPU_FW_LOAD_PSP))
amdgpu_device_ip_block_add(adev,
&psp_v11_0_ip_block);
amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
}

Alex

>
> Best wishes
> Emily Deng
>
> >-Original Message-
> >From: Zhou, Peng Ju 
> >Sent: Friday, May 21, 2021 5:58 PM
> >To: Alex Deucher ; Zhao, Victor
> >; Deng, Emily 
> >Cc: amd-gfx list 
> >Subject: RE: [PATCH v5 09/10] drm/amdgpu: Use PSP to program IH_RB_CNTL*
> >registers
> >
> >[AMD Official Use Only - Internal Distribution Only]
> >
> >Hi @Zhao, Victor/@Deng, Emily
> >
> >Can you help to answer Alex's question,?
> >Because this patch originally from @Zhao, Victor, it's hard for me to 
> >explain the
> >question.
> >
> >Alex's question:
> >> > --- a/drivers/gpu/drm/amd/amdgpu/nv.c
> >> > +++ b/drivers/gpu/drm/amd/amdgpu/nv.c
> >> > @@ -845,8 +845,8 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
> >> > case CHIP_NAVI12:
> >> > amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
> >> > amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
> >> > -   amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
> >> > amdgpu_device_ip_block_add(adev,
> >> > &psp_v11_0_ip_block);
> >> > +   amdgpu_device_ip_block_add(adev,
> >> > + &navi10_ih_ip_block);
> >>
> >> Is it safe to change the order like this on bare metal?  Please look
> >> at what was done for vega and sienna cichlid.  Something like that is 
> >> probably
> >a better bet.
> >
> >
> >--
> >BW
> >Pengju Zhou
> >
> >
> >
> >
> >> -Original Message-
> >> From: Alex Deucher 
> >> Sent: Thursday, May 20, 2021 11:47 AM
> >> To: Zhou, Peng Ju 
> >> Cc: amd-gfx list ; Zhao, Victor
> >> 
> >> Subject: Re: [PATCH v5 09/10] drm/amdgpu: Use PSP to program
> >> IH_RB_CNTL* registers
> >>
> >> On Mon, May 17, 2021 at 10:39 AM Peng Ju Zhou 
> >> wrote:
> >> >
> >> > use psp to program IH_RB_CNTL* if indirect access for ih enabled in
> >> > SRIOV environment.
> >> >
> >> > Signed-off-by: Victor 
> >> > Signed-off-by: Peng Ju Zhou 
> >> > ---
> >> >  drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 19 +--
> >> >  drivers/gpu/drm/amd/amdgpu/nv.c|  2 +-
> >> >  2 files changed, 18 insertions(+), 3 deletions(-)
> >> >
> >> > diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> >> > b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> >> > index f4e4040bbd25..2e69cf8db072 100644
> >> > --- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> >> > +++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> >> > @@ -151,7 +151,14 @@ static int navi10_ih_toggle_ring_interrupts(struct
> >> amdgpu_device *adev,
> >> > /* enable_intr field is only valid in ring0 */
> >> > if (ih == &adev->irq.ih)
> >> > tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, 
> >> > (enable ?
> >> 1 : 0));
> >> > -   WREG32(ih_regs->ih_rb_cntl, tmp);
> >> > +   if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) 
> >> > {
> >> > +   if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, 
> >> > tmp)) {
> >> > +   DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
> >> > +   return -ETIMEDOUT;
> >> > +   }
> >> > +   } else {
> >> > +   WREG32(ih_regs->ih_rb_cntl, tmp);
> >> > +   }
> >> >
> >> > if (enable) {
> >> > ih->enabled = true;
> >> > @@ -261,7 +268,15 @@ static int navi10_ih_enable_ring(struct
> >> amdgpu_device *adev,
> >> > tmp = REG_SET_FIELD(tmp, IH_RB_CNTL,
> >> WPTR_OVERFLOW_ENABLE, 0);
> >> > tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, 
> >> > RB_FULL_DRAIN_ENABLE,
> >> 1);
> >> > }
> >> > -   WREG32(ih_regs->ih_rb_cntl, tmp);
> >> > +
> >> > +   if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) 
> >> > {
> >> > +   if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, 
> >> > tmp)) {
> >> > +   DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
> >> > +   return -ETIMEDOUT;
> >> > +   }
> >> > +   } else {
> >> > +   WREG32(ih_regs->ih_rb_cntl, tmp);
> >> > +   }
> >> >
> >> > if (ih == &adev->irq.ih) {
> >> > /* set the ih 

Re: [PATCH 1/2] drm/amdgpu/acpi: unify ATCS handling (v3)

[Lijo Lazar]

Thanks for clarifying!

Reviewed-by: Lijo Lazar 

On 5/21/2021 7:17 PM, Alex Deucher wrote:

On Fri, May 21, 2021 at 3:12 AM Lijo Lazar  wrote:




On 5/20/2021 9:26 PM, Alex Deucher wrote:

Treat it like ATIF and check both the dGPU and APU for
the method.  This is required because ATCS may be hung
off of the APU in ACPI on A+A systems.

v2: add back accidently removed ACPI handle check.
v3: Fix incorrect atif check (Colin)
  Fix uninitialized variable (Colin)

Signed-off-by: Alex Deucher 
---
   drivers/gpu/drm/amd/amdgpu/amdgpu.h  |  17 +--
   drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 128 ---
   2 files changed, 93 insertions(+), 52 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index b6435479cac8..ece1aee5a667 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -268,6 +268,7 @@ struct amdgpu_irq_src;
   struct amdgpu_fpriv;
   struct amdgpu_bo_va_mapping;
   struct amdgpu_atif;
+struct amdgpu_atcs;
   struct kfd_vm_fault_info;
   struct amdgpu_hive_info;
   struct amdgpu_reset_context;
@@ -681,20 +682,6 @@ struct amdgpu_vram_scratch {
   u64 gpu_addr;
   };

-/*
- * ACPI
- */
-struct amdgpu_atcs_functions {
- bool get_ext_state;
- bool pcie_perf_req;
- bool pcie_dev_rdy;
- bool pcie_bus_width;
-};
-
-struct amdgpu_atcs {
- struct amdgpu_atcs_functions functions;
-};
-
   /*
* CGS
*/
@@ -825,7 +812,7 @@ struct amdgpu_device {
   struct amdgpu_i2c_chan  *i2c_bus[AMDGPU_MAX_I2C_BUS];
   struct debugfs_blob_wrapper debugfs_vbios_blob;
   struct amdgpu_atif  *atif;
- struct amdgpu_atcs  atcs;
+ struct amdgpu_atcs  *atcs;
   struct mutexsrbm_mutex;
   /* GRBM index mutex. Protects concurrent access to GRBM index */
   struct mutexgrbm_idx_mutex;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
index 6cf6231057fc..29708b5685ad 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
@@ -72,12 +72,25 @@ struct amdgpu_atif {
   struct amdgpu_dm_backlight_caps backlight_caps;
   };

+struct amdgpu_atcs_functions {
+ bool get_ext_state;
+ bool pcie_perf_req;
+ bool pcie_dev_rdy;
+ bool pcie_bus_width;
+};
+
+struct amdgpu_atcs {
+ acpi_handle handle;
+
+ struct amdgpu_atcs_functions functions;
+};
+
   /* Call the ATIF method
*/
   /**
* amdgpu_atif_call - call an ATIF method
*
- * @atif: acpi handle
+ * @atif: atif structure
* @function: the ATIF function to execute
* @params: ATIF function params
*
@@ -237,6 +250,35 @@ static acpi_handle amdgpu_atif_probe_handle(acpi_handle 
dhandle)
   return handle;
   }

+static acpi_handle amdgpu_atcs_probe_handle(acpi_handle dhandle)
+{
+ acpi_handle handle = NULL;
+ char acpi_method_name[255] = { 0 };
+ struct acpi_buffer buffer = { sizeof(acpi_method_name), acpi_method_name 
};
+ acpi_status status;
+
+ /* For PX/HG systems, ATCS and ATPX are in the iGPU's namespace, on dGPU 
only
+  * systems, ATIF is in the dGPU's namespace.
+  */
+ status = acpi_get_handle(dhandle, "ATCS", &handle);
+ if (ACPI_SUCCESS(status))
+ goto out;
+
+ if (amdgpu_has_atpx()) {
+ status = acpi_get_handle(amdgpu_atpx_get_dhandle(), "ATCS",
+  &handle);
+ if (ACPI_SUCCESS(status))
+ goto out;
+ }
+
+ DRM_DEBUG_DRIVER("No ATCS handle found\n");
+ return NULL;
+out:
+ acpi_get_name(handle, ACPI_FULL_PATHNAME, &buffer);
+ DRM_DEBUG_DRIVER("Found ATCS handle %s\n", acpi_method_name);
+ return handle;
+}
+
   /**
* amdgpu_atif_get_notification_params - determine notify configuration
*
@@ -486,14 +528,15 @@ static int amdgpu_atif_handler(struct amdgpu_device *adev,
   /**
* amdgpu_atcs_call - call an ATCS method
*
- * @handle: acpi handle
+ * @atcs: atcs structure
* @function: the ATCS function to execute
* @params: ATCS function params
*
* Executes the requested ATCS function (all asics).
* Returns a pointer to the acpi output buffer.
*/
-static union acpi_object *amdgpu_atcs_call(acpi_handle handle, int function,
+static union acpi_object *amdgpu_atcs_call(struct amdgpu_atcs *atcs,
+int function,
  struct acpi_buffer *params)
   {
   acpi_status status;
@@ -517,7 +560,7 @@ static union acpi_object *amdgpu_atcs_call(acpi_handle 
handle, int function,
   atcs_arg_elements[1].integer.value = 0;
   }

- status = acpi_evaluate_object(handle, "ATCS", &atcs_arg, &buffer);
+ status = acpi_evaluate_object(atcs->handle, "ATCS", &atcs_arg, &buffer);

   /* Fail o

Re: [PATCH v2 3/3] drm/amdgpu: Workaround IOMMU driver bug

[Zeng, Oak]

[Public]

Reviewed-by: oak zeng 


Get Outlook for Android


From: amd-gfx  on behalf of Felix 
Kuehling 
Sent: Friday, May 21, 2021 9:47:17 AM
To: Christian König ; 
amd-gfx@lists.freedesktop.org 
Subject: Re: [PATCH v2 3/3] drm/amdgpu: Workaround IOMMU driver bug

Am 2021-05-21 um 4:41 a.m. schrieb Christian König:
> Am 21.05.21 um 04:22 schrieb Felix Kuehling:
>> The intel IOMMU driver causes kernel oopses or internal errors flooding
>> kernel log when mapping larger SG tables. Limiting the size of
>> userptr BOs
>> to 6GB seems to avoid this.
>>
>> Signed-off-by: Felix Kuehling 
>
> CC whoever is the maintainer of the Intel IOMMU driver?
>
> Would be nice to have that bug fixed instead.

Yeah, I'm not ready to submit this hack. I want to run some more
experiments to see what's going on.

Regards,
  Felix


>
> Christian.
>
>> ---
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 3 +++
>>   1 file changed, 3 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
>> index 2b8b89535198..3becf9d9f8fd 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
>> @@ -1409,6 +1409,9 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
>>   domain = alloc_domain = AMDGPU_GEM_DOMAIN_GTT;
>>   alloc_flags = 0;
>>   } else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
>> +/* workaround IOMMU driver bug */
>> +if (size >= (6ULL << 30))
>> +return -ENOMEM;
>>   domain = AMDGPU_GEM_DOMAIN_GTT;
>>   alloc_domain = AMDGPU_GEM_DOMAIN_CPU;
>>   alloc_flags = AMDGPU_GEM_CREATE_PREEMPTIBLE;
>
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Re: [PATCH 7/7] drm/amdgpu: do not allocate entries separately

[Nirmoy]

On 5/21/21 3:01 PM, Christian König wrote:

Am 21.05.21 um 14:45 schrieb Nirmoy Das:

Allocate PD/PT entries while allocating VM BOs and use that
instead of allocating those entries separately.

Signed-off-by: Nirmoy Das 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 31 ++
  1 file changed, 17 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c

index 120e6b7a0286..4717f075a391 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -880,7 +880,12 @@ static int amdgpu_vm_pt_create(struct 
amdgpu_device *adev,

  bp.domain = amdgpu_bo_get_preferred_pin_domain(adev, bp.domain);
  bp.flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
  AMDGPU_GEM_CREATE_CPU_GTT_USWC;
-    bp.bo_ptr_size = sizeof(struct amdgpu_bo_vm);
+    if (level < AMDGPU_VM_PTB)
+    bp.bo_ptr_size = struct_size((*vmbo), entries,
+ amdgpu_vm_num_entries(adev, level));
+    else
+    bp.bo_ptr_size = sizeof(struct amdgpu_bo_vm);
+


Rather do it like this here:

if (level < AMDGPU_VM_PTB)
    num_entries = amdgpu_vm_num_entries(...)
else
    num_entries = 0;

bp.bo_ptr_size = struct_size()



Sure.




If we have that calculation more than once then it might make sense to 
unify it in a function, but I don't think so of hand.



Currently, we only need this calculation in amdgpu_vm_pt_create().


Nirmoy





Regards,
Christian.


  if (vm->use_cpu_for_update)
  bp.flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
  @@ -954,19 +959,14 @@ static int amdgpu_vm_alloc_pts(struct 
amdgpu_device *adev,

  struct amdgpu_bo_vm *pt;
  int r;
  -    if (cursor->level < AMDGPU_VM_PTB && !entry->entries) {
-    unsigned num_entries;
-
-    num_entries = amdgpu_vm_num_entries(adev, cursor->level);
-    entry->entries = kvmalloc_array(num_entries,
-    sizeof(*entry->entries),
-    GFP_KERNEL | __GFP_ZERO);
-    if (!entry->entries)
-    return -ENOMEM;
-    }
-
-    if (entry->base.bo)
+    if (entry->base.bo) {
+    if (cursor->level < AMDGPU_VM_PTB)
+    entry->entries =
+    to_amdgpu_bo_vm(entry->base.bo)->entries;
+    else
+    entry->entries = NULL;
  return 0;
+    }
    r = amdgpu_vm_pt_create(adev, vm, cursor->level, immediate, 
&pt);

  if (r)
@@ -978,6 +978,10 @@ static int amdgpu_vm_alloc_pts(struct 
amdgpu_device *adev,

  pt_bo = &pt->bo;
  pt_bo->parent = amdgpu_bo_ref(cursor->parent->base.bo);
  amdgpu_vm_bo_base_init(&entry->base, vm, pt_bo);
+    if (cursor->level < AMDGPU_VM_PTB)
+    entry->entries = pt->entries;
+    else
+    entry->entries = NULL;
    r = amdgpu_vm_clear_bo(adev, vm, pt_bo, immediate);
  if (r)
@@ -1005,7 +1009,6 @@ static void amdgpu_vm_free_table(struct 
amdgpu_vm_pt *entry)

amdgpu_bo_unref(&to_amdgpu_bo_vm(entry->base.bo)->shadow);
  amdgpu_bo_unref(&entry->base.bo);
  }
-    kvfree(entry->entries);
  entry->entries = NULL;
  }



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Re: [PATCH 2/7] drm/amdgpu: add a new identifier for amdgpu_bo

[Nirmoy]

On 5/21/21 2:58 PM, Christian König wrote:

Am 21.05.21 um 14:45 schrieb Nirmoy Das:

Add has_shadow to identify if a BO is shadowed.


Ok that is not going into the right direction.



I was expecting this :) but wasn't sure how to handle it.




Instead of identifying which BOs have a shadow we need to identify if 
this is a VM BO or not.


I think the first think you need to do is to move the shadow handling 
from amdgpu_cs_validate() into amdgpu_vm_validate_pt_bos().


And then do it only for ttm_bo_type_kernel BOs, cause those are the 
PD/PT BOs.



Thanks, this sounds good.


Nirmoy



Regards,
Christian.



Signed-off-by: Nirmoy Das 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 2 ++
  drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 5 ++---
  2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c

index 61b1edcb490a..eb3ce33cbfff 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -619,6 +619,7 @@ int amdgpu_bo_create(struct amdgpu_device *adev,
  }
  if (!bp->resv)
  amdgpu_bo_unreserve(bo);
+    bo->has_shadow = false;
  *bo_ptr = bo;
    trace_amdgpu_bo_create(bo);
@@ -657,6 +658,7 @@ int amdgpu_bo_create_shadow(struct amdgpu_device 
*adev,

  r = amdgpu_bo_create(adev, &bp, &bo->shadow);
  if (!r) {
  bo->shadow->parent = amdgpu_bo_ref(bo);
+    bo->has_shadow = true;
  mutex_lock(&adev->shadow_list_lock);
  list_add_tail(&bo->shadow->shadow_list, &adev->shadow_list);
  mutex_unlock(&adev->shadow_list_lock);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h

index a7fbf5f7051e..3a0e6ca88563 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
@@ -104,9 +104,8 @@ struct amdgpu_bo {
  struct amdgpu_vm_bo_base    *vm_bo;
  /* Constant after initialization */
  struct amdgpu_bo    *parent;
-    struct amdgpu_bo    *shadow;
-
-
+    struct amdgpu_bo    *shadow;
+    bool    has_shadow;
    #ifdef CONFIG_MMU_NOTIFIER
  struct mmu_interval_notifier    notifier;



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[PATCH] drm/amdkfd: use resource cursor in svm_migrate_copy_to_vram

[Christian König]

Access to the mm_node is now forbidden. So instead of hand wiring that
use the cursor functionality.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 76 +++-
 1 file changed, 9 insertions(+), 67 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
index fd8f544f0de2..cb28d1e660af 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
@@ -29,6 +29,7 @@
 #include "amdgpu_object.h"
 #include "amdgpu_vm.h"
 #include "amdgpu_mn.h"
+#include "amdgpu_res_cursor.h"
 #include "kfd_priv.h"
 #include "kfd_svm.h"
 #include "kfd_migrate.h"
@@ -205,34 +206,6 @@ svm_migrate_copy_done(struct amdgpu_device *adev, struct 
dma_fence *mfence)
return r;
 }
 
-static uint64_t
-svm_migrate_node_physical_addr(struct amdgpu_device *adev,
-  struct drm_mm_node **mm_node, uint64_t *offset)
-{
-   struct drm_mm_node *node = *mm_node;
-   uint64_t pos = *offset;
-
-   if (node->start == AMDGPU_BO_INVALID_OFFSET) {
-   pr_debug("drm node is not validated\n");
-   return 0;
-   }
-
-   pr_debug("vram node start 0x%llx npages 0x%llx\n", node->start,
-node->size);
-
-   if (pos >= node->size) {
-   do  {
-   pos -= node->size;
-   node++;
-   } while (pos >= node->size);
-
-   *mm_node = node;
-   *offset = pos;
-   }
-
-   return (node->start + pos) << PAGE_SHIFT;
-}
-
 unsigned long
 svm_migrate_addr_to_pfn(struct amdgpu_device *adev, unsigned long addr)
 {
@@ -297,11 +270,9 @@ svm_migrate_copy_to_vram(struct amdgpu_device *adev, 
struct svm_range *prange,
 {
uint64_t npages = migrate->cpages;
struct device *dev = adev->dev;
-   struct drm_mm_node *node;
+   struct amdgpu_res_cursor cursor;
dma_addr_t *src;
uint64_t *dst;
-   uint64_t vram_addr;
-   uint64_t offset;
uint64_t i, j;
int r;
 
@@ -317,19 +288,12 @@ svm_migrate_copy_to_vram(struct amdgpu_device *adev, 
struct svm_range *prange,
goto out;
}
 
-   node = prange->ttm_res->mm_node;
-   offset = prange->offset;
-   vram_addr = svm_migrate_node_physical_addr(adev, &node, &offset);
-   if (!vram_addr) {
-   WARN_ONCE(1, "vram node address is 0\n");
-   r = -ENOMEM;
-   goto out;
-   }
-
+   amdgpu_res_first(prange->ttm_res, prange->offset, npages << PAGE_SHIFT,
+&cursor);
for (i = j = 0; i < npages; i++) {
struct page *spage;
 
-   dst[i] = vram_addr + (j << PAGE_SHIFT);
+   dst[i] = cursor.start + (j << PAGE_SHIFT);
migrate->dst[i] = svm_migrate_addr_to_pfn(adev, dst[i]);
svm_migrate_get_vram_page(prange, migrate->dst[i]);
 
@@ -354,18 +318,10 @@ svm_migrate_copy_to_vram(struct amdgpu_device *adev, 
struct svm_range *prange,
mfence);
if (r)
goto out_free_vram_pages;
-   offset += j;
-   vram_addr = (node->start + offset) << 
PAGE_SHIFT;
+   amdgpu_res_next(&cursor, j << PAGE_SHIFT);
j = 0;
} else {
-   offset++;
-   vram_addr += PAGE_SIZE;
-   }
-   if (offset >= node->size) {
-   node++;
-   pr_debug("next node size 0x%llx\n", node->size);
-   vram_addr = node->start << PAGE_SHIFT;
-   offset = 0;
+   amdgpu_res_next(&cursor, PAGE_SIZE);
}
continue;
}
@@ -373,22 +329,8 @@ svm_migrate_copy_to_vram(struct amdgpu_device *adev, 
struct svm_range *prange,
pr_debug("dma mapping src to 0x%llx, page_to_pfn 0x%lx\n",
 src[i] >> PAGE_SHIFT, page_to_pfn(spage));
 
-   if (j + offset >= node->size - 1 && i < npages - 1) {
-   r = svm_migrate_copy_memory_gart(adev, src + i - j,
-dst + i - j, j + 1,
-FROM_RAM_TO_VRAM,
-mfence);
-   if (r)
-   goto out_free_vram_pages;
-
-   node++;
-   pr_debug("next node size 0x%llx\n", node->size);
-   vram_addr = node->start << PAGE_SHIFT;
-   offset = 0

Re: [PATCH 1/2] drm/amdgpu/acpi: unify ATCS handling (v3)

[Alex Deucher]

On Fri, May 21, 2021 at 3:12 AM Lijo Lazar  wrote:
>
>
>
> On 5/20/2021 9:26 PM, Alex Deucher wrote:
> > Treat it like ATIF and check both the dGPU and APU for
> > the method.  This is required because ATCS may be hung
> > off of the APU in ACPI on A+A systems.
> >
> > v2: add back accidently removed ACPI handle check.
> > v3: Fix incorrect atif check (Colin)
> >  Fix uninitialized variable (Colin)
> >
> > Signed-off-by: Alex Deucher 
> > ---
> >   drivers/gpu/drm/amd/amdgpu/amdgpu.h  |  17 +--
> >   drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 128 ---
> >   2 files changed, 93 insertions(+), 52 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > index b6435479cac8..ece1aee5a667 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > @@ -268,6 +268,7 @@ struct amdgpu_irq_src;
> >   struct amdgpu_fpriv;
> >   struct amdgpu_bo_va_mapping;
> >   struct amdgpu_atif;
> > +struct amdgpu_atcs;
> >   struct kfd_vm_fault_info;
> >   struct amdgpu_hive_info;
> >   struct amdgpu_reset_context;
> > @@ -681,20 +682,6 @@ struct amdgpu_vram_scratch {
> >   u64 gpu_addr;
> >   };
> >
> > -/*
> > - * ACPI
> > - */
> > -struct amdgpu_atcs_functions {
> > - bool get_ext_state;
> > - bool pcie_perf_req;
> > - bool pcie_dev_rdy;
> > - bool pcie_bus_width;
> > -};
> > -
> > -struct amdgpu_atcs {
> > - struct amdgpu_atcs_functions functions;
> > -};
> > -
> >   /*
> >* CGS
> >*/
> > @@ -825,7 +812,7 @@ struct amdgpu_device {
> >   struct amdgpu_i2c_chan  *i2c_bus[AMDGPU_MAX_I2C_BUS];
> >   struct debugfs_blob_wrapper debugfs_vbios_blob;
> >   struct amdgpu_atif  *atif;
> > - struct amdgpu_atcs  atcs;
> > + struct amdgpu_atcs  *atcs;
> >   struct mutexsrbm_mutex;
> >   /* GRBM index mutex. Protects concurrent access to GRBM index */
> >   struct mutexgrbm_idx_mutex;
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c 
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
> > index 6cf6231057fc..29708b5685ad 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
> > @@ -72,12 +72,25 @@ struct amdgpu_atif {
> >   struct amdgpu_dm_backlight_caps backlight_caps;
> >   };
> >
> > +struct amdgpu_atcs_functions {
> > + bool get_ext_state;
> > + bool pcie_perf_req;
> > + bool pcie_dev_rdy;
> > + bool pcie_bus_width;
> > +};
> > +
> > +struct amdgpu_atcs {
> > + acpi_handle handle;
> > +
> > + struct amdgpu_atcs_functions functions;
> > +};
> > +
> >   /* Call the ATIF method
> >*/
> >   /**
> >* amdgpu_atif_call - call an ATIF method
> >*
> > - * @atif: acpi handle
> > + * @atif: atif structure
> >* @function: the ATIF function to execute
> >* @params: ATIF function params
> >*
> > @@ -237,6 +250,35 @@ static acpi_handle 
> > amdgpu_atif_probe_handle(acpi_handle dhandle)
> >   return handle;
> >   }
> >
> > +static acpi_handle amdgpu_atcs_probe_handle(acpi_handle dhandle)
> > +{
> > + acpi_handle handle = NULL;
> > + char acpi_method_name[255] = { 0 };
> > + struct acpi_buffer buffer = { sizeof(acpi_method_name), 
> > acpi_method_name };
> > + acpi_status status;
> > +
> > + /* For PX/HG systems, ATCS and ATPX are in the iGPU's namespace, on 
> > dGPU only
> > +  * systems, ATIF is in the dGPU's namespace.
> > +  */
> > + status = acpi_get_handle(dhandle, "ATCS", &handle);
> > + if (ACPI_SUCCESS(status))
> > + goto out;
> > +
> > + if (amdgpu_has_atpx()) {
> > + status = acpi_get_handle(amdgpu_atpx_get_dhandle(), "ATCS",
> > +  &handle);
> > + if (ACPI_SUCCESS(status))
> > + goto out;
> > + }
> > +
> > + DRM_DEBUG_DRIVER("No ATCS handle found\n");
> > + return NULL;
> > +out:
> > + acpi_get_name(handle, ACPI_FULL_PATHNAME, &buffer);
> > + DRM_DEBUG_DRIVER("Found ATCS handle %s\n", acpi_method_name);
> > + return handle;
> > +}
> > +
> >   /**
> >* amdgpu_atif_get_notification_params - determine notify configuration
> >*
> > @@ -486,14 +528,15 @@ static int amdgpu_atif_handler(struct amdgpu_device 
> > *adev,
> >   /**
> >* amdgpu_atcs_call - call an ATCS method
> >*
> > - * @handle: acpi handle
> > + * @atcs: atcs structure
> >* @function: the ATCS function to execute
> >* @params: ATCS function params
> >*
> >* Executes the requested ATCS function (all asics).
> >* Returns a pointer to the acpi output buffer.
> >*/
> > -static union acpi_object *amdgpu_atcs_call(acpi_handle handle, int 
> > function,
> > +static union acpi_object *amdgpu_atcs_call(struct amdgpu_atcs *atcs,
> > +int func

Re: [PATCH v2 3/3] drm/amdgpu: Workaround IOMMU driver bug

[Felix Kuehling]

Am 2021-05-21 um 4:41 a.m. schrieb Christian König:
> Am 21.05.21 um 04:22 schrieb Felix Kuehling:
>> The intel IOMMU driver causes kernel oopses or internal errors flooding
>> kernel log when mapping larger SG tables. Limiting the size of
>> userptr BOs
>> to 6GB seems to avoid this.
>>
>> Signed-off-by: Felix Kuehling 
>
> CC whoever is the maintainer of the Intel IOMMU driver?
>
> Would be nice to have that bug fixed instead.

Yeah, I'm not ready to submit this hack. I want to run some more
experiments to see what's going on.

Regards,
  Felix


>
> Christian.
>
>> ---
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 3 +++
>>   1 file changed, 3 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
>> index 2b8b89535198..3becf9d9f8fd 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
>> @@ -1409,6 +1409,9 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
>>   domain = alloc_domain = AMDGPU_GEM_DOMAIN_GTT;
>>   alloc_flags = 0;
>>   } else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
>> +    /* workaround IOMMU driver bug */
>> +    if (size >= (6ULL << 30))
>> +    return -ENOMEM;
>>   domain = AMDGPU_GEM_DOMAIN_GTT;
>>   alloc_domain = AMDGPU_GEM_DOMAIN_CPU;
>>   alloc_flags = AMDGPU_GEM_CREATE_PREEMPTIBLE;
>
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Re: [PATCH] drm/amdgpu: Fix inconsistent indenting

[Christian König]

Am 21.05.21 um 11:50 schrieb Jiapeng Chong:

Eliminate the follow smatch warning:

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c:449
sdma_v5_0_ring_emit_mem_sync() warn: inconsistent indenting.

Reported-by: Abaci Robot 
Signed-off-by: Jiapeng Chong 


Reviewed-by: Christian König 


---
  drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 13 ++---
  1 file changed, 6 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
index 75d7310..c45e1b0 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
@@ -440,20 +440,19 @@ static void sdma_v5_0_ring_emit_ib(struct amdgpu_ring 
*ring,
   */
  static void sdma_v5_0_ring_emit_mem_sync(struct amdgpu_ring *ring)
  {
-uint32_t gcr_cntl =
-   SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV |
-   SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV |
-   SDMA_GCR_GLI_INV(1);
+   uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | 
SDMA_GCR_GLM_INV |
+   SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | 
SDMA_GCR_GLK_INV |
+   SDMA_GCR_GLI_INV(1);
  
  	/* flush entire cache L0/L1/L2, this can be optimized by performance requirement */

amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ));
amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0));
amdgpu_ring_write(ring, 
SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) |
-   SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0));
+ SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0));
amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) |
-   SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 
16));
+ SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl 
>> 16));
amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) |
-   SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0));
+ SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0));
  }
  
  /**


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[PATCH] drm/amdgpu: Fix inconsistent indenting

[Jiapeng Chong]

Eliminate the follow smatch warning:

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c:449
sdma_v5_0_ring_emit_mem_sync() warn: inconsistent indenting.

Reported-by: Abaci Robot 
Signed-off-by: Jiapeng Chong 
---
 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 13 ++---
 1 file changed, 6 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
index 75d7310..c45e1b0 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
@@ -440,20 +440,19 @@ static void sdma_v5_0_ring_emit_ib(struct amdgpu_ring 
*ring,
  */
 static void sdma_v5_0_ring_emit_mem_sync(struct amdgpu_ring *ring)
 {
-uint32_t gcr_cntl =
-   SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV |
-   SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV |
-   SDMA_GCR_GLI_INV(1);
+   uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | 
SDMA_GCR_GLM_INV |
+   SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | 
SDMA_GCR_GLK_INV |
+   SDMA_GCR_GLI_INV(1);
 
/* flush entire cache L0/L1/L2, this can be optimized by performance 
requirement */
amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ));
amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0));
amdgpu_ring_write(ring, 
SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) |
-   SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0));
+ SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0));
amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) |
-   SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 
16));
+ SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl 
>> 16));
amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) |
-   SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0));
+ SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0));
 }
 
 /**
-- 
1.8.3.1

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Re: [PATCH 7/7] drm/amdgpu: do not allocate entries separately

[Christian König]

Am 21.05.21 um 14:45 schrieb Nirmoy Das:

Allocate PD/PT entries while allocating VM BOs and use that
instead of allocating those entries separately.

Signed-off-by: Nirmoy Das 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 31 ++
  1 file changed, 17 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 120e6b7a0286..4717f075a391 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -880,7 +880,12 @@ static int amdgpu_vm_pt_create(struct amdgpu_device *adev,
bp.domain = amdgpu_bo_get_preferred_pin_domain(adev, bp.domain);
bp.flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
AMDGPU_GEM_CREATE_CPU_GTT_USWC;
-   bp.bo_ptr_size = sizeof(struct amdgpu_bo_vm);
+   if (level < AMDGPU_VM_PTB)
+   bp.bo_ptr_size = struct_size((*vmbo), entries,
+amdgpu_vm_num_entries(adev, 
level));
+   else
+   bp.bo_ptr_size = sizeof(struct amdgpu_bo_vm);
+


Rather do it like this here:

if (level < AMDGPU_VM_PTB)
    num_entries = amdgpu_vm_num_entries(...)
else
    num_entries = 0;

bp.bo_ptr_size = struct_size()

If we have that calculation more than once then it might make sense to 
unify it in a function, but I don't think so of hand.


Regards,
Christian.


if (vm->use_cpu_for_update)
bp.flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
  
@@ -954,19 +959,14 @@ static int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,

struct amdgpu_bo_vm *pt;
int r;
  
-	if (cursor->level < AMDGPU_VM_PTB && !entry->entries) {

-   unsigned num_entries;
-
-   num_entries = amdgpu_vm_num_entries(adev, cursor->level);
-   entry->entries = kvmalloc_array(num_entries,
-   sizeof(*entry->entries),
-   GFP_KERNEL | __GFP_ZERO);
-   if (!entry->entries)
-   return -ENOMEM;
-   }
-
-   if (entry->base.bo)
+   if (entry->base.bo) {
+   if (cursor->level < AMDGPU_VM_PTB)
+   entry->entries =
+   to_amdgpu_bo_vm(entry->base.bo)->entries;
+   else
+   entry->entries = NULL;
return 0;
+   }
  
  	r = amdgpu_vm_pt_create(adev, vm, cursor->level, immediate, &pt);

if (r)
@@ -978,6 +978,10 @@ static int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
pt_bo = &pt->bo;
pt_bo->parent = amdgpu_bo_ref(cursor->parent->base.bo);
amdgpu_vm_bo_base_init(&entry->base, vm, pt_bo);
+   if (cursor->level < AMDGPU_VM_PTB)
+   entry->entries = pt->entries;
+   else
+   entry->entries = NULL;
  
  	r = amdgpu_vm_clear_bo(adev, vm, pt_bo, immediate);

if (r)
@@ -1005,7 +1009,6 @@ static void amdgpu_vm_free_table(struct amdgpu_vm_pt 
*entry)

amdgpu_bo_unref(&to_amdgpu_bo_vm(entry->base.bo)->shadow);
amdgpu_bo_unref(&entry->base.bo);
}
-   kvfree(entry->entries);
entry->entries = NULL;
  }
  


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Re: [PATCH 2/7] drm/amdgpu: add a new identifier for amdgpu_bo

[Christian König]

Am 21.05.21 um 14:45 schrieb Nirmoy Das:

Add has_shadow to identify if a BO is shadowed.


Ok that is not going into the right direction.

Instead of identifying which BOs have a shadow we need to identify if 
this is a VM BO or not.


I think the first think you need to do is to move the shadow handling 
from amdgpu_cs_validate() into amdgpu_vm_validate_pt_bos().


And then do it only for ttm_bo_type_kernel BOs, cause those are the 
PD/PT BOs.


Regards,
Christian.



Signed-off-by: Nirmoy Das 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 2 ++
  drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 5 ++---
  2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 61b1edcb490a..eb3ce33cbfff 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -619,6 +619,7 @@ int amdgpu_bo_create(struct amdgpu_device *adev,
}
if (!bp->resv)
amdgpu_bo_unreserve(bo);
+   bo->has_shadow = false;
*bo_ptr = bo;
  
  	trace_amdgpu_bo_create(bo);

@@ -657,6 +658,7 @@ int amdgpu_bo_create_shadow(struct amdgpu_device *adev,
r = amdgpu_bo_create(adev, &bp, &bo->shadow);
if (!r) {
bo->shadow->parent = amdgpu_bo_ref(bo);
+   bo->has_shadow = true;
mutex_lock(&adev->shadow_list_lock);
list_add_tail(&bo->shadow->shadow_list, &adev->shadow_list);
mutex_unlock(&adev->shadow_list_lock);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
index a7fbf5f7051e..3a0e6ca88563 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
@@ -104,9 +104,8 @@ struct amdgpu_bo {
struct amdgpu_vm_bo_base*vm_bo;
/* Constant after initialization */
struct amdgpu_bo*parent;
-   struct amdgpu_bo*shadow;
-
-
+   struct amdgpu_bo*shadow;
+   boolhas_shadow;
  
  #ifdef CONFIG_MMU_NOTIFIER

struct mmu_interval_notifiernotifier;


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[PATCH 7/7] drm/amdgpu: do not allocate entries separately

[Nirmoy Das]

Allocate PD/PT entries while allocating VM BOs and use that
instead of allocating those entries separately.

Signed-off-by: Nirmoy Das 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 31 ++
 1 file changed, 17 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 120e6b7a0286..4717f075a391 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -880,7 +880,12 @@ static int amdgpu_vm_pt_create(struct amdgpu_device *adev,
bp.domain = amdgpu_bo_get_preferred_pin_domain(adev, bp.domain);
bp.flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
AMDGPU_GEM_CREATE_CPU_GTT_USWC;
-   bp.bo_ptr_size = sizeof(struct amdgpu_bo_vm);
+   if (level < AMDGPU_VM_PTB)
+   bp.bo_ptr_size = struct_size((*vmbo), entries,
+amdgpu_vm_num_entries(adev, 
level));
+   else
+   bp.bo_ptr_size = sizeof(struct amdgpu_bo_vm);
+
if (vm->use_cpu_for_update)
bp.flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 
@@ -954,19 +959,14 @@ static int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
struct amdgpu_bo_vm *pt;
int r;
 
-   if (cursor->level < AMDGPU_VM_PTB && !entry->entries) {
-   unsigned num_entries;
-
-   num_entries = amdgpu_vm_num_entries(adev, cursor->level);
-   entry->entries = kvmalloc_array(num_entries,
-   sizeof(*entry->entries),
-   GFP_KERNEL | __GFP_ZERO);
-   if (!entry->entries)
-   return -ENOMEM;
-   }
-
-   if (entry->base.bo)
+   if (entry->base.bo) {
+   if (cursor->level < AMDGPU_VM_PTB)
+   entry->entries =
+   to_amdgpu_bo_vm(entry->base.bo)->entries;
+   else
+   entry->entries = NULL;
return 0;
+   }
 
r = amdgpu_vm_pt_create(adev, vm, cursor->level, immediate, &pt);
if (r)
@@ -978,6 +978,10 @@ static int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
pt_bo = &pt->bo;
pt_bo->parent = amdgpu_bo_ref(cursor->parent->base.bo);
amdgpu_vm_bo_base_init(&entry->base, vm, pt_bo);
+   if (cursor->level < AMDGPU_VM_PTB)
+   entry->entries = pt->entries;
+   else
+   entry->entries = NULL;
 
r = amdgpu_vm_clear_bo(adev, vm, pt_bo, immediate);
if (r)
@@ -1005,7 +1009,6 @@ static void amdgpu_vm_free_table(struct amdgpu_vm_pt 
*entry)

amdgpu_bo_unref(&to_amdgpu_bo_vm(entry->base.bo)->shadow);
amdgpu_bo_unref(&entry->base.bo);
}
-   kvfree(entry->entries);
entry->entries = NULL;
 }
 
-- 
2.31.1

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[PATCH 4/7] drm/amdgpu: create shadow bo directly

[Nirmoy Das]

Shadow BOs are only needed by VM code so create it
directly within vm code.

Signed-off-by: Nirmoy Das 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 23 +--
 1 file changed, 21 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 1ac0293e5123..cead68181197 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -867,6 +867,8 @@ static int amdgpu_vm_pt_create(struct amdgpu_device *adev,
 {
struct amdgpu_bo_param bp;
struct amdgpu_bo *bo;
+   struct amdgpu_bo *shadow_bo;
+   struct dma_resv *resv;
int r;
 
memset(&bp, 0, sizeof(bp));
@@ -897,9 +899,19 @@ static int amdgpu_vm_pt_create(struct amdgpu_device *adev,
if (!bp.resv)
WARN_ON(dma_resv_lock(bo->tbo.base.resv,
  NULL));
-   r = amdgpu_bo_create_shadow(adev, bp.size, bo);
+   resv = bp.resv;
+   memset(&bp, 0, sizeof(bp));
+   bp.size = amdgpu_vm_bo_size(adev, level);
+   bp.domain = AMDGPU_GEM_DOMAIN_GTT;
+   bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
+   bp.type = ttm_bo_type_kernel;
+   bp.resv = bo->tbo.base.resv;
+   bp.bo_ptr_size = sizeof(struct amdgpu_bo);
 
-   if (!bp.resv)
+   r = amdgpu_bo_create(adev, &bp, &shadow_bo);
+
+
+   if (!resv)
dma_resv_unlock(bo->tbo.base.resv);
 
if (r) {
@@ -907,6 +919,13 @@ static int amdgpu_vm_pt_create(struct amdgpu_device *adev,
return r;
}
 
+   shadow_bo->parent = amdgpu_bo_ref(bo);
+   bo->has_shadow = true;
+   mutex_lock(&adev->shadow_list_lock);
+   list_add_tail(&shadow_bo->shadow_list, &adev->shadow_list);
+   mutex_unlock(&adev->shadow_list_lock);
+   bo->shadow = shadow_bo;
+
return 0;
 }
 
-- 
2.31.1

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[PATCH 5/7] drm/amdgpu: switch to amdgpu_bo_vm's shadow

[Nirmoy Das]

Use shadow of amdgpu_bo_vm instead of the base class.

Signed-off-by: Nirmoy Das 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c  |  4 +--
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c  | 27 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 16 ++--
 3 files changed, 26 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 90136f9dedd6..46ccd43566e2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -460,8 +460,8 @@ static int amdgpu_cs_validate(void *param, struct amdgpu_bo 
*bo)
if (r)
return r;
 
-   if (bo->shadow)
-   r = amdgpu_cs_bo_validate(p, bo->shadow);
+   if (bo->has_shadow)
+   r = amdgpu_cs_bo_validate(p, to_amdgpu_bo_vm(bo)->shadow);
 
return r;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index cead68181197..120e6b7a0286 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -658,9 +658,9 @@ void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev,
 
ttm_bo_move_to_lru_tail(&bo->tbo, &bo->tbo.mem,
&vm->lru_bulk_move);
-   if (bo->shadow)
-   ttm_bo_move_to_lru_tail(&bo->shadow->tbo,
-   &bo->shadow->tbo.mem,
+   if (bo->has_shadow)
+   
ttm_bo_move_to_lru_tail(&to_amdgpu_bo_vm(bo)->shadow->tbo,
+   
&to_amdgpu_bo_vm(bo)->shadow->tbo.mem,
&vm->lru_bulk_move);
}
spin_unlock(&adev->mman.bdev.lru_lock);
@@ -788,8 +788,9 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
if (r)
return r;
 
-   if (bo->shadow) {
-   r = ttm_bo_validate(&bo->shadow->tbo, &bo->shadow->placement,
+   if (bo->has_shadow) {
+   r = ttm_bo_validate(&to_amdgpu_bo_vm(bo)->shadow->tbo,
+   &to_amdgpu_bo_vm(bo)->shadow->placement,
&ctx);
if (r)
return r;
@@ -924,7 +925,7 @@ static int amdgpu_vm_pt_create(struct amdgpu_device *adev,
mutex_lock(&adev->shadow_list_lock);
list_add_tail(&shadow_bo->shadow_list, &adev->shadow_list);
mutex_unlock(&adev->shadow_list_lock);
-   bo->shadow = shadow_bo;
+   (*vmbo)->shadow = shadow_bo;
 
return 0;
 }
@@ -985,7 +986,7 @@ static int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
return 0;
 
 error_free_pt:
-   amdgpu_bo_unref(&pt_bo->shadow);
+   amdgpu_bo_unref(&pt->shadow);
amdgpu_bo_unref(&pt_bo);
return r;
 }
@@ -1000,7 +1001,8 @@ static void amdgpu_vm_free_table(struct amdgpu_vm_pt 
*entry)
if (entry->base.bo) {
entry->base.bo->vm_bo = NULL;
list_del(&entry->base.vm_status);
-   amdgpu_bo_unref(&entry->base.bo->shadow);
+   if (&entry->base.bo->has_shadow)
+   
amdgpu_bo_unref(&to_amdgpu_bo_vm(entry->base.bo)->shadow);
amdgpu_bo_unref(&entry->base.bo);
}
kvfree(entry->entries);
@@ -2691,7 +2693,8 @@ void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
struct amdgpu_vm_bo_base *bo_base;
 
/* shadow bo doesn't have bo base, its validation needs its parent */
-   if (bo->parent && bo->parent->shadow == bo)
+   if (bo->parent && bo->parent->has_shadow &&
+   to_amdgpu_bo_vm(bo->parent)->shadow == bo)
bo = bo->parent;
 
for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) {
@@ -2953,8 +2956,8 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct 
amdgpu_vm *vm, u32 pasid)
amdgpu_bo_unreserve(vm->root.base.bo);
 
 error_free_root:
-   amdgpu_bo_unref(&vm->root.base.bo->shadow);
-   amdgpu_bo_unref(&vm->root.base.bo);
+   amdgpu_bo_unref(&root->shadow);
+   amdgpu_bo_unref(&root_bo);
vm->root.base.bo = NULL;
 
 error_free_delayed:
@@ -3096,7 +3099,7 @@ int amdgpu_vm_make_compute(struct amdgpu_device *adev, 
struct amdgpu_vm *vm,
}
 
/* Free the shadow bo for compute VM */
-   amdgpu_bo_unref(&vm->root.base.bo->shadow);
+   amdgpu_bo_unref(&to_amdgpu_bo_vm(vm->root.base.bo)->shadow);
 
if (pasid)
vm->pasid = pasid;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
index a83a646759c5..f92260594c72 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
@@ -41,8 +41,8 @@ static int amdgpu_vm_sdma_map_table(struct amdgpu_bo *table)
if (r)
return r;
 
-   if (table->shadow)
-   

[PATCH 6/7] drm/amdgpu: remove unused code

[Nirmoy Das]

Remove unused code related to shadow BO.

Signed-off-by: Nirmoy Das 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 30 --
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.h |  4 ---
 2 files changed, 34 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index eb3ce33cbfff..7308048bb7cc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -637,36 +637,6 @@ int amdgpu_bo_create(struct amdgpu_device *adev,
return r;
 }
 
-int amdgpu_bo_create_shadow(struct amdgpu_device *adev,
-   unsigned long size,
-   struct amdgpu_bo *bo)
-{
-   struct amdgpu_bo_param bp;
-   int r;
-
-   if (bo->shadow)
-   return 0;
-
-   memset(&bp, 0, sizeof(bp));
-   bp.size = size;
-   bp.domain = AMDGPU_GEM_DOMAIN_GTT;
-   bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
-   bp.type = ttm_bo_type_kernel;
-   bp.resv = bo->tbo.base.resv;
-   bp.bo_ptr_size = sizeof(struct amdgpu_bo);
-
-   r = amdgpu_bo_create(adev, &bp, &bo->shadow);
-   if (!r) {
-   bo->shadow->parent = amdgpu_bo_ref(bo);
-   bo->has_shadow = true;
-   mutex_lock(&adev->shadow_list_lock);
-   list_add_tail(&bo->shadow->shadow_list, &adev->shadow_list);
-   mutex_unlock(&adev->shadow_list_lock);
-   }
-
-   return r;
-}
-
 /**
  * amdgpu_bo_create_user - create an &amdgpu_bo_user buffer object
  * @adev: amdgpu device object
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
index 3a0e6ca88563..df30dc7effda 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
@@ -104,7 +104,6 @@ struct amdgpu_bo {
struct amdgpu_vm_bo_base*vm_bo;
/* Constant after initialization */
struct amdgpu_bo*parent;
-   struct amdgpu_bo*shadow;
boolhas_shadow;
 
 #ifdef CONFIG_MMU_NOTIFIER
@@ -283,9 +282,6 @@ int amdgpu_bo_create_vm(struct amdgpu_device *adev,
struct amdgpu_bo_vm **ubo_ptr);
 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,
   void **cpu_addr);
-int amdgpu_bo_create_shadow(struct amdgpu_device *adev,
-   unsigned long size,
-   struct amdgpu_bo *bo);
 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr);
 void *amdgpu_bo_kptr(struct amdgpu_bo *bo);
 void amdgpu_bo_kunmap(struct amdgpu_bo *bo);
-- 
2.31.1

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[PATCH 2/7] drm/amdgpu: add a new identifier for amdgpu_bo

[Nirmoy Das]

Add has_shadow to identify if a BO is shadowed.

Signed-off-by: Nirmoy Das 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 2 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 5 ++---
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 61b1edcb490a..eb3ce33cbfff 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -619,6 +619,7 @@ int amdgpu_bo_create(struct amdgpu_device *adev,
}
if (!bp->resv)
amdgpu_bo_unreserve(bo);
+   bo->has_shadow = false;
*bo_ptr = bo;
 
trace_amdgpu_bo_create(bo);
@@ -657,6 +658,7 @@ int amdgpu_bo_create_shadow(struct amdgpu_device *adev,
r = amdgpu_bo_create(adev, &bp, &bo->shadow);
if (!r) {
bo->shadow->parent = amdgpu_bo_ref(bo);
+   bo->has_shadow = true;
mutex_lock(&adev->shadow_list_lock);
list_add_tail(&bo->shadow->shadow_list, &adev->shadow_list);
mutex_unlock(&adev->shadow_list_lock);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
index a7fbf5f7051e..3a0e6ca88563 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
@@ -104,9 +104,8 @@ struct amdgpu_bo {
struct amdgpu_vm_bo_base*vm_bo;
/* Constant after initialization */
struct amdgpu_bo*parent;
-   struct amdgpu_bo*shadow;
-
-
+   struct amdgpu_bo*shadow;
+   boolhas_shadow;
 
 #ifdef CONFIG_MMU_NOTIFIER
struct mmu_interval_notifiernotifier;
-- 
2.31.1

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[PATCH 1/7] drm/amdgpu: add amdgpu_bo_vm bo type

[Nirmoy Das]

Add new BO subcalss that will be used by amdgpu vm code.

Signed-off-by: Nirmoy Das 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 32 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 10 +++
 2 files changed, 42 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 745fcf3ea450..61b1edcb490a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -692,6 +692,38 @@ int amdgpu_bo_create_user(struct amdgpu_device *adev,
*ubo_ptr = to_amdgpu_bo_user(bo_ptr);
return r;
 }
+
+/**
+ * amdgpu_bo_create_vm - create an &amdgpu_bo_vm buffer object
+ * @adev: amdgpu device object
+ * @bp: parameters to be used for the buffer object
+ * @vmbo_ptr: pointer to the buffer object pointer
+ *
+ * Create a BO to be for GPUVM.
+ *
+ * Returns:
+ * 0 for success or a negative error code on failure.
+ */
+
+int amdgpu_bo_create_vm(struct amdgpu_device *adev,
+   struct amdgpu_bo_param *bp,
+   struct amdgpu_bo_vm **vmbo_ptr)
+{
+   struct amdgpu_bo *bo_ptr;
+   int r;
+
+   /* bo_ptr_size will be determined by the caller and it depends on
+* num of amdgpu_vm_pt entries.
+*/
+   BUG_ON(bp->bo_ptr_size < sizeof(struct amdgpu_bo_vm));
+   r = amdgpu_bo_create(adev, bp, &bo_ptr);
+   if (r)
+   return r;
+
+   *vmbo_ptr = to_amdgpu_bo_vm(bo_ptr);
+   return r;
+}
+
 /**
  * amdgpu_bo_validate - validate an &amdgpu_bo buffer object
  * @bo: pointer to the buffer object
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
index 11480c5a2716..a7fbf5f7051e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
@@ -44,6 +44,7 @@
 #define AMDGPU_AMDKFD_CREATE_SVM_BO(1ULL << 62)
 
 #define to_amdgpu_bo_user(abo) container_of((abo), struct amdgpu_bo_user, bo)
+#define to_amdgpu_bo_vm(abo) container_of((abo), struct amdgpu_bo_vm, bo)
 
 struct amdgpu_bo_param {
unsigned long   size;
@@ -125,6 +126,12 @@ struct amdgpu_bo_user {
 
 };
 
+struct amdgpu_bo_vm {
+   struct amdgpu_bobo;
+   struct amdgpu_bo*shadow;
+   struct amdgpu_vm_pt entries[];
+};
+
 static inline struct amdgpu_bo *ttm_to_amdgpu_bo(struct ttm_buffer_object *tbo)
 {
return container_of(tbo, struct amdgpu_bo, tbo);
@@ -272,6 +279,9 @@ int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev,
 int amdgpu_bo_create_user(struct amdgpu_device *adev,
  struct amdgpu_bo_param *bp,
  struct amdgpu_bo_user **ubo_ptr);
+int amdgpu_bo_create_vm(struct amdgpu_device *adev,
+   struct amdgpu_bo_param *bp,
+   struct amdgpu_bo_vm **ubo_ptr);
 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,
   void **cpu_addr);
 int amdgpu_bo_create_shadow(struct amdgpu_device *adev,
-- 
2.31.1

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[PATCH 3/7] drm/amdgpu: use amdgpu_bo_vm for vm code

[Nirmoy Das]

Use amdgpu_bo_vm for BO for PT/PD.

Signed-off-by: Nirmoy Das 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 43 ++
 1 file changed, 24 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 55991f393481..1ac0293e5123 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -863,9 +863,10 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
 static int amdgpu_vm_pt_create(struct amdgpu_device *adev,
   struct amdgpu_vm *vm,
   int level, bool immediate,
-  struct amdgpu_bo **bo)
+  struct amdgpu_bo_vm **vmbo)
 {
struct amdgpu_bo_param bp;
+   struct amdgpu_bo *bo;
int r;
 
memset(&bp, 0, sizeof(bp));
@@ -876,7 +877,7 @@ static int amdgpu_vm_pt_create(struct amdgpu_device *adev,
bp.domain = amdgpu_bo_get_preferred_pin_domain(adev, bp.domain);
bp.flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
AMDGPU_GEM_CREATE_CPU_GTT_USWC;
-   bp.bo_ptr_size = sizeof(struct amdgpu_bo);
+   bp.bo_ptr_size = sizeof(struct amdgpu_bo_vm);
if (vm->use_cpu_for_update)
bp.flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 
@@ -885,23 +886,24 @@ static int amdgpu_vm_pt_create(struct amdgpu_device *adev,
if (vm->root.base.bo)
bp.resv = vm->root.base.bo->tbo.base.resv;
 
-   r = amdgpu_bo_create(adev, &bp, bo);
+   r = amdgpu_bo_create_vm(adev, &bp, vmbo);
if (r)
return r;
 
+   bo = &(*vmbo)->bo;
if (vm->is_compute_context && (adev->flags & AMD_IS_APU))
return 0;
 
if (!bp.resv)
-   WARN_ON(dma_resv_lock((*bo)->tbo.base.resv,
+   WARN_ON(dma_resv_lock(bo->tbo.base.resv,
  NULL));
-   r = amdgpu_bo_create_shadow(adev, bp.size, *bo);
+   r = amdgpu_bo_create_shadow(adev, bp.size, bo);
 
if (!bp.resv)
-   dma_resv_unlock((*bo)->tbo.base.resv);
+   dma_resv_unlock(bo->tbo.base.resv);
 
if (r) {
-   amdgpu_bo_unref(bo);
+   amdgpu_bo_unref(&bo);
return r;
}
 
@@ -928,7 +930,8 @@ static int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
   bool immediate)
 {
struct amdgpu_vm_pt *entry = cursor->entry;
-   struct amdgpu_bo *pt;
+   struct amdgpu_bo *pt_bo;
+   struct amdgpu_bo_vm *pt;
int r;
 
if (cursor->level < AMDGPU_VM_PTB && !entry->entries) {
@@ -952,18 +955,19 @@ static int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
/* Keep a reference to the root directory to avoid
 * freeing them up in the wrong order.
 */
-   pt->parent = amdgpu_bo_ref(cursor->parent->base.bo);
-   amdgpu_vm_bo_base_init(&entry->base, vm, pt);
+   pt_bo = &pt->bo;
+   pt_bo->parent = amdgpu_bo_ref(cursor->parent->base.bo);
+   amdgpu_vm_bo_base_init(&entry->base, vm, pt_bo);
 
-   r = amdgpu_vm_clear_bo(adev, vm, pt, immediate);
+   r = amdgpu_vm_clear_bo(adev, vm, pt_bo, immediate);
if (r)
goto error_free_pt;
 
return 0;
 
 error_free_pt:
-   amdgpu_bo_unref(&pt->shadow);
-   amdgpu_bo_unref(&pt);
+   amdgpu_bo_unref(&pt_bo->shadow);
+   amdgpu_bo_unref(&pt_bo);
return r;
 }
 
@@ -2837,7 +2841,8 @@ long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long 
timeout)
  */
 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, u32 pasid)
 {
-   struct amdgpu_bo *root;
+   struct amdgpu_bo *root_bo;
+   struct amdgpu_bo_vm *root;
int r, i;
 
vm->va = RB_ROOT_CACHED;
@@ -2891,18 +2896,18 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct 
amdgpu_vm *vm, u32 pasid)
false, &root);
if (r)
goto error_free_delayed;
-
-   r = amdgpu_bo_reserve(root, true);
+   root_bo = &root->bo;
+   r = amdgpu_bo_reserve(root_bo, true);
if (r)
goto error_free_root;
 
-   r = dma_resv_reserve_shared(root->tbo.base.resv, 1);
+   r = dma_resv_reserve_shared(root_bo->tbo.base.resv, 1);
if (r)
goto error_unreserve;
 
-   amdgpu_vm_bo_base_init(&vm->root.base, vm, root);
+   amdgpu_vm_bo_base_init(&vm->root.base, vm, root_bo);
 
-   r = amdgpu_vm_clear_bo(adev, vm, root, false);
+   r = amdgpu_vm_clear_bo(adev, vm, root_bo, false);
if (r)
goto error_unreserve;
 
-- 
2.31.1

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RE: [PATCH v5 09/10] drm/amdgpu: Use PSP to program IH_RB_CNTL* registers

[Deng, Emily]

Hi Pengju,
 You'd better only switch for sriov.

Best wishes
Emily Deng

>-Original Message-
>From: Zhou, Peng Ju 
>Sent: Friday, May 21, 2021 5:58 PM
>To: Alex Deucher ; Zhao, Victor
>; Deng, Emily 
>Cc: amd-gfx list 
>Subject: RE: [PATCH v5 09/10] drm/amdgpu: Use PSP to program IH_RB_CNTL*
>registers
>
>[AMD Official Use Only - Internal Distribution Only]
>
>Hi @Zhao, Victor/@Deng, Emily
>
>Can you help to answer Alex's question,?
>Because this patch originally from @Zhao, Victor, it's hard for me to explain 
>the
>question.
>
>Alex's question:
>> > --- a/drivers/gpu/drm/amd/amdgpu/nv.c
>> > +++ b/drivers/gpu/drm/amd/amdgpu/nv.c
>> > @@ -845,8 +845,8 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
>> > case CHIP_NAVI12:
>> > amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
>> > amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
>> > -   amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
>> > amdgpu_device_ip_block_add(adev,
>> > &psp_v11_0_ip_block);
>> > +   amdgpu_device_ip_block_add(adev,
>> > + &navi10_ih_ip_block);
>>
>> Is it safe to change the order like this on bare metal?  Please look
>> at what was done for vega and sienna cichlid.  Something like that is 
>> probably
>a better bet.
>
>
>--
>BW
>Pengju Zhou
>
>
>
>
>> -Original Message-
>> From: Alex Deucher 
>> Sent: Thursday, May 20, 2021 11:47 AM
>> To: Zhou, Peng Ju 
>> Cc: amd-gfx list ; Zhao, Victor
>> 
>> Subject: Re: [PATCH v5 09/10] drm/amdgpu: Use PSP to program
>> IH_RB_CNTL* registers
>>
>> On Mon, May 17, 2021 at 10:39 AM Peng Ju Zhou 
>> wrote:
>> >
>> > use psp to program IH_RB_CNTL* if indirect access for ih enabled in
>> > SRIOV environment.
>> >
>> > Signed-off-by: Victor 
>> > Signed-off-by: Peng Ju Zhou 
>> > ---
>> >  drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 19 +--
>> >  drivers/gpu/drm/amd/amdgpu/nv.c|  2 +-
>> >  2 files changed, 18 insertions(+), 3 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
>> > b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
>> > index f4e4040bbd25..2e69cf8db072 100644
>> > --- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
>> > +++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
>> > @@ -151,7 +151,14 @@ static int navi10_ih_toggle_ring_interrupts(struct
>> amdgpu_device *adev,
>> > /* enable_intr field is only valid in ring0 */
>> > if (ih == &adev->irq.ih)
>> > tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ?
>> 1 : 0));
>> > -   WREG32(ih_regs->ih_rb_cntl, tmp);
>> > +   if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
>> > +   if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) 
>> > {
>> > +   DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
>> > +   return -ETIMEDOUT;
>> > +   }
>> > +   } else {
>> > +   WREG32(ih_regs->ih_rb_cntl, tmp);
>> > +   }
>> >
>> > if (enable) {
>> > ih->enabled = true;
>> > @@ -261,7 +268,15 @@ static int navi10_ih_enable_ring(struct
>> amdgpu_device *adev,
>> > tmp = REG_SET_FIELD(tmp, IH_RB_CNTL,
>> WPTR_OVERFLOW_ENABLE, 0);
>> > tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE,
>> 1);
>> > }
>> > -   WREG32(ih_regs->ih_rb_cntl, tmp);
>> > +
>> > +   if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
>> > +   if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) 
>> > {
>> > +   DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
>> > +   return -ETIMEDOUT;
>> > +   }
>> > +   } else {
>> > +   WREG32(ih_regs->ih_rb_cntl, tmp);
>> > +   }
>> >
>> > if (ih == &adev->irq.ih) {
>> > /* set the ih ring 0 writeback address whether it's
>> > enabled or not */ diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c
>> > b/drivers/gpu/drm/amd/amdgpu/nv.c index a9ad28fb55b3..b9c9c4d4606c
>> > 100644
>> > --- a/drivers/gpu/drm/amd/amdgpu/nv.c
>> > +++ b/drivers/gpu/drm/amd/amdgpu/nv.c
>> > @@ -845,8 +845,8 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
>> > case CHIP_NAVI12:
>> > amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
>> > amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
>> > -   amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
>> > amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
>> > +   amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
>>
>> Is it safe to change the order like this on bare metal?  Please look at what 
>> was
>> done for vega and sienna cichlid.  Something like that is probably a better 
>> bet.
>>
>> Alex
>>
>>
>> > if (adev->firmware.load_type == AMDGPU_F

RE: [PATCH v5 09/10] drm/amdgpu: Use PSP to program IH_RB_CNTL* registers

[Zhou, Peng Ju]

[AMD Official Use Only - Internal Distribution Only]

Hi @Zhao, Victor/@Deng, Emily

Can you help to answer Alex's question,?
Because this patch originally from @Zhao, Victor, it's hard for me to explain 
the question.

Alex's question:
> > --- a/drivers/gpu/drm/amd/amdgpu/nv.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/nv.c
> > @@ -845,8 +845,8 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
> > case CHIP_NAVI12:
> > amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
> > amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
> > -   amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
> > amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
> > +   amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
> 
> Is it safe to change the order like this on bare metal?  Please look at what 
> was
> done for vega and sienna cichlid.  Something like that is probably a better 
> bet.


-- 
BW
Pengju Zhou




> -Original Message-
> From: Alex Deucher 
> Sent: Thursday, May 20, 2021 11:47 AM
> To: Zhou, Peng Ju 
> Cc: amd-gfx list ; Zhao, Victor
> 
> Subject: Re: [PATCH v5 09/10] drm/amdgpu: Use PSP to program
> IH_RB_CNTL* registers
> 
> On Mon, May 17, 2021 at 10:39 AM Peng Ju Zhou 
> wrote:
> >
> > use psp to program IH_RB_CNTL* if indirect access for ih enabled in
> > SRIOV environment.
> >
> > Signed-off-by: Victor 
> > Signed-off-by: Peng Ju Zhou 
> > ---
> >  drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 19 +--
> >  drivers/gpu/drm/amd/amdgpu/nv.c|  2 +-
> >  2 files changed, 18 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> > b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> > index f4e4040bbd25..2e69cf8db072 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> > @@ -151,7 +151,14 @@ static int navi10_ih_toggle_ring_interrupts(struct
> amdgpu_device *adev,
> > /* enable_intr field is only valid in ring0 */
> > if (ih == &adev->irq.ih)
> > tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ?
> 1 : 0));
> > -   WREG32(ih_regs->ih_rb_cntl, tmp);
> > +   if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
> > +   if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
> > +   DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
> > +   return -ETIMEDOUT;
> > +   }
> > +   } else {
> > +   WREG32(ih_regs->ih_rb_cntl, tmp);
> > +   }
> >
> > if (enable) {
> > ih->enabled = true;
> > @@ -261,7 +268,15 @@ static int navi10_ih_enable_ring(struct
> amdgpu_device *adev,
> > tmp = REG_SET_FIELD(tmp, IH_RB_CNTL,
> WPTR_OVERFLOW_ENABLE, 0);
> > tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE,
> 1);
> > }
> > -   WREG32(ih_regs->ih_rb_cntl, tmp);
> > +
> > +   if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
> > +   if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
> > +   DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
> > +   return -ETIMEDOUT;
> > +   }
> > +   } else {
> > +   WREG32(ih_regs->ih_rb_cntl, tmp);
> > +   }
> >
> > if (ih == &adev->irq.ih) {
> > /* set the ih ring 0 writeback address whether it's
> > enabled or not */ diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c
> > b/drivers/gpu/drm/amd/amdgpu/nv.c index a9ad28fb55b3..b9c9c4d4606c
> > 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/nv.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/nv.c
> > @@ -845,8 +845,8 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
> > case CHIP_NAVI12:
> > amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
> > amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
> > -   amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
> > amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
> > +   amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
> 
> Is it safe to change the order like this on bare metal?  Please look at what 
> was
> done for vega and sienna cichlid.  Something like that is probably a better 
> bet.
> 
> Alex
> 
> 
> > if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
> > amdgpu_device_ip_block_add(adev, 
> > &smu_v11_0_ip_block);
> > if (adev->enable_virtual_display ||
> > amdgpu_sriov_vf(adev))
> > --
> > 2.17.1
> >
> > ___
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org
> > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flist
> > s.freedesktop.org%2Fmailman%2Flistinfo%2Famd-
> gfx&data=

Re: [PATCH] drm/ttm: Skip swapout if ttm object is not populated

[Christian König]

Am 21.05.21 um 10:31 schrieb xinhui pan:

Swapping a ttm object which has no backend pages makes no sense.

Suggested-by: Christian König 
Signed-off-by: xinhui pan 


Reviewed-by: Christian König 

Going to add a CC: stable and pushing that to drm-misc-fixes in a minute.


---
  drivers/gpu/drm/ttm/ttm_device.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/ttm/ttm_device.c b/drivers/gpu/drm/ttm/ttm_device.c
index 510e3e001dab..a1dcf7d55c90 100644
--- a/drivers/gpu/drm/ttm/ttm_device.c
+++ b/drivers/gpu/drm/ttm/ttm_device.c
@@ -145,7 +145,7 @@ int ttm_device_swapout(struct ttm_device *bdev, struct 
ttm_operation_ctx *ctx,
list_for_each_entry(bo, &man->lru[j], lru) {
uint32_t num_pages;
  
-if (!bo->ttm ||

+   if (!bo->ttm || !ttm_tt_is_populated(bo->ttm) ||
bo->ttm->page_flags & TTM_PAGE_FLAG_SG ||
bo->ttm->page_flags & TTM_PAGE_FLAG_SWAPPED)
continue;


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Re: [PATCH v2 3/3] drm/amdgpu: Workaround IOMMU driver bug

[Christian König]

Am 21.05.21 um 04:22 schrieb Felix Kuehling:

The intel IOMMU driver causes kernel oopses or internal errors flooding
kernel log when mapping larger SG tables. Limiting the size of userptr BOs
to 6GB seems to avoid this.

Signed-off-by: Felix Kuehling 


CC whoever is the maintainer of the Intel IOMMU driver?

Would be nice to have that bug fixed instead.

Christian.


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 3 +++
  1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index 2b8b89535198..3becf9d9f8fd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -1409,6 +1409,9 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
domain = alloc_domain = AMDGPU_GEM_DOMAIN_GTT;
alloc_flags = 0;
} else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
+   /* workaround IOMMU driver bug */
+   if (size >= (6ULL << 30))
+   return -ENOMEM;
domain = AMDGPU_GEM_DOMAIN_GTT;
alloc_domain = AMDGPU_GEM_DOMAIN_CPU;
alloc_flags = AMDGPU_GEM_CREATE_PREEMPTIBLE;


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Re: [PATCH v2 2/3] drm/amdgpu: Use preemptible placement for KFD

[Christian König]

Am 21.05.21 um 04:22 schrieb Felix Kuehling:

KFD userptr BOs and SG BOs used for DMA mappings can be preempted with
CWSR. Therefore we can use preemptible placement and avoid unwanted
evictions due to GTT accounting.

Signed-off-by: Felix Kuehling 


Acked-by: Christian König 


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 7 ---
  1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index 928e8d57cd08..2b8b89535198 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -621,8 +621,8 @@ kfd_mem_attach_userptr(struct amdgpu_device *adev, struct 
kgd_mem *mem,
  
  	ret = amdgpu_gem_object_create(adev, bo_size, 1,

   AMDGPU_GEM_DOMAIN_CPU,
-  0, ttm_bo_type_sg,
-  mem->bo->tbo.base.resv,
+  AMDGPU_GEM_CREATE_PREEMPTIBLE,
+  ttm_bo_type_sg, mem->bo->tbo.base.resv,
   &gobj);
if (ret)
return ret;
@@ -662,6 +662,7 @@ kfd_mem_attach_dmabuf(struct amdgpu_device *adev, struct 
kgd_mem *mem,
dma_buf_put(mem->dmabuf);
  
  	*bo = gem_to_amdgpu_bo(gobj);

+   (*bo)->flags |= AMDGPU_GEM_CREATE_PREEMPTIBLE;
(*bo)->parent = amdgpu_bo_ref(mem->bo);
  
  	return 0;

@@ -1410,7 +1411,7 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
} else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
domain = AMDGPU_GEM_DOMAIN_GTT;
alloc_domain = AMDGPU_GEM_DOMAIN_CPU;
-   alloc_flags = 0;
+   alloc_flags = AMDGPU_GEM_CREATE_PREEMPTIBLE;
if (!offset || !*offset)
return -EINVAL;
user_addr = untagged_addr(*offset);


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Re: [PATCH v2 1/3] drm/amdgpu: Add new placement for preemptible SG BOs

[Christian König]

Am 21.05.21 um 04:22 schrieb Felix Kuehling:

SG BOs such as dmabuf imports and userptr BOs do not consume system
resources directly. Instead they point to resources owned elsewhere.
They typically get evicted by DMABuf move notifiers of MMU notifiers.
If those notifiers don't need to wait for hardware fences (i.e. the SG
BOs are used in a preemptible context), then we don't need to limit
them to the GTT size and we don't need TTM to evict them.

Create a new placement for such preemptible SG BOs that does not impose
artificial size limits and TTM evictions.

Signed-off-by: Felix Kuehling 


Reviewed-by: Christian König 

This will clash with the TTM changes I have in pipeline, so somebody 
needs to handle the merge fallout at some point.


But I'm pretty sure that are just a few lines of code.


---
  drivers/gpu/drm/amd/amdgpu/Makefile   |   7 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_object.c|   4 +-
  .../gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.c   | 190 ++
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c   |  37 +++-
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h   |  11 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c|   3 +-
  include/uapi/drm/amdgpu_drm.h |   4 +
  7 files changed, 247 insertions(+), 9 deletions(-)
  create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.c

diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile 
b/drivers/gpu/drm/amd/amdgpu/Makefile
index 6331a11299d0..6cf0fe871d6c 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -51,9 +51,10 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
atombios_encoders.o amdgpu_sa.o atombios_i2c.o \
amdgpu_dma_buf.o amdgpu_vm.o amdgpu_ib.o amdgpu_pll.o \
amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o \
-   amdgpu_gtt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o amdgpu_atomfirmware.o \
-   amdgpu_vf_error.o amdgpu_sched.o amdgpu_debugfs.o amdgpu_ids.o \
-   amdgpu_gmc.o amdgpu_mmhub.o amdgpu_xgmi.o amdgpu_csa.o amdgpu_ras.o 
amdgpu_vm_cpu.o \
+   amdgpu_gtt_mgr.o amdgpu_preempt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o \
+   amdgpu_atomfirmware.o amdgpu_vf_error.o amdgpu_sched.o \
+   amdgpu_debugfs.o amdgpu_ids.o amdgpu_gmc.o amdgpu_mmhub.o \
+   amdgpu_xgmi.o amdgpu_csa.o amdgpu_ras.o amdgpu_vm_cpu.o \
amdgpu_vm_sdma.o amdgpu_discovery.o amdgpu_ras_eeprom.o amdgpu_nbio.o \
amdgpu_umc.o smu_v11_0_i2c.o amdgpu_fru_eeprom.o amdgpu_rap.o \
amdgpu_fw_attestation.o amdgpu_securedisplay.o amdgpu_hdp.o
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 745fcf3ea450..3f85ba8222ef 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -157,7 +157,9 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, 
u32 domain)
if (domain & AMDGPU_GEM_DOMAIN_GTT) {
places[c].fpfn = 0;
places[c].lpfn = 0;
-   places[c].mem_type = TTM_PL_TT;
+   places[c].mem_type =
+   abo->flags & AMDGPU_GEM_CREATE_PREEMPTIBLE ?
+   AMDGPU_PL_PREEMPT : TTM_PL_TT;
places[c].flags = 0;
c++;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.c
new file mode 100644
index ..d607f314cc1b
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.c
@@ -0,0 +1,190 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright 2016-2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Christian König, Felix Kuehling
+ */
+
+#include "amdgpu.h"
+
+static inline struct amdgpu_preempt_mgr *
+to_preempt_mgr(struct ttm_resource_manager *man)
+{
+   return container_of(man, struct amdgpu_preempt_mgr, manager);
+}
+
+/**
+ 

[PATCH] drm/ttm: Skip swapout if ttm object is not populated

[xinhui pan]

Swapping a ttm object which has no backend pages makes no sense.

Suggested-by: Christian König 
Signed-off-by: xinhui pan 
---
 drivers/gpu/drm/ttm/ttm_device.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/ttm/ttm_device.c b/drivers/gpu/drm/ttm/ttm_device.c
index 510e3e001dab..a1dcf7d55c90 100644
--- a/drivers/gpu/drm/ttm/ttm_device.c
+++ b/drivers/gpu/drm/ttm/ttm_device.c
@@ -145,7 +145,7 @@ int ttm_device_swapout(struct ttm_device *bdev, struct 
ttm_operation_ctx *ctx,
list_for_each_entry(bo, &man->lru[j], lru) {
uint32_t num_pages;
 
-   if (!bo->ttm ||
+   if (!bo->ttm || !ttm_tt_is_populated(bo->ttm) ||
bo->ttm->page_flags & TTM_PAGE_FLAG_SG ||
bo->ttm->page_flags & TTM_PAGE_FLAG_SWAPPED)
continue;
-- 
2.25.1

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Re: [PATCH 38/38] drm/amd/amdgpu/smuio_v13_0: Realign 'smuio_v13_0_is_host_gpu_xgmi_supported()' header

[Lee Jones]

On Thu, 20 May 2021, Alex Deucher wrote:

> Applied.  Thanks!

Thanks again Alex.

> On Thu, May 20, 2021 at 8:03 AM Lee Jones  wrote:
> >
> > Fixes the following W=1 kernel build warning(s):
> >
> >  drivers/gpu/drm/amd/amdgpu/smuio_v13_0.c:99: warning: expecting prototype 
> > for smuio_v13_0_supports_host_gpu_xgmi(). Prototype was for 
> > smuio_v13_0_is_host_gpu_xgmi_supported() instead
> >
> > Cc: Alex Deucher 
> > Cc: "Christian König" 
> > Cc: David Airlie 
> > Cc: Daniel Vetter 
> > Cc: Hawking Zhang 
> > Cc: amd-gfx@lists.freedesktop.org
> > Cc: dri-de...@lists.freedesktop.org
> > Signed-off-by: Lee Jones 
> > ---
> >  drivers/gpu/drm/amd/amdgpu/smuio_v13_0.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/smuio_v13_0.c 
> > b/drivers/gpu/drm/amd/amdgpu/smuio_v13_0.c
> > index 3c47c94846d6d..39b7c206770f6 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/smuio_v13_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/smuio_v13_0.c
> > @@ -106,7 +106,7 @@ static u32 smuio_v13_0_get_socket_id(struct 
> > amdgpu_device *adev)
> >  }
> >
> >  /**
> > - * smuio_v13_0_supports_host_gpu_xgmi - detect xgmi interface between cpu 
> > and gpu/s.
> > + * smuio_v13_0_is_host_gpu_xgmi_supported - detect xgmi interface between 
> > cpu and gpu/s.
> >   *
> >   * @adev: amdgpu device pointer
> >   *
> >

-- 
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Senior Technical Lead - Developer Services
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Re: [PATCH 2/2] drm/amdgpu/apci: switch ATIF/ATCS probe order

[Lijo Lazar]

Reviewed-by: Lijo Lazar 

On 5/20/2021 9:26 PM, Alex Deucher wrote:

Try the handle from ATPX first since this is the most
common case.

Signed-off-by: Alex Deucher 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 14 ++
  1 file changed, 6 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
index 29708b5685ad..49563ff87f1a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
@@ -231,16 +231,15 @@ static acpi_handle amdgpu_atif_probe_handle(acpi_handle 
dhandle)
/* For PX/HG systems, ATIF and ATPX are in the iGPU's namespace, on 
dGPU only
 * systems, ATIF is in the dGPU's namespace.
 */
-   status = acpi_get_handle(dhandle, "ATIF", &handle);
-   if (ACPI_SUCCESS(status))
-   goto out;
-
if (amdgpu_has_atpx()) {
status = acpi_get_handle(amdgpu_atpx_get_dhandle(), "ATIF",
 &handle);
if (ACPI_SUCCESS(status))
goto out;
}
+   status = acpi_get_handle(dhandle, "ATIF", &handle);
+   if (ACPI_SUCCESS(status))
+   goto out;
  
  	DRM_DEBUG_DRIVER("No ATIF handle found\n");

return NULL;
@@ -260,16 +259,15 @@ static acpi_handle amdgpu_atcs_probe_handle(acpi_handle 
dhandle)
/* For PX/HG systems, ATCS and ATPX are in the iGPU's namespace, on 
dGPU only
 * systems, ATIF is in the dGPU's namespace.
 */
-   status = acpi_get_handle(dhandle, "ATCS", &handle);
-   if (ACPI_SUCCESS(status))
-   goto out;
-
if (amdgpu_has_atpx()) {
status = acpi_get_handle(amdgpu_atpx_get_dhandle(), "ATCS",
 &handle);
if (ACPI_SUCCESS(status))
goto out;
}
+   status = acpi_get_handle(dhandle, "ATCS", &handle);
+   if (ACPI_SUCCESS(status))
+   goto out;
  
  	DRM_DEBUG_DRIVER("No ATCS handle found\n");

return NULL;



--
Thanks,
Lijo
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Re: [PATCH 1/2] drm/amdgpu/acpi: unify ATCS handling (v3)

[Lijo Lazar]

On 5/20/2021 9:26 PM, Alex Deucher wrote:

Treat it like ATIF and check both the dGPU and APU for
the method.  This is required because ATCS may be hung
off of the APU in ACPI on A+A systems.

v2: add back accidently removed ACPI handle check.
v3: Fix incorrect atif check (Colin)
 Fix uninitialized variable (Colin)

Signed-off-by: Alex Deucher 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu.h  |  17 +--
  drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 128 ---
  2 files changed, 93 insertions(+), 52 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index b6435479cac8..ece1aee5a667 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -268,6 +268,7 @@ struct amdgpu_irq_src;
  struct amdgpu_fpriv;
  struct amdgpu_bo_va_mapping;
  struct amdgpu_atif;
+struct amdgpu_atcs;
  struct kfd_vm_fault_info;
  struct amdgpu_hive_info;
  struct amdgpu_reset_context;
@@ -681,20 +682,6 @@ struct amdgpu_vram_scratch {
u64 gpu_addr;
  };
  
-/*

- * ACPI
- */
-struct amdgpu_atcs_functions {
-   bool get_ext_state;
-   bool pcie_perf_req;
-   bool pcie_dev_rdy;
-   bool pcie_bus_width;
-};
-
-struct amdgpu_atcs {
-   struct amdgpu_atcs_functions functions;
-};
-
  /*
   * CGS
   */
@@ -825,7 +812,7 @@ struct amdgpu_device {
struct amdgpu_i2c_chan  *i2c_bus[AMDGPU_MAX_I2C_BUS];
struct debugfs_blob_wrapper debugfs_vbios_blob;
struct amdgpu_atif  *atif;
-   struct amdgpu_atcs  atcs;
+   struct amdgpu_atcs  *atcs;
struct mutexsrbm_mutex;
/* GRBM index mutex. Protects concurrent access to GRBM index */
struct mutexgrbm_idx_mutex;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
index 6cf6231057fc..29708b5685ad 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
@@ -72,12 +72,25 @@ struct amdgpu_atif {
struct amdgpu_dm_backlight_caps backlight_caps;
  };
  
+struct amdgpu_atcs_functions {

+   bool get_ext_state;
+   bool pcie_perf_req;
+   bool pcie_dev_rdy;
+   bool pcie_bus_width;
+};
+
+struct amdgpu_atcs {
+   acpi_handle handle;
+
+   struct amdgpu_atcs_functions functions;
+};
+
  /* Call the ATIF method
   */
  /**
   * amdgpu_atif_call - call an ATIF method
   *
- * @atif: acpi handle
+ * @atif: atif structure
   * @function: the ATIF function to execute
   * @params: ATIF function params
   *
@@ -237,6 +250,35 @@ static acpi_handle amdgpu_atif_probe_handle(acpi_handle 
dhandle)
return handle;
  }
  
+static acpi_handle amdgpu_atcs_probe_handle(acpi_handle dhandle)

+{
+   acpi_handle handle = NULL;
+   char acpi_method_name[255] = { 0 };
+   struct acpi_buffer buffer = { sizeof(acpi_method_name), 
acpi_method_name };
+   acpi_status status;
+
+   /* For PX/HG systems, ATCS and ATPX are in the iGPU's namespace, on 
dGPU only
+* systems, ATIF is in the dGPU's namespace.
+*/
+   status = acpi_get_handle(dhandle, "ATCS", &handle);
+   if (ACPI_SUCCESS(status))
+   goto out;
+
+   if (amdgpu_has_atpx()) {
+   status = acpi_get_handle(amdgpu_atpx_get_dhandle(), "ATCS",
+&handle);
+   if (ACPI_SUCCESS(status))
+   goto out;
+   }
+
+   DRM_DEBUG_DRIVER("No ATCS handle found\n");
+   return NULL;
+out:
+   acpi_get_name(handle, ACPI_FULL_PATHNAME, &buffer);
+   DRM_DEBUG_DRIVER("Found ATCS handle %s\n", acpi_method_name);
+   return handle;
+}
+
  /**
   * amdgpu_atif_get_notification_params - determine notify configuration
   *
@@ -486,14 +528,15 @@ static int amdgpu_atif_handler(struct amdgpu_device *adev,
  /**
   * amdgpu_atcs_call - call an ATCS method
   *
- * @handle: acpi handle
+ * @atcs: atcs structure
   * @function: the ATCS function to execute
   * @params: ATCS function params
   *
   * Executes the requested ATCS function (all asics).
   * Returns a pointer to the acpi output buffer.
   */
-static union acpi_object *amdgpu_atcs_call(acpi_handle handle, int function,
+static union acpi_object *amdgpu_atcs_call(struct amdgpu_atcs *atcs,
+  int function,
   struct acpi_buffer *params)
  {
acpi_status status;
@@ -517,7 +560,7 @@ static union acpi_object *amdgpu_atcs_call(acpi_handle 
handle, int function,
atcs_arg_elements[1].integer.value = 0;
}
  
-	status = acpi_evaluate_object(handle, "ATCS", &atcs_arg, &buffer);

+   status = acpi_evaluate_object(atcs->handle, "ATCS", &atcs_arg, &buffer);
  
  	/* Fail only if calling the method fails and ATIF is supported */

if (ACPI_FAILURE(status)