Re: [PATCH 24/34] drm/amd/display/modules/hdcp/hdcp_psp: Remove unused function 'mod_hdcp_hdcp1_get_link_encryption_status()'
Applied. Thanks!
On Wed, May 26, 2021 at 4:48 AM Lee Jones wrote:
>
> Fixes the following W=1 kernel build warning(s):
>
> drivers/gpu/drm/amd/amdgpu/../display/modules/hdcp/hdcp_psp.c:374:22:
> warning: no previous prototype for
> ‘mod_hdcp_hdcp1_get_link_encryption_status’ [-Wmissing-prototypes]
>
> Cc: Harry Wentland
> Cc: Leo Li
> Cc: Alex Deucher
> Cc: "Christian König"
> Cc: David Airlie
> Cc: Daniel Vetter
> Cc: amd-gfx@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org
> Signed-off-by: Lee Jones
> ---
> drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c | 13 -
> 1 file changed, 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
> b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
> index 26f96c05e0ec8..06910d2fd57a0 100644
> --- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
> +++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
> @@ -371,19 +371,6 @@ enum mod_hdcp_status
> mod_hdcp_hdcp1_link_maintenance(struct mod_hdcp *hdcp)
> return status;
> }
>
> -enum mod_hdcp_status mod_hdcp_hdcp1_get_link_encryption_status(struct
> mod_hdcp *hdcp,
> - enum
> mod_hdcp_encryption_status *encryption_status)
> -{
> - *encryption_status = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF;
> -
> - if (mod_hdcp_hdcp1_link_maintenance(hdcp) != MOD_HDCP_STATUS_SUCCESS)
> - return MOD_HDCP_STATUS_FAILURE;
> -
> - *encryption_status = MOD_HDCP_ENCRYPTION_STATUS_HDCP1_ON;
> -
> - return MOD_HDCP_STATUS_SUCCESS;
> -}
> -
> enum mod_hdcp_status mod_hdcp_hdcp2_create_session(struct mod_hdcp *hdcp)
> {
> struct psp_context *psp = hdcp->config.psp.handle;
> --
> 2.31.1
>
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Re: [PATCH 23/34] drm/amd/display/dmub/src/dmub_srv_stat: Convert function header to kernel-doc
Applied. Thanks! On Wed, May 26, 2021 at 4:48 AM Lee Jones wrote: > > Fixes the following W=1 kernel build warning(s): > > drivers/gpu/drm/amd/amdgpu/../display/dmub/src/dmub_srv_stat.c:38: warning: > Cannot understand > * > > Cc: Harry Wentland > Cc: Leo Li > Cc: Alex Deucher > Cc: "Christian König" > Cc: David Airlie > Cc: Daniel Vetter > Cc: Jun Lei > Cc: Meenakshikumar Somasundaram > Cc: Rodrigo Siqueira > Cc: amd-gfx@lists.freedesktop.org > Cc: dri-de...@lists.freedesktop.org > Signed-off-by: Lee Jones > --- > .../drm/amd/display/dmub/src/dmub_srv_stat.c | 19 ++- > 1 file changed, 6 insertions(+), 13 deletions(-) > > diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv_stat.c > b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv_stat.c > index e6f3bfab33d3e..70766d534c9c8 100644 > --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv_stat.c > +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv_stat.c > @@ -35,20 +35,13 @@ > */ > > /** > - > * > - * Function: dmub_srv_stat_get_notification > + * dmub_srv_stat_get_notification - Retrieves a dmub outbox notification, > set up dmub notification > + * structure with message information. Also > a pending bit if queue > + * is having more notifications > + * @dmub: dmub srv structure > + * @notify: dmub notification structure to be filled up > * > - * @brief > - * Retrieves a dmub outbox notification, set up dmub notification > - * structure with message information. Also a pending bit if > queue > - * is having more notifications > - * > - * @param [in] dmub: dmub srv structure > - * @param [out] pnotify: dmub notification structure to be filled up > - * > - * @return > - * dmub_status > - > * > + * Returns: dmub_status > */ > enum dmub_status dmub_srv_stat_get_notification(struct dmub_srv *dmub, > struct dmub_notification > *notify) > -- > 2.31.1 > ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 22/34] drm/amd/display/dc/core/dc: Convert function headers to kernel-doc
Applied. Thanks!
On Wed, May 26, 2021 at 4:48 AM Lee Jones wrote:
>
> Fixes the following W=1 kernel build warning(s):
>
> drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:3324: warning: Cannot
> understand
> *
> drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:3344: warning: Cannot
> understand
> *
> drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:3417: warning: Cannot
> understand
> *
>
> Cc: Harry Wentland
> Cc: Leo Li
> Cc: Alex Deucher
> Cc: "Christian König"
> Cc: David Airlie
> Cc: Daniel Vetter
> Cc: amd-gfx@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org
> Signed-off-by: Lee Jones
> ---
> drivers/gpu/drm/amd/display/dc/core/dc.c | 46 ++--
> 1 file changed, 11 insertions(+), 35 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
> b/drivers/gpu/drm/amd/display/dc/core/dc.c
> index ef157b83bacd2..34c207f92df98 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
> @@ -3335,18 +3335,10 @@ void dc_hardware_release(struct dc *dc)
> #endif
>
> /**
> -
> *
> - * Function: dc_enable_dmub_notifications
> + * dc_enable_dmub_notifications - Returns whether dmub notification can be
> enabled
> + * @dc: dc structure
> *
> - * @brief
> - * Returns whether dmub notification can be enabled
> - *
> - * @param
> - * [in] dc: dc structure
> - *
> - * @return
> - * True to enable dmub notifications, False otherwise
> -
> *
> + * Returns: True to enable dmub notifications, False otherwise
> */
> bool dc_enable_dmub_notifications(struct dc *dc)
> {
> @@ -3355,21 +3347,13 @@ bool dc_enable_dmub_notifications(struct dc *dc)
> }
>
> /**
> -
> *
> - * Function: dc_process_dmub_aux_transfer_async
> - *
> - * @brief
> - * Submits aux command to dmub via inbox message
> - * Sets port index appropriately for legacy DDC
> - *
> - * @param
> - * [in] dc: dc structure
> - * [in] link_index: link index
> - * [in] payload: aux payload
> + * dc_process_dmub_aux_transfer_async - Submits aux command to dmub via
> inbox message
> + * Sets port index appropriately for
> legacy DDC
> + * @dc: dc structure
> + * @link_index: link index
> + * @payload: aux payload
> *
> - * @return
> - * True if successful, False if failure
> -
> *
> + * Returns: True if successful, False if failure
> */
> bool dc_process_dmub_aux_transfer_async(struct dc *dc,
> uint32_t link_index,
> @@ -3428,16 +3412,8 @@ bool dc_process_dmub_aux_transfer_async(struct dc *dc,
> }
>
> /**
> -
> *
> - * Function: dc_disable_accelerated_mode
> - *
> - * @brief
> - * disable accelerated mode
> - *
> - * @param
> - * [in] dc: dc structure
> - *
> -
> *
> + * dc_disable_accelerated_mode - disable accelerated mode
> + * @dc: dc structure
> */
> void dc_disable_accelerated_mode(struct dc *dc)
> {
> --
> 2.31.1
>
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Re: [PATCH 21/34] drm/amd/display/dc/dce110/dce110_hw_sequencer: Include header containing our prototypes
Applied. Thanks! On Wed, May 26, 2021 at 4:48 AM Lee Jones wrote: > > Fixes the following W=1 kernel build warning(s): > > drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_hw_sequencer.c:929:6: > warning: no previous prototype for ‘dce110_edp_wait_for_T12’ > [-Wmissing-prototypes] > > Cc: Harry Wentland > Cc: Leo Li > Cc: Alex Deucher > Cc: "Christian König" > Cc: David Airlie > Cc: Daniel Vetter > Cc: amd-gfx@lists.freedesktop.org > Cc: dri-de...@lists.freedesktop.org > Signed-off-by: Lee Jones > --- > drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c > b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c > index 9219db79f32b6..1ef1b1b33fb09 100644 > --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c > +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c > @@ -64,6 +64,7 @@ > #include "atomfirmware.h" > > #include "dce110_hw_sequencer.h" > +#include "dcn10/dcn10_hw_sequencer.h" > > #define GAMMA_HW_POINTS_NUM 256 > > -- > 2.31.1 > ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 20/34] drm/amd/display/amdgpu_dm/amdgpu_dm: Fix kernel-doc formatting issue
Applied. Thanks! On Wed, May 26, 2021 at 4:48 AM Lee Jones wrote: > > Fixes the following W=1 kernel build warning(s): > > drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:608: warning: > Function parameter or member 'interrupt_params' not described in > 'dm_dcn_vertical_interrupt0_high_irq' > > Cc: Harry Wentland > Cc: Leo Li > Cc: Alex Deucher > Cc: "Christian König" > Cc: David Airlie > Cc: Daniel Vetter > Cc: amd-gfx@lists.freedesktop.org > Cc: dri-de...@lists.freedesktop.org > Signed-off-by: Lee Jones > --- > drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > index ae0a95c5f1d8c..0b4841f377e41 100644 > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > @@ -605,7 +605,7 @@ static void dm_crtc_high_irq(void *interrupt_params) > /** > * dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0 > for > * DCN generation ASICs > - * @interrupt params - interrupt parameters > + * @interrupt_params: interrupt parameters > * > * Used to set crc window/read out crc value at vertical line 0 position > */ > -- > 2.31.1 > ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 19/34] drm/amd/amdgpu/amdgpu_device: Make local function static
Applied. Thanks!
On Wed, May 26, 2021 at 4:48 AM Lee Jones wrote:
>
> Fixes the following W=1 kernel build warning(s):
>
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:4624:6: warning: no previous
> prototype for ‘amdgpu_device_recheck_guilty_jobs’ [-Wmissing-prototypes]
>
> Cc: Alex Deucher
> Cc: "Christian König"
> Cc: David Airlie
> Cc: Daniel Vetter
> Cc: Sumit Semwal
> Cc: amd-gfx@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org
> Cc: linux-me...@vger.kernel.org
> Cc: linaro-mm-...@lists.linaro.org
> Signed-off-by: Lee Jones
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 4a040f89ca5aa..f15e180762d2e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -4692,7 +4692,7 @@ static int amdgpu_device_suspend_display_audio(struct
> amdgpu_device *adev)
> return 0;
> }
>
> -void amdgpu_device_recheck_guilty_jobs(
> +static void amdgpu_device_recheck_guilty_jobs(
> struct amdgpu_device *adev, struct list_head *device_list_handle,
> struct amdgpu_reset_context *reset_context)
> {
> --
> 2.31.1
>
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Re: [PATCH 18/34] drm/amd/display/dc/dce/dce_mem_input: Remove duplicate initialisation of GRPH_CONTROL__GRPH_NUM_BANKS_{SHIFT, MASK
Applied. Thanks!
On Wed, May 26, 2021 at 4:48 AM Lee Jones wrote:
>
> Fixes the following W=1 kernel build warning(s):
>
> In file included from
> drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:29:
>
> drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dce/dce_6_0_sh_mask.h:7270:45:
> warning: initialized field overwritten [-Woverride-init]
> drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_mem_input.h:155:28: note:
> in expansion of macro ‘GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT’
> drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_mem_input.h:159:2: note: in
> expansion of macro ‘SFB’
> drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_mem_input.h:264:2: note: in
> expansion of macro ‘MI_GFX6_TILE_MASK_SH_LIST’
> drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:657:3: note:
> in expansion of macro ‘MI_DCE6_MASK_SH_LIST’
>
> drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dce/dce_6_0_sh_mask.h:7270:45:
> note: (near initialization for ‘mi_shifts.GRPH_NUM_BANKS’)
> drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_mem_input.h:155:28: note:
> in expansion of macro ‘GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT’
> drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_mem_input.h:159:2: note: in
> expansion of macro ‘SFB’
> drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_mem_input.h:264:2: note: in
> expansion of macro ‘MI_GFX6_TILE_MASK_SH_LIST’
> drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:657:3: note:
> in expansion of macro ‘MI_DCE6_MASK_SH_LIST’
>
> drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dce/dce_6_0_sh_mask.h:7269:43:
> warning: initialized field overwritten [-Woverride-init]
> drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_mem_input.h:155:28: note:
> in expansion of macro ‘GRPH_CONTROL__GRPH_NUM_BANKS_MASK’
> drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_mem_input.h:159:2: note: in
> expansion of macro ‘SFB’
> drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_mem_input.h:264:2: note: in
> expansion of macro ‘MI_GFX6_TILE_MASK_SH_LIST’
> drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:662:3: note:
> in expansion of macro ‘MI_DCE6_MASK_SH_LIST’
>
> drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dce/dce_6_0_sh_mask.h:7269:43:
> note: (near initialization for ‘mi_masks.GRPH_NUM_BANKS’)
> drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_mem_input.h:155:28: note:
> in expansion of macro ‘GRPH_CONTROL__GRPH_NUM_BANKS_MASK’
> drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_mem_input.h:159:2: note: in
> expansion of macro ‘SFB’
> drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_mem_input.h:264:2: note: in
> expansion of macro ‘MI_GFX6_TILE_MASK_SH_LIST’
> drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:662:3: note:
> in expansion of macro ‘MI_DCE6_MASK_SH_LIST’
>
> Cc: Harry Wentland
> Cc: Leo Li
> Cc: Alex Deucher
> Cc: "Christian König"
> Cc: David Airlie
> Cc: Daniel Vetter
> Cc: Mauro Rossi
> Cc: Lee Jones
> Cc: amd-gfx@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org
> Signed-off-by: Lee Jones
> ---
> drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
> b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
> index 9b1c4d56275a4..08a4c8d029d9f 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
> +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
> @@ -206,7 +206,6 @@ struct dce_mem_input_registers {
> SFB(blk, GRPH_ENABLE, GRPH_ENABLE, mask_sh),\
> SFB(blk, GRPH_CONTROL, GRPH_DEPTH, mask_sh),\
> SFB(blk, GRPH_CONTROL, GRPH_FORMAT, mask_sh),\
> - SFB(blk, GRPH_CONTROL, GRPH_NUM_BANKS, mask_sh),\
> SFB(blk, GRPH_X_START, GRPH_X_START, mask_sh),\
> SFB(blk, GRPH_Y_START, GRPH_Y_START, mask_sh),\
> SFB(blk, GRPH_X_END, GRPH_X_END, mask_sh),\
> --
> 2.31.1
>
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Re: [PATCH 17/34] drm/amd/display/dc/dce/dce_mem_input: Remove duplicate initialisation of GRPH_CONTROL__GRPH_NUM_BANKS_{SHIFT, MASK}
Applied. Thanks!
On Wed, May 26, 2021 at 4:48 AM Lee Jones wrote:
>
> Fixes the following W=1 kernel build warning(s):
>
> In file included from
> drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:29:
>
> drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dce/dce_6_0_sh_mask.h:7270:45:
> warning: initialized field overwritten [-Woverride-init]
> drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_mem_input.h:155:28: note:
> in expansion of macro ‘GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT’
> drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_mem_input.h:159:2: note: in
> expansion of macro ‘SFB’
> drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_mem_input.h:265:2: note: in
> expansion of macro ‘MI_GFX6_TILE_MASK_SH_LIST’
> drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:657:3: note:
> in expansion of macro ‘MI_DCE6_MASK_SH_LIST’
>
> drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dce/dce_6_0_sh_mask.h:7270:45:
> note: (near initialization for ‘mi_shifts.GRPH_NUM_BANKS’)
> drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_mem_input.h:155:28: note:
> in expansion of macro ‘GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT’
> drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_mem_input.h:159:2: note: in
> expansion of macro ‘SFB’
> drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_mem_input.h:265:2: note: in
> expansion of macro ‘MI_GFX6_TILE_MASK_SH_LIST’
> drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:657:3: note:
> in expansion of macro ‘MI_DCE6_MASK_SH_LIST’
>
> drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dce/dce_6_0_sh_mask.h:7269:43:
> warning: initialized field overwritten [-Woverride-init]
> drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_mem_input.h:155:28: note:
> in expansion of macro ‘GRPH_CONTROL__GRPH_NUM_BANKS_MASK’
> drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_mem_input.h:159:2: note: in
> expansion of macro ‘SFB’
> drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_mem_input.h:265:2: note: in
> expansion of macro ‘MI_GFX6_TILE_MASK_SH_LIST’
> drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:662:3: note:
> in expansion of macro ‘MI_DCE6_MASK_SH_LIST’
>
> drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dce/dce_6_0_sh_mask.h:7269:43:
> note: (near initialization for ‘mi_masks.GRPH_NUM_BANKS’)
> drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_mem_input.h:155:28: note:
> in expansion of macro ‘GRPH_CONTROL__GRPH_NUM_BANKS_MASK’
> drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_mem_input.h:159:2: note: in
> expansion of macro ‘SFB’
> drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_mem_input.h:265:2: note: in
> expansion of macro ‘MI_GFX6_TILE_MASK_SH_LIST’
> drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:662:3: note:
> in expansion of macro ‘MI_DCE6_MASK_SH_LIST’
>
> Cc: Harry Wentland
> Cc: Leo Li
> Cc: Alex Deucher
> Cc: "Christian König"
> Cc: David Airlie
> Cc: Daniel Vetter
> Cc: Mauro Rossi
> Cc: amd-gfx@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org
> Signed-off-by: Lee Jones
> ---
> drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
> b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
> index 23db5c72f07ed..9b1c4d56275a4 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
> +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
> @@ -181,7 +181,6 @@ struct dce_mem_input_registers {
> SFB(blk, GRPH_ENABLE, GRPH_ENABLE, mask_sh),\
> SFB(blk, GRPH_CONTROL, GRPH_DEPTH, mask_sh),\
> SFB(blk, GRPH_CONTROL, GRPH_FORMAT, mask_sh),\
> - SFB(blk, GRPH_CONTROL, GRPH_NUM_BANKS, mask_sh),\
> SFB(blk, GRPH_X_START, GRPH_X_START, mask_sh),\
> SFB(blk, GRPH_Y_START, GRPH_Y_START, mask_sh),\
> SFB(blk, GRPH_X_END, GRPH_X_END, mask_sh),\
> --
> 2.31.1
>
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Re: [PATCH 16/34] drm/amd/display/dc/dce/dce_transform: Remove superfluous re-initialisation of DCFE_MEM_LIGHT_SLEEP_CNTL,
On Wed, May 26, 2021 at 4:48 AM Lee Jones wrote: > > Fixes the following W=1 kernel build warning(s): > > drivers/gpu/drm/amd/amdgpu/../display/modules/hdcp/hdcp_psp.c:374:22: > warning: no previous prototype for ‘mod_hdcp_hdcp1_get_link_encryption_status’ > In file included from > drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:28: > drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dce/dce_6_0_d.h:568:43: > warning: initialized field overwritten [-Woverride-init] > drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:157:14: > note: in expansion of macro ‘mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL’ > drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_transform.h:170:2: note: in > expansion of macro ‘SRI’ > drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:183:3: note: > in expansion of macro ‘XFM_COMMON_REG_LIST_DCE60’ > drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:187:3: note: > in expansion of macro ‘transform_regs’ > drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dce/dce_6_0_d.h:568:43: note: > (near initialization for ‘xfm_regs[0].DCFE_MEM_LIGHT_SLEEP_CNTL’) > drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:157:14: > note: in expansion of macro ‘mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL’ > drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_transform.h:170:2: note: in > expansion of macro ‘SRI’ > drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:183:3: note: > in expansion of macro ‘XFM_COMMON_REG_LIST_DCE60’ > drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:187:3: note: > in expansion of macro ‘transform_regs’ > drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dce/dce_6_0_d.h:645:43: > warning: initialized field overwritten [-Woverride-init] > > Cc: Harry Wentland > Cc: Leo Li > Cc: Alex Deucher > Cc: "Christian König" > Cc: David Airlie > Cc: Daniel Vetter > Cc: Mauro Rossi > Cc: amd-gfx@lists.freedesktop.org > Cc: dri-de...@lists.freedesktop.org > Signed-off-by: Lee Jones > --- > drivers/gpu/drm/amd/display/dc/dce/dce_transform.h | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h > b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h > index cbce194ec7b82..e98b5d4141739 100644 > --- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h > +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h > @@ -166,8 +166,7 @@ > SRI(SCL_F_SHARP_CONTROL, SCL, id) > > #define XFM_COMMON_REG_LIST_DCE60(id) \ > - XFM_COMMON_REG_LIST_DCE60_BASE(id), \ > - SRI(DCFE_MEM_LIGHT_SLEEP_CNTL, CRTC, id) > + XFM_COMMON_REG_LIST_DCE60_BASE(id) I believe this should be kept and it should be removed from XFM_COMMON_REG_LIST_DCE60_BASE(). Alex > #endif > > #define XFM_SF(reg_name, field_name, post_fix)\ > -- > 2.31.1 > ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 15/34] drm/amd/display/dc/dce110/dce110_hw_sequencer: Include our own header
Applied. Thanks! On Wed, May 26, 2021 at 4:48 AM Lee Jones wrote: > > Fixes the following W=1 kernel build warning(s): > > drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_hw_sequencer.c:927:6: > warning: no previous prototype for ‘dce110_edp_wait_for_T12’ > [-Wmissing-prototypes] > > Cc: Harry Wentland > Cc: Leo Li > Cc: Alex Deucher > Cc: "Christian König" > Cc: David Airlie > Cc: Daniel Vetter > Cc: amd-gfx@lists.freedesktop.org > Cc: dri-de...@lists.freedesktop.org > Signed-off-by: Lee Jones > --- > drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c > b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c > index 5ddeee96bf235..9219db79f32b6 100644 > --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c > +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c > @@ -63,6 +63,8 @@ > > #include "atomfirmware.h" > > +#include "dce110_hw_sequencer.h" > + > #define GAMMA_HW_POINTS_NUM 256 > > /* > -- > 2.31.1 > ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 14/34] drm/amd/display/dc/gpio/gpio_service: Pass around correct dce_{version, environment} types
Applied. Thanks!
On Wed, May 26, 2021 at 4:48 AM Lee Jones wrote:
>
> Fixes the following W=1 kernel build warning(s):
>
> drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/gpio_service.c: In function
> ‘dal_gpio_service_create’:
> drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/gpio_service.c:71:4: warning:
> implicit conversion from ‘enum dce_version’ to ‘enum dce_environment’
> [-Wenum-conversion]
> drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/gpio_service.c:77:4: warning:
> implicit conversion from ‘enum dce_version’ to ‘enum dce_environment’
> [-Wenum-conversion]
>
> Cc: Harry Wentland
> Cc: Leo Li
> Cc: Alex Deucher
> Cc: "Christian König"
> Cc: David Airlie
> Cc: Daniel Vetter
> Cc: amd-gfx@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org
> Signed-off-by: Lee Jones
> ---
> drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c | 12 ++--
> .../drm/amd/display/include/gpio_service_interface.h | 4 ++--
> 2 files changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c
> b/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c
> index 92280cc05e2db..dae8e489c8cf4 100644
> --- a/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c
> +++ b/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c
> @@ -53,8 +53,8 @@
> */
>
> struct gpio_service *dal_gpio_service_create(
> - enum dce_version dce_version_major,
> - enum dce_version dce_version_minor,
> + enum dce_version dce_version,
> + enum dce_environment dce_environment,
> struct dc_context *ctx)
> {
> struct gpio_service *service;
> @@ -67,14 +67,14 @@ struct gpio_service *dal_gpio_service_create(
> return NULL;
> }
>
> - if (!dal_hw_translate_init(>translate, dce_version_major,
> - dce_version_minor)) {
> + if (!dal_hw_translate_init(>translate, dce_version,
> + dce_environment)) {
> BREAK_TO_DEBUGGER();
> goto failure_1;
> }
>
> - if (!dal_hw_factory_init(>factory, dce_version_major,
> - dce_version_minor)) {
> + if (!dal_hw_factory_init(>factory, dce_version,
> + dce_environment)) {
> BREAK_TO_DEBUGGER();
> goto failure_1;
> }
> diff --git a/drivers/gpu/drm/amd/display/include/gpio_service_interface.h
> b/drivers/gpu/drm/amd/display/include/gpio_service_interface.h
> index 9c55d247227ea..7e3240e73c1fc 100644
> --- a/drivers/gpu/drm/amd/display/include/gpio_service_interface.h
> +++ b/drivers/gpu/drm/amd/display/include/gpio_service_interface.h
> @@ -42,8 +42,8 @@ void dal_gpio_destroy(
> struct gpio **ptr);
>
> struct gpio_service *dal_gpio_service_create(
> - enum dce_version dce_version_major,
> - enum dce_version dce_version_minor,
> + enum dce_version dce_version,
> + enum dce_environment dce_environment,
> struct dc_context *ctx);
>
> struct gpio *dal_gpio_service_create_irq(
> --
> 2.31.1
>
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RE: [PATCH] drm/amdgpu/swsmu/aldebaran: fix check in is_dpm_running
[Public]
Reviewed-by: Lijo Lazar
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: Thursday, May 27, 2021 9:20 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Lee Jones
Subject: [PATCH] drm/amdgpu/swsmu/aldebaran: fix check in is_dpm_running
If smu_cmn_get_enabled_mask() fails, return false to be consistent with other
asics.
Signed-off-by: Alex Deucher
Cc: Lee Jones
---
drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
index d6ce665baaf3..7a1abb3d6a7a 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
@@ -1368,10 +1368,13 @@ static int aldebaran_usr_edit_dpm_table(struct
smu_context *smu, enum PP_OD_DPM_
static bool aldebaran_is_dpm_running(struct smu_context *smu) {
- int ret = 0;
+ int ret;
uint32_t feature_mask[2];
unsigned long feature_enabled;
+
ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
+ if (ret)
+ return false;
feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
((uint64_t)feature_mask[1] << 32));
return !!(feature_enabled & SMC_DPM_FEATURE);
--
2.31.1
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Re: [PATCH 13/34] drm/amd/display/dc/dce/dmub_outbox: Convert over to kernel-doc
Applied. Thanks!
On Wed, May 26, 2021 at 4:48 AM Lee Jones wrote:
>
> Fixes the following W=1 kernel build warning(s):
>
> drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dmub_outbox.c:30: warning:
> Cannot understand
> *
>
> Cc: Harry Wentland
> Cc: Leo Li
> Cc: Alex Deucher
> Cc: "Christian König"
> Cc: David Airlie
> Cc: Daniel Vetter
> Cc: Rodrigo Siqueira
> Cc: Meenakshikumar Somasundaram
> Cc: Jun Lei
> Cc: amd-gfx@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org
> Signed-off-by: Lee Jones
> ---
> .../gpu/drm/amd/display/dc/dce/dmub_outbox.c| 17 -
> 1 file changed, 4 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_outbox.c
> b/drivers/gpu/drm/amd/display/dc/dce/dmub_outbox.c
> index 295596d1f47f2..faad8555ddbb6 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_outbox.c
> +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_outbox.c
> @@ -27,19 +27,10 @@
> #include "dmub/inc/dmub_cmd.h"
>
> /**
> -
> *
> - * Function: dmub_enable_outbox_notification
> - *
> - * @brief
> - * Sends inbox cmd to dmub to enable outbox1 messages with
> interrupt.
> - * Dmub sends outbox1 message and triggers outbox1 interrupt.
> - *
> - * @param
> - * [in] dc: dc structure
> - *
> - * @return
> - * None
> -
> *
> + * dmub_enable_outbox_notification - Sends inbox cmd to dmub to enable
> outbox1
> + *messages with interrupt. Dmub sends
> outbox1
> + *message and triggers outbox1 interrupt.
> + * @dc: dc structure
> */
> void dmub_enable_outbox_notification(struct dc *dc)
> {
> --
> 2.31.1
>
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Re: [PATCH 12/34] drm/amd/display/amdgpu_dm/amdgpu_dm: Functions must directly follow their headers
Applied. Thanks!
On Wed, May 26, 2021 at 4:47 AM Lee Jones wrote:
>
> Fixes the following W=1 kernel build warning(s):
>
> drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:608: warning:
> Function parameter or member 'interrupt_params' not described in
> 'dm_dcn_vertical_interrupt0_high_irq'
>
> Cc: Harry Wentland
> Cc: Leo Li
> Cc: Alex Deucher
> Cc: "Christian König"
> Cc: David Airlie
> Cc: Daniel Vetter
> Cc: amd-gfx@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org
> Signed-off-by: Lee Jones
> ---
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index b4e95d3ff3b88..ae0a95c5f1d8c 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -601,6 +601,7 @@ static void dm_crtc_high_irq(void *interrupt_params)
> }
>
> #if defined(CONFIG_DRM_AMD_DC_DCN)
> +#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
> /**
> * dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0
> for
> * DCN generation ASICs
> @@ -608,7 +609,6 @@ static void dm_crtc_high_irq(void *interrupt_params)
> *
> * Used to set crc window/read out crc value at vertical line 0 position
> */
> -#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
> static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params)
> {
> struct common_irq_params *irq_params = interrupt_params;
> --
> 2.31.1
>
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Re: [PATCH 10/34] drm/amd/display/dc/bios/bios_parser: Fix formatting and misnaming issues
Applied. Thanks! On Wed, May 26, 2021 at 4:47 AM Lee Jones wrote: > > Fixes the following W=1 kernel build warning(s): > > drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser.c:997: warning: > expecting prototype for get_ss_info_from_table(). Prototype was for > get_ss_info_from_tbl() instead > drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser.c:1562: warning: > expecting prototype for BiosParserObject(). Prototype was for > bios_parser_get_ss_entry_number() instead > drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser.c:1739: warning: > expecting prototype for > get_ss_entry_number_from_internal_ss_info_table_V3_1(). Prototype was for > get_ss_entry_number_from_internal_ss_info_tbl_V3_1() instead > > Cc: Harry Wentland > Cc: Leo Li > Cc: Alex Deucher > Cc: "Christian König" > Cc: David Airlie > Cc: Daniel Vetter > Cc: Lee Jones > Cc: amd-gfx@lists.freedesktop.org > Cc: dri-de...@lists.freedesktop.org > Signed-off-by: Lee Jones > --- > drivers/gpu/drm/amd/display/dc/bios/bios_parser.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c > b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c > index c67d21a5ee52f..9b8ea6e9a2b96 100644 > --- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c > +++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c > @@ -979,7 +979,7 @@ static enum bp_result > get_ss_info_from_internal_ss_info_tbl_V2_1( > struct spread_spectrum_info *info); > > /** > - * get_ss_info_from_table > + * get_ss_info_from_tbl > * Get spread sprectrum information from the ASIC_InternalSS_Info Ver 2.1 or > * SS_Info table from the VBIOS > * There can not be more than 1 entry for ASIC_InternalSS_Info Ver 2.1 or > @@ -1548,7 +1548,7 @@ static uint32_t get_ss_entry_number_from_ss_info_tbl( > uint32_t id); > > /** > - * BiosParserObject::GetNumberofSpreadSpectrumEntry > + * bios_parser_get_ss_entry_number > * Get Number of SpreadSpectrum Entry from the ASIC_InternalSS_Info table > from > * the VBIOS that match the SSid (to be converted from signal) > * > @@ -1725,7 +1725,7 @@ static uint32_t > get_ss_entry_number_from_internal_ss_info_tbl_v2_1( > return 0; > } > /** > - * get_ss_entry_number_from_internal_ss_info_table_V3_1 > + * get_ss_entry_number_from_internal_ss_info_tbl_V3_1 > * Get Number of SpreadSpectrum Entry from the ASIC_InternalSS_Info table of > * the VBIOS that matches id > * > -- > 2.31.1 > ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 09/34] drm/amd/display/dc/bios/command_table_helper2: Fix function name 'dal_cmd_table_helper_transmitter_bp_to_atom2()'
Applied. Thanks! On Wed, May 26, 2021 at 4:48 AM Lee Jones wrote: > > Fixes the following W=1 kernel build warning(s): > > drivers/gpu/drm/amd/amdgpu/../display/dc/bios/command_table_helper2.c:141: > warning: expecting prototype for translate_transmitter_bp_to_atom2(). > Prototype was for dal_cmd_table_helper_transmitter_bp_to_atom2() instead > > Cc: Harry Wentland > Cc: Leo Li > Cc: Alex Deucher > Cc: "Christian König" > Cc: David Airlie > Cc: Daniel Vetter > Cc: amd-gfx@lists.freedesktop.org > Cc: dri-de...@lists.freedesktop.org > Signed-off-by: Lee Jones > --- > drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c > b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c > index 00706b072b5f8..6d2fb112ad9f9 100644 > --- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c > +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c > @@ -129,7 +129,7 @@ bool dal_cmd_table_helper_controller_id_to_atom2( > } > > /** > - * translate_transmitter_bp_to_atom2 - Translate the Transmitter to the > + * dal_cmd_table_helper_transmitter_bp_to_atom2 - Translate the Transmitter > to the > * corresponding ATOM BIOS value > * @t: transmitter > * returns: digitalTransmitter > -- > 2.31.1 > ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 08/34] drm/amd/display/dc/bios/command_table_helper: Fix function name for 'dal_cmd_table_helper_transmitter_bp_to_atom()'
Applied. Thanks! On Wed, May 26, 2021 at 4:48 AM Lee Jones wrote: > > Fixes the following W=1 kernel build warning(s): > > drivers/gpu/drm/amd/amdgpu/../display/dc/bios/command_table_helper.c:127: > warning: expecting prototype for translate_transmitter_bp_to_atom(). > Prototype was for dal_cmd_table_helper_transmitter_bp_to_atom() instead > > Cc: Harry Wentland > Cc: Leo Li > Cc: Alex Deucher > Cc: "Christian König" > Cc: David Airlie > Cc: Daniel Vetter > Cc: Lee Jones > Cc: amd-gfx@lists.freedesktop.org > Cc: dri-de...@lists.freedesktop.org > Signed-off-by: Lee Jones > --- > drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c > b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c > index 5b77251e05909..e317a36151477 100644 > --- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c > +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c > @@ -114,7 +114,7 @@ bool dal_cmd_table_helper_controller_id_to_atom( > } > > /** > - * translate_transmitter_bp_to_atom - Translate the Transmitter to the > + * dal_cmd_table_helper_transmitter_bp_to_atom - Translate the Transmitter > to the > *corresponding ATOM BIOS value > * @t: transmitter > * returns: output digitalTransmitter > -- > 2.31.1 > ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 07/34] drm/amd/pm/powerplay/hwmgr/vega20_hwmgr: Provide function name 'vega20_init_smc_table()'
Applied. Thanks! On Wed, May 26, 2021 at 4:47 AM Lee Jones wrote: > > Fixes the following W=1 kernel build warning(s): > > drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega20_hwmgr.c:781: > warning: expecting prototype for Initializes the SMC table and uploads it(). > Prototype was for vega20_init_smc_table() instead > > Cc: Evan Quan > Cc: Alex Deucher > Cc: "Christian König" > Cc: David Airlie > Cc: Daniel Vetter > Cc: amd-gfx@lists.freedesktop.org > Cc: dri-de...@lists.freedesktop.org > Signed-off-by: Lee Jones > --- > drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c > b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c > index d3177a534fdf0..0791309586c58 100644 > --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c > +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c > @@ -772,7 +772,7 @@ static int vega20_setup_default_dpm_tables(struct > pp_hwmgr *hwmgr) > } > > /** > - * Initializes the SMC table and uploads it > + * vega20_init_smc_table - Initializes the SMC table and uploads it > * > * @hwmgr: the address of the powerplay hardware manager. > * return: always 0 > -- > 2.31.1 > ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 06/34] drm/amd/pm/powerplay/hwmgr/vega10_hwmgr: Kernel-doc headers must contain function names
Applied. Thanks! On Wed, May 26, 2021 at 4:47 AM Lee Jones wrote: > > Fixes the following W=1 kernel build warning(s): > > drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_hwmgr.c:547: > warning: This comment starts with '/**', but isn't a kernel-doc comment. > Refer Documentation/doc-guide/kernel-doc.rst > drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_hwmgr.c:603: > warning: This comment starts with '/**', but isn't a kernel-doc comment. > Refer Documentation/doc-guide/kernel-doc.rst > drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_hwmgr.c:629: > warning: This comment starts with '/**', but isn't a kernel-doc comment. > Refer Documentation/doc-guide/kernel-doc.rst > drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_hwmgr.c:1006: > warning: This comment starts with '/**', but isn't a kernel-doc comment. > Refer Documentation/doc-guide/kernel-doc.rst > drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_hwmgr.c:1155: > warning: This comment starts with '/**', but isn't a kernel-doc comment. > Refer Documentation/doc-guide/kernel-doc.rst > drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_hwmgr.c:1608: > warning: expecting prototype for Populates single SMC GFXSCLK structure using > the provided engine clock(). Prototype was for > vega10_populate_single_gfx_level() instead > drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_hwmgr.c:1663: > warning: This comment starts with '/**', but isn't a kernel-doc comment. > Refer Documentation/doc-guide/kernel-doc.rst > drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_hwmgr.c:1713: > warning: This comment starts with '/**', but isn't a kernel-doc comment. > Refer Documentation/doc-guide/kernel-doc.rst > drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_hwmgr.c:1862: > warning: This comment starts with '/**', but isn't a kernel-doc comment. > Refer Documentation/doc-guide/kernel-doc.rst > drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_hwmgr.c:2546: > warning: expecting prototype for Initializes the SMC table and uploads it(). > Prototype was for vega10_init_smc_table() instead > drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_hwmgr.c:2922: > warning: This comment starts with '/**', but isn't a kernel-doc comment. > Refer Documentation/doc-guide/kernel-doc.rst > > Cc: Evan Quan > Cc: Alex Deucher > Cc: "Christian König" > Cc: David Airlie > Cc: Daniel Vetter > Cc: amd-gfx@lists.freedesktop.org > Cc: dri-de...@lists.freedesktop.org > Signed-off-by: Lee Jones > --- > .../drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c | 26 +++ > 1 file changed, 15 insertions(+), 11 deletions(-) > > diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c > b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c > index 31c61ac3bd5e1..25979106fd255 100644 > --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c > +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c > @@ -544,7 +544,7 @@ static int vega10_get_socclk_for_voltage_evv(struct > pp_hwmgr *hwmgr, > > #define ATOM_VIRTUAL_VOLTAGE_ID0 0xff01 > /** > - * Get Leakage VDDC based on leakage ID. > + * vega10_get_evv_voltages - Get Leakage VDDC based on leakage ID. > * > * @hwmgr: the address of the powerplay hardware manager. > * return: always 0. > @@ -600,7 +600,7 @@ static int vega10_get_evv_voltages(struct pp_hwmgr *hwmgr) > } > > /** > - * Change virtual leakage voltage to actual value. > + * vega10_patch_with_vdd_leakage - Change virtual leakage voltage to actual > value. > * > * @hwmgr: the address of the powerplay hardware manager. > * @voltage: pointer to changing voltage > @@ -626,7 +626,7 @@ static void vega10_patch_with_vdd_leakage(struct pp_hwmgr > *hwmgr, > } > > /** > - * Patch voltage lookup table by EVV leakages. > + * vega10_patch_lookup_table_with_leakage - Patch voltage lookup table by > EVV leakages. > * > * @hwmgr: the address of the powerplay hardware manager. > * @lookup_table: pointer to voltage lookup table > @@ -1003,7 +1003,7 @@ static int vega10_setup_asic_task(struct pp_hwmgr > *hwmgr) > } > > /** > - * Remove repeated voltage values and create table with unique values. > + * vega10_trim_voltage_table - Remove repeated voltage values and create > table with unique values. > * > * @hwmgr: the address of the powerplay hardware manager. > * @vol_table: the pointer to changing voltage table > @@ -1152,7 +1152,7 @@ static void > vega10_trim_voltage_table_to_fit_state_table( > } > > /** > - * Create Voltage Tables. > + * vega10_construct_voltage_tables - Create Voltage Tables. > * > * @hwmgr: the address of the powerplay hardware manager. > * return: always 0 > @@ -1595,7 +1595,8 @@ static int vega10_populate_smc_link_levels(struct > pp_hwmgr *hwmgr) > } > > /** > - * Populates single SMC GFXSCLK structure using the provided engine clock > + *
Re: [PATCH 05/34] drm/amd/pm/powerplay/hwmgr/vega12_hwmgr: Provide 'vega12_init_smc_table()' function name
Applied. Thanks! On Wed, May 26, 2021 at 4:47 AM Lee Jones wrote: > > Fixes the following W=1 kernel build warning(s): > > drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega12_hwmgr.c:812: > warning: expecting prototype for Initializes the SMC table and uploads it(). > Prototype was for vega12_init_smc_table() instead > > Cc: Evan Quan > Cc: Alex Deucher > Cc: "Christian König" > Cc: David Airlie > Cc: Daniel Vetter > Cc: amd-gfx@lists.freedesktop.org > Cc: dri-de...@lists.freedesktop.org > Signed-off-by: Lee Jones > --- > drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c > b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c > index 1a097e608808e..29e0d1d4035ad 100644 > --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c > +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c > @@ -803,7 +803,7 @@ static int vega12_save_default_power_profile(struct > pp_hwmgr *hwmgr) > #endif > > /** > - * Initializes the SMC table and uploads it > + * vega12_init_smc_table - Initializes the SMC table and uploads it > * > * @hwmgr: the address of the powerplay hardware manager. > * return: always 0 > -- > 2.31.1 > ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 04/34] drm/amd/pm/powerplay/hwmgr/vega12_thermal: Provide function name
Applied. Thanks! On Wed, May 26, 2021 at 4:47 AM Lee Jones wrote: > > Fixes the following W=1 kernel build warning(s): > > drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega12_thermal.c:171: > warning: expecting prototype for Set the requested temperature range for high > and low alert signals(). Prototype was for > vega12_thermal_set_temperature_range() instead > > Cc: Evan Quan > Cc: Alex Deucher > Cc: "Christian König" > Cc: David Airlie > Cc: Daniel Vetter > Cc: amd-gfx@lists.freedesktop.org > Cc: dri-de...@lists.freedesktop.org > Signed-off-by: Lee Jones > --- > drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c > b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c > index 0dc16f25a463b..ed3dff0b52d21 100644 > --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c > +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c > @@ -159,7 +159,8 @@ int vega12_thermal_get_temperature(struct pp_hwmgr *hwmgr) > } > > /** > - * Set the requested temperature range for high and low alert signals > + * vega12_thermal_set_temperature_range - Set the requested temperature range > + *for high and low alert signals > * > * @hwmgr: The address of the hardware manager. > * @range: Temperature range to be programmed for > -- > 2.31.1 > ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 03/34] drm/amd/pm/powerplay/hwmgr/smu7_thermal: Provide function name for 'smu7_fan_ctrl_set_default_mode()'
Applied. Thanks!
On Wed, May 26, 2021 at 4:47 AM Lee Jones wrote:
>
> Fixes the following W=1 kernel build warning(s):
>
> drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu7_thermal.c:132:
> warning: This comment starts with '/**', but isn't a kernel-doc comment.
> Refer Documentation/doc-guide/kernel-doc.rst
>
> Cc: Evan Quan
> Cc: Alex Deucher
> Cc: "Christian König"
> Cc: David Airlie
> Cc: Daniel Vetter
> Cc: amd-gfx@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org
> Signed-off-by: Lee Jones
> ---
> drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c
> b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c
> index 0d38d4206848a..6cfe148ed45bb 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c
> @@ -129,10 +129,10 @@ int smu7_fan_ctrl_set_static_mode(struct pp_hwmgr
> *hwmgr, uint32_t mode)
> }
>
> /**
> -* Reset Fan Speed Control to default mode.
> -* @hwmgr: the address of the powerplay hardware manager.
> -* Exception: Should always succeed.
> -*/
> + * smu7_fan_ctrl_set_default_mode - Reset Fan Speed Control to default mode.
> + * @hwmgr: the address of the powerplay hardware manager.
> + * Exception: Should always succeed.
> + */
> int smu7_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr)
> {
> if (!hwmgr->fan_ctrl_is_in_default_mode) {
> --
> 2.31.1
>
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[PATCH] drm/amdgpu/swsmu/aldebaran: fix check in is_dpm_running
If smu_cmn_get_enabled_mask() fails, return false to be
consistent with other asics.
Signed-off-by: Alex Deucher
Cc: Lee Jones
---
drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
index d6ce665baaf3..7a1abb3d6a7a 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
@@ -1368,10 +1368,13 @@ static int aldebaran_usr_edit_dpm_table(struct
smu_context *smu, enum PP_OD_DPM_
static bool aldebaran_is_dpm_running(struct smu_context *smu)
{
- int ret = 0;
+ int ret;
uint32_t feature_mask[2];
unsigned long feature_enabled;
+
ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
+ if (ret)
+ return false;
feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
((uint64_t)feature_mask[1] << 32));
return !!(feature_enabled & SMC_DPM_FEATURE);
--
2.31.1
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Re: [PATCH 02/34] drm/amd/pm/swsmu/smu13/aldebaran_ppt: Remove unused variable 'ret'
This should be checked. Will send out a patch momentarily.
Thanks,
Alex
On Wed, May 26, 2021 at 4:47 AM Lee Jones wrote:
>
> Fixes the following W=1 kernel build warning(s):
>
> drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/aldebaran_ppt.c: In function
> ‘aldebaran_is_dpm_running’:
> drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/aldebaran_ppt.c:1260:6:
> warning: variable ‘ret’ set but not used [-Wunused-but-set-variable]
>
> Cc: Alex Deucher
> Cc: "Christian König"
> Cc: David Airlie
> Cc: Daniel Vetter
> Cc: amd-gfx@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org
> Signed-off-by: Lee Jones
> ---
> drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
> index d6ce665baaf3b..d077e211017a9 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
> @@ -1368,10 +1368,9 @@ static int aldebaran_usr_edit_dpm_table(struct
> smu_context *smu, enum PP_OD_DPM_
>
> static bool aldebaran_is_dpm_running(struct smu_context *smu)
> {
> - int ret = 0;
> uint32_t feature_mask[2];
> unsigned long feature_enabled;
> - ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
> + smu_cmn_get_enabled_mask(smu, feature_mask, 2);
> feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
> ((uint64_t)feature_mask[1] << 32));
> return !!(feature_enabled & SMC_DPM_FEATURE);
> --
> 2.31.1
>
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Re: [PATCH 01/34] drm/amd/pm/inc/smu_v13_0: Move table into the only source file that uses it
Applied. Thanks!
On Wed, May 26, 2021 at 4:47 AM Lee Jones wrote:
>
> Fixes the following W=1 kernel build warning(s):
>
> drivers/gpu/drm/amd/amdgpu/../pm/inc/smu_v13_0.h:54:43: warning:
> ‘smu13_thermal_policy’ defined but not used [-Wunused-const-variable=]
>
> Cc: Alex Deucher
> Cc: "Christian König"
> Cc: David Airlie
> Cc: Daniel Vetter
> Cc: Kevin Wang
> Cc: amd-gfx@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org
> Signed-off-by: Lee Jones
> ---
> drivers/gpu/drm/amd/pm/inc/smu_v13_0.h | 6 --
> drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c | 6 ++
> 2 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v13_0.h
> b/drivers/gpu/drm/amd/pm/inc/smu_v13_0.h
> index 1687709507b3d..6119a36b2cba0 100644
> --- a/drivers/gpu/drm/amd/pm/inc/smu_v13_0.h
> +++ b/drivers/gpu/drm/amd/pm/inc/smu_v13_0.h
> @@ -51,12 +51,6 @@
> #define CTF_OFFSET_HOTSPOT 5
> #define CTF_OFFSET_MEM 5
>
> -static const struct smu_temperature_range smu13_thermal_policy[] =
> -{
> - {-273150, 99000, 99000, -273150, 99000, 99000, -273150, 99000,
> 99000},
> - { 12, 12, 12, 12, 12, 12, 12, 12,
> 12},
> -};
> -
> struct smu_13_0_max_sustainable_clocks {
> uint32_t display_clock;
> uint32_t phy_clock;
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
> index d62cc6bb1a305..d6ce665baaf3b 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
> @@ -78,6 +78,12 @@
>
> #define smnPCIE_ESM_CTRL 0x111003D0
>
> +static const struct smu_temperature_range smu13_thermal_policy[] =
> +{
> + {-273150, 99000, 99000, -273150, 99000, 99000, -273150, 99000,
> 99000},
> + { 12, 12, 12, 12, 12, 12, 12, 12,
> 12},
> +};
> +
> static const struct cmn2asic_msg_mapping
> aldebaran_message_map[SMU_MSG_MAX_COUNT] = {
> MSG_MAP(TestMessage, PPSMC_MSG_TestMessage,
> 0),
> MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion,
> 1),
> --
> 2.31.1
>
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[pull] amdgpu, amdkfd drm-fixes-5.13
Hi Dave, Daniel, Fixes for 5.13. The following changes since commit a2b4785f01280a4291edb9fda69032fc2e4bfd3f: drm/amdgpu: stop touching sched.ready in the backend (2021-05-19 18:07:43 -0400) are available in the Git repository at: https://gitlab.freedesktop.org/agd5f/linux.git tags/amd-drm-fixes-5.13-2021-05-26 for you to fetch changes up to 20ebbfd22f8115a1e4f60d3d289f66be4d47f1ec: drm/amdgpu/jpeg3: add cancel_delayed_work_sync before power gate (2021-05-20 17:04:58 -0400) amd-drm-fixes-5.13-2021-05-26: amdgpu: - MultiGPU fan fix - VCN powergating fixes amdkfd: - Fix SDMA register offset error Evan Quan (1): drm/amd/pm: correct MGpuFanBoost setting James Zhu (7): drm/amdgpu/vcn1: add cancel_delayed_work_sync before power gate drm/amdgpu/vcn2.0: add cancel_delayed_work_sync before power gate drm/amdgpu/vcn2.5: add cancel_delayed_work_sync before power gate drm/amdgpu/vcn3: add cancel_delayed_work_sync before power gate drm/amdgpu/jpeg2.0: add cancel_delayed_work_sync before power gate drm/amdgpu/jpeg2.5: add cancel_delayed_work_sync before power gate drm/amdgpu/jpeg3: add cancel_delayed_work_sync before power gate Kevin Wang (1): drm/amdkfd: correct sienna_cichlid SDMA RLC register offset error drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c| 12 ++-- drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 2 ++ drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 6 +- drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 2 ++ drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 2 ++ drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 5 ++--- drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 9 + drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 10 ++ 10 files changed, 42 insertions(+), 14 deletions(-) ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 0/4] drm: Finally retire struct drm_format_name_buf
Acked-by: Alex Deucher for the amdgpu changes. On Wed, May 26, 2021 at 3:21 PM Thomas Zimmermann wrote: > > ping for further a-bs / r-bs > > Am 16.05.21 um 14:13 schrieb Thomas Zimmermann: > > This is a cleanup patchset to remove drm_format_name_buf et al. There > > are two instances in drivers that need to be replaced with the %4cc > > printk format modifier. Patch 3 was left over back from an earlier > > patchset. [1] Patch 4 removes struct drm_format_name_buf. > > > > I built-tested with drm-tip. The patchsetcan be mered through drm-misc. > > > > [1] > > https://lore.kernel.org/dri-devel/20210216155723.17109-1-sakari.ai...@linux.intel.com/ > > > > Sakari Ailus (1): > >drm: Remove drm_get_format_name() > > > > Thomas Zimmermann (3): > >drm/amdgpu: Use %p4cc to print 4CC format > >drm/simpledrm: Use %p4cc to print 4CC format > >drm/fourcc: Remove struct drm_format_buf_name > > > > drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 7 ++ > > drivers/gpu/drm/drm_fourcc.c| 25 - > > drivers/gpu/drm/tiny/simpledrm.c| 6 ++--- > > include/drm/drm_fourcc.h| 9 > > 4 files changed, 4 insertions(+), 43 deletions(-) > > > > -- > > 2.31.1 > > > > -- > Thomas Zimmermann > Graphics Driver Developer > SUSE Software Solutions Germany GmbH > Maxfeldstr. 5, 90409 Nürnberg, Germany > (HRB 36809, AG Nürnberg) > Geschäftsführer: Felix Imendörffer > ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 2/2] drm/amdgpu: stop bookkeeping of temporary GTT allocation
To improve buffer migration performace, stop bookkeeping of
temporary GTT allocation, including allocation for BO evicted
from VRAM and bounce buffer.
Signed-off-by: Lang Yu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 16 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 4 +++-
2 files changed, 13 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
index 8860545344c7..32fedd495c7f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
@@ -111,14 +111,15 @@ static int amdgpu_gtt_mgr_new(struct ttm_resource_manager
*man,
struct amdgpu_gtt_node *node;
int r;
- spin_lock(>lock);
- if ((>mem == mem || tbo->mem.mem_type != TTM_PL_TT) &&
- atomic64_read(>available) < mem->num_pages) {
+ if (!(mem->placement & TTM_PL_FLAG_TEMPORARY)) {
+ spin_lock(>lock);
+ if (atomic64_read(>available) < mem->num_pages) {
+ spin_unlock(>lock);
+ return -ENOSPC;
+ }
+ atomic64_sub(mem->num_pages, >available);
spin_unlock(>lock);
- return -ENOSPC;
}
- atomic64_sub(mem->num_pages, >available);
- spin_unlock(>lock);
if (!place->lpfn) {
mem->mm_node = NULL;
@@ -178,6 +179,9 @@ static void amdgpu_gtt_mgr_del(struct ttm_resource_manager
*man,
kfree(node);
}
+ if (mem->placement & TTM_PL_FLAG_TEMPORARY)
+ return;
+
atomic64_add(mem->num_pages, >available);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index c0aef327292a..129d39392859 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -152,9 +152,11 @@ static void amdgpu_evict_flags(struct ttm_buffer_object
*bo,
abo->placements[0].lpfn = 0;
abo->placement.busy_placement = >placements[1];
abo->placement.num_busy_placement = 1;
+ abo->placements[1].flags |= TTM_PL_FLAG_TEMPORARY;
} else {
/* Move to GTT memory */
amdgpu_bo_placement_from_domain(abo,
AMDGPU_GEM_DOMAIN_GTT);
+ abo->placements[0].flags |= TTM_PL_FLAG_TEMPORARY;
}
break;
case TTM_PL_TT:
@@ -538,7 +540,7 @@ static int amdgpu_bo_move(struct ttm_buffer_object *bo,
bool evict,
hop->fpfn = 0;
hop->lpfn = 0;
hop->mem_type = TTM_PL_TT;
- hop->flags = 0;
+ hop->flags |= TTM_PL_FLAG_TEMPORARY;
return -EMULTIHOP;
}
--
2.25.1
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[PATCH 1/2] drm/ttm: cleanup and add TTM_PL_FLAG_TEMPORARY
Make TTM_PL_FLAG_* start from zero and add TTM_PL_FLAG_TEMPORARY flag for temporary GTT allocation use. Signed-off-by: Lang Yu --- include/drm/ttm/ttm_placement.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/include/drm/ttm/ttm_placement.h b/include/drm/ttm/ttm_placement.h index aa6ba4d0cf78..9f5cfc7c2d5a 100644 --- a/include/drm/ttm/ttm_placement.h +++ b/include/drm/ttm/ttm_placement.h @@ -47,8 +47,9 @@ * top of the memory area, instead of the bottom. */ -#define TTM_PL_FLAG_CONTIGUOUS (1 << 19) -#define TTM_PL_FLAG_TOPDOWN (1 << 22) +#define TTM_PL_FLAG_CONTIGUOUS (1 << 0) +#define TTM_PL_FLAG_TOPDOWN (1 << 1) +#define TTM_PL_FLAG_TEMPORARY (1 << 2) /** * struct ttm_place -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH] drm/amdgpu: Fix Gstreamer api vaapih264enc missing
[AMD Official Use Only]
Looks it lack enough background for people to review:
- if (adev->vcn.inst[i].ring_dec.sched.ready)
+ if (adev->vcn.inst[i].ring_dec.sched.ready ||
+ (adev->asic_type == CHIP_NAVI12 &&
+ amdgpu_sriov_vf(adev)))
++num_rings;
[ml] why for SRIOV navi12 is forced to have those DEC rings ? since SRIOV
navi12 have no decode capability , any explain here ?
- if (amdgpu_is_tmz(adev))
- dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ;
[ML] why this is removed ? is it related to your issue ?
Thanks
--
Monk Liu | Cloud-GPU Core team
--
-Original Message-
From: amd-gfx On Behalf Of Li, Xin
(Justin)
Sent: Wednesday, May 26, 2021 6:13 PM
To: amd-gfx@lists.freedesktop.org
Cc: Li, Xin (Justin) ; Deucher, Alexander
; Min, Frank ; Koenig, Christian
Subject: [PATCH] drm/amdgpu: Fix Gstreamer api vaapih264enc missing
since vcn decoding ring is not required, so just disable it.
Cc: Alex.Deucher
Cc: Christian.Konig
Signed-off-by: Li.Xin.Justin
Signed-off-by: Frank.Min
---
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 25 ++---
2 files changed, 17 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 524e4fe5efe8..614e6b06e94e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -427,7 +427,9 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
if (adev->uvd.harvest_config & (1 << i))
continue;
- if (adev->vcn.inst[i].ring_dec.sched.ready)
+ if (adev->vcn.inst[i].ring_dec.sched.ready ||
+ (adev->asic_type == CHIP_NAVI12 &&
+ amdgpu_sriov_vf(adev)))
++num_rings;
}
ib_start_alignment = 16;
@@ -770,8 +772,6 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data,
struct drm_file *filp)
dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
if (amdgpu_mcbp || amdgpu_sriov_vf(adev))
dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
- if (amdgpu_is_tmz(adev))
- dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ;
vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
vm_size -= AMDGPU_VA_RESERVED_SIZE;
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index 8af567c546db..dc8a36766c4a 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -220,17 +220,20 @@ static int vcn_v2_0_hw_init(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct amdgpu_ring *ring = >vcn.inst->ring_dec;
- int i, r;
+ int i, r = -1;
adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
ring->doorbell_index, 0);
- if (amdgpu_sriov_vf(adev))
+ if (amdgpu_sriov_vf(adev)) {
vcn_v2_0_start_sriov(adev);
-
- r = amdgpu_ring_test_helper(ring);
- if (r)
- goto done;
+ if (adev->asic_type == CHIP_NAVI12)
+ ring->sched.ready = false;
+ } else {
+ r = amdgpu_ring_test_helper(ring);
+ if (r)
+ goto done;
+ }
//Disable vcn decode for sriov
if (amdgpu_sriov_vf(adev))
@@ -245,8 +248,11 @@ static int vcn_v2_0_hw_init(void *handle)
done:
if (!r)
- DRM_INFO("VCN decode and encode initialized successfully(under
%s).\n",
- (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG
Mode":"SPG Mode");
+ DRM_INFO("VCN %s encode initialized successfully(under %s).\n",
+ (adev->asic_type == CHIP_NAVI12 &&
+ amdgpu_sriov_vf(adev))?"":"decode and",
+ (adev->pg_flags &
+ AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode");
return r;
}
@@ -1721,9 +1727,6 @@ int vcn_v2_0_dec_ring_test_ring(struct amdgpu_ring *ring)
unsigned i;
int r;
- if (amdgpu_sriov_vf(adev))
- return 0;
-
WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD);
r = amdgpu_ring_alloc(ring, 4);
if (r)
--
2.25.1
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Re: [PATCH] drm/amdkfd: move flushing TLBs from map to unmap
Am 2021-05-26 um 3:21 p.m. schrieb Eric Huang:
>
> On 2021-05-25 3:16 p.m., Felix Kuehling wrote:
>> Similar to a recent fix by Philip Yang 76e08b37d0aa ("drm/amdgpu: flush
>> TLB if valid PDE turns into PTE"), there needs to be a conditional TLB
>> flush after map, if any PDEs were unmapped and turned into PTEs in the
>> process. This is currently returned by amdgpu_vm_bo_update_mapping in
>> the "table_freed" parameter. This needs to be also returned by
>> amdgpu_vm_bo_update and reported back to KFD, so KFD can do the TLB
>> flush after map, if needed.
> I follow up your suggestion to create another patch (attached) and
> test it. It seems it doesn't improve the latency when memory size is
> bigger than huge page (2M), because table_freed parameter will always
> be true when mapping page is huge page size. I think Philip's patch is
> to fix the case of remapping memory from small page to huge page in
> HMM, but it doesn't consider if the memory is remapped and arbitrarily
> flushes TLBs when mapping huge page.
That's unexpected. Turning an invalid PDE into a valid (huge) PTE should
not trigger a TLB flush.
Regards,
Felix
>> kfd_flush_tlb probably needs a new parameter to determine the flush
>> type. The flush after map can be a "legacy" flush (type 0). The flush
>> after unmap must be a "heavy-weight" flush (type 2) to make sure we
>> don't evict cache lines into pages that we no longer own.
>>
>> Finally, in the ticket I thought about possible optimizations using a
>> worker to minimize the impact of TLB flushes on unmap latency. That
>> could be a follow up commit.
> It is a good idea to use worker, but how do we grantee it done before
> memory is remapped? if remapping depends on it, then more latency will
> be introduced in map.
>
> Regards,
> Eric
>> Regards,
>> Felix
>>
>>
>> Am 2021-05-25 um 1:53 p.m. schrieb Eric Huang:
>>> It it to optimize memory allocation latency.
>>>
>>> Signed-off-by: Eric Huang
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
>>> b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
>>> index 960913a35ee4..ab73741edb97 100644
>>> --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
>>> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
>>> @@ -1657,20 +1657,6 @@ static int kfd_ioctl_map_memory_to_gpu(struct
>>> file *filep,
>>> goto sync_memory_failed;
>>> }
>>>
>>> - /* Flush TLBs after waiting for the page table updates to
>>> complete */
>>> - for (i = 0; i < args->n_devices; i++) {
>>> - peer = kfd_device_by_id(devices_arr[i]);
>>> - if (WARN_ON_ONCE(!peer))
>>> - continue;
>>> - peer_pdd = kfd_get_process_device_data(peer, p);
>>> - if (WARN_ON_ONCE(!peer_pdd))
>>> - continue;
>>> - if (!amdgpu_read_lock(peer->ddev, true)) {
>>> - kfd_flush_tlb(peer_pdd);
>>> - amdgpu_read_unlock(peer->ddev);
>>> - }
>>> - }
>>> -
>>> kfree(devices_arr);
>>>
>>> trace_kfd_map_memory_to_gpu_end(p,
>>> @@ -1766,6 +1752,7 @@ static int
>>> kfd_ioctl_unmap_memory_from_gpu(struct file *filep,
>>> amdgpu_read_unlock(peer->ddev);
>>> goto unmap_memory_from_gpu_failed;
>>> }
>>> + kfd_flush_tlb(peer_pdd);
>>> amdgpu_read_unlock(peer->ddev);
>>> args->n_success = i+1;
>>> }
>>> ___
>>> amd-gfx mailing list
>>> amd-gfx@lists.freedesktop.org
>>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>
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Re: [PATCH 3/3] drm/amdgpu: Use delayed work to collect RAS error counters
[Public]
Reviewed-by: Alex Deucher
From: Tuikov, Luben
Sent: Wednesday, May 26, 2021 12:43 PM
To: amd-gfx@lists.freedesktop.org
Cc: Tuikov, Luben ; Deucher, Alexander
; Koenig, Christian ;
Clements, John ; Zhang, Hawking
Subject: [PATCH 3/3] drm/amdgpu: Use delayed work to collect RAS error counters
On Context Query2 IOCTL return the correctable and
uncorrectable errors in O(1) fashion, from cached
values, and schedule a delayed work function to
calculate and cache them for the next such IOCTL.
v2: Cancel pending delayed work at ras_fini().
v3: Remove conditionals when dealing with delayed
work manipulation as they're inherently racy.
Cc: Alexander Deucher
Cc: Christian König
Cc: John Clements
Cc: Hawking Zhang
Signed-off-by: Luben Tuikov
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 31 +--
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 40 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 5
3 files changed, 74 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index bb0cfe871aba..e7a010b7ca1f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -331,10 +331,13 @@ static int amdgpu_ctx_query(struct amdgpu_device *adev,
return 0;
}
+#define AMDGPU_RAS_COUNTE_DELAY_MS 3000
+
static int amdgpu_ctx_query2(struct amdgpu_device *adev,
- struct amdgpu_fpriv *fpriv, uint32_t id,
- union drm_amdgpu_ctx_out *out)
+struct amdgpu_fpriv *fpriv, uint32_t id,
+union drm_amdgpu_ctx_out *out)
{
+ struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
struct amdgpu_ctx *ctx;
struct amdgpu_ctx_mgr *mgr;
@@ -361,6 +364,30 @@ static int amdgpu_ctx_query2(struct amdgpu_device *adev,
if (atomic_read(>guilty))
out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_GUILTY;
+ if (adev->ras_enabled && con) {
+ /* Return the cached values in O(1),
+* and schedule delayed work to cache
+* new vaues.
+*/
+ int ce_count, ue_count;
+
+ ce_count = atomic_read(>ras_ce_count);
+ ue_count = atomic_read(>ras_ue_count);
+
+ if (ce_count != ctx->ras_counter_ce) {
+ ctx->ras_counter_ce = ce_count;
+ out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RAS_CE;
+ }
+
+ if (ue_count != ctx->ras_counter_ue) {
+ ctx->ras_counter_ue = ue_count;
+ out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RAS_UE;
+ }
+
+ schedule_delayed_work(>ras_counte_delay_work,
+
msecs_to_jiffies(AMDGPU_RAS_COUNTE_DELAY_MS));
+ }
+
mutex_unlock(>lock);
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index ed3c43e8b0b5..ec936cde2726 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -27,6 +27,7 @@
#include
#include
#include
+#include
#include "amdgpu.h"
#include "amdgpu_ras.h"
@@ -2116,6 +2117,30 @@ static void amdgpu_ras_check_supported(struct
amdgpu_device *adev)
adev->ras_hw_enabled & amdgpu_ras_mask;
}
+static void amdgpu_ras_counte_dw(struct work_struct *work)
+{
+ struct amdgpu_ras *con = container_of(work, struct amdgpu_ras,
+ ras_counte_delay_work.work);
+ struct amdgpu_device *adev = con->adev;
+ struct drm_device *dev = >ddev;
+ unsigned long ce_count, ue_count;
+ int res;
+
+ res = pm_runtime_get_sync(dev->dev);
+ if (res < 0)
+ goto Out;
+
+ /* Cache new values.
+*/
+ amdgpu_ras_query_error_count(adev, _count, _count);
+ atomic_set(>ras_ce_count, ce_count);
+ atomic_set(>ras_ue_count, ue_count);
+
+ pm_runtime_mark_last_busy(dev->dev);
+Out:
+ pm_runtime_put_autosuspend(dev->dev);
+}
+
int amdgpu_ras_init(struct amdgpu_device *adev)
{
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
@@ -2130,6 +2155,11 @@ int amdgpu_ras_init(struct amdgpu_device *adev)
if (!con)
return -ENOMEM;
+ con->adev = adev;
+ INIT_DELAYED_WORK(>ras_counte_delay_work, amdgpu_ras_counte_dw);
+ atomic_set(>ras_ce_count, 0);
+ atomic_set(>ras_ue_count, 0);
+
con->objs = (struct ras_manager *)(con + 1);
amdgpu_ras_set_context(adev, con);
@@ -2233,6 +2263,8 @@ int amdgpu_ras_late_init(struct amdgpu_device *adev,
struct ras_fs_if *fs_info,
struct ras_ih_if *ih_info)
{
+ struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
+
Re: [PATCH 0/4] drm: Finally retire struct drm_format_name_buf
On Wed, May 26, 2021 at 09:21:10PM +0200, Thomas Zimmermann wrote: > ping for further a-bs / r-bs Thanks for the ping. For the series: Reviewed-by: Sakari Ailus > > Am 16.05.21 um 14:13 schrieb Thomas Zimmermann: > > This is a cleanup patchset to remove drm_format_name_buf et al. There > > are two instances in drivers that need to be replaced with the %4cc > > printk format modifier. Patch 3 was left over back from an earlier > > patchset. [1] Patch 4 removes struct drm_format_name_buf. > > > > I built-tested with drm-tip. The patchsetcan be mered through drm-misc. > > > > [1] > > https://lore.kernel.org/dri-devel/20210216155723.17109-1-sakari.ai...@linux.intel.com/ > > > > Sakari Ailus (1): > >drm: Remove drm_get_format_name() > > > > Thomas Zimmermann (3): > >drm/amdgpu: Use %p4cc to print 4CC format > >drm/simpledrm: Use %p4cc to print 4CC format > >drm/fourcc: Remove struct drm_format_buf_name > > > > drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 7 ++ > > drivers/gpu/drm/drm_fourcc.c| 25 - > > drivers/gpu/drm/tiny/simpledrm.c| 6 ++--- > > include/drm/drm_fourcc.h| 9 > > 4 files changed, 4 insertions(+), 43 deletions(-) > > > > -- > > 2.31.1 > > > -- Sakari Ailus ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 0/4] drm: Finally retire struct drm_format_name_buf
ping for further a-bs / r-bs Am 16.05.21 um 14:13 schrieb Thomas Zimmermann: This is a cleanup patchset to remove drm_format_name_buf et al. There are two instances in drivers that need to be replaced with the %4cc printk format modifier. Patch 3 was left over back from an earlier patchset. [1] Patch 4 removes struct drm_format_name_buf. I built-tested with drm-tip. The patchsetcan be mered through drm-misc. [1] https://lore.kernel.org/dri-devel/20210216155723.17109-1-sakari.ai...@linux.intel.com/ Sakari Ailus (1): drm: Remove drm_get_format_name() Thomas Zimmermann (3): drm/amdgpu: Use %p4cc to print 4CC format drm/simpledrm: Use %p4cc to print 4CC format drm/fourcc: Remove struct drm_format_buf_name drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 7 ++ drivers/gpu/drm/drm_fourcc.c| 25 - drivers/gpu/drm/tiny/simpledrm.c| 6 ++--- include/drm/drm_fourcc.h| 9 4 files changed, 4 insertions(+), 43 deletions(-) -- 2.31.1 -- Thomas Zimmermann Graphics Driver Developer SUSE Software Solutions Germany GmbH Maxfeldstr. 5, 90409 Nürnberg, Germany (HRB 36809, AG Nürnberg) Geschäftsführer: Felix Imendörffer OpenPGP_signature Description: OpenPGP digital signature ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdkfd: move flushing TLBs from map to unmap
On 2021-05-25 3:16 p.m., Felix Kuehling wrote:
Similar to a recent fix by Philip Yang 76e08b37d0aa ("drm/amdgpu: flush
TLB if valid PDE turns into PTE"), there needs to be a conditional TLB
flush after map, if any PDEs were unmapped and turned into PTEs in the
process. This is currently returned by amdgpu_vm_bo_update_mapping in
the "table_freed" parameter. This needs to be also returned by
amdgpu_vm_bo_update and reported back to KFD, so KFD can do the TLB
flush after map, if needed.
I follow up your suggestion to create another patch (attached) and test
it. It seems it doesn't improve the latency when memory size is bigger
than huge page (2M), because table_freed parameter will always be true
when mapping page is huge page size. I think Philip's patch is to fix
the case of remapping memory from small page to huge page in HMM, but it
doesn't consider if the memory is remapped and arbitrarily flushes TLBs
when mapping huge page.
kfd_flush_tlb probably needs a new parameter to determine the flush
type. The flush after map can be a "legacy" flush (type 0). The flush
after unmap must be a "heavy-weight" flush (type 2) to make sure we
don't evict cache lines into pages that we no longer own.
Finally, in the ticket I thought about possible optimizations using a
worker to minimize the impact of TLB flushes on unmap latency. That
could be a follow up commit.
It is a good idea to use worker, but how do we grantee it done before
memory is remapped? if remapping depends on it, then more latency will
be introduced in map.
Regards,
Eric
Regards,
Felix
Am 2021-05-25 um 1:53 p.m. schrieb Eric Huang:
It it to optimize memory allocation latency.
Signed-off-by: Eric Huang
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
index 960913a35ee4..ab73741edb97 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
@@ -1657,20 +1657,6 @@ static int kfd_ioctl_map_memory_to_gpu(struct
file *filep,
goto sync_memory_failed;
}
- /* Flush TLBs after waiting for the page table updates to
complete */
- for (i = 0; i < args->n_devices; i++) {
- peer = kfd_device_by_id(devices_arr[i]);
- if (WARN_ON_ONCE(!peer))
- continue;
- peer_pdd = kfd_get_process_device_data(peer, p);
- if (WARN_ON_ONCE(!peer_pdd))
- continue;
- if (!amdgpu_read_lock(peer->ddev, true)) {
- kfd_flush_tlb(peer_pdd);
- amdgpu_read_unlock(peer->ddev);
- }
- }
-
kfree(devices_arr);
trace_kfd_map_memory_to_gpu_end(p,
@@ -1766,6 +1752,7 @@ static int
kfd_ioctl_unmap_memory_from_gpu(struct file *filep,
amdgpu_read_unlock(peer->ddev);
goto unmap_memory_from_gpu_failed;
}
+ kfd_flush_tlb(peer_pdd);
amdgpu_read_unlock(peer->ddev);
args->n_success = i+1;
}
___
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>From 6218597e7117ec2f18cecd9314e196d598497b62 Mon Sep 17 00:00:00 2001
From: Eric Huang
Date: Wed, 26 May 2021 14:50:52 -0400
Subject: [PATCH] drm/amdkfd: conditionally flush TLBs after map
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h| 1 +
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c| 6 ++---
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c| 8 +++---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h| 2 +-
drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 27 ++-
.../drm/amd/amdkfd/kfd_device_queue_manager.c | 6 ++---
drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 2 +-
drivers/gpu/drm/amd/amdkfd/kfd_process.c | 4 +--
10 files changed, 32 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index 2560977760b3..997258c24ef2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -85,6 +85,7 @@ struct kgd_mem {
bool aql_queue;
bool is_imported;
+ bool table_freed;
};
/* KFD Memory Eviction */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index 385c33675227..e445ac7ff2ee 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -1126,7 +1126,7 @@ static int update_gpuvm_pte(struct kgd_mem *mem,
return ret;
/* Update the page tables */
- ret = amdgpu_vm_bo_update(adev, bo_va, false);
+ ret = amdgpu_vm_bo_update(adev, bo_va, false, >table_freed);
if (ret) {
pr_err("amdgpu_vm_bo_update
Re: [PATCH] drm/amdgpu: Fix Gstreamer api vaapih264enc missing
On Wed, May 26, 2021 at 6:13 AM Li, Xin (Justin) wrote:
>
> since vcn decoding ring is not required, so just disable it.
>
> Cc: Alex.Deucher
> Cc: Christian.Konig
> Signed-off-by: Li.Xin.Justin
> Signed-off-by: Frank.Min
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 6 +++---
> drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 25 ++---
> 2 files changed, 17 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> index 524e4fe5efe8..614e6b06e94e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> @@ -427,7 +427,9 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
> if (adev->uvd.harvest_config & (1 << i))
> continue;
>
> - if (adev->vcn.inst[i].ring_dec.sched.ready)
> + if (adev->vcn.inst[i].ring_dec.sched.ready ||
> + (adev->asic_type == CHIP_NAVI12 &&
> + amdgpu_sriov_vf(adev)))
> ++num_rings;
> }
> ib_start_alignment = 16;
> @@ -770,8 +772,6 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data,
> struct drm_file *filp)
> dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
> if (amdgpu_mcbp || amdgpu_sriov_vf(adev))
> dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
> - if (amdgpu_is_tmz(adev))
> - dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ;
>
This looks unrelated and should be dropped.
> vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
> vm_size -= AMDGPU_VA_RESERVED_SIZE;
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> index 8af567c546db..dc8a36766c4a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> @@ -220,17 +220,20 @@ static int vcn_v2_0_hw_init(void *handle)
> {
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> struct amdgpu_ring *ring = >vcn.inst->ring_dec;
> - int i, r;
> + int i, r = -1;
>
> adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
> ring->doorbell_index, 0);
>
> - if (amdgpu_sriov_vf(adev))
> + if (amdgpu_sriov_vf(adev)) {
> vcn_v2_0_start_sriov(adev);
> -
> - r = amdgpu_ring_test_helper(ring);
> - if (r)
> - goto done;
> + if (adev->asic_type == CHIP_NAVI12)
> + ring->sched.ready = false;
> + } else {
> + r = amdgpu_ring_test_helper(ring);
> + if (r)
> + goto done;
> + }
>
> //Disable vcn decode for sriov
> if (amdgpu_sriov_vf(adev))
> @@ -245,8 +248,11 @@ static int vcn_v2_0_hw_init(void *handle)
>
> done:
> if (!r)
> - DRM_INFO("VCN decode and encode initialized
> successfully(under %s).\n",
> - (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG
> Mode":"SPG Mode");
> + DRM_INFO("VCN %s encode initialized successfully(under
> %s).\n",
> + (adev->asic_type == CHIP_NAVI12 &&
> + amdgpu_sriov_vf(adev))?"":"decode and",
> + (adev->pg_flags &
> + AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG
> Mode");
>
> return r;
> }
> @@ -1721,9 +1727,6 @@ int vcn_v2_0_dec_ring_test_ring(struct amdgpu_ring
> *ring)
> unsigned i;
> int r;
>
> - if (amdgpu_sriov_vf(adev))
> - return 0;
> -
> WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD);
> r = amdgpu_ring_alloc(ring, 4);
> if (r)
> --
> 2.25.1
>
> ___
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> amd-gfx@lists.freedesktop.org
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Re: [PATCH v2 3/5] drm/amdgpu: switch to amdgpu_bo_vm for vm code
Hi Christian,
On 5/26/21 4:58 PM, Christian König wrote:
Am 26.05.21 um 15:06 schrieb Nirmoy Das:
The subclass, amdgpu_bo_vm is intended for PT/PD BOs which are also
shadowed, so switch to amdgpu_bo_vm BO for PT/PD BOs.
v2: squash three related patches.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 90 +
drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 16 ++--
2 files changed, 67 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 6bc7566cc193..80d50e6d75f9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -658,9 +658,9 @@ void amdgpu_vm_move_to_lru_tail(struct
amdgpu_device *adev,
ttm_bo_move_to_lru_tail(>tbo, >tbo.mem,
>lru_bulk_move);
- if (bo->shadow)
- ttm_bo_move_to_lru_tail(>shadow->tbo,
- >shadow->tbo.mem,
+ if (bo->tbo.type == ttm_bo_type_kernel)
+ ttm_bo_move_to_lru_tail(_amdgpu_bo_vm(bo)->shadow->tbo,
+ _amdgpu_bo_vm(bo)->shadow->tbo.mem,
Maybe use a local variable for the shadow BO here.
>lru_bulk_move);
}
spin_unlock(>mman.bdev.lru_lock);
@@ -696,8 +696,8 @@ int amdgpu_vm_validate_pt_bos(struct
amdgpu_device *adev, struct amdgpu_vm *vm,
r = validate(param, bo);
if (r)
return r;
- if (bo->shadow) {
- r = validate(param, bo->shadow);
+ if (bo->tbo.type == ttm_bo_type_kernel) {
+ r = validate(param, to_amdgpu_bo_vm(bo)->shadow);
if (r)
return r;
}
@@ -793,8 +793,9 @@ static int amdgpu_vm_clear_bo(struct
amdgpu_device *adev,
if (r)
return r;
- if (bo->shadow) {
- r = ttm_bo_validate(>shadow->tbo, >shadow->placement,
+ if (bo->tbo.type == ttm_bo_type_kernel) {
+ r = ttm_bo_validate(_amdgpu_bo_vm(bo)->shadow->tbo,
+ _amdgpu_bo_vm(bo)->shadow->placement,
Same here.
);
if (r)
return r;
@@ -863,14 +864,17 @@ static int amdgpu_vm_clear_bo(struct
amdgpu_device *adev,
* @vm: requesting vm
* @level: the page table level
* @immediate: use a immediate update
- * @bo: pointer to the buffer object pointer
+ * @vmbo: pointer to the buffer object pointer
*/
static int amdgpu_vm_pt_create(struct amdgpu_device *adev,
struct amdgpu_vm *vm,
int level, bool immediate,
- struct amdgpu_bo **bo)
+ struct amdgpu_bo_vm **vmbo)
{
struct amdgpu_bo_param bp;
+ struct amdgpu_bo *bo;
+ struct amdgpu_bo *shadow_bo;
+ struct dma_resv *resv;
int r;
memset(, 0, sizeof(bp));
@@ -881,7 +885,7 @@ static int amdgpu_vm_pt_create(struct
amdgpu_device *adev,
bp.domain = amdgpu_bo_get_preferred_pin_domain(adev, bp.domain);
bp.flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
AMDGPU_GEM_CREATE_CPU_GTT_USWC;
- bp.bo_ptr_size = sizeof(struct amdgpu_bo);
+ bp.bo_ptr_size = sizeof(struct amdgpu_bo_vm);
if (vm->use_cpu_for_update)
bp.flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
@@ -890,26 +894,43 @@ static int amdgpu_vm_pt_create(struct
amdgpu_device *adev,
if (vm->root.base.bo)
bp.resv = vm->root.base.bo->tbo.base.resv;
- r = amdgpu_bo_create(adev, , bo);
+ r = amdgpu_bo_create_vm(adev, , vmbo);
if (r)
return r;
+ bo = &(*vmbo)->bo;
if (vm->is_compute_context && (adev->flags & AMD_IS_APU))
return 0;
if (!bp.resv)
- WARN_ON(dma_resv_lock((*bo)->tbo.base.resv,
+ WARN_ON(dma_resv_lock(bo->tbo.base.resv,
NULL));
- r = amdgpu_bo_create_shadow(adev, bp.size, *bo);
+ resv = bp.resv;
Maybe shuffle that code around a bit, then you only need the resv
variable and no longer the bo variable.
I can remove the shadow_bo variable but I need the bo for
amdgpu_bo_unref(), as this takes amdgpu_bo ** as argument.
Regards,
Nirmoy
+ memset(, 0, sizeof(bp));
+ bp.size = amdgpu_vm_bo_size(adev, level);
+ bp.domain = AMDGPU_GEM_DOMAIN_GTT;
+ bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
+ bp.type = ttm_bo_type_kernel;
+ bp.resv = bo->tbo.base.resv;
+ bp.bo_ptr_size = sizeof(struct amdgpu_bo);
- if (!bp.resv)
- dma_resv_unlock((*bo)->tbo.base.resv);
+ r = amdgpu_bo_create(adev, , _bo);
+
+
Remove the two empty lines here
+ if (!resv)
+ dma_resv_unlock(bo->tbo.base.resv);
if (r) {
- amdgpu_bo_unref(bo);
+ amdgpu_bo_unref();
return r;
}
+ shadow_bo->parent = amdgpu_bo_ref(bo);
+ mutex_lock(>shadow_list_lock);
+ list_add_tail(_bo->shadow_list, >shadow_list);
+ mutex_unlock(>shadow_list_lock);
+ (*vmbo)->shadow = shadow_bo;
Ok, we should either move the shadow_list into the vm_mgr structure or
[PATCH 3/3] drm/amdgpu: Use delayed work to collect RAS error counters
On Context Query2 IOCTL return the correctable and
uncorrectable errors in O(1) fashion, from cached
values, and schedule a delayed work function to
calculate and cache them for the next such IOCTL.
v2: Cancel pending delayed work at ras_fini().
v3: Remove conditionals when dealing with delayed
work manipulation as they're inherently racy.
Cc: Alexander Deucher
Cc: Christian König
Cc: John Clements
Cc: Hawking Zhang
Signed-off-by: Luben Tuikov
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 31 +--
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 40 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 5
3 files changed, 74 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index bb0cfe871aba..e7a010b7ca1f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -331,10 +331,13 @@ static int amdgpu_ctx_query(struct amdgpu_device *adev,
return 0;
}
+#define AMDGPU_RAS_COUNTE_DELAY_MS 3000
+
static int amdgpu_ctx_query2(struct amdgpu_device *adev,
- struct amdgpu_fpriv *fpriv, uint32_t id,
- union drm_amdgpu_ctx_out *out)
+struct amdgpu_fpriv *fpriv, uint32_t id,
+union drm_amdgpu_ctx_out *out)
{
+ struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
struct amdgpu_ctx *ctx;
struct amdgpu_ctx_mgr *mgr;
@@ -361,6 +364,30 @@ static int amdgpu_ctx_query2(struct amdgpu_device *adev,
if (atomic_read(>guilty))
out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_GUILTY;
+ if (adev->ras_enabled && con) {
+ /* Return the cached values in O(1),
+* and schedule delayed work to cache
+* new vaues.
+*/
+ int ce_count, ue_count;
+
+ ce_count = atomic_read(>ras_ce_count);
+ ue_count = atomic_read(>ras_ue_count);
+
+ if (ce_count != ctx->ras_counter_ce) {
+ ctx->ras_counter_ce = ce_count;
+ out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RAS_CE;
+ }
+
+ if (ue_count != ctx->ras_counter_ue) {
+ ctx->ras_counter_ue = ue_count;
+ out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RAS_UE;
+ }
+
+ schedule_delayed_work(>ras_counte_delay_work,
+
msecs_to_jiffies(AMDGPU_RAS_COUNTE_DELAY_MS));
+ }
+
mutex_unlock(>lock);
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index ed3c43e8b0b5..ec936cde2726 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -27,6 +27,7 @@
#include
#include
#include
+#include
#include "amdgpu.h"
#include "amdgpu_ras.h"
@@ -2116,6 +2117,30 @@ static void amdgpu_ras_check_supported(struct
amdgpu_device *adev)
adev->ras_hw_enabled & amdgpu_ras_mask;
}
+static void amdgpu_ras_counte_dw(struct work_struct *work)
+{
+ struct amdgpu_ras *con = container_of(work, struct amdgpu_ras,
+ ras_counte_delay_work.work);
+ struct amdgpu_device *adev = con->adev;
+ struct drm_device *dev = >ddev;
+ unsigned long ce_count, ue_count;
+ int res;
+
+ res = pm_runtime_get_sync(dev->dev);
+ if (res < 0)
+ goto Out;
+
+ /* Cache new values.
+*/
+ amdgpu_ras_query_error_count(adev, _count, _count);
+ atomic_set(>ras_ce_count, ce_count);
+ atomic_set(>ras_ue_count, ue_count);
+
+ pm_runtime_mark_last_busy(dev->dev);
+Out:
+ pm_runtime_put_autosuspend(dev->dev);
+}
+
int amdgpu_ras_init(struct amdgpu_device *adev)
{
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
@@ -2130,6 +2155,11 @@ int amdgpu_ras_init(struct amdgpu_device *adev)
if (!con)
return -ENOMEM;
+ con->adev = adev;
+ INIT_DELAYED_WORK(>ras_counte_delay_work, amdgpu_ras_counte_dw);
+ atomic_set(>ras_ce_count, 0);
+ atomic_set(>ras_ue_count, 0);
+
con->objs = (struct ras_manager *)(con + 1);
amdgpu_ras_set_context(adev, con);
@@ -2233,6 +2263,8 @@ int amdgpu_ras_late_init(struct amdgpu_device *adev,
struct ras_fs_if *fs_info,
struct ras_ih_if *ih_info)
{
+ struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
+ unsigned long ue_count, ce_count;
int r;
/* disable RAS feature per IP block if it is not supported */
@@ -2273,6 +2305,12 @@ int amdgpu_ras_late_init(struct amdgpu_device *adev,
if (r)
goto sysfs;
+ /* Those are the cached values at init.
+*/
+ amdgpu_ras_query_error_count(adev,
[PATCH 2/3] drm/amdgpu: Fix RAS function interface
The correctable and uncorrectable errors
are calculated at each invocation of this
function. Therefore, it is highly inefficient to
return just one of them based on a Boolean
input. If the caller wants both, twice the work
would be done. (And this work is O(n^3) on
Vega20.)
Fix this "interface" to simply return what it had
calculated--both values. Let the caller choose
what it wants to record, inspect, use.
Cc: Alexander Deucher
Cc: John Clements
Cc: Hawking Zhang
Signed-off-by: Luben Tuikov
Reviewed-by: Alexander Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 23 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 5 +++--
2 files changed, 18 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index e3a4c3a7635a..ed3c43e8b0b5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -1043,29 +1043,36 @@ int amdgpu_ras_error_inject(struct amdgpu_device *adev,
}
/* get the total error counts on all IPs */
-unsigned long amdgpu_ras_query_error_count(struct amdgpu_device *adev,
- bool is_ce)
+void amdgpu_ras_query_error_count(struct amdgpu_device *adev,
+ unsigned long *ce_count,
+ unsigned long *ue_count)
{
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
struct ras_manager *obj;
- struct ras_err_data data = {0, 0};
+ unsigned long ce, ue;
if (!adev->ras_enabled || !con)
- return 0;
+ return;
+ ce = 0;
+ ue = 0;
list_for_each_entry(obj, >head, node) {
struct ras_query_if info = {
.head = obj->head,
};
if (amdgpu_ras_query_error_status(adev, ))
- return 0;
+ return;
- data.ce_count += info.ce_count;
- data.ue_count += info.ue_count;
+ ce += info.ce_count;
+ ue += info.ue_count;
}
- return is_ce ? data.ce_count : data.ue_count;
+ if (ce_count)
+ *ce_count = ce;
+
+ if (ue_count)
+ *ue_count = ue;
}
/* query/inject/cure end */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
index bfa40c8ecc94..10fca0393106 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
@@ -485,8 +485,9 @@ int amdgpu_ras_request_reset_on_boot(struct amdgpu_device
*adev,
void amdgpu_ras_resume(struct amdgpu_device *adev);
void amdgpu_ras_suspend(struct amdgpu_device *adev);
-unsigned long amdgpu_ras_query_error_count(struct amdgpu_device *adev,
- bool is_ce);
+void amdgpu_ras_query_error_count(struct amdgpu_device *adev,
+ unsigned long *ce_count,
+ unsigned long *ue_count);
/* error handling functions */
int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
--
2.31.1.527.g2d677e5b15
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[PATCH 1/3] drm/amdgpu: Don't query CE and UE errors
On QUERY2 IOCTL don't query counts of correctable
and uncorrectable errors, since when RAS is
enabled and supported on Vega20 server boards,
this takes insurmountably long time, in O(n^3),
which slows the system down to the point of it
being unusable when we have GUI up.
Fixes: ae363a212b14 ("drm/amdgpu: Add a new flag to AMDGPU_CTX_OP_QUERY_STATE2")
Cc: Alexander Deucher
Cc: sta...@vger.kernel.org
Signed-off-by: Luben Tuikov
Reviewed-by: Alexander Deucher
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 16
1 file changed, 16 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index fc83445fbc40..bb0cfe871aba 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -337,7 +337,6 @@ static int amdgpu_ctx_query2(struct amdgpu_device *adev,
{
struct amdgpu_ctx *ctx;
struct amdgpu_ctx_mgr *mgr;
- unsigned long ras_counter;
if (!fpriv)
return -EINVAL;
@@ -362,21 +361,6 @@ static int amdgpu_ctx_query2(struct amdgpu_device *adev,
if (atomic_read(>guilty))
out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_GUILTY;
- /*query ue count*/
- ras_counter = amdgpu_ras_query_error_count(adev, false);
- /*ras counter is monotonic increasing*/
- if (ras_counter != ctx->ras_counter_ue) {
- out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RAS_UE;
- ctx->ras_counter_ue = ras_counter;
- }
-
- /*query ce count*/
- ras_counter = amdgpu_ras_query_error_count(adev, true);
- if (ras_counter != ctx->ras_counter_ce) {
- out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RAS_CE;
- ctx->ras_counter_ce = ras_counter;
- }
-
mutex_unlock(>lock);
return 0;
}
--
2.31.1.527.g2d677e5b15
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Re: [PATCH 3/3] drm/amdgpu: Use delayed work to collect RAS error counters
Isn't that kind what this patch does? When the app is running, these IOCTL calls are happening at regular intervals, so if we schedule work, the cache should be updated by the next time we get the IOCTL call. I'm not sure how we would trigger the events. I don't think interrupts on correctable errors make sense. Alex On Wed, May 26, 2021 at 12:05 PM Lazar, Lijo wrote: > > [AMD Official Use Only] > > > Hi Luben, > > What I meant by event based is a thread waiting on wait queue for events, not > a periodic polling as you had in the original patch. It still fetches the > cached data on IOCTL but also triggers an event to poll for new errors. > Similarly, a periodic error handler running to handle threshold errors also > could trigger event. Basically, error data fetch is centralized to the thread. > > It's just a different approach, don't know if that will make things more > complex. > > Thanks, > Lijo > > From: Tuikov, Luben > Sent: Wednesday, May 26, 2021 8:42:29 PM > To: Lazar, Lijo ; amd-gfx@lists.freedesktop.org > > Cc: Deucher, Alexander ; Clements, John > ; Koenig, Christian ; Zhang, > Hawking > Subject: Re: [PATCH 3/3] drm/amdgpu: Use delayed work to collect RAS error > counters > > On 2021-05-26 7:00 a.m., Lazar, Lijo wrote: > > [AMD Official Use Only] > > > > Scheduling an error status query just based on IOCTL doesn't sound like a > > sound approach. What if driver needs to handle errors based on that - for > > ex: if the number of correctable errors exceed a certain threshold? > That's exactly the trigger which evokes the error count procedure. The > difference is that on that IOCTL, > we return in O(1), the cached values and then trigger the counting procedure > in a delayed work item, > since it takes O(n^3) and we cannot do it when the IOCTL is being processed > as that negatively > affects the user experience, and the overall agility of the system. > > This is the closest implementation to what was had before when the count was > trigger at the IOCTL time, > and the IOCTL blocked until the count was completed. > > Acting on exceeding a certain threshold is fine, since we're not competing > against the delta > of the excessive amount of errors, just so long as it does exceed. That is, > so long as it exceeds, > do something, we don't really care if it exceeds by delta or 10*delta. > > But what is important, is the _time_ frequency of the delayed work, > AMDGPU_RAS_COUNTE_DELAY_MS, > in my v2 of this patch. When set to 0, i.e. count as soon as possible, we get > about 22% duty cycle of > the CPU just doing that, all the time, as it seems this IOCTL is being called > constantly, and thus > the counting takes place all the time, continuously. And this isn't good for > the system's performance > and power management. > > When set to 3 seconds, we get a normal (expected) system behaviour in Vega20 > sever boards. > > > IMO, I'm more aligned to Luben's original approach of having something > > waiting in the background - instead of a periodic timer based trigger, it > > could be an event based trigger. Event may be an ioctl, error handler > > timer ticks or something else. > > Well, my original idea broke power management (PM), since it ran continuously > regardless of PM and whether we indeed need the count. > > Now, when you say "Event may be an ioctl"--this is exactly what, > > 1) was had before, interlocked, and it made the system unusable to a GUI > user, and > 2) is what we have in this patch, but we process the count asynchronously, > while > we return the O(1) count instantly. > > The advantage of 2) over my original approach, is that the count is triggered > only > on IOCTL call, albeit delayed so that we can return in O(1) the cached value. > Thus, > if no QUERY2 IOCTL is received, then we don't count the errors, as we don't > schedule > the delayed work. > > Regards, > Luben > > > Thanks, > > Lijo > > > > -Original Message- > > From: amd-gfx On Behalf Of Luben > > Tuikov > > Sent: Saturday, May 22, 2021 2:49 AM > > To: amd-gfx@lists.freedesktop.org > > Cc: Deucher, Alexander ; Tuikov, Luben > > ; Clements, John ; Koenig, > > Christian ; Zhang, Hawking > > Subject: [PATCH 3/3] drm/amdgpu: Use delayed work to collect RAS error > > counters > > > > On Context Query2 IOCTL return the correctable and uncorrectable errors in > > O(1) fashion, from cached values, and schedule a delayed work function to > > calculate and cache them for the next such IOCTL. > > > > Cc: Alexander Deucher > > Cc: Christian König > > Cc: John Clements > > Cc: Hawking Zhang > > Signed-off-by: Luben Tuikov > > --- > > drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 32 +++-- > > drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 38 + > > drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 5 > > 3 files changed, 73 insertions(+), 2 deletions(-) > > > > diff --git
Re: [PATCH 3/3] drm/amdgpu: Use delayed work to collect RAS error counters
[AMD Official Use Only] Hi Luben, What I meant by event based is a thread waiting on wait queue for events, not a periodic polling as you had in the original patch. It still fetches the cached data on IOCTL but also triggers an event to poll for new errors. Similarly, a periodic error handler running to handle threshold errors also could trigger event. Basically, error data fetch is centralized to the thread. It's just a different approach, don't know if that will make things more complex. Thanks, Lijo From: Tuikov, Luben Sent: Wednesday, May 26, 2021 8:42:29 PM To: Lazar, Lijo ; amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander ; Clements, John ; Koenig, Christian ; Zhang, Hawking Subject: Re: [PATCH 3/3] drm/amdgpu: Use delayed work to collect RAS error counters On 2021-05-26 7:00 a.m., Lazar, Lijo wrote: > [AMD Official Use Only] > > Scheduling an error status query just based on IOCTL doesn't sound like a > sound approach. What if driver needs to handle errors based on that - for ex: > if the number of correctable errors exceed a certain threshold? That's exactly the trigger which evokes the error count procedure. The difference is that on that IOCTL, we return in O(1), the cached values and then trigger the counting procedure in a delayed work item, since it takes O(n^3) and we cannot do it when the IOCTL is being processed as that negatively affects the user experience, and the overall agility of the system. This is the closest implementation to what was had before when the count was trigger at the IOCTL time, and the IOCTL blocked until the count was completed. Acting on exceeding a certain threshold is fine, since we're not competing against the delta of the excessive amount of errors, just so long as it does exceed. That is, so long as it exceeds, do something, we don't really care if it exceeds by delta or 10*delta. But what is important, is the _time_ frequency of the delayed work, AMDGPU_RAS_COUNTE_DELAY_MS, in my v2 of this patch. When set to 0, i.e. count as soon as possible, we get about 22% duty cycle of the CPU just doing that, all the time, as it seems this IOCTL is being called constantly, and thus the counting takes place all the time, continuously. And this isn't good for the system's performance and power management. When set to 3 seconds, we get a normal (expected) system behaviour in Vega20 sever boards. > IMO, I'm more aligned to Luben's original approach of having something > waiting in the background - instead of a periodic timer based trigger, it > could be an event based trigger. Event may be an ioctl, error handler timer > ticks or something else. Well, my original idea broke power management (PM), since it ran continuously regardless of PM and whether we indeed need the count. Now, when you say "Event may be an ioctl"--this is exactly what, 1) was had before, interlocked, and it made the system unusable to a GUI user, and 2) is what we have in this patch, but we process the count asynchronously, while we return the O(1) count instantly. The advantage of 2) over my original approach, is that the count is triggered only on IOCTL call, albeit delayed so that we can return in O(1) the cached value. Thus, if no QUERY2 IOCTL is received, then we don't count the errors, as we don't schedule the delayed work. Regards, Luben > Thanks, > Lijo > > -Original Message- > From: amd-gfx On Behalf Of Luben > Tuikov > Sent: Saturday, May 22, 2021 2:49 AM > To: amd-gfx@lists.freedesktop.org > Cc: Deucher, Alexander ; Tuikov, Luben > ; Clements, John ; Koenig, > Christian ; Zhang, Hawking > Subject: [PATCH 3/3] drm/amdgpu: Use delayed work to collect RAS error > counters > > On Context Query2 IOCTL return the correctable and uncorrectable errors in > O(1) fashion, from cached values, and schedule a delayed work function to > calculate and cache them for the next such IOCTL. > > Cc: Alexander Deucher > Cc: Christian König > Cc: John Clements > Cc: Hawking Zhang > Signed-off-by: Luben Tuikov > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 32 +++-- > drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 38 + > drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 5 > 3 files changed, 73 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c > index bb0cfe871aba..4e95d255960b 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c > @@ -331,10 +331,13 @@ static int amdgpu_ctx_query(struct amdgpu_device *adev, >return 0; > } > > +#define AMDGPU_RAS_COUNTE_DELAY_MS 3000 > + > static int amdgpu_ctx_query2(struct amdgpu_device *adev, > - struct amdgpu_fpriv *fpriv, uint32_t id, > - union drm_amdgpu_ctx_out *out) > + struct amdgpu_fpriv *fpriv, uint32_t id, > + union
Re: [PATCH 3/3] drm/amdgpu: Use delayed work to collect RAS error counters
On 2021-05-26 7:00 a.m., Lazar, Lijo wrote:
> [AMD Official Use Only]
>
> Scheduling an error status query just based on IOCTL doesn't sound like a
> sound approach. What if driver needs to handle errors based on that - for ex:
> if the number of correctable errors exceed a certain threshold?
That's exactly the trigger which evokes the error count procedure. The
difference is that on that IOCTL,
we return in O(1), the cached values and then trigger the counting procedure in
a delayed work item,
since it takes O(n^3) and we cannot do it when the IOCTL is being processed as
that negatively
affects the user experience, and the overall agility of the system.
This is the closest implementation to what was had before when the count was
trigger at the IOCTL time,
and the IOCTL blocked until the count was completed.
Acting on exceeding a certain threshold is fine, since we're not competing
against the delta
of the excessive amount of errors, just so long as it does exceed. That is, so
long as it exceeds,
do something, we don't really care if it exceeds by delta or 10*delta.
But what is important, is the _time_ frequency of the delayed work,
AMDGPU_RAS_COUNTE_DELAY_MS,
in my v2 of this patch. When set to 0, i.e. count as soon as possible, we get
about 22% duty cycle of
the CPU just doing that, all the time, as it seems this IOCTL is being called
constantly, and thus
the counting takes place all the time, continuously. And this isn't good for
the system's performance
and power management.
When set to 3 seconds, we get a normal (expected) system behaviour in Vega20
sever boards.
> IMO, I'm more aligned to Luben's original approach of having something
> waiting in the background - instead of a periodic timer based trigger, it
> could be an event based trigger. Event may be an ioctl, error handler timer
> ticks or something else.
Well, my original idea broke power management (PM), since it ran continuously
regardless of PM and whether we indeed need the count.
Now, when you say "Event may be an ioctl"--this is exactly what,
1) was had before, interlocked, and it made the system unusable to a GUI user,
and
2) is what we have in this patch, but we process the count asynchronously, while
we return the O(1) count instantly.
The advantage of 2) over my original approach, is that the count is triggered
only
on IOCTL call, albeit delayed so that we can return in O(1) the cached value.
Thus,
if no QUERY2 IOCTL is received, then we don't count the errors, as we don't
schedule
the delayed work.
Regards,
Luben
> Thanks,
> Lijo
>
> -Original Message-
> From: amd-gfx On Behalf Of Luben
> Tuikov
> Sent: Saturday, May 22, 2021 2:49 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Tuikov, Luben
> ; Clements, John ; Koenig,
> Christian ; Zhang, Hawking
> Subject: [PATCH 3/3] drm/amdgpu: Use delayed work to collect RAS error
> counters
>
> On Context Query2 IOCTL return the correctable and uncorrectable errors in
> O(1) fashion, from cached values, and schedule a delayed work function to
> calculate and cache them for the next such IOCTL.
>
> Cc: Alexander Deucher
> Cc: Christian König
> Cc: John Clements
> Cc: Hawking Zhang
> Signed-off-by: Luben Tuikov
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 32 +++--
> drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 38 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 5
> 3 files changed, 73 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
> index bb0cfe871aba..4e95d255960b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
> @@ -331,10 +331,13 @@ static int amdgpu_ctx_query(struct amdgpu_device *adev,
> return 0;
> }
>
> +#define AMDGPU_RAS_COUNTE_DELAY_MS 3000
> +
> static int amdgpu_ctx_query2(struct amdgpu_device *adev,
> - struct amdgpu_fpriv *fpriv, uint32_t id,
> - union drm_amdgpu_ctx_out *out)
> + struct amdgpu_fpriv *fpriv, uint32_t id,
> + union drm_amdgpu_ctx_out *out)
> {
> + struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
> struct amdgpu_ctx *ctx;
> struct amdgpu_ctx_mgr *mgr;
>
> @@ -361,6 +364,31 @@ static int amdgpu_ctx_query2(struct amdgpu_device *adev,
> if (atomic_read(>guilty))
> out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_GUILTY;
>
> + if (adev->ras_enabled && con) {
> + /* Return the cached values in O(1),
> + * and schedule delayed work to cache
> + * new vaues.
> + */
> + int ce_count, ue_count;
> +
> + ce_count = atomic_read(>ras_ce_count);
> + ue_count = atomic_read(>ras_ue_count);
> +
> + if (ce_count != ctx->ras_counter_ce) {
> + ctx->ras_counter_ce = ce_count;
> +
Re: [PATCH v2 3/5] drm/amdgpu: switch to amdgpu_bo_vm for vm code
Am 26.05.21 um 15:06 schrieb Nirmoy Das:
The subclass, amdgpu_bo_vm is intended for PT/PD BOs which are also
shadowed, so switch to amdgpu_bo_vm BO for PT/PD BOs.
v2: squash three related patches.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 90 +
drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 16 ++--
2 files changed, 67 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 6bc7566cc193..80d50e6d75f9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -658,9 +658,9 @@ void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev,
ttm_bo_move_to_lru_tail(>tbo, >tbo.mem,
>lru_bulk_move);
- if (bo->shadow)
- ttm_bo_move_to_lru_tail(>shadow->tbo,
- >shadow->tbo.mem,
+ if (bo->tbo.type == ttm_bo_type_kernel)
+
ttm_bo_move_to_lru_tail(_amdgpu_bo_vm(bo)->shadow->tbo,
+
_amdgpu_bo_vm(bo)->shadow->tbo.mem,
Maybe use a local variable for the shadow BO here.
>lru_bulk_move);
}
spin_unlock(>mman.bdev.lru_lock);
@@ -696,8 +696,8 @@ int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev,
struct amdgpu_vm *vm,
r = validate(param, bo);
if (r)
return r;
- if (bo->shadow) {
- r = validate(param, bo->shadow);
+ if (bo->tbo.type == ttm_bo_type_kernel) {
+ r = validate(param, to_amdgpu_bo_vm(bo)->shadow);
if (r)
return r;
}
@@ -793,8 +793,9 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
if (r)
return r;
- if (bo->shadow) {
- r = ttm_bo_validate(>shadow->tbo, >shadow->placement,
+ if (bo->tbo.type == ttm_bo_type_kernel) {
+ r = ttm_bo_validate(_amdgpu_bo_vm(bo)->shadow->tbo,
+ _amdgpu_bo_vm(bo)->shadow->placement,
Same here.
);
if (r)
return r;
@@ -863,14 +864,17 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
* @vm: requesting vm
* @level: the page table level
* @immediate: use a immediate update
- * @bo: pointer to the buffer object pointer
+ * @vmbo: pointer to the buffer object pointer
*/
static int amdgpu_vm_pt_create(struct amdgpu_device *adev,
struct amdgpu_vm *vm,
int level, bool immediate,
- struct amdgpu_bo **bo)
+ struct amdgpu_bo_vm **vmbo)
{
struct amdgpu_bo_param bp;
+ struct amdgpu_bo *bo;
+ struct amdgpu_bo *shadow_bo;
+ struct dma_resv *resv;
int r;
memset(, 0, sizeof(bp));
@@ -881,7 +885,7 @@ static int amdgpu_vm_pt_create(struct amdgpu_device *adev,
bp.domain = amdgpu_bo_get_preferred_pin_domain(adev, bp.domain);
bp.flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
AMDGPU_GEM_CREATE_CPU_GTT_USWC;
- bp.bo_ptr_size = sizeof(struct amdgpu_bo);
+ bp.bo_ptr_size = sizeof(struct amdgpu_bo_vm);
if (vm->use_cpu_for_update)
bp.flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
@@ -890,26 +894,43 @@ static int amdgpu_vm_pt_create(struct amdgpu_device *adev,
if (vm->root.base.bo)
bp.resv = vm->root.base.bo->tbo.base.resv;
- r = amdgpu_bo_create(adev, , bo);
+ r = amdgpu_bo_create_vm(adev, , vmbo);
if (r)
return r;
+ bo = &(*vmbo)->bo;
if (vm->is_compute_context && (adev->flags & AMD_IS_APU))
return 0;
if (!bp.resv)
- WARN_ON(dma_resv_lock((*bo)->tbo.base.resv,
+ WARN_ON(dma_resv_lock(bo->tbo.base.resv,
NULL));
- r = amdgpu_bo_create_shadow(adev, bp.size, *bo);
+ resv = bp.resv;
Maybe shuffle that code around a bit, then you only need the resv
variable and no longer the bo variable.
+ memset(, 0, sizeof(bp));
+ bp.size = amdgpu_vm_bo_size(adev, level);
+ bp.domain = AMDGPU_GEM_DOMAIN_GTT;
+ bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
+ bp.type = ttm_bo_type_kernel;
+ bp.resv = bo->tbo.base.resv;
+ bp.bo_ptr_size = sizeof(struct amdgpu_bo);
- if (!bp.resv)
- dma_resv_unlock((*bo)->tbo.base.resv);
+ r = amdgpu_bo_create(adev, , _bo);
+
+
Remove the two empty lines here
+ if (!resv)
+ dma_resv_unlock(bo->tbo.base.resv);
if (r) {
-
Re: [PATCH 3/3] drm/amdgpu: Use delayed work to collect RAS error counters
On 2021-05-26 6:15 a.m., Christian König wrote:
> Am 26.05.21 um 02:40 schrieb Luben Tuikov:
>> On Context Query2 IOCTL return the correctable and
>> uncorrectable errors in O(1) fashion, from cached
>> values, and schedule a delayed work function to
>> calculate and cache them for the next such IOCTL.
>>
>> v2: Cancel pending delayed work at ras_fini().
>>
>> Cc: Alexander Deucher
>> Cc: Christian König
>> Cc: John Clements
>> Cc: Hawking Zhang
>> Signed-off-by: Luben Tuikov
>> ---
>> drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 32 +--
>> drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 41 +
>> drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 5 +++
>> 3 files changed, 76 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
>> index bb0cfe871aba..4e95d255960b 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
>> @@ -331,10 +331,13 @@ static int amdgpu_ctx_query(struct amdgpu_device *adev,
>> return 0;
>> }
>>
>> +#define AMDGPU_RAS_COUNTE_DELAY_MS 3000
>> +
>> static int amdgpu_ctx_query2(struct amdgpu_device *adev,
>> -struct amdgpu_fpriv *fpriv, uint32_t id,
>> -union drm_amdgpu_ctx_out *out)
>> + struct amdgpu_fpriv *fpriv, uint32_t id,
>> + union drm_amdgpu_ctx_out *out)
>> {
>> +struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
>> struct amdgpu_ctx *ctx;
>> struct amdgpu_ctx_mgr *mgr;
>>
>> @@ -361,6 +364,31 @@ static int amdgpu_ctx_query2(struct amdgpu_device *adev,
>> if (atomic_read(>guilty))
>> out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_GUILTY;
>>
>> +if (adev->ras_enabled && con) {
>> +/* Return the cached values in O(1),
>> + * and schedule delayed work to cache
>> + * new vaues.
>> + */
>> +int ce_count, ue_count;
>> +
>> +ce_count = atomic_read(>ras_ce_count);
>> +ue_count = atomic_read(>ras_ue_count);
>> +
>> +if (ce_count != ctx->ras_counter_ce) {
>> +ctx->ras_counter_ce = ce_count;
>> +out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RAS_CE;
>> +}
>> +
>> +if (ue_count != ctx->ras_counter_ue) {
>> +ctx->ras_counter_ue = ue_count;
>> +out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RAS_UE;
>> +}
>> +
>> +if (!delayed_work_pending(>ras_counte_delay_work))
>> +schedule_delayed_work(>ras_counte_delay_work,
>> + msecs_to_jiffies(AMDGPU_RAS_COUNTE_DELAY_MS));
> You can skip the delayed_work_pending() check here, if I'm not totally
> mistaken that is already integrated in the schedule_delayed_work() logic.
I'll take a look and if so I'll remove the check. I've remembered this check
from many
years ago--habit.
>
>> +}
>> +
>> mutex_unlock(>lock);
>> return 0;
>> }
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
>> index ed3c43e8b0b5..01114529040a 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
>> @@ -27,6 +27,7 @@
>> #include
>> #include
>> #include
>> +#include
>>
>> #include "amdgpu.h"
>> #include "amdgpu_ras.h"
>> @@ -2116,6 +2117,30 @@ static void amdgpu_ras_check_supported(struct
>> amdgpu_device *adev)
>> adev->ras_hw_enabled & amdgpu_ras_mask;
>> }
>>
>> +static void amdgpu_ras_counte_dw(struct work_struct *work)
>> +{
>> +struct amdgpu_ras *con = container_of(work, struct amdgpu_ras,
>> + ras_counte_delay_work.work);
>> +struct amdgpu_device *adev = con->adev;
>> +struct drm_device *dev = >ddev;
>> +unsigned long ce_count, ue_count;
>> +int res;
>> +
>> +res = pm_runtime_get_sync(dev->dev);
>> +if (res < 0)
>> +goto Out;
>> +
>> +/* Cache new values.
>> + */
>> +amdgpu_ras_query_error_count(adev, _count, _count);
>> +atomic_set(>ras_ce_count, ce_count);
>> +atomic_set(>ras_ue_count, ue_count);
>> +
>> +pm_runtime_mark_last_busy(dev->dev);
>> +Out:
>> +pm_runtime_put_autosuspend(dev->dev);
>> +}
>> +
>> int amdgpu_ras_init(struct amdgpu_device *adev)
>> {
>> struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
>> @@ -2130,6 +2155,11 @@ int amdgpu_ras_init(struct amdgpu_device *adev)
>> if (!con)
>> return -ENOMEM;
>>
>> +con->adev = adev;
>> +INIT_DELAYED_WORK(>ras_counte_delay_work, amdgpu_ras_counte_dw);
>> +atomic_set(>ras_ce_count, 0);
>> +atomic_set(>ras_ue_count, 0);
>> +
>> con->objs = (struct ras_manager *)(con + 1);
>>
>> amdgpu_ras_set_context(adev, con);
>> @@ -2233,6 +2263,8 @@ int
Re: [PATCH v2 2/5] drm/amdgpu: move shadow bo validation to VM code
Am 26.05.21 um 15:06 schrieb Nirmoy Das:
Do the shadow bo validation in the VM code as
VM code knows/owns shadow BOs.
v2: Fix a typo.
Signed-off-by: Nirmoy Das
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 23 ---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 5 +
2 files changed, 9 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 90136f9dedd6..f6a8f0c5a52f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -396,10 +396,10 @@ void amdgpu_cs_report_moved_bytes(struct amdgpu_device
*adev, u64 num_bytes,
spin_unlock(>mm_stats.lock);
}
-static int amdgpu_cs_bo_validate(struct amdgpu_cs_parser *p,
-struct amdgpu_bo *bo)
+static int amdgpu_cs_bo_validate(void *param, struct amdgpu_bo *bo)
{
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
+ struct amdgpu_cs_parser *p = param;
struct ttm_operation_ctx ctx = {
.interruptible = true,
.no_wait_gpu = false,
@@ -451,21 +451,6 @@ static int amdgpu_cs_bo_validate(struct amdgpu_cs_parser
*p,
return r;
}
-static int amdgpu_cs_validate(void *param, struct amdgpu_bo *bo)
-{
- struct amdgpu_cs_parser *p = param;
- int r;
-
- r = amdgpu_cs_bo_validate(p, bo);
- if (r)
- return r;
-
- if (bo->shadow)
- r = amdgpu_cs_bo_validate(p, bo->shadow);
-
- return r;
-}
-
static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
struct list_head *validated)
{
@@ -493,7 +478,7 @@ static int amdgpu_cs_list_validate(struct amdgpu_cs_parser
*p,
lobj->user_pages);
}
- r = amdgpu_cs_validate(p, bo);
+ r = amdgpu_cs_bo_validate(p, bo);
if (r)
return r;
@@ -593,7 +578,7 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
p->bytes_moved_vis = 0;
r = amdgpu_vm_validate_pt_bos(p->adev, >vm,
- amdgpu_cs_validate, p);
+ amdgpu_cs_bo_validate, p);
if (r) {
DRM_ERROR("amdgpu_vm_validate_pt_bos() failed.\n");
goto error_validate;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index da155c276c51..6bc7566cc193 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -696,6 +696,11 @@ int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev,
struct amdgpu_vm *vm,
r = validate(param, bo);
if (r)
return r;
+ if (bo->shadow) {
+ r = validate(param, bo->shadow);
+ if (r)
+ return r;
+ }
if (bo->tbo.type != ttm_bo_type_kernel) {
amdgpu_vm_bo_moved(bo_base);
--
2.31.1
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RE: [PATCH 00/15] DC Patches May 24th, 2021
[AMD Official Use Only] Done. Hi all, This week this patchset was tested on the following systems: HP Envy 360, with Ryzen 5 4500U, on the following display types: eDP 1080p 60hz, 4k 60hz (via USB-C to DP/HDMI), 1440p 144hz (via USB-C to DP/HDMI), 1680*1050 60hz (via USB-C to DP and then DP to DVI/VGA) Sapphire Pulse RX5700XT on the following display types: 4k 60hz (via DP/HDMI), 1440p 144hz (via DP/HDMI), 1680*1050 60hz (via DP to DVI/VGA) Reference AMD RX6800 on the following display types: 4k 60hz (via DP/HDMI and USB-C to DP/HDMI), 1440p 144hz (via USB-C to DP/HDMI and USB-C to DP/HDMI), 1680*1050 60hz (via DP to DVI/VGA) Included testing using a Startech DP 1.4 MST hub at 2x 4k 60hz, and 3x 1080p 60hz on all systems. Tested-by: Daniel Wheeler Thank you, Dan Wheeler Technologist | AMD SW Display -- 1 Commerce Valley Dr E, Thornhill, ON L3T 7X6 Facebook | Twitter | amd.com -Original Message- From: amd-gfx On Behalf Of Qingqing Zhuo Sent: May 21, 2021 1:37 PM To: amd-gfx@lists.freedesktop.org Cc: Brol, Eryk ; Li, Sun peng (Leo) ; Wentland, Harry ; Zhuo, Qingqing ; Siqueira, Rodrigo ; Li, Roman ; Jacob, Anson ; Pillai, Aurabindo ; Lakha, Bhawanpreet ; R, Bindu Subject: [PATCH 00/15] DC Patches May 24th, 2021 This DC patchset brings improvements in multiple areas. In summary, we highlight: - DC 3.2.137 - Updates on DP configurations and clock recovery API - Improvements on DSC, link training sequence, etc. - Fixes on memory leak, ODM scaling, etc. --- Alvin Lee (1): drm/amd/display: Implement INBOX0 usage in driver Aric Cyr (1): drm/amd/display: 3.2.137 Dmytro Laktyushkin (1): drm/amd/display: fix odm scaling Fangzhi Zuo (3): drm/amd/display: Retrieve DSC Branch Decoder Caps drm/amd/display: Add Log for SST DSC Determination Policy drm/amd/display: Refactor SST DSC Determination Policy Jake Wang (1): drm/amd/display: Added support for individual control for multiple back-light instances. Jimmy Kizito (2): drm/amd/display: Update DP link configuration. drm/amd/display: Expand DP module clock recovery API. Qingqing Zhuo (1): Revert "drm/amd/display: Refactor and add visual confirm for HW Flip Queue" Roman Li (2): drm/amd/display: Remove redundant safeguards for dmub-srv destroy() drm/amd/display: Fix potential memory leak in DMUB hw_init Wenjing Liu (2): drm/amd/display: add exit training mode and update channel coding in LT drm/amd/display: isolate 8b 10b link training sequence into its own function hvanzyll (1): drm/amd/display: disable desktop VRR when using older flip model .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 138 +++-- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 10 +- .../gpu/drm/amd/display/dc/core/dc_link_dp.c | 307 ++ .../gpu/drm/amd/display/dc/core/dc_resource.c | 568 +++--- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 9 + drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h | 2 + drivers/gpu/drm/amd/display/dc/dc_link.h | 19 +- drivers/gpu/drm/amd/display/dc/dc_stream.h| 3 + drivers/gpu/drm/amd/display/dc/dc_types.h | 5 - drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c | 10 +- .../drm/amd/display/dc/dce/dmub_hw_lock_mgr.c | 8 + .../drm/amd/display/dc/dce/dmub_hw_lock_mgr.h | 3 + .../drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c | 12 +- .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 31 +- .../amd/display/dc/dcn10/dcn10_hw_sequencer.h | 6 - .../gpu/drm/amd/display/dc/dcn10/dcn10_init.c | 1 - .../gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c | 5 - .../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 28 +- .../drm/amd/display/dc/dcn20/dcn20_hwseq.h| 5 - .../gpu/drm/amd/display/dc/dcn20/dcn20_init.c | 1 - .../gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c | 2 +- .../drm/amd/display/dc/dcn20/dcn20_resource.c | 14 +- .../gpu/drm/amd/display/dc/dcn21/dcn21_init.c | 1 - .../gpu/drm/amd/display/dc/dcn30/dcn30_init.c | 1 - .../gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c | 2 +- .../drm/amd/display/dc/dcn301/dcn301_init.c | 1 - .../amd/display/dc/dml/display_mode_structs.h | 2 + .../drm/amd/display/dc/dml/display_mode_vba.c | 13 + .../gpu/drm/amd/display/dc/inc/dc_link_dp.h | 66 +- drivers/gpu/drm/amd/display/dc/inc/hw/abm.h | 3 +- drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h | 3 - .../gpu/drm/amd/display/dc/inc/hw/transform.h | 4 - .../gpu/drm/amd/display/dc/inc/hw_sequencer.h | 4 - drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 1 + .../amd/display/include/link_service_types.h | 1 + .../amd/display/modules/freesync/freesync.c | 29 +- .../amd/display/modules/power/power_helpers.c | 15 +- .../amd/display/modules/power/power_helpers.h | 3 +- 39 files changed, 683 insertions(+), 655
[amdgpu] question about HWS pipe multiplexing mechanism
Hi! I learned that each pipe can manage multiple hardware queues from the previous discussion: https://lists.freedesktop.org/archives/amd-gfx/2018-February/019034.html . And I had a few questions about the details. I was wondering that how a pipe switches between the hardware queues belong to it: 1. Dose the pipe process a queue continuously until the queue is empty? Or Dose it use round-robin with time-sharing between those hardware queues? 2. If the former, is it possible that some hardware queues suffer from starvation? 3. The previous discussion said that, at the same time, only one kernel can be running on each pipe. If the pipe used round-robin, did it incur the "compute wave save/restore"(CWSR) when the pipe switch from a hardware queue that has a running kernel to another hardware queue? ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 2/2] drm/amdgpu/acpi: make ATPX/ATCS structures global (v2)
They are global ACPI methods, so maybe the structures
global in the driver. This simplified a number of things
in the handling of these methods.
v2: reset the handle if verify interface fails (Lijo)
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 9 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 288 --
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 1 +
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
4 files changed, 139 insertions(+), 161 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index c759d5a8a3a0..2c063c550101 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -268,8 +268,6 @@ struct amdgpu_job;
struct amdgpu_irq_src;
struct amdgpu_fpriv;
struct amdgpu_bo_va_mapping;
-struct amdgpu_atif;
-struct amdgpu_atcs;
struct kfd_vm_fault_info;
struct amdgpu_hive_info;
struct amdgpu_reset_context;
@@ -812,8 +810,6 @@ struct amdgpu_device {
struct notifier_block acpi_nb;
struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
struct debugfs_blob_wrapper debugfs_vbios_blob;
- struct amdgpu_atif *atif;
- struct amdgpu_atcs *atcs;
struct mutexsrbm_mutex;
/* GRBM index mutex. Protects concurrent access to GRBM index */
struct mutexgrbm_idx_mutex;
@@ -1348,13 +1344,14 @@ int amdgpu_acpi_pcie_performance_request(struct
amdgpu_device *adev,
u8 perf_req, bool advertise);
int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
-void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev,
- struct amdgpu_dm_backlight_caps *caps);
+void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps);
bool amdgpu_acpi_is_s0ix_supported(struct amdgpu_device *adev);
+void amdgpu_acpi_detect(void);
#else
static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
static inline bool amdgpu_acpi_is_s0ix_supported(struct amdgpu_device *adev) {
return false; }
+void amdgpu_acpi_detect(void) { }
#endif
int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
index df216d12c507..5caa54ed6662 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
@@ -85,6 +85,11 @@ struct amdgpu_atcs {
struct amdgpu_atcs_functions functions;
};
+static struct amdgpu_acpi_priv {
+ struct amdgpu_atif atif;
+ struct amdgpu_atcs atcs;
+} amdgpu_acpi_priv;
+
/* Call the ATIF method
*/
/**
@@ -221,62 +226,6 @@ static int amdgpu_atif_verify_interface(struct amdgpu_atif
*atif)
return err;
}
-static acpi_handle amdgpu_atif_probe_handle(acpi_handle dhandle)
-{
- acpi_handle handle = NULL;
- char acpi_method_name[255] = { 0 };
- struct acpi_buffer buffer = { sizeof(acpi_method_name),
acpi_method_name };
- acpi_status status;
-
- /* For PX/HG systems, ATIF and ATPX are in the iGPU's namespace, on
dGPU only
-* systems, ATIF is in the dGPU's namespace.
-*/
- if (amdgpu_has_atpx()) {
- status = acpi_get_handle(amdgpu_atpx_get_dhandle(), "ATIF",
-);
- if (ACPI_SUCCESS(status))
- goto out;
- }
- status = acpi_get_handle(dhandle, "ATIF", );
- if (ACPI_SUCCESS(status))
- goto out;
-
- DRM_DEBUG_DRIVER("No ATIF handle found\n");
- return NULL;
-out:
- acpi_get_name(handle, ACPI_FULL_PATHNAME, );
- DRM_DEBUG_DRIVER("Found ATIF handle %s\n", acpi_method_name);
- return handle;
-}
-
-static acpi_handle amdgpu_atcs_probe_handle(acpi_handle dhandle)
-{
- acpi_handle handle = NULL;
- char acpi_method_name[255] = { 0 };
- struct acpi_buffer buffer = { sizeof(acpi_method_name),
acpi_method_name };
- acpi_status status;
-
- /* For PX/HG systems, ATCS and ATPX are in the iGPU's namespace, on
dGPU only
-* systems, ATIF is in the dGPU's namespace.
-*/
- if (amdgpu_has_atpx()) {
- status = acpi_get_handle(amdgpu_atpx_get_dhandle(), "ATCS",
-);
- if (ACPI_SUCCESS(status))
- goto out;
- }
- status = acpi_get_handle(dhandle, "ATCS", );
- if (ACPI_SUCCESS(status))
- goto out;
-
- DRM_DEBUG_DRIVER("No ATCS handle found\n");
- return NULL;
-out:
- acpi_get_name(handle, ACPI_FULL_PATHNAME, );
- DRM_DEBUG_DRIVER("Found ATCS handle %s\n", acpi_method_name);
- return handle;
-}
-
/**
*
[PATCH 1/2] drm/amdgpu/acpi: fix typo in ATCS handling
Path should be NULL when we already have the handle
to the object.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
index 49563ff87f1a..df216d12c507 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
@@ -558,7 +558,7 @@ static union acpi_object *amdgpu_atcs_call(struct
amdgpu_atcs *atcs,
atcs_arg_elements[1].integer.value = 0;
}
- status = acpi_evaluate_object(atcs->handle, "ATCS", _arg, );
+ status = acpi_evaluate_object(atcs->handle, NULL, _arg, );
/* Fail only if calling the method fails and ATIF is supported */
if (ACPI_FAILURE(status) && status != AE_NOT_FOUND) {
--
2.31.1
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Re: [PATCH RESEND] amd/display: convert DRM_DEBUG_ATOMIC to drm_dbg_atomic
Reviewed-by: Bas Nieuwenhuizen
I think there are plenty more occurrences too or did I miss the
cleanup of those?
On Wed, May 26, 2021 at 3:56 PM Simon Ser wrote:
>
> This allows to tie the log message to a specific DRM device.
>
> Signed-off-by: Simon Ser
> Cc: Alex Deucher
> Cc: Harry Wentland
> Cc: Nicholas Kazlauskas
> ---
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 2c9d099adfc2..4dd811816cba 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -10089,7 +10089,7 @@ static int dm_check_crtc_cursor(struct
> drm_atomic_state *state,
>
> if (cursor_scale_w != primary_scale_w ||
> cursor_scale_h != primary_scale_h) {
> - DRM_DEBUG_ATOMIC("Cursor plane scaling doesn't match primary
> plane\n");
> + drm_dbg_atomic(crtc->dev, "Cursor plane scaling doesn't match
> primary plane\n");
> return -EINVAL;
> }
>
> --
> 2.31.1
>
>
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Re: [PATCH] drm/amdgpu: Fix clang warning: unused label 'exit'
Am 25.05.21 um 20:44 schrieb Andrey Grodzovsky: Problem: drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:332:1: warning: unused label 'exit' [-Wunused-label] exit: ^ Fix: Put #ifdef CONFIG_64BIT around exit Reported-by: kernel test robot Signed-off-by: Andrey Grodzovsky Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index c547c78f3513..a10b4a7ccf5d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -330,7 +330,9 @@ void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, } spin_unlock_irqrestore(>mmio_idx_lock, flags); +#ifdef CONFIG_64BIT exit: +#endif drm_dev_exit(idx); } ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu: Don't flush HDP on A+A
Am 25.05.21 um 19:56 schrieb Eric Huang:
With XGMI connection flushing HDP on PCIe is unnecessary,
it is also to optimize memory allocation latency.
Signed-off-by: Eric Huang
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c
index ac45d9c7a4e9..aefb3d2927d5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c
@@ -108,6 +108,8 @@ static int amdgpu_vm_cpu_update(struct
amdgpu_vm_update_params *p,
static int amdgpu_vm_cpu_commit(struct amdgpu_vm_update_params *p,
struct dma_fence **fence)
{
+ if (p->adev->gmc.xgmi.connected_to_cpu)
+ return 0;
You still need at least the memory barrier and I suggest to add a common
flag/function to check if HDP flushing is needed or not.
We also have a bunch of cases in the IB submission code as well.
Christian.
/* Flush HDP */
mb();
amdgpu_asic_flush_hdp(p->adev, NULL);
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[PATCH RESEND] amd/display: convert DRM_DEBUG_ATOMIC to drm_dbg_atomic
This allows to tie the log message to a specific DRM device.
Signed-off-by: Simon Ser
Cc: Alex Deucher
Cc: Harry Wentland
Cc: Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 2c9d099adfc2..4dd811816cba 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -10089,7 +10089,7 @@ static int dm_check_crtc_cursor(struct drm_atomic_state
*state,
if (cursor_scale_w != primary_scale_w ||
cursor_scale_h != primary_scale_h) {
- DRM_DEBUG_ATOMIC("Cursor plane scaling doesn't match primary
plane\n");
+ drm_dbg_atomic(crtc->dev, "Cursor plane scaling doesn't match
primary plane\n");
return -EINVAL;
}
--
2.31.1
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Re: [PATCH] drm/amdgpu: Don't flush HDP on A+A
Am 2021-05-25 um 1:56 p.m. schrieb Eric Huang:
> With XGMI connection flushing HDP on PCIe is unnecessary,
> it is also to optimize memory allocation latency.
>
> Signed-off-by: Eric Huang
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c
> index ac45d9c7a4e9..aefb3d2927d5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c
> @@ -108,6 +108,8 @@ static int amdgpu_vm_cpu_update(struct
> amdgpu_vm_update_params *p,
> static int amdgpu_vm_cpu_commit(struct amdgpu_vm_update_params *p,
> struct dma_fence **fence)
> {
> + if (p->adev->gmc.xgmi.connected_to_cpu)
> + return 0;
I wonder if this check should be inside hdp_v4_0_flush_hdp instead so it
catches all unnecessary HDP flushing. On the other hand, that would
still leave the mb(). But that mb() is probably needed anyway to ensure
that the GPU will see any previous memory writes.
Regards,
Felix
> /* Flush HDP */
> mb();
> amdgpu_asic_flush_hdp(p->adev, NULL);
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[PATCH 5/5] drm/amdgpu: do not allocate entries separately
Allocate PD/PT entries while allocating VM BOs and use that
instead of allocating those entries separately.
v2: create a new var for num entries.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 34 +++---
1 file changed, 20 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 80d50e6d75f9..de9dd882ecdc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -876,6 +876,7 @@ static int amdgpu_vm_pt_create(struct amdgpu_device *adev,
struct amdgpu_bo *shadow_bo;
struct dma_resv *resv;
int r;
+ unsigned int num_entries;
memset(, 0, sizeof(bp));
@@ -885,7 +886,14 @@ static int amdgpu_vm_pt_create(struct amdgpu_device *adev,
bp.domain = amdgpu_bo_get_preferred_pin_domain(adev, bp.domain);
bp.flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
AMDGPU_GEM_CREATE_CPU_GTT_USWC;
- bp.bo_ptr_size = sizeof(struct amdgpu_bo_vm);
+
+ if (level < AMDGPU_VM_PTB)
+ num_entries = amdgpu_vm_num_entries(adev, level);
+ else
+ num_entries = 0;
+
+ bp.bo_ptr_size = struct_size((*vmbo), entries, num_entries);
+
if (vm->use_cpu_for_update)
bp.flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
@@ -958,19 +966,14 @@ static int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
struct amdgpu_bo_vm *pt;
int r;
- if (cursor->level < AMDGPU_VM_PTB && !entry->entries) {
- unsigned num_entries;
-
- num_entries = amdgpu_vm_num_entries(adev, cursor->level);
- entry->entries = kvmalloc_array(num_entries,
- sizeof(*entry->entries),
- GFP_KERNEL | __GFP_ZERO);
- if (!entry->entries)
- return -ENOMEM;
- }
-
- if (entry->base.bo)
+ if (entry->base.bo) {
+ if (cursor->level < AMDGPU_VM_PTB)
+ entry->entries =
+ to_amdgpu_bo_vm(entry->base.bo)->entries;
+ else
+ entry->entries = NULL;
return 0;
+ }
r = amdgpu_vm_pt_create(adev, vm, cursor->level, immediate, );
if (r)
@@ -982,6 +985,10 @@ static int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
pt_bo = >bo;
pt_bo->parent = amdgpu_bo_ref(cursor->parent->base.bo);
amdgpu_vm_bo_base_init(>base, vm, pt_bo);
+ if (cursor->level < AMDGPU_VM_PTB)
+ entry->entries = pt->entries;
+ else
+ entry->entries = NULL;
r = amdgpu_vm_clear_bo(adev, vm, pt_bo, immediate);
if (r)
@@ -1009,7 +1016,6 @@ static void amdgpu_vm_free_table(struct amdgpu_vm_pt
*entry)
amdgpu_bo_unref(_amdgpu_bo_vm(entry->base.bo)->shadow);
amdgpu_bo_unref(>base.bo);
}
- kvfree(entry->entries);
entry->entries = NULL;
}
--
2.31.1
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[PATCH v2 4/5] drm/amdgpu: remove unused code
Remove unused code related to shadow BO.
v2: removing shadow bo ptr from base class.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 29 --
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 6 -
2 files changed, 35 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 6870cc297ae6..7930b7d9a3b1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -638,35 +638,6 @@ int amdgpu_bo_create(struct amdgpu_device *adev,
return r;
}
-int amdgpu_bo_create_shadow(struct amdgpu_device *adev,
- unsigned long size,
- struct amdgpu_bo *bo)
-{
- struct amdgpu_bo_param bp;
- int r;
-
- if (bo->shadow)
- return 0;
-
- memset(, 0, sizeof(bp));
- bp.size = size;
- bp.domain = AMDGPU_GEM_DOMAIN_GTT;
- bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
- bp.type = ttm_bo_type_kernel;
- bp.resv = bo->tbo.base.resv;
- bp.bo_ptr_size = sizeof(struct amdgpu_bo);
-
- r = amdgpu_bo_create(adev, , >shadow);
- if (!r) {
- bo->shadow->parent = amdgpu_bo_ref(bo);
- mutex_lock(>shadow_list_lock);
- list_add_tail(>shadow->shadow_list, >shadow_list);
- mutex_unlock(>shadow_list_lock);
- }
-
- return r;
-}
-
/**
* amdgpu_bo_create_user - create an _bo_user buffer object
* @adev: amdgpu device object
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
index a7fbf5f7051e..07478f86f05a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
@@ -104,9 +104,6 @@ struct amdgpu_bo {
struct amdgpu_vm_bo_base*vm_bo;
/* Constant after initialization */
struct amdgpu_bo*parent;
- struct amdgpu_bo*shadow;
-
-
#ifdef CONFIG_MMU_NOTIFIER
struct mmu_interval_notifiernotifier;
@@ -284,9 +281,6 @@ int amdgpu_bo_create_vm(struct amdgpu_device *adev,
struct amdgpu_bo_vm **ubo_ptr);
void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,
void **cpu_addr);
-int amdgpu_bo_create_shadow(struct amdgpu_device *adev,
- unsigned long size,
- struct amdgpu_bo *bo);
int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr);
void *amdgpu_bo_kptr(struct amdgpu_bo *bo);
void amdgpu_bo_kunmap(struct amdgpu_bo *bo);
--
2.31.1
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[PATCH v2 2/5] drm/amdgpu: move shadow bo validation to VM code
Do the shadow bo validation in the VM code as
VM code knows/owns shadow BOs.
v2: Fix a typo.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 23 ---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 5 +
2 files changed, 9 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 90136f9dedd6..f6a8f0c5a52f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -396,10 +396,10 @@ void amdgpu_cs_report_moved_bytes(struct amdgpu_device
*adev, u64 num_bytes,
spin_unlock(>mm_stats.lock);
}
-static int amdgpu_cs_bo_validate(struct amdgpu_cs_parser *p,
-struct amdgpu_bo *bo)
+static int amdgpu_cs_bo_validate(void *param, struct amdgpu_bo *bo)
{
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
+ struct amdgpu_cs_parser *p = param;
struct ttm_operation_ctx ctx = {
.interruptible = true,
.no_wait_gpu = false,
@@ -451,21 +451,6 @@ static int amdgpu_cs_bo_validate(struct amdgpu_cs_parser
*p,
return r;
}
-static int amdgpu_cs_validate(void *param, struct amdgpu_bo *bo)
-{
- struct amdgpu_cs_parser *p = param;
- int r;
-
- r = amdgpu_cs_bo_validate(p, bo);
- if (r)
- return r;
-
- if (bo->shadow)
- r = amdgpu_cs_bo_validate(p, bo->shadow);
-
- return r;
-}
-
static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
struct list_head *validated)
{
@@ -493,7 +478,7 @@ static int amdgpu_cs_list_validate(struct amdgpu_cs_parser
*p,
lobj->user_pages);
}
- r = amdgpu_cs_validate(p, bo);
+ r = amdgpu_cs_bo_validate(p, bo);
if (r)
return r;
@@ -593,7 +578,7 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
p->bytes_moved_vis = 0;
r = amdgpu_vm_validate_pt_bos(p->adev, >vm,
- amdgpu_cs_validate, p);
+ amdgpu_cs_bo_validate, p);
if (r) {
DRM_ERROR("amdgpu_vm_validate_pt_bos() failed.\n");
goto error_validate;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index da155c276c51..6bc7566cc193 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -696,6 +696,11 @@ int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev,
struct amdgpu_vm *vm,
r = validate(param, bo);
if (r)
return r;
+ if (bo->shadow) {
+ r = validate(param, bo->shadow);
+ if (r)
+ return r;
+ }
if (bo->tbo.type != ttm_bo_type_kernel) {
amdgpu_vm_bo_moved(bo_base);
--
2.31.1
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[PATCH 1/5] drm/amdgpu: add amdgpu_bo_vm bo type
Add new BO subclass that will be used by amdgpu vm code.
Signed-off-by: Nirmoy Das
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 32 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 10 +++
2 files changed, 42 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 3f85ba8222ef..6870cc297ae6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -694,6 +694,38 @@ int amdgpu_bo_create_user(struct amdgpu_device *adev,
*ubo_ptr = to_amdgpu_bo_user(bo_ptr);
return r;
}
+
+/**
+ * amdgpu_bo_create_vm - create an _bo_vm buffer object
+ * @adev: amdgpu device object
+ * @bp: parameters to be used for the buffer object
+ * @vmbo_ptr: pointer to the buffer object pointer
+ *
+ * Create a BO to be for GPUVM.
+ *
+ * Returns:
+ * 0 for success or a negative error code on failure.
+ */
+
+int amdgpu_bo_create_vm(struct amdgpu_device *adev,
+ struct amdgpu_bo_param *bp,
+ struct amdgpu_bo_vm **vmbo_ptr)
+{
+ struct amdgpu_bo *bo_ptr;
+ int r;
+
+ /* bo_ptr_size will be determined by the caller and it depends on
+* num of amdgpu_vm_pt entries.
+*/
+ BUG_ON(bp->bo_ptr_size < sizeof(struct amdgpu_bo_vm));
+ r = amdgpu_bo_create(adev, bp, _ptr);
+ if (r)
+ return r;
+
+ *vmbo_ptr = to_amdgpu_bo_vm(bo_ptr);
+ return r;
+}
+
/**
* amdgpu_bo_validate - validate an _bo buffer object
* @bo: pointer to the buffer object
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
index 11480c5a2716..a7fbf5f7051e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
@@ -44,6 +44,7 @@
#define AMDGPU_AMDKFD_CREATE_SVM_BO(1ULL << 62)
#define to_amdgpu_bo_user(abo) container_of((abo), struct amdgpu_bo_user, bo)
+#define to_amdgpu_bo_vm(abo) container_of((abo), struct amdgpu_bo_vm, bo)
struct amdgpu_bo_param {
unsigned long size;
@@ -125,6 +126,12 @@ struct amdgpu_bo_user {
};
+struct amdgpu_bo_vm {
+ struct amdgpu_bobo;
+ struct amdgpu_bo*shadow;
+ struct amdgpu_vm_pt entries[];
+};
+
static inline struct amdgpu_bo *ttm_to_amdgpu_bo(struct ttm_buffer_object *tbo)
{
return container_of(tbo, struct amdgpu_bo, tbo);
@@ -272,6 +279,9 @@ int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev,
int amdgpu_bo_create_user(struct amdgpu_device *adev,
struct amdgpu_bo_param *bp,
struct amdgpu_bo_user **ubo_ptr);
+int amdgpu_bo_create_vm(struct amdgpu_device *adev,
+ struct amdgpu_bo_param *bp,
+ struct amdgpu_bo_vm **ubo_ptr);
void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,
void **cpu_addr);
int amdgpu_bo_create_shadow(struct amdgpu_device *adev,
--
2.31.1
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[PATCH v2 3/5] drm/amdgpu: switch to amdgpu_bo_vm for vm code
The subclass, amdgpu_bo_vm is intended for PT/PD BOs which are also
shadowed, so switch to amdgpu_bo_vm BO for PT/PD BOs.
v2: squash three related patches.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 90 +
drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 16 ++--
2 files changed, 67 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 6bc7566cc193..80d50e6d75f9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -658,9 +658,9 @@ void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev,
ttm_bo_move_to_lru_tail(>tbo, >tbo.mem,
>lru_bulk_move);
- if (bo->shadow)
- ttm_bo_move_to_lru_tail(>shadow->tbo,
- >shadow->tbo.mem,
+ if (bo->tbo.type == ttm_bo_type_kernel)
+
ttm_bo_move_to_lru_tail(_amdgpu_bo_vm(bo)->shadow->tbo,
+
_amdgpu_bo_vm(bo)->shadow->tbo.mem,
>lru_bulk_move);
}
spin_unlock(>mman.bdev.lru_lock);
@@ -696,8 +696,8 @@ int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev,
struct amdgpu_vm *vm,
r = validate(param, bo);
if (r)
return r;
- if (bo->shadow) {
- r = validate(param, bo->shadow);
+ if (bo->tbo.type == ttm_bo_type_kernel) {
+ r = validate(param, to_amdgpu_bo_vm(bo)->shadow);
if (r)
return r;
}
@@ -793,8 +793,9 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
if (r)
return r;
- if (bo->shadow) {
- r = ttm_bo_validate(>shadow->tbo, >shadow->placement,
+ if (bo->tbo.type == ttm_bo_type_kernel) {
+ r = ttm_bo_validate(_amdgpu_bo_vm(bo)->shadow->tbo,
+ _amdgpu_bo_vm(bo)->shadow->placement,
);
if (r)
return r;
@@ -863,14 +864,17 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
* @vm: requesting vm
* @level: the page table level
* @immediate: use a immediate update
- * @bo: pointer to the buffer object pointer
+ * @vmbo: pointer to the buffer object pointer
*/
static int amdgpu_vm_pt_create(struct amdgpu_device *adev,
struct amdgpu_vm *vm,
int level, bool immediate,
- struct amdgpu_bo **bo)
+ struct amdgpu_bo_vm **vmbo)
{
struct amdgpu_bo_param bp;
+ struct amdgpu_bo *bo;
+ struct amdgpu_bo *shadow_bo;
+ struct dma_resv *resv;
int r;
memset(, 0, sizeof(bp));
@@ -881,7 +885,7 @@ static int amdgpu_vm_pt_create(struct amdgpu_device *adev,
bp.domain = amdgpu_bo_get_preferred_pin_domain(adev, bp.domain);
bp.flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
AMDGPU_GEM_CREATE_CPU_GTT_USWC;
- bp.bo_ptr_size = sizeof(struct amdgpu_bo);
+ bp.bo_ptr_size = sizeof(struct amdgpu_bo_vm);
if (vm->use_cpu_for_update)
bp.flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
@@ -890,26 +894,43 @@ static int amdgpu_vm_pt_create(struct amdgpu_device *adev,
if (vm->root.base.bo)
bp.resv = vm->root.base.bo->tbo.base.resv;
- r = amdgpu_bo_create(adev, , bo);
+ r = amdgpu_bo_create_vm(adev, , vmbo);
if (r)
return r;
+ bo = &(*vmbo)->bo;
if (vm->is_compute_context && (adev->flags & AMD_IS_APU))
return 0;
if (!bp.resv)
- WARN_ON(dma_resv_lock((*bo)->tbo.base.resv,
+ WARN_ON(dma_resv_lock(bo->tbo.base.resv,
NULL));
- r = amdgpu_bo_create_shadow(adev, bp.size, *bo);
+ resv = bp.resv;
+ memset(, 0, sizeof(bp));
+ bp.size = amdgpu_vm_bo_size(adev, level);
+ bp.domain = AMDGPU_GEM_DOMAIN_GTT;
+ bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
+ bp.type = ttm_bo_type_kernel;
+ bp.resv = bo->tbo.base.resv;
+ bp.bo_ptr_size = sizeof(struct amdgpu_bo);
- if (!bp.resv)
- dma_resv_unlock((*bo)->tbo.base.resv);
+ r = amdgpu_bo_create(adev, , _bo);
+
+
+ if (!resv)
+ dma_resv_unlock(bo->tbo.base.resv);
if (r) {
- amdgpu_bo_unref(bo);
+ amdgpu_bo_unref();
return r;
}
+ shadow_bo->parent = amdgpu_bo_ref(bo);
+ mutex_lock(>shadow_list_lock);
+ list_add_tail(_bo->shadow_list, >shadow_list);
+
Re: [PATCH] drm/amd/pm: retain the fine grain tuning parameters after resume
On Wed, May 26, 2021 at 4:06 AM Xiaojian Du wrote:
>
> This patch is to retain the fine grain tuning parameters after resume for
> legacy APU, it will cover Raven/Raven2/Picasso.
>
> Signed-off-by: Xiaojian Du
> ---
> .../amd/pm/powerplay/hwmgr/hardwaremanager.c | 3 ++-
> .../drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c | 21 +++
> 2 files changed, 23 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/hardwaremanager.c
> b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/hardwaremanager.c
> index 25b5831a15cd..370deae7b054 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/hardwaremanager.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/hardwaremanager.c
> @@ -82,7 +82,8 @@ int phm_enable_dynamic_state_management(struct pp_hwmgr
> *hwmgr)
>
> /* Skip for suspend/resume case */
> if (!hwmgr->pp_one_vf && smum_is_dpm_running(hwmgr)
> - && !amdgpu_passthrough(adev) && adev->in_suspend) {
> + && !amdgpu_passthrough(adev) && adev->in_suspend
> + && !adev->apu_flags) {
Might be clearer to check (asic_type != CHIP_RAVEN) here rather than
apu_flags. Makes it more clear what you are checking for. With that
fixed,
Reviewed-by: Alex Deucher
Alex
> pr_info("dpm has been enabled\n");
> return 0;
> }
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
> b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
> index f5fe540cd536..8f71f6a4bb49 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
> @@ -377,6 +377,27 @@ static int smu10_enable_gfx_off(struct pp_hwmgr *hwmgr)
>
> static int smu10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
> {
> + struct amdgpu_device *adev = hwmgr->adev;
> + struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr
> *)(hwmgr->backend);
> + int ret = -EINVAL;
> +
> + if (adev->in_suspend) {
> + pr_info("restore the fine grain parameters\n");
> +
> + ret = smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetHardMinGfxClk,
> + smu10_data->gfx_actual_soft_min_freq,
> + NULL);
> + if (ret)
> + return ret;
> + ret = smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetSoftMaxGfxClk,
> + smu10_data->gfx_actual_soft_max_freq,
> + NULL);
> + if (ret)
> + return ret;
> + }
> +
> return 0;
> }
>
> --
> 2.25.1
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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Re: radeon ring 0 test failed on arm64
On 2021-05-26 10:42, Christian König wrote: Hi Robin, Am 25.05.21 um 22:09 schrieb Robin Murphy: On 2021-05-25 14:05, Alex Deucher wrote: On Tue, May 25, 2021 at 8:56 AM Peter Geis wrote: On Tue, May 25, 2021 at 8:47 AM Alex Deucher wrote: On Tue, May 25, 2021 at 8:42 AM Peter Geis wrote: Good Evening, I am stress testing the pcie controller on the rk3566-quartz64 prototype SBC. This device has 1GB available at <0x3 0x> for the PCIe controller, which makes a dGPU theoretically possible. While attempting to light off a HD7570 card I manage to get a modeset console, but ring0 test fails and disables acceleration. Note, we do not have UEFI, so all PCIe setup is from the Linux kernel. Any insight you can provide would be much appreciated. Does your platform support PCIe cache coherency with the CPU? I.e., does the CPU allow cache snoops from PCIe devices? That is required for the driver to operate. Ah, most likely not. This issue has come up already as the GIC isn't permitted to snoop on the CPUs, so I doubt the PCIe controller can either. Is there no way to work around this or is it dead in the water? It's required by the pcie spec. You could potentially work around it if you can allocate uncached memory for DMA, but I don't think that is possible currently. Ideally we'd figure out some way to detect if a particular platform supports cache snooping or not as well. There's device_get_dma_attr(), although I don't think it will work currently for PCI devices without an OF or ACPI node - we could perhaps do with a PCI-specific wrapper which can walk up and defer to the host bridge's firmware description as necessary. The common DMA ops *do* correctly keep track of per-device coherency internally, but drivers aren't supposed to be poking at that information directly. That sounds like you underestimate the problem. ARM has unfortunately made the coherency for PCI an optional IP. Sorry to be that guy, but I'm involved a lot internally with our system IP and interconnect, and I probably understand the situation better than 99% of the community ;) For the record, the SBSA specification (the closet thing we have to a "system architecture") does require that PCIe is integrated in an I/O-coherent manner, but we don't have any control over what people do in embedded applications (note that we don't make PCIe IP at all, and there is plenty of 3rd-party interconnect IP). So we are talking about a hardware limitation which potentially can't be fixed without replacing the hardware. You expressed interest in "some way to detect if a particular platform supports cache snooping or not", by which I assumed you meant a software method for the amdgpu/radeon drivers to call, rather than, say, a website that driver maintainers can look up SoC names on. I'm saying that that API already exists (just may need a bit more work). Note that it is emphatically not a platform-level thing since coherency can and does vary per device within a system. I wasn't suggesting that Linux could somehow make coherency magically work when the signals don't physically exist in the interconnect - I was assuming you'd merely want to do something like throw a big warning and taint the kernel to help triage bug reports. Some drivers like ahci_qoriq and panfrost simply need to know so they can program their device to emit the appropriate memory attributes either way, and rely on the DMA API to hide the rest of the difference, but if you want to treat non-coherent use as unsupported because it would require too invasive changes that's fine by me. Robin. ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 15/34] drm/amd/display/dc/dce110/dce110_hw_sequencer: Include our own header
Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_hw_sequencer.c:927:6: warning: no previous prototype for ‘dce110_edp_wait_for_T12’ [-Wmissing-prototypes] Cc: Harry Wentland Cc: Leo Li Cc: Alex Deucher Cc: "Christian König" Cc: David Airlie Cc: Daniel Vetter Cc: amd-gfx@lists.freedesktop.org Cc: dri-de...@lists.freedesktop.org Signed-off-by: Lee Jones --- drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 5ddeee96bf235..9219db79f32b6 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -63,6 +63,8 @@ #include "atomfirmware.h" +#include "dce110_hw_sequencer.h" + #define GAMMA_HW_POINTS_NUM 256 /* -- 2.31.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 08/34] drm/amd/display/dc/bios/command_table_helper: Fix function name for 'dal_cmd_table_helper_transmitter_bp_to_atom()'
Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/../display/dc/bios/command_table_helper.c:127: warning: expecting prototype for translate_transmitter_bp_to_atom(). Prototype was for dal_cmd_table_helper_transmitter_bp_to_atom() instead Cc: Harry Wentland Cc: Leo Li Cc: Alex Deucher Cc: "Christian König" Cc: David Airlie Cc: Daniel Vetter Cc: Lee Jones Cc: amd-gfx@lists.freedesktop.org Cc: dri-de...@lists.freedesktop.org Signed-off-by: Lee Jones --- drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c index 5b77251e05909..e317a36151477 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c @@ -114,7 +114,7 @@ bool dal_cmd_table_helper_controller_id_to_atom( } /** - * translate_transmitter_bp_to_atom - Translate the Transmitter to the + * dal_cmd_table_helper_transmitter_bp_to_atom - Translate the Transmitter to the *corresponding ATOM BIOS value * @t: transmitter * returns: output digitalTransmitter -- 2.31.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 13/34] drm/amd/display/dc/dce/dmub_outbox: Convert over to kernel-doc
Fixes the following W=1 kernel build warning(s):
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dmub_outbox.c:30: warning: Cannot
understand
*
Cc: Harry Wentland
Cc: Leo Li
Cc: Alex Deucher
Cc: "Christian König"
Cc: David Airlie
Cc: Daniel Vetter
Cc: Rodrigo Siqueira
Cc: Meenakshikumar Somasundaram
Cc: Jun Lei
Cc: amd-gfx@lists.freedesktop.org
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Lee Jones
---
.../gpu/drm/amd/display/dc/dce/dmub_outbox.c| 17 -
1 file changed, 4 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_outbox.c
b/drivers/gpu/drm/amd/display/dc/dce/dmub_outbox.c
index 295596d1f47f2..faad8555ddbb6 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_outbox.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_outbox.c
@@ -27,19 +27,10 @@
#include "dmub/inc/dmub_cmd.h"
/**
- *
- * Function: dmub_enable_outbox_notification
- *
- * @brief
- * Sends inbox cmd to dmub to enable outbox1 messages with
interrupt.
- * Dmub sends outbox1 message and triggers outbox1 interrupt.
- *
- * @param
- * [in] dc: dc structure
- *
- * @return
- * None
- *
+ * dmub_enable_outbox_notification - Sends inbox cmd to dmub to enable outbox1
+ *messages with interrupt. Dmub sends
outbox1
+ *message and triggers outbox1 interrupt.
+ * @dc: dc structure
*/
void dmub_enable_outbox_notification(struct dc *dc)
{
--
2.31.1
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[PATCH 21/34] drm/amd/display/dc/dce110/dce110_hw_sequencer: Include header containing our prototypes
Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_hw_sequencer.c:929:6: warning: no previous prototype for ‘dce110_edp_wait_for_T12’ [-Wmissing-prototypes] Cc: Harry Wentland Cc: Leo Li Cc: Alex Deucher Cc: "Christian König" Cc: David Airlie Cc: Daniel Vetter Cc: amd-gfx@lists.freedesktop.org Cc: dri-de...@lists.freedesktop.org Signed-off-by: Lee Jones --- drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 9219db79f32b6..1ef1b1b33fb09 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -64,6 +64,7 @@ #include "atomfirmware.h" #include "dce110_hw_sequencer.h" +#include "dcn10/dcn10_hw_sequencer.h" #define GAMMA_HW_POINTS_NUM 256 -- 2.31.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 16/34] drm/amd/display/dc/dce/dce_transform: Remove superfluous re-initialisation of DCFE_MEM_LIGHT_SLEEP_CNTL,
Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/../display/modules/hdcp/hdcp_psp.c:374:22: warning: no previous prototype for ‘mod_hdcp_hdcp1_get_link_encryption_status’ In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:28: drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dce/dce_6_0_d.h:568:43: warning: initialized field overwritten [-Woverride-init] drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:157:14: note: in expansion of macro ‘mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL’ drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_transform.h:170:2: note: in expansion of macro ‘SRI’ drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:183:3: note: in expansion of macro ‘XFM_COMMON_REG_LIST_DCE60’ drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:187:3: note: in expansion of macro ‘transform_regs’ drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dce/dce_6_0_d.h:568:43: note: (near initialization for ‘xfm_regs[0].DCFE_MEM_LIGHT_SLEEP_CNTL’) drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:157:14: note: in expansion of macro ‘mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL’ drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_transform.h:170:2: note: in expansion of macro ‘SRI’ drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:183:3: note: in expansion of macro ‘XFM_COMMON_REG_LIST_DCE60’ drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:187:3: note: in expansion of macro ‘transform_regs’ drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dce/dce_6_0_d.h:645:43: warning: initialized field overwritten [-Woverride-init] Cc: Harry Wentland Cc: Leo Li Cc: Alex Deucher Cc: "Christian König" Cc: David Airlie Cc: Daniel Vetter Cc: Mauro Rossi Cc: amd-gfx@lists.freedesktop.org Cc: dri-de...@lists.freedesktop.org Signed-off-by: Lee Jones --- drivers/gpu/drm/amd/display/dc/dce/dce_transform.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h index cbce194ec7b82..e98b5d4141739 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h @@ -166,8 +166,7 @@ SRI(SCL_F_SHARP_CONTROL, SCL, id) #define XFM_COMMON_REG_LIST_DCE60(id) \ - XFM_COMMON_REG_LIST_DCE60_BASE(id), \ - SRI(DCFE_MEM_LIGHT_SLEEP_CNTL, CRTC, id) + XFM_COMMON_REG_LIST_DCE60_BASE(id) #endif #define XFM_SF(reg_name, field_name, post_fix)\ -- 2.31.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 09/34] drm/amd/display/dc/bios/command_table_helper2: Fix function name 'dal_cmd_table_helper_transmitter_bp_to_atom2()'
Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/../display/dc/bios/command_table_helper2.c:141: warning: expecting prototype for translate_transmitter_bp_to_atom2(). Prototype was for dal_cmd_table_helper_transmitter_bp_to_atom2() instead Cc: Harry Wentland Cc: Leo Li Cc: Alex Deucher Cc: "Christian König" Cc: David Airlie Cc: Daniel Vetter Cc: amd-gfx@lists.freedesktop.org Cc: dri-de...@lists.freedesktop.org Signed-off-by: Lee Jones --- drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c index 00706b072b5f8..6d2fb112ad9f9 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c @@ -129,7 +129,7 @@ bool dal_cmd_table_helper_controller_id_to_atom2( } /** - * translate_transmitter_bp_to_atom2 - Translate the Transmitter to the + * dal_cmd_table_helper_transmitter_bp_to_atom2 - Translate the Transmitter to the * corresponding ATOM BIOS value * @t: transmitter * returns: digitalTransmitter -- 2.31.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 00/34] Rid W=1 warnings from GPU
This set is part of a larger effort attempting to clean-up W=1
kernel builds, which are currently overwhelmingly riddled with
niggly little warnings.
Lee Jones (34):
drm/amd/pm/inc/smu_v13_0: Move table into the only source file that
uses it
drm/amd/pm/swsmu/smu13/aldebaran_ppt: Remove unused variable 'ret'
drm/amd/pm/powerplay/hwmgr/smu7_thermal: Provide function name for
'smu7_fan_ctrl_set_default_mode()'
drm/amd/pm/powerplay/hwmgr/vega12_thermal: Provide function name
drm/amd/pm/powerplay/hwmgr/vega12_hwmgr: Provide
'vega12_init_smc_table()' function name
drm/amd/pm/powerplay/hwmgr/vega10_hwmgr: Kernel-doc headers must
contain function names
drm/amd/pm/powerplay/hwmgr/vega20_hwmgr: Provide function name
'vega20_init_smc_table()'
drm/amd/display/dc/bios/command_table_helper: Fix function name for
'dal_cmd_table_helper_transmitter_bp_to_atom()'
drm/amd/display/dc/bios/command_table_helper2: Fix function name
'dal_cmd_table_helper_transmitter_bp_to_atom2()'
drm/amd/display/dc/bios/bios_parser: Fix formatting and misnaming
issues
drm/nouveau/nvkm/subdev/mc/tu102: Make functions called by reference
static
drm/amd/display/amdgpu_dm/amdgpu_dm: Functions must directly follow
their headers
drm/amd/display/dc/dce/dmub_outbox: Convert over to kernel-doc
drm/amd/display/dc/gpio/gpio_service: Pass around correct
dce_{version,environment} types
drm/amd/display/dc/dce110/dce110_hw_sequencer: Include our own header
drm/amd/display/dc/dce/dce_transform: Remove superfluous
re-initialisation of DCFE_MEM_LIGHT_SLEEP_CNTL,
drm/amd/display/dc/dce/dce_mem_input: Remove duplicate initialisation
of GRPH_CONTROL__GRPH_NUM_BANKS_{SHIFT,MASK}
drm/amd/display/dc/dce/dce_mem_input: Remove duplicate initialisation
of GRPH_CONTROL__GRPH_NUM_BANKS_{SHIFT,MASK
drm/amd/amdgpu/amdgpu_device: Make local function static
drm/amd/display/amdgpu_dm/amdgpu_dm: Fix kernel-doc formatting issue
drm/amd/display/dc/dce110/dce110_hw_sequencer: Include header
containing our prototypes
drm/amd/display/dc/core/dc: Convert function headers to kernel-doc
drm/amd/display/dmub/src/dmub_srv_stat: Convert function header to
kernel-doc
drm/amd/display/modules/hdcp/hdcp_psp: Remove unused function
'mod_hdcp_hdcp1_get_link_encryption_status()'
drm/xlnx/zynqmp_disp: Fix incorrectly named enum
'zynqmp_disp_layer_id'
drm/xlnx/zynqmp_dp: Fix incorrectly name function 'zynqmp_dp_train()'
drm/ttm/ttm_tt: Demote non-conformant kernel-doc header
drm/panel/panel-raspberrypi-touchscreen: Demote kernel-doc abuse
drm/panel/panel-sitronix-st7701: Demote kernel-doc abuse
drm/vgem/vgem_drv: Standard comment blocks should not use kernel-doc
format
drm/exynos/exynos7_drm_decon: Fix incorrect naming of
'decon_shadow_protect_win()'
drm/exynos/exynos_drm_ipp: Fix documentation for
'exynos_drm_ipp_get_{caps,res}_ioctl()'
drm/vboxvideo/hgsmi_base: Place function names into headers
drm/vboxvideo/modesetting: Provide function names for prototype
headers
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 2 +-
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 +-
.../gpu/drm/amd/display/dc/bios/bios_parser.c | 6 +--
.../display/dc/bios/command_table_helper.c| 2 +-
.../display/dc/bios/command_table_helper2.c | 2 +-
drivers/gpu/drm/amd/display/dc/core/dc.c | 46 +--
.../drm/amd/display/dc/dce/dce_mem_input.h| 2 -
.../drm/amd/display/dc/dce/dce_transform.h| 3 +-
.../gpu/drm/amd/display/dc/dce/dmub_outbox.c | 17 ++-
.../display/dc/dce110/dce110_hw_sequencer.c | 3 ++
.../drm/amd/display/dc/gpio/gpio_service.c| 12 ++---
.../drm/amd/display/dmub/src/dmub_srv_stat.c | 19 +++-
.../display/include/gpio_service_interface.h | 4 +-
.../drm/amd/display/modules/hdcp/hdcp_psp.c | 13 --
drivers/gpu/drm/amd/pm/inc/smu_v13_0.h| 6 ---
.../drm/amd/pm/powerplay/hwmgr/smu7_thermal.c | 8 ++--
.../drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c | 26 ++-
.../drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c | 2 +-
.../amd/pm/powerplay/hwmgr/vega12_thermal.c | 3 +-
.../drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c | 2 +-
.../drm/amd/pm/swsmu/smu13/aldebaran_ppt.c| 9 +++-
drivers/gpu/drm/exynos/exynos7_drm_decon.c| 2 +-
drivers/gpu/drm/exynos/exynos_drm_ipp.c | 4 +-
.../gpu/drm/nouveau/nvkm/subdev/mc/tu102.c| 6 +--
.../drm/panel/panel-raspberrypi-touchscreen.c | 2 +-
drivers/gpu/drm/panel/panel-sitronix-st7701.c | 2 +-
drivers/gpu/drm/ttm/ttm_tt.c | 2 +-
drivers/gpu/drm/vboxvideo/hgsmi_base.c| 19 +---
drivers/gpu/drm/vboxvideo/modesetting.c | 20
drivers/gpu/drm/vgem/vgem_drv.c | 2 +-
drivers/gpu/drm/xlnx/zynqmp_disp.c| 2 +-
drivers/gpu/drm/xlnx/zynqmp_dp.c | 2 +-
32 files changed, 107 insertions(+), 147 deletions(-)
Cc: Adam Jackson
Cc: Ajay Kumar
[PATCH 01/34] drm/amd/pm/inc/smu_v13_0: Move table into the only source file that uses it
Fixes the following W=1 kernel build warning(s):
drivers/gpu/drm/amd/amdgpu/../pm/inc/smu_v13_0.h:54:43: warning:
‘smu13_thermal_policy’ defined but not used [-Wunused-const-variable=]
Cc: Alex Deucher
Cc: "Christian König"
Cc: David Airlie
Cc: Daniel Vetter
Cc: Kevin Wang
Cc: amd-gfx@lists.freedesktop.org
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Lee Jones
---
drivers/gpu/drm/amd/pm/inc/smu_v13_0.h | 6 --
drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c | 6 ++
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v13_0.h
b/drivers/gpu/drm/amd/pm/inc/smu_v13_0.h
index 1687709507b3d..6119a36b2cba0 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_v13_0.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v13_0.h
@@ -51,12 +51,6 @@
#define CTF_OFFSET_HOTSPOT 5
#define CTF_OFFSET_MEM 5
-static const struct smu_temperature_range smu13_thermal_policy[] =
-{
- {-273150, 99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
- { 12, 12, 12, 12, 12, 12, 12, 12,
12},
-};
-
struct smu_13_0_max_sustainable_clocks {
uint32_t display_clock;
uint32_t phy_clock;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
index d62cc6bb1a305..d6ce665baaf3b 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
@@ -78,6 +78,12 @@
#define smnPCIE_ESM_CTRL 0x111003D0
+static const struct smu_temperature_range smu13_thermal_policy[] =
+{
+ {-273150, 99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
+ { 12, 12, 12, 12, 12, 12, 12, 12,
12},
+};
+
static const struct cmn2asic_msg_mapping
aldebaran_message_map[SMU_MSG_MAX_COUNT] = {
MSG_MAP(TestMessage, PPSMC_MSG_TestMessage,
0),
MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion,
1),
--
2.31.1
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[PATCH 23/34] drm/amd/display/dmub/src/dmub_srv_stat: Convert function header to kernel-doc
Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/../display/dmub/src/dmub_srv_stat.c:38: warning: Cannot understand * Cc: Harry Wentland Cc: Leo Li Cc: Alex Deucher Cc: "Christian König" Cc: David Airlie Cc: Daniel Vetter Cc: Jun Lei Cc: Meenakshikumar Somasundaram Cc: Rodrigo Siqueira Cc: amd-gfx@lists.freedesktop.org Cc: dri-de...@lists.freedesktop.org Signed-off-by: Lee Jones --- .../drm/amd/display/dmub/src/dmub_srv_stat.c | 19 ++- 1 file changed, 6 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv_stat.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv_stat.c index e6f3bfab33d3e..70766d534c9c8 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv_stat.c +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv_stat.c @@ -35,20 +35,13 @@ */ /** - * - * Function: dmub_srv_stat_get_notification + * dmub_srv_stat_get_notification - Retrieves a dmub outbox notification, set up dmub notification + * structure with message information. Also a pending bit if queue + * is having more notifications + * @dmub: dmub srv structure + * @notify: dmub notification structure to be filled up * - * @brief - * Retrieves a dmub outbox notification, set up dmub notification - * structure with message information. Also a pending bit if queue - * is having more notifications - * - * @param [in] dmub: dmub srv structure - * @param [out] pnotify: dmub notification structure to be filled up - * - * @return - * dmub_status - * + * Returns: dmub_status */ enum dmub_status dmub_srv_stat_get_notification(struct dmub_srv *dmub, struct dmub_notification *notify) -- 2.31.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 19/34] drm/amd/amdgpu/amdgpu_device: Make local function static
Fixes the following W=1 kernel build warning(s):
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:4624:6: warning: no previous
prototype for ‘amdgpu_device_recheck_guilty_jobs’ [-Wmissing-prototypes]
Cc: Alex Deucher
Cc: "Christian König"
Cc: David Airlie
Cc: Daniel Vetter
Cc: Sumit Semwal
Cc: amd-gfx@lists.freedesktop.org
Cc: dri-de...@lists.freedesktop.org
Cc: linux-me...@vger.kernel.org
Cc: linaro-mm-...@lists.linaro.org
Signed-off-by: Lee Jones
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 4a040f89ca5aa..f15e180762d2e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -4692,7 +4692,7 @@ static int amdgpu_device_suspend_display_audio(struct
amdgpu_device *adev)
return 0;
}
-void amdgpu_device_recheck_guilty_jobs(
+static void amdgpu_device_recheck_guilty_jobs(
struct amdgpu_device *adev, struct list_head *device_list_handle,
struct amdgpu_reset_context *reset_context)
{
--
2.31.1
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[PATCH 07/34] drm/amd/pm/powerplay/hwmgr/vega20_hwmgr: Provide function name 'vega20_init_smc_table()'
Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega20_hwmgr.c:781: warning: expecting prototype for Initializes the SMC table and uploads it(). Prototype was for vega20_init_smc_table() instead Cc: Evan Quan Cc: Alex Deucher Cc: "Christian König" Cc: David Airlie Cc: Daniel Vetter Cc: amd-gfx@lists.freedesktop.org Cc: dri-de...@lists.freedesktop.org Signed-off-by: Lee Jones --- drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c index d3177a534fdf0..0791309586c58 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c @@ -772,7 +772,7 @@ static int vega20_setup_default_dpm_tables(struct pp_hwmgr *hwmgr) } /** - * Initializes the SMC table and uploads it + * vega20_init_smc_table - Initializes the SMC table and uploads it * * @hwmgr: the address of the powerplay hardware manager. * return: always 0 -- 2.31.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 18/34] drm/amd/display/dc/dce/dce_mem_input: Remove duplicate initialisation of GRPH_CONTROL__GRPH_NUM_BANKS_{SHIFT, MASK
Fixes the following W=1 kernel build warning(s):
In file included from
drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:29:
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dce/dce_6_0_sh_mask.h:7270:45:
warning: initialized field overwritten [-Woverride-init]
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_mem_input.h:155:28: note: in
expansion of macro ‘GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT’
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_mem_input.h:159:2: note: in
expansion of macro ‘SFB’
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_mem_input.h:264:2: note: in
expansion of macro ‘MI_GFX6_TILE_MASK_SH_LIST’
drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:657:3: note:
in expansion of macro ‘MI_DCE6_MASK_SH_LIST’
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dce/dce_6_0_sh_mask.h:7270:45:
note: (near initialization for ‘mi_shifts.GRPH_NUM_BANKS’)
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_mem_input.h:155:28: note: in
expansion of macro ‘GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT’
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_mem_input.h:159:2: note: in
expansion of macro ‘SFB’
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_mem_input.h:264:2: note: in
expansion of macro ‘MI_GFX6_TILE_MASK_SH_LIST’
drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:657:3: note:
in expansion of macro ‘MI_DCE6_MASK_SH_LIST’
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dce/dce_6_0_sh_mask.h:7269:43:
warning: initialized field overwritten [-Woverride-init]
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_mem_input.h:155:28: note: in
expansion of macro ‘GRPH_CONTROL__GRPH_NUM_BANKS_MASK’
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_mem_input.h:159:2: note: in
expansion of macro ‘SFB’
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_mem_input.h:264:2: note: in
expansion of macro ‘MI_GFX6_TILE_MASK_SH_LIST’
drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:662:3: note:
in expansion of macro ‘MI_DCE6_MASK_SH_LIST’
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dce/dce_6_0_sh_mask.h:7269:43:
note: (near initialization for ‘mi_masks.GRPH_NUM_BANKS’)
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_mem_input.h:155:28: note: in
expansion of macro ‘GRPH_CONTROL__GRPH_NUM_BANKS_MASK’
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_mem_input.h:159:2: note: in
expansion of macro ‘SFB’
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_mem_input.h:264:2: note: in
expansion of macro ‘MI_GFX6_TILE_MASK_SH_LIST’
drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:662:3: note:
in expansion of macro ‘MI_DCE6_MASK_SH_LIST’
Cc: Harry Wentland
Cc: Leo Li
Cc: Alex Deucher
Cc: "Christian König"
Cc: David Airlie
Cc: Daniel Vetter
Cc: Mauro Rossi
Cc: Lee Jones
Cc: amd-gfx@lists.freedesktop.org
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Lee Jones
---
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
index 9b1c4d56275a4..08a4c8d029d9f 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
@@ -206,7 +206,6 @@ struct dce_mem_input_registers {
SFB(blk, GRPH_ENABLE, GRPH_ENABLE, mask_sh),\
SFB(blk, GRPH_CONTROL, GRPH_DEPTH, mask_sh),\
SFB(blk, GRPH_CONTROL, GRPH_FORMAT, mask_sh),\
- SFB(blk, GRPH_CONTROL, GRPH_NUM_BANKS, mask_sh),\
SFB(blk, GRPH_X_START, GRPH_X_START, mask_sh),\
SFB(blk, GRPH_Y_START, GRPH_Y_START, mask_sh),\
SFB(blk, GRPH_X_END, GRPH_X_END, mask_sh),\
--
2.31.1
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[PATCH 02/34] drm/amd/pm/swsmu/smu13/aldebaran_ppt: Remove unused variable 'ret'
Fixes the following W=1 kernel build warning(s):
drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/aldebaran_ppt.c: In function
‘aldebaran_is_dpm_running’:
drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/aldebaran_ppt.c:1260:6: warning:
variable ‘ret’ set but not used [-Wunused-but-set-variable]
Cc: Alex Deucher
Cc: "Christian König"
Cc: David Airlie
Cc: Daniel Vetter
Cc: amd-gfx@lists.freedesktop.org
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Lee Jones
---
drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
index d6ce665baaf3b..d077e211017a9 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
@@ -1368,10 +1368,9 @@ static int aldebaran_usr_edit_dpm_table(struct
smu_context *smu, enum PP_OD_DPM_
static bool aldebaran_is_dpm_running(struct smu_context *smu)
{
- int ret = 0;
uint32_t feature_mask[2];
unsigned long feature_enabled;
- ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
+ smu_cmn_get_enabled_mask(smu, feature_mask, 2);
feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
((uint64_t)feature_mask[1] << 32));
return !!(feature_enabled & SMC_DPM_FEATURE);
--
2.31.1
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[PATCH 04/34] drm/amd/pm/powerplay/hwmgr/vega12_thermal: Provide function name
Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega12_thermal.c:171: warning: expecting prototype for Set the requested temperature range for high and low alert signals(). Prototype was for vega12_thermal_set_temperature_range() instead Cc: Evan Quan Cc: Alex Deucher Cc: "Christian König" Cc: David Airlie Cc: Daniel Vetter Cc: amd-gfx@lists.freedesktop.org Cc: dri-de...@lists.freedesktop.org Signed-off-by: Lee Jones --- drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c index 0dc16f25a463b..ed3dff0b52d21 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c @@ -159,7 +159,8 @@ int vega12_thermal_get_temperature(struct pp_hwmgr *hwmgr) } /** - * Set the requested temperature range for high and low alert signals + * vega12_thermal_set_temperature_range - Set the requested temperature range + *for high and low alert signals * * @hwmgr: The address of the hardware manager. * @range: Temperature range to be programmed for -- 2.31.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 14/34] drm/amd/display/dc/gpio/gpio_service: Pass around correct dce_{version, environment} types
Fixes the following W=1 kernel build warning(s):
drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/gpio_service.c: In function
‘dal_gpio_service_create’:
drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/gpio_service.c:71:4: warning:
implicit conversion from ‘enum dce_version’ to ‘enum dce_environment’
[-Wenum-conversion]
drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/gpio_service.c:77:4: warning:
implicit conversion from ‘enum dce_version’ to ‘enum dce_environment’
[-Wenum-conversion]
Cc: Harry Wentland
Cc: Leo Li
Cc: Alex Deucher
Cc: "Christian König"
Cc: David Airlie
Cc: Daniel Vetter
Cc: amd-gfx@lists.freedesktop.org
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Lee Jones
---
drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c | 12 ++--
.../drm/amd/display/include/gpio_service_interface.h | 4 ++--
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c
b/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c
index 92280cc05e2db..dae8e489c8cf4 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c
@@ -53,8 +53,8 @@
*/
struct gpio_service *dal_gpio_service_create(
- enum dce_version dce_version_major,
- enum dce_version dce_version_minor,
+ enum dce_version dce_version,
+ enum dce_environment dce_environment,
struct dc_context *ctx)
{
struct gpio_service *service;
@@ -67,14 +67,14 @@ struct gpio_service *dal_gpio_service_create(
return NULL;
}
- if (!dal_hw_translate_init(>translate, dce_version_major,
- dce_version_minor)) {
+ if (!dal_hw_translate_init(>translate, dce_version,
+ dce_environment)) {
BREAK_TO_DEBUGGER();
goto failure_1;
}
- if (!dal_hw_factory_init(>factory, dce_version_major,
- dce_version_minor)) {
+ if (!dal_hw_factory_init(>factory, dce_version,
+ dce_environment)) {
BREAK_TO_DEBUGGER();
goto failure_1;
}
diff --git a/drivers/gpu/drm/amd/display/include/gpio_service_interface.h
b/drivers/gpu/drm/amd/display/include/gpio_service_interface.h
index 9c55d247227ea..7e3240e73c1fc 100644
--- a/drivers/gpu/drm/amd/display/include/gpio_service_interface.h
+++ b/drivers/gpu/drm/amd/display/include/gpio_service_interface.h
@@ -42,8 +42,8 @@ void dal_gpio_destroy(
struct gpio **ptr);
struct gpio_service *dal_gpio_service_create(
- enum dce_version dce_version_major,
- enum dce_version dce_version_minor,
+ enum dce_version dce_version,
+ enum dce_environment dce_environment,
struct dc_context *ctx);
struct gpio *dal_gpio_service_create_irq(
--
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[PATCH 17/34] drm/amd/display/dc/dce/dce_mem_input: Remove duplicate initialisation of GRPH_CONTROL__GRPH_NUM_BANKS_{SHIFT, MASK}
Fixes the following W=1 kernel build warning(s):
In file included from
drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:29:
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dce/dce_6_0_sh_mask.h:7270:45:
warning: initialized field overwritten [-Woverride-init]
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_mem_input.h:155:28: note: in
expansion of macro ‘GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT’
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_mem_input.h:159:2: note: in
expansion of macro ‘SFB’
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_mem_input.h:265:2: note: in
expansion of macro ‘MI_GFX6_TILE_MASK_SH_LIST’
drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:657:3: note:
in expansion of macro ‘MI_DCE6_MASK_SH_LIST’
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dce/dce_6_0_sh_mask.h:7270:45:
note: (near initialization for ‘mi_shifts.GRPH_NUM_BANKS’)
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_mem_input.h:155:28: note: in
expansion of macro ‘GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT’
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_mem_input.h:159:2: note: in
expansion of macro ‘SFB’
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_mem_input.h:265:2: note: in
expansion of macro ‘MI_GFX6_TILE_MASK_SH_LIST’
drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:657:3: note:
in expansion of macro ‘MI_DCE6_MASK_SH_LIST’
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dce/dce_6_0_sh_mask.h:7269:43:
warning: initialized field overwritten [-Woverride-init]
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_mem_input.h:155:28: note: in
expansion of macro ‘GRPH_CONTROL__GRPH_NUM_BANKS_MASK’
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_mem_input.h:159:2: note: in
expansion of macro ‘SFB’
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_mem_input.h:265:2: note: in
expansion of macro ‘MI_GFX6_TILE_MASK_SH_LIST’
drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:662:3: note:
in expansion of macro ‘MI_DCE6_MASK_SH_LIST’
drivers/gpu/drm/amd/amdgpu/../include/asic_reg/dce/dce_6_0_sh_mask.h:7269:43:
note: (near initialization for ‘mi_masks.GRPH_NUM_BANKS’)
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_mem_input.h:155:28: note: in
expansion of macro ‘GRPH_CONTROL__GRPH_NUM_BANKS_MASK’
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_mem_input.h:159:2: note: in
expansion of macro ‘SFB’
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_mem_input.h:265:2: note: in
expansion of macro ‘MI_GFX6_TILE_MASK_SH_LIST’
drivers/gpu/drm/amd/amdgpu/../display/dc/dce60/dce60_resource.c:662:3: note:
in expansion of macro ‘MI_DCE6_MASK_SH_LIST’
Cc: Harry Wentland
Cc: Leo Li
Cc: Alex Deucher
Cc: "Christian König"
Cc: David Airlie
Cc: Daniel Vetter
Cc: Mauro Rossi
Cc: amd-gfx@lists.freedesktop.org
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Lee Jones
---
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
index 23db5c72f07ed..9b1c4d56275a4 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
@@ -181,7 +181,6 @@ struct dce_mem_input_registers {
SFB(blk, GRPH_ENABLE, GRPH_ENABLE, mask_sh),\
SFB(blk, GRPH_CONTROL, GRPH_DEPTH, mask_sh),\
SFB(blk, GRPH_CONTROL, GRPH_FORMAT, mask_sh),\
- SFB(blk, GRPH_CONTROL, GRPH_NUM_BANKS, mask_sh),\
SFB(blk, GRPH_X_START, GRPH_X_START, mask_sh),\
SFB(blk, GRPH_Y_START, GRPH_Y_START, mask_sh),\
SFB(blk, GRPH_X_END, GRPH_X_END, mask_sh),\
--
2.31.1
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[PATCH 20/34] drm/amd/display/amdgpu_dm/amdgpu_dm: Fix kernel-doc formatting issue
Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:608: warning: Function parameter or member 'interrupt_params' not described in 'dm_dcn_vertical_interrupt0_high_irq' Cc: Harry Wentland Cc: Leo Li Cc: Alex Deucher Cc: "Christian König" Cc: David Airlie Cc: Daniel Vetter Cc: amd-gfx@lists.freedesktop.org Cc: dri-de...@lists.freedesktop.org Signed-off-by: Lee Jones --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index ae0a95c5f1d8c..0b4841f377e41 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -605,7 +605,7 @@ static void dm_crtc_high_irq(void *interrupt_params) /** * dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0 for * DCN generation ASICs - * @interrupt params - interrupt parameters + * @interrupt_params: interrupt parameters * * Used to set crc window/read out crc value at vertical line 0 position */ -- 2.31.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 06/34] drm/amd/pm/powerplay/hwmgr/vega10_hwmgr: Kernel-doc headers must contain function names
Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_hwmgr.c:547: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_hwmgr.c:603: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_hwmgr.c:629: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_hwmgr.c:1006: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_hwmgr.c:1155: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_hwmgr.c:1608: warning: expecting prototype for Populates single SMC GFXSCLK structure using the provided engine clock(). Prototype was for vega10_populate_single_gfx_level() instead drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_hwmgr.c:1663: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_hwmgr.c:1713: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_hwmgr.c:1862: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_hwmgr.c:2546: warning: expecting prototype for Initializes the SMC table and uploads it(). Prototype was for vega10_init_smc_table() instead drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_hwmgr.c:2922: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst Cc: Evan Quan Cc: Alex Deucher Cc: "Christian König" Cc: David Airlie Cc: Daniel Vetter Cc: amd-gfx@lists.freedesktop.org Cc: dri-de...@lists.freedesktop.org Signed-off-by: Lee Jones --- .../drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c | 26 +++ 1 file changed, 15 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c index 31c61ac3bd5e1..25979106fd255 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c @@ -544,7 +544,7 @@ static int vega10_get_socclk_for_voltage_evv(struct pp_hwmgr *hwmgr, #define ATOM_VIRTUAL_VOLTAGE_ID0 0xff01 /** - * Get Leakage VDDC based on leakage ID. + * vega10_get_evv_voltages - Get Leakage VDDC based on leakage ID. * * @hwmgr: the address of the powerplay hardware manager. * return: always 0. @@ -600,7 +600,7 @@ static int vega10_get_evv_voltages(struct pp_hwmgr *hwmgr) } /** - * Change virtual leakage voltage to actual value. + * vega10_patch_with_vdd_leakage - Change virtual leakage voltage to actual value. * * @hwmgr: the address of the powerplay hardware manager. * @voltage: pointer to changing voltage @@ -626,7 +626,7 @@ static void vega10_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr, } /** - * Patch voltage lookup table by EVV leakages. + * vega10_patch_lookup_table_with_leakage - Patch voltage lookup table by EVV leakages. * * @hwmgr: the address of the powerplay hardware manager. * @lookup_table: pointer to voltage lookup table @@ -1003,7 +1003,7 @@ static int vega10_setup_asic_task(struct pp_hwmgr *hwmgr) } /** - * Remove repeated voltage values and create table with unique values. + * vega10_trim_voltage_table - Remove repeated voltage values and create table with unique values. * * @hwmgr: the address of the powerplay hardware manager. * @vol_table: the pointer to changing voltage table @@ -1152,7 +1152,7 @@ static void vega10_trim_voltage_table_to_fit_state_table( } /** - * Create Voltage Tables. + * vega10_construct_voltage_tables - Create Voltage Tables. * * @hwmgr: the address of the powerplay hardware manager. * return: always 0 @@ -1595,7 +1595,8 @@ static int vega10_populate_smc_link_levels(struct pp_hwmgr *hwmgr) } /** - * Populates single SMC GFXSCLK structure using the provided engine clock + * vega10_populate_single_gfx_level - Populates single SMC GFXSCLK structure + *using the provided engine clock * * @hwmgr: the address of the hardware manager * @gfx_clock: the GFX clock to use to populate the structure. @@ -1660,7 +1661,8 @@ static int
[PATCH 05/34] drm/amd/pm/powerplay/hwmgr/vega12_hwmgr: Provide 'vega12_init_smc_table()' function name
Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega12_hwmgr.c:812: warning: expecting prototype for Initializes the SMC table and uploads it(). Prototype was for vega12_init_smc_table() instead Cc: Evan Quan Cc: Alex Deucher Cc: "Christian König" Cc: David Airlie Cc: Daniel Vetter Cc: amd-gfx@lists.freedesktop.org Cc: dri-de...@lists.freedesktop.org Signed-off-by: Lee Jones --- drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c index 1a097e608808e..29e0d1d4035ad 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c @@ -803,7 +803,7 @@ static int vega12_save_default_power_profile(struct pp_hwmgr *hwmgr) #endif /** - * Initializes the SMC table and uploads it + * vega12_init_smc_table - Initializes the SMC table and uploads it * * @hwmgr: the address of the powerplay hardware manager. * return: always 0 -- 2.31.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH -next] drm/amdgpu: Fix Wunused-label warning
If CONFIG_64BIT is n, build warns:
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:333:1:
warning: label ‘exit’ defined but not used [-Wunused-label]
Fixes: f89f8c6bafd0 ("drm/amdgpu: Guard against write accesses after device
removal")
Signed-off-by: YueHaibing
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 4a040f89ca5a..841774f4aedc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -330,7 +330,9 @@ void amdgpu_device_vram_access(struct amdgpu_device *adev,
loff_t pos,
}
spin_unlock_irqrestore(>mmio_idx_lock, flags);
+#ifdef CONFIG_64BIT
exit:
+#endif
drm_dev_exit(idx);
}
--
2.17.1
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[PATCH 24/34] drm/amd/display/modules/hdcp/hdcp_psp: Remove unused function 'mod_hdcp_hdcp1_get_link_encryption_status()'
Fixes the following W=1 kernel build warning(s):
drivers/gpu/drm/amd/amdgpu/../display/modules/hdcp/hdcp_psp.c:374:22: warning:
no previous prototype for ‘mod_hdcp_hdcp1_get_link_encryption_status’
[-Wmissing-prototypes]
Cc: Harry Wentland
Cc: Leo Li
Cc: Alex Deucher
Cc: "Christian König"
Cc: David Airlie
Cc: Daniel Vetter
Cc: amd-gfx@lists.freedesktop.org
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Lee Jones
---
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c | 13 -
1 file changed, 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
index 26f96c05e0ec8..06910d2fd57a0 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
@@ -371,19 +371,6 @@ enum mod_hdcp_status
mod_hdcp_hdcp1_link_maintenance(struct mod_hdcp *hdcp)
return status;
}
-enum mod_hdcp_status mod_hdcp_hdcp1_get_link_encryption_status(struct mod_hdcp
*hdcp,
- enum
mod_hdcp_encryption_status *encryption_status)
-{
- *encryption_status = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF;
-
- if (mod_hdcp_hdcp1_link_maintenance(hdcp) != MOD_HDCP_STATUS_SUCCESS)
- return MOD_HDCP_STATUS_FAILURE;
-
- *encryption_status = MOD_HDCP_ENCRYPTION_STATUS_HDCP1_ON;
-
- return MOD_HDCP_STATUS_SUCCESS;
-}
-
enum mod_hdcp_status mod_hdcp_hdcp2_create_session(struct mod_hdcp *hdcp)
{
struct psp_context *psp = hdcp->config.psp.handle;
--
2.31.1
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[PATCH 22/34] drm/amd/display/dc/core/dc: Convert function headers to kernel-doc
Fixes the following W=1 kernel build warning(s):
drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:3324: warning: Cannot
understand
*
drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:3344: warning: Cannot
understand
*
drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:3417: warning: Cannot
understand
*
Cc: Harry Wentland
Cc: Leo Li
Cc: Alex Deucher
Cc: "Christian König"
Cc: David Airlie
Cc: Daniel Vetter
Cc: amd-gfx@lists.freedesktop.org
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Lee Jones
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 46 ++--
1 file changed, 11 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index ef157b83bacd2..34c207f92df98 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -3335,18 +3335,10 @@ void dc_hardware_release(struct dc *dc)
#endif
/**
- *
- * Function: dc_enable_dmub_notifications
+ * dc_enable_dmub_notifications - Returns whether dmub notification can be
enabled
+ * @dc: dc structure
*
- * @brief
- * Returns whether dmub notification can be enabled
- *
- * @param
- * [in] dc: dc structure
- *
- * @return
- * True to enable dmub notifications, False otherwise
- *
+ * Returns: True to enable dmub notifications, False otherwise
*/
bool dc_enable_dmub_notifications(struct dc *dc)
{
@@ -3355,21 +3347,13 @@ bool dc_enable_dmub_notifications(struct dc *dc)
}
/**
- *
- * Function: dc_process_dmub_aux_transfer_async
- *
- * @brief
- * Submits aux command to dmub via inbox message
- * Sets port index appropriately for legacy DDC
- *
- * @param
- * [in] dc: dc structure
- * [in] link_index: link index
- * [in] payload: aux payload
+ * dc_process_dmub_aux_transfer_async - Submits aux command to dmub via inbox
message
+ * Sets port index appropriately for
legacy DDC
+ * @dc: dc structure
+ * @link_index: link index
+ * @payload: aux payload
*
- * @return
- * True if successful, False if failure
- *
+ * Returns: True if successful, False if failure
*/
bool dc_process_dmub_aux_transfer_async(struct dc *dc,
uint32_t link_index,
@@ -3428,16 +3412,8 @@ bool dc_process_dmub_aux_transfer_async(struct dc *dc,
}
/**
- *
- * Function: dc_disable_accelerated_mode
- *
- * @brief
- * disable accelerated mode
- *
- * @param
- * [in] dc: dc structure
- *
- *
+ * dc_disable_accelerated_mode - disable accelerated mode
+ * @dc: dc structure
*/
void dc_disable_accelerated_mode(struct dc *dc)
{
--
2.31.1
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[PATCH 10/34] drm/amd/display/dc/bios/bios_parser: Fix formatting and misnaming issues
Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser.c:997: warning: expecting prototype for get_ss_info_from_table(). Prototype was for get_ss_info_from_tbl() instead drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser.c:1562: warning: expecting prototype for BiosParserObject(). Prototype was for bios_parser_get_ss_entry_number() instead drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser.c:1739: warning: expecting prototype for get_ss_entry_number_from_internal_ss_info_table_V3_1(). Prototype was for get_ss_entry_number_from_internal_ss_info_tbl_V3_1() instead Cc: Harry Wentland Cc: Leo Li Cc: Alex Deucher Cc: "Christian König" Cc: David Airlie Cc: Daniel Vetter Cc: Lee Jones Cc: amd-gfx@lists.freedesktop.org Cc: dri-de...@lists.freedesktop.org Signed-off-by: Lee Jones --- drivers/gpu/drm/amd/display/dc/bios/bios_parser.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c index c67d21a5ee52f..9b8ea6e9a2b96 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c +++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c @@ -979,7 +979,7 @@ static enum bp_result get_ss_info_from_internal_ss_info_tbl_V2_1( struct spread_spectrum_info *info); /** - * get_ss_info_from_table + * get_ss_info_from_tbl * Get spread sprectrum information from the ASIC_InternalSS_Info Ver 2.1 or * SS_Info table from the VBIOS * There can not be more than 1 entry for ASIC_InternalSS_Info Ver 2.1 or @@ -1548,7 +1548,7 @@ static uint32_t get_ss_entry_number_from_ss_info_tbl( uint32_t id); /** - * BiosParserObject::GetNumberofSpreadSpectrumEntry + * bios_parser_get_ss_entry_number * Get Number of SpreadSpectrum Entry from the ASIC_InternalSS_Info table from * the VBIOS that match the SSid (to be converted from signal) * @@ -1725,7 +1725,7 @@ static uint32_t get_ss_entry_number_from_internal_ss_info_tbl_v2_1( return 0; } /** - * get_ss_entry_number_from_internal_ss_info_table_V3_1 + * get_ss_entry_number_from_internal_ss_info_tbl_V3_1 * Get Number of SpreadSpectrum Entry from the ASIC_InternalSS_Info table of * the VBIOS that matches id * -- 2.31.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 03/34] drm/amd/pm/powerplay/hwmgr/smu7_thermal: Provide function name for 'smu7_fan_ctrl_set_default_mode()'
Fixes the following W=1 kernel build warning(s):
drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu7_thermal.c:132: warning:
This comment starts with '/**', but isn't a kernel-doc comment. Refer
Documentation/doc-guide/kernel-doc.rst
Cc: Evan Quan
Cc: Alex Deucher
Cc: "Christian König"
Cc: David Airlie
Cc: Daniel Vetter
Cc: amd-gfx@lists.freedesktop.org
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Lee Jones
---
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c
b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c
index 0d38d4206848a..6cfe148ed45bb 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c
@@ -129,10 +129,10 @@ int smu7_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr,
uint32_t mode)
}
/**
-* Reset Fan Speed Control to default mode.
-* @hwmgr: the address of the powerplay hardware manager.
-* Exception: Should always succeed.
-*/
+ * smu7_fan_ctrl_set_default_mode - Reset Fan Speed Control to default mode.
+ * @hwmgr: the address of the powerplay hardware manager.
+ * Exception: Should always succeed.
+ */
int smu7_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr)
{
if (!hwmgr->fan_ctrl_is_in_default_mode) {
--
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[PATCH 12/34] drm/amd/display/amdgpu_dm/amdgpu_dm: Functions must directly follow their headers
Fixes the following W=1 kernel build warning(s):
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:608: warning:
Function parameter or member 'interrupt_params' not described in
'dm_dcn_vertical_interrupt0_high_irq'
Cc: Harry Wentland
Cc: Leo Li
Cc: Alex Deucher
Cc: "Christian König"
Cc: David Airlie
Cc: Daniel Vetter
Cc: amd-gfx@lists.freedesktop.org
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Lee Jones
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index b4e95d3ff3b88..ae0a95c5f1d8c 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -601,6 +601,7 @@ static void dm_crtc_high_irq(void *interrupt_params)
}
#if defined(CONFIG_DRM_AMD_DC_DCN)
+#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
/**
* dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0 for
* DCN generation ASICs
@@ -608,7 +609,6 @@ static void dm_crtc_high_irq(void *interrupt_params)
*
* Used to set crc window/read out crc value at vertical line 0 position
*/
-#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params)
{
struct common_irq_params *irq_params = interrupt_params;
--
2.31.1
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Re: [PATCH] free the metadata buffer for sg type BOs as well
You need a commit message.
Am 26.05.21 um 05:46 schrieb Shiwu Zhang:
Signed-off-by: Shiwu Zhang
With that fixed the patch is Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 2d876e1eaa7c..e9f8701fd046 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -95,7 +95,7 @@ static void amdgpu_bo_destroy(struct ttm_buffer_object *tbo)
}
amdgpu_bo_unref(>parent);
- if (bo->tbo.type == ttm_bo_type_device) {
+ if (bo->tbo.type != ttm_bo_type_kernel) {
ubo = to_amdgpu_bo_user(bo);
kfree(ubo->metadata);
}
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Re: [PATCH 3/7] drm/amdgpu: use amdgpu_bo_vm for vm code
Am 26.05.21 um 12:10 schrieb Nirmoy Das:
Use amdgpu_bo_vm subclass for creating BOs related to PD/PT.
I think it would be better if you just squash patch #3, #4 and #5 together.
Apart from that looks good to me, but still need to double check patch #7.
Christian.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 43 ++
1 file changed, 24 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index f474f15ba344..2c97d67d9cfc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -868,9 +868,10 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
static int amdgpu_vm_pt_create(struct amdgpu_device *adev,
struct amdgpu_vm *vm,
int level, bool immediate,
- struct amdgpu_bo **bo)
+ struct amdgpu_bo_vm **vmbo)
{
struct amdgpu_bo_param bp;
+ struct amdgpu_bo *bo;
int r;
memset(, 0, sizeof(bp));
@@ -881,7 +882,7 @@ static int amdgpu_vm_pt_create(struct amdgpu_device *adev,
bp.domain = amdgpu_bo_get_preferred_pin_domain(adev, bp.domain);
bp.flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
AMDGPU_GEM_CREATE_CPU_GTT_USWC;
- bp.bo_ptr_size = sizeof(struct amdgpu_bo);
+ bp.bo_ptr_size = sizeof(struct amdgpu_bo_vm);
if (vm->use_cpu_for_update)
bp.flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
@@ -890,23 +891,24 @@ static int amdgpu_vm_pt_create(struct amdgpu_device *adev,
if (vm->root.base.bo)
bp.resv = vm->root.base.bo->tbo.base.resv;
- r = amdgpu_bo_create(adev, , bo);
+ r = amdgpu_bo_create_vm(adev, , vmbo);
if (r)
return r;
+ bo = &(*vmbo)->bo;
if (vm->is_compute_context && (adev->flags & AMD_IS_APU))
return 0;
if (!bp.resv)
- WARN_ON(dma_resv_lock((*bo)->tbo.base.resv,
+ WARN_ON(dma_resv_lock(bo->tbo.base.resv,
NULL));
- r = amdgpu_bo_create_shadow(adev, bp.size, *bo);
+ r = amdgpu_bo_create_shadow(adev, bp.size, bo);
if (!bp.resv)
- dma_resv_unlock((*bo)->tbo.base.resv);
+ dma_resv_unlock(bo->tbo.base.resv);
if (r) {
- amdgpu_bo_unref(bo);
+ amdgpu_bo_unref();
return r;
}
@@ -933,7 +935,8 @@ static int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
bool immediate)
{
struct amdgpu_vm_pt *entry = cursor->entry;
- struct amdgpu_bo *pt;
+ struct amdgpu_bo *pt_bo;
+ struct amdgpu_bo_vm *pt;
int r;
if (cursor->level < AMDGPU_VM_PTB && !entry->entries) {
@@ -957,18 +960,19 @@ static int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
/* Keep a reference to the root directory to avoid
* freeing them up in the wrong order.
*/
- pt->parent = amdgpu_bo_ref(cursor->parent->base.bo);
- amdgpu_vm_bo_base_init(>base, vm, pt);
+ pt_bo = >bo;
+ pt_bo->parent = amdgpu_bo_ref(cursor->parent->base.bo);
+ amdgpu_vm_bo_base_init(>base, vm, pt_bo);
- r = amdgpu_vm_clear_bo(adev, vm, pt, immediate);
+ r = amdgpu_vm_clear_bo(adev, vm, pt_bo, immediate);
if (r)
goto error_free_pt;
return 0;
error_free_pt:
- amdgpu_bo_unref(>shadow);
- amdgpu_bo_unref();
+ amdgpu_bo_unref(_bo->shadow);
+ amdgpu_bo_unref(_bo);
return r;
}
@@ -2843,7 +2847,8 @@ long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout)
*/
int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, u32
pasid)
{
- struct amdgpu_bo *root;
+ struct amdgpu_bo *root_bo;
+ struct amdgpu_bo_vm *root;
int r, i;
vm->va = RB_ROOT_CACHED;
@@ -2897,18 +2902,18 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct
amdgpu_vm *vm, u32 pasid)
false, );
if (r)
goto error_free_delayed;
-
- r = amdgpu_bo_reserve(root, true);
+ root_bo = >bo;
+ r = amdgpu_bo_reserve(root_bo, true);
if (r)
goto error_free_root;
- r = dma_resv_reserve_shared(root->tbo.base.resv, 1);
+ r = dma_resv_reserve_shared(root_bo->tbo.base.resv, 1);
if (r)
goto error_unreserve;
- amdgpu_vm_bo_base_init(>root.base, vm, root);
+ amdgpu_vm_bo_base_init(>root.base, vm, root_bo);
- r = amdgpu_vm_clear_bo(adev, vm, root, false);
+ r = amdgpu_vm_clear_bo(adev, vm, root_bo, false);
if (r)
goto error_unreserve;
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RE: [PATCH 2/7] drm/amdgpu: move shadow bo validation to VM code
[AMD Official Use Only]
Thanks Christian, I found some more issues as well, I will update and resend
again.
-Original Message-
From: Koenig, Christian
Sent: Wednesday, May 26, 2021 2:03 PM
To: Das, Nirmoy ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: Re: [PATCH 2/7] drm/amdgpu: move shadow bo validation to VM code
Am 26.05.21 um 12:10 schrieb Nirmoy Das:
> Do the shadow bo validation in the VM code as VM code knows/owns
> shadow BOs.
>
> Signed-off-by: Nirmoy Das
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 23 ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 5 +
> 2 files changed, 9 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> index 90136f9dedd6..f6a8f0c5a52f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> @@ -396,10 +396,10 @@ void amdgpu_cs_report_moved_bytes(struct amdgpu_device
> *adev, u64 num_bytes,
> spin_unlock(>mm_stats.lock);
> }
>
> -static int amdgpu_cs_bo_validate(struct amdgpu_cs_parser *p,
> - struct amdgpu_bo *bo)
> +static int amdgpu_cs_bo_validate(void *param, struct amdgpu_bo *bo)
> {
> struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
> + struct amdgpu_cs_parser *p = param;
> struct ttm_operation_ctx ctx = {
> .interruptible = true,
> .no_wait_gpu = false,
> @@ -451,21 +451,6 @@ static int amdgpu_cs_bo_validate(struct amdgpu_cs_parser
> *p,
> return r;
> }
>
> -static int amdgpu_cs_validate(void *param, struct amdgpu_bo *bo) -{
> - struct amdgpu_cs_parser *p = param;
> - int r;
> -
> - r = amdgpu_cs_bo_validate(p, bo);
> - if (r)
> - return r;
> -
> - if (bo->shadow)
> - r = amdgpu_cs_bo_validate(p, bo->shadow);
> -
> - return r;
> -}
> -
> static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
> struct list_head *validated)
> {
> @@ -493,7 +478,7 @@ static int amdgpu_cs_list_validate(struct
> amdgpu_cs_parser *p,
>lobj->user_pages);
> }
>
> - r = amdgpu_cs_validate(p, bo);
> + r = amdgpu_cs_bo_validate(p, bo);
> if (r)
> return r;
>
> @@ -593,7 +578,7 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser
> *p,
> p->bytes_moved_vis = 0;
>
> r = amdgpu_vm_validate_pt_bos(p->adev, >vm,
> - amdgpu_cs_validate, p);
> + amdgpu_cs_bo_validate, p);
> if (r) {
> DRM_ERROR("amdgpu_vm_validate_pt_bos() failed.\n");
> goto error_validate;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index da155c276c51..f474f15ba344 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -696,6 +696,11 @@ int amdgpu_vm_validate_pt_bos(struct amdgpu_device
> *adev, struct amdgpu_vm *vm,
> r = validate(param, bo);
> if (r)
> return r;
> + if (bo->shadow) {
> + r = validate(param, bo);
This needs to be "validate(param, bo->shadow)".
Apart from that looks good to me.
Christian.
> + if (r)
> + return r;
> + }
>
> if (bo->tbo.type != ttm_bo_type_kernel) {
> amdgpu_vm_bo_moved(bo_base);
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Re: [PATCH 2/7] drm/amdgpu: move shadow bo validation to VM code
Am 26.05.21 um 12:10 schrieb Nirmoy Das:
Do the shadow bo validation in the VM code as
VM code knows/owns shadow BOs.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 23 ---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 5 +
2 files changed, 9 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 90136f9dedd6..f6a8f0c5a52f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -396,10 +396,10 @@ void amdgpu_cs_report_moved_bytes(struct amdgpu_device
*adev, u64 num_bytes,
spin_unlock(>mm_stats.lock);
}
-static int amdgpu_cs_bo_validate(struct amdgpu_cs_parser *p,
-struct amdgpu_bo *bo)
+static int amdgpu_cs_bo_validate(void *param, struct amdgpu_bo *bo)
{
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
+ struct amdgpu_cs_parser *p = param;
struct ttm_operation_ctx ctx = {
.interruptible = true,
.no_wait_gpu = false,
@@ -451,21 +451,6 @@ static int amdgpu_cs_bo_validate(struct amdgpu_cs_parser
*p,
return r;
}
-static int amdgpu_cs_validate(void *param, struct amdgpu_bo *bo)
-{
- struct amdgpu_cs_parser *p = param;
- int r;
-
- r = amdgpu_cs_bo_validate(p, bo);
- if (r)
- return r;
-
- if (bo->shadow)
- r = amdgpu_cs_bo_validate(p, bo->shadow);
-
- return r;
-}
-
static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
struct list_head *validated)
{
@@ -493,7 +478,7 @@ static int amdgpu_cs_list_validate(struct amdgpu_cs_parser
*p,
lobj->user_pages);
}
- r = amdgpu_cs_validate(p, bo);
+ r = amdgpu_cs_bo_validate(p, bo);
if (r)
return r;
@@ -593,7 +578,7 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
p->bytes_moved_vis = 0;
r = amdgpu_vm_validate_pt_bos(p->adev, >vm,
- amdgpu_cs_validate, p);
+ amdgpu_cs_bo_validate, p);
if (r) {
DRM_ERROR("amdgpu_vm_validate_pt_bos() failed.\n");
goto error_validate;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index da155c276c51..f474f15ba344 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -696,6 +696,11 @@ int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev,
struct amdgpu_vm *vm,
r = validate(param, bo);
if (r)
return r;
+ if (bo->shadow) {
+ r = validate(param, bo);
This needs to be "validate(param, bo->shadow)".
Apart from that looks good to me.
Christian.
+ if (r)
+ return r;
+ }
if (bo->tbo.type != ttm_bo_type_kernel) {
amdgpu_vm_bo_moved(bo_base);
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Re: [PATCH 1/7] drm/amdgpu: add amdgpu_bo_vm bo type
Am 26.05.21 um 12:10 schrieb Nirmoy Das:
Add new BO subclass that will be used by amdgpu vm code.
Signed-off-by: Nirmoy Das
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 32 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 10 +++
2 files changed, 42 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 3f85ba8222ef..6870cc297ae6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -694,6 +694,38 @@ int amdgpu_bo_create_user(struct amdgpu_device *adev,
*ubo_ptr = to_amdgpu_bo_user(bo_ptr);
return r;
}
+
+/**
+ * amdgpu_bo_create_vm - create an _bo_vm buffer object
+ * @adev: amdgpu device object
+ * @bp: parameters to be used for the buffer object
+ * @vmbo_ptr: pointer to the buffer object pointer
+ *
+ * Create a BO to be for GPUVM.
+ *
+ * Returns:
+ * 0 for success or a negative error code on failure.
+ */
+
+int amdgpu_bo_create_vm(struct amdgpu_device *adev,
+ struct amdgpu_bo_param *bp,
+ struct amdgpu_bo_vm **vmbo_ptr)
+{
+ struct amdgpu_bo *bo_ptr;
+ int r;
+
+ /* bo_ptr_size will be determined by the caller and it depends on
+* num of amdgpu_vm_pt entries.
+*/
+ BUG_ON(bp->bo_ptr_size < sizeof(struct amdgpu_bo_vm));
+ r = amdgpu_bo_create(adev, bp, _ptr);
+ if (r)
+ return r;
+
+ *vmbo_ptr = to_amdgpu_bo_vm(bo_ptr);
+ return r;
+}
+
/**
* amdgpu_bo_validate - validate an _bo buffer object
* @bo: pointer to the buffer object
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
index 11480c5a2716..a7fbf5f7051e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
@@ -44,6 +44,7 @@
#define AMDGPU_AMDKFD_CREATE_SVM_BO (1ULL << 62)
#define to_amdgpu_bo_user(abo) container_of((abo), struct amdgpu_bo_user, bo)
+#define to_amdgpu_bo_vm(abo) container_of((abo), struct amdgpu_bo_vm, bo)
struct amdgpu_bo_param {
unsigned long size;
@@ -125,6 +126,12 @@ struct amdgpu_bo_user {
};
+struct amdgpu_bo_vm {
+ struct amdgpu_bobo;
+ struct amdgpu_bo*shadow;
+ struct amdgpu_vm_pt entries[];
+};
+
static inline struct amdgpu_bo *ttm_to_amdgpu_bo(struct ttm_buffer_object
*tbo)
{
return container_of(tbo, struct amdgpu_bo, tbo);
@@ -272,6 +279,9 @@ int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev,
int amdgpu_bo_create_user(struct amdgpu_device *adev,
struct amdgpu_bo_param *bp,
struct amdgpu_bo_user **ubo_ptr);
+int amdgpu_bo_create_vm(struct amdgpu_device *adev,
+ struct amdgpu_bo_param *bp,
+ struct amdgpu_bo_vm **ubo_ptr);
void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,
void **cpu_addr);
int amdgpu_bo_create_shadow(struct amdgpu_device *adev,
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Re: [PATCH v4 0/7] drm: Clean up mmap for TTM-based GEM drivers
Patches #1-#4 are Reviewed-by: Christian König Patches #5 and #6 are Acked-by: Christian König Patch #7 already has my rb. I would say push that to drm-misc-next ASAP. Regards, Christian. Am 25.05.21 um 17:10 schrieb Thomas Zimmermann: Implement mmap via struct drm_gem_object_functions.mmap in amdgpu, radeon and nouveau. This allows for using common DRM helpers for the mmap-related callbacks in struct file_operations and struct drm_driver. The drivers have their own vm_ops, which are now set automatically by the DRM core functions. The code in each driver's verify_access becomes part of the driver's new mmap implementation. With the GEM drivers converted, vmwgfx is the only user of ttm_bo_mmap() and related infrastructure. So move everything into vmwgfx and delete the rsp code from TTM. This touches several drivers. Preferably everything would be merged at once via drm-misc-next. v4: * rebase on top of amdgpu hot-unplug changes v3: * tidy up the new mmap functions in amdgpu and radeon (Christian) v2: * removal of amdgpu fbdev mmap already merged (Christian) * rebase on top of amdgpu fixes [1] (Felix) * replace pr_err() with drm_err() in vmwgfx patch (Zack) * several typos [1] https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwork.freedesktop.org%2Fseries%2F88822%2Fdata=04%7C01%7Cchristian.koenig%40amd.com%7C782d195c5e8e4ca6351b08d91f8f4e90%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637575522662233381%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000sdata=ZJ%2BIx9hFBXzQubYpEKcOngREtjjMKwaChyIonKSACFY%3Dreserved=0 Thomas Zimmermann (7): drm/ttm: Don't override vm_ops callbacks, if set drm/amdgpu: Implement mmap as GEM object function drm/radeon: Implement mmap as GEM object function drm/nouveau: Implement mmap as GEM object function drm/vmwgfx: Inline ttm_bo_mmap() into vmwgfx driver drm/vmwgfx: Inline vmw_verify_access() drm/ttm: Remove ttm_bo_mmap() and friends drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 46 - drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h | 2 - drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 4 +- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 55 +++ drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 75 - drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 1 - drivers/gpu/drm/nouveau/nouveau_bo.c| 10 --- drivers/gpu/drm/nouveau/nouveau_drm.c | 3 +- drivers/gpu/drm/nouveau/nouveau_gem.c | 36 ++ drivers/gpu/drm/nouveau/nouveau_ttm.c | 49 -- drivers/gpu/drm/nouveau/nouveau_ttm.h | 1 - drivers/gpu/drm/radeon/radeon_drv.c | 3 +- drivers/gpu/drm/radeon/radeon_gem.c | 49 ++ drivers/gpu/drm/radeon/radeon_ttm.c | 65 -- drivers/gpu/drm/radeon/radeon_ttm.h | 1 - drivers/gpu/drm/ttm/ttm_bo_vm.c | 60 ++--- drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c | 9 --- drivers/gpu/drm/vmwgfx/vmwgfx_ttm_glue.c| 53 ++- include/drm/ttm/ttm_bo_api.h| 13 include/drm/ttm/ttm_device.h| 15 - 20 files changed, 202 insertions(+), 348 deletions(-) base-commit: 28dddc0c90bc6464be4c5e3224a293c022564a4e prerequisite-patch-id: c2b2f08f0eccc9f5df0c0da49fa1d36267deb11d prerequisite-patch-id: c67e5d886a47b7d0266d81100837557fda34cb24 -- 2.31.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH] drm/amdgpu: Correctly clear GCEA error status
[AMD Official Use Only]
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: Joshi, Mukul
Sent: Wednesday, May 26, 2021 04:20
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Clements, John
; Li, Dennis ; Joshi, Mukul
Subject: [PATCH] drm/amdgpu: Correctly clear GCEA error status
While clearing GCEA error status, do not clear the bits set by RAS TA.
Signed-off-by: Mukul Joshi
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c
index 87ec96a18a5d..c0352dcc89be 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c
@@ -1676,13 +1676,14 @@ static void gfx_v9_4_2_reset_ea_err_status(struct
amdgpu_device *adev)
uint32_t i, j;
uint32_t value;
- value = REG_SET_FIELD(0, GCEA_ERR_STATUS, CLEAR_ERROR_STATUS, 0x1);
-
mutex_lock(>grbm_idx_mutex);
for (i = 0; i < gfx_v9_4_2_ea_err_status_regs.se_num; i++) {
for (j = 0; j < gfx_v9_4_2_ea_err_status_regs.instance;
j++) {
gfx_v9_4_2_select_se_sh(adev, i, 0, j);
+ value = RREG32(SOC15_REG_ENTRY_OFFSET(
+ gfx_v9_4_2_ea_err_status_regs));
+ value = REG_SET_FIELD(value, GCEA_ERR_STATUS,
CLEAR_ERROR_STATUS,
+0x1);
WREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_4_2_ea_err_status_regs), value);
}
}
@@ -1734,6 +1735,7 @@ static void gfx_v9_4_2_query_ea_err_status(struct
amdgpu_device *adev)
gfx_v9_4_2_select_se_sh(adev, i, 0, j);
reg_value = RREG32(SOC15_REG_ENTRY_OFFSET(
gfx_v9_4_2_ea_err_status_regs));
+
if (REG_GET_FIELD(reg_value, GCEA_ERR_STATUS,
SDP_RDRSP_STATUS) ||
REG_GET_FIELD(reg_value, GCEA_ERR_STATUS,
SDP_WRRSP_STATUS) ||
REG_GET_FIELD(reg_value, GCEA_ERR_STATUS,
SDP_RDRSP_DATAPARITY_ERROR)) { @@ -1741,7 +1743,9 @@ static void
gfx_v9_4_2_query_ea_err_status(struct amdgpu_device *adev)
j, reg_value);
}
/* clear after read */
-
WREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_4_2_ea_err_status_regs), 0x10);
+ reg_value = REG_SET_FIELD(reg_value, GCEA_ERR_STATUS,
+ CLEAR_ERROR_STATUS, 0x1);
+
WREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_4_2_ea_err_status_regs),
+reg_value);
}
}
--
2.17.1
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Re: [PATCH 6/7] drm/amdgpu: remove unused code
[AMD Official Use Only]
I just realized that I didn't remove the shadow pointer from the amdgpu_bo. I
will update that in the next version.
Regards,
Nirmoy
From: Das, Nirmoy
Sent: Wednesday, May 26, 2021 12:10 PM
To: amd-gfx@lists.freedesktop.org
Cc: Koenig, Christian ; Deucher, Alexander
; Das, Nirmoy
Subject: [PATCH 6/7] drm/amdgpu: remove unused code
Remove unused code related to shadow BO.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 29 --
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 3 ---
2 files changed, 32 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 6870cc297ae6..7930b7d9a3b1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -638,35 +638,6 @@ int amdgpu_bo_create(struct amdgpu_device *adev,
return r;
}
-int amdgpu_bo_create_shadow(struct amdgpu_device *adev,
- unsigned long size,
- struct amdgpu_bo *bo)
-{
- struct amdgpu_bo_param bp;
- int r;
-
- if (bo->shadow)
- return 0;
-
- memset(, 0, sizeof(bp));
- bp.size = size;
- bp.domain = AMDGPU_GEM_DOMAIN_GTT;
- bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
- bp.type = ttm_bo_type_kernel;
- bp.resv = bo->tbo.base.resv;
- bp.bo_ptr_size = sizeof(struct amdgpu_bo);
-
- r = amdgpu_bo_create(adev, , >shadow);
- if (!r) {
- bo->shadow->parent = amdgpu_bo_ref(bo);
- mutex_lock(>shadow_list_lock);
- list_add_tail(>shadow->shadow_list, >shadow_list);
- mutex_unlock(>shadow_list_lock);
- }
-
- return r;
-}
-
/**
* amdgpu_bo_create_user - create an _bo_user buffer object
* @adev: amdgpu device object
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
index a7fbf5f7051e..b8555c527613 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
@@ -284,9 +284,6 @@ int amdgpu_bo_create_vm(struct amdgpu_device *adev,
struct amdgpu_bo_vm **ubo_ptr);
void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,
void **cpu_addr);
-int amdgpu_bo_create_shadow(struct amdgpu_device *adev,
- unsigned long size,
- struct amdgpu_bo *bo);
int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr);
void *amdgpu_bo_kptr(struct amdgpu_bo *bo);
void amdgpu_bo_kunmap(struct amdgpu_bo *bo);
--
2.31.1
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RE: [PATCH] free the metadata buffer for sg type BOs as well
[AMD Official Use Only]
Please add a commit message as well.
With that, this is Acked-by: Nirmoy Das but Christian
should review it as well.
Nirmoy
-Original Message-
From: Zhang, Morris
Sent: Wednesday, May 26, 2021 5:46 AM
To: amd-gfx@lists.freedesktop.org; Das, Nirmoy
Subject: [PATCH] free the metadata buffer for sg type BOs as well
Signed-off-by: Shiwu Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 2d876e1eaa7c..e9f8701fd046 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -95,7 +95,7 @@ static void amdgpu_bo_destroy(struct ttm_buffer_object *tbo)
}
amdgpu_bo_unref(>parent);
- if (bo->tbo.type == ttm_bo_type_device) {
+ if (bo->tbo.type != ttm_bo_type_kernel) {
ubo = to_amdgpu_bo_user(bo);
kfree(ubo->metadata);
}
--
2.17.1
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Re: radeon ring 0 test failed on arm64
Hi Robin, Am 26.05.21 um 12:59 schrieb Robin Murphy: On 2021-05-26 10:42, Christian König wrote: Hi Robin, Am 25.05.21 um 22:09 schrieb Robin Murphy: On 2021-05-25 14:05, Alex Deucher wrote: On Tue, May 25, 2021 at 8:56 AM Peter Geis wrote: On Tue, May 25, 2021 at 8:47 AM Alex Deucher wrote: On Tue, May 25, 2021 at 8:42 AM Peter Geis wrote: Good Evening, I am stress testing the pcie controller on the rk3566-quartz64 prototype SBC. This device has 1GB available at <0x3 0x> for the PCIe controller, which makes a dGPU theoretically possible. While attempting to light off a HD7570 card I manage to get a modeset console, but ring0 test fails and disables acceleration. Note, we do not have UEFI, so all PCIe setup is from the Linux kernel. Any insight you can provide would be much appreciated. Does your platform support PCIe cache coherency with the CPU? I.e., does the CPU allow cache snoops from PCIe devices? That is required for the driver to operate. Ah, most likely not. This issue has come up already as the GIC isn't permitted to snoop on the CPUs, so I doubt the PCIe controller can either. Is there no way to work around this or is it dead in the water? It's required by the pcie spec. You could potentially work around it if you can allocate uncached memory for DMA, but I don't think that is possible currently. Ideally we'd figure out some way to detect if a particular platform supports cache snooping or not as well. There's device_get_dma_attr(), although I don't think it will work currently for PCI devices without an OF or ACPI node - we could perhaps do with a PCI-specific wrapper which can walk up and defer to the host bridge's firmware description as necessary. The common DMA ops *do* correctly keep track of per-device coherency internally, but drivers aren't supposed to be poking at that information directly. That sounds like you underestimate the problem. ARM has unfortunately made the coherency for PCI an optional IP. Sorry to be that guy, but I'm involved a lot internally with our system IP and interconnect, and I probably understand the situation better than 99% of the community ;) I need to apologize, didn't realized who was answering :) It just sounded to me that you wanted to suggest to the end user that this is fixable in software and I really wanted to avoid even more customers coming around asking how to do this. For the record, the SBSA specification (the closet thing we have to a "system architecture") does require that PCIe is integrated in an I/O-coherent manner, but we don't have any control over what people do in embedded applications (note that we don't make PCIe IP at all, and there is plenty of 3rd-party interconnect IP). So basically it is not the fault of the ARM IP-core, but people are just stitching together PCIe interconnect IP with a core where it is not supposed to be used with. Do I get that correctly? That's an interesting puzzle piece in the picture. So we are talking about a hardware limitation which potentially can't be fixed without replacing the hardware. You expressed interest in "some way to detect if a particular platform supports cache snooping or not", by which I assumed you meant a software method for the amdgpu/radeon drivers to call, rather than, say, a website that driver maintainers can look up SoC names on. I'm saying that that API already exists (just may need a bit more work). Note that it is emphatically not a platform-level thing since coherency can and does vary per device within a system. Well, I think this is not something an individual driver should mess with. What the driver should do is just express that it needs coherent access to all of system memory and if that is not possible fail to load with a warning why it is not possible. I wasn't suggesting that Linux could somehow make coherency magically work when the signals don't physically exist in the interconnect - I was assuming you'd merely want to do something like throw a big warning and taint the kernel to help triage bug reports. Some drivers like ahci_qoriq and panfrost simply need to know so they can program their device to emit the appropriate memory attributes either way, and rely on the DMA API to hide the rest of the difference, but if you want to treat non-coherent use as unsupported because it would require too invasive changes that's fine by me. Yes exactly that please. I mean not sure how panfrost is doing it, but at least the Vulkan userspace API specification requires devices to have coherent access to system memory. So even if I would want to do this it is simply not possible because the application doesn't tell the driver which memory is accessed by the device and which by the CPU. Christian. Robin. ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH 3/3] drm/amdgpu: Use delayed work to collect RAS error counters
[AMD Official Use Only]
Scheduling an error status query just based on IOCTL doesn't sound like a sound
approach. What if driver needs to handle errors based on that - for ex: if the
number of correctable errors exceed a certain threshold?
IMO, I'm more aligned to Luben's original approach of having something waiting
in the background - instead of a periodic timer based trigger, it could be an
event based trigger. Event may be an ioctl, error handler timer ticks or
something else.
Thanks,
Lijo
-Original Message-
From: amd-gfx On Behalf Of Luben Tuikov
Sent: Saturday, May 22, 2021 2:49 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Tuikov, Luben
; Clements, John ; Koenig,
Christian ; Zhang, Hawking
Subject: [PATCH 3/3] drm/amdgpu: Use delayed work to collect RAS error counters
On Context Query2 IOCTL return the correctable and uncorrectable errors in O(1)
fashion, from cached values, and schedule a delayed work function to calculate
and cache them for the next such IOCTL.
Cc: Alexander Deucher
Cc: Christian König
Cc: John Clements
Cc: Hawking Zhang
Signed-off-by: Luben Tuikov
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 32 +++--
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 38 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 5
3 files changed, 73 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index bb0cfe871aba..4e95d255960b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -331,10 +331,13 @@ static int amdgpu_ctx_query(struct amdgpu_device *adev,
return 0;
}
+#define AMDGPU_RAS_COUNTE_DELAY_MS 3000
+
static int amdgpu_ctx_query2(struct amdgpu_device *adev,
- struct amdgpu_fpriv *fpriv, uint32_t id,
- union drm_amdgpu_ctx_out *out)
+struct amdgpu_fpriv *fpriv, uint32_t id,
+union drm_amdgpu_ctx_out *out)
{
+ struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
struct amdgpu_ctx *ctx;
struct amdgpu_ctx_mgr *mgr;
@@ -361,6 +364,31 @@ static int amdgpu_ctx_query2(struct amdgpu_device *adev,
if (atomic_read(>guilty))
out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_GUILTY;
+ if (adev->ras_enabled && con) {
+ /* Return the cached values in O(1),
+* and schedule delayed work to cache
+* new vaues.
+*/
+ int ce_count, ue_count;
+
+ ce_count = atomic_read(>ras_ce_count);
+ ue_count = atomic_read(>ras_ue_count);
+
+ if (ce_count != ctx->ras_counter_ce) {
+ ctx->ras_counter_ce = ce_count;
+ out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RAS_CE;
+ }
+
+ if (ue_count != ctx->ras_counter_ue) {
+ ctx->ras_counter_ue = ue_count;
+ out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RAS_UE;
+ }
+
+ if (!delayed_work_pending(>ras_counte_delay_work))
+ schedule_delayed_work(>ras_counte_delay_work,
+ msecs_to_jiffies(AMDGPU_RAS_COUNTE_DELAY_MS));
+ }
+
mutex_unlock(>lock);
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index ed3c43e8b0b5..80f576098318 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -27,6 +27,7 @@
#include
#include
#include
+#include
#include "amdgpu.h"
#include "amdgpu_ras.h"
@@ -2116,6 +2117,30 @@ static void amdgpu_ras_check_supported(struct
amdgpu_device *adev)
adev->ras_hw_enabled & amdgpu_ras_mask; }
+static void amdgpu_ras_counte_dw(struct work_struct *work) {
+ struct amdgpu_ras *con = container_of(work, struct amdgpu_ras,
+ ras_counte_delay_work.work);
+ struct amdgpu_device *adev = con->adev;
+ struct drm_device *dev = >ddev;
+ unsigned long ce_count, ue_count;
+ int res;
+
+ res = pm_runtime_get_sync(dev->dev);
+ if (res < 0)
+ goto Out;
+
+ /* Cache new values.
+*/
+ amdgpu_ras_query_error_count(adev, _count, _count);
+ atomic_set(>ras_ce_count, ce_count);
+ atomic_set(>ras_ue_count, ue_count);
+
+ pm_runtime_mark_last_busy(dev->dev);
+Out:
+ pm_runtime_put_autosuspend(dev->dev);
+}
+
int amdgpu_ras_init(struct amdgpu_device *adev) {
struct amdgpu_ras *con = amdgpu_ras_get_context(adev); @@ -2130,6
+2155,11 @@ int amdgpu_ras_init(struct amdgpu_device *adev)
if (!con)
return -ENOMEM;
+ con->adev = adev;
+ INIT_DELAYED_WORK(>ras_counte_delay_work, amdgpu_ras_counte_dw);
+
Re: [PATCH] drm/amdgpu: Fix Gstreamer api vaapih264enc missing
Am 26.05.21 um 12:13 schrieb Li, Xin (Justin):
since vcn decoding ring is not required, so just disable it.
Cc: Alex.Deucher
Cc: Christian.Konig
Signed-off-by: Li.Xin.Justin
Signed-off-by: Frank.Min
---
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 25 ++---
2 files changed, 17 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 524e4fe5efe8..614e6b06e94e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -427,7 +427,9 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
if (adev->uvd.harvest_config & (1 << i))
continue;
- if (adev->vcn.inst[i].ring_dec.sched.ready)
+ if (adev->vcn.inst[i].ring_dec.sched.ready ||
+ (adev->asic_type == CHIP_NAVI12 &&
+ amdgpu_sriov_vf(adev)))
Leo needs to take a closer look, but that looks fishy to me.
Why should the ring be available if it is disabled? That doesn't make sense.
Christian.
++num_rings;
}
ib_start_alignment = 16;
@@ -770,8 +772,6 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data,
struct drm_file *filp)
dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
if (amdgpu_mcbp || amdgpu_sriov_vf(adev))
dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
- if (amdgpu_is_tmz(adev))
- dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ;
vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
vm_size -= AMDGPU_VA_RESERVED_SIZE;
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index 8af567c546db..dc8a36766c4a 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -220,17 +220,20 @@ static int vcn_v2_0_hw_init(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct amdgpu_ring *ring = >vcn.inst->ring_dec;
- int i, r;
+ int i, r = -1;
adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
ring->doorbell_index, 0);
- if (amdgpu_sriov_vf(adev))
+ if (amdgpu_sriov_vf(adev)) {
vcn_v2_0_start_sriov(adev);
-
- r = amdgpu_ring_test_helper(ring);
- if (r)
- goto done;
+ if (adev->asic_type == CHIP_NAVI12)
+ ring->sched.ready = false;
+ } else {
+ r = amdgpu_ring_test_helper(ring);
+ if (r)
+ goto done;
+ }
//Disable vcn decode for sriov
if (amdgpu_sriov_vf(adev))
@@ -245,8 +248,11 @@ static int vcn_v2_0_hw_init(void *handle)
done:
if (!r)
- DRM_INFO("VCN decode and encode initialized successfully(under
%s).\n",
- (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG
Mode");
+ DRM_INFO("VCN %s encode initialized successfully(under %s).\n",
+ (adev->asic_type == CHIP_NAVI12 &&
+ amdgpu_sriov_vf(adev))?"":"decode and",
+ (adev->pg_flags &
+ AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode");
return r;
}
@@ -1721,9 +1727,6 @@ int vcn_v2_0_dec_ring_test_ring(struct amdgpu_ring *ring)
unsigned i;
int r;
- if (amdgpu_sriov_vf(adev))
- return 0;
-
WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD);
r = amdgpu_ring_alloc(ring, 4);
if (r)
___
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