[PATCH] drm/amdgpu: Fix a a typo in a comment

[Christophe JAILLET]

s/than/then/

Signed-off-by: Christophe JAILLET 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 89ebbf363e27..1476236f5c7c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -662,7 +662,7 @@ static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
  * @error: error number
  * @backoff:   indicator to backoff the reservation
  *
- * If error is set than unvalidate buffer, otherwise just free memory
+ * If error is set then unvalidate buffer, otherwise just free memory
  * used by parsing context.
  **/
 static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error,
-- 
2.30.2

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[PATCH] drm/amd/display: remove no need variable

[Bernard Zhao]

remove no need variable, just return the DC_OK

Signed-off-by: Bernard Zhao 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index f962b905e79e..7daadb6a5233 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -1266,8 +1266,6 @@ static enum dc_status dcn10_validate_global(struct dc 
*dc, struct dc_state *cont
 
 static enum dc_status dcn10_patch_unknown_plane_state(struct dc_plane_state 
*plane_state)
 {
-   enum dc_status result = DC_OK;
-
enum surface_pixel_format surf_pix_format = plane_state->format;
unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format);
 
@@ -1279,7 +1277,7 @@ static enum dc_status 
dcn10_patch_unknown_plane_state(struct dc_plane_state *pla
swizzle = DC_SW_64KB_S;
 
plane_state->tiling_info.gfx9.swizzle = swizzle;
-   return result;
+   return DC_OK;
 }
 
 struct stream_encoder *dcn10_find_first_free_match_stream_enc_for_link(
-- 
2.31.0

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[PATCH] drm/amdgpu: Update psp fw attestation support list

[Clements, John]

[AMD Official Use Only - Internal Distribution Only]

Submitting patch to disable PSP FW attestation support on APU

Thank you,
John Clements


0001-drm-amdgpu-Update-psp-fw-attestation-support-list.patch
Description: 0001-drm-amdgpu-Update-psp-fw-attestation-support-list.patch
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RE: [PATCH] drm/amdgpu: Update psp fw attestation support list

[Zhu, Changfeng]

Hi John,

I think it's better to replace
if (adev->flags & AMD_IS_APU)
with
if (adev->asic_type >= CHIP_VANGOGH)

As you say, rembrandt should support this feature.

BR,
Changfeng.

From: Clements, John 
Sent: Monday, June 7, 2021 11:13 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhu, Changfeng 
Subject: [PATCH] drm/amdgpu: Update psp fw attestation support list


[AMD Official Use Only - Internal Distribution Only]

Submitting patch to disable PSP FW attestation support on APU

Thank you,
John Clements
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RE: [PATCH] drm/amdgpu: Update psp fw attestation support list

[Zhu, Changfeng]

if (adev->asic_type == CHIP_VANGOGH)

BR,
Changfeng.


From: amd-gfx  On Behalf Of Zhu, 
Changfeng
Sent: Monday, June 7, 2021 11:24 AM
To: Clements, John ; amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH] drm/amdgpu: Update psp fw attestation support list

Hi John,

I think it's better to replace
if (adev->flags & AMD_IS_APU)
with
if (adev->asic_type >= CHIP_VANGOGH)

As you say, rembrandt should support this feature.

BR,
Changfeng.

From: Clements, John mailto:john.cleme...@amd.com>>
Sent: Monday, June 7, 2021 11:13 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhu, Changfeng mailto:changfeng@amd.com>>
Subject: [PATCH] drm/amdgpu: Update psp fw attestation support list


[AMD Official Use Only - Internal Distribution Only]

Submitting patch to disable PSP FW attestation support on APU

Thank you,
John Clements
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Recall: [PATCH] drm/amdgpu: Update psp fw attestation support list

[Zhu, Changfeng]

Zhu, Changfeng would like to recall the message, "[PATCH] drm/amdgpu: Update 
psp fw attestation support list".
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Recall: [PATCH] drm/amdgpu: Update psp fw attestation support list

[Zhu, Changfeng]

Zhu, Changfeng would like to recall the message, "[PATCH] drm/amdgpu: Update 
psp fw attestation support list".
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Re: [PATCH 2/4] drm/uAPI: Add "active bpc" as feedback channel for "max bpc" drm property

[Pekka Paalanen]

On Fri,  4 Jun 2021 19:17:21 +0200
Werner Sembach  wrote:

> Add a new general drm property "active bpc" which can be used by graphic 
> drivers
> to report the applied bit depth per pixel back to userspace.
> 
> While "max bpc" can be used to change the color depth, there was no way to 
> check
> which one actually got used. While in theory the driver chooses the 
> best/highest
> color depth within the max bpc setting a user might not be fully aware what 
> his
> hardware is or isn't capable off. This is meant as a quick way to double check
> the setup.
> 
> In the future, automatic color calibration for screens might also depend on 
> this
> information available.
> 
> Signed-off-by: Werner Sembach 
> ---
>  drivers/gpu/drm/drm_atomic_uapi.c |  2 ++
>  drivers/gpu/drm/drm_connector.c   | 40 +++
>  include/drm/drm_connector.h   | 15 
>  3 files changed, 57 insertions(+)
> 
> diff --git a/drivers/gpu/drm/drm_atomic_uapi.c 
> b/drivers/gpu/drm/drm_atomic_uapi.c
> index 268bb69c2e2f..7ae4e40936b5 100644
> --- a/drivers/gpu/drm/drm_atomic_uapi.c
> +++ b/drivers/gpu/drm/drm_atomic_uapi.c
> @@ -873,6 +873,8 @@ drm_atomic_connector_get_property(struct drm_connector 
> *connector,
>   *val = 0;
>   } else if (property == connector->max_bpc_property) {
>   *val = state->max_requested_bpc;
> + } else if (property == connector->active_bpc_property) {
> + *val = state->active_bpc;
>   } else if (connector->funcs->atomic_get_property) {
>   return connector->funcs->atomic_get_property(connector,
>   state, property, val);
> diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
> index 7631f76e7f34..5f42a5be5822 100644
> --- a/drivers/gpu/drm/drm_connector.c
> +++ b/drivers/gpu/drm/drm_connector.c
> @@ -1195,6 +1195,13 @@ static const struct drm_prop_enum_list 
> dp_colorspaces[] = {
>   *   drm_connector_attach_max_bpc_property() to create and attach the
>   *   property to the connector during initialization.
>   *
> + * active bpc:
> + *   This read-only range property is used by userspace check the bit depth
> + *   actually applied by the GPU driver after evaluation all hardware
> + *   capabilities and max bpc. Drivers to use the function
> + *   drm_connector_attach_active_bpc_property() to create and attach the
> + *   property to the connector during initialization.
> + *

Hi Werner,

the idea looks good to me, but the above doc could be a little more
fluent. May I suggest something like:

This read-only range property tells userspace the pixel color
bit depth actually used by the hardware display engine on "the
cable" on a connector. The chosen value depends on hardware
capabilities, both display engine and connected monitor, and
the "max bpc" property. Drivers shall use
drm_connector_attach_active_bpc_property() to install this
property.

There should also be something said about dithering done by the display
engine (not monitor), but I'm not sure how that should be worded. It
may also depend on if and how userspace can know about dithering. So if
a dithering related property is added later, maybe add a note here too
in that patch.


Thanks,
pq


>   * Connectors also have one standardized atomic property:
>   *
>   * CRTC_ID:
> @@ -2150,6 +2157,39 @@ int drm_connector_attach_max_bpc_property(struct 
> drm_connector *connector,
>  }
>  EXPORT_SYMBOL(drm_connector_attach_max_bpc_property);
>  
> +/**
> + * drm_connector_attach_active_bpc_property - attach "active bpc" property
> + * @connector: connector to attach active bpc property on.
> + * @min: The minimum bit depth supported by the connector.
> + * @max: The maximum bit depth supported by the connector.
> + *
> + * This is used to check the applied bit depth on a connector.
> + *
> + * Returns:
> + * Zero on success, negative errno on failure.
> + */
> +int drm_connector_attach_active_bpc_property(struct drm_connector *connector,
> +   int min, int max)
> +{
> + struct drm_device *dev = connector->dev;
> + struct drm_property *prop;
> +
> + prop = connector->active_bpc_property;
> + if (!prop) {
> + prop = drm_property_create_range(dev, 0, "active bpc", min, 
> max);
> + if (!prop)
> + return -ENOMEM;
> +
> + connector->active_bpc_property = prop;
> + }
> +
> + drm_object_attach_property(&connector->base, prop, 0);
> + connector->state->active_bpc = 0;
> +
> + return 0;
> +}
> +EXPORT_SYMBOL(drm_connector_attach_active_bpc_property);
> +
>  /**
>   * drm_connector_set_vrr_capable_property - sets the variable refresh rate
>   * capable property for a connector
> diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
> index 1922b278ffad..c58cba2b6afe 100644
> --- a/include/drm/drm_connector.h
> +++ b/includ

Re: [PATCH 2/4] drm/uAPI: Add "active bpc" as feedback channel for "max bpc" drm property

[Werner Sembach]

Am 07.06.21 um 09:40 schrieb Maxime Ripard:

Hi,

On Fri, Jun 04, 2021 at 07:17:21PM +0200, Werner Sembach wrote:

Add a new general drm property "active bpc" which can be used by graphic drivers
to report the applied bit depth per pixel back to userspace.

Just a heads up, we'll need an open source project that has accepted it
before merging it.

See 
https://www.kernel.org/doc/html/latest/gpu/drm-uapi.html#open-source-userspace-requirements

Yes, I know.



While "max bpc" can be used to change the color depth, there was no way to check
which one actually got used. While in theory the driver chooses the best/highest
color depth within the max bpc setting a user might not be fully aware what his
hardware is or isn't capable off. This is meant as a quick way to double check
the setup.

In the future, automatic color calibration for screens might also depend on this
information available.

Signed-off-by: Werner Sembach 
---
  drivers/gpu/drm/drm_atomic_uapi.c |  2 ++
  drivers/gpu/drm/drm_connector.c   | 40 +++
  include/drm/drm_connector.h   | 15 
  3 files changed, 57 insertions(+)

diff --git a/drivers/gpu/drm/drm_atomic_uapi.c 
b/drivers/gpu/drm/drm_atomic_uapi.c
index 268bb69c2e2f..7ae4e40936b5 100644
--- a/drivers/gpu/drm/drm_atomic_uapi.c
+++ b/drivers/gpu/drm/drm_atomic_uapi.c
@@ -873,6 +873,8 @@ drm_atomic_connector_get_property(struct drm_connector 
*connector,
*val = 0;
} else if (property == connector->max_bpc_property) {
*val = state->max_requested_bpc;
+   } else if (property == connector->active_bpc_property) {
+   *val = state->active_bpc;
} else if (connector->funcs->atomic_get_property) {
return connector->funcs->atomic_get_property(connector,
state, property, val);
diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index 7631f76e7f34..5f42a5be5822 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -1195,6 +1195,13 @@ static const struct drm_prop_enum_list dp_colorspaces[] 
= {
   *drm_connector_attach_max_bpc_property() to create and attach the
   *property to the connector during initialization.
   *
+ * active bpc:
+ * This read-only range property is used by userspace check the bit depth
+ * actually applied by the GPU driver after evaluation all hardware

 ^ display

Depending on the system, the display component might have a GPU attached
or not, and the GPU might have a display component or not.

Ok, I try to bee more clear in the wording



+ * capabilities and max bpc. Drivers to use the function
+ * drm_connector_attach_active_bpc_property() to create and attach the
+ * property to the connector during initialization.
+ *
   * Connectors also have one standardized atomic property:
   *
   * CRTC_ID:
@@ -2150,6 +2157,39 @@ int drm_connector_attach_max_bpc_property(struct 
drm_connector *connector,
  }
  EXPORT_SYMBOL(drm_connector_attach_max_bpc_property);
  
+/**

+ * drm_connector_attach_active_bpc_property - attach "active bpc" property
+ * @connector: connector to attach active bpc property on.
+ * @min: The minimum bit depth supported by the connector.
+ * @max: The maximum bit depth supported by the connector.
+ *
+ * This is used to check the applied bit depth on a connector.
+ *
+ * Returns:
+ * Zero on success, negative errno on failure.
+ */
+int drm_connector_attach_active_bpc_property(struct drm_connector *connector,
+ int min, int max)
+{
+   struct drm_device *dev = connector->dev;
+   struct drm_property *prop;
+
+   prop = connector->active_bpc_property;
+   if (!prop) {
+   prop = drm_property_create_range(dev, 0, "active bpc", min, 
max);
+   if (!prop)
+   return -ENOMEM;
+
+   connector->active_bpc_property = prop;
+   }
+
+   drm_object_attach_property(&connector->base, prop, 0);
+   connector->state->active_bpc = 0;

I guess we want to default to 8?

Maxime
The default state should only be active when no display is connected or 
the display is off, so I thought 0 makes more sense, as no active 
display = no active bpc.

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Re: New uAPI for color management proposal and feedback request

[Pekka Paalanen]

On Mon, 7 Jun 2021 09:48:05 +0200
Maxime Ripard  wrote:

> I've started to implement this for the raspberrypi some time ago.
> 
> https://github.com/raspberrypi/linux/pull/4201
> 
> It's basically two properties: a bitmask of the available output pixel
> encoding to report both what the display and the controller supports,
> and one to actually set what the userspace wants to get enforced (and
> that would return the active one when read).

Hi Maxime,

I would like to point out that I think it is a bad design to create a
read/write property that returns not what was written to it. It can
cause headaches to userspace that wants to save and restore property
values it does not understand. Userspace would want to do that to
mitigate damage from switching to another KMS client and then back. The
other KMS client could change properties the first KMS client does not
understand, causing the first KMS client to show incorrectly after
switching back.

Please, consider whether this use-case will work before designing a
property where read-back may not necessarily return the written value.


Thanks,
pq


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Recall: [PATCH] drm/amdgpu: Update psp fw attestation support list

[Zhu, Changfeng]

Zhu, Changfeng would like to recall the message, "[PATCH] drm/amdgpu: Update 
psp fw attestation support list".
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RE: [PATCH] drm/amdgpu: Update psp fw attestation support list

[Zhu, Changfeng]

Hi John,

As talked offline, the patch fine with apu at present.

Reviewed-by: Changfeng 


BR,
Changfeng.

From: Clements, John 
Sent: Monday, June 7, 2021 11:13 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhu, Changfeng 
Subject: [PATCH] drm/amdgpu: Update psp fw attestation support list


[AMD Official Use Only - Internal Distribution Only]

Submitting patch to disable PSP FW attestation support on APU

Thank you,
John Clements
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Re: [PATCH 2/4] drm/uAPI: Add "active bpc" as feedback channel for "max bpc" drm property

[Werner Sembach]

Am 07.06.21 um 09:52 schrieb Pekka Paalanen:

On Fri,  4 Jun 2021 19:17:21 +0200
Werner Sembach  wrote:


Add a new general drm property "active bpc" which can be used by graphic drivers
to report the applied bit depth per pixel back to userspace.

While "max bpc" can be used to change the color depth, there was no way to check
which one actually got used. While in theory the driver chooses the best/highest
color depth within the max bpc setting a user might not be fully aware what his
hardware is or isn't capable off. This is meant as a quick way to double check
the setup.

In the future, automatic color calibration for screens might also depend on this
information available.

Signed-off-by: Werner Sembach 
---
  drivers/gpu/drm/drm_atomic_uapi.c |  2 ++
  drivers/gpu/drm/drm_connector.c   | 40 +++
  include/drm/drm_connector.h   | 15 
  3 files changed, 57 insertions(+)

diff --git a/drivers/gpu/drm/drm_atomic_uapi.c 
b/drivers/gpu/drm/drm_atomic_uapi.c
index 268bb69c2e2f..7ae4e40936b5 100644
--- a/drivers/gpu/drm/drm_atomic_uapi.c
+++ b/drivers/gpu/drm/drm_atomic_uapi.c
@@ -873,6 +873,8 @@ drm_atomic_connector_get_property(struct drm_connector 
*connector,
*val = 0;
} else if (property == connector->max_bpc_property) {
*val = state->max_requested_bpc;
+   } else if (property == connector->active_bpc_property) {
+   *val = state->active_bpc;
} else if (connector->funcs->atomic_get_property) {
return connector->funcs->atomic_get_property(connector,
state, property, val);
diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index 7631f76e7f34..5f42a5be5822 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -1195,6 +1195,13 @@ static const struct drm_prop_enum_list dp_colorspaces[] 
= {
   *drm_connector_attach_max_bpc_property() to create and attach the
   *property to the connector during initialization.
   *
+ * active bpc:
+ * This read-only range property is used by userspace check the bit depth
+ * actually applied by the GPU driver after evaluation all hardware
+ * capabilities and max bpc. Drivers to use the function
+ * drm_connector_attach_active_bpc_property() to create and attach the
+ * property to the connector during initialization.
+ *

Hi Werner,

the idea looks good to me, but the above doc could be a little more
fluent. May I suggest something like:

This read-only range property tells userspace the pixel color
bit depth actually used by the hardware display engine on "the
cable" on a connector. The chosen value depends on hardware
capabilities, both display engine and connected monitor, and
the "max bpc" property. Drivers shall use
drm_connector_attach_active_bpc_property() to install this
property.

There should also be something said about dithering done by the display
engine (not monitor), but I'm not sure how that should be worded. It
may also depend on if and how userspace can know about dithering. So if
a dithering related property is added later, maybe add a note here too
in that patch.
For this, and the DSC that Ville Syrjälä mentioned, I guess "the same 
behavior as max bpc" would be the most intuitive. But I don't know what 
that is and it's also not mentioned in the documentation.



Thanks,
pq



   * Connectors also have one standardized atomic property:
   *
   * CRTC_ID:
@@ -2150,6 +2157,39 @@ int drm_connector_attach_max_bpc_property(struct 
drm_connector *connector,
  }
  EXPORT_SYMBOL(drm_connector_attach_max_bpc_property);
  
+/**

+ * drm_connector_attach_active_bpc_property - attach "active bpc" property
+ * @connector: connector to attach active bpc property on.
+ * @min: The minimum bit depth supported by the connector.
+ * @max: The maximum bit depth supported by the connector.
+ *
+ * This is used to check the applied bit depth on a connector.
+ *
+ * Returns:
+ * Zero on success, negative errno on failure.
+ */
+int drm_connector_attach_active_bpc_property(struct drm_connector *connector,
+ int min, int max)
+{
+   struct drm_device *dev = connector->dev;
+   struct drm_property *prop;
+
+   prop = connector->active_bpc_property;
+   if (!prop) {
+   prop = drm_property_create_range(dev, 0, "active bpc", min, 
max);
+   if (!prop)
+   return -ENOMEM;
+
+   connector->active_bpc_property = prop;
+   }
+
+   drm_object_attach_property(&connector->base, prop, 0);
+   connector->state->active_bpc = 0;
+
+   return 0;
+}
+EXPORT_SYMBOL(drm_connector_attach_active_bpc_property);
+
  /**
   * drm_connector_set_vrr_capable_property - sets the variable refresh rate
   * capable property for a connector
diff --git a/include/drm/drm_connector.h b/inc

[PATCH] drm/amdgpu: Fixing "Indirect register access for Navi12 sriov" for vega10

[Peng Ju Zhou]

The NV12 and VEGA10 share the same interface W/RREG32_SOC15*,
the callback functions in these macros may not be defined,
so NULL pointer must be checked but not in
macro __WREG32_SOC15_RLC__, fixing the lock of NULL pointer check.

Signed-off-by: Peng Ju Zhou 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 ++-
 drivers/gpu/drm/amd/amdgpu/soc15_common.h | 4 ++--
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index fe5908f708cc..044076ec1d03 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -790,7 +790,8 @@ static void gfx_v9_0_rlcg_w(struct amdgpu_device *adev, u32 
offset, u32 v, u32 f
 static void gfx_v9_0_rlcg_wreg(struct amdgpu_device *adev, u32 offset,
   u32 v, u32 acc_flags, u32 hwip)
 {
-   if (amdgpu_sriov_fullaccess(adev)) {
+   if ((acc_flags & AMDGPU_REGS_RLC) &&
+   amdgpu_sriov_fullaccess(adev)) {
gfx_v9_0_rlcg_w(adev, offset, v, acc_flags);
 
return;
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h 
b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
index f6cf70e69cce..0eeb5e073be8 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15_common.h
+++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
@@ -28,12 +28,12 @@
 #define SOC15_REG_OFFSET(ip, inst, reg)
(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
 
 #define __WREG32_SOC15_RLC__(reg, value, flag, hwip) \
-   ((amdgpu_sriov_runtime(adev) && adev->gfx.rlc.funcs->rlcg_wreg) ? \
+   ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs && 
adev->gfx.rlc.funcs->rlcg_wreg) ? \
 adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, value, flag, hwip) : \
 WREG32(reg, value))
 
 #define __RREG32_SOC15_RLC__(reg, flag, hwip) \
-   ((amdgpu_sriov_runtime(adev) && adev->gfx.rlc.funcs->rlcg_rreg) ? \
+   ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs && 
adev->gfx.rlc.funcs->rlcg_rreg) ? \
 adev->gfx.rlc.funcs->rlcg_rreg(adev, reg, flag, hwip) : \
 RREG32(reg))
 
-- 
2.17.1

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Re: [PATCH] drm/amdgpu: Fix a a typo in a comment

[Christian König]

Am 05.06.21 um 11:06 schrieb Christophe JAILLET:

s/than/then/

Signed-off-by: Christophe JAILLET 


Acked-by: Christian König 


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 89ebbf363e27..1476236f5c7c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -662,7 +662,7 @@ static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
   * @error:error number
   * @backoff:  indicator to backoff the reservation
   *
- * If error is set than unvalidate buffer, otherwise just free memory
+ * If error is set then unvalidate buffer, otherwise just free memory
   * used by parsing context.
   **/
  static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error,


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RE: [PATCH V2 3/5] drm/amdgpu: correct the audio function initial Dstate

[Quan, Evan]

[AMD Official Use Only]



> -Original Message-
> From: Lazar, Lijo 
> Sent: Friday, June 4, 2021 8:24 PM
> To: Quan, Evan ; amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander 
> Subject: Re: [PATCH V2 3/5] drm/amdgpu: correct the audio function initial
> Dstate
> 
> 
> 
> On 6/4/2021 3:28 PM, Evan Quan wrote:
> > On driver loading, the ASIC is in D0 state. The bundled audio function
> > should be in the same state also.
> >
> > Change-Id: I136e196be7633e95883a7f6c33963f7583e9bad1
> > Signed-off-by: Evan Quan 
> > ---
> > V1->V2:
> >- Lijo: include the code in a seperate API for better readability
> >- limit the change for Navi10 and later dGPUs
> >- comments more about the background
> > ---
> >   drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 40
> +
> >   1 file changed, 40 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> > index c354ffa62483..e9f2161738d1 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> > @@ -123,6 +123,22 @@ void amdgpu_register_gpu_instance(struct
> amdgpu_device *adev)
> > mutex_unlock(&mgpu_info.mutex);
> >   }
> >
> > +static void amdgpu_get_audio_func(struct amdgpu_device *adev) {
> > +   struct pci_dev *p = NULL;
> > +
> > +   p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev-
> >bus),
> > +   adev->pdev->bus->number, 1);
> > +   if (p) {
> > +   pm_runtime_get_sync(&p->dev);
> > +
> > +   pm_runtime_mark_last_busy(&p->dev);
> > +   pm_runtime_put_autosuspend(&p->dev);
> > +
> > +   pci_dev_put(p);
> > +   }
> > +}
> > +
> >   /**
> >* amdgpu_driver_load_kms - Main load function for KMS.
> >*
> > @@ -212,9 +228,33 @@ int amdgpu_driver_load_kms(struct
> amdgpu_device *adev, unsigned long flags)
> >
>   DPM_FLAG_MAY_SKIP_RESUME);
> > pm_runtime_use_autosuspend(dev->dev);
> > pm_runtime_set_autosuspend_delay(dev->dev, 5000);
> > +
> > pm_runtime_allow(dev->dev);
> > +
> > pm_runtime_mark_last_busy(dev->dev);
> > pm_runtime_put_autosuspend(dev->dev);
> > +
> > +   /*
> > +* For runpm implemented via BACO, PMFW will handle the
> > +* timing for BACO in and out:
> > +*   - put ASIC into BACO state only when both video and
> > +* audio functions are in D3 state.
> > +*   - pull ASIC out of BACO state when either video or
> > +* audio function is in D0 state.
> > +* Also, at startup, PMFW assumes both functions are in
> > +* D0 state.
> > +*
> > +* So if snd driver was loaded prior to amdgpu driver
> > +* and audio function was put into D3 state behind PMFW's
> > +* back, the BACO may not correctly kicks in and out.
> > +*
> > +* Via amdgpu_get_audio_func() below, the audio function
> > +* is guarded to be in D0 correctly.
> > +*/
> 
> On a second look at the comments - should runpm _get on audio dev be
> done before doing device_init (so that it's in D0 while FW is getting
> loaded) and put done here?
[Quan, Evan] It does not matter as long as all those are performed before  
.runtime_suspend() kicks.
The issue around here is : if the audio dev is already in D3 state before PMFW 
alive, during .runtime_suspend there will be no Dstate transfer(D0->D3). Thus 
no interrupt will go to PMFW and PMFW will be not aware of the audio dev D3 
state. With the proper audio dev D3 state, the baco state will never kick in.
Via the amdgpu_get_audio_func(), the audio dev is put into D0 state. Then on 
the succeeding .runtime_suspend(), there will be Dstate transfer(D0->D3) and 
thus interrupt for PMFW.

BR
Evan
> 
> Thanks,
> Lijo
> 
> > +   if (amdgpu_device_supports_baco(dev) &&
> > +   !(adev->flags & AMD_IS_APU) &&
> > +   (adev->asic_type >= CHIP_NAVI10))
> > +   amdgpu_get_audio_func(adev);
> > }
> >
> > if (amdgpu_acpi_smart_shift_update(dev,
> AMDGPU_SS_DRV_LOAD))
> >
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[PATCH] drm/amd/amdgpu embed hw_fence into amdgpu_job

[Jack Zhang]

Why: Previously hw fence is alloced separately with job.
It caused historical lifetime issues and corner cases.
The ideal situation is to take fence to manage both job
and fence's lifetime, and simplify the design of gpu-scheduler.

How:
We propose to embed hw_fence into amdgpu_job.
1. We cover the normal job submission by this method.
2. For ib_test, and submit without a parent job keep the
legacy way to create a hw fence separately.

Signed-off-by: Jack Zhang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c  |  1 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c   | 64 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c  |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 35 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_job.h |  4 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h|  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c  |  2 +-
 8 files changed, 82 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index d2812182fd3d..2515b811d626 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -639,7 +639,6 @@ int amdgpu_amdkfd_submit_ib(struct kgd_dev *kgd, enum 
kgd_engine_type engine,
ret = dma_fence_wait(f, false);
 
 err_ib_sched:
-   dma_fence_put(f);
amdgpu_job_free(job);
 err:
return ret;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index 7b98a4771872..f2c1f32f40ea 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -1444,7 +1444,7 @@ static void amdgpu_ib_preempt_mark_partial_job(struct 
amdgpu_ring *ring)
continue;
}
job = to_amdgpu_job(s_job);
-   if (preempted && job->fence == fence)
+   if (preempted && (&job->hw_fence) == fence)
/* mark the job as preempted */
job->preemption_status |= AMDGPU_IB_PREEMPTED;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
index 4a3e3329d621..1c0562b888bd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
@@ -133,25 +133,40 @@ static u32 amdgpu_fence_read(struct amdgpu_ring *ring)
  * Emits a fence command on the requested ring (all asics).
  * Returns 0 on success, -ENOMEM on failure.
  */
-int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **f,
+int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **f, struct 
amdgpu_job *job,
  unsigned flags)
 {
struct amdgpu_device *adev = ring->adev;
-   struct amdgpu_fence *fence;
+   struct dma_fence *fence;
+   struct amdgpu_fence *am_fence;
struct dma_fence __rcu **ptr;
uint32_t seq;
int r;
 
-   fence = kmem_cache_alloc(amdgpu_fence_slab, GFP_KERNEL);
-   if (fence == NULL)
-   return -ENOMEM;
+   if (job == NULL) {
+   /* create a sperate hw fence */
+   am_fence = kmem_cache_alloc(amdgpu_fence_slab, GFP_KERNEL);
+   if (am_fence == NULL)
+   return -ENOMEM;
+   fence = &am_fence->base;
+   am_fence->ring = ring;
+   } else {
+   /* take use of job-embedded fence */
+   fence = &job->hw_fence;
+   job->ring = ring;
+   }
 
seq = ++ring->fence_drv.sync_seq;
-   fence->ring = ring;
-   dma_fence_init(&fence->base, &amdgpu_fence_ops,
+   dma_fence_init(fence, &amdgpu_fence_ops,
   &ring->fence_drv.lock,
   adev->fence_context + ring->idx,
   seq);
+
+   if (job != NULL) {
+   /* mark this fence has a parent job */
+   fence->flags |= 0x1000;
+   }
+
amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
   seq, flags | AMDGPU_FENCE_FLAG_INT);
pm_runtime_get_noresume(adev_to_drm(adev)->dev);
@@ -174,9 +189,9 @@ int amdgpu_fence_emit(struct amdgpu_ring *ring, struct 
dma_fence **f,
/* This function can't be called concurrently anyway, otherwise
 * emitting the fence would mess up the hardware ring buffer.
 */
-   rcu_assign_pointer(*ptr, dma_fence_get(&fence->base));
+   rcu_assign_pointer(*ptr, dma_fence_get(fence));
 
-   *f = &fence->base;
+   *f = fence;
 
return 0;
 }
@@ -648,8 +663,18 @@ static const char *amdgpu_fence_get_driver_name(struct 
dma_fence *fence)
 
 static const char *amdgpu_fence_get_timeline_name(struct dma_fence *f)
 {
-   struct amdgpu_fence *fence = to_amdgpu_fence(f);
-   return (const char *)fence->ring->name;
+   struct amdgpu_ring *ring;
+
+   if (f->flags & 0

RE: [PATCH V2 4/5] drm/amd/pm: clear the cached dpm feature status

[Quan, Evan]

[AMD Official Use Only]

Hi Lijo,

I got your concern. However, the problem is what amdgpu_smu.c can see is 
SMU_FEATURE_x_BIT(e.g. SMU_FEATURE_BACO_BIT) related.
While the bit mask stored in feature->enabled is FEATURE_x_BIT(e.g. 
FEATURE_BACO_BIT which is asic specific) related.
So, a SMU_FEATURE_BACO_BIT to FEATURE_BACO_BIT transfer is needed and for now 
this asic specific operation is performed in 
smu_cmn.c(smu_cmn_to_asic_specific_index).

The possible way to get this optimized I can see is either
1. try to fit this into smu_cmn_disable_all_features_with_exception()
2. make the bitmasks stored in feature->enabled are non asic specific ones. 
This will involve extra efforts and risks.
I personally prefer the approach 1 above.

Any thoughts?

BR
Evan
> -Original Message-
> From: Lazar, Lijo 
> Sent: Friday, June 4, 2021 7:56 PM
> To: Quan, Evan ; amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander 
> Subject: Re: [PATCH V2 4/5] drm/amd/pm: clear the cached dpm feature
> status
> 
> 
> 
> On 6/4/2021 3:28 PM, Evan Quan wrote:
> > For some ASICs, the real dpm feature disablement job is handled by
> > PMFW during baco reset and custom pptable loading. Cached dpm feature
> > status need to be cleared to pair that.
> >
> > Change-Id: I9e37d80e13599833301c04711b097fb37c2e41f9
> > Signed-off-by: Evan Quan 
> > ---
> > V1->V2:
> >- correct the setting for baco bit(pointed out by Lijo)
> > ---
> >   drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h   |  6 +
> >   drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 19 -
> -
> >   .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c   |  1 +
> >   .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c   |  1 +
> >   drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c| 25
> +++
> >   drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h|  3 +++
> >   drivers/gpu/drm/amd/pm/swsmu/smu_internal.h   |  1 +
> >   7 files changed, 54 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
> > b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
> > index fb7438224872..3f9b2a839a37 100644
> > --- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
> > +++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
> > @@ -937,6 +937,12 @@ struct pptable_funcs {
> >  */
> > int (*disable_all_features_with_exception)(struct smu_context
> *smu,
> > enum smu_feature_mask mask);
> >
> > +   /**
> > +* @clear_cached_dpm_feature_status_with_exception: Clear
> cached dpm feature status with
> > +*  exception to those 
> > in &mask.
> > +*/
> > +   int (*clear_cached_dpm_feature_status_with_exception)(struct
> > +smu_context *smu, enum smu_feature_mask mask);
> > +
> 
> Since this is a just a utility function which clears sw bitmask without 
> touching
> hardware, do we need a ppt_func? In case that is needed, we already have
> this - smu_cmn_disable_all_features_with_exception. So, can't this remain
> as a standalone smu_cmn function which can be called from anywhere?
> Nowadays, I get a red alert when a ppt_func gets added :)
> 
> Thanks,
> Lijo
> 
> > /**
> >  * @notify_display_change: Enable fast memory clock switching.
> >  *
> > diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> > b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> > index c9a31556e077..aba475d06507 100644
> > --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> > +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> > @@ -1352,6 +1352,16 @@ static int smu_hw_init(void *handle)
> > return 0;
> >   }
> >
> > +static void smu_reset_cached_dpm_feature_status(struct smu_context
> > +*smu) {
> > +   struct smu_feature *feature = &smu->smu_feature;
> > +
> > +   mutex_lock(&feature->mutex);
> > +   bitmap_zero(feature->enabled, feature->feature_num);
> > +   bitmap_zero(feature->supported, feature->feature_num);
> > +   mutex_unlock(&feature->mutex);
> > +}
> > +
> >   static int smu_disable_dpms(struct smu_context *smu)
> >   {
> > struct amdgpu_device *adev = smu->adev; @@ -1374,16 +1384,21
> @@
> > static int smu_disable_dpms(struct smu_context *smu)
> >  */
> > if (smu->uploading_custom_pp_table &&
> > (adev->asic_type >= CHIP_NAVI10) &&
> > -   (adev->asic_type <= CHIP_DIMGREY_CAVEFISH))
> > +   (adev->asic_type <= CHIP_DIMGREY_CAVEFISH)) {
> > +   smu_reset_cached_dpm_feature_status(smu);
> > return 0;
> > +   }
> >
> > /*
> >  * For Sienna_Cichlid, PMFW will handle the features disablement
> properly
> >  * on BACO in. Driver involvement is unnecessary.
> >  */
> > if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
> > -use_baco)
> > +use_baco) {
> > +
>   smu_clear_cached_dpm_feature_status_with_exception(smu,
> > +
> SMU_FEATURE_BACO_BIT);
> > return 0;
> > +   }
> >
> > /*
> >  * For gpu reset, runpm and hibernation through BACO, diff --git
> > a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> > b/drivers/gpu/drm

RE: [PATCH V2 4/5] drm/amd/pm: clear the cached dpm feature status

[Lazar, Lijo]

[Public]

What about separating to smu_cmn_utils.c/smu_utils.c or similar which is meant 
for software based common/util functions?  In general, it will have sw based 
common funcs (not ASIC specific) and may be used outside (for ex: in 
amdgpu_smu.c). smu_cmn continues to have the hw based common/ppt_func routines.

smu_cmn_to_asic_specific_index is also a good candidate for such a function as 
it fetches the sw lookup map (may be moved later).

Thanks,
Lijo

-Original Message-
From: Quan, Evan  
Sent: Monday, June 7, 2021 1:04 PM
To: Lazar, Lijo ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander 
Subject: RE: [PATCH V2 4/5] drm/amd/pm: clear the cached dpm feature status

[AMD Official Use Only]

Hi Lijo,

I got your concern. However, the problem is what amdgpu_smu.c can see is 
SMU_FEATURE_x_BIT(e.g. SMU_FEATURE_BACO_BIT) related.
While the bit mask stored in feature->enabled is FEATURE_x_BIT(e.g. 
FEATURE_BACO_BIT which is asic specific) related.
So, a SMU_FEATURE_BACO_BIT to FEATURE_BACO_BIT transfer is needed and for now 
this asic specific operation is performed in 
smu_cmn.c(smu_cmn_to_asic_specific_index).

The possible way to get this optimized I can see is either 1. try to fit this 
into smu_cmn_disable_all_features_with_exception()
2. make the bitmasks stored in feature->enabled are non asic specific ones. 
This will involve extra efforts and risks.
I personally prefer the approach 1 above.

Any thoughts?

BR
Evan
> -Original Message-
> From: Lazar, Lijo 
> Sent: Friday, June 4, 2021 7:56 PM
> To: Quan, Evan ; amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander 
> Subject: Re: [PATCH V2 4/5] drm/amd/pm: clear the cached dpm feature 
> status
> 
> 
> 
> On 6/4/2021 3:28 PM, Evan Quan wrote:
> > For some ASICs, the real dpm feature disablement job is handled by 
> > PMFW during baco reset and custom pptable loading. Cached dpm 
> > feature status need to be cleared to pair that.
> >
> > Change-Id: I9e37d80e13599833301c04711b097fb37c2e41f9
> > Signed-off-by: Evan Quan 
> > ---
> > V1->V2:
> >- correct the setting for baco bit(pointed out by Lijo)
> > ---
> >   drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h   |  6 +
> >   drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 19 -
> -
> >   .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c   |  1 +
> >   .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c   |  1 +
> >   drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c| 25
> +++
> >   drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h|  3 +++
> >   drivers/gpu/drm/amd/pm/swsmu/smu_internal.h   |  1 +
> >   7 files changed, 54 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
> > b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
> > index fb7438224872..3f9b2a839a37 100644
> > --- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
> > +++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
> > @@ -937,6 +937,12 @@ struct pptable_funcs {
> >  */
> > int (*disable_all_features_with_exception)(struct smu_context
> *smu,
> > enum smu_feature_mask mask);
> >
> > +   /**
> > +* @clear_cached_dpm_feature_status_with_exception: Clear
> cached dpm feature status with
> > +*  exception to those 
> > in &mask.
> > +*/
> > +   int (*clear_cached_dpm_feature_status_with_exception)(struct
> > +smu_context *smu, enum smu_feature_mask mask);
> > +
> 
> Since this is a just a utility function which clears sw bitmask 
> without touching hardware, do we need a ppt_func? In case that is 
> needed, we already have this - 
> smu_cmn_disable_all_features_with_exception. So, can't this remain as a 
> standalone smu_cmn function which can be called from anywhere?
> Nowadays, I get a red alert when a ppt_func gets added :)
> 
> Thanks,
> Lijo
> 
> > /**
> >  * @notify_display_change: Enable fast memory clock switching.
> >  *
> > diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> > b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> > index c9a31556e077..aba475d06507 100644
> > --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> > +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> > @@ -1352,6 +1352,16 @@ static int smu_hw_init(void *handle)
> > return 0;
> >   }
> >
> > +static void smu_reset_cached_dpm_feature_status(struct smu_context
> > +*smu) {
> > +   struct smu_feature *feature = &smu->smu_feature;
> > +
> > +   mutex_lock(&feature->mutex);
> > +   bitmap_zero(feature->enabled, feature->feature_num);
> > +   bitmap_zero(feature->supported, feature->feature_num);
> > +   mutex_unlock(&feature->mutex);
> > +}
> > +
> >   static int smu_disable_dpms(struct smu_context *smu)
> >   {
> > struct amdgpu_device *adev = smu->adev; @@ -1374,16 +1384,21
> @@
> > static int smu_disable_dpms(struct smu_context *smu)
> >  */
> > if (smu->uploading_custom_pp_table &&
> > (adev->asic_type >= CHIP_NAVI10) &&
> > -   (adev->asic_type <= CHIP_DIMGREY_CAVEFISH))
> > +   (adev->asic

RE: [PATCH 2/2] drm/amd/amdgpu: add instance_number check in amdgpu_discovery_get_ip_version

[Zhou, Peng Ju]

[AMD Official Use Only]

Hi Alex
The following patch series were ported from amd-staging-dkms to fix VCN IB test 
fail.
Can you help to review it?

[PATCH 1/2] drm/amd/amdgpu: Use IP discovery data to determine VCN enablement 
instead of MMSCH
[PATCH 2/2] drm/amd/amdgpu: add instance_number check in 
amdgpu_discovery_get_ip_version


-- 
BW
Pengju Zhou

 

> -Original Message-
> From: Peng Ju Zhou 
> Sent: Thursday, June 3, 2021 6:42 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhou, Peng Ju ; Zhang, Bokun
> 
> Subject: [PATCH 2/2] drm/amd/amdgpu: add instance_number check in
> amdgpu_discovery_get_ip_version
> 
> The original code returns IP version of instantce_0 for every IP. This
> implementation may be correct for most of IPs.
> 
> However, for certain IP block (VCN for example), it may have 2 instances and
> both of them have the same hw_id, BUT they have different revision number
> (0 and 1).
> 
> In this case, the original amdgpu_discovery_get_ip_version cannot correct
> reflects the result and returns false information
> 
> Signed-off-by: Bokun Zhang 
> Signed-off-by: Peng Ju Zhou 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h | 2 +-
>  2 files changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> index 99255c2f08f4..f949ed8bfd9e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> @@ -325,7 +325,7 @@ int amdgpu_discovery_reg_base_init(struct
> amdgpu_device *adev)
>   return 0;
>  }
> 
> -int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id,
> +int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int
> +hw_id, int number_instance,
>   int *major, int *minor, int *revision)  {
>   struct binary_header *bhdr;
> @@ -357,7 +357,7 @@ int amdgpu_discovery_get_ip_version(struct
> amdgpu_device *adev, int hw_id,
>   for (j = 0; j < num_ips; j++) {
>   ip = (struct ip *)(adev->mman.discovery_bin +
> ip_offset);
> 
> - if (le16_to_cpu(ip->hw_id) == hw_id) {
> + if ((le16_to_cpu(ip->hw_id) == hw_id) && (ip-
> >number_instance ==
> +number_instance)) {
>   if (major)
>   *major = ip->major;
>   if (minor)
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h
> index 1b1ae21b1037..02e340cd3a38 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h
> @@ -30,7 +30,7 @@
>  void amdgpu_discovery_fini(struct amdgpu_device *adev);  int
> amdgpu_discovery_reg_base_init(struct amdgpu_device *adev);  void
> amdgpu_discovery_harvest_ip(struct amdgpu_device *adev); -int
> amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id,
> +int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int
> +hw_id, int number_instance,
>  int *major, int *minor, int *revision);  
> int
> amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev);
> 
> --
> 2.17.1
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RE: [PATCH V2 3/5] drm/amdgpu: correct the audio function initial Dstate

[Lazar, Lijo]

[Public]

Thanks, that explains.  

You may modify the comment to something like " amdgpu_get_audio_func() makes a 
PMFW-aware D-state transition to update audio dev's D-state in PMFW" (now it 
gives the impression that function makes audio dev to stay in D0 state).

> > +* Via amdgpu_get_audio_func() below, the audio function
> > +* is guarded to be in D0 correctly.

Thanks,
Lijo

-Original Message-
From: Quan, Evan  
Sent: Monday, June 7, 2021 12:40 PM
To: Lazar, Lijo ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander 
Subject: RE: [PATCH V2 3/5] drm/amdgpu: correct the audio function initial 
Dstate

[AMD Official Use Only]



> -Original Message-
> From: Lazar, Lijo 
> Sent: Friday, June 4, 2021 8:24 PM
> To: Quan, Evan ; amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander 
> Subject: Re: [PATCH V2 3/5] drm/amdgpu: correct the audio function 
> initial Dstate
> 
> 
> 
> On 6/4/2021 3:28 PM, Evan Quan wrote:
> > On driver loading, the ASIC is in D0 state. The bundled audio 
> > function should be in the same state also.
> >
> > Change-Id: I136e196be7633e95883a7f6c33963f7583e9bad1
> > Signed-off-by: Evan Quan 
> > ---
> > V1->V2:
> >- Lijo: include the code in a seperate API for better readability
> >- limit the change for Navi10 and later dGPUs
> >- comments more about the background
> > ---
> >   drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 40
> +
> >   1 file changed, 40 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> > index c354ffa62483..e9f2161738d1 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> > @@ -123,6 +123,22 @@ void amdgpu_register_gpu_instance(struct
> amdgpu_device *adev)
> > mutex_unlock(&mgpu_info.mutex);
> >   }
> >
> > +static void amdgpu_get_audio_func(struct amdgpu_device *adev) {
> > +   struct pci_dev *p = NULL;
> > +
> > +   p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev-
> >bus),
> > +   adev->pdev->bus->number, 1);
> > +   if (p) {
> > +   pm_runtime_get_sync(&p->dev);
> > +
> > +   pm_runtime_mark_last_busy(&p->dev);
> > +   pm_runtime_put_autosuspend(&p->dev);
> > +
> > +   pci_dev_put(p);
> > +   }
> > +}
> > +
> >   /**
> >* amdgpu_driver_load_kms - Main load function for KMS.
> >*
> > @@ -212,9 +228,33 @@ int amdgpu_driver_load_kms(struct
> amdgpu_device *adev, unsigned long flags)
> >
>   DPM_FLAG_MAY_SKIP_RESUME);
> > pm_runtime_use_autosuspend(dev->dev);
> > pm_runtime_set_autosuspend_delay(dev->dev, 5000);
> > +
> > pm_runtime_allow(dev->dev);
> > +
> > pm_runtime_mark_last_busy(dev->dev);
> > pm_runtime_put_autosuspend(dev->dev);
> > +
> > +   /*
> > +* For runpm implemented via BACO, PMFW will handle the
> > +* timing for BACO in and out:
> > +*   - put ASIC into BACO state only when both video and
> > +* audio functions are in D3 state.
> > +*   - pull ASIC out of BACO state when either video or
> > +* audio function is in D0 state.
> > +* Also, at startup, PMFW assumes both functions are in
> > +* D0 state.
> > +*
> > +* So if snd driver was loaded prior to amdgpu driver
> > +* and audio function was put into D3 state behind PMFW's
> > +* back, the BACO may not correctly kicks in and out.
> > +*
> > +* Via amdgpu_get_audio_func() below, the audio function
> > +* is guarded to be in D0 correctly.
> > +*/
> 
> On a second look at the comments - should runpm _get on audio dev be 
> done before doing device_init (so that it's in D0 while FW is getting
> loaded) and put done here?
[Quan, Evan] It does not matter as long as all those are performed before  
.runtime_suspend() kicks.
The issue around here is : if the audio dev is already in D3 state before PMFW 
alive, during .runtime_suspend there will be no Dstate transfer(D0->D3). Thus 
no interrupt will go to PMFW and PMFW will be not aware of the audio dev D3 
state. With the proper audio dev D3 state, the baco state will never kick in.
Via the amdgpu_get_audio_func(), the audio dev is put into D0 state. Then on 
the succeeding .runtime_suspend(), there will be Dstate transfer(D0->D3) and 
thus interrupt for PMFW.

BR
Evan
> 
> Thanks,
> Lijo
> 
> > +   if (amdgpu_device_supports_baco(dev) &&
> > +   !(adev->flags & AMD_IS_APU) &&
> > +   (adev->asic_type >= CHIP_NAVI10))
> > +   amdgpu_get_audio_func(adev);
> > }
> >
> > if (amdgpu_acpi_smart_shift_update(dev,
> AMDGPU_SS_DRV_LOAD))
> >
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RE: [PATCH V2 3/5] drm/amdgpu: correct the audio function initial Dstate

[Quan, Evan]

[Public]



> -Original Message-
> From: Lazar, Lijo 
> Sent: Monday, June 7, 2021 4:19 PM
> To: Quan, Evan ; amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander 
> Subject: RE: [PATCH V2 3/5] drm/amdgpu: correct the audio function initial
> Dstate
> 
> [Public]
> 
> Thanks, that explains.
> 
> You may modify the comment to something like " amdgpu_get_audio_func()
> makes a PMFW-aware D-state transition to update audio dev's D-state in
> PMFW" (now it gives the impression that function makes audio dev to stay in
> D0 state).
[Quan, Evan] Sure. 
Thanks,
Evan
> 
> > > +  * Via amdgpu_get_audio_func() below, the audio function
> > > +  * is guarded to be in D0 correctly.
> 
> Thanks,
> Lijo
> 
> -Original Message-
> From: Quan, Evan 
> Sent: Monday, June 7, 2021 12:40 PM
> To: Lazar, Lijo ; amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander 
> Subject: RE: [PATCH V2 3/5] drm/amdgpu: correct the audio function initial
> Dstate
> 
> [AMD Official Use Only]
> 
> 
> 
> > -Original Message-
> > From: Lazar, Lijo 
> > Sent: Friday, June 4, 2021 8:24 PM
> > To: Quan, Evan ; amd-gfx@lists.freedesktop.org
> > Cc: Deucher, Alexander 
> > Subject: Re: [PATCH V2 3/5] drm/amdgpu: correct the audio function
> > initial Dstate
> >
> >
> >
> > On 6/4/2021 3:28 PM, Evan Quan wrote:
> > > On driver loading, the ASIC is in D0 state. The bundled audio
> > > function should be in the same state also.
> > >
> > > Change-Id: I136e196be7633e95883a7f6c33963f7583e9bad1
> > > Signed-off-by: Evan Quan 
> > > ---
> > > V1->V2:
> > >- Lijo: include the code in a seperate API for better readability
> > >- limit the change for Navi10 and later dGPUs
> > >- comments more about the background
> > > ---
> > >   drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 40
> > +
> > >   1 file changed, 40 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> > > b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> > > index c354ffa62483..e9f2161738d1 100644
> > > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> > > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> > > @@ -123,6 +123,22 @@ void amdgpu_register_gpu_instance(struct
> > amdgpu_device *adev)
> > >   mutex_unlock(&mgpu_info.mutex);
> > >   }
> > >
> > > +static void amdgpu_get_audio_func(struct amdgpu_device *adev) {
> > > + struct pci_dev *p = NULL;
> > > +
> > > + p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev-
> > >bus),
> > > + adev->pdev->bus->number, 1);
> > > + if (p) {
> > > + pm_runtime_get_sync(&p->dev);
> > > +
> > > + pm_runtime_mark_last_busy(&p->dev);
> > > + pm_runtime_put_autosuspend(&p->dev);
> > > +
> > > + pci_dev_put(p);
> > > + }
> > > +}
> > > +
> > >   /**
> > >* amdgpu_driver_load_kms - Main load function for KMS.
> > >*
> > > @@ -212,9 +228,33 @@ int amdgpu_driver_load_kms(struct
> > amdgpu_device *adev, unsigned long flags)
> > >
> > DPM_FLAG_MAY_SKIP_RESUME);
> > >   pm_runtime_use_autosuspend(dev->dev);
> > >   pm_runtime_set_autosuspend_delay(dev->dev, 5000);
> > > +
> > >   pm_runtime_allow(dev->dev);
> > > +
> > >   pm_runtime_mark_last_busy(dev->dev);
> > >   pm_runtime_put_autosuspend(dev->dev);
> > > +
> > > + /*
> > > +  * For runpm implemented via BACO, PMFW will handle the
> > > +  * timing for BACO in and out:
> > > +  *   - put ASIC into BACO state only when both video and
> > > +  * audio functions are in D3 state.
> > > +  *   - pull ASIC out of BACO state when either video or
> > > +  * audio function is in D0 state.
> > > +  * Also, at startup, PMFW assumes both functions are in
> > > +  * D0 state.
> > > +  *
> > > +  * So if snd driver was loaded prior to amdgpu driver
> > > +  * and audio function was put into D3 state behind PMFW's
> > > +  * back, the BACO may not correctly kicks in and out.
> > > +  *
> > > +  * Via amdgpu_get_audio_func() below, the audio function
> > > +  * is guarded to be in D0 correctly.
> > > +  */
> >
> > On a second look at the comments - should runpm _get on audio dev be
> > done before doing device_init (so that it's in D0 while FW is getting
> > loaded) and put done here?
> [Quan, Evan] It does not matter as long as all those are performed
> before  .runtime_suspend() kicks.
> The issue around here is : if the audio dev is already in D3 state before PMFW
> alive, during .runtime_suspend there will be no Dstate transfer(D0->D3).
> Thus no interrupt will go to PMFW and PMFW will be not aware of the audio
> dev D3 state. With the proper audio dev D3 state, the baco state will never
> kick in.
> Via the amdgpu_get_audio_func(), the audio dev is put into D0 state. Then
> on the succeeding .runtime_suspend(), there will be Dstate transfer

RE: [PATCH] drm/amdgpu: Fixing "Indirect register access for Navi12 sriov" for vega10

[Deng, Emily]

[AMD Official Use Only]

Reviewed-by: Emily Deng 

>-Original Message-
>From: amd-gfx  On Behalf Of Peng Ju
>Zhou
>Sent: Monday, June 7, 2021 1:55 PM
>To: amd-gfx@lists.freedesktop.org
>Subject: [PATCH] drm/amdgpu: Fixing "Indirect register access for Navi12 sriov"
>for vega10
>
>The NV12 and VEGA10 share the same interface W/RREG32_SOC15*, the
>callback functions in these macros may not be defined, so NULL pointer must be
>checked but not in macro __WREG32_SOC15_RLC__, fixing the lock of NULL
>pointer check.
>
>Signed-off-by: Peng Ju Zhou 
>---
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 ++-
> drivers/gpu/drm/amd/amdgpu/soc15_common.h | 4 ++--
> 2 files changed, 4 insertions(+), 3 deletions(-)
>
>diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>index fe5908f708cc..044076ec1d03 100644
>--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>@@ -790,7 +790,8 @@ static void gfx_v9_0_rlcg_w(struct amdgpu_device
>*adev, u32 offset, u32 v, u32 f  static void gfx_v9_0_rlcg_wreg(struct
>amdgpu_device *adev, u32 offset,
>  u32 v, u32 acc_flags, u32 hwip)  {
>-  if (amdgpu_sriov_fullaccess(adev)) {
>+  if ((acc_flags & AMDGPU_REGS_RLC) &&
>+  amdgpu_sriov_fullaccess(adev)) {
>   gfx_v9_0_rlcg_w(adev, offset, v, acc_flags);
>
>   return;
>diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h
>b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
>index f6cf70e69cce..0eeb5e073be8 100644
>--- a/drivers/gpu/drm/amd/amdgpu/soc15_common.h
>+++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
>@@ -28,12 +28,12 @@
> #define SOC15_REG_OFFSET(ip, inst, reg)   (adev-
>>reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
>
> #define __WREG32_SOC15_RLC__(reg, value, flag, hwip) \
>-  ((amdgpu_sriov_runtime(adev) && adev->gfx.rlc.funcs->rlcg_wreg) ? \
>+  ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs &&
>+adev->gfx.rlc.funcs->rlcg_wreg) ? \
>adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, value, flag, hwip) : \
>WREG32(reg, value))
>
> #define __RREG32_SOC15_RLC__(reg, flag, hwip) \
>-  ((amdgpu_sriov_runtime(adev) && adev->gfx.rlc.funcs->rlcg_rreg) ? \
>+  ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs &&
>+adev->gfx.rlc.funcs->rlcg_rreg) ? \
>adev->gfx.rlc.funcs->rlcg_rreg(adev, reg, flag, hwip) : \
>RREG32(reg))
>
>--
>2.17.1
>
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Re: [PATCH] drm/amdgpu: fix VM handling for GART allocations

[Das, Nirmoy]

Reviewed-by: Nirmoy Das 

On 6/5/2021 4:51 PM, Christian König wrote:

For GTT allocations with a GART address the res contains the VMID0
addresses and can't be used for VM handling.

So ignore the res when the pages array is given or we fill the page
tables with nonsense.

Signed-off-by: Christian König 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index c29fad97b63a..433642b3e498 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1705,8 +1705,8 @@ int amdgpu_vm_bo_update_mapping(struct amdgpu_device 
*adev,
if (r)
goto error_unlock;
  
-	amdgpu_res_first(res, offset, (last - start + 1) * AMDGPU_GPU_PAGE_SIZE,

-&cursor);
+   amdgpu_res_first(pages_addr ? NULL : res, offset,
+(last - start + 1) * AMDGPU_GPU_PAGE_SIZE, &cursor);
while (cursor.remaining) {
uint64_t tmp, num_entries, addr;
  

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[PATCH][next] drm/amd/display: Fix two spelling mistakes, clean wide lines

[Colin King]

From: Colin Ian King 

There are two spelling mistakes in dml_print messages, fix these and
clear up checkpatch warning on overly wide line length.

Signed-off-by: Colin Ian King 
---
 .../drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c | 10 ++
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
index c725160a095b..d655655baaba 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
@@ -1494,10 +1494,11 @@ static bool CalculatePrefetchSchedule(
dml_print(
"DML:  Tsw: %fus = time to fetch enough pixel 
data and cursor data to feed the scalers init position and detile\n",
(double) LinesToRequestPrefetchPixelData * 
LineTime);
-   dml_print("DML: To: %fus - time for propogation from scaler to 
optc\n", (*DSTYAfterScaler + ((double) (*DSTXAfterScaler) / (double) 
myPipe->HTotal)) * LineTime);
+   dml_print("DML: To: %fus - time for propagation from scaler to 
optc\n",
+ (*DSTYAfterScaler + ((double) (*DSTXAfterScaler) /
+ (double) myPipe->HTotal)) * LineTime);
dml_print("DML: Tvstartup - TSetup - Tcalc - Twait - Tpre - To 
> 0\n");
-   dml_print(
-   "DML: Tslack(pre): %fus - time left over in 
schedule\n",
+   dml_print("DML: Tslack(pre): %fus - time left over in 
schedule\n",
VStartup * LineTime - TimeForFetchingMetaPTE - 
2 * TimeForFetchingRowInVBlank
- (*DSTYAfterScaler + ((double) 
(*DSTXAfterScaler) / (double) myPipe->HTotal)) * LineTime - TWait - TCalc - 
*TSetup);
dml_print("DML: row_bytes = dpte_row_bytes (per_pipe) = 
PixelPTEBytesPerRow = : %d\n", PixelPTEBytesPerRow);
@@ -3023,7 +3024,8 @@ static void 
DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
if (v->ImmediateFlipSupportedForPipe[k] == 
false) {
 #ifdef __DML_VBA_DEBUG__
-   dml_print("DML::%s: Pipe %0d not 
supporing iflip\n", __func__, k);
+   dml_print("DML::%s: Pipe %0d not 
supporting iflip\n",
+ __func__, k);
 #endif
v->ImmediateFlipSupported = false;
}
-- 
2.31.1

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[PATCH] drm/amd/display: Fix duplicate included dce110_hw_sequencer.h

[Jiapeng Chong]

Clean up the following includecheck warning:

./drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c:
dce110_hw_sequencer.h is included more than once.

No functional change.

Reported-by: Abaci Robot 
Signed-off-by: Jiapeng Chong 
---
 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index e731987..04d02ce 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -32,7 +32,6 @@
 #include "core_status.h"
 #include "resource.h"
 #include "dm_helpers.h"
-#include "dce110_hw_sequencer.h"
 #include "dce110_timing_generator.h"
 #include "dce/dce_hwseq.h"
 #include "gpio_service_interface.h"
-- 
1.8.3.1

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Re: New uAPI for color management proposal and feedback request

[Maxime Ripard]

Hi,

On Wed, May 12, 2021 at 02:06:56PM +0200, Werner Sembach wrote:
> Hello,
> 
> In addition to the existing "max bpc", and "Broadcast RGB/output_csc"
> drm properties I propose 4 new properties: "preferred pixel encoding",
> "active color depth", "active color range", and "active pixel
> encoding"
> 
> 
> Motivation:
> 
> Current monitors have a variety pixel encodings available: RGB, YCbCr
> 4:4:4, YCbCr 4:2:2, YCbCr 4:2:0.
> 
> In addition they might be full or limited RGB range and the monitors
> accept different bit depths.
> 
> Currently the kernel driver for AMD and Intel GPUs automatically
> configure the color settings automatically with little to no influence
> of the user. However there are several real world scenarios where the
> user might disagree with the default chosen by the drivers and wants
> to set his or her own preference.
> 
> Some examples:
> 
> 1. While RGB and YCbCr 4:4:4 in theory carry the same amount of color
> information, some screens might look better on one than the other
> because of bad internal conversion. The driver currently however has a
> fixed default that is chosen if available (RGB for Intel and YCbCr
> 4:4:4 for AMD). The only way to change this currently is by editing
> and overloading the edid reported by the monitor to the kernel.
> 
> 2. RGB and YCbCr 4:4:4 need a higher port clock then YCbCr 4:2:0. Some
> hardware might report that it supports the higher port clock, but
> because of bad shielding on the PC, the cable, or the monitor the
> screen cuts out every few seconds when RGB or YCbCr 4:4:4 encoding is
> used, while YCbCr 4:2:0 might just work fine without changing
> hardware. The drivers currently however always default to the "best
> available" option even if it might be broken.
> 
> 3. Some screens natively only supporting 8-bit color, simulate 10-Bit
> color by rapidly switching between 2 adjacent colors. They advertise
> themselves to the kernel as 10-bit monitors but the user might not
> like the "fake" 10-bit effect and prefer running at the native 8-bit
> per color.
> 
> 4. Some screens are falsely classified as full RGB range wile they
> actually use limited RGB range. This results in washed out colors in
> dark and bright scenes. A user override can be helpful to manually fix
> this issue when it occurs.
> 
> There already exist several requests, discussion, and patches
> regarding the thematic:
> 
> - https://gitlab.freedesktop.org/drm/amd/-/issues/476
> 
> - https://gitlab.freedesktop.org/drm/amd/-/issues/1548
> 
> - https://lkml.org/lkml/2021/5/7/695
> 
> - https://lkml.org/lkml/2021/5/11/416
> 
> 
> Current State:
> 
> I only know bits about the Intel i915 and AMD amdgpu driver. I don't
> know how other driver handle color management
> 
> - "max bpc", global setting applied by both i915 (only on dp i think?)
> and amdgpu. Default value is "8". For every resolution + frequency
> combination the highest possible even number between 6 and max_bpc is
> chosen. If the range doesn't contain a valid mode the resolution +
> frequency combination is discarded (but I guess that would be a very
> special edge case, if existent at all, when 6 doesn't work but 10
> would work). Intel HDMI code always checks 8, 12, and 10 and does not
> check the max_bpc setting.
> 
> - "Broadcast RGB" for i915 and "output_csc" for the old radeon driver
> (not amdgpu), overwrites the kernel chosen color range setting (full
> or limited). If I recall correctly Intel HDMI code defaults to full
> unless this property is set, Intel dp code tries to probe the monitor
> to find out what to use. amdgpu has no corresponding setting (I don't
> know how it's decided there).
> 
> - RGB pixel encoding can be forced by overloading a Monitors edid with
> one that tells the kernel that only RGB is possible. That doesn't work
> for YCbCr 4:4:4 however because of the edid specification. Forcing
> YCbCr 4:2:0 would theoretically also be possible this way. amdgpu has
> a debugfs switch "force_ycbcr_420" which makes the driver default to
> YCbCr 4:2:0 on all monitors if possible.
> 
> 
> Proposed Solution:
> 
> 1. Add a new uAPI property "preferred pixel encoding", as a per port
>setting.
> 
>     - An amdgpu specific implementation was already shared here:
>   https://gitlab.freedesktop.org/drm/amd/-/issues/476
> 
>     - It also writes back the actually used encoding if the one
>   requested was not possible, overwriting the requested value in
>   the process. I think it would be better to have this feedback
>   channel as a different, read-only property.
> 
>     - Make this solution vendor agnostic by putting it in the
>   drm_connector_state struct next do max_bpc
>   
> https://elixir.bootlin.com/linux/v5.13-rc1/source/include/drm/drm_connector.h#L654
>   and add patches to amdgpu and i915 to respect this setting
> 
> 2. Convert "Broadcast RGB" to a vendor agnostic setting/replace with a
>vendor agnostic setting.
> 
>     - Imho the name is not v

Re: [PATCH 2/4] drm/uAPI: Add "active bpc" as feedback channel for "max bpc" drm property

[Maxime Ripard]

Hi,

On Fri, Jun 04, 2021 at 07:17:21PM +0200, Werner Sembach wrote:
> Add a new general drm property "active bpc" which can be used by graphic 
> drivers
> to report the applied bit depth per pixel back to userspace.

Just a heads up, we'll need an open source project that has accepted it
before merging it.

See 
https://www.kernel.org/doc/html/latest/gpu/drm-uapi.html#open-source-userspace-requirements

> While "max bpc" can be used to change the color depth, there was no way to 
> check
> which one actually got used. While in theory the driver chooses the 
> best/highest
> color depth within the max bpc setting a user might not be fully aware what 
> his
> hardware is or isn't capable off. This is meant as a quick way to double check
> the setup.
> 
> In the future, automatic color calibration for screens might also depend on 
> this
> information available.
> 
> Signed-off-by: Werner Sembach 
> ---
>  drivers/gpu/drm/drm_atomic_uapi.c |  2 ++
>  drivers/gpu/drm/drm_connector.c   | 40 +++
>  include/drm/drm_connector.h   | 15 
>  3 files changed, 57 insertions(+)
> 
> diff --git a/drivers/gpu/drm/drm_atomic_uapi.c 
> b/drivers/gpu/drm/drm_atomic_uapi.c
> index 268bb69c2e2f..7ae4e40936b5 100644
> --- a/drivers/gpu/drm/drm_atomic_uapi.c
> +++ b/drivers/gpu/drm/drm_atomic_uapi.c
> @@ -873,6 +873,8 @@ drm_atomic_connector_get_property(struct drm_connector 
> *connector,
>   *val = 0;
>   } else if (property == connector->max_bpc_property) {
>   *val = state->max_requested_bpc;
> + } else if (property == connector->active_bpc_property) {
> + *val = state->active_bpc;
>   } else if (connector->funcs->atomic_get_property) {
>   return connector->funcs->atomic_get_property(connector,
>   state, property, val);
> diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
> index 7631f76e7f34..5f42a5be5822 100644
> --- a/drivers/gpu/drm/drm_connector.c
> +++ b/drivers/gpu/drm/drm_connector.c
> @@ -1195,6 +1195,13 @@ static const struct drm_prop_enum_list 
> dp_colorspaces[] = {
>   *   drm_connector_attach_max_bpc_property() to create and attach the
>   *   property to the connector during initialization.
>   *
> + * active bpc:
> + *   This read-only range property is used by userspace check the bit depth
> + *   actually applied by the GPU driver after evaluation all hardware

^ display

Depending on the system, the display component might have a GPU attached
or not, and the GPU might have a display component or not.

> + *   capabilities and max bpc. Drivers to use the function
> + *   drm_connector_attach_active_bpc_property() to create and attach the
> + *   property to the connector during initialization.
> + *
>   * Connectors also have one standardized atomic property:
>   *
>   * CRTC_ID:
> @@ -2150,6 +2157,39 @@ int drm_connector_attach_max_bpc_property(struct 
> drm_connector *connector,
>  }
>  EXPORT_SYMBOL(drm_connector_attach_max_bpc_property);
>  
> +/**
> + * drm_connector_attach_active_bpc_property - attach "active bpc" property
> + * @connector: connector to attach active bpc property on.
> + * @min: The minimum bit depth supported by the connector.
> + * @max: The maximum bit depth supported by the connector.
> + *
> + * This is used to check the applied bit depth on a connector.
> + *
> + * Returns:
> + * Zero on success, negative errno on failure.
> + */
> +int drm_connector_attach_active_bpc_property(struct drm_connector *connector,
> +   int min, int max)
> +{
> + struct drm_device *dev = connector->dev;
> + struct drm_property *prop;
> +
> + prop = connector->active_bpc_property;
> + if (!prop) {
> + prop = drm_property_create_range(dev, 0, "active bpc", min, 
> max);
> + if (!prop)
> + return -ENOMEM;
> +
> + connector->active_bpc_property = prop;
> + }
> +
> + drm_object_attach_property(&connector->base, prop, 0);
> + connector->state->active_bpc = 0;

I guess we want to default to 8?

Maxime


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RE: [PATCH v3 0/6] Modify smu_get_power_limit to implement Powerplay API

[Lazar, Lijo]

[Public]

Series is 
Reviewed-by: Lijo Lazar 

-Original Message-
From: Powell, Darren  
Sent: Sunday, June 6, 2021 10:30 AM
To: amd-gfx@lists.freedesktop.org
Cc: Powell, Darren 
Subject: [PATCH v3 0/6] Modify smu_get_power_limit to implement Powerplay API


=== Description ===
modify smu_get_power_limit to implement Powerplay API

 v3: renamed enum pp_power_sample_window to enum pp_power_limit
 v2: rewrote the patchset to use two enums as args to get_power

=== Test System ===
* DESKTOP(AMD FX-8350 + NAVI10(731F/ca), BIOS: F2)  + ISO(Ubuntu 20.04.1 LTS)  
+ Kernel(5.11.0-custom-fdoagd5f)

=== Patch Summary ===
   linux: (g...@gitlab.freedesktop.org:agd5f) origin/amd-staging-drm-next @ 
3ac16cf10525
+ 1a7ee0a2bc79 amdgpu/pm: reorder definition of swsmu_pm_funcs for 
readability
+ 3d0481caced7 amdgpu/pm: clean up smu_get_power_limit function signature
+ 593d896cf90c amdgpu/pm: modify Powerplay API get_power_limit to use new 
pp_power enums
+ 45339b7190fc amdgpu/pm: modify and add smu_get_power_limit to Powerplay 
API
+ 8f4be6d2a9df amdgpu/pm: handle return value for get_power_limit
+ a2e5f8ecd04f amdgpu/pm: add kernel documentation for smu_get_power_limit

=== Tests ===
 get_power_limit Test 
* Test
 AMDGPU_PCI_ADDR=`lspci -nn | grep "VGA\|Display" | cut -d " " -f 1`  
AMDGPU_HWMON=`ls -la /sys/class/hwmon | grep $AMDGPU_PCI_ADDR | cut -d " " -f 
11`  HWMON_DIR=/sys/class/hwmon/${AMDGPU_HWMON}

 lspci -nn | grep "VGA\|Display" ; \
 echo "=== power1 cap ===" ; cat $HWMON_DIR/power1_cap ;   \
 echo "=== power1 cap max ===" ; cat $HWMON_DIR/power1_cap_max ;   \
 echo "=== power1 cap def ===" ; cat $HWMON_DIR/power1_cap_default

 Documentation Test 
* Insert temp documentation
** Documentation/gpu/amdgpu.rst
 vi Documentation/gpu/amdgpu.rst
** added text to start
START
Documentation Testing
=

Power Limit
---
.. kernel-doc:: drivers/gpu/drm/amd/include/kgd_pp_interface.h
   :doc: amdgpu_pp_power

.. kernel-doc:: drivers/gpu/drm/amd/include/kgd_pp_interface.h
   :identifiers: pp_power_limit_level

.. kernel-doc:: drivers/gpu/drm/amd/include/kgd_pp_interface.h
   :identifiers: pp_power_type

.. kernel-doc:: drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
   :identifiers: smu_get_power_limit
-END-

* Setup
 cd ~/workspace/linux
 . sphinx_2.4.4/bin/activate

* Build
 export SPHINXDOCLOG=sphinx.build.log
 cp $SPHINXDOCLOG{,.old}
 time make -j 8 htmldocs |& tee $SPHINXDOCLOG

* View
 firefox 
file:///home/dapowell/workspace/linux/Documentation/output/gpu/amdgpu.html

Darren Powell (6):
  amdgpu/pm: reorder definition of swsmu_pm_funcs for readability
  amdgpu/pm: clean up smu_get_power_limit function signature
  amdgpu/pm: modify Powerplay API get_power_limit to use new pp_power
enums
  amdgpu/pm: modify and add smu_get_power_limit to Powerplay API
  amdgpu/pm: handle return value for get_power_limit
  amdgpu/pm: add kernel documentation for smu_get_power_limit

 .../gpu/drm/amd/include/kgd_pp_interface.h| 47 -
 drivers/gpu/drm/amd/pm/amdgpu_pm.c| 64 +++--
 drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h   |  5 +-
 .../gpu/drm/amd/pm/powerplay/amd_powerplay.c  | 33 ---
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 96 +--
 5 files changed, 172 insertions(+), 73 deletions(-)


base-commit: f60839821f77d6db48bfc986e0391b70b31fede8
--
2.31.1
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Re: [PATCH] drm/radeon: Always call radeon_suspend_kms() in radeon_pci_shutdown()

[Alex Deucher]

On Mon, Jun 7, 2021 at 8:30 AM Christian König  wrote:
>
> Am 07.06.21 um 14:27 schrieb Tiezhu Yang:
> > radeon_suspend_kms() puts the hw in the suspend state (all asics),
> > it should always call radeon_suspend_kms() in radeon_pci_shutdown(),
> > this is a normal cleanup process to avoid more operations on radeon,
> > just remove #ifdef CONFIG_PPC64 and the related comments.
>
> Well NAK.
>
> Alex knows more about the details but suspending should not be part of
> the pci shotdown process at all.
>
> We just add that here to enforce a GPU reset on PPC64 boards for some
> reason.

Everything in the comment still applies.

Alex

>
> Regards,
> Christian.
>
> >
> > Co-developed-by: Jianmin Lv 
> > Signed-off-by: Jianmin Lv 
> > Signed-off-by: Tiezhu Yang 
> > ---
> >   drivers/gpu/drm/radeon/radeon_drv.c | 9 -
> >   1 file changed, 9 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/radeon/radeon_drv.c 
> > b/drivers/gpu/drm/radeon/radeon_drv.c
> > index efeb115..0b1f43d 100644
> > --- a/drivers/gpu/drm/radeon/radeon_drv.c
> > +++ b/drivers/gpu/drm/radeon/radeon_drv.c
> > @@ -386,16 +386,7 @@ radeon_pci_shutdown(struct pci_dev *pdev)
> >   if (radeon_device_is_virtual())
> >   radeon_pci_remove(pdev);
> >
> > -#ifdef CONFIG_PPC64
> > - /*
> > -  * Some adapters need to be suspended before a
> > -  * shutdown occurs in order to prevent an error
> > -  * during kexec.
> > -  * Make this power specific becauase it breaks
> > -  * some non-power boards.
> > -  */
> >   radeon_suspend_kms(pci_get_drvdata(pdev), true, true, false);
> > -#endif
> >   }
> >
> >   static int radeon_pmops_suspend(struct device *dev)
>
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Re: [PATCH] drm/amdgpu: Fix warning of Function parameter or member not described

[Christian König]

Am 07.06.21 um 16:21 schrieb Eric Huang:

Add the parameter table_freed description on function description.

Signed-off-by: Eric Huang 


Reviewed-by: Christian König 


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 1 +
  1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index b4f189ab672e..9db1b64d16d9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1823,6 +1823,7 @@ void amdgpu_vm_get_memory(struct amdgpu_vm *vm, uint64_t 
*vram_mem,
   * @adev: amdgpu_device pointer
   * @bo_va: requested BO and VM object
   * @clear: if true clear the entries
+ * @table_freed: return true if page table is freed
   *
   * Fill in the page table entries for @bo_va.
   *


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Re: [PATCH] drm/amd/display: Verify Gamma & Degamma LUT sizes in amdgpu_dm_atomic_check

[Mark Yacoub]

On Fri, Jun 4, 2021 at 4:17 PM Harry Wentland  wrote:
>
>
>
> On 2021-06-04 1:01 p.m., Mark Yacoub wrote:
> > From: Mark Yacoub 
> >
> > For each CRTC state, check the size of Gamma and Degamma LUTs  so
> > unexpected and larger sizes wouldn't slip through.
> >
> > TEST: IGT:kms_color::pipe-invalid-gamma-lut-sizes
> >
> > Signed-off-by: Mark Yacoub 
> > Change-Id: I9d513a38e8ac2af1b4bf802e1feb1a4d726fba4c
> > ---
> >  .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  3 ++
> >  .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h |  1 +
> >  .../amd/display/amdgpu_dm/amdgpu_dm_color.c   | 40 ---
> >  3 files changed, 38 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
> > b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > index 38d497d30dba8..f6cd522b42a80 100644
> > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > @@ -9402,6 +9402,9 @@ static int amdgpu_dm_atomic_check(struct drm_device 
> > *dev,
> >   dm_old_crtc_state->dsc_force_changed == false)
> >   continue;
> >
> > + if ((ret = amdgpu_dm_verify_lut_sizes(new_crtc_state)))
> > + goto fail;
> > +
> >   if (!new_crtc_state->enable)
> >   continue;
> >
> > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h 
> > b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
> > index 8bfe901cf2374..1b77cd2612691 100644
> > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
> > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
> > @@ -541,6 +541,7 @@ void amdgpu_dm_trigger_timing_sync(struct drm_device 
> > *dev);
> >  #define MAX_COLOR_LEGACY_LUT_ENTRIES 256
> >
> >  void amdgpu_dm_init_color_mod(void);
> > +int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state);
> >  int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc);
> >  int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc,
> > struct dc_plane_state *dc_plane_state);
> > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c 
> > b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
> > index 157fe4efbb599..da6f9fcc0b415 100644
> > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
> > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
> > @@ -284,6 +284,37 @@ static int __set_input_tf(struct dc_transfer_func 
> > *func,
> >   return res ? 0 : -ENOMEM;
> >  }
> >
> > +/**
> > + * Verifies that the Degamma and Gamma LUTs attached to the |crtc_state| 
> > are of
> > + * the expected size.
> > + * Returns 0 on success.
> > + */
> > +int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state)
> > +{
> > + const struct drm_color_lut *lut = NULL;
> > + uint32_t size = 0;
> > +
> > + lut = __extract_blob_lut(crtc_state->degamma_lut, &size);
> > + if (lut && size != MAX_COLOR_LUT_ENTRIES) {
>
> Isn't the point of the LUT size that it can be variable? Did you observe any
> problems with LUTs that are not of size 4096?
Is it supposed to be variable?
I'm basing my knowledge of LUTs on this IGT Test:
https://gitlab.freedesktop.org/drm/igt-gpu-tools/-/blob/master/tests/kms_color_helper.c#L281
It does check for invalid sizes and for the exact size, giving me the
impression that it's not too flexible.
Is variability of size an AMD specific behavior or should it be a DRM behavior?
>
> Legacy X-based userspace will give us 256 size LUTs. We can't break support 
> for
> that. See MAX_COLOR_LEGACY_LUT_ENTRIES.
In the new function `amdgpu_dm_verify_lut_sizes`, I maintained parity
with the old behavior. In `amdgpu_dm_update_crtc_color_mgmt`, the
degamma size is only checked against `MAX_COLOR_LUT_ENTRIES` while
regamma_size size is checked against both MAX_COLOR_LUT_ENTRIES and
MAX_COLOR_LEGACY_LUT_ENTRIES:
https://gitlab.freedesktop.org/agd5f/linux/-/blob/amd-staging-drm-next/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c#L321
Also, in the definition of MAX_COLOR_LEGACY_LUT_ENTRIES, it mentions
"Legacy gamm[sic] LUT" not degamma:
https://gitlab.freedesktop.org/agd5f/linux/-/blame/amd-staging-drm-next/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h#L616
As well as the commit when it was introduced, it seems to be handling
gammas rather than degamma LUTs:
https://gitlab.freedesktop.org/agd5f/linux/-/commit/086247a4b2fba49800b27807f22bb894cd8363fb
Let me know if this would be a bug in the old behavior and I can fix
it, or if i'm missing something.
>
> Harry
>
> > + DRM_DEBUG_DRIVER(
> > + "Invalid Degamma LUT size. Should be %u but got 
> > %u.\n",
> > + MAX_COLOR_LUT_ENTRIES, size);
> > + return -EINVAL;
> > + }
> > +
> > + lut = __extract_blob_lut(crtc_state->gamma_lut, &size);
> > + if (lut && size != MAX_COLOR_LUT_ENTRIES &&
> > +   

[PATCH AUTOSEL 5.12 42/49] drm/amdgpu: refine amdgpu_fru_get_product_info

[Sasha Levin]

From: Jiansong Chen 

[ Upstream commit 5cfc912582e13b05d71fb7acc4ec69ddfa9af320 ]

1. eliminate potential array index out of bounds.
2. return meaningful value for failure.

Signed-off-by: Jiansong Chen 
Reviewed-by: Jack Gui 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 .../gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c| 42 ++-
 1 file changed, 23 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
index 8f4a8f8d8146..39b6c6bfab45 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
@@ -101,7 +101,8 @@ static int amdgpu_fru_read_eeprom(struct amdgpu_device 
*adev, uint32_t addrptr,
 int amdgpu_fru_get_product_info(struct amdgpu_device *adev)
 {
unsigned char buff[34];
-   int addrptr = 0, size = 0;
+   int addrptr, size;
+   int len;
 
if (!is_fru_eeprom_supported(adev))
return 0;
@@ -109,7 +110,7 @@ int amdgpu_fru_get_product_info(struct amdgpu_device *adev)
/* If algo exists, it means that the i2c_adapter's initialized */
if (!adev->pm.smu_i2c.algo) {
DRM_WARN("Cannot access FRU, EEPROM accessor not initialized");
-   return 0;
+   return -ENODEV;
}
 
/* There's a lot of repetition here. This is due to the FRU having
@@ -128,7 +129,7 @@ int amdgpu_fru_get_product_info(struct amdgpu_device *adev)
size = amdgpu_fru_read_eeprom(adev, addrptr, buff);
if (size < 1) {
DRM_ERROR("Failed to read FRU Manufacturer, ret:%d", size);
-   return size;
+   return -EINVAL;
}
 
/* Increment the addrptr by the size of the field, and 1 due to the
@@ -138,43 +139,45 @@ int amdgpu_fru_get_product_info(struct amdgpu_device 
*adev)
size = amdgpu_fru_read_eeprom(adev, addrptr, buff);
if (size < 1) {
DRM_ERROR("Failed to read FRU product name, ret:%d", size);
-   return size;
+   return -EINVAL;
}
 
+   len = size;
/* Product name should only be 32 characters. Any more,
 * and something could be wrong. Cap it at 32 to be safe
 */
-   if (size > 32) {
+   if (len >= sizeof(adev->product_name)) {
DRM_WARN("FRU Product Number is larger than 32 characters. This 
is likely a mistake");
-   size = 32;
+   len = sizeof(adev->product_name) - 1;
}
/* Start at 2 due to buff using fields 0 and 1 for the address */
-   memcpy(adev->product_name, &buff[2], size);
-   adev->product_name[size] = '\0';
+   memcpy(adev->product_name, &buff[2], len);
+   adev->product_name[len] = '\0';
 
addrptr += size + 1;
size = amdgpu_fru_read_eeprom(adev, addrptr, buff);
if (size < 1) {
DRM_ERROR("Failed to read FRU product number, ret:%d", size);
-   return size;
+   return -EINVAL;
}
 
+   len = size;
/* Product number should only be 16 characters. Any more,
 * and something could be wrong. Cap it at 16 to be safe
 */
-   if (size > 16) {
+   if (len >= sizeof(adev->product_number)) {
DRM_WARN("FRU Product Number is larger than 16 characters. This 
is likely a mistake");
-   size = 16;
+   len = sizeof(adev->product_number) - 1;
}
-   memcpy(adev->product_number, &buff[2], size);
-   adev->product_number[size] = '\0';
+   memcpy(adev->product_number, &buff[2], len);
+   adev->product_number[len] = '\0';
 
addrptr += size + 1;
size = amdgpu_fru_read_eeprom(adev, addrptr, buff);
 
if (size < 1) {
DRM_ERROR("Failed to read FRU product version, ret:%d", size);
-   return size;
+   return -EINVAL;
}
 
addrptr += size + 1;
@@ -182,18 +185,19 @@ int amdgpu_fru_get_product_info(struct amdgpu_device 
*adev)
 
if (size < 1) {
DRM_ERROR("Failed to read FRU serial number, ret:%d", size);
-   return size;
+   return -EINVAL;
}
 
+   len = size;
/* Serial number should only be 16 characters. Any more,
 * and something could be wrong. Cap it at 16 to be safe
 */
-   if (size > 16) {
+   if (len >= sizeof(adev->serial)) {
DRM_WARN("FRU Serial Number is larger than 16 characters. This 
is likely a mistake");
-   size = 16;
+   len = sizeof(adev->serial) - 1;
}
-   memcpy(adev->serial, &buff[2], size);
-   adev->serial[size] = '\0';
+   memcpy(adev->serial, &buff[2], len);
+   adev->serial[len] = '\0';
 
return 0;
 }
-- 
2.30.2

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[PATCH AUTOSEL 5.12 41/49] drm/amd/display: Allow bandwidth validation for 0 streams.

[Sasha Levin]

From: Bindu Ramamurthy 

[ Upstream commit ba8e59773ae59818695d1e20b8939282da80ec8c ]

[Why]
Bandwidth calculations are triggered for non zero streams, and
in case of 0 streams, these calculations were skipped with
pstate status not being updated.

[How]
As the pstate status is applicable for non zero streams, check
added for allowing 0 streams inline with dcn internal bandwidth
validations.

Signed-off-by: Bindu Ramamurthy 
Reviewed-by: Roman Li 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index bfbc23b76cd5..3e3c898848bd 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -3231,7 +3231,7 @@ static noinline bool dcn20_validate_bandwidth_fp(struct 
dc *dc,
voltage_supported = dcn20_validate_bandwidth_internal(dc, context, 
false);
dummy_pstate_supported = 
context->bw_ctx.bw.dcn.clk.p_state_change_support;
 
-   if (voltage_supported && dummy_pstate_supported) {
+   if (voltage_supported && (dummy_pstate_supported || 
!(context->stream_count))) {
context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
goto restore_dml_state;
}
-- 
2.30.2

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[PATCH AUTOSEL 5.12 43/49] drm/amd/display: Fix overlay validation by considering cursors

[Sasha Levin]

From: Rodrigo Siqueira 

[ Upstream commit 33f409e60eb0c59a4d0d06a62ab4642a988e17f7 ]

A few weeks ago, we saw a two cursor issue in a ChromeOS system. We
fixed it in the commit:

 drm/amd/display: Fix two cursor duplication when using overlay
 (read the commit message for more details)

After this change, we noticed that some IGT subtests related to
kms_plane and kms_plane_scaling started to fail. After investigating
this issue, we noticed that all subtests that fail have a primary plane
covering the overlay plane, which is currently rejected by amdgpu dm.
Fail those IGT tests highlight that our verification was too broad and
compromises the overlay usage in our drive. This patch fixes this issue
by ensuring that we only reject commits where the primary plane is not
fully covered by the overlay when the cursor hardware is enabled. With
this fix, all IGT tests start to pass again, which means our overlay
support works as expected.

Cc: Tianci.Yin 
Cc: Harry Wentland 
Cc: Nicholas Choi 
Cc: Bhawanpreet Lakha 
Cc: Nicholas Kazlauskas 
Cc: Mark Yacoub 
Cc: Daniel Wheeler 

Tested-by: Daniel Wheeler 
Signed-off-by: Rodrigo Siqueira 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 10 +-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index b63f55ea8758..69023b4b0a8b 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -9349,7 +9349,7 @@ static int validate_overlay(struct drm_atomic_state 
*state)
int i;
struct drm_plane *plane;
struct drm_plane_state *old_plane_state, *new_plane_state;
-   struct drm_plane_state *primary_state, *overlay_state = NULL;
+   struct drm_plane_state *primary_state, *cursor_state, *overlay_state = 
NULL;
 
/* Check if primary plane is contained inside overlay */
for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, 
new_plane_state, i) {
@@ -9379,6 +9379,14 @@ static int validate_overlay(struct drm_atomic_state 
*state)
if (!primary_state->crtc)
return 0;
 
+   /* check if cursor plane is enabled */
+   cursor_state = drm_atomic_get_plane_state(state, 
overlay_state->crtc->cursor);
+   if (IS_ERR(cursor_state))
+   return PTR_ERR(cursor_state);
+
+   if (drm_atomic_plane_disabling(plane->state, cursor_state))
+   return 0;
+
/* Perform the bounds check to ensure the overlay plane covers the 
primary */
if (primary_state->crtc_x < overlay_state->crtc_x ||
primary_state->crtc_y < overlay_state->crtc_y ||
-- 
2.30.2

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[PATCH AUTOSEL 5.12 44/49] drm/amd/display: Fix potential memory leak in DMUB hw_init

[Sasha Levin]

From: Roman Li 

[ Upstream commit c5699e2d863f58221044efdc3fa712dd32d55cde ]

[Why]
On resume we perform DMUB hw_init which allocates memory:
dm_resume->dm_dmub_hw_init->dc_dmub_srv_create->kzalloc
That results in memory leak in suspend/resume scenarios.

[How]
Allocate memory for the DC wrapper to DMUB only if it was not
allocated before.
No need to reallocate it on suspend/resume.

Signed-off-by: Lang Yu 
Signed-off-by: Roman Li 
Reviewed-by: Nicholas Kazlauskas 
Acked-by: Qingqing Zhuo 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 69023b4b0a8b..95d5bc2da178 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -871,7 +871,8 @@ static int dm_dmub_hw_init(struct amdgpu_device *adev)
abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
}
 
-   adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv);
+   if (!adev->dm.dc->ctx->dmub_srv)
+   adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, 
dmub_srv);
if (!adev->dm.dc->ctx->dmub_srv) {
DRM_ERROR("Couldn't allocate DC DMUB server!\n");
return -ENOMEM;
@@ -1863,7 +1864,6 @@ static int dm_suspend(void *handle)
 
amdgpu_dm_irq_suspend(adev);
 
-
dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
 
return 0;
-- 
2.30.2

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[PATCH AUTOSEL 5.12 45/49] drm/amd/amdgpu:save psp ring wptr to avoid attack

[Sasha Levin]

From: Victor Zhao 

[ Upstream commit 2370eba9f552eaae3d8aa1f70b8e9eec5c560f9e ]

[Why]
When some tools performing psp mailbox attack, the readback value
of register can be a random value which may break psp.

[How]
Use a psp wptr cache machanism to aovid the change made by attack.

v2: unify change and add detailed reason

Signed-off-by: Victor Zhao 
Signed-off-by: Jingwen Chen 
Reviewed-by: Monk Liu 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 1 +
 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c  | 3 ++-
 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c   | 3 ++-
 3 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index cb50ba445f8c..0fd62a8e68c2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -76,6 +76,7 @@ struct psp_ring
uint64_tring_mem_mc_addr;
void*ring_mem_handle;
uint32_tring_size;
+   uint32_tring_wptr;
 };
 
 /* More registers may will be supported */
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c 
b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index c325d6f53a71..d39735a89a25 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -720,7 +720,7 @@ static uint32_t psp_v11_0_ring_get_wptr(struct psp_context 
*psp)
struct amdgpu_device *adev = psp->adev;
 
if (amdgpu_sriov_vf(adev))
-   data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
+   data = psp->km_ring.ring_wptr;
else
data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
 
@@ -734,6 +734,7 @@ static void psp_v11_0_ring_set_wptr(struct psp_context 
*psp, uint32_t value)
if (amdgpu_sriov_vf(adev)) {
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value);
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, 
GFX_CTRL_CMD_ID_CONSUME_CMD);
+   psp->km_ring.ring_wptr = value;
} else
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c 
b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
index f2e725f72d2f..908664a5774b 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
@@ -379,7 +379,7 @@ static uint32_t psp_v3_1_ring_get_wptr(struct psp_context 
*psp)
struct amdgpu_device *adev = psp->adev;
 
if (amdgpu_sriov_vf(adev))
-   data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
+   data = psp->km_ring.ring_wptr;
else
data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
return data;
@@ -394,6 +394,7 @@ static void psp_v3_1_ring_set_wptr(struct psp_context *psp, 
uint32_t value)
/* send interrupt to PSP for SRIOV ring write pointer update */
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
GFX_CTRL_CMD_ID_CONSUME_CMD);
+   psp->km_ring.ring_wptr = value;
} else
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
 }
-- 
2.30.2

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[PATCH AUTOSEL 5.10 31/39] drm/amd/display: Allow bandwidth validation for 0 streams.

[Sasha Levin]

From: Bindu Ramamurthy 

[ Upstream commit ba8e59773ae59818695d1e20b8939282da80ec8c ]

[Why]
Bandwidth calculations are triggered for non zero streams, and
in case of 0 streams, these calculations were skipped with
pstate status not being updated.

[How]
As the pstate status is applicable for non zero streams, check
added for allowing 0 streams inline with dcn internal bandwidth
validations.

Signed-off-by: Bindu Ramamurthy 
Reviewed-by: Roman Li 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 33488b3c5c3c..1812ec7ee11b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -3232,7 +3232,7 @@ static noinline bool dcn20_validate_bandwidth_fp(struct 
dc *dc,
voltage_supported = dcn20_validate_bandwidth_internal(dc, context, 
false);
dummy_pstate_supported = 
context->bw_ctx.bw.dcn.clk.p_state_change_support;
 
-   if (voltage_supported && dummy_pstate_supported) {
+   if (voltage_supported && (dummy_pstate_supported || 
!(context->stream_count))) {
context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
goto restore_dml_state;
}
-- 
2.30.2

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[PATCH AUTOSEL 5.10 32/39] drm/amdgpu: refine amdgpu_fru_get_product_info

[Sasha Levin]

From: Jiansong Chen 

[ Upstream commit 5cfc912582e13b05d71fb7acc4ec69ddfa9af320 ]

1. eliminate potential array index out of bounds.
2. return meaningful value for failure.

Signed-off-by: Jiansong Chen 
Reviewed-by: Jack Gui 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 .../gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c| 42 ++-
 1 file changed, 23 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
index 8f4a8f8d8146..39b6c6bfab45 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
@@ -101,7 +101,8 @@ static int amdgpu_fru_read_eeprom(struct amdgpu_device 
*adev, uint32_t addrptr,
 int amdgpu_fru_get_product_info(struct amdgpu_device *adev)
 {
unsigned char buff[34];
-   int addrptr = 0, size = 0;
+   int addrptr, size;
+   int len;
 
if (!is_fru_eeprom_supported(adev))
return 0;
@@ -109,7 +110,7 @@ int amdgpu_fru_get_product_info(struct amdgpu_device *adev)
/* If algo exists, it means that the i2c_adapter's initialized */
if (!adev->pm.smu_i2c.algo) {
DRM_WARN("Cannot access FRU, EEPROM accessor not initialized");
-   return 0;
+   return -ENODEV;
}
 
/* There's a lot of repetition here. This is due to the FRU having
@@ -128,7 +129,7 @@ int amdgpu_fru_get_product_info(struct amdgpu_device *adev)
size = amdgpu_fru_read_eeprom(adev, addrptr, buff);
if (size < 1) {
DRM_ERROR("Failed to read FRU Manufacturer, ret:%d", size);
-   return size;
+   return -EINVAL;
}
 
/* Increment the addrptr by the size of the field, and 1 due to the
@@ -138,43 +139,45 @@ int amdgpu_fru_get_product_info(struct amdgpu_device 
*adev)
size = amdgpu_fru_read_eeprom(adev, addrptr, buff);
if (size < 1) {
DRM_ERROR("Failed to read FRU product name, ret:%d", size);
-   return size;
+   return -EINVAL;
}
 
+   len = size;
/* Product name should only be 32 characters. Any more,
 * and something could be wrong. Cap it at 32 to be safe
 */
-   if (size > 32) {
+   if (len >= sizeof(adev->product_name)) {
DRM_WARN("FRU Product Number is larger than 32 characters. This 
is likely a mistake");
-   size = 32;
+   len = sizeof(adev->product_name) - 1;
}
/* Start at 2 due to buff using fields 0 and 1 for the address */
-   memcpy(adev->product_name, &buff[2], size);
-   adev->product_name[size] = '\0';
+   memcpy(adev->product_name, &buff[2], len);
+   adev->product_name[len] = '\0';
 
addrptr += size + 1;
size = amdgpu_fru_read_eeprom(adev, addrptr, buff);
if (size < 1) {
DRM_ERROR("Failed to read FRU product number, ret:%d", size);
-   return size;
+   return -EINVAL;
}
 
+   len = size;
/* Product number should only be 16 characters. Any more,
 * and something could be wrong. Cap it at 16 to be safe
 */
-   if (size > 16) {
+   if (len >= sizeof(adev->product_number)) {
DRM_WARN("FRU Product Number is larger than 16 characters. This 
is likely a mistake");
-   size = 16;
+   len = sizeof(adev->product_number) - 1;
}
-   memcpy(adev->product_number, &buff[2], size);
-   adev->product_number[size] = '\0';
+   memcpy(adev->product_number, &buff[2], len);
+   adev->product_number[len] = '\0';
 
addrptr += size + 1;
size = amdgpu_fru_read_eeprom(adev, addrptr, buff);
 
if (size < 1) {
DRM_ERROR("Failed to read FRU product version, ret:%d", size);
-   return size;
+   return -EINVAL;
}
 
addrptr += size + 1;
@@ -182,18 +185,19 @@ int amdgpu_fru_get_product_info(struct amdgpu_device 
*adev)
 
if (size < 1) {
DRM_ERROR("Failed to read FRU serial number, ret:%d", size);
-   return size;
+   return -EINVAL;
}
 
+   len = size;
/* Serial number should only be 16 characters. Any more,
 * and something could be wrong. Cap it at 16 to be safe
 */
-   if (size > 16) {
+   if (len >= sizeof(adev->serial)) {
DRM_WARN("FRU Serial Number is larger than 16 characters. This 
is likely a mistake");
-   size = 16;
+   len = sizeof(adev->serial) - 1;
}
-   memcpy(adev->serial, &buff[2], size);
-   adev->serial[size] = '\0';
+   memcpy(adev->serial, &buff[2], len);
+   adev->serial[len] = '\0';
 
return 0;
 }
-- 
2.30.2

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[PATCH AUTOSEL 5.10 33/39] drm/amd/display: Fix overlay validation by considering cursors

[Sasha Levin]

From: Rodrigo Siqueira 

[ Upstream commit 33f409e60eb0c59a4d0d06a62ab4642a988e17f7 ]

A few weeks ago, we saw a two cursor issue in a ChromeOS system. We
fixed it in the commit:

 drm/amd/display: Fix two cursor duplication when using overlay
 (read the commit message for more details)

After this change, we noticed that some IGT subtests related to
kms_plane and kms_plane_scaling started to fail. After investigating
this issue, we noticed that all subtests that fail have a primary plane
covering the overlay plane, which is currently rejected by amdgpu dm.
Fail those IGT tests highlight that our verification was too broad and
compromises the overlay usage in our drive. This patch fixes this issue
by ensuring that we only reject commits where the primary plane is not
fully covered by the overlay when the cursor hardware is enabled. With
this fix, all IGT tests start to pass again, which means our overlay
support works as expected.

Cc: Tianci.Yin 
Cc: Harry Wentland 
Cc: Nicholas Choi 
Cc: Bhawanpreet Lakha 
Cc: Nicholas Kazlauskas 
Cc: Mark Yacoub 
Cc: Daniel Wheeler 

Tested-by: Daniel Wheeler 
Signed-off-by: Rodrigo Siqueira 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 10 +-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index fbbb1bde6b06..4792228ed481 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -8616,7 +8616,7 @@ static int validate_overlay(struct drm_atomic_state 
*state)
int i;
struct drm_plane *plane;
struct drm_plane_state *old_plane_state, *new_plane_state;
-   struct drm_plane_state *primary_state, *overlay_state = NULL;
+   struct drm_plane_state *primary_state, *cursor_state, *overlay_state = 
NULL;
 
/* Check if primary plane is contained inside overlay */
for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, 
new_plane_state, i) {
@@ -8646,6 +8646,14 @@ static int validate_overlay(struct drm_atomic_state 
*state)
if (!primary_state->crtc)
return 0;
 
+   /* check if cursor plane is enabled */
+   cursor_state = drm_atomic_get_plane_state(state, 
overlay_state->crtc->cursor);
+   if (IS_ERR(cursor_state))
+   return PTR_ERR(cursor_state);
+
+   if (drm_atomic_plane_disabling(plane->state, cursor_state))
+   return 0;
+
/* Perform the bounds check to ensure the overlay plane covers the 
primary */
if (primary_state->crtc_x < overlay_state->crtc_x ||
primary_state->crtc_y < overlay_state->crtc_y ||
-- 
2.30.2

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[PATCH AUTOSEL 5.10 34/39] drm/amd/display: Fix potential memory leak in DMUB hw_init

[Sasha Levin]

From: Roman Li 

[ Upstream commit c5699e2d863f58221044efdc3fa712dd32d55cde ]

[Why]
On resume we perform DMUB hw_init which allocates memory:
dm_resume->dm_dmub_hw_init->dc_dmub_srv_create->kzalloc
That results in memory leak in suspend/resume scenarios.

[How]
Allocate memory for the DC wrapper to DMUB only if it was not
allocated before.
No need to reallocate it on suspend/resume.

Signed-off-by: Lang Yu 
Signed-off-by: Roman Li 
Reviewed-by: Nicholas Kazlauskas 
Acked-by: Qingqing Zhuo 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 4792228ed481..13588c46ae8e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -870,7 +870,8 @@ static int dm_dmub_hw_init(struct amdgpu_device *adev)
abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
}
 
-   adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv);
+   if (!adev->dm.dc->ctx->dmub_srv)
+   adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, 
dmub_srv);
if (!adev->dm.dc->ctx->dmub_srv) {
DRM_ERROR("Couldn't allocate DC DMUB server!\n");
return -ENOMEM;
@@ -1755,7 +1756,6 @@ static int dm_suspend(void *handle)
 
amdgpu_dm_irq_suspend(adev);
 
-
dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
 
return 0;
-- 
2.30.2

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[PATCH AUTOSEL 5.10 35/39] drm/amd/amdgpu:save psp ring wptr to avoid attack

[Sasha Levin]

From: Victor Zhao 

[ Upstream commit 2370eba9f552eaae3d8aa1f70b8e9eec5c560f9e ]

[Why]
When some tools performing psp mailbox attack, the readback value
of register can be a random value which may break psp.

[How]
Use a psp wptr cache machanism to aovid the change made by attack.

v2: unify change and add detailed reason

Signed-off-by: Victor Zhao 
Signed-off-by: Jingwen Chen 
Reviewed-by: Monk Liu 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 1 +
 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c  | 3 ++-
 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c   | 3 ++-
 3 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index 919d2fb7427b..60b7563f4c05 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -73,6 +73,7 @@ struct psp_ring
uint64_tring_mem_mc_addr;
void*ring_mem_handle;
uint32_tring_size;
+   uint32_tring_wptr;
 };
 
 /* More registers may will be supported */
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c 
b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index 6c5d9612abcb..cb764b554552 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -732,7 +732,7 @@ static uint32_t psp_v11_0_ring_get_wptr(struct psp_context 
*psp)
struct amdgpu_device *adev = psp->adev;
 
if (amdgpu_sriov_vf(adev))
-   data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
+   data = psp->km_ring.ring_wptr;
else
data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
 
@@ -746,6 +746,7 @@ static void psp_v11_0_ring_set_wptr(struct psp_context 
*psp, uint32_t value)
if (amdgpu_sriov_vf(adev)) {
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value);
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, 
GFX_CTRL_CMD_ID_CONSUME_CMD);
+   psp->km_ring.ring_wptr = value;
} else
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c 
b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
index f2e725f72d2f..908664a5774b 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
@@ -379,7 +379,7 @@ static uint32_t psp_v3_1_ring_get_wptr(struct psp_context 
*psp)
struct amdgpu_device *adev = psp->adev;
 
if (amdgpu_sriov_vf(adev))
-   data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
+   data = psp->km_ring.ring_wptr;
else
data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
return data;
@@ -394,6 +394,7 @@ static void psp_v3_1_ring_set_wptr(struct psp_context *psp, 
uint32_t value)
/* send interrupt to PSP for SRIOV ring write pointer update */
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
GFX_CTRL_CMD_ID_CONSUME_CMD);
+   psp->km_ring.ring_wptr = value;
} else
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
 }
-- 
2.30.2

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[PATCH AUTOSEL 5.4 24/29] drm/amd/display: Allow bandwidth validation for 0 streams.

[Sasha Levin]

From: Bindu Ramamurthy 

[ Upstream commit ba8e59773ae59818695d1e20b8939282da80ec8c ]

[Why]
Bandwidth calculations are triggered for non zero streams, and
in case of 0 streams, these calculations were skipped with
pstate status not being updated.

[How]
As the pstate status is applicable for non zero streams, check
added for allowing 0 streams inline with dcn internal bandwidth
validations.

Signed-off-by: Bindu Ramamurthy 
Reviewed-by: Roman Li 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 08062de3fbeb..2b1175bb2dae 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -2917,7 +2917,7 @@ bool dcn20_validate_bandwidth(struct dc *dc, struct 
dc_state *context,
voltage_supported = dcn20_validate_bandwidth_internal(dc, context, 
false);
dummy_pstate_supported = 
context->bw_ctx.bw.dcn.clk.p_state_change_support;
 
-   if (voltage_supported && dummy_pstate_supported) {
+   if (voltage_supported && (dummy_pstate_supported || 
!(context->stream_count))) {
context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
goto restore_dml_state;
}
-- 
2.30.2

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[PATCH AUTOSEL 5.4 25/29] drm/amd/display: Fix overlay validation by considering cursors

[Sasha Levin]

From: Rodrigo Siqueira 

[ Upstream commit 33f409e60eb0c59a4d0d06a62ab4642a988e17f7 ]

A few weeks ago, we saw a two cursor issue in a ChromeOS system. We
fixed it in the commit:

 drm/amd/display: Fix two cursor duplication when using overlay
 (read the commit message for more details)

After this change, we noticed that some IGT subtests related to
kms_plane and kms_plane_scaling started to fail. After investigating
this issue, we noticed that all subtests that fail have a primary plane
covering the overlay plane, which is currently rejected by amdgpu dm.
Fail those IGT tests highlight that our verification was too broad and
compromises the overlay usage in our drive. This patch fixes this issue
by ensuring that we only reject commits where the primary plane is not
fully covered by the overlay when the cursor hardware is enabled. With
this fix, all IGT tests start to pass again, which means our overlay
support works as expected.

Cc: Tianci.Yin 
Cc: Harry Wentland 
Cc: Nicholas Choi 
Cc: Bhawanpreet Lakha 
Cc: Nicholas Kazlauskas 
Cc: Mark Yacoub 
Cc: Daniel Wheeler 

Tested-by: Daniel Wheeler 
Signed-off-by: Rodrigo Siqueira 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 10 +-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 6e31e899192c..29657844bac1 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -7272,7 +7272,7 @@ static int validate_overlay(struct drm_atomic_state 
*state)
int i;
struct drm_plane *plane;
struct drm_plane_state *old_plane_state, *new_plane_state;
-   struct drm_plane_state *primary_state, *overlay_state = NULL;
+   struct drm_plane_state *primary_state, *cursor_state, *overlay_state = 
NULL;
 
/* Check if primary plane is contained inside overlay */
for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, 
new_plane_state, i) {
@@ -7302,6 +7302,14 @@ static int validate_overlay(struct drm_atomic_state 
*state)
if (!primary_state->crtc)
return 0;
 
+   /* check if cursor plane is enabled */
+   cursor_state = drm_atomic_get_plane_state(state, 
overlay_state->crtc->cursor);
+   if (IS_ERR(cursor_state))
+   return PTR_ERR(cursor_state);
+
+   if (drm_atomic_plane_disabling(plane->state, cursor_state))
+   return 0;
+
/* Perform the bounds check to ensure the overlay plane covers the 
primary */
if (primary_state->crtc_x < overlay_state->crtc_x ||
primary_state->crtc_y < overlay_state->crtc_y ||
-- 
2.30.2

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Re: [PATCH] drm/radeon: Always call radeon_suspend_kms() in radeon_pci_shutdown()

[Christian König]

Am 07.06.21 um 14:27 schrieb Tiezhu Yang:

radeon_suspend_kms() puts the hw in the suspend state (all asics),
it should always call radeon_suspend_kms() in radeon_pci_shutdown(),
this is a normal cleanup process to avoid more operations on radeon,
just remove #ifdef CONFIG_PPC64 and the related comments.


Well NAK.

Alex knows more about the details but suspending should not be part of 
the pci shotdown process at all.


We just add that here to enforce a GPU reset on PPC64 boards for some 
reason.


Regards,
Christian.



Co-developed-by: Jianmin Lv 
Signed-off-by: Jianmin Lv 
Signed-off-by: Tiezhu Yang 
---
  drivers/gpu/drm/radeon/radeon_drv.c | 9 -
  1 file changed, 9 deletions(-)

diff --git a/drivers/gpu/drm/radeon/radeon_drv.c 
b/drivers/gpu/drm/radeon/radeon_drv.c
index efeb115..0b1f43d 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -386,16 +386,7 @@ radeon_pci_shutdown(struct pci_dev *pdev)
if (radeon_device_is_virtual())
radeon_pci_remove(pdev);
  
-#ifdef CONFIG_PPC64

-   /*
-* Some adapters need to be suspended before a
-* shutdown occurs in order to prevent an error
-* during kexec.
-* Make this power specific becauase it breaks
-* some non-power boards.
-*/
radeon_suspend_kms(pci_get_drvdata(pdev), true, true, false);
-#endif
  }
  
  static int radeon_pmops_suspend(struct device *dev)


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[PATCH] drm/amd/pm: fix warning reported by kernel test robot

[Xiaomeng Hou]

Kernel test robot throws warning ->

>> drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/yellow_carp_ppt.c:483:2:
   warning: variable 'member_type' is used uninitialized whenever switch
   default is taken [-Wsometimes-uninitialized]
   default:
   ^~~
   drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/yellow_carp_ppt.c:487:47:
   note: uninitialized use occurs here
   return yellow_carp_get_smu_metrics_data(smu, member_type, value);
   ^~~
   drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/yellow_carp_ppt.c:465:2:
   note: variable 'member_type' is declared here
   MetricsMember_t member_type;
   ^
   1 warning generated.

Fix this warning by return errno when the clk type is unsupported.

Signed-off-by: Xiaomeng Hou 
Reported-by: kernel test robot 
---
 drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
index 031c49fb4582..0cd7902d5172 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
@@ -728,7 +728,7 @@ static int yellow_carp_get_current_clk_freq(struct 
smu_context *smu,
return smu_cmn_send_smc_msg_with_param(smu,
SMU_MSG_GetFclkFrequency, 0, value);
default:
-   break;
+   return -EINVAL;
}
 
return yellow_carp_get_smu_metrics_data(smu, member_type, value);
-- 
2.17.1

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[PATCH 06/30] drm/amd/display: Refactor visual confirm

[Stylon Wang]

From: Wyatt Wood 

[Why + How]
Visual confirm has no asic-specific logic,
so we can refactor and unify these functions
that are currently spread out across multiple
dcn files.
Add a new hw sequencer interface update_visual_confirm_color,
and a new mpc function pointer set_bg_color.
This will allow visual confirm to updated independently
of MPCC blending updates.

Signed-off-by: Wyatt Wood 
Reviewed-by: Aric Cyr 
Acked-by: Stylon Wang 
---
 .../drm/amd/display/dc/core/dc_hw_sequencer.c |  98 
 .../display/dc/dce110/dce110_hw_sequencer.c   |  35 --
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 108 +++---
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.h |  12 +-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_init.c |   3 +-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c  |   4 +-
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.c|  43 +++
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.h|   5 +
 .../gpu/drm/amd/display/dc/dcn20/dcn20_init.c |   3 +-
 .../gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c  |   2 +-
 .../gpu/drm/amd/display/dc/dcn21/dcn21_init.c |   3 +-
 .../gpu/drm/amd/display/dc/dcn30/dcn30_init.c |   3 +-
 .../gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c  |   2 +-
 .../drm/amd/display/dc/dcn301/dcn301_init.c   |   3 +-
 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h   |   3 +
 .../gpu/drm/amd/display/dc/inc/hw_sequencer.h |  15 +++
 .../amd/display/dc/inc/hw_sequencer_private.h |   5 -
 17 files changed, 170 insertions(+), 177 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
index 2a9080400bdd..e0badab842ba 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
@@ -291,3 +291,101 @@ bool hwss_wait_for_blank_complete(
 
return true;
 }
+
+void get_mpctree_visual_confirm_color(
+   struct pipe_ctx *pipe_ctx,
+   struct tg_color *color)
+{
+   const struct tg_color pipe_colors[6] = {
+   {MAX_TG_COLOR_VALUE, 0, 0}, /* red */
+   {MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE / 4, 0}, /* 
orange */
+   {MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE, 0}, /* yellow 
*/
+   {0, MAX_TG_COLOR_VALUE, 0}, /* green */
+   {0, 0, MAX_TG_COLOR_VALUE}, /* blue */
+   {MAX_TG_COLOR_VALUE / 2, 0, MAX_TG_COLOR_VALUE / 2}, /* 
purple */
+   };
+
+   struct pipe_ctx *top_pipe = pipe_ctx;
+
+   while (top_pipe->top_pipe)
+   top_pipe = top_pipe->top_pipe;
+
+   *color = pipe_colors[top_pipe->pipe_idx];
+}
+
+void get_surface_visual_confirm_color(
+   const struct pipe_ctx *pipe_ctx,
+   struct tg_color *color)
+{
+   uint32_t color_value = MAX_TG_COLOR_VALUE;
+
+   switch (pipe_ctx->plane_res.scl_data.format) {
+   case PIXEL_FORMAT_ARGB:
+   /* set border color to red */
+   color->color_r_cr = color_value;
+   break;
+
+   case PIXEL_FORMAT_ARGB2101010:
+   /* set border color to blue */
+   color->color_b_cb = color_value;
+   break;
+   case PIXEL_FORMAT_420BPP8:
+   /* set border color to green */
+   color->color_g_y = color_value;
+   break;
+   case PIXEL_FORMAT_420BPP10:
+   /* set border color to yellow */
+   color->color_g_y = color_value;
+   color->color_r_cr = color_value;
+   break;
+   case PIXEL_FORMAT_FP16:
+   /* set border color to white */
+   color->color_r_cr = color_value;
+   color->color_b_cb = color_value;
+   color->color_g_y = color_value;
+   break;
+   default:
+   break;
+   }
+}
+
+void get_hdr_visual_confirm_color(
+   struct pipe_ctx *pipe_ctx,
+   struct tg_color *color)
+{
+   uint32_t color_value = MAX_TG_COLOR_VALUE;
+
+   /* Determine the overscan color based on the top-most (desktop) plane's 
context */
+   struct pipe_ctx *top_pipe_ctx  = pipe_ctx;
+
+   while (top_pipe_ctx->top_pipe != NULL)
+   top_pipe_ctx = top_pipe_ctx->top_pipe;
+
+   switch (top_pipe_ctx->plane_res.scl_data.format) {
+   case PIXEL_FORMAT_ARGB2101010:
+   if (top_pipe_ctx->stream->out_transfer_func->tf == 
TRANSFER_FUNCTION_PQ) {
+   /* HDR10, ARGB2101010 - set border color to red */
+   color->color_r_cr = color_value;
+   } else if (top_pipe_ctx->stream->out_transfer_func->tf == 
TRANSFER_FUNCTION_GAMMA22) {
+   /* FreeSync 2 ARGB2101010 - set border color to pink */
+   color->color_r_cr = color_value;
+   color->color_b_cb = color_value;
+   }
+   break;
+   case PI

[PATCH 07/30] drm/amd/display: add visual confirm colors to differentiate layer_index > 0

[Stylon Wang]

From: Evgenii Krasnikov 

[WHY]
Currently there is no way to visually identify if there is one or more
layers presented fullscreen on the display

[HOW]
Add new visual confirm colors in get_surface_visual_confirm_color for
planes with layer_index > 0

Signed-off-by: Evgenii Krasnikov 
Reviewed-by: Aric Cyr 
Acked-by: Stylon Wang 
---
 .../gpu/drm/amd/display/dc/core/dc_hw_sequencer.c  | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
index e0badab842ba..ee3eef5a1f44 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
@@ -323,11 +323,20 @@ void get_surface_visual_confirm_color(
case PIXEL_FORMAT_ARGB:
/* set border color to red */
color->color_r_cr = color_value;
+   if (pipe_ctx->plane_state->layer_index > 0) {
+   /* set border color to pink */
+   color->color_b_cb = color_value;
+   color->color_g_y = color_value * 0.5;
+   }
break;
 
case PIXEL_FORMAT_ARGB2101010:
/* set border color to blue */
color->color_b_cb = color_value;
+   if (pipe_ctx->plane_state->layer_index > 0) {
+   /* set border color to cyan */
+   color->color_g_y = color_value;
+   }
break;
case PIXEL_FORMAT_420BPP8:
/* set border color to green */
@@ -343,6 +352,11 @@ void get_surface_visual_confirm_color(
color->color_r_cr = color_value;
color->color_b_cb = color_value;
color->color_g_y = color_value;
+   if (pipe_ctx->plane_state->layer_index > 0) {
+   /* set border color to orange */
+   color->color_g_y = 0.22 * color_value;
+   color->color_b_cb = 0;
+   }
break;
default:
break;
-- 
2.25.1

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[PATCH 28/30] drm/amd/display: Add swizzle visual confirm mode

[Stylon Wang]

From: Po-Ting Chen 

[Why]
To support a new visual confirm mode: swizzle to show the specific
color at the screen border according to different surface swizzle mode.
Currently we only support the Linear mode with red color.

Signed-off-by: Po-Ting Chen 
---
 .../drm/amd/display/dc/core/dc_hw_sequencer.c | 21 +++
 drivers/gpu/drm/amd/display/dc/dc.h   |  1 +
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c |  2 ++
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.c|  2 ++
 .../gpu/drm/amd/display/dc/inc/hw_sequencer.h |  4 +++-
 5 files changed, 29 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
index ee3eef5a1f44..15f987a63025 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
@@ -403,3 +403,24 @@ void get_hdr_visual_confirm_color(
break;
}
 }
+
+void get_surface_tile_visual_confirm_color(
+   struct pipe_ctx *pipe_ctx,
+   struct tg_color *color)
+{
+   uint32_t color_value = MAX_TG_COLOR_VALUE;
+   /* Determine the overscan color based on the top-most (desktop) plane's 
context */
+   struct pipe_ctx *top_pipe_ctx  = pipe_ctx;
+
+   while (top_pipe_ctx->top_pipe != NULL)
+   top_pipe_ctx = top_pipe_ctx->top_pipe;
+
+   switch (top_pipe_ctx->plane_state->tiling_info.gfx9.swizzle) {
+   case DC_SW_LINEAR:
+   /* LINEAR Surface - set border color to red */
+   color->color_r_cr = color_value;
+   break;
+   default:
+   break;
+   }
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 356e15c9df60..b4104b7422d8 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -318,6 +318,7 @@ enum visual_confirm {
VISUAL_CONFIRM_HDR = 2,
VISUAL_CONFIRM_MPCTREE = 4,
VISUAL_CONFIRM_PSR = 5,
+   VISUAL_CONFIRM_SWIZZLE = 9,
 };
 
 enum dcc_option {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index be5287e39dc0..3b175af97388 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2433,6 +2433,8 @@ void dcn10_update_visual_confirm_color(struct dc *dc, 
struct pipe_ctx *pipe_ctx,
get_hdr_visual_confirm_color(pipe_ctx, color);
else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE)
get_surface_visual_confirm_color(pipe_ctx, color);
+   else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SWIZZLE)
+   get_surface_tile_visual_confirm_color(pipe_ctx, color);
else
color_space_to_black_color(
dc, pipe_ctx->stream->output_color_space, 
color);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index a48467d75e3d..477e136ca8de 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -2257,6 +2257,8 @@ void dcn20_update_visual_confirm_color(struct dc *dc, 
struct pipe_ctx *pipe_ctx,
get_surface_visual_confirm_color(pipe_ctx, color);
else if (dc->debug.visual_confirm == VISUAL_CONFIRM_MPCTREE)
get_mpctree_visual_confirm_color(pipe_ctx, color);
+   else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SWIZZLE)
+   get_surface_tile_visual_confirm_color(pipe_ctx, color);
 
if (mpc->funcs->set_bg_color)
mpc->funcs->set_bg_color(mpc, color, mpcc_id);
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h 
b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index 25b3933375c7..420997e0b853 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -263,5 +263,7 @@ void get_hdr_visual_confirm_color(
 void get_mpctree_visual_confirm_color(
struct pipe_ctx *pipe_ctx,
struct tg_color *color);
-
+void get_surface_tile_visual_confirm_color(
+   struct pipe_ctx *pipe_ctx,
+   struct tg_color *color);
 #endif /* __DC_HW_SEQUENCER_H__ */
-- 
2.25.1

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Re: [PATCH] drm/amd/display: remove no need variable

[Alex Deucher]

On Sat, Jun 5, 2021 at 8:31 AM Bernard Zhao  wrote:
>
> remove no need variable, just return the DC_OK
>
> Signed-off-by: Bernard Zhao 

Applied.  Thanks!

Alex

> ---
>  drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 4 +---
>  1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 
> b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
> index f962b905e79e..7daadb6a5233 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
> @@ -1266,8 +1266,6 @@ static enum dc_status dcn10_validate_global(struct dc 
> *dc, struct dc_state *cont
>
>  static enum dc_status dcn10_patch_unknown_plane_state(struct dc_plane_state 
> *plane_state)
>  {
> -   enum dc_status result = DC_OK;
> -
> enum surface_pixel_format surf_pix_format = plane_state->format;
> unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format);
>
> @@ -1279,7 +1277,7 @@ static enum dc_status 
> dcn10_patch_unknown_plane_state(struct dc_plane_state *pla
> swizzle = DC_SW_64KB_S;
>
> plane_state->tiling_info.gfx9.swizzle = swizzle;
> -   return result;
> +   return DC_OK;
>  }
>
>  struct stream_encoder *dcn10_find_first_free_match_stream_enc_for_link(
> --
> 2.31.0
>
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Re: [PATCH] drm/amd/display: Fix duplicate included dce110_hw_sequencer.h

[Alex Deucher]

Applied.  Thanks!

Alex

On Mon, Jun 7, 2021 at 6:27 AM Jiapeng Chong
 wrote:
>
> Clean up the following includecheck warning:
>
> ./drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c:
> dce110_hw_sequencer.h is included more than once.
>
> No functional change.
>
> Reported-by: Abaci Robot 
> Signed-off-by: Jiapeng Chong 
> ---
>  drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 1 -
>  1 file changed, 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 
> b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
> index e731987..04d02ce 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
> +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
> @@ -32,7 +32,6 @@
>  #include "core_status.h"
>  #include "resource.h"
>  #include "dm_helpers.h"
> -#include "dce110_hw_sequencer.h"
>  #include "dce110_timing_generator.h"
>  #include "dce/dce_hwseq.h"
>  #include "gpio_service_interface.h"
> --
> 1.8.3.1
>
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Re: [PATCH] drm/amdgpu: Fix a a typo in a comment

[Alex Deucher]

Applied.  Thanks!

Alex

On Mon, Jun 7, 2021 at 6:46 AM Christian König
 wrote:
>
> Am 05.06.21 um 11:06 schrieb Christophe JAILLET:
> > s/than/then/
> >
> > Signed-off-by: Christophe JAILLET 
>
> Acked-by: Christian König 
>
> > ---
> >   drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 2 +-
> >   1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> > index 89ebbf363e27..1476236f5c7c 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> > @@ -662,7 +662,7 @@ static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser 
> > *p)
> >* @error:  error number
> >* @backoff:indicator to backoff the reservation
> >*
> > - * If error is set than unvalidate buffer, otherwise just free memory
> > + * If error is set then unvalidate buffer, otherwise just free memory
> >* used by parsing context.
> >**/
> >   static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int 
> > error,
>
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Re: [PATCH][next] drm/amd/display: Fix two spelling mistakes, clean wide lines

[Alex Deucher]

Applied.  Thanks!

Alex

On Mon, Jun 7, 2021 at 7:58 AM Colin King  wrote:
>
> From: Colin Ian King 
>
> There are two spelling mistakes in dml_print messages, fix these and
> clear up checkpatch warning on overly wide line length.
>
> Signed-off-by: Colin Ian King 
> ---
>  .../drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c | 10 ++
>  1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c 
> b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
> index c725160a095b..d655655baaba 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
> @@ -1494,10 +1494,11 @@ static bool CalculatePrefetchSchedule(
> dml_print(
> "DML:  Tsw: %fus = time to fetch enough pixel 
> data and cursor data to feed the scalers init position and detile\n",
> (double) LinesToRequestPrefetchPixelData * 
> LineTime);
> -   dml_print("DML: To: %fus - time for propogation from scaler 
> to optc\n", (*DSTYAfterScaler + ((double) (*DSTXAfterScaler) / (double) 
> myPipe->HTotal)) * LineTime);
> +   dml_print("DML: To: %fus - time for propagation from scaler 
> to optc\n",
> + (*DSTYAfterScaler + ((double) (*DSTXAfterScaler) /
> + (double) myPipe->HTotal)) * LineTime);
> dml_print("DML: Tvstartup - TSetup - Tcalc - Twait - Tpre - 
> To > 0\n");
> -   dml_print(
> -   "DML: Tslack(pre): %fus - time left over in 
> schedule\n",
> +   dml_print("DML: Tslack(pre): %fus - time left over in 
> schedule\n",
> VStartup * LineTime - TimeForFetchingMetaPTE 
> - 2 * TimeForFetchingRowInVBlank
> - (*DSTYAfterScaler + 
> ((double) (*DSTXAfterScaler) / (double) myPipe->HTotal)) * LineTime - TWait - 
> TCalc - *TSetup);
> dml_print("DML: row_bytes = dpte_row_bytes (per_pipe) = 
> PixelPTEBytesPerRow = : %d\n", PixelPTEBytesPerRow);
> @@ -3023,7 +3024,8 @@ static void 
> DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
> for (k = 0; k < v->NumberOfActivePlanes; ++k) {
> if (v->ImmediateFlipSupportedForPipe[k] == 
> false) {
>  #ifdef __DML_VBA_DEBUG__
> -   dml_print("DML::%s: Pipe %0d not 
> supporing iflip\n", __func__, k);
> +   dml_print("DML::%s: Pipe %0d not 
> supporting iflip\n",
> + __func__, k);
>  #endif
> v->ImmediateFlipSupported = false;
> }
> --
> 2.31.1
>
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Re: [PATCH] drm/amdkfd: remove duplicate include of kfd_svm.h

[Felix Kuehling]

Am 2021-06-04 um 10:54 p.m. schrieb Wan Jiabing:
> kfd_svm.h is included duplicately in commit 42de677f7
> ("drm/amdkfd: register svm range"). 
>
> After checking possible related header files,
> remove the former one to make the code format more reasonable.
>
> Signed-off-by: Wan Jiabing 

Reviewed-by: Felix Kuehling 

I will apply the patch to amd-staging-drm-next. Thanks.

> ---
>  drivers/gpu/drm/amd/amdkfd/kfd_process.c | 1 -
>  1 file changed, 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c 
> b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
> index bfa6c4cd2f44..f1f40bba5c60 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
> @@ -35,7 +35,6 @@
>  #include 
>  #include "amdgpu_amdkfd.h"
>  #include "amdgpu.h"
> -#include "kfd_svm.h"
>  
>  struct mm_struct;
>  
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Re: [PATCH] drm/amdgpu: Use PSP to program IH_RB_CNTL_RING1/2 on SRIOV

[Christian König]

That won't work either.

We still need to initialize the control registers and tell the hardware 
that we have properly setup the ring buffers.


Just add the error message to psp_reg_program() instead of duplicating 
that over and over again.


Christian.

Am 07.06.21 um 19:33 schrieb Khaire, Rohit:

[AMD Public Use]

OK.

I will just skip the function call for SRIOV and resend.

Rohit

-Original Message-
From: Koenig, Christian 
Sent: June 7, 2021 12:42 PM
To: Kuehling, Felix ; Khaire, Rohit ; amd-gfx@lists.freedesktop.org; 
Deucher, Alexander ; Zhang, Hawking ; Deng, Emily 
; Liu, Monk ; Zhou, Peng Ju ; Chen, Horace 

Cc: Ming, Davis 
Subject: Re: [PATCH] drm/amdgpu: Use PSP to program IH_RB_CNTL_RING1/2 on SRIOV

Ah, good point. In this case we should probably rather save than sorry.

Then I suggest to clean up this patch, repeating the psp_reg_program() and 
error message is pretty horrible coding style.

Christian.

Am 07.06.21 um 18:36 schrieb Felix Kuehling:

With SRIOV, the interrupt routing is setup by the hypervisor driver.
We need the secondary IH rings in case the hypervisor enabled
rerouting of page fault interrupts. I'm not sure what the hypervisor driver 
does today.

Regards,
    Felix


Am 2021-06-07 um 12:29 p.m. schrieb Christian König:

That's a workaround for bare metal and as far as I know doesn't apply
to SRIOV.

We only need the additional IH rings for page fault handling or log
handling and as far as I know that is incompatible with SRIOV for the
moment. But Felix might have some more updates on this.

So as long as we don't support that under SRIOV we don't need this
patch either.

Christian.

Am 07.06.21 um 17:59 schrieb Khaire, Rohit:

[AMD Public Use]

The hash is 5ea6f9c

Rohit

-Original Message-
From: Koenig, Christian 
Sent: June 7, 2021 11:58 AM
To: Khaire, Rohit ;
amd-gfx@lists.freedesktop.org; Deucher, Alexander
; Zhang, Hawking ;
Deng, Emily ; Liu, Monk ;
Zhou, Peng Ju ; Chen, Horace

Cc: Ming, Davis 
Subject: Re: [PATCH] drm/amdgpu: Use PSP to program
IH_RB_CNTL_RING1/2 on SRIOV

Do you have the hash for this commit?

Thanks,
Christian.

Am 07.06.21 um 17:30 schrieb Khaire, Rohit:

[AMD Public Use]

We don't need RING1 and RING2 functionality for SRIOV afaik.

But looking at the description of the original commit message it
affects RING0 too?

" drm/amdgpu: add timeout flush mechanism to update wptr for self
interrupt (v2)

outstanding log reaches threshold will trigger IH ring1/2's wptr
reported, that will avoid generating interrupts to ring0 too frequent.
But if ring1/2's wptr hasn't been increased for a long time, the
outstanding log can't reach threshold so that driver can't get
latest wptr info and miss some interrupts."

Rohit

-Original Message-
From: Koenig, Christian 
Sent: June 7, 2021 10:31 AM
To: Khaire, Rohit ;
amd-gfx@lists.freedesktop.org; Deucher, Alexander
; Zhang, Hawking
; Deng, Emily ; Liu,
Monk ; Zhou, Peng Ju ; Chen,
Horace 
Cc: Ming, Davis 
Subject: Re: [PATCH] drm/amdgpu: Use PSP to program
IH_RB_CNTL_RING1/2 on SRIOV

Why are the ring 1&2 enabled on SRIOV in the first place?

Christian.

Am 07.06.21 um 16:23 schrieb Rohit Khaire:

This is similar to IH_RB_CNTL programming in
navi10_ih_toggle_ring_interrupts

Signed-off-by: Rohit Khaire 
---
      drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 20
++--
      1 file changed, 18 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
index eac564e8dd52..e41188c04846 100644
--- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
@@ -120,11 +120,27 @@ force_update_wptr_for_self_int(struct
amdgpu_device *adev,
      ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
     RB_USED_INT_THRESHOLD, threshold);
      -    WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
+    if (amdgpu_sriov_vf(adev) &&
amdgpu_sriov_reg_indirect_ih(adev)) {
+    if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1,
ih_rb_cntl)) {
+    DRM_ERROR("PSP program IH_RB_CNTL_RING1 failed!\n");
+    return;
+    }
+    } else {
+    WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
+    }
+
      ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
      ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,
     RB_USED_INT_THRESHOLD, threshold);
-    WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
+    if (amdgpu_sriov_vf(adev) &&
amdgpu_sriov_reg_indirect_ih(adev)) {
+    if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2,
ih_rb_cntl)) {
+    DRM_ERROR("PSP program IH_RB_CNTL_RING2 failed!\n");
+    return;
+    }
+    } else {
+    WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
+    }
+
      WREG32_SOC15(OSSSYS, 0, mmIH_CNTL2, ih_cntl);
      }
  

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[PATCH v5 3/9] drm/amd/pm: Add common throttler translation func

[Graham Sider]

Defines smu_cmn_get_indep_throttler_status which performs ASIC
independent translation given a corresponding lookup table.

Signed-off-by: Graham Sider 
---
 drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 13 +
 drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h |  4 
 2 files changed, 17 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
index 01645537d9ab..269a42c0536a 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
@@ -398,6 +398,19 @@ int smu_cmn_get_enabled_32_bits_mask(struct smu_context 
*smu,
 
 }
 
+uint64_t smu_cmn_get_indep_throttler_status(
+   const unsigned long dep_status,
+   const uint8_t *throttler_map)
+{
+   uint64_t indep_status = 0;
+   uint8_t dep_bit = 0;
+
+   for_each_set_bit(dep_bit, &dep_status, 32)
+   indep_status |= 1ULL << throttler_map[dep_bit];
+
+   return indep_status;
+}
+
 int smu_cmn_feature_update_enable_state(struct smu_context *smu,
uint64_t feature_mask,
bool enabled)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h 
b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h
index da6ff6f024f9..c57ce2b2cdc6 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h
@@ -60,6 +60,10 @@ int smu_cmn_get_enabled_32_bits_mask(struct smu_context *smu,
uint32_t *feature_mask,
uint32_t num);
 
+uint64_t smu_cmn_get_indep_throttler_status(
+   const unsigned long dep_status,
+   const uint8_t *throttler_map);
+
 int smu_cmn_feature_update_enable_state(struct smu_context *smu,
uint64_t feature_mask,
bool enabled);
-- 
2.17.1

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[PATCH v5 1/9] drm/amd/pm: Add u64 throttler status field to gpu_metrics

[Graham Sider]

This patch set adds support for a new ASIC independant u64 throttler
status field (indep_throttle_status). Piggybacks off the
gpu_metrics_v1_3 bump and similarly bumps  gpu_metrics_v2 version (to
v2_2) to add field.

Signed-off-by: Graham Sider 
---
 .../gpu/drm/amd/include/kgd_pp_interface.h| 58 ++-
 drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c|  3 +
 2 files changed, 60 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h 
b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index 7bc7492f37b9..271018ce739b 100644
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -579,7 +579,7 @@ struct gpu_metrics_v1_3 {
uint16_tcurrent_vclk1;
uint16_tcurrent_dclk1;
 
-   /* Throttle status */
+   /* Throttle status (ASIC dependent) */
uint32_tthrottle_status;
 
/* Fans */
@@ -605,6 +605,9 @@ struct gpu_metrics_v1_3 {
uint16_tvoltage_mem;
 
uint16_tpadding1;
+
+   /* Throttle status (ASIC independent) */
+   uint64_tindep_throttle_status;
 };
 
 /*
@@ -711,4 +714,57 @@ struct gpu_metrics_v2_1 {
uint16_tpadding[3];
 };
 
+struct gpu_metrics_v2_2 {
+   struct metrics_table_header common_header;
+
+   /* Temperature */
+   uint16_ttemperature_gfx; // gfx temperature on 
APUs
+   uint16_ttemperature_soc; // soc temperature on 
APUs
+   uint16_ttemperature_core[8]; // CPU core 
temperature on APUs
+   uint16_ttemperature_l3[2];
+
+   /* Utilization */
+   uint16_taverage_gfx_activity;
+   uint16_taverage_mm_activity; // UVD or VCN
+
+   /* Driver attached timestamp (in ns) */
+   uint64_tsystem_clock_counter;
+
+   /* Power/Energy */
+   uint16_taverage_socket_power; // dGPU + APU 
power on A + A platform
+   uint16_taverage_cpu_power;
+   uint16_taverage_soc_power;
+   uint16_taverage_gfx_power;
+   uint16_taverage_core_power[8]; // CPU core 
power on APUs
+
+   /* Average clocks */
+   uint16_taverage_gfxclk_frequency;
+   uint16_taverage_socclk_frequency;
+   uint16_taverage_uclk_frequency;
+   uint16_taverage_fclk_frequency;
+   uint16_taverage_vclk_frequency;
+   uint16_taverage_dclk_frequency;
+
+   /* Current clocks */
+   uint16_tcurrent_gfxclk;
+   uint16_tcurrent_socclk;
+   uint16_tcurrent_uclk;
+   uint16_tcurrent_fclk;
+   uint16_tcurrent_vclk;
+   uint16_tcurrent_dclk;
+   uint16_tcurrent_coreclk[8]; // CPU core clocks
+   uint16_tcurrent_l3clk[2];
+
+   /* Throttle status (ASIC dependent) */
+   uint32_tthrottle_status;
+
+   /* Fans */
+   uint16_tfan_pwm;
+
+   uint16_tpadding[3];
+
+   /* Throttle status (ASIC independent) */
+   uint64_tindep_throttle_status;
+};
+
 #endif
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
index 0ceb7329838c..01645537d9ab 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
@@ -773,6 +773,9 @@ void smu_cmn_init_soft_gpu_metrics(void *table, uint8_t 
frev, uint8_t crev)
case METRICS_VERSION(2, 1):
structure_size = sizeof(struct gpu_metrics_v2_1);
break;
+   case METRICS_VERSION(2, 2):
+   structure_size = sizeof(struct gpu_metrics_v2_2);
+   break;
default:
return;
}
-- 
2.17.1

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[PATCH v5 5/9] drm/amd/pm: Add navi1x throttler translation

[Graham Sider]

Perform dependent to independent throttle status translation
for navi1x.

Signed-off-by: Graham Sider 
---
 .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c   | 34 +++
 1 file changed, 34 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index 78fe13183e8b..9e679912cd3f 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -238,6 +238,28 @@ static struct cmn2asic_mapping 
navi10_workload_map[PP_SMC_POWER_PROFILE_COUNT] =
WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,   
WORKLOAD_PPLIB_CUSTOM_BIT),
 };
 
+static const uint8_t navi1x_throttler_map[] = {
+   [THROTTLER_TEMP_EDGE_BIT]   = (SMU_THROTTLER_TEMP_EDGE_BIT),
+   [THROTTLER_TEMP_HOTSPOT_BIT]= (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
+   [THROTTLER_TEMP_MEM_BIT]= (SMU_THROTTLER_TEMP_MEM_BIT),
+   [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
+   [THROTTLER_TEMP_VR_MEM0_BIT]= (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
+   [THROTTLER_TEMP_VR_MEM1_BIT]= (SMU_THROTTLER_TEMP_VR_MEM1_BIT),
+   [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
+   [THROTTLER_TEMP_LIQUID0_BIT]= (SMU_THROTTLER_TEMP_LIQUID0_BIT),
+   [THROTTLER_TEMP_LIQUID1_BIT]= (SMU_THROTTLER_TEMP_LIQUID1_BIT),
+   [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT),
+   [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT),
+   [THROTTLER_PPT0_BIT]= (SMU_THROTTLER_PPT0_BIT),
+   [THROTTLER_PPT1_BIT]= (SMU_THROTTLER_PPT1_BIT),
+   [THROTTLER_PPT2_BIT]= (SMU_THROTTLER_PPT2_BIT),
+   [THROTTLER_PPT3_BIT]= (SMU_THROTTLER_PPT3_BIT),
+   [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT),
+   [THROTTLER_PPM_BIT] = (SMU_THROTTLER_PPM_BIT),
+   [THROTTLER_APCC_BIT]= (SMU_THROTTLER_APCC_BIT),
+};
+
+
 static bool is_asic_secure(struct smu_context *smu)
 {
struct amdgpu_device *adev = smu->adev;
@@ -2673,6 +2695,9 @@ static ssize_t navi10_get_legacy_gpu_metrics(struct 
smu_context *smu,
gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
 
gpu_metrics->throttle_status = metrics.ThrottlerStatus;
+   gpu_metrics->indep_throttle_status =
+   
smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
+  
navi1x_throttler_map);
 
gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
 
@@ -2750,6 +2775,9 @@ static ssize_t navi10_get_gpu_metrics(struct smu_context 
*smu,
gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
 
gpu_metrics->throttle_status = metrics.ThrottlerStatus;
+   gpu_metrics->indep_throttle_status =
+   
smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
+  
navi1x_throttler_map);
 
gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
 
@@ -2826,6 +2854,9 @@ static ssize_t navi12_get_legacy_gpu_metrics(struct 
smu_context *smu,
gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
 
gpu_metrics->throttle_status = metrics.ThrottlerStatus;
+   gpu_metrics->indep_throttle_status =
+   
smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
+  
navi1x_throttler_map);
 
gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
 
@@ -2908,6 +2939,9 @@ static ssize_t navi12_get_gpu_metrics(struct smu_context 
*smu,
gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
 
gpu_metrics->throttle_status = metrics.ThrottlerStatus;
+   gpu_metrics->indep_throttle_status =
+   
smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
+  
navi1x_throttler_map);
 
gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
 
-- 
2.17.1

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[PATCH v5 2/9] drm/amd/pm: Add ASIC independent throttle bits

[Graham Sider]

Add new defines for thermal throttle status bits which are ASIC
independent. This bit field will be visible to userspace via
gpu_metrics alongside the previous ASIC dependent bit fields. Seperated
into four 16-bit types: power throttlers, current throttlers,
temperature, other.

Signed-off-by: Graham Sider 
---
 drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 41 +
 1 file changed, 41 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h 
b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
index 71adb9e76a95..829fd8651221 100644
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
@@ -35,6 +35,47 @@
 
 #define SMU_DPM_USER_PROFILE_RESTORE (1 << 0)
 
+// Power Throttlers
+#define SMU_THROTTLER_PPT0_BIT 0
+#define SMU_THROTTLER_PPT1_BIT 1
+#define SMU_THROTTLER_PPT2_BIT 2
+#define SMU_THROTTLER_PPT3_BIT 3
+#define SMU_THROTTLER_SPL_BIT  4
+#define SMU_THROTTLER_FPPT_BIT 5
+#define SMU_THROTTLER_SPPT_BIT 6
+#define SMU_THROTTLER_SPPT_APU_BIT 7
+
+// Current Throttlers
+#define SMU_THROTTLER_TDC_GFX_BIT  16
+#define SMU_THROTTLER_TDC_SOC_BIT  17
+#define SMU_THROTTLER_TDC_MEM_BIT  18
+#define SMU_THROTTLER_TDC_VDD_BIT  19
+#define SMU_THROTTLER_TDC_CVIP_BIT 20
+#define SMU_THROTTLER_EDC_CPU_BIT  21
+#define SMU_THROTTLER_EDC_GFX_BIT  22
+#define SMU_THROTTLER_APCC_BIT 23
+
+// Temperature
+#define SMU_THROTTLER_TEMP_GPU_BIT 32
+#define SMU_THROTTLER_TEMP_CORE_BIT33
+#define SMU_THROTTLER_TEMP_MEM_BIT 34
+#define SMU_THROTTLER_TEMP_EDGE_BIT35
+#define SMU_THROTTLER_TEMP_HOTSPOT_BIT 36
+#define SMU_THROTTLER_TEMP_VR_GFX_BIT  37
+#define SMU_THROTTLER_TEMP_VR_SOC_BIT  38
+#define SMU_THROTTLER_TEMP_VR_MEM0_BIT 39
+#define SMU_THROTTLER_TEMP_VR_MEM1_BIT 40
+#define SMU_THROTTLER_TEMP_LIQUID0_BIT 41
+#define SMU_THROTTLER_TEMP_LIQUID1_BIT 42
+#define SMU_THROTTLER_VRHOT0_BIT   43
+#define SMU_THROTTLER_VRHOT1_BIT   44
+#define SMU_THROTTLER_PROCHOT_CPU_BIT  45
+#define SMU_THROTTLER_PROCHOT_GFX_BIT  46
+
+// Other
+#define SMU_THROTTLER_PPM_BIT  48
+#define SMU_THROTTLER_FIT_BIT  49
+
 struct smu_hw_power_state {
unsigned int magic;
 };
-- 
2.17.1

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[PATCH v5 4/9] drm/amd/pm: Add arcturus throttler translation

[Graham Sider]

Perform dependent to independent throttle status translation
for arcturus.

Signed-off-by: Graham Sider 
---
 .../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 33 ---
 1 file changed, 28 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
index 1735a96dd307..a47fc33e997d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
@@ -211,6 +211,26 @@ static const struct cmn2asic_mapping 
arcturus_workload_map[PP_SMC_POWER_PROFILE_
WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,   
WORKLOAD_PPLIB_CUSTOM_BIT),
 };
 
+static const uint8_t arcturus_throttler_map[] = {
+   [THROTTLER_TEMP_EDGE_BIT]   = (SMU_THROTTLER_TEMP_EDGE_BIT),
+   [THROTTLER_TEMP_HOTSPOT_BIT]= (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
+   [THROTTLER_TEMP_MEM_BIT]= (SMU_THROTTLER_TEMP_MEM_BIT),
+   [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
+   [THROTTLER_TEMP_VR_MEM_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
+   [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
+   [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT),
+   [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT),
+   [THROTTLER_PPT0_BIT]= (SMU_THROTTLER_PPT0_BIT),
+   [THROTTLER_PPT1_BIT]= (SMU_THROTTLER_PPT1_BIT),
+   [THROTTLER_PPT2_BIT]= (SMU_THROTTLER_PPT2_BIT),
+   [THROTTLER_PPT3_BIT]= (SMU_THROTTLER_PPT3_BIT),
+   [THROTTLER_PPM_BIT] = (SMU_THROTTLER_PPM_BIT),
+   [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT),
+   [THROTTLER_APCC_BIT]= (SMU_THROTTLER_APCC_BIT),
+   [THROTTLER_VRHOT0_BIT]  = (SMU_THROTTLER_VRHOT0_BIT),
+   [THROTTLER_VRHOT1_BIT]  = (SMU_THROTTLER_VRHOT1_BIT),
+};
+
 static int arcturus_tables_init(struct smu_context *smu)
 {
struct smu_table_context *smu_table = &smu->smu_table;
@@ -237,7 +257,7 @@ static int arcturus_tables_init(struct smu_context *smu)
return -ENOMEM;
smu_table->metrics_time = 0;
 
-   smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_1);
+   smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
smu_table->gpu_metrics_table = 
kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
if (!smu_table->gpu_metrics_table) {
kfree(smu_table->metrics_table);
@@ -2275,8 +2295,8 @@ static ssize_t arcturus_get_gpu_metrics(struct 
smu_context *smu,
void **table)
 {
struct smu_table_context *smu_table = &smu->smu_table;
-   struct gpu_metrics_v1_1 *gpu_metrics =
-   (struct gpu_metrics_v1_1 *)smu_table->gpu_metrics_table;
+   struct gpu_metrics_v1_3 *gpu_metrics =
+   (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
SmuMetrics_t metrics;
int ret = 0;
 
@@ -2286,7 +2306,7 @@ static ssize_t arcturus_get_gpu_metrics(struct 
smu_context *smu,
if (ret)
return ret;
 
-   smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 1);
+   smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
 
gpu_metrics->temperature_edge = metrics.TemperatureEdge;
gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
@@ -2315,6 +2335,9 @@ static ssize_t arcturus_get_gpu_metrics(struct 
smu_context *smu,
gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
 
gpu_metrics->throttle_status = metrics.ThrottlerStatus;
+   gpu_metrics->indep_throttle_status =
+   
smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
+  
arcturus_throttler_map);
 
gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
 
@@ -2327,7 +2350,7 @@ static ssize_t arcturus_get_gpu_metrics(struct 
smu_context *smu,
 
*table = (void *)gpu_metrics;
 
-   return sizeof(struct gpu_metrics_v1_1);
+   return sizeof(struct gpu_metrics_v1_3);
 }
 
 static const struct pptable_funcs arcturus_ppt_funcs = {
-- 
2.17.1

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[PATCH v5 9/9] drm/amd/pm: Add aldebaran throttler translation

[Graham Sider]

Perform dependent to independent throttle status translation
for aldebaran.

Signed-off-by: Graham Sider 
---
 .../drm/amd/pm/swsmu/smu13/aldebaran_ppt.c| 27 +++
 1 file changed, 22 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
index 7a1abb3d6a7a..0845d4b30a0d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
@@ -191,6 +191,20 @@ static const struct cmn2asic_mapping 
aldebaran_table_map[SMU_TABLE_COUNT] = {
TAB_MAP(I2C_COMMANDS),
 };
 
+static const uint8_t aldebaran_throttler_map[] = {
+   [THROTTLER_PPT0_BIT]= (SMU_THROTTLER_PPT0_BIT),
+   [THROTTLER_PPT1_BIT]= (SMU_THROTTLER_PPT1_BIT),
+   [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT),
+   [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT),
+   [THROTTLER_TDC_HBM_BIT] = (SMU_THROTTLER_TDC_MEM_BIT),
+   [THROTTLER_TEMP_GPU_BIT]= (SMU_THROTTLER_TEMP_GPU_BIT),
+   [THROTTLER_TEMP_MEM_BIT]= (SMU_THROTTLER_TEMP_MEM_BIT),
+   [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
+   [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
+   [THROTTLER_TEMP_VR_MEM_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
+   [THROTTLER_APCC_BIT]= (SMU_THROTTLER_APCC_BIT),
+};
+
 static int aldebaran_tables_init(struct smu_context *smu)
 {
struct smu_table_context *smu_table = &smu->smu_table;
@@ -213,7 +227,7 @@ static int aldebaran_tables_init(struct smu_context *smu)
return -ENOMEM;
smu_table->metrics_time = 0;
 
-   smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_2);
+   smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
smu_table->gpu_metrics_table = 
kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
if (!smu_table->gpu_metrics_table) {
kfree(smu_table->metrics_table);
@@ -1713,8 +1727,8 @@ static ssize_t aldebaran_get_gpu_metrics(struct 
smu_context *smu,
 void **table)
 {
struct smu_table_context *smu_table = &smu->smu_table;
-   struct gpu_metrics_v1_2 *gpu_metrics =
-   (struct gpu_metrics_v1_2 *)smu_table->gpu_metrics_table;
+   struct gpu_metrics_v1_3 *gpu_metrics =
+   (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
SmuMetrics_t metrics;
int i, ret = 0;
 
@@ -1724,7 +1738,7 @@ static ssize_t aldebaran_get_gpu_metrics(struct 
smu_context *smu,
if (ret)
return ret;
 
-   smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 2);
+   smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
 
gpu_metrics->temperature_edge = metrics.TemperatureEdge;
gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
@@ -1755,6 +1769,9 @@ static ssize_t aldebaran_get_gpu_metrics(struct 
smu_context *smu,
gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
 
gpu_metrics->throttle_status = metrics.ThrottlerStatus;
+   gpu_metrics->indep_throttle_status =
+   
smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
+  
aldebaran_throttler_map);
 
gpu_metrics->current_fan_speed = 0;
 
@@ -1776,7 +1793,7 @@ static ssize_t aldebaran_get_gpu_metrics(struct 
smu_context *smu,
 
*table = (void *)gpu_metrics;
 
-   return sizeof(struct gpu_metrics_v1_2);
+   return sizeof(struct gpu_metrics_v1_3);
 }
 
 static int aldebaran_mode2_reset(struct smu_context *smu)
-- 
2.17.1

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[PATCH v5 6/9] drm/amd/pm: Add sienna cichlid throttler translation

[Graham Sider]

Perform dependent to independent throttle status translation
for sienna cichlid.

Signed-off-by: Graham Sider 
---
 .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c   | 34 ---
 1 file changed, 29 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 75acdb80c499..0e847a85d4a9 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -239,6 +239,27 @@ static struct cmn2asic_mapping 
sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_
WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,   
WORKLOAD_PPLIB_CUSTOM_BIT),
 };
 
+static const uint8_t sienna_cichlid_throttler_map[] = {
+   [THROTTLER_TEMP_EDGE_BIT]   = (SMU_THROTTLER_TEMP_EDGE_BIT),
+   [THROTTLER_TEMP_HOTSPOT_BIT]= (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
+   [THROTTLER_TEMP_MEM_BIT]= (SMU_THROTTLER_TEMP_MEM_BIT),
+   [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
+   [THROTTLER_TEMP_VR_MEM0_BIT]= (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
+   [THROTTLER_TEMP_VR_MEM1_BIT]= (SMU_THROTTLER_TEMP_VR_MEM1_BIT),
+   [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
+   [THROTTLER_TEMP_LIQUID0_BIT]= (SMU_THROTTLER_TEMP_LIQUID0_BIT),
+   [THROTTLER_TEMP_LIQUID1_BIT]= (SMU_THROTTLER_TEMP_LIQUID1_BIT),
+   [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT),
+   [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT),
+   [THROTTLER_PPT0_BIT]= (SMU_THROTTLER_PPT0_BIT),
+   [THROTTLER_PPT1_BIT]= (SMU_THROTTLER_PPT1_BIT),
+   [THROTTLER_PPT2_BIT]= (SMU_THROTTLER_PPT2_BIT),
+   [THROTTLER_PPT3_BIT]= (SMU_THROTTLER_PPT3_BIT),
+   [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT),
+   [THROTTLER_PPM_BIT] = (SMU_THROTTLER_PPM_BIT),
+   [THROTTLER_APCC_BIT]= (SMU_THROTTLER_APCC_BIT),
+};
+
 static int
 sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
  uint32_t *feature_mask, uint32_t num)
@@ -434,7 +455,7 @@ static int sienna_cichlid_tables_init(struct smu_context 
*smu)
goto err0_out;
smu_table->metrics_time = 0;
 
-   smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_1);
+   smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
smu_table->gpu_metrics_table = 
kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
if (!smu_table->gpu_metrics_table)
goto err1_out;
@@ -3617,8 +3638,8 @@ static ssize_t sienna_cichlid_get_gpu_metrics(struct 
smu_context *smu,
  void **table)
 {
struct smu_table_context *smu_table = &smu->smu_table;
-   struct gpu_metrics_v1_1 *gpu_metrics =
-   (struct gpu_metrics_v1_1 *)smu_table->gpu_metrics_table;
+   struct gpu_metrics_v1_3 *gpu_metrics =
+   (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
SmuMetricsExternal_t metrics_external;
SmuMetrics_t *metrics =
&(metrics_external.SmuMetrics);
@@ -3632,7 +3653,7 @@ static ssize_t sienna_cichlid_get_gpu_metrics(struct 
smu_context *smu,
if (ret)
return ret;
 
-   smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 1);
+   smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
 
gpu_metrics->temperature_edge = metrics->TemperatureEdge;
gpu_metrics->temperature_hotspot = metrics->TemperatureHotspot;
@@ -3667,6 +3688,9 @@ static ssize_t sienna_cichlid_get_gpu_metrics(struct 
smu_context *smu,
gpu_metrics->current_dclk1 = metrics->CurrClock[PPCLK_DCLK_1];
 
gpu_metrics->throttle_status = metrics->ThrottlerStatus;
+   gpu_metrics->indep_throttle_status =
+   
smu_cmn_get_indep_throttler_status(metrics->ThrottlerStatus,
+  
sienna_cichlid_throttler_map);
 
gpu_metrics->current_fan_speed = metrics->CurrFanSpeed;
 
@@ -3689,7 +3713,7 @@ static ssize_t sienna_cichlid_get_gpu_metrics(struct 
smu_context *smu,
 
*table = (void *)gpu_metrics;
 
-   return sizeof(struct gpu_metrics_v1_1);
+   return sizeof(struct gpu_metrics_v1_3);
 }
 
 static int sienna_cichlid_enable_mgpu_fan_boost(struct smu_context *smu)
-- 
2.17.1

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[PATCH v5 7/9] drm/amd/pm: Add vangogh throttler translation

[Graham Sider]

Perform dependent to independent throttle status translation
for vangogh.

Signed-off-by: Graham Sider 
---
 .../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c  | 38 ++-
 1 file changed, 29 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
index 77f532a49e37..589304367929 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
@@ -190,6 +190,20 @@ static struct cmn2asic_mapping 
vangogh_workload_map[PP_SMC_POWER_PROFILE_COUNT]
WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,   
WORKLOAD_PPLIB_CUSTOM_BIT),
 };
 
+static const uint8_t vangogh_throttler_map[] = {
+   [THROTTLER_STATUS_BIT_SPL]  = (SMU_THROTTLER_SPL_BIT),
+   [THROTTLER_STATUS_BIT_FPPT] = (SMU_THROTTLER_FPPT_BIT),
+   [THROTTLER_STATUS_BIT_SPPT] = (SMU_THROTTLER_SPPT_BIT),
+   [THROTTLER_STATUS_BIT_SPPT_APU] = (SMU_THROTTLER_SPPT_APU_BIT),
+   [THROTTLER_STATUS_BIT_THM_CORE] = (SMU_THROTTLER_TEMP_CORE_BIT),
+   [THROTTLER_STATUS_BIT_THM_GFX]  = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
+   [THROTTLER_STATUS_BIT_THM_SOC]  = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
+   [THROTTLER_STATUS_BIT_TDC_VDD]  = (SMU_THROTTLER_TDC_VDD_BIT),
+   [THROTTLER_STATUS_BIT_TDC_SOC]  = (SMU_THROTTLER_TDC_SOC_BIT),
+   [THROTTLER_STATUS_BIT_TDC_GFX]  = (SMU_THROTTLER_TDC_GFX_BIT),
+   [THROTTLER_STATUS_BIT_TDC_CVIP] = (SMU_THROTTLER_TDC_CVIP_BIT),
+};
+
 static int vangogh_tables_init(struct smu_context *smu)
 {
struct smu_table_context *smu_table = &smu->smu_table;
@@ -226,7 +240,7 @@ static int vangogh_tables_init(struct smu_context *smu)
goto err0_out;
smu_table->metrics_time = 0;
 
-   smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_1);
+   smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_2);
smu_table->gpu_metrics_table = 
kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
if (!smu_table->gpu_metrics_table)
goto err1_out;
@@ -1632,8 +1646,8 @@ static ssize_t vangogh_get_legacy_gpu_metrics(struct 
smu_context *smu,
  void **table)
 {
struct smu_table_context *smu_table = &smu->smu_table;
-   struct gpu_metrics_v2_1 *gpu_metrics =
-   (struct gpu_metrics_v2_1 *)smu_table->gpu_metrics_table;
+   struct gpu_metrics_v2_2 *gpu_metrics =
+   (struct gpu_metrics_v2_2 *)smu_table->gpu_metrics_table;
SmuMetrics_legacy_t metrics;
int ret = 0;
 
@@ -1641,7 +1655,7 @@ static ssize_t vangogh_get_legacy_gpu_metrics(struct 
smu_context *smu,
if (ret)
return ret;
 
-   smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 1);
+   smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 2);
 
gpu_metrics->temperature_gfx = metrics.GfxTemperature;
gpu_metrics->temperature_soc = metrics.SocTemperature;
@@ -1674,20 +1688,23 @@ static ssize_t vangogh_get_legacy_gpu_metrics(struct 
smu_context *smu,
gpu_metrics->current_l3clk[0] = metrics.L3Frequency[0];
 
gpu_metrics->throttle_status = metrics.ThrottlerStatus;
+   gpu_metrics->indep_throttle_status =
+   
smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
+  
vangogh_throttler_map);
 
gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
 
*table = (void *)gpu_metrics;
 
-   return sizeof(struct gpu_metrics_v2_1);
+   return sizeof(struct gpu_metrics_v2_2);
 }
 
 static ssize_t vangogh_get_gpu_metrics(struct smu_context *smu,
  void **table)
 {
struct smu_table_context *smu_table = &smu->smu_table;
-   struct gpu_metrics_v2_1 *gpu_metrics =
-   (struct gpu_metrics_v2_1 *)smu_table->gpu_metrics_table;
+   struct gpu_metrics_v2_2 *gpu_metrics =
+   (struct gpu_metrics_v2_2 *)smu_table->gpu_metrics_table;
SmuMetrics_t metrics;
int ret = 0;
 
@@ -1695,7 +1712,7 @@ static ssize_t vangogh_get_gpu_metrics(struct smu_context 
*smu,
if (ret)
return ret;
 
-   smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 1);
+   smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 2);
 
gpu_metrics->temperature_gfx = metrics.Current.GfxTemperature;
gpu_metrics->temperature_soc = metrics.Current.SocTemperature;
@@ -1735,12 +1752,15 @@ static ssize_t vangogh_get_gpu_metrics(struct 
smu_context *smu,
gpu_metrics->current_l3clk[0] = metrics.Current.L3Frequency[0];
 
gpu_metrics->throttle_status = metrics.Current.ThrottlerStatus;
+   gpu_metrics->indep_throttle_status =
+   
smu_cmn_get_indep_throttler_status(metrics.Current.ThrottlerStatus,
+  
vangogh_throttler

[PATCH v5 8/9] drm/amd/pm: Add renoir throttler translation

[Graham Sider]

Perform dependent to independent throttle status translation
for renoir.

Signed-off-by: Graham Sider 
---
 .../gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c   | 29 +++
 1 file changed, 24 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
index 1c399c4ab4dc..6af67d372926 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
@@ -128,6 +128,22 @@ static struct cmn2asic_mapping 
renoir_workload_map[PP_SMC_POWER_PROFILE_COUNT] =
WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,   
WORKLOAD_PPLIB_CUSTOM_BIT),
 };
 
+static const uint8_t renoir_throttler_map[] = {
+   [THROTTLER_STATUS_BIT_SPL]  = (SMU_THROTTLER_SPL_BIT),
+   [THROTTLER_STATUS_BIT_FPPT] = (SMU_THROTTLER_FPPT_BIT),
+   [THROTTLER_STATUS_BIT_SPPT] = (SMU_THROTTLER_SPPT_BIT),
+   [THROTTLER_STATUS_BIT_SPPT_APU] = (SMU_THROTTLER_SPPT_APU_BIT),
+   [THROTTLER_STATUS_BIT_THM_CORE] = (SMU_THROTTLER_TEMP_CORE_BIT),
+   [THROTTLER_STATUS_BIT_THM_GFX]  = 
(SMU_THROTTLER_TEMP_VR_GFX_BIT),
+   [THROTTLER_STATUS_BIT_THM_SOC]  = 
(SMU_THROTTLER_TEMP_VR_SOC_BIT),
+   [THROTTLER_STATUS_BIT_TDC_VDD]  = (SMU_THROTTLER_TDC_VDD_BIT),
+   [THROTTLER_STATUS_BIT_TDC_SOC]  = (SMU_THROTTLER_TDC_SOC_BIT),
+   [THROTTLER_STATUS_BIT_PROCHOT_CPU]  = 
(SMU_THROTTLER_PROCHOT_CPU_BIT),
+   [THROTTLER_STATUS_BIT_PROCHOT_GFX]  = 
(SMU_THROTTLER_PROCHOT_GFX_BIT),
+   [THROTTLER_STATUS_BIT_EDC_CPU]  = (SMU_THROTTLER_EDC_CPU_BIT),
+   [THROTTLER_STATUS_BIT_EDC_GFX]  = (SMU_THROTTLER_EDC_GFX_BIT),
+};
+
 static int renoir_init_smc_tables(struct smu_context *smu)
 {
struct smu_table_context *smu_table = &smu->smu_table;
@@ -153,7 +169,7 @@ static int renoir_init_smc_tables(struct smu_context *smu)
if (!smu_table->watermarks_table)
goto err2_out;
 
-   smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_1);
+   smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_2);
smu_table->gpu_metrics_table = 
kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
if (!smu_table->gpu_metrics_table)
goto err3_out;
@@ -1264,8 +1280,8 @@ static ssize_t renoir_get_gpu_metrics(struct smu_context 
*smu,
  void **table)
 {
struct smu_table_context *smu_table = &smu->smu_table;
-   struct gpu_metrics_v2_1 *gpu_metrics =
-   (struct gpu_metrics_v2_1 *)smu_table->gpu_metrics_table;
+   struct gpu_metrics_v2_2 *gpu_metrics =
+   (struct gpu_metrics_v2_2 *)smu_table->gpu_metrics_table;
SmuMetrics_t metrics;
int ret = 0;
 
@@ -1273,7 +1289,7 @@ static ssize_t renoir_get_gpu_metrics(struct smu_context 
*smu,
if (ret)
return ret;
 
-   smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 1);
+   smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 2);
 
gpu_metrics->temperature_gfx = metrics.GfxTemperature;
gpu_metrics->temperature_soc = metrics.SocTemperature;
@@ -1311,6 +1327,9 @@ static ssize_t renoir_get_gpu_metrics(struct smu_context 
*smu,
gpu_metrics->current_l3clk[1] = metrics.L3Frequency[1];
 
gpu_metrics->throttle_status = metrics.ThrottlerStatus;
+   gpu_metrics->indep_throttle_status =
+   smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
+  renoir_throttler_map);
 
gpu_metrics->fan_pwm = metrics.FanPwm;
 
@@ -1318,7 +1337,7 @@ static ssize_t renoir_get_gpu_metrics(struct smu_context 
*smu,
 
*table = (void *)gpu_metrics;
 
-   return sizeof(struct gpu_metrics_v2_1);
+   return sizeof(struct gpu_metrics_v2_2);
 }
 
 static int renoir_gfx_state_change_set(struct smu_context *smu, uint32_t state)
-- 
2.17.1

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RE: [PATCH 4/5] drm/amdgpu: add psp microcode init for arcturus and aldebaran sriov vf

[Zhang, Hawking]

[AMD Official Use Only]

You can call psp_init_ta_microcode directly in sriov vf case so you don't need 
to initialize unnecessary psp firmware structures. 

Regards,
Hawking
-Original Message-
From: amd-gfx  On Behalf Of Luo, Zhigang
Sent: Thursday, June 3, 2021 23:32
To: Liu, Shaoyun ; amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH 4/5] drm/amdgpu: add psp microcode init for arcturus and 
aldebaran sriov vf

Yeah, it will also init psp sos and asd mircrocode. But I think it's harmless.

Thanks,
Zhigang

-Original Message-
From: Liu, Shaoyun  
Sent: June 3, 2021 11:13 AM
To: Luo, Zhigang ; amd-gfx@lists.freedesktop.org
Cc: Luo, Zhigang 
Subject: RE: [PATCH 4/5] drm/amdgpu: add psp microcode init for arcturus and 
aldebaran sriov vf

[AMD Official Use Only]

This one  doesn't looks apply to  XGMI TA  only , it's for whole PSP init , can 
 you double check it ? 


Shaoyun.liu

-Original Message-
From: amd-gfx  On Behalf Of Zhigang Luo
Sent: Thursday, June 3, 2021 10:13 AM
To: amd-gfx@lists.freedesktop.org
Cc: Luo, Zhigang 
Subject: [PATCH 4/5] drm/amdgpu: add psp microcode init for arcturus and 
aldebaran sriov vf

need to load xgmi ta for arcturus and aldebaran sriov vf.

Signed-off-by: Zhigang Luo 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 55378c6b9722..6bd7e39c3e75 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -170,7 +170,8 @@ static int psp_sw_init(void *handle)
struct psp_context *psp = &adev->psp;
int ret;
 
-   if (!amdgpu_sriov_vf(adev)) {
+   if ((adev->asic_type == CHIP_ARCTURUS) ||
+   (adev->asic_type == CHIP_ALDEBARAN) || (!amdgpu_sriov_vf(adev))) {
ret = psp_init_microcode(psp);
if (ret) {
DRM_ERROR("Failed to load psp firmware!\n");
-- 
2.17.1

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RE: [PATCH 4/5] drm/amdgpu: add psp microcode init for arcturus and aldebaran sriov vf

[Luo, Zhigang]

[Public]

Okay. I will update the change as you suggested.

Thanks,
Zhigang

-Original Message-
From: Zhang, Hawking 
Sent: June 7, 2021 9:52 AM
To: Luo, Zhigang ; Liu, Shaoyun ; 
amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH 4/5] drm/amdgpu: add psp microcode init for arcturus and 
aldebaran sriov vf

[AMD Official Use Only]

You can call psp_init_ta_microcode directly in sriov vf case so you don't need 
to initialize unnecessary psp firmware structures.

Regards,
Hawking
-Original Message-
From: amd-gfx  On Behalf Of Luo, Zhigang
Sent: Thursday, June 3, 2021 23:32
To: Liu, Shaoyun ; amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH 4/5] drm/amdgpu: add psp microcode init for arcturus and 
aldebaran sriov vf

Yeah, it will also init psp sos and asd mircrocode. But I think it's harmless.

Thanks,
Zhigang

-Original Message-
From: Liu, Shaoyun 
Sent: June 3, 2021 11:13 AM
To: Luo, Zhigang ; amd-gfx@lists.freedesktop.org
Cc: Luo, Zhigang 
Subject: RE: [PATCH 4/5] drm/amdgpu: add psp microcode init for arcturus and 
aldebaran sriov vf

[AMD Official Use Only]

This one  doesn't looks apply to  XGMI TA  only , it's for whole PSP init , can 
 you double check it ?


Shaoyun.liu

-Original Message-
From: amd-gfx  On Behalf Of Zhigang Luo
Sent: Thursday, June 3, 2021 10:13 AM
To: amd-gfx@lists.freedesktop.org
Cc: Luo, Zhigang 
Subject: [PATCH 4/5] drm/amdgpu: add psp microcode init for arcturus and 
aldebaran sriov vf

need to load xgmi ta for arcturus and aldebaran sriov vf.

Signed-off-by: Zhigang Luo 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 55378c6b9722..6bd7e39c3e75 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -170,7 +170,8 @@ static int psp_sw_init(void *handle)
struct psp_context *psp = &adev->psp;
int ret;

-   if (!amdgpu_sriov_vf(adev)) {
+   if ((adev->asic_type == CHIP_ARCTURUS) ||
+   (adev->asic_type == CHIP_ALDEBARAN) || (!amdgpu_sriov_vf(adev))) {
ret = psp_init_microcode(psp);
if (ret) {
DRM_ERROR("Failed to load psp firmware!\n");
--
2.17.1

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[PATCH] drm/amdgpu: Fix warning of Function parameter or member not described

[Eric Huang]

Add the parameter table_freed description on function description.

Signed-off-by: Eric Huang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index b4f189ab672e..9db1b64d16d9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1823,6 +1823,7 @@ void amdgpu_vm_get_memory(struct amdgpu_vm *vm, uint64_t 
*vram_mem,
  * @adev: amdgpu_device pointer
  * @bo_va: requested BO and VM object
  * @clear: if true clear the entries
+ * @table_freed: return true if page table is freed
  *
  * Fill in the page table entries for @bo_va.
  *
-- 
2.25.1

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[PATCH] drm/amdgpu: Use PSP to program IH_RB_CNTL_RING1/2 on SRIOV

[Rohit Khaire]

This is similar to IH_RB_CNTL programming in
navi10_ih_toggle_ring_interrupts

Signed-off-by: Rohit Khaire 
---
 drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 20 ++--
 1 file changed, 18 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c 
b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
index eac564e8dd52..e41188c04846 100644
--- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
@@ -120,11 +120,27 @@ force_update_wptr_for_self_int(struct amdgpu_device *adev,
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
   RB_USED_INT_THRESHOLD, threshold);
 
-   WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
+   if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
+   if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 
ih_rb_cntl)) {
+   DRM_ERROR("PSP program IH_RB_CNTL_RING1 failed!\n");
+   return;
+   }
+   } else {
+   WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
+   }
+
ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,
   RB_USED_INT_THRESHOLD, threshold);
-   WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
+   if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
+   if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 
ih_rb_cntl)) {
+   DRM_ERROR("PSP program IH_RB_CNTL_RING2 failed!\n");
+   return;
+   }
+   } else {
+   WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
+   }
+
WREG32_SOC15(OSSSYS, 0, mmIH_CNTL2, ih_cntl);
 }
 
-- 
2.17.1

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Re: [PATCH 0/7] libdrm tests for hot-unplug fe goature

[Andrey Grodzovsky]

Hey, MR created at 
https://gitlab.freedesktop.org/mesa/drm/-/merge_requests/172, please 
help review.


Andrey

On 2021-06-03 10:26 p.m., Alex Deucher wrote:

Code review happens on gitlab now for libdrm.

Alex

On Thu, Jun 3, 2021 at 6:02 PM Grodzovsky, Andrey
 wrote:

Is libdrm on gitlab ? I wasn't aware of this. I assumed code reviews still go 
through dri-devel.

Andrey


From: Alex Deucher 
Sent: 03 June 2021 17:20
To: Grodzovsky, Andrey 
Cc: Maling list - DRI developers ; amd-gfx list 
; Deucher, Alexander ; Christian 
König 
Subject: Re: [PATCH 0/7] libdrm tests for hot-unplug feature

Please open a gitlab MR for these.

Alex

On Tue, Jun 1, 2021 at 4:17 PM Andrey Grodzovsky
 wrote:

Adding some tests to acompany the recently added hot-unplug
feature. For now the test suite is disabled until the feature
propagates from drm-misc-next to drm-next.

Andrey Grodzovsky (7):
   tests/amdgpu: Fix valgrind warning
   xf86drm: Add function to retrieve char device path
   test/amdgpu: Add helper functions for hot unplug
   test/amdgpu/hotunplug: Add test suite for GPU unplug
   test/amdgpu/hotunplug: Add basic test
   tests/amdgpu/hotunplug: Add unplug with cs test.
   tests/amdgpu/hotunplug: Add hotunplug with exported bo test

  tests/amdgpu/amdgpu_test.c |  42 +++-
  tests/amdgpu/amdgpu_test.h |  26 +++
  tests/amdgpu/basic_tests.c |   5 +-
  tests/amdgpu/hotunplug_tests.c | 357 +
  tests/amdgpu/meson.build   |   1 +
  xf86drm.c  |  23 +++
  xf86drm.h  |   1 +
  7 files changed, 450 insertions(+), 5 deletions(-)
  create mode 100644 tests/amdgpu/hotunplug_tests.c

--
2.25.1

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Re: [PATCH] drm/amdgpu: Use PSP to program IH_RB_CNTL_RING1/2 on SRIOV

[Christian König]

Why are the ring 1&2 enabled on SRIOV in the first place?

Christian.

Am 07.06.21 um 16:23 schrieb Rohit Khaire:

This is similar to IH_RB_CNTL programming in
navi10_ih_toggle_ring_interrupts

Signed-off-by: Rohit Khaire 
---
  drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 20 ++--
  1 file changed, 18 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c 
b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
index eac564e8dd52..e41188c04846 100644
--- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
@@ -120,11 +120,27 @@ force_update_wptr_for_self_int(struct amdgpu_device *adev,
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
   RB_USED_INT_THRESHOLD, threshold);
  
-	WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);

+   if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
+   if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 
ih_rb_cntl)) {
+   DRM_ERROR("PSP program IH_RB_CNTL_RING1 failed!\n");
+   return;
+   }
+   } else {
+   WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
+   }
+
ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,
   RB_USED_INT_THRESHOLD, threshold);
-   WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
+   if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
+   if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 
ih_rb_cntl)) {
+   DRM_ERROR("PSP program IH_RB_CNTL_RING2 failed!\n");
+   return;
+   }
+   } else {
+   WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
+   }
+
WREG32_SOC15(OSSSYS, 0, mmIH_CNTL2, ih_cntl);
  }
  


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Re: [PATCH v5 7/9] drm/amd/pm: Add vangogh throttler translation

[Lazar, Lijo]

On 6/7/2021 7:14 PM, Graham Sider wrote:

Perform dependent to independent throttle status translation
for vangogh.

Signed-off-by: Graham Sider 
---
  .../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c  | 38 ++-
  1 file changed, 29 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
index 77f532a49e37..589304367929 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
@@ -190,6 +190,20 @@ static struct cmn2asic_mapping 
vangogh_workload_map[PP_SMC_POWER_PROFILE_COUNT]
WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,   
WORKLOAD_PPLIB_CUSTOM_BIT),
  };
  
+static const uint8_t vangogh_throttler_map[] = {

+   [THROTTLER_STATUS_BIT_SPL]  = (SMU_THROTTLER_SPL_BIT),
+   [THROTTLER_STATUS_BIT_FPPT] = (SMU_THROTTLER_FPPT_BIT),
+   [THROTTLER_STATUS_BIT_SPPT] = (SMU_THROTTLER_SPPT_BIT),
+   [THROTTLER_STATUS_BIT_SPPT_APU] = (SMU_THROTTLER_SPPT_APU_BIT),
+   [THROTTLER_STATUS_BIT_THM_CORE] = (SMU_THROTTLER_TEMP_CORE_BIT),
+   [THROTTLER_STATUS_BIT_THM_GFX]  = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
+   [THROTTLER_STATUS_BIT_THM_SOC]  = (SMU_THROTTLER_TEMP_VR_SOC_BIT),


Above two mappings don't look correct. They essentially mean throttling 
due to GFX/SOC domain temperatures in APU exceeding their limits, not 
the VR temperatures. Except those mappings, rest of the patch series 
looks good to me.


Thanks,
Lijo


+   [THROTTLER_STATUS_BIT_TDC_VDD]  = (SMU_THROTTLER_TDC_VDD_BIT),
+   [THROTTLER_STATUS_BIT_TDC_SOC]  = (SMU_THROTTLER_TDC_SOC_BIT),
+   [THROTTLER_STATUS_BIT_TDC_GFX]  = (SMU_THROTTLER_TDC_GFX_BIT),
+   [THROTTLER_STATUS_BIT_TDC_CVIP] = (SMU_THROTTLER_TDC_CVIP_BIT),
+};
+
  static int vangogh_tables_init(struct smu_context *smu)
  {
struct smu_table_context *smu_table = &smu->smu_table;
@@ -226,7 +240,7 @@ static int vangogh_tables_init(struct smu_context *smu)
goto err0_out;
smu_table->metrics_time = 0;
  
-	smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_1);

+   smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_2);
smu_table->gpu_metrics_table = 
kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
if (!smu_table->gpu_metrics_table)
goto err1_out;
@@ -1632,8 +1646,8 @@ static ssize_t vangogh_get_legacy_gpu_metrics(struct 
smu_context *smu,
  void **table)
  {
struct smu_table_context *smu_table = &smu->smu_table;
-   struct gpu_metrics_v2_1 *gpu_metrics =
-   (struct gpu_metrics_v2_1 *)smu_table->gpu_metrics_table;
+   struct gpu_metrics_v2_2 *gpu_metrics =
+   (struct gpu_metrics_v2_2 *)smu_table->gpu_metrics_table;
SmuMetrics_legacy_t metrics;
int ret = 0;
  
@@ -1641,7 +1655,7 @@ static ssize_t vangogh_get_legacy_gpu_metrics(struct smu_context *smu,

if (ret)
return ret;
  
-	smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 1);

+   smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 2);
  
  	gpu_metrics->temperature_gfx = metrics.GfxTemperature;

gpu_metrics->temperature_soc = metrics.SocTemperature;
@@ -1674,20 +1688,23 @@ static ssize_t vangogh_get_legacy_gpu_metrics(struct 
smu_context *smu,
gpu_metrics->current_l3clk[0] = metrics.L3Frequency[0];
  
  	gpu_metrics->throttle_status = metrics.ThrottlerStatus;

+   gpu_metrics->indep_throttle_status =
+   
smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
+  
vangogh_throttler_map);
  
  	gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
  
  	*table = (void *)gpu_metrics;
  
-	return sizeof(struct gpu_metrics_v2_1);

+   return sizeof(struct gpu_metrics_v2_2);
  }
  
  static ssize_t vangogh_get_gpu_metrics(struct smu_context *smu,

  void **table)
  {
struct smu_table_context *smu_table = &smu->smu_table;
-   struct gpu_metrics_v2_1 *gpu_metrics =
-   (struct gpu_metrics_v2_1 *)smu_table->gpu_metrics_table;
+   struct gpu_metrics_v2_2 *gpu_metrics =
+   (struct gpu_metrics_v2_2 *)smu_table->gpu_metrics_table;
SmuMetrics_t metrics;
int ret = 0;
  
@@ -1695,7 +1712,7 @@ static ssize_t vangogh_get_gpu_metrics(struct smu_context *smu,

if (ret)
return ret;
  
-	smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 1);

+   smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 2);
  
  	gpu_metrics->temperature_gfx = metrics.Current.GfxTemperature;

gpu_metrics->temperature_soc = metrics.Current.SocTemperature;
@@ -1735,12 +1752,15 @@ static ssize_t vangogh_get_gpu_metrics(struct 
smu_context *smu,
gpu_metrics->current_l3clk[0] = metrics.Current.L3Frequency[0];
  
  	gpu_

RE: [PATCH v5 7/9] drm/amd/pm: Add vangogh throttler translation

[Sider, Graham]

Great, thanks for all the feedback Lijo. Out of the new bit definitions in 
amdgpu_smu.h are there any that currently exist that are more applicable for 
these mappings? *_THM_GFX and *_THM_SOC only exist in VanGogh and Renoir. With 
the expansion of the MEM and LIQUID bits there is not enough room in the 
temperature field to add two new definitions.

Best,
Graham

-Original Message-
From: Lazar, Lijo  
Sent: Monday, June 7, 2021 10:35 AM
To: Sider, Graham ; amd-gfx@lists.freedesktop.org
Cc: Kasiviswanathan, Harish ; Sakhnovitch, 
Elena (Elen) 
Subject: Re: [PATCH v5 7/9] drm/amd/pm: Add vangogh throttler translation



On 6/7/2021 7:14 PM, Graham Sider wrote:
> Perform dependent to independent throttle status translation for 
> vangogh.
> 
> Signed-off-by: Graham Sider 
> ---
>   .../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c  | 38 ++-
>   1 file changed, 29 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c 
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> index 77f532a49e37..589304367929 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> @@ -190,6 +190,20 @@ static struct cmn2asic_mapping 
> vangogh_workload_map[PP_SMC_POWER_PROFILE_COUNT]
>   WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,   
> WORKLOAD_PPLIB_CUSTOM_BIT),
>   };
>   
> +static const uint8_t vangogh_throttler_map[] = {
> + [THROTTLER_STATUS_BIT_SPL]  = (SMU_THROTTLER_SPL_BIT),
> + [THROTTLER_STATUS_BIT_FPPT] = (SMU_THROTTLER_FPPT_BIT),
> + [THROTTLER_STATUS_BIT_SPPT] = (SMU_THROTTLER_SPPT_BIT),
> + [THROTTLER_STATUS_BIT_SPPT_APU] = (SMU_THROTTLER_SPPT_APU_BIT),
> + [THROTTLER_STATUS_BIT_THM_CORE] = (SMU_THROTTLER_TEMP_CORE_BIT),
> + [THROTTLER_STATUS_BIT_THM_GFX]  = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
> + [THROTTLER_STATUS_BIT_THM_SOC]  = (SMU_THROTTLER_TEMP_VR_SOC_BIT),

Above two mappings don't look correct. They essentially mean throttling due to 
GFX/SOC domain temperatures in APU exceeding their limits, not the VR 
temperatures. Except those mappings, rest of the patch series looks good to me.

Thanks,
Lijo

> + [THROTTLER_STATUS_BIT_TDC_VDD]  = (SMU_THROTTLER_TDC_VDD_BIT),
> + [THROTTLER_STATUS_BIT_TDC_SOC]  = (SMU_THROTTLER_TDC_SOC_BIT),
> + [THROTTLER_STATUS_BIT_TDC_GFX]  = (SMU_THROTTLER_TDC_GFX_BIT),
> + [THROTTLER_STATUS_BIT_TDC_CVIP] = (SMU_THROTTLER_TDC_CVIP_BIT),
> +};
> +
>   static int vangogh_tables_init(struct smu_context *smu)
>   {
>   struct smu_table_context *smu_table = &smu->smu_table; @@ -226,7 
> +240,7 @@ static int vangogh_tables_init(struct smu_context *smu)
>   goto err0_out;
>   smu_table->metrics_time = 0;
>   
> - smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_1);
> + smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_2);
>   smu_table->gpu_metrics_table = 
> kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
>   if (!smu_table->gpu_metrics_table)
>   goto err1_out;
> @@ -1632,8 +1646,8 @@ static ssize_t vangogh_get_legacy_gpu_metrics(struct 
> smu_context *smu,
> void **table)
>   {
>   struct smu_table_context *smu_table = &smu->smu_table;
> - struct gpu_metrics_v2_1 *gpu_metrics =
> - (struct gpu_metrics_v2_1 *)smu_table->gpu_metrics_table;
> + struct gpu_metrics_v2_2 *gpu_metrics =
> + (struct gpu_metrics_v2_2 *)smu_table->gpu_metrics_table;
>   SmuMetrics_legacy_t metrics;
>   int ret = 0;
>   
> @@ -1641,7 +1655,7 @@ static ssize_t vangogh_get_legacy_gpu_metrics(struct 
> smu_context *smu,
>   if (ret)
>   return ret;
>   
> - smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 1);
> + smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 2);
>   
>   gpu_metrics->temperature_gfx = metrics.GfxTemperature;
>   gpu_metrics->temperature_soc = metrics.SocTemperature; @@ -1674,20 
> +1688,23 @@ static ssize_t vangogh_get_legacy_gpu_metrics(struct smu_context 
> *smu,
>   gpu_metrics->current_l3clk[0] = metrics.L3Frequency[0];
>   
>   gpu_metrics->throttle_status = metrics.ThrottlerStatus;
> + gpu_metrics->indep_throttle_status =
> + 
> smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
> +
> vangogh_throttler_map);
>   
>   gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
>   
>   *table = (void *)gpu_metrics;
>   
> - return sizeof(struct gpu_metrics_v2_1);
> + return sizeof(struct gpu_metrics_v2_2);
>   }
>   
>   static ssize_t vangogh_get_gpu_metrics(struct smu_context *smu,
> void **table)
>   {
>   struct smu_table_context *smu_table = &smu->smu_table;
> - struct gpu_metrics_v2_1 *gpu_metrics =
> - (struct gpu_metrics_v2_1 *)smu_tabl

Re: [PATCH] drm/amd/pm: fix warning reported by kernel test robot

[Deucher, Alexander]

[Public]

Acked-by: Alex Deucher 

From: amd-gfx  on behalf of Xiaomeng Hou 

Sent: Monday, June 7, 2021 8:45 AM
To: amd-gfx@lists.freedesktop.org 
Cc: Huang, Ray ; Hou, Xiaomeng (Matthew) 
; Wang, Kevin(Yang) 
Subject: [PATCH] drm/amd/pm: fix warning reported by kernel test robot

Kernel test robot throws warning ->

>> drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/yellow_carp_ppt.c:483:2:
   warning: variable 'member_type' is used uninitialized whenever switch
   default is taken [-Wsometimes-uninitialized]
   default:
   ^~~
   drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/yellow_carp_ppt.c:487:47:
   note: uninitialized use occurs here
   return yellow_carp_get_smu_metrics_data(smu, member_type, value);
   ^~~
   drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/yellow_carp_ppt.c:465:2:
   note: variable 'member_type' is declared here
   MetricsMember_t member_type;
   ^
   1 warning generated.

Fix this warning by return errno when the clk type is unsupported.

Signed-off-by: Xiaomeng Hou 
Reported-by: kernel test robot 
---
 drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
index 031c49fb4582..0cd7902d5172 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
@@ -728,7 +728,7 @@ static int yellow_carp_get_current_clk_freq(struct 
smu_context *smu,
 return smu_cmn_send_smc_msg_with_param(smu,
 SMU_MSG_GetFclkFrequency, 0, value);
 default:
-   break;
+   return -EINVAL;
 }

 return yellow_carp_get_smu_metrics_data(smu, member_type, value);
--
2.17.1

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RE: [PATCH] drm/amdgpu: Use PSP to program IH_RB_CNTL_RING1/2 on SRIOV

[Khaire, Rohit]

[AMD Public Use]

We don't need RING1 and RING2 functionality for SRIOV afaik.

But looking at the description of the original commit message it affects RING0 
too?

" drm/amdgpu: add timeout flush mechanism to update wptr for self interrupt (v2)

outstanding log reaches threshold will trigger IH ring1/2's wptr
reported, that will avoid generating interrupts to ring0 too frequent.
But if ring1/2's wptr hasn't been increased for a long time, the outstanding log
can't reach threshold so that driver can't get latest wptr info and
miss some interrupts."

Rohit

-Original Message-
From: Koenig, Christian  
Sent: June 7, 2021 10:31 AM
To: Khaire, Rohit ; amd-gfx@lists.freedesktop.org; 
Deucher, Alexander ; Zhang, Hawking 
; Deng, Emily ; Liu, Monk 
; Zhou, Peng Ju ; Chen, Horace 

Cc: Ming, Davis 
Subject: Re: [PATCH] drm/amdgpu: Use PSP to program IH_RB_CNTL_RING1/2 on SRIOV

Why are the ring 1&2 enabled on SRIOV in the first place?

Christian.

Am 07.06.21 um 16:23 schrieb Rohit Khaire:
> This is similar to IH_RB_CNTL programming in 
> navi10_ih_toggle_ring_interrupts
>
> Signed-off-by: Rohit Khaire 
> ---
>   drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 20 ++--
>   1 file changed, 18 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c 
> b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> index eac564e8dd52..e41188c04846 100644
> --- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> @@ -120,11 +120,27 @@ force_update_wptr_for_self_int(struct amdgpu_device 
> *adev,
>   ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
>  RB_USED_INT_THRESHOLD, threshold);
>   
> - WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
> + if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
> + if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 
> ih_rb_cntl)) {
> + DRM_ERROR("PSP program IH_RB_CNTL_RING1 failed!\n");
> + return;
> + }
> + } else {
> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
> + }
> +
>   ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
>   ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,
>  RB_USED_INT_THRESHOLD, threshold);
> - WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
> + if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
> + if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 
> ih_rb_cntl)) {
> + DRM_ERROR("PSP program IH_RB_CNTL_RING2 failed!\n");
> + return;
> + }
> + } else {
> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
> + }
> +
>   WREG32_SOC15(OSSSYS, 0, mmIH_CNTL2, ih_cntl);
>   }
>   
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Re: [PATCH] drm/amdgpu: Use PSP to program IH_RB_CNTL_RING1/2 on SRIOV

[Christian König]

Do you have the hash for this commit?

Thanks,
Christian.

Am 07.06.21 um 17:30 schrieb Khaire, Rohit:

[AMD Public Use]

We don't need RING1 and RING2 functionality for SRIOV afaik.

But looking at the description of the original commit message it affects RING0 
too?

" drm/amdgpu: add timeout flush mechanism to update wptr for self interrupt (v2)

outstanding log reaches threshold will trigger IH ring1/2's wptr
reported, that will avoid generating interrupts to ring0 too frequent.
But if ring1/2's wptr hasn't been increased for a long time, the outstanding log
can't reach threshold so that driver can't get latest wptr info and
miss some interrupts."

Rohit

-Original Message-
From: Koenig, Christian 
Sent: June 7, 2021 10:31 AM
To: Khaire, Rohit ; amd-gfx@lists.freedesktop.org; Deucher, Alexander 
; Zhang, Hawking ; Deng, Emily ; 
Liu, Monk ; Zhou, Peng Ju ; Chen, Horace 
Cc: Ming, Davis 
Subject: Re: [PATCH] drm/amdgpu: Use PSP to program IH_RB_CNTL_RING1/2 on SRIOV

Why are the ring 1&2 enabled on SRIOV in the first place?

Christian.

Am 07.06.21 um 16:23 schrieb Rohit Khaire:

This is similar to IH_RB_CNTL programming in
navi10_ih_toggle_ring_interrupts

Signed-off-by: Rohit Khaire 
---
   drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 20 ++--
   1 file changed, 18 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
index eac564e8dd52..e41188c04846 100644
--- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
@@ -120,11 +120,27 @@ force_update_wptr_for_self_int(struct amdgpu_device *adev,
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
   RB_USED_INT_THRESHOLD, threshold);
   
-	WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);

+   if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
+   if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 
ih_rb_cntl)) {
+   DRM_ERROR("PSP program IH_RB_CNTL_RING1 failed!\n");
+   return;
+   }
+   } else {
+   WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
+   }
+
ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,
   RB_USED_INT_THRESHOLD, threshold);
-   WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
+   if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
+   if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 
ih_rb_cntl)) {
+   DRM_ERROR("PSP program IH_RB_CNTL_RING2 failed!\n");
+   return;
+   }
+   } else {
+   WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
+   }
+
WREG32_SOC15(OSSSYS, 0, mmIH_CNTL2, ih_cntl);
   }
   


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RE: [PATCH] drm/amdgpu: Use PSP to program IH_RB_CNTL_RING1/2 on SRIOV

[Khaire, Rohit]

[AMD Public Use]

The hash is 5ea6f9c

Rohit

-Original Message-
From: Koenig, Christian  
Sent: June 7, 2021 11:58 AM
To: Khaire, Rohit ; amd-gfx@lists.freedesktop.org; 
Deucher, Alexander ; Zhang, Hawking 
; Deng, Emily ; Liu, Monk 
; Zhou, Peng Ju ; Chen, Horace 

Cc: Ming, Davis 
Subject: Re: [PATCH] drm/amdgpu: Use PSP to program IH_RB_CNTL_RING1/2 on SRIOV

Do you have the hash for this commit?

Thanks,
Christian.

Am 07.06.21 um 17:30 schrieb Khaire, Rohit:
> [AMD Public Use]
>
> We don't need RING1 and RING2 functionality for SRIOV afaik.
>
> But looking at the description of the original commit message it affects 
> RING0 too?
>
> " drm/amdgpu: add timeout flush mechanism to update wptr for self 
> interrupt (v2)
>
> outstanding log reaches threshold will trigger IH ring1/2's wptr 
> reported, that will avoid generating interrupts to ring0 too frequent.
> But if ring1/2's wptr hasn't been increased for a long time, the 
> outstanding log can't reach threshold so that driver can't get latest 
> wptr info and miss some interrupts."
>
> Rohit
>
> -Original Message-
> From: Koenig, Christian 
> Sent: June 7, 2021 10:31 AM
> To: Khaire, Rohit ; 
> amd-gfx@lists.freedesktop.org; Deucher, Alexander 
> ; Zhang, Hawking ; 
> Deng, Emily ; Liu, Monk ; Zhou, 
> Peng Ju ; Chen, Horace 
> Cc: Ming, Davis 
> Subject: Re: [PATCH] drm/amdgpu: Use PSP to program IH_RB_CNTL_RING1/2 
> on SRIOV
>
> Why are the ring 1&2 enabled on SRIOV in the first place?
>
> Christian.
>
> Am 07.06.21 um 16:23 schrieb Rohit Khaire:
>> This is similar to IH_RB_CNTL programming in 
>> navi10_ih_toggle_ring_interrupts
>>
>> Signed-off-by: Rohit Khaire 
>> ---
>>drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 20 ++--
>>1 file changed, 18 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
>> b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
>> index eac564e8dd52..e41188c04846 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
>> @@ -120,11 +120,27 @@ force_update_wptr_for_self_int(struct amdgpu_device 
>> *adev,
>>  ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
>> RB_USED_INT_THRESHOLD, threshold);
>>
>> -WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
>> +if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
>> +if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 
>> ih_rb_cntl)) {
>> +DRM_ERROR("PSP program IH_RB_CNTL_RING1 failed!\n");
>> +return;
>> +}
>> +} else {
>> +WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
>> +}
>> +
>>  ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
>>  ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,
>> RB_USED_INT_THRESHOLD, threshold);
>> -WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
>> +if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
>> +if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 
>> ih_rb_cntl)) {
>> +DRM_ERROR("PSP program IH_RB_CNTL_RING2 failed!\n");
>> +return;
>> +}
>> +} else {
>> +WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
>> +}
>> +
>>  WREG32_SOC15(OSSSYS, 0, mmIH_CNTL2, ih_cntl);
>>}
>>
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Re: [PATCH] drm/amdgpu: Use PSP to program IH_RB_CNTL_RING1/2 on SRIOV

[Christian König]

That's a workaround for bare metal and as far as I know doesn't apply to 
SRIOV.


We only need the additional IH rings for page fault handling or log 
handling and as far as I know that is incompatible with SRIOV for the 
moment. But Felix might have some more updates on this.


So as long as we don't support that under SRIOV we don't need this patch 
either.


Christian.

Am 07.06.21 um 17:59 schrieb Khaire, Rohit:

[AMD Public Use]

The hash is 5ea6f9c

Rohit

-Original Message-
From: Koenig, Christian 
Sent: June 7, 2021 11:58 AM
To: Khaire, Rohit ; amd-gfx@lists.freedesktop.org; Deucher, Alexander 
; Zhang, Hawking ; Deng, Emily ; 
Liu, Monk ; Zhou, Peng Ju ; Chen, Horace 
Cc: Ming, Davis 
Subject: Re: [PATCH] drm/amdgpu: Use PSP to program IH_RB_CNTL_RING1/2 on SRIOV

Do you have the hash for this commit?

Thanks,
Christian.

Am 07.06.21 um 17:30 schrieb Khaire, Rohit:

[AMD Public Use]

We don't need RING1 and RING2 functionality for SRIOV afaik.

But looking at the description of the original commit message it affects RING0 
too?

" drm/amdgpu: add timeout flush mechanism to update wptr for self
interrupt (v2)

outstanding log reaches threshold will trigger IH ring1/2's wptr
reported, that will avoid generating interrupts to ring0 too frequent.
But if ring1/2's wptr hasn't been increased for a long time, the
outstanding log can't reach threshold so that driver can't get latest
wptr info and miss some interrupts."

Rohit

-Original Message-
From: Koenig, Christian 
Sent: June 7, 2021 10:31 AM
To: Khaire, Rohit ;
amd-gfx@lists.freedesktop.org; Deucher, Alexander
; Zhang, Hawking ;
Deng, Emily ; Liu, Monk ; Zhou,
Peng Ju ; Chen, Horace 
Cc: Ming, Davis 
Subject: Re: [PATCH] drm/amdgpu: Use PSP to program IH_RB_CNTL_RING1/2
on SRIOV

Why are the ring 1&2 enabled on SRIOV in the first place?

Christian.

Am 07.06.21 um 16:23 schrieb Rohit Khaire:

This is similar to IH_RB_CNTL programming in
navi10_ih_toggle_ring_interrupts

Signed-off-by: Rohit Khaire 
---
drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 20 ++--
1 file changed, 18 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
index eac564e8dd52..e41188c04846 100644
--- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
@@ -120,11 +120,27 @@ force_update_wptr_for_self_int(struct amdgpu_device *adev,
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
   RB_USED_INT_THRESHOLD, threshold);

-	WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);

+   if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
+   if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 
ih_rb_cntl)) {
+   DRM_ERROR("PSP program IH_RB_CNTL_RING1 failed!\n");
+   return;
+   }
+   } else {
+   WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
+   }
+
ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,
   RB_USED_INT_THRESHOLD, threshold);
-   WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
+   if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
+   if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 
ih_rb_cntl)) {
+   DRM_ERROR("PSP program IH_RB_CNTL_RING2 failed!\n");
+   return;
+   }
+   } else {
+   WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
+   }
+
WREG32_SOC15(OSSSYS, 0, mmIH_CNTL2, ih_cntl);
}



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Re: [PATCH 4/4] drm/i915/display: Add handling for new "active bpc" property

[Werner Sembach]

Am 07.06.21 um 08:47 schrieb Werner Sembach:


Am 04.06.21 um 19:30 schrieb Ville Syrjälä:

On Fri, Jun 04, 2021 at 07:17:23PM +0200, Werner Sembach wrote:
This commits implements the "active bpc" drm property for the Intel 
GPU driver.


Signed-off-by: Werner Sembach 
---
  drivers/gpu/drm/i915/display/intel_display.c | 13 +
  drivers/gpu/drm/i915/display/intel_dp.c  |  8 ++--
  drivers/gpu/drm/i915/display/intel_dp_mst.c  |  4 +++-
  drivers/gpu/drm/i915/display/intel_hdmi.c    |  4 +++-
  4 files changed, 25 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c

index 64e9107d70f7..f7898d9d7438 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -10164,6 +10164,8 @@ static void intel_atomic_commit_tail(struct 
intel_atomic_state *state)

  struct drm_i915_private *dev_priv = to_i915(dev);
  struct intel_crtc_state *new_crtc_state, *old_crtc_state;
  struct intel_crtc *crtc;
+    struct drm_connector *connector;
+    struct drm_connector_state *new_conn_state;
  u64 put_domains[I915_MAX_PIPES] = {};
  intel_wakeref_t wakeref = 0;
  int i;
@@ -10324,6 +10326,17 @@ static void intel_atomic_commit_tail(struct 
intel_atomic_state *state)

  }
  intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
  +    /* Extract information from crtc to communicate it to 
userspace as connector properties */
+    for_each_new_connector_in_state(&state->base, connector, 
new_conn_state, i) {

+    struct drm_crtc *crtc = new_conn_state->crtc;
+    if (crtc) {
+    new_crtc_state = 
to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base, crtc));

intel_atomic_get_new_crtc_state()

Thanks, will use that.



+ new_conn_state->active_bpc = new_crtc_state->pipe_bpp / 3;
+    }
+    else
+    new_conn_state->active_bpc = 0;
+    }

This also seems too late. I think the whole thing should be
done somewhere around the normal swap_state() stuff.

Ok, will look into it.
So I tried to put it in intel_atomic_commit() after 
drm_atomic_helper_swap_state() and before 
INIT_WORK(&state->base.commit_work, intel_atomic_commit_work) (which 
creates a worker for intel_atomic_commit_tail), but somewhere in 
between, the connector_state seems to change: The bpc written with the 
for_each_new_connector_in_state() loop, gets discarded.



+
  /*
   * Defer the cleanup of the old state to a separate worker to not
   * impede the current task (userspace for blocking modesets) that
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c

index 642c60f3d9b1..67826ba976ed 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4671,10 +4671,14 @@ intel_dp_add_properties(struct intel_dp 
*intel_dp, struct drm_connector *connect

  intel_attach_force_audio_property(connector);
    intel_attach_broadcast_rgb_property(connector);
-    if (HAS_GMCH(dev_priv))
+    if (HAS_GMCH(dev_priv)) {
  drm_connector_attach_max_bpc_property(connector, 6, 10);
-    else if (DISPLAY_VER(dev_priv) >= 5)
+    drm_connector_attach_active_bpc_property(connector, 6, 10);
+    }
+    else if (DISPLAY_VER(dev_priv) >= 5) {
  drm_connector_attach_max_bpc_property(connector, 6, 12);
+    drm_connector_attach_active_bpc_property(connector, 6, 12);
+    }
    /* Register HDMI colorspace for case of lspcon */
  if (intel_bios_is_lspcon_present(dev_priv, port)) {
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c 
b/drivers/gpu/drm/i915/display/intel_dp_mst.c

index 2daa3f67791e..5a1869dc2210 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -844,8 +844,10 @@ static struct drm_connector 
*intel_dp_add_mst_connector(struct drm_dp_mst_topolo

   */
  connector->max_bpc_property =
intel_dp->attached_connector->base.max_bpc_property;
-    if (connector->max_bpc_property)
+    if (connector->max_bpc_property) {
  drm_connector_attach_max_bpc_property(connector, 6, 12);
+    drm_connector_attach_active_bpc_property(connector, 6, 12);
+    }
    return connector;
  diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c 
b/drivers/gpu/drm/i915/display/intel_hdmi.c

index d69f0a6dc26d..8af78b27b6ce 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2463,8 +2463,10 @@ intel_hdmi_add_properties(struct intel_hdmi 
*intel_hdmi, struct drm_connector *c

  drm_object_attach_property(&connector->base,
connector->dev->mode_config.hdr_output_metadata_property, 0);
  -    if (!HAS_GMCH(dev_priv))
+    if (!HAS_GMCH(dev_priv)) {
  drm_connector_attach_max_bpc_property(connector, 8, 12);
+    drm_connector_attach_active_bpc_property(connector, 8, 12);
+    }
  

Re: [PATCH] drm/amdgpu: Use PSP to program IH_RB_CNTL_RING1/2 on SRIOV

[Felix Kuehling]

With SRIOV, the interrupt routing is setup by the hypervisor driver. We
need the secondary IH rings in case the hypervisor enabled rerouting of
page fault interrupts. I'm not sure what the hypervisor driver does today.

Regards,
  Felix


Am 2021-06-07 um 12:29 p.m. schrieb Christian König:
> That's a workaround for bare metal and as far as I know doesn't apply
> to SRIOV.
>
> We only need the additional IH rings for page fault handling or log
> handling and as far as I know that is incompatible with SRIOV for the
> moment. But Felix might have some more updates on this.
>
> So as long as we don't support that under SRIOV we don't need this
> patch either.
>
> Christian.
>
> Am 07.06.21 um 17:59 schrieb Khaire, Rohit:
>> [AMD Public Use]
>>
>> The hash is 5ea6f9c
>>
>> Rohit
>>
>> -Original Message-
>> From: Koenig, Christian 
>> Sent: June 7, 2021 11:58 AM
>> To: Khaire, Rohit ;
>> amd-gfx@lists.freedesktop.org; Deucher, Alexander
>> ; Zhang, Hawking ;
>> Deng, Emily ; Liu, Monk ; Zhou,
>> Peng Ju ; Chen, Horace 
>> Cc: Ming, Davis 
>> Subject: Re: [PATCH] drm/amdgpu: Use PSP to program
>> IH_RB_CNTL_RING1/2 on SRIOV
>>
>> Do you have the hash for this commit?
>>
>> Thanks,
>> Christian.
>>
>> Am 07.06.21 um 17:30 schrieb Khaire, Rohit:
>>> [AMD Public Use]
>>>
>>> We don't need RING1 and RING2 functionality for SRIOV afaik.
>>>
>>> But looking at the description of the original commit message it
>>> affects RING0 too?
>>>
>>> " drm/amdgpu: add timeout flush mechanism to update wptr for self
>>> interrupt (v2)
>>>
>>> outstanding log reaches threshold will trigger IH ring1/2's wptr
>>> reported, that will avoid generating interrupts to ring0 too frequent.
>>> But if ring1/2's wptr hasn't been increased for a long time, the
>>> outstanding log can't reach threshold so that driver can't get latest
>>> wptr info and miss some interrupts."
>>>
>>> Rohit
>>>
>>> -Original Message-
>>> From: Koenig, Christian 
>>> Sent: June 7, 2021 10:31 AM
>>> To: Khaire, Rohit ;
>>> amd-gfx@lists.freedesktop.org; Deucher, Alexander
>>> ; Zhang, Hawking ;
>>> Deng, Emily ; Liu, Monk ; Zhou,
>>> Peng Ju ; Chen, Horace 
>>> Cc: Ming, Davis 
>>> Subject: Re: [PATCH] drm/amdgpu: Use PSP to program IH_RB_CNTL_RING1/2
>>> on SRIOV
>>>
>>> Why are the ring 1&2 enabled on SRIOV in the first place?
>>>
>>> Christian.
>>>
>>> Am 07.06.21 um 16:23 schrieb Rohit Khaire:
 This is similar to IH_RB_CNTL programming in
 navi10_ih_toggle_ring_interrupts

 Signed-off-by: Rohit Khaire 
 ---
     drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 20 ++--
     1 file changed, 18 insertions(+), 2 deletions(-)

 diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
 b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
 index eac564e8dd52..e41188c04846 100644
 --- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
 +++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
 @@ -120,11 +120,27 @@ force_update_wptr_for_self_int(struct
 amdgpu_device *adev,
     ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
    RB_USED_INT_THRESHOLD, threshold);
     -    WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
 +    if (amdgpu_sriov_vf(adev) &&
 amdgpu_sriov_reg_indirect_ih(adev)) {
 +    if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1,
 ih_rb_cntl)) {
 +    DRM_ERROR("PSP program IH_RB_CNTL_RING1 failed!\n");
 +    return;
 +    }
 +    } else {
 +    WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
 +    }
 +
     ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
     ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,
    RB_USED_INT_THRESHOLD, threshold);
 -    WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
 +    if (amdgpu_sriov_vf(adev) &&
 amdgpu_sriov_reg_indirect_ih(adev)) {
 +    if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2,
 ih_rb_cntl)) {
 +    DRM_ERROR("PSP program IH_RB_CNTL_RING2 failed!\n");
 +    return;
 +    }
 +    } else {
 +    WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
 +    }
 +
     WREG32_SOC15(OSSSYS, 0, mmIH_CNTL2, ih_cntl);
     }
     
>
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Re: [PATCH] drm/amdgpu: Use PSP to program IH_RB_CNTL_RING1/2 on SRIOV

[Christian König]

Ah, good point. In this case we should probably rather save than sorry.

Then I suggest to clean up this patch, repeating the psp_reg_program() 
and error message is pretty horrible coding style.


Christian.

Am 07.06.21 um 18:36 schrieb Felix Kuehling:

With SRIOV, the interrupt routing is setup by the hypervisor driver. We
need the secondary IH rings in case the hypervisor enabled rerouting of
page fault interrupts. I'm not sure what the hypervisor driver does today.

Regards,
   Felix


Am 2021-06-07 um 12:29 p.m. schrieb Christian König:

That's a workaround for bare metal and as far as I know doesn't apply
to SRIOV.

We only need the additional IH rings for page fault handling or log
handling and as far as I know that is incompatible with SRIOV for the
moment. But Felix might have some more updates on this.

So as long as we don't support that under SRIOV we don't need this
patch either.

Christian.

Am 07.06.21 um 17:59 schrieb Khaire, Rohit:

[AMD Public Use]

The hash is 5ea6f9c

Rohit

-Original Message-
From: Koenig, Christian 
Sent: June 7, 2021 11:58 AM
To: Khaire, Rohit ;
amd-gfx@lists.freedesktop.org; Deucher, Alexander
; Zhang, Hawking ;
Deng, Emily ; Liu, Monk ; Zhou,
Peng Ju ; Chen, Horace 
Cc: Ming, Davis 
Subject: Re: [PATCH] drm/amdgpu: Use PSP to program
IH_RB_CNTL_RING1/2 on SRIOV

Do you have the hash for this commit?

Thanks,
Christian.

Am 07.06.21 um 17:30 schrieb Khaire, Rohit:

[AMD Public Use]

We don't need RING1 and RING2 functionality for SRIOV afaik.

But looking at the description of the original commit message it
affects RING0 too?

" drm/amdgpu: add timeout flush mechanism to update wptr for self
interrupt (v2)

outstanding log reaches threshold will trigger IH ring1/2's wptr
reported, that will avoid generating interrupts to ring0 too frequent.
But if ring1/2's wptr hasn't been increased for a long time, the
outstanding log can't reach threshold so that driver can't get latest
wptr info and miss some interrupts."

Rohit

-Original Message-
From: Koenig, Christian 
Sent: June 7, 2021 10:31 AM
To: Khaire, Rohit ;
amd-gfx@lists.freedesktop.org; Deucher, Alexander
; Zhang, Hawking ;
Deng, Emily ; Liu, Monk ; Zhou,
Peng Ju ; Chen, Horace 
Cc: Ming, Davis 
Subject: Re: [PATCH] drm/amdgpu: Use PSP to program IH_RB_CNTL_RING1/2
on SRIOV

Why are the ring 1&2 enabled on SRIOV in the first place?

Christian.

Am 07.06.21 um 16:23 schrieb Rohit Khaire:

This is similar to IH_RB_CNTL programming in
navi10_ih_toggle_ring_interrupts

Signed-off-by: Rohit Khaire 
---
     drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 20 ++--
     1 file changed, 18 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
index eac564e8dd52..e41188c04846 100644
--- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
@@ -120,11 +120,27 @@ force_update_wptr_for_self_int(struct
amdgpu_device *adev,
     ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
    RB_USED_INT_THRESHOLD, threshold);
     -    WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
+    if (amdgpu_sriov_vf(adev) &&
amdgpu_sriov_reg_indirect_ih(adev)) {
+    if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1,
ih_rb_cntl)) {
+    DRM_ERROR("PSP program IH_RB_CNTL_RING1 failed!\n");
+    return;
+    }
+    } else {
+    WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
+    }
+
     ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
     ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,
    RB_USED_INT_THRESHOLD, threshold);
-    WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
+    if (amdgpu_sriov_vf(adev) &&
amdgpu_sriov_reg_indirect_ih(adev)) {
+    if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2,
ih_rb_cntl)) {
+    DRM_ERROR("PSP program IH_RB_CNTL_RING2 failed!\n");
+    return;
+    }
+    } else {
+    WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
+    }
+
     WREG32_SOC15(OSSSYS, 0, mmIH_CNTL2, ih_cntl);
     }
 


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[PATCH 01/30] drm/amd/display: Trigger full update after DCC on/off

[Stylon Wang]

From: Jake Wang 

[Why]
During DCC on/off, stutter period is calculated before DCC has fully 
transitioned.
This results in incorrect stutter period calculation.

[How]
Trigger a full update when DCC changes between on/off.

Signed-off-by: Jake Wang 
Reviewed-by: Aric Cyr 
Acked-by: Stylon Wang 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 34c207f92df9..156ba8d3d4dc 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1918,8 +1918,13 @@ static enum surface_update_type 
get_plane_info_update_type(const struct dc_surfa
if (u->plane_info->dcc.enable != u->surface->dcc.enable
|| u->plane_info->dcc.independent_64b_blks != 
u->surface->dcc.independent_64b_blks
|| u->plane_info->dcc.meta_pitch != 
u->surface->dcc.meta_pitch) {
+   /* During DCC on/off, stutter period is calculated before
+* DCC has fully transitioned. This results in incorrect
+* stutter period calculation. Triggering a full update will
+* recalculate stutter period.
+*/
update_flags->bits.dcc_change = 1;
-   elevate_update_type(&update_type, UPDATE_TYPE_MED);
+   elevate_update_type(&update_type, UPDATE_TYPE_FULL);
}
 
if (resource_pixel_format_to_bpp(u->plane_info->format) !=
-- 
2.25.1

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[PATCH 00/30] DC Patches June, 7, 2021

[Stylon Wang]

This DC patchset brings improvements in multiple areas. In summary, we
highlight:

* DC v3.2.139
* FW v0.0.69
* Improvements across DP, eDP, DMUB, MPO, etc

--

Anthony Koo (1):
  drm/amd/display: [FW Promotion] Release 0.0.68

Aric Cyr (4):
  drm/amd/display: Change default policy for MPO with multidisplay
  drm/amd/display: 3.2.138
  drm/amd/display: Fix crash during MPO + ODM combine mode recalculation
  drm/amd/display: 3.2.139

Dingchen (David) Zhang (1):
  drm/amd/display: force CP to DESIRED when removing display

Eric Bernstein (1):
  drm/amd/display: Updates for ODM Transition Test

Evgenii Krasnikov (1):
  drm/amd/display: add visual confirm colors to differentiate
layer_index > 0

Fangzhi Zuo (1):
  drm/amd/display: Add debugfs entry for dsc passthrough

Ilya Bakoulin (1):
  drm/amd/display: Revert "Fix clock table filling logic"

Jake Wang (1):
  drm/amd/display: Trigger full update after DCC on/off

Jayendran Ramani (1):
  drm/amd/display: Return last used DRR VTOTAL from DC

Jimmy Kizito (2):
  drm/amd/display: Expand DP module equalization API.
  drm/amd/display: Support mappable encoders when transmitting training
patterns.

JinZe.Xu (1):
  drm/amd/display: Control power gating by driver.

Meenakshikumar Somasundaram (1):
  drm/amd/display: Remove unused definition of DMUB SET_CONFIG

Mikita Lipski (2):
  drm/amd/display: Enabling PSR support for multiple panels
  drm/amd/display: Enable PSR Residency for multiple panels

Nikola Cornij (1):
  drm/amd/display: Fix DCN 3.01 DSCCLK validation

Po-Ting Chen (1):
  drm/amd/display: Add swizzle visual confirm mode

Roman Li (1):
  drm/amd/display: Update scaling settings on modeset

Roy Chan (1):
  drm/amd/display: Revert "Disconnect non-DP with no EDID"

Vladimir Stempen (1):
  drm/amd/display: Release MST resources on switch from MST to SST

Wenjing Liu (1):
  drm/amd/display: delay 100ms before restart after failing to read
CP_IRQ

Wesley Chalmers (4):
  drm/amd/display: Add Interface to set FIFO ERRDET SW Override
  drm/amd/display: Add interface for ADD & DROP PIXEL Registers
  drm/amd/display: Set DISPCLK_MAX_ERRDET_CYCLES to 7
  drm/amd/display: Fix off-by-one error in DML

Wyatt Wood (2):
  drm/amd/display: Refactor visual confirm
  drm/amd/display: [FW Promotion] Release 0.0.69

 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |   3 +-
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h |   1 +
 .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c |  50 ++-
 .../amd/display/amdgpu_dm/amdgpu_dm_hdcp.c|  15 +-
 .../gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c  |  22 ++-
 .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c |  78 --
 drivers/gpu/drm/amd/display/dc/core/dc.c  |  60 +++-
 .../drm/amd/display/dc/core/dc_hw_sequencer.c | 133 ++
 drivers/gpu/drm/amd/display/dc/core/dc_link.c |  47 +++
 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  |  24 ++--
 .../drm/amd/display/dc/core/dc_link_hwss.c|  11 +-
 .../gpu/drm/amd/display/dc/core/dc_resource.c |   5 +
 drivers/gpu/drm/amd/display/dc/dc.h   |   3 +-
 drivers/gpu/drm/amd/display/dc/dc_stream.h|   4 +
 drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c |  41 --
 drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h |  17 ++-
 .../display/dc/dce110/dce110_hw_sequencer.c   |  35 -
 .../dc/dce110/dce110_timing_generator.c   |   1 +
 .../dc/dce120/dce120_timing_generator.c   |   1 +
 .../display/dc/dce80/dce80_timing_generator.c |   1 +
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 110 +++
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.h |  12 +-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_init.c |   3 +-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c  |   4 +-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_optc.c |   1 +
 .../gpu/drm/amd/display/dc/dcn10/dcn10_optc.h |   4 +-
 .../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c |  36 +
 .../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h |  76 +-
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.c|  47 +++
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.h|   5 +
 .../gpu/drm/amd/display/dc/dcn20/dcn20_init.c |   3 +-
 .../gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c  |   2 +-
 .../gpu/drm/amd/display/dc/dcn20/dcn20_optc.c |  10 +-
 .../gpu/drm/amd/display/dc/dcn20/dcn20_optc.h |   9 +-
 .../drm/amd/display/dc/dcn20/dcn20_resource.c |   3 +-
 .../gpu/drm/amd/display/dc/dcn21/dcn21_dccg.c |   3 +
 .../gpu/drm/amd/display/dc/dcn21/dcn21_init.c |   3 +-
 .../drm/amd/display/dc/dcn21/dcn21_resource.c |  37 ++---
 .../gpu/drm/amd/display/dc/dcn30/dcn30_dccg.c |   3 +
 .../gpu/drm/amd/display/dc/dcn30/dcn30_dccg.h |  17 ++-
 .../gpu/drm/amd/display/dc/dcn30/dcn30_init.c |   3 +-
 .../gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c  |   2 +-
 .../gpu/drm/amd/display/dc/dcn30/dcn30_optc.c |   1 +
 .../gpu/drm/amd/display/dc/dcn30/dcn30_optc.h |   6 +-
 .../drm/amd/display/dc/dcn30/dcn30_resource.c |   2 +-
 .../drm/amd/display/dc/dcn301/dcn301_dccg.c   |   3 +
 .../drm/amd/display/dc/dcn301/dcn301_init.c   |   

[PATCH 02/30] drm/amd/display: Enabling PSR support for multiple panels

[Stylon Wang]

From: Mikita Lipski 

[why]
Updating PSR interfaces to allow PSR enablement
per eDP panel.
[how]
- Copying PSR command structures to DC
- Changing function interfaces to pass panel instance
- Communicating with DMUB per link instead of assuming
to use a single one
-Iterating through all PSR capable panels when enabling/disabling
all

Signed-off-by: Mikita Lipski 
Reviewed-by: Nicholas Kazlauskas 
Acked-by: Stylon Wang 
---
 .../gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c  | 22 +++--
 drivers/gpu/drm/amd/display/dc/core/dc.c  | 11 ++-
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 21 -
 drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 34 +---
 drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h | 14 +--
 .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h   | 85 ++-
 6 files changed, 153 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
index dd52ebf56d62..7fcc32941f4d 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
@@ -90,15 +90,20 @@ void clk_mgr_exit_optimized_pwr_state(const struct dc *dc, 
struct clk_mgr *clk_m
struct dc_link *edp_links[MAX_NUM_EDP];
struct dc_link *edp_link = NULL;
int edp_num;
+   unsigned int panel_inst;
 
get_edp_links(dc, edp_links, &edp_num);
if (dc->hwss.exit_optimized_pwr_state)
dc->hwss.exit_optimized_pwr_state(dc, dc->current_state);
 
if (edp_num) {
-   edp_link = edp_links[0];
-   clk_mgr->psr_allow_active_cache = 
edp_link->psr_settings.psr_allow_active;
-   dc_link_set_psr_allow_active(edp_link, false, false, false);
+   for (panel_inst = 0; panel_inst < edp_num; panel_inst++) {
+   edp_link = edp_links[panel_inst];
+   if (!edp_link->psr_settings.psr_feature_enabled)
+   continue;
+   clk_mgr->psr_allow_active_cache = 
edp_link->psr_settings.psr_allow_active;
+   dc_link_set_psr_allow_active(edp_link, false, false, 
false);
+   }
}
 
 }
@@ -108,12 +113,17 @@ void clk_mgr_optimize_pwr_state(const struct dc *dc, 
struct clk_mgr *clk_mgr)
struct dc_link *edp_links[MAX_NUM_EDP];
struct dc_link *edp_link = NULL;
int edp_num;
+   unsigned int panel_inst;
 
get_edp_links(dc, edp_links, &edp_num);
if (edp_num) {
-   edp_link = edp_links[0];
-   dc_link_set_psr_allow_active(edp_link,
-   clk_mgr->psr_allow_active_cache, false, false);
+   for (panel_inst = 0; panel_inst < edp_num; panel_inst++) {
+   edp_link = edp_links[panel_inst];
+   if (!edp_link->psr_settings.psr_feature_enabled)
+   continue;
+   dc_link_set_psr_allow_active(edp_link,
+   clk_mgr->psr_allow_active_cache, false, 
false);
+   }
}
 
if (dc->hwss.optimize_pwr_state)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 156ba8d3d4dc..a368e7c5245d 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -3262,10 +3262,13 @@ bool dc_set_psr_allow_active(struct dc *dc, bool enable)
continue;
 
if (link->psr_settings.psr_feature_enabled) {
-   if (enable && !link->psr_settings.psr_allow_active)
-   return dc_link_set_psr_allow_active(link, true, 
false, false);
-   else if (!enable && link->psr_settings.psr_allow_active)
-   return dc_link_set_psr_allow_active(link, 
false, true, false);
+   if (enable && !link->psr_settings.psr_allow_active) {
+   if (!dc_link_set_psr_allow_active(link, true, 
false, false))
+   return false;
+   } else if (!enable && 
link->psr_settings.psr_allow_active) {
+   if (!dc_link_set_psr_allow_active(link, false, 
true, false))
+   return false;
+   }
}
}
 
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index c07b45c021d5..ce637bf0cb81 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -2701,16 +2701,20 @@ bool dc_link_set_psr_allow_active(struct dc_link *link, 
bool allow_active,
struct dc  *dc = link->ctx->dc;
struct dmcu *dmcu = dc->res_pool->dmcu;
struct dmub_psr *psr = dc->res_pool->psr;
+   unsigned int panel_inst;
 
if

[PATCH 10/30] drm/amd/display: Support mappable encoders when transmitting training patterns.

[Stylon Wang]

From: Jimmy Kizito 

[Why & How]
Add support for transmitting training pattern sequences for links whose
encoders have been dynamically assigned.

Signed-off-by: Jimmy Kizito 
Reviewed-by: Jun Lei 
Acked-by: Stylon Wang 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 11 ++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
index 13c5c4a34a58..f7dfc8fefdfa 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
@@ -332,7 +332,16 @@ void dp_set_hw_test_pattern(
uint32_t custom_pattern_size)
 {
struct encoder_set_dp_phy_pattern_param pattern_param = {0};
-   struct link_encoder *encoder = link->link_enc;
+   struct link_encoder *encoder;
+
+   /* Access link encoder based on whether it is statically
+* or dynamically assigned to a link.
+*/
+   if (link->is_dig_mapping_flexible &&
+   link->dc->res_pool->funcs->link_encs_assign)
+   encoder = 
link_enc_cfg_get_link_enc_used_by_link(link->dc->current_state, link);
+   else
+   encoder = link->link_enc;
 
pattern_param.dp_phy_pattern = test_pattern;
pattern_param.custom_pattern = custom_pattern;
-- 
2.25.1

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[PATCH 04/30] drm/amd/display: Fix DCN 3.01 DSCCLK validation

[Stylon Wang]

From: Nikola Cornij 

[why]
DSCCLK validation is not necessary because DSCCLK is derrived from
DISPCLK, therefore if DISPCLK validation passes, DSCCLK is valid, too.
Doing DSCLK validation in addition to DISPCLK leads to modes being
wrongly rejected when DSCCLK was incorrectly set outside of DML.

[how]
Remove DSCCLK validation because it's implicitly validated under DISPCLK

Signed-off-by: Nikola Cornij 
Reviewed-by: Dmytro Laktyushkin 
Acked-by: Stylon Wang 
---
 .../dc/dml/dcn30/display_mode_vba_30.c| 64 ++-
 1 file changed, 21 insertions(+), 43 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
index ec56210b6180..bd657029f8c9 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
@@ -64,6 +64,7 @@ typedef struct {
 #define BPP_INVALID 0
 #define BPP_BLENDED_PIPE 0x
 #define DCN30_MAX_DSC_IMAGE_WIDTH 5184
+#define DCN30_MAX_FMT_420_BUFFER_WIDTH 4096
 
 static void DisplayPipeConfiguration(struct display_mode_lib *mode_lib);
 static void 
DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation(
@@ -3987,19 +3988,30 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct 
display_mode_lib *mode_l
} else if 
(v->PlaneRequiredDISPCLKWithoutODMCombine > 
v->MaxDispclkRoundedDownToDFSGranularity) {
v->ODMCombineEnablePerState[i][k] = 
dm_odm_combine_mode_2to1;
v->PlaneRequiredDISPCLK = 
v->PlaneRequiredDISPCLKWithODMCombine2To1;
-   } else if (v->DSCEnabled[k] && (v->HActive[k] > 
DCN30_MAX_DSC_IMAGE_WIDTH)) {
-   v->ODMCombineEnablePerState[i][k] = 
dm_odm_combine_mode_2to1;
-   v->PlaneRequiredDISPCLK = 
v->PlaneRequiredDISPCLKWithODMCombine2To1;
} else {
v->ODMCombineEnablePerState[i][k] = 
dm_odm_combine_mode_disabled;
v->PlaneRequiredDISPCLK = 
v->PlaneRequiredDISPCLKWithoutODMCombine;
-   /*420 format workaround*/
-   if (v->HActive[k] > 4096 && 
v->OutputFormat[k] == dm_420) {
+   }
+   if (v->DSCEnabled[k] && v->HActive[k] > 
DCN30_MAX_DSC_IMAGE_WIDTH
+   && 
v->ODMCombineEnablePerState[i][k] != dm_odm_combine_mode_4to1) {
+   if (v->HActive[k] / 2 > 
DCN30_MAX_DSC_IMAGE_WIDTH) {
+   
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_4to1;
+   v->PlaneRequiredDISPCLK = 
v->PlaneRequiredDISPCLKWithODMCombine4To1;
+   } else {
+   
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
+   v->PlaneRequiredDISPCLK = 
v->PlaneRequiredDISPCLKWithODMCombine2To1;
+   }
+   }
+   if (v->OutputFormat[k] == dm_420 && 
v->HActive[k] > DCN30_MAX_FMT_420_BUFFER_WIDTH
+   && 
v->ODMCombineEnablePerState[i][k] != dm_odm_combine_mode_4to1) {
+   if (v->HActive[k] / 2 > 
DCN30_MAX_FMT_420_BUFFER_WIDTH) {
+   
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_4to1;
+   v->PlaneRequiredDISPCLK = 
v->PlaneRequiredDISPCLKWithODMCombine4To1;
+   } else {

v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
v->PlaneRequiredDISPCLK = 
v->PlaneRequiredDISPCLKWithODMCombine2To1;
}
}
-
if (v->ODMCombineEnablePerState[i][k] == 
dm_odm_combine_mode_4to1) {
v->MPCCombine[i][j][k] = false;
v->NoOfDPP[i][j][k] = 4;
@@ -4281,42 +4293,8 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct 
display_mode_lib *mode_l
}
}
 
-   for (i = 0; i < v->soc.num_states; i++) {
-   v->DSCCLKRequiredMoreThanSupported[i] = false;
-   for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
-   if (v->BlendingAndTiming[k] == k) {
-   if (v->Output[k] == dm_dp || v->Output[k] 

[PATCH 03/30] drm/amd/display: delay 100ms before restart after failing to read CP_IRQ

[Stylon Wang]

From: Wenjing Liu 

[why]
Some DPRX will issue CP_IRQ when user disconnects a display
that has been authenticated.
Since display is being disconnecting dpcd read will fail.
This will cause us to attempt HDCP retry on disconnection.
We are adding a 100ms delay before retry.
So we will only start retry if within 100ms there is no disconnection call
to HDCP module.

Signed-off-by: Wenjing Liu 
Reviewed-by: Nicholas Kazlauskas 
Acked-by: Stylon Wang 
---
 drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c 
b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c
index b0306ed6d6b4..70cb230d8f56 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c
@@ -564,7 +564,7 @@ enum mod_hdcp_status mod_hdcp_hdcp2_dp_transition(struct 
mod_hdcp *hdcp,
case D2_A5_AUTHENTICATED:
if (input->rxstatus_read == FAIL ||
input->reauth_request_check == FAIL) {
-   fail_and_restart_in_ms(0, &status, output);
+   fail_and_restart_in_ms(100, &status, output);
break;
} else if (input->link_integrity_check_dp == FAIL) {
if (hdcp->connection.hdcp2_retry_count >= 1)
-- 
2.25.1

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[PATCH 05/30] drm/amd/display: Control power gating by driver.

[Stylon Wang]

From: "JinZe.Xu" 

[Why]
This disablement would be specific for Nav10 and shouldn’t be propagated to the 
other programs.

[How]
Power gating is controlled by driver.

Signed-off-by: JinZe.Xu 
Reviewed-by: Jun Lei 
Acked-by: Stylon Wang 
---
 .../drm/amd/display/dc/dcn302/dcn302_hwseq.c  | 34 +++
 1 file changed, 12 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_hwseq.c
index e8580cccbebf..0a6d58dd8f6d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_hwseq.c
@@ -86,17 +86,12 @@ void dcn302_dpp_pg_control(struct dce_hwseq *hws, unsigned 
int dpp_inst, bool po
1, 1000);
break;
case 4: /* DPP4 */
-   /*
-* Do not power gate DPP4, should be left at HW default, power 
on permanently.
-* PG on Pipe4 is De-featured, attempting to put it to PG state 
may result in hard
-* reset.
-* REG_UPDATE(DOMAIN9_PG_CONFIG,
-*  DOMAIN9_POWER_GATE, power_gate);
-*
-* REG_WAIT(DOMAIN9_PG_STATUS,
-*  DOMAIN9_PGFSM_PWR_STATUS, pwr_status,
-*  1, 1000);
-*/
+   REG_UPDATE(DOMAIN9_PG_CONFIG,
+   DOMAIN9_POWER_GATE, power_gate);
+
+   REG_WAIT(DOMAIN9_PG_STATUS,
+   DOMAIN9_PGFSM_PWR_STATUS, pwr_status,
+   1, 1000);
break;
default:
BREAK_TO_DEBUGGER();
@@ -148,17 +143,12 @@ void dcn302_hubp_pg_control(struct dce_hwseq *hws, 
unsigned int hubp_inst, bool
1, 1000);
break;
case 4: /* DCHUBP4 */
-   /*
-* Do not power gate DCHUB4, should be left at HW default, 
power on permanently.
-* PG on Pipe4 is De-featured, attempting to put it to PG state 
may result in hard
-* reset.
-* REG_UPDATE(DOMAIN8_PG_CONFIG,
-*  DOMAIN8_POWER_GATE, power_gate);
-*
-* REG_WAIT(DOMAIN8_PG_STATUS,
-*  DOMAIN8_PGFSM_PWR_STATUS, pwr_status,
-*  1, 1000);
-*/
+   REG_UPDATE(DOMAIN8_PG_CONFIG,
+   DOMAIN8_POWER_GATE, power_gate);
+
+   REG_WAIT(DOMAIN8_PG_STATUS,
+   DOMAIN8_PGFSM_PWR_STATUS, pwr_status,
+   1, 1000);
break;
default:
BREAK_TO_DEBUGGER();
-- 
2.25.1

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[PATCH 08/30] drm/amd/display: Revert "Fix clock table filling logic"

[Stylon Wang]

From: Ilya Bakoulin 

[Why]
This change was found to break some high-refresh modes. Reverting
to unblock mainline.

Signed-off-by: Ilya Bakoulin 
Reviewed-by: Sung Lee 
Acked-by: Stylon Wang 
---
 .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 78 +++
 .../drm/amd/display/dc/dcn21/dcn21_resource.c | 33 +++-
 2 files changed, 39 insertions(+), 72 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
index 416a24db17a9..c6f494f0dcea 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
@@ -835,66 +835,47 @@ static struct wm_table lpddr4_wm_table_rn = {
}
 };
 
-static unsigned int find_max_fclk_for_voltage(struct dpm_clocks *clock_table,
-   unsigned int voltage)
+static unsigned int find_socclk_for_voltage(struct dpm_clocks *clock_table, 
unsigned int voltage)
 {
int i;
-   uint32_t max_clk = 0;
 
-   for (i = 0; i < PP_SMU_NUM_FCLK_DPM_LEVELS; i++) {
-   if (clock_table->FClocks[i].Vol <= voltage) {
-   max_clk = clock_table->FClocks[i].Freq > max_clk ?
-   clock_table->FClocks[i].Freq : max_clk;
-   }
-   }
-
-   return max_clk;
-}
-
-static unsigned int find_max_memclk_for_voltage(struct dpm_clocks *clock_table,
-   unsigned int voltage)
-{
-   int i;
-   uint32_t max_clk = 0;
-
-   for (i = 0; i < PP_SMU_NUM_MEMCLK_DPM_LEVELS; i++) {
-   if (clock_table->MemClocks[i].Vol <= voltage) {
-   max_clk = clock_table->MemClocks[i].Freq > max_clk ?
-   clock_table->MemClocks[i].Freq : max_clk;
-   }
+   for (i = 0; i < PP_SMU_NUM_SOCCLK_DPM_LEVELS; i++) {
+   if (clock_table->SocClocks[i].Vol == voltage)
+   return clock_table->SocClocks[i].Freq;
}
 
-   return max_clk;
+   ASSERT(0);
+   return 0;
 }
 
-static unsigned int find_max_socclk_for_voltage(struct dpm_clocks *clock_table,
-   unsigned int voltage)
+static unsigned int find_dcfclk_for_voltage(struct dpm_clocks *clock_table, 
unsigned int voltage)
 {
int i;
-   uint32_t max_clk = 0;
 
-   for (i = 0; i < PP_SMU_NUM_SOCCLK_DPM_LEVELS; i++) {
-   if (clock_table->SocClocks[i].Vol <= voltage) {
-   max_clk = clock_table->SocClocks[i].Freq > max_clk ?
-   clock_table->SocClocks[i].Freq : max_clk;
-   }
+   for (i = 0; i < PP_SMU_NUM_DCFCLK_DPM_LEVELS; i++) {
+   if (clock_table->DcfClocks[i].Vol == voltage)
+   return clock_table->DcfClocks[i].Freq;
}
 
-   return max_clk;
+   ASSERT(0);
+   return 0;
 }
 
 static void rn_clk_mgr_helper_populate_bw_params(struct clk_bw_params 
*bw_params, struct dpm_clocks *clock_table, struct integrated_info *bios_info)
 {
int i, j = 0;
-   unsigned int volt;
 
j = -1;
 
-   /* Find max DPM */
-   for (i = 0; i < PP_SMU_NUM_DCFCLK_DPM_LEVELS; ++i) {
-   if (clock_table->DcfClocks[i].Freq != 0 &&
-   clock_table->DcfClocks[i].Vol != 0)
+   ASSERT(PP_SMU_NUM_FCLK_DPM_LEVELS <= MAX_NUM_DPM_LVL);
+
+   /* Find lowest DPM, FCLK is filled in reverse order*/
+
+   for (i = PP_SMU_NUM_FCLK_DPM_LEVELS - 1; i >= 0; i--) {
+   if (clock_table->FClocks[i].Freq != 0 && 
clock_table->FClocks[i].Vol != 0) {
j = i;
+   break;
+   }
}
 
if (j == -1) {
@@ -905,18 +886,13 @@ static void rn_clk_mgr_helper_populate_bw_params(struct 
clk_bw_params *bw_params
 
bw_params->clk_table.num_entries = j + 1;
 
-   for (i = 0; i < bw_params->clk_table.num_entries; i++) {
-   volt = clock_table->DcfClocks[i].Vol;
-
-   bw_params->clk_table.entries[i].voltage = volt;
-   bw_params->clk_table.entries[i].dcfclk_mhz =
-   clock_table->DcfClocks[i].Freq;
-   bw_params->clk_table.entries[i].fclk_mhz =
-   find_max_fclk_for_voltage(clock_table, volt);
-   bw_params->clk_table.entries[i].memclk_mhz =
-   find_max_memclk_for_voltage(clock_table, volt);
-   bw_params->clk_table.entries[i].socclk_mhz =
-   find_max_socclk_for_voltage(clock_table, volt);
+   for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) {
+   bw_params->clk_table.entries[i].fclk_mhz = 
clock_table->FClocks[j].Freq;
+   bw_params->clk_table.entries[i].memclk_mhz = 
clock_table->MemClocks[j].Freq;
+   bw_params->clk_table.entries[i].voltage = 
clock_table->FClocks[j].Vol;
+   bw_params->clk_table.entries[i].

[PATCH 12/30] drm/amd/display: Remove unused definition of DMUB SET_CONFIG

[Stylon Wang]

From: Meenakshikumar Somasundaram 

[Why & How]
SET_CONFIG transactions with DMUB is not used and removed.

Signed-off-by: Meenakshikumar Somasundaram 
Reviewed-by: Jun Lei 
Acked-by: Stylon Wang 
---
 drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 
 1 file changed, 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h 
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index ac8c366c6e8c..6eae16c27b1d 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -631,10 +631,6 @@ enum dmub_out_cmd_type {
 * Command type used for DP AUX Reply data notification
 */
DMUB_OUT_CMD__DP_AUX_REPLY = 1,
-   /**
-* Command type used for DP HPD event notification
-*/
-   DMUB_OUT_CMD__DP_HPD_NOTIFY = 2,
 };
 
 #pragma pack(push, 1)
-- 
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[PATCH 13/30] drm/amd/display: Return last used DRR VTOTAL from DC

[Stylon Wang]

From: Jayendran Ramani 

[How]
Add call to get the last used VTOTAL from DC

Signed-off-by: Jayendran Ramani 
Reviewed-by: Anthony Koo 
Acked-by: Stylon Wang 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c  | 42 +++
 drivers/gpu/drm/amd/display/dc/dc_stream.h|  4 ++
 .../dc/dce110/dce110_timing_generator.c   |  1 +
 .../dc/dce120/dce120_timing_generator.c   |  1 +
 .../display/dc/dce80/dce80_timing_generator.c |  1 +
 .../gpu/drm/amd/display/dc/dcn10/dcn10_optc.c |  1 +
 .../gpu/drm/amd/display/dc/dcn10/dcn10_optc.h |  4 +-
 .../gpu/drm/amd/display/dc/dcn20/dcn20_optc.c | 10 -
 .../gpu/drm/amd/display/dc/dcn20/dcn20_optc.h |  9 +++-
 .../gpu/drm/amd/display/dc/dcn30/dcn30_optc.c |  1 +
 .../gpu/drm/amd/display/dc/dcn30/dcn30_optc.h |  6 ++-
 .../amd/display/dc/inc/hw/timing_generator.h  |  1 +
 12 files changed, 75 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index a368e7c5245d..3430f3001ade 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -325,6 +325,48 @@ bool dc_stream_adjust_vmin_vmax(struct dc *dc,
return ret;
 }
 
+/**
+ *
+ *  Function: dc_stream_get_last_vrr_vtotal
+ *
+ *  @brief
+ * Looks up the pipe context of dc_stream_state and gets the
+ * last VTOTAL used by DRR (Dynamic Refresh Rate)
+ *
+ *  @param [in] dc: dc reference
+ *  @param [in] stream: Initial dc stream state
+ *  @param [in] adjust: Updated parameters for vertical_total_min and
+ *  vertical_total_max
+ *
+ */
+bool dc_stream_get_last_used_drr_vtotal(struct dc *dc,
+   struct dc_stream_state *stream,
+   uint32_t *refresh_rate)
+{
+   bool status = false;
+
+   int i = 0;
+
+   for (i = 0; i < MAX_PIPES; i++) {
+   struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
+
+   if (pipe->stream == stream && pipe->stream_res.tg) {
+   /* Only execute if a function pointer has been defined 
for
+* the DC version in question
+*/
+   if 
(pipe->stream_res.tg->funcs->get_last_used_drr_vtotal) {
+   
pipe->stream_res.tg->funcs->get_last_used_drr_vtotal(pipe->stream_res.tg, 
refresh_rate);
+
+   status = true;
+
+   break;
+   }
+   }
+   }
+
+   return status;
+}
+
 bool dc_stream_get_crtc_position(struct dc *dc,
struct dc_stream_state **streams, int num_streams,
unsigned int *v_pos, unsigned int *nom_v_pos)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h 
b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index 0ab1a33dae84..b8ebc1f09538 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -465,6 +465,10 @@ bool dc_stream_adjust_vmin_vmax(struct dc *dc,
struct dc_stream_state *stream,
struct dc_crtc_timing_adjust *adjust);
 
+bool dc_stream_get_last_used_drr_vtotal(struct dc *dc,
+   struct dc_stream_state *stream,
+   uint32_t *refresh_rate);
+
 bool dc_stream_get_crtc_position(struct dc *dc,
 struct dc_stream_state **stream,
 int num_streams,
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
index d88a74559edd..27cbb5b42c7e 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
@@ -2231,6 +2231,7 @@ static const struct timing_generator_funcs 
dce110_tg_funcs = {
dce110_timing_generator_enable_advanced_request,
.set_drr =
dce110_timing_generator_set_drr,
+   .get_last_used_drr_vtotal = NULL,
.set_static_screen_control =
dce110_timing_generator_set_static_screen_control,
.set_test_pattern = dce110_timing_generator_set_test_pattern,
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 
b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
index b57c466124e7..4af0c70098c4 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
@@ -1190,6 +1190,7 @@ static const struct timing_generator_funcs 
dce120_tg_funcs = {
.tear_down_global_swap_lock = 
dce120_timing_generator_tear_down_global_swap_lock,
.enable_advance

[PATCH 15/30] drm/amd/display: Release MST resources on switch from MST to SST

[Stylon Wang]

From: Vladimir Stempen 

[why]
When OS overrides training link training parameters
for MST device to SST mode, MST resources are not
released and leak of the resource may result crash and
incorrect MST discovery during following hot plugs.

[how]
Retaining sink object to be reused by SST link and
releasing MST  resources.

Signed-off-by: Vladimir Stempen 
Reviewed-by: Wenjing Liu 
Acked-by: Stylon Wang 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 87f955820c0f..919c94de2a20 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -1917,6 +1917,8 @@ static void set_dp_mst_mode(struct dc_link *link, bool 
mst_enable)
link->type = dc_connection_single;
link->local_sink = link->remote_sinks[0];
link->local_sink->sink_signal = SIGNAL_TYPE_DISPLAY_PORT;
+   dc_sink_retain(link->local_sink);
+   dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
} else if (mst_enable == true &&
link->type == dc_connection_single &&
link->remote_sinks[0] != NULL) {
-- 
2.25.1

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[PATCH 14/30] drm/amd/display: Enable PSR Residency for multiple panels

[Stylon Wang]

From: Mikita Lipski 

[why]
Allow specifying which panel to take PSR Residency
measurements from.
[how]
Pass panel instance to DMUB through GPINT in the upper
8 bits of the parameter.

Signed-off-by: Mikita Lipski 
Reviewed-by: Nicholas Kazlauskas 
Acked-by: Stylon Wang 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 8 ++--
 drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 7 ---
 drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h | 3 ++-
 3 files changed, 12 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index ce637bf0cb81..d1ade55a8d47 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -2928,10 +2928,14 @@ void dc_link_get_psr_residency(const struct dc_link 
*link, uint32_t *residency)
 {
struct dc  *dc = link->ctx->dc;
struct dmub_psr *psr = dc->res_pool->psr;
+   unsigned int panel_inst;
+
+   if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
+   return;
 
-   // PSR residency measurements only supported on DMCUB
+   /* PSR residency measurements only supported on DMCUB */
if (psr != NULL && link->psr_settings.psr_feature_enabled)
-   psr->funcs->psr_get_residency(psr, residency);
+   psr->funcs->psr_get_residency(psr, residency, panel_inst);
else
*residency = 0;
 }
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c 
b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
index c41db6d4e794..10d42ae0cffe 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
@@ -327,12 +327,13 @@ static void dmub_psr_force_static(struct dmub_psr *dmub, 
uint8_t panel_inst)
 /*
  * Get PSR residency from firmware.
  */
-static void dmub_psr_get_residency(struct dmub_psr *dmub, uint32_t *residency)
+static void dmub_psr_get_residency(struct dmub_psr *dmub, uint32_t *residency, 
uint8_t panel_inst)
 {
struct dmub_srv *srv = dmub->ctx->dmub_srv->dmub;
+   uint16_t param = (uint16_t)(panel_inst << 8);
 
-   // Send gpint command and wait for ack
-   dmub_srv_send_gpint_command(srv, DMUB_GPINT__PSR_RESIDENCY, 0, 30);
+   /* Send gpint command and wait for ack */
+   dmub_srv_send_gpint_command(srv, DMUB_GPINT__PSR_RESIDENCY, param, 30);
 
dmub_srv_get_gpint_response(srv, residency);
 }
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h 
b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h
index bf73c7edbd9e..9675c269e649 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h
@@ -44,7 +44,8 @@ struct dmub_psr_funcs {
void (*psr_set_level)(struct dmub_psr *dmub, uint16_t psr_level,
uint8_t panel_inst);
void (*psr_force_static)(struct dmub_psr *dmub, uint8_t panel_inst);
-   void (*psr_get_residency)(struct dmub_psr *dmub, uint32_t *residency);
+   void (*psr_get_residency)(struct dmub_psr *dmub, uint32_t *residency,
+   uint8_t panel_inst);
 };
 
 struct dmub_psr *dmub_psr_create(struct dc_context *ctx);
-- 
2.25.1

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[PATCH 17/30] drm/amd/display: [FW Promotion] Release 0.0.68

[Stylon Wang]

From: Anthony Koo 

Signed-off-by: Anthony Koo 
Reviewed-by: Anthony Koo 
Acked-by: Stylon Wang 
---
 drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 9 +++--
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h 
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index 6eae16c27b1d..7c95d6eb930a 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -47,10 +47,10 @@
 
 /* Firmware versioning. */
 #ifdef DMUB_EXPOSE_VERSION
-#define DMUB_FW_VERSION_GIT_HASH 0x992f4893d
+#define DMUB_FW_VERSION_GIT_HASH 0xeb3203315
 #define DMUB_FW_VERSION_MAJOR 0
 #define DMUB_FW_VERSION_MINOR 0
-#define DMUB_FW_VERSION_REVISION 66
+#define DMUB_FW_VERSION_REVISION 68
 #define DMUB_FW_VERSION_TEST 0
 #define DMUB_FW_VERSION_VBIOS 0
 #define DMUB_FW_VERSION_HOTFIX 0
@@ -117,8 +117,6 @@
 /* Maximum number of planes on any ASIC. */
 #define DMUB_MAX_PLANES 6
 
-#define DMUB_MAX_SUBVP_STREAMS 2
-
 /* Trace buffer offset for entry */
 #define TRACE_BUFFER_ENTRY_OFFSET  16
 
@@ -1355,7 +1353,7 @@ struct dmub_cmd_psr_set_level_data {
 * 16-bit value dicated by driver that will enable/disable different 
functionality.
 */
uint16_t psr_level;
-   /**
+   /**
 * PSR control version.
 */
uint8_t cmd_version;
@@ -1552,7 +1550,6 @@ enum hw_lock_client {
 * Driver is the client of HW Lock Manager.
 */
HW_LOCK_CLIENT_DRIVER = 0,
-   HW_LOCK_CLIENT_SUBVP = 3,
/**
 * Invalid client.
 */
-- 
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[PATCH 09/30] drm/amd/display: Expand DP module equalization API.

[Stylon Wang]

From: Jimmy Kizito 

[Why & How]
Add functionality useful for DP equalization phase of link training to
public interface.

Signed-off-by: Jimmy Kizito 
Reviewed-by: Jun Lei 
Acked-by: Stylon Wang 
---
 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 22 +--
 .../gpu/drm/amd/display/dc/inc/dc_link_dp.h   |  8 +++
 2 files changed, 19 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 5a70f55e075c..87f955820c0f 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -435,7 +435,7 @@ bool dp_is_cr_done(enum dc_lane_count ln_count,
return true;
 }
 
-static bool is_ch_eq_done(enum dc_lane_count ln_count,
+bool dp_is_ch_eq_done(enum dc_lane_count ln_count,
union lane_status *dpcd_lane_status)
 {
bool done = true;
@@ -446,7 +446,7 @@ static bool is_ch_eq_done(enum dc_lane_count ln_count,
return done;
 }
 
-static bool is_symbol_locked(enum dc_lane_count ln_count,
+bool dp_is_symbol_locked(enum dc_lane_count ln_count,
union lane_status *dpcd_lane_status)
 {
bool locked = true;
@@ -457,7 +457,7 @@ static bool is_symbol_locked(enum dc_lane_count ln_count,
return locked;
 }
 
-static inline bool is_interlane_aligned(union lane_align_status_updated 
align_status)
+bool dp_is_interlane_aligned(union lane_align_status_updated align_status)
 {
return align_status.bits.INTERLANE_ALIGN_DONE == 1;
 }
@@ -865,9 +865,9 @@ static bool perform_post_lt_adj_req_sequence(
if (!dp_is_cr_done(lane_count, dpcd_lane_status))
return false;
 
-   if (!is_ch_eq_done(lane_count, dpcd_lane_status) ||
-   !is_symbol_locked(lane_count, 
dpcd_lane_status) ||
-   
!is_interlane_aligned(dpcd_lane_status_updated))
+   if (!dp_is_ch_eq_done(lane_count, dpcd_lane_status) ||
+   !dp_is_symbol_locked(lane_count, 
dpcd_lane_status) ||
+   
!dp_is_interlane_aligned(dpcd_lane_status_updated))
return false;
 
for (lane = 0; lane < (uint32_t)(lane_count); lane++) {
@@ -913,7 +913,7 @@ static bool perform_post_lt_adj_req_sequence(
 }
 
 /* Only used for channel equalization */
-static uint32_t translate_training_aux_read_interval(uint32_t 
dpcd_aux_read_interval)
+uint32_t dp_translate_training_aux_read_interval(uint32_t 
dpcd_aux_read_interval)
 {
unsigned int aux_rd_interval_us = 400;
 
@@ -998,7 +998,7 @@ static enum link_training_result 
perform_channel_equalization_sequence(
 
if (is_repeater(link, offset))
wait_time_microsec =
-   translate_training_aux_read_interval(
+   dp_translate_training_aux_read_interval(

link->dpcd_caps.lttpr_caps.aux_rd_interval[offset - 1]);
 
dp_wait_for_training_aux_rd_interval(
@@ -1021,9 +1021,9 @@ static enum link_training_result 
perform_channel_equalization_sequence(
return LINK_TRAINING_EQ_FAIL_CR;
 
/* 6. check CHEQ done*/
-   if (is_ch_eq_done(lane_count, dpcd_lane_status) &&
-   is_symbol_locked(lane_count, dpcd_lane_status) 
&&
-   is_interlane_aligned(dpcd_lane_status_updated))
+   if (dp_is_ch_eq_done(lane_count, dpcd_lane_status) &&
+   dp_is_symbol_locked(lane_count, 
dpcd_lane_status) &&
+   
dp_is_interlane_aligned(dpcd_lane_status_updated))
return LINK_TRAINING_SUCCESS;
 
/* 7. update VS/PE/PC2 in lt_settings*/
diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h 
b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
index bbb054f58fe2..883c3af51022 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
@@ -130,6 +130,12 @@ bool dp_is_cr_done(enum dc_lane_count ln_count,
 enum link_training_result dp_get_cr_failure(enum dc_lane_count ln_count,
union lane_status *dpcd_lane_status);
 
+bool dp_is_ch_eq_done(enum dc_lane_count ln_count,
+   union lane_status *dpcd_lane_status);
+bool dp_is_symbol_locked(enum dc_lane_count ln_count,
+   union lane_status *dpcd_lane_status);
+bool dp_is_interlane_aligned(union lane_align_status_updated align_status);
+
 bool dp_is_max_vs_reached(
const struct link_training_settings *lt_settings);
 
@@ -137,6 +143,8 @@ void dp_update_drive_settings(
struct link_training_settings *dest,
struct link_training_settings src);
 
+uint32_

[PATCH 18/30] drm/amd/display: 3.2.138

[Stylon Wang]

From: Aric Cyr 

Signed-off-by: Aric Cyr 
Reviewed-by: Aric Cyr 
Acked-by: Stylon Wang 
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index c0fbcbd4cbfc..356e15c9df60 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -45,7 +45,7 @@
 /* forward declaration */
 struct aux_payload;
 
-#define DC_VER "3.2.137"
+#define DC_VER "3.2.138"
 
 #define MAX_SURFACES 3
 #define MAX_PLANES 6
-- 
2.25.1

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[PATCH 11/30] drm/amd/display: Update scaling settings on modeset

[Stylon Wang]

From: Roman Li 

[Why]
We update scaling settings when scaling mode has been changed.
However when changing mode from native resolution the scaling mode previously
set gets ignored.

[How]
Perform scaling settings update on modeset.

Signed-off-by: Roman Li 
Reviewed-by: Nicholas Kazlauskas 
Acked-by: Stylon Wang 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 09bbec4dab7c..0b12299da93d 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -9737,7 +9737,8 @@ static int dm_update_crtc_state(struct 
amdgpu_display_manager *dm,
BUG_ON(dm_new_crtc_state->stream == NULL);
 
/* Scaling or underscan settings */
-   if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state))
+   if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) ||
+   drm_atomic_crtc_needs_modeset(new_crtc_state))
update_stream_scaling_settings(
&new_crtc_state->mode, dm_new_conn_state, 
dm_new_crtc_state->stream);
 
-- 
2.25.1

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[PATCH 16/30] drm/amd/display: Change default policy for MPO with multidisplay

[Stylon Wang]

From: Aric Cyr 

[Why]
Rearranging pipes with multiple displays and multiple planes cannot be
done atomically and requires a much improved sequence to deal with it.

[How]
To workaround such issues, prefer avoid pipe-split policy for
multidisplay scenarios.

Signed-off-by: Aric Cyr 
Reviewed-by: Krunoslav Kovac 
Acked-by: Stylon Wang 
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c   | 2 +-
 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c   | 2 +-
 drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c | 2 +-
 drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 0d06307456a2..43a6b6cf201e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -1065,7 +1065,7 @@ static const struct dc_debug_options debug_defaults_drv = 
{
.timing_trace = false,
.clock_trace = true,
.disable_pplib_clock_request = true,
-   .pipe_split_policy = MPC_SPLIT_DYNAMIC,
+   .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
.force_single_disp_pipe_split = false,
.disable_dcc = DCC_ENABLE,
.vsr_support = true,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
index 39920422409d..596c97dce67e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
@@ -840,7 +840,7 @@ static const struct dc_debug_options debug_defaults_drv = {
.timing_trace = false,
.clock_trace = true,
.disable_pplib_clock_request = true,
-   .pipe_split_policy = MPC_SPLIT_DYNAMIC,
+   .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
.force_single_disp_pipe_split = false,
.disable_dcc = DCC_ENABLE,
.vsr_support = true,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
index 00cb6d11ed0d..b16d19a25d88 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
@@ -211,7 +211,7 @@ static const struct dc_debug_options debug_defaults_drv = {
.timing_trace = false,
.clock_trace = true,
.disable_pplib_clock_request = true,
-   .pipe_split_policy = MPC_SPLIT_DYNAMIC,
+   .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
.force_single_disp_pipe_split = false,
.disable_dcc = DCC_ENABLE,
.vsr_support = true,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c
index aff0230c9193..758f89ba0192 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c
@@ -193,7 +193,7 @@ static const struct dc_debug_options debug_defaults_drv = {
.timing_trace = false,
.clock_trace = true,
.disable_pplib_clock_request = true,
-   .pipe_split_policy = MPC_SPLIT_DYNAMIC,
+   .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
.force_single_disp_pipe_split = false,
.disable_dcc = DCC_ENABLE,
.vsr_support = true,
-- 
2.25.1

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[PATCH 19/30] drm/amd/display: Add Interface to set FIFO ERRDET SW Override

[Stylon Wang]

From: Wesley Chalmers 

[WHY]
HW has handed down a new sequence which requires access to the FIFO
ERRDET SW Override register.

Signed-off-by: Wesley Chalmers 
Reviewed-by: Dmytro Laktyushkin 
Acked-by: Stylon Wang 
---
 .../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c | 10 +++
 .../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h | 29 +--
 .../gpu/drm/amd/display/dc/dcn21/dcn21_dccg.c |  1 +
 .../gpu/drm/amd/display/dc/dcn30/dcn30_dccg.c |  1 +
 .../drm/amd/display/dc/dcn301/dcn301_dccg.c   |  1 +
 drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h  |  2 ++
 6 files changed, 41 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c
index 8774406120fc..5679983158e2 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c
@@ -96,6 +96,15 @@ void dccg2_get_dccg_ref_freq(struct dccg *dccg,
return;
 }
 
+void dccg2_set_fifo_errdet_ovr_en(struct dccg *dccg,
+   bool en)
+{
+   struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+
+   REG_UPDATE(DISPCLK_FREQ_CHANGE_CNTL,
+   DCCG_FIFO_ERRDET_OVR_EN, en ? 1 : 0);
+}
+
 void dccg2_init(struct dccg *dccg)
 {
 }
@@ -103,6 +112,7 @@ void dccg2_init(struct dccg *dccg)
 static const struct dccg_funcs dccg2_funcs = {
.update_dpp_dto = dccg2_update_dpp_dto,
.get_dccg_ref_freq = dccg2_get_dccg_ref_freq,
+   .set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en,
.dccg_init = dccg2_init
 };
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
index d407f33308b9..7e471c9ed477 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
@@ -34,7 +34,8 @@
DCCG_SRII(DTO_PARAM, DPPCLK, 1),\
DCCG_SRII(DTO_PARAM, DPPCLK, 2),\
DCCG_SRII(DTO_PARAM, DPPCLK, 3),\
-   SR(REFCLK_CNTL)
+   SR(REFCLK_CNTL),\
+   SR(DISPCLK_FREQ_CHANGE_CNTL)
 
 #define DCCG_REG_LIST_DCN2() \
DCCG_COMMON_REG_LIST_DCN_BASE(),\
@@ -59,7 +60,16 @@
DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_PHASE, mask_sh),\
DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_MODULO, mask_sh),\
DCCG_SF(REFCLK_CNTL, REFCLK_CLOCK_EN, mask_sh),\
-   DCCG_SF(REFCLK_CNTL, REFCLK_SRC_SEL, mask_sh)
+   DCCG_SF(REFCLK_CNTL, REFCLK_SRC_SEL, mask_sh),\
+   DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_STEP_DELAY, mask_sh),\
+   DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_STEP_SIZE, mask_sh),\
+   DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_FREQ_RAMP_DONE, mask_sh),\
+   DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_MAX_ERRDET_CYCLES, mask_sh),\
+   DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_RESET, mask_sh),\
+   DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_STATE, mask_sh),\
+   DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_OVR_EN, mask_sh),\
+   DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_CHG_FWD_CORR_DISABLE, mask_sh)
+
 
 #define DCCG_MASK_SH_LIST_DCN2(mask_sh) \
DCCG_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh),\
@@ -74,7 +84,16 @@
type DPPCLK_DTO_ENABLE[6];\
type DPPCLK_DTO_DB_EN[6];\
type REFCLK_CLOCK_EN;\
-   type REFCLK_SRC_SEL;
+   type REFCLK_SRC_SEL;\
+   type DISPCLK_STEP_DELAY;\
+   type DISPCLK_STEP_SIZE;\
+   type DISPCLK_FREQ_RAMP_DONE;\
+   type DISPCLK_MAX_ERRDET_CYCLES;\
+   type DCCG_FIFO_ERRDET_RESET;\
+   type DCCG_FIFO_ERRDET_STATE;\
+   type DCCG_FIFO_ERRDET_OVR_EN;\
+   type DISPCLK_CHG_FWD_CORR_DISABLE;\
+   type DISPCLK_FREQ_CHANGE_CNTL;
 
 #define DCCG3_REG_FIELD_LIST(type) \
type PHYASYMCLK_FORCE_EN;\
@@ -98,6 +117,7 @@ struct dccg_registers {
uint32_t DPPCLK_DTO_CTRL;
uint32_t DPPCLK_DTO_PARAM[6];
uint32_t REFCLK_CNTL;
+   uint32_t DISPCLK_FREQ_CHANGE_CNTL;
uint32_t HDMICHARCLK_CLOCK_CNTL[6];
uint32_t PHYASYMCLK_CLOCK_CNTL;
uint32_t PHYBSYMCLK_CLOCK_CNTL;
@@ -117,6 +137,9 @@ void dccg2_get_dccg_ref_freq(struct dccg *dccg,
unsigned int xtalin_freq_inKhz,
unsigned int *dccg_ref_freq_inKhz);
 
+void dccg2_set_fifo_errdet_ovr_en(struct dccg *dccg,
+   bool en);
+
 void dccg2_init(struct dccg *dccg);
 
 struct dccg *dccg2_create(
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_dccg.c 
b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_dccg.c
index 60cf3ff68cb0..6e1befbb4458 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_dccg.c
@@ -100,6 +100,7 @@ void dccg21_update_dpp_dto(struct dccg *dccg, int dpp_inst, 
int req_dppclk)
 static const struct dccg_funcs dccg21_funcs = {
.update_dpp_dto = dccg21_update_dpp_dto,
.get_dccg_ref_freq = dccg2_get_dccg_ref_freq,
+   .set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_e

[PATCH 25/30] drm/amd/display: Revert "Disconnect non-DP with no EDID"

[Stylon Wang]

From: Roy Chan 

[Why]
Found a use case (IPKVM) that DP-VGA active dongle does
not return any EDID and the mentioned commit broke it.

[How]
This reverts "Disconnect non-DP with no EDID"

Signed-off-by: Roy Chan 
Reviewed-by: Chris Park 
Acked-by: Stylon Wang 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 18 --
 1 file changed, 18 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index d1ade55a8d47..7e699a5bfd24 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1099,24 +1099,6 @@ static bool dc_link_detect_helper(struct dc_link *link,
dc_is_dvi_signal(link->connector_signal)) {
if (prev_sink)
dc_sink_release(prev_sink);
-   link_disconnect_sink(link);
-
-   return false;
-   }
-   /*
-* Abort detection for DP connectors if we have
-* no EDID and connector is active converter
-* as there are no display downstream
-*
-*/
-   if (dc_is_dp_sst_signal(link->connector_signal) &&
-   (link->dpcd_caps.dongle_type ==
-   DISPLAY_DONGLE_DP_VGA_CONVERTER 
||
-   link->dpcd_caps.dongle_type ==
-   
DISPLAY_DONGLE_DP_DVI_CONVERTER)) {
-   if (prev_sink)
-   dc_sink_release(prev_sink);
-   link_disconnect_sink(link);
 
return false;
}
-- 
2.25.1

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[PATCH 24/30] drm/amd/display: Add debugfs entry for dsc passthrough

[Stylon Wang]

From: Fangzhi Zuo 

[Why & How]
Add debugfs entry to force dsc decoding at PCON when DSC capable
external RX is connected. In such case, it is free to test DSC
decoding at external RX or at PCON.

Signed-off-by: Fangzhi Zuo 
Reviewed-by: Hersen Wu 
Acked-by: Stylon Wang 
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h |  1 +
 .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 50 ++-
 2 files changed, 50 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index 7d39dfa7103b..fbec1a52e500 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -456,6 +456,7 @@ struct dsc_preferred_settings {
uint32_t dsc_num_slices_v;
uint32_t dsc_num_slices_h;
uint32_t dsc_bits_per_pixel;
+   bool dsc_force_disable_passthrough;
 };
 
 struct amdgpu_dm_connector {
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index 9fbbd0159119..f1145086a468 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -887,6 +887,47 @@ static int output_bpc_show(struct seq_file *m, void *data)
return res;
 }
 
+/*
+ * Example usage:
+ * Disable dsc passthrough, i.e.,: have dsc decoding at converver, not 
external RX
+ *   echo 1 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough
+ * Enable dsc passthrough, i.e.,: have dsc passthrough to external RX
+ *   echo 0 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough
+ */
+static ssize_t dp_dsc_passthrough_set(struct file *f, const char __user *buf,
+size_t size, loff_t *pos)
+{
+   struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
+   char *wr_buf = NULL;
+   uint32_t wr_buf_size = 42;
+   int max_param_num = 1;
+   long param;
+   uint8_t param_nums = 0;
+
+   if (size == 0)
+   return -EINVAL;
+
+   wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
+
+   if (!wr_buf) {
+   DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
+   return -ENOSPC;
+   }
+
+   if (parse_write_buffer_into_params(wr_buf, size,
+  ¶m, buf,
+  max_param_num,
+  ¶m_nums)) {
+   kfree(wr_buf);
+   return -EINVAL;
+   }
+
+   aconnector->dsc_settings.dsc_force_disable_passthrough = param;
+
+   kfree(wr_buf);
+   return 0;
+}
+
 #ifdef CONFIG_DRM_AMD_DC_HDCP
 /*
  * Returns the HDCP capability of the Display (1.4 for now).
@@ -2535,6 +2576,12 @@ static const struct file_operations 
dp_max_bpc_debugfs_fops = {
.llseek = default_llseek
 };
 
+static const struct file_operations dp_dsc_disable_passthrough_debugfs_fops = {
+   .owner = THIS_MODULE,
+   .write = dp_dsc_passthrough_set,
+   .llseek = default_llseek
+};
+
 static const struct {
char *name;
const struct file_operations *fops;
@@ -2559,7 +2606,8 @@ static const struct {
{"dsc_chunk_size", &dp_dsc_chunk_size_debugfs_fops},
{"dsc_slice_bpg", &dp_dsc_slice_bpg_offset_debugfs_fops},
{"dp_dsc_fec_support", &dp_dsc_fec_support_fops},
-   {"max_bpc", &dp_max_bpc_debugfs_fops}
+   {"max_bpc", &dp_max_bpc_debugfs_fops},
+   {"dsc_disable_passthrough", 
&dp_dsc_disable_passthrough_debugfs_fops},
 };
 
 #ifdef CONFIG_DRM_AMD_DC_HDCP
-- 
2.25.1

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