[PATCH v4 00/17] New uAPI drm properties for color management
Implementation of https://lkml.org/lkml/2021/5/12/764 now feature complete albeit not fully tested. I have not yet corrected the DSC behavior and double checked the dithering behavior. I release the feature complete patch series now anyways so that work on the userspace implementation can start. I have no DP MST splitter at hand. I tried my best to not break anything, but if one who has one could test it would be very helpful. amdgpu in the former implementation was full color range only, albeit there was a path prepared for limited color range on both rgb and ycbcr encoding, which was never selected however. With the Broadcast RGB property, a user can now select this program path. On i915 Broadcast RGB still only affects rgb as ycbcr was and is always limited with this driver, which I didn't change. gma500 driver still uses it's own implementation of the "Broadcast RGB" property, which doesn't have an "Automatic" setting. I too didn't touch this as I can't test a corresponding card. ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH v4 01/17] drm/amd/display: Remove unnecessary SIGNAL_TYPE_HDMI_TYPE_A check
Remove unnecessary SIGNAL_TYPE_HDMI_TYPE_A check that was performed in the drm_mode_is_420_only() case, but not in the drm_mode_is_420_also() && force_yuv420_output case. Without further knowledge if YCbCr 4:2:0 is supported outside of HDMI, there is no reason to use RGB when the display reports drm_mode_is_420_only() even on a non HDMI connection. This patch also moves both checks in the same if-case. This eliminates an extra else-if-case. Signed-off-by: Werner Sembach --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 + 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 6fda0dfb78f8..44757720b15f 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -5353,10 +5353,7 @@ static void fill_stream_properties_from_drm_display_mode( timing_out->v_border_bottom = 0; /* TODO: un-hardcode */ if (drm_mode_is_420_only(info, mode_in) - && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) - timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; - else if (drm_mode_is_420_also(info, mode_in) - && aconnector->force_yuv420_output) + || (drm_mode_is_420_also(info, mode_in) && aconnector->force_yuv420_output)) timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444) && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH v4 03/17] drm/uAPI: Add "active bpc" as feedback channel for "max bpc" drm property
Add a new general drm property "active bpc" which can be used by graphic
drivers to report the applied bit depth per pixel back to userspace.
While "max bpc" can be used to change the color depth, there was no way to
check which one actually got used. While in theory the driver chooses the
best/highest color depth within the max bpc setting a user might not be
fully aware what his hardware is or isn't capable off. This is meant as a
quick way to double check the setup.
In the future, automatic color calibration for screens might also depend on
this information being available.
Signed-off-by: Werner Sembach
---
drivers/gpu/drm/drm_connector.c | 51 +
include/drm/drm_connector.h | 8 ++
2 files changed, 59 insertions(+)
diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index da39e7ff6965..943f6b61053b 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -1197,6 +1197,14 @@ static const struct drm_prop_enum_list dp_colorspaces[]
= {
* drm_connector_attach_max_bpc_property() to create and attach the
* property to the connector during initialization.
*
+ * active bpc:
+ * This read-only range property tells userspace the pixel color bit depth
+ * actually used by the hardware display engine on "the cable" on a
+ * connector. The chosen value depends on hardware capabilities, both
+ * display engine and connected monitor, and the "max bpc" property.
+ * Drivers shall use drm_connector_attach_active_bpc_property() to install
+ * this property.
+ *
* Connectors also have one standardized atomic property:
*
* CRTC_ID:
@@ -2152,6 +2160,49 @@ int drm_connector_attach_max_bpc_property(struct
drm_connector *connector,
}
EXPORT_SYMBOL(drm_connector_attach_max_bpc_property);
+/**
+ * drm_connector_attach_active_bpc_property - attach "active bpc" property
+ * @connector: connector to attach active bpc property on.
+ * @min: The minimum bit depth supported by the connector.
+ * @max: The maximum bit depth supported by the connector.
+ *
+ * This is used to check the applied bit depth on a connector.
+ *
+ * Returns:
+ * Zero on success, negative errno on failure.
+ */
+int drm_connector_attach_active_bpc_property(struct drm_connector *connector,
int min, int max)
+{
+ struct drm_device *dev = connector->dev;
+ struct drm_property *prop;
+
+ if (!connector->active_bpc_property) {
+ prop = drm_property_create_range(dev, DRM_MODE_PROP_IMMUTABLE,
"active bpc",
+min, max);
+ if (!prop)
+ return -ENOMEM;
+
+ connector->active_bpc_property = prop;
+ drm_object_attach_property(&connector->base, prop, 0);
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_connector_attach_active_bpc_property);
+
+/**
+ * drm_connector_set_active_bpc_property - sets the active bits per color
property for a connector
+ * @connector: drm connector
+ * @active_bpc: bits per color for the connector currently active on "the
cable"
+ *
+ * Should be used by atomic drivers to update the active bits per color over a
connector.
+ */
+void drm_connector_set_active_bpc_property(struct drm_connector *connector,
int active_bpc)
+{
+ drm_object_property_set_value(&connector->base,
connector->active_bpc_property, active_bpc);
+}
+EXPORT_SYMBOL(drm_connector_set_active_bpc_property);
+
/**
* drm_connector_attach_hdr_output_metadata_property - attach
"HDR_OUTPUT_METADA" property
* @connector: connector to attach the property on.
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index 714d1a01c065..eee86de62a5f 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -1380,6 +1380,12 @@ struct drm_connector {
*/
struct drm_property *max_bpc_property;
+ /**
+* @active_bpc_property: Default connector property for the active bpc
+* to be driven out of the connector.
+*/
+ struct drm_property *active_bpc_property;
+
#define DRM_CONNECTOR_POLL_HPD (1 << 0)
#define DRM_CONNECTOR_POLL_CONNECT (1 << 1)
#define DRM_CONNECTOR_POLL_DISCONNECT (1 << 2)
@@ -1702,6 +1708,8 @@ int drm_connector_set_panel_orientation_with_quirk(
int width, int height);
int drm_connector_attach_max_bpc_property(struct drm_connector *connector,
int min, int max);
+int drm_connector_attach_active_bpc_property(struct drm_connector *connector,
int min, int max);
+void drm_connector_set_active_bpc_property(struct drm_connector *connector,
int active_bpc);
/**
* struct drm_tile_group - Tile group metadata
--
2.25.1
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[PATCH v4 04/17] drm/amd/display: Add handling for new "active bpc" property
This commit implements the "active bpc" drm property for the AMD GPU
driver.
Signed-off-by: Werner Sembach
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 19 ++-
.../display/amdgpu_dm/amdgpu_dm_mst_types.c | 4
2 files changed, 22 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index cd1df5cf4815..b6293b3104ed 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -7713,8 +7713,10 @@ void amdgpu_dm_connector_init_helper(struct
amdgpu_display_manager *dm,
adev->mode_info.underscan_vborder_property,
0);
- if (!aconnector->mst_port)
+ if (!aconnector->mst_port) {
drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16);
+ drm_connector_attach_active_bpc_property(&aconnector->base, 8,
16);
+ }
/* This defaults to the max in the range, but we want 8bpc for non-edp.
*/
aconnector->base.state->max_bpc = (connector_type ==
DRM_MODE_CONNECTOR_eDP) ? 16 : 8;
@@ -9083,6 +9085,21 @@ static void amdgpu_dm_atomic_commit_tail(struct
drm_atomic_state *state)
mutex_unlock(&dm->dc_lock);
}
+ /* Extract information from crtc to communicate it to userspace as
connector properties */
+ for_each_new_connector_in_state(state, connector, new_con_state, i) {
+ struct drm_crtc *crtc = new_con_state->crtc;
+
+ if (crtc) {
+ new_crtc_state = drm_atomic_get_new_crtc_state(state,
crtc);
+ dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
+ if (dm_new_crtc_state->stream)
+ drm_connector_set_active_bpc_property(connector,
+ convert_dc_color_depth_into_bpc(
+
dm_new_crtc_state->stream->timing.display_color_depth));
+ } else
+ drm_connector_set_active_bpc_property(connector, 0);
+ }
+
/* Count number of newly disabled CRTCs for dropping PM refs later. */
for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
new_crtc_state, i) {
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 5568d4e518e6..0cf38743ec47 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -409,6 +409,10 @@ dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr
*mgr,
if (connector->max_bpc_property)
drm_connector_attach_max_bpc_property(connector, 8, 16);
+ connector->active_bpc_property = master->base.active_bpc_property;
+ if (connector->active_bpc_property)
+ drm_connector_attach_active_bpc_property(&aconnector->base, 8,
16);
+
connector->vrr_capable_property = master->base.vrr_capable_property;
if (connector->vrr_capable_property)
drm_connector_attach_vrr_capable_property(connector);
--
2.25.1
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[PATCH v4 02/17] drm/amd/display: Add missing cases convert_dc_color_depth_into_bpc
convert_dc_color_depth_into_bpc() that converts the enum dc_color_depth to an integer had the casses for COLOR_DEPTH_999 and COLOR_DEPTH_11 missing. Signed-off-by: Werner Sembach --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 44757720b15f..cd1df5cf4815 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -6705,6 +6705,10 @@ static int convert_dc_color_depth_into_bpc (enum dc_color_depth display_color_de return 14; case COLOR_DEPTH_161616: return 16; + case COLOR_DEPTH_999: + return 9; + case COLOR_DEPTH_11: + return 11; default: break; } -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH v4 06/17] drm/uAPI: Add "active color format" drm property as feedback for userspace
Add a new general drm property "active color format" which can be used by
graphic drivers to report the used color format back to userspace.
There was no way to check which color format got actually used on a given
monitor. To surely predict this, one must know the exact capabilities of
the monitor, the GPU, and the connection used and what the default
behaviour of the used driver is (e.g. amdgpu prefers YCbCr 4:4:4 while i915
prefers RGB). This property helps eliminating the guessing on this point.
In the future, automatic color calibration for screens might also depend on
this information being available.
Signed-off-by: Werner Sembach
---
drivers/gpu/drm/drm_connector.c | 61 +
include/drm/drm_connector.h | 9 +
2 files changed, 70 insertions(+)
diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index 943f6b61053b..684d7abdf0eb 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -889,6 +889,14 @@ static const struct drm_prop_enum_list
drm_dp_subconnector_enum_list[] = {
{ DRM_MODE_SUBCONNECTOR_Native, "Native"}, /* DP */
};
+static const struct drm_prop_enum_list drm_active_color_format_enum_list[] = {
+ { 0, "unknown" },
+ { DRM_COLOR_FORMAT_RGB444, "rgb" },
+ { DRM_COLOR_FORMAT_YCRCB444, "ycbcr444" },
+ { DRM_COLOR_FORMAT_YCRCB422, "ycbcr422" },
+ { DRM_COLOR_FORMAT_YCRCB420, "ycbcr420" },
+};
+
DRM_ENUM_NAME_FN(drm_get_dp_subconnector_name,
drm_dp_subconnector_enum_list)
@@ -1205,6 +1213,14 @@ static const struct drm_prop_enum_list dp_colorspaces[]
= {
* Drivers shall use drm_connector_attach_active_bpc_property() to install
* this property.
*
+ * active color format:
+ * This read-only property tells userspace the color format actually used
+ * by the hardware display engine on "the cable" on a connector. The chosen
+ * value depends on hardware capabilities, both display engine and
+ * connected monitor. Drivers shall use
+ * drm_connector_attach_active_color_format_property() to install this
+ * property.
+ *
* Connectors also have one standardized atomic property:
*
* CRTC_ID:
@@ -2203,6 +2219,51 @@ void drm_connector_set_active_bpc_property(struct
drm_connector *connector, int
}
EXPORT_SYMBOL(drm_connector_set_active_bpc_property);
+/**
+ * drm_connector_attach_active_color_format_property - attach "active color
format" property
+ * @connector: connector to attach active color format property on.
+ *
+ * This is used to check the applied color format on a connector.
+ *
+ * Returns:
+ * Zero on success, negative errno on failure.
+ */
+int drm_connector_attach_active_color_format_property(struct drm_connector
*connector)
+{
+ struct drm_device *dev = connector->dev;
+ struct drm_property *prop;
+
+ if (!connector->active_color_format_property) {
+ prop = drm_property_create_enum(dev, DRM_MODE_PROP_IMMUTABLE,
"active color format",
+
drm_active_color_format_enum_list,
+
ARRAY_SIZE(drm_active_color_format_enum_list));
+ if (!prop)
+ return -ENOMEM;
+
+ connector->active_color_format_property = prop;
+ drm_object_attach_property(&connector->base, prop, 0);
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_connector_attach_active_color_format_property);
+
+/**
+ * drm_connector_set_active_color_format_property - sets the active color
format property for a
+ * connector
+ * @connector: drm connector
+ * @active_color_format: color format for the connector currently active on
"the cable"
+ *
+ * Should be used by atomic drivers to update the active color format over a
connector.
+ */
+void drm_connector_set_active_color_format_property(struct drm_connector
*connector,
+ u32 active_color_format)
+{
+ drm_object_property_set_value(&connector->base,
connector->active_color_format_property,
+ active_color_format);
+}
+EXPORT_SYMBOL(drm_connector_set_active_color_format_property);
+
/**
* drm_connector_attach_hdr_output_metadata_property - attach
"HDR_OUTPUT_METADA" property
* @connector: connector to attach the property on.
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index eee86de62a5f..8a5197f14e87 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -1386,6 +1386,12 @@ struct drm_connector {
*/
struct drm_property *active_bpc_property;
+ /**
+* @active_color_format_property: Default connector property for the
+* active color format to be driven out of the connector.
+*/
+ struct drm_property *active_color_format_property;
+
#define DRM_CONNECTOR_POLL_HPD (1 << 0)
#define DRM_CONN
[PATCH v4 05/17] drm/i915/display: Add handling for new "active bpc" property
This commit implements the "active bpc" drm property for the Intel GPU
driver.
Signed-off-by: Werner Sembach
---
drivers/gpu/drm/i915/display/intel_display.c | 17 +
drivers/gpu/drm/i915/display/intel_dp.c | 7 +--
drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 +
drivers/gpu/drm/i915/display/intel_hdmi.c| 4 +++-
4 files changed, 30 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 6be1b31af07b..4b00d2f3b3c8 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -10839,6 +10839,9 @@ static int intel_atomic_commit(struct drm_device *dev,
{
struct intel_atomic_state *state = to_intel_atomic_state(_state);
struct drm_i915_private *dev_priv = to_i915(dev);
+ struct drm_connector *connector;
+ struct drm_connector_state *new_conn_state;
+ int i;
int ret = 0;
state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
@@ -10907,6 +10910,20 @@ static int intel_atomic_commit(struct drm_device *dev,
intel_shared_dpll_swap_state(state);
intel_atomic_track_fbs(state);
+ /* Extract information from crtc to communicate it to userspace as
connector properties */
+ for_each_new_connector_in_state(&state->base, connector,
new_conn_state, i) {
+ struct intel_crtc *crtc = to_intel_crtc(new_conn_state->crtc);
+
+ if (crtc) {
+ struct intel_crtc_state *new_crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+
+ drm_connector_set_active_bpc_property(connector,
+ new_crtc_state->pipe_bpp / 3);
+ } else
+ drm_connector_set_active_bpc_property(connector, 0);
+ }
+
drm_atomic_state_get(&state->base);
INIT_WORK(&state->base.commit_work, intel_atomic_commit_work);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 5c983044..2d7b5318ae7b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4688,10 +4688,13 @@ intel_dp_add_properties(struct intel_dp *intel_dp,
struct drm_connector *connect
intel_attach_force_audio_property(connector);
intel_attach_broadcast_rgb_property(connector);
- if (HAS_GMCH(dev_priv))
+ if (HAS_GMCH(dev_priv)) {
drm_connector_attach_max_bpc_property(connector, 6, 10);
- else if (DISPLAY_VER(dev_priv) >= 5)
+ drm_connector_attach_active_bpc_property(connector, 6, 10);
+ } else if (DISPLAY_VER(dev_priv) >= 5) {
drm_connector_attach_max_bpc_property(connector, 6, 12);
+ drm_connector_attach_active_bpc_property(connector, 6, 12);
+ }
/* Register HDMI colorspace for case of lspcon */
if (intel_bios_is_lspcon_present(dev_priv, port)) {
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index b170e272bdee..16bfc59570a5 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -851,6 +851,11 @@ static struct drm_connector
*intel_dp_add_mst_connector(struct drm_dp_mst_topolo
if (connector->max_bpc_property)
drm_connector_attach_max_bpc_property(connector, 6, 12);
+ connector->active_bpc_property =
+ intel_dp->attached_connector->base.active_bpc_property;
+ if (connector->active_bpc_property)
+ drm_connector_attach_active_bpc_property(connector, 6, 12);
+
return connector;
err:
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 7e51c98c475e..9160e21ac9d6 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2513,8 +2513,10 @@ intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi,
struct drm_connector *c
if (DISPLAY_VER(dev_priv) >= 10)
drm_connector_attach_hdr_output_metadata_property(connector);
- if (!HAS_GMCH(dev_priv))
+ if (!HAS_GMCH(dev_priv)) {
drm_connector_attach_max_bpc_property(connector, 8, 12);
+ drm_connector_attach_active_bpc_property(connector, 8, 12);
+ }
}
/*
--
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[PATCH v4 08/17] drm/i915/display: Add handling for new "active color format" property
This commit implements the "active color format" drm property for the Intel
GPU driver.
Signed-off-by: Werner Sembach
---
drivers/gpu/drm/i915/display/intel_display.c | 22 +++-
drivers/gpu/drm/i915/display/intel_dp.c | 2 ++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 +
drivers/gpu/drm/i915/display/intel_hdmi.c| 1 +
4 files changed, 29 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 4b00d2f3b3c8..57bec7f452d8 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -10609,6 +10609,21 @@ static void
intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *s
}
}
+static int convert_intel_output_format_into_drm_color_format(enum
intel_output_format output_format)
+{
+ switch (output_format) {
+ case INTEL_OUTPUT_FORMAT_RGB:
+ return DRM_COLOR_FORMAT_RGB444;
+ case INTEL_OUTPUT_FORMAT_YCBCR420:
+ return DRM_COLOR_FORMAT_YCRCB420;
+ case INTEL_OUTPUT_FORMAT_YCBCR444:
+ return DRM_COLOR_FORMAT_YCRCB444;
+ default:
+ break;
+ }
+ return 0;
+}
+
static void intel_atomic_commit_tail(struct intel_atomic_state *state)
{
struct drm_device *dev = state->base.dev;
@@ -10920,8 +10935,13 @@ static int intel_atomic_commit(struct drm_device *dev,
drm_connector_set_active_bpc_property(connector,
new_crtc_state->pipe_bpp / 3);
- } else
+
drm_connector_set_active_color_format_property(connector,
+
convert_intel_output_format_into_drm_color_format(
+ new_crtc_state->output_format));
+ } else {
drm_connector_set_active_bpc_property(connector, 0);
+
drm_connector_set_active_color_format_property(connector, 0);
+ }
}
drm_atomic_state_get(&state->base);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 2d7b5318ae7b..9204bc14590a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4691,9 +4691,11 @@ intel_dp_add_properties(struct intel_dp *intel_dp,
struct drm_connector *connect
if (HAS_GMCH(dev_priv)) {
drm_connector_attach_max_bpc_property(connector, 6, 10);
drm_connector_attach_active_bpc_property(connector, 6, 10);
+ drm_connector_attach_active_color_format_property(connector);
} else if (DISPLAY_VER(dev_priv) >= 5) {
drm_connector_attach_max_bpc_property(connector, 6, 12);
drm_connector_attach_active_bpc_property(connector, 6, 12);
+ drm_connector_attach_active_color_format_property(connector);
}
/* Register HDMI colorspace for case of lspcon */
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 16bfc59570a5..3e4237df3360 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -856,6 +856,11 @@ static struct drm_connector
*intel_dp_add_mst_connector(struct drm_dp_mst_topolo
if (connector->active_bpc_property)
drm_connector_attach_active_bpc_property(connector, 6, 12);
+ connector->active_color_format_property =
+ intel_dp->attached_connector->base.active_color_format_property;
+ if (connector->active_color_format_property)
+ drm_connector_attach_active_color_format_property(connector);
+
return connector;
err:
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 9160e21ac9d6..367aba57b55f 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2516,6 +2516,7 @@ intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi,
struct drm_connector *c
if (!HAS_GMCH(dev_priv)) {
drm_connector_attach_max_bpc_property(connector, 8, 12);
drm_connector_attach_active_bpc_property(connector, 8, 12);
+ drm_connector_attach_active_color_format_property(connector);
}
}
--
2.25.1
___
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH v4 07/17] drm/amd/display: Add handling for new "active color format" property
This commit implements the "active color format" drm property for the AMD
GPU driver.
Signed-off-by: Werner Sembach
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 29 +--
.../display/amdgpu_dm/amdgpu_dm_mst_types.c | 4 +++
2 files changed, 31 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index b6293b3104ed..5086d6d74bf6 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -6715,6 +6715,24 @@ static int convert_dc_color_depth_into_bpc (enum
dc_color_depth display_color_de
return 0;
}
+static int convert_dc_pixel_encoding_into_drm_color_format(
+ enum dc_pixel_encoding display_pixel_encoding)
+{
+ switch (display_pixel_encoding) {
+ case PIXEL_ENCODING_RGB:
+ return DRM_COLOR_FORMAT_RGB444;
+ case PIXEL_ENCODING_YCBCR422:
+ return DRM_COLOR_FORMAT_YCRCB422;
+ case PIXEL_ENCODING_YCBCR444:
+ return DRM_COLOR_FORMAT_YCRCB444;
+ case PIXEL_ENCODING_YCBCR420:
+ return DRM_COLOR_FORMAT_YCRCB420;
+ default:
+ break;
+ }
+ return 0;
+}
+
static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
struct drm_crtc_state *crtc_state,
struct drm_connector_state
*conn_state)
@@ -7716,6 +7734,7 @@ void amdgpu_dm_connector_init_helper(struct
amdgpu_display_manager *dm,
if (!aconnector->mst_port) {
drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16);
drm_connector_attach_active_bpc_property(&aconnector->base, 8,
16);
+
drm_connector_attach_active_color_format_property(&aconnector->base);
}
/* This defaults to the max in the range, but we want 8bpc for non-edp.
*/
@@ -9092,12 +9111,18 @@ static void amdgpu_dm_atomic_commit_tail(struct
drm_atomic_state *state)
if (crtc) {
new_crtc_state = drm_atomic_get_new_crtc_state(state,
crtc);
dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
- if (dm_new_crtc_state->stream)
+ if (dm_new_crtc_state->stream) {
drm_connector_set_active_bpc_property(connector,
convert_dc_color_depth_into_bpc(
dm_new_crtc_state->stream->timing.display_color_depth));
- } else
+
drm_connector_set_active_color_format_property(connector,
+
convert_dc_pixel_encoding_into_drm_color_format(
+
dm_new_crtc_state->stream->timing.pixel_encoding));
+ }
+ } else {
drm_connector_set_active_bpc_property(connector, 0);
+
drm_connector_set_active_color_format_property(connector, 0);
+ }
}
/* Count number of newly disabled CRTCs for dropping PM refs later. */
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 0cf38743ec47..13151d13aa73 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -413,6 +413,10 @@ dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr
*mgr,
if (connector->active_bpc_property)
drm_connector_attach_active_bpc_property(&aconnector->base, 8,
16);
+ connector->active_color_format_property =
master->base.active_color_format_property;
+ if (connector->active_color_format_property)
+
drm_connector_attach_active_color_format_property(&aconnector->base);
+
connector->vrr_capable_property = master->base.vrr_capable_property;
if (connector->vrr_capable_property)
drm_connector_attach_vrr_capable_property(connector);
--
2.25.1
___
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH v4 09/17] drm/uAPI: Add "active color range" drm property as feedback for userspace
Add a new general drm property "active color range" which can be used by
graphic drivers to report the used color range back to userspace.
There was no way to check which color range got actually used on a given
monitor. To surely predict this, one must know the exact capabilities of
the monitor and what the default behaviour of the used driver is. This
property helps eliminating the guessing at this point.
In the future, automatic color calibration for screens might also depend on
this information being available.
Signed-off-by: Werner Sembach
---
drivers/gpu/drm/drm_connector.c | 59 +
include/drm/drm_connector.h | 27 +++
2 files changed, 86 insertions(+)
diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index 684d7abdf0eb..818de58d972f 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -897,6 +897,12 @@ static const struct drm_prop_enum_list
drm_active_color_format_enum_list[] = {
{ DRM_COLOR_FORMAT_YCRCB420, "ycbcr420" },
};
+static const struct drm_prop_enum_list drm_active_color_range_enum_list[] = {
+ { DRM_MODE_COLOR_RANGE_UNSET, "Unknown" },
+ { DRM_MODE_COLOR_RANGE_FULL, "Full" },
+ { DRM_MODE_COLOR_RANGE_LIMITED_16_235, "Limited 16:235" },
+};
+
DRM_ENUM_NAME_FN(drm_get_dp_subconnector_name,
drm_dp_subconnector_enum_list)
@@ -1221,6 +1227,14 @@ static const struct drm_prop_enum_list dp_colorspaces[]
= {
* drm_connector_attach_active_color_format_property() to install this
* property.
*
+ * active color range:
+ * This read-only property tells userspace the color range actually used by
+ * the hardware display engine on "the cable" on a connector. The chosen
+ * value depends on hardware capabilities of the monitor and the used color
+ * format. Drivers shall use
+ * drm_connector_attach_active_color_range_property() to install this
+ * property.
+ *
* Connectors also have one standardized atomic property:
*
* CRTC_ID:
@@ -2264,6 +2278,51 @@ void
drm_connector_set_active_color_format_property(struct drm_connector *connec
}
EXPORT_SYMBOL(drm_connector_set_active_color_format_property);
+/**
+ * drm_connector_attach_active_color_range_property - attach "active color
range" property
+ * @connector: connector to attach active color range property on.
+ *
+ * This is used to check the applied color range on a connector.
+ *
+ * Returns:
+ * Zero on success, negative errno on failure.
+ */
+int drm_connector_attach_active_color_range_property(struct drm_connector
*connector)
+{
+ struct drm_device *dev = connector->dev;
+ struct drm_property *prop;
+
+ if (!connector->active_color_range_property) {
+ prop = drm_property_create_enum(dev, DRM_MODE_PROP_IMMUTABLE,
"active color range",
+
drm_active_color_range_enum_list,
+
ARRAY_SIZE(drm_active_color_range_enum_list));
+ if (!prop)
+ return -ENOMEM;
+
+ connector->active_color_range_property = prop;
+ drm_object_attach_property(&connector->base, prop,
DRM_MODE_COLOR_RANGE_UNSET);
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_connector_attach_active_color_range_property);
+
+/**
+ * drm_connector_set_active_color_range_property - sets the active color range
property for a
+ * connector
+ * @connector: drm connector
+ * @active_color_range: color range for the connector currently active on "the
cable"
+ *
+ * Should be used by atomic drivers to update the active color range over a
connector.
+ */
+void drm_connector_set_active_color_range_property(struct drm_connector
*connector,
+ enum drm_mode_color_range
active_color_range)
+{
+ drm_object_property_set_value(&connector->base,
connector->active_color_range_property,
+ active_color_range);
+}
+EXPORT_SYMBOL(drm_connector_set_active_color_range_property);
+
/**
* drm_connector_attach_hdr_output_metadata_property - attach
"HDR_OUTPUT_METADA" property
* @connector: connector to attach the property on.
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index 8a5197f14e87..9fb7119b7a02 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -648,6 +648,24 @@ struct drm_tv_connector_state {
unsigned int hue;
};
+/**
+ * enum drm_mode_color_range - color_range info for &drm_connector
+ *
+ * This enum is used to represent full or limited color range on the display
+ * connector signal.
+ *
+ * @DRM_MODE_COLOR_RANGE_UNSET:Color range is
unspecified/default.
+ * @DRM_MODE_COLOR_RANGE_FULL: Color range is full range, 0-255 for
+ * 8-Bit color depth.
+ * DRM_MODE_COLOR_RANGE_LIMITED_16_235:
[PATCH v4 10/17] drm/amd/display: Add handling for new "active color range" property
This commit implements the "active color range" drm property for the AMD
GPU driver.
Signed-off-by: Werner Sembach
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 33 +++
.../display/amdgpu_dm/amdgpu_dm_mst_types.c | 4 +++
2 files changed, 37 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 5086d6d74bf6..bce47f28e20a 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -6733,6 +6733,33 @@ static int
convert_dc_pixel_encoding_into_drm_color_format(
return 0;
}
+static int convert_dc_color_space_into_drm_mode_color_range(enum
dc_color_space color_space)
+{
+ if (color_space == COLOR_SPACE_SRGB ||
+ color_space == COLOR_SPACE_XR_RGB ||
+ color_space == COLOR_SPACE_MSREF_SCRGB ||
+ color_space == COLOR_SPACE_2020_RGB_FULLRANGE ||
+ color_space == COLOR_SPACE_ADOBERGB ||
+ color_space == COLOR_SPACE_DCIP3 ||
+ color_space == COLOR_SPACE_DOLBYVISION ||
+ color_space == COLOR_SPACE_YCBCR601 ||
+ color_space == COLOR_SPACE_XV_YCC_601 ||
+ color_space == COLOR_SPACE_YCBCR709 ||
+ color_space == COLOR_SPACE_XV_YCC_709 ||
+ color_space == COLOR_SPACE_2020_YCBCR ||
+ color_space == COLOR_SPACE_YCBCR709_BLACK ||
+ color_space == COLOR_SPACE_DISPLAYNATIVE ||
+ color_space == COLOR_SPACE_APPCTRL ||
+ color_space == COLOR_SPACE_CUSTOMPOINTS)
+ return DRM_MODE_COLOR_RANGE_FULL;
+ if (color_space == COLOR_SPACE_SRGB_LIMITED ||
+ color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE ||
+ color_space == COLOR_SPACE_YCBCR601_LIMITED ||
+ color_space == COLOR_SPACE_YCBCR709_LIMITED)
+ return DRM_MODE_COLOR_RANGE_LIMITED_16_235;
+ return DRM_MODE_COLOR_RANGE_UNSET;
+}
+
static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
struct drm_crtc_state *crtc_state,
struct drm_connector_state
*conn_state)
@@ -7735,6 +7762,7 @@ void amdgpu_dm_connector_init_helper(struct
amdgpu_display_manager *dm,
drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16);
drm_connector_attach_active_bpc_property(&aconnector->base, 8,
16);
drm_connector_attach_active_color_format_property(&aconnector->base);
+
drm_connector_attach_active_color_range_property(&aconnector->base);
}
/* This defaults to the max in the range, but we want 8bpc for non-edp.
*/
@@ -9118,10 +9146,15 @@ static void amdgpu_dm_atomic_commit_tail(struct
drm_atomic_state *state)
drm_connector_set_active_color_format_property(connector,
convert_dc_pixel_encoding_into_drm_color_format(
dm_new_crtc_state->stream->timing.pixel_encoding));
+
drm_connector_set_active_color_range_property(connector,
+
convert_dc_color_space_into_drm_mode_color_range(
+
dm_new_crtc_state->stream->output_color_space));
}
} else {
drm_connector_set_active_bpc_property(connector, 0);
drm_connector_set_active_color_format_property(connector, 0);
+ drm_connector_set_active_color_range_property(connector,
+
DRM_MODE_COLOR_RANGE_UNSET);
}
}
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 13151d13aa73..b5d57bbbdd20 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -417,6 +417,10 @@ dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr
*mgr,
if (connector->active_color_format_property)
drm_connector_attach_active_color_format_property(&aconnector->base);
+ connector->active_color_range_property =
master->base.active_color_range_property;
+ if (connector->active_color_range_property)
+
drm_connector_attach_active_color_range_property(&aconnector->base);
+
connector->vrr_capable_property = master->base.vrr_capable_property;
if (connector->vrr_capable_property)
drm_connector_attach_vrr_capable_property(connector);
--
2.25.1
___
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH v4 12/17] drm/uAPI: Add "preferred color format" drm property as setting for userspace
Add a new general drm property "preferred color format" which can be used
by userspace to tell the graphic drivers to which color format to use.
Possible options are:
- auto (default/current behaviour)
- rgb
- ycbcr444
- ycbcr422 (not supported by both amdgpu and i915)
- ycbcr420
In theory the auto option should choose the best available option for the
current setup, but because of bad internal conversion some monitors look
better with rgb and some with ycbcr444.
Also, because of bad shielded connectors and/or cables, it might be
preferable to use the less bandwidth heavy ycbcr422 and ycbcr420 formats
for a signal that is less deceptible to interference.
In the future, automatic color calibration for screens might also depend on
this option being available.
Signed-off-by: Werner Sembach
---
drivers/gpu/drm/drm_atomic_helper.c | 4 +++
drivers/gpu/drm/drm_atomic_uapi.c | 4 +++
drivers/gpu/drm/drm_connector.c | 48 -
include/drm/drm_connector.h | 17 ++
4 files changed, 72 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_atomic_helper.c
b/drivers/gpu/drm/drm_atomic_helper.c
index bc3487964fb5..90d62f305257 100644
--- a/drivers/gpu/drm/drm_atomic_helper.c
+++ b/drivers/gpu/drm/drm_atomic_helper.c
@@ -687,6 +687,10 @@ drm_atomic_helper_check_modeset(struct drm_device *dev,
if (old_connector_state->max_requested_bpc !=
new_connector_state->max_requested_bpc)
new_crtc_state->connectors_changed = true;
+
+ if (old_connector_state->preferred_color_format !=
+ new_connector_state->preferred_color_format)
+ new_crtc_state->connectors_changed = true;
}
if (funcs->atomic_check)
diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
b/drivers/gpu/drm/drm_atomic_uapi.c
index 438e9585b225..c536f5e22016 100644
--- a/drivers/gpu/drm/drm_atomic_uapi.c
+++ b/drivers/gpu/drm/drm_atomic_uapi.c
@@ -796,6 +796,8 @@ static int drm_atomic_connector_set_property(struct
drm_connector *connector,
fence_ptr);
} else if (property == connector->max_bpc_property) {
state->max_requested_bpc = val;
+ } else if (property == connector->preferred_color_format_property) {
+ state->preferred_color_format = val;
} else if (connector->funcs->atomic_set_property) {
return connector->funcs->atomic_set_property(connector,
state, property, val);
@@ -873,6 +875,8 @@ drm_atomic_connector_get_property(struct drm_connector
*connector,
*val = 0;
} else if (property == connector->max_bpc_property) {
*val = state->max_requested_bpc;
+ } else if (property == connector->preferred_color_format_property) {
+ *val = state->preferred_color_format;
} else if (connector->funcs->atomic_get_property) {
return connector->funcs->atomic_get_property(connector,
state, property, val);
diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index 818de58d972f..aea03dd02e33 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -889,6 +889,14 @@ static const struct drm_prop_enum_list
drm_dp_subconnector_enum_list[] = {
{ DRM_MODE_SUBCONNECTOR_Native, "Native"}, /* DP */
};
+static const struct drm_prop_enum_list drm_preferred_color_format_enum_list[]
= {
+ { 0, "auto" },
+ { DRM_COLOR_FORMAT_RGB444, "rgb" },
+ { DRM_COLOR_FORMAT_YCRCB444, "ycbcr444" },
+ { DRM_COLOR_FORMAT_YCRCB422, "ycbcr422" },
+ { DRM_COLOR_FORMAT_YCRCB420, "ycbcr420" },
+};
+
static const struct drm_prop_enum_list drm_active_color_format_enum_list[] = {
{ 0, "unknown" },
{ DRM_COLOR_FORMAT_RGB444, "rgb" },
@@ -1219,11 +1227,19 @@ static const struct drm_prop_enum_list dp_colorspaces[]
= {
* Drivers shall use drm_connector_attach_active_bpc_property() to install
* this property.
*
+ * preferred color format:
+ * This property is used by userspace to change the used color format. When
+ * used the driver will use the selected format if valid for the hardware,
+ * sink, and current resolution and refresh rate combination. Drivers to
+ * use the function drm_connector_attach_preferred_color_format_property()
+ * to create and attach the property to the connector during
+ * initialization.
+ *
* active color format:
* This read-only property tells userspace the color format actually used
* by the hardware display engine on "the cable" on a connector. The chosen
* value depends on hardware capabilities, both display engine and
- * connected monitor. Drivers shall use
+ * connected
[PATCH v4 11/17] drm/i915/display: Add handling for new "active color range" property
This commit implements the "active color range" drm property for the Intel
GPU driver.
Signed-off-by: Werner Sembach
---
drivers/gpu/drm/i915/display/intel_display.c | 6 ++
drivers/gpu/drm/i915/display/intel_dp.c | 2 ++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 +
drivers/gpu/drm/i915/display/intel_hdmi.c| 1 +
4 files changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 57bec7f452d8..3d0bdca70c6a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -10938,9 +10938,15 @@ static int intel_atomic_commit(struct drm_device *dev,
drm_connector_set_active_color_format_property(connector,
convert_intel_output_format_into_drm_color_format(
new_crtc_state->output_format));
+ drm_connector_set_active_color_range_property(connector,
+ new_crtc_state->limited_color_range ?
+ DRM_MODE_COLOR_RANGE_LIMITED_16_235 :
+ DRM_MODE_COLOR_RANGE_FULL);
} else {
drm_connector_set_active_bpc_property(connector, 0);
drm_connector_set_active_color_format_property(connector, 0);
+ drm_connector_set_active_color_range_property(connector,
+
DRM_MODE_COLOR_RANGE_UNSET);
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 9204bc14590a..214010f7cbec 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4692,10 +4692,12 @@ intel_dp_add_properties(struct intel_dp *intel_dp,
struct drm_connector *connect
drm_connector_attach_max_bpc_property(connector, 6, 10);
drm_connector_attach_active_bpc_property(connector, 6, 10);
drm_connector_attach_active_color_format_property(connector);
+ drm_connector_attach_active_color_range_property(connector);
} else if (DISPLAY_VER(dev_priv) >= 5) {
drm_connector_attach_max_bpc_property(connector, 6, 12);
drm_connector_attach_active_bpc_property(connector, 6, 12);
drm_connector_attach_active_color_format_property(connector);
+ drm_connector_attach_active_color_range_property(connector);
}
/* Register HDMI colorspace for case of lspcon */
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 3e4237df3360..cb876175258f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -861,6 +861,11 @@ static struct drm_connector
*intel_dp_add_mst_connector(struct drm_dp_mst_topolo
if (connector->active_color_format_property)
drm_connector_attach_active_color_format_property(connector);
+ connector->active_color_range_property =
+ intel_dp->attached_connector->base.active_color_range_property;
+ if (connector->active_color_range_property)
+ drm_connector_attach_active_color_range_property(connector);
+
return connector;
err:
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 367aba57b55f..dacac23a6c30 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2517,6 +2517,7 @@ intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi,
struct drm_connector *c
drm_connector_attach_max_bpc_property(connector, 8, 12);
drm_connector_attach_active_bpc_property(connector, 8, 12);
drm_connector_attach_active_color_format_property(connector);
+ drm_connector_attach_active_color_range_property(connector);
}
}
--
2.25.1
___
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[PATCH v4 13/17] drm/amd/display: Add handling for new "preferred color format" property
This commit implements the "preferred color format" drm property for the
AMD GPU driver.
Signed-off-by: Werner Sembach
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 30 +++
.../display/amdgpu_dm/amdgpu_dm_mst_types.c | 4 +++
2 files changed, 28 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index bce47f28e20a..9ffd2f9d3d75 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -5351,15 +5351,32 @@ static void
fill_stream_properties_from_drm_display_mode(
timing_out->h_border_right = 0;
timing_out->v_border_top = 0;
timing_out->v_border_bottom = 0;
- /* TODO: un-hardcode */
- if (drm_mode_is_420_only(info, mode_in)
- || (drm_mode_is_420_also(info, mode_in) &&
aconnector->force_yuv420_output))
+
+ if (connector_state
+ && (connector_state->preferred_color_format ==
DRM_COLOR_FORMAT_YCRCB420
+ || aconnector->force_yuv420_output) &&
drm_mode_is_420(info, mode_in))
timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
- else if ((connector->display_info.color_formats &
DRM_COLOR_FORMAT_YCRCB444)
- && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
+ else if (connector_state
+ && connector_state->preferred_color_format ==
DRM_COLOR_FORMAT_YCRCB444
+ && connector->display_info.color_formats &
DRM_COLOR_FORMAT_YCRCB444)
timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
- else
+ else if (connector_state
+ && connector_state->preferred_color_format ==
DRM_COLOR_FORMAT_RGB444
+ && !drm_mode_is_420_only(info, mode_in))
timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
+ else
+ /*
+* connector_state->preferred_color_format not possible
+* || connector_state->preferred_color_format == 0 (auto)
+* || connector_state->preferred_color_format ==
DRM_COLOR_FORMAT_YCRCB422
+*/
+ if (drm_mode_is_420_only(info, mode_in))
+ timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
+ else if ((connector->display_info.color_formats &
DRM_COLOR_FORMAT_YCRCB444)
+ && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
+ timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
+ else
+ timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
timing_out->display_color_depth = convert_color_depth_from_display_info(
@@ -7761,6 +7778,7 @@ void amdgpu_dm_connector_init_helper(struct
amdgpu_display_manager *dm,
if (!aconnector->mst_port) {
drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16);
drm_connector_attach_active_bpc_property(&aconnector->base, 8,
16);
+
drm_connector_attach_preferred_color_format_property(&aconnector->base);
drm_connector_attach_active_color_format_property(&aconnector->base);
drm_connector_attach_active_color_range_property(&aconnector->base);
}
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index b5d57bbbdd20..2563788ba95a 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -413,6 +413,10 @@ dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr
*mgr,
if (connector->active_bpc_property)
drm_connector_attach_active_bpc_property(&aconnector->base, 8,
16);
+ connector->preferred_color_format_property =
master->base.preferred_color_format_property;
+ if (connector->preferred_color_format_property)
+
drm_connector_attach_preferred_color_format_property(&aconnector->base);
+
connector->active_color_format_property =
master->base.active_color_format_property;
if (connector->active_color_format_property)
drm_connector_attach_active_color_format_property(&aconnector->base);
--
2.25.1
___
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[PATCH v4 17/17] drm/amd/display: Add handling for new "Broadcast RGB" property
This commit implements the "Broadcast RGB" drm property for the AMD GPU
driver.
Signed-off-by: Werner Sembach
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 22 ++-
.../display/amdgpu_dm/amdgpu_dm_mst_types.c | 4
2 files changed, 21 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 9ffd2f9d3d75..c5dbf948a47a 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -5252,7 +5252,8 @@ get_aspect_ratio(const struct drm_display_mode *mode_in)
}
static enum dc_color_space
-get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
+get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing,
+ enum drm_mode_color_range preferred_color_range)
{
enum dc_color_space color_space = COLOR_SPACE_SRGB;
@@ -5267,13 +5268,17 @@ get_output_color_space(const struct dc_crtc_timing
*dc_crtc_timing)
* respectively
*/
if (dc_crtc_timing->pix_clk_100hz > 270300) {
- if (dc_crtc_timing->flags.Y_ONLY)
+ if (dc_crtc_timing->flags.Y_ONLY
+ || preferred_color_range ==
+
DRM_MODE_COLOR_RANGE_LIMITED_16_235)
color_space =
COLOR_SPACE_YCBCR709_LIMITED;
else
color_space = COLOR_SPACE_YCBCR709;
} else {
- if (dc_crtc_timing->flags.Y_ONLY)
+ if (dc_crtc_timing->flags.Y_ONLY
+ || preferred_color_range ==
+
DRM_MODE_COLOR_RANGE_LIMITED_16_235)
color_space =
COLOR_SPACE_YCBCR601_LIMITED;
else
@@ -5283,7 +5288,10 @@ get_output_color_space(const struct dc_crtc_timing
*dc_crtc_timing)
}
break;
case PIXEL_ENCODING_RGB:
- color_space = COLOR_SPACE_SRGB;
+ if (preferred_color_range ==
DRM_MODE_COLOR_RANGE_LIMITED_16_235)
+ color_space = COLOR_SPACE_SRGB_LIMITED;
+ else
+ color_space = COLOR_SPACE_SRGB;
break;
default:
@@ -5429,7 +5437,10 @@ static void fill_stream_properties_from_drm_display_mode(
timing_out->aspect_ratio = get_aspect_ratio(mode_in);
- stream->output_color_space = get_output_color_space(timing_out);
+ stream->output_color_space = get_output_color_space(timing_out,
+ connector_state ?
+
connector_state->preferred_color_range :
+
DRM_MODE_COLOR_RANGE_UNSET);
stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
@@ -7780,6 +7791,7 @@ void amdgpu_dm_connector_init_helper(struct
amdgpu_display_manager *dm,
drm_connector_attach_active_bpc_property(&aconnector->base, 8,
16);
drm_connector_attach_preferred_color_format_property(&aconnector->base);
drm_connector_attach_active_color_format_property(&aconnector->base);
+
drm_connector_attach_preferred_color_range_property(&aconnector->base);
drm_connector_attach_active_color_range_property(&aconnector->base);
}
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 2563788ba95a..80e1389fd0ec 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -421,6 +421,10 @@ dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr
*mgr,
if (connector->active_color_format_property)
drm_connector_attach_active_color_format_property(&aconnector->base);
+ connector->preferred_color_range_property =
master->base.preferred_color_range_property;
+ if (connector->preferred_color_range_property)
+
drm_connector_attach_preferred_color_range_property(&aconnector->base);
+
connector->active_color_range_property =
master->base.active_color_range_property;
if (connector->active_color_range_property)
drm_connector_attach_active_color_range_property(&aconnector->base);
--
2.25.1
___
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[PATCH v4 15/17] drm/uAPI: Move "Broadcast RGB" property from driver specific to general context
Add "Broadcast RGB" to general drm context so that more drivers besides
i915 and gma500 can implement it without duplicating code.
Userspace can use this property to tell the graphic driver to use full or
limited color range for a given connector, overwriting the default
behaviour/automatic detection.
Possible options are:
- Automatic (default/current behaviour)
- Full
- Limited 16:235
In theory the driver should be able to automatically detect the monitors
capabilities, but because of flawed standard implementations in Monitors,
this might fail. In this case a manual overwrite is required to not have
washed out colors or lose details in very dark or bright scenes.
Signed-off-by: Werner Sembach
---
drivers/gpu/drm/drm_atomic_helper.c | 4 +++
drivers/gpu/drm/drm_atomic_uapi.c | 4 +++
drivers/gpu/drm/drm_connector.c | 43 +
include/drm/drm_connector.h | 16 +++
4 files changed, 67 insertions(+)
diff --git a/drivers/gpu/drm/drm_atomic_helper.c
b/drivers/gpu/drm/drm_atomic_helper.c
index 90d62f305257..0c89d32efbd0 100644
--- a/drivers/gpu/drm/drm_atomic_helper.c
+++ b/drivers/gpu/drm/drm_atomic_helper.c
@@ -691,6 +691,10 @@ drm_atomic_helper_check_modeset(struct drm_device *dev,
if (old_connector_state->preferred_color_format !=
new_connector_state->preferred_color_format)
new_crtc_state->connectors_changed = true;
+
+ if (old_connector_state->preferred_color_range !=
+ new_connector_state->preferred_color_range)
+ new_crtc_state->connectors_changed = true;
}
if (funcs->atomic_check)
diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
b/drivers/gpu/drm/drm_atomic_uapi.c
index c536f5e22016..c589bb1a8163 100644
--- a/drivers/gpu/drm/drm_atomic_uapi.c
+++ b/drivers/gpu/drm/drm_atomic_uapi.c
@@ -798,6 +798,8 @@ static int drm_atomic_connector_set_property(struct
drm_connector *connector,
state->max_requested_bpc = val;
} else if (property == connector->preferred_color_format_property) {
state->preferred_color_format = val;
+ } else if (property == connector->preferred_color_range_property) {
+ state->preferred_color_range = val;
} else if (connector->funcs->atomic_set_property) {
return connector->funcs->atomic_set_property(connector,
state, property, val);
@@ -877,6 +879,8 @@ drm_atomic_connector_get_property(struct drm_connector
*connector,
*val = state->max_requested_bpc;
} else if (property == connector->preferred_color_format_property) {
*val = state->preferred_color_format;
+ } else if (property == connector->preferred_color_range_property) {
+ *val = state->preferred_color_range;
} else if (connector->funcs->atomic_get_property) {
return connector->funcs->atomic_get_property(connector,
state, property, val);
diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index aea03dd02e33..9bc596638613 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -905,6 +905,12 @@ static const struct drm_prop_enum_list
drm_active_color_format_enum_list[] = {
{ DRM_COLOR_FORMAT_YCRCB420, "ycbcr420" },
};
+static const struct drm_prop_enum_list drm_preferred_color_range_enum_list[] =
{
+ { DRM_MODE_COLOR_RANGE_UNSET, "Automatic" },
+ { DRM_MODE_COLOR_RANGE_FULL, "Full" },
+ { DRM_MODE_COLOR_RANGE_LIMITED_16_235, "Limited 16:235" },
+};
+
static const struct drm_prop_enum_list drm_active_color_range_enum_list[] = {
{ DRM_MODE_COLOR_RANGE_UNSET, "Unknown" },
{ DRM_MODE_COLOR_RANGE_FULL, "Full" },
@@ -1243,6 +1249,13 @@ static const struct drm_prop_enum_list dp_colorspaces[]
= {
* drm_connector_attach_active_color_format_property() to install this
* property.
*
+ * Broadcast RGB:
+ * This property is used by userspace to change the used color range. When
+ * used the driver will use the selected range if valid for the current
+ * color format. Drivers to use the function
+ * drm_connector_attach_preferred_color_format_property() to create and
+ * attach the property to the connector during initialization.
+ *
* active color range:
* This read-only property tells userspace the color range actually used by
* the hardware display engine on "the cable" on a connector. The chosen
@@ -2324,6 +2337,36 @@ void
drm_connector_set_active_color_format_property(struct drm_connector *connec
}
EXPORT_SYMBOL(drm_connector_set_active_color_format_property);
+/**
+ * drm_connector_attach_preferred_color_range_property - attach "Broadcast
RGB" property
+ * @connector: connector to attach preferred co
[PATCH v4 16/17] drm/i915/display: Use the general "Broadcast RGB" implementation
Change from the i915 specific "Broadcast RGB" drm property implementation
to the general one.
This commit delete all traces of the former "Broadcast RGB" implementation
and add a new one using the new driver agnoistic functions an variables.
Signed-off-by: Werner Sembach
---
drivers/gpu/drm/i915/display/intel_atomic.c | 8 --
.../gpu/drm/i915/display/intel_connector.c| 28 ---
.../gpu/drm/i915/display/intel_connector.h| 1 -
.../drm/i915/display/intel_display_types.h| 8 --
drivers/gpu/drm/i915/display/intel_dp.c | 9 ++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 6 +++-
drivers/gpu/drm/i915/display/intel_hdmi.c | 8 ++
drivers/gpu/drm/i915/display/intel_sdvo.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 1 -
9 files changed, 12 insertions(+), 59 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
b/drivers/gpu/drm/i915/display/intel_atomic.c
index b4e7ac51aa31..f8d5a0e287b0 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -63,8 +63,6 @@ int intel_digital_connector_atomic_get_property(struct
drm_connector *connector,
if (property == dev_priv->force_audio_property)
*val = intel_conn_state->force_audio;
- else if (property == dev_priv->broadcast_rgb_property)
- *val = intel_conn_state->broadcast_rgb;
else {
drm_dbg_atomic(&dev_priv->drm,
"Unknown property [PROP:%d:%s]\n",
@@ -99,11 +97,6 @@ int intel_digital_connector_atomic_set_property(struct
drm_connector *connector,
return 0;
}
- if (property == dev_priv->broadcast_rgb_property) {
- intel_conn_state->broadcast_rgb = val;
- return 0;
- }
-
drm_dbg_atomic(&dev_priv->drm, "Unknown property [PROP:%d:%s]\n",
property->base.id, property->name);
return -EINVAL;
@@ -134,7 +127,6 @@ int intel_digital_connector_atomic_check(struct
drm_connector *conn,
* up in a modeset.
*/
if (new_conn_state->force_audio != old_conn_state->force_audio ||
- new_conn_state->broadcast_rgb != old_conn_state->broadcast_rgb ||
new_conn_state->base.colorspace != old_conn_state->base.colorspace
||
new_conn_state->base.picture_aspect_ratio !=
old_conn_state->base.picture_aspect_ratio ||
new_conn_state->base.content_type !=
old_conn_state->base.content_type ||
diff --git a/drivers/gpu/drm/i915/display/intel_connector.c
b/drivers/gpu/drm/i915/display/intel_connector.c
index 9bed1ccecea0..89f0edf19182 100644
--- a/drivers/gpu/drm/i915/display/intel_connector.c
+++ b/drivers/gpu/drm/i915/display/intel_connector.c
@@ -241,34 +241,6 @@ intel_attach_force_audio_property(struct drm_connector
*connector)
drm_object_attach_property(&connector->base, prop, 0);
}
-static const struct drm_prop_enum_list broadcast_rgb_names[] = {
- { INTEL_BROADCAST_RGB_AUTO, "Automatic" },
- { INTEL_BROADCAST_RGB_FULL, "Full" },
- { INTEL_BROADCAST_RGB_LIMITED, "Limited 16:235" },
-};
-
-void
-intel_attach_broadcast_rgb_property(struct drm_connector *connector)
-{
- struct drm_device *dev = connector->dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
- struct drm_property *prop;
-
- prop = dev_priv->broadcast_rgb_property;
- if (prop == NULL) {
- prop = drm_property_create_enum(dev, DRM_MODE_PROP_ENUM,
- "Broadcast RGB",
- broadcast_rgb_names,
- ARRAY_SIZE(broadcast_rgb_names));
- if (prop == NULL)
- return;
-
- dev_priv->broadcast_rgb_property = prop;
- }
-
- drm_object_attach_property(&connector->base, prop, 0);
-}
-
void
intel_attach_aspect_ratio_property(struct drm_connector *connector)
{
diff --git a/drivers/gpu/drm/i915/display/intel_connector.h
b/drivers/gpu/drm/i915/display/intel_connector.h
index 661a37a3c6d8..f3058a035476 100644
--- a/drivers/gpu/drm/i915/display/intel_connector.h
+++ b/drivers/gpu/drm/i915/display/intel_connector.h
@@ -28,7 +28,6 @@ int intel_connector_update_modes(struct drm_connector
*connector,
struct edid *edid);
int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
void intel_attach_force_audio_property(struct drm_connector *connector);
-void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
void intel_attach_aspect_ratio_property(struct drm_connector *connector);
void intel_attach_hdmi_colorspace_property(struct drm_connector *connector);
void intel_attach_dp_colorspace_property(struct drm_connector *connector);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/dr
[PATCH v4 14/17] drm/i915/display: Add handling for new "preferred color format" property
This commit implements the "preferred color format" drm property for the
Intel GPU driver.
Signed-off-by: Werner Sembach
---
drivers/gpu/drm/i915/display/intel_dp.c | 7 ++-
drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 +
drivers/gpu/drm/i915/display/intel_hdmi.c | 6 ++
3 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 214010f7cbec..4c01ab887904 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -616,9 +616,12 @@ intel_dp_output_format(struct drm_connector *connector,
{
struct intel_dp *intel_dp =
intel_attached_dp(to_intel_connector(connector));
const struct drm_display_info *info = &connector->display_info;
+ const struct drm_connector_state *connector_state = connector->state;
if (!connector->ycbcr_420_allowed ||
- !drm_mode_is_420_only(info, mode))
+ !(drm_mode_is_420_only(info, mode) ||
+ (drm_mode_is_420_also(info, mode) && connector_state &&
+ connector_state->preferred_color_format ==
DRM_COLOR_FORMAT_YCRCB420)))
return INTEL_OUTPUT_FORMAT_RGB;
if (intel_dp->dfp.rgb_to_ycbcr &&
@@ -4691,11 +4694,13 @@ intel_dp_add_properties(struct intel_dp *intel_dp,
struct drm_connector *connect
if (HAS_GMCH(dev_priv)) {
drm_connector_attach_max_bpc_property(connector, 6, 10);
drm_connector_attach_active_bpc_property(connector, 6, 10);
+ drm_connector_attach_preferred_color_format_property(connector);
drm_connector_attach_active_color_format_property(connector);
drm_connector_attach_active_color_range_property(connector);
} else if (DISPLAY_VER(dev_priv) >= 5) {
drm_connector_attach_max_bpc_property(connector, 6, 12);
drm_connector_attach_active_bpc_property(connector, 6, 12);
+ drm_connector_attach_preferred_color_format_property(connector);
drm_connector_attach_active_color_format_property(connector);
drm_connector_attach_active_color_range_property(connector);
}
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index cb876175258f..67f0fb649876 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -856,6 +856,11 @@ static struct drm_connector
*intel_dp_add_mst_connector(struct drm_dp_mst_topolo
if (connector->active_bpc_property)
drm_connector_attach_active_bpc_property(connector, 6, 12);
+ connector->preferred_color_format_property =
+
intel_dp->attached_connector->base.preferred_color_format_property;
+ if (connector->preferred_color_format_property)
+ drm_connector_attach_preferred_color_format_property(connector);
+
connector->active_color_format_property =
intel_dp->attached_connector->base.active_color_format_property;
if (connector->active_color_format_property)
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index dacac23a6c30..bce253bc5b16 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2153,6 +2153,11 @@ static int intel_hdmi_compute_output_format(struct
intel_encoder *encoder,
crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;
}
+ if (connector->ycbcr_420_allowed &&
+ conn_state->preferred_color_format == DRM_COLOR_FORMAT_YCRCB420 &&
+ drm_mode_is_420_also(&connector->display_info, adjusted_mode))
+ crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
+
ret = intel_hdmi_compute_clock(encoder, crtc_state);
if (ret) {
if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_YCBCR420 &&
@@ -2516,6 +2521,7 @@ intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi,
struct drm_connector *c
if (!HAS_GMCH(dev_priv)) {
drm_connector_attach_max_bpc_property(connector, 8, 12);
drm_connector_attach_active_bpc_property(connector, 8, 12);
+ drm_connector_attach_preferred_color_format_property(connector);
drm_connector_attach_active_color_format_property(connector);
drm_connector_attach_active_color_range_property(connector);
}
--
2.25.1
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[PATCH] drm/amdgpu: fix amdgpu_preempt_mgr_new()
There is a reversed if statement in amdgpu_preempt_mgr_new() so it
always returns -ENOMEM.
Fixes: 09b020bb05a5 ("Merge tag 'drm-misc-next-2021-06-09' of
git://anongit.freedesktop.org/drm/drm-misc into drm-next")
Signed-off-by: Dan Carpenter
---
drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.c
index f6aff7ce5160..d02c8637f909 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.c
@@ -71,7 +71,7 @@ static int amdgpu_preempt_mgr_new(struct ttm_resource_manager
*man,
struct amdgpu_preempt_mgr *mgr = to_preempt_mgr(man);
*res = kzalloc(sizeof(**res), GFP_KERNEL);
- if (*res)
+ if (!*res)
return -ENOMEM;
ttm_resource_init(tbo, place, *res);
--
2.30.2
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Re: [PATCH] drm/amdgpu: fix amdgpu_preempt_mgr_new()
Am 18.06.21 um 10:37 schrieb Dan Carpenter:
There is a reversed if statement in amdgpu_preempt_mgr_new() so it
always returns -ENOMEM.
Fixes: 09b020bb05a5 ("Merge tag 'drm-misc-next-2021-06-09' of
git://anongit.freedesktop.org/drm/drm-misc into drm-next")
Signed-off-by: Dan Carpenter
Most be some fallout from merging it with the TTM changes.
Anyway, patch is Reviewed-by: Christian König
Thanks,
Christian.
---
drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.c
index f6aff7ce5160..d02c8637f909 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.c
@@ -71,7 +71,7 @@ static int amdgpu_preempt_mgr_new(struct ttm_resource_manager
*man,
struct amdgpu_preempt_mgr *mgr = to_preempt_mgr(man);
*res = kzalloc(sizeof(**res), GFP_KERNEL);
- if (*res)
+ if (!*res)
return -ENOMEM;
ttm_resource_init(tbo, place, *res);
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[PATCH] drm/amdgpu: Power down VCN and JPEG before disabling SMU features
When unloading driver, if VCN is powered on, sending message
DisableAllSmuFeatures to SMU will cause SMU hang. We need to
power down VCN and JPEG before clean up SMU.
Signed-off-by: Chengzhe Liu
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index cb375f1beebd..ebe672142808 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -1453,10 +1453,14 @@ static int smu_hw_fini(void *handle)
if (smu->is_apu) {
smu_powergate_sdma(&adev->smu, true);
- smu_dpm_set_vcn_enable(smu, false);
- smu_dpm_set_jpeg_enable(smu, false);
}
+ smu_dpm_set_vcn_enable(smu, false);
+ smu_dpm_set_jpeg_enable(smu, false);
+
+ adev->vcn.cur_state = AMD_PG_STATE_GATE;
+ adev->jpeg.cur_state = AMD_PG_STATE_GATE;
+
if (!smu->pm_enabled)
return 0;
--
2.25.1
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Re: [PATCH] drm/amd/display: Remove the repeated dpp1_full_bypass declaration
On 2021-06-17 9:23 p.m., Shaokun Zhang wrote: > Function 'dpp1_full_bypass' is declared twice, so remove the repeated > declaration and unnessary blank line. > > Cc: Harry Wentland > Cc: Leo Li > Cc: Alex Deucher > Signed-off-by: Shaokun Zhang Reviewed-by: Harry Wentland Harry > --- > drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h | 2 -- > 1 file changed, 2 deletions(-) > > diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h > b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h > index 9a1f40eb5c47..71b3a6949001 100644 > --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h > +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h > @@ -1497,8 +1497,6 @@ void dpp1_cnv_setup ( > enum dc_color_space input_color_space, > struct cnv_alpha_2bit_lut *alpha_2bit_lut); > > -void dpp1_full_bypass(struct dpp *dpp_base); > - > void dpp1_dppclk_control( > struct dpp *dpp_base, > bool dppclk_div, > ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/display: Fix duplicated argument
On 2021-06-16 10:40 a.m., Wan Jiabing wrote:
> Fix coccicheck warning:
>
> ./drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c:
> 55:12-42: duplicated argument to && or ||
>
> Signed-off-by: Wan Jiabing
Reviewed-by: Harry Wentland
Harry
> ---
> .../gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git
> a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
> b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
> index cb15525ddb49..dc8b3afef301 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
> @@ -52,7 +52,7 @@ static bool CalculateBytePerPixelAnd256BBlockSizes(
> *BytePerPixelDETC = 0;
> *BytePerPixelY = 4;
> *BytePerPixelC = 0;
> - } else if (SourcePixelFormat == dm_444_16 || SourcePixelFormat ==
> dm_444_16) {
> + } else if (SourcePixelFormat == dm_444_16) {
> *BytePerPixelDETY = 2;
> *BytePerPixelDETC = 0;
> *BytePerPixelY = 2;
>
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Re: [PATCH] drm/amdgpu: Power down VCN and JPEG before disabling SMU features
Acked-by: Alex Deucher
On Fri, Jun 18, 2021 at 5:17 AM Chengzhe Liu wrote:
>
> When unloading driver, if VCN is powered on, sending message
> DisableAllSmuFeatures to SMU will cause SMU hang. We need to
> power down VCN and JPEG before clean up SMU.
>
> Signed-off-by: Chengzhe Liu
> ---
> drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 8 ++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> index cb375f1beebd..ebe672142808 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> @@ -1453,10 +1453,14 @@ static int smu_hw_fini(void *handle)
>
> if (smu->is_apu) {
> smu_powergate_sdma(&adev->smu, true);
> - smu_dpm_set_vcn_enable(smu, false);
> - smu_dpm_set_jpeg_enable(smu, false);
> }
>
> + smu_dpm_set_vcn_enable(smu, false);
> + smu_dpm_set_jpeg_enable(smu, false);
> +
> + adev->vcn.cur_state = AMD_PG_STATE_GATE;
> + adev->jpeg.cur_state = AMD_PG_STATE_GATE;
> +
> if (!smu->pm_enabled)
> return 0;
>
> --
> 2.25.1
>
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Re: [PATCH v1] drm/amdgpu: fix framebuffer memory use after free
On 2021-06-18 10:46 a.m., Łukasz Bartosik wrote:
> czw., 17 cze 2021 o 16:18 Michel Dänzer napisał(a):
>>
>> On 2021-06-17 10:18 a.m., Lukasz Bartosik wrote:
>>> With option CONFIG_DEBUG_LIST enabled the kernel logs show list_add
>>> corruption warning. The warning originates from drm_framebuffer_init()
>>> function which adds framebuffer to a framebuffers list and is called by
>>> amdgpu_display_gem_fb_verify_and_init().
>>> If amdgpu_display_gem_fb_verify_and_init() encounters an error after
>>> calling drm_framebuffer_init() then framebuffer memory is released
>>> in amdgpu_display_user_framebuffer_create() without removing framebuffer
>>> from the list where it was added. Reuse of that memory by any other
>>> party cause corruption of the framebuffers linked list. This fix removes
>>> framebuffer from the linked list and unregisters it in case of failure.
>>>
>>> [...]
>>>
>>> Fixes: 6eed95b00b45 ("drm/amd/display: Store tiling_flags in the
>>> framebuffer.")
>>
>> I didn't realize there was already an issue before f258907fdd835e
>> "drm/amdgpu: Verify bo size can fit framebuffer size on init.". Looking at
>> the Git history again, I agree there's already at least a theoretical issue
>> in 5.11, though I suspect it's harder to hit in practice.
>>
>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
>>> index c13985fb35be..933190281b91 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
>>> @@ -1085,14 +1085,17 @@ int amdgpu_display_gem_fb_verify_and_init(
>>> mode_cmd->modifier[0]);
>>>
>>> ret = -EINVAL;
>>> - goto err;
>>> + goto err_fb_cleanup;
>>> }
>>>
>>> ret = amdgpu_display_framebuffer_init(dev, rfb, mode_cmd, obj);
>>> if (ret)
>>> - goto err;
>>> + goto err_fb_cleanup;
>>>
>>> return 0;
>>> +err_fb_cleanup:
>>> + drm_framebuffer_unregister_private(&rfb->base);
>>> + drm_framebuffer_cleanup(&rfb->base);
>>> err:
>>> drm_dbg_kms(dev, "Failed to verify and init gem fb: %d\n", ret);
>>> rfb->base.obj[0] = NULL;
>>>
>>
>> There's a similar issue in amdgpu_display_gem_fb_init.
>> https://patchwork.freedesktop.org/patch/439542/ fixes that as well, and
>> seems simpler (though I'm biased obviously :).
>
> I agree your patch is simpler and covers more cases, but IMHO my
> approach with explicit framebuffer cleanup has the advantage
> that it will be hard to miss in case of future code reorganizations in
> that area.
Fair enough.
FWIW, I went the "call drm_framebuffer_init last" route because it matches what
all other drivers do AFAICT.
--
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Libre software enthusiast | Mesa and X developer
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Re: [PATCH] drm/amdgpu: Revert enlarging CP_MEC_DOORBELL_RANGE patches.
Probably better to revert each patch individually for upstream. With
that changed,
Acked-by: Alex Deucher
Alex
On Thu, Jun 17, 2021 at 10:23 PM Yifan Zhang wrote:
>
> Revert "drm/amdgpu/gfx9: fix the doorbell missing when in CGPG issue."
> Revert "drm/amdgpu/gfx10: enlarge CP_MEC_DOORBELL_RANGE_UPPER to cover full
> doorbell."
>
> This revert commits:
> a3b4cfb09aa9e73cc48caff77efc161a396aeddb.
> feae47198886d0df7b43876916a0e4366f159b45
>
> Reason for revert: side effect of enlarging CP_MEC_DOORBELL_RANGE may
> cause some APUs fail to enter gfxoff in certain user cases.
>
> Signed-off-by: Yifan Zhang
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 6 +-
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 6 +-
> 2 files changed, 2 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index 7bfe6f9d3a52..15ae9e33b925 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -6974,12 +6974,8 @@ static int gfx_v10_0_kiq_init_register(struct
> amdgpu_ring *ring)
> if (ring->use_doorbell) {
> WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
> (adev->doorbell_index.kiq * 2) << 2);
> - /* If GC has entered CGPG, ringing doorbell > first page
> doesn't
> -* wakeup GC. Enlarge CP_MEC_DOORBELL_RANGE_UPPER to
> workaround
> -* this issue.
> -*/
> WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
> - (adev->doorbell.size - 4));
> + (adev->doorbell_index.userqueue_end * 2) << 2);
> }
>
> WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 922420a2c102..044076ec1d03 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -3675,12 +3675,8 @@ static int gfx_v9_0_kiq_init_register(struct
> amdgpu_ring *ring)
> if (ring->use_doorbell) {
> WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
> (adev->doorbell_index.kiq * 2) << 2);
> - /* If GC has entered CGPG, ringing doorbell > first page
> doesn't
> -* wakeup GC. Enlarge CP_MEC_DOORBELL_RANGE_UPPER to
> workaround
> -* this issue.
> -*/
> WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
> - (adev->doorbell.size - 4));
> + (adev->doorbell_index.userqueue_end *
> 2) << 2);
> }
>
> WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
> --
> 2.25.1
>
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[PATCH 10/12] drm/amd/display: do not compare integers of different widths
From: Josip Pavic
[Why & How]
Increase width of some variables to avoid comparing integers of
different widths
Signed-off-by: Josip Pavic
Reviewed-by: Aric Cyr
Acked-by: Bindu Ramamurthy
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c| 2 +-
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 9058e45add92..a033bec2cc4c 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -821,7 +821,7 @@ static bool dc_link_detect_helper(struct dc_link *link,
{
struct dc_sink_init_data sink_init_data = { 0 };
struct display_sink_capability sink_caps = { 0 };
- uint8_t i;
+ uint32_t i;
bool converter_disable_audio = false;
struct audio_support *aud_support = &link->dc->res_pool->audio_support;
bool same_edid = false;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 10b749ef7fbb..6af6247ae055 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -1768,7 +1768,7 @@ bool perform_link_training_with_retries(
enum signal_type signal,
bool do_fallback)
{
- uint8_t j;
+ int j;
uint8_t delay_between_attempts = LINK_TRAINING_RETRY_DELAY;
struct dc_stream_state *stream = pipe_ctx->stream;
struct dc_link *link = stream->link;
@@ -2307,7 +2307,7 @@ bool dp_verify_link_cap_with_retries(
struct dc_link_settings *known_limit_link_setting,
int attempts)
{
- uint8_t i = 0;
+ int i = 0;
bool success = false;
for (i = 0; i < attempts; i++) {
--
2.25.1
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Re: [PATCH] drm/amdgpu: fix amdgpu_preempt_mgr_new()
Am 2021-06-18 um 4:39 a.m. schrieb Christian König:
> Am 18.06.21 um 10:37 schrieb Dan Carpenter:
>> There is a reversed if statement in amdgpu_preempt_mgr_new() so it
>> always returns -ENOMEM.
>>
>> Fixes: 09b020bb05a5 ("Merge tag 'drm-misc-next-2021-06-09' of
>> git://anongit.freedesktop.org/drm/drm-misc into drm-next")
>> Signed-off-by: Dan Carpenter
>
> Most be some fallout from merging it with the TTM changes.
>
> Anyway, patch is Reviewed-by: Christian König
This is obviously not for amd-staging-drm-next. Christian, are you going
to apply it to the relevant branches?
Thanks,
Felix
>
> Thanks,
> Christian.
>
>> ---
>> drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.c
>> index f6aff7ce5160..d02c8637f909 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.c
>> @@ -71,7 +71,7 @@ static int amdgpu_preempt_mgr_new(struct
>> ttm_resource_manager *man,
>> struct amdgpu_preempt_mgr *mgr = to_preempt_mgr(man);
>> *res = kzalloc(sizeof(**res), GFP_KERNEL);
>> - if (*res)
>> + if (!*res)
>> return -ENOMEM;
>> ttm_resource_init(tbo, place, *res);
>
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Re: [PATCH -next] drm/amd/display: Fix gcc unused variable warning
Applied. Thanks!
Alex
On Thu, Jun 17, 2021 at 2:43 PM Harry Wentland wrote:
>
> On 2021-06-16 10:31 p.m., Pu Lehui wrote:
> > GCC reports the following warning with W=1:
> >
> > drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_dp.c:3635:17:
> > warning:
> > variable ‘status’ set but not used [-Wunused-but-set-variable]
> > 3635 | enum dc_status status = DC_ERROR_UNEXPECTED;
> >| ^~
> >
> > The variable should be used for error check, let's fix it.
> >
> > Signed-off-by: Pu Lehui
>
> Reviewed-by: Harry Wentland
>
> Harry
>
> > ---
> > drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 4
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> > b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> > index fcb635c85330..cf29265870c8 100644
> > --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> > +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> > @@ -3681,6 +3681,10 @@ bool dp_retrieve_lttpr_cap(struct dc_link *link)
> >
> > DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
> > lttpr_dpcd_data,
> > sizeof(lttpr_dpcd_data));
> > + if (status != DC_OK) {
> > + dm_error("%s: Read LTTPR caps data failed.\n",
> > __func__);
> > + return false;
> > + }
> >
> > link->dpcd_caps.lttpr_caps.revision.raw =
> >
> > lttpr_dpcd_data[DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV -
> >
>
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Re: [PATCH -next] drm/amd/display: remove unused variable 'dc'
Applied. Thanks!
On Thu, Jun 17, 2021 at 3:04 PM Harry Wentland wrote:
>
>
>
> On 2021-06-16 9:16 p.m., Pu Lehui wrote:
> > GCC reports the following warning with W=1:
> >
> > drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_psr.c:70:13:
> > warning:
> > variable ‘dc’ set but not used [-Wunused-but-set-variable]
> > 70 | struct dc *dc = NULL;
> >| ^~
> >
> > This variable is not used in function, this commit remove it to
> > fix the warning.
> >
> > Signed-off-by: Pu Lehui
>
> Reviewed-by: Harry Wentland
>
> Harry
>
> > ---
> > drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c | 2 --
> > 1 file changed, 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
> > b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
> > index f7c77ae0d965..70a554f1e725 100644
> > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
> > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
> > @@ -67,14 +67,12 @@ bool amdgpu_dm_link_setup_psr(struct dc_stream_state
> > *stream)
> > struct dc_link *link = NULL;
> > struct psr_config psr_config = {0};
> > struct psr_context psr_context = {0};
> > - struct dc *dc = NULL;
> > bool ret = false;
> >
> > if (stream == NULL)
> > return false;
> >
> > link = stream->link;
> > - dc = link->ctx->dc;
> >
> > psr_config.psr_version = link->dpcd_caps.psr_caps.psr_version;
> >
> >
>
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Re: [PATCH][next] drm/amd/display: Fix fall-through warning for Clang
Applied. Thanks! Alex On Thu, Jun 17, 2021 at 3:20 PM Harry Wentland wrote: > > > > On 2021-06-16 4:52 p.m., Gustavo A. R. Silva wrote: > > In preparation to enable -Wimplicit-fallthrough for Clang, fix > > the following warning by replacing a /* fall through */ comment > > with the new pseudo-keyword macro fallthrough: > > > > rivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.c:672:4: warning: > > unannotated fall-through between switch labels [-Wimplicit-fallthrough] > > case AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER: > > ^ > > > > Notice that Clang doesn't recognize /* fall through */ comments as > > implicit fall-through markings, so in order to globally enable > > -Wimplicit-fallthrough for Clang, these comments need to be > > replaced with fallthrough; in the whole codebase. > > > > Link: https://github.com/KSPP/linux/issues/115 > > Signed-off-by: Gustavo A. R. Silva > > Reviewed-by: Harry Wentland > > Harry > > > --- > > JFYI: We had thousands of these sorts of warnings and now we are down > > to just 15 in linux-next. This is one of those last remaining > > warnings. > > > > drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c > > b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c > > index 28631714f697..2fb88e54a4bf 100644 > > --- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c > > +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c > > @@ -668,7 +668,7 @@ bool dce_aux_transfer_with_retries(struct ddc_service > > *ddc, > > /* polling_timeout_period is in us */ > > defer_time_in_ms += > > aux110->polling_timeout_period / 1000; > > ++aux_defer_retries; > > - /* fall through */ > > + fallthrough; > > case AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER: > > retry_on_defer = true; > > fallthrough; > > > ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amd/display: Remove the repeated dpp1_full_bypass declaration
Applied. Thanks! On Fri, Jun 18, 2021 at 9:48 AM Harry Wentland wrote: > > > > On 2021-06-17 9:23 p.m., Shaokun Zhang wrote: > > Function 'dpp1_full_bypass' is declared twice, so remove the repeated > > declaration and unnessary blank line. > > > > Cc: Harry Wentland > > Cc: Leo Li > > Cc: Alex Deucher > > Signed-off-by: Shaokun Zhang > > Reviewed-by: Harry Wentland > > Harry > > > --- > > drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h | 2 -- > > 1 file changed, 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h > > b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h > > index 9a1f40eb5c47..71b3a6949001 100644 > > --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h > > +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h > > @@ -1497,8 +1497,6 @@ void dpp1_cnv_setup ( > > enum dc_color_space input_color_space, > > struct cnv_alpha_2bit_lut *alpha_2bit_lut); > > > > -void dpp1_full_bypass(struct dpp *dpp_base); > > - > > void dpp1_dppclk_control( > > struct dpp *dpp_base, > > bool dppclk_div, > > > > ___ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/display: Fix duplicated argument
Applied. Thanks!
On Fri, Jun 18, 2021 at 9:56 AM Harry Wentland wrote:
>
> On 2021-06-16 10:40 a.m., Wan Jiabing wrote:
> > Fix coccicheck warning:
> >
> > ./drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c:
> > 55:12-42: duplicated argument to && or ||
> >
> > Signed-off-by: Wan Jiabing
>
> Reviewed-by: Harry Wentland
>
> Harry
>
> > ---
> > .../gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git
> > a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
> > b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
> > index cb15525ddb49..dc8b3afef301 100644
> > --- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
> > +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
> > @@ -52,7 +52,7 @@ static bool CalculateBytePerPixelAnd256BBlockSizes(
> > *BytePerPixelDETC = 0;
> > *BytePerPixelY = 4;
> > *BytePerPixelC = 0;
> > - } else if (SourcePixelFormat == dm_444_16 || SourcePixelFormat ==
> > dm_444_16) {
> > + } else if (SourcePixelFormat == dm_444_16) {
> > *BytePerPixelDETY = 2;
> > *BytePerPixelDETC = 0;
> > *BytePerPixelY = 2;
> >
>
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Re: [PATCH] drm/amdgpu: Call drm_framebuffer_init last for framebuffer init
Applied. Thanks! Alex On Thu, Jun 17, 2021 at 6:33 AM Michel Dänzer wrote: > > On 2021-06-16 12:46 p.m., Michel Dänzer wrote: > > From: Michel Dänzer > > > > Once drm_framebuffer_init has returned 0, the framebuffer is hooked up > > to the reference counting machinery and can no longer be destroyed with > > a simple kfree. Therefore, it must be called last. > > > > Fixes: f258907fdd835e "drm/amdgpu: Verify bo size can fit framebuffer size > > on init." > > In case the commit log wasn't clear: If drm_framebuffer_init returns 0 but > its caller then returns non-0, there will likely be memory corruption > fireworks down the road. The following lead me to this fix: > > [ 12.891228] kernel BUG at lib/list_debug.c:25! > [...] > [ 12.891263] RIP: 0010:__list_add_valid+0x4b/0x70 > [...] > [ 12.891324] Call Trace: > [ 12.891330] drm_framebuffer_init+0xb5/0x100 [drm] > [ 12.891378] amdgpu_display_gem_fb_verify_and_init+0x47/0x120 [amdgpu] > [ 12.891592] ? amdgpu_display_user_framebuffer_create+0x10d/0x1f0 [amdgpu] > [ 12.891794] amdgpu_display_user_framebuffer_create+0x126/0x1f0 [amdgpu] > [ 12.891995] drm_internal_framebuffer_create+0x378/0x3f0 [drm] > [ 12.892036] ? drm_internal_framebuffer_create+0x3f0/0x3f0 [drm] > [ 12.892075] drm_mode_addfb2+0x34/0xd0 [drm] > [ 12.892115] ? drm_internal_framebuffer_create+0x3f0/0x3f0 [drm] > [ 12.892153] drm_ioctl_kernel+0xe2/0x150 [drm] > [ 12.892193] drm_ioctl+0x3da/0x460 [drm] > [ 12.892232] ? drm_internal_framebuffer_create+0x3f0/0x3f0 [drm] > [ 12.892274] amdgpu_drm_ioctl+0x43/0x80 [amdgpu] > [ 12.892475] __se_sys_ioctl+0x72/0xc0 > [ 12.892483] do_syscall_64+0x33/0x40 > [ 12.892491] entry_SYSCALL_64_after_hwframe+0x44/0xae > > > > -- > Earthling Michel Dänzer | https://redhat.com > Libre software enthusiast | Mesa and X developer > ___ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu: fix amdgpu_preempt_mgr_new()
On Fri, Jun 18, 2021 at 11:40 AM Felix Kuehling wrote:
>
> Am 2021-06-18 um 4:39 a.m. schrieb Christian König:
> > Am 18.06.21 um 10:37 schrieb Dan Carpenter:
> >> There is a reversed if statement in amdgpu_preempt_mgr_new() so it
> >> always returns -ENOMEM.
> >>
> >> Fixes: 09b020bb05a5 ("Merge tag 'drm-misc-next-2021-06-09' of
> >> git://anongit.freedesktop.org/drm/drm-misc into drm-next")
> >> Signed-off-by: Dan Carpenter
> >
> > Most be some fallout from merging it with the TTM changes.
> >
> > Anyway, patch is Reviewed-by: Christian König
>
> This is obviously not for amd-staging-drm-next. Christian, are you going
> to apply it to the relevant branches?
I've applied it to my drm-next branch.
Alex
>
> Thanks,
> Felix
>
>
> >
> > Thanks,
> > Christian.
> >
> >> ---
> >> drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.c | 2 +-
> >> 1 file changed, 1 insertion(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.c
> >> b/drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.c
> >> index f6aff7ce5160..d02c8637f909 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.c
> >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.c
> >> @@ -71,7 +71,7 @@ static int amdgpu_preempt_mgr_new(struct
> >> ttm_resource_manager *man,
> >> struct amdgpu_preempt_mgr *mgr = to_preempt_mgr(man);
> >> *res = kzalloc(sizeof(**res), GFP_KERNEL);
> >> -if (*res)
> >> +if (!*res)
> >> return -ENOMEM;
> >> ttm_resource_init(tbo, place, *res);
> >
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[PATCH 03/12] drm/amd/display: Clear lane settings after LTTPRs have been trained
From: Martin Tsai
[Why]
The voltage swing has to start from the minimum level when transmit TPS1 over
Main-Link in clock recovery sequence.
The lane settings from current design will inherit the existing VS/PE values
that could be adjusted by Repeater X, and to use the adjusted voltage swing
level
in Repeater X-1 or DPRX could violate DP specs.
[How]
To reset VS from lane settings after LTTPRs have been trained to meet the
requirement.
Signed-off-by: Martin Tsai
Reviewed-by: Wenjing Liu
Acked-by: Bindu Ramamurthy
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 5ecbe525b676..4326ac577756 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -1664,6 +1664,7 @@ static enum link_training_result
dp_perform_8b_10b_link_training(
uint8_t repeater_cnt;
uint8_t repeater_id;
+ uint8_t lane = 0;
if (link->ctx->dc->work_arounds.lt_early_cr_pattern)
start_clock_recovery_pattern_early(link, lt_settings, DPRX);
@@ -1694,6 +1695,9 @@ static enum link_training_result
dp_perform_8b_10b_link_training(
repeater_training_done(link, repeater_id);
}
+
+ for (lane = 0; lane <
(uint8_t)lt_settings->link_settings.lane_count; lane++)
+ lt_settings->lane_settings[lane].VOLTAGE_SWING =
VOLTAGE_SWING_LEVEL0;
}
if (status == LINK_TRAINING_SUCCESS) {
--
2.25.1
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[PATCH 02/12] drm/amd/display: Clamp VStartup value at DML calculations time
From: Nikola Cornij
[why]
Some timings with a large VBlank cause the value to overflow the
register related, while also producing other wrong values in DML output.
[how]
Clamp VStartup at the DCN3.1 maximum value
Signed-off-by: Nikola Cornij
Reviewed-by: Dmytro Laktyushkin
Acked-by: Bindu Ramamurthy
---
.../gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c| 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
index 06fac59a3d40..718d5a99dada 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
@@ -2668,6 +2668,8 @@ static void
DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
(double) v->WritebackDelay[v->VoltageLevel][k]
/ (v->HTotal[k] / v->PixelClock[k]),
1));
+ if (v->MaxVStartupLines[k] > 1023)
+ v->MaxVStartupLines[k] = 1023;
#ifdef __DML_VBA_DEBUG__
dml_print("DML::%s: k=%d MaxVStartupLines = %d\n", __func__, k,
v->MaxVStartupLines[k]);
@@ -5064,6 +5066,8 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct
display_mode_lib *mode_l
/ (v->HTotal[k]
/
v->PixelClock[k]),
1.0));
+ if (v->MaximumVStartup[i][j][k] > 1023)
+ v->MaximumVStartup[i][j][k] = 1023;
v->MaxMaxVStartup[i][j] =
dml_max(v->MaxMaxVStartup[i][j], v->MaximumVStartup[i][j][k]);
}
}
--
2.25.1
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[PATCH 07/12] drm/amd/display: get refclk from MICROSECOND_TIME_BASE_DIV HW register
From: Charlene Liu
[why]
recent VBIOS dce_infotable reference clock change caused a I2c regression.
instead of relying on vbios, let's get it from HW directly.
Signed-off-by: Charlene Liu
Reviewed-by: Chris Park
Reviewed-by: Nicholas Kazlauskas
Acked-by: Bindu Ramamurthy
---
drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c | 13 ++---
drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h | 3 +++
2 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
index a524f471e0d7..6d1b01c267b7 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
@@ -264,18 +264,25 @@ static void set_speed(
struct dce_i2c_hw *dce_i2c_hw,
uint32_t speed)
{
- uint32_t xtal_ref_div = 0;
+ uint32_t xtal_ref_div = 0, ref_base_div = 0;
uint32_t prescale = 0;
+ uint32_t i2c_ref_clock = 0;
if (speed == 0)
return;
- REG_GET(MICROSECOND_TIME_BASE_DIV, XTAL_REF_DIV, &xtal_ref_div);
+ REG_GET_2(MICROSECOND_TIME_BASE_DIV, MICROSECOND_TIME_BASE_DIV,
&ref_base_div,
+ XTAL_REF_DIV, &xtal_ref_div);
if (xtal_ref_div == 0)
xtal_ref_div = 2;
- prescale = ((dce_i2c_hw->reference_frequency * 2) / xtal_ref_div) /
speed;
+ if (ref_base_div == 0)
+ i2c_ref_clock = (dce_i2c_hw->reference_frequency * 2);
+ else
+ i2c_ref_clock = ref_base_div * 1000;
+
+ prescale = (i2c_ref_clock / xtal_ref_div) / speed;
if (dce_i2c_hw->masks->DC_I2C_DDC1_START_STOP_TIMING_CNTL)
REG_UPDATE_N(SPEED, 3,
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h
b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h
index 2309f2bb162c..3f45ecd189a2 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h
@@ -139,6 +139,7 @@ enum {
I2C_SF(DC_I2C_DATA, DC_I2C_INDEX, mask_sh),\
I2C_SF(DC_I2C_DATA, DC_I2C_INDEX_WRITE, mask_sh),\
I2C_SF(MICROSECOND_TIME_BASE_DIV, XTAL_REF_DIV, mask_sh),\
+ I2C_SF(MICROSECOND_TIME_BASE_DIV, MICROSECOND_TIME_BASE_DIV, mask_sh),\
I2C_SF(DC_I2C_ARBITRATION, DC_I2C_REG_RW_CNTL_STATUS, mask_sh)
#define I2C_COMMON_MASK_SH_LIST_DCE110(mask_sh)\
@@ -182,6 +183,7 @@ struct dce_i2c_shift {
uint8_t DC_I2C_INDEX;
uint8_t DC_I2C_INDEX_WRITE;
uint8_t XTAL_REF_DIV;
+ uint8_t MICROSECOND_TIME_BASE_DIV;
uint8_t DC_I2C_DDC1_SEND_RESET_LENGTH;
uint8_t DC_I2C_REG_RW_CNTL_STATUS;
uint8_t I2C_LIGHT_SLEEP_FORCE;
@@ -225,6 +227,7 @@ struct dce_i2c_mask {
uint32_t DC_I2C_INDEX;
uint32_t DC_I2C_INDEX_WRITE;
uint32_t XTAL_REF_DIV;
+ uint32_t MICROSECOND_TIME_BASE_DIV;
uint32_t DC_I2C_DDC1_SEND_RESET_LENGTH;
uint32_t DC_I2C_REG_RW_CNTL_STATUS;
uint32_t I2C_LIGHT_SLEEP_FORCE;
--
2.25.1
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[PATCH 01/12] drm/amd/display: Multiplane cursor position incorrect when plane rotated
From: Aric Cyr
[Why]
When video plane is rotate the cursor position is incorrect and not
matching the desktop location.
[How]
When a plane is rotated 90 or 270 degrees, the src_rect.width and height
should be swapped when determining the scaling factor compared to the
dst_rect.
Signed-off-by: Aric Cyr
Reviewed-by: Jun Lei
Acked-by: Bindu Ramamurthy
---
.../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 5d54900f7b61..c545eddabdcc 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -3245,10 +3245,17 @@ void dcn10_set_cursor_position(struct pipe_ctx
*pipe_ctx)
* about the actual size being incorrect, that's a limitation of
* the hardware.
*/
- x_pos = (x_pos - x_plane) * pipe_ctx->plane_state->src_rect.width /
- pipe_ctx->plane_state->dst_rect.width;
- y_pos = (y_pos - y_plane) * pipe_ctx->plane_state->src_rect.height /
- pipe_ctx->plane_state->dst_rect.height;
+ if (param.rotation == ROTATION_ANGLE_90 || param.rotation ==
ROTATION_ANGLE_270) {
+ x_pos = (x_pos - x_plane) *
pipe_ctx->plane_state->src_rect.height /
+ pipe_ctx->plane_state->dst_rect.width;
+ y_pos = (y_pos - y_plane) *
pipe_ctx->plane_state->src_rect.width /
+ pipe_ctx->plane_state->dst_rect.height;
+ } else {
+ x_pos = (x_pos - x_plane) *
pipe_ctx->plane_state->src_rect.width /
+ pipe_ctx->plane_state->dst_rect.width;
+ y_pos = (y_pos - y_plane) *
pipe_ctx->plane_state->src_rect.height /
+ pipe_ctx->plane_state->dst_rect.height;
+ }
/**
* If the cursor's source viewport is clipped then we need to
--
2.25.1
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[PATCH 06/12] drm/amd/display: Delay PSR entry
From: Roman Li
[Why]
After panel power up, if PSR entry attempted too early,
PSR state may get stuck in transition.
This could happen if the panel is not ready
to respond to the SDP PSR entry message.
In this case dmub f/w is unable to abort PSR entry
since abortion is not permitted after the SDP has been sent.
[How]
Skip 5 pageflips before PSR enable.
Signed-off-by: Roman Li
Reviewed-by: Hersen Wu
Acked-by: Bindu Ramamurthy
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 10 +-
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 2 ++
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.h | 3 +++
3 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index c3fbe35f07b9..0b21d011802e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -5967,6 +5967,8 @@ create_stream_for_sink(struct amdgpu_dm_connector
*aconnector,
stream->use_vsc_sdp_for_colorimetry = true;
}
mod_build_vsc_infopacket(stream, &stream->vsc_infopacket);
+ aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY;
+
}
finish:
dc_sink_release(sink);
@@ -8814,7 +8816,13 @@ static void amdgpu_dm_commit_planes(struct
drm_atomic_state *state,
else if ((acrtc_state->update_type == UPDATE_TYPE_FAST) &&
acrtc_state->stream->link->psr_settings.psr_feature_enabled &&
!acrtc_state->stream->link->psr_settings.psr_allow_active) {
- amdgpu_dm_psr_enable(acrtc_state->stream);
+ struct amdgpu_dm_connector *aconn = (struct
amdgpu_dm_connector *)
+ acrtc_state->stream->dm_stream_context;
+
+ if (aconn->psr_skip_count > 0)
+ aconn->psr_skip_count--;
+ else
+ amdgpu_dm_psr_enable(acrtc_state->stream);
}
mutex_unlock(&dm->dc_lock);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index 64cf5afbde6a..57996c364940 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -509,6 +509,8 @@ struct amdgpu_dm_connector {
struct dsc_preferred_settings dsc_settings;
/* Cached display modes */
struct drm_display_mode freesync_vid_base;
+
+ int psr_skip_count;
};
#define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector,
base)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.h
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.h
index 57bbb80421e8..6806b3c9c84b 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.h
@@ -28,6 +28,9 @@
#include "amdgpu.h"
+/* the number of pageflips before enabling psr */
+#define AMDGPU_DM_PSR_ENTRY_DELAY 5
+
void amdgpu_dm_set_psr_caps(struct dc_link *link);
bool amdgpu_dm_psr_enable(struct dc_stream_state *stream);
bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream);
--
2.25.1
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[PATCH 00/12] June, 21, 2021
This DC patchset brings improvements in multiple areas. In summary, we highlight: * DC 3.2.141 * Firmware release 0.0.71 * Improvements across LTTPR, edp initialization, DML calculations, VBIOS for dcn302 and dcn303 etc. Anthony Koo (1): drm/amd/display: [FW Promotion] Release 0.0.71 Aric Cyr (2): drm/amd/display: Multiplane cursor position incorrect when plane rotated drm/amd/display: 3.2.141 This version brings along following fixes: - FW release 0.0.71. - get socBB from VBIOS for dcn302 and dcn303. - refclk from MICROSECOND_TIME_BASE_DIV HW register. - Clear lane settings after LTTPRs have been trained. - Clamp VStartup value at DML calculations. Aurabindo Pillai (1): drm/amd/display: get socBB from VBIOS for dcn302 and dcn303 Charlene Liu (1): drm/amd/display: get refclk from MICROSECOND_TIME_BASE_DIV HW register Josip Pavic (1): drm/amd/display: do not compare integers of different widths Martin Tsai (1): drm/amd/display: Clear lane settings after LTTPRs have been trained Nikola Cornij (1): drm/amd/display: Clamp VStartup value at DML calculations time Roman Li (1): drm/amd/display: Delay PSR entry Stylon Wang (1): drm/amd/display: Revert "Guard ASSR with internal display flag" Wesley Chalmers (1): drm/amd/display: Fix incorrect variable name ollogush (1): drm/amd/display: Fix edp_bootup_bl_level initialization issue .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 10 ++- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 2 + .../drm/amd/display/amdgpu_dm/amdgpu_dm_psr.h | 3 + .../drm/amd/display/dc/bios/bios_parser2.c| 2 +- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 +- .../gpu/drm/amd/display/dc/core/dc_link_dp.c | 66 +- .../drm/amd/display/dc/core/dc_link_dpcd.c| 2 +- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- .../gpu/drm/amd/display/dc/dce/dce_i2c_hw.c | 13 ++- .../gpu/drm/amd/display/dc/dce/dce_i2c_hw.h | 3 + .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 15 +++- .../amd/display/dc/dcn302/dcn302_resource.c | 20 + .../amd/display/dc/dcn303/dcn303_resource.c | 20 + .../dc/dml/dcn31/display_mode_vba_31.c| 4 + .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 90 ++- 15 files changed, 197 insertions(+), 57 deletions(-) -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 05/12] drm/amd/display: get socBB from VBIOS for dcn302 and dcn303
From: Aurabindo Pillai
[why]
Some SOC BB paramters may vary per SKU, and it does
not make sense for driver to hardcode these values.
This change was added for dcn30 and dcn301, but not
for dcn302 and dcn303
[how]
Parse the values from VBIOS if available, and use
them if valid
Fixes: "drm/amd/display: get socBB from VBIOS"
Signed-off-by: Aurabindo Pillai
Reviewed-by: Rodrigo Siqueira
Acked-by: Alex Deucher
Acked-by: Bindu Ramamurthy
---
.../amd/display/dc/dcn302/dcn302_resource.c | 20 +++
.../amd/display/dc/dcn303/dcn303_resource.c | 20 +++
2 files changed, 40 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
index 628b227f0a13..16a75ba0ca82 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
@@ -1102,6 +1102,26 @@ static bool init_soc_bounding_box(struct dc *dc, struct
resource_pool *pool)
loaded_ip->max_num_dpp = pool->pipe_count;
loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk;
dcn20_patch_bounding_box(dc, loaded_bb);
+
+ if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {
+ struct bp_soc_bb_info bb_info = { 0 };
+
+ if (dc->ctx->dc_bios->funcs->get_soc_bb_info(
+ dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {
+ if (bb_info.dram_clock_change_latency_100ns > 0)
+ dcn3_02_soc.dram_clock_change_latency_us =
+ bb_info.dram_clock_change_latency_100ns
* 10;
+
+ if (bb_info.dram_sr_enter_exit_latency_100ns > 0)
+ dcn3_02_soc.sr_enter_plus_exit_time_us =
+
bb_info.dram_sr_enter_exit_latency_100ns * 10;
+
+ if (bb_info.dram_sr_exit_latency_100ns > 0)
+ dcn3_02_soc.sr_exit_time_us =
+ bb_info.dram_sr_exit_latency_100ns * 10;
+ }
+ }
+
return true;
}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c
index 88b609c32b0a..34b89464ae02 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c
@@ -1028,6 +1028,26 @@ static bool init_soc_bounding_box(struct dc *dc, struct
resource_pool *pool)
loaded_ip->max_num_dpp = pool->pipe_count;
loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk;
dcn20_patch_bounding_box(dc, loaded_bb);
+
+ if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {
+ struct bp_soc_bb_info bb_info = { 0 };
+
+ if (dc->ctx->dc_bios->funcs->get_soc_bb_info(
+ dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {
+ if (bb_info.dram_clock_change_latency_100ns > 0)
+ dcn3_03_soc.dram_clock_change_latency_us =
+ bb_info.dram_clock_change_latency_100ns
* 10;
+
+ if (bb_info.dram_sr_enter_exit_latency_100ns > 0)
+ dcn3_03_soc.sr_enter_plus_exit_time_us =
+
bb_info.dram_sr_enter_exit_latency_100ns * 10;
+
+ if (bb_info.dram_sr_exit_latency_100ns > 0)
+ dcn3_03_soc.sr_exit_time_us =
+ bb_info.dram_sr_exit_latency_100ns * 10;
+ }
+ }
+
return true;
}
--
2.25.1
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[PATCH 04/12] drm/amd/display: Fix incorrect variable name
From: Wesley Chalmers
[WHY]
extended_end_address can only be calculated from the extended_address and
extended_size
Signed-off-by: Wesley Chalmers
Reviewed-by: Ashley Thomas
Acked-by: Bindu Ramamurthy
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dpcd.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dpcd.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dpcd.c
index 27ec1e6e9c43..fe234760a0f5 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dpcd.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dpcd.c
@@ -152,7 +152,7 @@ static void dpcd_reduce_address_range(
const uint32_t reduced_size)
{
const uint32_t reduced_end_address = END_ADDRESS(reduced_address,
reduced_size);
- const uint32_t extended_end_address = END_ADDRESS(reduced_address,
extended_size);
+ const uint32_t extended_end_address = END_ADDRESS(extended_address,
extended_size);
const uint32_t offset = reduced_address - extended_address;
if (extended_end_address == reduced_end_address && extended_address ==
reduced_address)
--
2.25.1
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[PATCH 09/12] drm/amd/display: Revert "Guard ASSR with internal display flag"
From: Stylon Wang
[Why]
1. Previous patch regresses on some embedded panels.
2. Project coreboot doesn't support passing of internal display flag.
[How]
This reverts "Guard ASSR with internal display flag" commit.
Signed-off-by: Stylon Wang
Reviewed-by: Wesley Chalmers
Acked-by: Bindu Ramamurthy
---
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 58 ++-
1 file changed, 17 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 4326ac577756..10b749ef7fbb 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -1760,42 +1760,6 @@ enum link_training_result
dc_link_dp_perform_link_training(
return status;
}
-static enum dp_panel_mode try_enable_assr(struct dc_stream_state *stream)
-{
- struct dc_link *link = stream->link;
- enum dp_panel_mode panel_mode = dp_get_panel_mode(link);
-#ifdef CONFIG_DRM_AMD_DC_HDCP
- struct cp_psp *cp_psp = &stream->ctx->cp_psp;
-#endif
-
- /* ASSR must be supported on the panel */
- if (panel_mode == DP_PANEL_MODE_DEFAULT)
- return panel_mode;
-
- /* eDP or internal DP only */
- if (link->connector_signal != SIGNAL_TYPE_EDP &&
- !(link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
-link->is_internal_display))
- return DP_PANEL_MODE_DEFAULT;
-
-#ifdef CONFIG_DRM_AMD_DC_HDCP
- if (cp_psp && cp_psp->funcs.enable_assr) {
- if (!cp_psp->funcs.enable_assr(cp_psp->handle, link)) {
- /* since eDP implies ASSR on, change panel
-* mode to disable ASSR
-*/
- panel_mode = DP_PANEL_MODE_DEFAULT;
- }
- } else
- panel_mode = DP_PANEL_MODE_DEFAULT;
-
-#else
- /* turn off ASSR if the implementation is not compiled in */
- panel_mode = DP_PANEL_MODE_DEFAULT;
-#endif
- return panel_mode;
-}
-
bool perform_link_training_with_retries(
const struct dc_link_settings *link_setting,
bool skip_video_pattern,
@@ -1808,7 +1772,7 @@ bool perform_link_training_with_retries(
uint8_t delay_between_attempts = LINK_TRAINING_RETRY_DELAY;
struct dc_stream_state *stream = pipe_ctx->stream;
struct dc_link *link = stream->link;
- enum dp_panel_mode panel_mode;
+ enum dp_panel_mode panel_mode = dp_get_panel_mode(link);
struct link_encoder *link_enc;
enum link_training_result status = LINK_TRAINING_CR_FAIL_LANE0;
struct dc_link_settings current_setting = *link_setting;
@@ -1845,11 +1809,23 @@ bool perform_link_training_with_retries(
msleep(delay_dp_power_up_in_ms);
}
- panel_mode = try_enable_assr(stream);
+#ifdef CONFIG_DRM_AMD_DC_HDCP
+ if (panel_mode == DP_PANEL_MODE_EDP) {
+ struct cp_psp *cp_psp = &stream->ctx->cp_psp;
+
+ if (cp_psp && cp_psp->funcs.enable_assr) {
+ if (!cp_psp->funcs.enable_assr(cp_psp->handle,
link)) {
+ /* since eDP implies ASSR on, change
panel
+* mode to disable ASSR
+*/
+ panel_mode = DP_PANEL_MODE_DEFAULT;
+ }
+ } else
+ panel_mode = DP_PANEL_MODE_DEFAULT;
+ }
+#endif
+
dp_set_panel_mode(link, panel_mode);
- DC_LOG_DETECTION_DP_CAPS("Link: %d ASSR enabled: %d\n",
-link->link_index,
-panel_mode != DP_PANEL_MODE_DEFAULT);
if (link->aux_access_disabled) {
dc_link_dp_perform_link_training_skip_aux(link,
¤t_setting);
--
2.25.1
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[PATCH 12/12] drm/amd/display: 3.2.141
From: Aric Cyr Signed-off-by: Aric Cyr Reviewed-by: Aric Cyr Acked-by: Bindu Ramamurthy --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 9d924e8496f9..7674535654ec 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -45,7 +45,7 @@ /* forward declaration */ struct aux_payload; -#define DC_VER "3.2.140" +#define DC_VER "3.2.141" #define MAX_SURFACES 3 #define MAX_PLANES 6 -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 11/12] drm/amd/display: [FW Promotion] Release 0.0.71
From: Anthony Koo
- Introduce CMD for EDID CEA block parsing
- Add SCR5 definition for reporting eDP power sequencer status
Signed-off-by: Anthony Koo
Reviewed-by: Anthony Koo
Acked-by: Bindu Ramamurthy
---
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 90 ++-
1 file changed, 88 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index 18d2f51eb50d..707c7d0e370a 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -47,10 +47,10 @@
/* Firmware versioning. */
#ifdef DMUB_EXPOSE_VERSION
-#define DMUB_FW_VERSION_GIT_HASH 0x5cac099d3
+#define DMUB_FW_VERSION_GIT_HASH 0xf3da2b656
#define DMUB_FW_VERSION_MAJOR 0
#define DMUB_FW_VERSION_MINOR 0
-#define DMUB_FW_VERSION_REVISION 70
+#define DMUB_FW_VERSION_REVISION 71
#define DMUB_FW_VERSION_TEST 0
#define DMUB_FW_VERSION_VBIOS 0
#define DMUB_FW_VERSION_HOTFIX 0
@@ -309,6 +309,7 @@ struct dmcub_trace_buf_entry {
* Current scratch register usage is as follows:
*
* SCRATCH0: FW Boot Status register
+ * SCRATCH5: LVTMA Status Register
* SCRATCH15: FW Boot Options register
*/
@@ -335,6 +336,21 @@ enum dmub_fw_boot_status_bit {
DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver
should call restore */
};
+/* Register bit definition for SCRATCH5 */
+union dmub_lvtma_status {
+ struct {
+ uint32_t psp_ok : 1;
+ uint32_t edp_on : 1;
+ uint32_t reserved : 30;
+ } bits;
+ uint32_t all;
+};
+
+enum dmub_lvtma_status_bit {
+ DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0),
+ DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1),
+};
+
/**
* union dmub_fw_boot_options - Boot option definitions for SCRATCH15
*/
@@ -629,6 +645,10 @@ enum dmub_cmd_type {
*/
DMUB_CMD__PANEL_CNTL = 74,
#endif
+ /**
+* Command type used for EDID CEA parsing
+*/
+ DMUB_CMD__EDID_CEA = 79,
/**
* Command type used for all VBIOS interface commands.
*/
@@ -2152,6 +2172,68 @@ struct dmub_rb_cmd_lvtma_control {
struct dmub_cmd_lvtma_control_data data;
};
+/**
+ * Maximum number of bytes a chunk sent to DMUB for parsing
+ */
+#define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8
+
+/**
+ * Represent a chunk of CEA blocks sent to DMUB for parsing
+ */
+struct dmub_cmd_send_edid_cea {
+ uint16_t offset;/**< offset into the CEA block */
+ uint8_t length; /**< number of bytes in payload to copy as part of CEA
block */
+ uint16_t total_length; /**< total length of the CEA block */
+ uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the
CEA block */
+ uint8_t pad[3]; /**< padding and for future expansion */
+};
+
+/**
+ * Result of VSDB parsing from CEA block
+ */
+struct dmub_cmd_edid_cea_amd_vsdb {
+ uint8_t vsdb_found; /**< 1 if parsing has found valid AMD
VSDB */
+ uint8_t freesync_supported; /**< 1 if Freesync is supported */
+ uint16_t amd_vsdb_version; /**< AMD VSDB version */
+ uint16_t min_frame_rate;/**< Maximum frame rate */
+ uint16_t max_frame_rate;/**< Minimum frame rate */
+};
+
+/**
+ * Result of sending a CEA chunk
+ */
+struct dmub_cmd_edid_cea_ack {
+ uint16_t offset;/**< offset of the chunk into the CEA block */
+ uint8_t success;/**< 1 if this sending of chunk succeeded */
+ uint8_t pad;/**< padding and for future expansion */
+};
+
+/**
+ * Specify whether the result is an ACK/NACK or the parsing has finished
+ */
+enum dmub_cmd_edid_cea_reply_type {
+ DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */
+ DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending
is OK or failing */
+};
+
+/**
+ * Definition of a DMUB_CMD__EDID_CEA command.
+ */
+struct dmub_rb_cmd_edid_cea {
+ struct dmub_cmd_header header; /**< Command header */
+ union dmub_cmd_edid_cea_data {
+ struct dmub_cmd_send_edid_cea input; /**< input to send CEA
chunks */
+ struct dmub_cmd_edid_cea_output { /**< output with results */
+ uint8_t type; /**< dmub_cmd_edid_cea_reply_type */
+ union {
+ struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb;
+ struct dmub_cmd_edid_cea_ack ack;
+ };
+ } output; /**< output to retrieve ACK/NACK or VSDB
parsing results */
+ } data; /**< Command data */
+
+};
+
/**
* union dmub_rb_cmd - DMUB inbox command.
*/
@@ -2290,6 +2372,10 @@ union dmub_rb_cmd {
* Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
*/
struct dmub_rb_cmd_lvtma_control lvtma_control;
+ /**
+* Definition of a DMUB_CMD__EDID_CEA
RE: [PATCH 00/12] June, 21, 2021
[Public] Hi all, This week this patchset was tested on the following systems: HP Envy 360, with Ryzen 5 4500U, with the following display types: eDP 1080p 60hz, 4k 60hz (via USB-C to DP/HDMI), 1440p 144hz (via USB-C to DP/HDMI), 1680*1050 60hz (via USB-C to DP and then DP to DVI/VGA) AMD Ryzen 9 5900H, with the following display types: eDP 1080p 60hz, 4k 60hz (via USB-C to DP/HDMI), 1440p 144hz (via USB-C to DP/HDMI), 1680*1050 60hz (via USB-C to DP and then DP to DVI/VGA) Sapphire Pulse RX5700XT with the following display types: 4k 60hz (via DP/HDMI), 1440p 144hz (via DP/HDMI), 1680*1050 60hz (via DP to DVI/VGA) Reference AMD RX6800 with the following display types: 4k 60hz (via DP/HDMI and USB-C to DP/HDMI), 1440p 144hz (via USB-C to DP/HDMI and USB-C to DP/HDMI), 1680*1050 60hz (via DP to DVI/VGA) Included testing using a Startech DP 1.4 MST hub at 2x 4k 60hz, and 3x 1080p 60hz on all systems. Tested-by: Daniel Wheeler Thank you, Dan Wheeler Technologist | AMD SW Display -- 1 Commerce Valley Dr E, Thornhill, ON L3T 7X6 Facebook | Twitter | amd.com -Original Message- From: amd-gfx On Behalf Of Bindu Ramamurthy Sent: June 18, 2021 1:35 PM To: amd-gfx@lists.freedesktop.org Cc: Brol, Eryk ; Li, Sun peng (Leo) ; Wentland, Harry ; Zhuo, Qingqing ; Siqueira, Rodrigo ; Jacob, Anson ; Pillai, Aurabindo ; Lakha, Bhawanpreet ; R, Bindu Subject: [PATCH 00/12] June, 21, 2021 This DC patchset brings improvements in multiple areas. In summary, we highlight: * DC 3.2.141 * Firmware release 0.0.71 * Improvements across LTTPR, edp initialization, DML calculations, VBIOS for dcn302 and dcn303 etc. Anthony Koo (1): drm/amd/display: [FW Promotion] Release 0.0.71 Aric Cyr (2): drm/amd/display: Multiplane cursor position incorrect when plane rotated drm/amd/display: 3.2.141 This version brings along following fixes: - FW release 0.0.71. - get socBB from VBIOS for dcn302 and dcn303. - refclk from MICROSECOND_TIME_BASE_DIV HW register. - Clear lane settings after LTTPRs have been trained. - Clamp VStartup value at DML calculations. Aurabindo Pillai (1): drm/amd/display: get socBB from VBIOS for dcn302 and dcn303 Charlene Liu (1): drm/amd/display: get refclk from MICROSECOND_TIME_BASE_DIV HW register Josip Pavic (1): drm/amd/display: do not compare integers of different widths Martin Tsai (1): drm/amd/display: Clear lane settings after LTTPRs have been trained Nikola Cornij (1): drm/amd/display: Clamp VStartup value at DML calculations time Roman Li (1): drm/amd/display: Delay PSR entry Stylon Wang (1): drm/amd/display: Revert "Guard ASSR with internal display flag" Wesley Chalmers (1): drm/amd/display: Fix incorrect variable name ollogush (1): drm/amd/display: Fix edp_bootup_bl_level initialization issue .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 10 ++- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 2 + .../drm/amd/display/amdgpu_dm/amdgpu_dm_psr.h | 3 + .../drm/amd/display/dc/bios/bios_parser2.c| 2 +- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 +- .../gpu/drm/amd/display/dc/core/dc_link_dp.c | 66 +- .../drm/amd/display/dc/core/dc_link_dpcd.c| 2 +- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- .../gpu/drm/amd/display/dc/dce/dce_i2c_hw.c | 13 ++- .../gpu/drm/amd/display/dc/dce/dce_i2c_hw.h | 3 + .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 15 +++- .../amd/display/dc/dcn302/dcn302_resource.c | 20 + .../amd/display/dc/dcn303/dcn303_resource.c | 20 + .../dc/dml/dcn31/display_mode_vba_31.c| 4 + .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 90 ++- 15 files changed, 197 insertions(+), 57 deletions(-) -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=04%7C01%7Cdaniel.wheeler%40amd.com%7Ca309462e10d641ec36f308d9327f79a4%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637596345349689067%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=qX9J3g2j%2B%2FzJ8ZTp8Z7cY57N49S2S3KI5NRw7RMYXkM%3D&reserved=0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 08/12] drm/amd/display: Fix edp_bootup_bl_level initialization issue
From: Logush Oliver [why] Updating the file to fix the missing line Signed-off-by: Logush Oliver Reviewed-by: Charlene Liu Acked-by: Bindu Ramamurthy --- drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c index 7d1c1b76d8d0..840d7aca17cf 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c +++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c @@ -2140,7 +2140,7 @@ static enum bp_result get_integrated_info_v2_1( info_v2_1->edp1_info.edp_pwr_down_bloff_to_vary_bloff; info->edp1_info.edp_panel_bpc = info_v2_1->edp1_info.edp_panel_bpc; - info->edp1_info.edp_bootup_bl_level = + info->edp1_info.edp_bootup_bl_level = info_v2_1->edp1_info.edp_bootup_bl_level; info->edp2_info.edp_backlight_pwm_hz = le16_to_cpu(info_v2_1->edp2_info.edp_backlight_pwm_hz); -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH v3] drm/amdkfd: Fix some double free when destroy queue fails
Am 2021-06-18 um 2:02 a.m. schrieb xinhui pan:
> Handle queue destroy failure while CP hang.
> Once CP got hang, kfd trigger GPU reset and set related flags to stop
> driver touching the queue. But all usermode queues have stopped, we
> actually somehow succeed to remove queue from runlist. So lets do
> cleanup work as normal in -EIO/-ETIME case.
>
> For other fatal error cases, say ENOMEM, we have to skip cleanup this
> time as queue might still be running. Regardless user-space tries to
> destroy the queue again or not. We need put queue back to the list so
> process termination would do the cleanup work. What's more, if userspace
> tries to destroy the queue again, we would not free its resource twice.
>
> Paste some error log below without this patch.
>
> amdgpu: Can't create new usermode queue because -1 queues were already
> created
>
> refcount_t: underflow; use-after-free.
> Call Trace:
> kobject_put+0xe6/0x1b0
> kfd_procfs_del_queue+0x37/0x50 [amdgpu]
> pqm_destroy_queue+0x17a/0x390 [amdgpu]
> kfd_ioctl_destroy_queue+0x57/0xc0 [amdgpu]
> kfd_ioctl+0x463/0x690 [amdgpu]
>
> BUG kmalloc-32 (Tainted: GW): Object already free
> INFO: Allocated in allocate_sdma_mqd+0x30/0xb0 [amdgpu] age=4796 cpu=2
> __slab_alloc+0x72/0x80
> kmem_cache_alloc_trace+0x81f/0x8c0
> allocate_sdma_mqd+0x30/0xb0 [amdgpu]
> create_queue_cpsch+0xbf/0x470 [amdgpu]
> pqm_create_queue+0x28d/0x6d0 [amdgpu]
> kfd_ioctl_create_queue+0x492/0xae0 [amdgpu]
> INFO: Freed in free_mqd_hiq_sdma+0x20/0x60 [amdgpu] age=2537 cpu=7
> kfree+0x322/0x340
> free_mqd_hiq_sdma+0x20/0x60 [amdgpu]
> destroy_queue_cpsch+0x20c/0x330 [amdgpu]
> pqm_destroy_queue+0x1a3/0x390 [amdgpu]
> kfd_ioctl_destroy_queue+0x57/0xc0 [amdgpu]
>
> Signed-off-by: xinhui pan
> ---
> .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 15 ++-
> drivers/gpu/drm/amd/amdkfd/kfd_process.c | 4 +++-
> .../drm/amd/amdkfd/kfd_process_queue_manager.c| 4 +++-
> 3 files changed, 20 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> index 16a1713808c2..f38f011e6f97 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> @@ -1528,8 +1528,13 @@ static int destroy_queue_cpsch(struct
> device_queue_manager *dqm,
> decrement_queue_count(dqm, q->properties.type);
> retval = execute_queues_cpsch(dqm,
> KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
> - if (retval == -ETIME)
> + /* CP hang and all usermode queues have stopped.
> + * We are safe to do the cleanup work.
> + */
> + if (retval == -ETIME || retval == -EIO)
> qpd->reset_wavefronts = true;
> + else if (retval)
> + goto failed_execute_queue;
> if (q->properties.is_gws) {
> dqm->gws_queue_count--;
> qpd->mapped_gws_queue = false;
> @@ -1551,6 +1556,14 @@ static int destroy_queue_cpsch(struct
> device_queue_manager *dqm,
>
> return retval;
>
> +failed_execute_queue:
> + /* Put queue back to the list, then we have chance to destroy it.
> + * FIXME: we do NOT want the queue in the runlist again.
> + */
> + list_add(&q->list, &qpd->queues_list);
> + qpd->queue_count++;
> + if (q->properties.is_active)
> + increment_queue_count(dqm, q->properties.type);
You should be able to keep the queue off the runlist by disabling it.
You can do that e.g. by setting q->properties.queue_address = NULL and
q->proterties.is_active = false. You'd have to update
dqm->gws_queue_count and qpd->mapped_gws_queues manually, or move that
change before the execute_queues_cpsch above.
Regards,
Felix
> failed_try_destroy_debugged_queue:
>
> dqm_unlock(dqm);
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
> b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
> index 09b98a83f670..984197e5929f 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
> @@ -607,11 +607,13 @@ static int kfd_procfs_add_sysfs_files(struct
> kfd_process *p)
>
> void kfd_procfs_del_queue(struct queue *q)
> {
> - if (!q)
> + if (!q || !kobject_get_unless_zero(&q->kobj))
> return;
>
> kobject_del(&q->kobj);
> kobject_put(&q->kobj);
> + /* paired with the get above */
> + kobject_put(&q->kobj);
> }
>
> int kfd_process_create_wq(void)
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
> b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
> index 95a6c36cea4c..c796c7601365 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
> @@ -373,6 +373,7 @@ int pqm_destroy_
Re: [RFC] CRIU support for ROCm
Am 2021-05-01 um 1:03 p.m. schrieb Adrian Reber: > > It would also be good to have your patchset submitted as a PR on github > to have our normal CI test coverage of the changes. Hi Adrian, We moved our work to a new github repository that is a fork of checkpoint-restore/criu so that we could send a pull request: https://github.com/checkpoint-restore/criu/pull/1519. This is still an RFC. It has some updates that Rajneesh explained in the pull request. Two big things still missing that we are working on now are: * New ioctl API to make it maintainable and extensible for the future * Using DMA engines for saving/restoring VRAM contents We should have another update with those two things in about two weeks. We'd really appreciate feedback on the changes we had to make to core CRIU, and the build system changes for the new plugin directory. Thanks, Felix > > Adrian ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
