[PATCH] drm/amdgpu/display: only enable aux backlight control for OLED panels

[Alex Deucher]

We've gotten a number of reports about backlight control not
working on panels which indicate that they use aux backlight
control.  A recent patch:

commit 2d73eabe2984a435737498ab39bb1500a9ffe9a9
Author: Camille Cho 
Date:   Thu Jul 8 18:28:37 2021 +0800

drm/amd/display: Only set default brightness for OLED

[Why]
We used to unconditionally set backlight path as AUX for panels capable
of backlight adjustment via DPCD in set default brightness.

[How]
This should be limited to OLED panel only since we control backlight via
PWM path for SDR mode in LCD HDR panel.

Reviewed-by: Krunoslav Kovac 
Acked-by: Rodrigo Siqueira 
Signed-off-by: Camille Cho 
Signed-off-by: Alex Deucher 

Changes some other code to only use aux for backlight control on
OLED panels.  The commit message seems to indicate that PWM should
be used for SDR mode on HDR panels.  Do something similar for
backlight control in general.  This may need to be revisited if and
when HDR started to get used.

Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1438
Bug: https://bugzilla.kernel.org/show_bug.cgi?id=213715
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 12db13d2bce9..986c9d29d686 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -2436,9 +2436,9 @@ static void update_connector_ext_caps(struct 
amdgpu_dm_connector *aconnector)
max_cll = conn_base->hdr_sink_metadata.hdmi_type1.max_cll;
min_cll = conn_base->hdr_sink_metadata.hdmi_type1.min_cll;
 
-   if (caps->ext_caps->bits.oled == 1 ||
+   if (caps->ext_caps->bits.oled == 1 /*||
caps->ext_caps->bits.sdr_aux_backlight_control == 1 ||
-   caps->ext_caps->bits.hdr_aux_backlight_control == 1)
+   caps->ext_caps->bits.hdr_aux_backlight_control == 1*/)
caps->aux_support = true;
 
if (amdgpu_backlight == 0)
-- 
2.31.1

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[pull] amdgpu drm-fixes-5.14

[Alex Deucher]

Hi Dave, Daniel,

Updates for 5.14.  Mostly fixes for new asics added in 5.14.

The following changes since commit 876d98e5511d8cfd12fc617a6717e7a8ea07be17:

  Merge tag 'drm-intel-fixes-2021-07-15' of 
git://anongit.freedesktop.org/drm/drm-intel into drm-fixes (2021-07-16 10:53:02 
+1000)

are available in the Git repository at:

  https://gitlab.freedesktop.org/agd5f/linux.git 
tags/amd-drm-fixes-5.14-2021-07-21

for you to fetch changes up to d80cded9cc25f841d5250d2e94a7b42be1e81c97:

  drm/amdgpu - Corrected the video codecs array name for yellow carp 
(2021-07-21 17:47:28 -0400)


amd-drm-fixes-5.14-2021-07-21:

amdgpu:
- Yellow Carp updates
- Add some Yellow Carp DIDs
- Beige Goby updates
- CIK 10bit 4K regression fix
- GFX10 golden settings updates
- eDP panel regression fix
- Misc display fixes
- Aldebaran fix


Aaron Liu (2):
  drm/amdgpu: update yellow carp external rev_id handling
  drm/amdgpu: add yellow carp pci id (v2)

Bindu Ramamurthy (2):
  drm/amd/display: Populate socclk entries for dcn3.02/3.03
  drm/amd/display: Populate dtbclk entries for dcn3.02/3.03

Camille Cho (1):
  drm/amd/display: Only set default brightness for OLED

Eric Yang (2):
  drm/amd/display: implement workaround for riommu related hang
  drm/amd/display: change zstate allow msg condition

Lijo Lazar (1):
  drm/amd/pm: Support board calibration on aldebaran

Likun Gao (1):
  drm/amdgpu: update golden setting for sienna_cichlid

Liviu Dudau (1):
  drm/amd/display: Fix 10bit 4K display on CIK GPUs

Mikita Lipski (1):
  drm/amd/display: Remove MALL function from DCN3.1

Nevenko Stupar (1):
  drm/amd/display: Line Buffer changes

Nicholas Kazlauskas (3):
  drm/amd/display: Fix max vstartup calculation for modes with borders
  drm/amd/display: Query VCO frequency from register for DCN3.1
  drm/amd/display: Update bounding box for DCN3.1

Stylon Wang (1):
  drm/amd/display: Fix ASSR regression on embedded panels

Tao Zhou (2):
  drm/amdgpu: update gc golden setting for dimgrey_cavefish
  drm/amd/pm: update DRIVER_IF_VERSION for beige_goby

Veerabadhran Gopalakrishnan (3):
  amdgpu/nv.c - Added video codec support for Yellow Carp
  amdgpu/nv.c - Optimize code for video codec support structure
  drm/amdgpu - Corrected the video codecs array name for yellow carp

Victor Lu (1):
  drm/amd/display: Fix comparison error in dcn21 DML

Xiaojian Du (1):
  drm/amdgpu: update the golden setting for vangogh

 drivers/gpu/drm/amd/amdgpu/amdgpu.h|   7 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c|   4 +
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c |   3 +
 drivers/gpu/drm/amd/amdgpu/nv.c| 248 +
 drivers/gpu/drm/amd/amdgpu/soc15.c | 176 ++-
 .../amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c   |   4 +
 .../amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c   |  59 -
 .../amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.h   |  54 -
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c   |  12 +-
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c  |   2 +-
 drivers/gpu/drm/amd/display/dc/dc.h|  10 +-
 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h |   4 +-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c  |   7 +-
 .../gpu/drm/amd/display/dc/dcn20/dcn20_resource.c  |  50 +++--
 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c   |  16 --
 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h   |   3 +-
 .../drm/amd/display/dc/dcn302/dcn302_resource.c|  13 +-
 .../drm/amd/display/dc/dcn303/dcn303_resource.c|  13 +-
 drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c |  18 ++
 drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.h |   1 +
 drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c  |   3 +-
 .../gpu/drm/amd/display/dc/dcn31/dcn31_resource.c  |   4 +
 .../amd/display/dc/dml/dcn21/display_mode_vba_21.c |   2 +-
 drivers/gpu/drm/amd/display/dc/inc/hw/transform.h  |   3 +
 .../drm/amd/display/dc/inc/hw_sequencer_private.h  |   1 +
 drivers/gpu/drm/amd/pm/inc/aldebaran_ppsmc.h   |   3 +-
 drivers/gpu/drm/amd/pm/inc/smu_types.h |   3 +-
 drivers/gpu/drm/amd/pm/inc/smu_v11_0.h |   2 +-
 drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c |  46 +++-
 29 files changed, 288 insertions(+), 483 deletions(-)
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Re: [PATCH] drm/amd/pm: Fix a bug communicating with the SMU (v5)

[Alex Deucher]

On Mon, Jul 19, 2021 at 7:18 PM Luben Tuikov  wrote:
>
> This fixes a bug which if we probe a non-existing
> I2C device, and the SMU returns 0xFF, from then on
> we can never communicate with the SMU, because the
> code before this patch reads and interprets 0xFF
> as a terminal error, and thus we never write 0
> into register 90 to clear the status (and
> subsequently send a new command to the SMU.)
>
> It is not an error that the SMU returns status
> 0xFF. This means that the SMU executed the last
> command successfully (execution status), but the
> command result is an error of some sort (execution
> result), depending on what the command was.
>
> When doing a status check of the SMU, before we
> send a new command, the only status which
> precludes us from sending a new command is 0--the
> SMU hasn't finished executing a previous command,
> and 0xFC--the SMU is busy.
>
> This bug was seen as the following line in the
> kernel log,
>
> amdgpu: Msg issuing pre-check failed(0xff) and SMU may be not in the right 
> state!
>
> when subsequent SMU commands, not necessarily
> related to I2C, were sent to the SMU.
>
> This patch fixes this bug.
>
> v2: Add a comment to the description of
> __smu_cmn_poll_stat() to explain why we're NOT
> defining the SMU FW return codes as macros, but
> are instead hard-coding them. Such a change, can
> be followed up by a subsequent patch.
>
> v3: The changes are,
> a) Add comments to break labels in
>__smu_cmn_reg2errno().
>
> b) When an unknown/unspecified/undefined result is
>returned back from the SMU, map that to
>-EREMOTEIO, to distinguish failure at the SMU
>FW.
>
> c) Add kernel-doc to
>smu_cmn_send_msg_without_waiting(),
>smu_cmn_wait_for_response(),
>smu_cmn_send_smc_msg_with_param().
>
> d) In smu_cmn_send_smc_msg_with_param(), since we
>wait for completion of the command, if the
>result of the completion is
>undefined/unknown/unspecified, we print that to
>the kernel log.
>
> v4: a) Add macros as requested, though redundant, to
> be removed when SMU consolidates for all
> ASICs--see comment in code.
> b) Get out if the SMU code is unknown.
>
> v5: Rename the macro names.
>
> Cc: Alex Deucher 
> Cc: Evan Quan 
> Cc: Lijo Lazar 
> Fixes: fcb1fe9c9e0031 ("drm/amd/powerplay: pre-check the SMU state before 
> issuing message")
> Signed-off-by: Luben Tuikov 

This looks pretty good to me.  I think it should address Lijo's
concerns while still properly handling the error case with stuff like
i2c.

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 288 +
>  drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h |   3 +-
>  2 files changed, 244 insertions(+), 47 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c 
> b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
> index c902fdf322c1be..baf26d5bfb8ff4 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
> @@ -55,7 +55,7 @@
>
>  #undef __SMU_DUMMY_MAP
>  #define __SMU_DUMMY_MAP(type)  #type
> -static const char* __smu_message_names[] = {
> +static const char * const __smu_message_names[] = {
> SMU_MESSAGE_TYPES
>  };
>
> @@ -76,55 +76,258 @@ static void smu_cmn_read_arg(struct smu_context *smu,
> *arg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
>  }
>
> -int smu_cmn_wait_for_response(struct smu_context *smu)
> +/* Redefine the SMU error codes here.
> + *
> + * Note that these definitions are redundant and should be removed
> + * when the SMU has exported a unified header file containing these
> + * macros, which header file we can just include and use the SMU's
> + * macros. At the moment, these error codes are defined by the SMU
> + * per-ASIC unfortunately, yet we're a one driver for all ASICs.
> + */
> +#define SMU_RESP_NONE   0
> +#define SMU_RESP_OK 1
> +#define SMU_RESP_CMD_FAIL   0xFF
> +#define SMU_RESP_CMD_UNKNOWN0xFE
> +#define SMU_RESP_CMD_BAD_PREREQ 0xFD
> +#define SMU_RESP_BUSY_OTHER 0xFC
> +#define SMU_RESP_DEBUG_END  0xFB
> +
> +/**
> + * __smu_cmn_poll_stat -- poll for a status from the SMU
> + * smu: a pointer to SMU context
> + *
> + * Returns the status of the SMU, which could be,
> + *0, the SMU is busy with your previous command;
> + *1, execution status: success, execution result: success;
> + * 0xFF, execution status: success, execution result: failure;
> + * 0xFE, unknown command;
> + * 0xFD, valid command, but bad (command) prerequisites;
> + * 0xFC, the command was rejected as the SMU is busy;
> + * 0xFB, "SMC_Result_DebugDataDumpEnd".
> + *
> + * The values here are not defined by macros, because I'd rather we
> + * include a single header file which defines them, which is
> + * maintained by the SMU FW team, so that we're impervious to firmware
> + * changes. At the moment those values are defined in various header
> + * files, one for each ASIC, yet here we're a single ASIC-agnostic
> + * 

[PATCH 3/3] drm/amdgpu: replace dce_virtual with amdgpu_vkms (v3)

[Ryan Taylor]

Move dce_virtual into amdgpu_vkms and update all references to
dce_virtual with amdgpu_vkms.

v2: Removed more references to dce_virtual.

v3: Restored display modes from previous implementation.

Reported-by: kernel test robot 
Suggested-by: Alex Deucher 
Signed-off-by: Ryan Taylor 
---
 drivers/gpu/drm/amd/amdgpu/Makefile  |   3 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 234 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.h |   5 +-
 drivers/gpu/drm/amd/amdgpu/cik.c |  10 +-
 drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 223 -
 drivers/gpu/drm/amd/amdgpu/dce_virtual.h |  30 ---
 drivers/gpu/drm/amd/amdgpu/nv.c  |  20 +-
 drivers/gpu/drm/amd/amdgpu/si.c  |   8 +-
 drivers/gpu/drm/amd/amdgpu/soc15.c   |  10 +-
 drivers/gpu/drm/amd/amdgpu/vi.c  |  14 +-
 10 files changed, 264 insertions(+), 293 deletions(-)
 delete mode 100644 drivers/gpu/drm/amd/amdgpu/dce_virtual.c
 delete mode 100644 drivers/gpu/drm/amd/amdgpu/dce_virtual.h

diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile 
b/drivers/gpu/drm/amd/amdgpu/Makefile
index 30cbcd5ce1cc..0d814c957461 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -120,8 +120,7 @@ amdgpu-y += \
 amdgpu-y += \
dce_v10_0.o \
dce_v11_0.o \
-   amdgpu_vkms.o \
-   dce_virtual.o
+   amdgpu_vkms.o
 
 # add GFX block
 amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
index d5c1f1c58f5f..538d41ea 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
@@ -5,6 +5,15 @@
 #include 
 
 #include "amdgpu.h"
+#ifdef CONFIG_DRM_AMDGPU_SI
+#include "dce_v6_0.h"
+#endif
+#ifdef CONFIG_DRM_AMDGPU_CIK
+#include "dce_v8_0.h"
+#endif
+#include "dce_v10_0.h"
+#include "dce_v11_0.h"
+#include "ivsrcid/ivsrcid_vislands30.h"
 #include "amdgpu_vkms.h"
 #include "amdgpu_display.h"
 
@@ -180,12 +189,45 @@ static const struct drm_connector_funcs 
amdgpu_vkms_connector_funcs = {
 
 static int amdgpu_vkms_conn_get_modes(struct drm_connector *connector)
 {
-   int count;
+   struct drm_device *dev = connector->dev;
+   struct drm_display_mode *mode = NULL;
+   unsigned i;
+   static const struct mode_size {
+   int w;
+   int h;
+   } common_modes[] = {
+   { 640,  480},
+   { 720,  480},
+   { 800,  600},
+   { 848,  480},
+   {1024,  768},
+   {1152,  768},
+   {1280,  720},
+   {1280,  800},
+   {1280,  854},
+   {1280,  960},
+   {1280, 1024},
+   {1440,  900},
+   {1400, 1050},
+   {1680, 1050},
+   {1600, 1200},
+   {1920, 1080},
+   {1920, 1200},
+   {2560, 1440},
+   {4096, 3112},
+   {3656, 2664},
+   {3840, 2160},
+   {4096, 2160},
+   };
+
+   for (i = 0; i < ARRAY_SIZE(common_modes); i++) {
+   mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 
60, false, false, false);
+   drm_mode_probed_add(connector, mode);
+   }
 
-   count = drm_add_modes_noedid(connector, XRES_MAX, YRES_MAX);
drm_set_preferred_mode(connector, XRES_DEF, YRES_DEF);
 
-   return count;
+   return ARRAY_SIZE(common_modes);
 }
 
 static const struct drm_connector_helper_funcs amdgpu_vkms_conn_helper_funcs = 
{
@@ -409,3 +451,189 @@ int amdgpu_vkms_output_init(struct drm_device *dev,
 
return ret;
 }
+
+const struct drm_mode_config_funcs amdgpu_vkms_mode_funcs = {
+   .fb_create = amdgpu_display_user_framebuffer_create,
+   .atomic_check = drm_atomic_helper_check,
+   .atomic_commit = drm_atomic_helper_commit,
+};
+
+static int amdgpu_vkms_sw_init(void *handle)
+{
+   int r, i;
+   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+   adev_to_drm(adev)->max_vblank_count = 0;
+
+   adev_to_drm(adev)->mode_config.funcs = _vkms_mode_funcs;
+
+   adev_to_drm(adev)->mode_config.max_width = XRES_MAX;
+   adev_to_drm(adev)->mode_config.max_height = YRES_MAX;
+
+   adev_to_drm(adev)->mode_config.preferred_depth = 24;
+   adev_to_drm(adev)->mode_config.prefer_shadow = 1;
+
+   adev_to_drm(adev)->mode_config.fb_base = adev->gmc.aper_base;
+
+   r = amdgpu_display_modeset_create_props(adev);
+   if (r)
+   return r;
+
+   adev->amdgpu_vkms_output = kzalloc(sizeof(struct amdgpu_vkms_output) * 
adev->mode_info.num_crtc, GFP_KERNEL);
+
+   /* allocate crtcs, encoders, connectors */
+   for (i = 0; i < adev->mode_info.num_crtc; i++) {
+   r = amdgpu_vkms_output_init(adev_to_drm(adev), 
>amdgpu_vkms_output[i], i);
+   if (r)
+   return r;
+   }
+
+   

[PATCH 2/3] drm/amdgpu: cleanup dce_virtual

[Ryan Taylor]

Remove obsolete functions and variables from dce_virtual.

Signed-off-by: Ryan Taylor 
---
 drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 568 +--
 1 file changed, 3 insertions(+), 565 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c 
b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
index 642c77533157..18369b47eac7 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
@@ -21,15 +21,9 @@
  *
  */
 
-#include 
 #include 
 
 #include "amdgpu.h"
-#include "amdgpu_pm.h"
-#include "amdgpu_i2c.h"
-#include "atom.h"
-#include "amdgpu_pll.h"
-#include "amdgpu_connectors.h"
 #ifdef CONFIG_DRM_AMDGPU_SI
 #include "dce_v6_0.h"
 #endif
@@ -43,339 +37,6 @@
 #include "amdgpu_display.h"
 #include "amdgpu_vkms.h"
 
-#define DCE_VIRTUAL_VBLANK_PERIOD 1666
-
-
-static void dce_virtual_set_display_funcs(struct amdgpu_device *adev);
-static void dce_virtual_set_irq_funcs(struct amdgpu_device *adev);
-static int dce_virtual_connector_encoder_init(struct amdgpu_device *adev,
- int index);
-static int dce_virtual_pageflip(struct amdgpu_device *adev,
-   unsigned crtc_id);
-static enum hrtimer_restart dce_virtual_vblank_timer_handle(struct hrtimer 
*vblank_timer);
-static void dce_virtual_set_crtc_vblank_interrupt_state(struct amdgpu_device 
*adev,
-   int crtc,
-   enum 
amdgpu_interrupt_state state);
-
-static u32 dce_virtual_vblank_get_counter(struct amdgpu_device *adev, int crtc)
-{
-   return 0;
-}
-
-static void dce_virtual_page_flip(struct amdgpu_device *adev,
- int crtc_id, u64 crtc_base, bool async)
-{
-   return;
-}
-
-static int dce_virtual_crtc_get_scanoutpos(struct amdgpu_device *adev, int 
crtc,
-   u32 *vbl, u32 *position)
-{
-   *vbl = 0;
-   *position = 0;
-
-   return -EINVAL;
-}
-
-static bool dce_virtual_hpd_sense(struct amdgpu_device *adev,
-  enum amdgpu_hpd_id hpd)
-{
-   return true;
-}
-
-static void dce_virtual_hpd_set_polarity(struct amdgpu_device *adev,
- enum amdgpu_hpd_id hpd)
-{
-   return;
-}
-
-static u32 dce_virtual_hpd_get_gpio_reg(struct amdgpu_device *adev)
-{
-   return 0;
-}
-
-/**
- * dce_virtual_bandwidth_update - program display watermarks
- *
- * @adev: amdgpu_device pointer
- *
- * Calculate and program the display watermarks and line
- * buffer allocation (CIK).
- */
-static void dce_virtual_bandwidth_update(struct amdgpu_device *adev)
-{
-   return;
-}
-
-static int dce_virtual_crtc_gamma_set(struct drm_crtc *crtc, u16 *red,
- u16 *green, u16 *blue, uint32_t size,
- struct drm_modeset_acquire_ctx *ctx)
-{
-   return 0;
-}
-
-static void dce_virtual_crtc_destroy(struct drm_crtc *crtc)
-{
-   struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
-
-   drm_crtc_cleanup(crtc);
-   kfree(amdgpu_crtc);
-}
-
-static const struct drm_crtc_funcs dce_virtual_crtc_funcs = {
-   .cursor_set2 = NULL,
-   .cursor_move = NULL,
-   .gamma_set = dce_virtual_crtc_gamma_set,
-   .set_config = amdgpu_display_crtc_set_config,
-   .destroy = dce_virtual_crtc_destroy,
-   .page_flip_target = amdgpu_display_crtc_page_flip_target,
-   .get_vblank_counter = amdgpu_get_vblank_counter_kms,
-   .enable_vblank = amdgpu_enable_vblank_kms,
-   .disable_vblank = amdgpu_disable_vblank_kms,
-   .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
-};
-
-static void dce_virtual_crtc_dpms(struct drm_crtc *crtc, int mode)
-{
-   struct drm_device *dev = crtc->dev;
-   struct amdgpu_device *adev = drm_to_adev(dev);
-   struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
-   unsigned type;
-
-   switch (mode) {
-   case DRM_MODE_DPMS_ON:
-   amdgpu_crtc->enabled = true;
-   /* Make sure VBLANK interrupts are still enabled */
-   type = amdgpu_display_crtc_idx_to_irq_type(adev,
-   amdgpu_crtc->crtc_id);
-   amdgpu_irq_update(adev, >crtc_irq, type);
-   drm_crtc_vblank_on(crtc);
-   break;
-   case DRM_MODE_DPMS_STANDBY:
-   case DRM_MODE_DPMS_SUSPEND:
-   case DRM_MODE_DPMS_OFF:
-   drm_crtc_vblank_off(crtc);
-   amdgpu_crtc->enabled = false;
-   break;
-   }
-}
-
-
-static void dce_virtual_crtc_prepare(struct drm_crtc *crtc)
-{
-   dce_virtual_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
-}
-
-static void dce_virtual_crtc_commit(struct drm_crtc *crtc)
-{
-   dce_virtual_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
-}
-
-static void dce_virtual_crtc_disable(struct drm_crtc *crtc)
-{
-

[PATCH 1/3] drm/amdgpu: create amdgpu_vkms (v2)

[Ryan Taylor]

Modify the VKMS driver into an api that dce_virtual can use to create
virtual displays that obey drm's atomic modesetting api.

v2: Made local functions static.

Reported-by: kernel test robot 
Signed-off-by: Ryan Taylor 
---
 drivers/gpu/drm/amd/amdgpu/Makefile  |   1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu.h  |   1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c  |   2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c   |   2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 411 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.h |  29 ++
 drivers/gpu/drm/amd/amdgpu/dce_virtual.c |  23 +-
 7 files changed, 458 insertions(+), 11 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
 create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.h

diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile 
b/drivers/gpu/drm/amd/amdgpu/Makefile
index f089794bbdd5..30cbcd5ce1cc 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -120,6 +120,7 @@ amdgpu-y += \
 amdgpu-y += \
dce_v10_0.o \
dce_v11_0.o \
+   amdgpu_vkms.o \
dce_virtual.o
 
 # add GFX block
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 54cf647bd018..d0a2f2ed433d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -919,6 +919,7 @@ struct amdgpu_device {
 
/* display */
boolenable_virtual_display;
+   struct amdgpu_vkms_output   *amdgpu_vkms_output;
struct amdgpu_mode_info mode_info;
/* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */
struct work_struct  hotplug_work;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index d0c935cf4f0f..1b016e5bc75f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -1230,7 +1230,7 @@ static int amdgpu_pci_probe(struct pci_dev *pdev,
int ret, retry = 0;
bool supports_atomic = false;
 
-   if (!amdgpu_virtual_display &&
+   if (amdgpu_virtual_display ||
amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK))
supports_atomic = true;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
index 09b048647523..5a143ca02cf9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
@@ -344,7 +344,7 @@ int amdgpu_fbdev_init(struct amdgpu_device *adev)
}
 
/* disable all the possible outputs/crtcs before entering KMS mode */
-   if (!amdgpu_device_has_dc_support(adev))
+   if (!amdgpu_device_has_dc_support(adev) && !amdgpu_virtual_display)
drm_helper_disable_unused_functions(adev_to_drm(adev));
 
drm_fb_helper_initial_config(>helper, bpp_sel);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
new file mode 100644
index ..d5c1f1c58f5f
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
@@ -0,0 +1,411 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include 
+#include 
+#include 
+
+#include "amdgpu.h"
+#include "amdgpu_vkms.h"
+#include "amdgpu_display.h"
+
+/**
+ * DOC: amdgpu_vkms
+ *
+ * The amdgpu vkms interface provides a virtual KMS interface for several use
+ * cases: devices without display hardware, platforms where the actual display
+ * hardware is not useful (e.g., servers), SR-IOV virtual functions, device
+ * emulation/simulation, and device bring up prior to display hardware being
+ * usable. We previously emulated a legacy KMS interface, but there was a 
desire
+ * to move to the atomic KMS interface. The vkms driver did everything we
+ * needed, but we wanted KMS support natively in the driver without buffer
+ * sharing and the ability to support an instance of VKMS per device. We first
+ * looked at splitting vkms into a stub driver and a helper module that other
+ * drivers could use to implement a virtual display, but this strategy ended up
+ * being messy due to driver specific callbacks needed for buffer management.
+ * Ultimately, it proved easier to import the vkms code as it mostly used core
+ * drm helpers anyway.
+ */
+
+static const u32 amdgpu_vkms_formats[] = {
+   DRM_FORMAT_XRGB,
+};
+
+static enum hrtimer_restart amdgpu_vkms_vblank_simulate(struct hrtimer *timer)
+{
+   struct amdgpu_vkms_output *output = container_of(timer,
+struct 
amdgpu_vkms_output,
+vblank_hrtimer);
+   struct drm_crtc *crtc = >crtc;
+   u64 ret_overrun;
+   bool ret;
+
+   ret_overrun = hrtimer_forward_now(>vblank_hrtimer,
+ output->period_ns);
+   WARN_ON(ret_overrun != 1);
+
+   ret = drm_crtc_handle_vblank(crtc);
+   

[PATCH 0/3] drm/amdgpu: modernize virtual display feature

[Ryan Taylor]

The amdgpu vkms interface provides a virtual KMS interface for several use
cases: devices without display hardware, platforms where the actual display
hardware is not useful (e.g., servers), SR-IOV virtual functions, device
emulation/simulation, and device bring up prior to display hardware being
usable. We previously emulated a legacy KMS interface, but there was a desire
to move to the atomic KMS interface. The vkms driver did everything we
needed, but we wanted KMS support natively in the driver without buffer
sharing and the ability to support an instance of VKMS per device. We first
looked at splitting vkms into a stub driver and a helper module that other
drivers could use to implement a virtual display, but this strategy ended up
being messy due to driver specific callbacks needed for buffer management.
Ultimately, it proved easier to import the vkms code as it mostly used core
drm helpers anyway.

Ryan Taylor (3):
  drm/amdgpu: create amdgpu_vkms (v2)
  drm/amdgpu: cleanup dce_virtual
  drm/amdgpu: replace dce_virtual with amdgpu_vkms (v3)

 drivers/gpu/drm/amd/amdgpu/Makefile  |   2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu.h  |   1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c  |   2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c   |   2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 639 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.h |  26 +
 drivers/gpu/drm/amd/amdgpu/cik.c |  10 +-
 drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 780 ---
 drivers/gpu/drm/amd/amdgpu/dce_virtual.h |  30 -
 drivers/gpu/drm/amd/amdgpu/nv.c  |  20 +-
 drivers/gpu/drm/amd/amdgpu/si.c  |   8 +-
 drivers/gpu/drm/amd/amdgpu/soc15.c   |  10 +-
 drivers/gpu/drm/amd/amdgpu/vi.c  |  14 +-
 13 files changed, 700 insertions(+), 844 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
 create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.h
 delete mode 100644 drivers/gpu/drm/amd/amdgpu/dce_virtual.c
 delete mode 100644 drivers/gpu/drm/amd/amdgpu/dce_virtual.h


base-commit: cfd09f1e35231aa7f69845b6195e7d935e81421d
-- 
2.32.0

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Re: [PATCH 2/2] drm: add tdr support for embeded hw_fence

[Andrey Grodzovsky]

On 2021-07-20 11:13 p.m., Jingwen Chen wrote:

[Why]
After embeded hw_fence to amdgpu_job, we need to add tdr support
for this feature.

[How]
1. Add a resubmit_flag for resubmit jobs.
2. Clear job fence from RCU and force complete vm flush fences in
pre_asic_reset
3. skip dma_fence_get for resubmit jobs and add a dma_fence_put
for guilty jobs.

Signed-off-by: Jack Zhang 
Signed-off-by: Jingwen Chen 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 12 +++-
  drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c  | 16 +++-
  drivers/gpu/drm/amd/amdgpu/amdgpu_job.c|  4 +++-
  drivers/gpu/drm/scheduler/sched_main.c |  1 +
  include/drm/gpu_scheduler.h|  1 +
  5 files changed, 27 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 40461547701a..fe0237f72a09 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -4382,7 +4382,7 @@ int amdgpu_device_mode1_reset(struct amdgpu_device *adev)
  int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
 struct amdgpu_reset_context *reset_context)
  {
-   int i, r = 0;
+   int i, j, r = 0;
struct amdgpu_job *job = NULL;
bool need_full_reset =
test_bit(AMDGPU_NEED_FULL_RESET, _context->flags);
@@ -4406,6 +4406,16 @@ int amdgpu_device_pre_asic_reset(struct amdgpu_device 
*adev,
if (!ring || !ring->sched.thread)
continue;
  
+		/*clear job fence from fence drv to avoid force_completion

+*leave NULL and vm flush fence in fence drv */
+   for (j = 0; j <= ring->fence_drv.num_fences_mask; j ++) {
+   struct dma_fence *old,**ptr;
+   ptr = >fence_drv.fences[j];
+   old = rcu_dereference_protected(*ptr, 1);
+   if (old && test_bit(DMA_FENCE_FLAG_USER_BITS, 
>flags))) {
+   RCU_INIT_POINTER(*ptr, NULL);
+   }



Is this to avoid premature job free because of dma_fence_put inside 
amdgpu_fence_process ?
I can't currently remember why but we probably want all the HW fences 
currently in the ring to
be forced signaled - maybe better to test for DMA_FENCE_FLAG_USER_BITS 
inside amdgpu_fence_process

and still do the signaling but not the dma_fence_put part

Andrey



+   }
/* after all hw jobs are reset, hw fence is meaningless, so 
force_completion */
amdgpu_fence_driver_force_completion(ring);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
index eecf21d8ec33..815776c9a013 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
@@ -156,11 +156,17 @@ int amdgpu_fence_emit(struct amdgpu_ring *ring, struct 
dma_fence **f, struct amd
job->ring = ring;
}
  
-	seq = ++ring->fence_drv.sync_seq;

-   dma_fence_init(fence, _fence_ops,
-  >fence_drv.lock,
-  adev->fence_context + ring->idx,
-  seq);
+   if (job != NULL && job->base.resubmit_flag == 1) {
+   /* reinit seq for resubmitted jobs */
+   seq = ++ring->fence_drv.sync_seq;
+   fence->seqno = seq;
+   } else {
+   seq = ++ring->fence_drv.sync_seq;



Seems like you could do the above line only once above if-else as it was 
before




+   dma_fence_init(fence, _fence_ops,
+   >fence_drv.lock,
+   adev->fence_context + ring->idx,
+   seq);
+   }
  
  	if (job != NULL) {

/* mark this fence has a parent job */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
index 7c426e225b24..d6f848adc3f4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
@@ -241,6 +241,7 @@ static struct dma_fence *amdgpu_job_run(struct 
drm_sched_job *sched_job)
dma_fence_set_error(finished, -ECANCELED);/* skip IB as well if 
VRAM lost */
  
  	if (finished->error < 0) {

+   dma_fence_put(>hw_fence);
DRM_INFO("Skip scheduling IBs!\n");
} else {
r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs, job,
@@ -249,7 +250,8 @@ static struct dma_fence *amdgpu_job_run(struct 
drm_sched_job *sched_job)
DRM_ERROR("Error scheduling IBs (%d)\n", r);
}
  
-	dma_fence_get(fence);

+   if (!job->base.resubmit_flag)
+   dma_fence_get(fence);
amdgpu_job_free_resources(job);
  
  	fence = r ? ERR_PTR(r) : fence;

diff --git a/drivers/gpu/drm/scheduler/sched_main.c 
b/drivers/gpu/drm/scheduler/sched_main.c
index 

Re: [PATCH] drm/amdgpu: Clear doorbell interrupt status for Sienna Cichlid

[Luben Tuikov]

Yeah, looks good.

Acked-by: Luben Tuikov 

On 2021-07-20 11:02 p.m., Chengzhe Liu wrote:
> On Sienna Cichlid, in pass-through mode, if we unload the driver in BACO
> mode(RTPM), then the kernel would receive thousands of interrupts.
> That's because there is doorbell monitor interrupt on BIF, so KVM keeps
> injecting interrupts to the guest VM. So we should clear the doorbell
> interrupt status after BACO exit.
>
> v2: Modify coding style and commit message
>
> Signed-off-by: Chengzhe Liu 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  4 
>  drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h   |  1 +
>  drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c | 21 +
>  3 files changed, 26 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 37fa199be8b3..92f73d2bbfc9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -5265,6 +5265,10 @@ int amdgpu_device_baco_exit(struct drm_device *dev)
>   adev->nbio.funcs->enable_doorbell_interrupt)
>   adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
>  
> + if (amdgpu_passthrough(adev) &&
> + adev->nbio.funcs->clear_doorbell_interrupt)
> + adev->nbio.funcs->clear_doorbell_interrupt(adev);
> +
>   return 0;
>  }
>  
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
> index 45295dce5c3e..843052205bd5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
> @@ -95,6 +95,7 @@ struct amdgpu_nbio_funcs {
>   void (*program_aspm)(struct amdgpu_device *adev);
>   void (*apply_lc_spc_mode_wa)(struct amdgpu_device *adev);
>   void (*apply_l1_link_width_reconfig_wa)(struct amdgpu_device *adev);
> + void (*clear_doorbell_interrupt)(struct amdgpu_device *adev);
>  };
>  
>  struct amdgpu_nbio {
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c 
> b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
> index 7b79eeaa88aa..b184b656b9b6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
> @@ -508,6 +508,26 @@ static void 
> nbio_v2_3_apply_l1_link_width_reconfig_wa(struct amdgpu_device *adev
>   WREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL, reg_data);
>  }
>  
> +static void nbio_v2_3_clear_doorbell_interrupt(struct amdgpu_device *adev)
> +{
> + uint32_t reg, reg_data;
> +
> + if (adev->asic_type != CHIP_SIENNA_CICHLID)
> + return;
> +
> + reg = RREG32_SOC15(NBIO, 0, mmBIF_RB_CNTL);
> +
> + /* Clear Interrupt Status
> +  */
> + if ((reg & BIF_RB_CNTL__RB_ENABLE_MASK) == 0) {
> + reg = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL);
> + if (reg & 
> BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS_MASK) {
> + reg_data = 1 << 
> BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT;
> + WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, 
> reg_data);
> + }
> + }
> +}
> +
>  const struct amdgpu_nbio_funcs nbio_v2_3_funcs = {
>   .get_hdp_flush_req_offset = nbio_v2_3_get_hdp_flush_req_offset,
>   .get_hdp_flush_done_offset = nbio_v2_3_get_hdp_flush_done_offset,
> @@ -531,4 +551,5 @@ const struct amdgpu_nbio_funcs nbio_v2_3_funcs = {
>   .program_aspm =  nbio_v2_3_program_aspm,
>   .apply_lc_spc_mode_wa = nbio_v2_3_apply_lc_spc_mode_wa,
>   .apply_l1_link_width_reconfig_wa = 
> nbio_v2_3_apply_l1_link_width_reconfig_wa,
> + .clear_doorbell_interrupt = nbio_v2_3_clear_doorbell_interrupt,
>  };

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[PATCH 1/2] drm/amdgpu: update yellow carp external rev_id handling

[Alex Deucher]

From: Aaron Liu 

0x1681 has a different external revision id.

Signed-off-by: Aaron Liu 
Reviewed-by: Huang Rui 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/nv.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 751c7b8b13e6..94d029dbf30d 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -1236,7 +1236,10 @@ static int nv_common_early_init(void *handle)
AMD_PG_SUPPORT_VCN |
AMD_PG_SUPPORT_VCN_DPG |
AMD_PG_SUPPORT_JPEG;
-   adev->external_rev_id = adev->rev_id + 0x01;
+   if (adev->pdev->device == 0x1681)
+   adev->external_rev_id = adev->rev_id + 0x19;
+   else
+   adev->external_rev_id = adev->rev_id + 0x01;
break;
default:
/* FIXME: not supported yet */
-- 
2.31.1

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[PATCH 2/2] drm/amdgpu: add yellow carp pci id (v2)

[Alex Deucher]

From: Aaron Liu 

Add Yellow Carp PCI id support.

v2: add another DID

Signed-off-by: Aaron Liu 
Reviewed-by: Huang Rui 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 1db106b135f9..503a5fd0abaa 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -1188,6 +1188,10 @@ static const struct pci_device_id pciidlist[] = {
/* Van Gogh */
{0x1002, 0x163F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VANGOGH|AMD_IS_APU},
 
+   /* Yellow Carp */
+   {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_YELLOW_CARP|AMD_IS_APU},
+   {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
CHIP_YELLOW_CARP|AMD_IS_APU},
+
/* Navy_Flounder */
{0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
{0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
-- 
2.31.1

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Re: [PATCH v2 0/2] Fix regression on embedded panels caused by enabling ASSR

[Deucher, Alexander]

[Public]

Series looks good to me. Thanks!

Alex


From: amd-gfx  on behalf of Stylon Wang 

Sent: Wednesday, July 21, 2021 12:25 AM
To: amd-gfx@lists.freedesktop.org 
Cc: Wang, Chao-kai (Stylon) ; Li, Sun peng (Leo) 
; Wentland, Harry ; Zhuo, Qingqing 
; Siqueira, Rodrigo ; Jacob, 
Anson ; Pillai, Aurabindo ; 
Lakha, Bhawanpreet ; R, Bindu 
Subject: [PATCH v2 0/2] Fix regression on embedded panels caused by enabling 
ASSR

Previous ASSR-enabling patches cause blank screen on some embedded
panels. This patch set minimize the changes made to code logic prior to
the ASSR change and also improve on code readability.

Changes from prior rev1 to now:

v2:
 - Update reviewed-by and bug links

Stylon Wang (2):
  drm/amd/display: Revert "Re-enable 'Guard ASSR with internal display
flag'"
  drm/amd/display: Fix ASSR regression on embedded panels

 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 58 +++
 1 file changed, 20 insertions(+), 38 deletions(-)

--
2.32.0

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[RESEND PATCH v6 06/14] drm/amd: Gate i2c transaction logs on drm_debug_syslog

[Sean Paul]

From: Sean Paul 

Since the logs protected by these checks specifically target syslog,
use the new drm_debug_syslog_enabled() call to avoid triggering
these prints when only trace is enabled.

Acked-by: Christian König 
Signed-off-by: Sean Paul 
Link: 
https://patchwork.freedesktop.org/patch/msgid/20200608210505.48519-7-s...@poorly.run
 #v5

Changes in v5:
-Added to the set
Changes in v6:
-None
---
 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c 
b/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c
index 5c7d769aee3f..d9ceab332060 100644
--- a/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c
+++ b/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c
@@ -233,7 +233,7 @@ static uint32_t smu_v11_0_i2c_transmit(struct i2c_adapter 
*control,
DRM_DEBUG_DRIVER("I2C_Transmit(), address = %x, bytes = %d , data: ",
 (uint16_t)address, numbytes);
 
-   if (drm_debug_enabled(DRM_UT_DRIVER)) {
+   if (drm_debug_syslog_enabled(DRM_UT_DRIVER)) {
print_hex_dump(KERN_INFO, "data: ", DUMP_PREFIX_NONE,
   16, 1, data, numbytes, false);
}
@@ -389,7 +389,7 @@ static uint32_t smu_v11_0_i2c_receive(struct i2c_adapter 
*control,
DRM_DEBUG_DRIVER("I2C_Receive(), address = %x, bytes = %d, data :",
  (uint16_t)address, bytes_received);
 
-   if (drm_debug_enabled(DRM_UT_DRIVER)) {
+   if (drm_debug_syslog_enabled(DRM_UT_DRIVER)) {
print_hex_dump(KERN_INFO, "data: ", DUMP_PREFIX_NONE,
   16, 1, data, bytes_received, false);
}
-- 
Sean Paul, Software Engineer, Google / Chromium OS

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[PATCH] drm/amd/amdgpu: add consistent PSP FW loading size checking

[Li, Candice]

[Public]

Signed-off-by: Candice Li candice...@amd.com
---
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c   |   8 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c   | 108 --
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h   |  32 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c |   2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c  |   2 +-
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c|   4 +-
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c|   8 +-
drivers/gpu/drm/amd/amdgpu/psp_v12_0.c|   4 +-
drivers/gpu/drm/amd/amdgpu/psp_v13_0.c|   6 +-
drivers/gpu/drm/amd/amdgpu/psp_v3_1.c |   4 +-
drivers/gpu/drm/amd/amdgpu/soc15.c|   4 +-
11 files changed, 96 insertions(+), 86 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 66bf8b0c56bb..c239de0ace4f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -373,8 +373,8 @@ static int amdgpu_firmware_info(struct 
drm_amdgpu_info_firmware *fw_info,
fw_info->feature = 
adev->sdma.instance[query_fw->index].feature_version;
break;
 case AMDGPU_INFO_FW_SOS:
-   fw_info->ver = adev->psp.sos_fw_version;
-   fw_info->feature = adev->psp.sos_feature_version;
+   fw_info->ver = adev->psp.sos.fw_version;
+   fw_info->feature = adev->psp.sos.feature_version;
break;
 case AMDGPU_INFO_FW_ASD:
fw_info->ver = adev->psp.asd_fw_version;
@@ -389,8 +389,8 @@ static int amdgpu_firmware_info(struct 
drm_amdgpu_info_firmware *fw_info,
fw_info->feature = 0;
break;
 case AMDGPU_INFO_FW_TOC:
-   fw_info->ver = adev->psp.toc_fw_version;
-   fw_info->feature = adev->psp.toc_feature_version;
+   fw_info->ver = adev->psp.toc.fw_version;
+   fw_info->feature = adev->psp.toc.feature_version;
break;
 default:
return -EINVAL;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index bd079979d5a3..14ade5dfef75 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -510,9 +510,9 @@ static int psp_load_toc(struct psp_context *psp,
return -ENOMEM;
 /* Copy toc to psp firmware private buffer */
 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
- memcpy(psp->fw_pri_buf, psp->toc_start_addr, psp->toc_bin_size);
+memcpy(psp->fw_pri_buf, psp->toc.start_addr, psp->toc.size_bytes);
- psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, 
psp->toc_bin_size);
+psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, 
psp->toc.size_bytes);
  ret = psp_cmd_submit_buf(psp, NULL, cmd,
  
psp->fence_buf_mc_addr);
@@ -542,8 +542,8 @@ static int psp_tmr_init(struct psp_context *psp)
 /* For ASICs support RLC autoload, psp will parse the toc
  * and calculate the total size of TMR needed */
 if (!amdgpu_sriov_vf(psp->adev) &&
- psp->toc_start_addr &&
- psp->toc_bin_size &&
+psp->toc.start_addr &&
+psp->toc.size_bytes &&
 psp->fw_pri_buf) {
ret = psp_load_toc(psp, _size);
if (ret) {
@@ -722,18 +722,18 @@ static int psp_rl_load(struct amdgpu_device *adev)
 struct psp_context *psp = >psp;
 struct psp_gfx_cmd_resp *cmd = psp->cmd;
- if (psp->rl_bin_size == 0)
+if (!is_psp_fw_valid(psp->rl))
return 0;
  memset(psp->fw_pri_buf, 0, PSP_1_MEG);
- memcpy(psp->fw_pri_buf, psp->rl_start_addr, psp->rl_bin_size);
+memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes);
  memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
  cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = 
lower_32_bits(psp->fw_pri_mc_addr);
 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = 
upper_32_bits(psp->fw_pri_mc_addr);
- cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl_bin_size;
+cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes;
 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST;
  return psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
@@ -2129,7 +2129,7 @@ static int psp_hw_start(struct psp_context *psp)
 int ret;
  if (!amdgpu_sriov_vf(adev)) {
-   if 

Re: [PATCH v5 0/2] Add p2p via dmabuf to habanalabs

[Greg KH]

On Sun, Jul 11, 2021 at 05:05:59PM +0300, Oded Gabbay wrote:
> Hi,
> This is v5 of this patch-set following again a long email thread.
> 
> It contains fixes to the implementation according to the review that Jason
> did on v4. Jason, I appreciate your feedback. If you can take another look
> to see I didn't miss anything that would be great.
> 
> The details of the fixes are in the changelog in the commit message of
> the second patch.
> 
> There was one issue with your proposal to set the orig_nents to 0. I did
> that, but I also had to restore it to nents before calling sg_free_table
> because that function uses orig_nents to iterate.

Reviewed-by: Greg Kroah-Hartman 
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Re: [PATCH v3 2/4] drm/amd/display: Add FPU event trace

[Christian König]

Am 21.07.21 um 13:44 schrieb Rodrigo Siqueira:

On 07/20, Christian König wrote:


Am 20.07.21 um 02:49 schrieb Rodrigo Siqueira:

We don't have any mechanism for tracing FPU operations inside the
display core, making the debug work a little bit tricky. This commit
introduces a trace mechanism inside our DC_FP_START/END macros for
trying to alleviate this problem.

Changes since V2:
- Make sure that we compile FPU operation only in the context that DCN
is enabled.

Cc: Harry Wentland 
Cc: Anson Jacob 
Cc: Christian König 
Cc: Hersen Wu 
Cc: Aric Cyr 
Signed-off-by: Rodrigo Siqueira 
---
   .../gpu/drm/amd/display/amdgpu_dm/Makefile|  4 ++
   .../amd/display/amdgpu_dm/amdgpu_dm_trace.h   | 21 ++
   .../gpu/drm/amd/display/amdgpu_dm/dc_fpu.c| 64 +++
   .../gpu/drm/amd/display/amdgpu_dm/dc_fpu.h| 33 ++
   drivers/gpu/drm/amd/display/dc/dc_trace.h |  3 +
   drivers/gpu/drm/amd/display/dc/os_types.h |  6 +-
   6 files changed, 128 insertions(+), 3 deletions(-)
   create mode 100644 drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c
   create mode 100644 drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.h

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/Makefile 
b/drivers/gpu/drm/amd/display/amdgpu_dm/Makefile
index 91fb72c96545..718e123a3230 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/Makefile
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/Makefile
@@ -27,6 +27,10 @@
   AMDGPUDM = amdgpu_dm.o amdgpu_dm_irq.o amdgpu_dm_mst_types.o 
amdgpu_dm_color.o
+ifdef CONFIG_DRM_AMD_DC_DCN
+AMDGPUDM += dc_fpu.o
+endif
+
   ifneq ($(CONFIG_DRM_AMD_DC),)
   AMDGPUDM += amdgpu_dm_services.o amdgpu_dm_helpers.o amdgpu_dm_pp_smu.o 
amdgpu_dm_psr.o
   endif
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
index 46a33f64cf8e..230bb12c405e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
@@ -637,6 +637,27 @@ TRACE_EVENT(amdgpu_refresh_rate_track,
  __entry->refresh_rate_ns)
   );
+TRACE_EVENT(dcn_fpu,
+   TP_PROTO(bool begin, const char *function, const int line),
+   TP_ARGS(begin, function, line),
+
+   TP_STRUCT__entry(
+__field(bool, begin)
+__field(const char *, function)
+__field(int, line)
+   ),
+   TP_fast_assign(
+  __entry->begin = begin;
+  __entry->function = function;
+  __entry->line = line;
+   ),
+   TP_printk("%s()+%d: %s",
+ __entry->function,
+ __entry->line,
+ __entry->begin ? "begin" : "end"
+   )
+);
+
   #endif /* _AMDGPU_DM_TRACE_H_ */
   #undef TRACE_INCLUDE_PATH
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c
new file mode 100644
index ..d5d156a4517e
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dc_trace.h"
+
+#include 
+
+/**
+ * dc_fpu_begin - Enables FPU protection
+ * @function_name: A string containing the function name for debug purposes
+ *   (usually __func__)
+ *
+ * @line: A line number where DC_FP_START was invoked for debug purpose
+ *   (usually __LINE__)
+ *
+ * This function is responsible for managing the use of kernel_fpu_begin() with
+ * the advantage of providing an event trace for debugging.
+ *
+ * Note: Do not call this function directly; always use DC_FP_START().
+ */
+void dc_fpu_begin(const char *function_name, const int line)
+{
+   TRACE_DCN_FPU(true, 

Re: [PATCH v3 2/4] drm/amd/display: Add FPU event trace

[Rodrigo Siqueira]

On 07/20, Christian König wrote:
> 
> 
> Am 20.07.21 um 02:49 schrieb Rodrigo Siqueira:
> > We don't have any mechanism for tracing FPU operations inside the
> > display core, making the debug work a little bit tricky. This commit
> > introduces a trace mechanism inside our DC_FP_START/END macros for
> > trying to alleviate this problem.
> > 
> > Changes since V2:
> > - Make sure that we compile FPU operation only in the context that DCN
> >is enabled.
> > 
> > Cc: Harry Wentland 
> > Cc: Anson Jacob 
> > Cc: Christian König 
> > Cc: Hersen Wu 
> > Cc: Aric Cyr 
> > Signed-off-by: Rodrigo Siqueira 
> > ---
> >   .../gpu/drm/amd/display/amdgpu_dm/Makefile|  4 ++
> >   .../amd/display/amdgpu_dm/amdgpu_dm_trace.h   | 21 ++
> >   .../gpu/drm/amd/display/amdgpu_dm/dc_fpu.c| 64 +++
> >   .../gpu/drm/amd/display/amdgpu_dm/dc_fpu.h| 33 ++
> >   drivers/gpu/drm/amd/display/dc/dc_trace.h |  3 +
> >   drivers/gpu/drm/amd/display/dc/os_types.h |  6 +-
> >   6 files changed, 128 insertions(+), 3 deletions(-)
> >   create mode 100644 drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c
> >   create mode 100644 drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.h
> > 
> > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/Makefile 
> > b/drivers/gpu/drm/amd/display/amdgpu_dm/Makefile
> > index 91fb72c96545..718e123a3230 100644
> > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/Makefile
> > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/Makefile
> > @@ -27,6 +27,10 @@
> >   AMDGPUDM = amdgpu_dm.o amdgpu_dm_irq.o amdgpu_dm_mst_types.o 
> > amdgpu_dm_color.o
> > +ifdef CONFIG_DRM_AMD_DC_DCN
> > +AMDGPUDM += dc_fpu.o
> > +endif
> > +
> >   ifneq ($(CONFIG_DRM_AMD_DC),)
> >   AMDGPUDM += amdgpu_dm_services.o amdgpu_dm_helpers.o amdgpu_dm_pp_smu.o 
> > amdgpu_dm_psr.o
> >   endif
> > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h 
> > b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
> > index 46a33f64cf8e..230bb12c405e 100644
> > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
> > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
> > @@ -637,6 +637,27 @@ TRACE_EVENT(amdgpu_refresh_rate_track,
> >   __entry->refresh_rate_ns)
> >   );
> > +TRACE_EVENT(dcn_fpu,
> > +   TP_PROTO(bool begin, const char *function, const int line),
> > +   TP_ARGS(begin, function, line),
> > +
> > +   TP_STRUCT__entry(
> > +__field(bool, begin)
> > +__field(const char *, function)
> > +__field(int, line)
> > +   ),
> > +   TP_fast_assign(
> > +  __entry->begin = begin;
> > +  __entry->function = function;
> > +  __entry->line = line;
> > +   ),
> > +   TP_printk("%s()+%d: %s",
> > + __entry->function,
> > + __entry->line,
> > + __entry->begin ? "begin" : "end"
> > +   )
> > +);
> > +
> >   #endif /* _AMDGPU_DM_TRACE_H_ */
> >   #undef TRACE_INCLUDE_PATH
> > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c 
> > b/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c
> > new file mode 100644
> > index ..d5d156a4517e
> > --- /dev/null
> > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c
> > @@ -0,0 +1,64 @@
> > +// SPDX-License-Identifier: MIT
> > +/*
> > + * Copyright 2021 Advanced Micro Devices, Inc.
> > + *
> > + * Permission is hereby granted, free of charge, to any person obtaining a
> > + * copy of this software and associated documentation files (the 
> > "Software"),
> > + * to deal in the Software without restriction, including without 
> > limitation
> > + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> > + * and/or sell copies of the Software, and to permit persons to whom the
> > + * Software is furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice shall be included 
> > in
> > + * all copies or substantial portions of the Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 
> > OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> > + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> > + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> > + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> > + * OTHER DEALINGS IN THE SOFTWARE.
> > + *
> > + * Authors: AMD
> > + *
> > + */
> > +
> > +#include "dc_trace.h"
> > +
> > +#include 
> > +
> > +/**
> > + * dc_fpu_begin - Enables FPU protection
> > + * @function_name: A string containing the function name for debug purposes
> > + *   (usually __func__)
> > + *
> > + * @line: A line number where DC_FP_START was invoked for debug purpose
> > + 

Re: [PATCH] drm/amdgpu/acp: Make PM domain really work

[Alex Deucher]

Applied.  Thanks!  I've removed the unused variables when I applied.

Alex

On Tue, Jul 20, 2021 at 1:31 PM Kai-Heng Feng
 wrote:
>
> Devices created by mfd_add_hotplug_devices() don't really increase the
> index of its name, so get_mfd_cell_dev() cannot find any device, hence a
> NULL dev is passed to pm_genpd_add_device():
> [   56.974926] (NULL device *): amdgpu: device acp_audio_dma.0.auto added to 
> pm domain
> [   56.974933] (NULL device *): amdgpu: Failed to add dev to genpd
> [   56.974941] [drm:amdgpu_device_ip_init [amdgpu]] *ERROR* hw_init of IP 
> block  failed -22
> [   56.975810] amdgpu :00:01.0: amdgpu: amdgpu_device_ip_init failed
> [   56.975839] amdgpu :00:01.0: amdgpu: Fatal error during GPU init
> [   56.977136] [ cut here ]
> [   56.977143] kernel BUG at mm/slub.c:4206!
> [   56.977158] invalid opcode:  [#1] SMP NOPTI
> [   56.977167] CPU: 1 PID: 1648 Comm: modprobe Not tainted 
> 5.12.0-051200rc8-generic #202104182230
> [   56.977175] Hardware name: To Be Filled By O.E.M. To Be Filled By 
> O.E.M./FM2A68M-HD+, BIOS P5.20 02/13/2019
> [   56.977180] RIP: 0010:kfree+0x3bf/0x410
> [   56.977195] Code: 89 e7 48 d3 e2 f7 da e8 5f 0d 02 00 80 e7 02 75 3e 44 89 
> ee 4c 89 e7 e8 ef 5f fd ff e9 fa fe ff ff 49 8b 44 24 08 a8 01 75 b7 <0f> 0b 
> 4c 8b 4d b0 48 8b 4d a8 48 89 da 4c 89 e6 41 b8 01 00 00 00
> [   56.977202] RSP: 0018:a48640ff79f0 EFLAGS: 00010246
> [   56.977210] RAX:  RBX: 9286127d5608 RCX: 
> 
> [   56.977215] RDX:  RSI: c099d0fb RDI: 
> 9286127d5608
> [   56.977220] RBP: a48640ff7a48 R08: 0001 R09: 
> 0001
> [   56.977224] R10:  R11: 9286087d8458 R12: 
> f3ae0449f540
> [   56.977229] R13:  R14: dead0122 R15: 
> dead0100
> [   56.977234] FS:  7f9de5929540() GS:928612e8() 
> knlGS:
> [   56.977240] CS:  0010 DS:  ES:  CR0: 80050033
> [   56.977245] CR2: 7f697dd97160 CR3: 0001110f CR4: 
> 001506e0
> [   56.977251] Call Trace:
> [   56.977261]  amdgpu_dm_encoder_destroy+0x1b/0x30 [amdgpu]
> [   56.978056]  drm_mode_config_cleanup+0x4f/0x2e0 [drm]
> [   56.978147]  ? kfree+0x3dd/0x410
> [   56.978157]  ? drm_managed_release+0xc8/0x100 [drm]
> [   56.978232]  drm_mode_config_init_release+0xe/0x10 [drm]
> [   56.978311]  drm_managed_release+0x9d/0x100 [drm]
> [   56.978388]  devm_drm_dev_init_release+0x4d/0x70 [drm]
> [   56.978450]  devm_action_release+0x15/0x20
> [   56.978459]  release_nodes+0x77/0xc0
> [   56.978469]  devres_release_all+0x3f/0x50
> [   56.978477]  really_probe+0x245/0x460
> [   56.978485]  driver_probe_device+0xe9/0x160
> [   56.978492]  device_driver_attach+0xab/0xb0
> [   56.978499]  __driver_attach+0x8f/0x150
> [   56.978506]  ? device_driver_attach+0xb0/0xb0
> [   56.978513]  bus_for_each_dev+0x7e/0xc0
> [   56.978521]  driver_attach+0x1e/0x20
> [   56.978528]  bus_add_driver+0x135/0x1f0
> [   56.978534]  driver_register+0x91/0xf0
> [   56.978540]  __pci_register_driver+0x54/0x60
> [   56.978549]  amdgpu_init+0x77/0x1000 [amdgpu]
> [   56.979246]  ? 0xc0dbc000
> [   56.979254]  do_one_initcall+0x48/0x1d0
> [   56.979265]  ? kmem_cache_alloc_trace+0x120/0x230
> [   56.979274]  ? do_init_module+0x28/0x280
> [   56.979282]  do_init_module+0x62/0x280
> [   56.979288]  load_module+0x71c/0x7a0
> [   56.979296]  __do_sys_finit_module+0xc2/0x120
> [   56.979305]  __x64_sys_finit_module+0x1a/0x20
> [   56.979311]  do_syscall_64+0x38/0x90
> [   56.979319]  entry_SYSCALL_64_after_hwframe+0x44/0xae
> [   56.979328] RIP: 0033:0x7f9de54f989d
> [   56.979335] Code: 00 c3 66 2e 0f 1f 84 00 00 00 00 00 90 f3 0f 1e fa 48 89 
> f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08 0f 05 <48> 3d 
> 01 f0 ff ff 73 01 c3 48 8b 0d c3 f5 0c 00 f7 d8 64 89 01 48
> [   56.979342] RSP: 002b:7ffe3c395a28 EFLAGS: 0246 ORIG_RAX: 
> 0139
> [   56.979350] RAX: ffda RBX: 560df3ef4330 RCX: 
> 7f9de54f989d
> [   56.979355] RDX:  RSI: 560df3a07358 RDI: 
> 000f
> [   56.979360] RBP: 0004 R08:  R09: 
> 
> [   56.979365] R10: 000f R11: 0246 R12: 
> 560df3a07358
> [   56.979369] R13:  R14: 560df3ef4460 R15: 
> 560df3ef4330
> [   56.979377] Modules linked in: amdgpu(+) iommu_v2 gpu_sched drm_ttm_helper 
> ttm drm_kms_helper cec rc_core i2c_algo_bit fb_sys_fops syscopyarea 
> sysfillrect sysimgblt nft_counter xt_tcpudp ipt_REJECT nf_reject_ipv4 
> xt_conntrack iptable_nat nf_nat nf_conntrack nf_defrag_ipv6 nf_defrag_ipv4 
> iptable_mangle iptable_raw iptable_security ip_set nf_tables libcrc32c 
> nfnetlink ip6_tables iptable_filter bpfilter input_leds binfmt_misc 
> edac_mce_amd kvm_amd ccp kvm snd_hda_codec_realtek snd_hda_codec_generic 
> crct10dif_pclmul 

Re: [RFC v2 2/2] drm/amd/display: Use PPC FPU functions

[Christian König]

Am 21.07.21 um 08:51 schrieb Christoph Hellwig:

On Wed, Jul 21, 2021 at 08:29:43AM +0200, Christian K??nig wrote:

Looks good in general, but question is what about other architectures like
ARM?

DRM_AMD_DC_DCN currently requires X86 || PPC64.


And exactly that's the problem I'm noting here. At least officially AMD 
claims that we support ARM and some very brave still use the hardware 
together with MIPS as well.



Maybe a good think would be to add a new KERNEL_FPU_API Kconfig symbol,
selected by x86 and powerpc (I think ppc32 should be fine too now) so
that we get these arch dependencies out of the driver.


Good idea.

Christian.
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Re: [RFC v2 2/2] drm/amd/display: Use PPC FPU functions

[Christian König]

Am 21.07.21 um 06:48 schrieb Anson Jacob:

Use kernel_fpu_begin & kernel_fpu_end for PPC

Depends on "ppc/fpu: Add generic FPU api similar to x86"

v2:
- Got rid of macro switch for PPC as header file with same
   name as x86 is added by previous patch in the series

Signed-off-by: Anson Jacob 
CC: Christoph Hellwig 
CC: Rodrigo Siqueira 
CC: Harry Wentland 
CC: Christian König 


Looks good in general, but question is what about other architectures 
like ARM?


Regards,
Christian.


---
  drivers/gpu/drm/amd/display/dc/os_types.h | 29 ---
  1 file changed, 29 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/os_types.h 
b/drivers/gpu/drm/amd/display/dc/os_types.h
index 126c2f3a4dd3..47ef434f93d8 100644
--- a/drivers/gpu/drm/amd/display/dc/os_types.h
+++ b/drivers/gpu/drm/amd/display/dc/os_types.h
@@ -51,38 +51,9 @@
  #define dm_error(fmt, ...) DRM_ERROR(fmt, ##__VA_ARGS__)
  
  #if defined(CONFIG_DRM_AMD_DC_DCN)

-#if defined(CONFIG_X86)
  #include 
  #define DC_FP_START() kernel_fpu_begin()
  #define DC_FP_END() kernel_fpu_end()
-#elif defined(CONFIG_PPC64)
-#include 
-#include 
-#define DC_FP_START() { \
-   if (cpu_has_feature(CPU_FTR_VSX_COMP)) { \
-   preempt_disable(); \
-   enable_kernel_vsx(); \
-   } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) { \
-   preempt_disable(); \
-   enable_kernel_altivec(); \
-   } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) { \
-   preempt_disable(); \
-   enable_kernel_fp(); \
-   } \
-}
-#define DC_FP_END() { \
-   if (cpu_has_feature(CPU_FTR_VSX_COMP)) { \
-   disable_kernel_vsx(); \
-   preempt_enable(); \
-   } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) { \
-   disable_kernel_altivec(); \
-   preempt_enable(); \
-   } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) { \
-   disable_kernel_fp(); \
-   preempt_enable(); \
-   } \
-}
-#endif
  #endif
  
  /*


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[RFC v2 2/2] drm/amd/display: Use PPC FPU functions

[Anson Jacob]

Use kernel_fpu_begin & kernel_fpu_end for PPC

Depends on "ppc/fpu: Add generic FPU api similar to x86"

v2:
- Got rid of macro switch for PPC as header file with same
  name as x86 is added by previous patch in the series

Signed-off-by: Anson Jacob 
CC: Christoph Hellwig 
CC: Rodrigo Siqueira 
CC: Harry Wentland 
CC: Christian König 
---
 drivers/gpu/drm/amd/display/dc/os_types.h | 29 ---
 1 file changed, 29 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/os_types.h 
b/drivers/gpu/drm/amd/display/dc/os_types.h
index 126c2f3a4dd3..47ef434f93d8 100644
--- a/drivers/gpu/drm/amd/display/dc/os_types.h
+++ b/drivers/gpu/drm/amd/display/dc/os_types.h
@@ -51,38 +51,9 @@
 #define dm_error(fmt, ...) DRM_ERROR(fmt, ##__VA_ARGS__)
 
 #if defined(CONFIG_DRM_AMD_DC_DCN)
-#if defined(CONFIG_X86)
 #include 
 #define DC_FP_START() kernel_fpu_begin()
 #define DC_FP_END() kernel_fpu_end()
-#elif defined(CONFIG_PPC64)
-#include 
-#include 
-#define DC_FP_START() { \
-   if (cpu_has_feature(CPU_FTR_VSX_COMP)) { \
-   preempt_disable(); \
-   enable_kernel_vsx(); \
-   } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) { \
-   preempt_disable(); \
-   enable_kernel_altivec(); \
-   } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) { \
-   preempt_disable(); \
-   enable_kernel_fp(); \
-   } \
-}
-#define DC_FP_END() { \
-   if (cpu_has_feature(CPU_FTR_VSX_COMP)) { \
-   disable_kernel_vsx(); \
-   preempt_enable(); \
-   } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) { \
-   disable_kernel_altivec(); \
-   preempt_enable(); \
-   } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) { \
-   disable_kernel_fp(); \
-   preempt_enable(); \
-   } \
-}
-#endif
 #endif
 
 /*
-- 
2.25.1

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[RFC v2 1/2] ppc/fpu: Add generic FPU api similar to x86

[Anson Jacob]

- Add kernel_fpu_begin & kernel_fpu_end API as x86
- Add logic similar to x86 to ensure fpu
  begin/end call correctness
- Add kernel_fpu_enabled to know if FPU is enabled

v2:
- Added asm/fpu/api.h powerpc variant with kernel_fpu_begin/end()
  and kernel_fpu_enabled() declarations
- Updated kernel_fpu_enabled as EXPORT_SYMBOL_GPL

Signed-off-by: Anson Jacob 
CC: Christoph Hellwig 
CC: Rodrigo Siqueira 
CC: Harry Wentland 
CC: Christian König 
---
 arch/powerpc/include/asm/fpu/api.h   |  18 
 arch/powerpc/include/asm/switch_to.h |  25 +-
 arch/powerpc/kernel/process.c| 130 +++
 3 files changed, 151 insertions(+), 22 deletions(-)
 create mode 100644 arch/powerpc/include/asm/fpu/api.h

diff --git a/arch/powerpc/include/asm/fpu/api.h 
b/arch/powerpc/include/asm/fpu/api.h
new file mode 100644
index ..57308cdc65c9
--- /dev/null
+++ b/arch/powerpc/include/asm/fpu/api.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef _ASM_POWERPC_FPU_API_H
+#define _ASM_POWERPC_FPU_API_H
+
+/*
+ * Use kernel_fpu_begin/end() if you intend to use FPU in kernel context. It
+ * disables preemption so be careful if you intend to use it for long periods
+ * of time.
+ * TODO: If you intend to use the FPU in irq/softirq you need to check first 
with
+ * irq_fpu_usable() if it is possible.
+ */
+
+extern bool kernel_fpu_enabled(void);
+extern void kernel_fpu_begin(void);
+extern void kernel_fpu_end(void);
+
+#endif /* _ASM_POWERPC_FPU_API_H */
diff --git a/arch/powerpc/include/asm/switch_to.h 
b/arch/powerpc/include/asm/switch_to.h
index 9d1fbd8be1c7..a9a919279f48 100644
--- a/arch/powerpc/include/asm/switch_to.h
+++ b/arch/powerpc/include/asm/switch_to.h
@@ -41,10 +41,7 @@ extern void enable_kernel_fp(void);
 extern void flush_fp_to_thread(struct task_struct *);
 extern void giveup_fpu(struct task_struct *);
 extern void save_fpu(struct task_struct *);
-static inline void disable_kernel_fp(void)
-{
-   msr_check_and_clear(MSR_FP);
-}
+extern void disable_kernel_fp(void);
 #else
 static inline void save_fpu(struct task_struct *t) { }
 static inline void flush_fp_to_thread(struct task_struct *t) { }
@@ -55,10 +52,7 @@ extern void enable_kernel_altivec(void);
 extern void flush_altivec_to_thread(struct task_struct *);
 extern void giveup_altivec(struct task_struct *);
 extern void save_altivec(struct task_struct *);
-static inline void disable_kernel_altivec(void)
-{
-   msr_check_and_clear(MSR_VEC);
-}
+extern void disable_kernel_altivec(void);
 #else
 static inline void save_altivec(struct task_struct *t) { }
 static inline void __giveup_altivec(struct task_struct *t) { }
@@ -67,20 +61,7 @@ static inline void __giveup_altivec(struct task_struct *t) { 
}
 #ifdef CONFIG_VSX
 extern void enable_kernel_vsx(void);
 extern void flush_vsx_to_thread(struct task_struct *);
-static inline void disable_kernel_vsx(void)
-{
-   msr_check_and_clear(MSR_FP|MSR_VEC|MSR_VSX);
-}
-#else
-static inline void enable_kernel_vsx(void)
-{
-   BUILD_BUG();
-}
-
-static inline void disable_kernel_vsx(void)
-{
-   BUILD_BUG();
-}
+extern void disable_kernel_vsx(void);
 #endif
 
 #ifdef CONFIG_SPE
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index 185beb290580..969096c0123c 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -75,6 +75,17 @@
 #define TM_DEBUG(x...) do { } while(0)
 #endif
 
+/*
+ * Track whether the kernel is using the FPU state
+ * currently.
+ *
+ * This flag is used:
+ *
+ *   - kernel_fpu_begin()/end() correctness
+ *   - kernel_fpu_enabled info
+ */
+static DEFINE_PER_CPU(bool, in_kernel_fpu);
+
 extern unsigned long _get_SP(void);
 
 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
@@ -212,6 +223,9 @@ void enable_kernel_fp(void)
unsigned long cpumsr;
 
WARN_ON(preemptible());
+   WARN_ON_ONCE(this_cpu_read(in_kernel_fpu));
+
+   this_cpu_write(in_kernel_fpu, true);
 
cpumsr = msr_check_and_set(MSR_FP);
 
@@ -231,6 +245,15 @@ void enable_kernel_fp(void)
}
 }
 EXPORT_SYMBOL(enable_kernel_fp);
+
+void disable_kernel_fp(void)
+{
+   WARN_ON_ONCE(!this_cpu_read(in_kernel_fpu));
+
+   this_cpu_write(in_kernel_fpu, false);
+   msr_check_and_clear(MSR_FP);
+}
+EXPORT_SYMBOL(disable_kernel_fp);
 #else
 static inline void __giveup_fpu(struct task_struct *tsk) { }
 #endif /* CONFIG_PPC_FPU */
@@ -263,6 +286,9 @@ void enable_kernel_altivec(void)
unsigned long cpumsr;
 
WARN_ON(preemptible());
+   WARN_ON_ONCE(this_cpu_read(in_kernel_fpu));
+
+   this_cpu_write(in_kernel_fpu, true);
 
cpumsr = msr_check_and_set(MSR_VEC);
 
@@ -283,6 +309,14 @@ void enable_kernel_altivec(void)
 }
 EXPORT_SYMBOL(enable_kernel_altivec);
 
+void disable_kernel_altivec(void)
+{
+   WARN_ON_ONCE(!this_cpu_read(in_kernel_fpu));
+
+   this_cpu_write(in_kernel_fpu, false);
+   msr_check_and_clear(MSR_VEC);
+}
+EXPORT_SYMBOL(disable_kernel_altivec);
 

[RFC v2 0/2] PPC: Add generic FPU api similar to x86

[Anson Jacob]

This is an attempt to have generic FPU enable/disable
calls similar to x86. 
So that we can simplify gpu/drm/amd/display/dc/os_types.h

Also adds FPU correctness logic seen in x86.

v2:
- Added asm/fpu/api.h powerpc variant with kernel_fpu_begin/end()
  and kernel_fpu_enabled() declarations
- Updated kernel_fpu_enabled as EXPORT_SYMBOL_GPL
- Got rid of macro switch for PPC in dc/os_types.h as header file
  with same name as x86 is added by previous patch in the series

Anson Jacob (2):
  ppc/fpu: Add generic FPU api similar to x86
  drm/amd/display: Use PPC FPU functions

 arch/powerpc/include/asm/fpu/api.h|  18 +++
 arch/powerpc/include/asm/switch_to.h  |  25 +
 arch/powerpc/kernel/process.c | 130 ++
 drivers/gpu/drm/amd/display/dc/os_types.h |  29 -
 4 files changed, 151 insertions(+), 51 deletions(-)
 create mode 100644 arch/powerpc/include/asm/fpu/api.h

-- 
2.25.1

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Re: [PATCH 1/7] vgaarb: remove VGA_DEFAULT_DEVICE

[Christian König]

Am 20.07.21 um 15:50 schrieb Daniel Vetter:

On Fri, Jul 16, 2021 at 09:14:02AM +0200, Christian König wrote:

Am 16.07.21 um 08:16 schrieb Christoph Hellwig:

The define is entirely unused.

Signed-off-by: Christoph Hellwig 

I'm not an expert for this particular code, but at least of hand everything
you do here makes totally sense.

Whole series is Acked-by: Christian König 

Care to also push this into drm-misc-next since you looked already?


Done.

Christian.


-Daniel


Regards,
Christian.


---
   include/linux/vgaarb.h | 6 --
   1 file changed, 6 deletions(-)

diff --git a/include/linux/vgaarb.h b/include/linux/vgaarb.h
index dc6ddce92066..26ec8a057d2a 100644
--- a/include/linux/vgaarb.h
+++ b/include/linux/vgaarb.h
@@ -42,12 +42,6 @@
   #define VGA_RSRC_NORMAL_IO 0x04
   #define VGA_RSRC_NORMAL_MEM0x08
-/* Passing that instead of a pci_dev to use the system "default"
- * device, that is the one used by vgacon. Archs will probably
- * have to provide their own vga_default_device();
- */
-#define VGA_DEFAULT_DEVICE (NULL)
-
   struct pci_dev;
   /* For use by clients */


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[PATCH v2 0/2] Fix regression on embedded panels caused by enabling ASSR

[Stylon Wang]

Previous ASSR-enabling patches cause blank screen on some embedded
panels. This patch set minimize the changes made to code logic prior to
the ASSR change and also improve on code readability.

Changes from prior rev1 to now:

v2:
 - Update reviewed-by and bug links 

Stylon Wang (2):
  drm/amd/display: Revert "Re-enable 'Guard ASSR with internal display
flag'"
  drm/amd/display: Fix ASSR regression on embedded panels

 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 58 +++
 1 file changed, 20 insertions(+), 38 deletions(-)

-- 
2.32.0

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[PATCH v2 1/2] drm/amd/display: Revert "Re-enable 'Guard ASSR with internal display flag'"

[Stylon Wang]

[Why]
A new change that simplifies the ASSR enabling and guarding is found
that also fixes regression on some embedded panels.

[How]
Revert the ASSR changes in preparation for upcoming patch.

Reviewed-by: Alex Deucher 
Signed-off-by: Stylon Wang 
---
 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 54 ++-
 1 file changed, 17 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 8b35cd9d4c01..cc62124b0b82 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -1752,38 +1752,6 @@ enum link_training_result 
dc_link_dp_perform_link_training(
return status;
 }
 
-static enum dp_panel_mode try_enable_assr(struct dc_stream_state *stream)
-{
-   struct dc_link *link = stream->link;
-   enum dp_panel_mode panel_mode = dp_get_panel_mode(link);
-#ifdef CONFIG_DRM_AMD_DC_HDCP
-   struct cp_psp *cp_psp = >ctx->cp_psp;
-#endif
-
-   /* ASSR must be supported on the panel */
-   if (panel_mode == DP_PANEL_MODE_DEFAULT)
-   return panel_mode;
-
-   /* eDP or internal DP only */
-   if (link->connector_signal != SIGNAL_TYPE_EDP &&
-   !(link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
-link->is_internal_display))
-   return DP_PANEL_MODE_DEFAULT;
-
-#ifdef CONFIG_DRM_AMD_DC_HDCP
-   if (cp_psp && cp_psp->funcs.enable_assr) {
-   if (!cp_psp->funcs.enable_assr(cp_psp->handle, link)) {
-   /* since eDP implies ASSR on, change panel
-* mode to disable ASSR
-*/
-   panel_mode = DP_PANEL_MODE_DEFAULT;
-   }
-   } else
-   panel_mode = DP_PANEL_MODE_DEFAULT;
-#endif
-   return panel_mode;
-}
-
 bool perform_link_training_with_retries(
const struct dc_link_settings *link_setting,
bool skip_video_pattern,
@@ -1796,7 +1764,7 @@ bool perform_link_training_with_retries(
uint8_t delay_between_attempts = LINK_TRAINING_RETRY_DELAY;
struct dc_stream_state *stream = pipe_ctx->stream;
struct dc_link *link = stream->link;
-   enum dp_panel_mode panel_mode;
+   enum dp_panel_mode panel_mode = dp_get_panel_mode(link);
struct link_encoder *link_enc;
enum link_training_result status = LINK_TRAINING_CR_FAIL_LANE0;
struct dc_link_settings current_setting = *link_setting;
@@ -1832,11 +1800,23 @@ bool perform_link_training_with_retries(
msleep(delay_dp_power_up_in_ms);
}
 
-   panel_mode = try_enable_assr(stream);
+#ifdef CONFIG_DRM_AMD_DC_HDCP
+   if (panel_mode == DP_PANEL_MODE_EDP) {
+   struct cp_psp *cp_psp = >ctx->cp_psp;
+
+   if (cp_psp && cp_psp->funcs.enable_assr) {
+   if (!cp_psp->funcs.enable_assr(cp_psp->handle, 
link)) {
+   /* since eDP implies ASSR on, change 
panel
+* mode to disable ASSR
+*/
+   panel_mode = DP_PANEL_MODE_DEFAULT;
+   }
+   } else
+   panel_mode = DP_PANEL_MODE_DEFAULT;
+   }
+#endif
+
dp_set_panel_mode(link, panel_mode);
-   DC_LOG_DETECTION_DP_CAPS("Link: %d ASSR enabled: %d\n",
-link->link_index,
-panel_mode != DP_PANEL_MODE_DEFAULT);
 
if (link->aux_access_disabled) {
dc_link_dp_perform_link_training_skip_aux(link, 
_setting);
-- 
2.32.0

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[PATCH v2 2/2] drm/amd/display: Fix ASSR regression on embedded panels

[Stylon Wang]

[Why]
Regression found in some embedded panels traces back to the earliest
upstreamed ASSR patch. The changed code flow are causing problems
with some panels.

[How]
- Change ASSR enabling code while preserving original code flow
  as much as possible
- Simplify the code on guarding with internal display flag

Bug: https://bugzilla.kernel.org/show_bug.cgi?id=213779
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1620
Reviewed-by: Alex Deucher 
Signed-off-by: Stylon Wang 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 8 +---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index cc62124b0b82..f56e061d35bc 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -1811,8 +1811,7 @@ bool perform_link_training_with_retries(
 */
panel_mode = DP_PANEL_MODE_DEFAULT;
}
-   } else
-   panel_mode = DP_PANEL_MODE_DEFAULT;
+   }
}
 #endif
 
@@ -4643,7 +4642,10 @@ enum dp_panel_mode dp_get_panel_mode(struct dc_link 
*link)
}
}
 
-   if (link->dpcd_caps.panel_mode_edp) {
+   if (link->dpcd_caps.panel_mode_edp &&
+   (link->connector_signal == SIGNAL_TYPE_EDP ||
+(link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
+ link->is_internal_display))) {
return DP_PANEL_MODE_EDP;
}
 
-- 
2.32.0

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RE: [PATCH] drm/amd/amdgpu: consider paging job always not guilty

[Chen, JingWen]

[AMD Official Use Only]

Hi Christian,

I have uploaded the latest patch according to your suggestion.

Best Regards,
JingWen Chen

-Original Message-
From: Christian König 
Sent: Tuesday, July 20, 2021 8:13 PM
To: Chen, JingWen ; amd-gfx@lists.freedesktop.org
Cc: Chen, Horace ; Liu, Monk 
Subject: Re: [PATCH] drm/amd/amdgpu: consider paging job always not guilty



Am 20.07.21 um 13:02 schrieb Jingwen Chen:
> [Why]
> Currently all timedout job will be considered to be guilty. In SRIOV
> multi-vf use case, the vf flr happens first and then job time out is
> found. There can be several jobs timeout during a very small time slice.
> And if the innocent sdma job time out is found before the real bad
> job, then the innocent sdma job will be set to guilty. This will lead
> to a page fault after resubmitting job.
>
> [How]
> If the job is a paging job, we will always consider it not guilty

Don't say "paging job", better "kernel job". Since the PTE updates we are using 
here are not even remotely related to paging.

Regards,
Christian.

>
> Signed-off-by: Jingwen Chen 
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 +++---
>   1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 37fa199be8b3..40461547701a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -4410,7 +4410,7 @@ int amdgpu_device_pre_asic_reset(struct amdgpu_device 
> *adev,
>   amdgpu_fence_driver_force_completion(ring);
>   }
>
> - if(job)
> + if (job && job->vm)
>   drm_sched_increase_karma(>base);
>
>   r = amdgpu_reset_prepare_hwcontext(adev, reset_context); @@ -4874,7
> +4874,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
>   DRM_INFO("Bailing on TDR for s_job:%llx, hive: %llx as 
> another already in progress",
>   job ? job->base.id : -1, hive->hive_id);
>   amdgpu_put_xgmi_hive(hive);
> - if (job)
> + if (job && job->vm)
>   drm_sched_increase_karma(>base);
>   return 0;
>   }
> @@ -4898,7 +4898,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device 
> *adev,
>   job ? job->base.id : -1);
>
>   /* even we skipped this reset, still need to set the job to 
> guilty */
> - if (job)
> + if (job && job->vm)
>   drm_sched_increase_karma(>base);
>   goto skip_recovery;
>   }

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RE: [PATCH 1/2] drm/amd/pm: Add information about SMU11 firmware version

[Liang, Prike]

[Public]

> -Original Message-
> From: Limonciello, Mario 
> Sent: Wednesday, July 21, 2021 11:15 AM
> To: Liang, Prike ; amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH 1/2] drm/amd/pm: Add information about SMU11
> firmware version
>
> On 7/20/2021 22:07, Liang, Prike wrote:
> > [Public]
> >
> > In the SMU issue troubleshooting process we also can check the SMU
> > version by reading MP1 scratch register and  from long term we may
> > need put the SMC version collection in the debug sysfs
> > amdgpu_firmware_info
> >
> > In this patch fashion, we better use dev_dbg instead of dev_info for only
> debug purpose.
>
> Actually SMUv13 files have it at info level, which is why it was modeled this
> way.  Perhaps v13 should also decrease this to debug then.
>
[Prike] OK, that seems not great deal for setting print level here. Besides, 
now base on you patch we may also need clean up the SMU version in the header 
mismatch print info and just throw out the warning message like as following.

if (if_version != smu->smc_driver_if_version) {
dev_warn(smu->adev->dev, "SMU driver if version not matched\n");
}

> >
> >> -Original Message-
> >> From: amd-gfx  On Behalf Of
> >> Mario Limonciello
> >> Sent: Wednesday, July 21, 2021 12:18 AM
> >> To: amd-gfx@lists.freedesktop.org
> >> Cc: Limonciello, Mario 
> >> Subject: [PATCH 1/2] drm/amd/pm: Add information about SMU11
> firmware
> >> version
> >>
> >> This information is useful for root causing issues with S0ix.
> >>
> >> Signed-off-by: Mario Limonciello 
> >> ---
> >>   drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 3 +++
> >>   1 file changed, 3 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
> >> b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
> >> index 0a5d46ac9ccd..626d7c2bdf66 100644
> >> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
> >> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
> >> @@ -272,6 +272,9 @@ int smu_v11_0_check_fw_version(struct
> smu_context
> >> *smu)
> >>break;
> >>}
> >>
> >> + dev_info(smu->adev->dev, "smu fw reported version = 0x%08x
> >> (%d.%d.%d)\n",
> >> +  smu_version, smu_major, smu_minor, smu_debug);
> >> +
> >>/*
> >> * 1. if_version mismatch is not critical as our fw is designed
> >> * to be backward compatible.
> >> --
> >> 2.25.1
> >>
> >> ___
> >> amd-gfx mailing list
> >> amd-gfx@lists.freedesktop.org
> >> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flis
> >> ts.f
> >> reedesktop.org%2Fmailman%2Flistinfo%2Famd-
> >>
> gfxdata=04%7C01%7CPrike.Liang%40amd.com%7C62180964b7d24208
> >>
> b59908d94b99f971%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C
> >>
> 637623947521949203%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwM
> >>
> DAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C2000sdat
> >>
> a=ACcymqjRA5e1wmQmBCPW5cwsM1tF5QXOXQRukuAgkeg%3Dreser
> >> ved=0

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Re: [RFC v2 2/2] drm/amd/display: Use PPC FPU functions

[Christoph Hellwig]

On Wed, Jul 21, 2021 at 08:29:43AM +0200, Christian K??nig wrote:
> Looks good in general, but question is what about other architectures like
> ARM?

DRM_AMD_DC_DCN currently requires X86 || PPC64.

Maybe a good think would be to add a new KERNEL_FPU_API Kconfig symbol,
selected by x86 and powerpc (I think ppc32 should be fine too now) so
that we get these arch dependencies out of the driver.
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Re: [RFC v2 1/2] ppc/fpu: Add generic FPU api similar to x86

[Christoph Hellwig]

> +
> +/*
> + * Use kernel_fpu_begin/end() if you intend to use FPU in kernel context. It
> + * disables preemption so be careful if you intend to use it for long periods
> + * of time.
> + * TODO: If you intend to use the FPU in irq/softirq you need to check first 
> with
> + * irq_fpu_usable() if it is possible.

Please avoid the overly lone lines comments.

> +extern bool kernel_fpu_enabled(void);
> +extern void kernel_fpu_begin(void);
> +extern void kernel_fpu_end(void);

No need for the externs.

> +/*
> + * Track whether the kernel is using the FPU state
> + * currently.

This all fits on a single line.

> +static bool fpu_support(void)
> +{
> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
> + return true;
> + } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
> + return true;
> + } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
> + return true;
> + }

No need for the braces, or else after a return.  In fact this could
be simplified down to:

return cpu_has_feature(CPU_FTR_VSX_COMP) ||
cpu_has_feature(CPU_FTR_ALTIVEC_COMP) ||
cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE));

> + preempt_disable();
> +
> +#ifdef CONFIG_VSX
> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
> + enable_kernel_vsx();
> + return;
> + }
> +#endif
> +
> +#ifdef CONFIG_ALTIVEC
> + if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
> + enable_kernel_altivec();
> + return;
> + }
> +#endif
> +
> +#ifdef CONFIG_PPC_FPU
> + if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
> + enable_kernel_fp();
> + return;
> + }
> +#endif

All the features are defined away if not supported (and we already rely
on that in fpu_support()).  So this could become:

if (cpu_has_feature(CPU_FTR_VSX_COMP))
enable_kernel_vsx();
else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP))
enable_kernel_altivec();
else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE))
enable_kernel_fp();

Same for the disable path.
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[PATCH] drm/amdgpu/gfx10: fix mixed declaration and code warning

[Alex Deucher]

Move the declaration up to the top of the function.

Fixes: 631d55e089eaa8 ("drm/amdgpu: Add error message when programing registers 
fails")
Cc: Roy Sun 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index ca06fb137cac..d102cfd36ba2 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -1493,6 +1493,7 @@ static u32 gfx_v10_rlcg_rw(struct amdgpu_device *adev, 
u32 offset, u32 v, uint32
uint32_t i = 0;
uint32_t retries = 5;
u32 ret = 0;
+   u32 tmp;
 
scratch_reg0 = adev->rmmio +
   (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + 
mmSCRATCH_REG0) * 4;
@@ -1526,7 +1527,6 @@ static u32 gfx_v10_rlcg_rw(struct amdgpu_device *adev, 
u32 offset, u32 v, uint32
writel(v, scratch_reg0);
writel(offset | flag, scratch_reg1);
writel(1, spare_int);
-   u32 tmp;
 
for (i = 0; i < retries; i++) {
tmp = readl(scratch_reg1);
-- 
2.31.1

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Re: [PATCH 1/2] drm/amd/pm: Add information about SMU11 firmware version

[Limonciello, Mario]

On 7/20/2021 22:07, Liang, Prike wrote:

[Public]

In the SMU issue troubleshooting process we also can check the SMU version by 
reading MP1 scratch register and  from long term we may need put the SMC 
version collection in the debug sysfs amdgpu_firmware_info

In this patch fashion, we better use dev_dbg instead of dev_info for only debug 
purpose.


Actually SMUv13 files have it at info level, which is why it was modeled 
this way.  Perhaps v13 should also decrease this to debug then.





-Original Message-
From: amd-gfx  On Behalf Of
Mario Limonciello
Sent: Wednesday, July 21, 2021 12:18 AM
To: amd-gfx@lists.freedesktop.org
Cc: Limonciello, Mario 
Subject: [PATCH 1/2] drm/amd/pm: Add information about SMU11 firmware
version

This information is useful for root causing issues with S0ix.

Signed-off-by: Mario Limonciello 
---
  drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 3 +++
  1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
index 0a5d46ac9ccd..626d7c2bdf66 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
@@ -272,6 +272,9 @@ int smu_v11_0_check_fw_version(struct
smu_context *smu)
   break;
   }

+ dev_info(smu->adev->dev, "smu fw reported version = 0x%08x
(%d.%d.%d)\n",
+  smu_version, smu_major, smu_minor, smu_debug);
+
   /*
* 1. if_version mismatch is not critical as our fw is designed
* to be backward compatible.
--
2.25.1

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[PATCH 1/2] drm/amd/amdgpu embed hw_fence into amdgpu_job

[Jingwen Chen]

From: Jack Zhang 

Why: Previously hw fence is alloced separately with job.
It caused historical lifetime issues and corner cases.
The ideal situation is to take fence to manage both job
and fence's lifetime, and simplify the design of gpu-scheduler.

How:
We propose to embed hw_fence into amdgpu_job.
1. We cover the normal job submission by this method.
2. For ib_test, and submit without a parent job keep the
legacy way to create a hw fence separately.

Signed-off-by: Jingwen Chen 
Signed-off-by: Jack Zhang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c  |  1 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c   | 62 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c  |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 35 
 drivers/gpu/drm/amd/amdgpu/amdgpu_job.h |  4 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h|  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c  |  2 +-
 8 files changed, 80 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index b6d33f13b476..bad403978bac 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -714,7 +714,6 @@ int amdgpu_amdkfd_submit_ib(struct kgd_dev *kgd, enum 
kgd_engine_type engine,
ret = dma_fence_wait(f, false);
 
 err_ib_sched:
-   dma_fence_put(f);
amdgpu_job_free(job);
 err:
return ret;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index 536005bff24a..277128846dd1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -1414,7 +1414,7 @@ static void amdgpu_ib_preempt_mark_partial_job(struct 
amdgpu_ring *ring)
continue;
}
job = to_amdgpu_job(s_job);
-   if (preempted && job->fence == fence)
+   if (preempted && (>hw_fence) == fence)
/* mark the job as preempted */
job->preemption_status |= AMDGPU_IB_PREEMPTED;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
index 30772608eac6..eecf21d8ec33 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
@@ -133,25 +133,40 @@ static u32 amdgpu_fence_read(struct amdgpu_ring *ring)
  * Emits a fence command on the requested ring (all asics).
  * Returns 0 on success, -ENOMEM on failure.
  */
-int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **f,
+int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **f, struct 
amdgpu_job *job,
  unsigned flags)
 {
struct amdgpu_device *adev = ring->adev;
-   struct amdgpu_fence *fence;
+   struct dma_fence *fence;
+   struct amdgpu_fence *am_fence;
struct dma_fence __rcu **ptr;
uint32_t seq;
int r;
 
-   fence = kmem_cache_alloc(amdgpu_fence_slab, GFP_KERNEL);
-   if (fence == NULL)
-   return -ENOMEM;
+   if (job == NULL) {
+   /* create a sperate hw fence */
+   am_fence = kmem_cache_alloc(amdgpu_fence_slab, GFP_KERNEL);
+   if (am_fence == NULL)
+   return -ENOMEM;
+   fence = _fence->base;
+   am_fence->ring = ring;
+   } else {
+   /* take use of job-embedded fence */
+   fence = >hw_fence;
+   job->ring = ring;
+   }
 
seq = ++ring->fence_drv.sync_seq;
-   fence->ring = ring;
-   dma_fence_init(>base, _fence_ops,
+   dma_fence_init(fence, _fence_ops,
   >fence_drv.lock,
   adev->fence_context + ring->idx,
   seq);
+
+   if (job != NULL) {
+   /* mark this fence has a parent job */
+   set_bit(DMA_FENCE_FLAG_USER_BITS, >flags);
+   }
+
amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
   seq, flags | AMDGPU_FENCE_FLAG_INT);
pm_runtime_get_noresume(adev_to_drm(adev)->dev);
@@ -174,9 +189,9 @@ int amdgpu_fence_emit(struct amdgpu_ring *ring, struct 
dma_fence **f,
/* This function can't be called concurrently anyway, otherwise
 * emitting the fence would mess up the hardware ring buffer.
 */
-   rcu_assign_pointer(*ptr, dma_fence_get(>base));
+   rcu_assign_pointer(*ptr, dma_fence_get(fence));
 
-   *f = >base;
+   *f = fence;
 
return 0;
 }
@@ -636,8 +651,16 @@ static const char *amdgpu_fence_get_driver_name(struct 
dma_fence *fence)
 
 static const char *amdgpu_fence_get_timeline_name(struct dma_fence *f)
 {
-   struct amdgpu_fence *fence = to_amdgpu_fence(f);
-   return (const char *)fence->ring->name;
+   struct amdgpu_ring *ring;
+
+   

[PATCH 2/2] drm: add tdr support for embeded hw_fence

[Jingwen Chen]

[Why]
After embeded hw_fence to amdgpu_job, we need to add tdr support
for this feature.

[How]
1. Add a resubmit_flag for resubmit jobs.
2. Clear job fence from RCU and force complete vm flush fences in
   pre_asic_reset
3. skip dma_fence_get for resubmit jobs and add a dma_fence_put
   for guilty jobs.

Signed-off-by: Jack Zhang 
Signed-off-by: Jingwen Chen 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 12 +++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c  | 16 +++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_job.c|  4 +++-
 drivers/gpu/drm/scheduler/sched_main.c |  1 +
 include/drm/gpu_scheduler.h|  1 +
 5 files changed, 27 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 40461547701a..fe0237f72a09 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -4382,7 +4382,7 @@ int amdgpu_device_mode1_reset(struct amdgpu_device *adev)
 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
 struct amdgpu_reset_context *reset_context)
 {
-   int i, r = 0;
+   int i, j, r = 0;
struct amdgpu_job *job = NULL;
bool need_full_reset =
test_bit(AMDGPU_NEED_FULL_RESET, _context->flags);
@@ -4406,6 +4406,16 @@ int amdgpu_device_pre_asic_reset(struct amdgpu_device 
*adev,
if (!ring || !ring->sched.thread)
continue;
 
+   /*clear job fence from fence drv to avoid force_completion
+*leave NULL and vm flush fence in fence drv */
+   for (j = 0; j <= ring->fence_drv.num_fences_mask; j ++) {
+   struct dma_fence *old,**ptr;
+   ptr = >fence_drv.fences[j];
+   old = rcu_dereference_protected(*ptr, 1);
+   if (old && test_bit(DMA_FENCE_FLAG_USER_BITS, 
>flags))) {
+   RCU_INIT_POINTER(*ptr, NULL);
+   }
+   }
/* after all hw jobs are reset, hw fence is meaningless, so 
force_completion */
amdgpu_fence_driver_force_completion(ring);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
index eecf21d8ec33..815776c9a013 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
@@ -156,11 +156,17 @@ int amdgpu_fence_emit(struct amdgpu_ring *ring, struct 
dma_fence **f, struct amd
job->ring = ring;
}
 
-   seq = ++ring->fence_drv.sync_seq;
-   dma_fence_init(fence, _fence_ops,
-  >fence_drv.lock,
-  adev->fence_context + ring->idx,
-  seq);
+   if (job != NULL && job->base.resubmit_flag == 1) {
+   /* reinit seq for resubmitted jobs */
+   seq = ++ring->fence_drv.sync_seq;
+   fence->seqno = seq;
+   } else {
+   seq = ++ring->fence_drv.sync_seq;
+   dma_fence_init(fence, _fence_ops,
+   >fence_drv.lock,
+   adev->fence_context + ring->idx,
+   seq);
+   }
 
if (job != NULL) {
/* mark this fence has a parent job */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
index 7c426e225b24..d6f848adc3f4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
@@ -241,6 +241,7 @@ static struct dma_fence *amdgpu_job_run(struct 
drm_sched_job *sched_job)
dma_fence_set_error(finished, -ECANCELED);/* skip IB as well if 
VRAM lost */
 
if (finished->error < 0) {
+   dma_fence_put(>hw_fence);
DRM_INFO("Skip scheduling IBs!\n");
} else {
r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs, job,
@@ -249,7 +250,8 @@ static struct dma_fence *amdgpu_job_run(struct 
drm_sched_job *sched_job)
DRM_ERROR("Error scheduling IBs (%d)\n", r);
}
 
-   dma_fence_get(fence);
+   if (!job->base.resubmit_flag)
+   dma_fence_get(fence);
amdgpu_job_free_resources(job);
 
fence = r ? ERR_PTR(r) : fence;
diff --git a/drivers/gpu/drm/scheduler/sched_main.c 
b/drivers/gpu/drm/scheduler/sched_main.c
index f4f474944169..5a36ab5aea2d 100644
--- a/drivers/gpu/drm/scheduler/sched_main.c
+++ b/drivers/gpu/drm/scheduler/sched_main.c
@@ -544,6 +544,7 @@ void drm_sched_resubmit_jobs_ext(struct drm_gpu_scheduler 
*sched, int max)
dma_fence_set_error(_fence->finished, -ECANCELED);
 
dma_fence_put(s_job->s_fence->parent);
+   s_job->resubmit_flag = 1;
fence = sched->ops->run_job(s_job);
i++;
 
diff --git 

RE: [PATCH 1/2] drm/amd/pm: Add information about SMU11 firmware version

[Liang, Prike]

[Public]

In the SMU issue troubleshooting process we also can check the SMU version by 
reading MP1 scratch register and  from long term we may need put the SMC 
version collection in the debug sysfs amdgpu_firmware_info.

In this patch fashion, we better use dev_dbg instead of dev_info for only debug 
purpose.

> -Original Message-
> From: amd-gfx  On Behalf Of
> Mario Limonciello
> Sent: Wednesday, July 21, 2021 12:18 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Limonciello, Mario 
> Subject: [PATCH 1/2] drm/amd/pm: Add information about SMU11 firmware
> version
>
> This information is useful for root causing issues with S0ix.
>
> Signed-off-by: Mario Limonciello 
> ---
>  drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
> index 0a5d46ac9ccd..626d7c2bdf66 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
> @@ -272,6 +272,9 @@ int smu_v11_0_check_fw_version(struct
> smu_context *smu)
>   break;
>   }
>
> + dev_info(smu->adev->dev, "smu fw reported version = 0x%08x
> (%d.%d.%d)\n",
> +  smu_version, smu_major, smu_minor, smu_debug);
> +
>   /*
>* 1. if_version mismatch is not critical as our fw is designed
>* to be backward compatible.
> --
> 2.25.1
>
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> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.f
> reedesktop.org%2Fmailman%2Flistinfo%2Famd-
> gfxdata=04%7C01%7CPrike.Liang%40amd.com%7C62180964b7d24208
> b59908d94b99f971%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C
> 637623947521949203%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwM
> DAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C2000sdat
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[PATCH] drm/amdgpu: Clear doorbell interrupt status for Sienna Cichlid

[Chengzhe Liu]

On Sienna Cichlid, in pass-through mode, if we unload the driver in BACO
mode(RTPM), then the kernel would receive thousands of interrupts.
That's because there is doorbell monitor interrupt on BIF, so KVM keeps
injecting interrupts to the guest VM. So we should clear the doorbell
interrupt status after BACO exit.

v2: Modify coding style and commit message

Signed-off-by: Chengzhe Liu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  4 
 drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h   |  1 +
 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c | 21 +
 3 files changed, 26 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 37fa199be8b3..92f73d2bbfc9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -5265,6 +5265,10 @@ int amdgpu_device_baco_exit(struct drm_device *dev)
adev->nbio.funcs->enable_doorbell_interrupt)
adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
 
+   if (amdgpu_passthrough(adev) &&
+   adev->nbio.funcs->clear_doorbell_interrupt)
+   adev->nbio.funcs->clear_doorbell_interrupt(adev);
+
return 0;
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
index 45295dce5c3e..843052205bd5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
@@ -95,6 +95,7 @@ struct amdgpu_nbio_funcs {
void (*program_aspm)(struct amdgpu_device *adev);
void (*apply_lc_spc_mode_wa)(struct amdgpu_device *adev);
void (*apply_l1_link_width_reconfig_wa)(struct amdgpu_device *adev);
+   void (*clear_doorbell_interrupt)(struct amdgpu_device *adev);
 };
 
 struct amdgpu_nbio {
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c 
b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
index 7b79eeaa88aa..b184b656b9b6 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
@@ -508,6 +508,26 @@ static void 
nbio_v2_3_apply_l1_link_width_reconfig_wa(struct amdgpu_device *adev
WREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL, reg_data);
 }
 
+static void nbio_v2_3_clear_doorbell_interrupt(struct amdgpu_device *adev)
+{
+   uint32_t reg, reg_data;
+
+   if (adev->asic_type != CHIP_SIENNA_CICHLID)
+   return;
+
+   reg = RREG32_SOC15(NBIO, 0, mmBIF_RB_CNTL);
+
+   /* Clear Interrupt Status
+*/
+   if ((reg & BIF_RB_CNTL__RB_ENABLE_MASK) == 0) {
+   reg = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL);
+   if (reg & 
BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS_MASK) {
+   reg_data = 1 << 
BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT;
+   WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, 
reg_data);
+   }
+   }
+}
+
 const struct amdgpu_nbio_funcs nbio_v2_3_funcs = {
.get_hdp_flush_req_offset = nbio_v2_3_get_hdp_flush_req_offset,
.get_hdp_flush_done_offset = nbio_v2_3_get_hdp_flush_done_offset,
@@ -531,4 +551,5 @@ const struct amdgpu_nbio_funcs nbio_v2_3_funcs = {
.program_aspm =  nbio_v2_3_program_aspm,
.apply_lc_spc_mode_wa = nbio_v2_3_apply_lc_spc_mode_wa,
.apply_l1_link_width_reconfig_wa = 
nbio_v2_3_apply_l1_link_width_reconfig_wa,
+   .clear_doorbell_interrupt = nbio_v2_3_clear_doorbell_interrupt,
 };
-- 
2.25.1

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Re: [PATCH] drm/amdgpu/gfx10: fix mixed declaration and code warning

[Christian König]

Am 21.07.21 um 05:14 schrieb Alex Deucher:

Move the declaration up to the top of the function.

Fixes: 631d55e089eaa8 ("drm/amdgpu: Add error message when programing registers 
fails")
Cc: Roy Sun 
Signed-off-by: Alex Deucher 


Acked-by: Christian König 


---
  drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index ca06fb137cac..d102cfd36ba2 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -1493,6 +1493,7 @@ static u32 gfx_v10_rlcg_rw(struct amdgpu_device *adev, 
u32 offset, u32 v, uint32
uint32_t i = 0;
uint32_t retries = 5;
u32 ret = 0;
+   u32 tmp;
  
  	scratch_reg0 = adev->rmmio +

   (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + 
mmSCRATCH_REG0) * 4;
@@ -1526,7 +1527,6 @@ static u32 gfx_v10_rlcg_rw(struct amdgpu_device *adev, 
u32 offset, u32 v, uint32
writel(v, scratch_reg0);
writel(offset | flag, scratch_reg1);
writel(1, spare_int);
-   u32 tmp;
  
  		for (i = 0; i < retries; i++) {

tmp = readl(scratch_reg1);


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Re: [PATCH v2] drm/amd/amdgpu: consider kernel job always not guilty

[Christian König]

Am 21.07.21 um 04:05 schrieb Jingwen Chen:

[Why]
Currently all timedout job will be considered to be guilty. In SRIOV
multi-vf use case, the vf flr happens first and then job time out is
found. There can be several jobs timeout during a very small time slice.
And if the innocent sdma job time out is found before the real bad
job, then the innocent sdma job will be set to guilty. This will lead
to a page fault after resubmitting job.

[How]
If the job is a kernel job, we will always consider it not guilty

Signed-off-by: Jingwen Chen 


Reviewed-by: Christian König 


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 +++---
  1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 37fa199be8b3..40461547701a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -4410,7 +4410,7 @@ int amdgpu_device_pre_asic_reset(struct amdgpu_device 
*adev,
amdgpu_fence_driver_force_completion(ring);
}
  
-	if(job)

+   if (job && job->vm)
drm_sched_increase_karma(>base);
  
  	r = amdgpu_reset_prepare_hwcontext(adev, reset_context);

@@ -4874,7 +4874,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
DRM_INFO("Bailing on TDR for s_job:%llx, hive: %llx as 
another already in progress",
job ? job->base.id : -1, hive->hive_id);
amdgpu_put_xgmi_hive(hive);
-   if (job)
+   if (job && job->vm)
drm_sched_increase_karma(>base);
return 0;
}
@@ -4898,7 +4898,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
job ? job->base.id : -1);
  
  		/* even we skipped this reset, still need to set the job to guilty */

-   if (job)
+   if (job && job->vm)
drm_sched_increase_karma(>base);
goto skip_recovery;
}


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[PATCH v2] drm/amd/amdgpu: consider kernel job always not guilty

[Jingwen Chen]

[Why]
Currently all timedout job will be considered to be guilty. In SRIOV
multi-vf use case, the vf flr happens first and then job time out is
found. There can be several jobs timeout during a very small time slice.
And if the innocent sdma job time out is found before the real bad
job, then the innocent sdma job will be set to guilty. This will lead
to a page fault after resubmitting job.

[How]
If the job is a kernel job, we will always consider it not guilty

Signed-off-by: Jingwen Chen 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 37fa199be8b3..40461547701a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -4410,7 +4410,7 @@ int amdgpu_device_pre_asic_reset(struct amdgpu_device 
*adev,
amdgpu_fence_driver_force_completion(ring);
}
 
-   if(job)
+   if (job && job->vm)
drm_sched_increase_karma(>base);
 
r = amdgpu_reset_prepare_hwcontext(adev, reset_context);
@@ -4874,7 +4874,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
DRM_INFO("Bailing on TDR for s_job:%llx, hive: %llx as 
another already in progress",
job ? job->base.id : -1, hive->hive_id);
amdgpu_put_xgmi_hive(hive);
-   if (job)
+   if (job && job->vm)
drm_sched_increase_karma(>base);
return 0;
}
@@ -4898,7 +4898,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
job ? job->base.id : -1);
 
/* even we skipped this reset, still need to set the job to 
guilty */
-   if (job)
+   if (job && job->vm)
drm_sched_increase_karma(>base);
goto skip_recovery;
}
-- 
2.25.1

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