[PATCH 12/14] drm/amd/display: ensure dentist display clock update finished in DCN20
From: Dale Zhao [Why] We don't check DENTIST_DISPCLK_CHG_DONE to ensure dentist display clockis updated to target value. In some scenarios with large display clock margin, it will deliver unfinished display clock and cause issues like display black screen. [How] Checking DENTIST_DISPCLK_CHG_DONE to ensure display clock has been update to target value before driver do other clock related actions. Reviewed-by: Cyr Aric Acked-by: Solomon Chiu Signed-off-by: Dale Zhao --- drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c index eee406d11b1e..0d01aa9f15a6 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c @@ -197,7 +197,7 @@ void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr, struct REG_UPDATE(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, dispclk_wdivider); -// REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 5, 100); + REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 50, 1000); REG_UPDATE(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_WDIVIDER, dppclk_wdivider); REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_CHG_DONE, 1, 5, 100); -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 13/14] drm/amd/display: [FW Promotion] Release 0.0.76
From: Anthony Koo Reviewed-by: Cyr Aric Acked-by: Solomon Chiu Signed-off-by: Anthony Koo --- drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index 8b0b4d86986c..02921ad22310 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -47,10 +47,10 @@ /* Firmware versioning. */ #ifdef DMUB_EXPOSE_VERSION -#define DMUB_FW_VERSION_GIT_HASH 0x2d2f6f51e +#define DMUB_FW_VERSION_GIT_HASH 0xe599e0896 #define DMUB_FW_VERSION_MAJOR 0 #define DMUB_FW_VERSION_MINOR 0 -#define DMUB_FW_VERSION_REVISION 75 +#define DMUB_FW_VERSION_REVISION 76 #define DMUB_FW_VERSION_TEST 0 #define DMUB_FW_VERSION_VBIOS 0 #define DMUB_FW_VERSION_HOTFIX 0 -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 11/14] drm/amd/display: refactor riommu invalidation wa
From: Eric Yang
[Why]
A cleaner solution, only done once on boot.
[How]
Remove previous workaround and configure an extra
vmid one time on boot
Reviewed-by: Kazlauskas Nicholas
Acked-by: Solomon Chiu
Signed-off-by: Eric Yang
---
.../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 6 ---
.../drm/amd/display/dc/dcn31/dcn31_hubbub.c | 48 +++
.../drm/amd/display/dc/dcn31/dcn31_hwseq.c| 17 ---
.../gpu/drm/amd/display/dc/dcn31/dcn31_init.c | 2 +-
.../drm/amd/display/dc/dcn31/dcn31_resource.c | 1 -
.../gpu/drm/amd/display/dc/inc/hw/dchubbub.h | 3 --
.../amd/display/dc/inc/hw_sequencer_private.h | 1 -
7 files changed, 28 insertions(+), 50 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index ef185b93b31d..5c2853654cca 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -570,12 +570,6 @@ void dcn20_plane_atomic_disable(struct dc *dc, struct
pipe_ctx *pipe_ctx)
struct hubp *hubp = pipe_ctx->plane_res.hubp;
struct dpp *dpp = pipe_ctx->plane_res.dpp;
- if (hws->wa.early_riommu_invalidation) {
- struct hubbub *hubbub = dc->res_pool->hubbub;
-
- hubbub->funcs->apply_invalidation_req_wa(hubbub,
>vmid_cache);
- }
-
dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);
/* In flip immediate with pipe splitting case GSL is used for
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.c
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.c
index ef233cb49b31..90c73a1cb986 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.c
@@ -876,11 +876,35 @@ static bool hubbub31_get_dcc_compression_cap(struct
hubbub *hubbub,
static int hubbub31_init_dchub_sys_ctx(struct hubbub *hubbub,
struct dcn_hubbub_phys_addr_config *pa_config)
{
- hubbub3_init_dchub_sys_ctx(hubbub, pa_config);
+ struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
+ struct dcn_vmid_page_table_config phys_config;
- dcn21_dchvm_init(hubbub);
+ REG_SET(DCN_VM_FB_LOCATION_BASE, 0,
+ FB_BASE, pa_config->system_aperture.fb_base >> 24);
+ REG_SET(DCN_VM_FB_LOCATION_TOP, 0,
+ FB_TOP, pa_config->system_aperture.fb_top >> 24);
+ REG_SET(DCN_VM_FB_OFFSET, 0,
+ FB_OFFSET, pa_config->system_aperture.fb_offset >> 24);
+ REG_SET(DCN_VM_AGP_BOT, 0,
+ AGP_BOT, pa_config->system_aperture.agp_bot >> 24);
+ REG_SET(DCN_VM_AGP_TOP, 0,
+ AGP_TOP, pa_config->system_aperture.agp_top >> 24);
+ REG_SET(DCN_VM_AGP_BASE, 0,
+ AGP_BASE, pa_config->system_aperture.agp_base >> 24);
- hubbub->vmid_cache = *pa_config;
+ if (pa_config->gart_config.page_table_start_addr !=
pa_config->gart_config.page_table_end_addr) {
+ phys_config.page_table_start_addr =
pa_config->gart_config.page_table_start_addr >> 12;
+ phys_config.page_table_end_addr =
pa_config->gart_config.page_table_end_addr >> 12;
+ phys_config.page_table_base_addr =
pa_config->gart_config.page_table_base_addr;
+ phys_config.depth = 0;
+ phys_config.block_size = 0;
+ // Init VMID 0 based on PA config
+ dcn20_vmid_setup(>vmid[0], _config);
+
+ dcn20_vmid_setup(>vmid[15], _config);
+ }
+
+ dcn21_dchvm_init(hubbub);
return NUM_VMID;
}
@@ -922,23 +946,6 @@ static void hubbub31_get_dchub_ref_freq(struct hubbub
*hubbub,
}
}
-static void hubbub31_apply_invalidation_req_wa(struct hubbub *hubbub,
- struct dcn_hubbub_phys_addr_config *pa_config)
-{
- struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
- struct dcn_vmid_page_table_config phys_config;
-
- if (pa_config->gart_config.page_table_start_addr !=
pa_config->gart_config.page_table_end_addr) {
- phys_config.page_table_start_addr =
pa_config->gart_config.page_table_start_addr >> 12;
- phys_config.page_table_end_addr =
pa_config->gart_config.page_table_end_addr >> 12;
- phys_config.page_table_base_addr =
pa_config->gart_config.page_table_base_addr;
- phys_config.depth = 0;
- phys_config.block_size = 0;
- // Program an arbitrary unused VMID
- dcn20_vmid_setup(>vmid[15], _config);
- }
-}
-
static const struct hubbub_funcs hubbub31_funcs = {
.update_dchub = hubbub2_update_dchub,
.init_dchub_sys_ctx = hubbub31_init_dchub_sys_ctx,
@@ -955,7 +962,6 @@ static const struct hubbub_funcs hubbub31_funcs = {
.program_compbuf_size = dcn31_program_compbuf_size,
.init_crb = dcn31_init_crb,
[PATCH 10/14] drm/amd/display: Always wait for update lock status
From: Eric Bernstein Remove code that would skip wait for lock status for Diags FPGA case Reviewed-by: Laktyushkin Dmytro Acked-by: Solomon Chiu Signed-off-by: Eric Bernstein --- drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c | 8 +++- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c index f37e8254df21..089be7347591 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c @@ -109,11 +109,9 @@ void optc3_lock(struct timing_generator *optc) REG_SET(OTG_MASTER_UPDATE_LOCK, 0, OTG_MASTER_UPDATE_LOCK, 1); - /* Should be fast, status does not update on maximus */ - if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) - REG_WAIT(OTG_MASTER_UPDATE_LOCK, - UPDATE_LOCK_STATUS, 1, - 1, 10); + REG_WAIT(OTG_MASTER_UPDATE_LOCK, + UPDATE_LOCK_STATUS, 1, + 1, 10); } void optc3_set_out_mux(struct timing_generator *optc, enum otg_out_mux_dest dest) -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 14/14] drm/amd/display: 3.2.146
From: Aric Cyr This version brings along following fixed: - Guard DST_Y_PREFETCH register overflow in DCN21 - Add missing DCN21 IP parameter - Fix PSR command version - Add ETW logging for AUX failures - Add ETW log to dmub_psr_get_state - Fixed EdidUtility build errors - Fix missing reg offset for the dmcub test debug registers - Adding update authentication interface - Remove unused functions of opm state query support - Always wait for update lock status - Refactor riommu invalidation wa - Ensure dentist display clock update finished in DCN20 Reviewed-by: Hsieh Mike Acked-by: Solomon Chiu Signed-off-by: Aric Cyr --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 2f3810f0510c..a948f4f48935 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -45,7 +45,7 @@ /* forward declaration */ struct aux_payload; -#define DC_VER "3.2.145" +#define DC_VER "3.2.146" #define MAX_SURFACES 3 #define MAX_PLANES 6 -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 08/14] drm/amd/display: add update authentication interface
From: Wenjing Liu
[why]
Previously to toggle authentication, we need to remove and
add the same display back with modified adjustment.
This method will toggle DTM state without actual hardware changes.
This is not per design and would cause potential issues in the long run.
[how]
We are creating a dedicated interface that does the same thing as
remove and add back the display without changing DTM state.
Acked-by: Solomon Chiu
Signed-off-by: Wenjing Liu
---
.../gpu/drm/amd/display/modules/hdcp/hdcp.c | 64 +--
.../drm/amd/display/modules/inc/mod_hdcp.h| 11 +++-
2 files changed, 69 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
index b963226e8af4..2bcab9c9b96e 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
@@ -39,8 +39,12 @@ static void push_error_status(struct mod_hdcp *hdcp,
if (is_hdcp1(hdcp)) {
hdcp->connection.hdcp1_retry_count++;
+ if (hdcp->connection.hdcp1_retry_count == MAX_NUM_OF_ATTEMPTS)
+ hdcp->connection.link.adjust.hdcp1.disable = 1;
} else if (is_hdcp2(hdcp)) {
hdcp->connection.hdcp2_retry_count++;
+ if (hdcp->connection.hdcp2_retry_count == MAX_NUM_OF_ATTEMPTS)
+ hdcp->connection.link.adjust.hdcp2.disable = 1;
}
}
@@ -59,8 +63,7 @@ static uint8_t is_cp_desired_hdcp1(struct mod_hdcp *hdcp)
}
}
- return (hdcp->connection.hdcp1_retry_count < MAX_NUM_OF_ATTEMPTS) &&
- is_auth_needed &&
+ return is_auth_needed &&
!hdcp->connection.link.adjust.hdcp1.disable &&
!hdcp->connection.is_hdcp1_revoked;
}
@@ -80,8 +83,7 @@ static uint8_t is_cp_desired_hdcp2(struct mod_hdcp *hdcp)
}
}
- return (hdcp->connection.hdcp2_retry_count < MAX_NUM_OF_ATTEMPTS) &&
- is_auth_needed &&
+ return is_auth_needed &&
!hdcp->connection.link.adjust.hdcp2.disable &&
!hdcp->connection.is_hdcp2_revoked;
}
@@ -392,6 +394,60 @@ enum mod_hdcp_status mod_hdcp_remove_display(struct
mod_hdcp *hdcp,
return status;
}
+enum mod_hdcp_status mod_hdcp_update_authentication(struct mod_hdcp *hdcp,
+ uint8_t index,
+ struct mod_hdcp_link_adjustment *link_adjust,
+ struct mod_hdcp_display_adjustment *display_adjust,
+ struct mod_hdcp_output *output)
+{
+ enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
+ struct mod_hdcp_display *display = NULL;
+
+ HDCP_TOP_INTERFACE_TRACE_WITH_INDEX(hdcp, index);
+ memset(output, 0, sizeof(struct mod_hdcp_output));
+
+ /* find display in connection */
+ display = get_active_display_at_index(hdcp, index);
+ if (!display) {
+ status = MOD_HDCP_STATUS_DISPLAY_NOT_FOUND;
+ goto out;
+ }
+
+ /* skip if no changes */
+ if (memcmp(link_adjust, >connection.link.adjust,
+ sizeof(struct mod_hdcp_link_adjustment)) == 0 &&
+ memcmp(display_adjust, >adjust,
+ sizeof(struct
mod_hdcp_display_adjustment)) == 0) {
+ status = MOD_HDCP_STATUS_SUCCESS;
+ goto out;
+ }
+
+ /* stop current authentication */
+ status = reset_authentication(hdcp, output);
+ if (status != MOD_HDCP_STATUS_SUCCESS)
+ goto out;
+
+ /* clear retry counters */
+ reset_retry_counts(hdcp);
+
+ /* reset error trace */
+ memset(>connection.trace, 0, sizeof(hdcp->connection.trace));
+
+ /* set new adjustment */
+ hdcp->connection.link.adjust = *link_adjust;
+ display->adjust = *display_adjust;
+
+ /* request authentication when connection is not reset */
+ if (current_state(hdcp) != HDCP_UNINITIALIZED)
+ /* wait 100ms to debounce simultaneous updates for different
indices */
+ callback_in_ms(100, output);
+
+out:
+ if (status != MOD_HDCP_STATUS_SUCCESS)
+ push_error_status(hdcp, status);
+ return status;
+}
+
enum mod_hdcp_status mod_hdcp_query_display(struct mod_hdcp *hdcp,
uint8_t index, struct mod_hdcp_display_query *query)
{
diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h
b/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h
index c590493fd293..c1b485f5fb71 100644
--- a/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h
+++ b/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h
@@ -282,15 +282,22 @@ enum mod_hdcp_status mod_hdcp_setup(struct mod_hdcp *hdcp,
/* called per link on link destroy */
enum mod_hdcp_status mod_hdcp_teardown(struct mod_hdcp *hdcp);
-/* called per
[PATCH 09/14] drm/amd/display: remove unused functions
From: Wenjing Liu
[why]
It has been decided that opm state query support will be dropped.
Therefore link encryption enabled and save current encryption states
won't be used anymore and there are no foreseeable usages in the future.
We will remove these two interfaces for clean up.
Acked-by: Solomon Chiu
Signed-off-by: Wenjing Liu
---
.../amd/display/amdgpu_dm/amdgpu_dm_hdcp.c| 4 +-
.../gpu/drm/amd/display/modules/hdcp/hdcp.c | 6 ---
.../gpu/drm/amd/display/modules/hdcp/hdcp.h | 2 -
.../display/modules/hdcp/hdcp1_execution.c| 6 ---
.../display/modules/hdcp/hdcp2_execution.c| 3 --
.../drm/amd/display/modules/hdcp/hdcp_psp.c | 53 ---
.../drm/amd/display/modules/inc/mod_hdcp.h| 1 -
7 files changed, 22 insertions(+), 53 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
index e63c6885c757..8e39e9245d06 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
@@ -655,10 +655,8 @@ struct hdcp_workqueue *hdcp_create_workqueue(struct
amdgpu_device *adev, struct
INIT_DELAYED_WORK(_work[i].property_validate_dwork,
event_property_validate);
hdcp_work[i].hdcp.config.psp.handle = >psp;
- if (dc->ctx->dce_version == DCN_VERSION_3_1) {
+ if (dc->ctx->dce_version == DCN_VERSION_3_1)
hdcp_work[i].hdcp.config.psp.caps.dtm_v3_supported = 1;
-
hdcp_work[i].hdcp.config.psp.caps.opm_state_query_supported = false;
- }
hdcp_work[i].hdcp.config.ddc.handle = dc_get_link_at_index(dc,
i);
hdcp_work[i].hdcp.config.ddc.funcs.write_i2c = lp_write_i2c;
hdcp_work[i].hdcp.config.ddc.funcs.read_i2c = lp_read_i2c;
diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
index 2bcab9c9b96e..06d60f031a06 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
@@ -315,9 +315,6 @@ enum mod_hdcp_status mod_hdcp_add_display(struct mod_hdcp
*hdcp,
goto out;
}
- /* save current encryption states to restore after next authentication
*/
- mod_hdcp_save_current_encryption_states(hdcp);
-
/* reset existing authentication status */
status = reset_authentication(hdcp, output);
if (status != MOD_HDCP_STATUS_SUCCESS)
@@ -364,9 +361,6 @@ enum mod_hdcp_status mod_hdcp_remove_display(struct
mod_hdcp *hdcp,
goto out;
}
- /* save current encryption states to restore after next authentication
*/
- mod_hdcp_save_current_encryption_states(hdcp);
-
/* stop current authentication */
status = reset_authentication(hdcp, output);
if (status != MOD_HDCP_STATUS_SUCCESS)
diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
index 3ce91db560d1..7123f0915706 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
@@ -331,8 +331,6 @@ enum mod_hdcp_status mod_hdcp_add_display_to_topology(
struct mod_hdcp *hdcp, struct mod_hdcp_display *display);
enum mod_hdcp_status mod_hdcp_remove_display_from_topology(
struct mod_hdcp *hdcp, uint8_t index);
-bool mod_hdcp_is_link_encryption_enabled(struct mod_hdcp *hdcp);
-void mod_hdcp_save_current_encryption_states(struct mod_hdcp *hdcp);
enum mod_hdcp_status mod_hdcp_hdcp1_create_session(struct mod_hdcp *hdcp);
enum mod_hdcp_status mod_hdcp_hdcp1_destroy_session(struct mod_hdcp *hdcp);
enum mod_hdcp_status mod_hdcp_hdcp1_validate_rx(struct mod_hdcp *hdcp);
diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c
b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c
index de872e7958b0..6ec918af3bff 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c
@@ -266,9 +266,6 @@ static enum mod_hdcp_status authenticated(struct mod_hdcp
*hdcp,
mod_hdcp_execute_and_set(mod_hdcp_hdcp1_link_maintenance,
>link_maintenance, ,
hdcp, "link_maintenance");
-
- if (status != MOD_HDCP_STATUS_SUCCESS)
- mod_hdcp_save_current_encryption_states(hdcp);
out:
return status;
}
@@ -447,9 +444,6 @@ static enum mod_hdcp_status authenticated_dp(struct
mod_hdcp *hdcp,
mod_hdcp_execute_and_set(check_no_reauthentication_request_dp,
>reauth_request_check, ,
hdcp, "reauth_request_check");
-
- if (status != MOD_HDCP_STATUS_SUCCESS)
- mod_hdcp_save_current_encryption_states(hdcp);
out:
return status;
}
diff
[PATCH 07/14] drm/amd/display: fix missing reg offset
From: Eric Yang
[Why]
Initializing was missing reg offsets for the dmcub test debug registers
causing assert
[How]
Add initialization
Reviewed-by: Kazlauskas Nicholas
Acked-by: Solomon Chiu
Signed-off-by: Eric Yang
---
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
index c3ead13f4e2b..61446170056e 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
@@ -38,7 +38,10 @@
const struct dmub_srv_dcn31_regs dmub_srv_dcn31_regs = {
#define DMUB_SR(reg) REG_OFFSET_EXP(reg),
- { DMUB_DCN31_REGS() },
+ {
+ DMUB_DCN31_REGS()
+ DMCUB_INTERNAL_REGS()
+ },
#undef DMUB_SR
#define DMUB_SF(reg, field) FD_MASK(reg, field),
--
2.25.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 04/14] drm/amd/display: Add ETW logging for AUX failures
From: Wyatt Wood
[Why]
Would like to identify the cause of AUX transactions failing
via ETW logs.
[How]
Add ETW logging for AUX failures.
Reviewed-by: Pavic Josip
Acked-by: Solomon Chiu
Signed-off-by: Wyatt Wood
---
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
index 2fb88e54a4bf..058a9356a39a 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
@@ -71,6 +71,8 @@ enum {
#define DEFAULT_AUX_ENGINE_MULT 0
#define DEFAULT_AUX_ENGINE_LENGTH 69
+#define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */
+
static void release_engine(
struct dce_aux *engine)
{
@@ -743,5 +745,11 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
fail:
if (!payload_reply)
payload->reply = NULL;
+
+ DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_ERROR,
+ WPP_BIT_FLAG_DC_ERROR,
+ "AUX transaction failed. Result: %d",
+ operation_result);
+
return false;
}
--
2.25.1
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[PATCH 06/14] drm/amd/display: Fixed EdidUtility build errors
From: Mark Morra
[HOW]
Added #ifdefs and refactored various parts of dc to
allow dc_link to be built by AMD EDID UTILITY
[WHY]
dc_dsc was refactored moving some of the code that AMD EDID UTILITY needed
to dc_link, so now dc_link needs to be included by AMD EDID UTILITY
Reviewed-by: Leung Martin
Acked-by: Solomon Chiu
Signed-off-by: Mark Morra
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 108 +++--
drivers/gpu/drm/amd/display/dc/dc.h | 118 +++---
drivers/gpu/drm/amd/display/dc/dc_types.h | 81 ++--
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 393 ++
4 files changed, 380 insertions(+), 320 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index f68a0d9543f4..5be9d6c70ea6 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -3517,61 +3517,6 @@ void dc_link_enable_hpd_filter(struct dc_link *link,
bool enable)
}
}
-uint32_t dc_bandwidth_in_kbps_from_timing(
- const struct dc_crtc_timing *timing)
-{
- uint32_t bits_per_channel = 0;
- uint32_t kbps;
-
-#if defined(CONFIG_DRM_AMD_DC_DCN)
- if (timing->flags.DSC)
- return dc_dsc_stream_bandwidth_in_kbps(timing,
- timing->dsc_cfg.bits_per_pixel,
- timing->dsc_cfg.num_slices_h,
- timing->dsc_cfg.is_dp);
-#endif
-
- switch (timing->display_color_depth) {
- case COLOR_DEPTH_666:
- bits_per_channel = 6;
- break;
- case COLOR_DEPTH_888:
- bits_per_channel = 8;
- break;
- case COLOR_DEPTH_101010:
- bits_per_channel = 10;
- break;
- case COLOR_DEPTH_121212:
- bits_per_channel = 12;
- break;
- case COLOR_DEPTH_141414:
- bits_per_channel = 14;
- break;
- case COLOR_DEPTH_161616:
- bits_per_channel = 16;
- break;
- default:
- ASSERT(bits_per_channel != 0);
- bits_per_channel = 8;
- break;
- }
-
- kbps = timing->pix_clk_100hz / 10;
- kbps *= bits_per_channel;
-
- if (timing->flags.Y_ONLY != 1) {
- /*Only YOnly make reduce bandwidth by 1/3 compares to RGB*/
- kbps *= 3;
- if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
- kbps /= 2;
- else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
- kbps = kbps * 2 / 3;
- }
-
- return kbps;
-
-}
-
void dc_link_set_drive_settings(struct dc *dc,
struct link_training_settings *lt_settings,
const struct dc_link *link)
@@ -3777,3 +3722,56 @@ bool dc_link_should_enable_fec(const struct dc_link
*link)
return ret;
}
+
+uint32_t dc_bandwidth_in_kbps_from_timing(
+ const struct dc_crtc_timing *timing)
+{
+ uint32_t bits_per_channel = 0;
+ uint32_t kbps;
+
+ if (timing->flags.DSC)
+ return dc_dsc_stream_bandwidth_in_kbps(timing,
+ timing->dsc_cfg.bits_per_pixel,
+ timing->dsc_cfg.num_slices_h,
+ timing->dsc_cfg.is_dp);
+
+ switch (timing->display_color_depth) {
+ case COLOR_DEPTH_666:
+ bits_per_channel = 6;
+ break;
+ case COLOR_DEPTH_888:
+ bits_per_channel = 8;
+ break;
+ case COLOR_DEPTH_101010:
+ bits_per_channel = 10;
+ break;
+ case COLOR_DEPTH_121212:
+ bits_per_channel = 12;
+ break;
+ case COLOR_DEPTH_141414:
+ bits_per_channel = 14;
+ break;
+ case COLOR_DEPTH_161616:
+ bits_per_channel = 16;
+ break;
+ default:
+ ASSERT(bits_per_channel != 0);
+ bits_per_channel = 8;
+ break;
+ }
+
+ kbps = timing->pix_clk_100hz / 10;
+ kbps *= bits_per_channel;
+
+ if (timing->flags.Y_ONLY != 1) {
+ /*Only YOnly make reduce bandwidth by 1/3 compares to RGB*/
+ kbps *= 3;
+ if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
+ kbps /= 2;
+ else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
+ kbps = kbps * 2 / 3;
+ }
+
+ return kbps;
+
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 3f2a0f1807d2..2f3810f0510c 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -458,7 +458,65 @@ union mem_low_power_enable_options {
uint32_t u32All;
[PATCH 05/14] drm/amd/display: Add ETW log to dmub_psr_get_state
From: Wyatt Wood
[Why]
GPINT commands have the lowest priority in DMCUB, so it's possible
that the command isn't processed in time.
[How]
Add a log to help identify this case.
Reviewed-by: Koo Anthony
Acked-by: Solomon Chiu
Signed-off-by: Wyatt Wood
---
drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 17 ++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
index 3428334c6c57..1ca8b1d94bc2 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
@@ -29,6 +29,8 @@
#include "dmub/dmub_srv.h"
#include "core_types.h"
+#define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */
+
#define MAX_PIPES 6
/*
@@ -96,10 +98,19 @@ static void dmub_psr_get_state(struct dmub_psr *dmub, enum
dc_psr_state *state,
// Return invalid state when GPINT times out
*state = PSR_STATE_INVALID;
- // Assert if max retry hit
- if (retry_count >= 1000)
- ASSERT(0);
} while (++retry_count <= 1000 && *state == PSR_STATE_INVALID);
+
+ // Assert if max retry hit
+ if (retry_count >= 1000 && *state == PSR_STATE_INVALID) {
+ ASSERT(0);
+ DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_ERROR,
+ WPP_BIT_FLAG_Firmware_PsrState,
+ "Unable to get PSR state from FW.");
+ } else
+ DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_VERBOSE,
+ WPP_BIT_FLAG_Firmware_PsrState,
+ "Got PSR state from FW. PSR state: %d, Retry
count: %d",
+ *state, retry_count);
}
/*
--
2.25.1
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[PATCH 03/14] drm/amd/display: Fix PSR command version
From: Mikita Lipski [why] For dual eDP when setting the new settings we need to set command version to DMUB_CMD_PSR_CONTROL_VERSION_1, otherwise DMUB will not read panel_inst parameter. [how] Instead of PSR_VERSION_1 pass DMUB_CMD_PSR_CONTROL_VERSION_1 Reviewed-by: Wood Wyatt Acked-by: Solomon Chiu Signed-off-by: Mikita Lipski --- drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c index 10d42ae0cffe..3428334c6c57 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c @@ -207,7 +207,7 @@ static void dmub_psr_set_level(struct dmub_psr *dmub, uint16_t psr_level, uint8_ cmd.psr_set_level.header.sub_type = DMUB_CMD__PSR_SET_LEVEL; cmd.psr_set_level.header.payload_bytes = sizeof(struct dmub_cmd_psr_set_level_data); cmd.psr_set_level.psr_set_level_data.psr_level = psr_level; - cmd.psr_set_level.psr_set_level_data.cmd_version = PSR_VERSION_1; + cmd.psr_set_level.psr_set_level_data.cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1; cmd.psr_set_level.psr_set_level_data.panel_inst = panel_inst; dc_dmub_srv_cmd_queue(dc->dmub_srv, ); dc_dmub_srv_cmd_execute(dc->dmub_srv); @@ -293,7 +293,7 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub, copy_settings_data->debug.bitfields.use_hw_lock_mgr = 1; copy_settings_data->fec_enable_status = (link->fec_state == dc_link_fec_enabled); copy_settings_data->fec_enable_delay_in100us = link->dc->debug.fec_enable_delay_in100us; - copy_settings_data->cmd_version = PSR_VERSION_1; + copy_settings_data->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1; copy_settings_data->panel_inst = panel_inst; dc_dmub_srv_cmd_queue(dc->dmub_srv, ); -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 01/14] drm/amd/display: Guard DST_Y_PREFETCH register overflow in DCN21
From: Victor Lu
[why]
DST_Y_PREFETCH can overflow when DestinationLinesForPrefetch values are
too large due to the former being limited to 8 bits.
[how]
Set the maximum value of DestinationLinesForPrefetch to be 255 * refclk
period.
Reviewed-by: Laktyushkin Dmytro
Acked-by: Solomon Chiu
Signed-off-by: Victor Lu
---
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
index 506797c721ed..4136eb8256cb 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
@@ -841,6 +841,9 @@ static bool CalculatePrefetchSchedule(
else
*DestinationLinesForPrefetch = dst_y_prefetch_equ;
+ // Limit to prevent overflow in DST_Y_PREFETCH register
+ *DestinationLinesForPrefetch = dml_min(*DestinationLinesForPrefetch,
63.75);
+
dml_print("DML: VStartup: %d\n", VStartup);
dml_print("DML: TCalc: %f\n", TCalc);
dml_print("DML: TWait: %f\n", TWait);
--
2.25.1
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[PATCH 02/14] drm/amd/display: Add missing DCN21 IP parameter
From: Victor Lu
[why]
IP parameter min_meta_chunk_size_bytes is read for bandwidth
calculations but it was never defined.
[how]
Define min_meta_chunk_size_bytes and initialize value to 256.
Reviewed-by: Laktyushkin Dmytro
Acked-by: Solomon Chiu
Signed-off-by: Victor Lu
---
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index a5dd97a2c5a3..f27fc2acac57 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -109,6 +109,7 @@ struct _vcs_dpi_ip_params_st dcn2_1_ip = {
.max_page_table_levels = 4,
.pte_chunk_size_kbytes = 2,
.meta_chunk_size_kbytes = 2,
+ .min_meta_chunk_size_bytes = 256,
.writeback_chunk_size_kbytes = 2,
.line_buffer_size_bits = 789504,
.is_line_buffer_bpp_fixed = 0,
--
2.25.1
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[PATCH 00/14] DC Patches July 26, 2021
This DC patchset brings improvements in multiple areas. In summary, we highlight: * Guard DST_Y_PREFETCH register overflow in DCN21 * Add missing DCN21 IP parameter * Fix PSR command version * Add ETW logging for AUX failures * Add ETW log to dmub_psr_get_state * Fixed EdidUtility build errors * Fix missing reg offset for the dmcub test debug registers * Adding update authentication interface * Remove unused functions of opm state query support * Always wait for update lock status * Refactor riommu invalidation wa * Ensure dentist display clock update finished in DCN20 Anthony Koo (1): drm/amd/display: [FW Promotion] Release 0.0.76 Aric Cyr (1): drm/amd/display: 3.2.146 Dale Zhao (1): drm/amd/display: ensure dentist display clock update finished in DCN20 Eric Bernstein (1): drm/amd/display: Always wait for update lock status Eric Yang (2): drm/amd/display: fix missing reg offset drm/amd/display: refactor riommu invalidation wa Mark Morra (1): drm/amd/display: Fixed EdidUtility build errors Mikita Lipski (1): drm/amd/display: Fix PSR command version Victor Lu (2): drm/amd/display: Guard DST_Y_PREFETCH register overflow in DCN21 drm/amd/display: Add missing DCN21 IP parameter Wenjing Liu (2): drm/amd/display: add update authentication interface drm/amd/display: remove unused functions Wyatt Wood (2): drm/amd/display: Add ETW logging for AUX failures drm/amd/display: Add ETW log to dmub_psr_get_state .../amd/display/amdgpu_dm/amdgpu_dm_hdcp.c| 4 +- .../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 2 +- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 108 +++-- drivers/gpu/drm/amd/display/dc/dc.h | 120 +++--- drivers/gpu/drm/amd/display/dc/dc_types.h | 81 ++-- drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 8 + drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 21 +- .../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 6 - .../drm/amd/display/dc/dcn21/dcn21_resource.c | 1 + .../gpu/drm/amd/display/dc/dcn30/dcn30_optc.c | 8 +- .../drm/amd/display/dc/dcn31/dcn31_hubbub.c | 48 ++- .../drm/amd/display/dc/dcn31/dcn31_hwseq.c| 17 - .../gpu/drm/amd/display/dc/dcn31/dcn31_init.c | 2 +- .../drm/amd/display/dc/dcn31/dcn31_resource.c | 1 - .../dc/dml/dcn21/display_mode_vba_21.c| 3 + drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 393 ++ .../gpu/drm/amd/display/dc/inc/hw/dchubbub.h | 3 - .../amd/display/dc/inc/hw_sequencer_private.h | 1 - .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 +- .../gpu/drm/amd/display/dmub/src/dmub_dcn31.c | 5 +- .../gpu/drm/amd/display/modules/hdcp/hdcp.c | 70 +++- .../gpu/drm/amd/display/modules/hdcp/hdcp.h | 2 - .../display/modules/hdcp/hdcp1_execution.c| 6 - .../display/modules/hdcp/hdcp2_execution.c| 3 - .../drm/amd/display/modules/hdcp/hdcp_psp.c | 53 +-- .../drm/amd/display/modules/inc/mod_hdcp.h| 12 +- 26 files changed, 538 insertions(+), 444 deletions(-) -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 00/14] DC Patches July 26, 2021
This DC patchset brings improvements in multiple areas. In summary, we highlight: * Guard DST_Y_PREFETCH register overflow in DCN21 * Add missing DCN21 IP parameter * Fix PSR command version * Add ETW logging for AUX failures * Add ETW log to dmub_psr_get_state * Fixed EdidUtility build errors * Fix missing reg offset for the dmcub test debug registers * Adding update authentication interface * Remove unused functions of opm state query support * Always wait for update lock status * Refactor riommu invalidation wa * Ensure dentist display clock update finished in DCN20 Anthony Koo (1): drm/amd/display: [FW Promotion] Release 0.0.76 Aric Cyr (1): drm/amd/display: 3.2.146 Dale Zhao (1): drm/amd/display: ensure dentist display clock update finished in DCN20 Eric Bernstein (1): drm/amd/display: Always wait for update lock status Eric Yang (2): drm/amd/display: fix missing reg offset drm/amd/display: refactor riommu invalidation wa Mark Morra (1): drm/amd/display: Fixed EdidUtility build errors Mikita Lipski (1): drm/amd/display: Fix PSR command version Victor Lu (2): drm/amd/display: Guard DST_Y_PREFETCH register overflow in DCN21 drm/amd/display: Add missing DCN21 IP parameter Wenjing Liu (2): drm/amd/display: add update authentication interface drm/amd/display: remove unused functions Wyatt Wood (2): drm/amd/display: Add ETW logging for AUX failures drm/amd/display: Add ETW log to dmub_psr_get_state .../amd/display/amdgpu_dm/amdgpu_dm_hdcp.c| 4 +- .../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 2 +- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 108 +++-- drivers/gpu/drm/amd/display/dc/dc.h | 120 +++--- drivers/gpu/drm/amd/display/dc/dc_types.h | 81 ++-- drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 8 + drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 21 +- .../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 6 - .../drm/amd/display/dc/dcn21/dcn21_resource.c | 1 + .../gpu/drm/amd/display/dc/dcn30/dcn30_optc.c | 8 +- .../drm/amd/display/dc/dcn31/dcn31_hubbub.c | 48 ++- .../drm/amd/display/dc/dcn31/dcn31_hwseq.c| 17 - .../gpu/drm/amd/display/dc/dcn31/dcn31_init.c | 2 +- .../drm/amd/display/dc/dcn31/dcn31_resource.c | 1 - .../dc/dml/dcn21/display_mode_vba_21.c| 3 + drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 393 ++ .../gpu/drm/amd/display/dc/inc/hw/dchubbub.h | 3 - .../amd/display/dc/inc/hw_sequencer_private.h | 1 - .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 +- .../gpu/drm/amd/display/dmub/src/dmub_dcn31.c | 5 +- .../gpu/drm/amd/display/modules/hdcp/hdcp.c | 70 +++- .../gpu/drm/amd/display/modules/hdcp/hdcp.h | 2 - .../display/modules/hdcp/hdcp1_execution.c| 6 - .../display/modules/hdcp/hdcp2_execution.c| 3 - .../drm/amd/display/modules/hdcp/hdcp_psp.c | 53 +-- .../drm/amd/display/modules/inc/mod_hdcp.h| 12 +- 26 files changed, 538 insertions(+), 444 deletions(-) -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH 1/3] drm/amdgpu: create amdgpu_vkms (v2)
[Public]
Look copy right statement is missed in both amdgpu_vkms.c and amdgpu_vkms.h.
Regards,
Guchun
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: Friday, July 23, 2021 10:32 PM
To: Taylor, Ryan
Cc: kernel test robot ; Daniel Vetter ;
Siqueira, Rodrigo ; amd-gfx list
; Melissa Wen ; Maling
list - DRI developers
Subject: Re: [PATCH 1/3] drm/amdgpu: create amdgpu_vkms (v2)
On Wed, Jul 21, 2021 at 1:07 PM Ryan Taylor wrote:
>
> Modify the VKMS driver into an api that dce_virtual can use to create
> virtual displays that obey drm's atomic modesetting api.
>
> v2: Made local functions static.
>
> Reported-by: kernel test robot
> Signed-off-by: Ryan Taylor
> ---
> drivers/gpu/drm/amd/amdgpu/Makefile | 1 +
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 411
> +++ drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.h |
> 29 ++ drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 23 +-
> 7 files changed, 458 insertions(+), 11 deletions(-) create mode
> 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
> create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.h
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
> b/drivers/gpu/drm/amd/amdgpu/Makefile
> index f089794bbdd5..30cbcd5ce1cc 100644
> --- a/drivers/gpu/drm/amd/amdgpu/Makefile
> +++ b/drivers/gpu/drm/amd/amdgpu/Makefile
> @@ -120,6 +120,7 @@ amdgpu-y += \
> amdgpu-y += \
> dce_v10_0.o \
> dce_v11_0.o \
> + amdgpu_vkms.o \
> dce_virtual.o
>
> # add GFX block
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 54cf647bd018..d0a2f2ed433d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -919,6 +919,7 @@ struct amdgpu_device {
>
> /* display */
> boolenable_virtual_display;
> + struct amdgpu_vkms_output *amdgpu_vkms_output;
> struct amdgpu_mode_info mode_info;
> /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */
> struct work_struct hotplug_work;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index d0c935cf4f0f..1b016e5bc75f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -1230,7 +1230,7 @@ static int amdgpu_pci_probe(struct pci_dev *pdev,
> int ret, retry = 0;
> bool supports_atomic = false;
>
> - if (!amdgpu_virtual_display &&
> + if (amdgpu_virtual_display ||
> amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK))
> supports_atomic = true;
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
> index 09b048647523..5a143ca02cf9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
> @@ -344,7 +344,7 @@ int amdgpu_fbdev_init(struct amdgpu_device *adev)
> }
>
> /* disable all the possible outputs/crtcs before entering KMS mode */
> - if (!amdgpu_device_has_dc_support(adev))
> + if (!amdgpu_device_has_dc_support(adev) &&
> + !amdgpu_virtual_display)
>
> drm_helper_disable_unused_functions(adev_to_drm(adev));
>
> drm_fb_helper_initial_config(>helper, bpp_sel); diff
> --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
> new file mode 100644
> index ..d5c1f1c58f5f
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
> @@ -0,0 +1,411 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +
> +#include
> +#include #include
> +
> +#include "amdgpu.h"
> +#include "amdgpu_vkms.h"
> +#include "amdgpu_display.h"
> +
> +/**
> + * DOC: amdgpu_vkms
> + *
> + * The amdgpu vkms interface provides a virtual KMS interface for
> +several use
> + * cases: devices without display hardware, platforms where the
> +actual display
> + * hardware is not useful (e.g., servers), SR-IOV virtual functions,
> +device
> + * emulation/simulation, and device bring up prior to display
> +hardware being
> + * usable. We previously emulated a legacy KMS interface, but there
> +was a desire
> + * to move to the atomic KMS interface. The vkms driver did
> +everything we
> + * needed, but we wanted KMS support natively in the driver without
> +buffer
> + * sharing and the ability to support an instance of VKMS per device.
> +We first
> + * looked at splitting vkms into a stub driver and a helper module
> +that other
> + * drivers could use to implement a virtual display, but this
> +strategy ended up
> + * being messy due to driver specific callbacks needed for buffer management.
> + * Ultimately, it proved easier to import the vkms code as it mostly
>
