[PATCH AUTOSEL 5.14 15/40] drm/amdkfd: fix svm_migrate_fini warning

[Sasha Levin]

From: Philip Yang 

[ Upstream commit 197ae17722e989942b36e33e044787877f158574 ]

Device manager releases device-specific resources when a driver
disconnects from a device, devm_memunmap_pages and
devm_release_mem_region calls in svm_migrate_fini are redundant.

It causes below warning trace after patch "drm/amdgpu: Split
amdgpu_device_fini into early and late", so remove function
svm_migrate_fini.

BUG: https://gitlab.freedesktop.org/drm/amd/-/issues/1718

WARNING: CPU: 1 PID: 3646 at drivers/base/devres.c:795
devm_release_action+0x51/0x60
Call Trace:
? memunmap_pages+0x360/0x360
svm_migrate_fini+0x2d/0x60 [amdgpu]
kgd2kfd_device_exit+0x23/0xa0 [amdgpu]
amdgpu_amdkfd_device_fini_sw+0x1d/0x30 [amdgpu]
amdgpu_device_fini_sw+0x45/0x290 [amdgpu]
amdgpu_driver_release_kms+0x12/0x30 [amdgpu]
drm_dev_release+0x20/0x40 [drm]
release_nodes+0x196/0x1e0
device_release_driver_internal+0x104/0x1d0
driver_detach+0x47/0x90
bus_remove_driver+0x7a/0xd0
pci_unregister_driver+0x3d/0x90
amdgpu_exit+0x11/0x20 [amdgpu]

Signed-off-by: Philip Yang 
Reviewed-by: Felix Kuehling 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdkfd/kfd_device.c  |  1 -
 drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 13 -
 drivers/gpu/drm/amd/amdkfd/kfd_migrate.h |  5 -
 3 files changed, 4 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index 9e52948d4992..0e5ebb384164 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -910,7 +910,6 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd,
 void kgd2kfd_device_exit(struct kfd_dev *kfd)
 {
if (kfd->init_complete) {
-   svm_migrate_fini((struct amdgpu_device *)kfd->kgd);
device_queue_manager_uninit(kfd->dqm);
kfd_interrupt_exit(kfd);
kfd_topology_remove_device(kfd);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
index 165e0ebb619d..4a16e3c257b9 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
@@ -891,6 +891,10 @@ int svm_migrate_init(struct amdgpu_device *adev)
pgmap->ops = _migrate_pgmap_ops;
pgmap->owner = SVM_ADEV_PGMAP_OWNER(adev);
pgmap->flags = MIGRATE_VMA_SELECT_DEVICE_PRIVATE;
+
+   /* Device manager releases device-specific resources, memory region and
+* pgmap when driver disconnects from device.
+*/
r = devm_memremap_pages(adev->dev, pgmap);
if (IS_ERR(r)) {
pr_err("failed to register HMM device memory\n");
@@ -911,12 +915,3 @@ int svm_migrate_init(struct amdgpu_device *adev)
 
return 0;
 }
-
-void svm_migrate_fini(struct amdgpu_device *adev)
-{
-   struct dev_pagemap *pgmap = >kfd.dev->pgmap;
-
-   devm_memunmap_pages(adev->dev, pgmap);
-   devm_release_mem_region(adev->dev, pgmap->range.start,
-   pgmap->range.end - pgmap->range.start + 1);
-}
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.h 
b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.h
index 0de76b5d4973..2f5b3394c9ed 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.h
@@ -47,7 +47,6 @@ unsigned long
 svm_migrate_addr_to_pfn(struct amdgpu_device *adev, unsigned long addr);
 
 int svm_migrate_init(struct amdgpu_device *adev);
-void svm_migrate_fini(struct amdgpu_device *adev);
 
 #else
 
@@ -55,10 +54,6 @@ static inline int svm_migrate_init(struct amdgpu_device 
*adev)
 {
return 0;
 }
-static inline void svm_migrate_fini(struct amdgpu_device *adev)
-{
-   /* empty */
-}
 
 #endif /* IS_ENABLED(CONFIG_HSA_AMD_SVM) */
 
-- 
2.33.0

[PATCH AUTOSEL 5.14 14/40] drm/amdkfd: handle svm migrate init error

[Sasha Levin]

From: Philip Yang 

[ Upstream commit 7d6687200a939176847090bbde5cb79a82792a2f ]

If svm migration init failed to create pgmap for device memory, set
pgmap type to 0 to disable device SVM support capability.

Signed-off-by: Philip Yang 
Reviewed-by: Felix Kuehling 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
index dab290a4d19d..165e0ebb619d 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
@@ -894,6 +894,9 @@ int svm_migrate_init(struct amdgpu_device *adev)
r = devm_memremap_pages(adev->dev, pgmap);
if (IS_ERR(r)) {
pr_err("failed to register HMM device memory\n");
+
+   /* Disable SVM support capability */
+   pgmap->type = 0;
devm_release_mem_region(adev->dev, res->start,
res->end - res->start + 1);
return PTR_ERR(r);
-- 
2.33.0

Re: [PATCH] amd/amdkfd: add ras page retirement handling for sq/sdma (v2)

[Zhou1, Tao]

[AMD Official Use Only]

Ping...

From: Zhou1, Tao 
Sent: Friday, September 24, 2021 4:37 PM
To: amd-gfx@lists.freedesktop.org ; Zhang, 
Hawking ; Kuehling, Felix ; 
Joshi, Mukul ; Yang, Stanley 
Cc: Zhou1, Tao 
Subject: [PATCH] amd/amdkfd: add ras page retirement handling for sq/sdma (v2)

In ras poison mode, page retirement will be handled by the irq handler of the
module which consumes corrupted data.

v2: rename ras_process_cb to ras_poison_consumption_handler.
move the handler's implementation from ASIC specific file to common
file.

Signed-off-by: Tao Zhou 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c  | 14 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h  |  1 +
 drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c |  4 ++--
 3 files changed, 17 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index 1d41c2c00623..7bc4248a8d49 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -31,6 +31,8 @@
 #include 
 #include "amdgpu_xgmi.h"
 #include 
+#include "amdgpu_ras.h"
+#include "amdgpu_umc.h"

 /* Total memory size in system memory and all GPU VRAM. Used to
  * estimate worst case amount of memory to reserve for page tables
@@ -780,3 +782,15 @@ bool amdgpu_amdkfd_have_atomics_support(struct kgd_dev 
*kgd)

 return adev->have_atomics_support;
 }
+
+int amdgpu_amdkfd_ras_poison_consumption_handler(struct kgd_dev *kgd)
+{
+   struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
+   struct ras_err_data err_data = {0, 0, 0, NULL};
+
+   /* CPU MCA will handle it if connected_to_cpu is 1 */
+   if (!adev->gmc.xgmi.connected_to_cpu)
+   return amdgpu_umc_process_ras_data_cb(adev, _data, NULL);
+   else
+   return 0;
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index 3bc52b2c604f..d118e1dc273d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -290,6 +290,7 @@ int amdgpu_amdkfd_gpuvm_import_dmabuf(struct kgd_dev *kgd,
   uint64_t *mmap_offset);
 int amdgpu_amdkfd_get_tile_config(struct kgd_dev *kgd,
 struct tile_config *config);
+int amdgpu_amdkfd_ras_poison_consumption_handler(struct kgd_dev *kgd);
 #if IS_ENABLED(CONFIG_HSA_AMD)
 void amdgpu_amdkfd_gpuvm_init_mem_limits(void);
 void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c
index 12d91e53556c..543e7ea75593 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c
@@ -231,7 +231,7 @@ static void event_interrupt_wq_v9(struct kfd_dev *dev,
 if (sq_intr_err != 
SQ_INTERRUPT_ERROR_TYPE_ILLEGAL_INST &&
 sq_intr_err != 
SQ_INTERRUPT_ERROR_TYPE_MEMVIOL) {
 kfd_signal_poison_consumed_event(dev, 
pasid);
-   amdgpu_amdkfd_gpu_reset(dev->kgd);
+   
amdgpu_amdkfd_ras_poison_consumption_handler(dev->kgd);
 return;
 }
 break;
@@ -253,7 +253,7 @@ static void event_interrupt_wq_v9(struct kfd_dev *dev,
 kfd_signal_event_interrupt(pasid, context_id0 & 
0xfff, 28);
 } else if (source_id == SOC15_INTSRC_SDMA_ECC) {
 kfd_signal_poison_consumed_event(dev, pasid);
-   amdgpu_amdkfd_gpu_reset(dev->kgd);
+   amdgpu_amdkfd_ras_poison_consumption_handler(dev->kgd);
 return;
 }
 } else if (client_id == SOC15_IH_CLIENTID_VMC ||
--
2.17.1

[PATCH] drm/amd/pm: Fix that RPM cannot be obtained for specific GPU

[huangyizhi]

The current mechanism for obtaining RPM is to read tach_period from
the register, and then calculate the RPM together with the frequency.
But we found that on specific GPUs, such as RX 550 and RX 560D,
tach_period always reads as 0 and smu7_fan_ctrl_get_fan_speed_rpm
will returns -EINVAL.

To solve this problem, when reading tach_period as 0, we try
to estimate the current RPM using the percentage of current pwm, the
maximum and minimum RPM.

Signed-off-by: huangyizhi 
---
 .../drm/amd/pm/powerplay/hwmgr/smu7_thermal.c | 28 ---
 1 file changed, 24 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c 
b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c
index a6c3610db23e..307dd87d6882 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c
@@ -81,6 +81,11 @@ int smu7_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, 
uint32_t *speed)
 {
uint32_t tach_period;
uint32_t crystal_clock_freq;
+   uint32_t duty100;
+   uint32_t duty;
+   uint32_t speed_percent;
+   uint64_t tmp64;
+
 
if (hwmgr->thermal_controller.fanInfo.bNoFan ||
!hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution)
@@ -89,13 +94,28 @@ int smu7_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, 
uint32_t *speed)
tach_period = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, 
CGS_IND_REG__SMC,
CG_TACH_STATUS, TACH_PERIOD);
 
-   if (tach_period == 0)
-   return -EINVAL;
+   if (tach_period == 0) {
 
-   crystal_clock_freq = amdgpu_asic_get_xclk((struct amdgpu_device 
*)hwmgr->adev);
+   duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, 
CGS_IND_REG__SMC,
+   CG_FDO_CTRL1, FMAX_DUTY100);
+   duty = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, 
CGS_IND_REG__SMC,
+   CG_THERMAL_STATUS, FDO_PWM_DUTY);
 
-   *speed = 60 * crystal_clock_freq * 1 / tach_period;
+   if (duty100 == 0)
+   return -EINVAL;
 
+   tmp64 = (uint64_t)duty * 100;
+   do_div(tmp64, duty100);
+   speed_percent = MIN((uint32_t)tmp64, 100);
+
+   *speed = speed_percent * 
(hwmgr->thermal_controller.fanInfo.ulMaxRPM
+   - hwmgr->thermal_controller.fanInfo.ulMinRPM) / 100;
+   } else {
+
+   crystal_clock_freq = amdgpu_asic_get_xclk((struct amdgpu_device 
*)hwmgr->adev);
+
+   *speed = 60 * crystal_clock_freq * 1 / tach_period;
+   }
return 0;
 }
 
-- 
2.30.0

Re: [PATCH 02/02 v2] drm/amd/display: add cyan_skillfish display support

[Alex Deucher]

On Mon, Sep 27, 2021 at 5:16 PM Liu, Zhan  wrote:
>
> [Public]
>
> [Why]
> add display related cyan_skillfish files in.
>
> makefile controlled by CONFIG_DRM_AMD_DC_DCN201 flag.
>
> Signed-off-by: Charlene Liu 
> Signed-off-by: Zhan Liu 
> Reviewed-by: Charlene Liu 
> Acked-by: Jun Lei 
> ---
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 1d6cc93..0c669e4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -1968,6 +1968,9 @@
> case CHIP_VANGOGH:
> chip_name = "vangogh";
> break;
> +   case CHIP_CYAN_SKILLFISH:
> +   chip_name = "cyan_skillfish";
> +   break;
> case CHIP_YELLOW_CARP:
> chip_name = "yellow_carp";
> break;

Sorry I missed this before.  This change is unnecessary.  there is no
gpu_info firmware for cyan skillfish.  Please drop this hunk.  With
that fixed:
Acked-by: Alex Deucher 

Alex

[pull] amdgpu, amdkfd, radeon drm-next-5.16

[Alex Deucher]

Hi Dave, Daniel,

New stuff for 5.16.

The following changes since commit 8f0284f190e6a0aa09015090568c03f18288231a:

  Merge tag 'amd-drm-next-5.15-2021-08-27' of 
https://gitlab.freedesktop.org/agd5f/linux into drm-next (2021-08-30 09:06:03 
+1000)

are available in the Git repository at:

  https://gitlab.freedesktop.org/agd5f/linux.git 
tags/amd-drm-next-5.16-2021-09-27

for you to fetch changes up to 2485e2753ec896b169526e3ef7988589d1c458f5:

  drm/amdgpu: make soc15_common_ip_funcs static (2021-09-23 16:35:27 -0400)


amd-drm-next-5.16-2021-09-27:

amdgpu:
- RAS improvements
- BACO fixes
- Yellow Carp updates
- Misc code cleanups
- Initial DP 2.0 support
- VCN priority handling
- Cyan Skillfish updates
- Rework IB handling for multimedia engine tests
- Backlight fixes
- DCN 3.1 power saving improvements
- Runtime PM fixes
- Modifier support for DCC image stores for gfx 10.3
- Hotplug fixes
- Clean up stack related warnings in display code
- DP alt mode fixes
- Display rework for better handling FP code
- Debugfs fixes

amdkfd:
- SVM fixes
- DMA map fixes

radeon:
- AGP fix


Aaron Liu (1):
  drm/amd/display: setup system context for APUs

Alex Deucher (4):
  drm/amdgpu: add some additional RDNA2 PCI IDs
  drm/amdgpu/display: add a proper license to dc_link_dp.c
  MAINTAINERS: fix up entry for AMD Powerplay
  drm/amdgpu: make soc15_common_ip_funcs static

Alex Sierra (1):
  drm/amdkfd: drop process ref count when xnack disable

Alvin Lee (1):
  drm/amd/display: Update swizzle mode enums

Andrey Grodzovsky (4):
  drm/amd/display: Fix crash on device remove/driver unload
  drm/amdgpu: Fix crash on device remove/driver unload
  drm/amdgpu: Fix MMIO access page fault
  drm/amdgpu: Fix resume failures when device is gone

Angus Wang (1):
  drm/amd/display: cleanup idents after a revert

Anson Jacob (5):
  drm/amd/display: Fix memory leak reported by coverity
  drm/amd/display: dc_assert_fp_enabled assert only if FPU is not enabled
  drm/amd/display: Fix false BAD_FREE warning from Coverity
  drm/amd/display: Fix multiple memory leaks reported by coverity
  drm/amd/display: Revert "Directly retrain link from debugfs"

Anthony Koo (5):
  drm/amd/display: [FW Promotion] Release 0.0.80
  drm/amd/display: [FW Promotion] Release 0.0.81
  drm/amd/display: [FW Promotion] Release 0.0.82
  drm/amd/display: [FW Promotion] Release 0.0.83
  drm/amd/display: [FW Promotion] Release 0.0.84

Aric Cyr (5):
  drm/amd/display: 3.2.150
  drm/amd/display: 3.2.151
  drm/amd/display: 3.2.152
  drm/amd/display: 3.2.153
  drm/amd/display: 3.2.154

Arnd Bergmann (1):
  drm/amd/display: fix empty debug macros

Aurabindo Pillai (2):
  drm/amd/display: Add emulated sink support for updating FS
  drm/amd/display: Add flag to detect dpms force off during HPD

Candice Li (7):
  drm/amd/amdgpu: consolidate PSP TA unload function
  drm/amd/amdgpu: add mpio to ras block
  drm/amdgpu: Create common PSP TA load function
  drm/amdgpu: Unify PSP TA context
  drm/amdgpu: Conform ASD header/loading to generic TA systems
  drm/amdgpu: Update PSP TA unload function
  drm/amdgpu: Remove all code paths under the EAGAIN path in RAS late init

Christian König (2):
  drm/amdgpu: fix use after free during BO move
  drm/amdgpu: remove unused amdgpu_bo_validate

Colin Ian King (7):
  drm/amdgpu/swsmu: fix spelling mistake "minimun" -> "minimum"
  drm/amd/display: fix spelling mistake "alidation" -> "validation"
  drm/amd/display: Fix unused initialization of pointer sink
  drm/amdgpu: clean up inconsistent indenting
  drm/amdgpu: sdma: clean up identation
  drm/radeon/ci_dpm: Remove redundant initialization of variables hi_sidd, 
lo_sidd
  drm/radeon: make array encoded_lanes static

Dale Zhao (1):
  drm/amd/display: Refine condition of cursor visibility for pipe-split

Eric Yang (1):
  drm/amd/display: Add periodic detection when zstate is enabled

Ernst Sjöstrand (1):
  drm/amd/amdgpu: Increase HWIP_MAX_INSTANCE to 10

Evan Quan (2):
  drm/amdgpu: reenable BACO support for 699F:C7 polaris12 SKU
  drm/amd/pm: fix runpm hang when amdgpu loaded prior to sound driver

Fangzhi Zuo (6):
  drm/amd/display: Add DP 2.0 Audio Package Generator
  drm/amd/display: Add DP 2.0 HPO Stream Encoder
  drm/amd/display: Add DP 2.0 HPO Link Encoder
  drm/amd/display: Add DP 2.0 DCCG
  drm/amd/display: Add DP 2.0 BIOS and DMUB Support
  drm/amd/display: Add DP 2.0 SST DC Support

Felix Kuehling (1):
  drm/amdkfd: make needs_pcie_atomics FW-version dependent

Guchun Chen (2):
  drm/amdgpu: stop scheduler when calling hw_fini (v2)
  drm/amdgpu: move amdgpu_virt_release_full_gpu to fini_early stage

Guo, Bing (1):
 

RE: [PATCH 02/02] drm/amd/display: add cyan_skillfish display support

[Liu, Zhan]

[Public]

> -Original Message-
> From: Alex Deucher 
> Sent: 2021/September/27, Monday 4:50 PM
> To: Liu, Zhan 
> Cc: amd-gfx@lists.freedesktop.org; Liu, Charlene ;
> Wentland, Harry ; Deucher, Alexander
> ; Lei, Jun ; Pillai,
> Aurabindo 
> Subject: Re: [PATCH 02/02] drm/amd/display: add cyan_skillfish display
> support
>
> On Mon, Sep 27, 2021 at 4:43 PM Liu, Zhan  wrote:
> >
> > [Public]
> >
> > [Why]
> > add display related cyan_skillfish files in.
> >
> > makefile controlled by CONFIG_DRM_AMD_DC_DCN201 flag.
> >
> > Signed-off-by: Charlene Liu 
> > Signed-off-by: Zhan Liu 
> > Reviewed-by: Charlene Liu 
> > Acked-by: Jun Lei 
> > ---
> 
>
> > @@ -1457,34 +1460,33 @@
> >  #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
> > adev->dm.crc_rd_wrk =
> amdgpu_dm_crtc_secure_display_create_work();
> >  #endif
> > -   if (dc_enable_dmub_notifications(adev->dm.dc)) {
> > -   init_completion(>dm.dmub_aux_transfer_done);
> > -   adev->dm.dmub_notify = kzalloc(sizeof(struct 
> > dmub_notification),
> GFP_KERNEL);
> > -   if (!adev->dm.dmub_notify) {
> > -   DRM_INFO("amdgpu: fail to allocate 
> > adev->dm.dmub_notify");
> > -   goto error;
> > -   }
> >
> > -   adev->dm.delayed_hpd_wq =
> create_singlethread_workqueue("amdgpu_dm_hpd_wq");
> > -   if (!adev->dm.delayed_hpd_wq) {
> > -   DRM_ERROR("amdgpu: failed to create hpd offload
> workqueue.\n");
> > -   goto error;
> > -   }
> > -
> > -   amdgpu_dm_outbox_init(adev);
> > -#if defined(CONFIG_DRM_AMD_DC_DCN)
> > -   if (!register_dmub_notify_callback(adev,
> DMUB_NOTIFICATION_AUX_REPLY,
> > -   dmub_aux_setconfig_callback, false)) {
> > -   DRM_ERROR("amdgpu: fail to register dmub aux 
> > callback");
> > -   goto error;
> > -   }
> > -   if (!register_dmub_notify_callback(adev,
> DMUB_NOTIFICATION_HPD, dmub_hpd_callback, true)) {
> > -   DRM_ERROR("amdgpu: fail to register dmub hpd 
> > callback");
> > -   goto error;
> > -   }
> > -#endif
> > +   init_completion(>dm.dmub_aux_transfer_done);
> > +   adev->dm.dmub_notify = kzalloc(sizeof(struct dmub_notification),
> GFP_KERNEL);
> > +   if (!adev->dm.dmub_notify) {
> > +   DRM_INFO("amdgpu: fail to allocate adev->dm.dmub_notify");
> > +   goto error;
> > }
> >
> > +   adev->dm.delayed_hpd_wq =
> create_singlethread_workqueue("amdgpu_dm_hpd_wq");
> > +   if (!adev->dm.delayed_hpd_wq) {
> > +   DRM_ERROR("amdgpu: failed to create hpd offload
> workqueue.\n");
> > +   goto error;
> > +   }
> > +
> > +   amdgpu_dm_outbox_init(adev);
> > +#if defined(CONFIG_DRM_AMD_DC_DCN)
> > +   if (!register_dmub_notify_callback(adev,
> DMUB_NOTIFICATION_AUX_REPLY,
> > +   dmub_aux_setconfig_callback, false)) {
> > +   DRM_ERROR("amdgpu: fail to register dmub aux callback");
> > +   goto error;
> > +   }
> > +   if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD,
> dmub_hpd_callback, true)) {
> > +   DRM_ERROR("amdgpu: fail to register dmub hpd callback");
> > +   goto error;
> > +   }
> > +#endif
> > +
>
> This change above looks unrelated.  Please double check this is correct.

Hi Alex, sorry it was my bad. Yes, you are totally correct, thanks a lot for 
catching that. Let me send out my patch v2 soon.

Thanks,
Zhan

>
> Alex

Re: [PATCH 02/02] drm/amd/display: add cyan_skillfish display support

[Alex Deucher]

On Mon, Sep 27, 2021 at 4:43 PM Liu, Zhan  wrote:
>
> [Public]
>
> [Why]
> add display related cyan_skillfish files in.
>
> makefile controlled by CONFIG_DRM_AMD_DC_DCN201 flag.
>
> Signed-off-by: Charlene Liu 
> Signed-off-by: Zhan Liu 
> Reviewed-by: Charlene Liu 
> Acked-by: Jun Lei 
> ---


> @@ -1457,34 +1460,33 @@
>  #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
> adev->dm.crc_rd_wrk = amdgpu_dm_crtc_secure_display_create_work();
>  #endif
> -   if (dc_enable_dmub_notifications(adev->dm.dc)) {
> -   init_completion(>dm.dmub_aux_transfer_done);
> -   adev->dm.dmub_notify = kzalloc(sizeof(struct 
> dmub_notification), GFP_KERNEL);
> -   if (!adev->dm.dmub_notify) {
> -   DRM_INFO("amdgpu: fail to allocate 
> adev->dm.dmub_notify");
> -   goto error;
> -   }
>
> -   adev->dm.delayed_hpd_wq = 
> create_singlethread_workqueue("amdgpu_dm_hpd_wq");
> -   if (!adev->dm.delayed_hpd_wq) {
> -   DRM_ERROR("amdgpu: failed to create hpd offload 
> workqueue.\n");
> -   goto error;
> -   }
> -
> -   amdgpu_dm_outbox_init(adev);
> -#if defined(CONFIG_DRM_AMD_DC_DCN)
> -   if (!register_dmub_notify_callback(adev, 
> DMUB_NOTIFICATION_AUX_REPLY,
> -   dmub_aux_setconfig_callback, false)) {
> -   DRM_ERROR("amdgpu: fail to register dmub aux 
> callback");
> -   goto error;
> -   }
> -   if (!register_dmub_notify_callback(adev, 
> DMUB_NOTIFICATION_HPD, dmub_hpd_callback, true)) {
> -   DRM_ERROR("amdgpu: fail to register dmub hpd 
> callback");
> -   goto error;
> -   }
> -#endif
> +   init_completion(>dm.dmub_aux_transfer_done);
> +   adev->dm.dmub_notify = kzalloc(sizeof(struct dmub_notification), 
> GFP_KERNEL);
> +   if (!adev->dm.dmub_notify) {
> +   DRM_INFO("amdgpu: fail to allocate adev->dm.dmub_notify");
> +   goto error;
> }
>
> +   adev->dm.delayed_hpd_wq = 
> create_singlethread_workqueue("amdgpu_dm_hpd_wq");
> +   if (!adev->dm.delayed_hpd_wq) {
> +   DRM_ERROR("amdgpu: failed to create hpd offload 
> workqueue.\n");
> +   goto error;
> +   }
> +
> +   amdgpu_dm_outbox_init(adev);
> +#if defined(CONFIG_DRM_AMD_DC_DCN)
> +   if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_AUX_REPLY,
> +   dmub_aux_setconfig_callback, false)) {
> +   DRM_ERROR("amdgpu: fail to register dmub aux callback");
> +   goto error;
> +   }
> +   if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD, 
> dmub_hpd_callback, true)) {
> +   DRM_ERROR("amdgpu: fail to register dmub hpd callback");
> +   goto error;
> +   }
> +#endif
> +

This change above looks unrelated.  Please double check this is correct.

Alex

[PATCH 00/02] cyan skillfish display support

[Liu, Zhan]

[Public]

This patch set brings cyan skillfish display support

Charlene Liu / Zhan Liu (2):
drm/amdgpu: add cyan_skillfish asic header files
drm/amd/display: add cyan_skillfish display support

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 +
 drivers/gpu/drm/amd/amdgpu/nv.c| 2 +
 drivers/gpu/drm/amd/display/Kconfig| 9 +
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c  |55 +-
 drivers/gpu/drm/amd/display/dc/Makefile| 3 +
 drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c| 1 +
 drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile|11 +
 drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c   | 7 +
 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c |   260 +++
 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.h |34 +
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c  |10 +
 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h  | 9 +
 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h |39 +
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h   |27 +
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c  | 3 +
 drivers/gpu/drm/amd/display/dc/dcn201/Makefile |33 +
 drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dccg.c|84 +
 drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dccg.h|37 +
 drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dpp.c |   316 +++
 drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dpp.h |83 +
 drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hubbub.c  |   107 +
 drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hubbub.h  |45 +
 drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hubp.c|   150 ++
 drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hubp.h|   132 ++
 drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hwseq.c   |   630 ++
 drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hwseq.h   |46 +
 drivers/gpu/drm/amd/display/dc/dcn201/dcn201_init.c|   131 ++
 drivers/gpu/drm/amd/display/dc/dcn201/dcn201_init.h|33 +
 drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.c|   209 ++
 drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.h|59 +
 drivers/gpu/drm/amd/display/dc/dcn201/dcn201_mpc.c |   125 ++
 drivers/gpu/drm/amd/display/dc/dcn201/dcn201_mpc.h |86 +
 drivers/gpu/drm/amd/display/dc/dcn201/dcn201_opp.c |72 +
 drivers/gpu/drm/amd/display/dc/dcn201/dcn201_opp.h |74 +
 drivers/gpu/drm/amd/display/dc/dcn201/dcn201_optc.c|   203 ++
 drivers/gpu/drm/amd/display/dc/dcn201/dcn201_optc.h|74 +
 drivers/gpu/drm/amd/display/dc/dcn201/dcn201_resource.c|  1307 

 drivers/gpu/drm/amd/display/dc/dcn201/dcn201_resource.h|50 +
 drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c  | 1 +
 drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h  | 1 +
 drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c   | 1 +
 drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c | 1 +
 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h   |13 +
 drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h| 4 +-
 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h| 1 +
 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h  | 4 +
 drivers/gpu/drm/amd/display/dc/irq/Makefile|12 +
 drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c |   374 
 drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.h |34 +
 drivers/gpu/drm/amd/display/include/dal_asic_id.h  | 1 +
 drivers/gpu/drm/amd/display/include/dal_types.h| 1 +
 drivers/gpu/drm/amd/include/asic_reg/clk/clk_11_0_1_offset.h   |32 +
 drivers/gpu/drm/amd/include/asic_reg/clk/clk_11_0_1_sh_mask.h  |37 +
 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_3_offset.h|  6193 
+
 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_3_sh_mask.h   | 22091 
+
 drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_2_0_3_offset.h  |   151 ++
 drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_2_0_3_sh_mask.h |   952 
+
 57 files changed, 34439 insertions(+), 25 deletions(-)

--
2.25.1

Re: [PATCH] drm/amd/amdgpu: Validate ip discovery blob

[Alex Deucher]

Applied with minor updates to the error messages.

Thanks!

Alex

On Sun, Sep 26, 2021 at 5:27 PM Ernst Sjöstrand  wrote:
>
> We use the number_instance index that we get from the fw discovery blob
> to index into an array for example.
>
> Signed-off-by: Ernst Sjöstrand 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 19 +++
>  1 file changed, 19 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> index ada7bc19118a..b3fc46ba8144 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> @@ -245,6 +245,20 @@ void amdgpu_discovery_fini(struct amdgpu_device *adev)
> adev->mman.discovery_bin = NULL;
>  }
>
> +static int amdgpu_discovery_validate_ip(const struct ip *ip)
> +{
> +   if (ip->number_instance >= HWIP_MAX_INSTANCE) {
> +   DRM_ERROR("Unexpected number_instance from ip discovery 
> blob\n");
> +   return -EINVAL;
> +   }
> +   if (le16_to_cpu(ip->hw_id) >= HW_ID_MAX) {
> +   DRM_ERROR("Unexpected hw_id from ip discovery blob\n");
> +   return -EINVAL;
> +   }
> +
> +   return 0;
> +}
> +
>  int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev)
>  {
> struct binary_header *bhdr;
> @@ -290,6 +304,10 @@ int amdgpu_discovery_reg_base_init(struct amdgpu_device 
> *adev)
>
> for (j = 0; j < num_ips; j++) {
> ip = (struct ip *)(adev->mman.discovery_bin + 
> ip_offset);
> +
> +   if (amdgpu_discovery_validate_ip(ip))
> +   goto next_ip;
> +
> num_base_address = ip->num_base_address;
>
> DRM_DEBUG("%s(%d) #%d v%d.%d.%d:\n",
> @@ -321,6 +339,7 @@ int amdgpu_discovery_reg_base_init(struct amdgpu_device 
> *adev)
>
> }
>
> +next_ip:
> ip_offset += sizeof(*ip) + 4 * (ip->num_base_address 
> - 1);
> }
> }
> --
> 2.30.2
>

Re: [PATCH] gpu: amd: replace open-coded offsetof() with builtin

[Alex Deucher]

Applied.  Thanks!

Alex

On Mon, Sep 27, 2021 at 8:21 AM Arnd Bergmann  wrote:
>
> From: Arnd Bergmann 
>
> The two AMD drivers have their own custom offsetof() implementation
> that now triggers a warning with recent versions of clang:
>
> drivers/gpu/drm/radeon/radeon_atombios.c:133:14: error: performing pointer 
> subtraction with a null pointer has undefined behavior 
> [-Werror,-Wnull-pointer-subtraction]
>
> Change all the instances to use the normal offsetof() provided
> by the kernel that does not have this problem.
>
> Signed-off-by: Arnd Bergmann 
> ---
>  drivers/gpu/drm/amd/display/dc/bios/command_table2.c  | 4 +---
>  drivers/gpu/drm/amd/include/atombios.h| 2 +-
>  drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h | 4 ++--
>  drivers/gpu/drm/radeon/atombios.h | 2 +-
>  4 files changed, 5 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table2.c 
> b/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
> index f1f672a997d7..4f37be727332 100644
> --- a/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
> +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
> @@ -44,9 +44,7 @@
> bp->base.ctx->logger
>
>  #define GET_INDEX_INTO_MASTER_TABLE(MasterOrData, FieldName)\
> -   (((char *)(&((\
> -   struct atom_master_list_of_##MasterOrData##_functions_v2_1 
> *)0)\
> -   ->FieldName)-(char *)0)/sizeof(uint16_t))
> +   (offsetof(struct atom_master_list_of_##MasterOrData##_functions_v2_1, 
> FieldName) / sizeof(uint16_t))
>
>  #define EXEC_BIOS_CMD_TABLE(fname, params)\
> (amdgpu_atom_execute_table(((struct amdgpu_device 
> *)bp->base.ctx->driver_context)->mode_info.atom_context, \
> diff --git a/drivers/gpu/drm/amd/include/atombios.h 
> b/drivers/gpu/drm/amd/include/atombios.h
> index 6a505d1b82a5..da895d1f3b4f 100644
> --- a/drivers/gpu/drm/amd/include/atombios.h
> +++ b/drivers/gpu/drm/amd/include/atombios.h
> @@ -7148,7 +7148,7 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3
>  #define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) 
> (((static_cast(TABLE_HEADER_OFFSET))->ucTableFormatRevision
>  )&0x3F)
>  #define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET)  
> (((static_cast(TABLE_HEADER_OFFSET))->ucTableContentRevision)&0x3F)
>  #else // not __cplusplus
> -#define   GetIndexIntoMasterTable(MasterOrData, FieldName) 
> (((char*)(&((ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*)0)->FieldName)-(char*)0)/sizeof(USHORT))
> +#define   GetIndexIntoMasterTable(MasterOrData, FieldName) 
> (offsetof(ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES, FieldName) / 
> sizeof(USHORT))
>
>  #define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) 
> ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableFormatRevision)&0x3F)
>  #define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET)  
> ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableContentRevision)&0x3F)
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h 
> b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h
> index b7e2651b570b..2fc1733bcdcf 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h
> +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h
> @@ -29,9 +29,9 @@
>  typedef enum atom_smu9_syspll0_clock_id BIOS_CLKID;
>
>  #define GetIndexIntoMasterCmdTable(FieldName) \
> -   (((char*)(&((struct 
> atom_master_list_of_command_functions_v2_1*)0)->FieldName)-(char*)0)/sizeof(uint16_t))
> +   (offsetof(struct atom_master_list_of_command_functions_v2_1, 
> FieldName) / sizeof(uint16_t))
>  #define GetIndexIntoMasterDataTable(FieldName) \
> -   (((char*)(&((struct 
> atom_master_list_of_data_tables_v2_1*)0)->FieldName)-(char*)0)/sizeof(uint16_t))
> +   (offsetof(struct atom_master_list_of_data_tables_v2_1, FieldName) / 
> sizeof(uint16_t))
>
>  #define PP_ATOMFWCTRL_MAX_VOLTAGE_ENTRIES 32
>
> diff --git a/drivers/gpu/drm/radeon/atombios.h 
> b/drivers/gpu/drm/radeon/atombios.h
> index 83e8b8547f9b..bd5dc09e860f 100644
> --- a/drivers/gpu/drm/radeon/atombios.h
> +++ b/drivers/gpu/drm/radeon/atombios.h
> @@ -5983,7 +5983,7 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3
>  #define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) 
> (((static_cast(TABLE_HEADER_OFFSET))->ucTableFormatRevision
>  )&0x3F)
>  #define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET)  
> (((static_cast(TABLE_HEADER_OFFSET))->ucTableContentRevision)&0x3F)
>  #else // not __cplusplus
> -#defineGetIndexIntoMasterTable(MasterOrData, FieldName) 
> (((char*)(&((ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*)0)->FieldName)-(char*)0)/sizeof(USHORT))
> +#defineGetIndexIntoMasterTable(MasterOrData, FieldName) 
> (offsetof(ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES, 
> FieldName)/sizeof(USHORT))
>
>  #define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) 
> 

Re: [PATCH] drm/amdkfd: fix resource_size.cocci warnings

[Alex Deucher]

Applied.  Thanks!

Alex

On Sun, Sep 26, 2021 at 3:10 PM Amos Jianjun Kong  wrote:
>
> On Sun, Sep 26, 2021 at 3:17 PM Yang Li  wrote:
>>
>> Use resource_size function on resource object
>> instead of explicit computation.
>>
>> Clean up coccicheck warning:
>> ./drivers/gpu/drm/amd/amdkfd/kfd_migrate.c:905:10-13: ERROR: Missing
>> resource_size with res
>>
>> Reported-by: Abaci Robot 
>> Signed-off-by: Yang Li 
>> ---
>>  drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 3 +--
>>  1 file changed, 1 insertion(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c 
>> b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
>> index 4a16e3c..f53e17a 100644
>> --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
>> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
>> @@ -901,8 +901,7 @@ int svm_migrate_init(struct amdgpu_device *adev)
>>
>> /* Disable SVM support capability */
>> pgmap->type = 0;
>> -   devm_release_mem_region(adev->dev, res->start,
>> -   res->end - res->start + 1);
>> +   devm_release_mem_region(adev->dev, res->start, 
>> resource_size(res));
>
>
> Looks good.
> Reviewed-by: Amos Kong 
>
>
>>
>> return PTR_ERR(r);
>> }
>>
>> --
>> 1.8.3.1
>>

[PATCH v3] drm/dp: Add Additional DP2 Headers

[Fangzhi Zuo]

Include FEC, DSC, Link Training related headers.

Change since v2
- Align with the spec for DP_DSC_SUPPORT_AND_DSC_DECODER_COUNT

Signed-off-by: Fangzhi Zuo 
---
This patch is based on top of the other DP2.0 work in
"drm/dp: add LTTPR DP 2.0 DPCD addresses"
---
 include/drm/drm_dp_helper.h | 20 
 1 file changed, 20 insertions(+)

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 1d5b3dbb6e56..a1df35aa6e68 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -453,6 +453,7 @@ struct drm_panel;
 # define DP_FEC_UNCORR_BLK_ERROR_COUNT_CAP  (1 << 1)
 # define DP_FEC_CORR_BLK_ERROR_COUNT_CAP(1 << 2)
 # define DP_FEC_BIT_ERROR_COUNT_CAP(1 << 3)
+#define DP_FEC_CAPABILITY_10x091   /* 2.0 */
 
 /* DP-HDMI2.1 PCON DSC ENCODER SUPPORT */
 #define DP_PCON_DSC_ENCODER_CAP_SIZE0xC/* 0x9E - 0x92 */
@@ -537,6 +538,9 @@ struct drm_panel;
 #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1  0x0a1
 #define DP_DSC_BRANCH_MAX_LINE_WIDTH0x0a2
 
+/* DFP Capability Extension */
+#define DP_DFP_CAPABILITY_EXTENSION_SUPPORT0x0a3   /* 2.0 */
+
 /* Link Configuration */
 #defineDP_LINK_BW_SET  0x100
 # define DP_LINK_RATE_TABLE0x00/* eDP 1.4 */
@@ -688,6 +692,7 @@ struct drm_panel;
 
 #define DP_DSC_ENABLE   0x160   /* DP 1.4 */
 # define DP_DECOMPRESSION_EN(1 << 0)
+#define DP_DSC_CONFIGURATION   0x161   /* DP 2.0 */
 
 #define DP_PSR_EN_CFG  0x170   /* XXX 1.2? */
 # define DP_PSR_ENABLE BIT(0)
@@ -743,6 +748,7 @@ struct drm_panel;
 # define DP_RECEIVE_PORT_0_STATUS  (1 << 0)
 # define DP_RECEIVE_PORT_1_STATUS  (1 << 1)
 # define DP_STREAM_REGENERATION_STATUS  (1 << 2) /* 2.0 */
+# define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3) /* 2.0 */
 
 #define DP_ADJUST_REQUEST_LANE0_1  0x206
 #define DP_ADJUST_REQUEST_LANE2_3  0x207
@@ -865,6 +871,8 @@ struct drm_panel;
 # define DP_PHY_TEST_PATTERN_80BIT_CUSTOM   0x4
 # define DP_PHY_TEST_PATTERN_CP2520 0x5
 
+#define DP_PHY_SQUARE_PATTERN  0x249
+
 #define DP_TEST_HBR2_SCRAMBLER_RESET0x24A
 #define DP_TEST_80BIT_CUSTOM_PATTERN_7_00x250
 #defineDP_TEST_80BIT_CUSTOM_PATTERN_15_8   0x251
@@ -1109,6 +1117,18 @@ struct drm_panel;
 #define DP_128B132B_TRAINING_AUX_RD_INTERVAL   0x2216 /* 2.0 */
 # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK 0x7f
 
+#define DP_TEST_264BIT_CUSTOM_PATTERN_7_0  0x2230
+#define DP_TEST_264BIT_CUSTOM_PATTERN_263_256  0x2250
+
+/* DSC Extended Capability Branch Total DSC Resources */
+#define DP_DSC_SUPPORT_AND_DSC_DECODER_COUNT   0x2260  /* 2.0 */
+# define DP_DSC_DECODER_COUNT_MASK (0b111 << 5)
+# define DP_DSC_DECODER_COUNT_SHIFT5
+#define DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0   0x2270  /* 2.0 */
+# define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK (1 << 0)
+# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK (0b111 << 1)
+# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT1
+
 /* Protocol Converter Extension */
 /* HDMI CEC tunneling over AUX DP 1.3 section 5.3.3.3.1 DPCD 1.4+ */
 #define DP_CEC_TUNNELING_CAPABILITY0x3000
-- 
2.25.1

Re: [PATCH] drm/amdgpu: fix warning for overflow check

[Alex Deucher]

Applied.  Thanks!

On Mon, Sep 27, 2021 at 9:07 AM Christian König
 wrote:
>
> Am 27.09.21 um 14:58 schrieb Arnd Bergmann:
> > From: Arnd Bergmann 
> >
> > The overflow check in amdgpu_bo_list_create() causes a warning with
> > clang-14 on 64-bit architectures, since the limit can never be
> > exceeded.
> >
> > drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c:74:18: error: result of 
> > comparison of constant 256204778801521549 with expression of type 'unsigned 
> > int' is always false [-Werror,-Wtautological-constant-out-of-range-compare]
> >  if (num_entries > (SIZE_MAX - sizeof(struct amdgpu_bo_list))
> >  ~~~ ^ ~~
> >
> > The check remains useful for 32-bit architectures, so just avoid the
> > warning by using size_t as the type for the count.
> >
> > Fixes: 920990cb080a ("drm/amdgpu: allocate the bo_list array after the 
> > list")
> > Signed-off-by: Arnd Bergmann 
>
> Reviewed-by: Christian König 
>
> > ---
> >   drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c | 2 +-
> >   drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h | 2 +-
> >   2 files changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c 
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
> > index 15c45b2a3983..714178f1b6c6 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
> > @@ -61,7 +61,7 @@ static void amdgpu_bo_list_free(struct kref *ref)
> >
> >   int amdgpu_bo_list_create(struct amdgpu_device *adev, struct drm_file 
> > *filp,
> > struct drm_amdgpu_bo_list_entry *info,
> > -   unsigned num_entries, struct amdgpu_bo_list 
> > **result)
> > +   size_t num_entries, struct amdgpu_bo_list **result)
> >   {
> >   unsigned last_entry = 0, first_userptr = num_entries;
> >   struct amdgpu_bo_list_entry *array;
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h 
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h
> > index c905a4cfc173..044b41f0bfd9 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h
> > @@ -61,7 +61,7 @@ int amdgpu_bo_create_list_entry_array(struct 
> > drm_amdgpu_bo_list_in *in,
> >   int amdgpu_bo_list_create(struct amdgpu_device *adev,
> >struct drm_file *filp,
> >struct drm_amdgpu_bo_list_entry *info,
> > -  unsigned num_entries,
> > +  size_t num_entries,
> >struct amdgpu_bo_list **list);
> >
> >   static inline struct amdgpu_bo_list_entry *
>

Re: [PATCH v2] amdgpu: check tiling flags when creating FB on GFX8-

[Alex Deucher]

On Mon, Sep 27, 2021 at 11:09 AM Simon Ser  wrote:
>
> On GFX9+, format modifiers are always enabled and ensure the
> frame-buffers can be scanned out at ADDFB2 time.
>
> On GFX8-, format modifiers are not supported and no other check
> is performed. This means ADDFB2 IOCTLs will succeed even if the
> tiling isn't supported for scan-out, and will result in garbage
> displayed on screen [1].
>
> Fix this by adding a check for tiling flags for GFX8 and older.
> The check is taken from radeonsi in Mesa (see how is_displayable
> is populated in gfx6_compute_surface).
>
> Changes in v2: use drm_WARN_ONCE instead of drm_WARN (Michel)
>
> [1]: https://github.com/swaywm/wlroots/issues/3185
>
> Signed-off-by: Simon Ser 
> Cc: sta...@vger.kernel.org
> Acked-by: Michel Dänzer 
> Cc: Alex Deucher 
> Cc: Harry Wentland 
> Cc: Nicholas Kazlauskas 
> Cc: Bas Nieuwenhuizen 

Applied.  Thanks.

Alex

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 31 +
>  1 file changed, 31 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> index 58bfc7f00d76..5faf3ef28080 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> @@ -837,6 +837,28 @@ static int convert_tiling_flags_to_modifier(struct 
> amdgpu_framebuffer *afb)
> return 0;
>  }
>
> +/* Mirrors the is_displayable check in radeonsi's gfx6_compute_surface */
> +static int check_tiling_flags_gfx6(struct amdgpu_framebuffer *afb)
> +{
> +   u64 micro_tile_mode;
> +
> +   /* Zero swizzle mode means linear */
> +   if (AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0)
> +   return 0;
> +
> +   micro_tile_mode = AMDGPU_TILING_GET(afb->tiling_flags, 
> MICRO_TILE_MODE);
> +   switch (micro_tile_mode) {
> +   case 0: /* DISPLAY */
> +   case 3: /* RENDER */
> +   return 0;
> +   default:
> +   drm_dbg_kms(afb->base.dev,
> +   "Micro tile mode %llu not supported for 
> scanout\n",
> +   micro_tile_mode);
> +   return -EINVAL;
> +   }
> +}
> +
>  static void get_block_dimensions(unsigned int block_log2, unsigned int cpp,
>  unsigned int *width, unsigned int *height)
>  {
> @@ -1103,6 +1125,7 @@ int amdgpu_display_framebuffer_init(struct drm_device 
> *dev,
> const struct drm_mode_fb_cmd2 *mode_cmd,
> struct drm_gem_object *obj)
>  {
> +   struct amdgpu_device *adev = drm_to_adev(dev);
> int ret, i;
>
> /*
> @@ -1122,6 +1145,14 @@ int amdgpu_display_framebuffer_init(struct drm_device 
> *dev,
> if (ret)
> return ret;
>
> +   if (!dev->mode_config.allow_fb_modifiers) {
> +   drm_WARN_ONCE(dev, adev->family >= AMDGPU_FAMILY_AI,
> + "GFX9+ requires FB check based on format 
> modifier\n");
> +   ret = check_tiling_flags_gfx6(rfb);
> +   if (ret)
> +   return ret;
> +   }
> +
> if (dev->mode_config.allow_fb_modifiers &&
> !(rfb->base.flags & DRM_MODE_FB_MODIFIERS)) {
> ret = convert_tiling_flags_to_modifier(rfb);
> --
> 2.33.0
>
>

[PATCH] drm/amdgpu/display: remove unused variable

[Alex Deucher]

No longer used, drop it.

Fixes: 1e07005161fc ("drm/amd/display: add function to convert hw to dpcd lane 
settings")
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 029cc78bc9e9..5eb40dcff315 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -520,7 +520,6 @@ static void dpcd_set_lt_pattern_and_lane_settings(
 
uint8_t dpcd_lt_buffer[5] = {0};
union dpcd_training_pattern dpcd_pattern = { {0} };
-   uint32_t lane;
uint32_t size_in_bytes;
bool edp_workaround = false; /* TODO link_prop.INTERNAL */
dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET;
@@ -1020,7 +1019,6 @@ enum dc_status dpcd_set_lane_settings(
uint32_t offset)
 {
union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = {{{0}}};
-   uint32_t lane;
unsigned int lane0_set_address;
enum dc_status status;
 
-- 
2.31.1

Re: [PATCHv3 2/2] drm/amdgpu: Register MCE notifier for Aldebaran RAS

[Yazen Ghannam]

On Sat, Sep 25, 2021 at 01:20:57PM +0200, Borislav Petkov wrote:
> On Fri, Sep 24, 2021 at 07:46:10PM +, Yazen Ghannam wrote:
> > I agree with you in general. But this device isn't really a GPU. And
> > users of this device seem to want to count *every* error, at least for
> > now.
> 
> Aha, so something accelerator-y where they do general purpose computation.
> 
> So what's the big picture here: they count all the errors and when they
> reach a certain amount, they decide to replace the GPUs just in case?
> 
> Or wait until they become uncorrectable? But then it doesn't matter
> because we will handle it properly by excluding the VRAM range from
> further use.
> 
> Or do they wanna see *when* they had the correctable errors so that they
> can restart the computation, just in case.
> 
> Dunno, it would be a lot helpful if we had some RAS strategy for those
> things...
>

I completely agree. The system integrators have their own policies for error
tracking, part replacement, etc. I expect they'll propose kernel changes if
they want any. Though I think general strategies will become apparent once
these sort of devices are in wider use.

Thanks,
Yazen

[PATCH v2] drm/dp: Add Additional DP2 Headers

[Fangzhi Zuo]

Include FEC, DSC, Link Training related headers.

Signed-off-by: Fangzhi Zuo 
---
This patch is based on top of the other DP2.0 work in
"drm/dp: add LTTPR DP 2.0 DPCD addresses"
---
 include/drm/drm_dp_helper.h | 20 
 1 file changed, 20 insertions(+)

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 1d5b3dbb6e56..f1fd9889f190 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -453,6 +453,7 @@ struct drm_panel;
 # define DP_FEC_UNCORR_BLK_ERROR_COUNT_CAP  (1 << 1)
 # define DP_FEC_CORR_BLK_ERROR_COUNT_CAP(1 << 2)
 # define DP_FEC_BIT_ERROR_COUNT_CAP(1 << 3)
+#define DP_FEC_CAPABILITY_10x091   /* 2.0 */
 
 /* DP-HDMI2.1 PCON DSC ENCODER SUPPORT */
 #define DP_PCON_DSC_ENCODER_CAP_SIZE0xC/* 0x9E - 0x92 */
@@ -537,6 +538,9 @@ struct drm_panel;
 #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1  0x0a1
 #define DP_DSC_BRANCH_MAX_LINE_WIDTH0x0a2
 
+/* DFP Capability Extension */
+#define DP_DFP_CAPABILITY_EXTENSION_SUPPORT0x0a3   /* 2.0 */
+
 /* Link Configuration */
 #defineDP_LINK_BW_SET  0x100
 # define DP_LINK_RATE_TABLE0x00/* eDP 1.4 */
@@ -688,6 +692,7 @@ struct drm_panel;
 
 #define DP_DSC_ENABLE   0x160   /* DP 1.4 */
 # define DP_DECOMPRESSION_EN(1 << 0)
+#define DP_DSC_CONFIGURATION   0x161   /* DP 2.0 */
 
 #define DP_PSR_EN_CFG  0x170   /* XXX 1.2? */
 # define DP_PSR_ENABLE BIT(0)
@@ -743,6 +748,7 @@ struct drm_panel;
 # define DP_RECEIVE_PORT_0_STATUS  (1 << 0)
 # define DP_RECEIVE_PORT_1_STATUS  (1 << 1)
 # define DP_STREAM_REGENERATION_STATUS  (1 << 2) /* 2.0 */
+# define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3) /* 2.0 */
 
 #define DP_ADJUST_REQUEST_LANE0_1  0x206
 #define DP_ADJUST_REQUEST_LANE2_3  0x207
@@ -865,6 +871,8 @@ struct drm_panel;
 # define DP_PHY_TEST_PATTERN_80BIT_CUSTOM   0x4
 # define DP_PHY_TEST_PATTERN_CP2520 0x5
 
+#define DP_PHY_SQUARE_PATTERN  0x249
+
 #define DP_TEST_HBR2_SCRAMBLER_RESET0x24A
 #define DP_TEST_80BIT_CUSTOM_PATTERN_7_00x250
 #defineDP_TEST_80BIT_CUSTOM_PATTERN_15_8   0x251
@@ -1109,6 +1117,18 @@ struct drm_panel;
 #define DP_128B132B_TRAINING_AUX_RD_INTERVAL   0x2216 /* 2.0 */
 # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK 0x7f
 
+#define DP_TEST_264BIT_CUSTOM_PATTERN_7_0  0x2230
+#define DP_TEST_264BIT_CUSTOM_PATTERN_263_256  0x2250
+
+/* DSC Extended Capability Branch Total DSC Resources */
+#define DP_DSC_SUPPORT_AND_DECODER_COUNT   0x2260  /* 2.0 
*/
+# define DP_DSC_DECODER_COUNT_MASK (0b111 << 5)
+# define DP_DSC_DECODER_COUNT_SHIFT5
+#define DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0   0x2270  /* 2.0 */
+# define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK (1 << 0)
+# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK (0b111 << 1)
+# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT1
+
 /* Protocol Converter Extension */
 /* HDMI CEC tunneling over AUX DP 1.3 section 5.3.3.3.1 DPCD 1.4+ */
 #define DP_CEC_TUNNELING_CAPABILITY0x3000
-- 
2.25.1

Re: [PATCH] drm/amdgpu: force exit gfxoff on sdma resume for rmb s0ix

[Alex Deucher]

On Sun, Sep 26, 2021 at 9:14 AM Prike Liang  wrote:
>
> In the s2idle stress test sdma resume fail occasionally,in the
> failed case GPU is in the gfxoff state.This issue may introduce
> by FSDL miss handle doorbell S/R and now temporary fix the issue
> by forcing exit gfxoff for sdma resume.
>
> Signed-off-by: Prike Liang 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 8 
>  1 file changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c 
> b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> index e4a96e7e386d..81906955ef52 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> @@ -868,6 +868,12 @@ static int sdma_v5_2_start(struct amdgpu_device *adev)
> msleep(1000);
> }
>
> +   /* TODO: check whether can submit a doorbell request to raise
> +* a doorbell fence to exit gfxoff.
> +*/
> +   if (adev->in_s0ix)
> +   amdgpu_gfx_off_ctrl(adev, false);
> +
> sdma_v5_2_soft_reset(adev);
> /* unhalt the MEs */
> sdma_v5_2_enable(adev, true);
> @@ -876,6 +882,8 @@ static int sdma_v5_2_start(struct amdgpu_device *adev)
>
> /* start the gfx rings and rlc compute queues */
> r = sdma_v5_2_gfx_resume(adev);
> +   if (adev->in_s0ix)
> +   amdgpu_gfx_off_ctrl(adev, true);
> if (r)
> return r;
> r = sdma_v5_2_rlc_resume(adev);
> --
> 2.17.1
>

Re: [PATCH] amdgpu: check tiling flags when creating FB on GFX8-

[Simon Ser]

On Monday, September 27th, 2021 at 16:57, Alex Deucher  
wrote:

> No objections from me with the WARN_ONCE change suggested by Michel.

Cool, just sent v2 with Michel's comment fixed.

[PATCH v2] amdgpu: check tiling flags when creating FB on GFX8-

[Simon Ser]

On GFX9+, format modifiers are always enabled and ensure the
frame-buffers can be scanned out at ADDFB2 time.

On GFX8-, format modifiers are not supported and no other check
is performed. This means ADDFB2 IOCTLs will succeed even if the
tiling isn't supported for scan-out, and will result in garbage
displayed on screen [1].

Fix this by adding a check for tiling flags for GFX8 and older.
The check is taken from radeonsi in Mesa (see how is_displayable
is populated in gfx6_compute_surface).

Changes in v2: use drm_WARN_ONCE instead of drm_WARN (Michel)

[1]: https://github.com/swaywm/wlroots/issues/3185

Signed-off-by: Simon Ser 
Cc: sta...@vger.kernel.org
Acked-by: Michel Dänzer 
Cc: Alex Deucher 
Cc: Harry Wentland 
Cc: Nicholas Kazlauskas 
Cc: Bas Nieuwenhuizen 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 31 +
 1 file changed, 31 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index 58bfc7f00d76..5faf3ef28080 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -837,6 +837,28 @@ static int convert_tiling_flags_to_modifier(struct 
amdgpu_framebuffer *afb)
return 0;
 }
 
+/* Mirrors the is_displayable check in radeonsi's gfx6_compute_surface */
+static int check_tiling_flags_gfx6(struct amdgpu_framebuffer *afb)
+{
+   u64 micro_tile_mode;
+
+   /* Zero swizzle mode means linear */
+   if (AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0)
+   return 0;
+
+   micro_tile_mode = AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE);
+   switch (micro_tile_mode) {
+   case 0: /* DISPLAY */
+   case 3: /* RENDER */
+   return 0;
+   default:
+   drm_dbg_kms(afb->base.dev,
+   "Micro tile mode %llu not supported for scanout\n",
+   micro_tile_mode);
+   return -EINVAL;
+   }
+}
+
 static void get_block_dimensions(unsigned int block_log2, unsigned int cpp,
 unsigned int *width, unsigned int *height)
 {
@@ -1103,6 +1125,7 @@ int amdgpu_display_framebuffer_init(struct drm_device 
*dev,
const struct drm_mode_fb_cmd2 *mode_cmd,
struct drm_gem_object *obj)
 {
+   struct amdgpu_device *adev = drm_to_adev(dev);
int ret, i;
 
/*
@@ -1122,6 +1145,14 @@ int amdgpu_display_framebuffer_init(struct drm_device 
*dev,
if (ret)
return ret;
 
+   if (!dev->mode_config.allow_fb_modifiers) {
+   drm_WARN_ONCE(dev, adev->family >= AMDGPU_FAMILY_AI,
+ "GFX9+ requires FB check based on format 
modifier\n");
+   ret = check_tiling_flags_gfx6(rfb);
+   if (ret)
+   return ret;
+   }
+
if (dev->mode_config.allow_fb_modifiers &&
!(rfb->base.flags & DRM_MODE_FB_MODIFIERS)) {
ret = convert_tiling_flags_to_modifier(rfb);
-- 
2.33.0

Re: [PATCH] amdgpu: check tiling flags when creating FB on GFX8-

[Alex Deucher]

On Mon, Sep 27, 2021 at 9:09 AM Simon Ser  wrote:
>
> Alex, Harry, Nicholas: any thoughts on this patch?

No objections from me with the WARN_ONCE change suggested by Michel.

Alex

RE: [PATCH 00/24] DC Patches Sep 24, 2021

[Wheeler, Daniel]

[Public]

Hi all,
 
This week this patchset was tested on the following systems:
 
HP Envy 360, with Ryzen 5 4500U, with the following display types: eDP 1080p 
60hz, 4k 60hz  (via USB-C to DP/HDMI), 1440p 144hz (via USB-C to DP/HDMI), 
1680*1050 60hz (via USB-C to DP and then DP to DVI/VGA)
 
AMD Ryzen 9 5900H, with the following display types: eDP 1080p 60hz, 4k 60hz  
(via USB-C to DP/HDMI), 1440p 144hz (via USB-C to DP/HDMI), 1680*1050 60hz (via 
USB-C to DP and then DP to DVI/VGA)
 
Sapphire Pulse RX5700XT with the following display types:
4k 60hz  (via DP/HDMI), 1440p 144hz (via DP/HDMI), 1680*1050 60hz (via DP to 
DVI/VGA)
 
Reference AMD RX6800 with the following display types:
4k 60hz  (via DP/HDMI and USB-C to DP/HDMI), 1440p 144hz (via USB-C to DP/HDMI 
and USB-C to DP/HDMI), 1680*1050 60hz (via DP to DVI/VGA)
 
Included testing using a Startech DP 1.4 MST hub at 2x 4k 60hz, and 3x 1080p 
60hz on all systems.
 
 
Tested-by: Daniel Wheeler 
 
 
Thank you,
 
Dan Wheeler
Technologist  |  AMD
SW Display
--
1 Commerce Valley Dr E, Thornhill, ON L3T 7X6
Facebook |  Twitter |  amd.com  


-Original Message-
From: amd-gfx  On Behalf Of Anson Jacob
Sent: September 24, 2021 3:09 PM
To: amd-gfx@lists.freedesktop.org
Cc: Wentland, Harry ; Li, Sun peng (Leo) 
; Lakha, Bhawanpreet ; Siqueira, 
Rodrigo ; Pillai, Aurabindo 
; Zhuo, Qingqing ; Lipski, 
Mikita ; Li, Roman ; Jacob, Anson 
; Lin, Wayne ; Wang, Chao-kai (Stylon) 
; Chiu, Solomon 
Subject: [PATCH 00/24] DC Patches Sep 24, 2021

This DC patchset brings improvements in multiple areas. In summary, we
have:
- Fixes to backlight, LUT, PPS, MST
- Use correct vpg for 128b/132b encoding
- Improved logging for VCP
- Replace referral of dal with dc

Anthony Koo (2):
  drm/amd/display: [FW Promotion] Release 0.0.85
  drm/amd/display: [FW Promotion] Release 0.0.86

Aric Cyr (1):
  drm/amd/display: 3.2.155

Charlene Liu (1):
  drm/amd/display: Pass PCI deviceid into DC

David Galiffi (1):
  drm/amd/display: Add debug support to override the Minimum DRAM Clock

Eric Yang (1):
  drm/amd/display: add vsync notify to dmub for abm pause

George Shen (2):
  drm/amd/display: Handle Y carry-over in VCP X.Y calculation
  drm/amd/display: Update VCP X.Y logging to improve usefulness

Ilya (1):
  drm/amd/display: Add PPS immediate update flag for DCN2

Jimmy Kizito (1):
  drm/amd/display: Fix MST link encoder availability check.

Josip Pavic (1):
  drm/amd/display: initialize backlight_ramping_override to false

Meenakshikumar Somasundaram (1):
  drm/amd/display: Fix for link encoder access for MST.

Michael Strauss (2):
  drm/amd/display: Don't enable AFMT for DP audio stream
  drm/amd/display: Defer LUT memory powerdown until LUT bypass latches

Oliver Logush (1):
  drm/amd/display: Add an extra check for dcn10 OPTC data format

Qingqing Zhuo (1):
  drm/amd/display: Replace referral of dal with dc

Wenjing Liu (8):
  drm/amd/display: use correct vpg instance for 128b/132b encoding
  drm/amd/display: update cur_lane_setting to an array one for each lane
  drm/amd/display: add function to convert hw to dpcd lane settings
  drm/amd/display: implement decide lane settings
  drm/amd/display: rename lane_settings to hw_lane_settings
  drm/amd/display: decouple hw_lane_settings from dpcd_lane_settings
  drm/amd/display: add two lane settings training options
  drm/amd/display: make verified link cap not exceeding max link cap

 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |   2 +
 .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c |  14 +-
 .../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c  |   2 +-
 .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c |   2 +-
 drivers/gpu/drm/amd/display/dc/core/dc.c  |  73 +++
 drivers/gpu/drm/amd/display/dc/core/dc_link.c |  73 ++-  
.../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 591 +++---  
.../drm/amd/display/dc/core/dc_link_enc_cfg.c |  23 +-
 .../drm/amd/display/dc/core/dc_link_hwss.c|   5 +-
 drivers/gpu/drm/amd/display/dc/dc.h   |   5 +-
 drivers/gpu/drm/amd/display/dc/dc_dp_types.h  |   5 -
 drivers/gpu/drm/amd/display/dc/dc_link.h  |   2 +-
 .../drm/amd/display/dc/dce/dce_link_encoder.c |   6 +-
 drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c |  21 +
 .../gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h  |   6 -
 .../amd/display/dc/dcn10/dcn10_link_encoder.c |   6 +-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_optc.c |   2 +-
 .../display/dc/dcn10/dcn10_stream_encoder.c   |  11 +-
 .../gpu/drm/amd/display/dc/dcn20/dcn20_optc.c |   5 +
 .../drm/amd/display/dc/dcn20/dcn20_resource.c |   4 +
 .../display/dc/dcn20/dcn20_stream_encoder.c   |   9 +-
 .../dc/dcn30/dcn30_dio_stream_encoder.c   |   2 -
 .../gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c  |  59 +-
 .../drm/amd/display/dc/dcn31/dcn31_resource.c |   2 +-
 .../gpu/drm/amd/display/dc/inc/dc_link_dp.h   |  21 +-
 

Re: [PATCH] amdgpu: check tiling flags when creating FB on GFX8-

[Simon Ser]

Alex, Harry, Nicholas: any thoughts on this patch?

Re: [PATCH] drm/amdgpu: fix warning for overflow check

[Christian König]

Am 27.09.21 um 14:58 schrieb Arnd Bergmann:

From: Arnd Bergmann 

The overflow check in amdgpu_bo_list_create() causes a warning with
clang-14 on 64-bit architectures, since the limit can never be
exceeded.

drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c:74:18: error: result of comparison 
of constant 256204778801521549 with expression of type 'unsigned int' is always 
false [-Werror,-Wtautological-constant-out-of-range-compare]
 if (num_entries > (SIZE_MAX - sizeof(struct amdgpu_bo_list))
 ~~~ ^ ~~

The check remains useful for 32-bit architectures, so just avoid the
warning by using size_t as the type for the count.

Fixes: 920990cb080a ("drm/amdgpu: allocate the bo_list array after the list")
Signed-off-by: Arnd Bergmann 


Reviewed-by: Christian König 


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c | 2 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h | 2 +-
  2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
index 15c45b2a3983..714178f1b6c6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
@@ -61,7 +61,7 @@ static void amdgpu_bo_list_free(struct kref *ref)
  
  int amdgpu_bo_list_create(struct amdgpu_device *adev, struct drm_file *filp,

  struct drm_amdgpu_bo_list_entry *info,
- unsigned num_entries, struct amdgpu_bo_list **result)
+ size_t num_entries, struct amdgpu_bo_list **result)
  {
unsigned last_entry = 0, first_userptr = num_entries;
struct amdgpu_bo_list_entry *array;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h
index c905a4cfc173..044b41f0bfd9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h
@@ -61,7 +61,7 @@ int amdgpu_bo_create_list_entry_array(struct 
drm_amdgpu_bo_list_in *in,
  int amdgpu_bo_list_create(struct amdgpu_device *adev,
 struct drm_file *filp,
 struct drm_amdgpu_bo_list_entry *info,
-unsigned num_entries,
+size_t num_entries,
 struct amdgpu_bo_list **list);
  
  static inline struct amdgpu_bo_list_entry *

[PATCH] drm/amd/amdgpu: Add missing mp_11_0_8_sh_mask.h header

[Tom St Denis]

The commit 9b716ef1501b2e62181073493dc1c7a17140bd21 added the offset
header but didn't add the masks.  This adds the masks based on what
was selected for the offsets.

Signed-off-by: Tom St Denis 
---
 .../include/asic_reg/mp/mp_11_0_8_sh_mask.h   | 355 ++
 1 file changed, 355 insertions(+)
 create mode 100644 drivers/gpu/drm/amd/include/asic_reg/mp/mp_11_0_8_sh_mask.h

diff --git a/drivers/gpu/drm/amd/include/asic_reg/mp/mp_11_0_8_sh_mask.h 
b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_11_0_8_sh_mask.h
new file mode 100644
index ..b7d3d0df3260
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_11_0_8_sh_mask.h
@@ -0,0 +1,355 @@
+/*
+ * Copyright (C) 2021  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 
LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _mp_11_0_8_SH_MASK_HEADER
+#define _mp_11_0_8_SH_MASK_HEADER
+
+#define MP0_SMN_C2PMSG_100__CONTENT_MASK   
   0xL
+#define MP0_SMN_C2PMSG_100__CONTENT__SHIFT 
   0x0
+#define MP0_SMN_C2PMSG_101__CONTENT_MASK   
   0xL
+#define MP0_SMN_C2PMSG_101__CONTENT__SHIFT 
   0x0
+#define MP0_SMN_C2PMSG_102__CONTENT_MASK   
   0xL
+#define MP0_SMN_C2PMSG_102__CONTENT__SHIFT 
   0x0
+#define MP0_SMN_C2PMSG_103__CONTENT_MASK   
   0xL
+#define MP0_SMN_C2PMSG_103__CONTENT__SHIFT 
   0x0
+#define MP0_SMN_C2PMSG_32__CONTENT_MASK
   0xL
+#define MP0_SMN_C2PMSG_32__CONTENT__SHIFT  
   0x0
+#define MP0_SMN_C2PMSG_33__CONTENT_MASK
   0xL
+#define MP0_SMN_C2PMSG_33__CONTENT__SHIFT  
   0x0
+#define MP0_SMN_C2PMSG_34__CONTENT_MASK
   0xL
+#define MP0_SMN_C2PMSG_34__CONTENT__SHIFT  
   0x0
+#define MP0_SMN_C2PMSG_35__CONTENT_MASK
   0xL
+#define MP0_SMN_C2PMSG_35__CONTENT__SHIFT  
   0x0
+#define MP0_SMN_C2PMSG_36__CONTENT_MASK
   0xL
+#define MP0_SMN_C2PMSG_36__CONTENT__SHIFT  
   0x0
+#define MP0_SMN_C2PMSG_37__CONTENT_MASK
   0xL
+#define MP0_SMN_C2PMSG_37__CONTENT__SHIFT  
   0x0
+#define MP0_SMN_C2PMSG_38__CONTENT_MASK
   0xL
+#define MP0_SMN_C2PMSG_38__CONTENT__SHIFT  
   0x0
+#define MP0_SMN_C2PMSG_39__CONTENT_MASK
   0xL
+#define MP0_SMN_C2PMSG_39__CONTENT__SHIFT  
   0x0
+#define MP0_SMN_C2PMSG_40__CONTENT_MASK
   0xL
+#define MP0_SMN_C2PMSG_40__CONTENT__SHIFT  
 

[PATCH] drm/amdgpu: fix warning for overflow check

[Arnd Bergmann]

From: Arnd Bergmann 

The overflow check in amdgpu_bo_list_create() causes a warning with
clang-14 on 64-bit architectures, since the limit can never be
exceeded.

drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c:74:18: error: result of comparison 
of constant 256204778801521549 with expression of type 'unsigned int' is always 
false [-Werror,-Wtautological-constant-out-of-range-compare]
if (num_entries > (SIZE_MAX - sizeof(struct amdgpu_bo_list))
~~~ ^ ~~

The check remains useful for 32-bit architectures, so just avoid the
warning by using size_t as the type for the count.

Fixes: 920990cb080a ("drm/amdgpu: allocate the bo_list array after the list")
Signed-off-by: Arnd Bergmann 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c | 2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
index 15c45b2a3983..714178f1b6c6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
@@ -61,7 +61,7 @@ static void amdgpu_bo_list_free(struct kref *ref)
 
 int amdgpu_bo_list_create(struct amdgpu_device *adev, struct drm_file *filp,
  struct drm_amdgpu_bo_list_entry *info,
- unsigned num_entries, struct amdgpu_bo_list **result)
+ size_t num_entries, struct amdgpu_bo_list **result)
 {
unsigned last_entry = 0, first_userptr = num_entries;
struct amdgpu_bo_list_entry *array;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h
index c905a4cfc173..044b41f0bfd9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h
@@ -61,7 +61,7 @@ int amdgpu_bo_create_list_entry_array(struct 
drm_amdgpu_bo_list_in *in,
 int amdgpu_bo_list_create(struct amdgpu_device *adev,
 struct drm_file *filp,
 struct drm_amdgpu_bo_list_entry *info,
-unsigned num_entries,
+size_t num_entries,
 struct amdgpu_bo_list **list);
 
 static inline struct amdgpu_bo_list_entry *
-- 
2.29.2

Re: [PATCH] drm/amdgpu: fix clang out-of-range warning

[Christian König]

In general that change looks good. But what configuration is that?

Background is that it doesn't make much sense to compile the amdgpu 
driver on systems where resource_size_t is only 32bit.


Christian.

Am 27.09.21 um 14:19 schrieb Arnd Bergmann:

From: Arnd Bergmann 

clang-14 points out that comparing an 'unsigned int' against a large
64-bit constantn is pointless:

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1206:18: error: result of comparison 
of constant 4294967296 with expression of type 'resource_size_t' (aka 'unsigned 
int') is always false [-Werror,-Wtautological-constant-out-of-range-compare]
 res->start > 0x1ull)

Rephrase the comparison using the upper_32_bits() macro, which should
keep it legible while avoiding the warning.

Fixes: 31b8adab3247 ("drm/amdgpu: require a root bus window above 4GB for BAR 
resize")
Signed-off-by: Arnd Bergmann 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index ab3794c42d36..741a55031ca1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1203,7 +1203,7 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device 
*adev)
  
  	pci_bus_for_each_resource(root, res, i) {

if (res && res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) &&
-   res->start > 0x1ull)
+   upper_32_bits(res->start) != 0)
break;
}
  

[PATCH] gpu: amd: replace open-coded offsetof() with builtin

[Arnd Bergmann]

From: Arnd Bergmann 

The two AMD drivers have their own custom offsetof() implementation
that now triggers a warning with recent versions of clang:

drivers/gpu/drm/radeon/radeon_atombios.c:133:14: error: performing pointer 
subtraction with a null pointer has undefined behavior 
[-Werror,-Wnull-pointer-subtraction]

Change all the instances to use the normal offsetof() provided
by the kernel that does not have this problem.

Signed-off-by: Arnd Bergmann 
---
 drivers/gpu/drm/amd/display/dc/bios/command_table2.c  | 4 +---
 drivers/gpu/drm/amd/include/atombios.h| 2 +-
 drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h | 4 ++--
 drivers/gpu/drm/radeon/atombios.h | 2 +-
 4 files changed, 5 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table2.c 
b/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
index f1f672a997d7..4f37be727332 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
@@ -44,9 +44,7 @@
bp->base.ctx->logger
 
 #define GET_INDEX_INTO_MASTER_TABLE(MasterOrData, FieldName)\
-   (((char *)(&((\
-   struct atom_master_list_of_##MasterOrData##_functions_v2_1 *)0)\
-   ->FieldName)-(char *)0)/sizeof(uint16_t))
+   (offsetof(struct atom_master_list_of_##MasterOrData##_functions_v2_1, 
FieldName) / sizeof(uint16_t))
 
 #define EXEC_BIOS_CMD_TABLE(fname, params)\
(amdgpu_atom_execute_table(((struct amdgpu_device 
*)bp->base.ctx->driver_context)->mode_info.atom_context, \
diff --git a/drivers/gpu/drm/amd/include/atombios.h 
b/drivers/gpu/drm/amd/include/atombios.h
index 6a505d1b82a5..da895d1f3b4f 100644
--- a/drivers/gpu/drm/amd/include/atombios.h
+++ b/drivers/gpu/drm/amd/include/atombios.h
@@ -7148,7 +7148,7 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3
 #define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) 
(((static_cast(TABLE_HEADER_OFFSET))->ucTableFormatRevision
 )&0x3F)
 #define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET)  
(((static_cast(TABLE_HEADER_OFFSET))->ucTableContentRevision)&0x3F)
 #else // not __cplusplus
-#define   GetIndexIntoMasterTable(MasterOrData, FieldName) 
(((char*)(&((ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*)0)->FieldName)-(char*)0)/sizeof(USHORT))
+#define   GetIndexIntoMasterTable(MasterOrData, FieldName) 
(offsetof(ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES, FieldName) / 
sizeof(USHORT))
 
 #define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) 
ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableFormatRevision)&0x3F)
 #define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET)  
ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableContentRevision)&0x3F)
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h 
b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h
index b7e2651b570b..2fc1733bcdcf 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h
@@ -29,9 +29,9 @@
 typedef enum atom_smu9_syspll0_clock_id BIOS_CLKID;
 
 #define GetIndexIntoMasterCmdTable(FieldName) \
-   (((char*)(&((struct 
atom_master_list_of_command_functions_v2_1*)0)->FieldName)-(char*)0)/sizeof(uint16_t))
+   (offsetof(struct atom_master_list_of_command_functions_v2_1, FieldName) 
/ sizeof(uint16_t))
 #define GetIndexIntoMasterDataTable(FieldName) \
-   (((char*)(&((struct 
atom_master_list_of_data_tables_v2_1*)0)->FieldName)-(char*)0)/sizeof(uint16_t))
+   (offsetof(struct atom_master_list_of_data_tables_v2_1, FieldName) / 
sizeof(uint16_t))
 
 #define PP_ATOMFWCTRL_MAX_VOLTAGE_ENTRIES 32
 
diff --git a/drivers/gpu/drm/radeon/atombios.h 
b/drivers/gpu/drm/radeon/atombios.h
index 83e8b8547f9b..bd5dc09e860f 100644
--- a/drivers/gpu/drm/radeon/atombios.h
+++ b/drivers/gpu/drm/radeon/atombios.h
@@ -5983,7 +5983,7 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3
 #define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) 
(((static_cast(TABLE_HEADER_OFFSET))->ucTableFormatRevision
 )&0x3F)
 #define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET)  
(((static_cast(TABLE_HEADER_OFFSET))->ucTableContentRevision)&0x3F)
 #else // not __cplusplus
-#defineGetIndexIntoMasterTable(MasterOrData, FieldName) 
(((char*)(&((ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*)0)->FieldName)-(char*)0)/sizeof(USHORT))
+#defineGetIndexIntoMasterTable(MasterOrData, FieldName) 
(offsetof(ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES, 
FieldName)/sizeof(USHORT))
 
 #define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) 
ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableFormatRevision)&0x3F)
 #define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET)  
ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableContentRevision)&0x3F)
-- 
2.29.2

[PATCH] drm/amdgpu: fix clang out-of-range warning

[Arnd Bergmann]

From: Arnd Bergmann 

clang-14 points out that comparing an 'unsigned int' against a large
64-bit constantn is pointless:

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1206:18: error: result of comparison 
of constant 4294967296 with expression of type 'resource_size_t' (aka 'unsigned 
int') is always false [-Werror,-Wtautological-constant-out-of-range-compare]
res->start > 0x1ull)

Rephrase the comparison using the upper_32_bits() macro, which should
keep it legible while avoiding the warning.

Fixes: 31b8adab3247 ("drm/amdgpu: require a root bus window above 4GB for BAR 
resize")
Signed-off-by: Arnd Bergmann 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index ab3794c42d36..741a55031ca1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1203,7 +1203,7 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device 
*adev)
 
pci_bus_for_each_resource(root, res, i) {
if (res && res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) &&
-   res->start > 0x1ull)
+   upper_32_bits(res->start) != 0)
break;
}
 
-- 
2.29.2

[PATCH] [RESEND] drm/amdgpu: fix enum odm_combine_mode mismatch

[Arnd Bergmann]

From: Arnd Bergmann 

A conversion from 'bool' to 'enum odm_combine_mode' was incomplete,
and gcc warns about this with many instances of

display/dc/dml/dcn20/display_mode_vba_20.c:3899:44: warning: implicit 
conversion from 'enum ' to 'enum
odm_combine_mode' [-Wenum-conversion]
 3899 | locals->ODMCombineEnablePerState[i][k] = false;

Change the ones that we get a warning for, using the same numerical
values to leave the behavior unchanged.

Fixes: 5fc11598166d ("drm/amd/display: expand dml structs")
Link: https://lore.kernel.org/all/20201026210039.3884312-3-a...@kernel.org/
Signed-off-by: Arnd Bergmann 
---
I cannot tell if this is the correct conversion, please review
carefully.

Tested on v5.15-rc2, please just ignore if a patch is already pending
for v5.15.

I got now reply to this patch when I originally sent it. With -Werror
being the default now, it is still needed to make the driver build, please
have another look.
---
 .../amd/display/dc/dml/dcn20/display_mode_vba_20.c   |  8 
 .../amd/display/dc/dml/dcn20/display_mode_vba_20v2.c | 10 +-
 .../amd/display/dc/dml/dcn21/display_mode_vba_21.c   | 12 ++--
 3 files changed, 15 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
index f34bc3c8da41..69c41e3e3ba2 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
@@ -3901,14 +3901,14 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct 
display_mode_lib *mode_l

mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine = mode_lib->vba.PixelClock[k] 
/ 2
* (1 + 
mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
 
-   locals->ODMCombineEnablePerState[i][k] = false;
+   locals->ODMCombineEnablePerState[i][k] = 
dm_odm_combine_mode_disabled;
mode_lib->vba.PlaneRequiredDISPCLK = 
mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine;
if (mode_lib->vba.ODMCapability) {
if 
(locals->PlaneRequiredDISPCLKWithoutODMCombine > 
mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity) {
-   
locals->ODMCombineEnablePerState[i][k] = true;
+   
locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;

mode_lib->vba.PlaneRequiredDISPCLK = 
mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine;
} else if (locals->HActive[k] > 
DCN20_MAX_420_IMAGE_WIDTH && locals->OutputFormat[k] == dm_420) {
-   
locals->ODMCombineEnablePerState[i][k] = true;
+   
locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;

mode_lib->vba.PlaneRequiredDISPCLK = 
mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine;
}
}
@@ -3961,7 +3961,7 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct 
display_mode_lib *mode_l
locals->RequiredDISPCLK[i][j] = 0.0;
locals->DISPCLK_DPPCLK_Support[i][j] = true;
for (k = 0; k <= 
mode_lib->vba.NumberOfActivePlanes - 1; k++) {
-   locals->ODMCombineEnablePerState[i][k] 
= false;
+   locals->ODMCombineEnablePerState[i][k] 
= dm_odm_combine_mode_disabled;
if (locals->SwathWidthYSingleDPP[k] <= 
locals->MaximumSwathWidth[k]) {
locals->NoOfDPP[i][j][k] = 1;
locals->RequiredDPPCLK[i][j][k] 
= locals->MinDPPCLKUsingSingleDPP[k]
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
index 719949ad49ed..3c8c03496611 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
@@ -4012,17 +4012,17 @@ void 
dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode

mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine = mode_lib->vba.PixelClock[k] 
/ 2
* (1 + 
mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
 
-   locals->ODMCombineEnablePerState[i][k] = false;
+   

Re: [PATCHv3 2/2] drm/amdgpu: Register MCE notifier for Aldebaran RAS

[Borislav Petkov]

On Fri, Sep 24, 2021 at 07:46:10PM +, Yazen Ghannam wrote:
> I agree with you in general. But this device isn't really a GPU. And
> users of this device seem to want to count *every* error, at least for
> now.

Aha, so something accelerator-y where they do general purpose computation.

So what's the big picture here: they count all the errors and when they
reach a certain amount, they decide to replace the GPUs just in case?

Or wait until they become uncorrectable? But then it doesn't matter
because we will handle it properly by excluding the VRAM range from
further use.

Or do they wanna see *when* they had the correctable errors so that they
can restart the computation, just in case.

Dunno, it would be a lot helpful if we had some RAS strategy for those
things...

Thx.

-- 
Regards/Gruss,
Boris.

https://people.kernel.org/tglx/notes-about-netiquette

[PATCH] drm/amdkfd: fix resource_size.cocci warnings

[Yang Li]

Use resource_size function on resource object
instead of explicit computation.

Clean up coccicheck warning:
./drivers/gpu/drm/amd/amdkfd/kfd_migrate.c:905:10-13: ERROR: Missing
resource_size with res

Reported-by: Abaci Robot 
Signed-off-by: Yang Li 
---
 drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
index 4a16e3c..f53e17a 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
@@ -901,8 +901,7 @@ int svm_migrate_init(struct amdgpu_device *adev)
 
/* Disable SVM support capability */
pgmap->type = 0;
-   devm_release_mem_region(adev->dev, res->start,
-   res->end - res->start + 1);
+   devm_release_mem_region(adev->dev, res->start, 
resource_size(res));
return PTR_ERR(r);
}
 
-- 
1.8.3.1

RE: [PATCH] drm/amdgpu: correct initial cp_hqd_quantum for gfx9

[Ma, Le]

[AMD Official Use Only]

Reviewed-by: Le Ma 

-Original Message-
From: Hawking Zhang 
Sent: Sunday, September 26, 2021 10:29 PM
To: amd-gfx@lists.freedesktop.org; Ma, Le ; Deucher, Alexander 
; Zhang, Morris 
Cc: Zhang, Hawking 
Subject: [PATCH] drm/amdgpu: correct initial cp_hqd_quantum for gfx9

didn't read the value of mmCP_HQD_QUANTUM from correct register offset

Signed-off-by: Hawking Zhang 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 603c259..025184a5 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3599,7 +3599,7 @@ static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring)

/* set static priority for a queue/ring */
gfx_v9_0_mqd_set_priority(ring, mqd);
-   mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM);
+   mqd->cp_hqd_quantum = RREG32_SOC15(GC, 0, mmCP_HQD_QUANTUM);

/* map_queues packet doesn't need activate the queue,
 * so only kiq need set this field.
--
2.7.4