date:20211015

Re: [PATCH 16/27] drm/amd/display: increase Z9 latency to workaround underflow in Z9

2021-10-15 Thread Mike Lothian

This patch seems to change z8 - not that I know what z8 or z9 are

On Fri, 15 Oct 2021 at 19:44, Agustin Gutierrez
 wrote:
>
> From: Eric Yang 
>
> [Why]
> Z9 latency is higher than when we originally tuned the watermark
> parameters, causing underflow. Increasing the value until the latency
> issues is resolved.
>
> Reviewed-by: Nicholas Kazlauskas 
> Acked-by: Agustin Gutierrez Sanchez 
> Signed-off-by: Eric Yang 
> ---
>  drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c 
> b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
> index c9d3d691f4c6..12ebd9f8912f 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
> @@ -222,8 +222,8 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_1_soc = {
> .num_states = 5,
> .sr_exit_time_us = 9.0,
> .sr_enter_plus_exit_time_us = 11.0,
> -   .sr_exit_z8_time_us = 402.0,
> -   .sr_enter_plus_exit_z8_time_us = 520.0,
> +   .sr_exit_z8_time_us = 442.0,
> +   .sr_enter_plus_exit_z8_time_us = 560.0,
> .writeback_latency_us = 12.0,
> .dram_channel_width_bytes = 4,
> .round_trip_ping_latency_dcfclk_cycles = 106,
> --
> 2.25.1
>

[PATCH] drm/amd/display: Fully switch to dmub for all dcn21 asics

2021-10-15 Thread Roman.Li

From: Roman Li 

[Why]
On renoir usb-c port stops functioning on resume after f/w update.
New dmub firmware caused regression due to conflict with dmcu.
With new dmub f/w dmcu is superseded and should be disabled.

[How]
- Disable dmcu for all dcn21.

Check dmesg for dmub f/w version.
The old firmware (before regression):
[drm] DMUB hardware initialized: version=0x0001
All other versions require that patch for renoir.

Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1735
Cc: sta...@vger.kernel.org
Signed-off-by: Roman Li 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index ff54550..e56f73e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1356,8 +1356,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
switch (adev->ip_versions[DCE_HWIP][0]) {
case IP_VERSION(2, 1, 0):
init_data.flags.gpu_vm_support = true;
-   if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
-   init_data.flags.disable_dmcu = true;
+   init_data.flags.disable_dmcu = true;
break;
case IP_VERSION(1, 0, 0):
case IP_VERSION(1, 0, 1):
-- 
2.7.4

Re: [PATCH] drm/amdkfd: map gpu hive id to xgmi connected cpu

2021-10-15 Thread Felix Kuehling




On 2021-10-15 11:11 a.m., Jonathan Kim wrote:

ROCr needs to be able to identify all devices that have direct access to
fine grain memory, which should include CPUs that are connected to GPUs
over xGMI. The GPU hive ID can be mapped onto the CPU hive ID since the
CPU is part of the hive.

v3: avoid quadratic search by doing linear list read instead querying per
proximity id

v2: fixup to ensure all numa nodes get the hive id mapped

Signed-off-by: Jonathan Kim 


Reviewed-by: Felix Kuehling 



---
  drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 19 ++-
  1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
index 98cca5f2b27f..dd593ad0614a 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
@@ -1296,6 +1296,24 @@ int kfd_topology_add_device(struct kfd_dev *gpu)
  
  	proximity_domain = atomic_inc_return(_crat_proximity_domain);
  
+	adev = (struct amdgpu_device *)(gpu->kgd);

+
+   /* Include the CPU in xGMI hive if xGMI connected by assigning it the 
hive ID. */
+   if (gpu->hive_id && adev->gmc.xgmi.connected_to_cpu) {
+   struct kfd_topology_device *top_dev;
+
+   down_read(_lock);
+
+   list_for_each_entry(top_dev, _device_list, list) {
+   if (top_dev->gpu)
+   break;
+
+   top_dev->node_props.hive_id = gpu->hive_id;
+   }
+
+   up_read(_lock);
+   }
+
/* Check to see if this gpu device exists in the topology_device_list.
 * If so, assign the gpu to that device,
 * else create a Virtual CRAT for this gpu device and then parse that
@@ -1457,7 +1475,6 @@ int kfd_topology_add_device(struct kfd_dev *gpu)
dev->node_props.max_waves_per_simd = 10;
}
  
-	adev = (struct amdgpu_device *)(dev->gpu->kgd);

/* kfd only concerns sram ecc on GFX and HBM ecc on UMC */
dev->node_props.capability |=
((adev->ras_enabled & BIT(AMDGPU_RAS_BLOCK__GFX)) != 0) ?

Re: [Intel-gfx] [PATCH 01/15] gpu/drm: make drm_add_edid_modes() consistent when updating connector->display_info

2021-10-15 Thread Ville Syrjälä

On Fri, Oct 15, 2021 at 10:33:29PM +0300, Ville Syrjälä wrote:
> On Fri, Oct 15, 2021 at 09:24:06PM +0200, Claudio Suarez wrote:
> > On Fri, Oct 15, 2021 at 03:03:13PM +0300, Ville Syrjälä wrote:
> > > On Fri, Oct 15, 2021 at 01:36:59PM +0200, Claudio Suarez wrote:
> > > > According to the documentation, drm_add_edid_modes
> > > > "... Also fills out the _display_info structure and ELD in 
> > > > @connector
> > > > with any information which can be derived from the edid."
> > > > 
> > > > drm_add_edid_modes accepts a struct edid *edid parameter which may have 
> > > > a
> > > > value or may be null. When it is not null, connector->display_info and
> > > > connector->eld are updated according to the edid. When edid=NULL, only
> > > > connector->eld is reset. Reset connector->display_info to be consistent
> > > > and accurate.
> > > > 
> > > > Signed-off-by: Claudio Suarez 
> > > > ---
> > > >  drivers/gpu/drm/drm_edid.c | 2 ++
> > > >  1 file changed, 2 insertions(+)
> > > > 
> > > > diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> > > > index 6325877c5fd6..6cbe09b2357c 100644
> > > > --- a/drivers/gpu/drm/drm_edid.c
> > > > +++ b/drivers/gpu/drm/drm_edid.c
> > > > @@ -5358,10 +5358,12 @@ int drm_add_edid_modes(struct drm_connector 
> > > > *connector, struct edid *edid)
> > > >  
> > > > if (edid == NULL) {
> > > > clear_eld(connector);
> > > > +   drm_reset_display_info(connector);
> > > > return 0;
> > > > }
> > > > if (!drm_edid_is_valid(edid)) {
> > > > clear_eld(connector);
> > > > +   drm_reset_display_info(connector);
> > > 
> > > Looks easier if you pull both of those out from these branches and
> > > just call them unconditionally at the start.
> > 
> > After looking at the full code, I am not sure. This is the code:
> > ==
> > int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
> > {
> > int num_modes = 0;
> > u32 quirks;
> > 
> > if (edid == NULL) {
> > clear_eld(connector);
> > drm_reset_display_info(connector); <--- added by me
> > return 0;
> > }
> > if (!drm_edid_is_valid(edid)) {
> > clear_eld(connector);
> > drm_reset_display_info(connector); <--- added by me
> > drm_warn(connector->dev, "%s: EDID invalid.\n",
> >  connector->name);
> > return 0;
> > }
> > 
> > drm_edid_to_eld(connector, edid);
> > 
> > quirks = drm_add_display_info(connector, edid);
> > etc...
> > =
> > 
> > If we move those out of these branches and edid != NULL, we are executing an
> > unnecessary clear_eld(connector) and an unnecessary 
> > drm_reset_display_info(connector)
> > because the fields will be set in the next drm_edid_to_eld(connector, edid) 
> > and
> > drm_add_display_info(connector, edid)
> > 
> > Do we want this ?
> 
> Seems fine by me. And maybe we could nuke the second
> drm_reset_display_info() from deeper inside drm_add_display_info()?
> Not sure if drm_add_display_info() still has to be able to operate
> standalone or not.
> 
> Hmm. Another option is to just move all these NULL/invalid edid
> checks into drm_edid_to_eld() and drm_add_display_info().

But maybe that's not so easy. Would still need to bail out
from drm_add_edid_modes() I guess.

-- 
Ville Syrjälä
Intel

Re: [PATCH 01/15] gpu/drm: make drm_add_edid_modes() consistent when updating connector->display_info

2021-10-15 Thread Ville Syrjälä

On Fri, Oct 15, 2021 at 09:24:06PM +0200, Claudio Suarez wrote:
> On Fri, Oct 15, 2021 at 03:03:13PM +0300, Ville Syrjälä wrote:
> > On Fri, Oct 15, 2021 at 01:36:59PM +0200, Claudio Suarez wrote:
> > > According to the documentation, drm_add_edid_modes
> > > "... Also fills out the _display_info structure and ELD in @connector
> > > with any information which can be derived from the edid."
> > > 
> > > drm_add_edid_modes accepts a struct edid *edid parameter which may have a
> > > value or may be null. When it is not null, connector->display_info and
> > > connector->eld are updated according to the edid. When edid=NULL, only
> > > connector->eld is reset. Reset connector->display_info to be consistent
> > > and accurate.
> > > 
> > > Signed-off-by: Claudio Suarez 
> > > ---
> > >  drivers/gpu/drm/drm_edid.c | 2 ++
> > >  1 file changed, 2 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> > > index 6325877c5fd6..6cbe09b2357c 100644
> > > --- a/drivers/gpu/drm/drm_edid.c
> > > +++ b/drivers/gpu/drm/drm_edid.c
> > > @@ -5358,10 +5358,12 @@ int drm_add_edid_modes(struct drm_connector 
> > > *connector, struct edid *edid)
> > >  
> > >   if (edid == NULL) {
> > >   clear_eld(connector);
> > > + drm_reset_display_info(connector);
> > >   return 0;
> > >   }
> > >   if (!drm_edid_is_valid(edid)) {
> > >   clear_eld(connector);
> > > + drm_reset_display_info(connector);
> > 
> > Looks easier if you pull both of those out from these branches and
> > just call them unconditionally at the start.
> 
> After looking at the full code, I am not sure. This is the code:
> ==
> int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
> {
> int num_modes = 0;
> u32 quirks;
> 
> if (edid == NULL) {
> clear_eld(connector);
> drm_reset_display_info(connector); <--- added by me
> return 0;
> }
> if (!drm_edid_is_valid(edid)) {
> clear_eld(connector);
> drm_reset_display_info(connector); <--- added by me
> drm_warn(connector->dev, "%s: EDID invalid.\n",
>  connector->name);
> return 0;
> }
> 
> drm_edid_to_eld(connector, edid);
> 
> quirks = drm_add_display_info(connector, edid);
>   etc...
> =
> 
> If we move those out of these branches and edid != NULL, we are executing an
> unnecessary clear_eld(connector) and an unnecessary 
> drm_reset_display_info(connector)
> because the fields will be set in the next drm_edid_to_eld(connector, edid) 
> and
> drm_add_display_info(connector, edid)
> 
> Do we want this ?

Seems fine by me. And maybe we could nuke the second
drm_reset_display_info() from deeper inside drm_add_display_info()?
Not sure if drm_add_display_info() still has to be able to operate
standalone or not.

Hmm. Another option is to just move all these NULL/invalid edid
checks into drm_edid_to_eld() and drm_add_display_info().

-- 
Ville Syrjälä
Intel

Re: [PATCH 01/15] gpu/drm: make drm_add_edid_modes() consistent when updating connector->display_info

2021-10-15 Thread Claudio Suarez

On Fri, Oct 15, 2021 at 03:03:13PM +0300, Ville Syrjälä wrote:
> On Fri, Oct 15, 2021 at 01:36:59PM +0200, Claudio Suarez wrote:
> > According to the documentation, drm_add_edid_modes
> > "... Also fills out the _display_info structure and ELD in @connector
> > with any information which can be derived from the edid."
> > 
> > drm_add_edid_modes accepts a struct edid *edid parameter which may have a
> > value or may be null. When it is not null, connector->display_info and
> > connector->eld are updated according to the edid. When edid=NULL, only
> > connector->eld is reset. Reset connector->display_info to be consistent
> > and accurate.
> > 
> > Signed-off-by: Claudio Suarez 
> > ---
> >  drivers/gpu/drm/drm_edid.c | 2 ++
> >  1 file changed, 2 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> > index 6325877c5fd6..6cbe09b2357c 100644
> > --- a/drivers/gpu/drm/drm_edid.c
> > +++ b/drivers/gpu/drm/drm_edid.c
> > @@ -5358,10 +5358,12 @@ int drm_add_edid_modes(struct drm_connector 
> > *connector, struct edid *edid)
> >  
> > if (edid == NULL) {
> > clear_eld(connector);
> > +   drm_reset_display_info(connector);
> > return 0;
> > }
> > if (!drm_edid_is_valid(edid)) {
> > clear_eld(connector);
> > +   drm_reset_display_info(connector);
> 
> Looks easier if you pull both of those out from these branches and
> just call them unconditionally at the start.

After looking at the full code, I am not sure. This is the code:
==
int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
{
int num_modes = 0;
u32 quirks;

if (edid == NULL) {
clear_eld(connector);
drm_reset_display_info(connector); <--- added by me
return 0;
}
if (!drm_edid_is_valid(edid)) {
clear_eld(connector);
drm_reset_display_info(connector); <--- added by me
drm_warn(connector->dev, "%s: EDID invalid.\n",
 connector->name);
return 0;
}

drm_edid_to_eld(connector, edid);

quirks = drm_add_display_info(connector, edid);
etc...
=

If we move those out of these branches and edid != NULL, we are executing an
unnecessary clear_eld(connector) and an unnecessary 
drm_reset_display_info(connector)
because the fields will be set in the next drm_edid_to_eld(connector, edid) and
drm_add_display_info(connector, edid)

Do we want this ?

BR
Claudio Suarez

Re: [Intel-gfx] [PATCH 15/15] drm/i915: replace drm_detect_hdmi_monitor() with drm_display_info.is_hdmi

2021-10-15 Thread Claudio Suarez

On Fri, Oct 15, 2021 at 06:18:34PM +0300, Jani Nikula wrote:
> On Fri, 15 Oct 2021, Ville Syrjälä  wrote:
> > On Fri, Oct 15, 2021 at 03:44:48PM +0300, Jani Nikula wrote:
> >> On Fri, 15 Oct 2021, Claudio Suarez  wrote:
> >> > Once EDID is parsed, the monitor HDMI support information is available
> >> > through drm_display_info.is_hdmi. Retriving the same information with
> >> > drm_detect_hdmi_monitor() is less efficient. Change to
> >> > drm_display_info.is_hdmi where possible.
> >> >
> >> > This is a TODO task in Documentation/gpu/todo.rst
> >> >
> >> > Signed-off-by: Claudio Suarez 
> >> > ---
> >> >  drivers/gpu/drm/i915/display/intel_connector.c | 5 +
> >> >  drivers/gpu/drm/i915/display/intel_connector.h | 1 +
> >> >  drivers/gpu/drm/i915/display/intel_hdmi.c  | 2 +-
> >> >  drivers/gpu/drm/i915/display/intel_sdvo.c  | 3 ++-
> >> >  4 files changed, 9 insertions(+), 2 deletions(-)
> >> >
> >> > diff --git a/drivers/gpu/drm/i915/display/intel_connector.c 
> >> > b/drivers/gpu/drm/i915/display/intel_connector.c
> >> > index 9bed1ccecea0..3346b55df6e1 100644
> >> > --- a/drivers/gpu/drm/i915/display/intel_connector.c
> >> > +++ b/drivers/gpu/drm/i915/display/intel_connector.c
> >> > @@ -213,6 +213,11 @@ int intel_ddc_get_modes(struct drm_connector 
> >> > *connector,
> >> >  return ret;
> >> >  }
> >> >  
> >> > +bool intel_connector_is_hdmi_monitor(struct drm_connector *connector)
> >> > +{
> >> > +return connector->display_info.is_hdmi;
> >> > +}
> >> > +
> >> 
> >> A helper like this belongs in drm, not i915. Seems useful in other
> >> drivers too.
> >
> > Not sure it's actually helpful for i915. We end up having to root around
> > in the display_info in a lot of places anyway. So a helper for single
> > boolean seems a bit out of place perhaps.
> 
> *shrug*
> 
> Maybe it's just my frustration at the lack of interfaces and poking
> around in the depths of nested structs and pointer chasing that's coming
> through. You just need to change so many things if you want to later
> refactor where "is hdmi" comes from and is stored.
> 
> Anyway, if a helper is being added like in this series, I think it
> should be one helper in drm, not redundant copies in multiple
> drivers. Or we should not have the helper(s) at all. One or the other,
> not the worst of both worlds.

Thank you all for your comments :)
The big work here was to figure out which drm_detect_hdmi_monitor() can be
replaced. Changing a helper isn't a problem.
I'll send a new patch in a few hours.

BR
Claudio Suarez.

[PATCH 22/27] drm/amd/display: Change initializer to single brace

2021-10-15 Thread Agustin Gutierrez

From: Anthony Koo 

Acked-by: Agustin Gutierrez Sanchez 
Signed-off-by: Aric Cyr 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c |  7 ++---
 .../gpu/drm/amd/display/dc/core/dc_link_ddc.c |  2 +-
 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 30 +--
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c |  8 ++---
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.c|  4 +--
 5 files changed, 25 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index d54592b573e9..6db611f9f554 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -674,13 +674,13 @@ static void query_hdcp_capability(enum signal_type 
signal, struct dc_link *link)
 
 static void read_current_link_settings_on_detect(struct dc_link *link)
 {
-   union lane_count_set lane_count_set = { {0} };
+   union lane_count_set lane_count_set = {0};
uint8_t link_bw_set;
uint8_t link_rate_set;
uint32_t read_dpcd_retry_cnt = 10;
enum dc_status status = DC_ERROR_UNEXPECTED;
int i;
-   union max_down_spread max_down_spread = { {0} };
+   union max_down_spread max_down_spread = {0};
 
// Read DPCD 00101h to find out the number of lanes currently set
for (i = 0; i < read_dpcd_retry_cnt; i++) {
@@ -3279,8 +3279,7 @@ static void update_mst_stream_alloc_table(
struct stream_encoder *stream_enc,
const struct dp_mst_stream_allocation_table *proposed_table)
 {
-   struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = {
-   { 0 } };
+   struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = { 0 
};
struct link_mst_stream_allocation *dc_alloc;
 
int i;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
index b0f1cd7268c8..471a67a64299 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
@@ -763,7 +763,7 @@ void dal_ddc_service_read_scdc_data(struct ddc_service 
*ddc_service)
dal_ddc_service_query_ddc_data(ddc_service, slave_address, ,
sizeof(offset), _config, sizeof(tmds_config));
if (tmds_config & 0x1) {
-   union hdmi_scdc_status_flags_data status_data = { {0} };
+   union hdmi_scdc_status_flags_data status_data = {0};
uint8_t scramble_status = 0;
 
offset = HDMI_SCDC_SCRAMBLER_STATUS;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 8e0b40c7a1ee..296b0defcd1c 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -259,7 +259,7 @@ static void dpcd_set_training_pattern(
struct dc_link *link,
enum dc_dp_training_pattern training_pattern)
 {
-   union dpcd_training_pattern dpcd_pattern = { {0} };
+   union dpcd_training_pattern dpcd_pattern = {0};
 
dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
dc_dp_training_pattern_to_dpcd_training_pattern(
@@ -401,8 +401,8 @@ enum dc_status dpcd_set_link_settings(
uint8_t rate;
enum dc_status status;
 
-   union down_spread_ctrl downspread = { {0} };
-   union lane_count_set lane_count_set = { {0} };
+   union down_spread_ctrl downspread = {0};
+   union lane_count_set lane_count_set = {0};
 
downspread.raw = (uint8_t)
(lt_settings->link_settings.link_spread);
@@ -520,7 +520,7 @@ static void dpcd_set_lt_pattern_and_lane_settings(
uint32_t dpcd_base_lt_offset;
 
uint8_t dpcd_lt_buffer[5] = {0};
-   union dpcd_training_pattern dpcd_pattern = { {0} };
+   union dpcd_training_pattern dpcd_pattern = { 0 };
uint32_t size_in_bytes;
bool edp_workaround = false; /* TODO link_prop.INTERNAL */
dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET;
@@ -1266,8 +1266,8 @@ static enum link_training_result 
perform_channel_equalization_sequence(
uint32_t retries_ch_eq;
uint32_t wait_time_microsec;
enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
-   union lane_align_status_updated dpcd_lane_status_updated = { {0} };
-   union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } };
+   union lane_align_status_updated dpcd_lane_status_updated = {0};
+   union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0};
 
/* Note: also check that TPS4 is a supported feature*/
 
@@ -1487,7 +1487,7 @@ static inline enum link_training_result 
dp_transition_to_video_idle(
struct link_training_settings *lt_settings,
enum link_training_result status)
 {
-   union lane_count_set lane_count_set = { {0} };
+   union lane_count_set lane_count_set = {0};
 
/*

[PATCH 23/27] drm/amd/display: 3.2.157

2021-10-15 Thread Agustin Gutierrez

From: Aric Cyr 

This DC patchset brings improvements in multiple areas. In summary, we
highlight:

* Fix some issues such as DP2 problem, prefetch bandwidth calculation
for DCN3.1 and others.
* Increased Z9 latency and removed z10 save after dsc disable.
* Revert a couple of bad changes.
* Added missing PSR state patch.

Acked-by: Agustin Gutierrez Sanchez 
Signed-off-by: Aric Cyr 
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 254b760ae91f..fc3f0fd1f068 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -47,7 +47,7 @@ struct aux_payload;
 struct set_config_cmd_payload;
 struct dmub_notification;
 
-#define DC_VER "3.2.156"
+#define DC_VER "3.2.157"
 
 #define MAX_SURFACES 3
 #define MAX_PLANES 6
-- 
2.25.1

[PATCH 27/27] Revert "drm/amd/display: Add helper for blanking all dp displays"

2021-10-15 Thread Agustin Gutierrez

This reverts commit 50ac5b14c74c5706796cb6378f25a2121dba5b2d.

This patch introduced a couple of dmesg warnings, this is not a valid
approach anymore. For this reason, we are reverting this patch, and we
need to revert the workaround patch.

Cc: Hanghong Ma 
Cc: Mark Broadworth 
Signed-off-by: Agustin Gutierrez 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 45 ---
 drivers/gpu/drm/amd/display/dc/dc_link.h  |  1 -
 .../display/dc/dce110/dce110_hw_sequencer.c   | 24 --
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 41 +++--
 .../drm/amd/display/dc/dcn30/dcn30_hwseq.c| 39 ++--
 .../drm/amd/display/dc/dcn31/dcn31_hwseq.c| 40 +++--
 6 files changed, 131 insertions(+), 59 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index c01309a1cbf2..e5d6cbd7ea78 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1988,51 +1988,6 @@ static enum dc_status enable_link_dp_mst(
return enable_link_dp(state, pipe_ctx);
 }
 
-void blank_all_dp_displays(struct dc *dc, bool hw_init)
-{
-   unsigned int i, j, fe;
-   uint8_t dpcd_power_state = '\0';
-   enum dc_status status = DC_ERROR_UNEXPECTED;
-
-   for (i = 0; i < dc->link_count; i++) {
-   enum signal_type signal = dc->links[i]->connector_signal;
-
-   if ((signal == SIGNAL_TYPE_EDP) ||
-   (signal == SIGNAL_TYPE_DISPLAY_PORT)) {
-   if (hw_init && signal != SIGNAL_TYPE_EDP) {
-   /* DP 2.0 spec requires that we read LTTPR caps 
first */
-   dp_retrieve_lttpr_cap(dc->links[i]);
-   /* if any of the displays are lit up turn them 
off */
-   status = core_link_read_dpcd(dc->links[i], 
DP_SET_POWER,
-   _power_state, 
sizeof(dpcd_power_state));
-   }
-
-   if ((signal != SIGNAL_TYPE_EDP && status == DC_OK && 
dpcd_power_state == DP_POWER_STATE_D0) ||
-   (!hw_init && dc->links[i]->link_enc &&
-   
dc->links[i]->link_enc->funcs->is_dig_enabled(dc->links[i]->link_enc))) {
-   if 
(dc->links[i]->link_enc->funcs->get_dig_frontend) {
-   fe = 
dc->links[i]->link_enc->funcs->get_dig_frontend(dc->links[i]->link_enc);
-   if (fe == ENGINE_ID_UNKNOWN)
-   continue;
-
-   for (j = 0; j < 
dc->res_pool->stream_enc_count; j++) {
-   if (fe == 
dc->res_pool->stream_enc[j]->id) {
-   
dc->res_pool->stream_enc[j]->funcs->dp_blank(dc->links[i],
-   
dc->res_pool->stream_enc[j]);
-   break;
-   }
-   }
-   }
-
-   if 
(!dc->links[i]->wa_flags.dp_keep_receiver_powered ||
-   (hw_init && signal != SIGNAL_TYPE_EDP))
-   dp_receiver_power_ctrl(dc->links[i], 
false);
-   }
-   }
-   }
-
-}
-
 static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx,
enum engine_id eng_id,
struct ext_hdmi_settings *settings)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h 
b/drivers/gpu/drm/amd/display/dc/dc_link.h
index 69b008bafbbc..a73d64b1fd33 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_link.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
@@ -277,7 +277,6 @@ bool dc_link_setup_psr(struct dc_link *dc_link,
struct psr_context *psr_context);
 
 void dc_link_get_psr_residency(const struct dc_link *link, uint32_t 
*residency);
-void blank_all_dp_displays(struct dc *dc, bool hw_init);
 
 /* Request DC to detect if there is a Panel connected.
  * boot - If this call is during initial boot.
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 8108f9ae2638..af3e68d3e747 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1649,13 +1649,31 @@ static enum dc_status apply_single_controller_ctx_to_hw(
 
 static void power_down_encoders(struct dc *dc)
 {
-   int i;
-
-   blank_all_dp_displays(dc, false);
+   int i, j;
 
for (i = 0; i < dc->link_count; i++) {

[PATCH 26/27] Revert "drm/amd/display: Fix error in dmesg at boot"

2021-10-15 Thread Agustin Gutierrez

This reverts commit 4e605d4b6a510f751b22df4d13829aefb8a0ccec.
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 6db611f9f554..c01309a1cbf2 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1999,7 +1999,7 @@ void blank_all_dp_displays(struct dc *dc, bool hw_init)
 
if ((signal == SIGNAL_TYPE_EDP) ||
(signal == SIGNAL_TYPE_DISPLAY_PORT)) {
-   if (hw_init && signal != SIGNAL_TYPE_EDP && 
dc->links[i]->priv != NULL) {
+   if (hw_init && signal != SIGNAL_TYPE_EDP) {
/* DP 2.0 spec requires that we read LTTPR caps 
first */
dp_retrieve_lttpr_cap(dc->links[i]);
/* if any of the displays are lit up turn them 
off */
@@ -2025,7 +2025,7 @@ void blank_all_dp_displays(struct dc *dc, bool hw_init)
}
 
if 
(!dc->links[i]->wa_flags.dp_keep_receiver_powered ||
-   (hw_init && signal != SIGNAL_TYPE_EDP 
&& dc->links[i]->priv != NULL))
+   (hw_init && signal != SIGNAL_TYPE_EDP))
dp_receiver_power_ctrl(dc->links[i], 
false);
}
}
-- 
2.25.1

[PATCH 25/27] drm/amd/display: [FW Promotion] Release 0.0.88

2021-10-15 Thread Agustin Gutierrez

From: Anthony Koo 

Acked-by: Agustin Gutierrez Sanchez 
Signed-off-by: Anthony Koo 
---
 drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h 
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index b37a485fcba5..bfe052afc518 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -47,10 +47,10 @@
 
 /* Firmware versioning. */
 #ifdef DMUB_EXPOSE_VERSION
-#define DMUB_FW_VERSION_GIT_HASH 0xf0c64c97
+#define DMUB_FW_VERSION_GIT_HASH 0xd146258f
 #define DMUB_FW_VERSION_MAJOR 0
 #define DMUB_FW_VERSION_MINOR 0
-#define DMUB_FW_VERSION_REVISION 87
+#define DMUB_FW_VERSION_REVISION 88
 #define DMUB_FW_VERSION_TEST 0
 #define DMUB_FW_VERSION_VBIOS 0
 #define DMUB_FW_VERSION_HOTFIX 0
-- 
2.25.1

[PATCH 17/27] drm/amd/display: Increase watermark latencies for DCN3.1

2021-10-15 Thread Agustin Gutierrez

From: Nikola Cornij 

[why]
The original latencies were causing underflow in some modes

[how]
Replace with the up-to-date watermark values based on new measurments

Reviewed-by: Ahmad Othman 
Acked-by: Agustin Gutierrez Sanchez 
Signed-off-by: Nikola Cornij 
---
 .../amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c | 16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
index 3fae1f1f028d..0088dff441da 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
@@ -371,32 +371,32 @@ static struct wm_table lpddr5_wm_table = {
.wm_inst = WM_A,
.wm_type = WM_TYPE_PSTATE_CHG,
.pstate_latency_us = 11.65333,
-   .sr_exit_time_us = 5.32,
-   .sr_enter_plus_exit_time_us = 6.38,
+   .sr_exit_time_us = 11.5,
+   .sr_enter_plus_exit_time_us = 14.5,
.valid = true,
},
{
.wm_inst = WM_B,
.wm_type = WM_TYPE_PSTATE_CHG,
.pstate_latency_us = 11.65333,
-   .sr_exit_time_us = 9.82,
-   .sr_enter_plus_exit_time_us = 11.196,
+   .sr_exit_time_us = 11.5,
+   .sr_enter_plus_exit_time_us = 14.5,
.valid = true,
},
{
.wm_inst = WM_C,
.wm_type = WM_TYPE_PSTATE_CHG,
.pstate_latency_us = 11.65333,
-   .sr_exit_time_us = 9.89,
-   .sr_enter_plus_exit_time_us = 11.24,
+   .sr_exit_time_us = 11.5,
+   .sr_enter_plus_exit_time_us = 14.5,
.valid = true,
},
{
.wm_inst = WM_D,
.wm_type = WM_TYPE_PSTATE_CHG,
.pstate_latency_us = 11.65333,
-   .sr_exit_time_us = 9.748,
-   .sr_enter_plus_exit_time_us = 11.102,
+   .sr_exit_time_us = 11.5,
+   .sr_enter_plus_exit_time_us = 14.5,
.valid = true,
},
}
-- 
2.25.1

[PATCH 20/27] drm/amd/display: Moved dccg init to after bios golden init

2021-10-15 Thread Agustin Gutierrez

From: Jake Wang 

[Why]
bios_golden_init will override dccg_init during init_hw.

[How]
Move dccg_init to after bios_golden_init.

Reviewed-by: Aric Cyr 
Reviewed-by: Eric Yang 
Acked-by: Agustin Gutierrez Sanchez 
Signed-off-by: Jake Wang 
---
 drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c | 7 +++
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
index 65f66687af4c..186d08aec812 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
@@ -77,10 +77,6 @@ void dcn31_init_hw(struct dc *dc)
if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
 
-   // Initialize the dccg
-   if (res_pool->dccg->funcs->dccg_init)
-   res_pool->dccg->funcs->dccg_init(res_pool->dccg);
-
if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
 
REG_WRITE(REFCLK_CNTL, 0);
@@ -107,6 +103,9 @@ void dcn31_init_hw(struct dc *dc)
hws->funcs.bios_golden_init(dc);
hws->funcs.disable_vga(dc->hwseq);
}
+   // Initialize the dccg
+   if (res_pool->dccg->funcs->dccg_init)
+   res_pool->dccg->funcs->dccg_init(res_pool->dccg);
 
if (dc->debug.enable_mem_low_power.bits.dmcu) {
// Force ERAM to shutdown if DMCU is not enabled
-- 
2.25.1

[PATCH 24/27] drm/amd/display: Add bios parser support for latest firmware_info

2021-10-15 Thread Agustin Gutierrez

From: Nevenko Stupar 

[Why]
V3_4 is latest in use.

[How]
Add bios parser support for firmware_info_v3_4 along
with some relevant fields it is also retrieving from dce_info
and smu_info.

Reviewed-by: Jun Lei 
Acked-by: Agustin Gutierrez Sanchez 
Signed-off-by: Nevenko Stupar 
---
 .../drm/amd/display/dc/bios/bios_parser2.c| 90 ++-
 1 file changed, 89 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c 
b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
index cdb5c027411a..c17732fba039 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
@@ -99,6 +99,10 @@ static enum bp_result get_firmware_info_v3_2(
struct bios_parser *bp,
struct dc_firmware_info *info);
 
+static enum bp_result get_firmware_info_v3_4(
+   struct bios_parser *bp,
+   struct dc_firmware_info *info);
+
 static struct atom_hpd_int_record *get_hpd_record(struct bios_parser *bp,
struct atom_display_object_path_v2 *object);
 
@@ -1426,8 +1430,10 @@ static enum bp_result bios_parser_get_firmware_info(
break;
case 2:
case 3:
-   case 4:
result = get_firmware_info_v3_2(bp, info);
+break;
+   case 4:
+   result = get_firmware_info_v3_4(bp, info);
break;
default:
break;
@@ -1575,6 +1581,88 @@ static enum bp_result get_firmware_info_v3_2(
return BP_RESULT_OK;
 }
 
+static enum bp_result get_firmware_info_v3_4(
+   struct bios_parser *bp,
+   struct dc_firmware_info *info)
+{
+   struct atom_firmware_info_v3_4 *firmware_info;
+   struct atom_common_table_header *header;
+   struct atom_data_revision revision;
+   struct atom_display_controller_info_v4_1 *dce_info_v4_1 = NULL;
+   struct atom_display_controller_info_v4_4 *dce_info_v4_4 = NULL;
+   if (!info)
+   return BP_RESULT_BADINPUT;
+
+   firmware_info = GET_IMAGE(struct atom_firmware_info_v3_4,
+   DATA_TABLES(firmwareinfo));
+
+   if (!firmware_info)
+   return BP_RESULT_BADBIOSTABLE;
+
+   memset(info, 0, sizeof(*info));
+
+   header = GET_IMAGE(struct atom_common_table_header,
+   DATA_TABLES(dce_info));
+
+   get_atom_data_table_revision(header, );
+
+   switch (revision.major) {
+   case 4:
+   switch (revision.minor) {
+   case 4:
+   dce_info_v4_4 = GET_IMAGE(struct 
atom_display_controller_info_v4_4,
+   DATA_TABLES(dce_info));
+
+   if (!dce_info_v4_4)
+   return BP_RESULT_BADBIOSTABLE;
+
+   /* 100MHz expected */
+   info->pll_info.crystal_frequency = 
dce_info_v4_4->dce_refclk_10khz * 10;
+   info->dp_phy_ref_clk = 
dce_info_v4_4->dpphy_refclk_10khz * 10;
+   /* 50MHz expected */
+   info->i2c_engine_ref_clk = 
dce_info_v4_4->i2c_engine_refclk_10khz * 10;
+
+   /* Get SMU Display PLL VCO Frequency in KHz*/
+   info->smu_gpu_pll_output_freq = 
dce_info_v4_4->dispclk_pll_vco_freq * 10;
+   break;
+
+   default:
+   /* should not come here, keep as backup, as was before 
*/
+   dce_info_v4_1 = GET_IMAGE(struct 
atom_display_controller_info_v4_1,
+   DATA_TABLES(dce_info));
+
+   if (!dce_info_v4_1)
+   return BP_RESULT_BADBIOSTABLE;
+
+   info->pll_info.crystal_frequency = 
dce_info_v4_1->dce_refclk_10khz * 10;
+   info->dp_phy_ref_clk = 
dce_info_v4_1->dpphy_refclk_10khz * 10;
+   info->i2c_engine_ref_clk = 
dce_info_v4_1->i2c_engine_refclk_10khz * 10;
+   break;
+   }
+   break;
+
+   default:
+   ASSERT(0);
+   break;
+   }
+
+   header = GET_IMAGE(struct atom_common_table_header,
+   DATA_TABLES(smu_info));
+   get_atom_data_table_revision(header, );
+
+// We need to convert from 10KHz units into KHz units.
+   info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10;
+
+   if (firmware_info->board_i2c_feature_id == 0x2) {
+   info->oem_i2c_present = true;
+   info->oem_i2c_obj_id = firmware_info->board_i2c_feature_gpio_id;
+   } else {
+

[PATCH 21/27] drm/amd/display: Disable hdmistream and hdmichar clocks

2021-10-15 Thread Agustin Gutierrez

From: Jake Wang 

[Why & How]
Disable hdmistream and hdmichar root clocks when not being used.

Reviewed-by: Aric Cyr 
Acked-by: Agustin Gutierrez Sanchez 
Signed-off-by: Jake Wang 
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h| 9 +++--
 drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h| 9 +
 .../gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_offset.h  | 2 ++
 .../gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_sh_mask.h | 8 
 4 files changed, 22 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
index 4098669a0c1f..f98aba308028 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
@@ -186,8 +186,11 @@
type SYMCLK32_ROOT_LE0_GATE_DISABLE;\
type SYMCLK32_ROOT_LE1_GATE_DISABLE;\
type DPSTREAMCLK_ROOT_GATE_DISABLE;\
-   type DPSTREAMCLK_GATE_DISABLE;
-
+   type DPSTREAMCLK_GATE_DISABLE;\
+   type HDMISTREAMCLK0_DTO_PHASE;\
+   type HDMISTREAMCLK0_DTO_MODULO;\
+   type HDMICHARCLK0_GATE_DISABLE;\
+   type HDMICHARCLK0_ROOT_GATE_DISABLE;
 
 
 struct dccg_shift {
@@ -231,6 +234,8 @@ struct dccg_registers {
uint32_t DPSTREAMCLK_ROOT_GATE_DISABLE;
uint32_t DPSTREAMCLK_GATE_DISABLE;
uint32_t DCCG_GATE_DISABLE_CNTL3;
+   uint32_t HDMISTREAMCLK0_DTO_PARAM;
+   uint32_t DCCG_GATE_DISABLE_CNTL4;
 
 };
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h 
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h
index 602bf461298b..a013a32bbaf7 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h
@@ -66,7 +66,8 @@
SR(DSCCLK1_DTO_PARAM),\
SR(DSCCLK2_DTO_PARAM),\
SR(DSCCLK_DTO_CTRL),\
-   SR(DCCG_GATE_DISABLE_CNTL3)
+   SR(DCCG_GATE_DISABLE_CNTL3),\
+   SR(HDMISTREAMCLK0_DTO_PARAM)
 
 
 #define DCCG_MASK_SH_LIST_DCN31(mask_sh) \
@@ -141,9 +142,9 @@
DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE2_GATE_DISABLE, 
mask_sh),\
DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE3_GATE_DISABLE, 
mask_sh),\
DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE0_GATE_DISABLE, 
mask_sh),\
-   DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE1_GATE_DISABLE, 
mask_sh)
-
-
+   DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE1_GATE_DISABLE, 
mask_sh),\
+   DCCG_SF(HDMISTREAMCLK0_DTO_PARAM, HDMISTREAMCLK0_DTO_PHASE, mask_sh),\
+   DCCG_SF(HDMISTREAMCLK0_DTO_PARAM, HDMISTREAMCLK0_DTO_MODULO, mask_sh)
 
 
 struct dccg *dccg31_create(
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_offset.h 
b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_offset.h
index 312c50ea30f3..f268d33c4744 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_offset.h
@@ -436,6 +436,8 @@
 #define regPHYESYMCLK_CLOCK_CNTL_BASE_IDX  
 2
 #define regDCCG_GATE_DISABLE_CNTL3 
 0x005a
 #define regDCCG_GATE_DISABLE_CNTL3_BASE_IDX
 2
+#define regHDMISTREAMCLK0_DTO_PARAM
 0x005b
+#define regHDMISTREAMCLK0_DTO_PARAM_BASE_IDX   
 2
 #define regDCCG_AUDIO_DTBCLK_DTO_PHASE 
 0x0061
 #define regDCCG_AUDIO_DTBCLK_DTO_PHASE_BASE_IDX
 2
 #define regDCCG_AUDIO_DTBCLK_DTO_MODULO
 0x0062
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_sh_mask.h 
b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_sh_mask.h
index a9d553ef26c0..1f21f313bd1d 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_sh_mask.h
@@ -1438,6 +1438,14 @@
 #define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE0_GATE_DISABLE_MASK
   0x0020L
 #define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE1_GATE_DISABLE_MASK   
   0x0040L
 #define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE1_GATE_DISABLE_MASK
   0x0080L
+//HDMISTREAMCLK0_DTO_PARAM
+#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_PHASE__SHIFT  
   0x0
+#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_MODULO__SHIFT 
   0x8
+#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_EN__SHIFT 
   0x10
+#define

[PATCH 18/27] drm/amd/display: Disable dpstreamclk, symclk32_se, and symclk32_le

2021-10-15 Thread Agustin Gutierrez

From: Jake Wang 

[Why & How]
Disable dpstreamclk, symclk32_se, and symclk32_le when not in use.

Reviewed-by: Ariel Bernstein 
Acked-by: Agustin Gutierrez Sanchez 
Signed-off-by: Jake Wang 
---
 .../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h |  15 ++-
 .../gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c | 107 --
 .../gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h |  19 +++-
 3 files changed, 130 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
index f6f2d48a70c1..4098669a0c1f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
@@ -178,7 +178,16 @@
type DSCCLK2_DTO_MODULO;\
type DSCCLK0_DTO_ENABLE;\
type DSCCLK1_DTO_ENABLE;\
-   type DSCCLK2_DTO_ENABLE;
+   type DSCCLK2_DTO_ENABLE;\
+   type SYMCLK32_ROOT_SE0_GATE_DISABLE;\
+   type SYMCLK32_ROOT_SE1_GATE_DISABLE;\
+   type SYMCLK32_ROOT_SE2_GATE_DISABLE;\
+   type SYMCLK32_ROOT_SE3_GATE_DISABLE;\
+   type SYMCLK32_ROOT_LE0_GATE_DISABLE;\
+   type SYMCLK32_ROOT_LE1_GATE_DISABLE;\
+   type DPSTREAMCLK_ROOT_GATE_DISABLE;\
+   type DPSTREAMCLK_GATE_DISABLE;
+
 
 
 struct dccg_shift {
@@ -219,6 +228,10 @@ struct dccg_registers {
uint32_t DSCCLK0_DTO_PARAM;
uint32_t DSCCLK1_DTO_PARAM;
uint32_t DSCCLK2_DTO_PARAM;
+   uint32_t DPSTREAMCLK_ROOT_GATE_DISABLE;
+   uint32_t DPSTREAMCLK_GATE_DISABLE;
+   uint32_t DCCG_GATE_DISABLE_CNTL3;
+
 };
 
 struct dcn_dccg {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c 
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
index 3a325e4afe2f..815481a3ef54 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
@@ -94,10 +94,7 @@ static enum phyd32clk_clock_source get_phy_mux_symclk(
return src;
 }
 
-void dccg31_set_dpstreamclk(
-   struct dccg *dccg,
-   enum hdmistreamclk_source src,
-   int otg_inst)
+static void dccg31_enable_dpstreamclk(struct dccg *dccg, int otg_inst)
 {
struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
 
@@ -105,24 +102,69 @@ void dccg31_set_dpstreamclk(
switch (otg_inst) {
case 0:
REG_UPDATE(DPSTREAMCLK_CNTL,
-   DPSTREAMCLK_PIPE0_EN, (src == REFCLK) ? 0 : 1);
+   DPSTREAMCLK_PIPE0_EN, 1);
break;
case 1:
REG_UPDATE(DPSTREAMCLK_CNTL,
-   DPSTREAMCLK_PIPE1_EN, (src == REFCLK) ? 0 : 1);
+   DPSTREAMCLK_PIPE1_EN, 1);
break;
case 2:
REG_UPDATE(DPSTREAMCLK_CNTL,
-   DPSTREAMCLK_PIPE2_EN, (src == REFCLK) ? 0 : 1);
+   DPSTREAMCLK_PIPE2_EN, 1);
break;
case 3:
REG_UPDATE(DPSTREAMCLK_CNTL,
-   DPSTREAMCLK_PIPE3_EN, (src == REFCLK) ? 0 : 1);
+   DPSTREAMCLK_PIPE3_EN, 1);
break;
default:
BREAK_TO_DEBUGGER();
return;
}
+   if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)
+   REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,
+   DPSTREAMCLK_ROOT_GATE_DISABLE, 1);
+}
+
+static void dccg31_disable_dpstreamclk(struct dccg *dccg, int otg_inst)
+{
+   struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+
+   if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)
+   REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,
+   DPSTREAMCLK_ROOT_GATE_DISABLE, 0);
+
+   switch (otg_inst) {
+   case 0:
+   REG_UPDATE(DPSTREAMCLK_CNTL,
+   DPSTREAMCLK_PIPE0_EN, 0);
+   break;
+   case 1:
+   REG_UPDATE(DPSTREAMCLK_CNTL,
+   DPSTREAMCLK_PIPE1_EN, 0);
+   break;
+   case 2:
+   REG_UPDATE(DPSTREAMCLK_CNTL,
+   DPSTREAMCLK_PIPE2_EN, 0);
+   break;
+   case 3:
+   REG_UPDATE(DPSTREAMCLK_CNTL,
+   DPSTREAMCLK_PIPE3_EN, 0);
+   break;
+   default:
+   BREAK_TO_DEBUGGER();
+   return;
+   }
+}
+
+void dccg31_set_dpstreamclk(
+   struct dccg *dccg,
+   enum hdmistreamclk_source src,
+   int otg_inst)
+{
+   if (src == REFCLK)
+   dccg31_disable_dpstreamclk(dccg, otg_inst);
+   else
+   dccg31_enable_dpstreamclk(dccg, otg_inst);
 }
 
 void dccg31_enable_symclk32_se(
@@ -137,21 +179,33 @@ void dccg31_enable_symclk32_se(
/* select one of the PHYD32CLKs as the source for symclk32_se */
switch (hpo_se_inst) {

[PATCH 19/27] drm/amd/display: Removed z10 save after dsc disable

2021-10-15 Thread Agustin Gutierrez

From: Jake Wang 

[Why & How]
Z10 save is done during PSR and bootup.
DSC disable does not need to save for Z10.

Reviewed-by: Eric Yang 
Acked-by: Agustin Gutierrez Sanchez 
Signed-off-by: Jake Wang 
---
 drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c | 4 
 1 file changed, 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
index fee385e37c9b..65f66687af4c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
@@ -317,10 +317,6 @@ void dcn31_dsc_pg_control(
if (hws->ctx->dc->res_pool->dccg->funcs->disable_dsc && 
!power_on)
hws->ctx->dc->res_pool->dccg->funcs->disable_dsc(
hws->ctx->dc->res_pool->dccg, dsc_inst);
-
-#if defined(CONFIG_DRM_AMD_DC_DCN)
-   dc_z10_save_init(hws->ctx->dc);
-#endif
}
 
 }
-- 
2.25.1

[PATCH 16/27] drm/amd/display: increase Z9 latency to workaround underflow in Z9

2021-10-15 Thread Agustin Gutierrez

From: Eric Yang 

[Why]
Z9 latency is higher than when we originally tuned the watermark
parameters, causing underflow. Increasing the value until the latency
issues is resolved.

Reviewed-by: Nicholas Kazlauskas 
Acked-by: Agustin Gutierrez Sanchez 
Signed-off-by: Eric Yang 
---
 drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
index c9d3d691f4c6..12ebd9f8912f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
@@ -222,8 +222,8 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_1_soc = {
.num_states = 5,
.sr_exit_time_us = 9.0,
.sr_enter_plus_exit_time_us = 11.0,
-   .sr_exit_z8_time_us = 402.0,
-   .sr_enter_plus_exit_z8_time_us = 520.0,
+   .sr_exit_z8_time_us = 442.0,
+   .sr_enter_plus_exit_z8_time_us = 560.0,
.writeback_latency_us = 12.0,
.dram_channel_width_bytes = 4,
.round_trip_ping_latency_dcfclk_cycles = 106,
-- 
2.25.1

[PATCH 14/27] drm/amd/display: Disable dsc root clock when not being used

2021-10-15 Thread Agustin Gutierrez

From: Jake Wang 

[Why & How]
Disable root clock for dsc when not being used.

Reviewed-by: Nikola Cornij 
Acked-by: Agustin Gutierrez Sanchez 
Signed-off-by: Jake Wang 
---
 .../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h | 16 -
 .../gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c | 72 +++
 .../gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h | 18 -
 .../drm/amd/display/dc/dcn31/dcn31_hwseq.c| 17 +
 drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h  |  9 +++
 5 files changed, 129 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
index ede65100a050..f6f2d48a70c1 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
@@ -169,7 +169,17 @@
type DTBCLK_DTO_DIV[MAX_PIPES];\
type DCCG_AUDIO_DTO_SEL;\
type DCCG_AUDIO_DTO0_SOURCE_SEL;\
-   type DENTIST_DISPCLK_CHG_MODE;
+   type DENTIST_DISPCLK_CHG_MODE;\
+   type DSCCLK0_DTO_PHASE;\
+   type DSCCLK0_DTO_MODULO;\
+   type DSCCLK1_DTO_PHASE;\
+   type DSCCLK1_DTO_MODULO;\
+   type DSCCLK2_DTO_PHASE;\
+   type DSCCLK2_DTO_MODULO;\
+   type DSCCLK0_DTO_ENABLE;\
+   type DSCCLK1_DTO_ENABLE;\
+   type DSCCLK2_DTO_ENABLE;
+
 
 struct dccg_shift {
DCCG_REG_FIELD_LIST(uint8_t)
@@ -205,6 +215,10 @@ struct dccg_registers {
uint32_t SYMCLK32_SE_CNTL;
uint32_t SYMCLK32_LE_CNTL;
uint32_t DENTIST_DISPCLK_CNTL;
+   uint32_t DSCCLK_DTO_CTRL;
+   uint32_t DSCCLK0_DTO_PARAM;
+   uint32_t DSCCLK1_DTO_PARAM;
+   uint32_t DSCCLK2_DTO_PARAM;
 };
 
 struct dcn_dccg {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c 
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
index 152adb597d48..3a325e4afe2f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
@@ -247,6 +247,76 @@ void dccg31_disable_symclk32_le(
}
 }
 
+static void dccg31_disable_dscclk(struct dccg *dccg, int inst)
+{
+   struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+
+   if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)
+   return;
+   //DTO must be enabled to generate a 0 Hz clock output
+   switch (inst) {
+   case 0:
+   REG_UPDATE(DSCCLK_DTO_CTRL,
+   DSCCLK0_DTO_ENABLE, 1);
+   REG_UPDATE_2(DSCCLK0_DTO_PARAM,
+   DSCCLK0_DTO_PHASE, 0,
+   DSCCLK0_DTO_MODULO, 1);
+   break;
+   case 1:
+   REG_UPDATE(DSCCLK_DTO_CTRL,
+   DSCCLK1_DTO_ENABLE, 1);
+   REG_UPDATE_2(DSCCLK1_DTO_PARAM,
+   DSCCLK1_DTO_PHASE, 0,
+   DSCCLK1_DTO_MODULO, 1);
+   break;
+   case 2:
+   REG_UPDATE(DSCCLK_DTO_CTRL,
+   DSCCLK2_DTO_ENABLE, 1);
+   REG_UPDATE_2(DSCCLK2_DTO_PARAM,
+   DSCCLK2_DTO_PHASE, 0,
+   DSCCLK2_DTO_MODULO, 1);
+   break;
+   default:
+   BREAK_TO_DEBUGGER();
+   return;
+   }
+}
+
+static void dccg31_enable_dscclk(struct dccg *dccg, int inst)
+{
+   struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+
+   if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)
+   return;
+   //Disable DTO
+   switch (inst) {
+   case 0:
+   REG_UPDATE_2(DSCCLK0_DTO_PARAM,
+   DSCCLK0_DTO_PHASE, 0,
+   DSCCLK0_DTO_MODULO, 0);
+   REG_UPDATE(DSCCLK_DTO_CTRL,
+   DSCCLK0_DTO_ENABLE, 0);
+   break;
+   case 1:
+   REG_UPDATE_2(DSCCLK1_DTO_PARAM,
+   DSCCLK1_DTO_PHASE, 0,
+   DSCCLK1_DTO_MODULO, 0);
+   REG_UPDATE(DSCCLK_DTO_CTRL,
+   DSCCLK1_DTO_ENABLE, 0);
+   break;
+   case 2:
+   REG_UPDATE_2(DSCCLK2_DTO_PARAM,
+   DSCCLK2_DTO_PHASE, 0,
+   DSCCLK2_DTO_MODULO, 0);
+   REG_UPDATE(DSCCLK_DTO_CTRL,
+   DSCCLK2_DTO_ENABLE, 0);
+   break;
+   default:
+   BREAK_TO_DEBUGGER();
+   return;
+   }
+}
+
 void dccg31_set_physymclk(
struct dccg *dccg,
int phy_inst,
@@ -469,6 +539,8 @@ static const struct dccg_funcs dccg31_funcs = {
.set_dtbclk_dto = dccg31_set_dtbclk_dto,
.set_audio_dtbclk_dto = dccg31_set_audio_dtbclk_dto,
.set_dispclk_change_mode = dccg31_set_dispclk_change_mode,
+   .disable_dsc = dccg31_disable_dscclk,
+   .enable_dsc = dccg31_enable_dscclk,
 };

[PATCH 15/27] drm/amd/display: Require immediate flip support for DCN3.1 planes

2021-10-15 Thread Agustin Gutierrez

From: Nicholas Kazlauskas 

[Why]
Immediate flip can be enabled dynamically and has higher BW requirements
when validating which voltage mode to use.

If we validate when it's not set then potentially DCFCLK will be too low
and we will underflow.

[How]
DM always requires support so always require it as part of DML input
parameters.

This can't be enabled unconditionally on older ASIC because it blocks
some expected modes so only target DCN3.1 for now.

Reviewed-by: Dmytro Laktyushkin 
Acked-by: Agustin Gutierrez Sanchez 
Signed-off-by: Nicholas Kazlauskas 
---
 drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
index a2e40405c97d..c9d3d691f4c6 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
@@ -1778,6 +1778,13 @@ static int dcn31_populate_dml_pipes_from_context(
pipe = _ctx->pipe_ctx[i];
timing = >stream->timing;
 
+   /*
+* Immediate flip can be set dynamically after enabling the 
plane.
+* We need to require support for immediate flip or underflow 
can be
+* intermittently experienced depending on peak b/w 
requirements.
+*/
+   pipes[pipe_cnt].pipe.src.immediate_flip = true;
+
pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
pipes[pipe_cnt].pipe.src.gpuvm = true;
pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0;
-- 
2.25.1

[PATCH 13/27] drm/amd/display: Add missing PSR state

2021-10-15 Thread Agustin Gutierrez

From: Mikita Lipski 

[why]
PSR_STATE2b was introduced on DMCUB side, but not on the driver side,
which caused convert_psr_state helper function to return
PSR_STATE_INVALID. That caused visual lagging during state transition.

[how]
Add PSR_STATE2b to dc_psr_state and convert_psr_state

Reviewed-by: Wyatt Wood 
Acked-by: Agustin Gutierrez Sanchez 
Signed-off-by: Mikita Lipski 
---
 drivers/gpu/drm/amd/display/dc/dc_types.h | 1 +
 drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h 
b/drivers/gpu/drm/amd/display/dc/dc_types.h
index 15c353c389d8..388457ffc0a8 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -653,6 +653,7 @@ enum dc_psr_state {
PSR_STATE1a,
PSR_STATE2,
PSR_STATE2a,
+   PSR_STATE2b,
PSR_STATE3,
PSR_STATE3Init,
PSR_STATE4,
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c 
b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
index aa8403bc4c83..05d96ca80512 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
@@ -50,6 +50,8 @@ static enum dc_psr_state convert_psr_state(uint32_t raw_state)
state = PSR_STATE2;
else if (raw_state == 0x21)
state = PSR_STATE2a;
+   else if (raw_state == 0x22)
+   state = PSR_STATE2b;
else if (raw_state == 0x30)
state = PSR_STATE3;
else if (raw_state == 0x31)
-- 
2.25.1

[PATCH 11/27] drm/amd/display: Fix DP2 SE and LE SYMCLK selection for B0 PHY

2021-10-15 Thread Agustin Gutierrez

From: Hansen 

Remap phyd32clk to PHYF and PHYG for B0, PHYC and PHYD are unused

Reviewed-by: Nicholas Kazlauskas 
Acked-by: Agustin Gutierrez Sanchez 
Signed-off-by: Hansen 
---
 .../gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c   | 17 +
 1 file changed, 17 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c 
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
index 582c500ecb49..152adb597d48 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
@@ -26,6 +26,7 @@
 #include "reg_helper.h"
 #include "core_types.h"
 #include "dcn31_dccg.h"
+#include "dal_asic_id.h"
 
 #define TO_DCN_DCCG(dccg)\
container_of(dccg, struct dcn_dccg, base)
@@ -80,6 +81,18 @@ static void dccg31_update_dpp_dto(struct dccg *dccg, int 
dpp_inst, int req_dppcl
dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk;
 }
 
+static enum phyd32clk_clock_source get_phy_mux_symclk(
+   struct dcn_dccg *dccg_dcn,
+   enum phyd32clk_clock_source src)
+{
+   if (dccg_dcn->base.ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) {
+   if (src == PHYD32CLKC)
+   src = PHYD32CLKF;
+   if (src == PHYD32CLKD)
+   src = PHYD32CLKG;
+   }
+   return src;
+}
 
 void dccg31_set_dpstreamclk(
struct dccg *dccg,
@@ -119,6 +132,8 @@ void dccg31_enable_symclk32_se(
 {
struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
 
+   phyd32clk = get_phy_mux_symclk(dccg_dcn, phyd32clk);
+
/* select one of the PHYD32CLKs as the source for symclk32_se */
switch (hpo_se_inst) {
case 0:
@@ -188,6 +203,8 @@ void dccg31_enable_symclk32_le(
 {
struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
 
+   phyd32clk = get_phy_mux_symclk(dccg_dcn, phyd32clk);
+
/* select one of the PHYD32CLKs as the source for symclk32_le */
switch (hpo_le_inst) {
case 0:
-- 
2.25.1

[PATCH 12/27] drm/amd/display: Fix prefetch bandwidth calculation for DCN3.1

2021-10-15 Thread Agustin Gutierrez

From: Nicholas Kazlauskas 

[Why]
Prefetch BW calculated is lower than the DML reference because of a
porting error that's excluding cursor and row bandwidth from the
pixel data bandwidth.

[How]
Change the dml_max4 to dml_max3 and include cursor and row bandwidth
in the same calculation as the rest of the pixel data during vactive.

Reviewed-by: Dmytro Laktyushkin 
Acked-by: Agustin Gutierrez Sanchez 
Signed-off-by: Nicholas Kazlauskas 
---
 .../gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c  | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
index ce55c9caf9a2..d58925cff420 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
@@ -5398,9 +5398,9 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct 
display_mode_lib *mode_l
 
v->MaximumReadBandwidthWithPrefetch =

v->MaximumReadBandwidthWithPrefetch
-   + 
dml_max4(
-   
v->VActivePixelBandwidth[i][j][k],
-   
v->VActiveCursorBandwidth[i][j][k]
+   + 
dml_max3(
+   
v->VActivePixelBandwidth[i][j][k]
+   
+ v->VActiveCursorBandwidth[i][j][k]

+ v->NoOfDPP[i][j][k]

* (v->meta_row_bandwidth[i][j][k]

+ 
v->dpte_row_bandwidth[i][j][k]),
-- 
2.25.1

[PATCH 09/27] drm/amd/display: Removed power down on boot from DCN31

2021-10-15 Thread Agustin Gutierrez

From: "Lai, Derek" 

[Why]
Error message on Linux when booting.

[How]
Removed power down on boot from DCN31 HW init
to match DCN10 HW init.

Reviewed-by: Anthony Koo 
Acked-by: Agustin Gutierrez Sanchez 
Signed-off-by: Derek Lai 
---
 .../drm/amd/display/dc/dcn31/dcn31_hwseq.c| 43 ---
 1 file changed, 43 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
index 968b8825dec7..52947c03be31 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
@@ -73,7 +73,6 @@ void dcn31_init_hw(struct dc *dc)
struct resource_pool *res_pool = dc->res_pool;
uint32_t backlight = MAX_BACKLIGHT_LEVEL;
int i;
-   int edp_num;
 
if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
@@ -209,48 +208,6 @@ void dcn31_init_hw(struct dc *dc)

!dc->res_pool->hubbub->ctx->dc->debug.disable_stutter);
}
 
-   /* In headless boot cases, DIG may be turned
-* on which causes HW/SW discrepancies.
-* To avoid this, power down hardware on boot
-* if DIG is turned on and seamless boot not enabled
-*/
-   if (dc->config.power_down_display_on_boot) {
-   struct dc_link *edp_links[MAX_NUM_EDP];
-   struct dc_link *edp_link;
-   bool power_down = false;
-
-   get_edp_links(dc, edp_links, _num);
-   if (edp_num) {
-   for (i = 0; i < edp_num; i++) {
-   edp_link = edp_links[i];
-   if (edp_link->link_enc->funcs->is_dig_enabled &&
-   
edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) &&
-   dc->hwss.edp_backlight_control 
&&
-   dc->hwss.power_down &&
-   dc->hwss.edp_power_control) {
-   
dc->hwss.edp_backlight_control(edp_link, false);
-   dc->hwss.power_down(dc);
-   dc->hwss.edp_power_control(edp_link, 
false);
-   power_down = true;
-   }
-   }
-   }
-   if (!power_down) {
-   for (i = 0; i < dc->link_count; i++) {
-   struct dc_link *link = dc->links[i];
-
-   if (link->ep_type == DISPLAY_ENDPOINT_PHY &&
-   
link->link_enc->funcs->is_dig_enabled &&
-   
link->link_enc->funcs->is_dig_enabled(link->link_enc) &&
-   dc->hwss.power_down) {
-   dc->hwss.power_down(dc);
-   break;
-   }
-
-   }
-   }
-   }
-
for (i = 0; i < res_pool->audio_count; i++) {
struct audio *audio = res_pool->audios[i];
 
-- 
2.25.1

[PATCH 10/27] drm/amd/display: Limit display scaling to up to true 4k for DCN 3.1

2021-10-15 Thread Agustin Gutierrez

From: Nikola Cornij 

[why]
The requirement is that image width up to 4096 shall be supported

Reviewed-by: Aric Cyr 
Acked-by: Agustin Gutierrez Sanchez 
Signed-off-by: Nikola Cornij 
---
 drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
index 20b4202bda13..a2e40405c97d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
@@ -998,7 +998,7 @@ static const struct dc_debug_options debug_defaults_drv = {
.disable_dcc = DCC_ENABLE,
.vsr_support = true,
.performance_trace = false,
-   .max_downscale_src_width = 3840,/*upto 4K*/
+   .max_downscale_src_width = 4096,/*upto true 4K*/
.disable_pplib_wm_range = false,
.scl_reset_length10 = true,
.sanity_checks = false,
-- 
2.25.1

[PATCH 08/27] drm/amd/display: Validate plane rects before use

2021-10-15 Thread Agustin Gutierrez

From: Aric Cyr 

[Why]
Calculation of scaling ratio can result in a crash due to zero'd src or
dst plane rects.

[How]
Validate that src and dst rects are valid before using for scaling
calculations.

Reviewed-by: Josip Pavic 
Acked-by: Agustin Gutierrez Sanchez 
Signed-off-by: Aric Cyr 
---
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 561c10a92bb5..9e83fd54e2ca 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -3009,6 +3009,11 @@ enum dc_status dc_validate_plane(struct dc *dc, const 
struct dc_plane_state *pla
 {
enum dc_status res = DC_OK;
 
+   /* check if surface has invalid dimensions */
+   if (plane_state->src_rect.width == 0 || plane_state->src_rect.height == 
0 ||
+   plane_state->dst_rect.width == 0 || 
plane_state->dst_rect.height == 0)
+   return DC_FAIL_SURFACE_VALIDATE;
+
/* TODO For now validates pixel format only */
if (dc->res_pool->funcs->validate_plane)
return dc->res_pool->funcs->validate_plane(plane_state, 
>caps);
-- 
2.25.1

[PATCH 06/27] drm/amd/display: do not compare integers of different widths

2021-10-15 Thread Agustin Gutierrez

From: Josip Pavic 

[Why & How]
Increase width of some variables to avoid comparing integers of
different widths

Reviewed-by: Aric Cyr 
Acked-by: Agustin Gutierrez Sanchez 
Signed-off-by: Josip Pavic 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index fa11a2b094ba..d54592b573e9 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -3439,7 +3439,7 @@ enum dc_status dc_link_allocate_mst_payload(struct 
pipe_ctx *pipe_ctx)
struct fixed31_32 avg_time_slots_per_mtp;
struct fixed31_32 pbn;
struct fixed31_32 pbn_per_slot;
-   uint8_t i;
+   int i;
enum act_return_status ret;
DC_LOGGER_INIT(link->ctx->logger);
 
@@ -3531,7 +3531,7 @@ static enum dc_status deallocate_mst_payload(struct 
pipe_ctx *pipe_ctx)
struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
struct dp_mst_stream_allocation_table proposed_table = {0};
struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0);
-   uint8_t i;
+   int i;
bool mst_mode = (link->type == dc_connection_mst_branch);
DC_LOGGER_INIT(link->ctx->logger);
 
-- 
2.25.1

[PATCH 07/27] drm/amd/display: correct apg audio channel enable golden value

2021-10-15 Thread Agustin Gutierrez

From: Wenjing Liu 

Hardware team has recommended to generically hard code this register to
0xFF as part of the effort to eventually remove this control.  However
we set it to 0xF instead.
This causes 4 of audio 8ch to be muted.

Reviewed-by: Ariel Bernstein 
Acked-by: Agustin Gutierrez Sanchez 
Signed-off-by: Wenjing Liu 
---
 drivers/gpu/drm/amd/display/dc/dcn31/dcn31_apg.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_apg.c 
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_apg.c
index 6bd7a0626665..de5e18c2a3ac 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_apg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_apg.c
@@ -129,7 +129,7 @@ static void apg31_se_audio_setup(
 
/* When running in "pair mode", pairs of audio channels have their own 
enable
 * this is for really old audio drivers */
-   REG_UPDATE(APG_DBG_GEN_CONTROL, APG_DBG_AUDIO_CHANNEL_ENABLE, 0xF);
+   REG_UPDATE(APG_DBG_GEN_CONTROL, APG_DBG_AUDIO_CHANNEL_ENABLE, 0xFF);
// REG_UPDATE(APG_DBG_GEN_CONTROL, APG_DBG_AUDIO_CHANNEL_ENABLE, 
channels);
 
/* Disable forced mem power off */
-- 
2.25.1

[PATCH 04/27] drm/amd/display: add DP2.0 debug option to set MST_EN for SST stream

2021-10-15 Thread Agustin Gutierrez

From: Wenjing Liu 

[why]
Some DP2.0 RX requires us to set MST_EN even for SST configuration.
We added this debug option so we can configure this temporary workaround
for the RX.

Reviewed-by: George Shen 
Acked-by: Agustin Gutierrez Sanchez 
Signed-off-by: Wenjing Liu 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 7 ++-
 drivers/gpu/drm/amd/display/dc/dc.h   | 1 +
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index ca5dc3c168ec..fa11a2b094ba 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1869,8 +1869,13 @@ static enum dc_status enable_link_dp(struct dc_state 
*state,
do_fallback = true;
 
 #if defined(CONFIG_DRM_AMD_DC_DCN)
+   /*
+* Temporary w/a to get DP2.0 link rates to work with SST.
+* TODO DP2.0 - Workaround: Remove w/a if and when the issue is 
resolved.
+*/
if (dp_get_link_encoding_format(_settings) == 
DP_128b_132b_ENCODING &&
-   pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT) {
+   pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&
+   link->dc->debug.set_mst_en_for_sst) {
dp_enable_mst_on_sink(link, true);
}
 #endif
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index dd995905b0cb..254b760ae91f 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -664,6 +664,7 @@ struct dc_debug_options {
 #if defined(CONFIG_DRM_AMD_DC_DCN)
/* TODO - remove once tested */
bool legacy_dp2_lt;
+   bool set_mst_en_for_sst;
 #endif
union mem_low_power_enable_options enable_mem_low_power;
union root_clock_optimization_options root_clock_optimization;
-- 
2.25.1

[PATCH 03/27] drm/amd/display: Do not skip link training on DP quick hot plug

2021-10-15 Thread Agustin Gutierrez

From: Jimmy Kizito 

[Why]
When rapidly plugging and unplugging a DP sink, detection link
training can be mistakenly skipped.

This is due to the hotplug processing occurring before the
encoder assignment logic has had a chance to process the removal
of a stream. The encoder that would be used for detection link
training is then erroneously reported as already in use and
detection link training is skipped.

[How]
During hot plug processing, only determine a link encoder to be
unavailable for a particular link if it has been assigned to a
different link.

Reviewed-by: Meenakshikumar Somasundaram 
Reviewed-by: Jun Lei 
Acked-by: Agustin Gutierrez Sanchez 
Signed-off-by: Jimmy Kizito 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c  | 2 +-
 drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c | 9 ++---
 drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h | 2 +-
 3 files changed, 8 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 54662d74c65a..8e0b40c7a1ee 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -2863,7 +2863,7 @@ bool dp_verify_link_cap(
link->verified_link_cap = *known_limit_link_setting;
return true;
} else if (link->link_enc && 
link->dc->res_pool->funcs->link_encs_assign &&
-   !link_enc_cfg_is_link_enc_avail(link->ctx->dc, 
link->link_enc->preferred_engine)) {
+   !link_enc_cfg_is_link_enc_avail(link->ctx->dc, 
link->link_enc->preferred_engine, link)) {
link->verified_link_cap = initial_link_settings;
return true;
}
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c
index 1cab4bf06abe..72b0f8594b4a 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c
@@ -488,16 +488,19 @@ struct link_encoder 
*link_enc_cfg_get_link_enc_used_by_stream(
return link_enc;
 }
 
-bool link_enc_cfg_is_link_enc_avail(struct dc *dc, enum engine_id eng_id)
+bool link_enc_cfg_is_link_enc_avail(struct dc *dc, enum engine_id eng_id, 
struct dc_link *link)
 {
bool is_avail = true;
int i;
 
-   /* Add assigned encoders to list. */
+   /* An encoder is not available if it has already been assigned to a 
different endpoint. */
for (i = 0; i < MAX_PIPES; i++) {
struct link_enc_assignment assignment = get_assignment(dc, i);
+   struct display_endpoint_id ep_id = (struct display_endpoint_id) 
{
+   .link_id = link->link_id,
+   .ep_type = link->ep_type};
 
-   if (assignment.valid && assignment.eng_id == eng_id) {
+   if (assignment.valid && assignment.eng_id == eng_id && 
!are_ep_ids_equal(_id, _id)) {
is_avail = false;
break;
}
diff --git a/drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h 
b/drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h
index 83b2199b2c83..10dcf6a5e9b1 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h
@@ -97,7 +97,7 @@ struct link_encoder *link_enc_cfg_get_link_enc_used_by_stream(
const struct dc_stream_state *stream);
 
 /* Return true if encoder available to use. */
-bool link_enc_cfg_is_link_enc_avail(struct dc *dc, enum engine_id eng_id);
+bool link_enc_cfg_is_link_enc_avail(struct dc *dc, enum engine_id eng_id, 
struct dc_link *link);
 
 /* Returns true if encoder assignments in supplied state pass validity checks. 
*/
 bool link_enc_cfg_validate(struct dc *dc, struct dc_state *state);
-- 
2.25.1

[PATCH 02/27] drm/amd/display: Clear encoder assignment for copied streams

2021-10-15 Thread Agustin Gutierrez

From: Jimmy Kizito 

[Why]
When copying a stream, the encoder assigned to it is copied too.
Encoder assignment should only happen when executing the encoder
assignment function link_encs_assign().

[How]
Clear the link encoder pointer for copied stream.

Reviewed-by: Meenakshikumar Somasundaram 
Reviewed-by: Jun Lei 
Acked-by: Agustin Gutierrez Sanchez 
Signed-off-by: Jimmy Kizito 
---
 drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index f0f54f4d3d9b..57cf4cb82370 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -202,6 +202,10 @@ struct dc_stream_state *dc_copy_stream(const struct 
dc_stream_state *stream)
new_stream->stream_id = new_stream->ctx->dc_stream_id_count;
new_stream->ctx->dc_stream_id_count++;
 
+   /* If using dynamic encoder assignment, wait till stream committed to 
assign encoder. */
+   if (new_stream->ctx->dc->res_pool->funcs->link_encs_assign)
+   new_stream->link_enc = NULL;
+
kref_init(_stream->refcount);
 
return new_stream;
-- 
2.25.1

[PATCH 05/27] drm/amd/display: Clean Up VPG Low Mem Power

2021-10-15 Thread Agustin Gutierrez

From: Michael Strauss 

[WHAT]
One of the current VPG power on calls is unnecessary

Reviewed-by: Eric Yang 
Acked-by: Agustin Gutierrez Sanchez 
Signed-off-by: Michael Strauss 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c| 10 --
 drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c  | 13 +
 .../gpu/drm/amd/display/dc/dcn31/dcn31_resource.c   |  4 
 3 files changed, 13 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index f9876e429f26..8be04be19124 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -71,8 +71,6 @@
 
 #include "dmub/dmub_srv.h"
 
-#include "dcn30/dcn30_vpg.h"
-
 #include "i2caux_interface.h"
 #include "dce/dmub_hw_lock_mgr.h"
 
@@ -2674,9 +2672,6 @@ static void commit_planes_do_stream_update(struct dc *dc,
enum surface_update_type update_type,
struct dc_state *context)
 {
-#if defined(CONFIG_DRM_AMD_DC_DCN)
-   struct vpg *vpg;
-#endif
int j;
 
// Stream updates
@@ -2697,11 +2692,6 @@ static void commit_planes_do_stream_update(struct dc *dc,
stream_update->vrr_infopacket ||
stream_update->vsc_infopacket ||
stream_update->vsp_infopacket) {
-#if defined(CONFIG_DRM_AMD_DC_DCN)
-   vpg = pipe_ctx->stream_res.stream_enc->vpg;
-   if (vpg && vpg->funcs->vpg_poweron)
-   vpg->funcs->vpg_poweron(vpg);
-#endif
resource_build_info_frame(pipe_ctx);
dc->hwss.update_info_frame(pipe_ctx);
}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
index 18e33ef3d217..968b8825dec7 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
@@ -49,6 +49,7 @@
 #include "inc/link_dpcd.h"
 #include "dcn10/dcn10_hw_sequencer.h"
 #include "inc/link_enc_cfg.h"
+#include "dcn30/dcn30_vpg.h"
 
 #define DC_LOGGER_INIT(logger)
 
@@ -126,6 +127,18 @@ void dcn31_init_hw(struct dc *dc)
REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1);
}
 
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+   if (dc->debug.enable_mem_low_power.bits.vpg && 
dc->res_pool->stream_enc[0]->vpg->funcs->vpg_powerdown) {
+   // Power down VPGs
+   for (i = 0; i < dc->res_pool->stream_enc_count; i++)
+   
dc->res_pool->stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->stream_enc[i]->vpg);
+#if defined(CONFIG_DRM_AMD_DC_DP2_0)
+   for (i = 0; i < dc->res_pool->hpo_dp_stream_enc_count; i++)
+   
dc->res_pool->hpo_dp_stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->hpo_dp_stream_enc[i]->vpg);
+#endif
+   }
+#endif
+
if (dc->ctx->dc_bios->fw_info_valid) {
res_pool->ref_clocks.xtalin_clock_inKhz =

dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
index 7cb7604a35eb..20b4202bda13 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
@@ -1312,10 +1312,6 @@ static struct vpg *dcn31_vpg_create(
_shift,
_mask);
 
-   // Will re-enable hw block when we enable stream
-   // Check for enabled stream before powering down?
-   vpg31_powerdown(>base);
-
return >base;
 }
 
-- 
2.25.1

[PATCH 01/27] drm/amd/display: Disable dpp root clock when not being used

2021-10-15 Thread Agustin Gutierrez

From: Jake Wang 

[Why & How]
Disable root clock for dpp when not being used.

Reviewed-by: Eric Yang 
Acked-by: Agustin Gutierrez Sanchez 
Signed-off-by: Jake Wang 
---
 .../display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c  |  5 ++-
 .../gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c | 41 ++-
 2 files changed, 44 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
index d7bf9283dc90..3fae1f1f028d 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
@@ -219,14 +219,17 @@ static void dcn31_update_clocks(struct clk_mgr 
*clk_mgr_base,
update_dispclk = true;
}
 
-   /* TODO: add back DTO programming when DPPCLK restore is fixed in FSDL*/
if (dpp_clock_lowered) {
// increase per DPP DTO before lowering global dppclk
+   dcn20_update_clocks_update_dpp_dto(clk_mgr, context, 
safe_to_lower);
dcn31_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
} else {
// increase global DPPCLK before lowering per DPP DTO
if (update_dppclk || update_dispclk)
dcn31_smu_set_dppclk(clk_mgr, 
clk_mgr_base->clks.dppclk_khz);
+   // always update dtos unless clock is lowered and not safe to 
lower
+   if (new_clocks->dppclk_khz >= 
dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)
+   dcn20_update_clocks_update_dpp_dto(clk_mgr, context, 
safe_to_lower);
}
 
// notify DMCUB of latest clocks
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c 
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
index 9896adf67425..582c500ecb49 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
@@ -42,6 +42,45 @@
 #define DC_LOGGER \
dccg->ctx->logger
 
+static void dccg31_update_dpp_dto(struct dccg *dccg, int dpp_inst, int 
req_dppclk)
+{
+   struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+
+   if (dccg->ref_dppclk && req_dppclk) {
+   int ref_dppclk = dccg->ref_dppclk;
+   int modulo, phase;
+
+   // phase / modulo = dpp pipe clk / dpp global clk
+   modulo = 0xff;   // use FF at the end
+   phase = ((modulo * req_dppclk) + ref_dppclk - 1) / ref_dppclk;
+
+   if (phase > 0xff) {
+   ASSERT(false);
+   phase = 0xff;
+   }
+
+   REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
+   DPPCLK0_DTO_PHASE, phase,
+   DPPCLK0_DTO_MODULO, modulo);
+   REG_UPDATE(DPPCLK_DTO_CTRL,
+   DPPCLK_DTO_ENABLE[dpp_inst], 1);
+   } else {
+   //DTO must be enabled to generate a 0Hz clock output
+   if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpp) {
+   REG_UPDATE(DPPCLK_DTO_CTRL,
+   DPPCLK_DTO_ENABLE[dpp_inst], 1);
+   REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
+   DPPCLK0_DTO_PHASE, 0,
+   DPPCLK0_DTO_MODULO, 1);
+   } else {
+   REG_UPDATE(DPPCLK_DTO_CTRL,
+   DPPCLK_DTO_ENABLE[dpp_inst], 0);
+   }
+   }
+   dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk;
+}
+
+
 void dccg31_set_dpstreamclk(
struct dccg *dccg,
enum hdmistreamclk_source src,
@@ -401,7 +440,7 @@ void dccg31_init(struct dccg *dccg)
 }
 
 static const struct dccg_funcs dccg31_funcs = {
-   .update_dpp_dto = dccg2_update_dpp_dto,
+   .update_dpp_dto = dccg31_update_dpp_dto,
.get_dccg_ref_freq = dccg31_get_dccg_ref_freq,
.dccg_init = dccg31_init,
.set_dpstreamclk = dccg31_set_dpstreamclk,
-- 
2.25.1

[PATCH 00/27] DC Patchset for October 15

2021-10-15 Thread Agustin Gutierrez

This DC patchset brings improvements in multiple areas. In summary, we
highlight:

* Fix some issues such as DP2 problem, prefetch bandwidth calculation
for DCN3.1 and others.
* Increased Z9 latency and removed z10 save after dsc disable.
* Revert a couple of bad changes.
* Added missing PSR state patch.

Cc: Daniel Wheeler 
Cc: Mark Broadworth 

Agustin Gutierrez (2):
  Revert "drm/amd/display: Fix error in dmesg at boot"
  Revert "drm/amd/display: Add helper for blanking all dp displays"

Anthony Koo (2):
  drm/amd/display: Change initializer to single brace
  drm/amd/display: [FW Promotion] Release 0.0.88

Aric Cyr (2):
  drm/amd/display: Validate plane rects before use
  drm/amd/display: 3.2.157

Eric Yang (1):
  drm/amd/display: increase Z9 latency to workaround underflow in Z9

Hansen (1):
  drm/amd/display: Fix DP2 SE and LE SYMCLK selection for B0 PHY

Jake Wang (6):
  drm/amd/display: Disable dpp root clock when not being used
  drm/amd/display: Disable dsc root clock when not being used
  drm/amd/display: Disable dpstreamclk, symclk32_se, and symclk32_le
  drm/amd/display: Removed z10 save after dsc disable
  drm/amd/display: Moved dccg init to after bios golden init
  drm/amd/display: Disable hdmistream and hdmichar clocks

Jimmy Kizito (2):
  drm/amd/display: Clear encoder assignment for copied streams
  drm/amd/display: Do not skip link training on DP quick hot plug

Josip Pavic (1):
  drm/amd/display: do not compare integers of different widths

Lai, Derek (1):
  drm/amd/display: Removed power down on boot from DCN31

Michael Strauss (1):
  drm/amd/display: Clean Up VPG Low Mem Power

Mikita Lipski (1):
  drm/amd/display: Add missing PSR state

Nevenko Stupar (1):
  drm/amd/display: Add bios parser support for latest firmware_info

Nicholas Kazlauskas (2):
  drm/amd/display: Fix prefetch bandwidth calculation for DCN3.1
  drm/amd/display: Require immediate flip support for DCN3.1 planes

Nikola Cornij (2):
  drm/amd/display: Limit display scaling to up to true 4k for DCN 3.1
  drm/amd/display: Increase watermark latencies for DCN3.1

Wenjing Liu (2):
  drm/amd/display: add DP2.0 debug option to set MST_EN for SST stream
  drm/amd/display: correct apg audio channel enable golden value

 .../drm/amd/display/dc/bios/bios_parser2.c|  90 ++-
 .../display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c  |  21 +-
 drivers/gpu/drm/amd/display/dc/core/dc.c  |  10 -
 drivers/gpu/drm/amd/display/dc/core/dc_link.c |  63 +
 .../gpu/drm/amd/display/dc/core/dc_link_ddc.c |   2 +-
 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  |  32 +--
 .../drm/amd/display/dc/core/dc_link_enc_cfg.c |   9 +-
 .../gpu/drm/amd/display/dc/core/dc_resource.c |   5 +
 .../gpu/drm/amd/display/dc/core/dc_stream.c   |   4 +
 drivers/gpu/drm/amd/display/dc/dc.h   |   3 +-
 drivers/gpu/drm/amd/display/dc/dc_link.h  |   1 -
 drivers/gpu/drm/amd/display/dc/dc_types.h |   1 +
 drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c |   2 +
 .../display/dc/dce110/dce110_hw_sequencer.c   |  24 +-
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c |  49 +++-
 .../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h |  34 ++-
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.c|   4 +-
 .../drm/amd/display/dc/dcn30/dcn30_hwseq.c|  39 ++-
 .../gpu/drm/amd/display/dc/dcn31/dcn31_apg.c  |   2 +-
 .../gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c | 237 +-
 .../gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h |  34 ++-
 .../drm/amd/display/dc/dcn31/dcn31_hwseq.c| 114 +
 .../drm/amd/display/dc/dcn31/dcn31_resource.c |  17 +-
 .../dc/dml/dcn31/display_mode_vba_31.c|   6 +-
 drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h  |   9 +
 .../gpu/drm/amd/display/dc/inc/link_enc_cfg.h |   2 +-
 .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h   |   4 +-
 .../include/asic_reg/dcn/dcn_3_1_2_offset.h   |   2 +
 .../include/asic_reg/dcn/dcn_3_1_2_sh_mask.h  |   8 +
 29 files changed, 643 insertions(+), 185 deletions(-)

-- 
2.25.1

[PATCH 07/27] drm/amd/display: correct apg audio channel enable golden value

2021-10-15 Thread Agustin Gutierrez

From: Wenjing Liu 

Hardware team has recommended to generically hard code this register to
0xFF as part of the effort to eventually remove this control.  However
we set it to 0xF instead.
This causes 4 of audio 8ch to be muted.

Reviewed-by: Ariel Bernstein 
Acked-by: Agustin Gutierrez Sanchez 
Signed-off-by: Wenjing Liu 
---
 drivers/gpu/drm/amd/display/dc/dcn31/dcn31_apg.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_apg.c 
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_apg.c
index 6bd7a0626665..de5e18c2a3ac 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_apg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_apg.c
@@ -129,7 +129,7 @@ static void apg31_se_audio_setup(
 
/* When running in "pair mode", pairs of audio channels have their own 
enable
 * this is for really old audio drivers */
-   REG_UPDATE(APG_DBG_GEN_CONTROL, APG_DBG_AUDIO_CHANNEL_ENABLE, 0xF);
+   REG_UPDATE(APG_DBG_GEN_CONTROL, APG_DBG_AUDIO_CHANNEL_ENABLE, 0xFF);
// REG_UPDATE(APG_DBG_GEN_CONTROL, APG_DBG_AUDIO_CHANNEL_ENABLE, 
channels);
 
/* Disable forced mem power off */
-- 
2.25.1

[PATCH 08/27] drm/amd/display: Validate plane rects before use

2021-10-15 Thread Agustin Gutierrez

From: Aric Cyr 

[Why]
Calculation of scaling ratio can result in a crash due to zero'd src or
dst plane rects.

[How]
Validate that src and dst rects are valid before using for scaling
calculations.

Reviewed-by: Josip Pavic 
Acked-by: Agustin Gutierrez Sanchez 
Signed-off-by: Aric Cyr 
---
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 561c10a92bb5..9e83fd54e2ca 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -3009,6 +3009,11 @@ enum dc_status dc_validate_plane(struct dc *dc, const 
struct dc_plane_state *pla
 {
enum dc_status res = DC_OK;
 
+   /* check if surface has invalid dimensions */
+   if (plane_state->src_rect.width == 0 || plane_state->src_rect.height == 
0 ||
+   plane_state->dst_rect.width == 0 || 
plane_state->dst_rect.height == 0)
+   return DC_FAIL_SURFACE_VALIDATE;
+
/* TODO For now validates pixel format only */
if (dc->res_pool->funcs->validate_plane)
return dc->res_pool->funcs->validate_plane(plane_state, 
>caps);
-- 
2.25.1

[PATCH 04/27] drm/amd/display: add DP2.0 debug option to set MST_EN for SST stream

2021-10-15 Thread Agustin Gutierrez

From: Wenjing Liu 

[why]
Some DP2.0 RX requires us to set MST_EN even for SST configuration.
We added this debug option so we can configure this temporary workaround
for the RX.

Reviewed-by: George Shen 
Acked-by: Agustin Gutierrez Sanchez 
Signed-off-by: Wenjing Liu 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 7 ++-
 drivers/gpu/drm/amd/display/dc/dc.h   | 1 +
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index ca5dc3c168ec..fa11a2b094ba 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1869,8 +1869,13 @@ static enum dc_status enable_link_dp(struct dc_state 
*state,
do_fallback = true;
 
 #if defined(CONFIG_DRM_AMD_DC_DCN)
+   /*
+* Temporary w/a to get DP2.0 link rates to work with SST.
+* TODO DP2.0 - Workaround: Remove w/a if and when the issue is 
resolved.
+*/
if (dp_get_link_encoding_format(_settings) == 
DP_128b_132b_ENCODING &&
-   pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT) {
+   pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&
+   link->dc->debug.set_mst_en_for_sst) {
dp_enable_mst_on_sink(link, true);
}
 #endif
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index dd995905b0cb..254b760ae91f 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -664,6 +664,7 @@ struct dc_debug_options {
 #if defined(CONFIG_DRM_AMD_DC_DCN)
/* TODO - remove once tested */
bool legacy_dp2_lt;
+   bool set_mst_en_for_sst;
 #endif
union mem_low_power_enable_options enable_mem_low_power;
union root_clock_optimization_options root_clock_optimization;
-- 
2.25.1

[PATCH 06/27] drm/amd/display: do not compare integers of different widths

2021-10-15 Thread Agustin Gutierrez

From: Josip Pavic 

[Why & How]
Increase width of some variables to avoid comparing integers of
different widths

Reviewed-by: Aric Cyr 
Acked-by: Agustin Gutierrez Sanchez 
Signed-off-by: Josip Pavic 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index fa11a2b094ba..d54592b573e9 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -3439,7 +3439,7 @@ enum dc_status dc_link_allocate_mst_payload(struct 
pipe_ctx *pipe_ctx)
struct fixed31_32 avg_time_slots_per_mtp;
struct fixed31_32 pbn;
struct fixed31_32 pbn_per_slot;
-   uint8_t i;
+   int i;
enum act_return_status ret;
DC_LOGGER_INIT(link->ctx->logger);
 
@@ -3531,7 +3531,7 @@ static enum dc_status deallocate_mst_payload(struct 
pipe_ctx *pipe_ctx)
struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
struct dp_mst_stream_allocation_table proposed_table = {0};
struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0);
-   uint8_t i;
+   int i;
bool mst_mode = (link->type == dc_connection_mst_branch);
DC_LOGGER_INIT(link->ctx->logger);
 
-- 
2.25.1

[PATCH 05/27] drm/amd/display: Clean Up VPG Low Mem Power

2021-10-15 Thread Agustin Gutierrez

From: Michael Strauss 

[WHAT]
One of the current VPG power on calls is unnecessary

Reviewed-by: Eric Yang 
Acked-by: Agustin Gutierrez Sanchez 
Signed-off-by: Michael Strauss 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c| 10 --
 drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c  | 13 +
 .../gpu/drm/amd/display/dc/dcn31/dcn31_resource.c   |  4 
 3 files changed, 13 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index f9876e429f26..8be04be19124 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -71,8 +71,6 @@
 
 #include "dmub/dmub_srv.h"
 
-#include "dcn30/dcn30_vpg.h"
-
 #include "i2caux_interface.h"
 #include "dce/dmub_hw_lock_mgr.h"
 
@@ -2674,9 +2672,6 @@ static void commit_planes_do_stream_update(struct dc *dc,
enum surface_update_type update_type,
struct dc_state *context)
 {
-#if defined(CONFIG_DRM_AMD_DC_DCN)
-   struct vpg *vpg;
-#endif
int j;
 
// Stream updates
@@ -2697,11 +2692,6 @@ static void commit_planes_do_stream_update(struct dc *dc,
stream_update->vrr_infopacket ||
stream_update->vsc_infopacket ||
stream_update->vsp_infopacket) {
-#if defined(CONFIG_DRM_AMD_DC_DCN)
-   vpg = pipe_ctx->stream_res.stream_enc->vpg;
-   if (vpg && vpg->funcs->vpg_poweron)
-   vpg->funcs->vpg_poweron(vpg);
-#endif
resource_build_info_frame(pipe_ctx);
dc->hwss.update_info_frame(pipe_ctx);
}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
index 18e33ef3d217..968b8825dec7 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
@@ -49,6 +49,7 @@
 #include "inc/link_dpcd.h"
 #include "dcn10/dcn10_hw_sequencer.h"
 #include "inc/link_enc_cfg.h"
+#include "dcn30/dcn30_vpg.h"
 
 #define DC_LOGGER_INIT(logger)
 
@@ -126,6 +127,18 @@ void dcn31_init_hw(struct dc *dc)
REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1);
}
 
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+   if (dc->debug.enable_mem_low_power.bits.vpg && 
dc->res_pool->stream_enc[0]->vpg->funcs->vpg_powerdown) {
+   // Power down VPGs
+   for (i = 0; i < dc->res_pool->stream_enc_count; i++)
+   
dc->res_pool->stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->stream_enc[i]->vpg);
+#if defined(CONFIG_DRM_AMD_DC_DP2_0)
+   for (i = 0; i < dc->res_pool->hpo_dp_stream_enc_count; i++)
+   
dc->res_pool->hpo_dp_stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->hpo_dp_stream_enc[i]->vpg);
+#endif
+   }
+#endif
+
if (dc->ctx->dc_bios->fw_info_valid) {
res_pool->ref_clocks.xtalin_clock_inKhz =

dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
index 7cb7604a35eb..20b4202bda13 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
@@ -1312,10 +1312,6 @@ static struct vpg *dcn31_vpg_create(
_shift,
_mask);
 
-   // Will re-enable hw block when we enable stream
-   // Check for enabled stream before powering down?
-   vpg31_powerdown(>base);
-
return >base;
 }
 
-- 
2.25.1

[PATCH 03/27] drm/amd/display: Do not skip link training on DP quick hot plug

2021-10-15 Thread Agustin Gutierrez

From: Jimmy Kizito 

[Why]
When rapidly plugging and unplugging a DP sink, detection link
training can be mistakenly skipped.

This is due to the hotplug processing occurring before the
encoder assignment logic has had a chance to process the removal
of a stream. The encoder that would be used for detection link
training is then erroneously reported as already in use and
detection link training is skipped.

[How]
During hot plug processing, only determine a link encoder to be
unavailable for a particular link if it has been assigned to a
different link.

Reviewed-by: Meenakshikumar Somasundaram 
Reviewed-by: Jun Lei 
Acked-by: Agustin Gutierrez Sanchez 
Signed-off-by: Jimmy Kizito 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c  | 2 +-
 drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c | 9 ++---
 drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h | 2 +-
 3 files changed, 8 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 54662d74c65a..8e0b40c7a1ee 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -2863,7 +2863,7 @@ bool dp_verify_link_cap(
link->verified_link_cap = *known_limit_link_setting;
return true;
} else if (link->link_enc && 
link->dc->res_pool->funcs->link_encs_assign &&
-   !link_enc_cfg_is_link_enc_avail(link->ctx->dc, 
link->link_enc->preferred_engine)) {
+   !link_enc_cfg_is_link_enc_avail(link->ctx->dc, 
link->link_enc->preferred_engine, link)) {
link->verified_link_cap = initial_link_settings;
return true;
}
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c
index 1cab4bf06abe..72b0f8594b4a 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c
@@ -488,16 +488,19 @@ struct link_encoder 
*link_enc_cfg_get_link_enc_used_by_stream(
return link_enc;
 }
 
-bool link_enc_cfg_is_link_enc_avail(struct dc *dc, enum engine_id eng_id)
+bool link_enc_cfg_is_link_enc_avail(struct dc *dc, enum engine_id eng_id, 
struct dc_link *link)
 {
bool is_avail = true;
int i;
 
-   /* Add assigned encoders to list. */
+   /* An encoder is not available if it has already been assigned to a 
different endpoint. */
for (i = 0; i < MAX_PIPES; i++) {
struct link_enc_assignment assignment = get_assignment(dc, i);
+   struct display_endpoint_id ep_id = (struct display_endpoint_id) 
{
+   .link_id = link->link_id,
+   .ep_type = link->ep_type};
 
-   if (assignment.valid && assignment.eng_id == eng_id) {
+   if (assignment.valid && assignment.eng_id == eng_id && 
!are_ep_ids_equal(_id, _id)) {
is_avail = false;
break;
}
diff --git a/drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h 
b/drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h
index 83b2199b2c83..10dcf6a5e9b1 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h
@@ -97,7 +97,7 @@ struct link_encoder *link_enc_cfg_get_link_enc_used_by_stream(
const struct dc_stream_state *stream);
 
 /* Return true if encoder available to use. */
-bool link_enc_cfg_is_link_enc_avail(struct dc *dc, enum engine_id eng_id);
+bool link_enc_cfg_is_link_enc_avail(struct dc *dc, enum engine_id eng_id, 
struct dc_link *link);
 
 /* Returns true if encoder assignments in supplied state pass validity checks. 
*/
 bool link_enc_cfg_validate(struct dc *dc, struct dc_state *state);
-- 
2.25.1

[PATCH 02/27] drm/amd/display: Clear encoder assignment for copied streams

2021-10-15 Thread Agustin Gutierrez

From: Jimmy Kizito 

[Why]
When copying a stream, the encoder assigned to it is copied too.
Encoder assignment should only happen when executing the encoder
assignment function link_encs_assign().

[How]
Clear the link encoder pointer for copied stream.

Reviewed-by: Meenakshikumar Somasundaram 
Reviewed-by: Jun Lei 
Acked-by: Agustin Gutierrez Sanchez 
Signed-off-by: Jimmy Kizito 
---
 drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index f0f54f4d3d9b..57cf4cb82370 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -202,6 +202,10 @@ struct dc_stream_state *dc_copy_stream(const struct 
dc_stream_state *stream)
new_stream->stream_id = new_stream->ctx->dc_stream_id_count;
new_stream->ctx->dc_stream_id_count++;
 
+   /* If using dynamic encoder assignment, wait till stream committed to 
assign encoder. */
+   if (new_stream->ctx->dc->res_pool->funcs->link_encs_assign)
+   new_stream->link_enc = NULL;
+
kref_init(_stream->refcount);
 
return new_stream;
-- 
2.25.1

[PATCH 01/27] drm/amd/display: Disable dpp root clock when not being used

2021-10-15 Thread Agustin Gutierrez

From: Jake Wang 

[Why & How]
Disable root clock for dpp when not being used.

Reviewed-by: Eric Yang 
Acked-by: Agustin Gutierrez Sanchez 
Signed-off-by: Jake Wang 
---
 .../display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c  |  5 ++-
 .../gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c | 41 ++-
 2 files changed, 44 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
index d7bf9283dc90..3fae1f1f028d 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
@@ -219,14 +219,17 @@ static void dcn31_update_clocks(struct clk_mgr 
*clk_mgr_base,
update_dispclk = true;
}
 
-   /* TODO: add back DTO programming when DPPCLK restore is fixed in FSDL*/
if (dpp_clock_lowered) {
// increase per DPP DTO before lowering global dppclk
+   dcn20_update_clocks_update_dpp_dto(clk_mgr, context, 
safe_to_lower);
dcn31_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
} else {
// increase global DPPCLK before lowering per DPP DTO
if (update_dppclk || update_dispclk)
dcn31_smu_set_dppclk(clk_mgr, 
clk_mgr_base->clks.dppclk_khz);
+   // always update dtos unless clock is lowered and not safe to 
lower
+   if (new_clocks->dppclk_khz >= 
dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)
+   dcn20_update_clocks_update_dpp_dto(clk_mgr, context, 
safe_to_lower);
}
 
// notify DMCUB of latest clocks
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c 
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
index 9896adf67425..582c500ecb49 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
@@ -42,6 +42,45 @@
 #define DC_LOGGER \
dccg->ctx->logger
 
+static void dccg31_update_dpp_dto(struct dccg *dccg, int dpp_inst, int 
req_dppclk)
+{
+   struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+
+   if (dccg->ref_dppclk && req_dppclk) {
+   int ref_dppclk = dccg->ref_dppclk;
+   int modulo, phase;
+
+   // phase / modulo = dpp pipe clk / dpp global clk
+   modulo = 0xff;   // use FF at the end
+   phase = ((modulo * req_dppclk) + ref_dppclk - 1) / ref_dppclk;
+
+   if (phase > 0xff) {
+   ASSERT(false);
+   phase = 0xff;
+   }
+
+   REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
+   DPPCLK0_DTO_PHASE, phase,
+   DPPCLK0_DTO_MODULO, modulo);
+   REG_UPDATE(DPPCLK_DTO_CTRL,
+   DPPCLK_DTO_ENABLE[dpp_inst], 1);
+   } else {
+   //DTO must be enabled to generate a 0Hz clock output
+   if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpp) {
+   REG_UPDATE(DPPCLK_DTO_CTRL,
+   DPPCLK_DTO_ENABLE[dpp_inst], 1);
+   REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
+   DPPCLK0_DTO_PHASE, 0,
+   DPPCLK0_DTO_MODULO, 1);
+   } else {
+   REG_UPDATE(DPPCLK_DTO_CTRL,
+   DPPCLK_DTO_ENABLE[dpp_inst], 0);
+   }
+   }
+   dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk;
+}
+
+
 void dccg31_set_dpstreamclk(
struct dccg *dccg,
enum hdmistreamclk_source src,
@@ -401,7 +440,7 @@ void dccg31_init(struct dccg *dccg)
 }
 
 static const struct dccg_funcs dccg31_funcs = {
-   .update_dpp_dto = dccg2_update_dpp_dto,
+   .update_dpp_dto = dccg31_update_dpp_dto,
.get_dccg_ref_freq = dccg31_get_dccg_ref_freq,
.dccg_init = dccg31_init,
.set_dpstreamclk = dccg31_set_dpstreamclk,
-- 
2.25.1

[PATCH 00/27] DC patchset for October 15

2021-10-15 Thread Agustin Gutierrez

This DC patchset brings improvements in multiple areas. In summary, we
highlight:

* Fix some issues such as DP2 problem, prefetch bandwidth calculation
for DCN3.1 and others.
* Increased Z9 latency and removed z10 save after dsc disable.
* Revert a couple of bad changes.
* Added missing PSR state patch.

Cc: Daniel Wheeler 
Cc: Mark Broadworth 

Agustin Gutierrez (2):
  Revert "drm/amd/display: Fix error in dmesg at boot"
  Revert "drm/amd/display: Add helper for blanking all dp displays"

Anthony Koo (2):
  drm/amd/display: Change initializer to single brace
  drm/amd/display: [FW Promotion] Release 0.0.88

Aric Cyr (2):
  drm/amd/display: Validate plane rects before use
  drm/amd/display: 3.2.157

Eric Yang (1):
  drm/amd/display: increase Z9 latency to workaround underflow in Z9

Hansen (1):
  drm/amd/display: Fix DP2 SE and LE SYMCLK selection for B0 PHY

Jake Wang (6):
  drm/amd/display: Disable dpp root clock when not being used
  drm/amd/display: Disable dsc root clock when not being used
  drm/amd/display: Disable dpstreamclk, symclk32_se, and symclk32_le
  drm/amd/display: Removed z10 save after dsc disable
  drm/amd/display: Moved dccg init to after bios golden init
  drm/amd/display: Disable hdmistream and hdmichar clocks

Jimmy Kizito (2):
  drm/amd/display: Clear encoder assignment for copied streams
  drm/amd/display: Do not skip link training on DP quick hot plug

Josip Pavic (1):
  drm/amd/display: do not compare integers of different widths

Lai, Derek (1):
  drm/amd/display: Removed power down on boot from DCN31

Michael Strauss (1):
  drm/amd/display: Clean Up VPG Low Mem Power

Mikita Lipski (1):
  drm/amd/display: Add missing PSR state

Nevenko Stupar (1):
  drm/amd/display: Add bios parser support for latest firmware_info

Nicholas Kazlauskas (2):
  drm/amd/display: Fix prefetch bandwidth calculation for DCN3.1
  drm/amd/display: Require immediate flip support for DCN3.1 planes

Nikola Cornij (2):
  drm/amd/display: Limit display scaling to up to true 4k for DCN 3.1
  drm/amd/display: Increase watermark latencies for DCN3.1

Wenjing Liu (2):
  drm/amd/display: add DP2.0 debug option to set MST_EN for SST stream
  drm/amd/display: correct apg audio channel enable golden value

 .../drm/amd/display/dc/bios/bios_parser2.c|  90 ++-
 .../display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c  |  21 +-
 drivers/gpu/drm/amd/display/dc/core/dc.c  |  10 -
 drivers/gpu/drm/amd/display/dc/core/dc_link.c |  63 +
 .../gpu/drm/amd/display/dc/core/dc_link_ddc.c |   2 +-
 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  |  32 +--
 .../drm/amd/display/dc/core/dc_link_enc_cfg.c |   9 +-
 .../gpu/drm/amd/display/dc/core/dc_resource.c |   5 +
 .../gpu/drm/amd/display/dc/core/dc_stream.c   |   4 +
 drivers/gpu/drm/amd/display/dc/dc.h   |   3 +-
 drivers/gpu/drm/amd/display/dc/dc_link.h  |   1 -
 drivers/gpu/drm/amd/display/dc/dc_types.h |   1 +
 drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c |   2 +
 .../display/dc/dce110/dce110_hw_sequencer.c   |  24 +-
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c |  49 +++-
 .../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h |  34 ++-
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.c|   4 +-
 .../drm/amd/display/dc/dcn30/dcn30_hwseq.c|  39 ++-
 .../gpu/drm/amd/display/dc/dcn31/dcn31_apg.c  |   2 +-
 .../gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c | 237 +-
 .../gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h |  34 ++-
 .../drm/amd/display/dc/dcn31/dcn31_hwseq.c| 114 +
 .../drm/amd/display/dc/dcn31/dcn31_resource.c |  17 +-
 .../dc/dml/dcn31/display_mode_vba_31.c|   6 +-
 drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h  |   9 +
 .../gpu/drm/amd/display/dc/inc/link_enc_cfg.h |   2 +-
 .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h   |   4 +-
 .../include/asic_reg/dcn/dcn_3_1_2_offset.h   |   2 +
 .../include/asic_reg/dcn/dcn_3_1_2_sh_mask.h  |   8 +
 29 files changed, 643 insertions(+), 185 deletions(-)

-- 
2.25.1

Re: [Intel-gfx] [PATCH 15/15] drm/i915: replace drm_detect_hdmi_monitor() with drm_display_info.is_hdmi

2021-10-15 Thread Claudio Suarez

On Fri, Oct 15, 2021 at 03:30:49PM +0300, Ville Syrjälä wrote:
> On Fri, Oct 15, 2021 at 01:37:13PM +0200, Claudio Suarez wrote:
> > Once EDID is parsed, the monitor HDMI support information is available
> > through drm_display_info.is_hdmi. Retriving the same information with
> > drm_detect_hdmi_monitor() is less efficient. Change to
> > drm_display_info.is_hdmi where possible.
> > 
> > This is a TODO task in Documentation/gpu/todo.rst
> > 
> > Signed-off-by: Claudio Suarez 
> > ---
> >  drivers/gpu/drm/i915/display/intel_connector.c | 5 +
> >  drivers/gpu/drm/i915/display/intel_connector.h | 1 +
> >  drivers/gpu/drm/i915/display/intel_hdmi.c  | 2 +-
> >  drivers/gpu/drm/i915/display/intel_sdvo.c  | 3 ++-
> >  4 files changed, 9 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_connector.c 
> > b/drivers/gpu/drm/i915/display/intel_connector.c
> > index 9bed1ccecea0..3346b55df6e1 100644
> > --- a/drivers/gpu/drm/i915/display/intel_connector.c
> > +++ b/drivers/gpu/drm/i915/display/intel_connector.c
> > @@ -213,6 +213,11 @@ int intel_ddc_get_modes(struct drm_connector 
> > *connector,
> > return ret;
> >  }
> >  
> > +bool intel_connector_is_hdmi_monitor(struct drm_connector *connector)
> > +{
> > +   return connector->display_info.is_hdmi;
> > +}
> > +
> >  static const struct drm_prop_enum_list force_audio_names[] = {
> > { HDMI_AUDIO_OFF_DVI, "force-dvi" },
> > { HDMI_AUDIO_OFF, "off" },
> > diff --git a/drivers/gpu/drm/i915/display/intel_connector.h 
> > b/drivers/gpu/drm/i915/display/intel_connector.h
> > index 661a37a3c6d8..ceda6e72ece6 100644
> > --- a/drivers/gpu/drm/i915/display/intel_connector.h
> > +++ b/drivers/gpu/drm/i915/display/intel_connector.h
> > @@ -27,6 +27,7 @@ enum pipe intel_connector_get_pipe(struct intel_connector 
> > *connector);
> >  int intel_connector_update_modes(struct drm_connector *connector,
> >  struct edid *edid);
> >  int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter 
> > *adapter);
> > +bool intel_connector_is_hdmi_monitor(struct drm_connector *connector);
> >  void intel_attach_force_audio_property(struct drm_connector *connector);
> >  void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
> >  void intel_attach_aspect_ratio_property(struct drm_connector *connector);
> > diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c 
> > b/drivers/gpu/drm/i915/display/intel_hdmi.c
> > index b04685bb6439..2b1d7c5bebdd 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> > @@ -2355,7 +2355,7 @@ intel_hdmi_set_edid(struct drm_connector *connector)
> > to_intel_connector(connector)->detect_edid = edid;
> > if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
> > intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
> > -   intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
> > +   intel_hdmi->has_hdmi_sink = 
> > intel_connector_is_hdmi_monitor(connector);
> 
> Hmm. Have we parse the EDID by this point actually? I don't think that
> was the case in the past but maybe it changed at some point.

Yes, I think so. The complete code is:


edid = drm_get_edid(connector, i2c);

if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
drm_dbg_kms(_priv->drm,
"HDMI GMBUS EDID read failed, retry using GPIO 
bit-banging\n");
intel_gmbus_force_bit(i2c, true);
edid = drm_get_edid(connector, i2c);
intel_gmbus_force_bit(i2c, false);
}

intel_hdmi_dp_dual_mode_detect(connector, edid != NULL);

intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);

to_intel_connector(connector)->detect_edid = edid;
if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
intel_hdmi->has_hdmi_sink = 
intel_connector_is_hdmi_monitor(connector);

The edid value comes from drm_get_edid(), first or second.
drm_get_edid() internally calls drm_connector_update_edid_property()
drm_connector_update_edid_property() calls drm_add_display_info() and parses 
the edid.
So, the edid is parsed.
I checked this and I read the docs many times because at the first time I felt 
something
was wrong. But that is the sequence of calls.

> 
> >  
> > connected = true;
> > }
> > diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c 
> > b/drivers/gpu/drm/i915/display/intel_sdvo.c
> > index 6cb27599ea03..a32279e4fee8 100644
> > --- a/drivers/gpu/drm/i915/display/intel_sdvo.c
> > +++ b/drivers/gpu/drm/i915/display/intel_sdvo.c
> > @@ -2060,8 +2060,9 @@ intel_sdvo_tmds_sink_detect(struct drm_connector 
> > *connector)
> > if (edid->input & DRM_EDID_INPUT_DIGITAL) {
> > status = connector_status_connected;
> >

Re: [Intel-gfx] [PATCH 15/15] drm/i915: replace drm_detect_hdmi_monitor() with drm_display_info.is_hdmi

2021-10-15 Thread Jani Nikula

On Fri, 15 Oct 2021, Ville Syrjälä  wrote:
> On Fri, Oct 15, 2021 at 03:44:48PM +0300, Jani Nikula wrote:
>> On Fri, 15 Oct 2021, Claudio Suarez  wrote:
>> > Once EDID is parsed, the monitor HDMI support information is available
>> > through drm_display_info.is_hdmi. Retriving the same information with
>> > drm_detect_hdmi_monitor() is less efficient. Change to
>> > drm_display_info.is_hdmi where possible.
>> >
>> > This is a TODO task in Documentation/gpu/todo.rst
>> >
>> > Signed-off-by: Claudio Suarez 
>> > ---
>> >  drivers/gpu/drm/i915/display/intel_connector.c | 5 +
>> >  drivers/gpu/drm/i915/display/intel_connector.h | 1 +
>> >  drivers/gpu/drm/i915/display/intel_hdmi.c  | 2 +-
>> >  drivers/gpu/drm/i915/display/intel_sdvo.c  | 3 ++-
>> >  4 files changed, 9 insertions(+), 2 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/display/intel_connector.c 
>> > b/drivers/gpu/drm/i915/display/intel_connector.c
>> > index 9bed1ccecea0..3346b55df6e1 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_connector.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_connector.c
>> > @@ -213,6 +213,11 @@ int intel_ddc_get_modes(struct drm_connector 
>> > *connector,
>> >return ret;
>> >  }
>> >  
>> > +bool intel_connector_is_hdmi_monitor(struct drm_connector *connector)
>> > +{
>> > +  return connector->display_info.is_hdmi;
>> > +}
>> > +
>> 
>> A helper like this belongs in drm, not i915. Seems useful in other
>> drivers too.
>
> Not sure it's actually helpful for i915. We end up having to root around
> in the display_info in a lot of places anyway. So a helper for single
> boolean seems a bit out of place perhaps.

*shrug*

Maybe it's just my frustration at the lack of interfaces and poking
around in the depths of nested structs and pointer chasing that's coming
through. You just need to change so many things if you want to later
refactor where "is hdmi" comes from and is stored.

Anyway, if a helper is being added like in this series, I think it
should be one helper in drm, not redundant copies in multiple
drivers. Or we should not have the helper(s) at all. One or the other,
not the worst of both worlds.


BR,
Jani.


-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [PATCH 02/15] drm/amdgpu: use drm_* functions instead of duplicated code in amdgpu driver

2021-10-15 Thread Harry Wentland




On 2021-10-15 07:37, Claudio Suarez wrote:
> a) Once EDID is parsed, the monitor HDMI support information is available
> through drm_display_info.is_hdmi. The amdgpu driver still calls
> drm_detect_hdmi_monitor() to retrieve the same information, which
> is less efficient. Change to drm_display_info.is_hdmi
> 
> This is a TODO task in Documentation/gpu/todo.rst
> 
> b) drm_display_info is updated by drm_get_edid() or
> drm_connector_update_edid_property(). In the amdgpu driver it is almost
> always updated when the edid is read in amdgpu_connector_get_edid(),
> but not always.  Change amdgpu_connector_get_edid() and
> amdgpu_connector_free_edid() to keep drm_display_info updated. This allows a)
> to work properly.
> 
> c) Use drm_edid_get_monitor_name() instead of duplicating the code that
> parses the EDID in dm_helpers_parse_edid_caps()
> 
> Also, remove the unused "struct dc_context *ctx" parameter in
> dm_helpers_parse_edid_caps()
> 

Thanks for this work.

The fact that you listed three separate changes in this commit
is a clear indication that this patch should be three separate
patches instead. Separating the functional bits from the straight
refactor will help with bisection if this leads to a regression.

All changes look reasonable to me, though. With this patch split
into three patches in the sequence (b), (c), then (a) this is
Reviewed-by: Harry Wentland 

Harry

> Signed-off-by: Claudio Suarez 
> ---
>  .../gpu/drm/amd/amdgpu/amdgpu_connectors.c| 23 +++
>  .../gpu/drm/amd/amdgpu/amdgpu_connectors.h|  2 +
>  drivers/gpu/drm/amd/amdgpu/amdgpu_display.c   |  2 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c  |  4 +-
>  .../gpu/drm/amd/amdgpu/atombios_encoders.c|  6 +--
>  .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  3 +-
>  .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 39 ++-
>  drivers/gpu/drm/amd/display/dc/core/dc.c  |  2 +-
>  drivers/gpu/drm/amd/display/dc/dm_helpers.h   |  2 +-
>  9 files changed, 39 insertions(+), 44 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
> index b9c11c2b2885..7b41a1120b70 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
> @@ -25,6 +25,7 @@
>   */
>  
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -108,7 +109,7 @@ int amdgpu_connector_get_monitor_bpc(struct drm_connector 
> *connector)
>   case DRM_MODE_CONNECTOR_DVII:
>   case DRM_MODE_CONNECTOR_HDMIB:
>   if (amdgpu_connector->use_digital) {
> - if 
> (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
> + if (amdgpu_connector_is_hdmi_monitor(connector)) {
>   if (connector->display_info.bpc)
>   bpc = connector->display_info.bpc;
>   }
> @@ -116,7 +117,7 @@ int amdgpu_connector_get_monitor_bpc(struct drm_connector 
> *connector)
>   break;
>   case DRM_MODE_CONNECTOR_DVID:
>   case DRM_MODE_CONNECTOR_HDMIA:
> - if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
> + if (amdgpu_connector_is_hdmi_monitor(connector)) {
>   if (connector->display_info.bpc)
>   bpc = connector->display_info.bpc;
>   }
> @@ -125,7 +126,7 @@ int amdgpu_connector_get_monitor_bpc(struct drm_connector 
> *connector)
>   dig_connector = amdgpu_connector->con_priv;
>   if ((dig_connector->dp_sink_type == 
> CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
>   (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) ||
> - drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
> + (amdgpu_connector_is_hdmi_monitor(connector))) {
>   if (connector->display_info.bpc)
>   bpc = connector->display_info.bpc;
>   }
> @@ -149,7 +150,7 @@ int amdgpu_connector_get_monitor_bpc(struct drm_connector 
> *connector)
>   break;
>   }
>  
> - if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
> + if (amdgpu_connector_is_hdmi_monitor(connector)) {
>   /*
>* Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc 
> doesn't make
>* much sense without support for > 12 bpc framebuffers. RGB 
> 4:4:4 at
> @@ -315,8 +316,10 @@ static void amdgpu_connector_get_edid(struct 
> drm_connector *connector)
>   if (!amdgpu_connector->edid) {
>   /* some laptops provide a hardcoded edid in rom for LCDs */
>   if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) ||
> -  (connector->connector_type == DRM_MODE_CONNECTOR_eDP)))
> +  (connector->connector_type == DRM_MODE_CONNECTOR_eDP))) {
>

[PATCH] drm/amdkfd: map gpu hive id to xgmi connected cpu

2021-10-15 Thread Jonathan Kim

ROCr needs to be able to identify all devices that have direct access to
fine grain memory, which should include CPUs that are connected to GPUs
over xGMI. The GPU hive ID can be mapped onto the CPU hive ID since the
CPU is part of the hive.

v3: avoid quadratic search by doing linear list read instead querying per
proximity id

v2: fixup to ensure all numa nodes get the hive id mapped

Signed-off-by: Jonathan Kim 
---
 drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 19 ++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
index 98cca5f2b27f..dd593ad0614a 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
@@ -1296,6 +1296,24 @@ int kfd_topology_add_device(struct kfd_dev *gpu)
 
proximity_domain = atomic_inc_return(_crat_proximity_domain);
 
+   adev = (struct amdgpu_device *)(gpu->kgd);
+
+   /* Include the CPU in xGMI hive if xGMI connected by assigning it the 
hive ID. */
+   if (gpu->hive_id && adev->gmc.xgmi.connected_to_cpu) {
+   struct kfd_topology_device *top_dev;
+
+   down_read(_lock);
+
+   list_for_each_entry(top_dev, _device_list, list) {
+   if (top_dev->gpu)
+   break;
+
+   top_dev->node_props.hive_id = gpu->hive_id;
+   }
+
+   up_read(_lock);
+   }
+
/* Check to see if this gpu device exists in the topology_device_list.
 * If so, assign the gpu to that device,
 * else create a Virtual CRAT for this gpu device and then parse that
@@ -1457,7 +1475,6 @@ int kfd_topology_add_device(struct kfd_dev *gpu)
dev->node_props.max_waves_per_simd = 10;
}
 
-   adev = (struct amdgpu_device *)(dev->gpu->kgd);
/* kfd only concerns sram ecc on GFX and HBM ecc on UMC */
dev->node_props.capability |=
((adev->ras_enabled & BIT(AMDGPU_RAS_BLOCK__GFX)) != 0) ?
-- 
2.25.1

RE: [PATCH] drm/amdgpu: output warning for unsupported ras error inject

2021-10-15 Thread Zhang, Hawking

[AMD Official Use Only]

Would it better create a function to interpret the RAS TA error? I expect more 
error status is available soon?

Regards,
Hawking
-Original Message-
From: Zhou1, Tao  
Sent: Friday, October 15, 2021 17:11
To: amd-gfx@lists.freedesktop.org; Clements, John ; 
Zhang, Hawking ; Yang, Stanley 
Cc: Zhou1, Tao 
Subject: [PATCH] drm/amdgpu: output warning for unsupported ras error inject

Output a warning message if RAS TA returns UNSUPPORTED_ERROR_INJ status.

Signed-off-by: Tao Zhou 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 3 +++  
drivers/gpu/drm/amd/amdgpu/ta_ras_if.h  | 7 ++-
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 88274c254c76..50d84deeb8f4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -1328,6 +1328,9 @@ int psp_ras_invoke(struct psp_context *psp, uint32_t 
ta_cmd_id)
 
if (ras_cmd->ras_status == TA_RAS_STATUS__ERROR_UNSUPPORTED_IP)
dev_warn(psp->adev->dev, "RAS WARNING: cmd failed due to 
unsupported ip\n");
+   else if (ras_cmd->ras_status == 
TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ)
+   dev_warn(psp->adev->dev,
+   "RAS WARNING: cmd failed due to unsupported 
error injection\n");
else if (ras_cmd->ras_status)
dev_warn(psp->adev->dev, "RAS WARNING: ras status = 
0x%X\n", ras_cmd->ras_status);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/ta_ras_if.h 
b/drivers/gpu/drm/amd/amdgpu/ta_ras_if.h
index de24a0a97d5e..5093826a43d1 100644
--- a/drivers/gpu/drm/amd/amdgpu/ta_ras_if.h
+++ b/drivers/gpu/drm/amd/amdgpu/ta_ras_if.h
@@ -59,7 +59,12 @@ enum ta_ras_status {
TA_RAS_STATUS__ERROR_SYS_DRV_REG_ACCESS = 0xA011,
TA_RAS_STATUS__ERROR_RAS_READ_WRITE = 0xA012,
TA_RAS_STATUS__ERROR_NULL_PTR   = 0xA013,
-   TA_RAS_STATUS__ERROR_UNSUPPORTED_IP = 0xA014
+   TA_RAS_STATUS__ERROR_UNSUPPORTED_IP = 0xA014,
+   TA_RAS_STATUS__ERROR_PCS_STATE_QUIET= 0xA015,
+   TA_RAS_STATUS__ERROR_PCS_STATE_ERROR= 0xA016,
+   TA_RAS_STATUS__ERROR_PCS_STATE_HANG = 0xA017,
+   TA_RAS_STATUS__ERROR_PCS_STATE_UNKNOWN  = 0xA018,
+   TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ  = 0xA019
 };
 
 enum ta_ras_block {
--
2.17.1

Re: [Intel-gfx] [PATCH 15/15] drm/i915: replace drm_detect_hdmi_monitor() with drm_display_info.is_hdmi

2021-10-15 Thread Ville Syrjälä

On Fri, Oct 15, 2021 at 03:44:48PM +0300, Jani Nikula wrote:
> On Fri, 15 Oct 2021, Claudio Suarez  wrote:
> > Once EDID is parsed, the monitor HDMI support information is available
> > through drm_display_info.is_hdmi. Retriving the same information with
> > drm_detect_hdmi_monitor() is less efficient. Change to
> > drm_display_info.is_hdmi where possible.
> >
> > This is a TODO task in Documentation/gpu/todo.rst
> >
> > Signed-off-by: Claudio Suarez 
> > ---
> >  drivers/gpu/drm/i915/display/intel_connector.c | 5 +
> >  drivers/gpu/drm/i915/display/intel_connector.h | 1 +
> >  drivers/gpu/drm/i915/display/intel_hdmi.c  | 2 +-
> >  drivers/gpu/drm/i915/display/intel_sdvo.c  | 3 ++-
> >  4 files changed, 9 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_connector.c 
> > b/drivers/gpu/drm/i915/display/intel_connector.c
> > index 9bed1ccecea0..3346b55df6e1 100644
> > --- a/drivers/gpu/drm/i915/display/intel_connector.c
> > +++ b/drivers/gpu/drm/i915/display/intel_connector.c
> > @@ -213,6 +213,11 @@ int intel_ddc_get_modes(struct drm_connector 
> > *connector,
> > return ret;
> >  }
> >  
> > +bool intel_connector_is_hdmi_monitor(struct drm_connector *connector)
> > +{
> > +   return connector->display_info.is_hdmi;
> > +}
> > +
> 
> A helper like this belongs in drm, not i915. Seems useful in other
> drivers too.

Not sure it's actually helpful for i915. We end up having to root around
in the display_info in a lot of places anyway. So a helper for single
boolean seems a bit out of place perhaps.

-- 
Ville Syrjälä
Intel

Re: [PATCH 15/15] drm/i915: replace drm_detect_hdmi_monitor() with drm_display_info.is_hdmi

2021-10-15 Thread Jani Nikula

On Fri, 15 Oct 2021, Claudio Suarez  wrote:
> Once EDID is parsed, the monitor HDMI support information is available
> through drm_display_info.is_hdmi. Retriving the same information with
> drm_detect_hdmi_monitor() is less efficient. Change to
> drm_display_info.is_hdmi where possible.
>
> This is a TODO task in Documentation/gpu/todo.rst
>
> Signed-off-by: Claudio Suarez 
> ---
>  drivers/gpu/drm/i915/display/intel_connector.c | 5 +
>  drivers/gpu/drm/i915/display/intel_connector.h | 1 +
>  drivers/gpu/drm/i915/display/intel_hdmi.c  | 2 +-
>  drivers/gpu/drm/i915/display/intel_sdvo.c  | 3 ++-
>  4 files changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_connector.c 
> b/drivers/gpu/drm/i915/display/intel_connector.c
> index 9bed1ccecea0..3346b55df6e1 100644
> --- a/drivers/gpu/drm/i915/display/intel_connector.c
> +++ b/drivers/gpu/drm/i915/display/intel_connector.c
> @@ -213,6 +213,11 @@ int intel_ddc_get_modes(struct drm_connector *connector,
>   return ret;
>  }
>  
> +bool intel_connector_is_hdmi_monitor(struct drm_connector *connector)
> +{
> + return connector->display_info.is_hdmi;
> +}
> +

A helper like this belongs in drm, not i915. Seems useful in other
drivers too.

BR,
Jani.

>  static const struct drm_prop_enum_list force_audio_names[] = {
>   { HDMI_AUDIO_OFF_DVI, "force-dvi" },
>   { HDMI_AUDIO_OFF, "off" },
> diff --git a/drivers/gpu/drm/i915/display/intel_connector.h 
> b/drivers/gpu/drm/i915/display/intel_connector.h
> index 661a37a3c6d8..ceda6e72ece6 100644
> --- a/drivers/gpu/drm/i915/display/intel_connector.h
> +++ b/drivers/gpu/drm/i915/display/intel_connector.h
> @@ -27,6 +27,7 @@ enum pipe intel_connector_get_pipe(struct intel_connector 
> *connector);
>  int intel_connector_update_modes(struct drm_connector *connector,
>struct edid *edid);
>  int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter 
> *adapter);
> +bool intel_connector_is_hdmi_monitor(struct drm_connector *connector);
>  void intel_attach_force_audio_property(struct drm_connector *connector);
>  void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
>  void intel_attach_aspect_ratio_property(struct drm_connector *connector);
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c 
> b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index b04685bb6439..2b1d7c5bebdd 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -2355,7 +2355,7 @@ intel_hdmi_set_edid(struct drm_connector *connector)
>   to_intel_connector(connector)->detect_edid = edid;
>   if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
>   intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
> - intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
> + intel_hdmi->has_hdmi_sink = 
> intel_connector_is_hdmi_monitor(connector);
>  
>   connected = true;
>   }
> diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c 
> b/drivers/gpu/drm/i915/display/intel_sdvo.c
> index 6cb27599ea03..a32279e4fee8 100644
> --- a/drivers/gpu/drm/i915/display/intel_sdvo.c
> +++ b/drivers/gpu/drm/i915/display/intel_sdvo.c
> @@ -2060,8 +2060,9 @@ intel_sdvo_tmds_sink_detect(struct drm_connector 
> *connector)
>   if (edid->input & DRM_EDID_INPUT_DIGITAL) {
>   status = connector_status_connected;
>   if (intel_sdvo_connector->is_hdmi) {
> - intel_sdvo->has_hdmi_monitor = 
> drm_detect_hdmi_monitor(edid);
>   intel_sdvo->has_hdmi_audio = 
> drm_detect_monitor_audio(edid);
> + intel_sdvo->has_hdmi_monitor =
> + 
> intel_connector_is_hdmi_monitor(connector);
>   }
>   } else
>   status = connector_status_disconnected;

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 15/15] drm/i915: replace drm_detect_hdmi_monitor() with drm_display_info.is_hdmi

2021-10-15 Thread Ville Syrjälä

On Fri, Oct 15, 2021 at 01:37:13PM +0200, Claudio Suarez wrote:
> Once EDID is parsed, the monitor HDMI support information is available
> through drm_display_info.is_hdmi. Retriving the same information with
> drm_detect_hdmi_monitor() is less efficient. Change to
> drm_display_info.is_hdmi where possible.
> 
> This is a TODO task in Documentation/gpu/todo.rst
> 
> Signed-off-by: Claudio Suarez 
> ---
>  drivers/gpu/drm/i915/display/intel_connector.c | 5 +
>  drivers/gpu/drm/i915/display/intel_connector.h | 1 +
>  drivers/gpu/drm/i915/display/intel_hdmi.c  | 2 +-
>  drivers/gpu/drm/i915/display/intel_sdvo.c  | 3 ++-
>  4 files changed, 9 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_connector.c 
> b/drivers/gpu/drm/i915/display/intel_connector.c
> index 9bed1ccecea0..3346b55df6e1 100644
> --- a/drivers/gpu/drm/i915/display/intel_connector.c
> +++ b/drivers/gpu/drm/i915/display/intel_connector.c
> @@ -213,6 +213,11 @@ int intel_ddc_get_modes(struct drm_connector *connector,
>   return ret;
>  }
>  
> +bool intel_connector_is_hdmi_monitor(struct drm_connector *connector)
> +{
> + return connector->display_info.is_hdmi;
> +}
> +
>  static const struct drm_prop_enum_list force_audio_names[] = {
>   { HDMI_AUDIO_OFF_DVI, "force-dvi" },
>   { HDMI_AUDIO_OFF, "off" },
> diff --git a/drivers/gpu/drm/i915/display/intel_connector.h 
> b/drivers/gpu/drm/i915/display/intel_connector.h
> index 661a37a3c6d8..ceda6e72ece6 100644
> --- a/drivers/gpu/drm/i915/display/intel_connector.h
> +++ b/drivers/gpu/drm/i915/display/intel_connector.h
> @@ -27,6 +27,7 @@ enum pipe intel_connector_get_pipe(struct intel_connector 
> *connector);
>  int intel_connector_update_modes(struct drm_connector *connector,
>struct edid *edid);
>  int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter 
> *adapter);
> +bool intel_connector_is_hdmi_monitor(struct drm_connector *connector);
>  void intel_attach_force_audio_property(struct drm_connector *connector);
>  void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
>  void intel_attach_aspect_ratio_property(struct drm_connector *connector);
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c 
> b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index b04685bb6439..2b1d7c5bebdd 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -2355,7 +2355,7 @@ intel_hdmi_set_edid(struct drm_connector *connector)
>   to_intel_connector(connector)->detect_edid = edid;
>   if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
>   intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
> - intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
> + intel_hdmi->has_hdmi_sink = 
> intel_connector_is_hdmi_monitor(connector);

Hmm. Have we parse the EDID by this point actually? I don't think that
was the case in the past but maybe it changed at some point.

>  
>   connected = true;
>   }
> diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c 
> b/drivers/gpu/drm/i915/display/intel_sdvo.c
> index 6cb27599ea03..a32279e4fee8 100644
> --- a/drivers/gpu/drm/i915/display/intel_sdvo.c
> +++ b/drivers/gpu/drm/i915/display/intel_sdvo.c
> @@ -2060,8 +2060,9 @@ intel_sdvo_tmds_sink_detect(struct drm_connector 
> *connector)
>   if (edid->input & DRM_EDID_INPUT_DIGITAL) {
>   status = connector_status_connected;
>   if (intel_sdvo_connector->is_hdmi) {
> - intel_sdvo->has_hdmi_monitor = 
> drm_detect_hdmi_monitor(edid);
>   intel_sdvo->has_hdmi_audio = 
> drm_detect_monitor_audio(edid);
> + intel_sdvo->has_hdmi_monitor =
> + 
> intel_connector_is_hdmi_monitor(connector);

FYI there's a third copy of this in intel_dp.c

>   }
>   } else
>   status = connector_status_disconnected;
> -- 
> 2.33.0
> 

-- 
Ville Syrjälä
Intel

[PATCH 03/15] drm/vc4: replace drm_detect_hdmi_monitor() with drm_display_info.is_hdmi

2021-10-15 Thread Claudio Suarez

Once EDID is parsed, the monitor HDMI support information is available
through drm_display_info.is_hdmi. Use this value instead of calling
drm_detect_hdmi_monitor() to avoid a second parse.

This is a TODO task in Documentation/gpu/todo.rst

Signed-off-by: Claudio Suarez 
---
 drivers/gpu/drm/vc4/vc4_hdmi.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index b4b4653fe301..d531e4c501eb 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -182,7 +182,8 @@ vc4_hdmi_connector_detect(struct drm_connector *connector, 
bool force)
 
if (edid) {
cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, 
edid);
-   vc4_hdmi->encoder.hdmi_monitor = 
drm_detect_hdmi_monitor(edid);
+   vc4_hdmi->encoder.hdmi_monitor =
+   connector->display_info.is_hdmi;
kfree(edid);
}
}
@@ -212,10 +213,9 @@ static int vc4_hdmi_connector_get_modes(struct 
drm_connector *connector)
if (!edid)
return -ENODEV;
 
-   vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid);
-
drm_connector_update_edid_property(connector, edid);
ret = drm_add_edid_modes(connector, edid);
+   vc4_encoder->hdmi_monitor = connector->display_info.is_hdmi;
kfree(edid);
 
if (vc4_hdmi->disable_4kp60) {
-- 
2.33.0

[PATCH 01/15] gpu/drm: make drm_add_edid_modes() consistent when updating connector->display_info

2021-10-15 Thread Claudio Suarez

According to the documentation, drm_add_edid_modes
"... Also fills out the _display_info structure and ELD in @connector
with any information which can be derived from the edid."

drm_add_edid_modes accepts a struct edid *edid parameter which may have a
value or may be null. When it is not null, connector->display_info and
connector->eld are updated according to the edid. When edid=NULL, only
connector->eld is reset. Reset connector->display_info to be consistent
and accurate.

Signed-off-by: Claudio Suarez 
---
 drivers/gpu/drm/drm_edid.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 6325877c5fd6..6cbe09b2357c 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -5358,10 +5358,12 @@ int drm_add_edid_modes(struct drm_connector *connector, 
struct edid *edid)
 
if (edid == NULL) {
clear_eld(connector);
+   drm_reset_display_info(connector);
return 0;
}
if (!drm_edid_is_valid(edid)) {
clear_eld(connector);
+   drm_reset_display_info(connector);
drm_warn(connector->dev, "%s: EDID invalid.\n",
 connector->name);
return 0;
-- 
2.33.0

[PATCH 05/15] drm/tegra: replace drm_detect_hdmi_monitor() with drm_display_info.is_hdmi

2021-10-15 Thread Claudio Suarez

Once EDID is parsed, the monitor HDMI support information is available
through drm_display_info.is_hdmi. Retriving the same information with
drm_detect_hdmi_monitor() is less efficient. Change to
drm_display_info.is_hdmi

Signed-off-by: Claudio Suarez 
---
 drivers/gpu/drm/tegra/hdmi.c | 6 +-
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/tegra/hdmi.c b/drivers/gpu/drm/tegra/hdmi.c
index e5d2a4026028..21571221b49b 100644
--- a/drivers/gpu/drm/tegra/hdmi.c
+++ b/drivers/gpu/drm/tegra/hdmi.c
@@ -831,14 +831,10 @@ static void tegra_hdmi_setup_tmds(struct tegra_hdmi *hdmi,
 
 static bool tegra_output_is_hdmi(struct tegra_output *output)
 {
-   struct edid *edid;
-
if (!output->connector.edid_blob_ptr)
return false;
 
-   edid = (struct edid *)output->connector.edid_blob_ptr->data;
-
-   return drm_detect_hdmi_monitor(edid);
+   return output->connector.display_info.is_hdmi;
 }
 
 static enum drm_connector_status
-- 
2.33.0

[PATCH 04/15] drm/radeon: replace drm_detect_hdmi_monitor() with drm_display_info.is_hdmi

2021-10-15 Thread Claudio Suarez

Once EDID is parsed, the monitor HDMI support information is available
through drm_display_info.is_hdmi. Retriving the same information is less
efficient. Change to drm_display_info.is_hdmi

This is a TODO task in Documentation/gpu/todo.rst

Also, correct an inacurracy or bug in
radeon_connector_get_edid()/radeon_connector_free_edid(). Two variables
have EDID data:
- struct radeon_connector.edid
- struct drm_connector.edid_blob_ptr
The second is updated by calling drm_connector_update_edid_property() or
drm_get_edid() - which internally calls drm_connector_update_edid_property().
drm_display_info.is_hdmi is updated when this function is called.
radeon_connector_get_edid() calls drm_get_edid() to update
drm_connector.edid_blob_ptr/drm_display_info only in some cases. Change it
to be always up to date, so drm_display_info is always correct.
As counterpart, reset these values in radeon_connector_free_edid().

This second change is necessary for the previous one to work properly.

Signed-off-by: Claudio Suarez 
---
 drivers/gpu/drm/radeon/atombios_encoders.c |  6 +++---
 drivers/gpu/drm/radeon/radeon_connectors.c | 20 ++--
 drivers/gpu/drm/radeon/radeon_display.c|  2 +-
 drivers/gpu/drm/radeon/radeon_encoders.c   |  4 ++--
 drivers/gpu/drm/radeon/radeon_mode.h   |  1 +
 5 files changed, 21 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c 
b/drivers/gpu/drm/radeon/atombios_encoders.c
index 0fce73b9a646..29a140732f71 100644
--- a/drivers/gpu/drm/radeon/atombios_encoders.c
+++ b/drivers/gpu/drm/radeon/atombios_encoders.c
@@ -713,7 +713,7 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
if (radeon_connector->use_digital &&
(radeon_connector->audio == RADEON_AUDIO_ENABLE))
return ATOM_ENCODER_MODE_HDMI;
-   else if 
(drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
+   else if (radeon_connector_is_hdmi_monitor(connector) &&
 (radeon_connector->audio == RADEON_AUDIO_AUTO))
return ATOM_ENCODER_MODE_HDMI;
else if (radeon_connector->use_digital)
@@ -732,7 +732,7 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
if (radeon_audio != 0) {
if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
return ATOM_ENCODER_MODE_HDMI;
-   else if 
(drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
+   else if (radeon_connector_is_hdmi_monitor(connector) &&
 (radeon_connector->audio == RADEON_AUDIO_AUTO))
return ATOM_ENCODER_MODE_HDMI;
else
@@ -756,7 +756,7 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
} else if (radeon_audio != 0) {
if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
return ATOM_ENCODER_MODE_HDMI;
-   else if 
(drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
+   else if (radeon_connector_is_hdmi_monitor(connector) &&
 (radeon_connector->audio == RADEON_AUDIO_AUTO))
return ATOM_ENCODER_MODE_HDMI;
else
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c 
b/drivers/gpu/drm/radeon/radeon_connectors.c
index 607ad5620bd9..0200f094467c 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -130,7 +130,7 @@ int radeon_get_monitor_bpc(struct drm_connector *connector)
case DRM_MODE_CONNECTOR_DVII:
case DRM_MODE_CONNECTOR_HDMIB:
if (radeon_connector->use_digital) {
-   if 
(drm_detect_hdmi_monitor(radeon_connector_edid(connector))) {
+   if (radeon_connector_is_hdmi_monitor(connector)) {
if (connector->display_info.bpc)
bpc = connector->display_info.bpc;
}
@@ -138,7 +138,7 @@ int radeon_get_monitor_bpc(struct drm_connector *connector)
break;
case DRM_MODE_CONNECTOR_DVID:
case DRM_MODE_CONNECTOR_HDMIA:
-   if (drm_detect_hdmi_monitor(radeon_connector_edid(connector))) {
+   if (radeon_connector_is_hdmi_monitor(connector)) {
if (connector->display_info.bpc)
bpc = connector->display_info.bpc;
}
@@ -147,7 +147,7 @@ int radeon_get_monitor_bpc(struct drm_connector *connector)
dig_connector = radeon_connector->con_priv;
if ((dig_connector->dp_sink_type == 
CONNECTOR_OBJECT_ID_DISPLAYPORT) ||

[PATCH 08/15] drm/msm: replace drm_detect_hdmi_monitor() with drm_display_info.is_hdmi

2021-10-15 Thread Claudio Suarez

Once EDID is parsed, the monitor HDMI support information is available
through drm_display_info.is_hdmi. Retriving the same information with
drm_detect_hdmi_monitor() is less efficient. Change to
drm_display_info.is_hdmi

Signed-off-by: Claudio Suarez 
---
 drivers/gpu/drm/msm/hdmi/hdmi_connector.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_connector.c 
b/drivers/gpu/drm/msm/hdmi/hdmi_connector.c
index 58707a1f3878..07585092f919 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi_connector.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi_connector.c
@@ -364,8 +364,8 @@ static int msm_hdmi_connector_get_modes(struct 
drm_connector *connector)
 
hdmi_write(hdmi, REG_HDMI_CTRL, hdmi_ctrl);
 
-   hdmi->hdmi_mode = drm_detect_hdmi_monitor(edid);
drm_connector_update_edid_property(connector, edid);
+   hdmi->hdmi_mode = connector->display_info.is_hdmi;
 
if (edid) {
ret = drm_add_edid_modes(connector, edid);
-- 
2.33.0

[PATCH 09/15] drm/sun4i: replace drm_detect_hdmi_monitor() with drm_display_info.is_hdmi

2021-10-15 Thread Claudio Suarez

Once EDID is parsed, the monitor HDMI support information is available
through drm_display_info.is_hdmi. Retriving the same information with
drm_detect_hdmi_monitor() is less efficient. Change to
drm_display_info.is_hdmi

Signed-off-by: Claudio Suarez 
---
 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c 
b/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
index 2f2c9f0a1071..f57bedbbeeb8 100644
--- a/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
+++ b/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
@@ -215,11 +215,11 @@ static int sun4i_hdmi_get_modes(struct drm_connector 
*connector)
if (!edid)
return 0;
 
-   hdmi->hdmi_monitor = drm_detect_hdmi_monitor(edid);
+   drm_connector_update_edid_property(connector, edid);
+   hdmi->hdmi_monitor = connector->display_info.is_hdmi;
DRM_DEBUG_DRIVER("Monitor is %s monitor\n",
 hdmi->hdmi_monitor ? "an HDMI" : "a DVI");
 
-   drm_connector_update_edid_property(connector, edid);
cec_s_phys_addr_from_edid(hdmi->cec_adap, edid);
ret = drm_add_edid_modes(connector, edid);
kfree(edid);
-- 
2.33.0

[PATCH 02/15] drm/amdgpu: use drm_* functions instead of duplicated code in amdgpu driver

2021-10-15 Thread Claudio Suarez

a) Once EDID is parsed, the monitor HDMI support information is available
through drm_display_info.is_hdmi. The amdgpu driver still calls
drm_detect_hdmi_monitor() to retrieve the same information, which
is less efficient. Change to drm_display_info.is_hdmi

This is a TODO task in Documentation/gpu/todo.rst

b) drm_display_info is updated by drm_get_edid() or
drm_connector_update_edid_property(). In the amdgpu driver it is almost
always updated when the edid is read in amdgpu_connector_get_edid(),
but not always.  Change amdgpu_connector_get_edid() and
amdgpu_connector_free_edid() to keep drm_display_info updated. This allows a)
to work properly.

c) Use drm_edid_get_monitor_name() instead of duplicating the code that
parses the EDID in dm_helpers_parse_edid_caps()

Also, remove the unused "struct dc_context *ctx" parameter in
dm_helpers_parse_edid_caps()

Signed-off-by: Claudio Suarez 
---
 .../gpu/drm/amd/amdgpu/amdgpu_connectors.c| 23 +++
 .../gpu/drm/amd/amdgpu/amdgpu_connectors.h|  2 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_display.c   |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c  |  4 +-
 .../gpu/drm/amd/amdgpu/atombios_encoders.c|  6 +--
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  3 +-
 .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 39 ++-
 drivers/gpu/drm/amd/display/dc/core/dc.c  |  2 +-
 drivers/gpu/drm/amd/display/dc/dm_helpers.h   |  2 +-
 9 files changed, 39 insertions(+), 44 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
index b9c11c2b2885..7b41a1120b70 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
@@ -25,6 +25,7 @@
  */
 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -108,7 +109,7 @@ int amdgpu_connector_get_monitor_bpc(struct drm_connector 
*connector)
case DRM_MODE_CONNECTOR_DVII:
case DRM_MODE_CONNECTOR_HDMIB:
if (amdgpu_connector->use_digital) {
-   if 
(drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
+   if (amdgpu_connector_is_hdmi_monitor(connector)) {
if (connector->display_info.bpc)
bpc = connector->display_info.bpc;
}
@@ -116,7 +117,7 @@ int amdgpu_connector_get_monitor_bpc(struct drm_connector 
*connector)
break;
case DRM_MODE_CONNECTOR_DVID:
case DRM_MODE_CONNECTOR_HDMIA:
-   if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
+   if (amdgpu_connector_is_hdmi_monitor(connector)) {
if (connector->display_info.bpc)
bpc = connector->display_info.bpc;
}
@@ -125,7 +126,7 @@ int amdgpu_connector_get_monitor_bpc(struct drm_connector 
*connector)
dig_connector = amdgpu_connector->con_priv;
if ((dig_connector->dp_sink_type == 
CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
(dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) ||
-   drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
+   (amdgpu_connector_is_hdmi_monitor(connector))) {
if (connector->display_info.bpc)
bpc = connector->display_info.bpc;
}
@@ -149,7 +150,7 @@ int amdgpu_connector_get_monitor_bpc(struct drm_connector 
*connector)
break;
}
 
-   if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
+   if (amdgpu_connector_is_hdmi_monitor(connector)) {
/*
 * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc 
doesn't make
 * much sense without support for > 12 bpc framebuffers. RGB 
4:4:4 at
@@ -315,8 +316,10 @@ static void amdgpu_connector_get_edid(struct drm_connector 
*connector)
if (!amdgpu_connector->edid) {
/* some laptops provide a hardcoded edid in rom for LCDs */
if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) ||
-(connector->connector_type == DRM_MODE_CONNECTOR_eDP)))
+(connector->connector_type == DRM_MODE_CONNECTOR_eDP))) {
amdgpu_connector->edid = 
amdgpu_connector_get_hardcoded_edid(adev);
+   drm_connector_update_edid_property(connector, 
amdgpu_connector->edid);
+   }
}
 }
 
@@ -326,6 +329,7 @@ static void amdgpu_connector_free_edid(struct drm_connector 
*connector)
 
kfree(amdgpu_connector->edid);
amdgpu_connector->edid = NULL;
+   drm_connector_update_edid_property(connector, NULL);
 }
 
 static int amdgpu_connector_ddc_get_modes(struct drm_connector *connector)
@@ -1170,7 +1174,7 @@ static enum drm_mode_status 
amdgpu_connector_dvi_mode_valid(struct drm_connector

[PATCH 00/15] replace drm_detect_hdmi_monitor() with drm_display_info.is_hdmi

2021-10-15 Thread Claudio Suarez

Copy from the TODO document Documentation/gpu/todo.rst 

===
Replace drm_detect_hdmi_monitor() with drm_display_info.is_hdmi
---

Once EDID is parsed, the monitor HDMI support information is available through
drm_display_info.is_hdmi. Many drivers still call drm_detect_hdmi_monitor() to
retrieve the same information, which is less efficient.

Audit each individual driver calling drm_detect_hdmi_monitor() and switch to
drm_display_info.is_hdmi if applicable.
=

I did it in two steps:
- check that drm_display_info has a correct value.
- in that case, replace drm_detect_hdmi_monitor() with drm_display_info.is_hdmi

Almost all occurrences of drm_detect_hdmi_monitor() could be changed. Some
small inconsistencies have been solved.

Stats:
 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c| 23 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.h|  2 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_display.c   |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c  |  4 ++--
 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c|  6 +++---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  3 +--
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 39 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c  |  2 +-
 drivers/gpu/drm/amd/display/dc/dm_helpers.h   |  2 +-
 drivers/gpu/drm/bridge/adv7511/adv7511_drv.c  |  2 +-
 drivers/gpu/drm/bridge/sii902x.c  |  2 +-
 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c |  2 +-
 drivers/gpu/drm/drm_edid.c|  2 ++
 drivers/gpu/drm/exynos/exynos_hdmi.c  |  6 --
 drivers/gpu/drm/gma500/cdv_intel_hdmi.c   |  3 ++-
 drivers/gpu/drm/gma500/psb_intel_sdvo.c   |  6 --
 drivers/gpu/drm/i915/display/intel_connector.c|  5 +
 drivers/gpu/drm/i915/display/intel_connector.h|  1 +
 drivers/gpu/drm/i915/display/intel_hdmi.c |  2 +-
 drivers/gpu/drm/i915/display/intel_sdvo.c |  3 ++-
 drivers/gpu/drm/msm/hdmi/hdmi_connector.c |  2 +-
 drivers/gpu/drm/nouveau/dispnv50/disp.c   |  4 ++--
 drivers/gpu/drm/nouveau/dispnv50/head.c   |  8 +---
 drivers/gpu/drm/nouveau/nouveau_connector.c   |  2 +-
 drivers/gpu/drm/nouveau/nouveau_connector.h   |  6 ++
 drivers/gpu/drm/radeon/atombios_encoders.c|  6 +++---
 drivers/gpu/drm/radeon/radeon_connectors.c| 20 
++--
 drivers/gpu/drm/radeon/radeon_display.c   |  2 +-
 drivers/gpu/drm/radeon/radeon_encoders.c  |  4 ++--
 drivers/gpu/drm/radeon/radeon_mode.h  |  1 +
 drivers/gpu/drm/rockchip/inno_hdmi.c  |  4 ++--
 drivers/gpu/drm/rockchip/rk3066_hdmi.c|  2 +-
 drivers/gpu/drm/sti/sti_hdmi.c| 10 ++
 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c|  4 ++--
 drivers/gpu/drm/tegra/hdmi.c  |  6 +-
 drivers/gpu/drm/vc4/vc4_hdmi.c|  6 +++---
 drivers/gpu/drm/zte/zx_hdmi.c |  4 ++--
 37 files changed, 112 insertions(+), 96 deletions(-)

Best regards.
Claudio Suarez

[PATCH 10/15] drm/sti: replace drm_detect_hdmi_monitor() with drm_display_info.is_hdmi

2021-10-15 Thread Claudio Suarez

Once EDID is parsed, the monitor HDMI support information is available
through drm_display_info.is_hdmi. Retriving the same information with
drm_detect_hdmi_monitor() is less efficient. Change to
drm_display_info.is_hdmi

Signed-off-by: Claudio Suarez 
---
 drivers/gpu/drm/sti/sti_hdmi.c | 10 ++
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/sti/sti_hdmi.c b/drivers/gpu/drm/sti/sti_hdmi.c
index f3ace11209dd..3f8b04a1407e 100644
--- a/drivers/gpu/drm/sti/sti_hdmi.c
+++ b/drivers/gpu/drm/sti/sti_hdmi.c
@@ -984,14 +984,16 @@ static int sti_hdmi_connector_get_modes(struct 
drm_connector *connector)
if (!edid)
goto fail;
 
-   hdmi->hdmi_monitor = drm_detect_hdmi_monitor(edid);
-   DRM_DEBUG_KMS("%s : %dx%d cm\n",
- (hdmi->hdmi_monitor ? "hdmi monitor" : "dvi monitor"),
- edid->width_cm, edid->height_cm);
cec_notifier_set_phys_addr_from_edid(hdmi->notifier, edid);
 
count = drm_add_edid_modes(connector, edid);
+
+   /* This updates connector->display_info */
drm_connector_update_edid_property(connector, edid);
+   hdmi->hdmi_monitor = connector->display_info.is_hdmi;
+   DRM_DEBUG_KMS("%s : %dx%d cm\n",
+ (hdmi->hdmi_monitor ? "hdmi monitor" : "dvi monitor"),
+ edid->width_cm, edid->height_cm);
 
kfree(edid);
return count;
-- 
2.33.0

[PATCH 12/15] drm/rockchip: replace drm_detect_hdmi_monitor() with drm_display_info.is_hdmi

2021-10-15 Thread Claudio Suarez

Once EDID is parsed, the monitor HDMI support information is available
through drm_display_info.is_hdmi. Retriving the same information with
drm_detect_hdmi_monitor() is less efficient. Change to
drm_display_info.is_hdmi

Signed-off-by: Claudio Suarez 
---
 drivers/gpu/drm/rockchip/inno_hdmi.c   | 4 ++--
 drivers/gpu/drm/rockchip/rk3066_hdmi.c | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/inno_hdmi.c 
b/drivers/gpu/drm/rockchip/inno_hdmi.c
index 7afdc54eb3ec..d479f230833e 100644
--- a/drivers/gpu/drm/rockchip/inno_hdmi.c
+++ b/drivers/gpu/drm/rockchip/inno_hdmi.c
@@ -553,9 +553,9 @@ static int inno_hdmi_connector_get_modes(struct 
drm_connector *connector)
 
edid = drm_get_edid(connector, hdmi->ddc);
if (edid) {
-   hdmi->hdmi_data.sink_is_hdmi = drm_detect_hdmi_monitor(edid);
-   hdmi->hdmi_data.sink_has_audio = drm_detect_monitor_audio(edid);
drm_connector_update_edid_property(connector, edid);
+   hdmi->hdmi_data.sink_is_hdmi = connector->display_info.is_hdmi;
+   hdmi->hdmi_data.sink_has_audio = drm_detect_monitor_audio(edid);
ret = drm_add_edid_modes(connector, edid);
kfree(edid);
}
diff --git a/drivers/gpu/drm/rockchip/rk3066_hdmi.c 
b/drivers/gpu/drm/rockchip/rk3066_hdmi.c
index 1c546c3a8998..03aaae39cf61 100644
--- a/drivers/gpu/drm/rockchip/rk3066_hdmi.c
+++ b/drivers/gpu/drm/rockchip/rk3066_hdmi.c
@@ -472,8 +472,8 @@ static int rk3066_hdmi_connector_get_modes(struct 
drm_connector *connector)
 
edid = drm_get_edid(connector, hdmi->ddc);
if (edid) {
-   hdmi->hdmi_data.sink_is_hdmi = drm_detect_hdmi_monitor(edid);
drm_connector_update_edid_property(connector, edid);
+   hdmi->hdmi_data.sink_is_hdmi = connector->display_info.is_hdmi;
ret = drm_add_edid_modes(connector, edid);
kfree(edid);
}
-- 
2.33.0

[PATCH 11/15] drm/zte: replace drm_detect_hdmi_monitor() with drm_display_info.is_hdmi

2021-10-15 Thread Claudio Suarez

Once EDID is parsed, the monitor HDMI support information is available
through drm_display_info.is_hdmi. Retriving the same information with
drm_detect_hdmi_monitor() is less efficient. Change to
drm_display_info.is_hdmi

Signed-off-by: Claudio Suarez 
---
 drivers/gpu/drm/zte/zx_hdmi.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/zte/zx_hdmi.c b/drivers/gpu/drm/zte/zx_hdmi.c
index cd79ca0a92a9..7df682d90723 100644
--- a/drivers/gpu/drm/zte/zx_hdmi.c
+++ b/drivers/gpu/drm/zte/zx_hdmi.c
@@ -265,9 +265,9 @@ static int zx_hdmi_connector_get_modes(struct drm_connector 
*connector)
if (!edid)
return 0;
 
-   hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid);
-   hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
drm_connector_update_edid_property(connector, edid);
+   hdmi->sink_is_hdmi = connector->display_info.is_hdmi;
+   hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
ret = drm_add_edid_modes(connector, edid);
kfree(edid);
 
-- 
2.33.0

[PATCH 13/15] drm/bridge: replace drm_detect_hdmi_monitor() with drm_display_info.is_hdmi

2021-10-15 Thread Claudio Suarez

Once EDID is parsed, the monitor HDMI support information is available
through drm_display_info.is_hdmi. Retriving the same information with
drm_detect_hdmi_monitor() is less efficient. Change to
drm_display_info.is_hdmi where possible

Signed-off-by: Claudio Suarez 
---
 drivers/gpu/drm/bridge/adv7511/adv7511_drv.c | 2 +-
 drivers/gpu/drm/bridge/sii902x.c | 2 +-
 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c| 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c 
b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
index 76555ae64e9c..f6891280a58d 100644
--- a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
+++ b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
@@ -617,7 +617,7 @@ static struct edid *adv7511_get_edid(struct adv7511 
*adv7511,
__adv7511_power_off(adv7511);
 
adv7511_set_config_csc(adv7511, connector, adv7511->rgb,
-  drm_detect_hdmi_monitor(edid));
+  connector->display_info.is_hdmi);
 
cec_s_phys_addr_from_edid(adv7511->cec_adap, edid);
 
diff --git a/drivers/gpu/drm/bridge/sii902x.c b/drivers/gpu/drm/bridge/sii902x.c
index 89558e581530..5719be0a03c7 100644
--- a/drivers/gpu/drm/bridge/sii902x.c
+++ b/drivers/gpu/drm/bridge/sii902x.c
@@ -283,7 +283,7 @@ static int sii902x_get_modes(struct drm_connector 
*connector)
edid = drm_get_edid(connector, sii902x->i2cmux->adapter[0]);
drm_connector_update_edid_property(connector, edid);
if (edid) {
-   if (drm_detect_hdmi_monitor(edid))
+   if (connector->display_info.is_hdmi)
output_mode = SII902X_SYS_CTRL_OUTPUT_HDMI;
 
num = drm_add_edid_modes(connector, edid);
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
index f08d0fded61f..33f0afb6b646 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
@@ -2359,7 +2359,7 @@ static struct edid *dw_hdmi_get_edid(struct dw_hdmi *hdmi,
dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
edid->width_cm, edid->height_cm);
 
-   hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid);
+   hdmi->sink_is_hdmi = connector->display_info.is_hdmi;
hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
 
return edid;
-- 
2.33.0

[PATCH 14/15] drm/nouveau: replace drm_detect_hdmi_monitor() with drm_display_info.is_hdmi

2021-10-15 Thread Claudio Suarez

Once EDID is parsed, the monitor HDMI support information is available
through drm_display_info.is_hdmi. Retriving the same information with
drm_detect_hdmi_monitor() is less efficient. Change to
drm_display_info.is_hdmi

Signed-off-by: Claudio Suarez 
---
 drivers/gpu/drm/nouveau/dispnv50/disp.c | 4 ++--
 drivers/gpu/drm/nouveau/dispnv50/head.c | 8 +---
 drivers/gpu/drm/nouveau/nouveau_connector.c | 2 +-
 drivers/gpu/drm/nouveau/nouveau_connector.h | 6 ++
 4 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c 
b/drivers/gpu/drm/nouveau/dispnv50/disp.c
index d7b9f7f8c9e3..fadd58b015d6 100644
--- a/drivers/gpu/drm/nouveau/dispnv50/disp.c
+++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c
@@ -844,7 +844,7 @@ nv50_hdmi_enable(struct drm_encoder *encoder, struct 
nouveau_crtc *nv_crtc,
int ret;
int size;
 
-   if (!drm_detect_hdmi_monitor(nv_connector->edid))
+   if (nouveau_connector_is_hdmi_monitor(_connector->base))
return;
 
hdmi = _connector->base.display_info.hdmi;
@@ -1745,7 +1745,7 @@ nv50_sor_atomic_enable(struct drm_encoder *encoder, 
struct drm_atomic_state *sta
 */
if (mode->clock >= 165000 &&
nv_encoder->dcb->duallink_possible &&
-   !drm_detect_hdmi_monitor(nv_connector->edid))
+   
!nouveau_connector_is_hdmi_monitor(_connector->base))
proto = 
NV507D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS;
} else {
proto = NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B;
diff --git a/drivers/gpu/drm/nouveau/dispnv50/head.c 
b/drivers/gpu/drm/nouveau/dispnv50/head.c
index d66f97280282..0a138bfb8f32 100644
--- a/drivers/gpu/drm/nouveau/dispnv50/head.c
+++ b/drivers/gpu/drm/nouveau/dispnv50/head.c
@@ -127,14 +127,8 @@ nv50_head_atomic_check_view(struct nv50_head_atom *armh,
struct drm_display_mode *omode = >state.adjusted_mode;
struct drm_display_mode *umode = >state.mode;
int mode = asyc->scaler.mode;
-   struct edid *edid;
int umode_vdisplay, omode_hdisplay, omode_vdisplay;
 
-   if (connector->edid_blob_ptr)
-   edid = (struct edid *)connector->edid_blob_ptr->data;
-   else
-   edid = NULL;
-
if (!asyc->scaler.full) {
if (mode == DRM_MODE_SCALE_NONE)
omode = umode;
@@ -162,7 +156,7 @@ nv50_head_atomic_check_view(struct nv50_head_atom *armh,
 */
if ((asyc->scaler.underscan.mode == UNDERSCAN_ON ||
(asyc->scaler.underscan.mode == UNDERSCAN_AUTO &&
-drm_detect_hdmi_monitor(edid {
+nouveau_connector_is_hdmi_monitor(connector {
u32 bX = asyc->scaler.underscan.hborder;
u32 bY = asyc->scaler.underscan.vborder;
u32 r = (asyh->view.oH << 19) / asyh->view.oW;
diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c 
b/drivers/gpu/drm/nouveau/nouveau_connector.c
index 22b83a6577eb..211543373b72 100644
--- a/drivers/gpu/drm/nouveau/nouveau_connector.c
+++ b/drivers/gpu/drm/nouveau/nouveau_connector.c
@@ -1010,7 +1010,7 @@ get_tmds_link_bandwidth(struct drm_connector *connector)
unsigned duallink_scale =
nouveau_duallink && nv_encoder->dcb->duallink_possible ? 2 : 1;
 
-   if (drm_detect_hdmi_monitor(nv_connector->edid)) {
+   if (nouveau_connector_is_hdmi_monitor(connector)) {
info = _connector->base.display_info;
duallink_scale = 1;
}
diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.h 
b/drivers/gpu/drm/nouveau/nouveau_connector.h
index 40f90e353540..299f3a3b2331 100644
--- a/drivers/gpu/drm/nouveau/nouveau_connector.h
+++ b/drivers/gpu/drm/nouveau/nouveau_connector.h
@@ -167,6 +167,12 @@ nouveau_connector_is_mst(struct drm_connector *connector)
return encoder->encoder_type == DRM_MODE_ENCODER_DPMST;
 }
 
+static inline bool
+nouveau_connector_is_hdmi_monitor(struct drm_connector *connector)
+{
+   return connector->display_info.is_hdmi;
+}
+
 #define nouveau_for_each_non_mst_connector_iter(connector, iter) \
drm_for_each_connector_iter(connector, iter) \
for_each_if(!nouveau_connector_is_mst(connector))
-- 
2.33.0

[PATCH 15/15] drm/i915: replace drm_detect_hdmi_monitor() with drm_display_info.is_hdmi

2021-10-15 Thread Claudio Suarez

Once EDID is parsed, the monitor HDMI support information is available
through drm_display_info.is_hdmi. Retriving the same information with
drm_detect_hdmi_monitor() is less efficient. Change to
drm_display_info.is_hdmi where possible.

This is a TODO task in Documentation/gpu/todo.rst

Signed-off-by: Claudio Suarez 
---
 drivers/gpu/drm/i915/display/intel_connector.c | 5 +
 drivers/gpu/drm/i915/display/intel_connector.h | 1 +
 drivers/gpu/drm/i915/display/intel_hdmi.c  | 2 +-
 drivers/gpu/drm/i915/display/intel_sdvo.c  | 3 ++-
 4 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_connector.c 
b/drivers/gpu/drm/i915/display/intel_connector.c
index 9bed1ccecea0..3346b55df6e1 100644
--- a/drivers/gpu/drm/i915/display/intel_connector.c
+++ b/drivers/gpu/drm/i915/display/intel_connector.c
@@ -213,6 +213,11 @@ int intel_ddc_get_modes(struct drm_connector *connector,
return ret;
 }
 
+bool intel_connector_is_hdmi_monitor(struct drm_connector *connector)
+{
+   return connector->display_info.is_hdmi;
+}
+
 static const struct drm_prop_enum_list force_audio_names[] = {
{ HDMI_AUDIO_OFF_DVI, "force-dvi" },
{ HDMI_AUDIO_OFF, "off" },
diff --git a/drivers/gpu/drm/i915/display/intel_connector.h 
b/drivers/gpu/drm/i915/display/intel_connector.h
index 661a37a3c6d8..ceda6e72ece6 100644
--- a/drivers/gpu/drm/i915/display/intel_connector.h
+++ b/drivers/gpu/drm/i915/display/intel_connector.h
@@ -27,6 +27,7 @@ enum pipe intel_connector_get_pipe(struct intel_connector 
*connector);
 int intel_connector_update_modes(struct drm_connector *connector,
 struct edid *edid);
 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
+bool intel_connector_is_hdmi_monitor(struct drm_connector *connector);
 void intel_attach_force_audio_property(struct drm_connector *connector);
 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c 
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index b04685bb6439..2b1d7c5bebdd 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2355,7 +2355,7 @@ intel_hdmi_set_edid(struct drm_connector *connector)
to_intel_connector(connector)->detect_edid = edid;
if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
-   intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
+   intel_hdmi->has_hdmi_sink = 
intel_connector_is_hdmi_monitor(connector);
 
connected = true;
}
diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c 
b/drivers/gpu/drm/i915/display/intel_sdvo.c
index 6cb27599ea03..a32279e4fee8 100644
--- a/drivers/gpu/drm/i915/display/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/display/intel_sdvo.c
@@ -2060,8 +2060,9 @@ intel_sdvo_tmds_sink_detect(struct drm_connector 
*connector)
if (edid->input & DRM_EDID_INPUT_DIGITAL) {
status = connector_status_connected;
if (intel_sdvo_connector->is_hdmi) {
-   intel_sdvo->has_hdmi_monitor = 
drm_detect_hdmi_monitor(edid);
intel_sdvo->has_hdmi_audio = 
drm_detect_monitor_audio(edid);
+   intel_sdvo->has_hdmi_monitor =
+   
intel_connector_is_hdmi_monitor(connector);
}
} else
status = connector_status_disconnected;
-- 
2.33.0

[PATCH 06/15] drm/gma500: replace drm_detect_hdmi_monitor() with drm_display_info.is_hdmi

2021-10-15 Thread Claudio Suarez

Once EDID is parsed, the monitor HDMI support information is available
through drm_display_info.is_hdmi. Retriving the same information with
drm_detect_hdmi_monitor() is less efficient. Change to
drm_display_info.is_hdmi

Signed-off-by: Claudio Suarez 
---
 drivers/gpu/drm/gma500/cdv_intel_hdmi.c | 3 ++-
 drivers/gpu/drm/gma500/psb_intel_sdvo.c | 6 --
 2 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/gma500/cdv_intel_hdmi.c 
b/drivers/gpu/drm/gma500/cdv_intel_hdmi.c
index e525689f84f0..d9db5d52d52e 100644
--- a/drivers/gpu/drm/gma500/cdv_intel_hdmi.c
+++ b/drivers/gpu/drm/gma500/cdv_intel_hdmi.c
@@ -130,6 +130,7 @@ static enum drm_connector_status cdv_hdmi_detect(
struct edid *edid = NULL;
enum drm_connector_status status = connector_status_disconnected;
 
+   /* This updates connector->display_info */
edid = drm_get_edid(connector, _encoder->i2c_bus->adapter);
 
hdmi_priv->has_hdmi_sink = false;
@@ -138,7 +139,7 @@ static enum drm_connector_status cdv_hdmi_detect(
if (edid->input & DRM_EDID_INPUT_DIGITAL) {
status = connector_status_connected;
hdmi_priv->has_hdmi_sink =
-   drm_detect_hdmi_monitor(edid);
+   connector->display_info.is_hdmi;
hdmi_priv->has_hdmi_audio =
drm_detect_monitor_audio(edid);
}
diff --git a/drivers/gpu/drm/gma500/psb_intel_sdvo.c 
b/drivers/gpu/drm/gma500/psb_intel_sdvo.c
index 355da2856389..5ef49d17de98 100644
--- a/drivers/gpu/drm/gma500/psb_intel_sdvo.c
+++ b/drivers/gpu/drm/gma500/psb_intel_sdvo.c
@@ -1266,8 +1266,10 @@ psb_intel_sdvo_hdmi_sink_detect(struct drm_connector 
*connector)
if (edid->input & DRM_EDID_INPUT_DIGITAL) {
status = connector_status_connected;
if (psb_intel_sdvo->is_hdmi) {
-   psb_intel_sdvo->has_hdmi_monitor = 
drm_detect_hdmi_monitor(edid);
-   psb_intel_sdvo->has_hdmi_audio = 
drm_detect_monitor_audio(edid);
+   psb_intel_sdvo->has_hdmi_monitor =
+   connector->display_info.is_hdmi;
+   psb_intel_sdvo->has_hdmi_audio =
+   drm_detect_monitor_audio(edid);
}
} else
status = connector_status_disconnected;
-- 
2.33.0

[PATCH 07/15] drm/exynos: replace drm_detect_hdmi_monitor() with drm_display_info.is_hdmi

2021-10-15 Thread Claudio Suarez

Once EDID is parsed, the monitor HDMI support information is available
through drm_display_info.is_hdmi. Retriving the same information with
drm_detect_hdmi_monitor() is less efficient. Change to
drm_display_info.is_hdmi

Signed-off-by: Claudio Suarez 
---
 drivers/gpu/drm/exynos/exynos_hdmi.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c 
b/drivers/gpu/drm/exynos/exynos_hdmi.c
index 7655142a4651..a563d6386abe 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -893,12 +893,14 @@ static int hdmi_get_modes(struct drm_connector *connector)
if (!edid)
return -ENODEV;
 
-   hdata->dvi_mode = !drm_detect_hdmi_monitor(edid);
+   /* This updates connector->display_info */
+   drm_connector_update_edid_property(connector, edid);
+
+   hdata->dvi_mode = !connector->display_info.is_hdmi;
DRM_DEV_DEBUG_KMS(hdata->dev, "%s : width[%d] x height[%d]\n",
  (hdata->dvi_mode ? "dvi monitor" : "hdmi monitor"),
  edid->width_cm, edid->height_cm);
 
-   drm_connector_update_edid_property(connector, edid);
cec_notifier_set_phys_addr_from_edid(hdata->notifier, edid);
 
ret = drm_add_edid_modes(connector, edid);
-- 
2.33.0

Re: [PATCH 01/15] gpu/drm: make drm_add_edid_modes() consistent when updating connector->display_info

2021-10-15 Thread Ville Syrjälä

On Fri, Oct 15, 2021 at 01:36:59PM +0200, Claudio Suarez wrote:
> According to the documentation, drm_add_edid_modes
> "... Also fills out the _display_info structure and ELD in @connector
> with any information which can be derived from the edid."
> 
> drm_add_edid_modes accepts a struct edid *edid parameter which may have a
> value or may be null. When it is not null, connector->display_info and
> connector->eld are updated according to the edid. When edid=NULL, only
> connector->eld is reset. Reset connector->display_info to be consistent
> and accurate.
> 
> Signed-off-by: Claudio Suarez 
> ---
>  drivers/gpu/drm/drm_edid.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index 6325877c5fd6..6cbe09b2357c 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -5358,10 +5358,12 @@ int drm_add_edid_modes(struct drm_connector 
> *connector, struct edid *edid)
>  
>   if (edid == NULL) {
>   clear_eld(connector);
> + drm_reset_display_info(connector);
>   return 0;
>   }
>   if (!drm_edid_is_valid(edid)) {
>   clear_eld(connector);
> + drm_reset_display_info(connector);

Looks easier if you pull both of those out from these branches and
just call them unconditionally at the start.

>   drm_warn(connector->dev, "%s: EDID invalid.\n",
>connector->name);
>   return 0;
> -- 
> 2.33.0
> 
> 

-- 
Ville Syrjälä
Intel

RE: bf756fb833cb ("drm/amdgpu: add missing cleanups for Polaris12 UVD/VCE on suspend")

2021-10-15 Thread Quan, Evan

[AMD Official Use Only]



> -Original Message-
> From: Borislav Petkov 
> Sent: Thursday, October 14, 2021 5:01 PM
> To: Quan, Evan 
> Cc: Alex Deucher ; amd-gfx list  g...@lists.freedesktop.org>; LKML ; Deucher,
> Alexander ; Pan, Xinhui
> ; Chen, Guchun 
> Subject: Re: bf756fb833cb ("drm/amdgpu: add missing cleanups for Polaris12
> UVD/VCE on suspend")
> 
> On Thu, Oct 14, 2021 at 02:02:48AM +, Quan, Evan wrote:
> > [Quan, Evan] Yes, but not(apply them) at the same time. One by one as
> you did before.
> > - try the patch1 first
> 
> Ok, first patch worked fine.
> 
> > - undo the changes of patch1 and try patch2
> 
> Did that, worked fine too except after the first resume cycle, the video 
> didn't
> continue playing.
> 
> Then I restarted the video and did a couple more suspend cycles to see if it
> would not continue again. In the subsequent tries it would resume fine and
> the video would continue playing too.
> 
> So I'm going to chalk that single case of halted video with the second patch 
> to
> a resume glitch or so.
> 
> Btw, I don't have pm-suspend on that box but I did suspend to RAM
> assuming this is what you wanted, which is done as root with two
> commands:
> 
> # echo "suspend" > /sys/power/disk
> # echo "mem" > /sys/power/state
[Quan, Evan] Yes, that also works.
> 
> If you want me to do more extensive testing, just shoot.
[Quan, Evan] Thanks! That's enough for now. I will prepare an official solution 
for the issue.

BR
Evan
> 
> HTH.
> 
> --
> Regards/Gruss,
> Boris.
> 
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpeo
> ple.kernel.org%2Ftglx%2Fnotes-about-
> netiquettedata=04%7C01%7CEvan.Quan%40amd.com%7C08df3d5453
> d64ad40dfa08d98ef119ec%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C
> 0%7C637697988457790715%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLj
> AwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000
> sdata=zmFVlmUBv6byoDYyUhSgk9J9Zmvexz5IqG7xBxwiR3M%3Drese
> rved=0

[PATCH] drm/amdgpu: output warning for unsupported ras error inject

2021-10-15 Thread Tao Zhou

Output a warning message if RAS TA returns UNSUPPORTED_ERROR_INJ status.

Signed-off-by: Tao Zhou 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 3 +++
 drivers/gpu/drm/amd/amdgpu/ta_ras_if.h  | 7 ++-
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 88274c254c76..50d84deeb8f4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -1328,6 +1328,9 @@ int psp_ras_invoke(struct psp_context *psp, uint32_t 
ta_cmd_id)
 
if (ras_cmd->ras_status == TA_RAS_STATUS__ERROR_UNSUPPORTED_IP)
dev_warn(psp->adev->dev, "RAS WARNING: cmd failed due to 
unsupported ip\n");
+   else if (ras_cmd->ras_status == 
TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ)
+   dev_warn(psp->adev->dev,
+   "RAS WARNING: cmd failed due to unsupported 
error injection\n");
else if (ras_cmd->ras_status)
dev_warn(psp->adev->dev, "RAS WARNING: ras status = 
0x%X\n", ras_cmd->ras_status);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/ta_ras_if.h 
b/drivers/gpu/drm/amd/amdgpu/ta_ras_if.h
index de24a0a97d5e..5093826a43d1 100644
--- a/drivers/gpu/drm/amd/amdgpu/ta_ras_if.h
+++ b/drivers/gpu/drm/amd/amdgpu/ta_ras_if.h
@@ -59,7 +59,12 @@ enum ta_ras_status {
TA_RAS_STATUS__ERROR_SYS_DRV_REG_ACCESS = 0xA011,
TA_RAS_STATUS__ERROR_RAS_READ_WRITE = 0xA012,
TA_RAS_STATUS__ERROR_NULL_PTR   = 0xA013,
-   TA_RAS_STATUS__ERROR_UNSUPPORTED_IP = 0xA014
+   TA_RAS_STATUS__ERROR_UNSUPPORTED_IP = 0xA014,
+   TA_RAS_STATUS__ERROR_PCS_STATE_QUIET= 0xA015,
+   TA_RAS_STATUS__ERROR_PCS_STATE_ERROR= 0xA016,
+   TA_RAS_STATUS__ERROR_PCS_STATE_HANG = 0xA017,
+   TA_RAS_STATUS__ERROR_PCS_STATE_UNKNOWN  = 0xA018,
+   TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ  = 0xA019
 };
 
 enum ta_ras_block {
-- 
2.17.1

[PATCH 2/2] drm/amdkfd: Remove cu mask from struct queue_properties

2021-10-15 Thread Lang Yu

Actually, cu_mask has been copied to mqd memory and
don't have to persist in queue_properties. Remove it
from queue_properties.

Use struct queue_update_info to wrap queue_properties
and cu mask, then pass it to update queue operation.

Signed-off-by: Lang Yu 
---
 drivers/gpu/drm/amd/amdkfd/kfd_chardev.c  | 41 +++---
 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c |  1 -
 .../gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c  | 10 ++--
 .../gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c  | 10 ++--
 .../gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c   | 10 ++--
 .../gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c   | 10 ++--
 drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 22 ++--
 .../amd/amdkfd/kfd_process_queue_manager.c| 56 ++-
 8 files changed, 80 insertions(+), 80 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
index 9317a2e238d0..baa5de9dd361 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
@@ -371,7 +371,7 @@ static int kfd_ioctl_update_queue(struct file *filp, struct 
kfd_process *p,
 {
int retval;
struct kfd_ioctl_update_queue_args *args = data;
-   struct queue_properties properties;
+   struct queue_update_info qinfo = {0};
 
if (args->queue_percentage > KFD_MAX_QUEUE_PERCENTAGE) {
pr_err("Queue percentage must be between 0 to 
KFD_MAX_QUEUE_PERCENTAGE\n");
@@ -395,17 +395,18 @@ static int kfd_ioctl_update_queue(struct file *filp, 
struct kfd_process *p,
return -EINVAL;
}
 
-   properties.queue_address = args->ring_base_address;
-   properties.queue_size = args->ring_size;
-   properties.queue_percent = args->queue_percentage;
-   properties.priority = args->queue_priority;
+   qinfo.properties.queue_address = args->ring_base_address;
+   qinfo.properties.queue_size = args->ring_size;
+   qinfo.properties.queue_percent = args->queue_percentage;
+   qinfo.properties.priority = args->queue_priority;
+   qinfo.update_flag = UPDATE_FLAG_PROPERTITY;
 
pr_debug("Updating queue id %d for pasid 0x%x\n",
args->queue_id, p->pasid);
 
mutex_lock(>mutex);
 
-   retval = pqm_update_queue(>pqm, args->queue_id, );
+   retval = pqm_update_queue(>pqm, args->queue_id, );
 
mutex_unlock(>mutex);
 
@@ -418,7 +419,7 @@ static int kfd_ioctl_set_cu_mask(struct file *filp, struct 
kfd_process *p,
int retval;
const int max_num_cus = 1024;
struct kfd_ioctl_set_cu_mask_args *args = data;
-   struct queue_properties properties;
+   struct queue_update_info qinfo = {0};
uint32_t __user *cu_mask_ptr = (uint32_t __user *)args->cu_mask_ptr;
size_t cu_mask_size = sizeof(uint32_t) * (args->num_cu_mask / 32);
 
@@ -428,8 +429,8 @@ static int kfd_ioctl_set_cu_mask(struct file *filp, struct 
kfd_process *p,
return -EINVAL;
}
 
-   properties.cu_mask_count = args->num_cu_mask;
-   if (properties.cu_mask_count == 0) {
+   qinfo.cu_mask.count = args->num_cu_mask;
+   if (qinfo.cu_mask.count == 0) {
pr_debug("CU mask cannot be 0");
return -EINVAL;
}
@@ -438,31 +439,33 @@ static int kfd_ioctl_set_cu_mask(struct file *filp, 
struct kfd_process *p,
 * limit of max_num_cus bits.  We can then just drop any CU mask bits
 * past max_num_cus bits and just use the first max_num_cus bits.
 */
-   if (properties.cu_mask_count > max_num_cus) {
+   if (qinfo.cu_mask.count > max_num_cus) {
pr_debug("CU mask cannot be greater than 1024 bits");
-   properties.cu_mask_count = max_num_cus;
+   qinfo.cu_mask.count = max_num_cus;
cu_mask_size = sizeof(uint32_t) * (max_num_cus/32);
}
 
-   properties.cu_mask = kzalloc(cu_mask_size, GFP_KERNEL);
-   if (!properties.cu_mask)
+   qinfo.cu_mask.ptr = kzalloc(cu_mask_size, GFP_KERNEL);
+   if (!qinfo.cu_mask.ptr)
return -ENOMEM;
 
-   retval = copy_from_user(properties.cu_mask, cu_mask_ptr, cu_mask_size);
+   retval = copy_from_user(qinfo.cu_mask.ptr, cu_mask_ptr, cu_mask_size);
if (retval) {
pr_debug("Could not copy CU mask from userspace");
-   kfree(properties.cu_mask);
-   return -EFAULT;
+   retval = -EFAULT;
+   goto out;
}
 
+   qinfo.update_flag = UPDATE_FLAG_CU_MASK;
+
mutex_lock(>mutex);
 
-   retval = pqm_set_cu_mask(>pqm, args->queue_id, );
+   retval = pqm_update_queue(>pqm, args->queue_id, );
 
mutex_unlock(>mutex);
 
-   if (retval)
-   kfree(properties.cu_mask);
+out:
+   kfree(qinfo.cu_mask.ptr);
 
return retval;
 }
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c

[PATCH 1/2] drm/amdkfd: Add an optional argument into update queue operation

2021-10-15 Thread Lang Yu

Currently, queue is updated with data stored in queue_properties.
And all allocated resource in queue_properties will not be freed
until the queue is destroyed.

But some properties(e.g., cu mask) bring some memory management
headaches(e.g., memory leak) and make code complex. Actually they
don't have to persist in queue_properties.

So add an argument into update queue to pass such properties and
remove them from queue_properties.

Signed-off-by: Lang Yu 
---
 .../drm/amd/amdkfd/kfd_device_queue_manager.c |  4 ++--
 .../drm/amd/amdkfd/kfd_device_queue_manager.h |  2 +-
 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h  |  2 +-
 .../gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c  | 18 +++
 .../gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c  |  8 +++
 .../gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c   |  8 +++
 .../gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c   | 22 +--
 .../amd/amdkfd/kfd_process_queue_manager.c|  6 ++---
 8 files changed, 35 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index f8fce9d05f50..7f6f4937eedb 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -557,7 +557,7 @@ static int destroy_queue_nocpsch(struct 
device_queue_manager *dqm,
return retval;
 }
 
-static int update_queue(struct device_queue_manager *dqm, struct queue *q)
+static int update_queue(struct device_queue_manager *dqm, struct queue *q, 
void *args)
 {
int retval = 0;
struct mqd_manager *mqd_mgr;
@@ -605,7 +605,7 @@ static int update_queue(struct device_queue_manager *dqm, 
struct queue *q)
}
}
 
-   mqd_mgr->update_mqd(mqd_mgr, q->mqd, >properties);
+   mqd_mgr->update_mqd(mqd_mgr, q->mqd, >properties, args);
 
/*
 * check active state vs. the previous state and modify
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h 
b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
index c8719682c4da..08cfc2a2fdbb 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
@@ -93,7 +93,7 @@ struct device_queue_manager_ops {
struct queue *q);
 
int (*update_queue)(struct device_queue_manager *dqm,
-   struct queue *q);
+   struct queue *q, void *args);
 
int (*register_process)(struct device_queue_manager *dqm,
struct qcm_process_device *qpd);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h 
b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h
index 6e6918ccedfd..6ddf93629b8c 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h
@@ -80,7 +80,7 @@ struct mqd_manager {
struct mm_struct *mms);
 
void(*update_mqd)(struct mqd_manager *mm, void *mqd,
-   struct queue_properties *q);
+   struct queue_properties *q, void *args);
 
int (*destroy_mqd)(struct mqd_manager *mm, void *mqd,
enum kfd_preempt_type type,
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
index 064914e1e8d6..8bb2fd4cba41 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
@@ -135,7 +135,7 @@ static void init_mqd(struct mqd_manager *mm, void **mqd,
*mqd = m;
if (gart_addr)
*gart_addr = addr;
-   mm->update_mqd(mm, m, q);
+   mm->update_mqd(mm, m, q, NULL);
 }
 
 static void init_mqd_sdma(struct mqd_manager *mm, void **mqd,
@@ -152,7 +152,7 @@ static void init_mqd_sdma(struct mqd_manager *mm, void 
**mqd,
if (gart_addr)
*gart_addr = mqd_mem_obj->gpu_addr;
 
-   mm->update_mqd(mm, m, q);
+   mm->update_mqd(mm, m, q, NULL);
 }
 
 static void free_mqd(struct mqd_manager *mm, void *mqd,
@@ -185,7 +185,7 @@ static int load_mqd_sdma(struct mqd_manager *mm, void *mqd,
 }
 
 static void __update_mqd(struct mqd_manager *mm, void *mqd,
-   struct queue_properties *q, unsigned int atc_bit)
+   struct queue_properties *q, void *args, unsigned int 
atc_bit)
 {
struct cik_mqd *m;
 
@@ -221,9 +221,9 @@ static void __update_mqd(struct mqd_manager *mm, void *mqd,
 }
 
 static void update_mqd(struct mqd_manager *mm, void *mqd,
-   struct queue_properties *q)
+   struct queue_properties *q, void *args)
 {
-   __update_mqd(mm, mqd, q, 1);
+   __update_mqd(mm, mqd, q, args, 1);
 }
 
 static uint32_t read_doorbell_id(void *mqd)
@@ -234,13 +234,13 @@ static uint32_t read_doorbell_id(void *mqd)
 }

RE: [PATCH] drm/amdgpu: load PSP RL in resume path

2021-10-15 Thread Zhang, Hawking

[AMD Official Use Only]

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: amd-gfx  On Behalf Of Tao Zhou
Sent: Friday, October 15, 2021 15:28
To: amd-gfx@lists.freedesktop.org; Zhang, Hawking ; 
Clements, John ; Yang, Stanley 
Cc: Zhou1, Tao 
Subject: [PATCH] drm/amdgpu: load PSP RL in resume path

Some registers' access will fail without PSP RL after resume.

Signed-off-by: Tao Zhou 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 2bfe0682e0e6..88274c254c76 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -2623,6 +2623,12 @@ static int psp_resume(void *handle)
goto failed;
}
 
+   ret = psp_rl_load(adev);
+   if (ret) {
+   dev_err(adev->dev, "PSP load RL failed!\n");
+   goto failed;
+   }
+
if (adev->gmc.xgmi.num_physical_nodes > 1) {
ret = psp_xgmi_initialize(psp, false, true);
/* Warning the XGMI seesion initialize failure
-- 
2.17.1

[PATCH] drm/amdgpu: load PSP RL in resume path

2021-10-15 Thread Tao Zhou

Some registers' access will fail without PSP RL after resume.

Signed-off-by: Tao Zhou 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 2bfe0682e0e6..88274c254c76 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -2623,6 +2623,12 @@ static int psp_resume(void *handle)
goto failed;
}
 
+   ret = psp_rl_load(adev);
+   if (ret) {
+   dev_err(adev->dev, "PSP load RL failed!\n");
+   goto failed;
+   }
+
if (adev->gmc.xgmi.num_physical_nodes > 1) {
ret = psp_xgmi_initialize(psp, false, true);
/* Warning the XGMI seesion initialize failure
-- 
2.17.1

Re: [PATCH v1 1/2] ext4/xfs: add page refcount helper

2021-10-15 Thread Jason Gunthorpe

On Thu, Oct 14, 2021 at 10:39:27AM -0500, Alex Sierra wrote:
> From: Ralph Campbell 
> 
> There are several places where ZONE_DEVICE struct pages assume a reference
> count == 1 means the page is idle and free. Instead of open coding this,
> add a helper function to hide this detail.
> 
> Signed-off-by: Ralph Campbell 
> Signed-off-by: Alex Sierra 
> Reviewed-by: Christoph Hellwig 
> Acked-by: Theodore Ts'o 
> Acked-by: Darrick J. Wong 
> ---
> v3:
> [AS]: rename dax_layout_is_idle_page func to dax_page_unused
> 
> v4:
> [AS]: This ref count functionality was missing on fuse/dax.c.
> ---
>  fs/dax.c|  4 ++--
>  fs/ext4/inode.c |  5 +
>  fs/fuse/dax.c   |  4 +---
>  fs/xfs/xfs_file.c   |  4 +---
>  include/linux/dax.h | 10 ++
>  5 files changed, 15 insertions(+), 12 deletions(-)

Reviewed-by: Jason Gunthorpe 

Jason

Re: [PATCH v1 1/2] ext4/xfs: add page refcount helper

2021-10-15 Thread Matthew Wilcox

On Thu, Oct 14, 2021 at 10:39:27AM -0500, Alex Sierra wrote:
> From: Ralph Campbell 
> 
> There are several places where ZONE_DEVICE struct pages assume a reference
> count == 1 means the page is idle and free. Instead of open coding this,
> add a helper function to hide this detail.
> 
> Signed-off-by: Ralph Campbell 
> Signed-off-by: Alex Sierra 
> Reviewed-by: Christoph Hellwig 
> Acked-by: Theodore Ts'o 
> Acked-by: Darrick J. Wong 

Reviewed-by: Matthew Wilcox (Oracle)

Re: [PATCH v1 2/2] mm: remove extra ZONE_DEVICE struct page refcount

2021-10-15 Thread Matthew Wilcox

On Thu, Oct 14, 2021 at 10:39:28AM -0500, Alex Sierra wrote:
> From: Ralph Campbell 
> 
> ZONE_DEVICE struct pages have an extra reference count that complicates the
> code for put_page() and several places in the kernel that need to check the
> reference count to see that a page is not being used (gup, compaction,
> migration, etc.). Clean up the code so the reference count doesn't need to
> be treated specially for ZONE_DEVICE.
> 
> Signed-off-by: Ralph Campbell 
> Signed-off-by: Alex Sierra 
> Reviewed-by: Christoph Hellwig 

Reviewed-by: Matthew Wilcox (Oracle)

[PATCH] amdgpu: replace snprintf in show functions with sysfs_emit

2021-10-15 Thread Qing Wang

show() must not use snprintf() when formatting the value to be
returned to user space.

Fix the following coccicheck warning:
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c:427: 
WARNING: use scnprintf or sprintf.

Signed-off-by: Qing Wang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index 2834981..faf4011 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -424,7 +424,7 @@ static ssize_t show_##name(struct device *dev,  
\
struct drm_device *ddev = dev_get_drvdata(dev); \
struct amdgpu_device *adev = drm_to_adev(ddev); \
\
-   return snprintf(buf, PAGE_SIZE, "0x%08x\n", adev->field);   \
+   return sysfs_emit(buf, "0x%08x\n", adev->field);\
 }  \
 static DEVICE_ATTR(name, mode, show_##name, NULL)
 
-- 
2.7.4

Re: [PATCH v1 2/2] mm: remove extra ZONE_DEVICE struct page refcount

2021-10-15 Thread Jason Gunthorpe

On Thu, Oct 14, 2021 at 10:35:27AM -0700, Ralph Campbell wrote:

> I ran xfstests-dev using the kernel boot option to "fake" a pmem device
> when I first posted this patch. The tests ran OK (or at least the same
> tests passed with and without my patch). 

Hmm. I know nothing of xfstests but 

tests/generic/413

Looks kind of like it might cover this situation?

Did it run for you?

Jason

Re: [PATCH v1 2/2] mm: remove extra ZONE_DEVICE struct page refcount

2021-10-15 Thread Jason Gunthorpe

On Thu, Oct 14, 2021 at 10:39:28AM -0500, Alex Sierra wrote:
> From: Ralph Campbell 
> 
> ZONE_DEVICE struct pages have an extra reference count that complicates the
> code for put_page() and several places in the kernel that need to check the
> reference count to see that a page is not being used (gup, compaction,
> migration, etc.). Clean up the code so the reference count doesn't need to
> be treated specially for ZONE_DEVICE.
> 
> Signed-off-by: Ralph Campbell 
> Signed-off-by: Alex Sierra 
> Reviewed-by: Christoph Hellwig 
> ---
> v2:
> AS: merged this patch in linux 5.11 version
> 
> v5:
> AS: add condition at try_grab_page to check for the zone device type, while
> page ref counter is checked less/equal to zero. In case of device zone, pages
> ref counter are initialized to zero.
> 
> v7:
> AS: fix condition at try_grab_page added at v5, is invalid. It supposed
> to fix xfstests/generic/413 test, however, there's a known issue on
> this test where DAX mapped area DIO to non-DAX expect to fail.
> https://patchwork.kernel.org/project/fstests/patch/1489463960-3579-1-git-send-email-xz...@redhat.com
> This condition was removed after rebase over patch series
> https://lore.kernel.org/r/20210813044133.1536842-4-jhubb...@nvidia.com
> ---
>  arch/powerpc/kvm/book3s_hv_uvmem.c |  2 +-
>  drivers/gpu/drm/nouveau/nouveau_dmem.c |  2 +-
>  fs/dax.c   |  4 +-
>  include/linux/dax.h|  2 +-
>  include/linux/memremap.h   |  7 +--
>  include/linux/mm.h | 11 
>  lib/test_hmm.c |  2 +-
>  mm/internal.h  |  8 +++
>  mm/memcontrol.c|  6 +--
>  mm/memremap.c  | 69 +++---
>  mm/migrate.c   |  5 --
>  mm/page_alloc.c|  3 ++
>  mm/swap.c  | 45 ++---
>  13 files changed, 46 insertions(+), 120 deletions(-)

Has anyone tested this with FSDAX? Does get_user_pages() on fsdax
backed memory still work?

What refcount value does the struct pages have when they are installed
in the PTEs? Remember a 0 refcount will make all the get_user_pages()
fail.

I'm looking at the call path starting in ext4_punch_hole() and I would
expect to see something manipulating the page ref count before
the ext4_break_layouts() call path gets to the dax_page_unused() test.

All I see is we go into unmap_mapping_pages() - that would normally
put back the page references held by PTEs but insert_pfn() has this:

if (pfn_t_devmap(pfn))
entry = pte_mkdevmap(pfn_t_pte(pfn, prot));

And:

static inline pte_t pte_mkdevmap(pte_t pte)
{
return pte_set_flags(pte, _PAGE_SPECIAL|_PAGE_DEVMAP);
}

Which interacts with vm_normal_page():

if (pte_devmap(pte))
return NULL;

To disable that refcounting?

So... I have a feeling this will have PTEs pointing to 0 refcount
pages? Unless FSDAX is !pte_devmap which is not the case, right?

This seems further confirmed by this comment:

/*
 * If we race get_user_pages_fast() here either we'll see the
 * elevated page count in the iteration and wait, or
 * get_user_pages_fast() will see that the page it took a reference
 * against is no longer mapped in the page tables and bail to the
 * get_user_pages() slow path.  The slow path is protected by
 * pte_lock() and pmd_lock(). New references are not taken without
 * holding those locks, and unmap_mapping_pages() will not zero the
 * pte or pmd without holding the respective lock, so we are
 * guaranteed to either see new references or prevent new
 * references from being established.
 */

Which seems to explain this scheme relies on unmap_mapping_pages() to
fence GUP_fast, not on GUP_fast observing 0 refcounts when it should
stop.

This seems like it would be properly fixed by using normal page
refcounting for PTEs - ie stop using special for these pages?

Does anyone know why devmap is pte_special anyhow?

> +void free_zone_device_page(struct page *page)
> +{
> + switch (page->pgmap->type) {
> + case MEMORY_DEVICE_PRIVATE:
> + free_device_page(page);
> + return;
> + case MEMORY_DEVICE_FS_DAX:
> + /* notify page idle */
> + wake_up_var(>_refcount);
> + return;

It is not for this series, but I wonder if we should just always call
ops->page_free and have free_device_page() logic in that callback for
the non-fs-dax cases?

For instance where is the mem_cgroup_charge() call to pair with the
mem_cgroup_uncharge() in free_device_page()?

Isn't cgroup charging (or not) the responsibility of the "allocator"
eg the pgmap_ops owner?

Jason

[PATCH v2] drm/amdkfd: Separate pinned BOs destruction from general routine

2021-10-15 Thread Lang Yu

Currently, all kfd BOs use same destruction routine. But pinned
BOs are not unpinned properly. Separate them from general routine.

v2 (Felix):
Add safeguard to prevent user space from freeing signal BO.
Kunmap signal BO in the event of setting event page error.
Just kunmap signal BO to avoid duplicating the code.

Signed-off-by: Lang Yu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h|   2 +
 .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c  |  10 ++
 drivers/gpu/drm/amd/amdkfd/kfd_chardev.c  |  31 +++--
 drivers/gpu/drm/amd/amdkfd/kfd_priv.h |   3 +
 drivers/gpu/drm/amd/amdkfd/kfd_process.c  | 110 +-
 5 files changed, 119 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index 69de31754907..751557af09bb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -279,6 +279,8 @@ int amdgpu_amdkfd_gpuvm_sync_memory(
struct kgd_dev *kgd, struct kgd_mem *mem, bool intr);
 int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct kgd_dev *kgd,
struct kgd_mem *mem, void **kptr, uint64_t *size);
+void amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(struct kgd_dev *kgd, struct 
kgd_mem *mem);
+
 int amdgpu_amdkfd_gpuvm_restore_process_bos(void *process_info,
struct dma_fence **ef);
 int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct kgd_dev *kgd,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index cdf46bd0d8d5..4969763c2e47 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -1871,6 +1871,16 @@ int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct 
kgd_dev *kgd,
return ret;
 }
 
+void amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(struct kgd_dev *kgd, struct 
kgd_mem *mem)
+{
+   struct amdgpu_bo *bo = mem->bo;
+
+   amdgpu_bo_reserve(bo, true);
+   amdgpu_bo_kunmap(bo);
+   amdgpu_bo_unpin(bo);
+   amdgpu_bo_unreserve(bo);
+}
+
 int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct kgd_dev *kgd,
  struct kfd_vm_fault_info *mem)
 {
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
index f1e7edeb4e6b..9317a2e238d0 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
@@ -1011,11 +1011,6 @@ static int kfd_ioctl_create_event(struct file *filp, 
struct kfd_process *p,
void *mem, *kern_addr;
uint64_t size;
 
-   if (p->signal_page) {
-   pr_err("Event page is already set\n");
-   return -EINVAL;
-   }
-
kfd = kfd_device_by_id(GET_GPU_ID(args->event_page_offset));
if (!kfd) {
pr_err("Getting device by id failed in %s\n", __func__);
@@ -1023,6 +1018,13 @@ static int kfd_ioctl_create_event(struct file *filp, 
struct kfd_process *p,
}
 
mutex_lock(>mutex);
+
+   if (p->signal_page) {
+   pr_err("Event page is already set\n");
+   err = -EINVAL;
+   goto out_unlock;
+   }
+
pdd = kfd_bind_process_to_device(kfd, p);
if (IS_ERR(pdd)) {
err = PTR_ERR(pdd);
@@ -1037,20 +1039,24 @@ static int kfd_ioctl_create_event(struct file *filp, 
struct kfd_process *p,
err = -EINVAL;
goto out_unlock;
}
-   mutex_unlock(>mutex);
 
err = amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(kfd->kgd,
mem, _addr, );
if (err) {
pr_err("Failed to map event page to kernel\n");
-   return err;
+   goto out_unlock;
}
 
err = kfd_event_page_set(p, kern_addr, size);
if (err) {
pr_err("Failed to set event page\n");
-   return err;
+   amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(kfd->kgd, 
mem);
+   goto out_unlock;
}
+
+   p->signal_handle = args->event_page_offset;
+
+   mutex_unlock(>mutex);
}
 
err = kfd_event_create(filp, p, args->event_type,
@@ -1368,6 +1374,15 @@ static int kfd_ioctl_free_memory_of_gpu(struct file 
*filep,
return -EINVAL;
 
mutex_lock(>mutex);
+   /*
+* Safeguard to prevent user space from freeing signal BO.
+* It will be freed at process termination.
+*/
+   if (p->signal_handle && (p->signal_handle == args->handle)) {
+   pr_err("Free

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