Re: [PATCH 1/2] drm/amd/pm: add get_dpm_ultimate_freq function for cyan skillfish

[Lazar, Lijo]

On 1/24/2022 12:13 PM, Lang Yu wrote:

Some clients(e.g., kfd) query sclk/mclk through this function.

Before this patch:
  # /opt/rocm/opencl/bin/clinfo

  Max clock frequency:   0Mhz

After this patch:
  # /opt/rocm/opencl/bin/clinfo

  Max clock frequency:   1500Mhz

Signed-off-by: Lang Yu 
---
  drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c | 9 +
  1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
index 2238ee19c222..665905a568eb 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
@@ -552,6 +552,14 @@ static int cyan_skillfish_od_edit_dpm_table(struct 
smu_context *smu,
return ret;
  }
  
+static int cyan_skillfish_get_dpm_ultimate_freq(struct smu_context *smu,

+   enum smu_clk_type clk_type,
+   uint32_t *min,
+   uint32_t *max)
+{
+   return cyan_skillfish_get_current_clk_freq(smu, clk_type, min ? min : 
max);
+}
+


I see the below logic already there and this patch doesn't match with that.

case SMU_GFXCLK:
ret = cyan_skillfish_get_current_clk_freq(smu, 
clk_type, &cur_value);

if (ret)
return ret;
if (cur_value  == CYAN_SKILLFISH_SCLK_MAX)
i = 2;
else if (cur_value == CYAN_SKILLFISH_SCLK_MIN)
i = 0;
else
i = 1;
size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", 
CYAN_SKILLFISH_SCLK_MIN,

i == 0 ? "*" : "");
size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
i == 1 ? cur_value : 
cyan_skillfish_sclk_default,

i == 1 ? "*" : "");
size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", 
CYAN_SKILLFISH_SCLK_MAX,

i == 2 ? "*" : "");
break;


Thanks,
Lijo


  static const struct pptable_funcs cyan_skillfish_ppt_funcs = {
  
  	.check_fw_status = smu_v11_0_check_fw_status,

@@ -565,6 +573,7 @@ static const struct pptable_funcs cyan_skillfish_ppt_funcs 
= {
.is_dpm_running = cyan_skillfish_is_dpm_running,
.get_gpu_metrics = cyan_skillfish_get_gpu_metrics,
.od_edit_dpm_table = cyan_skillfish_od_edit_dpm_table,
+   .get_dpm_ultimate_freq = cyan_skillfish_get_dpm_ultimate_freq,
.register_irq_handler = smu_v11_0_register_irq_handler,
.notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
.send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,

Re: [PATCH 2/2] drm/amd/pm: use existing fini_smc_tables function for cyan skillfish

[Huang Rui]

On Mon, Jan 24, 2022 at 02:43:42PM +0800, Yu, Lang wrote:
> Remove redundant code and use general smu_v11_0_fini_smc_tables function.
> 
> Signed-off-by: Lang Yu 

Reviewed-by: Huang Rui 

> ---
>  .../amd/pm/swsmu/smu11/cyan_skillfish_ppt.c| 18 +-
>  1 file changed, 1 insertion(+), 17 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c 
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
> index 665905a568eb..a2b72d19a400 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
> @@ -125,22 +125,6 @@ static int cyan_skillfish_init_smc_tables(struct 
> smu_context *smu)
>   return smu_v11_0_init_smc_tables(smu);
>  }
>  
> -static int cyan_skillfish_finit_smc_tables(struct smu_context *smu)
> -{
> - struct smu_table_context *smu_table = &smu->smu_table;
> -
> - kfree(smu_table->metrics_table);
> - smu_table->metrics_table = NULL;
> -
> - kfree(smu_table->gpu_metrics_table);
> - smu_table->gpu_metrics_table = NULL;
> - smu_table->gpu_metrics_table_size = 0;
> -
> - smu_table->metrics_time = 0;
> -
> - return 0;
> -}
> -
>  static int
>  cyan_skillfish_get_smu_metrics_data(struct smu_context *smu,
>   MetricsMember_t member,
> @@ -567,7 +551,7 @@ static const struct pptable_funcs 
> cyan_skillfish_ppt_funcs = {
>   .init_power = smu_v11_0_init_power,
>   .fini_power = smu_v11_0_fini_power,
>   .init_smc_tables = cyan_skillfish_init_smc_tables,
> - .fini_smc_tables = cyan_skillfish_finit_smc_tables,
> + .fini_smc_tables = smu_v11_0_fini_smc_tables,
>   .read_sensor = cyan_skillfish_read_sensor,
>   .print_clk_levels = cyan_skillfish_print_clk_levels,
>   .is_dpm_running = cyan_skillfish_is_dpm_running,
> -- 
> 2.25.1
> 

Re: [PATCH 1/2] drm/amd/pm: add get_dpm_ultimate_freq function for cyan skillfish

[Huang Rui]

On Mon, Jan 24, 2022 at 02:43:41PM +0800, Yu, Lang wrote:
> Some clients(e.g., kfd) query sclk/mclk through this function.
> 
> Before this patch:
>  # /opt/rocm/opencl/bin/clinfo
> 
>  Max clock frequency:   0Mhz
> 
> After this patch:
>  # /opt/rocm/opencl/bin/clinfo
> 
>  Max clock frequency:   1500Mhz
> 
> Signed-off-by: Lang Yu 
> ---
>  drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c | 9 +
>  1 file changed, 9 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c 
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
> index 2238ee19c222..665905a568eb 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
> @@ -552,6 +552,14 @@ static int cyan_skillfish_od_edit_dpm_table(struct 
> smu_context *smu,
>   return ret;
>  }
>  
> +static int cyan_skillfish_get_dpm_ultimate_freq(struct smu_context *smu,
> + enum smu_clk_type clk_type,
> + uint32_t *min,
> + uint32_t *max)
> +{

We need to add comment here to explain in Cyan Skillfish, the clock is
constant and not changed. So here, min = max = current clock.

With that updated, patch is Reviewed-by: Huang Rui 

> + return cyan_skillfish_get_current_clk_freq(smu, clk_type, min ? min : 
> max);
> +}
> +
>  static const struct pptable_funcs cyan_skillfish_ppt_funcs = {
>  
>   .check_fw_status = smu_v11_0_check_fw_status,
> @@ -565,6 +573,7 @@ static const struct pptable_funcs 
> cyan_skillfish_ppt_funcs = {
>   .is_dpm_running = cyan_skillfish_is_dpm_running,
>   .get_gpu_metrics = cyan_skillfish_get_gpu_metrics,
>   .od_edit_dpm_table = cyan_skillfish_od_edit_dpm_table,
> + .get_dpm_ultimate_freq = cyan_skillfish_get_dpm_ultimate_freq,
>   .register_irq_handler = smu_v11_0_register_irq_handler,
>   .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
>   .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
> -- 
> 2.25.1
> 

Re: [PATCH 3/3] drm/amd/display: convert to DCE IP version checking

[Huang Rui]

On Mon, Jan 24, 2022 at 11:20:42AM +0800, Huang, Tim wrote:
> Use IP versions rather than asic_type to differentiate IP version specific 
> features.
> 
> Signed-off-by: Tim Huang 
> ---
>  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 12 +---
>  1 file changed, 5 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 87299e62fe12..c967e1e344e4 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -1119,19 +1119,17 @@ static int dm_dmub_hw_init(struct amdgpu_device *adev)
>   for (i = 0; i < fb_info->num_fb; ++i)
>   hw_params.fb[i] = &fb_info->fb[i];
>  
> - switch (adev->asic_type) {
> - case CHIP_YELLOW_CARP:
> - if (dc->ctx->asic_id.hw_internal_rev != YELLOW_CARP_A0) {
> - hw_params.dpia_supported = true;
> + switch (adev->ip_versions[DCE_HWIP][0]) {
> + case IP_VERSION(3, 1, 3): /* Only for this asic hw internal rev B0 */

There is another way to define a APU flag on enum amd_apu_flags to
differentiate A0 and B0 for yellow carp.

But this way looks good for me as well.
Patch is Acked-by: Huang Rui 

> + hw_params.dpia_supported = true;
>  #if defined(CONFIG_DRM_AMD_DC_DCN)
> - hw_params.disable_dpia = 
> dc->debug.dpia_debug.bits.disable_dpia;
> + hw_params.disable_dpia = dc->debug.dpia_debug.bits.disable_dpia;
>  #endif
> - }
>   break;
>   default:
>   break;
>   }
> -
> + 
>   status = dmub_srv_hw_init(dmub_srv, &hw_params);
>   if (status != DMUB_STATUS_OK) {
>   DRM_ERROR("Error initializing DMUB HW: %d\n", status);
> -- 
> 2.25.1
> 

Re: [PATCH 2/3] drm/amdgpu: convert to UVD IP version checking

[Huang Rui]

On Mon, Jan 24, 2022 at 11:20:41AM +0800, Huang, Tim wrote:
> Use IP versions rather than asic_type to differentiate IP version specific 
> features.
> 
> Signed-off-by: Tim Huang 

Reviewed-by: Huang Rui 

> ---
>  drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c | 9 +++--
>  1 file changed, 7 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c 
> b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
> index 01c242c5abc3..c5ffb14ba183 100644
> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
> @@ -50,11 +50,16 @@ static int jpeg_v3_0_early_init(void *handle)
>  {
>   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>  
> - if (adev->asic_type != CHIP_YELLOW_CARP) {
> - u32 harvest = RREG32_SOC15(JPEG, 0, mmCC_UVD_HARVESTING);
> + u32 harvest;
>  
> + switch (adev->ip_versions[UVD_HWIP][0]) {
> + case IP_VERSION(3, 1, 1): 
> + break;
> + default:
> + harvest = RREG32_SOC15(JPEG, 0, mmCC_UVD_HARVESTING);
>   if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK)
>   return -ENOENT;
> + break;
>   }
>  
>   adev->jpeg.num_jpeg_inst = 1;
> -- 
> 2.25.1
> 

Re: [PATCH 1/3] drm/amdgpu: convert to NBIO IP version checking

[Huang Rui]

On Mon, Jan 24, 2022 at 11:20:40AM +0800, Huang, Tim wrote:
> Use IP versions rather than asic_type to differentiate IP version specific 
> features.
> 
> Signed-off-by: Tim Huang 

Reviewed-by: Huang Rui 

> ---
>  drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c | 48 ++
>  1 file changed, 34 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c 
> b/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c
> index 3444332ea110..70e341d884d5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c
> @@ -59,10 +59,15 @@ static u32 nbio_v7_2_get_rev_id(struct amdgpu_device 
> *adev)
>  {
>   u32 tmp;
>  
> - if (adev->asic_type == CHIP_YELLOW_CARP)
> + switch (adev->ip_versions[NBIO_HWIP][0]) {
> + case IP_VERSION(7, 2, 1):
> + case IP_VERSION(7, 5, 0):
>   tmp = RREG32_SOC15(NBIO, 0, 
> regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_YC);
> - else
> + break;
> + default:
>   tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);
> + break;
> + }
>  
>   tmp &= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
>   tmp >>= 
> RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
> @@ -72,20 +77,25 @@ static u32 nbio_v7_2_get_rev_id(struct amdgpu_device 
> *adev)
>  
>  static void nbio_v7_2_mc_access_enable(struct amdgpu_device *adev, bool 
> enable)
>  {
> - if (enable)
> - if (adev->asic_type == CHIP_YELLOW_CARP)
> + switch (adev->ip_versions[NBIO_HWIP][0]) {
> + case IP_VERSION(7, 2, 1):
> + case IP_VERSION(7, 5, 0):
> + if (enable)
>   WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN_YC,
>   BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK |
>   BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK);
>   else
> + WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN_YC, 0);
> + break;
> + default:
> + if (enable)
>   WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN,
>   BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK |
>   BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK);
> - else
> - if (adev->asic_type == CHIP_YELLOW_CARP)
> - WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN_YC, 0);
>   else
>   WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 0);
> + break;
> + }
>  }
>  
>  static u32 nbio_v7_2_get_memsize(struct amdgpu_device *adev)
> @@ -249,8 +259,10 @@ static void 
> nbio_v7_2_update_medium_grain_light_sleep(struct amdgpu_device *adev
> bool enable)
>  {
>   uint32_t def, data;
> -
> - if (adev->asic_type == CHIP_YELLOW_CARP) {
> + 
> + switch (adev->ip_versions[NBIO_HWIP][0]) {
> + case IP_VERSION(7, 2, 1):
> + case IP_VERSION(7, 5, 0):
>   def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, 
> regPCIE_CNTL2));
>   if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
>   data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK;
> @@ -260,8 +272,8 @@ static void 
> nbio_v7_2_update_medium_grain_light_sleep(struct amdgpu_device *adev
>   if (def != data)
>   WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, 
> regPCIE_CNTL2), data);
>  
> - data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, 
> regBIF1_PCIE_TX_POWER_CTRL_1));
> - def = data;
> + def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, 
> + regBIF1_PCIE_TX_POWER_CTRL_1));
>   if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
>   data |= (BIF1_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK |
>   
> BIF1_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK);
> @@ -272,7 +284,8 @@ static void 
> nbio_v7_2_update_medium_grain_light_sleep(struct amdgpu_device *adev
>   if (def != data)
>   WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, 
> regBIF1_PCIE_TX_POWER_CTRL_1),
>   data);
> - } else {
> + break;
> + default:
>   def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, 
> regPCIE_CNTL2));
>   if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
>   data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
> @@ -285,6 +298,8 @@ static void 
> nbio_v7_2_update_medium_grain_light_sleep(struct amdgpu_device *adev
>  
>   if (def != data)
>   WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, 
> regPCIE_CNTL2), data);
> +
> + break;
>   }
>  }
>  
> @@ -352,7 +367,9 @@ const struct nbio_hdp_flush_reg nbio_v7_2_hdp_flush_reg = 
> {
>  static void nbio_v7_2_init_registers(struct amdgpu_device *adev)
>  {
>   uint32_t def, data;
> - if (ade

Re: [PATCH 4/4] drm/amdgpu/nv: add navi GPU reset handler

[Christian König]

Am 21.01.22 um 21:34 schrieb Sharma, Shashank:

From 899ec6060eb7d8a3d4d56ab439e4e6cdd74190a4 Mon Sep 17 00:00:00 2001
From: Somalapuram Amaranath 
Date: Fri, 21 Jan 2022 14:19:42 +0530
Subject: [PATCH 4/4] drm/amdgpu/nv: add navi GPU reset handler

This patch adds a GPU reset handler for Navi ASIC family, which
typically dumps some of the registersand sends a trace event.

V2: Accomodated call to work function to send uevent

Signed-off-by: Somalapuram Amaranath 
Signed-off-by: Shashank Sharma 
---
 drivers/gpu/drm/amd/amdgpu/nv.c | 28 
 1 file changed, 28 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c 
b/drivers/gpu/drm/amd/amdgpu/nv.c

index 01efda4398e5..ada35d4c5245 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -528,10 +528,38 @@ nv_asic_reset_method(struct amdgpu_device *adev)
 }
 }

+static void amdgpu_reset_dumps(struct amdgpu_device *adev)
+{
+    int r = 0, i;


Please don't initialize variables if it isn't absolutely necessary.


+
+    /* original raven doesn't have full asic reset */
+    if ((adev->apu_flags & AMD_APU_IS_RAVEN) &&
+    !(adev->apu_flags & AMD_APU_IS_RAVEN2))
+    return;
+    for (i = 0; i < adev->num_ip_blocks; i++) {
+    if (!adev->ip_blocks[i].status.valid)
+    continue;
+    if (!adev->ip_blocks[i].version->funcs->reset_reg_dumps)
+    continue;
+    r = adev->ip_blocks[i].version->funcs->reset_reg_dumps(adev);
+
+    if (r)
+    DRM_ERROR("reset_reg_dumps of IP block <%s> failed %d\n",
+ adev->ip_blocks[i].version->funcs->name, r);
+    }
+
+    /* Schedule work to send uevent */
+    if (!queue_work(system_unbound_wq, &adev->gpu_reset_work))
+    DRM_ERROR("failed to add GPU reset work\n");
+
+    dump_stack();
+}
+


I'm pretty sure that should be inside common code and not here.

In other words that is absolutely not ASIC specific at all.

Regards,
Christian.


 static int nv_asic_reset(struct amdgpu_device *adev)
 {
 int ret = 0;

+    amdgpu_reset_dumps(adev);
 switch (nv_asic_reset_method(adev)) {
 case AMD_RESET_METHOD_PCI:
 dev_info(adev->dev, "PCI reset\n");

Re: [PATCH 2/4] drm/amdgpu: add work function for GPU reset

[Christian König]

Am 21.01.22 um 21:37 schrieb Sharma, Shashank:

From c598dd586dd15fc5ae0a883a2e6f4094ec024085 Mon Sep 17 00:00:00 2001
From: Shashank Sharma 
Date: Fri, 21 Jan 2022 17:33:10 +0100
Subject: [PATCH 2/4] drm/amdgpu: add work function for GPU reset

This patch adds a new work function, which will get scheduled
in event of a GPU reset, and will send a uevent to indicate the same.
The userspace can do some post-processing work like collecting data
from a trace event.

Cc: Alexander Deucher 
Cc: Christian Koenig 
Signed-off-by: Shashank Sharma 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h    |  2 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 14 ++
 2 files changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h

index 269437b01328..79192f43bb71 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1057,6 +1057,8 @@ struct amdgpu_device {
 struct work_struct    xgmi_reset_work;
 struct list_head    reset_list;

+    struct work_struct    gpu_reset_work;


This needs a different name. "gpu_reset_work" would indicate that it 
does the GPU reset, but this really only signals the reset to userspace.


Christian.


+
 long    gfx_timeout;
 long    sdma_timeout;
 long    video_timeout;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

index af9bdf16eefd..e29e58240869 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -72,6 +72,7 @@
 #include 

 #include 
+#include 

 MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
 MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin");
@@ -3274,6 +3275,18 @@ bool amdgpu_device_has_dc_support(struct 
amdgpu_device *adev)

 return amdgpu_device_asic_has_dc_support(adev->asic_type);
 }

+static void amdgpu_device_gpu_reset_func(struct work_struct *__work)
+{
+    struct amdgpu_device *adev =
+    container_of(__work, struct amdgpu_device, gpu_reset_work);
+
+    /*
+ * Inform userspace that a GPU reset happened, and it should collect
+ * data from the trace event.
+ */
+    drm_sysfs_gpu_reset_event(&adev->ddev);
+}
+
 static void amdgpu_device_xgmi_reset_func(struct work_struct *__work)
 {
 struct amdgpu_device *adev =
@@ -3506,6 +3519,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
   amdgpu_device_delay_enable_gfx_off);

 INIT_WORK(&adev->xgmi_reset_work, amdgpu_device_xgmi_reset_func);
+    INIT_WORK(&adev->gpu_reset_work, amdgpu_device_gpu_reset_func);

 adev->gfx.gfx_off_req_count = 1;
 adev->pm.ac_power = power_supply_is_system_supplied() > 0;

Re: [PATCH 3/4] drm/amdgpu: add reset register trace dump function

[Christian König]

Am 21.01.22 um 21:34 schrieb Sharma, Shashank:

From 1c5c552eeddaffd9fb3e7d45ece1b2b28fccc575 Mon Sep 17 00:00:00 2001
From: Somalapuram Amaranath 
Date: Fri, 21 Jan 2022 14:19:10 +0530
Subject: [PATCH 3/4] drm/amdgpu: add reset register trace dump 
function for

 gfx_v10_0

Implementation of register trace dump function on the AMD GPU resets

Signed-off-by: Somalapuram Amaranath 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h |  8 
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c    | 53 ++-
 drivers/gpu/drm/amd/include/amd_shared.h  |  1 +
 3 files changed, 60 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h

index d855cb53c7e0..c97b53b54333 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
@@ -537,6 +537,14 @@ TRACE_EVENT(amdgpu_ib_pipe_sync,
   __entry->seqno)
 );

+TRACE_EVENT(gfx_v10_0_reset_reg_dumps,
+    TP_PROTO(char *reg_dumps),
+    TP_ARGS(reg_dumps),
+    TP_STRUCT__entry(__string(dumps, reg_dumps)),
+    TP_fast_assign(__assign_str(dumps, reg_dumps);),
+    TP_printk("amdgpu register dump {%s}", __get_str(dumps))
+);
+
 #undef AMDGPU_JOB_GET_TIMELINE_NAME
 #endif

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

index 16dbe593cba2..05974ed5416d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -46,7 +46,7 @@
 #include "v10_structs.h"
 #include "gfx_v10_0.h"
 #include "nbio_v2_3.h"
-
+#include "amdgpu_trace.h"
 /*
  * Navi10 has two graphic rings to share each graphic pipe.
  * 1. Primary ring
@@ -188,6 +188,12 @@
 #define RLCG_ERROR_REPORT_ENABLED(adev) \
 (amdgpu_sriov_reg_indirect_mmhub(adev) || 
amdgpu_sriov_reg_indirect_gc(adev))


+#define N_REGS (17)
+#define DUMP_REG(addr) do {    \
+    (dump)[i][0] = (addr);    \
+    (dump)[i++][1] =  RREG32_SOC15_IP(GC, addr);    \
+    } while (0)


Those macros need an AMDGPU_ prefix and maybe some better names.

From the design POV I'm really wondering if it wouldn't be better if 
userspace defines the registers we want to dump in case of a crash.


Regards,
Christian.


+
 MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
 MODULE_FIRMWARE("amdgpu/navi10_me.bin");
@@ -7488,7 +7494,6 @@ static int gfx_v10_0_hw_init(void *handle)
 {
 int r;
 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
 if (!amdgpu_emu_mode)
 gfx_v10_0_init_golden_registers(adev);

@@ -7602,6 +7607,49 @@ static int gfx_v10_0_hw_fini(void *handle)
 return 0;
 }

+static int gfx_v10_0_reset_reg_dumps(void *handle)
+{
+    struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+    uint32_t i = 0;
+    uint32_t (*dump)[2], n_regs = 0;
+    char *reg_dumps;
+
+    dump = kmalloc(N_REGS*2*sizeof(uint32_t), GFP_KERNEL);
+    reg_dumps = kmalloc(1024, GFP_KERNEL);
+
+    if (dump == NULL || reg_dumps == NULL)
+    return -ENOMEM;
+
+    DUMP_REG(mmGRBM_STATUS2);
+    DUMP_REG(mmGRBM_STATUS_SE0);
+    DUMP_REG(mmGRBM_STATUS_SE1);
+    DUMP_REG(mmGRBM_STATUS_SE2);
+    DUMP_REG(mmGRBM_STATUS_SE3);
+    DUMP_REG(mmSDMA0_STATUS_REG);
+    DUMP_REG(mmSDMA1_STATUS_REG);
+    DUMP_REG(mmCP_STAT);
+    DUMP_REG(mmCP_STALLED_STAT1);
+    DUMP_REG(mmCP_STALLED_STAT1);
+    DUMP_REG(mmCP_STALLED_STAT3);
+    DUMP_REG(mmCP_CPC_STATUS);
+    DUMP_REG(mmCP_CPC_BUSY_STAT);
+    DUMP_REG(mmCP_CPC_STALLED_STAT1);
+    DUMP_REG(mmCP_CPF_STATUS);
+    DUMP_REG(mmCP_CPF_BUSY_STAT);
+    DUMP_REG(mmCP_CPF_STALLED_STAT1);
+
+    n_regs = i;
+
+    for (i = 0; i < n_regs; i++)
+    sprintf(reg_dumps + strlen(reg_dumps), "%08x: %08x, ", 
dump[i][0], dump[i][1]);

+
+    trace_gfx_v10_0_reset_reg_dumps(reg_dumps);
+    kfree(dump);
+    kfree(reg_dumps);
+
+    return 0;
+}
+
 static int gfx_v10_0_suspend(void *handle)
 {
 return gfx_v10_0_hw_fini(handle);
@@ -9367,6 +9415,7 @@ static const struct amd_ip_funcs 
gfx_v10_0_ip_funcs = {

 .set_clockgating_state = gfx_v10_0_set_clockgating_state,
 .set_powergating_state = gfx_v10_0_set_powergating_state,
 .get_clockgating_state = gfx_v10_0_get_clockgating_state,
+    .reset_reg_dumps = gfx_v10_0_reset_reg_dumps,
 };

 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
diff --git a/drivers/gpu/drm/amd/include/amd_shared.h 
b/drivers/gpu/drm/amd/include/amd_shared.h

index 257f280d3d53..76d3a55278df 100644
--- a/drivers/gpu/drm/amd/include/amd_shared.h
+++ b/drivers/gpu/drm/amd/include/amd_shared.h
@@ -296,6 +296,7 @@ struct amd_ip_funcs {
  enum amd_powergating_state state);
 void (*get_clockgating_state)(void *handle, u32 *flags);
 int (*enable_umd_pstate)(void *handle, enum amd_dpm_forced_level 
*level);

+    int (*reset_reg_dumps)(void *handle);
 };

[PATCH] drm/amdgpu: add determine passthrough under arm64

[Victor Zhao]

add determine for passthrough mode under arm64 by reading
CurrentEL register

Signed-off-by: Victor Zhao 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
index c5edd84c1c12..40803aab136f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
@@ -296,6 +296,8 @@ static inline bool is_virtual_machine(void)
 {
 #ifdef CONFIG_X86
return boot_cpu_has(X86_FEATURE_HYPERVISOR);
+#elif CONFIG_ARM64
+   return !is_kernel_in_hyp_mode();
 #else
return false;
 #endif
-- 
2.25.1

[PATCH 2/2] drm/amd/pm: use existing fini_smc_tables function for cyan skillfish

[Lang Yu]

Remove redundant code and use general smu_v11_0_fini_smc_tables function.

Signed-off-by: Lang Yu 
---
 .../amd/pm/swsmu/smu11/cyan_skillfish_ppt.c| 18 +-
 1 file changed, 1 insertion(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
index 665905a568eb..a2b72d19a400 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
@@ -125,22 +125,6 @@ static int cyan_skillfish_init_smc_tables(struct 
smu_context *smu)
return smu_v11_0_init_smc_tables(smu);
 }
 
-static int cyan_skillfish_finit_smc_tables(struct smu_context *smu)
-{
-   struct smu_table_context *smu_table = &smu->smu_table;
-
-   kfree(smu_table->metrics_table);
-   smu_table->metrics_table = NULL;
-
-   kfree(smu_table->gpu_metrics_table);
-   smu_table->gpu_metrics_table = NULL;
-   smu_table->gpu_metrics_table_size = 0;
-
-   smu_table->metrics_time = 0;
-
-   return 0;
-}
-
 static int
 cyan_skillfish_get_smu_metrics_data(struct smu_context *smu,
MetricsMember_t member,
@@ -567,7 +551,7 @@ static const struct pptable_funcs cyan_skillfish_ppt_funcs 
= {
.init_power = smu_v11_0_init_power,
.fini_power = smu_v11_0_fini_power,
.init_smc_tables = cyan_skillfish_init_smc_tables,
-   .fini_smc_tables = cyan_skillfish_finit_smc_tables,
+   .fini_smc_tables = smu_v11_0_fini_smc_tables,
.read_sensor = cyan_skillfish_read_sensor,
.print_clk_levels = cyan_skillfish_print_clk_levels,
.is_dpm_running = cyan_skillfish_is_dpm_running,
-- 
2.25.1

[PATCH 1/2] drm/amd/pm: add get_dpm_ultimate_freq function for cyan skillfish

[Lang Yu]

Some clients(e.g., kfd) query sclk/mclk through this function.

Before this patch:
 # /opt/rocm/opencl/bin/clinfo

 Max clock frequency:   0Mhz

After this patch:
 # /opt/rocm/opencl/bin/clinfo

 Max clock frequency:   1500Mhz

Signed-off-by: Lang Yu 
---
 drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
index 2238ee19c222..665905a568eb 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
@@ -552,6 +552,14 @@ static int cyan_skillfish_od_edit_dpm_table(struct 
smu_context *smu,
return ret;
 }
 
+static int cyan_skillfish_get_dpm_ultimate_freq(struct smu_context *smu,
+   enum smu_clk_type clk_type,
+   uint32_t *min,
+   uint32_t *max)
+{
+   return cyan_skillfish_get_current_clk_freq(smu, clk_type, min ? min : 
max);
+}
+
 static const struct pptable_funcs cyan_skillfish_ppt_funcs = {
 
.check_fw_status = smu_v11_0_check_fw_status,
@@ -565,6 +573,7 @@ static const struct pptable_funcs cyan_skillfish_ppt_funcs 
= {
.is_dpm_running = cyan_skillfish_is_dpm_running,
.get_gpu_metrics = cyan_skillfish_get_gpu_metrics,
.od_edit_dpm_table = cyan_skillfish_od_edit_dpm_table,
+   .get_dpm_ultimate_freq = cyan_skillfish_get_dpm_ultimate_freq,
.register_irq_handler = smu_v11_0_register_irq_handler,
.notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
.send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
-- 
2.25.1

RE: [PATCH 3/3] drm/amd/display: convert to DCE IP version checking

[Liu, Aaron]

[AMD Official Use Only]


Tim，

Please remove TAB in the beginning of an empty line and the SPACE in the end of 
a line.

With this fixed, series is:
Reviewed-by: Aaron Liu aaron@amd.com



--

Best Regards

Aaron Liu



> -Original Message-

> From: Huang, Tim 

> Sent: Monday, January 24, 2022 11:21 AM

> To: amd-gfx@lists.freedesktop.org

> Cc: Deucher, Alexander ; Huang, Ray

> ; Liu, Aaron ; Huang, Tim

> 

> Subject: [PATCH 3/3] drm/amd/display: convert to DCE IP version checking

>

> Use IP versions rather than asic_type to differentiate IP version specific

> features.

>

> Signed-off-by: Tim Huang mailto:xiaohu.hu...@amd.com>>

> ---

>  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 12 +---

>  1 file changed, 5 insertions(+), 7 deletions(-)

>

> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

> index 87299e62fe12..c967e1e344e4 100644

> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

> @@ -1119,19 +1119,17 @@ static int dm_dmub_hw_init(struct

> amdgpu_device *adev)

>  for (i = 0; i < fb_info->num_fb; ++i)

>  hw_params.fb[i] = &fb_info->fb[i];

>

> -switch (adev->asic_type) {

> -case CHIP_YELLOW_CARP:

> -if (dc->ctx->asic_id.hw_internal_rev != YELLOW_CARP_A0) {

> -hw_params.dpia_supported = true;

> +   switch (adev->ip_versions[DCE_HWIP][0]) {

> +   case IP_VERSION(3, 1, 3): /* Only for this asic hw internal rev B0 */

> +   hw_params.dpia_supported = true;

>  #if defined(CONFIG_DRM_AMD_DC_DCN)

> -hw_params.disable_dpia = dc-

> >debug.dpia_debug.bits.disable_dpia;

> +   hw_params.disable_dpia = dc-

> >debug.dpia_debug.bits.disable_dpia;

>  #endif

> -}

>  break;

>  default:

>  break;

>  }

> -

> +

>  status = dmub_srv_hw_init(dmub_srv, &hw_params);

>  if (status != DMUB_STATUS_OK) {

>  DRM_ERROR("Error initializing DMUB HW: %d\n", status);

> --

> 2.25.1

RE: [PATCH 1/5] drm/amdgpu: set APU flag based on IP discovery table

[Liu, Aaron]

[AMD Official Use Only]

Reviewed-by: Aaron Liu 

--
Best Regards
Aaron Liu

> -Original Message-
> From: amd-gfx  On Behalf Of Alex
> Deucher
> Sent: Saturday, January 22, 2022 4:22 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander 
> Subject: [PATCH 1/5] drm/amdgpu: set APU flag based on IP discovery table
> 
> Use the IP versions to set the APU flag when necessary.
> 
> Signed-off-by: Alex Deucher 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 13 +
>  1 file changed, 13 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> index e6a26b554254..ddbe13c9e4c7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> @@ -1253,6 +1253,19 @@ int amdgpu_discovery_set_ip_blocks(struct
> amdgpu_device *adev)
>   return -EINVAL;
>   }
> 
> + switch (adev->ip_versions[GC_HWIP][0]) {
> + case IP_VERSION(9, 1, 0):
> + case IP_VERSION(9, 2, 2):
> + case IP_VERSION(9, 3, 0):
> + case IP_VERSION(10, 1, 3):
> + case IP_VERSION(10, 3, 1):
> + case IP_VERSION(10, 3, 3):
> + adev->flags |= AMD_IS_APU;
> + break;
> + default:
> + break;
> + }
> +
>   if (adev->ip_versions[XGMI_HWIP][0] == IP_VERSION(4, 8, 0))
>   adev->gmc.xgmi.supported = true;
> 
> --
> 2.34.1

Re: [PATCH 3/7] drm/amd/pm: drop the redundant 'supported' member of smu_feature structure

[Lazar, Lijo]

On 1/24/2022 9:51 AM, Quan, Evan wrote:

[AMD Official Use Only]




-Original Message-
From: Lazar, Lijo 
Sent: Friday, January 21, 2022 5:37 PM
To: Quan, Evan ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Chen, Guchun
; Huang, Ray 
Subject: Re: [PATCH 3/7] drm/amd/pm: drop the redundant 'supported'
member of smu_feature structure



On 1/21/2022 2:56 PM, Quan, Evan wrote:

[AMD Official Use Only]




-Original Message-
From: Lazar, Lijo 
Sent: Friday, January 21, 2022 4:52 PM
To: Quan, Evan ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Chen, Guchun
; Huang, Ray 
Subject: Re: [PATCH 3/7] drm/amd/pm: drop the redundant 'supported'
member of smu_feature structure



On 1/21/2022 1:14 PM, Evan Quan wrote:

As it has exactly the same value as the 'enabled' member and also do
the same thing.



I believe the original intention is different. We need to cache the
features which are really supported by PMFW on that device on init.
When a request comes through sysfs node for enable/disable of a
feature, we should check against this and disallow those which are not

supported.

[Quan, Evan] Uh, I doubt it was designed with such intention. As if it was,

there should be checks in ->get_allowed_feature_mask(e.g.
navi10_get_allowed_feature_mask) whether driver tries to enable/disable
different features from PMFW.

" When a request comes through sysfs node for enable/disable of a

feature" If the sysfs node mentioned is "pp_features", I might be able to
provide some insights why there is no such checks added when I made them.
Considering there may be some dependency between those dpm
features(e.g. gfx ulv depends on gfx dpm), we actually cannot guard user
whether their settings will succeed. E.g. If PMFW supports both GFX ULV and
DPM but user wants ULV only, the checks against pmfw supported features
seem fine. But actually that cannot work due to the dependency between
them. So, instead of applying some checks which actually cannot guard
anything, we just let user take the risks.




Below is one example

  > -if (!smu_cmn_feature_is_supported(smu,
SMU_FEATURE_FAN_CONTROL_BIT))
  > +if (!smu_cmn_feature_is_enabled(smu,
SMU_FEATURE_FAN_CONTROL_BIT))

Let's say user switched to manual mode, that time we disable fan control and
move to manual mode. Next time when user requests auto mode, we check
if fan control is originally supported on that platform and switch to auto.


[Quan, Evan] Logically yes. But in reality I assume this should not happen. As 
during our post-silicon bringup,
we enable those features(and corresponding sysfs interfaces)support only after 
verified. It means if the feature(auto fan control)
is not supported, the sysfs interface should be not visible to user.


Well, there are multiple examples -

amdgpu_asic_update_umd_stable_pstate(smu->adev, 
false);

smu_deep_sleep_control(smu, true);
smu_gfx_ulv_control(smu, true);
smu_gpo_control(smu, true);

This is yet another one. Some aspects are disabled while umd profiling 
and then they are enabled back when it's back to FW control. This is 
internal logic and it could be disastrous if we try to enable a feature 
without checking if it's really supported on production SKUs.



Either way, we should cache the features which are originally supported on
the platform (through a combination of PPTable features and allowed
feature masks on ASICs which are applicable) and disallow anything outside
of that.

[Quan, Evan] Although I doubt the necessity of such cache. But I do keep a structure member 
"feature->allowed" which does the similar job.
It may be more reasonable to expand its scope to handle the job described here.



It would be needed for both internal and external interfaces, I strongly 
suggest to keep it. The name 'supported' is more intuitive and 'allowed 
feature' concept from PMFW is not there for all ASICs, though I don't 
mind the name anyway.


Thanks,
Lijo


BR
Evan


Thanks,
Lijo


BR
Evan


Thanks,
Lijo


Signed-off-by: Evan Quan 
Change-Id: I07c9a5ac5290cd0d88a40ce1768d393156419b5a
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c |  1 -
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h |  1 -
.../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c   |  8 
.../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c   | 10 +-
.../gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c| 19 ---





.../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c  |  5 +
.../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c|  5 +
.../drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c  |  3 ---
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c| 17 -
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h|  3 ---
10 files changed, 19 insertions(+), 53 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 5ace30434e60..d32

RE: [PATCH 3/7] drm/amd/pm: drop the redundant 'supported' member of smu_feature structure

[Quan, Evan]

[AMD Official Use Only]



> -Original Message-
> From: Lazar, Lijo 
> Sent: Friday, January 21, 2022 5:37 PM
> To: Quan, Evan ; amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Chen, Guchun
> ; Huang, Ray 
> Subject: Re: [PATCH 3/7] drm/amd/pm: drop the redundant 'supported'
> member of smu_feature structure
> 
> 
> 
> On 1/21/2022 2:56 PM, Quan, Evan wrote:
> > [AMD Official Use Only]
> >
> >
> >
> >> -Original Message-
> >> From: Lazar, Lijo 
> >> Sent: Friday, January 21, 2022 4:52 PM
> >> To: Quan, Evan ; amd-gfx@lists.freedesktop.org
> >> Cc: Deucher, Alexander ; Chen, Guchun
> >> ; Huang, Ray 
> >> Subject: Re: [PATCH 3/7] drm/amd/pm: drop the redundant 'supported'
> >> member of smu_feature structure
> >>
> >>
> >>
> >> On 1/21/2022 1:14 PM, Evan Quan wrote:
> >>> As it has exactly the same value as the 'enabled' member and also do
> >>> the same thing.
> >>>
> >>
> >> I believe the original intention is different. We need to cache the
> >> features which are really supported by PMFW on that device on init.
> >> When a request comes through sysfs node for enable/disable of a
> >> feature, we should check against this and disallow those which are not
> supported.
> > [Quan, Evan] Uh, I doubt it was designed with such intention. As if it was,
> there should be checks in ->get_allowed_feature_mask(e.g.
> navi10_get_allowed_feature_mask) whether driver tries to enable/disable
> different features from PMFW.
> > " When a request comes through sysfs node for enable/disable of a
> feature" If the sysfs node mentioned is "pp_features", I might be able to
> provide some insights why there is no such checks added when I made them.
> Considering there may be some dependency between those dpm
> features(e.g. gfx ulv depends on gfx dpm), we actually cannot guard user
> whether their settings will succeed. E.g. If PMFW supports both GFX ULV and
> DPM but user wants ULV only, the checks against pmfw supported features
> seem fine. But actually that cannot work due to the dependency between
> them. So, instead of applying some checks which actually cannot guard
> anything, we just let user take the risks.
> >
> 
> Below is one example
> 
>  > -  if (!smu_cmn_feature_is_supported(smu,
> SMU_FEATURE_FAN_CONTROL_BIT))
>  > +  if (!smu_cmn_feature_is_enabled(smu,
> SMU_FEATURE_FAN_CONTROL_BIT))
> 
> Let's say user switched to manual mode, that time we disable fan control and
> move to manual mode. Next time when user requests auto mode, we check
> if fan control is originally supported on that platform and switch to auto.
> 
[Quan, Evan] Logically yes. But in reality I assume this should not happen. As 
during our post-silicon bringup,
we enable those features(and corresponding sysfs interfaces)support only after 
verified. It means if the feature(auto fan control)
is not supported, the sysfs interface should be not visible to user.
> Either way, we should cache the features which are originally supported on
> the platform (through a combination of PPTable features and allowed
> feature masks on ASICs which are applicable) and disallow anything outside
> of that.
[Quan, Evan] Although I doubt the necessity of such cache. But I do keep a 
structure member "feature->allowed" which does the similar job.
It may be more reasonable to expand its scope to handle the job described here.

BR
Evan
> 
> Thanks,
> Lijo
> 
> > BR
> > Evan
> >>
> >> Thanks,
> >> Lijo
> >>
> >>> Signed-off-by: Evan Quan 
> >>> Change-Id: I07c9a5ac5290cd0d88a40ce1768d393156419b5a
> >>> ---
> >>>drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c |  1 -
> >>>drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h |  1 -
> >>>.../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c   |  8 
> >>>.../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c   | 10 +-
> >>>.../gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c| 19 ---
> 
> >> 
> >>>.../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c  |  5 +
> >>>.../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c|  5 +
> >>>.../drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c  |  3 ---
> >>>drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c| 17 -
> >>>drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h|  3 ---
> >>>10 files changed, 19 insertions(+), 53 deletions(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> >>> b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> >>> index 5ace30434e60..d3237b89f2c5 100644
> >>> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> >>> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> >>> @@ -949,7 +949,6 @@ static int smu_sw_init(void *handle)
> >>>
> >>>   smu->pool_size = adev->pm.smu_prv_buffer_size;
> >>>   smu->smu_feature.feature_num = SMU_FEATURE_MAX;
> >>> - bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX);
> >>>   bitmap_zero(smu->smu_feature.enabled, SMU_FEATURE_MAX);
> >>>   bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX);
> >>>
> >>> diff --git a/drivers/gpu

RE: [PATCH 4/5] drm/amdgpu: handle BACO synchronization with secondary funcs

[Quan, Evan]

[AMD Official Use Only]



> -Original Message-
> From: amd-gfx  On Behalf Of Alex
> Deucher
> Sent: Saturday, January 22, 2022 4:22 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander 
> Subject: [PATCH 4/5] drm/amdgpu: handle BACO synchronization with
> secondary funcs
> 
> Extend secondary function handling for runtime pm beyond audio
> to USB and UCSI.
> 
> Signed-off-by: Alex Deucher 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 30 +++--
> 
>  1 file changed, 18 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index 89c3578bc818..119a5798623e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -1968,19 +1968,25 @@ static bool
> amdgpu_is_fw_framebuffer(resource_size_t base,
>   return found;
>  }
> 
> -static void amdgpu_get_audio_func(struct amdgpu_device *adev)
> +static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev)
>  {
>   struct pci_dev *p = NULL;
> + int i;
> 
> - p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev-
> >bus),
> - adev->pdev->bus->number, 1);
> - if (p) {
> - pm_runtime_get_sync(&p->dev);
> -
> - pm_runtime_mark_last_busy(&p->dev);
> - pm_runtime_put_autosuspend(&p->dev);
> -
> - pci_dev_put(p);
> + /* 0 - GPU
> +  * 1 - audio
> +  * 2 - USB
> +  * 3 - UCSI
> +  */
> + for (i = 1; i < 4; i++) {
> + p = pci_get_domain_bus_and_slot(pci_domain_nr(adev-
> >pdev->bus),
> + adev->pdev->bus->number,
> i);
> + if (p) {
> + pm_runtime_get_sync(&p->dev);
> + pm_runtime_mark_last_busy(&p->dev);
> + pm_runtime_put_autosuspend(&p->dev);
> + pci_dev_put(p);
> + }
>   }
>  }
[Quan, Evan] Although PMFW does not care the status of those functions except 
audio. Logically this seems more reasonable and should be harmless.
Patch 3 & 4 are reviewed-by: Evan Quan 
Patch 1, 2, 5 are acked-by: Evan Quan 
> 
> @@ -2148,14 +2154,14 @@ static int amdgpu_pci_probe(struct pci_dev
> *pdev,
>* be no PMFW-aware D-state transition(D0->D3) on runpm
>* suspend. Thus the BACO will be not correctly kicked in.
>*
> -  * Via amdgpu_get_audio_func(), the audio dev is put
> +  * Via amdgpu_get_secondary_funcs(), the audio dev is put
>* into D0 state. Then there will be a PMFW-aware D-state
>* transition(D0->D3) on runpm suspend.
>*/
>   if (amdgpu_device_supports_baco(ddev) &&
>   !(adev->flags & AMD_IS_APU) &&
>   (adev->asic_type >= CHIP_NAVI10))
> - amdgpu_get_audio_func(adev);
> + amdgpu_get_secondary_funcs(adev);
>   }
> 
>   return 0;
> --
> 2.34.1

RE: [PATCH] drm/amdgpu/pm/smu7: drop message about VI performance levels

[Quan, Evan]

[AMD Official Use Only]

Reviewed-by: Evan Quan 

> -Original Message-
> From: amd-gfx  On Behalf Of Alex
> Deucher
> Sent: Saturday, January 22, 2022 4:22 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander 
> Subject: [PATCH] drm/amdgpu/pm/smu7: drop message about VI
> performance levels
> 
> Earlier chips only had two performance levels, but newer
> ones potentially had more.  The message is harmless.  Drop the
> message to avoid spamming the log.
> 
> Bug:
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgitla
> b.freedesktop.org%2Fdrm%2Famd%2F-
> %2Fissues%2F1874&data=04%7C01%7Cevan.quan%40amd.com%7C008
> 496779cf84e3eb9bc08d9dd1bb44e%7C3dd8961fe4884e608e11a82d994e183d
> %7C0%7C0%7C63778391038923%7CUnknown%7CTWFpbGZsb3d8eyJWIj
> oiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3
> 000&sdata=e53W24tcHU8hRut26458QE5v%2BrTk0xRd4eTMxaFn72E%3
> D&reserved=0
> Signed-off-by: Alex Deucher 
> ---
>  drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c | 4 
>  1 file changed, 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
> b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
> index cd99db0dc2be..a1e11037831a 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
> @@ -3295,10 +3295,6 @@ static int smu7_apply_state_adjust_rules(struct
> pp_hwmgr *hwmgr,
>   request_ps->classification.ui_label);
>   data->mclk_ignore_signal = false;
> 
> - PP_ASSERT_WITH_CODE(smu7_ps->performance_level_count == 2,
> -  "VI should always have 2 performance
> levels",
> - );
> -
>   max_limits = adev->pm.ac_power ?
>   &(hwmgr->dyn_state.max_clock_voltage_on_ac) :
>   &(hwmgr->dyn_state.max_clock_voltage_on_dc);
> --
> 2.34.1

[PATCH 3/3] drm/amd/display: convert to DCE IP version checking

[Tim Huang]

Use IP versions rather than asic_type to differentiate IP version specific 
features.

Signed-off-by: Tim Huang 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 12 +---
 1 file changed, 5 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 87299e62fe12..c967e1e344e4 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1119,19 +1119,17 @@ static int dm_dmub_hw_init(struct amdgpu_device *adev)
for (i = 0; i < fb_info->num_fb; ++i)
hw_params.fb[i] = &fb_info->fb[i];
 
-   switch (adev->asic_type) {
-   case CHIP_YELLOW_CARP:
-   if (dc->ctx->asic_id.hw_internal_rev != YELLOW_CARP_A0) {
-   hw_params.dpia_supported = true;
+   switch (adev->ip_versions[DCE_HWIP][0]) {
+   case IP_VERSION(3, 1, 3): /* Only for this asic hw internal rev B0 */
+   hw_params.dpia_supported = true;
 #if defined(CONFIG_DRM_AMD_DC_DCN)
-   hw_params.disable_dpia = 
dc->debug.dpia_debug.bits.disable_dpia;
+   hw_params.disable_dpia = dc->debug.dpia_debug.bits.disable_dpia;
 #endif
-   }
break;
default:
break;
}
-
+   
status = dmub_srv_hw_init(dmub_srv, &hw_params);
if (status != DMUB_STATUS_OK) {
DRM_ERROR("Error initializing DMUB HW: %d\n", status);
-- 
2.25.1

[PATCH 2/3] drm/amdgpu: convert to UVD IP version checking

[Tim Huang]

Use IP versions rather than asic_type to differentiate IP version specific 
features.

Signed-off-by: Tim Huang 
---
 drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c | 9 +++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c 
b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
index 01c242c5abc3..c5ffb14ba183 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
@@ -50,11 +50,16 @@ static int jpeg_v3_0_early_init(void *handle)
 {
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-   if (adev->asic_type != CHIP_YELLOW_CARP) {
-   u32 harvest = RREG32_SOC15(JPEG, 0, mmCC_UVD_HARVESTING);
+   u32 harvest;
 
+   switch (adev->ip_versions[UVD_HWIP][0]) {
+   case IP_VERSION(3, 1, 1): 
+   break;
+   default:
+   harvest = RREG32_SOC15(JPEG, 0, mmCC_UVD_HARVESTING);
if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK)
return -ENOENT;
+   break;
}
 
adev->jpeg.num_jpeg_inst = 1;
-- 
2.25.1

[PATCH 1/3] drm/amdgpu: convert to NBIO IP version checking

[Tim Huang]

Use IP versions rather than asic_type to differentiate IP version specific 
features.

Signed-off-by: Tim Huang 
---
 drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c | 48 ++
 1 file changed, 34 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c 
b/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c
index 3444332ea110..70e341d884d5 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c
@@ -59,10 +59,15 @@ static u32 nbio_v7_2_get_rev_id(struct amdgpu_device *adev)
 {
u32 tmp;
 
-   if (adev->asic_type == CHIP_YELLOW_CARP)
+   switch (adev->ip_versions[NBIO_HWIP][0]) {
+   case IP_VERSION(7, 2, 1):
+   case IP_VERSION(7, 5, 0):
tmp = RREG32_SOC15(NBIO, 0, 
regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_YC);
-   else
+   break;
+   default:
tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);
+   break;
+   }
 
tmp &= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
tmp >>= 
RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
@@ -72,20 +77,25 @@ static u32 nbio_v7_2_get_rev_id(struct amdgpu_device *adev)
 
 static void nbio_v7_2_mc_access_enable(struct amdgpu_device *adev, bool enable)
 {
-   if (enable)
-   if (adev->asic_type == CHIP_YELLOW_CARP)
+   switch (adev->ip_versions[NBIO_HWIP][0]) {
+   case IP_VERSION(7, 2, 1):
+   case IP_VERSION(7, 5, 0):
+   if (enable)
WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN_YC,
BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK |
BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK);
else
+   WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN_YC, 0);
+   break;
+   default:
+   if (enable)
WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN,
BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK |
BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK);
-   else
-   if (adev->asic_type == CHIP_YELLOW_CARP)
-   WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN_YC, 0);
else
WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 0);
+   break;
+   }
 }
 
 static u32 nbio_v7_2_get_memsize(struct amdgpu_device *adev)
@@ -249,8 +259,10 @@ static void 
nbio_v7_2_update_medium_grain_light_sleep(struct amdgpu_device *adev
  bool enable)
 {
uint32_t def, data;
-
-   if (adev->asic_type == CHIP_YELLOW_CARP) {
+   
+   switch (adev->ip_versions[NBIO_HWIP][0]) {
+   case IP_VERSION(7, 2, 1):
+   case IP_VERSION(7, 5, 0):
def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, 
regPCIE_CNTL2));
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK;
@@ -260,8 +272,8 @@ static void 
nbio_v7_2_update_medium_grain_light_sleep(struct amdgpu_device *adev
if (def != data)
WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, 
regPCIE_CNTL2), data);
 
-   data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, 
regBIF1_PCIE_TX_POWER_CTRL_1));
-   def = data;
+   def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, 
+   regBIF1_PCIE_TX_POWER_CTRL_1));
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
data |= (BIF1_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK |

BIF1_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK);
@@ -272,7 +284,8 @@ static void 
nbio_v7_2_update_medium_grain_light_sleep(struct amdgpu_device *adev
if (def != data)
WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, 
regBIF1_PCIE_TX_POWER_CTRL_1),
data);
-   } else {
+   break;
+   default:
def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, 
regPCIE_CNTL2));
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
@@ -285,6 +298,8 @@ static void 
nbio_v7_2_update_medium_grain_light_sleep(struct amdgpu_device *adev
 
if (def != data)
WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, 
regPCIE_CNTL2), data);
+
+   break;
}
 }
 
@@ -352,7 +367,9 @@ const struct nbio_hdp_flush_reg nbio_v7_2_hdp_flush_reg = {
 static void nbio_v7_2_init_registers(struct amdgpu_device *adev)
 {
uint32_t def, data;
-   if (adev->asic_type == CHIP_YELLOW_CARP) {
+   switch (adev->ip_versions[NBIO_HWIP][0]) {
+   case IP_VERSION(7, 2, 1):
+   case IP_VERSION(7, 5, 0):
def = data = RREG32_PCIE_PORT

RE: [PATCH v2 0/3] Implement parallel sysfs_emit solution for navi10

[Quan, Evan]

[AMD Official Use Only]

The whole idea seems fine to me. Just some nitpicks for patch1 and patch3.

BR
Evan
> -Original Message-
> From: Powell, Darren 
> Sent: Saturday, January 22, 2022 11:47 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Powell, Darren 
> Subject: [PATCH v2 0/3] Implement parallel sysfs_emit solution for navi10
> 
> == Description ==
> Scnprintf use within the kernel is not recommended, but simple sysfs_emit
> replacement has not been successful due to the page alignment
> requirement of the function. This patch set implements a new api
> "emit_clock_levels" to facilitate passing both the base and offset to the
> device rather than just the write pointer.
> This patch is only implemented for navi10 for some clocks to seek comment
> on the implementation before extending the implementation to other clock
> values and devices.
> 
> Needs to be verified on a platform that supports the overclocking
> 
>(v2)
>   Update to apply on commit 801771de03
>   adjust printing of empty carriage return only if size == 0
>   change return from amdgpu_dpm_emit_clock_levels if emit_clock_levels
> not found
> 
> == Patch Summary ==
>linux: (g...@gitlab.freedesktop.org:agd5f) origin/amd-staging-drm-next @
> 28907fd9e048
> + f83a3144ede4 amdgpu/pm: Implement new API function "emit" that
> accepts buffer base and write offset
> + 82de36426a1f amdgpu/pm: insert attempt to call emit_clock_levels into
> amdgpu_get_pp_od_clk_voltage
> + 32f0fcf45dd8 amdgpu/pm: Add Error Handling to emit_clocks stack
> 
> == System Summary ==
>  * DESKTOP(AMD FX-8350 + NAVI10(731F/ca), BIOS: F2)
>   + ISO(Ubuntu 20.04.3 LTS)
>   + Kernel(5.13.0-fdoagd5f-20220112-g28907fd9e0)
> 
> == Test ==
> LOGFILE=pp_clk.test.log
> AMDGPU_PCI_ADDR=`lspci -nn | grep "VGA\|Display" | cut -d " " -f 1`
> AMDGPU_HWMON=`ls -la /sys/class/hwmon | grep $AMDGPU_PCI_ADDR |
> awk '{print $9}'` HWMON_DIR=/sys/class/hwmon/${AMDGPU_HWMON}
> 
> lspci -nn | grep "VGA\|Display"  > $LOGFILE FILES="pp_od_clk_voltage
> pp_dpm_sclk pp_dpm_mclk pp_dpm_pcie pp_dpm_socclk pp_dpm_fclk
> pp_dpm_dcefclk pp_dpm_vclk pp_dpm_dclk "
> 
> for f in $FILES
> do
>   echo === $f === >> $LOGFILE
>   cat $HWMON_DIR/device/$f >> $LOGFILE
> done
> cat $LOGFILE
> 
> Darren Powell (3):
>   amdgpu/pm: Implement new API function "emit" that accepts buffer base
> and write offset
>   amdgpu/pm: insert attempt to call emit_clock_levels into
> amdgpu_get_pp_od_clk_voltage
>   amdgpu/pm: Add Error Handling to emit_clocks stack
> 
>  .../gpu/drm/amd/include/kgd_pp_interface.h|   1 +
>  drivers/gpu/drm/amd/pm/amdgpu_dpm.c   |  21 ++
>  drivers/gpu/drm/amd/pm/amdgpu_pm.c|  49 +++--
>  drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h   |   4 +
>  drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c |  44 +++-
>  drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h |  14 ++
>  .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c   | 188
> ++
>  7 files changed, 302 insertions(+), 19 deletions(-)
> 
> 
> base-commit: 28907fd9e04859fab86a143271d29ff0ff043154
> --
> 2.34.1

RE: [PATCH 3/3] amdgpu/pm: Add Error Handling to emit_clocks stack

[Quan, Evan]

[AMD Official Use Only]

It seems this patch should be combined with patch1. Rather than as a separate 
patch.

BR
Evan
> -Original Message-
> From: Powell, Darren 
> Sent: Saturday, January 22, 2022 11:47 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Powell, Darren 
> Subject: [PATCH 3/3] amdgpu/pm: Add Error Handling to emit_clocks stack
> 
>  Previous implementation of print_clocks required return of bytes written
>  to calling function via return value. Passing this value in by reference
>  allows us now to pass back error codes up the calling stack.
> 
>  (v1)
>  - Errors from get_current_clk_freq, get_dpm_level_count & get_dpm_freq
>   now passed back up the stack
>  - Added -EOPNOTSUPP when encountering for OD clocks
>   !od_enabled
>   missing od_table or od_settings
>  - OD_RANGE continues to print any subset of the ODCAP settings it can find
>   without reporting error for any missing
>  - smu_emit_ppclk returns ENOENT if emit_clk_levels is not supported by the
>   device
>  - modified calling logic so fallback to print_clock_levels is only attempted
>   if emit_clk_levels is not (yet) supported by the device
> 
>  (v2)
>  - change return from amdgpu_dpm_emit_clock_levels if emit_clock_levels
> not found
>  - updated documentation of pptable_func members print_clk_levels,
> emit_clk_levels
> 
>  == Test ==
>  LOGFILE=pp_clk.test.log
>  AMDGPU_PCI_ADDR=`lspci -nn | grep "VGA\|Display" | cut -d " " -f 1`
>  AMDGPU_HWMON=`ls -la /sys/class/hwmon | grep $AMDGPU_PCI_ADDR |
> awk '{print $9}'`
>  HWMON_DIR=/sys/class/hwmon/${AMDGPU_HWMON}
> 
>  lspci -nn | grep "VGA\|Display"  > $LOGFILE
>  FILES="pp_od_clk_voltage
>  pp_dpm_sclk
>  pp_dpm_mclk
>  pp_dpm_pcie
>  pp_dpm_socclk
>  pp_dpm_fclk
>  pp_dpm_dcefclk
>  pp_dpm_vclk
>  pp_dpm_dclk "
> 
>  for f in $FILES
>  do
>echo === $f === >> $LOGFILE
>cat $HWMON_DIR/device/$f >> $LOGFILE
>  done
>  cat $LOGFILE
> 
> Signed-off-by: Darren Powell 
> ---
>  drivers/gpu/drm/amd/pm/amdgpu_dpm.c   |  2 +-
>  drivers/gpu/drm/amd/pm/amdgpu_pm.c| 13 ++--
>  drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c |  8 +++
>  drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h |  6 +-
>  .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c   | 21 +-
> -
>  5 files changed, 25 insertions(+), 25 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
> b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
> index e45578124928..03a690a3abb7 100644
> --- a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
> +++ b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
> @@ -915,7 +915,7 @@ int amdgpu_dpm_emit_clock_levels(struct
> amdgpu_device *adev,
>   int ret = 0;
> 
>   if (!pp_funcs->emit_clock_levels)
> - return 0;
> + return -ENOENT;
> 
>   mutex_lock(&adev->pm.mutex);
>   ret = pp_funcs->emit_clock_levels(adev->powerplay.pp_handle,
> diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> index 97a8dcbe6eaf..a11def0ee761 100644
> --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> @@ -855,13 +855,12 @@ static ssize_t
> amdgpu_get_pp_od_clk_voltage(struct device *dev,
>   return ret;
>   }
> 
> - ret = amdgpu_dpm_emit_clock_levels(adev, od_clocks[0], buf,
> &size);
> - if (ret >= 0) {
> - /* Proceed with emit for other od clocks if the first call
> succeeds */
> - for(clk_index = 1 ; clk_index < 6 ; clk_index++)
> - amdgpu_dpm_emit_clock_levels(adev,
> od_clocks[clk_index], buf, &size);
> + for(clk_index = 0 ; clk_index < 6 ; clk_index++) {
> + ret = amdgpu_dpm_emit_clock_levels(adev,
> od_clocks[clk_index], buf, &size);
> + if (ret)
> + break;
>   }
> - else {
> + if (ret == -ENOENT) {
>   size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
>   if (size > 0) {
>   size += amdgpu_dpm_print_clock_levels(adev,
> OD_MCLK, buf+size);
> @@ -1014,7 +1013,7 @@ static ssize_t amdgpu_get_pp_dpm_clock(struct
> device *dev,
>   }
> 
>   ret = amdgpu_dpm_emit_clock_levels(adev, type, buf, &size);
> - if (ret < 0)
> + if (ret == -ENOENT)
>   size = amdgpu_dpm_print_clock_levels(adev, type, buf);
> 
>   if (size == 0)
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> index d82ea7ee223f..29c101a93dc4 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> @@ -2454,12 +2454,10 @@ static int smu_emit_ppclk_levels(void *handle,
> enum pp_clock_type type, char *bu
>   if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
>   return -EOPNOTSUPP;
> 
> - if (smu->ppt_funcs->emit_clk_levels) {
> + if (smu->ppt_funcs->emit_clk_levels)
>   ret = smu->ppt_funcs->emit_clk_levels(smu, clk_type, buf,
> offset);
> - 

RE: [PATCH 1/3] amdgpu/pm: Implement new API function "emit" that accepts buffer base and write offset

[Quan, Evan]

[AMD Official Use Only]



> -Original Message-
> From: Powell, Darren 
> Sent: Saturday, January 22, 2022 11:47 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Powell, Darren 
> Subject: [PATCH 1/3] amdgpu/pm: Implement new API function "emit" that
> accepts buffer base and write offset
> 
>(v1)
>  - new power management function emit_clk_levels implemented by
> navi10_emit_clk_levels()
>This function currently duplicates the functionality of
> navi10_print_clk_levels, where
>snprintf is used write to the sysfs buffer. The first implementation 
> to use
> sysfs_emit
>was unsuccessful due to requirement that buf must be aligned to a
> specific memory
>boundary. This solution passes the buffer base and write offset down 
> the
> stack.
>  - new power management function emit_clock_levels implemented by
> smu_emit_ppclk_levels()
>This function combines implementation of smu_print_ppclk_levels and
>smu_print_smuclk_levels and calls emit_clk_levels
>  - new helper function smu_convert_to_smuclk called by
> smu_print_ppclk_levels and
>smu_emit_ppclk_levels
>  - emit_clock_levels currently returns the length of the string written to the
> buffer,
>maintaining the behaviour of print_clock_levels, but will be upgraded 
> to
> return
>error values in a subsequent patch
>  - failure of the emit_clock_levels at the top level
> (amdgpu_get_pp_dpm_clock) triggers a
>fallback to the print_clock_levels, which can be removed after
> emit_clock_levels is
>implemented across all platforms.
> 
>(v2)
>   Update to apply on commit 801771de03
>   adjust printing of empty carriage return only if size == 0
> 
>  == Test ==
>  LOGFILE=pp_clk.test.log
>  AMDGPU_PCI_ADDR=`lspci -nn | grep "VGA\|Display" | cut -d " " -f 1`
>  AMDGPU_HWMON=`ls -la /sys/class/hwmon | grep $AMDGPU_PCI_ADDR |
> awk '{print $9}'`
>  HWMON_DIR=/sys/class/hwmon/${AMDGPU_HWMON}
> 
>  lspci -nn | grep "VGA\|Display"  > $LOGFILE
>  FILES="pp_od_clk_voltage
>  pp_dpm_sclk
>  pp_dpm_mclk
>  pp_dpm_pcie
>  pp_dpm_socclk
>  pp_dpm_fclk
>  pp_dpm_dcefclk
>  pp_dpm_vclk
>  pp_dpm_dclk "
> 
>  for f in $FILES
>  do
>echo === $f === >> $LOGFILE
>cat $HWMON_DIR/device/$f >> $LOGFILE
>  done
>  cat $LOGFILE
> 
> Signed-off-by: Darren Powell 
> ---
>  .../gpu/drm/amd/include/kgd_pp_interface.h|   1 +
>  drivers/gpu/drm/amd/pm/amdgpu_dpm.c   |  21 ++
>  drivers/gpu/drm/amd/pm/amdgpu_pm.c|  11 +-
>  drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h   |   4 +
>  drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c |  46 -
>  drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h |  10 +
>  .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c   | 189
> ++
>  7 files changed, 273 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> index a8eec91c0995..8a8eb9411cdf 100644
> --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> @@ -321,6 +321,7 @@ struct amd_pm_funcs {
>   int (*get_fan_speed_pwm)(void *handle, u32 *speed);
>   int (*force_clock_level)(void *handle, enum pp_clock_type type,
> uint32_t mask);
>   int (*print_clock_levels)(void *handle, enum pp_clock_type type,
> char *buf);
> + int (*emit_clock_levels)(void *handle, enum pp_clock_type type,
> char *buf, int *offset);
>   int (*force_performance_level)(void *handle, enum
> amd_dpm_forced_level level);
>   int (*get_sclk_od)(void *handle);
>   int (*set_sclk_od)(void *handle, uint32_t value);
> diff --git a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
> b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
> index 728b6e10f302..e45578124928 100644
> --- a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
> +++ b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
> @@ -906,6 +906,27 @@ int amdgpu_dpm_print_clock_levels(struct
> amdgpu_device *adev,
>   return ret;
>  }
> 
> +int amdgpu_dpm_emit_clock_levels(struct amdgpu_device *adev,
> +   enum pp_clock_type type,
> +   char *buf,
> +   int *offset)
> +{
> + const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
> + int ret = 0;
> +
> + if (!pp_funcs->emit_clock_levels)
> + return 0;
> +
> + mutex_lock(&adev->pm.mutex);
> + ret = pp_funcs->emit_clock_levels(adev->powerplay.pp_handle,
> +type,
> +buf,
> +offset);
> + mutex_unlock(&adev->pm.mutex);
> +
> + return ret;
> +}
> +
>  int amdgpu_dpm_set_ppfeature_status(struct amdgpu_device *adev,
>   uint64_t ppfeature_masks)
>  {
> diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> index d2823aaeca09..ec2729b3930e 100644
> --- a/drivers/gpu/drm/amd

[PATCH 1/2] drm/amd/display: Fix FP start/end for dcn30_internal_validate_bw.

[Bas Nieuwenhuizen]

It calls populate_dml_pipes which uses doubles to initialize the
scale_ratio_depth params. Mirrors the dcn20 logic.

Signed-off-by: Bas Nieuwenhuizen 
---
 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
index 602ec9a08549..8ca26383b568 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
@@ -1878,7 +1878,6 @@ noinline bool dcn30_internal_validate_bw(
dc->res_pool->funcs->update_soc_for_wm_a(dc, context);
pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, 
fast_validate);
 
-   DC_FP_START();
if (!pipe_cnt) {
out = true;
goto validate_out;
@@ -2104,7 +2103,6 @@ noinline bool dcn30_internal_validate_bw(
out = false;
 
 validate_out:
-   DC_FP_END();
return out;
 }
 
@@ -2306,7 +2304,9 @@ bool dcn30_validate_bandwidth(struct dc *dc,
 
BW_VAL_TRACE_COUNT();
 
+   DC_FP_START();
out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, 
&vlevel, fast_validate);
+   DC_FP_END();
 
if (pipe_cnt == 0)
goto validate_out;
-- 
2.34.1

[PATCH 2/2] drm/amd/display: Wrap dcn301_calculate_wm_and_dlg for FPU.

[Bas Nieuwenhuizen]

Mirrors the logic for dcn30. Cue lots of WARNs and some
kernel panics without this fix.

Signed-off-by: Bas Nieuwenhuizen 
---
 .../gpu/drm/amd/display/dc/dcn301/dcn301_resource.c   | 11 +++
 .../gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c|  2 +-
 .../gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.h|  2 +-
 3 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
index b4001233867c..5d9637b07429 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
@@ -1380,6 +1380,17 @@ static void set_wm_ranges(
pp_smu->nv_funcs.set_wm_ranges(&pp_smu->nv_funcs.pp_smu, &ranges);
 }
 
+static void dcn301_calculate_wm_and_dlg(
+   struct dc *dc, struct dc_state *context,
+   display_e2e_pipe_params_st *pipes,
+   int pipe_cnt,
+   int vlevel)
+{
+   DC_FP_START();
+   dcn301_calculate_wm_and_dlg_fp(dc, context, pipes, pipe_cnt, vlevel);
+   DC_FP_END();
+}
+
 static struct resource_funcs dcn301_res_pool_funcs = {
.destroy = dcn301_destroy_resource_pool,
.link_enc_create = dcn301_link_encoder_create,
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c
index 94c32832a0e7..0a7a33864973 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c
@@ -327,7 +327,7 @@ void dcn301_fpu_init_soc_bounding_box(struct bp_soc_bb_info 
bb_info)
dcn3_01_soc.sr_exit_time_us = 
bb_info.dram_sr_exit_latency_100ns * 10;
 }
 
-void dcn301_calculate_wm_and_dlg(struct dc *dc,
+void dcn301_calculate_wm_and_dlg_fp(struct dc *dc,
struct dc_state *context,
display_e2e_pipe_params_st *pipes,
int pipe_cnt,
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.h 
b/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.h
index fc7065d17842..774b0fdfc80b 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.h
@@ -34,7 +34,7 @@ void dcn301_fpu_set_wm_ranges(int i,
 
 void dcn301_fpu_init_soc_bounding_box(struct bp_soc_bb_info bb_info);
 
-void dcn301_calculate_wm_and_dlg(struct dc *dc,
+void dcn301_calculate_wm_and_dlg_fp(struct dc *dc,
struct dc_state *context,
display_e2e_pipe_params_st *pipes,
int pipe_cnt,
-- 
2.34.1

Re: [RFC PATCH v3 1/3] drm: introduce fb_modifiers_not_supported flag in mode_config

[Laurent Pinchart]

Hello Esaki-san,

On Fri, Jan 14, 2022 at 07:17:51PM +0900, Tomohito Esaki wrote:
> If only linear modifier is advertised, since there are many drivers that
> only linear supported, the DRM core should handle this rather than
> open-coding in every driver. However, there are legacy drivers such as
> radeon that do not support modifiers but infer the actual layout of the
> underlying buffer. Therefore, a new flag fb_modifiers_not_supported is
> introduced for these legacy drivers, and allow_fb_modifiers is replaced
> with this new flag.
> 
> Signed-off-by: Tomohito Esaki 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_display.c   |  6 +++---
>  drivers/gpu/drm/amd/amdgpu/dce_v10_0.c|  2 ++
>  drivers/gpu/drm/amd/amdgpu/dce_v11_0.c|  2 ++
>  drivers/gpu/drm/amd/amdgpu/dce_v6_0.c |  1 +
>  drivers/gpu/drm/amd/amdgpu/dce_v8_0.c |  2 ++
>  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  3 +++
>  drivers/gpu/drm/drm_framebuffer.c |  6 +++---
>  drivers/gpu/drm/drm_ioctl.c   |  2 +-
>  drivers/gpu/drm/nouveau/nouveau_display.c |  6 --
>  drivers/gpu/drm/radeon/radeon_display.c   |  2 ++
>  include/drm/drm_mode_config.h | 10 ++
>  11 files changed, 33 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> index 82011e75ed85..edbb30d47b8c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> @@ -954,7 +954,7 @@ static int amdgpu_display_verify_sizes(struct 
> amdgpu_framebuffer *rfb)
>   int ret;
>   unsigned int i, block_width, block_height, block_size_log2;
>  
> - if (!rfb->base.dev->mode_config.allow_fb_modifiers)
> + if (rfb->base.dev->mode_config.fb_modifiers_not_supported)
>   return 0;
>  
>   for (i = 0; i < format_info->num_planes; ++i) {
> @@ -1141,7 +1141,7 @@ int amdgpu_display_framebuffer_init(struct drm_device 
> *dev,
>   if (ret)
>   return ret;
>  
> - if (!dev->mode_config.allow_fb_modifiers) {
> + if (dev->mode_config.fb_modifiers_not_supported) {
>   drm_WARN_ONCE(dev, adev->family >= AMDGPU_FAMILY_AI,
> "GFX9+ requires FB check based on format 
> modifier\n");
>   ret = check_tiling_flags_gfx6(rfb);
> @@ -1149,7 +1149,7 @@ int amdgpu_display_framebuffer_init(struct drm_device 
> *dev,
>   return ret;
>   }
>  
> - if (dev->mode_config.allow_fb_modifiers &&
> + if (!dev->mode_config.fb_modifiers_not_supported &&
>   !(rfb->base.flags & DRM_MODE_FB_MODIFIERS)) {
>   ret = convert_tiling_flags_to_modifier(rfb);
>   if (ret) {
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 
> b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> index d1570a462a51..fb61c0814115 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> @@ -2798,6 +2798,8 @@ static int dce_v10_0_sw_init(void *handle)
>   adev_to_drm(adev)->mode_config.preferred_depth = 24;
>   adev_to_drm(adev)->mode_config.prefer_shadow = 1;
>  
> + adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true;
> +
>   adev_to_drm(adev)->mode_config.fb_base = adev->gmc.aper_base;
>  
>   r = amdgpu_display_modeset_create_props(adev);
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 
> b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> index 18a7b3bd633b..17942a11366d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> @@ -2916,6 +2916,8 @@ static int dce_v11_0_sw_init(void *handle)
>   adev_to_drm(adev)->mode_config.preferred_depth = 24;
>   adev_to_drm(adev)->mode_config.prefer_shadow = 1;
>  
> + adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true;
> +
>   adev_to_drm(adev)->mode_config.fb_base = adev->gmc.aper_base;
>  
>   r = amdgpu_display_modeset_create_props(adev);
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 
> b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> index c7803dc2b2d5..2ec99ec8e1a3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> @@ -2674,6 +2674,7 @@ static int dce_v6_0_sw_init(void *handle)
>   adev_to_drm(adev)->mode_config.max_height = 16384;
>   adev_to_drm(adev)->mode_config.preferred_depth = 24;
>   adev_to_drm(adev)->mode_config.prefer_shadow = 1;
> + adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true;
>   adev_to_drm(adev)->mode_config.fb_base = adev->gmc.aper_base;
>  
>   r = amdgpu_display_modeset_create_props(adev);
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 
> b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
> index 8318ee8339f1..de11fbe5aba2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_

Re: [RFC PATCH v3 3/3] drm: remove allow_fb_modifiers

[Laurent Pinchart]

Hello Esaki-san,

Thank you for the patch.

On Fri, Jan 14, 2022 at 07:17:53PM +0900, Tomohito Esaki wrote:
> The allow_fb_modifiers flag is unnecessary since it has been replaced
> with cannot_support_modifiers flag.

The new flag is fb_modifiers_not_supported, not
cannot_support_modifiers.

> Signed-off-by: Tomohito Esaki 
> ---
>  drivers/gpu/drm/drm_plane.c  |  9 -
>  drivers/gpu/drm/selftests/test-drm_framebuffer.c |  1 -
>  include/drm/drm_mode_config.h| 16 
>  3 files changed, 26 deletions(-)
> 
> diff --git a/drivers/gpu/drm/drm_plane.c b/drivers/gpu/drm/drm_plane.c
> index 5aa7e241971e..89a3d044ab59 100644
> --- a/drivers/gpu/drm/drm_plane.c
> +++ b/drivers/gpu/drm/drm_plane.c
> @@ -288,15 +288,6 @@ static int __drm_universal_plane_init(struct drm_device 
> *dev,
>   }
>   }
>  
> - /* autoset the cap and check for consistency across all planes */
> - if (format_modifier_count) {
> - drm_WARN_ON(dev, !config->allow_fb_modifiers &&
> - !list_empty(&config->plane_list));
> - config->allow_fb_modifiers = true;
> - } else {
> - drm_WARN_ON(dev, config->allow_fb_modifiers);
> - }
> -

Shouldn't we keep a sanity check to ensure that drivers setting
fb_modifiers_not_supported do not pass modifiers ?

drm_WARN_ON(dev, config->fb_modifiers_not_supported &&
format_modifier_count);

Reviewed-by: Laurent Pinchart 

>   plane->modifier_count = format_modifier_count;
>   plane->modifiers = kmalloc_array(format_modifier_count,
>sizeof(format_modifiers[0]),
> diff --git a/drivers/gpu/drm/selftests/test-drm_framebuffer.c 
> b/drivers/gpu/drm/selftests/test-drm_framebuffer.c
> index 61b44d3a6a61..f6d66285c5fc 100644
> --- a/drivers/gpu/drm/selftests/test-drm_framebuffer.c
> +++ b/drivers/gpu/drm/selftests/test-drm_framebuffer.c
> @@ -323,7 +323,6 @@ static struct drm_device mock_drm_device = {
>   .max_width = MAX_WIDTH,
>   .min_height = MIN_HEIGHT,
>   .max_height = MAX_HEIGHT,
> - .allow_fb_modifiers = true,
>   .funcs = &mock_config_funcs,
>   },
>  };
> diff --git a/include/drm/drm_mode_config.h b/include/drm/drm_mode_config.h
> index da82f45351c7..5001bda9f9af 100644
> --- a/include/drm/drm_mode_config.h
> +++ b/include/drm/drm_mode_config.h
> @@ -917,22 +917,6 @@ struct drm_mode_config {
>*/
>   bool async_page_flip;
>  
> - /**
> -  * @allow_fb_modifiers:
> -  *
> -  * Whether the driver supports fb modifiers in the ADDFB2.1 ioctl call.
> -  * Note that drivers should not set this directly, it is automatically
> -  * set in drm_universal_plane_init().
> -  *
> -  * IMPORTANT:
> -  *
> -  * If this is set the driver must fill out the full implicit modifier
> -  * information in their &drm_mode_config_funcs.fb_create hook for legacy
> -  * userspace which does not set modifiers. Otherwise the GETFB2 ioctl is
> -  * broken for modifier aware userspace.
> -  */
> - bool allow_fb_modifiers;
> -
>   /**
>* @fb_modifiers_not_supported:
>*

-- 
Regards,

Laurent Pinchart

Re: [RFC PATCH v3 2/3] drm: add support modifiers for drivers whose planes only support linear layout

[Laurent Pinchart]

Hello Esaki-san,

Thank you for the patch.

On Fri, Jan 14, 2022 at 07:17:52PM +0900, Tomohito Esaki wrote:
> The LINEAR modifier is advertised as default if a driver doesn't specify
> modifiers.
> 
> Signed-off-by: Tomohito Esaki 
> ---
>  drivers/gpu/drm/drm_plane.c | 15 ---
>  include/drm/drm_plane.h |  3 +++
>  2 files changed, 15 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/drm_plane.c b/drivers/gpu/drm/drm_plane.c
> index deeec60a3315..5aa7e241971e 100644
> --- a/drivers/gpu/drm/drm_plane.c
> +++ b/drivers/gpu/drm/drm_plane.c
> @@ -237,6 +237,10 @@ static int __drm_universal_plane_init(struct drm_device 
> *dev,
> const char *name, va_list ap)
>  {
>   struct drm_mode_config *config = &dev->mode_config;
> + const uint64_t default_modifiers[] = {

This can be static.

> + DRM_FORMAT_MOD_LINEAR,
> + DRM_FORMAT_MOD_INVALID

No need for a terminator here. The terminator is needed in the
format_modifiers array passed to this function, to count the number of
elements, but the default_modifiers is used with a hard-coded count.

> + };
>   unsigned int format_modifier_count = 0;
>   int ret;
>  
> @@ -277,6 +281,11 @@ static int __drm_universal_plane_init(struct drm_device 
> *dev,
>  
>   while (*temp_modifiers++ != DRM_FORMAT_MOD_INVALID)
>   format_modifier_count++;
> + } else {
> + if (!dev->mode_config.fb_modifiers_not_supported) {
> + format_modifiers = default_modifiers;
> + format_modifier_count = 1;

You can use

format_modifier_count = ARRAY_SIZE(default_modifiers);

> + }
>   }
>  
>   /* autoset the cap and check for consistency across all planes */
> @@ -341,7 +350,7 @@ static int __drm_universal_plane_init(struct drm_device 
> *dev,
>   drm_object_attach_property(&plane->base, config->prop_src_h, 0);
>   }
>  
> - if (config->allow_fb_modifiers)
> + if (format_modifier_count)
>   create_in_format_blob(dev, plane);
>  
>   return 0;
> @@ -368,8 +377,8 @@ static int __drm_universal_plane_init(struct drm_device 
> *dev,
>   * drm_universal_plane_init() to let the DRM managed resource infrastructure
>   * take care of cleanup and deallocation.
>   *
> - * Drivers supporting modifiers must set @format_modifiers on all their 
> planes,
> - * even those that only support DRM_FORMAT_MOD_LINEAR.
> + * For drivers supporting modifiers, all planes will advertise
> + * DRM_FORMAT_MOD_LINEAR support, if @format_modifiers is not set.

I'd write this a bit differently:

 * Drivers that only support the DRM_FORMAT_MOD_LINEAR modifier support may set
 * @format_modifiers to NULL. The plane will advertise the linear modifier.

As fb_modifiers_not_supported is only for a few legacy drivers, I
wouldn't even mention it here, it would only obfuscate things.

>   *
>   * Returns:
>   * Zero on success, error code on failure.
> diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h
> index 0c1102dc4d88..cad641b1f797 100644
> --- a/include/drm/drm_plane.h
> +++ b/include/drm/drm_plane.h
> @@ -803,6 +803,9 @@ void *__drmm_universal_plane_alloc(struct drm_device *dev,
>   *
>   * The @drm_plane_funcs.destroy hook must be NULL.
>   *
> + * For drivers supporting modifiers, all planes will advertise
> + * DRM_FORMAT_MOD_LINEAR support, if @format_modifiers is not set.

Same here.

With these small issues addressed,

Reviewed-by: Laurent Pinchart 

> + *
>   * Returns:
>   * Pointer to new plane, or ERR_PTR on failure.
>   */

-- 
Regards,

Laurent Pinchart

[PATCH 19/24] drm/amd/display: Remove unnecessary function definition

[Rodrigo Siqueira]

From: Aric Cyr 

Acked-by: Rodrigo Siqueira 
Signed-off-by: Aric Cyr 
---
 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c | 5 -
 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h | 3 ---
 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c  | 2 +-
 3 files changed, 1 insertion(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
index dec8604a0612..ed0a0e5fd805 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
@@ -355,11 +355,6 @@ void dcn30_prepare_bandwidth(struct dc *dc,
dcn20_prepare_bandwidth(dc, context);
 }
 
-void dcn30_optimize_bandwidth(struct dc *dc, struct dc_state *context)
-{
-   dcn20_optimize_bandwidth(dc, context);
-}
-
 void dcn30_disable_writeback(
struct dc *dc,
unsigned int dwb_pipe_inst)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h 
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h
index 357ee14711ad..73e7b690e82c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h
@@ -50,9 +50,6 @@ void dcn30_disable_writeback(
 void dcn30_prepare_bandwidth(struct dc *dc,
struct dc_state *context);
 
-void dcn30_optimize_bandwidth(struct dc *dc,
-   struct dc_state *context);
-
 bool dcn30_mmhubbub_warmup(
struct dc *dc,
unsigned int num_dwb,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c 
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c
index 73a416cba563..bb347319de83 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c
@@ -60,7 +60,7 @@ static const struct hw_sequencer_funcs dcn30_funcs = {
.interdependent_update_lock = dcn10_lock_all_pipes,
.cursor_lock = dcn10_cursor_lock,
.prepare_bandwidth = dcn20_prepare_bandwidth,
-   .optimize_bandwidth = dcn30_optimize_bandwidth,
+   .optimize_bandwidth = dcn20_optimize_bandwidth,
.update_bandwidth = dcn20_update_bandwidth,
.set_drr = dcn10_set_drr,
.get_position = dcn10_get_position,
-- 
2.25.1

[PATCH 21/24] drm/amd/display: Fix disabling dccg clocks

[Rodrigo Siqueira]

From: David Galiffi 

[How & Why]
Updated procedure to match hardware programming guide.

Reviewed-by: Eric Yang 
Acked-by: Rodrigo Siqueira 
Signed-off-by: David Galiffi 
---
 .../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h |  7 +++
 .../gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c | 44 ---
 .../gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h |  1 +
 3 files changed, 37 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
index f98aba308028..493c47a3d06e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
@@ -183,8 +183,14 @@
type SYMCLK32_ROOT_SE1_GATE_DISABLE;\
type SYMCLK32_ROOT_SE2_GATE_DISABLE;\
type SYMCLK32_ROOT_SE3_GATE_DISABLE;\
+   type SYMCLK32_SE0_GATE_DISABLE;\
+   type SYMCLK32_SE1_GATE_DISABLE;\
+   type SYMCLK32_SE2_GATE_DISABLE;\
+   type SYMCLK32_SE3_GATE_DISABLE;\
type SYMCLK32_ROOT_LE0_GATE_DISABLE;\
type SYMCLK32_ROOT_LE1_GATE_DISABLE;\
+   type SYMCLK32_LE0_GATE_DISABLE;\
+   type SYMCLK32_LE1_GATE_DISABLE;\
type DPSTREAMCLK_ROOT_GATE_DISABLE;\
type DPSTREAMCLK_GATE_DISABLE;\
type HDMISTREAMCLK0_DTO_PHASE;\
@@ -233,6 +239,7 @@ struct dccg_registers {
uint32_t DSCCLK2_DTO_PARAM;
uint32_t DPSTREAMCLK_ROOT_GATE_DISABLE;
uint32_t DPSTREAMCLK_GATE_DISABLE;
+   uint32_t DCCG_GATE_DISABLE_CNTL2;
uint32_t DCCG_GATE_DISABLE_CNTL3;
uint32_t HDMISTREAMCLK0_DTO_PARAM;
uint32_t DCCG_GATE_DISABLE_CNTL4;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c 
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
index ea4f8e06b07c..720bd35582b0 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
@@ -121,7 +121,8 @@ static void dccg31_enable_dpstreamclk(struct dccg *dccg, 
int otg_inst)
return;
}
if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)
-   REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,
+   REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
+   DPSTREAMCLK_GATE_DISABLE, 1,
DPSTREAMCLK_ROOT_GATE_DISABLE, 1);
 }
 
@@ -130,8 +131,9 @@ static void dccg31_disable_dpstreamclk(struct dccg *dccg, 
int otg_inst)
struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
 
if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)
-   REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,
-   DPSTREAMCLK_ROOT_GATE_DISABLE, 0);
+   REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
+   DPSTREAMCLK_ROOT_GATE_DISABLE, 0,
+   DPSTREAMCLK_GATE_DISABLE, 0);
 
switch (otg_inst) {
case 0:
@@ -180,7 +182,8 @@ void dccg31_enable_symclk32_se(
switch (hpo_se_inst) {
case 0:
if 
(dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
-   REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,
+   REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
+   SYMCLK32_SE0_GATE_DISABLE, 1,
SYMCLK32_ROOT_SE0_GATE_DISABLE, 1);
REG_UPDATE_2(SYMCLK32_SE_CNTL,
SYMCLK32_SE0_SRC_SEL, phyd32clk,
@@ -188,7 +191,8 @@ void dccg31_enable_symclk32_se(
break;
case 1:
if 
(dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
-   REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,
+   REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
+   SYMCLK32_SE1_GATE_DISABLE, 1,
SYMCLK32_ROOT_SE1_GATE_DISABLE, 1);
REG_UPDATE_2(SYMCLK32_SE_CNTL,
SYMCLK32_SE1_SRC_SEL, phyd32clk,
@@ -196,7 +200,8 @@ void dccg31_enable_symclk32_se(
break;
case 2:
if 
(dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
-   REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,
+   REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
+   SYMCLK32_SE2_GATE_DISABLE, 1,
SYMCLK32_ROOT_SE2_GATE_DISABLE, 1);
REG_UPDATE_2(SYMCLK32_SE_CNTL,
SYMCLK32_SE2_SRC_SEL, phyd32clk,
@@ -204,7 +209,8 @@ void dccg31_enable_symclk32_se(
break;
case 3:
if 
(dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
-   REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,
+   REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
+   SYMCLK32_SE3_GATE_DISABLE, 1,
SYMCLK32_ROOT_SE3_GA

[PATCH 24/24] drm/amd/display: add debug option for z9 disable interface

[Rodrigo Siqueira]

From: Eric Yang 

[Why]
To help triage issues and coordinate driver/bios release dependency

[How]
Only enable the new Z9 interface when debug option is set, otherwise
treat Z10 only support case as Zstate disallowed.

Reviewed-by: Nicholas Kazlauskas 
Acked-by: Rodrigo Siqueira 
Signed-off-by: Eric Yang 
---
 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c | 6 +-
 drivers/gpu/drm/amd/display/dc/dc.h  | 1 +
 drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c| 1 +
 3 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
index 1c0415366216..9b4836350547 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
@@ -308,12 +308,16 @@ void dcn31_smu_transfer_wm_table_dram_2_smu(struct 
clk_mgr_internal *clk_mgr)
 
 void dcn31_smu_set_zstate_support(struct clk_mgr_internal *clk_mgr, enum 
dcn_zstate_support_state support)
 {
-   //TODO: Work with smu team to define optimization options.
unsigned int msg_id, param;
 
if (!clk_mgr->smu_present)
return;
 
+   if (!clk_mgr->base.ctx->dc->debug.enable_z9_disable_interface &&
+   (support == DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY))
+   support = DCN_ZSTATE_SUPPORT_DISALLOW;
+
+
if (support == DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY)
param = 1;
else
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 69cf78fe78cf..4f9dacd09856 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -703,6 +703,7 @@ struct dc_debug_options {
int crb_alloc_policy_min_disp_count;
 #if defined(CONFIG_DRM_AMD_DC_DCN)
bool disable_z10;
+   bool enable_z9_disable_interface;
bool enable_sw_cntl_psr;
union dpia_debug_options dpia_debug;
 #endif
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
index 40778c05f9b3..7f9ceda4229b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
@@ -1033,6 +1033,7 @@ static const struct dc_debug_options debug_defaults_drv = 
{
.optimize_edp_link_rate = true,
.enable_sw_cntl_psr = true,
.apply_vendor_specific_lttpr_wa = true,
+   .enable_z9_disable_interface = false
 };
 
 static const struct dc_debug_options debug_defaults_diags = {
-- 
2.25.1

[PATCH 23/24] drm/amd/display: fix zstate allow interface to PMFW

[Rodrigo Siqueira]

From: Eric Yang 

[Why]
psr_feature_enabled flag is dynamically updated, and sometimes when
zstate allow status is determined the flag has not been set to true yet
even on PSR enabled config, lid off/on is such a case, which will result
in zstate disabled even though PSR is supported.

[How]
Check the supported PSR version and the PSR disable status instead.

Reviewed-by: Nicholas Kazlauskas 
Acked-by: Rodrigo Siqueira 
Signed-off-by: Eric Yang 
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index d0a5c7afa265..fcf388b509db 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -3099,7 +3099,7 @@ static enum dcn_zstate_support_state  
decide_zstate_support(struct dc *dc, struc
 
if (context->bw_ctx.dml.vba.StutterPeriod > 5000.0)
return DCN_ZSTATE_SUPPORT_ALLOW;
-   else if (link->psr_settings.psr_feature_enabled)
+   else if (link->psr_settings.psr_version == DC_PSR_VERSION_1 && 
!dc->debug.disable_psr)
return DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY;
else
return DCN_ZSTATE_SUPPORT_DISALLOW;
-- 
2.25.1

[PATCH 20/24] drm/amd/display: allow set dp drive setting when stream is not present

[Rodrigo Siqueira]

From: Wenjing Liu 

[why]
There is a change previously to disallow DM to set dp drive setings when
stream is not present. The logic might not work well with DP PHY
complaince scenario with a PHY test fixture attachment. We need to make
the method allow DP link drive settings changes even without stream
attached to it.

[how]
revert back to previous code in set drive setting function then add an
empty link_resource structure, then assign link resource based on
current link resource if link resource is allocated to the current pipe.

Reviewed-by: Wayne Lin 
Acked-by: Rodrigo Siqueira 
Signed-off-by: Wenjing Liu 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 30 ---
 drivers/gpu/drm/amd/display/dc/dc_link.h  |  3 +-
 2 files changed, 15 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index d0aba8d7b1c3..6be2ae743cc5 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -4454,22 +4454,17 @@ void dc_link_set_drive_settings(struct dc *dc,
 {
 
int i;
-   struct pipe_ctx *pipe = NULL;
-   const struct link_resource *link_res;
+   struct link_resource link_res;
 
-   link_res = dc_link_get_cur_link_res(link);
+   for (i = 0; i < dc->link_count; i++)
+   if (dc->links[i] == link)
+   break;
 
-   for (i = 0; i < MAX_PIPES; i++) {
-   pipe = &dc->current_state->res_ctx.pipe_ctx[i];
-   if (pipe->stream && pipe->stream->link) {
-   if (pipe->stream->link == link)
-   break;
-   }
-   }
-   if (pipe && link_res)
-   dc_link_dp_set_drive_settings(pipe->stream->link, link_res, 
lt_settings);
-   else
+   if (i >= dc->link_count)
ASSERT_CRITICAL(false);
+
+   dc_link_get_cur_link_res(link, &link_res);
+   dc_link_dp_set_drive_settings(dc->links[i], &link_res, lt_settings);
 }
 
 void dc_link_set_preferred_link_settings(struct dc *dc,
@@ -4711,23 +4706,24 @@ uint32_t dc_bandwidth_in_kbps_from_timing(
 
 }
 
-const struct link_resource *dc_link_get_cur_link_res(const struct dc_link 
*link)
+void dc_link_get_cur_link_res(const struct dc_link *link,
+   struct link_resource *link_res)
 {
int i;
struct pipe_ctx *pipe = NULL;
-   const struct link_resource *link_res = NULL;
+
+   memset(link_res, 0, sizeof(*link_res));
 
for (i = 0; i < MAX_PIPES; i++) {
pipe = &link->dc->current_state->res_ctx.pipe_ctx[i];
if (pipe->stream && pipe->stream->link && pipe->top_pipe == 
NULL) {
if (pipe->stream->link == link) {
-   link_res = &pipe->link_res;
+   *link_res = pipe->link_res;
break;
}
}
}
 
-   return link_res;
 }
 
 /**
diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h 
b/drivers/gpu/drm/amd/display/dc/dc_link.h
index b1c79b3f26aa..6c02244e7fe7 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_link.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
@@ -459,7 +459,8 @@ bool dc_link_should_enable_fec(const struct dc_link *link);
 uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(uint8_t bw);
 enum dp_link_encoding dc_link_dp_mst_decide_link_encoding_format(const struct 
dc_link *link);
 
-const struct link_resource *dc_link_get_cur_link_res(const struct dc_link 
*link);
+void dc_link_get_cur_link_res(const struct dc_link *link,
+   struct link_resource *link_res);
 /* take a snapshot of current link resource allocation state */
 void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map);
 /* restore link resource allocation state from a snapshot */
-- 
2.25.1

[PATCH 18/24] drm/amd/display: 3.2.170

[Rodrigo Siqueira]

From: Aric Cyr 

This version brings along the following fixes:

- Z9 improvements
- Clocks management adjustments
- Code cleanup
- Improve DSC and MST code

Acked-by: Rodrigo Siqueira 
Signed-off-by: Aric Cyr 
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 0dc183d6af5d..69cf78fe78cf 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -47,7 +47,7 @@ struct aux_payload;
 struct set_config_cmd_payload;
 struct dmub_notification;
 
-#define DC_VER "3.2.169"
+#define DC_VER "3.2.170"
 
 #define MAX_SURFACES 3
 #define MAX_PLANES 6
-- 
2.25.1

[PATCH 22/24] drm/amd/display: Disable physym clock

[Rodrigo Siqueira]

From: David Galiffi 

[How & Why]
Disable physym clock when it's not in use.

Reviewed-by: Eric Yang 
Acked-by: Rodrigo Siqueira 
Signed-off-by: David Galiffi 
---
 .../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h |  8 ++-
 .../gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c | 62 ---
 .../gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h |  5 ++
 3 files changed, 63 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
index 493c47a3d06e..b3c9a9724efd 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
@@ -196,8 +196,12 @@
type HDMISTREAMCLK0_DTO_PHASE;\
type HDMISTREAMCLK0_DTO_MODULO;\
type HDMICHARCLK0_GATE_DISABLE;\
-   type HDMICHARCLK0_ROOT_GATE_DISABLE;
-
+   type HDMICHARCLK0_ROOT_GATE_DISABLE; \
+   type PHYASYMCLK_GATE_DISABLE; \
+   type PHYBSYMCLK_GATE_DISABLE; \
+   type PHYCSYMCLK_GATE_DISABLE; \
+   type PHYDSYMCLK_GATE_DISABLE; \
+   type PHYESYMCLK_GATE_DISABLE;
 
 struct dccg_shift {
DCCG_REG_FIELD_LIST(uint8_t)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c 
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
index 720bd35582b0..287a1066b547 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
@@ -420,54 +420,89 @@ void dccg31_set_physymclk(
/* Force PHYSYMCLK on and Select phyd32clk as the source of clock which 
is output to PHY through DCIO */
switch (phy_inst) {
case 0:
-   if (force_enable)
+   if (force_enable) {
REG_UPDATE_2(PHYASYMCLK_CLOCK_CNTL,
PHYASYMCLK_FORCE_EN, 1,
PHYASYMCLK_FORCE_SRC_SEL, clk_src);
-   else
+   if 
(dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)
+   REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
+   PHYASYMCLK_GATE_DISABLE, 1);
+   } else {
REG_UPDATE_2(PHYASYMCLK_CLOCK_CNTL,
PHYASYMCLK_FORCE_EN, 0,
PHYASYMCLK_FORCE_SRC_SEL, 0);
+   if 
(dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)
+   REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
+   PHYASYMCLK_GATE_DISABLE, 0);
+   }
break;
case 1:
-   if (force_enable)
+   if (force_enable) {
REG_UPDATE_2(PHYBSYMCLK_CLOCK_CNTL,
PHYBSYMCLK_FORCE_EN, 1,
PHYBSYMCLK_FORCE_SRC_SEL, clk_src);
-   else
+   if 
(dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)
+   REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
+   PHYBSYMCLK_GATE_DISABLE, 1);
+   } else {
REG_UPDATE_2(PHYBSYMCLK_CLOCK_CNTL,
PHYBSYMCLK_FORCE_EN, 0,
PHYBSYMCLK_FORCE_SRC_SEL, 0);
+   if 
(dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)
+   REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
+   PHYBSYMCLK_GATE_DISABLE, 0);
+   }
break;
case 2:
-   if (force_enable)
+   if (force_enable) {
REG_UPDATE_2(PHYCSYMCLK_CLOCK_CNTL,
PHYCSYMCLK_FORCE_EN, 1,
PHYCSYMCLK_FORCE_SRC_SEL, clk_src);
-   else
+   if 
(dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)
+   REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
+   PHYCSYMCLK_GATE_DISABLE, 1);
+   } else {
REG_UPDATE_2(PHYCSYMCLK_CLOCK_CNTL,
PHYCSYMCLK_FORCE_EN, 0,
PHYCSYMCLK_FORCE_SRC_SEL, 0);
+   if 
(dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)
+   REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
+   PHYCSYMCLK_GATE_DISABLE, 0);
+   }
break;
case 3:
-   if (force_enable)
+   if (force_enable) {
REG_UPDATE_2(PHYDSYMCLK_CLOCK_CNTL,
PHYDSYMCLK_FORCE_EN, 1,
PHYDSYMCLK_FORCE_SRC_SEL, clk_src);
-   else
+  

[PATCH 17/24] drm/amd/display: Reset preferred training settings immediately

[Rodrigo Siqueira]

From: Wayne Lin 

[Why & How]
In order to easily test ilr by immediately reset the preferred training 
settings,
fix the code to disable skip_immediate_retrain.

Reviewed-by: Solomon Chiu 
Acked-by: Rodrigo Siqueira 
Signed-off-by: Wayne Lin 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index ded64d0e34c1..c783643d2940 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -2851,7 +2851,7 @@ static ssize_t edp_ilr_write(struct file *f, const char 
__user *buf,
kfree(wr_buf);
DRM_DEBUG_DRIVER("Invalid Input value. No HW will be 
programmed\n");
prefer_link_settings.use_link_rate_set = false;
-   dc_link_set_preferred_training_settings(dc, NULL, NULL, link, 
true);
+   dc_link_set_preferred_training_settings(dc, NULL, NULL, link, 
false);
return size;
}
 
-- 
2.25.1

[PATCH 15/24] drm/amd/display: Update VSC HDR infoPacket on TF change

[Rodrigo Siqueira]

From: Reza Amini 

[why]
OnSetSourceContentAttribute it does not trigger an update for the VSC
with TF change.

[how]
In this call, create a new VSC infoPacket based on the new config, and
allow DisplayTarget decide if an update and pursuant passive flip is
necessary

Reviewed-by: Krunoslav Kovac 
Acked-by: Rodrigo Siqueira 
Signed-off-by: Reza Amini 
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  2 +-
 .../amd/display/modules/inc/mod_info_packet.h |  3 ++-
 .../display/modules/info_packet/info_packet.c | 25 ++-
 3 files changed, 16 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 94b4d7f70e45..fa2c1a3efbbf 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -6494,7 +6494,7 @@ create_stream_for_sink(struct amdgpu_dm_connector 
*aconnector,
if 
(stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED)
stream->use_vsc_sdp_for_colorimetry = true;
}
-   mod_build_vsc_infopacket(stream, &stream->vsc_infopacket);
+   mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, 
stream->output_color_space);
aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY;
 
}
diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet.h 
b/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet.h
index 1ab813b4fd14..1d8b746b02f2 100644
--- a/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet.h
+++ b/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet.h
@@ -34,7 +34,8 @@ struct dc_info_packet;
 struct mod_vrr_params;
 
 void mod_build_vsc_infopacket(const struct dc_stream_state *stream,
-   struct dc_info_packet *info_packet);
+   struct dc_info_packet *info_packet,
+   enum dc_color_space cs);
 
 void mod_build_hf_vsif_infopacket(const struct dc_stream_state *stream,
struct dc_info_packet *info_packet);
diff --git a/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c 
b/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c
index 57f198de5e2c..b691aa45e84f 100644
--- a/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c
+++ b/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c
@@ -130,7 +130,8 @@ enum ColorimetryYCCDP {
 };
 
 void mod_build_vsc_infopacket(const struct dc_stream_state *stream,
-   struct dc_info_packet *info_packet)
+   struct dc_info_packet *info_packet,
+   enum dc_color_space cs)
 {
unsigned int vsc_packet_revision = vsc_packet_undefined;
unsigned int i;
@@ -331,13 +332,13 @@ void mod_build_vsc_infopacket(const struct 
dc_stream_state *stream,
/* Set Colorimetry format based on pixel encoding */
switch (stream->timing.pixel_encoding) {
case PIXEL_ENCODING_RGB:
-   if ((stream->output_color_space == COLOR_SPACE_SRGB) ||
-   (stream->output_color_space == 
COLOR_SPACE_SRGB_LIMITED))
+   if ((cs == COLOR_SPACE_SRGB) ||
+   (cs == COLOR_SPACE_SRGB_LIMITED))
colorimetryFormat = ColorimetryRGB_DP_sRGB;
-   else if (stream->output_color_space == 
COLOR_SPACE_ADOBERGB)
+   else if (cs == COLOR_SPACE_ADOBERGB)
colorimetryFormat = ColorimetryRGB_DP_AdobeRGB;
-   else if ((stream->output_color_space == 
COLOR_SPACE_2020_RGB_FULLRANGE) ||
-   (stream->output_color_space == 
COLOR_SPACE_2020_RGB_LIMITEDRANGE))
+   else if ((cs == COLOR_SPACE_2020_RGB_FULLRANGE) ||
+   (cs == 
COLOR_SPACE_2020_RGB_LIMITEDRANGE))
colorimetryFormat = 
ColorimetryRGB_DP_ITU_R_BT2020RGB;
break;
 
@@ -347,13 +348,13 @@ void mod_build_vsc_infopacket(const struct 
dc_stream_state *stream,
/* Note: xvYCC probably not supported correctly here on 
DP since colorspace translation
 * loses distinction between BT601 vs xvYCC601 in 
translation
 */
-   if (stream->output_color_space == COLOR_SPACE_YCBCR601)
+   if (cs == COLOR_SPACE_YCBCR601)
colorimetryFormat = ColorimetryYCC_DP_ITU601;
-   else if (stream->output_color_space == 
COLOR_SPACE_YCBCR709)
+   else if (cs == COLOR_SPACE_YCBCR709)
colorimetryFormat = ColorimetryYCC_DP_ITU709;
-   else if (stream->output_color_space == 
COLOR_SPACE_ADOBERGB)
+

[PATCH 14/24] drm/amd/display: remove PHY repeater count check for LTTPR mode

[Rodrigo Siqueira]

From: Sung Joon Kim 

[why]
Due to bad hardware, the PHY repeater count in LTTPR cap is read as 0xFF
in some monitors while the LTTPR is actually present.

[how]
Remove PHY repeater counter check when configuring LTTPR mode.

Reviewed-by: Jun Lei 
Acked-by: Rodrigo Siqueira 
Signed-off-by: Sung Joon Kim 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 0033d2a0cfe5..f7ddba9cc63a 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -5069,9 +5069,8 @@ bool dp_retrieve_lttpr_cap(struct dc_link *link)

DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
 
/* Attempt to train in LTTPR transparent mode if repeater count 
exceeds 8. */
-   is_lttpr_present = 
(dp_convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt) != 0 &&
+   is_lttpr_present = (link->dpcd_caps.lttpr_caps.max_lane_count > 
0 &&
link->dpcd_caps.lttpr_caps.phy_repeater_cnt < 
0xff &&
-   link->dpcd_caps.lttpr_caps.max_lane_count > 0 &&
link->dpcd_caps.lttpr_caps.max_lane_count <= 4 
&&
link->dpcd_caps.lttpr_caps.revision.raw >= 
0x14);
if (is_lttpr_present) {
-- 
2.25.1

[PATCH 13/24] drm/amd/display: Basic support with device ID

[Rodrigo Siqueira]

From: Oliver Logush 

[why]
Need to add Cyan Skillfish support by adding the correct Device ID

Reviewed-by: Charlene Liu 
Acked-by: Rodrigo Siqueira 
Signed-off-by: Oliver Logush 
---
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 3 ++-
 drivers/gpu/drm/amd/display/include/dal_asic_id.h | 2 ++
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 3aa6d347d73c..5642f93a7c76 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -131,7 +131,8 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id 
asic_id)
 
case FAMILY_NV:
dc_version = DCN_VERSION_2_0;
-   if (asic_id.chip_id == DEVICE_ID_NV_13FE) {
+
+   if (asic_id.chip_id == DEVICE_ID_NV_13FE || asic_id.chip_id == 
DEVICE_ID_NV_NAVI10_LITE_P_1400) {
dc_version = DCN_VERSION_2_01;
break;
}
diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h 
b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
index e4a2dfacab4c..707abe96f928 100644
--- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
+++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
@@ -255,6 +255,8 @@ enum {
 #define DEVICE_ID_TEMASH_9839 0x9839
 #define DEVICE_ID_TEMASH_983D 0x983D
 
+#define DEVICE_ID_NV_NAVI10_LITE_P_14000x1400 // 
CYAN_SKILLFISH
+
 /* RENOIR */
 #define DEVICE_ID_RENOIR_1636 0x1636
 
-- 
2.25.1

[PATCH 12/24] drm/amd/display: Support synchronized indirect reg access

[Rodrigo Siqueira]

From: Roy Chan 

[Why]
indirect register index/data pair may be used by multi-threads.  when it
happens, it would cause register access issue that is hard to trace.

[How]
Using cgs service, which provide a sync indirect reg access api.

Reviewed-by: Aric Cyr 
Acked-by: Rodrigo Siqueira 
Signed-off-by: Roy Chan 
---
 drivers/gpu/drm/amd/display/dc/dc_helper.c| 60 +++
 .../gpu/drm/amd/display/dc/inc/reg_helper.h   | 34 +++
 2 files changed, 94 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dc_helper.c 
b/drivers/gpu/drm/amd/display/dc/dc_helper.c
index a612ba6dc389..05ad9f52b9c7 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_helper.c
@@ -588,6 +588,66 @@ uint32_t generic_indirect_reg_update_ex(const struct 
dc_context *ctx,
return reg_val;
 }
 
+
+uint32_t generic_indirect_reg_update_ex_sync(const struct dc_context *ctx,
+   uint32_t index, uint32_t reg_val, int n,
+   uint8_t shift1, uint32_t mask1, uint32_t field_value1,
+   ...)
+{
+   uint32_t shift, mask, field_value;
+   int i = 1;
+
+   va_list ap;
+
+   va_start(ap, field_value1);
+
+   reg_val = set_reg_field_value_ex(reg_val, field_value1, mask1, shift1);
+
+   while (i < n) {
+   shift = va_arg(ap, uint32_t);
+   mask = va_arg(ap, uint32_t);
+   field_value = va_arg(ap, uint32_t);
+
+   reg_val = set_reg_field_value_ex(reg_val, field_value, mask, 
shift);
+   i++;
+   }
+
+   dm_write_index_reg(ctx, CGS_IND_REG__PCIE, index, reg_val);
+   va_end(ap);
+
+   return reg_val;
+}
+
+uint32_t generic_indirect_reg_get_sync(const struct dc_context *ctx,
+   uint32_t index, int n,
+   uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
+   ...)
+{
+   uint32_t shift, mask, *field_value;
+   uint32_t value = 0;
+   int i = 1;
+
+   va_list ap;
+
+   va_start(ap, field_value1);
+
+   value = dm_read_index_reg(ctx, CGS_IND_REG__PCIE, index);
+   *field_value1 = get_reg_field_value_ex(value, mask1, shift1);
+
+   while (i < n) {
+   shift = va_arg(ap, uint32_t);
+   mask = va_arg(ap, uint32_t);
+   field_value = va_arg(ap, uint32_t *);
+
+   *field_value = get_reg_field_value_ex(value, mask, shift);
+   i++;
+   }
+
+   va_end(ap);
+
+   return value;
+}
+
 void reg_sequence_start_gather(const struct dc_context *ctx)
 {
/* if reg sequence is supported and enabled, set flag to
diff --git a/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h 
b/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
index 2470405e996b..a402df225a76 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
@@ -498,6 +498,40 @@ uint32_t generic_indirect_reg_update_ex(const struct 
dc_context *ctx,
uint8_t shift1, uint32_t mask1, uint32_t field_value1,
...);
 
+/* indirect register access
+ * underlying implementation determines which index/data pair to be used
+ * in a synchronous way
+ */
+#define IX_REG_SET_N_SYNC(index, n, initial_val, ...)  \
+   generic_indirect_reg_update_ex_sync(CTX, \
+   IND_REG(index), \
+   initial_val, \
+   n, __VA_ARGS__)
+
+#define IX_REG_SET_2_SYNC(index, init_value, f1, v1, f2, v2)   \
+   IX_REG_SET_N_SYNC(index, 2, init_value, \
+   FN(reg, f1), v1,\
+   FN(reg, f2), v2)
+
+#define IX_REG_GET_N_SYNC(index, n, ...) \
+   generic_indirect_reg_get_sync(CTX, \
+   IND_REG(index), \
+   n, __VA_ARGS__)
+
+#define IX_REG_GET_SYNC(index, field, val) \
+   IX_REG_GET_N_SYNC(index, 1, \
+   FN(data_reg_name, field), val)
+
+uint32_t generic_indirect_reg_get_sync(const struct dc_context *ctx,
+   uint32_t index, int n,
+   uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
+   ...);
+
+uint32_t generic_indirect_reg_update_ex_sync(const struct dc_context *ctx,
+   uint32_t index, uint32_t reg_val, int n,
+   uint8_t shift1, uint32_t mask1, uint32_t field_value1,
+   ...);
+
 /* register offload macros
  *
  * instead of MMIO to register directly, in some cases we want
-- 
2.25.1

[PATCH 11/24] drm/amd/display: Add DSC Enable for Synaptics Hub

[Rodrigo Siqueira]

From: Fangzhi Zuo 

DSC sequence for non virtual dpcd synaptics hub

Reviewed-by: Hersen Wu 
Acked-by: Rodrigo Siqueira 
Signed-off-by: Fangzhi Zuo 
---
 .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 48 +++
 .../amd/display/include/ddc_service_types.h   |  3 ++
 2 files changed, 51 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index b760c0b199d5..32fbd3902e93 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -39,6 +39,7 @@
 #include "amdgpu_dm_mst_types.h"
 
 #include "dm_helpers.h"
+#include "ddc_service_types.h"
 
 struct monitor_patch_info {
unsigned int manufacturer_id;
@@ -537,6 +538,7 @@ bool dm_helpers_submit_i2c(
return result;
 }
 
+#if defined(CONFIG_DRM_AMD_DC_DCN)
 static bool execute_synatpics_rc_command(struct drm_dp_aux *aux,
bool is_write_cmd,
unsigned char cmd,
@@ -669,6 +671,43 @@ static void apply_synaptics_fifo_reset_wa(struct 
drm_dp_aux *aux)
DC_LOG_DC("Done apply_synaptics_fifo_reset_wa\n");
 }
 
+static uint8_t write_dsc_enable_synaptics_non_virtual_dpcd_mst(
+   struct drm_dp_aux *aux,
+   const struct dc_stream_state *stream,
+   bool enable)
+{
+   uint8_t ret = 0;
+
+   DC_LOG_DC("Configure DSC to non-virtual dpcd synaptics\n");
+
+   if (enable) {
+   /* When DSC is enabled on previous boot and reboot with the hub,
+* there is a chance that Synaptics hub gets stuck during 
reboot sequence.
+* Applying a workaround to reset Synaptics SDP fifo before 
enabling the first stream
+*/
+   if (!stream->link->link_status.link_active &&
+   memcmp(stream->link->dpcd_caps.branch_dev_name,
+   (int8_t *)SYNAPTICS_DEVICE_ID, 4) == 0)
+   apply_synaptics_fifo_reset_wa(aux);
+
+   ret = drm_dp_dpcd_write(aux, DP_DSC_ENABLE, &enable, 1);
+   DRM_INFO("Send DSC enable to synaptics\n");
+
+   } else {
+   /* Synaptics hub not support virtual dpcd,
+* external monitor occur garbage while disable DSC,
+* Disable DSC only when entire link status turn to false,
+*/
+   if (!stream->link->link_status.link_active) {
+   ret = drm_dp_dpcd_write(aux, DP_DSC_ENABLE, &enable, 1);
+   DRM_INFO("Send DSC disable to synaptics\n");
+   }
+   }
+
+   return ret;
+}
+#endif
+
 bool dm_helpers_dp_write_dsc_enable(
struct dc_context *ctx,
const struct dc_stream_state *stream,
@@ -687,7 +726,16 @@ bool dm_helpers_dp_write_dsc_enable(
if (!aconnector->dsc_aux)
return false;
 
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+   // apply w/a to synaptics
+   if (needs_dsc_aux_workaround(aconnector->dc_link) &&
+   (aconnector->mst_downstream_port_present.byte & 0x7) != 0x3)
+   return write_dsc_enable_synaptics_non_virtual_dpcd_mst(
+   aconnector->dsc_aux, stream, enable_dsc);
+#endif
+
ret = drm_dp_dpcd_write(aconnector->dsc_aux, DP_DSC_ENABLE, 
&enable_dsc, 1);
+   DC_LOG_DC("Send DSC %s to MST RX\n", enable_dsc ? "enable" : 
"disable");
}
 
if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT || stream->signal == 
SIGNAL_TYPE_EDP) {
diff --git a/drivers/gpu/drm/amd/display/include/ddc_service_types.h 
b/drivers/gpu/drm/amd/display/include/ddc_service_types.h
index 57f92bd2814f..fb289a5c873a 100644
--- a/drivers/gpu/drm/amd/display/include/ddc_service_types.h
+++ b/drivers/gpu/drm/amd/display/include/ddc_service_types.h
@@ -123,4 +123,7 @@ struct av_sync_data {
 static const uint8_t DP_SINK_DEVICE_STR_ID_1[] = {7, 1, 8, 7, 3, 0};
 static const uint8_t DP_SINK_DEVICE_STR_ID_2[] = {7, 1, 8, 7, 5, 0};
 
+/*MST Dock*/
+static const uint8_t SYNAPTICS_DEVICE_ID[] = "SYNA";
+
 #endif /* __DAL_DDC_SERVICE_TYPES_H__ */
-- 
2.25.1

[PATCH 16/24] drm/amd/display: [FW Promotion] Release 0.0.101.0

[Rodrigo Siqueira]

From: Anthony Koo 

- Add Scr8 for GPINT messaging between driver and fw

Acked-by: Rodrigo Siqueira 
Signed-off-by: Anthony Koo 
---
 drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 9 ++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h 
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index eb152f5e3ec3..9f609829955d 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -47,10 +47,10 @@
 
 /* Firmware versioning. */
 #ifdef DMUB_EXPOSE_VERSION
-#define DMUB_FW_VERSION_GIT_HASH 0x56a29f36
+#define DMUB_FW_VERSION_GIT_HASH 0x1288a7b7
 #define DMUB_FW_VERSION_MAJOR 0
 #define DMUB_FW_VERSION_MINOR 0
-#define DMUB_FW_VERSION_REVISION 100
+#define DMUB_FW_VERSION_REVISION 101
 #define DMUB_FW_VERSION_TEST 0
 #define DMUB_FW_VERSION_VBIOS 0
 #define DMUB_FW_VERSION_HOTFIX 0
@@ -368,8 +368,9 @@ union dmub_fw_boot_options {
/**< 1 if all root clock gating is enabled and low power memory 
is enabled*/
uint32_t power_optimization: 1;
uint32_t diag_env: 1; /* 1 if diagnostic environment */
+   uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/
 
-   uint32_t reserved : 19; /**< reserved */
+   uint32_t reserved : 18; /**< reserved */
} bits; /**< boot bits */
uint32_t all; /**< 32-bit access to bits */
 };
@@ -645,6 +646,7 @@ enum dmub_cmd_type {
 * Command type used for OUTBOX1 notification enable
 */
DMUB_CMD__OUTBOX1_ENABLE = 71,
+
/**
 * Command type used for all idle optimization commands.
 */
@@ -657,6 +659,7 @@ enum dmub_cmd_type {
 * Command type used for all panel control commands.
 */
DMUB_CMD__PANEL_CNTL = 74,
+
/**
 * Command type used for interfacing with DPIA.
 */
-- 
2.25.1

[PATCH 04/24] drm/amd/display: Change error to warning when hpd remains low for eDP

[Rodrigo Siqueira]

From: Varone 

[WHY?]
SKUs that contain an unused eDP connector will throw an error when no
display is connected.

[HOW?]
Change error to a warning.

Reviewed-by: Martin Leung 
Acked-by: Rodrigo Siqueira 
Signed-off-by: Dillon Varone 
---
 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 9857e7b1b37d..bdde8786ff9b 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -793,7 +793,7 @@ void dce110_edp_wait_for_hpd_ready(
dal_gpio_destroy_irq(&hpd);
 
if (false == edp_hpd_high) {
-   DC_LOG_ERROR(
+   DC_LOG_WARNING(
"%s: wait timed out!\n", __func__);
}
 }
-- 
2.25.1

[PATCH 09/24] drm/amd/display: Add Synaptics Fifo Reset Workaround

[Rodrigo Siqueira]

From: Fangzhi Zuo 

Sequence to reset synaptics SDP fifo before enabling first stream

Reviewed-by: Hersen Wu 
Acked-by: Rodrigo Siqueira 
Signed-off-by: Fangzhi Zuo 
---
 .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 133 ++
 .../display/amdgpu_dm/amdgpu_dm_mst_types.c   |   2 +-
 .../display/amdgpu_dm/amdgpu_dm_mst_types.h   |  10 ++
 3 files changed, 144 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index d757bdd9f0e2..b760c0b199d5 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -536,6 +536,139 @@ bool dm_helpers_submit_i2c(
 
return result;
 }
+
+static bool execute_synatpics_rc_command(struct drm_dp_aux *aux,
+   bool is_write_cmd,
+   unsigned char cmd,
+   unsigned int length,
+   unsigned int offset,
+   unsigned char *data)
+{
+   bool success = false;
+   unsigned char rc_data[16] = {0};
+   unsigned char rc_offset[4] = {0};
+   unsigned char rc_length[2] = {0};
+   unsigned char rc_cmd = 0;
+   unsigned char rc_result = 0xFF;
+   unsigned char i = 0;
+   uint8_t ret = 0;
+
+   if (is_write_cmd) {
+   // write rc data
+   memmove(rc_data, data, length);
+   ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_DATA, rc_data, 
sizeof(rc_data));
+   }
+
+   // write rc offset
+   rc_offset[0] = (unsigned char) offset & 0xFF;
+   rc_offset[1] = (unsigned char) (offset >> 8) & 0xFF;
+   rc_offset[2] = (unsigned char) (offset >> 16) & 0xFF;
+   rc_offset[3] = (unsigned char) (offset >> 24) & 0xFF;
+   ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_OFFSET, rc_offset, 
sizeof(rc_offset));
+
+   // write rc length
+   rc_length[0] = (unsigned char) length & 0xFF;
+   rc_length[1] = (unsigned char) (length >> 8) & 0xFF;
+   ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_LENGTH, rc_length, 
sizeof(rc_length));
+
+   // write rc cmd
+   rc_cmd = cmd | 0x80;
+   ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_COMMAND, &rc_cmd, 
sizeof(rc_cmd));
+
+   if (ret < 0) {
+   DRM_ERROR(" execute_synatpics_rc_command - write cmd ..., 
err = %d\n", ret);
+   return false;
+   }
+
+   // poll until active is 0
+   for (i = 0; i < 10; i++) {
+   drm_dp_dpcd_read(aux, SYNAPTICS_RC_COMMAND, &rc_cmd, 
sizeof(rc_cmd));
+   if (rc_cmd == cmd)
+   // active is 0
+   break;
+   msleep(10);
+   }
+
+   // read rc result
+   drm_dp_dpcd_read(aux, SYNAPTICS_RC_RESULT, &rc_result, 
sizeof(rc_result));
+   success = (rc_result == 0);
+
+   if (success && !is_write_cmd) {
+   // read rc data
+   drm_dp_dpcd_read(aux, SYNAPTICS_RC_DATA, data, length);
+   }
+
+   DC_LOG_DC(" execute_synatpics_rc_command - success = %d\n", 
success);
+
+   return success;
+}
+
+static void apply_synaptics_fifo_reset_wa(struct drm_dp_aux *aux)
+{
+   unsigned char data[16] = {0};
+
+   DC_LOG_DC("Start apply_synaptics_fifo_reset_wa\n");
+
+   // Step 2
+   data[0] = 'P';
+   data[1] = 'R';
+   data[2] = 'I';
+   data[3] = 'U';
+   data[4] = 'S';
+
+   if (!execute_synatpics_rc_command(aux, true, 0x01, 5, 0, data))
+   return;
+
+   // Step 3 and 4
+   if (!execute_synatpics_rc_command(aux, false, 0x31, 4, 0x220998, data))
+   return;
+
+   data[0] &= (~(1 << 1)); // set bit 1 to 0
+   if (!execute_synatpics_rc_command(aux, true, 0x21, 4, 0x220998, data))
+   return;
+
+   if (!execute_synatpics_rc_command(aux, false, 0x31, 4, 0x220D98, data))
+   return;
+
+   data[0] &= (~(1 << 1)); // set bit 1 to 0
+   if (!execute_synatpics_rc_command(aux, true, 0x21, 4, 0x220D98, data))
+   return;
+
+   if (!execute_synatpics_rc_command(aux, false, 0x31, 4, 0x221198, data))
+   return;
+
+   data[0] &= (~(1 << 1)); // set bit 1 to 0
+   if (!execute_synatpics_rc_command(aux, true, 0x21, 4, 0x221198, data))
+   return;
+
+   // Step 3 and 5
+   if (!execute_synatpics_rc_command(aux, false, 0x31, 4, 0x220998, data))
+   return;
+
+   data[0] |= (1 << 1); // set bit 1 to 1
+   if (!execute_synatpics_rc_command(aux, true, 0x21, 4, 0x220998, data))
+   return;
+
+   if (!execute_synatpics_rc_command(aux, false, 0x31, 4, 0x220D98, data))
+   return;
+
+   data[0] |= (1 << 1); // set bit 1 to 1
+   return;
+
+   if (!execute_synatpics_rc_command(aux, false, 0x31, 4, 0x221198, data))
+   return;
+
+   data[0] |= (1 << 1); // set bit 1 to 1
+   if (!execute_sy

[PATCH 10/24] drm/amd/display: Retrieve MST Downstream Port Status

[Rodrigo Siqueira]

From: Fangzhi Zuo 

Determine if DFP present and the type of downstream device
based on dsc_aux

Reviewed-by: Hersen Wu 
Acked-by: Rodrigo Siqueira 
Signed-off-by: Fangzhi Zuo 
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h |  1 +
 .../display/amdgpu_dm/amdgpu_dm_mst_types.c   | 23 +++
 2 files changed, 24 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index b9a69b0cef23..e35977fda5c1 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -604,6 +604,7 @@ struct amdgpu_dm_connector {
 #endif
bool force_yuv420_output;
struct dsc_preferred_settings dsc_settings;
+   union dp_downstream_port_present mst_downstream_port_present;
/* Cached display modes */
struct drm_display_mode freesync_vid_base;
 
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 23cc6a6fe70e..8e97d21bdf5c 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -209,6 +209,25 @@ static bool validate_dsc_caps_on_connector(struct 
amdgpu_dm_connector *aconnecto
 
return true;
 }
+
+bool retrieve_downstream_port_device(struct amdgpu_dm_connector *aconnector)
+{
+   union dp_downstream_port_present ds_port_present;
+
+   if (!aconnector->dsc_aux)
+   return false;
+
+   if (drm_dp_dpcd_read(aconnector->dsc_aux, DP_DOWNSTREAMPORT_PRESENT, 
&ds_port_present, 1) < 0) {
+   DRM_INFO("Failed to read downstream_port_present 0x05 from DFP 
of branch device\n");
+   return false;
+   }
+
+   aconnector->mst_downstream_port_present = ds_port_present;
+   DRM_INFO("Downstream port present %d, type %d\n",
+   ds_port_present.fields.PORT_PRESENT, 
ds_port_present.fields.PORT_TYPE);
+
+   return true;
+}
 #endif
 
 static int dm_dp_mst_get_modes(struct drm_connector *connector)
@@ -289,6 +308,10 @@ static int dm_dp_mst_get_modes(struct drm_connector 
*connector)
if (!validate_dsc_caps_on_connector(aconnector))
memset(&aconnector->dc_sink->dsc_caps,
   0, 
sizeof(aconnector->dc_sink->dsc_caps));
+
+   if (!retrieve_downstream_port_device(aconnector))
+   memset(&aconnector->mst_downstream_port_present,
+   0, 
sizeof(aconnector->mst_downstream_port_present));
 #endif
}
}
-- 
2.25.1

[PATCH 08/24] drm/amd/display: Add Cable ID support for native DP

[Rodrigo Siqueira]

From: "Shen, George" 

[Why/How]
We need to handle cable capabilities for cables that support cable ID.
The cable attributes are intersected with the verified link caps to
determine appropriate max link rate. After determining cable attributes
we update the DP receiver.

Reviewed-by: Wenjing Liu 
Acked-by: Rodrigo Siqueira 
Signed-off-by: George Shen 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c |  5 ++
 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 59 +++
 drivers/gpu/drm/amd/display/dc/dc.h   |  2 +
 drivers/gpu/drm/amd/display/dc/dc_dp_types.h  | 16 +
 drivers/gpu/drm/amd/display/dc/dc_link.h  |  7 +++
 .../gpu/drm/amd/display/dc/inc/dc_link_dp.h   |  3 +
 6 files changed, 92 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index b826ac9bd85d..d0aba8d7b1c3 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1290,6 +1290,8 @@ static bool detect_link_and_local_sink(struct dc_link 
*link,
 *  Clear dongle_max_pix_clk on disconnect to fix this
 */
link->dongle_max_pix_clk = 0;
+
+   dc_link_dp_clear_rx_status(link);
}
 
LINK_INFO("link=%d, dc_sink_in=%p is now %s prev_sink=%p edid 
same=%d\n",
@@ -1969,6 +1971,9 @@ static enum dc_status enable_link_dp(struct dc_state 
*state,
if (link->dpcd_sink_ext_caps.raw != 0)
msleep(post_oui_delay);
 
+   // similarly, mode switch can cause loss of cable ID
+   dpcd_update_cable_id(link);
+
skip_video_pattern = true;
 
if (link_settings.link_rate == LINK_RATE_LOW)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 1730be6c64ed..0033d2a0cfe5 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -2981,6 +2981,20 @@ static enum dc_link_rate get_lttpr_max_link_rate(struct 
dc_link *link)
return lttpr_max_link_rate;
 }
 
+static enum dc_link_rate get_cable_max_link_rate(struct dc_link *link)
+{
+   enum dc_link_rate cable_max_link_rate = LINK_RATE_HIGH3;
+
+   if (link->dpcd_caps.cable_attributes.bits.UHBR10_20_CAPABILITY & 
DP_UHBR20)
+   cable_max_link_rate = LINK_RATE_UHBR20;
+   else if (link->dpcd_caps.cable_attributes.bits.UHBR13_5_CAPABILITY)
+   cable_max_link_rate = LINK_RATE_UHBR13_5;
+   else if (link->dpcd_caps.cable_attributes.bits.UHBR10_20_CAPABILITY & 
DP_UHBR10)
+   cable_max_link_rate = LINK_RATE_UHBR10;
+
+   return cable_max_link_rate;
+}
+
 bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link, struct 
dc_link_settings *max_link_enc_cap)
 {
struct link_encoder *link_enc = NULL;
@@ -3009,8 +3023,10 @@ struct dc_link_settings dp_get_max_link_cap(struct 
dc_link *link)
 {
struct dc_link_settings max_link_cap = {0};
enum dc_link_rate lttpr_max_link_rate;
+   enum dc_link_rate cable_max_link_rate;
struct link_encoder *link_enc = NULL;
 
+
link_enc = link_enc_cfg_get_link_enc(link);
ASSERT(link_enc);
 
@@ -3029,6 +3045,14 @@ struct dc_link_settings dp_get_max_link_cap(struct 
dc_link *link)
max_link_cap.link_spread)
max_link_cap.link_spread =
link->reported_link_cap.link_spread;
+
+   /* Lower link settings based on cable attributes */
+   cable_max_link_rate = get_cable_max_link_rate(link);
+
+   if (!link->dc->debug.ignore_cable_id &&
+   cable_max_link_rate < max_link_cap.link_rate)
+   max_link_cap.link_rate = cable_max_link_rate;
+
/*
 * account for lttpr repeaters cap
 * notes: repeaters do not snoop in the DPRX Capabilities addresses 
(3.6.3).
@@ -5059,6 +5083,13 @@ bool dp_retrieve_lttpr_cap(struct dc_link *link)
return is_lttpr_present;
 }
 
+
+static bool is_usbc_connector(struct dc_link *link)
+{
+   return link->link_enc &&
+   link->link_enc->features.flags.bits.DP_IS_USB_C;
+}
+
 static bool retrieve_link_cap(struct dc_link *link)
 {
/* DP_ADAPTER_CAP - DP_DPCD_REV + 1 == 16 and also 
DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT + 1 == 16,
@@ -5115,6 +5146,9 @@ static bool retrieve_link_cap(struct dc_link *link)
 */
msleep(post_oui_delay);
 
+   /* Read cable ID and update receiver */
+   dpcd_update_cable_id(link);
+
for (i = 0; i < read_dpcd_retry_cnt; i++) {
status = core_link_read_dpcd(
link,
@@ -6292,6 +6326,26 @@ void dpcd_set_source_specific_data(struct dc_link *link)
}
 }
 
+void dpcd_update_cable_id(struct dc_link *link)
+{
+   if (!link->link_enc->features.flags.bits.IS_UHBR10_CAPABLE ||
+   link->dp

[PATCH 07/24] drm/amd/display: Use PSR version selected during set_psr_caps

[Rodrigo Siqueira]

From: Nicholas Kazlauskas 

[Why]
If the DPCD caps specifies a PSR version newer than PSR_VERSION_1 then
we fallback to using PSR_VERSION_1 in amdgpu_dm_set_psr_caps.

This gets overriden with the raw DPCD value in amdgpu_dm_link_setup_psr,
which can result in DMCUB hanging if we pass in an unsupported PSR
version number.

[How]
Fix the hang by using link->psr_settings.psr_version directly during
amdgpu_dm_link_setup_psr.

Reviewed-by: Anthony Koo 
Acked-by: Rodrigo Siqueira 
Signed-off-by: Nicholas Kazlauskas 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c | 6 ++
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
index c510638b4f99..a009fc654ac9 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
@@ -149,10 +149,8 @@ bool amdgpu_dm_link_setup_psr(struct dc_stream_state 
*stream)
 
link = stream->link;
 
-   psr_config.psr_version = link->dpcd_caps.psr_caps.psr_version;
-
-   if (psr_config.psr_version > 0) {
-   psr_config.psr_exit_link_training_required = 0x1;
+   if (link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED) {
+   psr_config.psr_version = link->psr_settings.psr_version;
psr_config.psr_frame_capture_indication_req = 0;
psr_config.psr_rfb_setup_time = 0x37;
psr_config.psr_sdp_transmit_line_num_deadline = 0x20;
-- 
2.25.1

[PATCH 06/24] drm/amd/display: Change return type of dm_helpers_dp_mst_stop_top_mgr

[Rodrigo Siqueira]

From: Ian Chen 

Prepare for future dm can have different implementation depends on the
return value.

Reviewed-by: Wenjing Liu 
Acked-by: Rodrigo Siqueira 
Signed-off-by: Ian Chen 
---
 .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 24 ---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 14 ++-
 drivers/gpu/drm/amd/display/dc/dm_helpers.h   |  2 +-
 3 files changed, 13 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index 03a04b1e37f2..d757bdd9f0e2 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -445,40 +445,24 @@ bool dm_helpers_dp_mst_start_top_mgr(
return (drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true) == 
0);
 }
 
-void dm_helpers_dp_mst_stop_top_mgr(
+bool dm_helpers_dp_mst_stop_top_mgr(
struct dc_context *ctx,
struct dc_link *link)
 {
struct amdgpu_dm_connector *aconnector = link->priv;
-   uint8_t i;
 
if (!aconnector) {
DRM_ERROR("Failed to find connector for link!");
-   return;
+   return false;
}
 
DRM_INFO("DM_MST: stopping TM on aconnector: %p [id: %d]\n",
aconnector, aconnector->base.base.id);
 
-   if (aconnector->mst_mgr.mst_state == true) {
+   if (aconnector->mst_mgr.mst_state == true)
drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, false);
 
-   for (i = 0; i < MAX_SINKS_PER_LINK; i++) {
-   if (link->remote_sinks[i] == NULL)
-   continue;
-
-   if (link->remote_sinks[i]->sink_signal ==
-   SIGNAL_TYPE_DISPLAY_PORT_MST) {
-   dc_link_remove_remote_sink(link, 
link->remote_sinks[i]);
-
-   if (aconnector->dc_sink) {
-   dc_sink_release(aconnector->dc_sink);
-   aconnector->dc_sink = NULL;
-   
aconnector->dc_link->cur_link_settings.lane_count = 0;
-   }
-   }
-   }
-   }
+   return false;
 }
 
 bool dm_helpers_dp_read_dpcd(
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index b94927eaba8d..b826ac9bd85d 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -840,20 +840,22 @@ static bool discover_dp_mst_topology(struct dc_link 
*link, enum dc_detect_reason
return link->type == dc_connection_mst_branch;
 }
 
-static void reset_cur_dp_mst_topology(struct dc_link *link)
+static bool reset_cur_dp_mst_topology(struct dc_link *link)
 {
+   bool result = false;
DC_LOGGER_INIT(link->ctx->logger);
 
LINK_INFO("link=%d, mst branch is now Disconnected\n",
  link->link_index);
 
revert_dpia_mst_dsc_always_on_wa(link);
-   dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
+   result = dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
 
link->mst_stream_alloc_table.stream_count = 0;
memset(link->mst_stream_alloc_table.stream_allocations,
0,

sizeof(link->mst_stream_alloc_table.stream_allocations));
+   return result;
 }
 
 static bool should_prepare_phy_clocks_for_link_verification(const struct dc 
*dc,
@@ -1305,7 +1307,7 @@ static bool detect_link_and_local_sink(struct dc_link 
*link,
 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
 {
bool is_local_sink_detect_success;
-   bool is_remote_sink_detect_required = false;
+   bool is_delegated_to_mst_top_mgr = false;
enum dc_connection_type pre_link_type = link->type;
 
is_local_sink_detect_success = detect_link_and_local_sink(link, reason);
@@ -1316,14 +1318,14 @@ bool dc_link_detect(struct dc_link *link, enum 
dc_detect_reason reason)
if (is_local_sink_detect_success && link->local_sink &&
dc_is_dp_signal(link->local_sink->sink_signal) &&
link->dpcd_caps.is_mst_capable)
-   is_remote_sink_detect_required = discover_dp_mst_topology(link, 
reason);
+   is_delegated_to_mst_top_mgr = discover_dp_mst_topology(link, 
reason);
 
if (is_local_sink_detect_success &&
pre_link_type == dc_connection_mst_branch &&
link->type != dc_connection_mst_branch)
-   reset_cur_dp_mst_topology(link);
+   is_delegated_to_mst_top_mgr = reset_cur_dp_mst_topology(link);
 
-   return is_local_sink_detect_success && !is_remote_sink_detect_required;
+   return is_local_sink_detect_succes

[PATCH 03/24] drm/amd/display: Driver support for MCLK query tool

[Rodrigo Siqueira]

From: Alvin Lee 

Implement handling for escape call to query the MCLK switch support for
the current display config.

Reviewed-by: Jun Lei 
Acked-by: Rodrigo Siqueira 
Signed-off-by: Alvin Lee 
---
 .../drm/amd/display/dc/dml/display_mode_vba.c | 24 +++
 .../drm/amd/display/dc/dml/display_mode_vba.h |  1 +
 2 files changed, 25 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c 
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
index 0fad15020c74..c0740dbdcc2e 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
@@ -47,6 +47,7 @@ static void recalculate_params(
unsigned int num_pipes);
 
 static unsigned int CursorBppEnumToBits(enum cursor_bpp ebpp);
+static void cache_debug_params(struct display_mode_lib *mode_lib);
 
 unsigned int dml_get_voltage_level(
struct display_mode_lib *mode_lib,
@@ -73,6 +74,7 @@ unsigned int dml_get_voltage_level(
PixelClockAdjustmentForProgressiveToInterlaceUnit(mode_lib);
}
mode_lib->funcs.validate(mode_lib);
+   cache_debug_params(mode_lib);
 
return mode_lib->vba.VoltageLevel;
 }
@@ -745,6 +747,28 @@ static void fetch_pipe_params(struct display_mode_lib 
*mode_lib)
mode_lib->vba.HostVMEnable = mode_lib->vba.HostVMEnable && 
!!ip->hostvm_enable;
 }
 
+/**
+ * 

+ * cache_debug_params: Cache any params that needed to be maintained from the 
initial validation
+ * for debug purposes.
+ *
+ * The DML getters can modify some of the VBA params that we are interested in 
(for example when
+ * calculating with dummy p-state latency), so cache any params here that we 
want for debugging
+ *
+ * @param [in] mode_lib: mode_lib input/output of validate call
+ *
+ * @return: void
+ *
+ * 

+ */
+static void cache_debug_params(struct display_mode_lib *mode_lib)
+{
+   int k = 0;
+
+   for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; k++)
+   mode_lib->vba.CachedActiveDRAMClockChangeLatencyMargin[k] = 
mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k];
+}
+
 // in wm mode we pull the parameters needed from the 
display_e2e_pipe_params_st structs
 // rather than working them out as in recalculate_ms
 static void recalculate_params(
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h 
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
index 8fe74a3b39a8..0603b32971a6 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
@@ -195,6 +195,7 @@ struct vba_vars_st {
unsigned int LBLatencyHidingSourceLinesY;
unsigned int LBLatencyHidingSourceLinesC;
double ActiveDRAMClockChangeLatencyMargin[DC__NUM_DPP__MAX];
+   double CachedActiveDRAMClockChangeLatencyMargin[DC__NUM_DPP__MAX]; // 
Cache in dml_get_voltage_level for debug purposes only
double MinActiveDRAMClockChangeMargin;
double InitFillLevel;
double FinalFillMargin;
-- 
2.25.1

[PATCH 05/24] drm/amd/display: Only set PSR version when valid

[Rodrigo Siqueira]

From: Nicholas Kazlauskas 

[Why]
DMCUB will hang if we send a PSR unsupported set version command.

This can occur if we fall-through into the default case in the switch
statement for PSR version.

[How]
Add an unsupported check after the switch statement.

Reviewed-by: Anthony Koo 
Acked-by: Rodrigo Siqueira 
Signed-off-by: Nicholas Kazlauskas 
---
 drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c 
b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
index 87ed48d5530d..8bd265b40847 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
@@ -138,6 +138,10 @@ static bool dmub_psr_set_version(struct dmub_psr *dmub, 
struct dc_stream_state *
cmd.psr_set_version.psr_set_version_data.version = 
PSR_VERSION_UNSUPPORTED;
break;
}
+
+   if (cmd.psr_set_version.psr_set_version_data.version == 
PSR_VERSION_UNSUPPORTED)
+   return false;
+
cmd.psr_set_version.psr_set_version_data.cmd_version = 
DMUB_CMD_PSR_CONTROL_VERSION_1;
cmd.psr_set_version.psr_set_version_data.panel_inst = panel_inst;
cmd.psr_set_version.header.payload_bytes = sizeof(struct 
dmub_cmd_psr_set_version_data);
-- 
2.25.1

[PATCH 02/24] drm/amd/display: do not compare integers of different widths

[Rodrigo Siqueira]

From: Josip Pavic 

[Why & How]
Increase width of some variables to avoid comparing integers of
different widths

Reviewed-by: Anthony Koo 
Acked-by: Rodrigo Siqueira 
Signed-off-by: Josip Pavic 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 2ff4869d190c..b94927eaba8d 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -4743,7 +4743,7 @@ const struct link_resource 
*dc_link_get_cur_link_res(const struct dc_link *link)
 void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map)
 {
struct dc_link *link;
-   uint8_t i;
+   uint32_t i;
uint32_t hpo_dp_recycle_map = 0;
 
*map = 0;
@@ -4784,7 +4784,7 @@ void dc_get_cur_link_res_map(const struct dc *dc, 
uint32_t *map)
 void dc_restore_link_res_map(const struct dc *dc, uint32_t *map)
 {
struct dc_link *link;
-   uint8_t i;
+   uint32_t i;
unsigned int available_hpo_dp_count;
uint32_t hpo_dp_recycle_map = (*map & LINK_RES_HPO_DP_REC_MAP__MASK)
>> LINK_RES_HPO_DP_REC_MAP__SHIFT;
-- 
2.25.1

[PATCH 01/24] drm/amd/display: add protection in link encoder matching logic

[Rodrigo Siqueira]

From: Martin Tsai 

[Why]
Link encoders are created based on its engine ID. The position of a link
encoder in an array could be null since it didn't be allocated.  Current
matching logic didn't consider this situation and could get null
encoder.

[How]
To add null encoder check to make the matching logic can go to next to
get a valid one.

Reviewed-by: Aric Cyr 
Acked-by: Rodrigo Siqueira 
Signed-off-by: Martin Tsai 
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  2 +-
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 11 +---
 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 66 ++-
 .../drm/amd/display/dc/core/dc_link_enc_cfg.c | 23 ++-
 .../drm/amd/display/dc/core/dc_link_hwss.c| 22 ++-
 .../gpu/drm/amd/display/dc/inc/dc_link_dp.h   |  1 -
 .../gpu/drm/amd/display/dc/inc/link_enc_cfg.h |  3 +
 7 files changed, 36 insertions(+), 92 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 87299e62fe12..94b4d7f70e45 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -8366,7 +8366,7 @@ void amdgpu_dm_connector_init_helper(struct 
amdgpu_display_manager *dm,
break;
case DRM_MODE_CONNECTOR_DisplayPort:
aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
-   link->link_enc = dp_get_link_enc(link);
+   link->link_enc = link_enc_cfg_get_link_enc(link);
ASSERT(link->link_enc);
if (link->link_enc)
aconnector->base.ycbcr_420_allowed =
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 507ed14a1eb1..2ff4869d190c 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -4620,16 +4620,7 @@ bool dc_link_is_fec_supported(const struct dc_link *link)
 */
struct link_encoder *link_enc = NULL;
 
-   /* Links supporting dynamically assigned link encoder will be assigned 
next
-* available encoder if one not already assigned.
-*/
-   if (link->is_dig_mapping_flexible &&
-   link->dc->res_pool->funcs->link_encs_assign) {
-   link_enc = 
link_enc_cfg_get_link_enc_used_by_link(link->ctx->dc, link);
-   if (link_enc == NULL)
-   link_enc = 
link_enc_cfg_get_next_avail_link_enc(link->ctx->dc);
-   } else
-   link_enc = link->link_enc;
+   link_enc = link_enc_cfg_get_link_enc(link);
ASSERT(link_enc);
 
return (dc_is_dp_signal(link->connector_signal) && link_enc &&
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 9511c65e0603..1730be6c64ed 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -261,14 +261,7 @@ static enum dc_dp_training_pattern 
decide_eq_training_pattern(struct dc_link *li
struct dpcd_caps *rx_caps = &link->dpcd_caps;
enum dc_dp_training_pattern pattern = DP_TRAINING_PATTERN_SEQUENCE_2;
 
-   /* Access link encoder capability based on whether it is statically
-* or dynamically assigned to a link.
-*/
-   if (link->is_dig_mapping_flexible &&
-   link->dc->res_pool->funcs->link_encs_assign)
-   link_enc = 
link_enc_cfg_get_link_enc_used_by_link(link->ctx->dc, link);
-   else
-   link_enc = link->link_enc;
+   link_enc = link_enc_cfg_get_link_enc(link);
ASSERT(link_enc);
enc_caps = &link_enc->features;
 
@@ -2997,16 +2990,7 @@ bool dc_link_dp_get_max_link_enc_cap(const struct 
dc_link *link, struct dc_link_
return false;
}
 
-   /* Links supporting dynamically assigned link encoder will be assigned 
next
-* available encoder if one not already assigned.
-*/
-   if (link->is_dig_mapping_flexible &&
-   link->dc->res_pool->funcs->link_encs_assign) {
-   link_enc = 
link_enc_cfg_get_link_enc_used_by_link(link->ctx->dc, link);
-   if (link_enc == NULL)
-   link_enc = 
link_enc_cfg_get_next_avail_link_enc(link->ctx->dc);
-   } else
-   link_enc = link->link_enc;
+   link_enc = link_enc_cfg_get_link_enc(link);
ASSERT(link_enc);
 
if (link_enc && link_enc->funcs->get_max_link_cap) {
@@ -3027,16 +3011,7 @@ struct dc_link_settings dp_get_max_link_cap(struct 
dc_link *link)
enum dc_link_rate lttpr_max_link_rate;
struct link_encoder *link_enc = NULL;
 
-   /* Links supporting dynamically assigned link encoder will be assigned 
next
-* available encoder if one not already assigned.
-*/
-   if (link->is_dig_mapping_flexible &&
-   link->dc

[PATCH 00/24] DC Patches Jan 23, 2022

[Rodrigo Siqueira]

This DC patchset brings improvements in multiple areas. In summary, we
have:
 - Z9 improvements
 - Clocks management adjustments
 - Code cleanup
 - Improve DSC and MST code

Thanks
Siqueira

Alvin Lee (1):
  drm/amd/display: Driver support for MCLK query tool

Anthony Koo (1):
  drm/amd/display: [FW Promotion] Release 0.0.101.0

Aric Cyr (2):
  drm/amd/display: 3.2.170
  drm/amd/display: Remove unnecessary function definition

David Galiffi (2):
  drm/amd/display: Fix disabling dccg clocks
  drm/amd/display: Disable physym clock

Eric Yang (2):
  drm/amd/display: fix zstate allow interface to PMFW
  drm/amd/display: add debug option for z9 disable interface

Fangzhi Zuo (3):
  drm/amd/display: Add Synaptics Fifo Reset Workaround
  drm/amd/display: Retrieve MST Downstream Port Status
  drm/amd/display: Add DSC Enable for Synaptics Hub

Ian Chen (1):
  drm/amd/display: Change return type of dm_helpers_dp_mst_stop_top_mgr

Josip Pavic (1):
  drm/amd/display: do not compare integers of different widths

Martin Tsai (1):
  drm/amd/display: add protection in link encoder matching logic

Nicholas Kazlauskas (2):
  drm/amd/display: Only set PSR version when valid
  drm/amd/display: Use PSR version selected during set_psr_caps

Oliver Logush (1):
  drm/amd/display: Basic support with device ID

Reza Amini (1):
  drm/amd/display: Update VSC HDR infoPacket on TF change

Roy Chan (1):
  drm/amd/display: Support synchronized indirect reg access

Shen, George (1):
  drm/amd/display: Add Cable ID support for native DP

Sung Joon Kim (1):
  drm/amd/display: remove PHY repeater count check for LTTPR mode

Varone (1):
  drm/amd/display: Change error to warning when hpd remains low for eDP

Wayne Lin (1):
  drm/amd/display: Reset preferred training settings immediately

Wenjing Liu (1):
  drm/amd/display: allow set dp drive setting when stream is not present

 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |   4 +-
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h |   1 +
 .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c |   2 +-
 .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 205 --
 .../display/amdgpu_dm/amdgpu_dm_mst_types.c   |  25 ++-
 .../display/amdgpu_dm/amdgpu_dm_mst_types.h   |  10 +
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c |   6 +-
 .../amd/display/dc/clk_mgr/dcn31/dcn31_smu.c  |   6 +-
 drivers/gpu/drm/amd/display/dc/core/dc_link.c |  64 +++---
 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 128 +--
 .../drm/amd/display/dc/core/dc_link_enc_cfg.c |  23 +-
 .../drm/amd/display/dc/core/dc_link_hwss.c|  22 +-
 .../gpu/drm/amd/display/dc/core/dc_resource.c |   3 +-
 drivers/gpu/drm/amd/display/dc/dc.h   |   5 +-
 drivers/gpu/drm/amd/display/dc/dc_dp_types.h  |  16 ++
 drivers/gpu/drm/amd/display/dc/dc_helper.c|  60 +
 drivers/gpu/drm/amd/display/dc/dc_link.h  |  10 +-
 drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c |   4 +
 .../display/dc/dce110/dce110_hw_sequencer.c   |   2 +-
 .../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h |  15 +-
 .../drm/amd/display/dc/dcn20/dcn20_resource.c |   2 +-
 .../drm/amd/display/dc/dcn30/dcn30_hwseq.c|   5 -
 .../drm/amd/display/dc/dcn30/dcn30_hwseq.h|   3 -
 .../gpu/drm/amd/display/dc/dcn30/dcn30_init.c |   2 +-
 .../gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c | 106 ++---
 .../gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h |   6 +
 .../drm/amd/display/dc/dcn31/dcn31_resource.c |   1 +
 drivers/gpu/drm/amd/display/dc/dm_helpers.h   |   2 +-
 .../drm/amd/display/dc/dml/display_mode_vba.c |  24 ++
 .../drm/amd/display/dc/dml/display_mode_vba.h |   1 +
 .../gpu/drm/amd/display/dc/inc/dc_link_dp.h   |   4 +-
 .../gpu/drm/amd/display/dc/inc/link_enc_cfg.h |   3 +
 .../gpu/drm/amd/display/dc/inc/reg_helper.h   |  34 +++
 .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h   |   9 +-
 .../gpu/drm/amd/display/include/dal_asic_id.h |   2 +
 .../amd/display/include/ddc_service_types.h   |   3 +
 .../amd/display/modules/inc/mod_info_packet.h |   3 +-
 .../display/modules/info_packet/info_packet.c |  25 ++-
 38 files changed, 641 insertions(+), 205 deletions(-)

-- 
2.25.1

RE: [PATCH 1/2] drm/amdgpu/display: adjust msleep limit in dp_wait_for_training_aux_rd_interval

[Chen, Guchun]

[Public]

Series is: Reviewed-by: Guchun Chen 
guchun.c...@amd.com

Regards,
Guchun

From: Deucher, Alexander 
Sent: Saturday, January 22, 2022 1:00 AM
To: Chen, Guchun ; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/2] drm/amdgpu/display: adjust msleep limit in 
dp_wait_for_training_aux_rd_interval


[Public]

It just changes the limit for when we use msleep vs udelay, not the units.

Alex

From: Chen, Guchun mailto:guchun.c...@amd.com>>
Sent: Thursday, January 20, 2022 8:49 PM
To: Deucher, Alexander 
mailto:alexander.deuc...@amd.com>>; 
amd-gfx@lists.freedesktop.org 
mailto:amd-gfx@lists.freedesktop.org>>
Cc: Deucher, Alexander 
mailto:alexander.deuc...@amd.com>>
Subject: RE: [PATCH 1/2] drm/amdgpu/display: adjust msleep limit in 
dp_wait_for_training_aux_rd_interval

[Public]

If we change if condition, how about the division by "wait_in_micro_secs/1000", 
as the sleep time is less now. Shall we adjust it as well?

Regards,
Guchun

-Original Message-
From: amd-gfx 
mailto:amd-gfx-boun...@lists.freedesktop.org>>
 On Behalf Of Alex Deucher
Sent: Friday, January 21, 2022 2:04 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander 
mailto:alexander.deuc...@amd.com>>
Subject: [PATCH 1/2] drm/amdgpu/display: adjust msleep limit in 
dp_wait_for_training_aux_rd_interval

Some architectures (e.g., ARM) have relatively low udelay limits.
On most architectures, anything longer than 2000us is not recommended.
Change the check to align with other similar checks in DC.

Signed-off-by: Alex Deucher 
mailto:alexander.deuc...@amd.com>>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 1f8831156bc4..aa1c67c3c386 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -202,7 +202,7 @@ void dp_wait_for_training_aux_rd_interval(
 uint32_t wait_in_micro_secs)
 {
 #if defined(CONFIG_DRM_AMD_DC_DCN)
-   if (wait_in_micro_secs > 16000)
+   if (wait_in_micro_secs > 1000)
 msleep(wait_in_micro_secs/1000);
 else
 udelay(wait_in_micro_secs);
--
2.34.1