Re: [PATCH v2] drm/amdgpu: check vm ready by amdgpu_vm->evicting flag

[Qiang Yu]

On Wed, Feb 23, 2022 at 3:47 PM Paul Menzel  wrote:
>
> Dear Qiang,
>
>
> Am 22.02.22 um 03:46 schrieb Qiang Yu:
> > Workstation application ANSA/META v21.1.4 get this error dmesg when
> > running CI test suite provided by ANSA/META:
> > [drm:amdgpu_gem_va_ioctl [amdgpu]] *ERROR* Couldn't update BO_VA (-16)
> >
> > This is caused by:
> > 1. create a 256MB buffer in invisible VRAM
> > 2. CPU map the buffer and access it causes vm_fault and try to move
> > it to visible VRAM
> > 3. force visible VRAM space and traverse all VRAM bos to check if
> > evicting this bo is valuable
> > 4. when checking a VM bo (in invisible VRAM), amdgpu_vm_evictable()
> > will set amdgpu_vm->evicting, but latter due to not in visible
> > VRAM, won't really evict it so not add it to amdgpu_vm->evicted
> > 5. before next CS to clear the amdgpu_vm->evicting, user VM ops
> > ioctl will pass amdgpu_vm_ready() (check amdgpu_vm->evicted)
> > but fail in amdgpu_vm_bo_update_mapping() (check
> > amdgpu_vm->evicting) and get this error log
> >
> > This error won't affect functionality as next CS will finish the
> > waiting VM ops. But we'd better clear the error log by checking
> > the amdgpu_vm->evicting flag in amdgpu_vm_ready() to stop calling
> > amdgpu_vm_bo_update_mapping() latter.
>
> later
> > Another reason is amdgpu_vm->evicted list holds all BOs (both
> > user buffer and page table), but only page table BOs' eviction
> > prevent VM ops. amdgpu_vm->evicting flag is set only for page
> > table BOs, so we should use evicting flag instead of evicted list
> > in amdgpu_vm_ready().
> >
> > The side effect of This change is: previously blocked VM op (user
>
> this
>
> > buffer in "evicted" list but no page table in it) gets done
> > immediately.
> >
> > v2: update commit comments.
> >
> > Reviewed-by: Christian König 
> > Signed-off-by: Qiang Yu 
> > ---
> >   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 9 +++--
> >   1 file changed, 7 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> > index 37acd8911168..2cd9f1a2e5fa 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> > @@ -770,11 +770,16 @@ int amdgpu_vm_validate_pt_bos(struct amdgpu_device 
> > *adev, struct amdgpu_vm *vm,
> >* Check if all VM PDs/PTs are ready for updates
> >*
> >* Returns:
> > - * True if eviction list is empty.
> > + * True if VM is not evicting.
> >*/
> >   bool amdgpu_vm_ready(struct amdgpu_vm *vm)
> >   {
> > - return list_empty(&vm->evicted);
> > + bool ret;
> > +
> > + amdgpu_vm_eviction_lock(vm);
> > + ret = !vm->evicting;
> > + amdgpu_vm_eviction_unlock(vm);
> > + return ret;
> >   }
> >
> >   /**
>
> Acked-by: Paul Menzel 
>
Thanks, will submit with the typo fixed.

Regards,
Qiang

>
> Kind regards,
>
> Paul

Re: [PATCH v2] drm/amdgpu: check vm ready by amdgpu_vm->evicting flag

[Paul Menzel]

Dear Qiang,


Am 22.02.22 um 03:46 schrieb Qiang Yu:

Workstation application ANSA/META v21.1.4 get this error dmesg when
running CI test suite provided by ANSA/META:
[drm:amdgpu_gem_va_ioctl [amdgpu]] *ERROR* Couldn't update BO_VA (-16)

This is caused by:
1. create a 256MB buffer in invisible VRAM
2. CPU map the buffer and access it causes vm_fault and try to move
it to visible VRAM
3. force visible VRAM space and traverse all VRAM bos to check if
evicting this bo is valuable
4. when checking a VM bo (in invisible VRAM), amdgpu_vm_evictable()
will set amdgpu_vm->evicting, but latter due to not in visible
VRAM, won't really evict it so not add it to amdgpu_vm->evicted
5. before next CS to clear the amdgpu_vm->evicting, user VM ops
ioctl will pass amdgpu_vm_ready() (check amdgpu_vm->evicted)
but fail in amdgpu_vm_bo_update_mapping() (check
amdgpu_vm->evicting) and get this error log

This error won't affect functionality as next CS will finish the
waiting VM ops. But we'd better clear the error log by checking
the amdgpu_vm->evicting flag in amdgpu_vm_ready() to stop calling
amdgpu_vm_bo_update_mapping() latter.


later

Another reason is amdgpu_vm->evicted list holds all BOs (both
user buffer and page table), but only page table BOs' eviction
prevent VM ops. amdgpu_vm->evicting flag is set only for page
table BOs, so we should use evicting flag instead of evicted list
in amdgpu_vm_ready().

The side effect of This change is: previously blocked VM op (user


this


buffer in "evicted" list but no page table in it) gets done
immediately.

v2: update commit comments.

Reviewed-by: Christian König 
Signed-off-by: Qiang Yu 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 9 +++--
  1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 37acd8911168..2cd9f1a2e5fa 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -770,11 +770,16 @@ int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, 
struct amdgpu_vm *vm,
   * Check if all VM PDs/PTs are ready for updates
   *
   * Returns:
- * True if eviction list is empty.
+ * True if VM is not evicting.
   */
  bool amdgpu_vm_ready(struct amdgpu_vm *vm)
  {
-   return list_empty(&vm->evicted);
+   bool ret;
+
+   amdgpu_vm_eviction_lock(vm);
+   ret = !vm->evicting;
+   amdgpu_vm_eviction_unlock(vm);
+   return ret;
  }
  
  /**


Acked-by: Paul Menzel 


Kind regards,

Paul

Re: [PATCH] drm/sched: Add device pointer to drm_gpu_scheduler

[Christian König]

Well that's bad. This should not be pushed to amd-staging-drm-next at all.

This patch is touching multiple drivers and therefore needs to go 
upstream through drm-misc-next.


Alex can you drop that one before you send out a pull request? I'm going 
to cherry-pick it over to drm-misc-next.


Thanks,
Christian.

Am 23.02.22 um 08:15 schrieb Gu, JiaWei (Will):

[AMD Official Use Only]

Hi Christian,

I noticed that and it has been fixed with the latest patch.
And I pushed it to amd-staging-drm-next already.

Best regards,
Jiawei

-Original Message-
From: Koenig, Christian 
Sent: Wednesday, February 23, 2022 3:12 PM
To: kernel test robot ; Gu, JiaWei (Will) ; 
dri-de...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org; Grodzovsky, Andrey 
; Liu, Monk ; Deng, Emily ; 
Chen, Horace 
Cc: kbuild-...@lists.01.org
Subject: Re: [PATCH] drm/sched: Add device pointer to drm_gpu_scheduler

Hi Jiawei,


can you take a look at this? The kernel build robots screaming that this breaks 
the V3D build. Probably just a typo or missing include.

I would rather like to push this sooner than later.

Thanks,
Christian.

Am 21.02.22 um 16:51 schrieb kernel test robot:

Hi Jiawei,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on drm/drm-next] [also build test ERROR on
drm-intel/for-linux-next drm-exynos/exynos-drm-next
tegra-drm/drm/tegra/for-next v5.17-rc5 next-20220217] [cannot apply to
drm-tip/drm-tip] [If your patch is applied to the wrong git tree, kindly drop 
us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit-
scm.com%2Fdocs%2Fgit-format-patch&data=04%7C01%7CChristian.Koenig%
40amd.com%7C33c94d7ecffe465c671d08d9f5522651%7C3dd8961fe4884e608e11a82
d994e183d%7C0%7C0%7C637810555454343325%7CUnknown%7CTWFpbGZsb3d8eyJWIjo
iMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&
;sdata=8Kj1h9%2BCR%2B8nDeUXW%2B%2FQOFbiavK5oHons0mRPyHhq%2F0%3D&re
served=0]

url:
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com%2F0day-ci%2Flinux%2Fcommits%2FJiawei-Gu%2Fdrm-sched-Add-device-pointer-to-drm_gpu_scheduler%2F20220221-175818&data=04%7C01%7CChristian.Koenig%40amd.com%7C33c94d7ecffe465c671d08d9f5522651%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637810555454343325%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata=KMrQ%2FsAoUV768eWdTF1FdmXo44kDPjWKnwoi4rvVnqs%3D&reserved=0
base:   git://anongit.freedesktop.org/drm/drm drm-next
config: ia64-allmodconfig
(https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fdow
nload.01.org%2F0day-ci%2Farchive%2F20220221%2F202202212330.nxcvFWEe-lk
p%40intel.com%2Fconfig&data=04%7C01%7CChristian.Koenig%40amd.com%7
C33c94d7ecffe465c671d08d9f5522651%7C3dd8961fe4884e608e11a82d994e183d%7
C0%7C0%7C637810555454343325%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMD
AiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata=tLVb
OkxAyxSD%2BVUHUmS6BT5RfOzO4q3sotVZ2YHGV9o%3D&reserved=0)
compiler: ia64-linux-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
  wget 
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fraw.githubusercontent.com%2Fintel%2Flkp-tests%2Fmaster%2Fsbin%2Fmake.cross&data=04%7C01%7CChristian.Koenig%40amd.com%7C33c94d7ecffe465c671d08d9f5522651%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637810555454343325%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata=8QLSr7JTjK87bBGwgOLxU6AU4bCeHoWX2zyx7SGYL7M%3D&reserved=0
 -O ~/bin/make.cross
  chmod +x ~/bin/make.cross
  # 
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com%2F0day-ci%2Flinux%2Fcommit%2F9fdafca855faca0a3b8f213f024985c4112fa0bb&data=04%7C01%7CChristian.Koenig%40amd.com%7C33c94d7ecffe465c671d08d9f5522651%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637810555454343325%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata=W9HKTScDzhoA1DClCigH2QQUgcIzLStBS%2Bx9ieYPbK4%3D&reserved=0
  git remote add linux-review 
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com%2F0day-ci%2Flinux&data=04%7C01%7CChristian.Koenig%40amd.com%7C33c94d7ecffe465c671d08d9f5522651%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637810555454343325%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata=FNJyugHVXenGmYqwgoK9kzKKjC3WGMia%2BNUduLNb0Pc%3D&reserved=0
  git fetch --no-tags linux-review 
Jiawei-Gu/drm-sched-Add-device-pointer-to-drm_gpu_scheduler/20220221-175818
  git checkout 9fdafca855faca0a3b8f213f024985c4112fa0bb
  # save the config file to linux build tree
  mkdir build_dir
  COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0
make.cross O=build_dir ARCH=ia64 SHELL=/bin/bash drivers/gpu/drm/msm/
drivers/gpu/drm/v3d/

If you fix the 

Re: [PATCH v13 1/2] drm/amdgpu: add debugfs for reset registers list

[Christian König]

Am 23.02.22 um 08:13 schrieb Somalapuram Amaranath:

List of register populated for dump collection during the GPU reset.

Signed-off-by: Somalapuram Amaranath 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu.h |  4 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 82 +
  2 files changed, 86 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index b85b67a88a3d..6e35f2c4c869 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1097,6 +1097,10 @@ struct amdgpu_device {
  
  	struct amdgpu_reset_control *reset_cntl;

uint32_t
ip_versions[HW_ID_MAX][HWIP_MAX_INSTANCE];
+
+   /* reset dump register */
+   uint32_t*reset_dump_reg_list;
+   int num_regs;
  };
  
  static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index 164d6a9e9fbb..b91f21cec269 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -1609,6 +1609,86 @@ DEFINE_DEBUGFS_ATTRIBUTE(fops_ib_preempt, NULL,
  DEFINE_DEBUGFS_ATTRIBUTE(fops_sclk_set, NULL,
amdgpu_debugfs_sclk_set, "%llu\n");
  
+static ssize_t amdgpu_reset_dump_register_list_read(struct file *f,

+   char __user *buf, size_t size, loff_t *pos)
+{
+   struct amdgpu_device *adev = (struct amdgpu_device 
*)file_inode(f)->i_private;
+   char reg_offset[12];
+   int i, ret, len = 0;
+
+   if (*pos)
+   return 0;
+
+   memset(reg_offset, 0, 12);
+   ret = down_read_killable(&adev->reset_sem);
+   if (ret)
+   return ret;
+
+   for (i = 0; i < adev->num_regs; i++) {
+   sprintf(reg_offset, "0x%x\n", adev->reset_dump_reg_list[i]);
+   up_read(&adev->reset_sem);
+   if (copy_to_user(buf + len, reg_offset, strlen(reg_offset)))
+   return -EFAULT;
+
+   len += strlen(reg_offset);
+   ret = down_read_killable(&adev->reset_sem);
+   if (ret)
+   return ret;
+   }
+
+   up_read(&adev->reset_sem);
+   *pos += len;
+
+   return len;
+}
+
+static ssize_t amdgpu_reset_dump_register_list_write(struct file *f,
+   const char __user *buf, size_t size, loff_t *pos)
+{
+   struct amdgpu_device *adev = (struct amdgpu_device 
*)file_inode(f)->i_private;
+   char reg_offset[11];
+   uint32_t *tmp;
+   int ret, i = 0, len = 0;
+
+   do {
+   memset(reg_offset, 0, 11);
+   if (copy_from_user(reg_offset, buf + len,
+   min(10, ((int)size-len {
+   ret = -EFAULT;
+   goto error_free;
+   }
+
+   tmp = krealloc_array(tmp, i + 1, sizeof(uint32_t), GFP_KERNEL);
+   if (sscanf(reg_offset, "%X %n", &tmp[i], &ret) != 1) {
+   return -EINVAL;
+   goto error_free;


So close :(

The "return -EINVAL;" is erroneous here. That should probably be a "ret 
= -EINVAL;".


With that fixed the patch is Reviewed-by: Christian König 
.


Regards,
Christian.


+   }
+
+   len += ret;
+   i++;
+   } while (len < size);
+
+   ret = down_write_killable(&adev->reset_sem);
+   if (ret)
+   goto error_free;
+
+   swap(adev->reset_dump_reg_list, tmp);
+   adev->num_regs = i;
+   up_write(&adev->reset_sem);
+   ret = size;
+
+error_free:
+   kfree(tmp);
+   return ret;
+}
+
+static const struct file_operations amdgpu_reset_dump_register_list = {
+   .owner = THIS_MODULE,
+   .read = amdgpu_reset_dump_register_list_read,
+   .write = amdgpu_reset_dump_register_list_write,
+   .llseek = default_llseek
+};
+
  int amdgpu_debugfs_init(struct amdgpu_device *adev)
  {
struct dentry *root = adev_to_drm(adev)->primary->debugfs_root;
@@ -1672,6 +1752,8 @@ int amdgpu_debugfs_init(struct amdgpu_device *adev)
&amdgpu_debugfs_test_ib_fops);
debugfs_create_file("amdgpu_vm_info", 0444, root, adev,
&amdgpu_debugfs_vm_info_fops);
+   debugfs_create_file("amdgpu_reset_dump_register_list", 0644, root, adev,
+   &amdgpu_reset_dump_register_list);
  
  	adev->debugfs_vbios_blob.data = adev->bios;

adev->debugfs_vbios_blob.size = adev->bios_size;

RE: [PATCH] drm/sched: Add device pointer to drm_gpu_scheduler

[Gu, JiaWei (Will)]

[AMD Official Use Only]

Hi Christian,

I noticed that and it has been fixed with the latest patch.
And I pushed it to amd-staging-drm-next already.

Best regards,
Jiawei

-Original Message-
From: Koenig, Christian  
Sent: Wednesday, February 23, 2022 3:12 PM
To: kernel test robot ; Gu, JiaWei (Will) ; 
dri-de...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org; Grodzovsky, 
Andrey ; Liu, Monk ; Deng, Emily 
; Chen, Horace 
Cc: kbuild-...@lists.01.org
Subject: Re: [PATCH] drm/sched: Add device pointer to drm_gpu_scheduler

Hi Jiawei,


can you take a look at this? The kernel build robots screaming that this breaks 
the V3D build. Probably just a typo or missing include.

I would rather like to push this sooner than later.

Thanks,
Christian.

Am 21.02.22 um 16:51 schrieb kernel test robot:
> Hi Jiawei,
>
> Thank you for the patch! Yet something to improve:
>
> [auto build test ERROR on drm/drm-next] [also build test ERROR on 
> drm-intel/for-linux-next drm-exynos/exynos-drm-next 
> tegra-drm/drm/tegra/for-next v5.17-rc5 next-20220217] [cannot apply to 
> drm-tip/drm-tip] [If your patch is applied to the wrong git tree, kindly drop 
> us a note.
> And when submitting patch, we suggest to use '--base' as documented in 
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit-
> scm.com%2Fdocs%2Fgit-format-patch&data=04%7C01%7CChristian.Koenig%
> 40amd.com%7C33c94d7ecffe465c671d08d9f5522651%7C3dd8961fe4884e608e11a82
> d994e183d%7C0%7C0%7C637810555454343325%7CUnknown%7CTWFpbGZsb3d8eyJWIjo
> iMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&
> ;sdata=8Kj1h9%2BCR%2B8nDeUXW%2B%2FQOFbiavK5oHons0mRPyHhq%2F0%3D&re
> served=0]
>
> url:
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com%2F0day-ci%2Flinux%2Fcommits%2FJiawei-Gu%2Fdrm-sched-Add-device-pointer-to-drm_gpu_scheduler%2F20220221-175818&data=04%7C01%7CChristian.Koenig%40amd.com%7C33c94d7ecffe465c671d08d9f5522651%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637810555454343325%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata=KMrQ%2FsAoUV768eWdTF1FdmXo44kDPjWKnwoi4rvVnqs%3D&reserved=0
> base:   git://anongit.freedesktop.org/drm/drm drm-next
> config: ia64-allmodconfig 
> (https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fdow
> nload.01.org%2F0day-ci%2Farchive%2F20220221%2F202202212330.nxcvFWEe-lk
> p%40intel.com%2Fconfig&data=04%7C01%7CChristian.Koenig%40amd.com%7
> C33c94d7ecffe465c671d08d9f5522651%7C3dd8961fe4884e608e11a82d994e183d%7
> C0%7C0%7C637810555454343325%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMD
> AiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata=tLVb
> OkxAyxSD%2BVUHUmS6BT5RfOzO4q3sotVZ2YHGV9o%3D&reserved=0)
> compiler: ia64-linux-gcc (GCC) 11.2.0
> reproduce (this is a W=1 build):
>  wget 
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fraw.githubusercontent.com%2Fintel%2Flkp-tests%2Fmaster%2Fsbin%2Fmake.cross&data=04%7C01%7CChristian.Koenig%40amd.com%7C33c94d7ecffe465c671d08d9f5522651%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637810555454343325%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata=8QLSr7JTjK87bBGwgOLxU6AU4bCeHoWX2zyx7SGYL7M%3D&reserved=0
>  -O ~/bin/make.cross
>  chmod +x ~/bin/make.cross
>  # 
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com%2F0day-ci%2Flinux%2Fcommit%2F9fdafca855faca0a3b8f213f024985c4112fa0bb&data=04%7C01%7CChristian.Koenig%40amd.com%7C33c94d7ecffe465c671d08d9f5522651%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637810555454343325%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata=W9HKTScDzhoA1DClCigH2QQUgcIzLStBS%2Bx9ieYPbK4%3D&reserved=0
>  git remote add linux-review 
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com%2F0day-ci%2Flinux&data=04%7C01%7CChristian.Koenig%40amd.com%7C33c94d7ecffe465c671d08d9f5522651%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637810555454343325%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata=FNJyugHVXenGmYqwgoK9kzKKjC3WGMia%2BNUduLNb0Pc%3D&reserved=0
>  git fetch --no-tags linux-review 
> Jiawei-Gu/drm-sched-Add-device-pointer-to-drm_gpu_scheduler/20220221-175818
>  git checkout 9fdafca855faca0a3b8f213f024985c4112fa0bb
>  # save the config file to linux build tree
>  mkdir build_dir
>  COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 
> make.cross O=build_dir ARCH=ia64 SHELL=/bin/bash drivers/gpu/drm/msm/ 
> drivers/gpu/drm/v3d/
>
> If you fix the issue, kindly add following tag as appropriate
> Reported-by: kernel test robot 
>
> All errors (new ones prefixed by >>):
>
> drivers/gpu/drm/msm/msm_ringbuffer.c: In function 'msm_ringbuffer_new':
>>> drivers/gpu/drm/msm/msm_ringbuffer.c:90:15: error: too few argume

[PATCH v13 2/2] drm/amdgpu: add reset register dump trace on GPU

[Somalapuram Amaranath]

Dump the list of register values to trace event on GPU reset.

Signed-off-by: Somalapuram Amaranath 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 17 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h  | 16 
 2 files changed, 33 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 1e651b959141..7c48fd716adb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -4534,6 +4534,22 @@ int amdgpu_device_pre_asic_reset(struct amdgpu_device 
*adev,
return r;
 }
 
+static int amdgpu_reset_reg_dumps(struct amdgpu_device *adev)
+{
+   uint32_t reg_value;
+   int i;
+
+   lockdep_assert_held(&adev->reset_sem);
+   dump_stack();
+
+   for (i = 0; i < adev->num_regs; i++) {
+   reg_value = RREG32(adev->reset_dump_reg_list[i]);
+   trace_amdgpu_reset_reg_dumps(adev->reset_dump_reg_list[i], 
reg_value);
+   }
+
+   return 0;
+}
+
 int amdgpu_do_asic_reset(struct list_head *device_list_handle,
 struct amdgpu_reset_context *reset_context)
 {
@@ -4544,6 +4560,7 @@ int amdgpu_do_asic_reset(struct list_head 
*device_list_handle,
/* Try reset handler method first */
tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,
reset_list);
+   amdgpu_reset_reg_dumps(tmp_adev);
r = amdgpu_reset_perform_reset(tmp_adev, reset_context);
/* If reset handler not implemented, continue; otherwise return */
if (r == -ENOSYS)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
index d855cb53c7e0..b9637925e85c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
@@ -537,6 +537,22 @@ TRACE_EVENT(amdgpu_ib_pipe_sync,
  __entry->seqno)
 );
 
+TRACE_EVENT(amdgpu_reset_reg_dumps,
+   TP_PROTO(uint32_t address, uint32_t value),
+   TP_ARGS(address, value),
+   TP_STRUCT__entry(
+__field(uint32_t, address)
+__field(uint32_t, value)
+),
+   TP_fast_assign(
+  __entry->address = address;
+  __entry->value = value;
+  ),
+   TP_printk("amdgpu register dump 0x%x: 0x%x",
+ __entry->address,
+ __entry->value)
+);
+
 #undef AMDGPU_JOB_GET_TIMELINE_NAME
 #endif
 
-- 
2.25.1

[PATCH v13 1/2] drm/amdgpu: add debugfs for reset registers list

[Somalapuram Amaranath]

List of register populated for dump collection during the GPU reset.

Signed-off-by: Somalapuram Amaranath 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h |  4 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 82 +
 2 files changed, 86 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index b85b67a88a3d..6e35f2c4c869 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1097,6 +1097,10 @@ struct amdgpu_device {
 
struct amdgpu_reset_control *reset_cntl;
uint32_t
ip_versions[HW_ID_MAX][HWIP_MAX_INSTANCE];
+
+   /* reset dump register */
+   uint32_t*reset_dump_reg_list;
+   int num_regs;
 };
 
 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index 164d6a9e9fbb..b91f21cec269 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -1609,6 +1609,86 @@ DEFINE_DEBUGFS_ATTRIBUTE(fops_ib_preempt, NULL,
 DEFINE_DEBUGFS_ATTRIBUTE(fops_sclk_set, NULL,
amdgpu_debugfs_sclk_set, "%llu\n");
 
+static ssize_t amdgpu_reset_dump_register_list_read(struct file *f,
+   char __user *buf, size_t size, loff_t *pos)
+{
+   struct amdgpu_device *adev = (struct amdgpu_device 
*)file_inode(f)->i_private;
+   char reg_offset[12];
+   int i, ret, len = 0;
+
+   if (*pos)
+   return 0;
+
+   memset(reg_offset, 0, 12);
+   ret = down_read_killable(&adev->reset_sem);
+   if (ret)
+   return ret;
+
+   for (i = 0; i < adev->num_regs; i++) {
+   sprintf(reg_offset, "0x%x\n", adev->reset_dump_reg_list[i]);
+   up_read(&adev->reset_sem);
+   if (copy_to_user(buf + len, reg_offset, strlen(reg_offset)))
+   return -EFAULT;
+
+   len += strlen(reg_offset);
+   ret = down_read_killable(&adev->reset_sem);
+   if (ret)
+   return ret;
+   }
+
+   up_read(&adev->reset_sem);
+   *pos += len;
+
+   return len;
+}
+
+static ssize_t amdgpu_reset_dump_register_list_write(struct file *f,
+   const char __user *buf, size_t size, loff_t *pos)
+{
+   struct amdgpu_device *adev = (struct amdgpu_device 
*)file_inode(f)->i_private;
+   char reg_offset[11];
+   uint32_t *tmp;
+   int ret, i = 0, len = 0;
+
+   do {
+   memset(reg_offset, 0, 11);
+   if (copy_from_user(reg_offset, buf + len,
+   min(10, ((int)size-len {
+   ret = -EFAULT;
+   goto error_free;
+   }
+
+   tmp = krealloc_array(tmp, i + 1, sizeof(uint32_t), GFP_KERNEL);
+   if (sscanf(reg_offset, "%X %n", &tmp[i], &ret) != 1) {
+   return -EINVAL;
+   goto error_free;
+   }
+
+   len += ret;
+   i++;
+   } while (len < size);
+
+   ret = down_write_killable(&adev->reset_sem);
+   if (ret)
+   goto error_free;
+
+   swap(adev->reset_dump_reg_list, tmp);
+   adev->num_regs = i;
+   up_write(&adev->reset_sem);
+   ret = size;
+
+error_free:
+   kfree(tmp);
+   return ret;
+}
+
+static const struct file_operations amdgpu_reset_dump_register_list = {
+   .owner = THIS_MODULE,
+   .read = amdgpu_reset_dump_register_list_read,
+   .write = amdgpu_reset_dump_register_list_write,
+   .llseek = default_llseek
+};
+
 int amdgpu_debugfs_init(struct amdgpu_device *adev)
 {
struct dentry *root = adev_to_drm(adev)->primary->debugfs_root;
@@ -1672,6 +1752,8 @@ int amdgpu_debugfs_init(struct amdgpu_device *adev)
&amdgpu_debugfs_test_ib_fops);
debugfs_create_file("amdgpu_vm_info", 0444, root, adev,
&amdgpu_debugfs_vm_info_fops);
+   debugfs_create_file("amdgpu_reset_dump_register_list", 0644, root, adev,
+   &amdgpu_reset_dump_register_list);
 
adev->debugfs_vbios_blob.data = adev->bios;
adev->debugfs_vbios_blob.size = adev->bios_size;
-- 
2.25.1

Re: [PATCH] drm/sched: Add device pointer to drm_gpu_scheduler

[Christian König]

Hi Jiawei,


can you take a look at this? The kernel build robots screaming that this 
breaks the V3D build. Probably just a typo or missing include.


I would rather like to push this sooner than later.

Thanks,
Christian.

Am 21.02.22 um 16:51 schrieb kernel test robot:

Hi Jiawei,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on drm/drm-next]
[also build test ERROR on drm-intel/for-linux-next drm-exynos/exynos-drm-next 
tegra-drm/drm/tegra/for-next v5.17-rc5 next-20220217]
[cannot apply to drm-tip/drm-tip]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit-scm.com%2Fdocs%2Fgit-format-patch&data=04%7C01%7CChristian.Koenig%40amd.com%7C33c94d7ecffe465c671d08d9f5522651%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637810555454343325%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata=8Kj1h9%2BCR%2B8nDeUXW%2B%2FQOFbiavK5oHons0mRPyHhq%2F0%3D&reserved=0]

url:
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com%2F0day-ci%2Flinux%2Fcommits%2FJiawei-Gu%2Fdrm-sched-Add-device-pointer-to-drm_gpu_scheduler%2F20220221-175818&data=04%7C01%7CChristian.Koenig%40amd.com%7C33c94d7ecffe465c671d08d9f5522651%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637810555454343325%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata=KMrQ%2FsAoUV768eWdTF1FdmXo44kDPjWKnwoi4rvVnqs%3D&reserved=0
base:   git://anongit.freedesktop.org/drm/drm drm-next
config: ia64-allmodconfig 
(https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fdownload.01.org%2F0day-ci%2Farchive%2F20220221%2F202202212330.nxcvFWEe-lkp%40intel.com%2Fconfig&data=04%7C01%7CChristian.Koenig%40amd.com%7C33c94d7ecffe465c671d08d9f5522651%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637810555454343325%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata=tLVbOkxAyxSD%2BVUHUmS6BT5RfOzO4q3sotVZ2YHGV9o%3D&reserved=0)
compiler: ia64-linux-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
 wget 
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fraw.githubusercontent.com%2Fintel%2Flkp-tests%2Fmaster%2Fsbin%2Fmake.cross&data=04%7C01%7CChristian.Koenig%40amd.com%7C33c94d7ecffe465c671d08d9f5522651%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637810555454343325%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata=8QLSr7JTjK87bBGwgOLxU6AU4bCeHoWX2zyx7SGYL7M%3D&reserved=0
 -O ~/bin/make.cross
 chmod +x ~/bin/make.cross
 # 
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com%2F0day-ci%2Flinux%2Fcommit%2F9fdafca855faca0a3b8f213f024985c4112fa0bb&data=04%7C01%7CChristian.Koenig%40amd.com%7C33c94d7ecffe465c671d08d9f5522651%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637810555454343325%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata=W9HKTScDzhoA1DClCigH2QQUgcIzLStBS%2Bx9ieYPbK4%3D&reserved=0
 git remote add linux-review 
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com%2F0day-ci%2Flinux&data=04%7C01%7CChristian.Koenig%40amd.com%7C33c94d7ecffe465c671d08d9f5522651%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637810555454343325%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata=FNJyugHVXenGmYqwgoK9kzKKjC3WGMia%2BNUduLNb0Pc%3D&reserved=0
 git fetch --no-tags linux-review 
Jiawei-Gu/drm-sched-Add-device-pointer-to-drm_gpu_scheduler/20220221-175818
 git checkout 9fdafca855faca0a3b8f213f024985c4112fa0bb
 # save the config file to linux build tree
 mkdir build_dir
 COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross 
O=build_dir ARCH=ia64 SHELL=/bin/bash drivers/gpu/drm/msm/ drivers/gpu/drm/v3d/

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot 

All errors (new ones prefixed by >>):

drivers/gpu/drm/msm/msm_ringbuffer.c: In function 'msm_ringbuffer_new':

drivers/gpu/drm/msm/msm_ringbuffer.c:90:15: error: too few arguments to 
function 'drm_sched_init'

   90 | ret = drm_sched_init(&ring->sched, &msm_sched_ops,
  |   ^~
In file included from drivers/gpu/drm/msm/msm_ringbuffer.h:10,
 from drivers/gpu/drm/msm/msm_ringbuffer.c:7:
include/drm/gpu_scheduler.h:463:5: note: declared here
  463 | int drm_sched_init(struct drm_gpu_scheduler *sched,
  | ^~
--
In file included from drivers/gpu/drm/v3d/v3d_sched.c:23:
drivers/gpu/drm/v3d/v3d_sched.c: In function 'v3d_sched_init':

drivers/gpu/drm/v3d/v3d_drv.h:158:26: error: implicit declaration of function 
'to_platform_de

[PATCH v2] drm/amdgpu: config HDP_MISC_CNTL.READ_BUFFER_WATERMARK to fix applications running across multiple GPU config hang.

[Xiaogang . Chen]

From: Xiaogang Chen 

Signed-off-by: Xiaogang Chen 
---
 drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c  | 3 +++
 drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_sh_mask.h | 2 ++
 2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
index d7811e0327cb..02400d97a95c 100644
--- a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
@@ -146,6 +146,9 @@ static void hdp_v4_0_init_registers(struct amdgpu_device 
*adev)
 
WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);
 
+   if (adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 4, 0))
+   WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, READ_BUFFER_WATERMARK, 2);
+
WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 
8));
WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE_HI, (adev->gmc.vram_start >> 
40));
 }
diff --git a/drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_sh_mask.h 
b/drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_sh_mask.h
index 25e28691d62d..65c91b0102e4 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_sh_mask.h
@@ -104,6 +104,7 @@
 #define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024__SHIFT 0x5
 #define HDP_MISC_CNTL__MULTIPLE_READS__SHIFT   0x6
 #define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES__SHIFT0xb
+#define HDP_MISC_CNTL__READ_BUFFER_WATERMARK__SHIFT 0xe
 #define HDP_MISC_CNTL__FED_ENABLE__SHIFT   0x15
 #define HDP_MISC_CNTL__SYSHUB_CHANNEL_PRIORITY__SHIFT  0x17
 #define HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE__SHIFT 0x18
@@ -118,6 +119,7 @@
 #define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024_MASK   0x0020L
 #define HDP_MISC_CNTL__MULTIPLE_READS_MASK 0x0040L
 #define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES_MASK  0x0800L
+#define HDP_MISC_CNTL__READ_BUFFER_WATERMARK_MASK   0xc000L
 #define HDP_MISC_CNTL__FED_ENABLE_MASK 0x0020L
 #define HDP_MISC_CNTL__SYSHUB_CHANNEL_PRIORITY_MASK0x0080L
 #define HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE_MASK   0x0100L
-- 
2.25.1

RE: [PATCH] drm/amd/pm: Fix missing prototype warning

[Chen, Guchun]

Reviewed-by: Guchun Chen 

Regards,
Guchun

-Original Message-
From: amd-gfx  On Behalf Of Lijo Lazar
Sent: Wednesday, February 23, 2022 1:27 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Liang, Prike 
; kernel test robot ; Zhang, Hawking 

Subject: [PATCH] drm/amd/pm: Fix missing prototype warning

Fix below warning
warning: no previous prototype for '__smu_get_enabled_features' 
[-Wmissing-prototypes]

Fixes: 716622108a9f("drm/amd/pm: validate SMU feature enable message for 
getting feature enabled mask")
Reported-by: kernel test robot 
Signed-off-by: Lijo Lazar 
---
 drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
index 1bd6edf2be41..590a6ed12d54 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
@@ -523,7 +523,7 @@ int smu_cmn_feature_is_supported(struct smu_context *smu,
return test_bit(feature_id, feature->supported);  }
 
-int __smu_get_enabled_features(struct smu_context *smu,
+static int __smu_get_enabled_features(struct smu_context *smu,
   uint64_t *enabled_features)
 {
return smu_cmn_call_asic_func(get_enabled_mask, smu, enabled_features);
--
2.25.1

[PATCH] drm/amd/pm: Fix missing prototype warning

[Lijo Lazar]

Fix below warning
warning: no previous prototype for '__smu_get_enabled_features' 
[-Wmissing-prototypes]

Fixes: 716622108a9f("drm/amd/pm: validate SMU feature enable message for 
getting feature enabled mask")
Reported-by: kernel test robot 
Signed-off-by: Lijo Lazar 
---
 drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
index 1bd6edf2be41..590a6ed12d54 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
@@ -523,7 +523,7 @@ int smu_cmn_feature_is_supported(struct smu_context *smu,
return test_bit(feature_id, feature->supported);
 }
 
-int __smu_get_enabled_features(struct smu_context *smu,
+static int __smu_get_enabled_features(struct smu_context *smu,
   uint64_t *enabled_features)
 {
return smu_cmn_call_asic_func(get_enabled_mask, smu, enabled_features);
-- 
2.25.1

Re: [PATCH 1/2] drm/amdgpu/nv: enable gfx10.3.7 clock gating support

[Huang Rui]

On Wed, Feb 23, 2022 at 10:42:34AM +0800, Liang, Prike wrote:
> This will enable the following gfx clock gating.
> - Fine clock gating
> - Medium Grain clock gating
> - 3D Coarse clock gating
> - Coarse Grain clock gating
> - RLC/CP light sleep clock gating
> 
> Signed-off-by: Prike Liang 

Series are Reviewed-by: Huang Rui 

> ---
>  drivers/gpu/drm/amd/amdgpu/nv.c | 10 +-
>  1 file changed, 9 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
> index 74e0550d00bd..5f375f3430e1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nv.c
> @@ -936,7 +936,15 @@ static int nv_common_early_init(void *handle)
>   adev->external_rev_id = adev->rev_id + 0x01;
>   break;
>   case IP_VERSION(10, 3, 7):
> - adev->cg_flags = 0;
> + adev->cg_flags =  AMD_CG_SUPPORT_GFX_MGCG |
> + AMD_CG_SUPPORT_GFX_MGLS |
> + AMD_CG_SUPPORT_GFX_CGCG |
> + AMD_CG_SUPPORT_GFX_CGLS |
> + AMD_CG_SUPPORT_GFX_3D_CGCG |
> + AMD_CG_SUPPORT_GFX_3D_CGLS |
> + AMD_CG_SUPPORT_GFX_RLC_LS |
> + AMD_CG_SUPPORT_GFX_CP_LS |
> + AMD_CG_SUPPORT_GFX_FGCG;
>   adev->pg_flags = AMD_PG_SUPPORT_VCN |
>   AMD_PG_SUPPORT_VCN_DPG |
>   AMD_PG_SUPPORT_JPEG;
> -- 
> 2.17.1
> 

[PATCH 2/2] drm/amdgpu/nv: set mode2 reset for MP1 13.0.8

[Prike Liang]

Set mode2 reset support for MP1 13.0.8.

Signed-off-by: Prike Liang 
---
 drivers/gpu/drm/amd/amdgpu/nv.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 5f375f3430e1..f414b7ca0ab7 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -454,6 +454,7 @@ nv_asic_reset_method(struct amdgpu_device *adev)
case IP_VERSION(11, 5, 0):
case IP_VERSION(13, 0, 1):
case IP_VERSION(13, 0, 3):
+   case IP_VERSION(13, 0, 8):
return AMD_RESET_METHOD_MODE2;
case IP_VERSION(11, 0, 7):
case IP_VERSION(11, 0, 11):
-- 
2.17.1

[PATCH 1/2] drm/amdgpu/nv: enable gfx10.3.7 clock gating support

[Prike Liang]

This will enable the following gfx clock gating.
- Fine clock gating
- Medium Grain clock gating
- 3D Coarse clock gating
- Coarse Grain clock gating
- RLC/CP light sleep clock gating

Signed-off-by: Prike Liang 
---
 drivers/gpu/drm/amd/amdgpu/nv.c | 10 +-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 74e0550d00bd..5f375f3430e1 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -936,7 +936,15 @@ static int nv_common_early_init(void *handle)
adev->external_rev_id = adev->rev_id + 0x01;
break;
case IP_VERSION(10, 3, 7):
-   adev->cg_flags = 0;
+   adev->cg_flags =  AMD_CG_SUPPORT_GFX_MGCG |
+   AMD_CG_SUPPORT_GFX_MGLS |
+   AMD_CG_SUPPORT_GFX_CGCG |
+   AMD_CG_SUPPORT_GFX_CGLS |
+   AMD_CG_SUPPORT_GFX_3D_CGCG |
+   AMD_CG_SUPPORT_GFX_3D_CGLS |
+   AMD_CG_SUPPORT_GFX_RLC_LS |
+   AMD_CG_SUPPORT_GFX_CP_LS |
+   AMD_CG_SUPPORT_GFX_FGCG;
adev->pg_flags = AMD_PG_SUPPORT_VCN |
AMD_PG_SUPPORT_VCN_DPG |
AMD_PG_SUPPORT_JPEG;
-- 
2.17.1

RE: [PATCH] PCI: Apply quirk_amd_harvest_no_ats to all navi10 and 14 asics

[Chen, Guchun]

Acked-by: Guchun Chen 

Regards,
Guchun

-Original Message-
From: amd-gfx  On Behalf Of Alex Deucher
Sent: Wednesday, February 23, 2022 12:08 AM
To: amd-gfx@lists.freedesktop.org; bhelg...@google.com; 
linux-...@vger.kernel.org
Cc: Deucher, Alexander 
Subject: [PATCH] PCI: Apply quirk_amd_harvest_no_ats to all navi10 and 14 asics

There are enough vbios escapes without the proper workaround that some users 
still hit this.  MS never productized ATS on windows so OEM platforms that were 
windows only didn't always validate ATS.

The advantages of ATS are not worth it compared to the potential instabilities 
on harvested boards.  Just disable ATS on all navi10 and 14 boards.

Bug: 
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgitlab.freedesktop.org%2Fdrm%2Famd%2F-%2Fissues%2F1760&data=04%7C01%7Cguchun.chen%40amd.com%7C1f54cd26c00041e476d008d9f61d92e8%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637811429151667411%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata=1seVVxNb09HvAGelvuyN3WuHI%2BkCkfU%2F50Zzx4rifT4%3D&reserved=0
Signed-off-by: Alex Deucher 
---
 drivers/pci/quirks.c | 14 +-
 1 file changed, 9 insertions(+), 5 deletions(-)

diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 
003950c738d2..ea2de1616510 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -5341,11 +5341,6 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 
0x0422, quirk_no_ext_tags);
  */
 static void quirk_amd_harvest_no_ats(struct pci_dev *pdev)  {
-   if ((pdev->device == 0x7312 && pdev->revision != 0x00) ||
-   (pdev->device == 0x7340 && pdev->revision != 0xc5) ||
-   (pdev->device == 0x7341 && pdev->revision != 0x00))
-   return;
-
if (pdev->device == 0x15d8) {
if (pdev->revision == 0xcf &&
pdev->subsystem_vendor == 0xea50 && @@ -5367,10 +5362,19 @@ 
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_amd_harvest_no_ats);
 /* AMD Iceland dGPU */
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6900, quirk_amd_harvest_no_ats);
 /* AMD Navi10 dGPU */
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7310, 
+quirk_amd_harvest_no_ats);
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7312, quirk_amd_harvest_no_ats);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7318, 
+quirk_amd_harvest_no_ats); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 
+0x7319, quirk_amd_harvest_no_ats); 
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731a, 
+quirk_amd_harvest_no_ats); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 
+0x731b, quirk_amd_harvest_no_ats); 
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731e, 
+quirk_amd_harvest_no_ats); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 
+0x731f, quirk_amd_harvest_no_ats);
 /* AMD Navi14 dGPU */
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7340, quirk_amd_harvest_no_ats);  
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7341, quirk_amd_harvest_no_ats);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7347, 
+quirk_amd_harvest_no_ats); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 
+0x734f, quirk_amd_harvest_no_ats);
 /* AMD Raven platform iGPU */
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x15d8, quirk_amd_harvest_no_ats);  
#endif /* CONFIG_PCI_ATS */
--
2.35.1

Re: [PATCH] drm/amdgpu: limit harvest bit read on several ASICs

[Deucher, Alexander]

[AMD Official Use Only]

No that's fine.  Just checking.

Alex


From: Chen, Guchun 
Sent: Tuesday, February 22, 2022 9:29 PM
To: Alex Deucher 
Cc: amd-gfx list ; Deucher, Alexander 
; Zhang, Hawking ; Koenig, 
Christian ; Pan, Xinhui 
Subject: RE: [PATCH] drm/amdgpu: limit harvest bit read on several ASICs

Hi Alex,

This patch has covered the check of VCN as well. So you want me to modify the 
comments to add VCN as well?

Regards,
Guchun

-Original Message-
From: Alex Deucher 
Sent: Wednesday, February 23, 2022 1:00 AM
To: Chen, Guchun 
Cc: amd-gfx list ; Deucher, Alexander 
; Zhang, Hawking ; Koenig, 
Christian ; Pan, Xinhui 
Subject: Re: [PATCH] drm/amdgpu: limit harvest bit read on several ASICs

On Tue, Feb 22, 2022 at 10:07 AM Guchun Chen  wrote:
>
> Due to faulty VBIOS out there, harvest bit setting is not consistently
> correct especially for display IP. So far, it's hard to work out a
> solution on all the legacy Navi1x ASICs in a short time, so to avoid
> regression, limit harvest bit read on several ASICs. Will revisit
> later once VBIOS has corrected it in long term.
>

Looks like it may be incorrect for VCN as well.  Double check that.

Alex


> Fixes: b3f4ea887d5f("drm/amdgpu: read harvest bit per IP data on
> legacy GPUs")
> Signed-off-by: Guchun Chen 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 18 +-
>  1 file changed, 13 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> index 11255290f117..2e0ff1ace6fc 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> @@ -1129,12 +1129,20 @@ void amdgpu_discovery_harvest_ip(struct amdgpu_device 
> *adev)
>  * so read harvest bit per IP data structure to set
>  * harvest configuration.
>  */
> -   if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 2, 0))
> -   amdgpu_discovery_read_harvest_bit_per_ip(adev,
> -   &vcn_harvest_count);
> -   else
> +   if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 2, 0)) {
> +   if ((adev->pdev->device == 0x731E &&
> +   (adev->pdev->revision == 0xC6 ||
> +adev->pdev->revision == 0xC7)) ||
> +   (adev->pdev->device == 0x7340 &&
> +adev->pdev->revision == 0xC9) ||
> +   (adev->pdev->device == 0x7360 &&
> +adev->pdev->revision == 0xC7))
> +   amdgpu_discovery_read_harvest_bit_per_ip(adev,
> +   &vcn_harvest_count);
> +   } else {
> amdgpu_disocvery_read_from_harvest_table(adev,
> -   &vcn_harvest_count);
> +   &vcn_harvest_count);
> +   }
>
> amdgpu_discovery_harvest_config_quirk(adev);
>
> --
> 2.17.1
>

[PATCH AUTOSEL 5.15 20/28] drm/amd/pm: correct UMD pstate clocks for Dimgrey Cavefish and Beige Goby

[Sasha Levin]

From: Evan Quan 

[ Upstream commit 0136f5844b006e2286f873457c3fcba8c45a3735 ]

Correct the UMD pstate profiling clocks for Dimgrey Cavefish and Beige
Goby.

Signed-off-by: Evan Quan 
Reviewed-by: Alex Deucher 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c   | 26 +++
 .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.h   |  8 ++
 2 files changed, 29 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index f89bf49965fcd..20ab937c6450a 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -1278,21 +1278,37 @@ static int sienna_cichlid_populate_umd_state_clk(struct 
smu_context *smu)
&dpm_context->dpm_tables.soc_table;
struct smu_umd_pstate_table *pstate_table =
&smu->pstate_table;
+   struct amdgpu_device *adev = smu->adev;
 
pstate_table->gfxclk_pstate.min = gfx_table->min;
pstate_table->gfxclk_pstate.peak = gfx_table->max;
-   if (gfx_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK)
-   pstate_table->gfxclk_pstate.standard = 
SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK;
 
pstate_table->uclk_pstate.min = mem_table->min;
pstate_table->uclk_pstate.peak = mem_table->max;
-   if (mem_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK)
-   pstate_table->uclk_pstate.standard = 
SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK;
 
pstate_table->socclk_pstate.min = soc_table->min;
pstate_table->socclk_pstate.peak = soc_table->max;
-   if (soc_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK)
+
+   switch (adev->asic_type) {
+   case CHIP_SIENNA_CICHLID:
+   case CHIP_NAVY_FLOUNDER:
+   pstate_table->gfxclk_pstate.standard = 
SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK;
+   pstate_table->uclk_pstate.standard = 
SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK;
pstate_table->socclk_pstate.standard = 
SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK;
+   break;
+   case CHIP_DIMGREY_CAVEFISH:
+   pstate_table->gfxclk_pstate.standard = 
DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_GFXCLK;
+   pstate_table->uclk_pstate.standard = 
DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_MEMCLK;
+   pstate_table->socclk_pstate.standard = 
DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_SOCCLK;
+   break;
+   case CHIP_BEIGE_GOBY:
+   pstate_table->gfxclk_pstate.standard = 
BEIGE_GOBY_UMD_PSTATE_PROFILING_GFXCLK;
+   pstate_table->uclk_pstate.standard = 
BEIGE_GOBY_UMD_PSTATE_PROFILING_MEMCLK;
+   pstate_table->socclk_pstate.standard = 
BEIGE_GOBY_UMD_PSTATE_PROFILING_SOCCLK;
+   break;
+   default:
+   break;
+   }
 
return 0;
 }
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.h 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.h
index 38cd0ece24f6b..42f705c7a36f8 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.h
@@ -33,6 +33,14 @@ typedef enum {
 #define SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK960
 #define SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK1000
 
+#define DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_GFXCLK 1950
+#define DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_SOCCLK 960
+#define DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_MEMCLK 676
+
+#define BEIGE_GOBY_UMD_PSTATE_PROFILING_GFXCLK 2200
+#define BEIGE_GOBY_UMD_PSTATE_PROFILING_SOCCLK 960
+#define BEIGE_GOBY_UMD_PSTATE_PROFILING_MEMCLK 1000
+
 extern void sienna_cichlid_set_ppt_funcs(struct smu_context *smu);
 
 #endif
-- 
2.34.1

RE: [PATCH] drm/amdgpu: limit harvest bit read on several ASICs

[Chen, Guchun]

Hi Alex,

This patch has covered the check of VCN as well. So you want me to modify the 
comments to add VCN as well?

Regards,
Guchun

-Original Message-
From: Alex Deucher  
Sent: Wednesday, February 23, 2022 1:00 AM
To: Chen, Guchun 
Cc: amd-gfx list ; Deucher, Alexander 
; Zhang, Hawking ; Koenig, 
Christian ; Pan, Xinhui 
Subject: Re: [PATCH] drm/amdgpu: limit harvest bit read on several ASICs

On Tue, Feb 22, 2022 at 10:07 AM Guchun Chen  wrote:
>
> Due to faulty VBIOS out there, harvest bit setting is not consistently 
> correct especially for display IP. So far, it's hard to work out a 
> solution on all the legacy Navi1x ASICs in a short time, so to avoid 
> regression, limit harvest bit read on several ASICs. Will revisit 
> later once VBIOS has corrected it in long term.
>

Looks like it may be incorrect for VCN as well.  Double check that.

Alex


> Fixes: b3f4ea887d5f("drm/amdgpu: read harvest bit per IP data on 
> legacy GPUs")
> Signed-off-by: Guchun Chen 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 18 +-
>  1 file changed, 13 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> index 11255290f117..2e0ff1ace6fc 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> @@ -1129,12 +1129,20 @@ void amdgpu_discovery_harvest_ip(struct amdgpu_device 
> *adev)
>  * so read harvest bit per IP data structure to set
>  * harvest configuration.
>  */
> -   if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 2, 0))
> -   amdgpu_discovery_read_harvest_bit_per_ip(adev,
> -   &vcn_harvest_count);
> -   else
> +   if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 2, 0)) {
> +   if ((adev->pdev->device == 0x731E &&
> +   (adev->pdev->revision == 0xC6 ||
> +adev->pdev->revision == 0xC7)) ||
> +   (adev->pdev->device == 0x7340 &&
> +adev->pdev->revision == 0xC9) ||
> +   (adev->pdev->device == 0x7360 &&
> +adev->pdev->revision == 0xC7))
> +   amdgpu_discovery_read_harvest_bit_per_ip(adev,
> +   &vcn_harvest_count);
> +   } else {
> amdgpu_disocvery_read_from_harvest_table(adev,
> -   &vcn_harvest_count);
> +   &vcn_harvest_count);
> +   }
>
> amdgpu_discovery_harvest_config_quirk(adev);
>
> --
> 2.17.1
>

[PATCH AUTOSEL 5.16 22/30] drm/amd/pm: correct UMD pstate clocks for Dimgrey Cavefish and Beige Goby

[Sasha Levin]

From: Evan Quan 

[ Upstream commit 0136f5844b006e2286f873457c3fcba8c45a3735 ]

Correct the UMD pstate profiling clocks for Dimgrey Cavefish and Beige
Goby.

Signed-off-by: Evan Quan 
Reviewed-by: Alex Deucher 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c   | 26 +++
 .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.h   |  8 ++
 2 files changed, 29 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 446d37320b948..cd75a65982cf7 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -1231,21 +1231,37 @@ static int sienna_cichlid_populate_umd_state_clk(struct 
smu_context *smu)
&dpm_context->dpm_tables.soc_table;
struct smu_umd_pstate_table *pstate_table =
&smu->pstate_table;
+   struct amdgpu_device *adev = smu->adev;
 
pstate_table->gfxclk_pstate.min = gfx_table->min;
pstate_table->gfxclk_pstate.peak = gfx_table->max;
-   if (gfx_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK)
-   pstate_table->gfxclk_pstate.standard = 
SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK;
 
pstate_table->uclk_pstate.min = mem_table->min;
pstate_table->uclk_pstate.peak = mem_table->max;
-   if (mem_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK)
-   pstate_table->uclk_pstate.standard = 
SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK;
 
pstate_table->socclk_pstate.min = soc_table->min;
pstate_table->socclk_pstate.peak = soc_table->max;
-   if (soc_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK)
+
+   switch (adev->asic_type) {
+   case CHIP_SIENNA_CICHLID:
+   case CHIP_NAVY_FLOUNDER:
+   pstate_table->gfxclk_pstate.standard = 
SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK;
+   pstate_table->uclk_pstate.standard = 
SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK;
pstate_table->socclk_pstate.standard = 
SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK;
+   break;
+   case CHIP_DIMGREY_CAVEFISH:
+   pstate_table->gfxclk_pstate.standard = 
DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_GFXCLK;
+   pstate_table->uclk_pstate.standard = 
DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_MEMCLK;
+   pstate_table->socclk_pstate.standard = 
DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_SOCCLK;
+   break;
+   case CHIP_BEIGE_GOBY:
+   pstate_table->gfxclk_pstate.standard = 
BEIGE_GOBY_UMD_PSTATE_PROFILING_GFXCLK;
+   pstate_table->uclk_pstate.standard = 
BEIGE_GOBY_UMD_PSTATE_PROFILING_MEMCLK;
+   pstate_table->socclk_pstate.standard = 
BEIGE_GOBY_UMD_PSTATE_PROFILING_SOCCLK;
+   break;
+   default:
+   break;
+   }
 
return 0;
 }
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.h 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.h
index 38cd0ece24f6b..42f705c7a36f8 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.h
@@ -33,6 +33,14 @@ typedef enum {
 #define SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK960
 #define SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK1000
 
+#define DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_GFXCLK 1950
+#define DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_SOCCLK 960
+#define DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_MEMCLK 676
+
+#define BEIGE_GOBY_UMD_PSTATE_PROFILING_GFXCLK 2200
+#define BEIGE_GOBY_UMD_PSTATE_PROFILING_SOCCLK 960
+#define BEIGE_GOBY_UMD_PSTATE_PROFILING_MEMCLK 1000
+
 extern void sienna_cichlid_set_ppt_funcs(struct smu_context *smu);
 
 #endif
-- 
2.34.1

[PATCH] Revert "drm/amd/display: Remove unused temp variable"

[Alex Deucher]

This reverts commit b1f0ab445ec609f9b58e0969c5d052b52d9a54e7.

This patch is not valid.  The driver needs to actually read the
entries in the ring buffer.  Add a comment to make this clear.

Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1916
Cc: Maíra Canal 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 9 -
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h 
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index d3088836d4e4..cb92ab4c8b98 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -2918,8 +2918,15 @@ static inline void dmub_rb_flush_pending(const struct 
dmub_rb *rb)
while (rptr != wptr) {
uint64_t volatile *data = (uint64_t volatile *)((uint8_t 
*)(rb->base_address) + rptr);
//uint64_t volatile *p = (uint64_t volatile *)data;
+   uint64_t temp;
+   uint8_t i;
 
-   *data += DMUB_RB_CMD_SIZE / sizeof(uint64_t);
+   /* Don't remove this.
+* The contents need to actually be read from the ring buffer
+* for this function to be effective.
+*/
+   for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++)
+   temp = *data++;
 
rptr += DMUB_RB_CMD_SIZE;
if (rptr >= rb->capacity)
-- 
2.35.1

RE: [PATCH] drm/amdgpu: fix typo in amdgpu_discovery.c

[Chen, Guchun]

Reviewed-by: Guchun Chen 

Regards,
Guchun

-Original Message-
From: amd-gfx  On Behalf Of Alex Deucher
Sent: Wednesday, February 23, 2022 4:57 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander 
Subject: [PATCH] drm/amdgpu: fix typo in amdgpu_discovery.c

disocvery -> discovery

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index 2e0ff1ace6fc..e4fcbb385a62 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -435,8 +435,8 @@ static void amdgpu_discovery_read_harvest_bit_per_ip(struct 
amdgpu_device *adev,
}
 }
 
-static void amdgpu_disocvery_read_from_harvest_table(struct amdgpu_device 
*adev,
-   uint32_t *vcn_harvest_count)
+static void amdgpu_discovery_read_from_harvest_table(struct amdgpu_device 
*adev,
+uint32_t 
*vcn_harvest_count)
 {
struct binary_header *bhdr;
struct harvest_table *harvest_info;
@@ -1140,7 +1140,7 @@ void amdgpu_discovery_harvest_ip(struct amdgpu_device 
*adev)
amdgpu_discovery_read_harvest_bit_per_ip(adev,
&vcn_harvest_count);
} else {
-   amdgpu_disocvery_read_from_harvest_table(adev,
+   amdgpu_discovery_read_from_harvest_table(adev,
&vcn_harvest_count);
}
 
-- 
2.35.1

[PATCH 4/4] drm/amd/display: increasing DRAM BW percent for DCN315

[Qingqing Zhuo]

From: Sung Joon Kim 

[why]
DML validation fails when we connect two or
more displays with HDR. Need to increase
DRAM BW to make the validation passing.
Following the value from DCN31.

[how]
Change the max DRAM BW DML field to 60%.

Reviewed-by: Charlene Liu 
Acked-by: Qingqing Zhuo 
Signed-off-by: Sung Joon Kim 
Reviewed-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
index 46b170e60a54..a71073482881 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
@@ -273,7 +273,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_15_soc = {
.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0,
.pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0,
.max_avg_sdp_bw_use_normal_percent = 60.0,
-   .max_avg_dram_bw_use_normal_percent = 30.0,
+   .max_avg_dram_bw_use_normal_percent = 60.0,
.fabric_datapath_to_dcn_data_return_bytes = 32,
.return_bus_width_bytes = 64,
.downspread_percent = 0.38,
-- 
2.25.1

[PATCH 3/4] drm/amd/display: Set compbuf size to min at prep prevent overbook crb

[Qingqing Zhuo]

From: "Ma, Duncan" 

[Why]
Detbuffer size is dynamically set for dcn31x. At certain moment,
compbuf+(def size * num pipes) > config return buffer size causing
flickering. This is easily reproducible when MPO is
enabled with two displays.

[How]
At prepare BW, use the min comp buffer size. When it is to
optimize BW, set compbuf size back to maximum possible size.

Reviewed-by: Charlene Liu 
Acked-by: Qingqing Zhuo 
Signed-off-by: Duncan Ma 
Reviewed-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c   | 12 ++--
 .../gpu/drm/amd/display/dc/dcn315/dcn315_resource.c  |  1 +
 .../drm/amd/display/dc/dml/display_mode_structs.h|  1 +
 3 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 20a9cbb7c0a8..1ef880fed776 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1818,6 +1818,7 @@ void dcn20_prepare_bandwidth(
struct dc_state *context)
 {
struct hubbub *hubbub = dc->res_pool->hubbub;
+   unsigned int compbuf_size_kb = 0;
 
dc->clk_mgr->funcs->update_clocks(
dc->clk_mgr,
@@ -1829,9 +1830,16 @@ void dcn20_prepare_bandwidth(
&context->bw_ctx.bw.dcn.watermarks,

dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
false);
+
/* decrease compbuf size */
-   if (hubbub->funcs->program_compbuf_size)
-   hubbub->funcs->program_compbuf_size(hubbub, 
context->bw_ctx.bw.dcn.compbuf_size_kb, false);
+   if (hubbub->funcs->program_compbuf_size) {
+   if (context->bw_ctx.dml.ip.min_comp_buffer_size_kbytes)
+   compbuf_size_kb = 
context->bw_ctx.dml.ip.min_comp_buffer_size_kbytes;
+   else
+   compbuf_size_kb = 
context->bw_ctx.bw.dcn.compbuf_size_kb;
+
+   hubbub->funcs->program_compbuf_size(hubbub, compbuf_size_kb, 
false);
+   }
 }
 
 void dcn20_optimize_bandwidth(
diff --git a/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
index f22158bb4b13..46b170e60a54 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
@@ -147,6 +147,7 @@ struct _vcs_dpi_ip_params_st dcn3_15_ip = {
.hostvm_max_page_table_levels = 2,
.rob_buffer_size_kbytes = 64,
.det_buffer_size_kbytes = DCN3_15_DEFAULT_DET_SIZE,
+   .min_comp_buffer_size_kbytes = DCN3_15_MIN_COMPBUF_SIZE_KB,
.config_return_buffer_size_in_kbytes = 1024,
.compressed_buffer_segment_size_in_kbytes = 64,
.meta_fifo_size_in_kentries = 32,
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h 
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
index 8f9f1d607f7c..59f0a61c33cf 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
@@ -141,6 +141,7 @@ struct _vcs_dpi_ip_params_st {
unsigned int odm_capable;
unsigned int rob_buffer_size_kbytes;
unsigned int det_buffer_size_kbytes;
+   unsigned int min_comp_buffer_size_kbytes;
unsigned int dpte_buffer_size_in_pte_reqs_luma;
unsigned int dpte_buffer_size_in_pte_reqs_chroma;
unsigned int pde_proc_buffer_size_64k_reqs;
-- 
2.25.1

[PATCH 2/4] drm/amd/display: revert populating dcn315 clk table based on dcfclk

[Qingqing Zhuo]

From: Dmytro Laktyushkin 

[Why & How]
Due to how pmfw fills out the table when dcfclk states are disabled,
using dcfclk based clk table would cause a no read situation.
Revert the change to prevent underflow until a better solution is coded.

Reviewed-by: Charlene Liu 
Acked-by: Qingqing Zhuo 
Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Harry Wentland 
---
 .../dc/clk_mgr/dcn315/dcn315_clk_mgr.c| 52 +++
 1 file changed, 31 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
index 90c265275f93..d66633bef2b3 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
@@ -414,23 +414,20 @@ static uint32_t find_max_clk_value(const uint32_t 
clocks[], uint32_t num_clocks)
return max;
 }
 
-static unsigned int find_dfpstate_for_voltage(
-   const DfPstateTable_t table[],
-   unsigned int NumDfPstatesEnabled,
+static unsigned int find_clk_for_voltage(
+   const DpmClocks_315_t *clock_table,
+   const uint32_t clocks[],
unsigned int voltage)
 {
int i;
-   unsigned int minVoltage = table[0].Voltage;
-   unsigned int minlevel = 0;
 
-   for (i = 1; i < NumDfPstatesEnabled; i++) {
-   if (table[i].Voltage >= voltage && minVoltage > 
table[i].Voltage) {
-   minVoltage = table[i].Voltage;
-   minlevel = i;
-   }
+   for (i = 0; i < NUM_SOC_VOLTAGE_LEVELS; i++) {
+   if (clock_table->SocVoltage[i] == voltage)
+   return clocks[i];
}
 
-   return minlevel;
+   ASSERT(0);
+   return 0;
 }
 
 void dcn315_clk_mgr_helper_populate_bw_params(
@@ -438,21 +435,30 @@ void dcn315_clk_mgr_helper_populate_bw_params(
struct integrated_info *bios_info,
const DpmClocks_315_t *clock_table)
 {
-   int i, num_clk_lvl;
+   int i, j;
struct clk_bw_params *bw_params = clk_mgr->base.bw_params;
uint32_t max_dispclk = 0, max_dppclk = 0;
 
-   num_clk_lvl = clock_table->NumDcfClkLevelsEnabled;
+   j = -1;
+
+   ASSERT(NUM_DF_PSTATE_LEVELS <= MAX_NUM_DPM_LVL);
+
+   /* Find lowest DPM, FCLK is filled in reverse order*/
 
-   ASSERT(num_clk_lvl <= MAX_NUM_DPM_LVL);
+   for (i = NUM_DF_PSTATE_LEVELS - 1; i >= 0; i--) {
+   if (clock_table->DfPstateTable[i].FClk != 0) {
+   j = i;
+   break;
+   }
+   }
 
-   if (num_clk_lvl == 0 || clock_table->DcfClocks[0] == 0) {
-   /* clock table is no good, just use our own hardcode */
+   if (j == -1) {
+   /* clock table is all 0s, just use our own hardcode */
ASSERT(0);
return;
}
 
-   bw_params->clk_table.num_entries = num_clk_lvl;
+   bw_params->clk_table.num_entries = j + 1;
 
/* dispclk and dppclk can be max at any voltage, same number of levels 
for both */
if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS &&
@@ -463,15 +469,19 @@ void dcn315_clk_mgr_helper_populate_bw_params(
ASSERT(0);
}
 
-   for (i = 0; i < bw_params->clk_table.num_entries; i++) {
-   int j = find_dfpstate_for_voltage(clock_table->DfPstateTable, 
clock_table->NumDfPstatesEnabled, clock_table->SocVoltage[i]);
+   for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) {
+   int temp;
 
bw_params->clk_table.entries[i].fclk_mhz = 
clock_table->DfPstateTable[j].FClk;
bw_params->clk_table.entries[i].memclk_mhz = 
clock_table->DfPstateTable[j].MemClk;
bw_params->clk_table.entries[i].voltage = 
clock_table->DfPstateTable[j].Voltage;
bw_params->clk_table.entries[i].wck_ratio = 1;
-   bw_params->clk_table.entries[i].dcfclk_mhz = 
clock_table->DcfClocks[i];
-   bw_params->clk_table.entries[i].socclk_mhz = 
clock_table->SocClocks[i];
+   temp = find_clk_for_voltage(clock_table, 
clock_table->DcfClocks, clock_table->DfPstateTable[j].Voltage);
+   if (temp)
+   bw_params->clk_table.entries[i].dcfclk_mhz = temp;
+   temp = find_clk_for_voltage(clock_table, 
clock_table->SocClocks, clock_table->DfPstateTable[j].Voltage);
+   if (temp)
+   bw_params->clk_table.entries[i].socclk_mhz = temp;
bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk;
bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk;
}
-- 
2.25.1

[PATCH 1/4] drm/amd/display: limit unbounded requesting to 5k

[Qingqing Zhuo]

From: Dmytro Laktyushkin 

[WHy & How]
Unbounded requesting is unsupported on pipe split modes
and this change prevents us running into such a situation
with wide modes.

Reviewed-by: Charlene Liu 
Acked-by: Qingqing Zhuo 
Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
index 406492655dee..f22158bb4b13 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
@@ -1841,7 +1841,8 @@ static int dcn315_populate_dml_pipes_from_context(
dc->config.enable_4to1MPC = true;
context->bw_ctx.dml.ip.det_buffer_size_kbytes =
(max_usable_det / 
DCN3_15_CRB_SEGMENT_SIZE_KB / 4) * DCN3_15_CRB_SEGMENT_SIZE_KB;
-   } else if (!is_dual_plane(pipe->plane_state->format)) {
+   } else if (!is_dual_plane(pipe->plane_state->format) && 
pipe->plane_state->src_rect.width <= 5120) {
+   /* Limit to 5k max to avoid forced pipe split when 
there is not enough detile for swath */
context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192;
pipes[0].pipe.src.unbounded_req_mode = true;
}
-- 
2.25.1

[PATCH] drm/amdgpu: fix typo in amdgpu_discovery.c

[Alex Deucher]

disocvery -> discovery

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index 2e0ff1ace6fc..e4fcbb385a62 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -435,8 +435,8 @@ static void amdgpu_discovery_read_harvest_bit_per_ip(struct 
amdgpu_device *adev,
}
 }
 
-static void amdgpu_disocvery_read_from_harvest_table(struct amdgpu_device 
*adev,
-   uint32_t *vcn_harvest_count)
+static void amdgpu_discovery_read_from_harvest_table(struct amdgpu_device 
*adev,
+uint32_t 
*vcn_harvest_count)
 {
struct binary_header *bhdr;
struct harvest_table *harvest_info;
@@ -1140,7 +1140,7 @@ void amdgpu_discovery_harvest_ip(struct amdgpu_device 
*adev)
amdgpu_discovery_read_harvest_bit_per_ip(adev,
&vcn_harvest_count);
} else {
-   amdgpu_disocvery_read_from_harvest_table(adev,
+   amdgpu_discovery_read_from_harvest_table(adev,
&vcn_harvest_count);
}
 
-- 
2.35.1

Re: [PATCH v2] drm/amdkfd: Print bdf in peer map failure message

[Felix Kuehling]

Am 2022-02-22 um 13:55 schrieb Harish Kasiviswanathan:

Print alloc node, peer node and memory domain when peer map fails. This
is more useful

v2: use dev_err instead of pr_err
 use bdf for identify peer gpu

Signed-off-by: Harish Kasiviswanathan 


Reviewed-by: Felix Kuehling 



---
  drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 11 +--
  1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
index 965af2a08bc0..9141b674947d 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
@@ -1215,8 +1215,15 @@ static int kfd_ioctl_map_memory_to_gpu(struct file 
*filep,
peer_pdd->dev->adev, (struct kgd_mem *)mem,
peer_pdd->drm_priv, &table_freed);
if (err) {
-   pr_err("Failed to map to gpu %d/%d\n",
-  i, args->n_devices);
+   struct pci_dev *pdev = peer_pdd->dev->adev->pdev;
+
+   dev_err(dev->adev->dev,
+  "Failed to map peer:%04x:%02x:%02x.%d 
mem_domain:%d\n",
+  pci_domain_nr(pdev->bus),
+  pdev->bus->number,
+  PCI_SLOT(pdev->devfn),
+  PCI_FUNC(pdev->devfn),
+  ((struct kgd_mem *)mem)->domain);
goto map_memory_to_gpu_failed;
}
args->n_success = i+1;

Re: [PATCH] drm/amdgpu: fix amdgpu_ras_block_late_init error handler

[Kenny Ho]

On Thu, Feb 17, 2022 at 2:06 PM Alex Deucher  wrote:
>
> On Thu, Feb 17, 2022 at 2:04 PM Nick Desaulniers
>  wrote:
> >
> >
> > Alex,
> > Has AMD been able to set up clang builds, yet?
>
> No.  I think some individual teams do, but it's never been integrated
> into our larger CI systems as of yet as far as I know.

I have just added clang build to our CI last night so hopefully we
should be catching these now.

Kenny

>
> Alex
>
>
> >
> > --
> > Thanks,
> > ~Nick Desaulniers

Re: [PATCH v2] drm/amdkfd: Print bdf in peer map failure message

[Alex Deucher]

On Tue, Feb 22, 2022 at 1:56 PM Harish Kasiviswanathan
 wrote:
>
> Print alloc node, peer node and memory domain when peer map fails. This
> is more useful
>
> v2: use dev_err instead of pr_err
> use bdf for identify peer gpu
>
> Signed-off-by: Harish Kasiviswanathan 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 11 +--
>  1 file changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c 
> b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
> index 965af2a08bc0..9141b674947d 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
> @@ -1215,8 +1215,15 @@ static int kfd_ioctl_map_memory_to_gpu(struct file 
> *filep,
> peer_pdd->dev->adev, (struct kgd_mem *)mem,
> peer_pdd->drm_priv, &table_freed);
> if (err) {
> -   pr_err("Failed to map to gpu %d/%d\n",
> -  i, args->n_devices);
> +   struct pci_dev *pdev = peer_pdd->dev->adev->pdev;
> +
> +   dev_err(dev->adev->dev,
> +  "Failed to map peer:%04x:%02x:%02x.%d 
> mem_domain:%d\n",
> +  pci_domain_nr(pdev->bus),
> +  pdev->bus->number,
> +  PCI_SLOT(pdev->devfn),
> +  PCI_FUNC(pdev->devfn),
> +  ((struct kgd_mem *)mem)->domain);
> goto map_memory_to_gpu_failed;
> }
> args->n_success = i+1;
> --
> 2.25.1
>

Re: [PATCH 2/7] drm/selftests: add drm buddy alloc limit testcase

[Arunpravin]

On 08/02/22 3:10 pm, Matthew Auld wrote:
> On 03/02/2022 13:32, Arunpravin wrote:
>> add a test to check the maximum allocation limit
>>
>> Signed-off-by: Arunpravin 
>> ---
>>   .../gpu/drm/selftests/drm_buddy_selftests.h   |  1 +
>>   drivers/gpu/drm/selftests/test-drm_buddy.c| 60 +++
>>   2 files changed, 61 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/selftests/drm_buddy_selftests.h 
>> b/drivers/gpu/drm/selftests/drm_buddy_selftests.h
>> index a4bcf3a6dfe3..ebe16162762f 100644
>> --- a/drivers/gpu/drm/selftests/drm_buddy_selftests.h
>> +++ b/drivers/gpu/drm/selftests/drm_buddy_selftests.h
>> @@ -7,3 +7,4 @@
>>* Tests are executed in order by igt/drm_buddy
>>*/
>>   selftest(sanitycheck, igt_sanitycheck) /* keep first (selfcheck for igt) */
>> +selftest(buddy_alloc_limit, igt_buddy_alloc_limit)
>> diff --git a/drivers/gpu/drm/selftests/test-drm_buddy.c 
>> b/drivers/gpu/drm/selftests/test-drm_buddy.c
>> index 51e4d393d22c..fd7d1a112458 100644
>> --- a/drivers/gpu/drm/selftests/test-drm_buddy.c
>> +++ b/drivers/gpu/drm/selftests/test-drm_buddy.c
>> @@ -16,6 +16,66 @@
>>   
>>   static unsigned int random_seed;
>>   
>> +static int igt_buddy_alloc_limit(void *arg)
>> +{
>> +u64 end, size = U64_MAX, start = 0;
>> +struct drm_buddy_block *block;
>> +unsigned long flags = 0;
>> +LIST_HEAD(allocated);
>> +struct drm_buddy mm;
>> +int err;
>> +
>> +size = end = round_down(size, 4096);
>> +err = drm_buddy_init(&mm, size, PAGE_SIZE);
>> +if (err)
>> +return err;
>> +
>> +if (mm.max_order != DRM_BUDDY_MAX_ORDER) {
>> +pr_err("mm.max_order(%d) != %d\n",
>> +   mm.max_order, DRM_BUDDY_MAX_ORDER);
>> +err = -EINVAL;
>> +goto out_fini;
>> +}
>> +
>> +err = drm_buddy_alloc_blocks(&mm, start, end, size,
>> + PAGE_SIZE, &allocated, flags);
>> +
>> +if (unlikely(err))
>> +goto out_free;
>> +
>> +block = list_first_entry_or_null(&allocated,
>> + struct drm_buddy_block,
>> + link);
>> +
>> +if (!block)
> 
> err = -EINVAL;
> 
>> +goto out_fini;
>> +
>> +if (drm_buddy_block_order(block) != mm.max_order) {
>> +pr_err("block order(%d) != %d\n",
>> +   drm_buddy_block_order(block), mm.max_order);
>> +err = -EINVAL;
>> +goto out_free;
>> +}
>> +
>> +if (drm_buddy_block_size(&mm, block) !=
>> +BIT_ULL(mm.max_order) * PAGE_SIZE) {
>> +pr_err("block size(%llu) != %llu\n",
>> +   drm_buddy_block_size(&mm, block),
>> +   BIT_ULL(mm.max_order) * PAGE_SIZE);
>> +err = -EINVAL;
>> +goto out_free;
>> +}
>> +
>> +if (!err)
> 
> Always true AFAICT?
> 
>> +pr_info("%s - succeeded\n", __func__);
> 
> I guess this could be made part of the run_selftests()? It looks like it 
> already prints the current test, perhaps that is already enough?

removed all unnecessary succeeded prints

Thanks,
Arun
> 
> With the err = -EINVAL change, feel free to add,
> Reviewed-by: Matthew Auld 
> 
>> +
>> +out_free:
>> +drm_buddy_free_list(&mm, &allocated);
>> +out_fini:
>> +drm_buddy_fini(&mm);
>> +return err;
>> +}
>> +
>>   static int igt_sanitycheck(void *ignored)
>>   {
>>  pr_info("%s - ok!\n", __func__);

[PATCH v2] drm/amdkfd: Print bdf in peer map failure message

[Harish Kasiviswanathan]

Print alloc node, peer node and memory domain when peer map fails. This
is more useful

v2: use dev_err instead of pr_err
use bdf for identify peer gpu

Signed-off-by: Harish Kasiviswanathan 
---
 drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 11 +--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
index 965af2a08bc0..9141b674947d 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
@@ -1215,8 +1215,15 @@ static int kfd_ioctl_map_memory_to_gpu(struct file 
*filep,
peer_pdd->dev->adev, (struct kgd_mem *)mem,
peer_pdd->drm_priv, &table_freed);
if (err) {
-   pr_err("Failed to map to gpu %d/%d\n",
-  i, args->n_devices);
+   struct pci_dev *pdev = peer_pdd->dev->adev->pdev;
+
+   dev_err(dev->adev->dev,
+  "Failed to map peer:%04x:%02x:%02x.%d 
mem_domain:%d\n",
+  pci_domain_nr(pdev->bus),
+  pdev->bus->number,
+  PCI_SLOT(pdev->devfn),
+  PCI_FUNC(pdev->devfn),
+  ((struct kgd_mem *)mem)->domain);
goto map_memory_to_gpu_failed;
}
args->n_success = i+1;
-- 
2.25.1

Re: [PATCH 1/7] drm/selftests: Move i915 buddy selftests into drm

[Arunpravin]

On 08/02/22 4:05 pm, Matthew Auld wrote:
> On 03/02/2022 13:32, Arunpravin wrote:
>> - move i915 buddy selftests into drm selftests folder
>> - add Makefile and Kconfig support
>> - add sanitycheck testcase
>>
>> Prerequisites
>> - These series of selftests patches are created on top of
>>drm buddy series
>> - Enable kselftests for DRM as a module in .config
>>
>> Signed-off-by: Arunpravin 
> 
> At some point I guess we also want some IGT that picks this up? Like we 
> do in tests/drm_mm.c? That way this can get picked up by CI?

igt-gpu-tools? we need to create tests/drm_buddy.c to pick these tests.
I will create a patch to include drm buddy selftests into igt-gpu-tools
> 
> Acked-by: Matthew Auld 
> 
>> ---
>>   drivers/gpu/drm/Kconfig   |  1 +
>>   drivers/gpu/drm/selftests/Makefile|  3 +-
>>   .../gpu/drm/selftests/drm_buddy_selftests.h   |  9 
>>   drivers/gpu/drm/selftests/test-drm_buddy.c| 49 +++
>>   4 files changed, 61 insertions(+), 1 deletion(-)
>>   create mode 100644 drivers/gpu/drm/selftests/drm_buddy_selftests.h
>>   create mode 100644 drivers/gpu/drm/selftests/test-drm_buddy.c
>>
>> diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
>> index eb5a57ae3c5c..ff856df3f97f 100644
>> --- a/drivers/gpu/drm/Kconfig
>> +++ b/drivers/gpu/drm/Kconfig
>> @@ -71,6 +71,7 @@ config DRM_DEBUG_SELFTEST
>>  select DRM_DP_HELPER
>>  select DRM_LIB_RANDOM
>>  select DRM_KMS_HELPER
>> +select DRM_BUDDY
>>  select DRM_EXPORT_FOR_TESTS if m
>>  default n
>>  help
>> diff --git a/drivers/gpu/drm/selftests/Makefile 
>> b/drivers/gpu/drm/selftests/Makefile
>> index 0856e4b12f70..5ba5f9138c95 100644
>> --- a/drivers/gpu/drm/selftests/Makefile
>> +++ b/drivers/gpu/drm/selftests/Makefile
>> @@ -4,4 +4,5 @@ test-drm_modeset-y := test-drm_modeset_common.o 
>> test-drm_plane_helper.o \
>>test-drm_damage_helper.o test-drm_dp_mst_helper.o \
>>test-drm_rect.o
>>   
>> -obj-$(CONFIG_DRM_DEBUG_SELFTEST) += test-drm_mm.o test-drm_modeset.o 
>> test-drm_cmdline_parser.o
>> +obj-$(CONFIG_DRM_DEBUG_SELFTEST) += test-drm_mm.o test-drm_modeset.o 
>> test-drm_cmdline_parser.o \
>> +test-drm_buddy.o
>> diff --git a/drivers/gpu/drm/selftests/drm_buddy_selftests.h 
>> b/drivers/gpu/drm/selftests/drm_buddy_selftests.h
>> new file mode 100644
>> index ..a4bcf3a6dfe3
>> --- /dev/null
>> +++ b/drivers/gpu/drm/selftests/drm_buddy_selftests.h
>> @@ -0,0 +1,9 @@
>> +/* SPDX-License-Identifier: GPL-2.0 */
>> +/* List each unit test as selftest(name, function)
>> + *
>> + * The name is used as both an enum and expanded as igt__name to create
>> + * a module parameter. It must be unique and legal for a C identifier.
>> + *
>> + * Tests are executed in order by igt/drm_buddy
>> + */
>> +selftest(sanitycheck, igt_sanitycheck) /* keep first (selfcheck for igt) */
>> diff --git a/drivers/gpu/drm/selftests/test-drm_buddy.c 
>> b/drivers/gpu/drm/selftests/test-drm_buddy.c
>> new file mode 100644
>> index ..51e4d393d22c
>> --- /dev/null
>> +++ b/drivers/gpu/drm/selftests/test-drm_buddy.c
>> @@ -0,0 +1,49 @@
>> +// SPDX-License-Identifier: MIT
>> +/*
>> + * Copyright © 2019 Intel Corporation
>> + */
>> +
>> +#define pr_fmt(fmt) "drm_buddy: " fmt
>> +
>> +#include 
>> +
>> +#include 
>> +
>> +#include "../lib/drm_random.h"
>> +
>> +#define TESTS "drm_buddy_selftests.h"
>> +#include "drm_selftest.h"
>> +
>> +static unsigned int random_seed;
>> +
>> +static int igt_sanitycheck(void *ignored)
>> +{
>> +pr_info("%s - ok!\n", __func__);
>> +return 0;
>> +}
>> +
>> +#include "drm_selftest.c"
>> +
>> +static int __init test_drm_buddy_init(void)
>> +{
>> +int err;
>> +
>> +while (!random_seed)
>> +random_seed = get_random_int();
>> +
>> +pr_info("Testing DRM buddy manager (struct drm_buddy), with 
>> random_seed=0x%x\n",
>> +random_seed);
>> +err = run_selftests(selftests, ARRAY_SIZE(selftests), NULL);
>> +
>> +return err > 0 ? 0 : err;
>> +}
>> +
>> +static void __exit test_drm_buddy_exit(void)
>> +{
>> +}
>> +
>> +module_init(test_drm_buddy_init);
>> +module_exit(test_drm_buddy_exit);
>> +
>> +MODULE_AUTHOR("Intel Corporation");
>> +MODULE_LICENSE("GPL");

Re: [PATCH 2/2] drm/amdgpu: use ktime rather than jiffies for benchmark results

[Felix Kuehling]

Am 2022-02-21 um 17:30 schrieb Alex Deucher:

To protect against wraparounds.

Signed-off-by: Alex Deucher 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c | 31 ++-
  1 file changed, 17 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
index 92a2ffefe62e..3136a9ad2d54 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
@@ -29,14 +29,13 @@
  #define AMDGPU_BENCHMARK_COMMON_MODES_N 17
  
  static int amdgpu_benchmark_do_move(struct amdgpu_device *adev, unsigned size,

-   uint64_t saddr, uint64_t daddr, int n)
+   uint64_t saddr, uint64_t daddr, int n, s64 
*time_ms)
  {
-   unsigned long start_jiffies;
-   unsigned long end_jiffies;
+   ktime_t stime, etime;
struct dma_fence *fence;
int i, r;
  
-	start_jiffies = jiffies;

+   stime = ktime_get();
for (i = 0; i < n; i++) {
struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
r = amdgpu_copy_buffer(ring, saddr, daddr, size, NULL, &fence,
@@ -48,25 +47,28 @@ static int amdgpu_benchmark_do_move(struct amdgpu_device 
*adev, unsigned size,
if (r)
goto exit_do_move;
}
-   end_jiffies = jiffies;
-   r = jiffies_to_msecs(end_jiffies - start_jiffies);
  
  exit_do_move:

+   etime = ktime_get();
+   *time_ms = ktime_ms_delta(etime, stime);


Milliseconds are pretty coarse. Would it make sense to use microseconds 
(ktime_us_delta) to get more accurate measurements instead?


Regards,
  Felix



+
return r;
  }
  
  
  static void amdgpu_benchmark_log_results(struct amdgpu_device *adev,

 int n, unsigned size,
-unsigned int time,
+s64 time_ms,
 unsigned sdomain, unsigned ddomain,
 char *kind)
  {
-   unsigned int throughput = (n * (size >> 10)) / time;
+   s64 throughput = (n * (size >> 10));
+
+   throughput = div64_s64(throughput, time_ms);
  
  	dev_info(adev->dev, "amdgpu: %s %u bo moves of %u kB from"

-" %d to %d in %u ms, throughput: %u Mb/s or %u MB/s\n",
-kind, n, size >> 10, sdomain, ddomain, time,
+" %d to %d in %lld ms, throughput: %lld Mb/s or %lld MB/s\n",
+kind, n, size >> 10, sdomain, ddomain, time_ms,
 throughput * 8, throughput);
  }
  
@@ -76,6 +78,7 @@ static int amdgpu_benchmark_move(struct amdgpu_device *adev, unsigned size,

struct amdgpu_bo *dobj = NULL;
struct amdgpu_bo *sobj = NULL;
uint64_t saddr, daddr;
+   s64 time_ms;
int r, n;
  
  	n = AMDGPU_BENCHMARK_ITERATIONS;

@@ -96,11 +99,11 @@ static int amdgpu_benchmark_move(struct amdgpu_device 
*adev, unsigned size,
goto out_cleanup;
  
  	if (adev->mman.buffer_funcs) {

-   r = amdgpu_benchmark_do_move(adev, size, saddr, daddr, n);
-   if (r < 0)
+   r = amdgpu_benchmark_do_move(adev, size, saddr, daddr, n, 
&time_ms);
+   if (r)
goto out_cleanup;
-   if (r > 0)
-   amdgpu_benchmark_log_results(adev, n, size, r,
+   else
+   amdgpu_benchmark_log_results(adev, n, size, time_ms,
 sdomain, ddomain, "dma");
}
  

[PATCH v2 7/7] drm/selftests: add drm buddy pathological testcase

[Arunpravin]

create a pot-sized mm, then allocate one of each possible
order within. This should leave the mm with exactly one
page left. Free the largest block, then whittle down again.
Eventually we will have a fully 50% fragmented mm.

v2(Matthew Auld):
  - removed unnecessary test succeeded print
  - replace list_del()/list_add_tail() with list_move_tail()

Signed-off-by: Arunpravin 
Reviewed-by: Matthew Auld 
Acked-by: Christian König 
---
 .../gpu/drm/selftests/drm_buddy_selftests.h   |   1 +
 drivers/gpu/drm/selftests/test-drm_buddy.c| 130 ++
 2 files changed, 131 insertions(+)

diff --git a/drivers/gpu/drm/selftests/drm_buddy_selftests.h 
b/drivers/gpu/drm/selftests/drm_buddy_selftests.h
index 411d072cbfc5..455b756c4ae5 100644
--- a/drivers/gpu/drm/selftests/drm_buddy_selftests.h
+++ b/drivers/gpu/drm/selftests/drm_buddy_selftests.h
@@ -12,3 +12,4 @@ selftest(buddy_alloc_range, igt_buddy_alloc_range)
 selftest(buddy_alloc_optimistic, igt_buddy_alloc_optimistic)
 selftest(buddy_alloc_pessimistic, igt_buddy_alloc_pessimistic)
 selftest(buddy_alloc_smoke, igt_buddy_alloc_smoke)
+selftest(buddy_alloc_pathological, igt_buddy_alloc_pathological)
diff --git a/drivers/gpu/drm/selftests/test-drm_buddy.c 
b/drivers/gpu/drm/selftests/test-drm_buddy.c
index e1cc2353a476..fa997f89522b 100644
--- a/drivers/gpu/drm/selftests/test-drm_buddy.c
+++ b/drivers/gpu/drm/selftests/test-drm_buddy.c
@@ -338,6 +338,136 @@ static void igt_mm_config(u64 *size, u64 *chunk_size)
*size = (u64)s << 12;
 }
 
+static int igt_buddy_alloc_pathological(void *arg)
+{
+   u64 mm_size, size, min_page_size, start = 0;
+   struct drm_buddy_block *block;
+   const int max_order = 3;
+   unsigned long flags = 0;
+   int order, top, err;
+   struct drm_buddy mm;
+   LIST_HEAD(blocks);
+   LIST_HEAD(holes);
+   LIST_HEAD(tmp);
+
+   /*
+* Create a pot-sized mm, then allocate one of each possible
+* order within. This should leave the mm with exactly one
+* page left. Free the largest block, then whittle down again.
+* Eventually we will have a fully 50% fragmented mm.
+*/
+
+   mm_size = PAGE_SIZE << max_order;
+   err = drm_buddy_init(&mm, mm_size, PAGE_SIZE);
+   if (err) {
+   pr_err("buddy_init failed(%d)\n", err);
+   return err;
+   }
+   BUG_ON(mm.max_order != max_order);
+
+   for (top = max_order; top; top--) {
+   /* Make room by freeing the largest allocated block */
+   block = list_first_entry_or_null(&blocks, typeof(*block), link);
+   if (block) {
+   list_del(&block->link);
+   drm_buddy_free_block(&mm, block);
+   }
+
+   for (order = top; order--; ) {
+   size = min_page_size = get_size(order, PAGE_SIZE);
+   err = drm_buddy_alloc_blocks(&mm, start, mm_size, size,
+min_page_size, &tmp, 
flags);
+   if (err) {
+   pr_info("buddy_alloc hit -ENOMEM with order=%d, 
top=%d\n",
+   order, top);
+   goto err;
+   }
+
+   block = list_first_entry_or_null(&tmp,
+struct drm_buddy_block,
+link);
+   if (!block) {
+   pr_err("alloc_blocks has no blocks\n");
+   err = -EINVAL;
+   goto err;
+   }
+
+   list_move_tail(&block->link, &blocks);
+   }
+
+   /* There should be one final page for this sub-allocation */
+   size = min_page_size = get_size(0, PAGE_SIZE);
+   err = drm_buddy_alloc_blocks(&mm, start, mm_size, size, 
min_page_size, &tmp, flags);
+   if (err) {
+   pr_info("buddy_alloc hit -ENOMEM for hole\n");
+   goto err;
+   }
+
+   block = list_first_entry_or_null(&tmp,
+struct drm_buddy_block,
+link);
+   if (!block) {
+   pr_err("alloc_blocks has no blocks\n");
+   err = -EINVAL;
+   goto err;
+   }
+
+   list_move_tail(&block->link, &holes);
+
+   size = min_page_size = get_size(top, PAGE_SIZE);
+   err = drm_buddy_alloc_blocks(&mm, start, mm_size, size, 
min_page_size, &tmp, flags);
+   if (!err) {
+   pr_info("buddy_alloc unexpectedly succeeded at 
top-order %d/%d, it should be full!",
+   top, max_order

[PATCH v2 6/7] drm/selftests: add drm buddy smoke testcase

[Arunpravin]

- add a test to ascertain that the critical functionalities
  of the program is working fine
- add a timeout helper function

v2:
  - removed unnecessary test succeeded print
  - replace list_del()/list_add_tail() with list_move_tail()

Signed-off-by: Arunpravin 
Reviewed-by: Matthew Auld 
Acked-by: Christian König 
---
 .../gpu/drm/selftests/drm_buddy_selftests.h   |   1 +
 drivers/gpu/drm/selftests/test-drm_buddy.c| 139 ++
 2 files changed, 140 insertions(+)

diff --git a/drivers/gpu/drm/selftests/drm_buddy_selftests.h 
b/drivers/gpu/drm/selftests/drm_buddy_selftests.h
index b14f04a1de19..411d072cbfc5 100644
--- a/drivers/gpu/drm/selftests/drm_buddy_selftests.h
+++ b/drivers/gpu/drm/selftests/drm_buddy_selftests.h
@@ -11,3 +11,4 @@ selftest(buddy_alloc_limit, igt_buddy_alloc_limit)
 selftest(buddy_alloc_range, igt_buddy_alloc_range)
 selftest(buddy_alloc_optimistic, igt_buddy_alloc_optimistic)
 selftest(buddy_alloc_pessimistic, igt_buddy_alloc_pessimistic)
+selftest(buddy_alloc_smoke, igt_buddy_alloc_smoke)
diff --git a/drivers/gpu/drm/selftests/test-drm_buddy.c 
b/drivers/gpu/drm/selftests/test-drm_buddy.c
index 2496113c4868..e1cc2353a476 100644
--- a/drivers/gpu/drm/selftests/test-drm_buddy.c
+++ b/drivers/gpu/drm/selftests/test-drm_buddy.c
@@ -7,6 +7,7 @@
 
 #include 
 #include 
+#include 
 
 #include 
 
@@ -15,6 +16,9 @@
 #define TESTS "drm_buddy_selftests.h"
 #include "drm_selftest.h"
 
+#define IGT_TIMEOUT(name__) \
+   unsigned long name__ = jiffies + MAX_SCHEDULE_TIMEOUT
+
 static unsigned int random_seed;
 
 static inline u64 get_size(int order, u64 chunk_size)
@@ -22,6 +26,26 @@ static inline u64 get_size(int order, u64 chunk_size)
return (1 << order) * chunk_size;
 }
 
+__printf(2, 3)
+static bool __igt_timeout(unsigned long timeout, const char *fmt, ...)
+{
+   va_list va;
+
+   if (!signal_pending(current)) {
+   cond_resched();
+   if (time_before(jiffies, timeout))
+   return false;
+   }
+
+   if (fmt) {
+   va_start(va, fmt);
+   vprintk(fmt, va);
+   va_end(va);
+   }
+
+   return true;
+}
+
 static inline const char *yesno(bool v)
 {
return v ? "yes" : "no";
@@ -314,6 +338,121 @@ static void igt_mm_config(u64 *size, u64 *chunk_size)
*size = (u64)s << 12;
 }
 
+static int igt_buddy_alloc_smoke(void *arg)
+{
+   u64 mm_size, min_page_size, chunk_size, start = 0;
+   unsigned long flags = 0;
+   struct drm_buddy mm;
+   int *order;
+   int err, i;
+
+   DRM_RND_STATE(prng, random_seed);
+   IGT_TIMEOUT(end_time);
+
+   igt_mm_config(&mm_size, &chunk_size);
+
+   err = drm_buddy_init(&mm, mm_size, chunk_size);
+   if (err) {
+   pr_err("buddy_init failed(%d)\n", err);
+   return err;
+   }
+
+   order = drm_random_order(mm.max_order + 1, &prng);
+   if (!order)
+   goto out_fini;
+
+   for (i = 0; i <= mm.max_order; ++i) {
+   struct drm_buddy_block *block;
+   int max_order = order[i];
+   bool timeout = false;
+   LIST_HEAD(blocks);
+   u64 total, size;
+   LIST_HEAD(tmp);
+   int order;
+
+   err = igt_check_mm(&mm);
+   if (err) {
+   pr_err("pre-mm check failed, abort\n");
+   break;
+   }
+
+   order = max_order;
+   total = 0;
+
+   do {
+retry:
+   size = min_page_size = get_size(order, chunk_size);
+   err = drm_buddy_alloc_blocks(&mm, start, mm_size, size,
+min_page_size, &tmp, 
flags);
+   if (err) {
+   if (err == -ENOMEM) {
+   pr_info("buddy_alloc hit -ENOMEM with 
order=%d\n",
+   order);
+   } else {
+   if (order--) {
+   err = 0;
+   goto retry;
+   }
+
+   pr_err("buddy_alloc with order=%d 
failed(%d)\n",
+  order, err);
+   }
+
+   break;
+   }
+
+   block = list_first_entry_or_null(&tmp,
+struct drm_buddy_block,
+link);
+   if (!block) {
+   pr_err("alloc_blocks has no blocks\n");
+   err = -EINVAL;
+   break;
+   }
+
+  

[PATCH v2 5/7] drm/selftests: add drm buddy pessimistic testcase

[Arunpravin]

create a pot-sized mm, then allocate one of each possible
order within. This should leave the mm with exactly one
page left.

v2:
  - removed unnecessary test succeeded print
  - replace list_del()/list_add_tail() with list_move_tail()

Signed-off-by: Arunpravin 
Reviewed-by: Matthew Auld 
Acked-by: Christian König 
---
 .../gpu/drm/selftests/drm_buddy_selftests.h   |   1 +
 drivers/gpu/drm/selftests/test-drm_buddy.c| 147 ++
 2 files changed, 148 insertions(+)

diff --git a/drivers/gpu/drm/selftests/drm_buddy_selftests.h 
b/drivers/gpu/drm/selftests/drm_buddy_selftests.h
index 21a6bd38864f..b14f04a1de19 100644
--- a/drivers/gpu/drm/selftests/drm_buddy_selftests.h
+++ b/drivers/gpu/drm/selftests/drm_buddy_selftests.h
@@ -10,3 +10,4 @@ selftest(sanitycheck, igt_sanitycheck) /* keep first 
(selfcheck for igt) */
 selftest(buddy_alloc_limit, igt_buddy_alloc_limit)
 selftest(buddy_alloc_range, igt_buddy_alloc_range)
 selftest(buddy_alloc_optimistic, igt_buddy_alloc_optimistic)
+selftest(buddy_alloc_pessimistic, igt_buddy_alloc_pessimistic)
diff --git a/drivers/gpu/drm/selftests/test-drm_buddy.c 
b/drivers/gpu/drm/selftests/test-drm_buddy.c
index f20d3ad1ac65..2496113c4868 100644
--- a/drivers/gpu/drm/selftests/test-drm_buddy.c
+++ b/drivers/gpu/drm/selftests/test-drm_buddy.c
@@ -314,6 +314,153 @@ static void igt_mm_config(u64 *size, u64 *chunk_size)
*size = (u64)s << 12;
 }
 
+static int igt_buddy_alloc_pessimistic(void *arg)
+{
+   u64 mm_size, size, min_page_size, start = 0;
+   struct drm_buddy_block *block, *bn;
+   const unsigned int max_order = 16;
+   unsigned long flags = 0;
+   struct drm_buddy mm;
+   unsigned int order;
+   LIST_HEAD(blocks);
+   LIST_HEAD(tmp);
+   int err;
+
+   /*
+* Create a pot-sized mm, then allocate one of each possible
+* order within. This should leave the mm with exactly one
+* page left.
+*/
+
+   mm_size = PAGE_SIZE << max_order;
+   err = drm_buddy_init(&mm, mm_size, PAGE_SIZE);
+   if (err) {
+   pr_err("buddy_init failed(%d)\n", err);
+   return err;
+   }
+   BUG_ON(mm.max_order != max_order);
+
+   for (order = 0; order < max_order; order++) {
+   size = min_page_size = get_size(order, PAGE_SIZE);
+   err = drm_buddy_alloc_blocks(&mm, start, mm_size, size, 
min_page_size, &tmp, flags);
+   if (err) {
+   pr_info("buddy_alloc hit -ENOMEM with order=%d\n",
+   order);
+   goto err;
+   }
+
+   block = list_first_entry_or_null(&tmp,
+struct drm_buddy_block,
+link);
+   if (!block) {
+   pr_err("alloc_blocks has no blocks\n");
+   err = -EINVAL;
+   goto err;
+   }
+
+   list_move_tail(&block->link, &blocks);
+   }
+
+   /* And now the last remaining block available */
+   size = min_page_size = get_size(0, PAGE_SIZE);
+   err = drm_buddy_alloc_blocks(&mm, start, mm_size, size, min_page_size, 
&tmp, flags);
+   if (err) {
+   pr_info("buddy_alloc hit -ENOMEM on final alloc\n");
+   goto err;
+   }
+
+   block = list_first_entry_or_null(&tmp,
+struct drm_buddy_block,
+link);
+   if (!block) {
+   pr_err("alloc_blocks has no blocks\n");
+   err = -EINVAL;
+   goto err;
+   }
+
+   list_move_tail(&block->link, &blocks);
+
+   /* Should be completely full! */
+   for (order = max_order; order--; ) {
+   size = min_page_size = get_size(order, PAGE_SIZE);
+   err = drm_buddy_alloc_blocks(&mm, start, mm_size, size, 
min_page_size, &tmp, flags);
+   if (!err) {
+   pr_info("buddy_alloc unexpectedly succeeded at order 
%d, it should be full!",
+   order);
+   block = list_first_entry_or_null(&tmp,
+struct drm_buddy_block,
+link);
+   if (!block) {
+   pr_err("alloc_blocks has no blocks\n");
+   err = -EINVAL;
+   goto err;
+   }
+
+   list_move_tail(&block->link, &blocks);
+   err = -EINVAL;
+   goto err;
+   }
+   }
+
+   block = list_last_entry(&blocks, typeof(*block), link);
+   list_del(&block->link);
+   drm_buddy_free_block(&mm, block);
+
+   /* As we free in increasing size, we make available larger blocks

[PATCH v2 4/7] drm/selftests: add drm buddy optimistic testcase

[Arunpravin]

create a mm with one block of each order available, and
try to allocate them all.

v2(Matthew Auld):
  - removed unnecessary test succeeded print
  - replace list_del()/list_add_tail() with list_move_tail()

Signed-off-by: Arunpravin 
Reviewed-by: Matthew Auld 
Acked-by: Christian König 
---
 .../gpu/drm/selftests/drm_buddy_selftests.h   |  1 +
 drivers/gpu/drm/selftests/test-drm_buddy.c| 80 +++
 2 files changed, 81 insertions(+)

diff --git a/drivers/gpu/drm/selftests/drm_buddy_selftests.h 
b/drivers/gpu/drm/selftests/drm_buddy_selftests.h
index 3230bfd2770b..21a6bd38864f 100644
--- a/drivers/gpu/drm/selftests/drm_buddy_selftests.h
+++ b/drivers/gpu/drm/selftests/drm_buddy_selftests.h
@@ -9,3 +9,4 @@
 selftest(sanitycheck, igt_sanitycheck) /* keep first (selfcheck for igt) */
 selftest(buddy_alloc_limit, igt_buddy_alloc_limit)
 selftest(buddy_alloc_range, igt_buddy_alloc_range)
+selftest(buddy_alloc_optimistic, igt_buddy_alloc_optimistic)
diff --git a/drivers/gpu/drm/selftests/test-drm_buddy.c 
b/drivers/gpu/drm/selftests/test-drm_buddy.c
index 586e0673a67c..f20d3ad1ac65 100644
--- a/drivers/gpu/drm/selftests/test-drm_buddy.c
+++ b/drivers/gpu/drm/selftests/test-drm_buddy.c
@@ -17,6 +17,11 @@
 
 static unsigned int random_seed;
 
+static inline u64 get_size(int order, u64 chunk_size)
+{
+   return (1 << order) * chunk_size;
+}
+
 static inline const char *yesno(bool v)
 {
return v ? "yes" : "no";
@@ -309,6 +314,81 @@ static void igt_mm_config(u64 *size, u64 *chunk_size)
*size = (u64)s << 12;
 }
 
+static int igt_buddy_alloc_optimistic(void *arg)
+{
+   u64 mm_size, size, min_page_size, start = 0;
+   struct drm_buddy_block *block;
+   unsigned long flags = 0;
+   const int max_order = 16;
+   struct drm_buddy mm;
+   LIST_HEAD(blocks);
+   LIST_HEAD(tmp);
+   int order, err;
+
+   /*
+* Create a mm with one block of each order available, and
+* try to allocate them all.
+*/
+
+   mm_size = PAGE_SIZE * ((1 << (max_order + 1)) - 1);
+   err = drm_buddy_init(&mm,
+mm_size,
+PAGE_SIZE);
+   if (err) {
+   pr_err("buddy_init failed(%d)\n", err);
+   return err;
+   }
+
+   BUG_ON(mm.max_order != max_order);
+
+   for (order = 0; order <= max_order; order++) {
+   size = min_page_size = get_size(order, PAGE_SIZE);
+   err = drm_buddy_alloc_blocks(&mm, start, mm_size, size, 
min_page_size, &tmp, flags);
+   if (err) {
+   pr_info("buddy_alloc hit -ENOMEM with order=%d\n",
+   order);
+   goto err;
+   }
+
+   block = list_first_entry_or_null(&tmp,
+struct drm_buddy_block,
+link);
+   if (!block) {
+   pr_err("alloc_blocks has no blocks\n");
+   err = -EINVAL;
+   goto err;
+   }
+
+   list_move_tail(&block->link, &blocks);
+   }
+
+   /* Should be completely full! */
+   size = min_page_size = get_size(0, PAGE_SIZE);
+   err = drm_buddy_alloc_blocks(&mm, start, mm_size, size, min_page_size, 
&tmp, flags);
+   if (!err) {
+   pr_info("buddy_alloc unexpectedly succeeded, it should be 
full!");
+   block = list_first_entry_or_null(&tmp,
+struct drm_buddy_block,
+link);
+   if (!block) {
+   pr_err("alloc_blocks has no blocks\n");
+   err = -EINVAL;
+   goto err;
+   }
+
+   list_move_tail(&block->link, &blocks);
+   err = -EINVAL;
+   goto err;
+   } else {
+   err = 0;
+   }
+
+err:
+   drm_buddy_free_list(&mm, &blocks);
+   drm_buddy_fini(&mm);
+   return err;
+}
+
 static int igt_buddy_alloc_range(void *arg)
 {
unsigned long flags = DRM_BUDDY_RANGE_ALLOCATION;
-- 
2.25.1

[PATCH v2 2/7] drm/selftests: add drm buddy alloc limit testcase

[Arunpravin]

add a test to check the maximum allocation limit

v2(Matthew Auld):
  - added err = -EINVAL in block NULL check
  - removed unnecessary test succeeded print

Signed-off-by: Arunpravin 
Reviewed-by: Matthew Auld 
Acked-by: Christian König 
---
 .../gpu/drm/selftests/drm_buddy_selftests.h   |  1 +
 drivers/gpu/drm/selftests/test-drm_buddy.c| 59 +++
 2 files changed, 60 insertions(+)

diff --git a/drivers/gpu/drm/selftests/drm_buddy_selftests.h 
b/drivers/gpu/drm/selftests/drm_buddy_selftests.h
index a4bcf3a6dfe3..ebe16162762f 100644
--- a/drivers/gpu/drm/selftests/drm_buddy_selftests.h
+++ b/drivers/gpu/drm/selftests/drm_buddy_selftests.h
@@ -7,3 +7,4 @@
  * Tests are executed in order by igt/drm_buddy
  */
 selftest(sanitycheck, igt_sanitycheck) /* keep first (selfcheck for igt) */
+selftest(buddy_alloc_limit, igt_buddy_alloc_limit)
diff --git a/drivers/gpu/drm/selftests/test-drm_buddy.c 
b/drivers/gpu/drm/selftests/test-drm_buddy.c
index 51e4d393d22c..0df41e1cb8a6 100644
--- a/drivers/gpu/drm/selftests/test-drm_buddy.c
+++ b/drivers/gpu/drm/selftests/test-drm_buddy.c
@@ -16,6 +16,65 @@
 
 static unsigned int random_seed;
 
+static int igt_buddy_alloc_limit(void *arg)
+{
+   u64 end, size = U64_MAX, start = 0;
+   struct drm_buddy_block *block;
+   unsigned long flags = 0;
+   LIST_HEAD(allocated);
+   struct drm_buddy mm;
+   int err;
+
+   size = end = round_down(size, 4096);
+   err = drm_buddy_init(&mm, size, PAGE_SIZE);
+   if (err)
+   return err;
+
+   if (mm.max_order != DRM_BUDDY_MAX_ORDER) {
+   pr_err("mm.max_order(%d) != %d\n",
+  mm.max_order, DRM_BUDDY_MAX_ORDER);
+   err = -EINVAL;
+   goto out_fini;
+   }
+
+   err = drm_buddy_alloc_blocks(&mm, start, end, size,
+PAGE_SIZE, &allocated, flags);
+
+   if (unlikely(err))
+   goto out_free;
+
+   block = list_first_entry_or_null(&allocated,
+struct drm_buddy_block,
+link);
+
+   if (!block) {
+   err = -EINVAL;
+   goto out_fini;
+   }
+
+   if (drm_buddy_block_order(block) != mm.max_order) {
+   pr_err("block order(%d) != %d\n",
+  drm_buddy_block_order(block), mm.max_order);
+   err = -EINVAL;
+   goto out_free;
+   }
+
+   if (drm_buddy_block_size(&mm, block) !=
+   BIT_ULL(mm.max_order) * PAGE_SIZE) {
+   pr_err("block size(%llu) != %llu\n",
+  drm_buddy_block_size(&mm, block),
+  BIT_ULL(mm.max_order) * PAGE_SIZE);
+   err = -EINVAL;
+   goto out_free;
+   }
+
+out_free:
+   drm_buddy_free_list(&mm, &allocated);
+out_fini:
+   drm_buddy_fini(&mm);
+   return err;
+}
+
 static int igt_sanitycheck(void *ignored)
 {
pr_info("%s - ok!\n", __func__);
-- 
2.25.1

[PATCH v2 3/7] drm/selftests: add drm buddy alloc range testcase

[Arunpravin]

- add a test to check the range allocation
- export get_buddy() function in drm_buddy.c
- export drm_prandom_u32_max_state() in lib/drm_random.c
- include helper functions
- include prime number header file

v2:
  - add drm_get_buddy() function description (Matthew Auld)
  - removed unnecessary test succeeded print

Signed-off-by: Arunpravin 
Reviewed-by: Matthew Auld 
Acked-by: Christian König 
---
 drivers/gpu/drm/drm_buddy.c   |  25 +-
 drivers/gpu/drm/lib/drm_random.c  |   3 +-
 drivers/gpu/drm/lib/drm_random.h  |   2 +
 .../gpu/drm/selftests/drm_buddy_selftests.h   |   1 +
 drivers/gpu/drm/selftests/test-drm_buddy.c| 388 ++
 include/drm/drm_buddy.h   |   3 +
 6 files changed, 417 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/drm_buddy.c b/drivers/gpu/drm/drm_buddy.c
index edef30be8304..72f52f293249 100644
--- a/drivers/gpu/drm/drm_buddy.c
+++ b/drivers/gpu/drm/drm_buddy.c
@@ -211,7 +211,7 @@ static int split_block(struct drm_buddy *mm,
 }
 
 static struct drm_buddy_block *
-get_buddy(struct drm_buddy_block *block)
+__get_buddy(struct drm_buddy_block *block)
 {
struct drm_buddy_block *parent;
 
@@ -225,6 +225,23 @@ get_buddy(struct drm_buddy_block *block)
return parent->left;
 }
 
+/**
+ * drm_get_buddy - get buddy address
+ *
+ * @block: DRM buddy block
+ *
+ * Returns the corresponding buddy block for @block, or NULL
+ * if this is a root block and can't be merged further.
+ * Requires some kind of locking to protect against
+ * any concurrent allocate and free operations.
+ */
+struct drm_buddy_block *
+drm_get_buddy(struct drm_buddy_block *block)
+{
+   return __get_buddy(block);
+}
+EXPORT_SYMBOL(drm_get_buddy);
+
 static void __drm_buddy_free(struct drm_buddy *mm,
 struct drm_buddy_block *block)
 {
@@ -233,7 +250,7 @@ static void __drm_buddy_free(struct drm_buddy *mm,
while ((parent = block->parent)) {
struct drm_buddy_block *buddy;
 
-   buddy = get_buddy(block);
+   buddy = __get_buddy(block);
 
if (!drm_buddy_block_is_free(buddy))
break;
@@ -361,7 +378,7 @@ alloc_range_bias(struct drm_buddy *mm,
 * bigger is better, so make sure we merge everything back before we
 * free the allocated blocks.
 */
-   buddy = get_buddy(block);
+   buddy = __get_buddy(block);
if (buddy &&
(drm_buddy_block_is_free(block) &&
 drm_buddy_block_is_free(buddy)))
@@ -500,7 +517,7 @@ static int __alloc_range(struct drm_buddy *mm,
 * bigger is better, so make sure we merge everything back before we
 * free the allocated blocks.
 */
-   buddy = get_buddy(block);
+   buddy = __get_buddy(block);
if (buddy &&
(drm_buddy_block_is_free(block) &&
 drm_buddy_block_is_free(buddy)))
diff --git a/drivers/gpu/drm/lib/drm_random.c b/drivers/gpu/drm/lib/drm_random.c
index eeb155826d27..31b5a3e21911 100644
--- a/drivers/gpu/drm/lib/drm_random.c
+++ b/drivers/gpu/drm/lib/drm_random.c
@@ -7,10 +7,11 @@
 
 #include "drm_random.h"
 
-static inline u32 drm_prandom_u32_max_state(u32 ep_ro, struct rnd_state *state)
+u32 drm_prandom_u32_max_state(u32 ep_ro, struct rnd_state *state)
 {
return upper_32_bits((u64)prandom_u32_state(state) * ep_ro);
 }
+EXPORT_SYMBOL(drm_prandom_u32_max_state);
 
 void drm_random_reorder(unsigned int *order, unsigned int count,
struct rnd_state *state)
diff --git a/drivers/gpu/drm/lib/drm_random.h b/drivers/gpu/drm/lib/drm_random.h
index 4a3e94dfa0c0..5543bf0474bc 100644
--- a/drivers/gpu/drm/lib/drm_random.h
+++ b/drivers/gpu/drm/lib/drm_random.h
@@ -22,5 +22,7 @@ unsigned int *drm_random_order(unsigned int count,
 void drm_random_reorder(unsigned int *order,
unsigned int count,
struct rnd_state *state);
+u32 drm_prandom_u32_max_state(u32 ep_ro,
+ struct rnd_state *state);
 
 #endif /* !__DRM_RANDOM_H__ */
diff --git a/drivers/gpu/drm/selftests/drm_buddy_selftests.h 
b/drivers/gpu/drm/selftests/drm_buddy_selftests.h
index ebe16162762f..3230bfd2770b 100644
--- a/drivers/gpu/drm/selftests/drm_buddy_selftests.h
+++ b/drivers/gpu/drm/selftests/drm_buddy_selftests.h
@@ -8,3 +8,4 @@
  */
 selftest(sanitycheck, igt_sanitycheck) /* keep first (selfcheck for igt) */
 selftest(buddy_alloc_limit, igt_buddy_alloc_limit)
+selftest(buddy_alloc_range, igt_buddy_alloc_range)
diff --git a/drivers/gpu/drm/selftests/test-drm_buddy.c 
b/drivers/gpu/drm/selftests/test-drm_buddy.c
index 0df41e1cb8a6..586e0673a67c 100644
--- a/drivers/gpu/drm/selftests/test-drm_buddy.c
+++ b/drivers/gpu/drm/selftests/test-drm_buddy.c
@@ -6,6 +6,7 @@
 #define pr_fmt(fmt) "drm_buddy: " fmt
 
 #include 
+#include 
 
 #include 
 
@@ -16,6 +17,393 @@
 
 static unsigned int random_seed;
 
+static inlin

[PATCH v2 1/7] drm/selftests: Move i915 buddy selftests into drm

[Arunpravin]

- move i915 buddy selftests into drm selftests folder
- add Makefile and Kconfig support
- add sanitycheck testcase

Prerequisites
- These series of selftests patches are created on top of
  drm buddy series
- Enable kselftests for DRM as a module in .config

Signed-off-by: Arunpravin 
Acked-by: Christian König 
Acked-by: Matthew Auld 
---
 drivers/gpu/drm/Kconfig   |  1 +
 drivers/gpu/drm/selftests/Makefile|  3 +-
 .../gpu/drm/selftests/drm_buddy_selftests.h   |  9 
 drivers/gpu/drm/selftests/test-drm_buddy.c| 49 +++
 4 files changed, 61 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/selftests/drm_buddy_selftests.h
 create mode 100644 drivers/gpu/drm/selftests/test-drm_buddy.c

diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index 763355330b17..f1422bee3dcc 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -71,6 +71,7 @@ config DRM_DEBUG_SELFTEST
select DRM_DP_HELPER
select DRM_LIB_RANDOM
select DRM_KMS_HELPER
+   select DRM_BUDDY
select DRM_EXPORT_FOR_TESTS if m
default n
help
diff --git a/drivers/gpu/drm/selftests/Makefile 
b/drivers/gpu/drm/selftests/Makefile
index 0856e4b12f70..5ba5f9138c95 100644
--- a/drivers/gpu/drm/selftests/Makefile
+++ b/drivers/gpu/drm/selftests/Makefile
@@ -4,4 +4,5 @@ test-drm_modeset-y := test-drm_modeset_common.o 
test-drm_plane_helper.o \
  test-drm_damage_helper.o test-drm_dp_mst_helper.o \
  test-drm_rect.o
 
-obj-$(CONFIG_DRM_DEBUG_SELFTEST) += test-drm_mm.o test-drm_modeset.o 
test-drm_cmdline_parser.o
+obj-$(CONFIG_DRM_DEBUG_SELFTEST) += test-drm_mm.o test-drm_modeset.o 
test-drm_cmdline_parser.o \
+   test-drm_buddy.o
diff --git a/drivers/gpu/drm/selftests/drm_buddy_selftests.h 
b/drivers/gpu/drm/selftests/drm_buddy_selftests.h
new file mode 100644
index ..a4bcf3a6dfe3
--- /dev/null
+++ b/drivers/gpu/drm/selftests/drm_buddy_selftests.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* List each unit test as selftest(name, function)
+ *
+ * The name is used as both an enum and expanded as igt__name to create
+ * a module parameter. It must be unique and legal for a C identifier.
+ *
+ * Tests are executed in order by igt/drm_buddy
+ */
+selftest(sanitycheck, igt_sanitycheck) /* keep first (selfcheck for igt) */
diff --git a/drivers/gpu/drm/selftests/test-drm_buddy.c 
b/drivers/gpu/drm/selftests/test-drm_buddy.c
new file mode 100644
index ..51e4d393d22c
--- /dev/null
+++ b/drivers/gpu/drm/selftests/test-drm_buddy.c
@@ -0,0 +1,49 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2019 Intel Corporation
+ */
+
+#define pr_fmt(fmt) "drm_buddy: " fmt
+
+#include 
+
+#include 
+
+#include "../lib/drm_random.h"
+
+#define TESTS "drm_buddy_selftests.h"
+#include "drm_selftest.h"
+
+static unsigned int random_seed;
+
+static int igt_sanitycheck(void *ignored)
+{
+   pr_info("%s - ok!\n", __func__);
+   return 0;
+}
+
+#include "drm_selftest.c"
+
+static int __init test_drm_buddy_init(void)
+{
+   int err;
+
+   while (!random_seed)
+   random_seed = get_random_int();
+
+   pr_info("Testing DRM buddy manager (struct drm_buddy), with 
random_seed=0x%x\n",
+   random_seed);
+   err = run_selftests(selftests, ARRAY_SIZE(selftests), NULL);
+
+   return err > 0 ? 0 : err;
+}
+
+static void __exit test_drm_buddy_exit(void)
+{
+}
+
+module_init(test_drm_buddy_init);
+module_exit(test_drm_buddy_exit);
+
+MODULE_AUTHOR("Intel Corporation");
+MODULE_LICENSE("GPL");

base-commit: 95ee2a8b4b3cd1fb25f7e14e2202da4045030173
-- 
2.25.1

Re: [PATCH v11 2/2] drm/amdgpu: add reset register dump trace on GPU

[Andrey Grodzovsky]

Reviewed-by: Andrey Grodzovsky 

Andrey

On 2022-02-22 09:37, Somalapuram Amaranath wrote:

Dump the list of register values to trace event on GPU reset.

Signed-off-by: Somalapuram Amaranath 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 17 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h  | 16 
  2 files changed, 33 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 1e651b959141..7c48fd716adb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -4534,6 +4534,22 @@ int amdgpu_device_pre_asic_reset(struct amdgpu_device 
*adev,
return r;
  }
  
+static int amdgpu_reset_reg_dumps(struct amdgpu_device *adev)

+{
+   uint32_t reg_value;
+   int i;
+
+   lockdep_assert_held(&adev->reset_sem);
+   dump_stack();
+
+   for (i = 0; i < adev->num_regs; i++) {
+   reg_value = RREG32(adev->reset_dump_reg_list[i]);
+   trace_amdgpu_reset_reg_dumps(adev->reset_dump_reg_list[i], 
reg_value);
+   }
+
+   return 0;
+}
+
  int amdgpu_do_asic_reset(struct list_head *device_list_handle,
 struct amdgpu_reset_context *reset_context)
  {
@@ -4544,6 +4560,7 @@ int amdgpu_do_asic_reset(struct list_head 
*device_list_handle,
/* Try reset handler method first */
tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,
reset_list);
+   amdgpu_reset_reg_dumps(tmp_adev);
r = amdgpu_reset_perform_reset(tmp_adev, reset_context);
/* If reset handler not implemented, continue; otherwise return */
if (r == -ENOSYS)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
index d855cb53c7e0..b9637925e85c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
@@ -537,6 +537,22 @@ TRACE_EVENT(amdgpu_ib_pipe_sync,
  __entry->seqno)
  );
  
+TRACE_EVENT(amdgpu_reset_reg_dumps,

+   TP_PROTO(uint32_t address, uint32_t value),
+   TP_ARGS(address, value),
+   TP_STRUCT__entry(
+__field(uint32_t, address)
+__field(uint32_t, value)
+),
+   TP_fast_assign(
+  __entry->address = address;
+  __entry->value = value;
+  ),
+   TP_printk("amdgpu register dump 0x%x: 0x%x",
+ __entry->address,
+ __entry->value)
+);
+
  #undef AMDGPU_JOB_GET_TIMELINE_NAME
  #endif
  

Re: [PATCH] drm/amdgpu: limit harvest bit read on several ASICs

[Alex Deucher]

On Tue, Feb 22, 2022 at 10:07 AM Guchun Chen  wrote:
>
> Due to faulty VBIOS out there, harvest bit setting is not
> consistently correct especially for display IP. So far,
> it's hard to work out a solution on all the legacy Navi1x
> ASICs in a short time, so to avoid regression, limit harvest
> bit read on several ASICs. Will revisit later once VBIOS has
> corrected it in long term.
>

Looks like it may be incorrect for VCN as well.  Double check that.

Alex


> Fixes: b3f4ea887d5f("drm/amdgpu: read harvest bit per IP data on legacy GPUs")
> Signed-off-by: Guchun Chen 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 18 +-
>  1 file changed, 13 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> index 11255290f117..2e0ff1ace6fc 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> @@ -1129,12 +1129,20 @@ void amdgpu_discovery_harvest_ip(struct amdgpu_device 
> *adev)
>  * so read harvest bit per IP data structure to set
>  * harvest configuration.
>  */
> -   if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 2, 0))
> -   amdgpu_discovery_read_harvest_bit_per_ip(adev,
> -   &vcn_harvest_count);
> -   else
> +   if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 2, 0)) {
> +   if ((adev->pdev->device == 0x731E &&
> +   (adev->pdev->revision == 0xC6 ||
> +adev->pdev->revision == 0xC7)) ||
> +   (adev->pdev->device == 0x7340 &&
> +adev->pdev->revision == 0xC9) ||
> +   (adev->pdev->device == 0x7360 &&
> +adev->pdev->revision == 0xC7))
> +   amdgpu_discovery_read_harvest_bit_per_ip(adev,
> +   &vcn_harvest_count);
> +   } else {
> amdgpu_disocvery_read_from_harvest_table(adev,
> -   &vcn_harvest_count);
> +   &vcn_harvest_count);
> +   }
>
> amdgpu_discovery_harvest_config_quirk(adev);
>
> --
> 2.17.1
>

Re: [PATCH 10/10] drm/amd/display: Turn global functions into static functions

[Alex Deucher]

On Tue, Feb 22, 2022 at 8:18 AM Maíra Canal  wrote:
>
> Turn previously global functions into static functions to avoid
> -Wmissing-prototype warnings, such as:
>
> drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn30/irq_service_dcn30.c:50:20:
> warning: no previous prototype for function 'to_dal_irq_source_dcn30'
> [-Wmissing-prototypes]
> enum dc_irq_source to_dal_irq_source_dcn30(
>^
> drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn30/irq_service_dcn30.c:50:1:
> note: declare 'static' if the function is not intended to be used outside
> of this translation unit
> enum dc_irq_source to_dal_irq_source_dcn30(
> ^
> static
> 1 warning generated.
>
> drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c:488:6:
> warning: no previous prototype for function
> 'dcn316_clk_mgr_helper_populate_bw_params' [-Wmissing-prototypes]
> void dcn316_clk_mgr_helper_populate_bw_params(
>  ^
> drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c:488:1:
> note: declare 'static' if the function is not intended to be used outside
> of this translation unit
> void dcn316_clk_mgr_helper_populate_bw_params(
> ^
> static
> 1 warning generated.
>
> Signed-off-by: Maíra Canal 
> ---
>  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++--
>  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c   | 2 +-
>  .../drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c  | 3 ++-
>  .../gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c| 2 +-
>  drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c| 2 +-
>  drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 2 +-
>  drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c  | 2 +-
>  drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c  | 2 +-
>  8 files changed, 10 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index c9ca328d34e3..a99b92526b55 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -6362,7 +6362,7 @@ static bool is_freesync_video_mode(const struct 
> drm_display_mode *mode,
> return true;
>  }
>
> -struct dc_stream_state *
> +static struct dc_stream_state *
>  create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
>const struct drm_display_mode *drm_mode,
>const struct dm_connector_state *dm_state,
> @@ -10189,7 +10189,7 @@ static void set_freesync_fixed_config(struct 
> dm_crtc_state *dm_new_crtc_state) {
> dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res;
>  }
>
> -int dm_update_crtc_state(struct amdgpu_display_manager *dm,
> +static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
>  struct drm_atomic_state *state,
>  struct drm_crtc *crtc,
>  struct drm_crtc_state *old_crtc_state,
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c 
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> index 389b0cb37995..05573f073b21 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> @@ -213,7 +213,7 @@ static bool validate_dsc_caps_on_connector(struct 
> amdgpu_dm_connector *aconnecto
> return true;
>  }
>
> -bool retrieve_downstream_port_device(struct amdgpu_dm_connector *aconnector)
> +static bool retrieve_downstream_port_device(struct amdgpu_dm_connector 
> *aconnector)
>  {
> union dp_downstream_port_present ds_port_present;
>
> diff --git 
> a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c 
> b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c
> index 06bab24d8e27..450eaead4f20 100644
> --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c
> +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c
> @@ -101,7 +101,8 @@ static uint32_t rv1_smu_wait_for_response(struct 
> clk_mgr_internal *clk_mgr, unsi
> return res_val;
>  }
>
> -int rv1_vbios_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, 
> unsigned int msg_id, unsigned int param)
> +static int rv1_vbios_smu_send_msg_with_param(struct clk_mgr_internal 
> *clk_mgr,
> +   unsigned int msg_id, unsigned int param)
>  {
> uint32_t result;
>
> diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c 
> b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
> index ffd3d5cb9871..02a59adff90d 100644
> --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
> +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
> @@ -485,7 +485,7 @@ static unsigned int find_clk_for_voltage(
> return clock;
>  }
>
> -void dcn316_clk_mgr_helper_populate_bw_p

Re: [PATCH 09/10] drm/amd/display: Add missing prototypes to dcn201_init

[Alex Deucher]

Applied.  Thanks!

On Tue, Feb 22, 2022 at 8:18 AM Maíra Canal  wrote:
>
> Include the header with the prototype to silence the following clang
> warning:
>
> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_init.c:127:6:
> warning: no previous prototype for function 'dcn201_hw_sequencer_construct'
> [-Wmissing-prototypes]
> void dcn201_hw_sequencer_construct(struct dc *dc)
>  ^
>
> Signed-off-by: Maíra Canal 
> ---
>  drivers/gpu/drm/amd/display/dc/dcn201/dcn201_init.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_init.c 
> b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_init.c
> index f1f89f93603f..1826dd7f3da1 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_init.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_init.c
> @@ -27,6 +27,7 @@
>  #include "dcn10/dcn10_hw_sequencer.h"
>  #include "dcn20/dcn20_hwseq.h"
>  #include "dcn201_hwseq.h"
> +#include "dcn201_init.h"
>
>  static const struct hw_sequencer_funcs dcn201_funcs = {
> .program_gamut_remap = dcn10_program_gamut_remap,
> --
> 2.35.1
>

Re: [PATCH 08/10] drm/amd/display: Remove unused variable

[Alex Deucher]

Applied.  Thanks!

On Tue, Feb 22, 2022 at 8:18 AM Maíra Canal  wrote:
>
> Remove the variable clamshell_closed from the function
> dcn10_align_pixel_clocks.
>
> This was pointed by clang with the following warning:
>
> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:2063:7:
> warning: variable 'clamshell_closed' set but not used
> [-Wunused-but-set-variable]
> bool clamshell_closed = false;
>  ^
>
> Signed-off-by: Maíra Canal 
> ---
>  drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 3 ---
>  1 file changed, 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
> b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
> index 8dc1afc03961..559aa45f27e7 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
> @@ -2060,14 +2060,11 @@ static int dcn10_align_pixel_clocks(struct dc *dc, 
> int group_size,
> uint32_t embedded_pix_clk_100hz;
> uint16_t embedded_h_total;
> uint16_t embedded_v_total;
> -   bool clamshell_closed = false;
> uint32_t dp_ref_clk_100hz =
> 
> dc->res_pool->dp_clock_source->ctx->dc->clk_mgr->dprefclk_khz*10;
>
> if (dc->config.vblank_alignment_dto_params &&
> dc->res_pool->dp_clock_source->funcs->override_dp_pix_clk) {
> -   clamshell_closed =
> -   (dc->config.vblank_alignment_dto_params >> 63);
> embedded_h_total =
> (dc->config.vblank_alignment_dto_params >> 32) & 
> 0x7FFF;
> embedded_v_total =
> --
> 2.35.1
>

Re: [PATCH 07/10] drm/amd/display: Remove unused dmub_outbox_irq_info_funcs variable

[Alex Deucher]

Applied.  Thanks!

Alex

On Tue, Feb 22, 2022 at 8:18 AM Maíra Canal  wrote:
>
> Remove the unused struct irq_source_info_funcs
> dmub_outbox_irq_info_funcs from the file, which was declared but never
> hooked up.
>
> This was pointed by clang with the following warning:
>
> drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn201/irq_service_dcn201.c:141:43:
> warning: unused variable 'dmub_outbox_irq_info_funcs'
> [-Wunused-const-variable]
> static const struct irq_source_info_funcs dmub_outbox_irq_info_funcs = {
>   ^
>
> Signed-off-by: Maíra Canal 
> ---
>  .../gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c   | 5 -
>  1 file changed, 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c 
> b/drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c
> index aa708b61142f..45f99351a0ab 100644
> --- a/drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c
> +++ b/drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c
> @@ -138,11 +138,6 @@ static const struct irq_source_info_funcs 
> vupdate_no_lock_irq_info_funcs = {
> .ack = NULL
>  };
>
> -static const struct irq_source_info_funcs dmub_outbox_irq_info_funcs = {
> -   .set = NULL,
> -   .ack = NULL
> -};
> -
>  #undef BASE_INNER
>  #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
>
> --
> 2.35.1
>

Re: [PATCH 06/10] drm/amd/display: Remove vupdate_int_entry definition

[Alex Deucher]

Applied.  Thanks!

Alex

On Tue, Feb 22, 2022 at 8:18 AM Maíra Canal  wrote:
>
> Remove the vupdate_int_entry definition and utilization to avoid the
> following warning by Clang:
>
> drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:410:2:
> warning: initializer overrides prior initialization of this subobject
> [-Winitializer-overrides]
> vupdate_no_lock_int_entry(0),
> ^~~~
> drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:280:39:
> note: expanded from macro 'vupdate_no_lock_int_entry'
> [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
> ^~
> drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:404:2:
> note: previous initialization is here
> vupdate_int_entry(0),
> ^~~~
> drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:269:39:
> note: expanded from macro 'vupdate_int_entry'
> [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
> ^~
> drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:411:2:
> warning: initializer overrides prior initialization of this subobject
> [-Winitializer-overrides]
> vupdate_no_lock_int_entry(1),
> ^~~~
> drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:280:39:
> note: expanded from macro 'vupdate_no_lock_int_entry'
> [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
> ^~
> drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:405:2:
> note: previous initialization is here
> vupdate_int_entry(1),
> ^~~~
> drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:269:39:
> note: expanded from macro 'vupdate_int_entry'
> [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
> ^~
> drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:412:2:
> warning: initializer overrides prior initialization of this subobject
> [-Winitializer-overrides]
> vupdate_no_lock_int_entry(2),
> ^~~~
> drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:280:39:
> note: expanded from macro 'vupdate_no_lock_int_entry'
> [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
> ^~
> drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:406:2:
> note: previous initialization is here
> vupdate_int_entry(2),
> ^~~~
> drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:269:39:
> note: expanded from macro 'vupdate_int_entry'
> [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
> ^~
> drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:413:2:
> warning: initializer overrides prior initialization of this subobject
> [-Winitializer-overrides]
> vupdate_no_lock_int_entry(3),
> ^~~~
> drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:280:39:
> note: expanded from macro 'vupdate_no_lock_int_entry'
> [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
> ^~
> drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:407:2:
> note: previous initialization is here
> vupdate_int_entry(3),
> ^~~~
> drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:269:39:
> note: expanded from macro 'vupdate_int_entry'
> [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
> ^~
> drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:414:2:
> warning: initializer overrides prior initialization of this subobject
> [-Winitializer-overrides]
> vupdate_no_lock_int_entry(4),
> ^~~~
> drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:280:39:
> note: expanded from macro 'vupdate_no_lock_int_entry'
> [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
> ^~
> drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:408:2:
> note: previous initialization is here
> vupdate_int_entry(4),
> ^~~~
> drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:269:39:
> note: expanded from macro 'vupdate_int_entry'
> [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
> ^~
> drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:415:2:
> warning: initializer overrides prior initialization of this subobject
> [-Winitializer-overrides]
> vupdate_no_lock_int_entry(5),
> ^~~~
> drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:280:39:
> note: expanded from macro 'vupdate_no_lock_int_entry'
> [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
> ^~
> drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:409:2:
> note: previous initialization is here
> vupdate_int_entry(5),
> ^~~~
> drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:269:39:
> note: expanded from macro 'vupdate_int_entry'
> [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
> 

Re: [PATCH 05/10] drm/amd/display: Remove unused dcn316_smu_set_voltage_via_phyclk function

[Alex Deucher]

Applied.  Thanks!

Alex

On Tue, Feb 22, 2022 at 8:18 AM Maíra Canal  wrote:
>
> Remove dcn316_smu_set_voltage_via_phyclk function, which is not used in the
> codebase.
>
> This was pointed by clang with the following warning:
>
> drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn316/dcn316_smu.c:171:5:
> warning: no previous prototype for function
> 'dcn316_smu_set_voltage_via_phyclk' [-Wmissing-prototypes]
> int dcn316_smu_set_voltage_via_phyclk(struct clk_mgr_internal *clk_mgr, int
> requested_phyclk_khz)
> ^
>
> Signed-off-by: Maíra Canal 
> ---
>  .../amd/display/dc/clk_mgr/dcn316/dcn316_smu.c   | 16 
>  1 file changed, 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c 
> b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c
> index b7f9e1b34c11..fd6497fd2dc5 100644
> --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c
> +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c
> @@ -168,22 +168,6 @@ int dcn316_smu_set_dispclk(struct clk_mgr_internal 
> *clk_mgr, int requested_dispc
> return actual_dispclk_set_mhz * 1000;
>  }
>
> -int dcn316_smu_set_voltage_via_phyclk(struct clk_mgr_internal *clk_mgr, int 
> requested_phyclk_khz)
> -{
> -   int actual_phypclk_set_mhz = -1;
> -
> -   if (!clk_mgr->smu_present && requested_phyclk_khz)
> -   return requested_phyclk_khz;
> -
> -   /*  Unit of SMU msg parameter is Mhz */
> -   actual_phypclk_set_mhz = dcn316_smu_send_msg_with_param(
> -   clk_mgr,
> -   VBIOSSMC_MSG_SetPhyclkVoltageByFreq,
> -   khz_to_mhz_ceil(requested_phyclk_khz));
> -
> -   return actual_phypclk_set_mhz * 1000;
> -}
> -
>  int dcn316_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int 
> requested_dcfclk_khz)
>  {
> int actual_dcfclk_set_mhz = -1;
> --
> 2.35.1
>

Re: [PATCH 04/10] drm/amd/display: Remove unused temp variable

[Alex Deucher]

Applied.  Thanks!

Alex

On Tue, Feb 22, 2022 at 8:18 AM Maíra Canal  wrote:
>
> Remove unused temp variable from the dmub_rb_flush_pending function by
> using arithmetic to remove the loop.
>
> The -Wunused-but-set-variable warning was pointed out by Clang with the
> following warning:
>
> drivers/gpu/drm/amd/amdgpu/../display/dmub/inc/dmub_cmd.h:2921:12: warning:
> variable 'temp' set but not used [-Wunused-but-set-variable]
> uint64_t temp;
>  ^
>
> Signed-off-by: Maíra Canal 
> ---
>  drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 5 +
>  1 file changed, 1 insertion(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h 
> b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
> index fb01ff49e655..d3088836d4e4 100644
> --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
> +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
> @@ -2918,11 +2918,8 @@ static inline void dmub_rb_flush_pending(const struct 
> dmub_rb *rb)
> while (rptr != wptr) {
> uint64_t volatile *data = (uint64_t volatile *)((uint8_t 
> *)(rb->base_address) + rptr);
> //uint64_t volatile *p = (uint64_t volatile *)data;
> -   uint64_t temp;
> -   uint8_t i;
>
> -   for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++)
> -   temp = *data++;
> +   *data += DMUB_RB_CMD_SIZE / sizeof(uint64_t);
>
> rptr += DMUB_RB_CMD_SIZE;
> if (rptr >= rb->capacity)
> --
> 2.35.1
>

Re: [PATCH 03/10] drm/amdgpu: Remove unused get_umc_v8_7_channel_index function

[Alex Deucher]

Applied.  Thanks!

Alex

On Tue, Feb 22, 2022 at 8:17 AM Maíra Canal  wrote:
>
> Remove get_umc_v8_7_channel_index function, which is not used
> in the codebase.
>
> This was pointed by clang with the following warning:
>
> drivers/gpu/drm/amd/amdgpu/umc_v8_7.c:50:24: warning: unused function
> 'get_umc_v8_7_channel_index' [-Wunused-function]
> static inline uint32_t get_umc_v8_7_channel_index(struct amdgpu_device *adev,
>^
>
> Signed-off-by: Maíra Canal 
> ---
>  drivers/gpu/drm/amd/amdgpu/umc_v8_7.c | 7 ---
>  1 file changed, 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v8_7.c 
> b/drivers/gpu/drm/amd/amdgpu/umc_v8_7.c
> index de85a998ef99..f35253e0eaa6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/umc_v8_7.c
> +++ b/drivers/gpu/drm/amd/amdgpu/umc_v8_7.c
> @@ -47,13 +47,6 @@ static inline uint32_t get_umc_v8_7_reg_offset(struct 
> amdgpu_device *adev,
> return adev->umc.channel_offs*ch_inst + UMC_8_INST_DIST*umc_inst;
>  }
>
> -static inline uint32_t get_umc_v8_7_channel_index(struct amdgpu_device *adev,
> -   uint32_t umc_inst,
> -   uint32_t ch_inst)
> -{
> -   return adev->umc.channel_idx_tbl[umc_inst * 
> adev->umc.channel_inst_num + ch_inst];
> -}
> -
>  static void umc_v8_7_ecc_info_query_correctable_error_count(struct 
> amdgpu_device *adev,
> uint32_t umc_inst, uint32_t 
> ch_inst,
> unsigned long *error_count)
> --
> 2.35.1
>

Re: [PATCH 02/10] drm/amdgpu: Remove tmp unused variable

[Alex Deucher]

On Tue, Feb 22, 2022 at 8:17 AM Maíra Canal  wrote:
>
> The variable tmp is not used in the dce_v6_0_hpd_fini and
> dce_v8_0_hpd_fini functions. Therefor, the variable is removed in order to
> avoid the following Clang warnings:
>
> drivers/gpu/drm/amd/amdgpu/dce_v6_0.c:331:6: warning: variable 'tmp' set but
> not used [-Wunused-but-set-variable]
> u32 tmp;
> ^
> drivers/gpu/drm/amd/amdgpu/dce_v8_0.c:325:6: warning: variable 'tmp' set but
> not used [-Wunused-but-set-variable]
> u32 tmp;
> ^
>
> Signed-off-by: Maíra Canal 
> ---
>  drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 4 +---
>  drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 4 +---
>  2 files changed, 2 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 
> b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> index b90bc2adf778..2c61f0c2e709 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> @@ -328,7 +328,6 @@ static void dce_v6_0_hpd_fini(struct amdgpu_device *adev)
> struct drm_device *dev = adev_to_drm(adev);
> struct drm_connector *connector;
> struct drm_connector_list_iter iter;
> -   u32 tmp;
>
> drm_connector_list_iter_begin(dev, &iter);
> drm_for_each_connector_iter(connector, &iter) {
> @@ -337,8 +336,7 @@ static void dce_v6_0_hpd_fini(struct amdgpu_device *adev)
> if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
> continue;
>
> -   tmp = RREG32(mmDC_HPD1_CONTROL + 
> hpd_offsets[amdgpu_connector->hpd.hpd]);
> -   tmp &= ~DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
> +   RREG32(mmDC_HPD1_CONTROL + 
> hpd_offsets[amdgpu_connector->hpd.hpd]);
> WREG32(mmDC_HPD1_CONTROL + 
> hpd_offsets[amdgpu_connector->hpd.hpd], 0);

We should be writing tmp out here rather than 0.

>
> amdgpu_irq_put(adev, &adev->hpd_irq, 
> amdgpu_connector->hpd.hpd);
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 
> b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
> index 7c1379b02f94..c5e9c5dbd165 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
> @@ -322,7 +322,6 @@ static void dce_v8_0_hpd_fini(struct amdgpu_device *adev)
> struct drm_device *dev = adev_to_drm(adev);
> struct drm_connector *connector;
> struct drm_connector_list_iter iter;
> -   u32 tmp;
>
> drm_connector_list_iter_begin(dev, &iter);
> drm_for_each_connector_iter(connector, &iter) {
> @@ -331,8 +330,7 @@ static void dce_v8_0_hpd_fini(struct amdgpu_device *adev)
> if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
> continue;
>
> -   tmp = RREG32(mmDC_HPD1_CONTROL + 
> hpd_offsets[amdgpu_connector->hpd.hpd]);
> -   tmp &= ~DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
> +   RREG32(mmDC_HPD1_CONTROL + 
> hpd_offsets[amdgpu_connector->hpd.hpd]);
> WREG32(mmDC_HPD1_CONTROL + 
> hpd_offsets[amdgpu_connector->hpd.hpd], 0);

Same here.  Care to send a patch to fix this up?

Thanks,

Alex

>
> amdgpu_irq_put(adev, &adev->hpd_irq, 
> amdgpu_connector->hpd.hpd);
> --
> 2.35.1
>

Re: [PATCH 01/10] drm/amdgpu: Change amdgpu_ras_block_late_init_default function scope

[Alex Deucher]

Applied.  Thanks!

On Tue, Feb 22, 2022 at 8:17 AM Maíra Canal  wrote:
>
> Turn previously global function into a static function to avoid the
> following Clang warning:
>
> drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:2459:5: warning: no previous prototype
> for function 'amdgpu_ras_block_late_init_default' [-Wmissing-prototypes]
> int amdgpu_ras_block_late_init_default(struct amdgpu_device *adev,
> ^
> drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:2459:1: note: declare 'static' if the
> function is not intended to be used outside of this translation unit
> int amdgpu_ras_block_late_init_default(struct amdgpu_device *adev,
> ^
> static
>
> Signed-off-by: Maíra Canal 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> index e5874df3c9ca..dff5240efcc7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> @@ -2456,7 +2456,7 @@ int amdgpu_ras_block_late_init(struct amdgpu_device 
> *adev,
> return r;
>  }
>
> -int amdgpu_ras_block_late_init_default(struct amdgpu_device *adev,
> +static int amdgpu_ras_block_late_init_default(struct amdgpu_device *adev,
>  struct ras_common_if *ras_block)
>  {
> return amdgpu_ras_block_late_init(adev, ras_block);
> --
> 2.35.1
>

Re: [PATCH] PCI: Apply quirk_amd_harvest_no_ats to all navi10 and 14 asics

[Christian König]

Am 22.02.22 um 17:08 schrieb Alex Deucher:

There are enough vbios escapes without the proper workaround
that some users still hit this.  MS never productized ATS on
windows so OEM platforms that were windows only didn't always
validate ATS.

The advantages of ATS are not worth it compared to the potential
instabilities on harvested boards.  Just disable ATS on all navi10
and 14 boards.

Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1760
Signed-off-by: Alex Deucher 


Acked-by: Christian König 


---
  drivers/pci/quirks.c | 14 +-
  1 file changed, 9 insertions(+), 5 deletions(-)

diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 003950c738d2..ea2de1616510 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -5341,11 +5341,6 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 
0x0422, quirk_no_ext_tags);
   */
  static void quirk_amd_harvest_no_ats(struct pci_dev *pdev)
  {
-   if ((pdev->device == 0x7312 && pdev->revision != 0x00) ||
-   (pdev->device == 0x7340 && pdev->revision != 0xc5) ||
-   (pdev->device == 0x7341 && pdev->revision != 0x00))
-   return;
-
if (pdev->device == 0x15d8) {
if (pdev->revision == 0xcf &&
pdev->subsystem_vendor == 0xea50 &&
@@ -5367,10 +5362,19 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, 
quirk_amd_harvest_no_ats);
  /* AMD Iceland dGPU */
  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6900, quirk_amd_harvest_no_ats);
  /* AMD Navi10 dGPU */
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7310, quirk_amd_harvest_no_ats);
  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7312, quirk_amd_harvest_no_ats);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7318, quirk_amd_harvest_no_ats);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7319, quirk_amd_harvest_no_ats);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731a, quirk_amd_harvest_no_ats);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731b, quirk_amd_harvest_no_ats);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731e, quirk_amd_harvest_no_ats);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731f, quirk_amd_harvest_no_ats);
  /* AMD Navi14 dGPU */
  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7340, quirk_amd_harvest_no_ats);
  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7341, quirk_amd_harvest_no_ats);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7347, quirk_amd_harvest_no_ats);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x734f, quirk_amd_harvest_no_ats);
  /* AMD Raven platform iGPU */
  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x15d8, quirk_amd_harvest_no_ats);
  #endif /* CONFIG_PCI_ATS */

[PATCH] PCI: Apply quirk_amd_harvest_no_ats to all navi10 and 14 asics

[Alex Deucher]

There are enough vbios escapes without the proper workaround
that some users still hit this.  MS never productized ATS on
windows so OEM platforms that were windows only didn't always
validate ATS.

The advantages of ATS are not worth it compared to the potential
instabilities on harvested boards.  Just disable ATS on all navi10
and 14 boards.

Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1760
Signed-off-by: Alex Deucher 
---
 drivers/pci/quirks.c | 14 +-
 1 file changed, 9 insertions(+), 5 deletions(-)

diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 003950c738d2..ea2de1616510 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -5341,11 +5341,6 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 
0x0422, quirk_no_ext_tags);
  */
 static void quirk_amd_harvest_no_ats(struct pci_dev *pdev)
 {
-   if ((pdev->device == 0x7312 && pdev->revision != 0x00) ||
-   (pdev->device == 0x7340 && pdev->revision != 0xc5) ||
-   (pdev->device == 0x7341 && pdev->revision != 0x00))
-   return;
-
if (pdev->device == 0x15d8) {
if (pdev->revision == 0xcf &&
pdev->subsystem_vendor == 0xea50 &&
@@ -5367,10 +5362,19 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, 
quirk_amd_harvest_no_ats);
 /* AMD Iceland dGPU */
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6900, quirk_amd_harvest_no_ats);
 /* AMD Navi10 dGPU */
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7310, quirk_amd_harvest_no_ats);
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7312, quirk_amd_harvest_no_ats);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7318, quirk_amd_harvest_no_ats);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7319, quirk_amd_harvest_no_ats);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731a, quirk_amd_harvest_no_ats);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731b, quirk_amd_harvest_no_ats);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731e, quirk_amd_harvest_no_ats);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731f, quirk_amd_harvest_no_ats);
 /* AMD Navi14 dGPU */
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7340, quirk_amd_harvest_no_ats);
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7341, quirk_amd_harvest_no_ats);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7347, quirk_amd_harvest_no_ats);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x734f, quirk_amd_harvest_no_ats);
 /* AMD Raven platform iGPU */
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x15d8, quirk_amd_harvest_no_ats);
 #endif /* CONFIG_PCI_ATS */
-- 
2.35.1

Re: [PATCH] drm/amdkfd: make CRAT table missing message informational only

[Felix Kuehling]

Am 2022-02-21 um 17:45 schrieb Alex Deucher:

On Fri, Feb 18, 2022 at 11:25 PM Paul Menzel  wrote:

Dear Alex,


Thank you for the patch.

Am 18.02.22 um 21:42 schrieb Alex Deucher:

The driver has a fallback, to make the message informational

s/to/so/?

fixed up locally.


rather than a warning.

Maybe extend it a little?

Done.


Component Resource Association Table (CRAT) are only applicable on some
AMD APUs. The message is perfectly expected. Even on AMD APUs we can now
fall back to treating it like a dGPU when the CRAT table is missing.


Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1906
Signed-off-by: Alex Deucher 
---
   drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 2 +-
   1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
index 24898238b024..1eaabd2cb41b 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
@@ -1569,7 +1569,7 @@ int kfd_create_crat_image_acpi(void **crat_image, size_t 
*size)
   /* Fetch the CRAT table from ACPI */
   status = acpi_get_table(CRAT_SIGNATURE, 0, &crat_table);
   if (status == AE_NOT_FOUND) {
- pr_warn("CRAT table not found\n");
+ pr_info("CRAT table not found\n");

Maybe make it even a debug message, or only print it, when a
corresponding AMD APU is found like in `kfd_is_acpi_crat_invalid()`?
Especially since Linux logs

  amdgpu: Virtual CRAT table created for CPU

  later on.


I think it's still valid so you know that no CRAT table was found on
the platform.  @Kuehling, Felix any opinion?


CRAT tables are only relevant on some generations of AMD APUs. Later 
developments of the ACPI standards have basically made it obsolete. Most 
systems today and in the future don't have a CRAT table. So I'm OK with 
not mentioning it when it's missing.


Regards,
  Felix




Alex


   return -ENODATA;
   } else if (ACPI_FAILURE(status)) {
   const char *err = acpi_format_exception(status);

Kind regards,

Paul

Re: [PATCH v12 1/2] drm/amdgpu: add debugfs for reset registers list

[Somalapuram, Amaranath]

On 2/22/2022 9:08 PM, Christian König wrote:

Am 22.02.22 um 16:34 schrieb Somalapuram Amaranath:

List of register populated for dump collection during the GPU reset.

Signed-off-by: Somalapuram Amaranath 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu.h |  4 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 83 +
  2 files changed, 87 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h

index b85b67a88a3d..6e35f2c4c869 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1097,6 +1097,10 @@ struct amdgpu_device {
    struct amdgpu_reset_control *reset_cntl;
  uint32_t ip_versions[HW_ID_MAX][HWIP_MAX_INSTANCE];
+
+    /* reset dump register */
+    uint32_t    *reset_dump_reg_list;
+    int num_regs;
  };
    static inline struct amdgpu_device *drm_to_adev(struct drm_device 
*ddev)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c

index 164d6a9e9fbb..0cc80aa1b5ec 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -1609,6 +1609,87 @@ DEFINE_DEBUGFS_ATTRIBUTE(fops_ib_preempt, NULL,
  DEFINE_DEBUGFS_ATTRIBUTE(fops_sclk_set, NULL,
  amdgpu_debugfs_sclk_set, "%llu\n");
  +static ssize_t amdgpu_reset_dump_register_list_read(struct file *f,
+    char __user *buf, size_t size, loff_t *pos)
+{
+    struct amdgpu_device *adev = (struct amdgpu_device 
*)file_inode(f)->i_private;

+    char reg_offset[11];
+    int i, ret, len = 0;
+
+    if (*pos)
+    return 0;
+
+    ret = down_read_killable(&adev->reset_sem);
+    if (ret)
+    return ret;
+
+    for (i = 0; i < adev->num_regs; i++) {
+    sprintf(reg_offset, "0x%x\n", adev->reset_dump_reg_list[i]);
+    up_read(&adev->reset_sem);
+    ret = copy_to_user(buf + len, reg_offset, strlen(reg_offset));
+    if (ret)
+    return -EFAULT;
+
+    len += strlen(reg_offset);
+    ret = down_read_killable(&adev->reset_sem);
+    if (ret)
+    return ret;
+    }
+
+    up_read(&adev->reset_sem);
+    if (ret)
+    return ret;


That if and return now looks superfluous.


+
+    *pos += len;
+
+    return len;
+}
+
+static ssize_t amdgpu_reset_dump_register_list_write(struct file *f,
+    const char __user *buf, size_t size, loff_t *pos)
+{
+    struct amdgpu_device *adev = (struct amdgpu_device 
*)file_inode(f)->i_private;

+    char reg_offset[12];
+    uint32_t *tmp;
+    int ret, i = 0, len = 0;
+
+    do {
+    memset(reg_offset, 0, 12);
+    if (copy_from_user(reg_offset, buf + len,
+    min(11, ((int)size-len {
+    ret = -EFAULT;
+    goto error_free;
+    }
+
+    tmp = krealloc_array(tmp, i + 1, sizeof(uint32_t), GFP_KERNEL);
+    if (sscanf(reg_offset, "%X %n", &tmp[i], &ret) != 1)


Does this also work when we write the registers separated with 
newlines into the debugfs file?

Yes. tested with with both.


Regards,
Christian.


+    goto error_free;
+
+    len += ret;
+    i++;
+    } while (len < size);
+
+    ret = down_write_killable(&adev->reset_sem);
+    if (ret)
+    goto error_free;
+
+    swap(adev->reset_dump_reg_list, tmp);
+    adev->num_regs = i;
+    up_write(&adev->reset_sem);
+    ret = size;
+
+error_free:
+    kfree(tmp);
+    return ret;
+}
+
+static const struct file_operations amdgpu_reset_dump_register_list = {
+    .owner = THIS_MODULE,
+    .read = amdgpu_reset_dump_register_list_read,
+    .write = amdgpu_reset_dump_register_list_write,
+    .llseek = default_llseek
+};
+
  int amdgpu_debugfs_init(struct amdgpu_device *adev)
  {
  struct dentry *root = adev_to_drm(adev)->primary->debugfs_root;
@@ -1672,6 +1753,8 @@ int amdgpu_debugfs_init(struct amdgpu_device 
*adev)

  &amdgpu_debugfs_test_ib_fops);
  debugfs_create_file("amdgpu_vm_info", 0444, root, adev,
  &amdgpu_debugfs_vm_info_fops);
+    debugfs_create_file("amdgpu_reset_dump_register_list", 0644, 
root, adev,

+    &amdgpu_reset_dump_register_list);
    adev->debugfs_vbios_blob.data = adev->bios;
  adev->debugfs_vbios_blob.size = adev->bios_size;

Re: [PATCH v12 1/2] drm/amdgpu: add debugfs for reset registers list

[Christian König]

Am 22.02.22 um 16:34 schrieb Somalapuram Amaranath:

List of register populated for dump collection during the GPU reset.

Signed-off-by: Somalapuram Amaranath 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu.h |  4 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 83 +
  2 files changed, 87 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index b85b67a88a3d..6e35f2c4c869 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1097,6 +1097,10 @@ struct amdgpu_device {
  
  	struct amdgpu_reset_control *reset_cntl;

uint32_t
ip_versions[HW_ID_MAX][HWIP_MAX_INSTANCE];
+
+   /* reset dump register */
+   uint32_t*reset_dump_reg_list;
+   int num_regs;
  };
  
  static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index 164d6a9e9fbb..0cc80aa1b5ec 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -1609,6 +1609,87 @@ DEFINE_DEBUGFS_ATTRIBUTE(fops_ib_preempt, NULL,
  DEFINE_DEBUGFS_ATTRIBUTE(fops_sclk_set, NULL,
amdgpu_debugfs_sclk_set, "%llu\n");
  
+static ssize_t amdgpu_reset_dump_register_list_read(struct file *f,

+   char __user *buf, size_t size, loff_t *pos)
+{
+   struct amdgpu_device *adev = (struct amdgpu_device 
*)file_inode(f)->i_private;
+   char reg_offset[11];
+   int i, ret, len = 0;
+
+   if (*pos)
+   return 0;
+
+   ret = down_read_killable(&adev->reset_sem);
+   if (ret)
+   return ret;
+
+   for (i = 0; i < adev->num_regs; i++) {
+   sprintf(reg_offset, "0x%x\n", adev->reset_dump_reg_list[i]);
+   up_read(&adev->reset_sem);
+   ret = copy_to_user(buf + len, reg_offset, strlen(reg_offset));
+   if (ret)
+   return -EFAULT;
+
+   len += strlen(reg_offset);
+   ret = down_read_killable(&adev->reset_sem);
+   if (ret)
+   return ret;
+   }
+
+   up_read(&adev->reset_sem);
+   if (ret)
+   return ret;


That if and return now looks superfluous.


+
+   *pos += len;
+
+   return len;
+}
+
+static ssize_t amdgpu_reset_dump_register_list_write(struct file *f,
+   const char __user *buf, size_t size, loff_t *pos)
+{
+   struct amdgpu_device *adev = (struct amdgpu_device 
*)file_inode(f)->i_private;
+   char reg_offset[12];
+   uint32_t *tmp;
+   int ret, i = 0, len = 0;
+
+   do {
+   memset(reg_offset, 0, 12);
+   if (copy_from_user(reg_offset, buf + len,
+   min(11, ((int)size-len {
+   ret = -EFAULT;
+   goto error_free;
+   }
+
+   tmp = krealloc_array(tmp, i + 1, sizeof(uint32_t), GFP_KERNEL);
+   if (sscanf(reg_offset, "%X %n", &tmp[i], &ret) != 1)


Does this also work when we write the registers separated with newlines 
into the debugfs file?


Regards,
Christian.


+   goto error_free;
+
+   len += ret;
+   i++;
+   } while (len < size);
+
+   ret = down_write_killable(&adev->reset_sem);
+   if (ret)
+   goto error_free;
+
+   swap(adev->reset_dump_reg_list, tmp);
+   adev->num_regs = i;
+   up_write(&adev->reset_sem);
+   ret = size;
+
+error_free:
+   kfree(tmp);
+   return ret;
+}
+
+static const struct file_operations amdgpu_reset_dump_register_list = {
+   .owner = THIS_MODULE,
+   .read = amdgpu_reset_dump_register_list_read,
+   .write = amdgpu_reset_dump_register_list_write,
+   .llseek = default_llseek
+};
+
  int amdgpu_debugfs_init(struct amdgpu_device *adev)
  {
struct dentry *root = adev_to_drm(adev)->primary->debugfs_root;
@@ -1672,6 +1753,8 @@ int amdgpu_debugfs_init(struct amdgpu_device *adev)
&amdgpu_debugfs_test_ib_fops);
debugfs_create_file("amdgpu_vm_info", 0444, root, adev,
&amdgpu_debugfs_vm_info_fops);
+   debugfs_create_file("amdgpu_reset_dump_register_list", 0644, root, adev,
+   &amdgpu_reset_dump_register_list);
  
  	adev->debugfs_vbios_blob.data = adev->bios;

adev->debugfs_vbios_blob.size = adev->bios_size;

[PATCH v12 2/2] drm/amdgpu: add reset register dump trace on GPU

[Somalapuram Amaranath]

Dump the list of register values to trace event on GPU reset.

Signed-off-by: Somalapuram Amaranath 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 17 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h  | 16 
 2 files changed, 33 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 1e651b959141..7c48fd716adb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -4534,6 +4534,22 @@ int amdgpu_device_pre_asic_reset(struct amdgpu_device 
*adev,
return r;
 }
 
+static int amdgpu_reset_reg_dumps(struct amdgpu_device *adev)
+{
+   uint32_t reg_value;
+   int i;
+
+   lockdep_assert_held(&adev->reset_sem);
+   dump_stack();
+
+   for (i = 0; i < adev->num_regs; i++) {
+   reg_value = RREG32(adev->reset_dump_reg_list[i]);
+   trace_amdgpu_reset_reg_dumps(adev->reset_dump_reg_list[i], 
reg_value);
+   }
+
+   return 0;
+}
+
 int amdgpu_do_asic_reset(struct list_head *device_list_handle,
 struct amdgpu_reset_context *reset_context)
 {
@@ -4544,6 +4560,7 @@ int amdgpu_do_asic_reset(struct list_head 
*device_list_handle,
/* Try reset handler method first */
tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,
reset_list);
+   amdgpu_reset_reg_dumps(tmp_adev);
r = amdgpu_reset_perform_reset(tmp_adev, reset_context);
/* If reset handler not implemented, continue; otherwise return */
if (r == -ENOSYS)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
index d855cb53c7e0..b9637925e85c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
@@ -537,6 +537,22 @@ TRACE_EVENT(amdgpu_ib_pipe_sync,
  __entry->seqno)
 );
 
+TRACE_EVENT(amdgpu_reset_reg_dumps,
+   TP_PROTO(uint32_t address, uint32_t value),
+   TP_ARGS(address, value),
+   TP_STRUCT__entry(
+__field(uint32_t, address)
+__field(uint32_t, value)
+),
+   TP_fast_assign(
+  __entry->address = address;
+  __entry->value = value;
+  ),
+   TP_printk("amdgpu register dump 0x%x: 0x%x",
+ __entry->address,
+ __entry->value)
+);
+
 #undef AMDGPU_JOB_GET_TIMELINE_NAME
 #endif
 
-- 
2.25.1

[PATCH v12 1/2] drm/amdgpu: add debugfs for reset registers list

[Somalapuram Amaranath]

List of register populated for dump collection during the GPU reset.

Signed-off-by: Somalapuram Amaranath 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h |  4 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 83 +
 2 files changed, 87 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index b85b67a88a3d..6e35f2c4c869 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1097,6 +1097,10 @@ struct amdgpu_device {
 
struct amdgpu_reset_control *reset_cntl;
uint32_t
ip_versions[HW_ID_MAX][HWIP_MAX_INSTANCE];
+
+   /* reset dump register */
+   uint32_t*reset_dump_reg_list;
+   int num_regs;
 };
 
 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index 164d6a9e9fbb..0cc80aa1b5ec 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -1609,6 +1609,87 @@ DEFINE_DEBUGFS_ATTRIBUTE(fops_ib_preempt, NULL,
 DEFINE_DEBUGFS_ATTRIBUTE(fops_sclk_set, NULL,
amdgpu_debugfs_sclk_set, "%llu\n");
 
+static ssize_t amdgpu_reset_dump_register_list_read(struct file *f,
+   char __user *buf, size_t size, loff_t *pos)
+{
+   struct amdgpu_device *adev = (struct amdgpu_device 
*)file_inode(f)->i_private;
+   char reg_offset[11];
+   int i, ret, len = 0;
+
+   if (*pos)
+   return 0;
+
+   ret = down_read_killable(&adev->reset_sem);
+   if (ret)
+   return ret;
+
+   for (i = 0; i < adev->num_regs; i++) {
+   sprintf(reg_offset, "0x%x\n", adev->reset_dump_reg_list[i]);
+   up_read(&adev->reset_sem);
+   ret = copy_to_user(buf + len, reg_offset, strlen(reg_offset));
+   if (ret)
+   return -EFAULT;
+
+   len += strlen(reg_offset);
+   ret = down_read_killable(&adev->reset_sem);
+   if (ret)
+   return ret;
+   }
+
+   up_read(&adev->reset_sem);
+   if (ret)
+   return ret;
+
+   *pos += len;
+
+   return len;
+}
+
+static ssize_t amdgpu_reset_dump_register_list_write(struct file *f,
+   const char __user *buf, size_t size, loff_t *pos)
+{
+   struct amdgpu_device *adev = (struct amdgpu_device 
*)file_inode(f)->i_private;
+   char reg_offset[12];
+   uint32_t *tmp;
+   int ret, i = 0, len = 0;
+
+   do {
+   memset(reg_offset, 0, 12);
+   if (copy_from_user(reg_offset, buf + len,
+   min(11, ((int)size-len {
+   ret = -EFAULT;
+   goto error_free;
+   }
+
+   tmp = krealloc_array(tmp, i + 1, sizeof(uint32_t), GFP_KERNEL);
+   if (sscanf(reg_offset, "%X %n", &tmp[i], &ret) != 1)
+   goto error_free;
+
+   len += ret;
+   i++;
+   } while (len < size);
+
+   ret = down_write_killable(&adev->reset_sem);
+   if (ret)
+   goto error_free;
+
+   swap(adev->reset_dump_reg_list, tmp);
+   adev->num_regs = i;
+   up_write(&adev->reset_sem);
+   ret = size;
+
+error_free:
+   kfree(tmp);
+   return ret;
+}
+
+static const struct file_operations amdgpu_reset_dump_register_list = {
+   .owner = THIS_MODULE,
+   .read = amdgpu_reset_dump_register_list_read,
+   .write = amdgpu_reset_dump_register_list_write,
+   .llseek = default_llseek
+};
+
 int amdgpu_debugfs_init(struct amdgpu_device *adev)
 {
struct dentry *root = adev_to_drm(adev)->primary->debugfs_root;
@@ -1672,6 +1753,8 @@ int amdgpu_debugfs_init(struct amdgpu_device *adev)
&amdgpu_debugfs_test_ib_fops);
debugfs_create_file("amdgpu_vm_info", 0444, root, adev,
&amdgpu_debugfs_vm_info_fops);
+   debugfs_create_file("amdgpu_reset_dump_register_list", 0644, root, adev,
+   &amdgpu_reset_dump_register_list);
 
adev->debugfs_vbios_blob.data = adev->bios;
adev->debugfs_vbios_blob.size = adev->bios_size;
-- 
2.25.1

Re: [PATCH] drm/amdgpu: limit harvest bit read on several ASICs

[Deucher, Alexander]

[AMD Official Use Only]

Acked-by: Alex Deucher 

From: Chen, Guchun 
Sent: Tuesday, February 22, 2022 10:07 AM
To: amd-gfx@lists.freedesktop.org ; Deucher, 
Alexander ; Zhang, Hawking ; 
Koenig, Christian ; Pan, Xinhui 
Cc: Chen, Guchun 
Subject: [PATCH] drm/amdgpu: limit harvest bit read on several ASICs

Due to faulty VBIOS out there, harvest bit setting is not
consistently correct especially for display IP. So far,
it's hard to work out a solution on all the legacy Navi1x
ASICs in a short time, so to avoid regression, limit harvest
bit read on several ASICs. Will revisit later once VBIOS has
corrected it in long term.

Fixes: b3f4ea887d5f("drm/amdgpu: read harvest bit per IP data on legacy GPUs")
Signed-off-by: Guchun Chen 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 18 +-
 1 file changed, 13 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index 11255290f117..2e0ff1ace6fc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -1129,12 +1129,20 @@ void amdgpu_discovery_harvest_ip(struct amdgpu_device 
*adev)
  * so read harvest bit per IP data structure to set
  * harvest configuration.
  */
-   if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 2, 0))
-   amdgpu_discovery_read_harvest_bit_per_ip(adev,
-   &vcn_harvest_count);
-   else
+   if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 2, 0)) {
+   if ((adev->pdev->device == 0x731E &&
+   (adev->pdev->revision == 0xC6 ||
+adev->pdev->revision == 0xC7)) ||
+   (adev->pdev->device == 0x7340 &&
+adev->pdev->revision == 0xC9) ||
+   (adev->pdev->device == 0x7360 &&
+adev->pdev->revision == 0xC7))
+   amdgpu_discovery_read_harvest_bit_per_ip(adev,
+   &vcn_harvest_count);
+   } else {
 amdgpu_disocvery_read_from_harvest_table(adev,
-   &vcn_harvest_count);
+   &vcn_harvest_count);
+   }

 amdgpu_discovery_harvest_config_quirk(adev);

--
2.17.1

[PATCH] drm/amdgpu: limit harvest bit read on several ASICs

[Guchun Chen]

Due to faulty VBIOS out there, harvest bit setting is not
consistently correct especially for display IP. So far,
it's hard to work out a solution on all the legacy Navi1x
ASICs in a short time, so to avoid regression, limit harvest
bit read on several ASICs. Will revisit later once VBIOS has
corrected it in long term.

Fixes: b3f4ea887d5f("drm/amdgpu: read harvest bit per IP data on legacy GPUs")
Signed-off-by: Guchun Chen 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 18 +-
 1 file changed, 13 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index 11255290f117..2e0ff1ace6fc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -1129,12 +1129,20 @@ void amdgpu_discovery_harvest_ip(struct amdgpu_device 
*adev)
 * so read harvest bit per IP data structure to set
 * harvest configuration.
 */
-   if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 2, 0))
-   amdgpu_discovery_read_harvest_bit_per_ip(adev,
-   &vcn_harvest_count);
-   else
+   if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 2, 0)) {
+   if ((adev->pdev->device == 0x731E &&
+   (adev->pdev->revision == 0xC6 ||
+adev->pdev->revision == 0xC7)) ||
+   (adev->pdev->device == 0x7340 &&
+adev->pdev->revision == 0xC9) ||
+   (adev->pdev->device == 0x7360 &&
+adev->pdev->revision == 0xC7))
+   amdgpu_discovery_read_harvest_bit_per_ip(adev,
+   &vcn_harvest_count);
+   } else {
amdgpu_disocvery_read_from_harvest_table(adev,
-   &vcn_harvest_count);
+   &vcn_harvest_count);
+   }
 
amdgpu_discovery_harvest_config_quirk(adev);
 
-- 
2.17.1

RE: [PATCH] drm/amdgpu: config HDP_MISC_CNTL.READ_BUFFER_WATERMARK to fix applications running across multiple GPU config hang.

[Kasiviswanathan, Harish]

[Public]

I think is safer only to set it for IP_VERSION(4, 4, 0): which is Aldebaran.


From: amd-gfx  On Behalf Of Deucher, 
Alexander
Sent: Tuesday, February 22, 2022 8:55 AM
To: Chen, Xiaogang ; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu: config HDP_MISC_CNTL.READ_BUFFER_WATERMARK to 
fix applications running across multiple GPU config hang.


[Public]


[Public]

Please be sure to test this on other asics which use the HDP 4.0 code.  I don't 
think this field exists for all of them.

Alex


From: amd-gfx 
mailto:amd-gfx-boun...@lists.freedesktop.org>>
 on behalf of Xiaogang.Chen 
mailto:xiaogang.c...@amd.com>>
Sent: Monday, February 21, 2022 6:05 PM
To: amd-gfx@lists.freedesktop.org 
mailto:amd-gfx@lists.freedesktop.org>>
Cc: Chen, Xiaogang mailto:xiaogang.c...@amd.com>>
Subject: [PATCH] drm/amdgpu: config HDP_MISC_CNTL.READ_BUFFER_WATERMARK to fix 
applications running across multiple GPU config hang.

From: Xiaogang Chen mailto:xiaogang.c...@amd.com>>

Signed-off-by: Xiaogang Chen 
mailto:xiaogang.c...@amd.com>>
---
 drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c  | 1 +
 drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_sh_mask.h | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
index d7811e0327cb..aa2c7c3f721f 100644
--- a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
@@ -145,6 +145,7 @@ static void hdp_v4_0_init_registers(struct amdgpu_device 
*adev)
 }

 WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);
+   WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, READ_BUFFER_WATERMARK, 2);

 WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 
8));
 WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE_HI, (adev->gmc.vram_start 
>> 40));
diff --git a/drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_sh_mask.h 
b/drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_sh_mask.h
index 25e28691d62d..65c91b0102e4 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_sh_mask.h
@@ -104,6 +104,7 @@
 #define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024__SHIFT  0x5
 #define HDP_MISC_CNTL__MULTIPLE_READS__SHIFT0x6
 #define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES__SHIFT 0xb
+#define HDP_MISC_CNTL__READ_BUFFER_WATERMARK__SHIFT 0xe
 #define HDP_MISC_CNTL__FED_ENABLE__SHIFT0x15
 #define HDP_MISC_CNTL__SYSHUB_CHANNEL_PRIORITY__SHIFT   0x17
 #define HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE__SHIFT  0x18
@@ -118,6 +119,7 @@
 #define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024_MASK0x0020L
 #define HDP_MISC_CNTL__MULTIPLE_READS_MASK  0x0040L
 #define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES_MASK   0x0800L
+#define HDP_MISC_CNTL__READ_BUFFER_WATERMARK_MASK   0xc000L
 #define HDP_MISC_CNTL__FED_ENABLE_MASK  0x0020L
 #define HDP_MISC_CNTL__SYSHUB_CHANNEL_PRIORITY_MASK 0x0080L
 #define HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE_MASK0x0100L
--
2.25.1

RE: [PATCH v2] drm/amd/display: add GTT domain support for dcn 3.1.5 and 3.1.6

[Zhang, Yifan]

[AMD Official Use Only]

Hi Alex,

I'm OK w/ this series. Acked.

BRs,
Yifan

-Original Message-
From: Alex Deucher  
Sent: Tuesday, February 22, 2022 10:17 PM
To: Wentland, Harry 
Cc: Zhang, Yifan ; amd-gfx list 
; Li, Sun peng (Leo) ; 
Deucher, Alexander ; Liang, Prike 
; Yin, Tianci (Rico) ; Koenig, 
Christian 
Subject: Re: [PATCH v2] drm/amd/display: add GTT domain support for dcn 3.1.5 
and 3.1.6

How about this series instead?
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwork.freedesktop.org%2Fseries%2F100519%2F&data=04%7C01%7Cyifan1.zhang%40amd.com%7C23aba82394f446c4c41b08d9f60e0687%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637811362370697462%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata=oMn8bBcpNupXv3Kf%2FkMMbHLBtuQ45b46rEq4cAZYs2g%3D&reserved=0

Alex

On Tue, Feb 22, 2022 at 8:53 AM Harry Wentland  wrote:
>
> On 2022-02-22 01:03, Yifan Zhang wrote:
> > From: "Tianci.Yin" 
> >
> > this patch adds GTT domain support for dcn 3.1.5 and 3.1.6
> >
> > Signed-off-by: Tianci.Yin 
> > Signed-off-by: Yifan Zhang 
>
> Acked-by: Harry Wentland 
>
> Harry
>
> > ---
> >  drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 2 ++
> >  1 file changed, 2 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c 
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> > index 9709368b4915..37f4da219a5f 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> > @@ -523,6 +523,8 @@ uint32_t amdgpu_display_supported_domains(struct 
> > amdgpu_device *adev,
> >   case IP_VERSION(3, 0, 1):
> >   case IP_VERSION(3, 1, 2):
> >   case IP_VERSION(3, 1, 3):
> > + case IP_VERSION(3, 1, 5):
> > + case IP_VERSION(3, 1, 6):
> >   domain |= AMDGPU_GEM_DOMAIN_GTT;
> >   break;
> >   default:
>

RE: [PATCH 1/2] drm/amdgpu/display: split dmcu and gpuvm handling logic

[Zhang, Yifan]

[AMD Official Use Only]

This series is 
Acked-by: Yifan Zhang 

-Original Message-
From: amd-gfx  On Behalf Of Alex Deucher
Sent: Tuesday, February 22, 2022 3:54 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander 
Subject: [PATCH 1/2] drm/amdgpu/display: split dmcu and gpuvm handling logic

Separate the logic for each of these features to make the code easier to 
understand and update in the future.

Signed-off-by: Alex Deucher 
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 35 +++
 1 file changed, 20 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 8cfe18b92c99..306b321bb70d 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1443,6 +1443,25 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
 
init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
 
+   switch (adev->ip_versions[DCE_HWIP][0]) {
+   case IP_VERSION(2, 1, 0):
+   switch (adev->dm.dmcub_fw_version) {
+   case 0: /* development */
+   case 0x1: /* linux-firmware.git hash 6d9f399 */
+   case 0x0100: /* linux-firmware.git hash 9a0b0f4 */
+   init_data.flags.disable_dmcu = false;
+   break;
+   default:
+   init_data.flags.disable_dmcu = true;
+   }
+   break;
+   case IP_VERSION(2, 0, 3):
+   init_data.flags.disable_dmcu = true;
+   break;
+   default:
+   break;
+   }
+
switch (adev->asic_type) {
case CHIP_CARRIZO:
case CHIP_STONEY:
@@ -1450,29 +1469,15 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
break;
default:
switch (adev->ip_versions[DCE_HWIP][0]) {
-   case IP_VERSION(2, 1, 0):
-   init_data.flags.gpu_vm_support = true;
-   switch (adev->dm.dmcub_fw_version) {
-   case 0: /* development */
-   case 0x1: /* linux-firmware.git hash 6d9f399 */
-   case 0x0100: /* linux-firmware.git hash 9a0b0f4 */
-   init_data.flags.disable_dmcu = false;
-   break;
-   default:
-   init_data.flags.disable_dmcu = true;
-   }
-   break;
case IP_VERSION(1, 0, 0):
case IP_VERSION(1, 0, 1):
+   case IP_VERSION(2, 1, 0):
case IP_VERSION(3, 0, 1):
case IP_VERSION(3, 1, 2):
case IP_VERSION(3, 1, 3):
case IP_VERSION(3, 1, 5):
init_data.flags.gpu_vm_support = true;
break;
-   case IP_VERSION(2, 0, 3):
-   init_data.flags.disable_dmcu = true;
-   break;
default:
break;
}
--
2.35.1

Re: [PATCH v11 1/2] drm/amdgpu: add debugfs for reset registers list

[Christian König]

Am 22.02.22 um 15:37 schrieb Somalapuram Amaranath:

List of register populated for dump collection during the GPU reset.

Signed-off-by: Somalapuram Amaranath 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu.h |  4 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 81 +
  2 files changed, 85 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index b85b67a88a3d..6e35f2c4c869 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1097,6 +1097,10 @@ struct amdgpu_device {
  
  	struct amdgpu_reset_control *reset_cntl;

uint32_t
ip_versions[HW_ID_MAX][HWIP_MAX_INSTANCE];
+
+   /* reset dump register */
+   uint32_t*reset_dump_reg_list;
+   int num_regs;
  };
  
  static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index 164d6a9e9fbb..df6d9fb69657 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -1609,6 +1609,85 @@ DEFINE_DEBUGFS_ATTRIBUTE(fops_ib_preempt, NULL,
  DEFINE_DEBUGFS_ATTRIBUTE(fops_sclk_set, NULL,
amdgpu_debugfs_sclk_set, "%llu\n");
  
+static ssize_t amdgpu_reset_dump_register_list_read(struct file *f,

+   char __user *buf, size_t size, loff_t *pos)
+{
+   struct amdgpu_device *adev = (struct amdgpu_device 
*)file_inode(f)->i_private;
+   char reg_offset[11];
+   int i, ret, len = 0;
+
+   if (*pos)
+   return 0;
+
+   ret = down_read_killable(&adev->reset_sem);
+   if (ret)
+   return ret;
+
+   for (i = 0; i < adev->num_regs; i++) {
+   sprintf(reg_offset, "0x%x\n", adev->reset_dump_reg_list[i]);
+   up_read(&adev->reset_sem);
+   ret = copy_to_user(buf + len, reg_offset, strlen(reg_offset));
+   if (ret)
+   return ret;


You need to return -EFAULT here, not the return value of copy_to_user() 
cause that are the number of bytes which couldn't be copied.



+
+   len += strlen(reg_offset);
+   ret = down_read_killable(&adev->reset_sem);
+   if (ret)
+   return ret;
+   }
+
+   up_read(&adev->reset_sem);
+   if (ret)
+   return ret;
+
+   *pos += len;
+
+   return len;
+}
+
+static ssize_t amdgpu_reset_dump_register_list_write(struct file *f,
+   const char __user *buf, size_t size, loff_t *pos)
+{
+   struct amdgpu_device *adev = (struct amdgpu_device 
*)file_inode(f)->i_private;
+   char reg_offset[12];
+   uint32_t *tmp;
+   int ret, i = 0, len = 0;
+
+   do {
+   memset(reg_offset, 0, 12);
+   ret = copy_from_user(reg_offset, buf + len, min(11, 
((int)size-len)));
+   if (ret)
+   goto error_free;


Same here.


+
+   tmp = krealloc_array(tmp, i + 1, sizeof(uint32_t), GFP_KERNEL);
+   if (sscanf(reg_offset, "%X %n", &tmp[i], &ret) != 1)
+   goto error_free;
+
+   len += ret;
+   i++;
+   } while (len < size);
+
+   ret = down_write_killable(&adev->reset_sem);
+   if (ret)
+   goto error_free;
+
+   swap(adev->reset_dump_reg_list, tmp);
+   adev->num_regs = i;
+   up_write(&adev->reset_sem);
+   ret = size;
+
+error_free:
+   kfree(tmp);
+   return ret;



+}
+
+static const struct file_operations amdgpu_reset_dump_register_list = {
+   .owner = THIS_MODULE,
+   .read = amdgpu_reset_dump_register_list_read,
+   .write = amdgpu_reset_dump_register_list_write,
+   .llseek = default_llseek
+};
+
  int amdgpu_debugfs_init(struct amdgpu_device *adev)
  {
struct dentry *root = adev_to_drm(adev)->primary->debugfs_root;
@@ -1672,6 +1751,8 @@ int amdgpu_debugfs_init(struct amdgpu_device *adev)
&amdgpu_debugfs_test_ib_fops);
debugfs_create_file("amdgpu_vm_info", 0444, root, adev,
&amdgpu_debugfs_vm_info_fops);
+   debugfs_create_file("amdgpu_reset_dump_register_list", 0644, root, adev,
+   &amdgpu_reset_dump_register_list);
  
  	adev->debugfs_vbios_blob.data = adev->bios;

adev->debugfs_vbios_blob.size = adev->bios_size;

[PATCH v11 2/2] drm/amdgpu: add reset register dump trace on GPU

[Somalapuram Amaranath]

Dump the list of register values to trace event on GPU reset.

Signed-off-by: Somalapuram Amaranath 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 17 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h  | 16 
 2 files changed, 33 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 1e651b959141..7c48fd716adb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -4534,6 +4534,22 @@ int amdgpu_device_pre_asic_reset(struct amdgpu_device 
*adev,
return r;
 }
 
+static int amdgpu_reset_reg_dumps(struct amdgpu_device *adev)
+{
+   uint32_t reg_value;
+   int i;
+
+   lockdep_assert_held(&adev->reset_sem);
+   dump_stack();
+
+   for (i = 0; i < adev->num_regs; i++) {
+   reg_value = RREG32(adev->reset_dump_reg_list[i]);
+   trace_amdgpu_reset_reg_dumps(adev->reset_dump_reg_list[i], 
reg_value);
+   }
+
+   return 0;
+}
+
 int amdgpu_do_asic_reset(struct list_head *device_list_handle,
 struct amdgpu_reset_context *reset_context)
 {
@@ -4544,6 +4560,7 @@ int amdgpu_do_asic_reset(struct list_head 
*device_list_handle,
/* Try reset handler method first */
tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,
reset_list);
+   amdgpu_reset_reg_dumps(tmp_adev);
r = amdgpu_reset_perform_reset(tmp_adev, reset_context);
/* If reset handler not implemented, continue; otherwise return */
if (r == -ENOSYS)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
index d855cb53c7e0..b9637925e85c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
@@ -537,6 +537,22 @@ TRACE_EVENT(amdgpu_ib_pipe_sync,
  __entry->seqno)
 );
 
+TRACE_EVENT(amdgpu_reset_reg_dumps,
+   TP_PROTO(uint32_t address, uint32_t value),
+   TP_ARGS(address, value),
+   TP_STRUCT__entry(
+__field(uint32_t, address)
+__field(uint32_t, value)
+),
+   TP_fast_assign(
+  __entry->address = address;
+  __entry->value = value;
+  ),
+   TP_printk("amdgpu register dump 0x%x: 0x%x",
+ __entry->address,
+ __entry->value)
+);
+
 #undef AMDGPU_JOB_GET_TIMELINE_NAME
 #endif
 
-- 
2.25.1

[PATCH v11 1/2] drm/amdgpu: add debugfs for reset registers list

[Somalapuram Amaranath]

List of register populated for dump collection during the GPU reset.

Signed-off-by: Somalapuram Amaranath 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h |  4 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 81 +
 2 files changed, 85 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index b85b67a88a3d..6e35f2c4c869 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1097,6 +1097,10 @@ struct amdgpu_device {
 
struct amdgpu_reset_control *reset_cntl;
uint32_t
ip_versions[HW_ID_MAX][HWIP_MAX_INSTANCE];
+
+   /* reset dump register */
+   uint32_t*reset_dump_reg_list;
+   int num_regs;
 };
 
 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index 164d6a9e9fbb..df6d9fb69657 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -1609,6 +1609,85 @@ DEFINE_DEBUGFS_ATTRIBUTE(fops_ib_preempt, NULL,
 DEFINE_DEBUGFS_ATTRIBUTE(fops_sclk_set, NULL,
amdgpu_debugfs_sclk_set, "%llu\n");
 
+static ssize_t amdgpu_reset_dump_register_list_read(struct file *f,
+   char __user *buf, size_t size, loff_t *pos)
+{
+   struct amdgpu_device *adev = (struct amdgpu_device 
*)file_inode(f)->i_private;
+   char reg_offset[11];
+   int i, ret, len = 0;
+
+   if (*pos)
+   return 0;
+
+   ret = down_read_killable(&adev->reset_sem);
+   if (ret)
+   return ret;
+
+   for (i = 0; i < adev->num_regs; i++) {
+   sprintf(reg_offset, "0x%x\n", adev->reset_dump_reg_list[i]);
+   up_read(&adev->reset_sem);
+   ret = copy_to_user(buf + len, reg_offset, strlen(reg_offset));
+   if (ret)
+   return ret;
+
+   len += strlen(reg_offset);
+   ret = down_read_killable(&adev->reset_sem);
+   if (ret)
+   return ret;
+   }
+
+   up_read(&adev->reset_sem);
+   if (ret)
+   return ret;
+
+   *pos += len;
+
+   return len;
+}
+
+static ssize_t amdgpu_reset_dump_register_list_write(struct file *f,
+   const char __user *buf, size_t size, loff_t *pos)
+{
+   struct amdgpu_device *adev = (struct amdgpu_device 
*)file_inode(f)->i_private;
+   char reg_offset[12];
+   uint32_t *tmp;
+   int ret, i = 0, len = 0;
+
+   do {
+   memset(reg_offset, 0, 12);
+   ret = copy_from_user(reg_offset, buf + len, min(11, 
((int)size-len)));
+   if (ret)
+   goto error_free;
+
+   tmp = krealloc_array(tmp, i + 1, sizeof(uint32_t), GFP_KERNEL);
+   if (sscanf(reg_offset, "%X %n", &tmp[i], &ret) != 1)
+   goto error_free;
+
+   len += ret;
+   i++;
+   } while (len < size);
+
+   ret = down_write_killable(&adev->reset_sem);
+   if (ret)
+   goto error_free;
+
+   swap(adev->reset_dump_reg_list, tmp);
+   adev->num_regs = i;
+   up_write(&adev->reset_sem);
+   ret = size;
+
+error_free:
+   kfree(tmp);
+   return ret;
+}
+
+static const struct file_operations amdgpu_reset_dump_register_list = {
+   .owner = THIS_MODULE,
+   .read = amdgpu_reset_dump_register_list_read,
+   .write = amdgpu_reset_dump_register_list_write,
+   .llseek = default_llseek
+};
+
 int amdgpu_debugfs_init(struct amdgpu_device *adev)
 {
struct dentry *root = adev_to_drm(adev)->primary->debugfs_root;
@@ -1672,6 +1751,8 @@ int amdgpu_debugfs_init(struct amdgpu_device *adev)
&amdgpu_debugfs_test_ib_fops);
debugfs_create_file("amdgpu_vm_info", 0444, root, adev,
&amdgpu_debugfs_vm_info_fops);
+   debugfs_create_file("amdgpu_reset_dump_register_list", 0644, root, adev,
+   &amdgpu_reset_dump_register_list);
 
adev->debugfs_vbios_blob.data = adev->bios;
adev->debugfs_vbios_blob.size = adev->bios_size;
-- 
2.25.1

Re: [PATCH v2] drm/amd/display: add GTT domain support for dcn 3.1.5 and 3.1.6

[Alex Deucher]

How about this series instead?
https://patchwork.freedesktop.org/series/100519/

Alex

On Tue, Feb 22, 2022 at 8:53 AM Harry Wentland  wrote:
>
> On 2022-02-22 01:03, Yifan Zhang wrote:
> > From: "Tianci.Yin" 
> >
> > this patch adds GTT domain support for dcn 3.1.5 and 3.1.6
> >
> > Signed-off-by: Tianci.Yin 
> > Signed-off-by: Yifan Zhang 
>
> Acked-by: Harry Wentland 
>
> Harry
>
> > ---
> >  drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 2 ++
> >  1 file changed, 2 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c 
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> > index 9709368b4915..37f4da219a5f 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> > @@ -523,6 +523,8 @@ uint32_t amdgpu_display_supported_domains(struct 
> > amdgpu_device *adev,
> >   case IP_VERSION(3, 0, 1):
> >   case IP_VERSION(3, 1, 2):
> >   case IP_VERSION(3, 1, 3):
> > + case IP_VERSION(3, 1, 5):
> > + case IP_VERSION(3, 1, 6):
> >   domain |= AMDGPU_GEM_DOMAIN_GTT;
> >   break;
> >   default:
>

[PATCH 10/10] drm/amd/display: Turn global functions into static functions

[Maíra Canal]

Turn previously global functions into static functions to avoid
-Wmissing-prototype warnings, such as:

drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn30/irq_service_dcn30.c:50:20:
warning: no previous prototype for function 'to_dal_irq_source_dcn30'
[-Wmissing-prototypes]
enum dc_irq_source to_dal_irq_source_dcn30(
   ^
drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn30/irq_service_dcn30.c:50:1:
note: declare 'static' if the function is not intended to be used outside
of this translation unit
enum dc_irq_source to_dal_irq_source_dcn30(
^
static
1 warning generated.

drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c:488:6:
warning: no previous prototype for function
'dcn316_clk_mgr_helper_populate_bw_params' [-Wmissing-prototypes]
void dcn316_clk_mgr_helper_populate_bw_params(
 ^
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c:488:1:
note: declare 'static' if the function is not intended to be used outside
of this translation unit
void dcn316_clk_mgr_helper_populate_bw_params(
^
static
1 warning generated.

Signed-off-by: Maíra Canal 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++--
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c   | 2 +-
 .../drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c  | 3 ++-
 .../gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c| 2 +-
 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c| 2 +-
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 2 +-
 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c  | 2 +-
 drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c  | 2 +-
 8 files changed, 10 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index c9ca328d34e3..a99b92526b55 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -6362,7 +6362,7 @@ static bool is_freesync_video_mode(const struct 
drm_display_mode *mode,
return true;
 }
 
-struct dc_stream_state *
+static struct dc_stream_state *
 create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
   const struct drm_display_mode *drm_mode,
   const struct dm_connector_state *dm_state,
@@ -10189,7 +10189,7 @@ static void set_freesync_fixed_config(struct 
dm_crtc_state *dm_new_crtc_state) {
dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res;
 }
 
-int dm_update_crtc_state(struct amdgpu_display_manager *dm,
+static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
 struct drm_atomic_state *state,
 struct drm_crtc *crtc,
 struct drm_crtc_state *old_crtc_state,
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 389b0cb37995..05573f073b21 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -213,7 +213,7 @@ static bool validate_dsc_caps_on_connector(struct 
amdgpu_dm_connector *aconnecto
return true;
 }
 
-bool retrieve_downstream_port_device(struct amdgpu_dm_connector *aconnector)
+static bool retrieve_downstream_port_device(struct amdgpu_dm_connector 
*aconnector)
 {
union dp_downstream_port_present ds_port_present;
 
diff --git 
a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c
index 06bab24d8e27..450eaead4f20 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c
@@ -101,7 +101,8 @@ static uint32_t rv1_smu_wait_for_response(struct 
clk_mgr_internal *clk_mgr, unsi
return res_val;
 }
 
-int rv1_vbios_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, 
unsigned int msg_id, unsigned int param)
+static int rv1_vbios_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr,
+   unsigned int msg_id, unsigned int param)
 {
uint32_t result;
 
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
index ffd3d5cb9871..02a59adff90d 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
@@ -485,7 +485,7 @@ static unsigned int find_clk_for_voltage(
return clock;
 }
 
-void dcn316_clk_mgr_helper_populate_bw_params(
+static void dcn316_clk_mgr_helper_populate_bw_params(
struct clk_mgr_internal *clk_mgr,
struct integrated_info *bios_info,
const DpmClocks_316_t *clock_table)
diff --git a/drivers/gpu/drm/amd/display/dc/

[PATCH 02/10] drm/amdgpu: Remove tmp unused variable

[Maíra Canal]

The variable tmp is not used in the dce_v6_0_hpd_fini and
dce_v8_0_hpd_fini functions. Therefor, the variable is removed in order to
avoid the following Clang warnings:

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c:331:6: warning: variable 'tmp' set but
not used [-Wunused-but-set-variable]
u32 tmp;
^
drivers/gpu/drm/amd/amdgpu/dce_v8_0.c:325:6: warning: variable 'tmp' set but
not used [-Wunused-but-set-variable]
u32 tmp;
^

Signed-off-by: Maíra Canal 
---
 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 4 +---
 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 4 +---
 2 files changed, 2 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
index b90bc2adf778..2c61f0c2e709 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
@@ -328,7 +328,6 @@ static void dce_v6_0_hpd_fini(struct amdgpu_device *adev)
struct drm_device *dev = adev_to_drm(adev);
struct drm_connector *connector;
struct drm_connector_list_iter iter;
-   u32 tmp;
 
drm_connector_list_iter_begin(dev, &iter);
drm_for_each_connector_iter(connector, &iter) {
@@ -337,8 +336,7 @@ static void dce_v6_0_hpd_fini(struct amdgpu_device *adev)
if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
continue;
 
-   tmp = RREG32(mmDC_HPD1_CONTROL + 
hpd_offsets[amdgpu_connector->hpd.hpd]);
-   tmp &= ~DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
+   RREG32(mmDC_HPD1_CONTROL + 
hpd_offsets[amdgpu_connector->hpd.hpd]);
WREG32(mmDC_HPD1_CONTROL + 
hpd_offsets[amdgpu_connector->hpd.hpd], 0);
 
amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
index 7c1379b02f94..c5e9c5dbd165 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
@@ -322,7 +322,6 @@ static void dce_v8_0_hpd_fini(struct amdgpu_device *adev)
struct drm_device *dev = adev_to_drm(adev);
struct drm_connector *connector;
struct drm_connector_list_iter iter;
-   u32 tmp;
 
drm_connector_list_iter_begin(dev, &iter);
drm_for_each_connector_iter(connector, &iter) {
@@ -331,8 +330,7 @@ static void dce_v8_0_hpd_fini(struct amdgpu_device *adev)
if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
continue;
 
-   tmp = RREG32(mmDC_HPD1_CONTROL + 
hpd_offsets[amdgpu_connector->hpd.hpd]);
-   tmp &= ~DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
+   RREG32(mmDC_HPD1_CONTROL + 
hpd_offsets[amdgpu_connector->hpd.hpd]);
WREG32(mmDC_HPD1_CONTROL + 
hpd_offsets[amdgpu_connector->hpd.hpd], 0);
 
amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
-- 
2.35.1

[PATCH 06/10] drm/amd/display: Remove vupdate_int_entry definition

[Maíra Canal]

Remove the vupdate_int_entry definition and utilization to avoid the
following warning by Clang:

drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:410:2:
warning: initializer overrides prior initialization of this subobject
[-Winitializer-overrides]
vupdate_no_lock_int_entry(0),
^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:280:39:
note: expanded from macro 'vupdate_no_lock_int_entry'
[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
^~
drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:404:2:
note: previous initialization is here
vupdate_int_entry(0),
^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:269:39:
note: expanded from macro 'vupdate_int_entry'
[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
^~
drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:411:2:
warning: initializer overrides prior initialization of this subobject
[-Winitializer-overrides]
vupdate_no_lock_int_entry(1),
^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:280:39:
note: expanded from macro 'vupdate_no_lock_int_entry'
[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
^~
drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:405:2:
note: previous initialization is here
vupdate_int_entry(1),
^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:269:39:
note: expanded from macro 'vupdate_int_entry'
[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
^~
drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:412:2:
warning: initializer overrides prior initialization of this subobject
[-Winitializer-overrides]
vupdate_no_lock_int_entry(2),
^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:280:39:
note: expanded from macro 'vupdate_no_lock_int_entry'
[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
^~
drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:406:2:
note: previous initialization is here
vupdate_int_entry(2),
^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:269:39:
note: expanded from macro 'vupdate_int_entry'
[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
^~
drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:413:2:
warning: initializer overrides prior initialization of this subobject
[-Winitializer-overrides]
vupdate_no_lock_int_entry(3),
^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:280:39:
note: expanded from macro 'vupdate_no_lock_int_entry'
[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
^~
drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:407:2:
note: previous initialization is here
vupdate_int_entry(3),
^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:269:39:
note: expanded from macro 'vupdate_int_entry'
[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
^~
drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:414:2:
warning: initializer overrides prior initialization of this subobject
[-Winitializer-overrides]
vupdate_no_lock_int_entry(4),
^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:280:39:
note: expanded from macro 'vupdate_no_lock_int_entry'
[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
^~
drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:408:2:
note: previous initialization is here
vupdate_int_entry(4),
^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:269:39:
note: expanded from macro 'vupdate_int_entry'
[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
^~
drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:415:2:
warning: initializer overrides prior initialization of this subobject
[-Winitializer-overrides]
vupdate_no_lock_int_entry(5),
^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:280:39:
note: expanded from macro 'vupdate_no_lock_int_entry'
[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
^~
drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:409:2:
note: previous initialization is here
vupdate_int_entry(5),
^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.c:269:39:
note: expanded from macro 'vupdate_int_entry'
[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
^~
6 warnings generated.

fixes: 688f97ed ("drm/amd/display: Add vupdate_no_lock interrupts for
DCN2.1")

Signed-off-by: Maíra Canal 
---
 .../amd/display/dc/irq/dcn21/irq_service_dcn21.c   | 14 --
 1 file changed, 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/

[PATCH 03/10] drm/amdgpu: Remove unused get_umc_v8_7_channel_index function

[Maíra Canal]

Remove get_umc_v8_7_channel_index function, which is not used
in the codebase.

This was pointed by clang with the following warning:

drivers/gpu/drm/amd/amdgpu/umc_v8_7.c:50:24: warning: unused function
'get_umc_v8_7_channel_index' [-Wunused-function]
static inline uint32_t get_umc_v8_7_channel_index(struct amdgpu_device *adev,
   ^

Signed-off-by: Maíra Canal 
---
 drivers/gpu/drm/amd/amdgpu/umc_v8_7.c | 7 ---
 1 file changed, 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v8_7.c 
b/drivers/gpu/drm/amd/amdgpu/umc_v8_7.c
index de85a998ef99..f35253e0eaa6 100644
--- a/drivers/gpu/drm/amd/amdgpu/umc_v8_7.c
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v8_7.c
@@ -47,13 +47,6 @@ static inline uint32_t get_umc_v8_7_reg_offset(struct 
amdgpu_device *adev,
return adev->umc.channel_offs*ch_inst + UMC_8_INST_DIST*umc_inst;
 }
 
-static inline uint32_t get_umc_v8_7_channel_index(struct amdgpu_device *adev,
-   uint32_t umc_inst,
-   uint32_t ch_inst)
-{
-   return adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num 
+ ch_inst];
-}
-
 static void umc_v8_7_ecc_info_query_correctable_error_count(struct 
amdgpu_device *adev,
uint32_t umc_inst, uint32_t 
ch_inst,
unsigned long *error_count)
-- 
2.35.1

[PATCH 01/10] drm/amdgpu: Change amdgpu_ras_block_late_init_default function scope

[Maíra Canal]

Turn previously global function into a static function to avoid the
following Clang warning:

drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:2459:5: warning: no previous prototype
for function 'amdgpu_ras_block_late_init_default' [-Wmissing-prototypes]
int amdgpu_ras_block_late_init_default(struct amdgpu_device *adev,
^
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:2459:1: note: declare 'static' if the
function is not intended to be used outside of this translation unit
int amdgpu_ras_block_late_init_default(struct amdgpu_device *adev,
^
static

Signed-off-by: Maíra Canal 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index e5874df3c9ca..dff5240efcc7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -2456,7 +2456,7 @@ int amdgpu_ras_block_late_init(struct amdgpu_device *adev,
return r;
 }
 
-int amdgpu_ras_block_late_init_default(struct amdgpu_device *adev,
+static int amdgpu_ras_block_late_init_default(struct amdgpu_device *adev,
 struct ras_common_if *ras_block)
 {
return amdgpu_ras_block_late_init(adev, ras_block);
-- 
2.35.1

[PATCH 00/10] Fix multiple compilation warnings

[Maíra Canal]

This patchset intends to deal with a couple of warnings in the AMD graphic
drivers. All warnings were generated with Clang and W=1 flag.

Maíra Canal (10):
  drm/amdgpu: Change amdgpu_ras_block_late_init_default function scope
  drm/amdgpu: Remove tmp unused variable
  drm/amdgpu: Remove unused get_umc_v8_7_channel_index function
  drm/amd/display: Remove unused temp variable
  drm/amd/display: Remove unused dcn316_smu_set_voltage_via_phyclk
function
  drm/amd/display: Remove vupdate_int_entry definition
  drm/amd/display: Remove unused dmub_outbox_irq_info_funcs variable
  drm/amd/display: Remove unused variable
  drm/amd/display: Add missing prototypes to dcn201_init
  drm/amd/display: Turn global functions into static functions

 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c|  2 +-
 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c  |  4 +---
 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c  |  4 +---
 drivers/gpu/drm/amd/amdgpu/umc_v8_7.c  |  7 ---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c  |  4 ++--
 .../display/amdgpu_dm/amdgpu_dm_mst_types.c|  2 +-
 .../dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c   |  3 ++-
 .../display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c |  2 +-
 .../amd/display/dc/clk_mgr/dcn316/dcn316_smu.c | 18 +-
 .../gpu/drm/amd/display/dc/core/dc_resource.c  |  2 +-
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c  |  3 ---
 .../drm/amd/display/dc/dcn201/dcn201_init.c|  1 +
 .../display/dc/irq/dcn20/irq_service_dcn20.c   |  2 +-
 .../display/dc/irq/dcn201/irq_service_dcn201.c |  5 -
 .../display/dc/irq/dcn21/irq_service_dcn21.c   | 14 --
 .../display/dc/irq/dcn30/irq_service_dcn30.c   |  2 +-
 .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h|  5 +
 17 files changed, 15 insertions(+), 65 deletions(-)

-- 
2.35.1

[PATCH 08/10] drm/amd/display: Remove unused variable

[Maíra Canal]

Remove the variable clamshell_closed from the function
dcn10_align_pixel_clocks.

This was pointed by clang with the following warning:

drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:2063:7:
warning: variable 'clamshell_closed' set but not used
[-Wunused-but-set-variable]
bool clamshell_closed = false;
 ^

Signed-off-by: Maíra Canal 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 8dc1afc03961..559aa45f27e7 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2060,14 +2060,11 @@ static int dcn10_align_pixel_clocks(struct dc *dc, int 
group_size,
uint32_t embedded_pix_clk_100hz;
uint16_t embedded_h_total;
uint16_t embedded_v_total;
-   bool clamshell_closed = false;
uint32_t dp_ref_clk_100hz =

dc->res_pool->dp_clock_source->ctx->dc->clk_mgr->dprefclk_khz*10;
 
if (dc->config.vblank_alignment_dto_params &&
dc->res_pool->dp_clock_source->funcs->override_dp_pix_clk) {
-   clamshell_closed =
-   (dc->config.vblank_alignment_dto_params >> 63);
embedded_h_total =
(dc->config.vblank_alignment_dto_params >> 32) & 0x7FFF;
embedded_v_total =
-- 
2.35.1

[PATCH 04/10] drm/amd/display: Remove unused temp variable

[Maíra Canal]

Remove unused temp variable from the dmub_rb_flush_pending function by
using arithmetic to remove the loop.

The -Wunused-but-set-variable warning was pointed out by Clang with the
following warning:

drivers/gpu/drm/amd/amdgpu/../display/dmub/inc/dmub_cmd.h:2921:12: warning:
variable 'temp' set but not used [-Wunused-but-set-variable]
uint64_t temp;
 ^

Signed-off-by: Maíra Canal 
---
 drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 5 +
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h 
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index fb01ff49e655..d3088836d4e4 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -2918,11 +2918,8 @@ static inline void dmub_rb_flush_pending(const struct 
dmub_rb *rb)
while (rptr != wptr) {
uint64_t volatile *data = (uint64_t volatile *)((uint8_t 
*)(rb->base_address) + rptr);
//uint64_t volatile *p = (uint64_t volatile *)data;
-   uint64_t temp;
-   uint8_t i;
 
-   for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++)
-   temp = *data++;
+   *data += DMUB_RB_CMD_SIZE / sizeof(uint64_t);
 
rptr += DMUB_RB_CMD_SIZE;
if (rptr >= rb->capacity)
-- 
2.35.1

[PATCH 05/10] drm/amd/display: Remove unused dcn316_smu_set_voltage_via_phyclk function

[Maíra Canal]

Remove dcn316_smu_set_voltage_via_phyclk function, which is not used in the
codebase.

This was pointed by clang with the following warning:

drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn316/dcn316_smu.c:171:5:
warning: no previous prototype for function
'dcn316_smu_set_voltage_via_phyclk' [-Wmissing-prototypes]
int dcn316_smu_set_voltage_via_phyclk(struct clk_mgr_internal *clk_mgr, int
requested_phyclk_khz)
^

Signed-off-by: Maíra Canal 
---
 .../amd/display/dc/clk_mgr/dcn316/dcn316_smu.c   | 16 
 1 file changed, 16 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c
index b7f9e1b34c11..fd6497fd2dc5 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c
@@ -168,22 +168,6 @@ int dcn316_smu_set_dispclk(struct clk_mgr_internal 
*clk_mgr, int requested_dispc
return actual_dispclk_set_mhz * 1000;
 }
 
-int dcn316_smu_set_voltage_via_phyclk(struct clk_mgr_internal *clk_mgr, int 
requested_phyclk_khz)
-{
-   int actual_phypclk_set_mhz = -1;
-
-   if (!clk_mgr->smu_present && requested_phyclk_khz)
-   return requested_phyclk_khz;
-
-   /*  Unit of SMU msg parameter is Mhz */
-   actual_phypclk_set_mhz = dcn316_smu_send_msg_with_param(
-   clk_mgr,
-   VBIOSSMC_MSG_SetPhyclkVoltageByFreq,
-   khz_to_mhz_ceil(requested_phyclk_khz));
-
-   return actual_phypclk_set_mhz * 1000;
-}
-
 int dcn316_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int 
requested_dcfclk_khz)
 {
int actual_dcfclk_set_mhz = -1;
-- 
2.35.1

[PATCH 09/10] drm/amd/display: Add missing prototypes to dcn201_init

[Maíra Canal]

Include the header with the prototype to silence the following clang
warning:

drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_init.c:127:6:
warning: no previous prototype for function 'dcn201_hw_sequencer_construct'
[-Wmissing-prototypes]
void dcn201_hw_sequencer_construct(struct dc *dc)
 ^

Signed-off-by: Maíra Canal 
---
 drivers/gpu/drm/amd/display/dc/dcn201/dcn201_init.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_init.c 
b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_init.c
index f1f89f93603f..1826dd7f3da1 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_init.c
@@ -27,6 +27,7 @@
 #include "dcn10/dcn10_hw_sequencer.h"
 #include "dcn20/dcn20_hwseq.h"
 #include "dcn201_hwseq.h"
+#include "dcn201_init.h"
 
 static const struct hw_sequencer_funcs dcn201_funcs = {
.program_gamut_remap = dcn10_program_gamut_remap,
-- 
2.35.1

[PATCH 07/10] drm/amd/display: Remove unused dmub_outbox_irq_info_funcs variable

[Maíra Canal]

Remove the unused struct irq_source_info_funcs
dmub_outbox_irq_info_funcs from the file, which was declared but never
hooked up.

This was pointed by clang with the following warning:

drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn201/irq_service_dcn201.c:141:43:
warning: unused variable 'dmub_outbox_irq_info_funcs'
[-Wunused-const-variable]
static const struct irq_source_info_funcs dmub_outbox_irq_info_funcs = {
  ^

Signed-off-by: Maíra Canal 
---
 .../gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c   | 5 -
 1 file changed, 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c 
b/drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c
index aa708b61142f..45f99351a0ab 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c
@@ -138,11 +138,6 @@ static const struct irq_source_info_funcs 
vupdate_no_lock_irq_info_funcs = {
.ack = NULL
 };
 
-static const struct irq_source_info_funcs dmub_outbox_irq_info_funcs = {
-   .set = NULL,
-   .ack = NULL
-};
-
 #undef BASE_INNER
 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
 
-- 
2.35.1

Re: [PATCH] drm/amdgpu: config HDP_MISC_CNTL.READ_BUFFER_WATERMARK to fix applications running across multiple GPU config hang.

[Deucher, Alexander]

[Public]

Please be sure to test this on other asics which use the HDP 4.0 code.  I don't 
think this field exists for all of them.

Alex


From: amd-gfx  on behalf of 
Xiaogang.Chen 
Sent: Monday, February 21, 2022 6:05 PM
To: amd-gfx@lists.freedesktop.org 
Cc: Chen, Xiaogang 
Subject: [PATCH] drm/amdgpu: config HDP_MISC_CNTL.READ_BUFFER_WATERMARK to fix 
applications running across multiple GPU config hang.

From: Xiaogang Chen 

Signed-off-by: Xiaogang Chen 
---
 drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c  | 1 +
 drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_sh_mask.h | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
index d7811e0327cb..aa2c7c3f721f 100644
--- a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
@@ -145,6 +145,7 @@ static void hdp_v4_0_init_registers(struct amdgpu_device 
*adev)
 }

 WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);
+   WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, READ_BUFFER_WATERMARK, 2);

 WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 
8));
 WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE_HI, (adev->gmc.vram_start 
>> 40));
diff --git a/drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_sh_mask.h 
b/drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_sh_mask.h
index 25e28691d62d..65c91b0102e4 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_sh_mask.h
@@ -104,6 +104,7 @@
 #define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024__SHIFT  0x5
 #define HDP_MISC_CNTL__MULTIPLE_READS__SHIFT0x6
 #define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES__SHIFT 0xb
+#define HDP_MISC_CNTL__READ_BUFFER_WATERMARK__SHIFT 0xe
 #define HDP_MISC_CNTL__FED_ENABLE__SHIFT0x15
 #define HDP_MISC_CNTL__SYSHUB_CHANNEL_PRIORITY__SHIFT   0x17
 #define HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE__SHIFT  0x18
@@ -118,6 +119,7 @@
 #define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024_MASK0x0020L
 #define HDP_MISC_CNTL__MULTIPLE_READS_MASK  0x0040L
 #define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES_MASK   0x0800L
+#define HDP_MISC_CNTL__READ_BUFFER_WATERMARK_MASK   0xc000L
 #define HDP_MISC_CNTL__FED_ENABLE_MASK  0x0020L
 #define HDP_MISC_CNTL__SYSHUB_CHANNEL_PRIORITY_MASK 0x0080L
 #define HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE_MASK0x0100L
--
2.25.1

Re: [PATCH v2] drm/amd/display: add GTT domain support for dcn 3.1.5 and 3.1.6

[Harry Wentland]

On 2022-02-22 01:03, Yifan Zhang wrote:
> From: "Tianci.Yin" 
> 
> this patch adds GTT domain support for dcn 3.1.5 and 3.1.6
> 
> Signed-off-by: Tianci.Yin 
> Signed-off-by: Yifan Zhang 

Acked-by: Harry Wentland 

Harry

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> index 9709368b4915..37f4da219a5f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> @@ -523,6 +523,8 @@ uint32_t amdgpu_display_supported_domains(struct 
> amdgpu_device *adev,
>   case IP_VERSION(3, 0, 1):
>   case IP_VERSION(3, 1, 2):
>   case IP_VERSION(3, 1, 3):
> + case IP_VERSION(3, 1, 5):
> + case IP_VERSION(3, 1, 6):
>   domain |= AMDGPU_GEM_DOMAIN_GTT;
>   break;
>   default:

Re: [PATCH v13 4/5] drm/amdgpu: move vram inline functions into a header

[Christian König]

Am 21.02.22 um 17:45 schrieb Arunpravin:

Move shared vram inline functions and structs
into a header file

Signed-off-by: Arunpravin 


Patches #1-#3 haven been pushed to drm-misc-next.

For this one it might be better to squash that into commit #5 as well 
since this is otherwise unused.


Might be a good idea to move the vram_mgr structur and function from 
amdgpu_ttm.h over to this file as well.


Regards,
Christian.


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h | 51 
  1 file changed, 51 insertions(+)
  create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h
new file mode 100644
index ..59983464cce5
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: MIT
+ * Copyright 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __AMDGPU_VRAM_MGR_H__
+#define __AMDGPU_VRAM_MGR_H__
+
+#include 
+
+struct amdgpu_vram_mgr_node {
+   struct ttm_resource base;
+   struct list_head blocks;
+   unsigned long flags;
+};
+
+static inline u64 amdgpu_node_start(struct drm_buddy_block *block)
+{
+   return drm_buddy_block_offset(block);
+}
+
+static inline u64 amdgpu_node_size(struct drm_buddy_block *block)
+{
+   return PAGE_SIZE << drm_buddy_block_order(block);
+}
+
+static inline struct amdgpu_vram_mgr_node *
+to_amdgpu_vram_mgr_node(struct ttm_resource *res)
+{
+   return container_of(res, struct amdgpu_vram_mgr_node, base);
+}
+
+#endif

Re: [PATCH v13 5/5] drm/amdgpu: add drm buddy support to amdgpu

[Christian König]

Am 21.02.22 um 17:45 schrieb Arunpravin:

- Remove drm_mm references and replace with drm buddy functionalities
- Add res cursor support for drm buddy

v2(Matthew Auld):
   - replace spinlock with mutex as we call kmem_cache_zalloc
 (..., GFP_KERNEL) in drm_buddy_alloc() function

   - lock drm_buddy_block_trim() function as it calls
 mark_free/mark_split are all globally visible

v3(Matthew Auld):
   - remove trim method error handling as we address the failure case
 at drm_buddy_block_trim() function

v4:
   - fix warnings reported by kernel test robot 

v5:
   - fix merge conflict issue

v6:
   - fix warnings reported by kernel test robot 

v7:
   - remove DRM_BUDDY_RANGE_ALLOCATION flag usage

v8:
   - keep DRM_BUDDY_RANGE_ALLOCATION flag usage
   - resolve conflicts created by drm/amdgpu: remove VRAM accounting v2

Signed-off-by: Arunpravin 
---
  drivers/gpu/drm/Kconfig   |   1 +
  .../gpu/drm/amd/amdgpu/amdgpu_res_cursor.h|  97 +--
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h   |   7 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c  | 256 ++
  4 files changed, 229 insertions(+), 132 deletions(-)

diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index 763355330b17..019ec0440ced 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -279,6 +279,7 @@ config DRM_AMDGPU
select HWMON
select BACKLIGHT_CLASS_DEVICE
select INTERVAL_TREE
+   select DRM_BUDDY
help
  Choose this option if you have a recent AMD Radeon graphics card.
  
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h

index acfa207cf970..da12b4ff2e45 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h
@@ -30,12 +30,15 @@
  #include 
  #include 
  
+#include "amdgpu_vram_mgr.h"

+
  /* state back for walking over vram_mgr and gtt_mgr allocations */
  struct amdgpu_res_cursor {
uint64_tstart;
uint64_tsize;
uint64_tremaining;
-   struct drm_mm_node  *node;
+   void*node;
+   uint32_tmem_type;
  };
  
  /**

@@ -52,27 +55,63 @@ static inline void amdgpu_res_first(struct ttm_resource 
*res,
uint64_t start, uint64_t size,
struct amdgpu_res_cursor *cur)
  {
+   struct drm_buddy_block *block;
+   struct list_head *head, *next;
struct drm_mm_node *node;
  
-	if (!res || res->mem_type == TTM_PL_SYSTEM) {

-   cur->start = start;
-   cur->size = size;
-   cur->remaining = size;
-   cur->node = NULL;
-   WARN_ON(res && start + size > res->num_pages << PAGE_SHIFT);
-   return;
-   }
+   if (!res)
+   goto err_out;


It's not really an error to not have a resource. So I would rather name 
the label fallback or something like that.


  
  	BUG_ON(start + size > res->num_pages << PAGE_SHIFT);
  
-	node = to_ttm_range_mgr_node(res)->mm_nodes;

-   while (start >= node->size << PAGE_SHIFT)
-   start -= node++->size << PAGE_SHIFT;
+   cur->mem_type = res->mem_type;
+
+   switch (cur->mem_type) {
+   case TTM_PL_VRAM:
+   head = &to_amdgpu_vram_mgr_node(res)->blocks;
+
+   block = list_first_entry_or_null(head,
+struct drm_buddy_block,
+link);
+   if (!block)
+   goto err_out;
+
+   while (start >= amdgpu_node_size(block)) {
+   start -= amdgpu_node_size(block);
+
+   next = block->link.next;
+   if (next != head)
+   block = list_entry(next, struct 
drm_buddy_block, link);
+   }
+
+   cur->start = amdgpu_node_start(block) + start;
+   cur->size = min(amdgpu_node_size(block) - start, size);
+   cur->remaining = size;
+   cur->node = block;
+   break;
+   case TTM_PL_TT:
+   node = to_ttm_range_mgr_node(res)->mm_nodes;
+   while (start >= node->size << PAGE_SHIFT)
+   start -= node++->size << PAGE_SHIFT;
+
+   cur->start = (node->start << PAGE_SHIFT) + start;
+   cur->size = min((node->size << PAGE_SHIFT) - start, size);
+   cur->remaining = size;
+   cur->node = node;
+   break;
+   default:
+   goto err_out;
+   }
  
-	cur->start = (node->start << PAGE_SHIFT) + start;

-   cur->size = min((node->size << PAGE_SHIFT) - start, size);
+   return;
+
+err_out:
+   cur->start = start;
+   cur->size = size;
cur->remaining = size;
-

Re: [PATCH 1/2] drm/amdgpu: use kernel BO API for benchmark buffer management

[Christian König]

Am 21.02.22 um 23:30 schrieb Alex Deucher:

Simplifies the code quite a bit.

Signed-off-by: Alex Deucher 


Reviewed-by: Christian König  for the series.


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c | 78 ---
  1 file changed, 17 insertions(+), 61 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
index 4f3cdd8cfb6a..92a2ffefe62e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
@@ -75,57 +75,25 @@ static int amdgpu_benchmark_move(struct amdgpu_device 
*adev, unsigned size,
  {
struct amdgpu_bo *dobj = NULL;
struct amdgpu_bo *sobj = NULL;
-   struct amdgpu_bo_param bp;
uint64_t saddr, daddr;
int r, n;
  
-	memset(&bp, 0, sizeof(bp));

-   bp.size = size;
-   bp.byte_align = PAGE_SIZE;
-   bp.domain = sdomain;
-   bp.flags = 0;
-   bp.type = ttm_bo_type_kernel;
-   bp.resv = NULL;
-   bp.bo_ptr_size = sizeof(struct amdgpu_bo);
-
n = AMDGPU_BENCHMARK_ITERATIONS;
-   r = amdgpu_bo_create(adev, &bp, &sobj);
-   if (r) {
-   goto out_cleanup;
-   }
-   r = amdgpu_bo_reserve(sobj, false);
-   if (unlikely(r != 0))
-   goto out_cleanup;
-   r = amdgpu_bo_pin(sobj, sdomain);
-   if (r) {
-   amdgpu_bo_unreserve(sobj);
-   goto out_cleanup;
-   }
-   r = amdgpu_ttm_alloc_gart(&sobj->tbo);
-   amdgpu_bo_unreserve(sobj);
-   if (r) {
-   goto out_cleanup;
-   }
-   saddr = amdgpu_bo_gpu_offset(sobj);
-   bp.domain = ddomain;
-   r = amdgpu_bo_create(adev, &bp, &dobj);
-   if (r) {
-   goto out_cleanup;
-   }
-   r = amdgpu_bo_reserve(dobj, false);
-   if (unlikely(r != 0))
+
+   r = amdgpu_bo_create_kernel(adev, size,
+   PAGE_SIZE, sdomain,
+   &sobj,
+   &saddr,
+   NULL);
+   if (r)
goto out_cleanup;
-   r = amdgpu_bo_pin(dobj, ddomain);
-   if (r) {
-   amdgpu_bo_unreserve(sobj);
+   r = amdgpu_bo_create_kernel(adev, size,
+   PAGE_SIZE, ddomain,
+   &dobj,
+   &daddr,
+   NULL);
+   if (r)
goto out_cleanup;
-   }
-   r = amdgpu_ttm_alloc_gart(&dobj->tbo);
-   amdgpu_bo_unreserve(dobj);
-   if (r) {
-   goto out_cleanup;
-   }
-   daddr = amdgpu_bo_gpu_offset(dobj);
  
  	if (adev->mman.buffer_funcs) {

r = amdgpu_benchmark_do_move(adev, size, saddr, daddr, n);
@@ -141,22 +109,10 @@ static int amdgpu_benchmark_move(struct amdgpu_device 
*adev, unsigned size,
if (r < 0)
dev_info(adev->dev, "Error while benchmarking BO move.\n");
  
-	if (sobj) {

-   r = amdgpu_bo_reserve(sobj, true);
-   if (likely(r == 0)) {
-   amdgpu_bo_unpin(sobj);
-   amdgpu_bo_unreserve(sobj);
-   }
-   amdgpu_bo_unref(&sobj);
-   }
-   if (dobj) {
-   r = amdgpu_bo_reserve(dobj, true);
-   if (likely(r == 0)) {
-   amdgpu_bo_unpin(dobj);
-   amdgpu_bo_unreserve(dobj);
-   }
-   amdgpu_bo_unref(&dobj);
-   }
+   if (sobj)
+   amdgpu_bo_free_kernel(&sobj, &saddr, NULL);
+   if (dobj)
+   amdgpu_bo_free_kernel(&dobj, &daddr, NULL);
return r;
  }
  

Re: [PATCH 7/7] drm/amdgpu: drop testing module parameter

[Christian König]

Am 22.02.22 um 10:07 schrieb Michel Dänzer:

On 2022-02-21 22:35, Alex Deucher wrote:

On Mon, Feb 21, 2022 at 12:44 PM Michel Dänzer
 wrote:

On 2022-02-18 23:26, Alex Deucher wrote:

This was always duplicate functionality with the benchmark tests.

Not really. The purpose of amdgpu_do_test_moves is testing that copies between GTT 
& VRAM work across the whole GTT aperture (when I originally wrote 
radeon_do_test_moves, they didn't on the PowerBook I was using at the time).


Fair enough.  I'll drop it for now.  Might be useful to convert to
debugfs at some point as well.

To be clear, I'm not saying this needs to stay — maybe it's not useful anymore. 
I'm just pointing out that it's not redundant with the benchmarks.


Yeah, the test doesn't necessary work that well any more since we now 
have the GART table much smaller than the GTT size.


I think it's still the best to just remove that.

Regards,
Christian.

Re: [PATCH] drm/amdgpu: Fixed warning reported by kernel test robot

[Paul Menzel]

Dear yipechai,


Am 22.02.22 um 09:39 schrieb Zhou1, Tao:

[AMD Official Use Only]

With my inline concerns addressed, the patch is:

Reviewed-by: Tao Zhou 


-Original Message-
From: Chai, Thomas 


Can you please configure the full name too for the From: header field, 
and Signed-off-by line.


[…]


Kind regards,

Paul

[PATCH] drm/sched: Add device pointer to drm_gpu_scheduler

[Jiawei Gu]

Add device pointer so scheduler's printing can use
DRM_DEV_ERROR() instead, which makes life easier under multiple GPU
scenario.

v2: amend all calls of drm_sched_init()
v3: fill dev pointer for all drm_sched_init() calls

Signed-off-by: Jiawei Gu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c |  2 +-
 drivers/gpu/drm/etnaviv/etnaviv_sched.c   |  2 +-
 drivers/gpu/drm/lima/lima_sched.c |  2 +-
 drivers/gpu/drm/msm/msm_ringbuffer.c  |  2 +-
 drivers/gpu/drm/panfrost/panfrost_job.c   |  2 +-
 drivers/gpu/drm/scheduler/sched_main.c|  9 +
 drivers/gpu/drm/v3d/v3d_sched.c   | 10 +-
 include/drm/gpu_scheduler.h   |  3 ++-
 8 files changed, 17 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
index 45977a72b5dd..cd2d594d4ffc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
@@ -502,7 +502,7 @@ int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
 
r = drm_sched_init(&ring->sched, &amdgpu_sched_ops,
   num_hw_submission, amdgpu_job_hang_limit,
-  timeout, NULL, sched_score, ring->name);
+  timeout, NULL, sched_score, ring->name, adev->dev);
if (r) {
DRM_ERROR("Failed to create scheduler on ring %s.\n",
  ring->name);
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_sched.c 
b/drivers/gpu/drm/etnaviv/etnaviv_sched.c
index 58f593b278c1..35e5ef7dbdcc 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_sched.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_sched.c
@@ -195,7 +195,7 @@ int etnaviv_sched_init(struct etnaviv_gpu *gpu)
ret = drm_sched_init(&gpu->sched, &etnaviv_sched_ops,
 etnaviv_hw_jobs_limit, etnaviv_job_hang_limit,
 msecs_to_jiffies(500), NULL, NULL,
-dev_name(gpu->dev));
+dev_name(gpu->dev), gpu->dev);
if (ret)
return ret;
 
diff --git a/drivers/gpu/drm/lima/lima_sched.c 
b/drivers/gpu/drm/lima/lima_sched.c
index 5612d73f238f..8d517c8880e3 100644
--- a/drivers/gpu/drm/lima/lima_sched.c
+++ b/drivers/gpu/drm/lima/lima_sched.c
@@ -490,7 +490,7 @@ int lima_sched_pipe_init(struct lima_sched_pipe *pipe, 
const char *name)
return drm_sched_init(&pipe->base, &lima_sched_ops, 1,
  lima_job_hang_limit,
  msecs_to_jiffies(timeout), NULL,
- NULL, name);
+ NULL, name, pipe->ldev->dev);
 }
 
 void lima_sched_pipe_fini(struct lima_sched_pipe *pipe)
diff --git a/drivers/gpu/drm/msm/msm_ringbuffer.c 
b/drivers/gpu/drm/msm/msm_ringbuffer.c
index 3bbf574c3bdc..367a6aaa3a20 100644
--- a/drivers/gpu/drm/msm/msm_ringbuffer.c
+++ b/drivers/gpu/drm/msm/msm_ringbuffer.c
@@ -89,7 +89,7 @@ struct msm_ringbuffer *msm_ringbuffer_new(struct msm_gpu 
*gpu, int id,
 
ret = drm_sched_init(&ring->sched, &msm_sched_ops,
num_hw_submissions, 0, sched_timeout,
-   NULL, NULL, to_msm_bo(ring->bo)->name);
+   NULL, NULL, to_msm_bo(ring->bo)->name, gpu->dev->dev);
if (ret) {
goto fail;
}
diff --git a/drivers/gpu/drm/panfrost/panfrost_job.c 
b/drivers/gpu/drm/panfrost/panfrost_job.c
index 908d79520853..a6925dbb6224 100644
--- a/drivers/gpu/drm/panfrost/panfrost_job.c
+++ b/drivers/gpu/drm/panfrost/panfrost_job.c
@@ -812,7 +812,7 @@ int panfrost_job_init(struct panfrost_device *pfdev)
 nentries, 0,
 msecs_to_jiffies(JOB_TIMEOUT_MS),
 pfdev->reset.wq,
-NULL, "pan_js");
+NULL, "pan_js", pfdev->dev);
if (ret) {
dev_err(pfdev->dev, "Failed to create scheduler: %d.", 
ret);
goto err_sched;
diff --git a/drivers/gpu/drm/scheduler/sched_main.c 
b/drivers/gpu/drm/scheduler/sched_main.c
index f91fb31ab7a7..b81fceb0b8a2 100644
--- a/drivers/gpu/drm/scheduler/sched_main.c
+++ b/drivers/gpu/drm/scheduler/sched_main.c
@@ -491,7 +491,7 @@ void drm_sched_start(struct drm_gpu_scheduler *sched, bool 
full_recovery)
if (r == -ENOENT)
drm_sched_job_done(s_job);
else if (r)
-   DRM_ERROR("fence add callback failed (%d)\n",
+   DRM_DEV_ERROR(sched->dev, "fence add callback 
failed (%d)\n",
  r);
} else
drm_sched_job_done(s_job);
@@ -957,7 +957,7 @@ static int drm_sched_main(void *param)
if (r == -ENOENT)
   

Re: [PATCH v10 1/2] drm/amdgpu: add debugfs for reset registers list

[Christian König]

Am 22.02.22 um 10:35 schrieb Somalapuram Amaranath:

List of register populated for dump collection during the GPU reset.

Signed-off-by: Somalapuram Amaranath 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu.h |  4 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 92 +
  2 files changed, 96 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index b85b67a88a3d..6e35f2c4c869 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1097,6 +1097,10 @@ struct amdgpu_device {
  
  	struct amdgpu_reset_control *reset_cntl;

uint32_t
ip_versions[HW_ID_MAX][HWIP_MAX_INSTANCE];
+
+   /* reset dump register */
+   uint32_t*reset_dump_reg_list;
+   int num_regs;
  };
  
  static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index 164d6a9e9fbb..733ee54efa34 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -1609,6 +1609,96 @@ DEFINE_DEBUGFS_ATTRIBUTE(fops_ib_preempt, NULL,
  DEFINE_DEBUGFS_ATTRIBUTE(fops_sclk_set, NULL,
amdgpu_debugfs_sclk_set, "%llu\n");
  
+static ssize_t amdgpu_reset_dump_register_list_read(struct file *f,

+   char __user *buf, size_t size, loff_t *pos)
+{
+   struct amdgpu_device *adev = (struct amdgpu_device 
*)file_inode(f)->i_private;
+   char reg_offset[11];
+   int i, ret, len = 0;
+
+   if (*pos)
+   return 0;
+
+   ret = down_read_killable(&adev->reset_sem);
+   if (ret)
+   return ret;
+
+   for (i = 0; i < adev->num_regs; i++) {
+   sprintf(reg_offset, "0x%x ", adev->reset_dump_reg_list[i]);
+   up_read(&adev->reset_sem);
+   ret = copy_to_user(buf + len, reg_offset, strlen(reg_offset));
+   if (ret)
+   goto error;


There is nothing to cleanup here any more, just return -EFAULT.


+
+   len += strlen(reg_offset);
+   ret = down_read_killable(&adev->reset_sem);
+   if (ret)
+   return ret;
+   }
+
+   up_read(&adev->reset_sem);
+   ret = copy_to_user(buf + len, "\n", 1);
+   if (ret)
+   return -EFAULT;
+
+   len++;
+   *pos += len;
+
+   return len;
+error:
+   up_read(&adev->reset_sem);
+   return -EFAULT;


That's actually wrong. The code now drops the lock before calling 
copy_to_user().



+}
+
+static ssize_t amdgpu_reset_dump_register_list_write(struct file *f,
+   const char __user *buf, size_t size, loff_t *pos)
+{
+   struct amdgpu_device *adev = (struct amdgpu_device 
*)file_inode(f)->i_private;
+   char *reg_offset, *reg, reg_temp[11];
+   uint32_t *tmp;
+   int ret, i = 0, len = 0;
+
+   do {
+   reg_offset = reg_temp;
+   memset(reg_offset, 0, 11);
+   ret = copy_from_user(reg_offset, buf + len, min(11, 
((int)size-len)));
+   if (ret)
+   goto error_free;
+
+   reg = strsep(®_offset, " ");


As I said before using strsep() is a rather bad idea here. The function 
doesn't takes a count argument and there is no guarantee that there is a 
space or zero terminator inside the string.


What should do instead is to use memchr() or alternatively using 
sscanf() should work as well and does both things in just one call. E.g. 
something like this


if (sscanf(reg, "%Lx %n", &tmp[i], &ret) != 1)
    goto error_free;

len += ret;
i++

And BTW: I would use a newline instead of a space as separator. This way 
read and write interface matches.


Regards,
Christian.


+   tmp = krealloc_array(tmp, i + 1, sizeof(uint32_t), GFP_KERNEL);
+   ret = kstrtouint(reg, 16, &tmp[i]);
+   if (ret)
+   goto error_free;
+
+   len += strlen(reg) + 1;
+   i++;
+
+   } while (len < size);
+
+   ret = down_write_killable(&adev->reset_sem);
+   if (ret)
+   goto error_free;
+
+   swap(adev->reset_dump_reg_list, tmp);
+   adev->num_regs = i;
+   up_write(&adev->reset_sem);
+   ret = size;
+
+error_free:
+   kfree(tmp);
+   return ret;
+}
+
+
+
+static const struct file_operations amdgpu_reset_dump_register_list = {
+   .owner = THIS_MODULE,
+   .read = amdgpu_reset_dump_register_list_read,
+   .write = amdgpu_reset_dump_register_list_write,
+   .llseek = default_llseek
+};
+
  int amdgpu_debugfs_init(struct amdgpu_device *adev)
  {
struct dentry *root = adev_to_drm(adev)->primary->debugfs_root;
@@ -1672,6 +1762,8 @@ int amdgpu_debugfs_init(struct amdgpu_device *adev)

[PATCH v10 2/2] drm/amdgpu: add reset register dump trace on GPU reset

[Somalapuram Amaranath]

Dump the list of register values to trace event on GPU reset.

Signed-off-by: Somalapuram Amaranath 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 16 
 drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h  | 16 
 2 files changed, 32 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 1e651b959141..0eedcd4e2227 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -4534,6 +4534,21 @@ int amdgpu_device_pre_asic_reset(struct amdgpu_device 
*adev,
return r;
 }
 
+static int amdgpu_reset_reg_dumps(struct amdgpu_device *adev)
+{
+   uint32_t reg_value;
+   int i;
+
+   lockdep_assert_held(&adev->reset_sem);
+
+   for (i = 0; i < adev->num_regs; i++) {
+   reg_value = RREG32(adev->reset_dump_reg_list[i]);
+   trace_amdgpu_reset_reg_dumps(adev->reset_dump_reg_list[i], 
reg_value);
+   }
+
+   return 0;
+}
+
 int amdgpu_do_asic_reset(struct list_head *device_list_handle,
 struct amdgpu_reset_context *reset_context)
 {
@@ -4544,6 +4559,7 @@ int amdgpu_do_asic_reset(struct list_head 
*device_list_handle,
/* Try reset handler method first */
tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,
reset_list);
+   amdgpu_reset_reg_dumps(tmp_adev);
r = amdgpu_reset_perform_reset(tmp_adev, reset_context);
/* If reset handler not implemented, continue; otherwise return */
if (r == -ENOSYS)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
index d855cb53c7e0..b9637925e85c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
@@ -537,6 +537,22 @@ TRACE_EVENT(amdgpu_ib_pipe_sync,
  __entry->seqno)
 );
 
+TRACE_EVENT(amdgpu_reset_reg_dumps,
+   TP_PROTO(uint32_t address, uint32_t value),
+   TP_ARGS(address, value),
+   TP_STRUCT__entry(
+__field(uint32_t, address)
+__field(uint32_t, value)
+),
+   TP_fast_assign(
+  __entry->address = address;
+  __entry->value = value;
+  ),
+   TP_printk("amdgpu register dump 0x%x: 0x%x",
+ __entry->address,
+ __entry->value)
+);
+
 #undef AMDGPU_JOB_GET_TIMELINE_NAME
 #endif
 
-- 
2.25.1

[PATCH v10 1/2] drm/amdgpu: add debugfs for reset registers list

[Somalapuram Amaranath]

List of register populated for dump collection during the GPU reset.

Signed-off-by: Somalapuram Amaranath 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h |  4 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 92 +
 2 files changed, 96 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index b85b67a88a3d..6e35f2c4c869 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1097,6 +1097,10 @@ struct amdgpu_device {
 
struct amdgpu_reset_control *reset_cntl;
uint32_t
ip_versions[HW_ID_MAX][HWIP_MAX_INSTANCE];
+
+   /* reset dump register */
+   uint32_t*reset_dump_reg_list;
+   int num_regs;
 };
 
 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index 164d6a9e9fbb..733ee54efa34 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -1609,6 +1609,96 @@ DEFINE_DEBUGFS_ATTRIBUTE(fops_ib_preempt, NULL,
 DEFINE_DEBUGFS_ATTRIBUTE(fops_sclk_set, NULL,
amdgpu_debugfs_sclk_set, "%llu\n");
 
+static ssize_t amdgpu_reset_dump_register_list_read(struct file *f,
+   char __user *buf, size_t size, loff_t *pos)
+{
+   struct amdgpu_device *adev = (struct amdgpu_device 
*)file_inode(f)->i_private;
+   char reg_offset[11];
+   int i, ret, len = 0;
+
+   if (*pos)
+   return 0;
+
+   ret = down_read_killable(&adev->reset_sem);
+   if (ret)
+   return ret;
+
+   for (i = 0; i < adev->num_regs; i++) {
+   sprintf(reg_offset, "0x%x ", adev->reset_dump_reg_list[i]);
+   up_read(&adev->reset_sem);
+   ret = copy_to_user(buf + len, reg_offset, strlen(reg_offset));
+   if (ret)
+   goto error;
+
+   len += strlen(reg_offset);
+   ret = down_read_killable(&adev->reset_sem);
+   if (ret)
+   return ret;
+   }
+
+   up_read(&adev->reset_sem);
+   ret = copy_to_user(buf + len, "\n", 1);
+   if (ret)
+   return -EFAULT;
+
+   len++;
+   *pos += len;
+
+   return len;
+error:
+   up_read(&adev->reset_sem);
+   return -EFAULT;
+}
+
+static ssize_t amdgpu_reset_dump_register_list_write(struct file *f,
+   const char __user *buf, size_t size, loff_t *pos)
+{
+   struct amdgpu_device *adev = (struct amdgpu_device 
*)file_inode(f)->i_private;
+   char *reg_offset, *reg, reg_temp[11];
+   uint32_t *tmp;
+   int ret, i = 0, len = 0;
+
+   do {
+   reg_offset = reg_temp;
+   memset(reg_offset, 0, 11);
+   ret = copy_from_user(reg_offset, buf + len, min(11, 
((int)size-len)));
+   if (ret)
+   goto error_free;
+
+   reg = strsep(®_offset, " ");
+   tmp = krealloc_array(tmp, i + 1, sizeof(uint32_t), GFP_KERNEL);
+   ret = kstrtouint(reg, 16, &tmp[i]);
+   if (ret)
+   goto error_free;
+
+   len += strlen(reg) + 1;
+   i++;
+
+   } while (len < size);
+
+   ret = down_write_killable(&adev->reset_sem);
+   if (ret)
+   goto error_free;
+
+   swap(adev->reset_dump_reg_list, tmp);
+   adev->num_regs = i;
+   up_write(&adev->reset_sem);
+   ret = size;
+
+error_free:
+   kfree(tmp);
+   return ret;
+}
+
+
+
+static const struct file_operations amdgpu_reset_dump_register_list = {
+   .owner = THIS_MODULE,
+   .read = amdgpu_reset_dump_register_list_read,
+   .write = amdgpu_reset_dump_register_list_write,
+   .llseek = default_llseek
+};
+
 int amdgpu_debugfs_init(struct amdgpu_device *adev)
 {
struct dentry *root = adev_to_drm(adev)->primary->debugfs_root;
@@ -1672,6 +1762,8 @@ int amdgpu_debugfs_init(struct amdgpu_device *adev)
&amdgpu_debugfs_test_ib_fops);
debugfs_create_file("amdgpu_vm_info", 0444, root, adev,
&amdgpu_debugfs_vm_info_fops);
+   debugfs_create_file("amdgpu_reset_dump_register_list", 0644, root, adev,
+   &amdgpu_reset_dump_register_list);
 
adev->debugfs_vbios_blob.data = adev->bios;
adev->debugfs_vbios_blob.size = adev->bios_size;
-- 
2.25.1

Re: [PATCH 7/7] drm/amdgpu: drop testing module parameter

[Michel Dänzer]

On 2022-02-21 22:35, Alex Deucher wrote:
> On Mon, Feb 21, 2022 at 12:44 PM Michel Dänzer
>  wrote:
>>
>> On 2022-02-18 23:26, Alex Deucher wrote:
>>> This was always duplicate functionality with the benchmark tests.
>>
>> Not really. The purpose of amdgpu_do_test_moves is testing that copies 
>> between GTT & VRAM work across the whole GTT aperture (when I originally 
>> wrote radeon_do_test_moves, they didn't on the PowerBook I was using at the 
>> time).
>>
> 
> Fair enough.  I'll drop it for now.  Might be useful to convert to
> debugfs at some point as well.

To be clear, I'm not saying this needs to stay — maybe it's not useful anymore. 
I'm just pointing out that it's not redundant with the benchmarks.


-- 
Earthling Michel Dänzer|  https://redhat.com
Libre software enthusiast  | Mesa and Xwayland developer

RE: [PATCH] drm/amdgpu: add mode2 reset support for smu 13.0.5

[Huang, Ray]

[AMD Official Use Only]

Reviewed-by: Huang Rui 

-Original Message-
From: Zhang, Yifan  
Sent: Tuesday, February 22, 2022 4:26 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Huang, Ray 
; Zhang, Yifan 
Subject: [PATCH] drm/amdgpu: add mode2 reset support for smu 13.0.5

This patch adds mode2 reset support for smu 13.0.5.

Signed-off-by: Yifan Zhang 
---
 drivers/gpu/drm/amd/amdgpu/nv.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c 
index 74e0550d00bd..80caf73bc2ce 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -454,6 +454,7 @@ nv_asic_reset_method(struct amdgpu_device *adev)
case IP_VERSION(11, 5, 0):
case IP_VERSION(13, 0, 1):
case IP_VERSION(13, 0, 3):
+   case IP_VERSION(13, 0, 5):
return AMD_RESET_METHOD_MODE2;
case IP_VERSION(11, 0, 7):
case IP_VERSION(11, 0, 11):
--
2.25.1

[PATCH] powerpc: Fix missing declaration of [en/dis]able_kernel_altivec()

[Magali Lemes]

When CONFIG_PPC64 is set and CONFIG_ALTIVEC is not the following build
failures occur:

   drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/dc_fpu.c: In function 
'dc_fpu_begin':
>> drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/dc_fpu.c:61:17: error: 
>> implicit declaration of function 'enable_kernel_altivec'; did you mean 
>> 'enable_kernel_vsx'? [-Werror=implicit-function-declaration]
  61 | enable_kernel_altivec();
 | ^
 | enable_kernel_vsx
   drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/dc_fpu.c: In function 
'dc_fpu_end':
>> drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/dc_fpu.c:89:17: error: 
>> implicit declaration of function 'disable_kernel_altivec'; did you mean 
>> 'disable_kernel_vsx'? [-Werror=implicit-function-declaration]
  89 | disable_kernel_altivec();
 | ^~
 | disable_kernel_vsx
   cc1: some warnings being treated as errors

This commit adds stub instances of both enable_kernel_altivec() and
disable_kernel_altivec() the same way as done in commit bd73758803c2
regarding enable_kernel_vsx() and disable_kernel_vsx().

Reported-by: kernel test robot 
Signed-off-by: Magali Lemes 
---
 arch/powerpc/include/asm/switch_to.h | 9 +
 1 file changed, 9 insertions(+)

diff --git a/arch/powerpc/include/asm/switch_to.h 
b/arch/powerpc/include/asm/switch_to.h
index 1f43ef696033..aee25e3ebf96 100644
--- a/arch/powerpc/include/asm/switch_to.h
+++ b/arch/powerpc/include/asm/switch_to.h
@@ -62,6 +62,15 @@ static inline void disable_kernel_altivec(void)
 #else
 static inline void save_altivec(struct task_struct *t) { }
 static inline void __giveup_altivec(struct task_struct *t) { }
+static inline void enable_kernel_altivec(void)
+{
+   BUILD_BUG();
+}
+
+static inline void disable_kernel_altivec(void)
+{
+   BUILD_BUG();
+}
 #endif
 
 #ifdef CONFIG_VSX
-- 
2.25.1

RE: [PATCH] drm/amdgpu: Fixed warning reported by kernel test robot

[Zhou1, Tao]

[AMD Official Use Only]

With my inline concerns addressed, the patch is:

Reviewed-by: Tao Zhou 

> -Original Message-
> From: Chai, Thomas 
> Sent: Tuesday, February 22, 2022 3:07 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Chai, Thomas ; Zhang, Hawking
> ; Zhou1, Tao ; Clements,
> John ; Chai, Thomas 
> Subject: [PATCH] drm/amdgpu: Fixed warning reported by kernel test robot
[Tao] "Fix warnings for RAS reported by robot" is recommended

> 
> Fixed warning reported by kernel test robot:
[Tao]: Fixed -> Fix

> 1.warning: no previous prototype for function
> 'amdgpu_ras_block_late_init_default'.
> 2.warning: variable 'ras_obj' is used uninitialized whenever '||' condition 
> is true.
> 
> Signed-off-by: yipechai 
[Tao]: "Reported-by: kernel test robot " can be added

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> index e5874df3c9ca..a73567ea03d5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> @@ -2400,7 +2400,7 @@ bool amdgpu_ras_is_poison_mode_supported(struct
> amdgpu_device *adev)  int amdgpu_ras_block_late_init(struct amdgpu_device
> *adev,
>struct ras_common_if *ras_block)
>  {
> - struct amdgpu_ras_block_object *ras_obj;
> + struct amdgpu_ras_block_object *ras_obj = NULL;
>   struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
>   unsigned long ue_count, ce_count;
>   int r;
> @@ -2456,7 +2456,7 @@ int amdgpu_ras_block_late_init(struct
> amdgpu_device *adev,
>   return r;
>  }
> 
> -int amdgpu_ras_block_late_init_default(struct amdgpu_device *adev,
> +static int amdgpu_ras_block_late_init_default(struct amdgpu_device
> +*adev,
>struct ras_common_if *ras_block)
>  {
>   return amdgpu_ras_block_late_init(adev, ras_block);
> --
> 2.25.1

[PATCH] drm/amdgpu: add mode2 reset support for smu 13.0.5

[Yifan Zhang]

This patch adds mode2 reset support for smu 13.0.5.

Signed-off-by: Yifan Zhang 
---
 drivers/gpu/drm/amd/amdgpu/nv.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 74e0550d00bd..80caf73bc2ce 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -454,6 +454,7 @@ nv_asic_reset_method(struct amdgpu_device *adev)
case IP_VERSION(11, 5, 0):
case IP_VERSION(13, 0, 1):
case IP_VERSION(13, 0, 3):
+   case IP_VERSION(13, 0, 5):
return AMD_RESET_METHOD_MODE2;
case IP_VERSION(11, 0, 7):
case IP_VERSION(11, 0, 11):
-- 
2.25.1