date:20220325

From: Roman Li 

[Why]
On resume we do link detection for all non-MST connectors.
MST is handled separately. However the condition for telling
if connector is on mst branch is not enough for mst hub case.
Link detection for mst branch link leads to mst topology reset.
That causes assert in dc_link_allocate_mst_payload()

[How]
Use link type as indicator for mst link.

Reviewed-by: Wayne Lin 
Acked-by: Alex Hung 
Signed-off-by: Roman Li 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 6633df7682ce..cbeb9db1014b 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -2714,7 +2714,8 @@ static int dm_resume(void *handle)
 * this is the case when traversing through already created
 * MST connectors, should be skipped
 */
-   if (aconnector->mst_port)
+   if (aconnector->dc_link &&
+   aconnector->dc_link->type == dc_connection_mst_branch)
continue;
 
mutex_lock(>hpd_lock);
-- 
2.35.1

[PATCH 15/16] drm/amd/display: 3.2.179

From: Aric Cyr 

- [FW Promotion] Release 0.0.110.0
- Revert FEC check in validation
- Update LTTPR UHBR link rate support struct
- Add support for USBC connector
- Add work around for AUX failure on wake
- Clear optc false state when disable otg
- Enable power gating before init_pipes
- Remove redundant dsc power gating from init_hw
- Power down hardware if timer not trigger
- Correct Slice reset calculation
- Enable 3-plane MPO for DCN31
- Set fec register init value
- Remove SW w/a for HDCP 1.4 1A-07 failure based on ECO fix
- Create underflow interrupt IRQ type

Acked-by: Alex Hung 
Signed-off-by: Aric Cyr 
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index ced40fe218ac..ef286aa30294 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -47,7 +47,7 @@ struct aux_payload;
 struct set_config_cmd_payload;
 struct dmub_notification;
 
-#define DC_VER "3.2.178"
+#define DC_VER "3.2.179"
 
 #define MAX_SURFACES 3
 #define MAX_PLANES 6
-- 
2.35.1

[PATCH 14/16] drm/amd/display: [FW Promotion] Release 0.0.110.0

From: Anthony Koo 

 - Revert save/restore PANEL_PWRSEQ_REF_DIV2 and
 other psr phy optimizations

Reviewed-by: Aric Cyr 
Acked-by: Alex Hung 
Signed-off-by: Anthony Koo 
---
 .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h   | 90 +--
 1 file changed, 4 insertions(+), 86 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h 
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index ce773b56a778..9b5db16b2619 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -46,10 +46,10 @@
 
 /* Firmware versioning. */
 #ifdef DMUB_EXPOSE_VERSION
-#define DMUB_FW_VERSION_GIT_HASH 0x51b95a35
+#define DMUB_FW_VERSION_GIT_HASH 0x19edd13d
 #define DMUB_FW_VERSION_MAJOR 0
 #define DMUB_FW_VERSION_MINOR 0
-#define DMUB_FW_VERSION_REVISION 109
+#define DMUB_FW_VERSION_REVISION 110
 #define DMUB_FW_VERSION_TEST 0
 #define DMUB_FW_VERSION_VBIOS 0
 #define DMUB_FW_VERSION_HOTFIX 0
@@ -1450,81 +1450,6 @@ enum dmub_cmd_mall_type {
DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3,
 };
 
-/**
- * PHY Link rate for DP.
- */
-enum phy_link_rate {
-   /**
-* not supported.
-*/
-   PHY_RATE_UNKNOWN = 0,
-   /**
-* Rate_1 (RBR) - 1.62 Gbps/Lane
-*/
-   PHY_RATE_162 = 1,
-   /**
-* Rate_2   - 2.16 Gbps/Lane
-*/
-   PHY_RATE_216 = 2,
-   /**
-* Rate_3   - 2.43 Gbps/Lane
-*/
-   PHY_RATE_243 = 3,
-   /**
-* Rate_4 (HBR) - 2.70 Gbps/Lane
-*/
-   PHY_RATE_270 = 4,
-   /**
-* Rate_5 (RBR2)- 3.24 Gbps/Lane
-*/
-   PHY_RATE_324 = 5,
-   /**
-* Rate_6   - 4.32 Gbps/Lane
-*/
-   PHY_RATE_432 = 6,
-   /**
-* Rate_7 (HBR2)- 5.40 Gbps/Lane
-*/
-   PHY_RATE_540 = 7,
-   /**
-* Rate_8 (HBR3)- 8.10 Gbps/Lane
-*/
-   PHY_RATE_810 = 8,
-   /**
-* UHBR10 - 10.0 Gbps/Lane
-*/
-   PHY_RATE_1000 = 9,
-   /**
-* UHBR13.5 - 13.5 Gbps/Lane
-*/
-   PHY_RATE_1350 = 10,
-   /**
-* UHBR10 - 20.0 Gbps/Lane
-*/
-   PHY_RATE_2000 = 11,
-};
-
-/**
- * enum dmub_phy_fsm_state - PHY FSM states.
- * PHY FSM state to transit to during PSR enable/disable.
- */
-enum dmub_phy_fsm_state {
-   DMUB_PHY_FSM_POWER_UP_DEFAULT = 0,
-   DMUB_PHY_FSM_RESET,
-   DMUB_PHY_FSM_RESET_RELEASED,
-   DMUB_PHY_FSM_SRAM_LOAD_DONE,
-   DMUB_PHY_FSM_INITIALIZED,
-   DMUB_PHY_FSM_CALIBRATED,
-   DMUB_PHY_FSM_CALIBRATED_LP,
-   DMUB_PHY_FSM_CALIBRATED_PG,
-   DMUB_PHY_FSM_POWER_DOWN,
-   DMUB_PHY_FSM_PLL_EN,
-   DMUB_PHY_FSM_TX_EN,
-   DMUB_PHY_FSM_FAST_LP,
-};
-
-
-
 /**
  * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command.
  */
@@ -1772,16 +1697,9 @@ struct dmub_cmd_psr_force_static_data {
 */
uint8_t panel_inst;
/**
-* Phy state to enter.
-* Values to use are defined in dmub_phy_fsm_state
-*/
-   uint8_t phy_fsm_state;
-   /**
-* Phy rate for DP - RBR/HBR/HBR2/HBR3.
-* Set this using enum phy_link_rate.
-* This does not support HDMI/DP2 for now.
+* Explicit padding to 4 byte boundary.
 */
-   uint8_t phy_rate;
+   uint8_t pad[2];
 };
 
 /**
-- 
2.35.1

[PATCH 13/16] drm/amd/display: Revert FEC check in validation

From: Martin Leung 

why and how:
causes failure on install on certain machines

Reviewed-by: George Shen 
Acked-by: Alex Hung 
Signed-off-by: Martin Leung 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 4 
 1 file changed, 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index f2ad8f58e69c..c436db416708 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1496,10 +1496,6 @@ bool dc_validate_boot_timing(const struct dc *dc,
if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
return false;
 
-   /* Check for FEC status*/
-   if (link->link_enc->funcs->fec_is_active(link->link_enc))
-   return false;
-
enc_inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
 
if (enc_inst == ENGINE_ID_UNKNOWN)
-- 
2.35.1

[PATCH 12/16] drm/amd/display: Update LTTPR UHBR link rate support struct

From: Michael Strauss 

[WHY]
Update field order to match DP2.0 spec SCR

Reviewed-by: George Shen 
Acked-by: Alex Hung 
Signed-off-by: Michael Strauss 
---
 drivers/gpu/drm/amd/display/dc/dc_dp_types.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h 
b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
index 36ac2a8746bd..7d4aa99525da 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
@@ -993,8 +993,8 @@ union dp_128b_132b_supported_link_rates {
 union dp_128b_132b_supported_lttpr_link_rates {
struct {
uint8_t UHBR10  :1;
-   uint8_t UHBR13_5:1;
uint8_t UHBR20  :1;
+   uint8_t UHBR13_5:1;
uint8_t RESERVED:5;
} bits;
uint8_t raw;
-- 
2.35.1

[PATCH 11/16] drm/amd/display: Add support for USBC connector

From: Samson Tam 

[Why]
Add support for CONNECTOR_ID_USBC

Reviewed-by: Alvin Lee 
Acked-by: Alex Hung 
Signed-off-by: Samson Tam 
---
 drivers/gpu/drm/amd/display/dc/bios/bios_parser_common.c | 3 +++
 drivers/gpu/drm/amd/display/dc/bios/command_table.c  | 3 ++-
 drivers/gpu/drm/amd/display/dc/core/dc_link.c| 8 ++--
 drivers/gpu/drm/amd/display/include/grph_object_id.h | 1 +
 4 files changed, 12 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser_common.c 
b/drivers/gpu/drm/amd/display/dc/bios/bios_parser_common.c
index a8cb039d2572..34e3a64f556e 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser_common.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser_common.c
@@ -213,6 +213,9 @@ static enum connector_id connector_id_from_bios_object_id(
case CONNECTOR_OBJECT_ID_MXM:
id = CONNECTOR_ID_MXM;
break;
+   case CONNECTOR_OBJECT_ID_USBC:
+   id = CONNECTOR_ID_USBC;
+   break;
default:
id = CONNECTOR_ID_UNKNOWN;
break;
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table.c 
b/drivers/gpu/drm/amd/display/dc/bios/command_table.c
index 0e36cd800fc9..32efa92422e8 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table.c
@@ -522,7 +522,8 @@ static enum bp_result transmitter_control_v2(
 */
params.acConfig.ucEncoderSel = 1;
 
-   if (CONNECTOR_ID_DISPLAY_PORT == connector_id)
+   if (CONNECTOR_ID_DISPLAY_PORT == connector_id
+   || CONNECTOR_ID_USBC == connector_id)
/* Bit4: DP connector flag
 * =0 connector is none-DP connector
 * =1 connector is DP connector
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index c7c4d9867c52..7aede6495e5e 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -345,6 +345,7 @@ static enum signal_type get_basic_signal_type(struct 
graphics_object_id encoder,
case CONNECTOR_ID_LVDS:
return SIGNAL_TYPE_LVDS;
case CONNECTOR_ID_DISPLAY_PORT:
+   case CONNECTOR_ID_USBC:
return SIGNAL_TYPE_DISPLAY_PORT;
case CONNECTOR_ID_EDP:
return SIGNAL_TYPE_EDP;
@@ -380,7 +381,8 @@ bool dc_link_is_dp_sink_present(struct dc_link *link)
 
bool present =
((connector_id == CONNECTOR_ID_DISPLAY_PORT) ||
-   (connector_id == CONNECTOR_ID_EDP));
+   (connector_id == CONNECTOR_ID_EDP) ||
+   (connector_id == CONNECTOR_ID_USBC));
 
ddc = dal_ddc_service_get_ddc_pin(link->ddc);
 
@@ -476,7 +478,8 @@ static enum signal_type link_detect_sink(struct dc_link 
*link,
result = SIGNAL_TYPE_DVI_SINGLE_LINK;
}
break;
-   case CONNECTOR_ID_DISPLAY_PORT: {
+   case CONNECTOR_ID_DISPLAY_PORT:
+   case CONNECTOR_ID_USBC: {
/* DP HPD short pulse. Passive DP dongle will not
 * have short pulse
 */
@@ -1591,6 +1594,7 @@ static bool dc_link_construct_legacy(struct dc_link *link,
link->connector_signal = SIGNAL_TYPE_DVI_DUAL_LINK;
break;
case CONNECTOR_ID_DISPLAY_PORT:
+   case CONNECTOR_ID_USBC:
link->connector_signal = SIGNAL_TYPE_DISPLAY_PORT;
 
if (link->hpd_gpio)
diff --git a/drivers/gpu/drm/amd/display/include/grph_object_id.h 
b/drivers/gpu/drm/amd/display/include/grph_object_id.h
index fed1edc038d8..c6bbd262f1ac 100644
--- a/drivers/gpu/drm/amd/display/include/grph_object_id.h
+++ b/drivers/gpu/drm/amd/display/include/grph_object_id.h
@@ -162,6 +162,7 @@ enum connector_id {
CONNECTOR_ID_MXM = 21,
CONNECTOR_ID_WIRELESS = 22,
CONNECTOR_ID_MIRACAST = 23,
+   CONNECTOR_ID_USBC = 24,
 
CONNECTOR_ID_VIRTUAL = 100
 };
-- 
2.35.1

[PATCH 10/16] drm/amd/display: Add work around for AUX failure on wake.

From: Jimmy Kizito 

[Why]
When waking from low-power states, a DP sink may remain unresponsive to
AUX transactions.

[How]
Try to toggle DPCD SET_POWER register repeatedly (up to a maximum
timeout value) until DP sink becomes responsive.

Reviewed-by: Mustapha Ghaddar 
Acked-by: Alex Hung 
Signed-off-by: Jimmy Kizito 
---
 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 59 +++
 .../gpu/drm/amd/display/dc/inc/dc_link_dp.h   |  1 +
 2 files changed, 60 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 351081f574cb..e4df81dc1dc2 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -5216,6 +5216,62 @@ static void retrieve_cable_id(struct dc_link *link)
>dpcd_caps.cable_id, _cable_id);
 }
 
+/* DPRX may take some time to respond to AUX messages after HPD asserted.
+ * If AUX read unsuccessful, try to wake unresponsive DPRX by toggling DPCD 
SET_POWER (0x600).
+ */
+static enum dc_status wa_try_to_wake_dprx(struct dc_link *link, uint64_t 
timeout_ms)
+{
+   enum dc_status status = DC_ERROR_UNEXPECTED;
+   uint8_t dpcd_data = 0;
+   uint64_t start_ts = 0;
+   uint64_t current_ts = 0;
+   uint64_t time_taken_ms = 0;
+   enum dc_connection_type type = dc_connection_none;
+
+   status = core_link_read_dpcd(
+   link,
+   DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
+   _data,
+   sizeof(dpcd_data));
+
+   if (status != DC_OK) {
+   DC_LOG_WARNING("%s: Read DPCD LTTPR_CAP failed - try to toggle 
DPCD SET_POWER for %lld ms.",
+   __func__,
+   timeout_ms);
+   start_ts = dm_get_timestamp(link->ctx);
+
+   do {
+   if (!dc_link_detect_sink(link, ) || type == 
dc_connection_none)
+   break;
+
+   dpcd_data = DP_SET_POWER_D3;
+   status = core_link_write_dpcd(
+   link,
+   DP_SET_POWER,
+   _data,
+   sizeof(dpcd_data));
+
+   dpcd_data = DP_SET_POWER_D0;
+   status = core_link_write_dpcd(
+   link,
+   DP_SET_POWER,
+   _data,
+   sizeof(dpcd_data));
+
+   current_ts = dm_get_timestamp(link->ctx);
+   time_taken_ms = 
div_u64(dm_get_elapse_time_in_ns(link->ctx, current_ts, start_ts), 100);
+   } while (status != DC_OK && time_taken_ms < timeout_ms);
+
+   DC_LOG_WARNING("%s: DPCD SET_POWER %s after %lld ms%s",
+   __func__,
+   (status == DC_OK) ? "succeeded" : "failed",
+   time_taken_ms,
+   (type == dc_connection_none) ? ". Unplugged." : 
".");
+   }
+
+   return status;
+}
+
 static bool retrieve_link_cap(struct dc_link *link)
 {
/* DP_ADAPTER_CAP - DP_DPCD_REV + 1 == 16 and also 
DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT + 1 == 16,
@@ -5251,6 +5307,9 @@ static bool retrieve_link_cap(struct dc_link *link)
dc_link_aux_try_to_configure_timeout(link->ddc,
LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
 
+   /* Try to ensure AUX channel active before proceeding. */
+   status = wa_try_to_wake_dprx(link, LINK_AUX_WAKE_TIMEOUT_MS);
+
is_lttpr_present = dp_retrieve_lttpr_cap(link);
/* Read DP tunneling information. */
status = dpcd_get_tunneling_device_data(link);
diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h 
b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
index ab9939db8cea..44f167d2584f 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
@@ -33,6 +33,7 @@
 #define MAX_MTP_SLOT_COUNT 64
 #define DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE 0x50
 #define TRAINING_AUX_RD_INTERVAL 100 //us
+#define LINK_AUX_WAKE_TIMEOUT_MS 1500 // Timeout when trying to wake 
unresponsive DPRX.
 
 struct dc_link;
 struct dc_stream_state;
-- 
2.35.1

[PATCH 09/16] drm/amd/display: Clear optc false state when disable otg

From: Charlene Liu 

[why]
when disable optc, need to clear the underflow status as well.

Reviewed-by: Chris Park 
Acked-by: Alex Hung 
Signed-off-by: Charlene Liu 
---
 drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c | 14 +++---
 drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c  |  5 -
 2 files changed, 11 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
index 67c13654ab99..531dd2c65007 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
@@ -343,20 +343,20 @@ void dcn31_enable_power_gating_plane(
bool enable)
 {
bool force_on = true; /* disable power gating */
+   uint32_t org_ip_request_cntl = 0;
 
if (enable && !hws->ctx->dc->debug.disable_hubp_power_gate)
force_on = false;
 
+   REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, _ip_request_cntl);
+   if (org_ip_request_cntl == 0)
+   REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
/* DCHUBP0/1/2/3/4/5 */
REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
-   REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, force_on, 1, 1000);
REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
-   REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, force_on, 1, 1000);
/* DPP0/1/2/3/4/5 */
REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
-   REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, force_on, 1, 1000);
REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
-   REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, force_on, 1, 1000);
 
force_on = true; /* disable power gating */
if (enable && !hws->ctx->dc->debug.disable_dsc_power_gate)
@@ -364,11 +364,11 @@ void dcn31_enable_power_gating_plane(
 
/* DCS0/1/2/3/4/5 */
REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
-   REG_WAIT(DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, force_on, 1, 
1000);
REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
-   REG_WAIT(DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, force_on, 1, 
1000);
REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
-   REG_WAIT(DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, force_on, 1, 
1000);
+
+   if (org_ip_request_cntl == 0)
+   REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
 }
 
 void dcn31_update_info_frame(struct pipe_ctx *pipe_ctx)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c 
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c
index 8afe2130d7c5..e05527a3a8ba 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c
@@ -124,7 +124,6 @@ static bool optc31_enable_crtc(struct timing_generator 
*optc)
 static bool optc31_disable_crtc(struct timing_generator *optc)
 {
struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
/* disable otg request until end of the first line
 * in the vertical blank region
 */
@@ -138,6 +137,7 @@ static bool optc31_disable_crtc(struct timing_generator 
*optc)
REG_WAIT(OTG_CLOCK_CONTROL,
OTG_BUSY, 0,
1, 10);
+   optc1_clear_optc_underflow(optc);
 
return true;
 }
@@ -158,6 +158,9 @@ static bool optc31_immediate_disable_crtc(struct 
timing_generator *optc)
OTG_BUSY, 0,
1, 10);
 
+   /* clear the false state */
+   optc1_clear_optc_underflow(optc);
+
return true;
 }
 
-- 
2.35.1

[PATCH 08/16] drm/amd/display: Enable power gating before init_pipes

From: Roman Li 

[Why]
In init_hw() we call init_pipes() before enabling power gating.
init_pipes() tries to power gate dsc but it may fail because
required force-ons are not released yet.
As a result with dsc config the following errors observed on resume:
"REG_WAIT timeout 1us * 1000 tries - dcn20_dsc_pg_control"
"REG_WAIT timeout 1us * 1000 tries - dcn20_dpp_pg_control"
"REG_WAIT timeout 1us * 1000 tries - dcn20_hubp_pg_control"

[How]
Move enable_power_gating_plane() before init_pipes() in init_hw()

Reviewed-by: Anthony Koo 
Reviewed-by: Eric Yang 
Acked-by: Alex Hung 
Signed-off-by: Roman Li 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 5 +++--
 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c| 5 +++--
 drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c| 5 +++--
 3 files changed, 9 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index bb309ccee3e4..e4247740ac12 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1504,6 +1504,9 @@ void dcn10_init_hw(struct dc *dc)
/* we want to turn off all dp displays before doing detection */
dc_link_blank_all_dp_displays(dc);
 
+   if (hws->funcs.enable_power_gating_plane)
+   hws->funcs.enable_power_gating_plane(dc->hwseq, true);
+
/* If taking control over from VBIOS, we may want to optimize our first
 * mode set, so we need to skip powering down pipes until we know which
 * pipes we want to use.
@@ -1556,8 +1559,6 @@ void dcn10_init_hw(struct dc *dc)
 
REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
}
-   if (hws->funcs.enable_power_gating_plane)
-   hws->funcs.enable_power_gating_plane(dc->hwseq, true);
 
if (dc->clk_mgr->funcs->notify_wm_ranges)
dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
index ed0a0e5fd805..f61ec8763844 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
@@ -547,6 +547,9 @@ void dcn30_init_hw(struct dc *dc)
/* we want to turn off all dp displays before doing detection */
dc_link_blank_all_dp_displays(dc);
 
+   if (hws->funcs.enable_power_gating_plane)
+   hws->funcs.enable_power_gating_plane(dc->hwseq, true);
+
/* If taking control over from VBIOS, we may want to optimize our first
 * mode set, so we need to skip powering down pipes until we know which
 * pipes we want to use.
@@ -624,8 +627,6 @@ void dcn30_init_hw(struct dc *dc)
 
REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
}
-   if (hws->funcs.enable_power_gating_plane)
-   hws->funcs.enable_power_gating_plane(dc->hwseq, true);
 
if (!dcb->funcs->is_accelerated_mode(dcb) && 
dc->res_pool->hubbub->funcs->init_watermarks)

dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
index b57f657c4e44..67c13654ab99 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
@@ -203,6 +203,9 @@ void dcn31_init_hw(struct dc *dc)
/* we want to turn off all dp displays before doing detection */
dc_link_blank_all_dp_displays(dc);
 
+   if (hws->funcs.enable_power_gating_plane)
+   hws->funcs.enable_power_gating_plane(dc->hwseq, true);
+
/* If taking control over from VBIOS, we may want to optimize our first
 * mode set, so we need to skip powering down pipes until we know which
 * pipes we want to use.
@@ -252,8 +255,6 @@ void dcn31_init_hw(struct dc *dc)
 
REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
}
-   if (hws->funcs.enable_power_gating_plane)
-   hws->funcs.enable_power_gating_plane(dc->hwseq, true);
 
if (!dcb->funcs->is_accelerated_mode(dcb) && 
dc->res_pool->hubbub->funcs->init_watermarks)

dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub);
-- 
2.35.1

[PATCH 07/16] drm/amd/display: Remove redundant dsc power gating from init_hw

From: Roman Li 

[Why]
DSC Power down code has been moved from dcn31_init_hw into init_pipes()
Need to remove it from dcn10_init_hw() as well to avoid duplicated action
on dcn1.x/2.x

[How]
Remove DSC power down code from dcn10_init_hw()

Fixes: 8fa6f4c5715c ("drm/amd/display: fixed the DSC power off sequence during 
Driver PnP")

Reviewed-by: Anthony Koo 
Reviewed-by: Eric Yang 
Acked-by: Alex Hung 
Signed-off-by: Roman Li 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 7 ---
 1 file changed, 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 911c5d103c64..bb309ccee3e4 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1501,13 +1501,6 @@ void dcn10_init_hw(struct dc *dc)
}
}
 
-   /* Power gate DSCs */
-   if (!is_optimized_init_done) {
-   for (i = 0; i < res_pool->res_cap->num_dsc; i++)
-   if (hws->funcs.dsc_pg_control != NULL)
-   hws->funcs.dsc_pg_control(hws, 
res_pool->dscs[i]->inst, false);
-   }
-
/* we want to turn off all dp displays before doing detection */
dc_link_blank_all_dp_displays(dc);
 
-- 
2.35.1

[PATCH 06/16] drm/amd/display: Power down hardware if timer not trigger

From: Paul Hsieh 

[WHY]
In headless systems, if SetMode/Power down timer
is not called, hardware will not be powered down
causing HW/SW discrepancies. Powering down hardware
on SetPowerState to D3 will ensure SW/HW state is accurate.

[HOW]
If PowerDownThread timer is not trigger but OS call
SetPowerState to D3, power down hardware.

Reviewed-by: Eric Yang 
Acked-by: Alex Hung 
Signed-off-by: Paul Hsieh 
---
 .../display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c  | 26 ++-
 1 file changed, 25 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
index 59fdd7f0d609..969b40250434 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
@@ -615,13 +615,37 @@ static void 
dcn31_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk
}
 }
 
+void dcn31_set_low_power_state(struct clk_mgr *clk_mgr_base)
+{
+   int display_count;
+   struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
+   struct dc *dc = clk_mgr_base->ctx->dc;
+   struct dc_state *context = dc->current_state;
+
+   if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
+   display_count = dcn31_get_active_display_cnt_wa(dc, context);
+   /* if we can go lower, go lower */
+   if (display_count == 0) {
+   union display_idle_optimization_u idle_info = { 0 };
+
+   idle_info.idle_info.df_request_disabled = 1;
+   idle_info.idle_info.phy_ref_clk_off = 1;
+   idle_info.idle_info.s0i2_rdy = 1;
+   dcn31_smu_set_display_idle_optimization(clk_mgr, 
idle_info.data);
+   /* update power state */
+   clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
+   }
+   }
+}
+
 static struct clk_mgr_funcs dcn31_funcs = {
.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
.update_clocks = dcn31_update_clocks,
.init_clocks = dcn31_init_clocks,
.enable_pme_wa = dcn31_enable_pme_wa,
.are_clock_states_equal = dcn31_are_clock_states_equal,
-   .notify_wm_ranges = dcn31_notify_wm_ranges
+   .notify_wm_ranges = dcn31_notify_wm_ranges,
+   .set_low_power_state = dcn31_set_low_power_state
 };
 extern struct clk_mgr_funcs dcn3_fpga_funcs;
 
-- 
2.35.1

[PATCH 05/16] drm/amd/display: Correct Slice reset calculation

From: Chris Park 

[Why]
Once DSC slice cannot fit pixel clock, we incorrectly
reset min slices to 0 and allow max slice to operate,
even when max slice itself cannot fit the pixel clock
properly.

[How]
Change the sequence such that we correctly determine
DSC is not possible when both min slices and max
slices cannot fit pixel clock per slice.

Reviewed-by: Wenjing Liu 
Acked-by: Alex Hung 
Signed-off-by: Chris Park 
---
 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 
b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
index 9c74564cbd8d..8973d3a38f9c 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
@@ -864,11 +864,11 @@ static bool setup_dsc_config(
min_slices_h = inc_num_slices(dsc_common_caps.slice_caps, 
min_slices_h);
}
 
+   is_dsc_possible = (min_slices_h <= max_slices_h);
+
if (pic_width % min_slices_h != 0)
min_slices_h = 0; // DSC TODO: Maybe try increasing the number 
of slices first?
 
-   is_dsc_possible = (min_slices_h <= max_slices_h);
-
if (min_slices_h == 0 && max_slices_h == 0)
is_dsc_possible = false;
 
-- 
2.35.1

[PATCH 04/16] drm/amd/display: Enable 3-plane MPO for DCN31

From: Krunoslav Kovac 

[WHY]
It can be enabled by users, but proper way is to report max_slave_planes
in DC caps for each ASIC.
Some structures use hardcoded max_plane=2, this is also addressed here.

Reviewed-by: Nevenko Stupar 
Reviewed-by: Aric Cyr 
Acked-by: Alex Hung 
Signed-off-by: Krunoslav Kovac 
---
 drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
index bf130b2435ab..826970f2bd0a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
@@ -1868,9 +1868,9 @@ static bool dcn31_resource_construct(
dc->caps.min_horizontal_blanking_period = 80;
dc->caps.dmdata_alloc_size = 2048;
 
-   dc->caps.max_slave_planes = 1;
-   dc->caps.max_slave_yuv_planes = 1;
-   dc->caps.max_slave_rgb_planes = 1;
+   dc->caps.max_slave_planes = 2;
+   dc->caps.max_slave_yuv_planes = 2;
+   dc->caps.max_slave_rgb_planes = 2;
dc->caps.post_blend_color_processing = true;
dc->caps.force_dp_tps4_for_cp2520 = true;
dc->caps.dp_hpo = true;
-- 
2.35.1

[PATCH 03/16] drm/amd/display: Set fec register init value

From: Jingwen Zhu 

[Why]
We don't include this eDP FEC init on fastboot.

[How]
Set the fec to init value when stopping driver  the fec register value to 
check should enable FEC.

Co-authored-by: Jingwen Zhu 
Reviewed-by: Wenjing Liu 
Acked-by: Alex Hung 
Signed-off-by: Jingwen Zhu 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 26 +--
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c |  6 -
 .../drm/amd/display/dc/dcn31/dcn31_hwseq.c|  6 -
 3 files changed, 22 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index bbaa5abdf888..c7c4d9867c52 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -4683,22 +4683,20 @@ bool dc_link_is_fec_supported(const struct dc_link 
*link)
 
 bool dc_link_should_enable_fec(const struct dc_link *link)
 {
-   bool is_fec_disable = false;
-   bool ret = false;
+   bool force_disable = false;
 
-   if ((link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT_MST &&
+   if (link->fec_state == dc_link_fec_enabled)
+   force_disable = false;
+   else if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT_MST &&
link->local_sink &&
-   link->local_sink->edid_caps.panel_patch.disable_fec) ||
-   (link->connector_signal == SIGNAL_TYPE_EDP
-   // enable FEC for EDP if DSC is supported
-   && 
link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT == false
-   ))
-   is_fec_disable = true;
-
-   if (dc_link_is_fec_supported(link) && !link->dc->debug.disable_fec && 
!is_fec_disable)
-   ret = true;
-
-   return ret;
+   link->local_sink->edid_caps.panel_patch.disable_fec)
+   force_disable = true;
+   else if (link->connector_signal == SIGNAL_TYPE_EDP
+   && link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.
+dsc_support.DSC_SUPPORT == false)
+   force_disable = true;
+
+   return !force_disable && dc_link_is_fec_supported(link);
 }
 
 uint32_t dc_bandwidth_in_kbps_from_timing(
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index ad757b59e00e..911c5d103c64 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1493,8 +1493,12 @@ void dcn10_init_hw(struct dc *dc)
 
/* Check for enabled DIG to identify enabled display */
if (link->link_enc->funcs->is_dig_enabled &&
-   link->link_enc->funcs->is_dig_enabled(link->link_enc))
+   link->link_enc->funcs->is_dig_enabled(link->link_enc)) {
link->link_status.link_active = true;
+   if (link->link_enc->funcs->fec_is_active &&
+   
link->link_enc->funcs->fec_is_active(link->link_enc))
+   link->fec_state = dc_link_fec_enabled;
+   }
}
 
/* Power gate DSCs */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
index 4be228680909..b57f657c4e44 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
@@ -188,8 +188,12 @@ void dcn31_init_hw(struct dc *dc)
 
/* Check for enabled DIG to identify enabled display */
if (link->link_enc->funcs->is_dig_enabled &&
-   link->link_enc->funcs->is_dig_enabled(link->link_enc))
+   link->link_enc->funcs->is_dig_enabled(link->link_enc)) {
link->link_status.link_active = true;
+   if (link->link_enc->funcs->fec_is_active &&
+   
link->link_enc->funcs->fec_is_active(link->link_enc))
+   link->fec_state = dc_link_fec_enabled;
+   }
}
 
/* Enables outbox notifications for usb4 dpia */
-- 
2.35.1

[PATCH 02/16] drm/amd/display: Remove SW w/a for HDCP 1.4 1A-07 failure based on ECO fix

From: Oliver Logush 

[why]
W/a no longer needed

Reviewed-by: Charlene Liu 
Acked-by: Alex Hung 
Signed-off-by: Oliver Logush 
---
 drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c | 3 +--
 drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c | 3 +--
 2 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
index fadb89326999..e6f9312e3a48 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
@@ -1758,11 +1758,10 @@ static bool dcn315_resource_construct(
pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
dc->caps.max_downscale_ratio = 600;
dc->caps.i2c_speed_in_khz = 100;
-   dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by default*/
+   dc->caps.i2c_speed_in_khz_hdcp = 100;
dc->caps.max_cursor_size = 256;
dc->caps.min_horizontal_blanking_period = 80;
dc->caps.dmdata_alloc_size = 2048;
-
dc->caps.max_slave_planes = 1;
dc->caps.max_slave_yuv_planes = 1;
dc->caps.max_slave_rgb_planes = 1;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c
index d73145dab173..d5c195749a81 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c
@@ -1760,11 +1760,10 @@ static bool dcn316_resource_construct(
pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
dc->caps.max_downscale_ratio = 600;
dc->caps.i2c_speed_in_khz = 100;
-   dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by default*/
+   dc->caps.i2c_speed_in_khz_hdcp = 100;
dc->caps.max_cursor_size = 256;
dc->caps.min_horizontal_blanking_period = 80;
dc->caps.dmdata_alloc_size = 2048;
-
dc->caps.max_slave_planes = 1;
dc->caps.max_slave_yuv_planes = 1;
dc->caps.max_slave_rgb_planes = 1;
-- 
2.35.1

[PATCH 01/16] drm/amd/display: Create underflow interrupt IRQ type

From: Angus Wang 

[WHY]
We want another entry in IRQ type that can be used to
help find the underflow interrupt source.

[HOW]
Added another mapping in IRQ type enum.

Reviewed-by: Jun Lei 
Acked-by: Alex Hung 
Signed-off-by: Angus Wang 
---
 drivers/gpu/drm/amd/display/dc/irq_types.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/display/dc/irq_types.h 
b/drivers/gpu/drm/amd/display/dc/irq_types.h
index 530c2578db40..36d8243cfbff 100644
--- a/drivers/gpu/drm/amd/display/dc/irq_types.h
+++ b/drivers/gpu/drm/amd/display/dc/irq_types.h
@@ -162,6 +162,7 @@ enum irq_type
IRQ_TYPE_VUPDATE = DC_IRQ_SOURCE_VUPDATE1,
IRQ_TYPE_VBLANK = DC_IRQ_SOURCE_VBLANK1,
IRQ_TYPE_VLINE0 = DC_IRQ_SOURCE_DC1_VLINE0,
+   IRQ_TYPE_DCUNDERFLOW = DC_IRQ_SOURCE_DC1UNDERFLOW,
 };
 
 #define DAL_VALID_IRQ_SRC_NUM(src) \
-- 
2.35.1

[PATCH 00/16] DC Patches March 25, 2022

This DC patchset brings improvements in multiple areas. In summary, we 
highlight:

* Fix allocate_mst_payload assert on resume
* [FW Promotion] Release 0.0.110.0
* Revert FEC check in validation
* Update LTTPR UHBR link rate support struct
* Add support for USBC connector
* Add work around for AUX failure on wake
* Clear optc false state when disable otg
* Enable power gating before init_pipes
* Remove redundant dsc power gating from init_hw
* Power down hardware if timer not trigger
* Correct Slice reset calculation
* Enable 3-plane MPO for DCN31
* Set fec register init value
* Remove SW w/a for HDCP 1.4 1A-07 failure based on ECO fix
* Create underflow interrupt IRQ type

Angus Wang (1):
  drm/amd/display: Create underflow interrupt IRQ type

Anthony Koo (1):
  drm/amd/display: [FW Promotion] Release 0.0.110.0

Aric Cyr (1):
  drm/amd/display: 3.2.179

Charlene Liu (1):
  drm/amd/display: Clear optc false state when disable otg

Chris Park (1):
  drm/amd/display: Correct Slice reset calculation

Jimmy Kizito (1):
  drm/amd/display: Add work around for AUX failure on wake.

Jingwen Zhu (1):
  drm/amd/display: Set fec register init value

Krunoslav Kovac (1):
  drm/amd/display: Enable 3-plane MPO for DCN31

Martin Leung (1):
  drm/amd/display: Revert FEC check in validation

Michael Strauss (1):
  drm/amd/display: Update LTTPR UHBR link rate support struct

Oliver Logush (1):
  drm/amd/display: Remove SW w/a for HDCP 1.4 1A-07 failure based on ECO
fix

Paul Hsieh (1):
  drm/amd/display: Power down hardware if timer not trigger

Roman Li (3):
  drm/amd/display: Remove redundant dsc power gating from init_hw
  drm/amd/display: Enable power gating before init_pipes
  drm/amd/display: Fix allocate_mst_payload assert on resume

Samson Tam (1):
  drm/amd/display: Add support for USBC connector

 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  3 +-
 .../amd/display/dc/bios/bios_parser_common.c  |  3 +
 .../drm/amd/display/dc/bios/command_table.c   |  3 +-
 .../display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c  | 26 +-
 drivers/gpu/drm/amd/display/dc/core/dc.c  |  4 -
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 34 +++
 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 59 
 drivers/gpu/drm/amd/display/dc/dc.h   |  2 +-
 drivers/gpu/drm/amd/display/dc/dc_dp_types.h  |  2 +-
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 18 ++--
 .../drm/amd/display/dc/dcn30/dcn30_hwseq.c|  5 +-
 .../drm/amd/display/dc/dcn31/dcn31_hwseq.c| 25 +++---
 .../gpu/drm/amd/display/dc/dcn31/dcn31_optc.c |  5 +-
 .../drm/amd/display/dc/dcn31/dcn31_resource.c |  6 +-
 .../amd/display/dc/dcn315/dcn315_resource.c   |  3 +-
 .../amd/display/dc/dcn316/dcn316_resource.c   |  3 +-
 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c   |  4 +-
 .../gpu/drm/amd/display/dc/inc/dc_link_dp.h   |  1 +
 drivers/gpu/drm/amd/display/dc/irq_types.h|  1 +
 .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h   | 90 +--
 .../drm/amd/display/include/grph_object_id.h  |  1 +
 21 files changed, 155 insertions(+), 143 deletions(-)

-- 
2.35.1

[RFC PATCH] drm/amd/display: dont ignore alpha property

2022-03-25 Thread Melissa Wen

Hi all,

I'm examining the IGT kms_plane_alpha_blend test, specifically the
alpha-7efc. It fails on AMD and Intel gen8 hw, but passes on Intel
gen11. At first, I thought it was a rounding issue. In fact, it may be
the problem for different results between intel hw generations.

However, I changed the test locally to compare CRCs for all alpha values
in the range before the test fails. Interestingly, it fails for all
values when running on AMD, even when comparing planes with zero alpha
(fully transparent). Moreover, I see the same CRC values regardless of
the value set in the alpha property.

To ensure that the blending mode is as expected, I explicitly set the
Pre-multiplied blending mode in the test. Then I tried using different
framebuffer data and alpha values. I've tried obvious comparisons too,
such as fully opaque and fully transparent.

As far as I could verify and understand, the value set for the ALPHA
property is totally ignored by AMD drivers. I'm not sure if this is a
matter of how we interpret the meaning of the premultiplied blend mode
or the driver's assumptions about the data in these blend modes.
For example, I made a change in the test as here:
https://paste.debian.net/1235620/
That basically means same framebuffer, but different alpha values for
each plane. And the result was succesful (but I expected it fails).

Besides that, I see that other subtests in kms_plane_alpha_blend are
skipped, use "None" pixel blend mode, or are not changing the
IGT_PLANE_ALPHA property. So, this alpha-7efc seems to be the only one
in the subset that is checking changes on alpha property under a
Pre-multiplied blend mode, and it is failing.

I see some inputs in this issue:
https://gitlab.freedesktop.org/drm/amd/-/issues/1769.
But them, I guessed there are different interpretations for handling
plane alpha in the pre-multiplied blend mode. Tbh, I'm not clear, but
there's always a chance of different interpretations, and I don't have
a third driver with CRC capabilities for further comparisons.

I made some experiments on blnd_cfg values, changing alpha_mode vs
global_gain and global_alpha. I think the expected behaviour for the
Pre-multiplied blend mode is achieved by applying this RFC patch (for
Cezanne).

Does it seems reasonable? Can anyone help me with more inputs to guide
me the right direction or point out what I misunderstood about these
concepts?

Thanks,

Signed-off-by: Melissa Wen 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c  | 2 +-
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 4 
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 6633df7682ce..821ffafa441e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -5438,7 +5438,7 @@ fill_blending_from_plane_state(const struct 
drm_plane_state *plane_state,
 
if (plane_state->alpha < 0x) {
*global_alpha = true;
-   *global_alpha_value = plane_state->alpha >> 8;
+   *global_alpha_value = plane_state->alpha;
}
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 4290eaf11a04..b4888f91a9d0 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -2367,6 +2367,10 @@ void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx 
*pipe_ctx)
== SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA)
blnd_cfg.pre_multiplied_alpha = false;
 
+   if (blnd_cfg.pre_multiplied_alpha) {
+   blnd_cfg.alpha_mode = 
MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN;
+   blnd_cfg.global_gain = blnd_cfg.global_alpha;
+   }
/*
 * TODO: remove hack
 * Note: currently there is a bug in init_hw such that
-- 
2.35.1



signature.asc
Description: PGP signature

Re: [PATCH 01/13] drm/amd/display: HDCP SEND AKI INIT error

2022-03-25 Thread Hung, Alex

[AMD Official Use Only]

Hi Paul,

Thanks for your feedbacks. I fixed many errors and typos you highlighted in 
this series. In cases where modification requires re-testing we or anyone can 
have follow-up patches in the future.

From: Paul Menzel 
Sent: 19 March 2022 01:16
To: Hung, Alex ; Othman, Ahmad 
Cc: amd-gfx@lists.freedesktop.org ; Wang, 
Chao-kai (Stylon) ; Li, Sun peng (Leo) 
; Wentland, Harry ; Zhuo, Qingqing 
(Lillian) ; Siqueira, Rodrigo 
; Li, Roman ; Chiu, Solomon 
; Pillai, Aurabindo ; Lin, 
Wayne ; Liu, Wenjing ; Lakha, 
Bhawanpreet ; Gutierrez, Agustin 
; Kotarac, Pavle 
Subject: Re: [PATCH 01/13] drm/amd/display: HDCP SEND AKI INIT error

Dear Alex, dear Ahmad,


Thank you for the patch.

Am 18.03.22 um 22:47 schrieb Alex Hung:
> From: Ahmad Othman 

Could you please make the commit message summary/title a statement by
adding a verb (imperative mood) [1]. Maybe:

drm/amd/display: Fix HDCP SEND AKI INIT error

> [why]
> HDCP sends AKI INIT error in case of multiple display on dock

What is the test setup exactly, and how can the error be reproduced?
Does Linux log something?

> [how]
> Added new checks and method to handfle display adjustment

s/Added/Add/
s/handfle/handle/

> for multiple display cases

Why are these checks and methods correct, and what do they try to
achieve? Is it the HDCP(?) specification?

> Reviewed-by: Wenjing Liu 
> Acked-by: Alex Hung 
> Signed-off-by: Ahmad Othman 

Could the order be reversed, so it’s clear that the Signed-off-by line
came first and not after the review? Or is it actually signed off after
the review again?

> ---
>   .../gpu/drm/amd/display/modules/hdcp/hdcp.c   | 38 ++-
>   .../gpu/drm/amd/display/modules/hdcp/hdcp.h   |  8 
>   .../drm/amd/display/modules/inc/mod_hdcp.h|  2 +-
>   3 files changed, 46 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c 
> b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
> index 3e81850a7ffe..5e01c6e24cbc 100644
> --- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
> +++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
> @@ -251,6 +251,33 @@ static enum mod_hdcp_status reset_connection(struct 
> mod_hdcp *hdcp,
>return status;
>   }
>
> +static enum mod_hdcp_status update_display_adjustments(struct mod_hdcp *hdcp,
> + struct mod_hdcp_display *display,
> + struct mod_hdcp_display_adjustment *adj)
> +{
> + enum mod_hdcp_status status = MOD_HDCP_STATUS_NOT_IMPLEMENTED;
> +
> + if (is_in_authenticated_states(hdcp) &&
> + is_dp_mst_hdcp(hdcp) &&
> + display->adjust.disable == true &&
> + adj->disable == false) {
> + display->adjust.disable = false;
> + if (is_hdcp1(hdcp))
> + status = 
> mod_hdcp_hdcp1_enable_dp_stream_encryption(hdcp);
> + else if (is_hdcp2(hdcp))
> + status = 
> mod_hdcp_hdcp2_enable_dp_stream_encryption(hdcp);
> +
> + if (status != MOD_HDCP_STATUS_SUCCESS)
> + display->adjust.disable = true;
> + }
> +
> + if (status == MOD_HDCP_STATUS_SUCCESS &&
> + memcmp(adj, >adjust,
> + sizeof(struct mod_hdcp_display_adjustment)) != 0)
> + status = MOD_HDCP_STATUS_NOT_IMPLEMENTED;
> +
> + return status;
> +}
>   /*
>* Implementation of functions in mod_hdcp.h
>*/
> @@ -391,7 +418,7 @@ enum mod_hdcp_status mod_hdcp_remove_display(struct 
> mod_hdcp *hdcp,
>return status;
>   }
>
> -enum mod_hdcp_status mod_hdcp_update_authentication(struct mod_hdcp *hdcp,
> +enum mod_hdcp_status mod_hdcp_update_display(struct mod_hdcp *hdcp,
>uint8_t index,
>struct mod_hdcp_link_adjustment *link_adjust,
>struct mod_hdcp_display_adjustment *display_adjust,
> @@ -419,6 +446,15 @@ enum mod_hdcp_status 
> mod_hdcp_update_authentication(struct mod_hdcp *hdcp,
>goto out;
>}
>
> + if (memcmp(link_adjust, >connection.link.adjust,
> + sizeof(struct mod_hdcp_link_adjustment)) == 0 &&
> + memcmp(display_adjust, >adjust,
> + sizeof(struct 
> mod_hdcp_display_adjustment)) != 0) {
> + status = update_display_adjustments(hdcp, display, 
> display_adjust);
> + if (status != MOD_HDCP_STATUS_NOT_IMPLEMENTED)
> + goto out;
> + }
> +
>/* stop current authentication */
>status = reset_authentication(hdcp, output);
>if (status != MOD_HDCP_STATUS_SUCCESS)
> diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h 
> b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
> index 399fbca8947b..6b195207de90 100644
> --- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
> +++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
> @@ -445,6 +445,14 @@ static inline

Re: [PATCH] drm/amd/display: Fix pointer dereferenced before checking

Applied both patches.  Thanks!

Alex

On Thu, Mar 24, 2022 at 9:46 AM Haowen Bai  wrote:
>
> The value actual_pix_clk_100Hz is dereferencing pointer pix_clk_params
> before pix_clk_params is being null checked. Fix this by assigning
> pix_clk_params->requested_pix_clk_100hz to actual_pix_clk_100Hz only if
> pix_clk_params is not NULL, otherwise just NULL.
>
> Signed-off-by: Haowen Bai 
> ---
>  drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 
> b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
> index 2c7eb98..4db45bb 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
> +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
> @@ -1162,7 +1162,7 @@ static uint32_t dcn3_get_pix_clk_dividers(
> struct pixel_clk_params *pix_clk_params,
> struct pll_settings *pll_settings)
>  {
> -   unsigned long long actual_pix_clk_100Hz = 
> pix_clk_params->requested_pix_clk_100hz;
> +   unsigned long long actual_pix_clk_100Hz = pix_clk_params ? 
> pix_clk_params->requested_pix_clk_100hz : 0;
> struct dce110_clk_src *clk_src;
>
> clk_src = TO_DCE110_CLK_SRC(cs);
> --
> 2.7.4
>

RE: [PATCH] drm/amdgpu/display: change pipe policy for DCN 2.1

2022-03-25 Thread Wheeler, Daniel

[Public]

I never saw the hang with my testing, not sure if anyone else happened to see 
it. I'm not opposed to including the line.

Thank you,

Dan Wheeler
Technologist  |  AMD
SW Display
--
1 Commerce Valley Dr E, Thornhill, ON L3T 7X6
Facebook |  Twitter |  amd.com  


-Original Message-
From: Alex Deucher  
Sent: March 25, 2022 2:11 PM
To: Benjamin Marty ; Siqueira, Rodrigo 
; Wheeler, Daniel 
Cc: amd-gfx list 
Subject: Re: [PATCH] drm/amdgpu/display: change pipe policy for DCN 2.1

@Wheeler, Daniel
 @Siqueira, Rodrigo were you able to repro this?  Any ideas?  Any downsides to 
picking this up for now?

Alex

On Wed, Mar 23, 2022 at 5:18 PM Benjamin Marty  wrote:
>
> Fixes crash on MST Hub disconnect.
>
> Bug: 
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgitl
> ab.freedesktop.org%2Fdrm%2Famd%2F-%2Fissues%2F1849data=04%7C01%7C
> Daniel.Wheeler%40amd.com%7C21ed4881f6604db48b0208da0e8ae079%7C3dd8961f
> e4884e608e11a82d994e183d%7C0%7C0%7C637838286884708200%7CUnknown%7CTWFp
> bGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn
> 0%3D%7C3000sdata=9cpmXVrAtmDeAe2VMzcgT7%2B%2BYwmwEOb40fLuY7%2F5dJ
> o%3Dreserved=0
> Fixes: ee2698cf79cc ("drm/amd/display: Changed pipe split policy to 
> allow for multi-display pipe split")
> Signed-off-by: Benjamin Marty 
> ---
>  drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 
> b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
> index e5cc6bf45743..ca1bbc942fd4 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
> @@ -873,7 +873,7 @@ static const struct dc_debug_options debug_defaults_drv = 
> {
> .clock_trace = true,
> .disable_pplib_clock_request = true,
> .min_disp_clk_khz = 10,
> -   .pipe_split_policy = MPC_SPLIT_DYNAMIC,
> +   .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
> .force_single_disp_pipe_split = false,
> .disable_dcc = DCC_ENABLE,
> .vsr_support = true,
> --
> 2.35.1
>

[pull] amdgpu, amdkfd drm-next-5.18

Hi Dave, Daniel,

Fixes for 5.18.

The following changes since commit c6e90a1c660874736bd09c1fec6312b4b4c2ff7b:

  Merge tag 'amd-drm-next-5.18-2022-03-18' of 
https://gitlab.freedesktop.org/agd5f/linux into drm-next (2022-03-21 13:48:20 
+1000)

are available in the Git repository at:

  https://gitlab.freedesktop.org/agd5f/linux.git 
tags/amd-drm-next-5.18-2022-03-25

for you to fetch changes up to 15f9cd4334c83716fa32647652a609e3ba6c998d:

  drm/amdgpu/gfx10: enable gfx1037 clock counter retrieval function (2022-03-25 
12:40:25 -0400)


amd-drm-next-5.18-2022-03-25:

amdgpu:
- GFX 10.3.7 fixes
- noretry updates
- VCN fixes
- TMDS fix
- zstate fix for freesync video
- DCN 3.1.5 fix
- Display stack size fix
- Audio fix
- DCN 3.1 pstate fix
- TMZ VCN fix
- APU passthrough fix
- Misc other fixes

amdkfd:
- Error handling fix
- xgmi p2p fix
- HWS VMIDs fix


Alex Deucher (2):
  drm/amdgpu/gmc: use PCI BARs for APUs in passthrough
  drm/amdgpu: add more cases to noretry=1

Aurabindo Pillai (1):
  drm/amd: Add USBC connector ID

Charlene Liu (2):
  drm/amd/display: fix audio format not updated after edid updated
  drm/amd/display: remove destructive verify link for TMDS

Chiawen Huang (1):
  drm/amd/display: FEC check in timing validation

Dan Carpenter (1):
  drm/amdgpu: fix off by one in amdgpu_gfx_kiq_acquire()

Divya Shikre (1):
  drm/amdkfd: Check use_xgmi_p2p before reporting hive_id

Emily Deng (1):
  drm/amdgpu/vcn: Fix the register setting for vcn1

Felix Kuehling (1):
  drm/amdgpu: set noretry=1 for GFX 10.3.4

Gabe Teeger (1):
  drm/amd/display: Add support for zstate during extended vblank

Guchun Chen (2):
  drm/amdgpu: prevent memory wipe in suspend/shutdown stage
  drm/amdgpu: conduct a proper cleanup of PDB bo

Lang Yu (1):
  drm/amdgpu: add workarounds for VCN TMZ issue on CHIP_RAVEN

Leo (Hanghong) Ma (1):
  drm/amd/display: Update VTEM Infopacket definition

Nicholas Kazlauskas (1):
  drm/amd/display: Fix p-state allow debug index on dcn31

Oliver Logush (1):
  drm/amd/display: Add fSMC_MSG_SetDtbClk support

Prike Liang (2):
  drm/amdgpu: set noretry for gfx 10.3.7
  drm/amdgpu/gfx10: enable gfx1037 clock counter retrieval function

QintaoShen (1):
  drm/amdkfd: Check for potential null return of kmalloc_array()

Rodrigo Siqueira (1):
  drm/amd/display: Reduce stack size

Stanley.Yang (1):
  drm/amdgpu/pm: add asic smu support check

Tianci Yin (1):
  drm/amdgpu/vcn: improve vcn dpg stop procedure

Tushar Patel (1):
  drm/amdkfd: Fix Incorrect VMIDs passed to HWS

Yifan Zhang (2):
  drm/amdgpu/pm: fix the Stable pstate Test in amdgpu_test
  drm/amdgpu: set noretry=1 for gc 10.3.6

 drivers/gpu/drm/amd/amdgpu/ObjectID.h  |  1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  4 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c|  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c|  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c|  6 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c |  4 +-
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c |  1 +
 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c |  2 +-
 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c  |  5 +-
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c  |  2 +-
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c  |  4 +-
 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c  | 71 ++
 drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c  |  7 ++-
 drivers/gpu/drm/amd/amdkfd/kfd_device.c| 14 ++---
 drivers/gpu/drm/amd/amdkfd/kfd_events.c|  2 +
 .../drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c | 19 --
 .../drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h |  4 +-
 drivers/gpu/drm/amd/display/dc/core/dc.c   | 23 +++
 drivers/gpu/drm/amd/display/dc/core/dc_link.c  |  3 +-
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c  |  4 +-
 drivers/gpu/drm/amd/display/dc/dc.h|  6 +-
 drivers/gpu/drm/amd/display/dc/dc_stream.h |  2 +
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  |  8 ++-
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 12 
 .../gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.c|  2 +
 drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubp.c  |  8 +++
 .../gpu/drm/amd/display/dc/dcn31/dcn31_resource.c  |  1 +
 .../gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c   | 18 +-
 .../display/dc/dml/dcn31/display_rq_dlg_calc_31.c  | 13 
 .../drm/amd/display/dc/dml/display_mode_structs.h  |  2 +
 drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h   |  3 +
 .../amd/display/modules/info_packet/info_packet.c  |  5 +-
 drivers/gpu/drm/amd/pm/amdgpu_dpm.c|  6 ++
 .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c   |  2 +-
 34 files changed, 229 insertions(+), 39

Re: [PATCH] drm/amdgpu/display: change pipe policy for DCN 2.1

@Wheeler, Daniel
 @Siqueira, Rodrigo were you able to repro this?  Any ideas?  Any
downsides to picking this up for now?

Alex

On Wed, Mar 23, 2022 at 5:18 PM Benjamin Marty  wrote:
>
> Fixes crash on MST Hub disconnect.
>
> Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1849
> Fixes: ee2698cf79cc ("drm/amd/display: Changed pipe split policy to allow for 
> multi-display pipe split")
> Signed-off-by: Benjamin Marty 
> ---
>  drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 
> b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
> index e5cc6bf45743..ca1bbc942fd4 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
> @@ -873,7 +873,7 @@ static const struct dc_debug_options debug_defaults_drv = 
> {
> .clock_trace = true,
> .disable_pplib_clock_request = true,
> .min_disp_clk_khz = 10,
> -   .pipe_split_policy = MPC_SPLIT_DYNAMIC,
> +   .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
> .force_single_disp_pipe_split = false,
> .disable_dcc = DCC_ENABLE,
> .vsr_support = true,
> --
> 2.35.1
>

Re: Commit messages

2022-03-25 Thread Paul Menzel

Dear Christian, dear Daniel, dear Alex,

Am 23.03.22 um 16:32 schrieb Christian König:

Am 23.03.22 um 16:24 schrieb Daniel Stone:

On Wed, 23 Mar 2022 at 15:14, Alex Deucher wrote:
On Wed, Mar 23, 2022 at 11:04 AM Daniel Stone
wrote:

That's not what anyone's saying here ...

No-one's demanding AMD publish RTL, or internal design docs, or
hardware specs, or URLs to JIRA tickets no-one can access.

This is a large and invasive commit with pretty big ramifications;
containing exactly two lines of commit message, one of which just
duplicates the subject.

It cannot be the case that it's completely impossible to provide any
justification, background, or details, about this commit being made.
Unless, of course, it's to fix a non-public security issue, that is
reasonable justification for eliding some of the details. But then
again, 'huge change which is very deliberately opaque' is a really
good way to draw a lot of attention to the commit, and it would be
better to provide more detail about the change to help it slip under
the radar.

If dri-devel@ isn't allowed to inquire about patches which are posted,
then CCing the list is just a façade; might as well just do it all
internally and periodically dump out pull requests.

I think we are in agreement. I think the withheld information
Christian was referring to was on another thread with Christian and
Paul discussing a workaround for a hardware bug:
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.spinics.net%2Flists%2Famd-gfx%2Fmsg75908.htmldata=04%7C01%7Cchristian.koenig%40amd.com%7C6a3f2815d83b4872577008da0ce1347a%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637836458652370599%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000sdata=QtNB0XHMhTgH%2FNHMwF23Qn%2BgSdYyHJSenbpP%2FHG%2BkxE%3Dreserved=0

(Thank you Microsoft for keeping us safe.)

I guess it proves, how assuming what other people should know/have read,
especially when crossing message threads, is causing confusion and
misunderstandings.

Right, that definitely seems like some crossed wires. I don't see
anything wrong with that commit at all: the commit message and a
comment notes that there is a hardware issue preventing Raven from
being able to do TMZ+GTT, and the code does the very straightforward
and obvious thing to ensure that on VCN 1.0, any TMZ buffer must be
VRAM-placed.

My questions were:

Where is that documented, and how can this be reproduced?

Shouldn’t these be answered by the commit message? In five(?) years,
somebody, maybe even with access to the currently non-public documents,
finds a fault in the commit, and would be helped by having an
document/errata number where to look at. To verify the fix, the
developer would need a method to produce the error, so why not just
share it?

Also, I assume that workarounds often come with downsides, as otherwise
it would have been programmed like this from the beginning, or instead
of “workaround” it would be called “improvement”. Shouldn’t that also be
answered?

So totally made-up example:

Currently, there is a graphics corruption running X on system Y. This is
caused by a hardware bug in Raven ASIC (details internal document
#/AMD-Jira #N), and can be worked around by [what is in the commit
message].

The workaround does not affect the performance, and testing X shows the
error is fixed.

This one, on the other hand, is much less clear ...

Yes, completely agree. I mean a good bunch of comments on commit
messages are certainly valid and we could improve them.

That’d be great.

But this patch here was worked on by both AMD and Intel developers.
Where both sides and I think even people from other companies perfectly
understands why, what, how etc...

When now somebody comes along and asks for a whole explanation of the
context why we do it then that sounds really strange to me.

The motivation should be part of the commit message. I didn’t mean
anyone to rewrite buddy memory allocator Wikipedia article [1]. But the
commit message at hand for switching the allocator is definitely too terse.

Kind regards,

Paul

[1]: https://en.wikipedia.org/wiki/Buddy_memory_allocation

Re: [PATCH] drm/amd: Re-classify some log messages in commit path

Thanks.  Fixed up the title when I applied it.

Alex

On Fri, Mar 25, 2022 at 10:55 AM Harry Wentland  wrote:
>
> On 2022-03-24 20:06, Sean Paul wrote:
> > From: Sean Paul 
> >
> > ATOMIC and DRIVER log categories do not typically contain per-frame log
> > messages. This patch re-classifies some messages in amd to chattier
> > categories to keep ATOMIC/DRIVER quiet.
> >
> > Signed-off-by: Sean Paul 
>
> With the subject line fixed as per Christian's comment this is
> Reviewed-by: Harry Wentland 
>
> Harry
>
> > ---
> >  drivers/gpu/drm/amd/amdgpu/amdgpu_display.c   | 5 +++--
> >  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 
> >  2 files changed, 7 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c 
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> > index fae5c1debfad..1fcbab2fd3c3 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> > @@ -113,8 +113,9 @@ static void amdgpu_display_flip_work_func(struct 
> > work_struct *__work)
> >   spin_unlock_irqrestore(>dev->event_lock, flags);
> >
> >
> > - DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_SUBMITTED, 
> > work: %p,\n",
> > -  amdgpu_crtc->crtc_id, amdgpu_crtc, 
> > work);
> > + drm_dbg_vbl(adev_to_drm(adev),
> > + "crtc:%d[%p], pflip_stat:AMDGPU_FLIP_SUBMITTED, work: 
> > %p,\n",
> > + amdgpu_crtc->crtc_id, amdgpu_crtc, work);
> >
> >  }
> >
> > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
> > b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > index b30656959fd8..45d130f86114 100644
> > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > @@ -9248,7 +9248,7 @@ static void amdgpu_dm_commit_planes(struct 
> > drm_atomic_state *state,
> >   >flip_addrs[planes_count].address,
> >   afb->tmz_surface, false);
> >
> > - DRM_DEBUG_ATOMIC("plane: id=%d dcc_en=%d\n",
> > + drm_dbg_state(state->dev, "plane: id=%d dcc_en=%d\n",
> >new_plane_state->plane->index,
> >
> > bundle->plane_infos[planes_count].dcc.enable);
> >
> > @@ -9282,7 +9282,7 @@ static void amdgpu_dm_commit_planes(struct 
> > drm_atomic_state *state,
> >   dc_plane,
> >   
> > bundle->flip_addrs[planes_count].flip_timestamp_in_us);
> >
> > - DRM_DEBUG_ATOMIC("%s Flipping to hi: 0x%x, low: 0x%x\n",
> > + drm_dbg_state(state->dev, "%s Flipping to hi: 0x%x, low: 
> > 0x%x\n",
> >__func__,
> >
> > bundle->flip_addrs[planes_count].address.grph.addr.high_part,
> >
> > bundle->flip_addrs[planes_count].address.grph.addr.low_part);
> > @@ -9624,7 +9624,7 @@ static void amdgpu_dm_atomic_commit_tail(struct 
> > drm_atomic_state *state)
> >   dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
> >   dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
> >
> > - DRM_DEBUG_ATOMIC(
> > + drm_dbg_state(state->dev,
> >   "amdgpu_crtc id:%d crtc_state_flags: enable:%d, 
> > active:%d, "
> >   "planes_changed:%d, 
> > mode_changed:%d,active_changed:%d,"
> >   "connectors_changed:%d\n",
> > @@ -10328,7 +10328,7 @@ static int dm_update_crtc_state(struct 
> > amdgpu_display_manager *dm,
> >   if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
> >   goto skip_modeset;
> >
> > - DRM_DEBUG_ATOMIC(
> > + drm_dbg_state(state->dev,
> >   "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
> >   "planes_changed:%d, mode_changed:%d,active_changed:%d,"
> >   "connectors_changed:%d\n",
>

Re: [PATCH] amdgpu/pm: Enable sysfs node for pp_dpm_vclk for NAVI12

On Fri, Mar 25, 2022 at 10:29 AM Marko Zekovic  wrote:
>
> SMI clock measure API is failing, because sysfs node
> for pp_dpm_vclk is not existing
> Bug:
> https://ontrack-internal.amd.com/browse/SWDEV-327254

Please drop internal bug tickets.  With that fixed, assuming vclk dpm
node is actually supported on navi12,
Acked-by: Alex Deucher 

>
> Signed-off-by: Marko Zekovic 
> ---
>  drivers/gpu/drm/amd/pm/amdgpu_pm.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c 
> b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> index 5cd67ddf84956..095cf57d73de4 100644
> --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> @@ -1999,7 +1999,7 @@ static int default_attr_update(struct amdgpu_device 
> *adev, struct amdgpu_device_
> if (asic_type < CHIP_VEGA12)
> *states = ATTR_STATE_UNSUPPORTED;
> } else if (DEVICE_ATTR_IS(pp_dpm_vclk)) {
> -   if (!(asic_type == CHIP_VANGOGH || asic_type == 
> CHIP_SIENNA_CICHLID))
> +   if (!(asic_type == CHIP_VANGOGH || asic_type == 
> CHIP_SIENNA_CICHLID || asic_type == CHIP_NAVI12))
> *states = ATTR_STATE_UNSUPPORTED;
> } else if (DEVICE_ATTR_IS(pp_dpm_dclk)) {
> if (!(asic_type == CHIP_VANGOGH || asic_type == 
> CHIP_SIENNA_CICHLID))
> --
> 2.24.1.windows.2
>

Re: [PATCH] drm/amd: Re-classify some log messages in commit path

2022-03-25 Thread Harry Wentland

On 2022-03-24 20:06, Sean Paul wrote:
> From: Sean Paul 
> 
> ATOMIC and DRIVER log categories do not typically contain per-frame log
> messages. This patch re-classifies some messages in amd to chattier
> categories to keep ATOMIC/DRIVER quiet.
> 
> Signed-off-by: Sean Paul 

With the subject line fixed as per Christian's comment this is
Reviewed-by: Harry Wentland 

Harry

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_display.c   | 5 +++--
>  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 
>  2 files changed, 7 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> index fae5c1debfad..1fcbab2fd3c3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> @@ -113,8 +113,9 @@ static void amdgpu_display_flip_work_func(struct 
> work_struct *__work)
>   spin_unlock_irqrestore(>dev->event_lock, flags);
>  
>  
> - DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_SUBMITTED, work: 
> %p,\n",
> -  amdgpu_crtc->crtc_id, amdgpu_crtc, 
> work);
> + drm_dbg_vbl(adev_to_drm(adev),
> + "crtc:%d[%p], pflip_stat:AMDGPU_FLIP_SUBMITTED, work: 
> %p,\n",
> + amdgpu_crtc->crtc_id, amdgpu_crtc, work);
>  
>  }
>  
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index b30656959fd8..45d130f86114 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -9248,7 +9248,7 @@ static void amdgpu_dm_commit_planes(struct 
> drm_atomic_state *state,
>   >flip_addrs[planes_count].address,
>   afb->tmz_surface, false);
>  
> - DRM_DEBUG_ATOMIC("plane: id=%d dcc_en=%d\n",
> + drm_dbg_state(state->dev, "plane: id=%d dcc_en=%d\n",
>new_plane_state->plane->index,
>bundle->plane_infos[planes_count].dcc.enable);
>  
> @@ -9282,7 +9282,7 @@ static void amdgpu_dm_commit_planes(struct 
> drm_atomic_state *state,
>   dc_plane,
>   
> bundle->flip_addrs[planes_count].flip_timestamp_in_us);
>  
> - DRM_DEBUG_ATOMIC("%s Flipping to hi: 0x%x, low: 0x%x\n",
> + drm_dbg_state(state->dev, "%s Flipping to hi: 0x%x, low: 
> 0x%x\n",
>__func__,
>
> bundle->flip_addrs[planes_count].address.grph.addr.high_part,
>
> bundle->flip_addrs[planes_count].address.grph.addr.low_part);
> @@ -9624,7 +9624,7 @@ static void amdgpu_dm_atomic_commit_tail(struct 
> drm_atomic_state *state)
>   dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
>   dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
>  
> - DRM_DEBUG_ATOMIC(
> + drm_dbg_state(state->dev,
>   "amdgpu_crtc id:%d crtc_state_flags: enable:%d, 
> active:%d, "
>   "planes_changed:%d, mode_changed:%d,active_changed:%d,"
>   "connectors_changed:%d\n",
> @@ -10328,7 +10328,7 @@ static int dm_update_crtc_state(struct 
> amdgpu_display_manager *dm,
>   if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
>   goto skip_modeset;
>  
> - DRM_DEBUG_ATOMIC(
> + drm_dbg_state(state->dev,
>   "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
>   "planes_changed:%d, mode_changed:%d,active_changed:%d,"
>   "connectors_changed:%d\n",

Re: [PATCH v2 3/25] drm/amdgpu: Disable ABM when AC mode

2022-03-25 Thread Harry Wentland




On 2022-03-25 00:05, Ryan Lin wrote:
> Disable ABM feature when the system is running on AC mode to get
> the more perfect contrast of the display.

It says patch 3 out of 25. Are there other patches? If so, I can't
find them in my mailbox and neither can patchwork
https://patchwork.freedesktop.org/series/101767/
 
> Signed-off-by: Ryan Lin 
> 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c  |  4 ++
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c|  1 +
>  drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c | 58 ---
>  drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h   |  1 +
>  4 files changed, 42 insertions(+), 22 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
> index c560c1ab62ecb..bc8bb9aad2e36 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
> @@ -822,6 +822,10 @@ static int amdgpu_acpi_event(struct notifier_block *nb,
>   struct amdgpu_device *adev = container_of(nb, struct amdgpu_device, 
> acpi_nb);
>   struct acpi_bus_event *entry = (struct acpi_bus_event *)data;
>  
> + if (strcmp(entry->device_class, "battery") == 0) {
> + adev->pm.ac_power = power_supply_is_system_supplied() > 0;
> + }
> +
>   if (strcmp(entry->device_class, ACPI_AC_CLASS) == 0) {
>   if (power_supply_is_system_supplied() > 0)
>   DRM_DEBUG_DRIVER("pm: AC\n");
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index abfcc1304ba0c..3a0afe7602727 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -3454,6 +3454,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
>  
>   adev->gfx.gfx_off_req_count = 1;
>   adev->pm.ac_power = power_supply_is_system_supplied() > 0;
> + adev->pm.old_ac_power = true;
>  
>   atomic_set(>throttling_logging_enabled, 1);
>   /*
> diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c 
> b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
> index 54a1408c8015c..478a734b66926 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
> +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
> @@ -23,6 +23,8 @@
>   *
>   */
>  
> +#include 
> +#include "amdgpu.h"
>  #include "dmub_abm.h"
>  #include "dce_abm.h"
>  #include "dc.h"
> @@ -51,6 +53,7 @@
>  #define DISABLE_ABM_IMMEDIATELY 255
>  
>  
> +extern uint amdgpu_dm_abm_level;
>  
>  static void dmub_abm_enable_fractional_pwm(struct dc_context *dc)
>  {
> @@ -117,28 +120,6 @@ static void dmub_abm_init(struct abm *abm, uint32_t 
> backlight)
>   dmub_abm_enable_fractional_pwm(abm->ctx);
>  }
>  
> -static unsigned int dmub_abm_get_current_backlight(struct abm *abm)
> -{
> - struct dce_abm *dce_abm = TO_DMUB_ABM(abm);
> - unsigned int backlight = REG_READ(BL1_PWM_CURRENT_ABM_LEVEL);
> -
> - /* return backlight in hardware format which is unsigned 17 bits, with
> -  * 1 bit integer and 16 bit fractional
> -  */
> - return backlight;
> -}
> -
> -static unsigned int dmub_abm_get_target_backlight(struct abm *abm)
> -{
> - struct dce_abm *dce_abm = TO_DMUB_ABM(abm);
> - unsigned int backlight = REG_READ(BL1_PWM_TARGET_ABM_LEVEL);
> -
> - /* return backlight in hardware format which is unsigned 17 bits, with
> -  * 1 bit integer and 16 bit fractional
> -  */
> - return backlight;
> -}
> -
>  static bool dmub_abm_set_level(struct abm *abm, uint32_t level)
>  {
>   union dmub_rb_cmd cmd;
> @@ -148,6 +129,9 @@ static bool dmub_abm_set_level(struct abm *abm, uint32_t 
> level)
>   int edp_num;
>   uint8_t panel_mask = 0;
>  
> + if (power_supply_is_system_supplied() > 0)
> + level = 0;
> +
>   get_edp_links(dc->dc, edp_links, _num);
>  
>   for (i = 0; i < edp_num; i++) {
> @@ -170,6 +154,36 @@ static bool dmub_abm_set_level(struct abm *abm, uint32_t 
> level)
>   return true;
>  }
>  
> +static unsigned int dmub_abm_get_current_backlight(struct abm *abm)
> +{
> + struct dce_abm *dce_abm = TO_DMUB_ABM(abm);
> + unsigned int backlight = REG_READ(BL1_PWM_CURRENT_ABM_LEVEL);
> + struct dc_context *dc = abm->ctx;
> + struct amdgpu_device *adev = dc->driver_context;
> +
> + if (adev->pm.ac_power != adev->pm.old_ac_power) {

This file lives in DC, which is shared code between Windows and Linux. We
cannot directly use adev here. Any information needs to go through DC structs.

I seem to remember someone saying that ABM gets disabled on Windows when
we're in AC mode. Have you checked with our Windows guys about this? I feel
we're re-inventing the wheel here for no good reason.

Harry

> + dmub_abm_set_level(abm, amdgpu_dm_abm_level);
> + adev->pm.ac_power = power_supply_is_system_supplied() > 0;
> + adev->pm.old_ac_power = adev->pm.ac_power;
> + }
> +
> + /* return backlight

[PATCH] amdgpu/pm: Enable sysfs node for pp_dpm_vclk for NAVI12

2022-03-25 Thread Marko Zekovic

SMI clock measure API is failing, because sysfs node
for pp_dpm_vclk is not existing
Bug:
https://ontrack-internal.amd.com/browse/SWDEV-327254

Signed-off-by: Marko Zekovic 
---
 drivers/gpu/drm/amd/pm/amdgpu_pm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c 
b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index 5cd67ddf84956..095cf57d73de4 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -1999,7 +1999,7 @@ static int default_attr_update(struct amdgpu_device 
*adev, struct amdgpu_device_
if (asic_type < CHIP_VEGA12)
*states = ATTR_STATE_UNSUPPORTED;
} else if (DEVICE_ATTR_IS(pp_dpm_vclk)) {
-   if (!(asic_type == CHIP_VANGOGH || asic_type == 
CHIP_SIENNA_CICHLID))
+   if (!(asic_type == CHIP_VANGOGH || asic_type == 
CHIP_SIENNA_CICHLID || asic_type == CHIP_NAVI12))
*states = ATTR_STATE_UNSUPPORTED;
} else if (DEVICE_ATTR_IS(pp_dpm_dclk)) {
if (!(asic_type == CHIP_VANGOGH || asic_type == 
CHIP_SIENNA_CICHLID))
-- 
2.24.1.windows.2

Re: [PATCH] drm/amdgpu: fix some kerneldoc in the VM code

On Fri, Mar 25, 2022 at 5:41 AM Christian König
 wrote:
>
> Fix two incorrect kerneldocs for the recent VM code changes.
>
> Signed-off-by: Christian König 
> Reported-by: kernel test robot 
> Reported-by: Stephen Rothwell 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c| 2 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c | 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index 48f326609976..fa4def290dec 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -89,7 +89,7 @@ struct amdgpu_prt_cb {
>  };
>
>  /**
> - * amdgpu_vm_tlb_seq_cb - Helper to increment the TLB flush sequence
> + * struct amdgpu_vm_tlb_seq_cb - Helper to increment the TLB flush sequence
>   */
>  struct amdgpu_vm_tlb_seq_cb {
> /**
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
> index a821ada5f8ca..ecd8a3d60803 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
> @@ -620,7 +620,7 @@ static int amdgpu_vm_pt_alloc(struct amdgpu_device *adev,
>  }
>
>  /**
> - * amdgpu_vm_free_table - fre one PD/PT
> + * amdgpu_vm_pt_free - fre one PD/PT

typo: fre -> free
With that fixed:
Reviewed-by: Alex Deucher 

>   *
>   * @entry: PDE to free
>   */
> --
> 2.25.1
>

Re: [PATCH] drm/amd/pm: Check feature support using IP version

2022-03-25 Thread Lazar, Lijo





On 3/25/2022 4:55 PM, Wang, Yang(Kevin) wrote:

[AMD Official Use Only]


    if (adev->asic_type > CHIP_VEGA20) {
+   if (gc_ver != IP_VERSION(9, 4, 0) && mp1_ver > IP_VERSION(9, 0, 
0)) {

  /* VCN clocks */
[kevin]:

please put some comments here (why mp1_ver and gc_ver is needed both), 
it can help developer to understand some backgrounds.

thanks.



Sure, will add them. > VEGA_20 includes RAVEN whose GC and MP1 IP 
versions are lesser than VG20. For clarity, I will add something like > 
VEG20 supports this.


Thanks,
Lijo


Reviewed-by: Kevin Wang 
Best Regards,
Kevin

*From:* Lazar, Lijo 
*Sent:* Friday, March 25, 2022 4:31 PM
*To:* amd-gfx@lists.freedesktop.org 
*Cc:* Zhang, Hawking ; Deucher, Alexander 
; Wang, Yang(Kevin) ; 
Quan, Evan 

*Subject:* [PATCH] drm/amd/pm: Check feature support using IP version
Instead of ASIC type, use GC and MP1 IP versions for feature support checks.

Signed-off-by: Lijo Lazar 
---
  drivers/gpu/drm/amd/pm/amdgpu_pm.c | 72 --
  1 file changed, 39 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c 
b/drivers/gpu/drm/amd/pm/amdgpu_pm.c

index 5cd67ddf8495..f89e0ff3f5a4 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -1954,8 +1954,9 @@ static int default_attr_update(struct 
amdgpu_device *adev, struct amdgpu_device_
     uint32_t mask, enum 
amdgpu_device_attr_states *states)

  {
  struct device_attribute *dev_attr = >dev_attr;
+   uint32_t mp1_ver = adev->ip_versions[MP1_HWIP][0];
+   uint32_t gc_ver = adev->ip_versions[GC_HWIP][0];
  const char *attr_name = dev_attr->attr.name;
-   enum amd_asic_type asic_type = adev->asic_type;

  if (!(attr->flags & mask)) {
  *states = ATTR_STATE_UNSUPPORTED;
@@ -1965,53 +1966,55 @@ static int default_attr_update(struct 
amdgpu_device *adev, struct amdgpu_device_

  #define DEVICE_ATTR_IS(_name)   (!strcmp(attr_name, #_name))

  if (DEVICE_ATTR_IS(pp_dpm_socclk)) {
-   if (asic_type < CHIP_VEGA10)
+   if (gc_ver < IP_VERSION(9, 0, 0))
  *states = ATTR_STATE_UNSUPPORTED;
  } else if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) {
-   if (asic_type < CHIP_VEGA10 ||
-   asic_type == CHIP_ARCTURUS ||
-   asic_type == CHIP_ALDEBARAN)
+   if (gc_ver < IP_VERSION(9, 0, 0) ||
+   gc_ver == IP_VERSION(9, 4, 1) ||
+   gc_ver == IP_VERSION(9, 4, 2))
  *states = ATTR_STATE_UNSUPPORTED;
  } else if (DEVICE_ATTR_IS(pp_dpm_fclk)) {
-   if (asic_type < CHIP_VEGA20)
+   if (mp1_ver < IP_VERSION(10, 0, 0))
  *states = ATTR_STATE_UNSUPPORTED;
  } else if (DEVICE_ATTR_IS(pp_od_clk_voltage)) {
  *states = ATTR_STATE_UNSUPPORTED;
  if (amdgpu_dpm_is_overdrive_supported(adev))
  *states = ATTR_STATE_SUPPORTED;
  } else if (DEVICE_ATTR_IS(mem_busy_percent)) {
-   if (adev->flags & AMD_IS_APU || asic_type == CHIP_VEGA10)
+   if (adev->flags & AMD_IS_APU || gc_ver == IP_VERSION(9, 
0, 1))

  *states = ATTR_STATE_UNSUPPORTED;
  } else if (DEVICE_ATTR_IS(pcie_bw)) {
  /* PCIe Perf counters won't work on APU nodes */
  if (adev->flags & AMD_IS_APU)
  *states = ATTR_STATE_UNSUPPORTED;
  } else if (DEVICE_ATTR_IS(unique_id)) {
-   if (asic_type != CHIP_VEGA10 &&
-   asic_type != CHIP_VEGA20 &&
-   asic_type != CHIP_ARCTURUS &&
-   asic_type != CHIP_ALDEBARAN)
+   if (gc_ver != IP_VERSION(9, 0, 1) &&
+   gc_ver != IP_VERSION(9, 4, 0) &&
+   gc_ver != IP_VERSION(9, 4, 1) &&
+   gc_ver != IP_VERSION(9, 4, 2))
  *states = ATTR_STATE_UNSUPPORTED;
  } else if (DEVICE_ATTR_IS(pp_features)) {
-   if (adev->flags & AMD_IS_APU || asic_type < CHIP_VEGA10)
+   if (adev->flags & AMD_IS_APU || gc_ver < IP_VERSION(9, 
0, 0))

  *states = ATTR_STATE_UNSUPPORTED;
  } else if (DEVICE_ATTR_IS(gpu_metrics)) {
-   if (asic_type < CHIP_VEGA12)
+   if (gc_ver < IP_VERSION(9, 1, 0))
  *states = ATTR_STATE_UNSUPPORTED;
  } else if (DEVICE_ATTR_IS(pp_dpm_vclk)) {
-   if (!(asic_type == CHIP_VANGOGH || asic_type == 
CHIP_SIENNA_CICHLID))

+   if (!(gc_ver == IP_VERSION(10, 3, 1) ||
+ gc_ver == IP_VERSION(10, 3, 0)))
  *states = ATTR_STATE_UNSUPPORTED;
  } else if

Re: [PATCH] drm/amdgpu: Add unique_id support for sienna cichlid

On Fri, Mar 25, 2022 at 9:05 AM Kent Russell  wrote:
>
> This is being added to SMU Metrics, so add the required tie-ins in the
> kernel. Also create the corresponding unique_id sysfs file.
>
> v2: Add FW version check, remove SMU mutex
>
> Signed-off-by: Kent Russell 
> ---
>  drivers/gpu/drm/amd/pm/amdgpu_pm.c|  3 +-
>  .../pmfw_if/smu11_driver_if_sienna_cichlid.h  | 12 +--
>  .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c   | 35 +++
>  3 files changed, 47 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c 
> b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> index 5cd67ddf8495..1ed13bf77cbc 100644
> --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> @@ -1990,7 +1990,8 @@ static int default_attr_update(struct amdgpu_device 
> *adev, struct amdgpu_device_
> if (asic_type != CHIP_VEGA10 &&
> asic_type != CHIP_VEGA20 &&
> asic_type != CHIP_ARCTURUS &&
> -   asic_type != CHIP_ALDEBARAN)
> +   asic_type != CHIP_ALDEBARAN &&
> +   asic_type != CHIP_SIENNA_CICHLID)

As a follow on or precursor patch, we should convert this to IP
version checks.  Also, you may want to switch the logic here and mark
the attr as supported only if it matches one of the chips that
supports it.

Alex


> *states = ATTR_STATE_UNSUPPORTED;
> } else if (DEVICE_ATTR_IS(pp_features)) {
> if (adev->flags & AMD_IS_APU || asic_type < CHIP_VEGA10)
> diff --git 
> a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h 
> b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h
> index 3e4a314ef925..58f977320d06 100644
> --- 
> a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h
> +++ 
> b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h
> @@ -1419,8 +1419,12 @@ typedef struct {
>uint8_t  PcieRate   ;
>uint8_t  PcieWidth  ;
>uint16_t AverageGfxclkFrequencyTarget;
> -  uint16_t Padding16_2;
>
> +  //PMFW-8711
> +  uint32_t PublicSerialNumLower32;
> +  uint32_t PublicSerialNumUpper32;
> +
> +  uint16_t Padding16_2;
>  } SmuMetrics_t;
>
>  typedef struct {
> @@ -1476,8 +1480,12 @@ typedef struct {
>uint8_t  PcieRate   ;
>uint8_t  PcieWidth  ;
>uint16_t AverageGfxclkFrequencyTarget;
> -  uint16_t Padding16_2;
>
> +  //PMFW-8711
> +  uint32_t PublicSerialNumLower32;
> +  uint32_t PublicSerialNumUpper32;
> +
> +  uint16_t Padding16_2;
>  } SmuMetrics_V2_t;
>
>  typedef struct {
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c 
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> index 38f04836c82f..39d12bc6daaa 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> @@ -481,6 +481,40 @@ static int sienna_cichlid_setup_pptable(struct 
> smu_context *smu)
> return sienna_cichlid_patch_pptable_quirk(smu);
>  }
>
> +static void sienna_cichlid_get_unique_id(struct smu_context *smu)
> +{
> +   struct amdgpu_device *adev = smu->adev;
> +   struct smu_table_context *smu_table = >smu_table;
> +   SmuMetrics_t *metrics =
> +   &(((SmuMetricsExternal_t 
> *)(smu_table->metrics_table))->SmuMetrics);
> +   SmuMetrics_V2_t *metrics_v2 =
> +   &(((SmuMetricsExternal_t 
> *)(smu_table->metrics_table))->SmuMetrics_V2);
> +   uint32_t upper32 = 0, lower32 = 0;
> +   int ret;
> +
> +   /* Only supported as of version 0.58.83.0 */
> +   if (smu->smc_fw_version < 0x3A5300)
> +   return;
> +
> +   ret = smu_cmn_get_metrics_table_locked(smu, NULL, false);
> +   if (ret)
> +   goto out_unlock;
> +
> +   bool use_metrics_v2 = ((smu->adev->ip_versions[MP1_HWIP][0] == 
> IP_VERSION(11, 0, 7)) &&
> +   (smu->smc_fw_version >= 0x3A4300)) ? true : false;
> +
> +   upper32 = use_metrics_v2 ? metrics_v2->PublicSerialNumUpper32 :
> +  metrics->PublicSerialNumUpper32;
> +   lower32 = use_metrics_v2 ? metrics_v2->PublicSerialNumLower32 :
> +  metrics->PublicSerialNumLower32;
> +
> +out_unlock:
> +
> +   adev->unique_id = ((uint64_t)upper32 << 32) | lower32;
> +   if (adev->serial[0] == '\0')
> +   sprintf(adev->serial, "%016llx", adev->unique_id);
> +}
> +
>  static int sienna_cichlid_tables_init(struct smu_context *smu)
>  {
> struct smu_table_context *smu_table = >smu_table;
> @@ -4182,6 +4216,7 @@ static const struct pptable_funcs 
> sienna_cichlid_ppt_funcs = {
> .get_ecc_info = sienna_cichlid_get_ecc_info,
> .get_default_config_table_settings = 
> sienna_cichlid_get_default_config_table_settings,
> .set_config_table =

RE: [PATCH] drm/amdgpu: Add unique_id support for sienna cichlid

2022-03-25 Thread Russell, Kent

[AMD Official Use Only]

> -Original Message-
> From: Alex Deucher 
> Sent: Friday, March 25, 2022 9:26 AM
> To: Russell, Kent 
> Cc: amd-gfx list 
> Subject: Re: [PATCH] drm/amdgpu: Add unique_id support for sienna cichlid
>
> On Fri, Mar 25, 2022 at 9:05 AM Kent Russell  wrote:
> >
> > This is being added to SMU Metrics, so add the required tie-ins in the
> > kernel. Also create the corresponding unique_id sysfs file.
> >
> > v2: Add FW version check, remove SMU mutex
> >
> > Signed-off-by: Kent Russell 
> > ---
> >  drivers/gpu/drm/amd/pm/amdgpu_pm.c|  3 +-
> >  .../pmfw_if/smu11_driver_if_sienna_cichlid.h  | 12 +--
> >  .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c   | 35 +++
> >  3 files changed, 47 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> > index 5cd67ddf8495..1ed13bf77cbc 100644
> > --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> > +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> > @@ -1990,7 +1990,8 @@ static int default_attr_update(struct amdgpu_device 
> > *adev,
> struct amdgpu_device_
> > if (asic_type != CHIP_VEGA10 &&
> > asic_type != CHIP_VEGA20 &&
> > asic_type != CHIP_ARCTURUS &&
> > -   asic_type != CHIP_ALDEBARAN)
> > +   asic_type != CHIP_ALDEBARAN &&
> > +   asic_type != CHIP_SIENNA_CICHLID)
>
> As a follow on or precursor patch, we should convert this to IP
> version checks.  Also, you may want to switch the logic here and mark
> the attr as supported only if it matches one of the chips that
> supports it.

I can make the change now. Evan liked the logic before, just requesting a mutex 
drop and a version check, so I can do that now since I think he's probably done 
for the day. Thanks for the recommendation!

 Kent


>
> Alex
>
>
> > *states = ATTR_STATE_UNSUPPORTED;
> > } else if (DEVICE_ATTR_IS(pp_features)) {
> > if (adev->flags & AMD_IS_APU || asic_type < CHIP_VEGA10)
> > diff --git
> a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h
> b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h
> > index 3e4a314ef925..58f977320d06 100644
> > --- 
> > a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h
> > +++ 
> > b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h
> > @@ -1419,8 +1419,12 @@ typedef struct {
> >uint8_t  PcieRate   ;
> >uint8_t  PcieWidth  ;
> >uint16_t AverageGfxclkFrequencyTarget;
> > -  uint16_t Padding16_2;
> >
> > +  //PMFW-8711
> > +  uint32_t PublicSerialNumLower32;
> > +  uint32_t PublicSerialNumUpper32;
> > +
> > +  uint16_t Padding16_2;
> >  } SmuMetrics_t;
> >
> >  typedef struct {
> > @@ -1476,8 +1480,12 @@ typedef struct {
> >uint8_t  PcieRate   ;
> >uint8_t  PcieWidth  ;
> >uint16_t AverageGfxclkFrequencyTarget;
> > -  uint16_t Padding16_2;
> >
> > +  //PMFW-8711
> > +  uint32_t PublicSerialNumLower32;
> > +  uint32_t PublicSerialNumUpper32;
> > +
> > +  uint16_t Padding16_2;
> >  } SmuMetrics_V2_t;
> >
> >  typedef struct {
> > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > index 38f04836c82f..39d12bc6daaa 100644
> > --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > @@ -481,6 +481,40 @@ static int sienna_cichlid_setup_pptable(struct 
> > smu_context
> *smu)
> > return sienna_cichlid_patch_pptable_quirk(smu);
> >  }
> >
> > +static void sienna_cichlid_get_unique_id(struct smu_context *smu)
> > +{
> > +   struct amdgpu_device *adev = smu->adev;
> > +   struct smu_table_context *smu_table = >smu_table;
> > +   SmuMetrics_t *metrics =
> > +   &(((SmuMetricsExternal_t 
> > *)(smu_table->metrics_table))->SmuMetrics);
> > +   SmuMetrics_V2_t *metrics_v2 =
> > +   &(((SmuMetricsExternal_t 
> > *)(smu_table->metrics_table))->SmuMetrics_V2);
> > +   uint32_t upper32 = 0, lower32 = 0;
> > +   int ret;
> > +
> > +   /* Only supported as of version 0.58.83.0 */
> > +   if (smu->smc_fw_version < 0x3A5300)
> > +   return;
> > +
> > +   ret = smu_cmn_get_metrics_table_locked(smu, NULL, false);
> > +   if (ret)
> > +   goto out_unlock;
> > +
> > +   bool use_metrics_v2 = ((smu->adev->ip_versions[MP1_HWIP][0] == 
> > IP_VERSION(11,
> 0, 7)) &&
> > +   (smu->smc_fw_version >= 0x3A4300)) ? true : false;
> > +
> > +   upper32 = use_metrics_v2 ? metrics_v2->PublicSerialNumUpper32 :
> > +  metrics->PublicSerialNumUpper32;
> > +   lower32 = use_metrics_v2 ? metrics_v2->PublicSerialNumLower32 :
> > +

Re: [PATCH v2 3/25] drm/amdgpu: Disable ABM when AC mode

On Fri, Mar 25, 2022 at 2:27 AM Ryan Lin  wrote:
>
> Disable ABM feature when the system is running on AC mode to get
> the more perfect contrast of the display.
>
> Signed-off-by: Ryan Lin 
>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c  |  4 ++
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c|  1 +
>  drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c | 58 ---
>  drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h   |  1 +
>  4 files changed, 42 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
> index c560c1ab62ecb..bc8bb9aad2e36 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
> @@ -822,6 +822,10 @@ static int amdgpu_acpi_event(struct notifier_block *nb,
> struct amdgpu_device *adev = container_of(nb, struct amdgpu_device, 
> acpi_nb);
> struct acpi_bus_event *entry = (struct acpi_bus_event *)data;
>
> +   if (strcmp(entry->device_class, "battery") == 0) {
> +   adev->pm.ac_power = power_supply_is_system_supplied() > 0;
> +   }
> +

We already set adev->pm.ac_power in amdgpu_pm_acpi_event_handler()
which gets called a few lines below.

Alex


> if (strcmp(entry->device_class, ACPI_AC_CLASS) == 0) {
> if (power_supply_is_system_supplied() > 0)
> DRM_DEBUG_DRIVER("pm: AC\n");
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index abfcc1304ba0c..3a0afe7602727 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -3454,6 +3454,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
>
> adev->gfx.gfx_off_req_count = 1;
> adev->pm.ac_power = power_supply_is_system_supplied() > 0;
> +   adev->pm.old_ac_power = true;
>
> atomic_set(>throttling_logging_enabled, 1);
> /*
> diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c 
> b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
> index 54a1408c8015c..478a734b66926 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
> +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
> @@ -23,6 +23,8 @@
>   *
>   */
>
> +#include 
> +#include "amdgpu.h"
>  #include "dmub_abm.h"
>  #include "dce_abm.h"
>  #include "dc.h"
> @@ -51,6 +53,7 @@
>  #define DISABLE_ABM_IMMEDIATELY 255
>
>
> +extern uint amdgpu_dm_abm_level;
>
>  static void dmub_abm_enable_fractional_pwm(struct dc_context *dc)
>  {
> @@ -117,28 +120,6 @@ static void dmub_abm_init(struct abm *abm, uint32_t 
> backlight)
> dmub_abm_enable_fractional_pwm(abm->ctx);
>  }
>
> -static unsigned int dmub_abm_get_current_backlight(struct abm *abm)
> -{
> -   struct dce_abm *dce_abm = TO_DMUB_ABM(abm);
> -   unsigned int backlight = REG_READ(BL1_PWM_CURRENT_ABM_LEVEL);
> -
> -   /* return backlight in hardware format which is unsigned 17 bits, with
> -* 1 bit integer and 16 bit fractional
> -*/
> -   return backlight;
> -}
> -
> -static unsigned int dmub_abm_get_target_backlight(struct abm *abm)
> -{
> -   struct dce_abm *dce_abm = TO_DMUB_ABM(abm);
> -   unsigned int backlight = REG_READ(BL1_PWM_TARGET_ABM_LEVEL);
> -
> -   /* return backlight in hardware format which is unsigned 17 bits, with
> -* 1 bit integer and 16 bit fractional
> -*/
> -   return backlight;
> -}
> -
>  static bool dmub_abm_set_level(struct abm *abm, uint32_t level)
>  {
> union dmub_rb_cmd cmd;
> @@ -148,6 +129,9 @@ static bool dmub_abm_set_level(struct abm *abm, uint32_t 
> level)
> int edp_num;
> uint8_t panel_mask = 0;
>
> +   if (power_supply_is_system_supplied() > 0)
> +   level = 0;
> +
> get_edp_links(dc->dc, edp_links, _num);
>
> for (i = 0; i < edp_num; i++) {
> @@ -170,6 +154,36 @@ static bool dmub_abm_set_level(struct abm *abm, uint32_t 
> level)
> return true;
>  }
>
> +static unsigned int dmub_abm_get_current_backlight(struct abm *abm)
> +{
> +   struct dce_abm *dce_abm = TO_DMUB_ABM(abm);
> +   unsigned int backlight = REG_READ(BL1_PWM_CURRENT_ABM_LEVEL);
> +   struct dc_context *dc = abm->ctx;
> +   struct amdgpu_device *adev = dc->driver_context;
> +
> +   if (adev->pm.ac_power != adev->pm.old_ac_power) {
> +   dmub_abm_set_level(abm, amdgpu_dm_abm_level);
> +   adev->pm.ac_power = power_supply_is_system_supplied() > 0;
> +   adev->pm.old_ac_power = adev->pm.ac_power;
> +   }
> +
> +   /* return backlight in hardware format which is unsigned 17 bits, with
> +* 1 bit integer and 16 bit fractional
> +*/
> +   return backlight;
> +}
> +
> +static unsigned int dmub_abm_get_target_backlight(struct abm *abm)
> +{
> +   struct dce_abm *dce_abm = TO_DMUB_ABM(abm);
> +   unsigned int backlight =

[PATCH] drm/amdgpu: Add unique_id support for sienna cichlid

2022-03-25 Thread Kent Russell

This is being added to SMU Metrics, so add the required tie-ins in the
kernel. Also create the corresponding unique_id sysfs file.

v2: Add FW version check, remove SMU mutex

Signed-off-by: Kent Russell 
---
 drivers/gpu/drm/amd/pm/amdgpu_pm.c|  3 +-
 .../pmfw_if/smu11_driver_if_sienna_cichlid.h  | 12 +--
 .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c   | 35 +++
 3 files changed, 47 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c 
b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index 5cd67ddf8495..1ed13bf77cbc 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -1990,7 +1990,8 @@ static int default_attr_update(struct amdgpu_device 
*adev, struct amdgpu_device_
if (asic_type != CHIP_VEGA10 &&
asic_type != CHIP_VEGA20 &&
asic_type != CHIP_ARCTURUS &&
-   asic_type != CHIP_ALDEBARAN)
+   asic_type != CHIP_ALDEBARAN &&
+   asic_type != CHIP_SIENNA_CICHLID)
*states = ATTR_STATE_UNSUPPORTED;
} else if (DEVICE_ATTR_IS(pp_features)) {
if (adev->flags & AMD_IS_APU || asic_type < CHIP_VEGA10)
diff --git 
a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h 
b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h
index 3e4a314ef925..58f977320d06 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h
@@ -1419,8 +1419,12 @@ typedef struct {
   uint8_t  PcieRate   ;
   uint8_t  PcieWidth  ;
   uint16_t AverageGfxclkFrequencyTarget;
-  uint16_t Padding16_2;
 
+  //PMFW-8711
+  uint32_t PublicSerialNumLower32;
+  uint32_t PublicSerialNumUpper32;
+
+  uint16_t Padding16_2;
 } SmuMetrics_t;
 
 typedef struct {
@@ -1476,8 +1480,12 @@ typedef struct {
   uint8_t  PcieRate   ;
   uint8_t  PcieWidth  ;
   uint16_t AverageGfxclkFrequencyTarget;
-  uint16_t Padding16_2;
 
+  //PMFW-8711
+  uint32_t PublicSerialNumLower32;
+  uint32_t PublicSerialNumUpper32;
+
+  uint16_t Padding16_2;
 } SmuMetrics_V2_t;
 
 typedef struct {
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 38f04836c82f..39d12bc6daaa 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -481,6 +481,40 @@ static int sienna_cichlid_setup_pptable(struct smu_context 
*smu)
return sienna_cichlid_patch_pptable_quirk(smu);
 }
 
+static void sienna_cichlid_get_unique_id(struct smu_context *smu)
+{
+   struct amdgpu_device *adev = smu->adev;
+   struct smu_table_context *smu_table = >smu_table;
+   SmuMetrics_t *metrics =
+   &(((SmuMetricsExternal_t 
*)(smu_table->metrics_table))->SmuMetrics);
+   SmuMetrics_V2_t *metrics_v2 =
+   &(((SmuMetricsExternal_t 
*)(smu_table->metrics_table))->SmuMetrics_V2);
+   uint32_t upper32 = 0, lower32 = 0;
+   int ret;
+
+   /* Only supported as of version 0.58.83.0 */
+   if (smu->smc_fw_version < 0x3A5300)
+   return;
+
+   ret = smu_cmn_get_metrics_table_locked(smu, NULL, false);
+   if (ret)
+   goto out_unlock;
+
+   bool use_metrics_v2 = ((smu->adev->ip_versions[MP1_HWIP][0] == 
IP_VERSION(11, 0, 7)) &&
+   (smu->smc_fw_version >= 0x3A4300)) ? true : false;
+
+   upper32 = use_metrics_v2 ? metrics_v2->PublicSerialNumUpper32 :
+  metrics->PublicSerialNumUpper32;
+   lower32 = use_metrics_v2 ? metrics_v2->PublicSerialNumLower32 :
+  metrics->PublicSerialNumLower32;
+
+out_unlock:
+
+   adev->unique_id = ((uint64_t)upper32 << 32) | lower32;
+   if (adev->serial[0] == '\0')
+   sprintf(adev->serial, "%016llx", adev->unique_id);
+}
+
 static int sienna_cichlid_tables_init(struct smu_context *smu)
 {
struct smu_table_context *smu_table = >smu_table;
@@ -4182,6 +4216,7 @@ static const struct pptable_funcs 
sienna_cichlid_ppt_funcs = {
.get_ecc_info = sienna_cichlid_get_ecc_info,
.get_default_config_table_settings = 
sienna_cichlid_get_default_config_table_settings,
.set_config_table = sienna_cichlid_set_config_table,
+   .get_unique_id = sienna_cichlid_get_unique_id,
 };
 
 void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
-- 
2.25.1

Re: [PATCH] drm/amd/pm: Check feature support using IP version

2022-03-25 Thread Wang, Yang(Kevin)

[AMD Official Use Only]

   if (adev->asic_type > CHIP_VEGA20) {
+   if (gc_ver != IP_VERSION(9, 4, 0) && mp1_ver > IP_VERSION(9, 0, 0)) {
 /* VCN clocks */
[kevin]:

please put some comments here (why mp1_ver and gc_ver is needed both), it can 
help developer to understand some backgrounds.
thanks.

Reviewed-by: Kevin Wang 

Best Regards,
Kevin

From: Lazar, Lijo 
Sent: Friday, March 25, 2022 4:31 PM
To: amd-gfx@lists.freedesktop.org 
Cc: Zhang, Hawking ; Deucher, Alexander 
; Wang, Yang(Kevin) ; Quan, 
Evan 
Subject: [PATCH] drm/amd/pm: Check feature support using IP version

Instead of ASIC type, use GC and MP1 IP versions for feature support checks.

Signed-off-by: Lijo Lazar 
---
 drivers/gpu/drm/amd/pm/amdgpu_pm.c | 72 --
 1 file changed, 39 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c 
b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index 5cd67ddf8495..f89e0ff3f5a4 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -1954,8 +1954,9 @@ static int default_attr_update(struct amdgpu_device 
*adev, struct amdgpu_device_
uint32_t mask, enum amdgpu_device_attr_states 
*states)
 {
 struct device_attribute *dev_attr = >dev_attr;
+   uint32_t mp1_ver = adev->ip_versions[MP1_HWIP][0];
+   uint32_t gc_ver = adev->ip_versions[GC_HWIP][0];
 const char *attr_name = dev_attr->attr.name;
-   enum amd_asic_type asic_type = adev->asic_type;

 if (!(attr->flags & mask)) {
 *states = ATTR_STATE_UNSUPPORTED;
@@ -1965,53 +1966,55 @@ static int default_attr_update(struct amdgpu_device 
*adev, struct amdgpu_device_
 #define DEVICE_ATTR_IS(_name)   (!strcmp(attr_name, #_name))

 if (DEVICE_ATTR_IS(pp_dpm_socclk)) {
-   if (asic_type < CHIP_VEGA10)
+   if (gc_ver < IP_VERSION(9, 0, 0))
 *states = ATTR_STATE_UNSUPPORTED;
 } else if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) {
-   if (asic_type < CHIP_VEGA10 ||
-   asic_type == CHIP_ARCTURUS ||
-   asic_type == CHIP_ALDEBARAN)
+   if (gc_ver < IP_VERSION(9, 0, 0) ||
+   gc_ver == IP_VERSION(9, 4, 1) ||
+   gc_ver == IP_VERSION(9, 4, 2))
 *states = ATTR_STATE_UNSUPPORTED;
 } else if (DEVICE_ATTR_IS(pp_dpm_fclk)) {
-   if (asic_type < CHIP_VEGA20)
+   if (mp1_ver < IP_VERSION(10, 0, 0))
 *states = ATTR_STATE_UNSUPPORTED;
 } else if (DEVICE_ATTR_IS(pp_od_clk_voltage)) {
 *states = ATTR_STATE_UNSUPPORTED;
 if (amdgpu_dpm_is_overdrive_supported(adev))
 *states = ATTR_STATE_SUPPORTED;
 } else if (DEVICE_ATTR_IS(mem_busy_percent)) {
-   if (adev->flags & AMD_IS_APU || asic_type == CHIP_VEGA10)
+   if (adev->flags & AMD_IS_APU || gc_ver == IP_VERSION(9, 0, 1))
 *states = ATTR_STATE_UNSUPPORTED;
 } else if (DEVICE_ATTR_IS(pcie_bw)) {
 /* PCIe Perf counters won't work on APU nodes */
 if (adev->flags & AMD_IS_APU)
 *states = ATTR_STATE_UNSUPPORTED;
 } else if (DEVICE_ATTR_IS(unique_id)) {
-   if (asic_type != CHIP_VEGA10 &&
-   asic_type != CHIP_VEGA20 &&
-   asic_type != CHIP_ARCTURUS &&
-   asic_type != CHIP_ALDEBARAN)
+   if (gc_ver != IP_VERSION(9, 0, 1) &&
+   gc_ver != IP_VERSION(9, 4, 0) &&
+   gc_ver != IP_VERSION(9, 4, 1) &&
+   gc_ver != IP_VERSION(9, 4, 2))
 *states = ATTR_STATE_UNSUPPORTED;
 } else if (DEVICE_ATTR_IS(pp_features)) {
-   if (adev->flags & AMD_IS_APU || asic_type < CHIP_VEGA10)
+   if (adev->flags & AMD_IS_APU || gc_ver < IP_VERSION(9, 0, 0))
 *states = ATTR_STATE_UNSUPPORTED;
 } else if (DEVICE_ATTR_IS(gpu_metrics)) {
-   if (asic_type < CHIP_VEGA12)
+   if (gc_ver < IP_VERSION(9, 1, 0))
 *states = ATTR_STATE_UNSUPPORTED;
 } else if (DEVICE_ATTR_IS(pp_dpm_vclk)) {
-   if (!(asic_type == CHIP_VANGOGH || asic_type == 
CHIP_SIENNA_CICHLID))
+   if (!(gc_ver == IP_VERSION(10, 3, 1) ||
+ gc_ver == IP_VERSION(10, 3, 0)))
 *states = ATTR_STATE_UNSUPPORTED;
 } else if (DEVICE_ATTR_IS(pp_dpm_dclk)) {
-   if (!(asic_type == CHIP_VANGOGH || asic_type == 
CHIP_SIENNA_CICHLID))
+   if (!(gc_ver == IP_VERSION(10, 3, 1) ||
+ gc_ver == IP_VERSION(10, 3, 0)))
 *states = ATTR_STATE_UNSUPPORTED;
 } else if

Re: [PATCH v2 3/25] drm/amdgpu: Disable ABM when AC mode


Am 25.03.22 um 10:49 schrieb Daniel Vetter:

On Fri, Mar 25, 2022 at 08:22:29AM +0100, Christian König wrote:

Hi Ryan,

we should try to avoid that and if it isn't possible at least use some
constant like ACPI_AC_CLASS.

Could be that the information isn't available otherwise. Alex should know
more about that.

I wonder whether we shouldn't need a more dedicated notification from acpi
for power supply events instead of stitching this together ourselves. At
least this kind of stuff feels more into the policy/tuning territory where
a bit more careful interfaces might be good instead of just "hey there's
this very funny acpi protocol we just have to take part in to not upset
the hw/fw".


That is pretty much my thinking as well.

A quick grep shows that both amdgpu, radeon, nouveau and i915 all parse 
the same information with self defined macros and strcmp(). That's not 
really the way we usually do stuff like this.


Ideally the ACPI layer in the core kernel would parse the information 
and give it as enum or flags to the drivers instead.


At bare minimum we should move all the ACPI_AC_CLASS, ACPI_VIDEO_CLASS 
and raw strings into a common place to start with.


Regards,
Christian.


-Daniel


Regards,
Christian.

Am 25.03.22 um 08:09 schrieb Lin, Tsung-hua (Ryan):

[AMD Official Use Only]

Hi Christian,

There is already a string comparison in the same function. I just reference 
that to port this solution.



#define ACPI_AC_CLASS   "ac_adapter"


static int amdgpu_acpi_event(struct notifier_block *nb,
 unsigned long val,
 void *data)
{
struct amdgpu_device *adev = container_of(nb, struct amdgpu_device, 
acpi_nb);
struct acpi_bus_event *entry = (struct acpi_bus_event *)data;

+   if (strcmp(entry->device_class, "battery") == 0) {
+   adev->pm.ac_power = power_supply_is_system_supplied() > 0;
+   }

if (strcmp(entry->device_class, ACPI_AC_CLASS) == 0) {  
<---here!
if (power_supply_is_system_supplied() > 0)
DRM_DEBUG_DRIVER("pm: AC\n");
else
DRM_DEBUG_DRIVER("pm: DC\n");

amdgpu_pm_acpi_event_handler(adev);
}

/* Check for pending SBIOS requests */
return amdgpu_atif_handler(adev, entry);
}

Thanks,
Ryan Lin.

-Original Message-
From: Koenig, Christian 
Sent: Friday, March 25, 2022 2:58 PM
To: Lin, Tsung-hua (Ryan) ; Wentland, Harry ; Li, Sun peng 
(Leo) ; Deucher, Alexander ; david1.z...@amd.com; 
airl...@linux.ie; dan...@ffwll.ch; seanp...@chromium.org; b...@basnieuwenhuizen.nl; Kazlauskas, Nicholas 
; sas...@kernel.org; markyac...@google.com; victorchengchi...@amd.com; 
ching-shih...@amd.corp-partner.google.com; Siqueira, Rodrigo ; ddavenp...@chromium.org; 
amd-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org; linux-ker...@vger.kernel.org; Li, Leon 

Subject: Re: [PATCH v2 3/25] drm/amdgpu: Disable ABM when AC mode

Am 25.03.22 um 05:05 schrieb Ryan Lin:

Disable ABM feature when the system is running on AC mode to get the
more perfect contrast of the display.

Signed-off-by: Ryan Lin 

---
drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c  |  4 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c|  1 +
drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c | 58 ---
drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h   |  1 +
4 files changed, 42 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
index c560c1ab62ecb..bc8bb9aad2e36 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
@@ -822,6 +822,10 @@ static int amdgpu_acpi_event(struct notifier_block *nb,
struct amdgpu_device *adev = container_of(nb, struct amdgpu_device, 
acpi_nb);
struct acpi_bus_event *entry = (struct acpi_bus_event *)data;
+   if (strcmp(entry->device_class, "battery") == 0) {

String comparison in a hot path is not something we usually like to see in the 
kernel.

Isn't there any other way to detect that? Like a flag or similar?

Regards,
Christian.


+   adev->pm.ac_power = power_supply_is_system_supplied() > 0;
+   }
+
if (strcmp(entry->device_class, ACPI_AC_CLASS) == 0) {
if (power_supply_is_system_supplied() > 0)
DRM_DEBUG_DRIVER("pm: AC\n");
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index abfcc1304ba0c..3a0afe7602727 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3454,6 +3454,7 @@ int amdgpu_device_init(struct amdgpu_device
*adev,
adev->gfx.gfx_off_req_count = 1;
adev->pm.ac_power = power_supply_is_system_supplied() > 0;
+   adev->pm.old_ac_power = true;
atomic_set(>throttling_logging_enabled, 1);

Re: [PATCH v2 3/25] drm/amdgpu: Disable ABM when AC mode

2022-03-25 Thread Daniel Vetter

On Fri, Mar 25, 2022 at 08:22:29AM +0100, Christian König wrote:
> Hi Ryan,
> 
> we should try to avoid that and if it isn't possible at least use some
> constant like ACPI_AC_CLASS.
> 
> Could be that the information isn't available otherwise. Alex should know
> more about that.

I wonder whether we shouldn't need a more dedicated notification from acpi
for power supply events instead of stitching this together ourselves. At
least this kind of stuff feels more into the policy/tuning territory where
a bit more careful interfaces might be good instead of just "hey there's
this very funny acpi protocol we just have to take part in to not upset
the hw/fw".
-Daniel

> 
> Regards,
> Christian.
> 
> Am 25.03.22 um 08:09 schrieb Lin, Tsung-hua (Ryan):
> > [AMD Official Use Only]
> > 
> > Hi Christian,
> > 
> > There is already a string comparison in the same function. I just reference 
> > that to port this solution.
> > 
> > 
> > 
> > #define ACPI_AC_CLASS   "ac_adapter"
> > 
> > 
> > static int amdgpu_acpi_event(struct notifier_block *nb,
> >  unsigned long val,
> >  void *data)
> > {
> > struct amdgpu_device *adev = container_of(nb, struct amdgpu_device, 
> > acpi_nb);
> > struct acpi_bus_event *entry = (struct acpi_bus_event *)data;
> > 
> > +   if (strcmp(entry->device_class, "battery") == 0) {
> > +   adev->pm.ac_power = power_supply_is_system_supplied() > 0;
> > +   }
> > 
> > if (strcmp(entry->device_class, ACPI_AC_CLASS) == 0) {  
> > <---here!
> > if (power_supply_is_system_supplied() > 0)
> > DRM_DEBUG_DRIVER("pm: AC\n");
> > else
> > DRM_DEBUG_DRIVER("pm: DC\n");
> > 
> > amdgpu_pm_acpi_event_handler(adev);
> > }
> > 
> > /* Check for pending SBIOS requests */
> > return amdgpu_atif_handler(adev, entry);
> > }
> > 
> > Thanks,
> > Ryan Lin.
> > 
> > -Original Message-
> > From: Koenig, Christian 
> > Sent: Friday, March 25, 2022 2:58 PM
> > To: Lin, Tsung-hua (Ryan) ; Wentland, Harry 
> > ; Li, Sun peng (Leo) ; Deucher, 
> > Alexander ; david1.z...@amd.com; 
> > airl...@linux.ie; dan...@ffwll.ch; seanp...@chromium.org; 
> > b...@basnieuwenhuizen.nl; Kazlauskas, Nicholas 
> > ; sas...@kernel.org; markyac...@google.com; 
> > victorchengchi...@amd.com; ching-shih...@amd.corp-partner.google.com; 
> > Siqueira, Rodrigo ; ddavenp...@chromium.org; 
> > amd-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org; 
> > linux-ker...@vger.kernel.org; Li, Leon 
> > Subject: Re: [PATCH v2 3/25] drm/amdgpu: Disable ABM when AC mode
> > 
> > Am 25.03.22 um 05:05 schrieb Ryan Lin:
> > > Disable ABM feature when the system is running on AC mode to get the
> > > more perfect contrast of the display.
> > > 
> > > Signed-off-by: Ryan Lin 
> > > 
> > > ---
> > >drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c  |  4 ++
> > >drivers/gpu/drm/amd/amdgpu/amdgpu_device.c|  1 +
> > >drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c | 58 ---
> > >drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h   |  1 +
> > >4 files changed, 42 insertions(+), 22 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
> > > b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
> > > index c560c1ab62ecb..bc8bb9aad2e36 100644
> > > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
> > > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
> > > @@ -822,6 +822,10 @@ static int amdgpu_acpi_event(struct notifier_block 
> > > *nb,
> > >   struct amdgpu_device *adev = container_of(nb, struct 
> > > amdgpu_device, acpi_nb);
> > >   struct acpi_bus_event *entry = (struct acpi_bus_event *)data;
> > > + if (strcmp(entry->device_class, "battery") == 0) {
> > String comparison in a hot path is not something we usually like to see in 
> > the kernel.
> > 
> > Isn't there any other way to detect that? Like a flag or similar?
> > 
> > Regards,
> > Christian.
> > 
> > > + adev->pm.ac_power = power_supply_is_system_supplied() > 0;
> > > + }
> > > +
> > >   if (strcmp(entry->device_class, ACPI_AC_CLASS) == 0) {
> > >   if (power_supply_is_system_supplied() > 0)
> > >   DRM_DEBUG_DRIVER("pm: AC\n");
> > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > > b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > > index abfcc1304ba0c..3a0afe7602727 100644
> > > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > > @@ -3454,6 +3454,7 @@ int amdgpu_device_init(struct amdgpu_device
> > > *adev,
> > >   adev->gfx.gfx_off_req_count = 1;
> > >   adev->pm.ac_power = power_supply_is_system_supplied() > 0;
> > > + adev->pm.old_ac_power = true;
> > >   atomic_set(>throttling_logging_enabled, 1);
> > >   /*
> > > diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
> > >

[PATCH] drm/amdgpu: fix some kerneldoc in the VM code

Fix two incorrect kerneldocs for the recent VM code changes.

Signed-off-by: Christian König 
Reported-by: kernel test robot 
Reported-by: Stephen Rothwell 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c| 2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 48f326609976..fa4def290dec 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -89,7 +89,7 @@ struct amdgpu_prt_cb {
 };
 
 /**
- * amdgpu_vm_tlb_seq_cb - Helper to increment the TLB flush sequence
+ * struct amdgpu_vm_tlb_seq_cb - Helper to increment the TLB flush sequence
  */
 struct amdgpu_vm_tlb_seq_cb {
/**
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
index a821ada5f8ca..ecd8a3d60803 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
@@ -620,7 +620,7 @@ static int amdgpu_vm_pt_alloc(struct amdgpu_device *adev,
 }
 
 /**
- * amdgpu_vm_free_table - fre one PD/PT
+ * amdgpu_vm_pt_free - fre one PD/PT
  *
  * @entry: PDE to free
  */
-- 
2.25.1

[PATCH] drm/amd/pm: Check feature support using IP version

2022-03-25 Thread Lijo Lazar

Instead of ASIC type, use GC and MP1 IP versions for feature support checks.

Signed-off-by: Lijo Lazar 
---
 drivers/gpu/drm/amd/pm/amdgpu_pm.c | 72 --
 1 file changed, 39 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c 
b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index 5cd67ddf8495..f89e0ff3f5a4 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -1954,8 +1954,9 @@ static int default_attr_update(struct amdgpu_device 
*adev, struct amdgpu_device_
   uint32_t mask, enum amdgpu_device_attr_states 
*states)
 {
struct device_attribute *dev_attr = >dev_attr;
+   uint32_t mp1_ver = adev->ip_versions[MP1_HWIP][0];
+   uint32_t gc_ver = adev->ip_versions[GC_HWIP][0];
const char *attr_name = dev_attr->attr.name;
-   enum amd_asic_type asic_type = adev->asic_type;
 
if (!(attr->flags & mask)) {
*states = ATTR_STATE_UNSUPPORTED;
@@ -1965,53 +1966,55 @@ static int default_attr_update(struct amdgpu_device 
*adev, struct amdgpu_device_
 #define DEVICE_ATTR_IS(_name)  (!strcmp(attr_name, #_name))
 
if (DEVICE_ATTR_IS(pp_dpm_socclk)) {
-   if (asic_type < CHIP_VEGA10)
+   if (gc_ver < IP_VERSION(9, 0, 0))
*states = ATTR_STATE_UNSUPPORTED;
} else if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) {
-   if (asic_type < CHIP_VEGA10 ||
-   asic_type == CHIP_ARCTURUS ||
-   asic_type == CHIP_ALDEBARAN)
+   if (gc_ver < IP_VERSION(9, 0, 0) ||
+   gc_ver == IP_VERSION(9, 4, 1) ||
+   gc_ver == IP_VERSION(9, 4, 2))
*states = ATTR_STATE_UNSUPPORTED;
} else if (DEVICE_ATTR_IS(pp_dpm_fclk)) {
-   if (asic_type < CHIP_VEGA20)
+   if (mp1_ver < IP_VERSION(10, 0, 0))
*states = ATTR_STATE_UNSUPPORTED;
} else if (DEVICE_ATTR_IS(pp_od_clk_voltage)) {
*states = ATTR_STATE_UNSUPPORTED;
if (amdgpu_dpm_is_overdrive_supported(adev))
*states = ATTR_STATE_SUPPORTED;
} else if (DEVICE_ATTR_IS(mem_busy_percent)) {
-   if (adev->flags & AMD_IS_APU || asic_type == CHIP_VEGA10)
+   if (adev->flags & AMD_IS_APU || gc_ver == IP_VERSION(9, 0, 1))
*states = ATTR_STATE_UNSUPPORTED;
} else if (DEVICE_ATTR_IS(pcie_bw)) {
/* PCIe Perf counters won't work on APU nodes */
if (adev->flags & AMD_IS_APU)
*states = ATTR_STATE_UNSUPPORTED;
} else if (DEVICE_ATTR_IS(unique_id)) {
-   if (asic_type != CHIP_VEGA10 &&
-   asic_type != CHIP_VEGA20 &&
-   asic_type != CHIP_ARCTURUS &&
-   asic_type != CHIP_ALDEBARAN)
+   if (gc_ver != IP_VERSION(9, 0, 1) &&
+   gc_ver != IP_VERSION(9, 4, 0) &&
+   gc_ver != IP_VERSION(9, 4, 1) &&
+   gc_ver != IP_VERSION(9, 4, 2))
*states = ATTR_STATE_UNSUPPORTED;
} else if (DEVICE_ATTR_IS(pp_features)) {
-   if (adev->flags & AMD_IS_APU || asic_type < CHIP_VEGA10)
+   if (adev->flags & AMD_IS_APU || gc_ver < IP_VERSION(9, 0, 0))
*states = ATTR_STATE_UNSUPPORTED;
} else if (DEVICE_ATTR_IS(gpu_metrics)) {
-   if (asic_type < CHIP_VEGA12)
+   if (gc_ver < IP_VERSION(9, 1, 0))
*states = ATTR_STATE_UNSUPPORTED;
} else if (DEVICE_ATTR_IS(pp_dpm_vclk)) {
-   if (!(asic_type == CHIP_VANGOGH || asic_type == 
CHIP_SIENNA_CICHLID))
+   if (!(gc_ver == IP_VERSION(10, 3, 1) ||
+ gc_ver == IP_VERSION(10, 3, 0)))
*states = ATTR_STATE_UNSUPPORTED;
} else if (DEVICE_ATTR_IS(pp_dpm_dclk)) {
-   if (!(asic_type == CHIP_VANGOGH || asic_type == 
CHIP_SIENNA_CICHLID))
+   if (!(gc_ver == IP_VERSION(10, 3, 1) ||
+ gc_ver == IP_VERSION(10, 3, 0)))
*states = ATTR_STATE_UNSUPPORTED;
} else if (DEVICE_ATTR_IS(pp_power_profile_mode)) {
if (amdgpu_dpm_get_power_profile_mode(adev, NULL) == 
-EOPNOTSUPP)
*states = ATTR_STATE_UNSUPPORTED;
}
 
-   switch (asic_type) {
-   case CHIP_ARCTURUS:
-   case CHIP_ALDEBARAN:
+   switch (gc_ver) {
+   case IP_VERSION(9, 4, 1):
+   case IP_VERSION(9, 4, 2):
/* the Mi series card does not support standalone 
mclk/socclk/fclk level setting */
if (DEVICE_ATTR_IS(pp_dpm_mclk) ||
DEVICE_ATTR_IS(pp_dpm_socclk) ||
@@ -2026,7 +2029,7 @@ static int default_attr_update(struct amdgpu_device 
*adev, struct amdgpu_device_
 
if

Re: [PATCH] drm/amd: Re-classify some log messages in commit path


Am 25.03.22 um 01:06 schrieb Sean Paul:

From: Sean Paul 

ATOMIC and DRIVER log categories do not typically contain per-frame log
messages. This patch re-classifies some messages in amd to chattier
categories to keep ATOMIC/DRIVER quiet.

Signed-off-by: Sean Paul 


Please use drm/amdgpu for the subject line in the future, apart from 
that looks like a really clean patch to me.


Feel free to add an Acked-by: Christian König 


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_display.c   | 5 +++--
  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 
  2 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index fae5c1debfad..1fcbab2fd3c3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -113,8 +113,9 @@ static void amdgpu_display_flip_work_func(struct 
work_struct *__work)
spin_unlock_irqrestore(>dev->event_lock, flags);
  
  
-	DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_SUBMITTED, work: %p,\n",

-amdgpu_crtc->crtc_id, amdgpu_crtc, 
work);
+   drm_dbg_vbl(adev_to_drm(adev),
+   "crtc:%d[%p], pflip_stat:AMDGPU_FLIP_SUBMITTED, work: 
%p,\n",
+   amdgpu_crtc->crtc_id, amdgpu_crtc, work);
  
  }
  
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

index b30656959fd8..45d130f86114 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -9248,7 +9248,7 @@ static void amdgpu_dm_commit_planes(struct 
drm_atomic_state *state,
>flip_addrs[planes_count].address,
afb->tmz_surface, false);
  
-		DRM_DEBUG_ATOMIC("plane: id=%d dcc_en=%d\n",

+   drm_dbg_state(state->dev, "plane: id=%d dcc_en=%d\n",
 new_plane_state->plane->index,
 bundle->plane_infos[planes_count].dcc.enable);
  
@@ -9282,7 +9282,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,

dc_plane,

bundle->flip_addrs[planes_count].flip_timestamp_in_us);
  
-		DRM_DEBUG_ATOMIC("%s Flipping to hi: 0x%x, low: 0x%x\n",

+   drm_dbg_state(state->dev, "%s Flipping to hi: 0x%x, low: 
0x%x\n",
 __func__,
 
bundle->flip_addrs[planes_count].address.grph.addr.high_part,
 
bundle->flip_addrs[planes_count].address.grph.addr.low_part);
@@ -9624,7 +9624,7 @@ static void amdgpu_dm_atomic_commit_tail(struct 
drm_atomic_state *state)
dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
  
-		DRM_DEBUG_ATOMIC(

+   drm_dbg_state(state->dev,
"amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, 
"
"planes_changed:%d, mode_changed:%d,active_changed:%d,"
"connectors_changed:%d\n",
@@ -10328,7 +10328,7 @@ static int dm_update_crtc_state(struct 
amdgpu_display_manager *dm,
if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
goto skip_modeset;
  
-	DRM_DEBUG_ATOMIC(

+   drm_dbg_state(state->dev,
"amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
"planes_changed:%d, mode_changed:%d,active_changed:%d,"
"connectors_changed:%d\n",

Re: [PATCH] drm/amdkfd: fix comparison warning with min() macro





Am 24.03.22 um 22:31 schrieb Alex Deucher:

Properly case to u32 to fix the warning.

Fixes: 83f1287c57228f ("drm/amdkfd: Fix Incorrect VMIDs passed to HWS")
Signed-off-by: Alex Deucher 
---
  drivers/gpu/drm/amd/amdkfd/kfd_device.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index d70f787369a0..62aa6c9d5123 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -484,7 +484,7 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd,
  
  	/* Verify module parameters regarding mapped process number*/

if (hws_max_conc_proc >= 0)
-   kfd->max_proc_per_quantum = min(hws_max_conc_proc, 
kfd->vm_info.vmid_num_kfd);
+   kfd->max_proc_per_quantum = min((u32)hws_max_conc_proc, 
kfd->vm_info.vmid_num_kfd);


You could use min_t() her instead of the manual casting.

Christian.


else
kfd->max_proc_per_quantum = kfd->vm_info.vmid_num_kfd;

Re: [PATCH v2 3/25] drm/amdgpu: Disable ABM when AC mode


Hi Ryan,

we should try to avoid that and if it isn't possible at least use some 
constant like ACPI_AC_CLASS.


Could be that the information isn't available otherwise. Alex should 
know more about that.


Regards,
Christian.

Am 25.03.22 um 08:09 schrieb Lin, Tsung-hua (Ryan):

[AMD Official Use Only]

Hi Christian,

There is already a string comparison in the same function. I just reference 
that to port this solution.



#define ACPI_AC_CLASS   "ac_adapter"


static int amdgpu_acpi_event(struct notifier_block *nb,
 unsigned long val,
 void *data)
{
struct amdgpu_device *adev = container_of(nb, struct amdgpu_device, 
acpi_nb);
struct acpi_bus_event *entry = (struct acpi_bus_event *)data;

+   if (strcmp(entry->device_class, "battery") == 0) {
+   adev->pm.ac_power = power_supply_is_system_supplied() > 0;
+   }

if (strcmp(entry->device_class, ACPI_AC_CLASS) == 0) {  
<---here!
if (power_supply_is_system_supplied() > 0)
DRM_DEBUG_DRIVER("pm: AC\n");
else
DRM_DEBUG_DRIVER("pm: DC\n");

amdgpu_pm_acpi_event_handler(adev);
}

/* Check for pending SBIOS requests */
return amdgpu_atif_handler(adev, entry);
}

Thanks,
Ryan Lin.

-Original Message-
From: Koenig, Christian 
Sent: Friday, March 25, 2022 2:58 PM
To: Lin, Tsung-hua (Ryan) ; Wentland, Harry ; Li, Sun peng 
(Leo) ; Deucher, Alexander ; david1.z...@amd.com; 
airl...@linux.ie; dan...@ffwll.ch; seanp...@chromium.org; b...@basnieuwenhuizen.nl; Kazlauskas, Nicholas 
; sas...@kernel.org; markyac...@google.com; victorchengchi...@amd.com; 
ching-shih...@amd.corp-partner.google.com; Siqueira, Rodrigo ; ddavenp...@chromium.org; 
amd-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org; linux-ker...@vger.kernel.org; Li, Leon 

Subject: Re: [PATCH v2 3/25] drm/amdgpu: Disable ABM when AC mode

Am 25.03.22 um 05:05 schrieb Ryan Lin:

Disable ABM feature when the system is running on AC mode to get the
more perfect contrast of the display.

Signed-off-by: Ryan Lin 

---
   drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c  |  4 ++
   drivers/gpu/drm/amd/amdgpu/amdgpu_device.c|  1 +
   drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c | 58 ---
   drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h   |  1 +
   4 files changed, 42 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
index c560c1ab62ecb..bc8bb9aad2e36 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
@@ -822,6 +822,10 @@ static int amdgpu_acpi_event(struct notifier_block *nb,
struct amdgpu_device *adev = container_of(nb, struct amdgpu_device, 
acpi_nb);
struct acpi_bus_event *entry = (struct acpi_bus_event *)data;
   
+	if (strcmp(entry->device_class, "battery") == 0) {

String comparison in a hot path is not something we usually like to see in the 
kernel.

Isn't there any other way to detect that? Like a flag or similar?

Regards,
Christian.


+   adev->pm.ac_power = power_supply_is_system_supplied() > 0;
+   }
+
if (strcmp(entry->device_class, ACPI_AC_CLASS) == 0) {
if (power_supply_is_system_supplied() > 0)
DRM_DEBUG_DRIVER("pm: AC\n");
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index abfcc1304ba0c..3a0afe7602727 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3454,6 +3454,7 @@ int amdgpu_device_init(struct amdgpu_device
*adev,
   
   	adev->gfx.gfx_off_req_count = 1;

adev->pm.ac_power = power_supply_is_system_supplied() > 0;
+   adev->pm.old_ac_power = true;
   
   	atomic_set(>throttling_logging_enabled, 1);

/*
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
index 54a1408c8015c..478a734b66926 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
@@ -23,6 +23,8 @@
*
*/
   
+#include 

+#include "amdgpu.h"
   #include "dmub_abm.h"
   #include "dce_abm.h"
   #include "dc.h"
@@ -51,6 +53,7 @@
   #define DISABLE_ABM_IMMEDIATELY 255
   
   
+extern uint amdgpu_dm_abm_level;
   
   static void dmub_abm_enable_fractional_pwm(struct dc_context *dc)

   {
@@ -117,28 +120,6 @@ static void dmub_abm_init(struct abm *abm, uint32_t 
backlight)
dmub_abm_enable_fractional_pwm(abm->ctx);
   }
   
-static unsigned int dmub_abm_get_current_backlight(struct abm *abm)

-{
-   struct dce_abm *dce_abm = TO_DMUB_ABM(abm);
-   unsigned int backlight = REG_READ(BL1_PWM_CURRENT_ABM_LEVEL);
-
-   /* return backlight in hardware format which is unsigned 17 bits, with
-* 1

RE: [PATCH v2 3/25] drm/amdgpu: Disable ABM when AC mode

2022-03-25 Thread Lin, Tsung-hua (Ryan)

[AMD Official Use Only]

Hi Christian,

There is already a string comparison in the same function. I just reference 
that to port this solution.



#define ACPI_AC_CLASS   "ac_adapter"


static int amdgpu_acpi_event(struct notifier_block *nb,
 unsigned long val,
 void *data)
{
struct amdgpu_device *adev = container_of(nb, struct amdgpu_device, 
acpi_nb);
struct acpi_bus_event *entry = (struct acpi_bus_event *)data;

+   if (strcmp(entry->device_class, "battery") == 0) {
+   adev->pm.ac_power = power_supply_is_system_supplied() > 0;
+   }

if (strcmp(entry->device_class, ACPI_AC_CLASS) == 0) {  
<---here!
if (power_supply_is_system_supplied() > 0)
DRM_DEBUG_DRIVER("pm: AC\n");
else
DRM_DEBUG_DRIVER("pm: DC\n");

amdgpu_pm_acpi_event_handler(adev);
}

/* Check for pending SBIOS requests */
return amdgpu_atif_handler(adev, entry);
}

Thanks,
Ryan Lin.

-Original Message-
From: Koenig, Christian  
Sent: Friday, March 25, 2022 2:58 PM
To: Lin, Tsung-hua (Ryan) ; Wentland, Harry 
; Li, Sun peng (Leo) ; Deucher, 
Alexander ; david1.z...@amd.com; airl...@linux.ie; 
dan...@ffwll.ch; seanp...@chromium.org; b...@basnieuwenhuizen.nl; Kazlauskas, 
Nicholas ; sas...@kernel.org; 
markyac...@google.com; victorchengchi...@amd.com; 
ching-shih...@amd.corp-partner.google.com; Siqueira, Rodrigo 
; ddavenp...@chromium.org; 
amd-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org; 
linux-ker...@vger.kernel.org; Li, Leon 
Subject: Re: [PATCH v2 3/25] drm/amdgpu: Disable ABM when AC mode

Am 25.03.22 um 05:05 schrieb Ryan Lin:
> Disable ABM feature when the system is running on AC mode to get the 
> more perfect contrast of the display.
>
> Signed-off-by: Ryan Lin 
>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c  |  4 ++
>   drivers/gpu/drm/amd/amdgpu/amdgpu_device.c|  1 +
>   drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c | 58 ---
>   drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h   |  1 +
>   4 files changed, 42 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
> index c560c1ab62ecb..bc8bb9aad2e36 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
> @@ -822,6 +822,10 @@ static int amdgpu_acpi_event(struct notifier_block *nb,
>   struct amdgpu_device *adev = container_of(nb, struct amdgpu_device, 
> acpi_nb);
>   struct acpi_bus_event *entry = (struct acpi_bus_event *)data;
>   
> + if (strcmp(entry->device_class, "battery") == 0) {

String comparison in a hot path is not something we usually like to see in the 
kernel.

Isn't there any other way to detect that? Like a flag or similar?

Regards,
Christian.

> + adev->pm.ac_power = power_supply_is_system_supplied() > 0;
> + }
> +
>   if (strcmp(entry->device_class, ACPI_AC_CLASS) == 0) {
>   if (power_supply_is_system_supplied() > 0)
>   DRM_DEBUG_DRIVER("pm: AC\n");
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index abfcc1304ba0c..3a0afe7602727 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -3454,6 +3454,7 @@ int amdgpu_device_init(struct amdgpu_device 
> *adev,
>   
>   adev->gfx.gfx_off_req_count = 1;
>   adev->pm.ac_power = power_supply_is_system_supplied() > 0;
> + adev->pm.old_ac_power = true;
>   
>   atomic_set(>throttling_logging_enabled, 1);
>   /*
> diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c 
> b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
> index 54a1408c8015c..478a734b66926 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
> +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
> @@ -23,6 +23,8 @@
>*
>*/
>   
> +#include 
> +#include "amdgpu.h"
>   #include "dmub_abm.h"
>   #include "dce_abm.h"
>   #include "dc.h"
> @@ -51,6 +53,7 @@
>   #define DISABLE_ABM_IMMEDIATELY 255
>   
>   
> +extern uint amdgpu_dm_abm_level;
>   
>   static void dmub_abm_enable_fractional_pwm(struct dc_context *dc)
>   {
> @@ -117,28 +120,6 @@ static void dmub_abm_init(struct abm *abm, uint32_t 
> backlight)
>   dmub_abm_enable_fractional_pwm(abm->ctx);
>   }
>   
> -static unsigned int dmub_abm_get_current_backlight(struct abm *abm) 
> -{
> - struct dce_abm *dce_abm = TO_DMUB_ABM(abm);
> - unsigned int backlight = REG_READ(BL1_PWM_CURRENT_ABM_LEVEL);
> -
> - /* return backlight in hardware format which is unsigned 17 bits, with
> -  * 1 bit integer and 16 bit fractional
> -  */
> - return backlight;
> -}
> -
> -static unsigned int dmub_abm_get_target_backlight(struct abm *abm) -{
> - struct

Re: [PATCH v2 3/25] drm/amdgpu: Disable ABM when AC mode