Re: [PATCH v4 12/41] dyndbg: add DECLARE_DYNDBG_CLASSMAP
On Fri, Jul 22, 2022 at 2:23 PM Jason Baron wrote: > > > > On 7/20/22 11:32, Jim Cromie wrote: > > DECLARE_DYNDBG_CLASSMAP lets modules declare a set of classnames, this > > opt-in authorizes dyndbg to allow enabling of prdbgs by their class: > > > >:#> echo class DRM_UT_KMS +p > /proc/dynamic_debug/control > > > > This is just the setup; following commits deliver. > > > > The macro declares and initializes a static struct ddebug_class_map: > > > > - maps approved class-names to class_ids used in module, > >by array order. forex: DRM_UT_* > > - class-name vals allow validation of "class FOO" queries > >using macro is opt-in > > - enum class_map_type - determines interface, behavior > > > > Each module has its own .class_id space, and only known class-names > > will be authorized for a manipulation. Only DRM stuff should know this: > > > > :#> echo class DRM_UT_CORE +p > control # across all modules > > > > pr_debugs (with default class_id) are still controllable as before. > > > > DECLARE_DYNDBG_CLASSMAP(_var, _maptype, _base, classes...) is:: > > > > _var: name of the static struct var. user passes to module_param_cb() > >if they want a sysfs node. (ive only done it this way). > > > > _maptype: this is hard-coded to DD_CLASS_TYPE_DISJOINT for now. > > > > _base: usually 0, it allows splitting 31 classes into subranges, so > > that multiple classes / sysfs-nodes can share the module's > > class-id space. > > > > classes: list of class_name strings, these are mapped to class-ids > > starting at _base. This class-names list must have a > > corresponding ENUM, with SYMBOLS that match the literals, > > and 1st enum val = _base. > > > > enum class_map_type has 4 values, on 2 factors:: > > > > - classes are disjoint/independent vs relative/x >disjoint is basis, verbosity by overlay. > > > > - input NUMBERS vs [+-]CLASS_NAMES > >uints, ideally hex. vs +DRM_UT_CORE,-DRM_UT_KMS > > > > Could the naming here directly reflect the 2 factors? At least for me > I think it's more readable. So something like: > yeah, those were 1st-pass names. your names are more regular > DD_CLASS_TYPE_DISJOINT_NUM > DD_CLASS_TYPE_DISJOINT_NAME > DD_CLASS_TYPE_LEVEL_NUM > DD_CLASS_TYPE_LEVEL_NAME s/_NAME/_NAMES/ - the plural suggests list,comma-separated s/(DISJOINT)_NUM/$1_BITS/ - strongly signals expected input form LEVEL - while VERBOSE spoke to me, LEVEL has legacy: include/linux/kern_levels.h LEVELS - pluralize ? NUM - Im not crazy about, but it stands well in opposition to _BITS
Re: [PATCH 1/4] Documentation/amdgpu_dm: Add DM color correction documentation
On 2022-07-20 18:54, Melissa Wen wrote:
On 07/17, Tales Lelo da Aparecida wrote:
On 16/07/2022 19:25, Melissa Wen wrote:
AMDGPU DM maps DRM color management properties (degamma, ctm and gamma)
to DC color correction entities. Part of this mapping is already
documented as code comments and can be converted as kernel docs.
v2:
- rebase to amd-staging-drm-next
Reviewed-by: Harry Wentland
Signed-off-by: Melissa Wen
---
.../gpu/amdgpu/display/display-manager.rst| 9 ++
.../amd/display/amdgpu_dm/amdgpu_dm_color.c | 121 +-
2 files changed, 98 insertions(+), 32 deletions(-)
diff --git a/Documentation/gpu/amdgpu/display/display-manager.rst
b/Documentation/gpu/amdgpu/display/display-manager.rst
index 7ce31f89d9a0..b1b0f11aed83 100644
--- a/Documentation/gpu/amdgpu/display/display-manager.rst
+++ b/Documentation/gpu/amdgpu/display/display-manager.rst
@@ -40,3 +40,12 @@ Atomic Implementation
.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
:functions: amdgpu_dm_atomic_check amdgpu_dm_atomic_commit_tail
+
+Color Management Properties
+===
+
+.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
+ :doc: overview
+
+.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
+ :internal:
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
index a71177305bcd..93c813089bff 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
@@ -29,7 +29,9 @@
#include "modules/color/color_gamma.h"
#include "basics/conversion.h"
-/*
+/**
+ * DOC: overview
+ *
* The DC interface to HW gives us the following color management blocks
* per pipe (surface):
*
@@ -71,8 +73,8 @@
#define MAX_DRM_LUT_VALUE 0x
-/*
- * Initialize the color module.
+/**
+ * amdgpu_dm_init_color_mod - Initialize the color module.
*
* We're not using the full color module, only certain components.
* Only call setup functions for components that we need.
@@ -82,7 +84,14 @@ void amdgpu_dm_init_color_mod(void)
setup_x_points_distribution();
}
-/* Extracts the DRM lut and lut size from a blob. */
+/**
+ * __extract_blob_lut - Extracts the DRM lut and lut size from a blob.
+ * @blob: DRM color mgmt property blob
+ * @size: lut size
+ *
+ * Returns:
+ * DRM LUT or NULL
+ */
static const struct drm_color_lut *
__extract_blob_lut(const struct drm_property_blob *blob, uint32_t *size)
{
@@ -90,13 +99,18 @@ __extract_blob_lut(const struct drm_property_blob *blob,
uint32_t *size)
return blob ? (struct drm_color_lut *)blob->data : NULL;
}
I don't think everyone would approve using actual kernel-doc for these
static functions, but I can appreciate they being formatted as such.
Consider replacing /** with /*.
IMHO, although they are static, they provide info to understand the AMD
DM programming of DRM color correction properties. I see the value for
external contributors, but I'm not sure about kernel-doc rules about it.
Yeah... I agree, I don't mind seeing kernel-doc for some static
functions. Iirc, DRM documentation also documents some static functions.
-/*
- * Return true if the given lut is a linear mapping of values, i.e. it acts
- * like a bypass LUT.
+/**
+ * __is_lut_linear - check if the given lut is a linear mapping of values
+ * @lut: given lut to check values
+ * @size: lut size
*
* It is considered linear if the lut represents:
- * f(a) = (0xFF00/MAX_COLOR_LUT_ENTRIES-1)a; for integer a in
- * [0, MAX_COLOR_LUT_ENTRIES)
+ * f(a) = (0xFF00/MAX_COLOR_LUT_ENTRIES-1)a; for integer a in [0,
+ * MAX_COLOR_LUT_ENTRIES)
+ *
+ * Returns:
+ * True if the given lut is a linear mapping of values, i.e. it acts like a
+ * bypass LUT. Otherwise, false.
*/
static bool __is_lut_linear(const struct drm_color_lut *lut, uint32_t size)
{
@@ -119,9 +133,13 @@ static bool __is_lut_linear(const struct drm_color_lut
*lut, uint32_t size)
return true;
}
-/*
- * Convert the drm_color_lut to dc_gamma. The conversion depends on the size
- * of the lut - whether or not it's legacy.
+/**
+ * __drm_lut_to_dc_gamma - convert the drm_color_lut to dc_gamma.
+ * @lut: DRM lookup table for color conversion
+ * @gamma: DC gamma to set entries
+ * @is_legacy: legacy or atomic gamma
+ *
+ * The conversion depends on the size of the lut - whether or not it's legacy.
*/
static void __drm_lut_to_dc_gamma(const struct drm_color_lut *lut,
struct dc_gamma *gamma, bool is_legacy)
@@ -154,8 +172,11 @@ static void __drm_lut_to_dc_gamma(const struct
drm_color_lut *lut,
}
}
-/*
- * Converts a DRM CTM to a DC CSC float matrix.
+/**
+ * __drm_ctm_to_dc_matrix - converts a DRM CTM to a DC CSC float matrix
+ * @ctm: DRM color transformation matrix
Re: [PATCH v4 12/41] dyndbg: add DECLARE_DYNDBG_CLASSMAP
On 7/20/22 11:32, Jim Cromie wrote: > DECLARE_DYNDBG_CLASSMAP lets modules declare a set of classnames, this > opt-in authorizes dyndbg to allow enabling of prdbgs by their class: > >:#> echo class DRM_UT_KMS +p > /proc/dynamic_debug/control > > This is just the setup; following commits deliver. > > The macro declares and initializes a static struct ddebug_class_map: > > - maps approved class-names to class_ids used in module, >by array order. forex: DRM_UT_* > - class-name vals allow validation of "class FOO" queries >using macro is opt-in > - enum class_map_type - determines interface, behavior > > Each module has its own .class_id space, and only known class-names > will be authorized for a manipulation. Only DRM stuff should know this: > > :#> echo class DRM_UT_CORE +p > control # across all modules > > pr_debugs (with default class_id) are still controllable as before. > > DECLARE_DYNDBG_CLASSMAP(_var, _maptype, _base, classes...) is:: > > _var: name of the static struct var. user passes to module_param_cb() >if they want a sysfs node. (ive only done it this way). > > _maptype: this is hard-coded to DD_CLASS_TYPE_DISJOINT for now. > > _base: usually 0, it allows splitting 31 classes into subranges, so > that multiple classes / sysfs-nodes can share the module's > class-id space. > > classes: list of class_name strings, these are mapped to class-ids > starting at _base. This class-names list must have a > corresponding ENUM, with SYMBOLS that match the literals, > and 1st enum val = _base. > > enum class_map_type has 4 values, on 2 factors:: > > - classes are disjoint/independent vs relative/xdisjoint is basis, verbosity by overlay. > > - input NUMBERS vs [+-]CLASS_NAMES >uints, ideally hex. vs +DRM_UT_CORE,-DRM_UT_KMS > Could the naming here directly reflect the 2 factors? At least for me I think it's more readable. So something like: > DD_CLASS_TYPE_DISJOINT: classes are separate, one per bit. >expecting hex input. basis for others. DD_CLASS_TYPE_DISJOINT_NUM > > DD_CLASS_TYPE_SYMBOLIC: input is a CSV of [+-]CLASS_NAMES, >classes are independent, like DISJOINT > DD_CLASS_TYPE_DISJOINT_NAME > DD_CLASS_TYPE_VERBOSE: input is numeric level, 0-N. >0 implies silence. use printk to break that. >relative levels applied on bitmaps. > DD_CLASS_TYPE_LEVEL_NUM > DD_CLASS_TYPE_LEVELS: input is a CSV of [+-]CLASS_NAMES, >names like: ERR,WARNING,NOTICE,INFO,DEBUG >avoiding EMERG,ALERT,CRIT,ERR - no point. > DD_CLASS_TYPE_LEVEL_NAME > NOTES: > > The macro places the initialized struct ddebug_class_map into the > __dyndbg_classes section. That draws a 'orphan' warning which we > handle in next commit. The struct attributes are necessary: > __aligned(8) stopped null-ptr derefs (why?), __used is needed by drm > drivers, which declare class-maps, but don't also declare a > sysfs-param, and thus dont ref the classmap; __used insures that the > linkage is made, then the class-map is found at load-time. > > While its possible to handle both NAMES and NUMBERS in the same > sys-interface, there is ambiguity to avoid, by disallowing them > together. Later, if ambiguities are resolved, 2 new enums can permit > both inputs, on verbose & independent types separately, and authors > can select the interface they like. > > RFC: > > My plan is to implement LEVELS in the callbacks, outside of > ddebug_exec_query(), which for simplicity will treat the CLASSES in > the map as disjoint. This should handle most situations. > > The callbacks can see map-type, and apply ++/-- loops (or bitops) to > force the relative meanings across the class-bitmap. > > That leaves 2 issues: > > 1. doing LEVELs in callbacks means that the native >control interface > doesn't enforce the LEVELS relationship, so you could confusingly have > V3 enabled, but V1 disabled. OTOH, the control iface already allows > infinite variety in the underlying callsites, despite the veneer of > uniformity suggested by the bitmap overlay, and LEVELS over that. > > 2. All dyndbg >control reduces to a query/command, includes +/-, which > is at-root a kernel patching operation with +/- semantics. And the > symbolic sys-node handling exposes it to the user: > > Consider whether these are/should-be 'exactly' the same: > ># force both 2 "half-duplex" relations >echo +V3,-V4 > /sys/module/test_dynamic_debug/p_VX > ># should these both do the same ? >echo +V3 > /sys/module/test_dynamic_debug/p_VX >echo -V4 > /sys/module/test_dynamic_debug/p_VX > > IOW, half relations are suggested by the +/-, and enum control of > individual behaviors leaves some room for this, especially wrt > handling [+-]SYMBOLIC inputs from the user. > > Signed-off-by: Jim Cromie > --- > include/linux/dynamic_debug.h | 55 +++ > 1 file changed, 55 insertions(+) > > diff --git
Re: [PATCH v4 16/41] dyndbg: add drm.debug style bitmap support
On 7/20/22 11:32, Jim Cromie wrote:
> Add kernel_param_ops and callbacks to apply a class-map to a
> sysfs-node, which then can control classes defined in that class-map.
> This supports uses like:
>
> echo 0x3 > /sys/module/drm/parameters/debug
>
> IE add these:
>
> - int param_set_dyndbg_classes()
> - int param_get_dyndbg_classes()
> - struct kernel_param_ops param_ops_dyndbg_classes
>
> Following the model of kernel/params.c STANDARD_PARAM_DEFS, these are
> non-static and exported. This might be unnecessary here.
>
> get/set use an augmented kernel_param; the arg refs a new struct
> ddebug_classes_bitmap_param, initialized by DYNAMIC_DEBUG_CLASSBITS
> macro, which contains:
>
> BITS: a pointer to the user module's ulong holding the bits/state. By
> ref'g the client's bit-state _var, we coordinate with existing code
> (such as drm_debug_enabled) which uses the _var, so it works
> unchanged, even as the foundation is switched out underneath it..
> Using a ulong allows use of BIT() etc.
>
> FLAGS: dyndbg.flags toggled by changes to bitmap. Usually just "p".
>
> MAP: a pointer to struct ddebug_classes_map, which maps those
> class-names to .class_ids 0..N that the module is using. This
> class-map is declared & initialized by DEFINE_DYNDBG_CLASSMAP.
>
> map-type: add support here for DD_CLASS_DISJOINT, DD_CLASS_VERBOSE.
>
> These 2 class-types both expect an integer; _DISJOINT treats input
> like a bit-vector (ala drm.debug), and sets each bit accordingly.
>
> _VERBOSE treats input like a bit-pos:N, then sets bits(0..N)=1, and
> bits(N+1..max)=0. This applies (bit bits.
>
> cases DD_CLASS_SYMBOLIC, DD_CLASS_LEVELS are included for the complete
> picture, with commented out call to a following commit.
>
> NOTES:
>
> this now includes SYMBOLIC/LEVELS support, too tedious to keep
> separate thru all the tweaking.
>
> get-param undoes the bit-pos -> bitmap transform that set-param does
> on VERBOSE inputs, this gives the read-what-was-written property.
>
> _VERBOSE is overlay on _DISJOINT:
>
> verbose-maps still need class-names, even though theyre not usable at
> the sysfs interface (unlike with _SYMBOLIC/_LEVELS).
>
> - It must have a "V0" name,
>something below "V1" to turn "V1" off.
>__pr_debug_cls(V0,..) is printk, don't do that.
>
> - "class names" is required at the >control interface.
> - relative levels are not enforced at >control
>
> IOW this is possible, and maybe confusing:
>
> echo class V3 +p > control
> echo class V1 -p > control
>
> IMO thats ok, relative verbosity is an interface property.
>
> Signed-off-by: Jim Cromie
> ---
> . drop kp->mod->name as unneeded (build-dependent)
> ---
> include/linux/dynamic_debug.h | 18
> lib/dynamic_debug.c | 193 ++
> 2 files changed, 211 insertions(+)
>
> diff --git a/include/linux/dynamic_debug.h b/include/linux/dynamic_debug.h
> index f57076e02767..b50bdd5c8184 100644
> --- a/include/linux/dynamic_debug.h
> +++ b/include/linux/dynamic_debug.h
> @@ -113,6 +113,12 @@ struct ddebug_class_map {
> #define NUM_TYPE_ARGS(eltype, ...) \
> (sizeof((eltype[]) {__VA_ARGS__}) / sizeof(eltype))
>
> +struct ddebug_classes_bitmap_param {
> + unsigned long *bits;
> + char flags[8];
> + const struct ddebug_class_map *map;
> +};
> +
> #if defined(CONFIG_DYNAMIC_DEBUG_CORE)
>
> int ddebug_add_module(struct _ddebug *tab, unsigned int num_debugs,
> @@ -274,6 +280,10 @@ void __dynamic_ibdev_dbg(struct _ddebug *descriptor,
> KERN_DEBUG, prefix_str, prefix_type, \
> rowsize, groupsize, buf, len, ascii)
>
> +struct kernel_param;
> +int param_set_dyndbg_classes(const char *instr, const struct kernel_param
> *kp);
> +int param_get_dyndbg_classes(char *buffer, const struct kernel_param *kp);
> +
> /* for test only, generally expect drm.debug style macro wrappers */
> #define __pr_debug_cls(cls, fmt, ...) do { \
> BUILD_BUG_ON_MSG(!__builtin_constant_p(cls),\
> @@ -322,6 +332,14 @@ static inline int ddebug_dyndbg_module_param_cb(char
> *param, char *val,
> rowsize, groupsize, buf, len, ascii); \
> } while (0)
>
> +struct kernel_param;
> +static inline int param_set_dyndbg_classes(const char *instr, const struct
> kernel_param *kp)
> +{ return 0; }
> +static inline int param_get_dyndbg_classes(char *buffer, const struct
> kernel_param *kp)
> +{ return 0; }
> +
> #endif /* !CONFIG_DYNAMIC_DEBUG_CORE */
>
> +extern const struct kernel_param_ops param_ops_dyndbg_classes;
> +
> #endif
> diff --git a/lib/dynamic_debug.c b/lib/dynamic_debug.c
> index 4c27bbe5187e..dd27dc514aa3 100644
> --- a/lib/dynamic_debug.c
> +++ b/lib/dynamic_debug.c
> @@ -596,6 +596,199 @@ static int ddebug_exec_queries(char *query, const char
> *modname)
> return nfound;
> }
>
> +static int
Re: [PATCH] amdgpu: re-enable DCN for ppc64le
Hi Dan, [ Cc += linuxppc-dev ] Dan Horák writes: > Commit d11219ad53dc disabled the DCN driver for all platforms that > define PPC64 due long build issues during "make allmodconfig" using > cross-compilation. Cross-compilation defaults to the ppc64_defconfig > and thus big-endian toolchain configuration. The ppc64le platform uses a > different ABI and doesn't suffer from the build issues. Unfortunately it's a bit messier than that. The build error occurs when the compiler is built to use a 64-bit long double type. The ppc64le ABI document says that long double should be 128-bits, but there are ppc64le compilers out there that are configured to use 64-bit long double, notably the kernel.org crosstool compilers. So just testing for CPU_LITTLE_ENDIAN means we'll still get build errors on those compilers. But I think we can detect the long double size and key off that. Can you test the patch below works for you? cheers diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index 7aa12e88c580..e9f8cd50af99 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -281,6 +281,9 @@ config PPC # Please keep this list sorted alphabetically. # +config PCC_LONG_DOUBLE_128 + def_bool $(success,test "$(shell,echo __LONG_DOUBLE_128__ | $(CC) -E -P -)" = 1) + config PPC_BARRIER_NOSPEC bool default y diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/display/Kconfig index b4029c0d5d8c..ec6771e87e73 100644 --- a/drivers/gpu/drm/amd/display/Kconfig +++ b/drivers/gpu/drm/amd/display/Kconfig @@ -6,7 +6,7 @@ config DRM_AMD_DC bool "AMD DC - Enable new display engine" default y select SND_HDA_COMPONENT if SND_HDA_CORE - select DRM_AMD_DC_DCN if (X86 || PPC64) && !(KCOV_INSTRUMENT_ALL && KCOV_ENABLE_COMPARISONS) + select DRM_AMD_DC_DCN if (X86 || PPC_LONG_DOUBLE_128) && !(KCOV_INSTRUMENT_ALL && KCOV_ENABLE_COMPARISONS) help Choose this option if you want to use the new display engine support for AMDGPU. This adds required support for Vega and
Re: [PATCH v2 3/4] drm/amd/display: Remove parameters from rq_dlg_get_dlg_reg
Hi Siqueira,
On 7/22/22 17:11, Rodrigo Siqueira Jordao wrote:
> Hi Maira,
>
> First of all, thanks a lot for this patch. This change is really helpful
> for reducing the stack size. I just have few comments inline.
Thank you for the feedback!
>
> On 2022-07-21 14:36, Maíra Canal wrote:
>> Across all DCN's (except DCN32, that has a separate
>> rq_dlg_get_dlg_reg), the parameters const bool vm_en, const bool
>> ignore_viewport_pos, and const bool immediate_flip_support are not used
>> on the function. Therefore, change the rq_dlg_get_dlg_reg signature
>> by deleting those parameters.
>>
>> Signed-off-by: Maíra Canal
>> ---
>> v1 -> v2:
>> - Replace "enum" to "enum entries" (André Almeida).
>> ---
>> .../drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 3 +--
>> .../dc/dml/dcn20/display_rq_dlg_calc_20.c | 5 +
>> .../dc/dml/dcn20/display_rq_dlg_calc_20.h | 5 +
>> .../dc/dml/dcn20/display_rq_dlg_calc_20v2.c | 5 +
>> .../dc/dml/dcn20/display_rq_dlg_calc_20v2.h | 5 +
>> .../dc/dml/dcn21/display_rq_dlg_calc_21.c | 5 +
>> .../dc/dml/dcn21/display_rq_dlg_calc_21.h | 5 +
>> .../dc/dml/dcn30/display_rq_dlg_calc_30.c | 18 +++---
>> .../dc/dml/dcn30/display_rq_dlg_calc_30.h | 5 +
>> .../dc/dml/dcn31/display_rq_dlg_calc_31.c | 19 +++
>> .../dc/dml/dcn31/display_rq_dlg_calc_31.h | 5 +
>> .../dc/dml/dcn314/display_rq_dlg_calc_314.c | 15 ++-
>> .../dc/dml/dcn314/display_rq_dlg_calc_314.h | 5 +
>> .../drm/amd/display/dc/dml/display_mode_lib.h | 5 +
>> .../gpu/drm/amd/display/dc/dml/dml_wrapper.c | 3 +--
>> 15 files changed, 20 insertions(+), 88 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
>> b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
>> index dc60b835e938..d9cfb29a2651 100644
>> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
>> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
>> @@ -857,8 +857,7 @@ void dcn20_calculate_dlg_params(
>> pipe_cnt,
>> pipe_idx,
>> cstate_en,
>> - context->bw_ctx.bw.dcn.clk.p_state_change_support,
>> - false, false, true);
>> + context->bw_ctx.bw.dcn.clk.p_state_change_support);
>>
>> context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg(>bw_ctx.dml,
>> >res_ctx.pipe_ctx[i].rq_regs,
>> diff --git
>> a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
>> b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
>> index 548cdef8a8ad..d0a4c69b47c8 100644
>> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
>> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
>> @@ -1553,10 +1553,7 @@ void dml20_rq_dlg_get_dlg_reg(struct
>> display_mode_lib *mode_lib,
>> const unsigned int num_pipes,
>> const unsigned int pipe_idx,
>> const bool cstate_en,
>> - const bool pstate_en,
>> - const bool vm_en,
>> - const bool ignore_viewport_pos,
>> - const bool immediate_flip_support)
>> + const bool pstate_en)
>> {
>> display_rq_params_st rq_param = {0};
>> display_dlg_sys_params_st dlg_sys_param = {0};
>> diff --git
>> a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.h
>> b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.h
>> index 8b23867e97c1..36c3692e53b8 100644
>> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.h
>> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.h
>> @@ -65,9 +65,6 @@ void dml20_rq_dlg_get_dlg_reg(
>> const unsigned int num_pipes,
>> const unsigned int pipe_idx,
>> const bool cstate_en,
>> - const bool pstate_en,
>> - const bool vm_en,
>> - const bool ignore_viewport_pos,
>> - const bool immediate_flip_support);
>> + const bool pstate_en);
>> #endif
>> diff --git
>> a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
>> b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
>> index 0fc9f3e3ffae..17df9d31c11f 100644
>> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
>> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
>> @@ -1554,10 +1554,7 @@ void dml20v2_rq_dlg_get_dlg_reg(struct
>> display_mode_lib *mode_lib,
>> const unsigned int num_pipes,
>> const unsigned int pipe_idx,
>> const bool cstate_en,
>> - const bool pstate_en,
>> - const bool vm_en,
>> - const bool ignore_viewport_pos,
>> - const bool immediate_flip_support)
>> + const bool pstate_en)
>> {
>> display_rq_params_st rq_param = {0};
>> display_dlg_sys_params_st dlg_sys_param = {0};
>> diff --git
>>
[PATCH 31/31] drm/amd/display: 3.2.196
From: Anthony Koo This version brings along following fixes: - Copy crc_skip_count when duplicating CRTC state - Add debug option for idle optimizations on cursor updates - Disable MPC split for DCN32/321 - Add missing ODM 2:1 policy logic - Update DCN32 and DCN321 SR latencies - Add reinstate dram in the FPO logic - Add dc_ctx to link_enc_create() parameters - Cache cursor when cursor exceeds 64x64 - Add support for manual DMUB FAMS trigger - Fix dpstreamclk programming - Add missing AUDIO_DTO_SEL reg field - Add OTG/ODM functions - Use correct clock source constructor for DCN314 - Use correct DTO_SRC_SEL for 128b/132b encoding - Add pixel rate div calcs and programming - Remove FPU flags from DCN30 Makefile - Create patch bounding box function for isolate FPU - Move mclk calculation function to DML - Remove FPU operations from dcn201 resources - Fallback to SW cursor if SubVP + cursor too big - Drop unnecessary FPU flags on dcn302 files - Reboot while unplug hdcp enabled dp from mst hub - Reset pipe count when iterating for DET override - Calculate MALL cache lines based on Mblks required - Fix two MPO videos in single display ODM combine mode - Guard against zero memory channels - Updates SubVP + SubVP DRR cases updates - Fix OPTC function pointers for DCN314 - Add enable/disable FIFO callbacks to stream setup - Avoid MPC infinite loop Acked-by: Alex Hung Signed-off-by: Anthony Koo --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index d05bbe193bfa..8e1e40083ec8 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -47,7 +47,7 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.195" +#define DC_VER "3.2.196" #define MAX_SURFACES 3 #define MAX_PLANES 6 -- 2.37.1
[PATCH 30/31] drm/amd/display: Copy crc_skip_count when duplicating CRTC state
From: Leo Li [Why] crc_skip_count is used to track how many frames to skip to allow the OTG CRC engine to "warm up" before it outputs correct CRC values. Experimentally, this seems to be 2 frames. When duplicating CRTC states, this value was not copied to the duplicated state. Therefore, when this state is committed, we will needlessly wait 2 frames before outputing CRC values. Even if the CRC engine is already warmed up. [How] Copy the crc_skip_count as part of dm_crtc_duplicate_state. Acked-by: Alex Hung Signed-off-by: Leo Li --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index a9413acfe4dc..c89594f3a5cb 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c @@ -243,6 +243,7 @@ static struct drm_crtc_state *dm_crtc_duplicate_state(struct drm_crtc *crtc) state->freesync_config = cur->freesync_config; state->cm_has_degamma = cur->cm_has_degamma; state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb; + state->crc_skip_count = cur->crc_skip_count; state->mpo_requested = cur->mpo_requested; /* TODO Duplicate dc_stream after objects are stream object is flattened */ -- 2.37.1
[PATCH 29/31] drm/amd/display: Add debug option for idle optimizations on cursor updates
From: Alvin Lee
For optimizations and debug purposes we added an option to exit idle
operations on cursor updates.
Acked-by: Alex Hung
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c | 1 +
drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
index 2278181ad3d6..9a26d24b579f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
@@ -868,6 +868,7 @@ static const struct dc_debug_options debug_defaults_drv = {
},
.use_max_lb = true,
.force_disable_subvp = true,
+ .exit_idle_opt_for_cursor_updates = true,
.enable_single_display_2to1_odm_policy = true,
.enable_dp_dig_pixel_rate_div_policy = 1,
};
diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
index ea5160d0c92e..8157e40d2c7e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
@@ -869,6 +869,7 @@ static const struct dc_debug_options debug_defaults_drv = {
},
.use_max_lb = true,
.force_disable_subvp = true,
+ .exit_idle_opt_for_cursor_updates = true,
.enable_single_display_2to1_odm_policy = true,
.enable_dp_dig_pixel_rate_div_policy = 1,
};
--
2.37.1
[PATCH 28/31] drm/amd/display: Disable MPC split for DCN32/321
From: Alvin Lee
Due to CRB, no need to rely on MPC splitting to maximize use of DET
anymore.
Reviewed-by: Rodrigo Siqueira
Acked-by: Alex Hung
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c | 2 +-
drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
index bb1d880eee1e..2278181ad3d6 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
@@ -843,7 +843,7 @@ static const struct dc_debug_options debug_defaults_drv = {
.timing_trace = false,
.clock_trace = true,
.disable_pplib_clock_request = false,
- .pipe_split_policy = MPC_SPLIT_DYNAMIC,
+ .pipe_split_policy = MPC_SPLIT_AVOID, // Due to CRB, no need to MPC
split anymore
.force_single_disp_pipe_split = false,
.disable_dcc = DCC_ENABLE,
.vsr_support = true,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
index 73d2a653a279..ea5160d0c92e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
@@ -844,7 +844,7 @@ static const struct dc_debug_options debug_defaults_drv = {
.timing_trace = false,
.clock_trace = true,
.disable_pplib_clock_request = false,
- .pipe_split_policy = MPC_SPLIT_DYNAMIC,
+ .pipe_split_policy = MPC_SPLIT_AVOID,
.force_single_disp_pipe_split = false,
.disable_dcc = DCC_ENABLE,
.vsr_support = true,
--
2.37.1
[PATCH 27/31] drm/amd/display: Add missing ODM 2:1 policy logic
From: Samson Tam
Phantom pipes must use the same configuration used in main pipes. This
commit add this check.
Reviewed-by: Rodrigo Siqueira
Acked-by: Alex Hung
Signed-off-by: Samson Tam
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 1 -
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c| 7 ++-
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 621767e994bd..8224b9bf01d1 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -1269,7 +1269,6 @@ static void get_pixel_clock_parameters(
pixel_clk_params->requested_pix_clk_100hz /= 4;
else if (optc2_is_two_pixels_per_containter(>timing) || opp_cnt
== 2)
pixel_clk_params->requested_pix_clk_100hz /= 2;
-
else if (hws->funcs.is_dp_dig_pixel_rate_div_policy) {
if (hws->funcs.is_dp_dig_pixel_rate_div_policy(pipe_ctx))
pixel_clk_params->requested_pix_clk_100hz /= 2;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
index 1f845e9ac406..be2e3b9e971e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
@@ -1084,8 +1084,13 @@ unsigned int dcn32_calculate_dccg_k1_k2_values(struct
pipe_ctx *pipe_ctx, unsign
struct dc_stream_state *stream = pipe_ctx->stream;
unsigned int odm_combine_factor = 0;
struct dc *dc = pipe_ctx->stream->ctx->dc;
- bool two_pix_per_container =
optc2_is_two_pixels_per_containter(>timing);
+ bool two_pix_per_container = false;
+ // For phantom pipes, use the same programming as the main pipes
+ if (pipe_ctx->stream->mall_stream_config.type == SUBVP_PHANTOM) {
+ stream = pipe_ctx->stream->mall_stream_config.paired_stream;
+ }
+ two_pix_per_container =
optc2_is_two_pixels_per_containter(>timing);
odm_combine_factor = get_odm_config(pipe_ctx, NULL);
if (is_dp_128b_132b_signal(pipe_ctx)) {
--
2.37.1
[PATCH 26/31] drm/amd/display: Update DCN32 and DCN321 SR latencies
From: Alvin Lee
Update worst case SR latencies according to values measured by hardware
team.
Reviewed-by: Rodrigo Siqueira
Acked-by: Alex Hung
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 4 ++--
drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index 01e272f0bb05..66453546e24f 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -121,8 +121,8 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_2_soc = {
},
},
.num_states = 1,
- .sr_exit_time_us = 5.20,
- .sr_enter_plus_exit_time_us = 9.60,
+ .sr_exit_time_us = 20.16,
+ .sr_enter_plus_exit_time_us = 27.13,
.sr_exit_z8_time_us = 285.0,
.sr_enter_plus_exit_z8_time_us = 320,
.writeback_latency_us = 12.0,
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
index 6e72336b7975..84b4b00f29cb 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
@@ -119,8 +119,8 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_21_soc = {
},
},
.num_states = 1,
- .sr_exit_time_us = 5.20,
- .sr_enter_plus_exit_time_us = 9.60,
+ .sr_exit_time_us = 12.36,
+ .sr_enter_plus_exit_time_us = 16.72,
.sr_exit_z8_time_us = 285.0,
.sr_enter_plus_exit_z8_time_us = 320,
.writeback_latency_us = 12.0,
--
2.37.1
[PATCH 25/31] drm/amd/display: Add reinstate dram in the FPO logic
From: Rodrigo Siqueira
In order to handle FPO correctly, we need to reinstate the dram values.
This function adds the required code to handle the vblank stretch and
the dram calculation.
Acked-by: Alex Hung
Signed-off-by: Rodrigo Siqueira
---
.../drm/amd/display/dc/dcn30/dcn30_resource.h | 3 +
.../drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 67 ---
2 files changed, 60 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.h
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.h
index 3330a1026fa5..7d063c7d6a4b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.h
@@ -99,6 +99,9 @@ enum dc_status dcn30_add_stream_to_ctx(
void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params
*bw_params);
+bool dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch(struct dc
*dc, struct dc_state *context);
void dcn30_setup_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc,
struct dc_state *context);
+int dcn30_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc,
struct dc_state *context,
+ display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel);
#endif /* _DCN30_RESOURCE_H_ */
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index 9175fe1f9be3..01e272f0bb05 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -30,6 +30,7 @@
#include "display_mode_vba_util_32.h"
// We need this includes for WATERMARKS_* defines
#include "clk_mgr/dcn32/dcn32_smu13_driver_if.h"
+#include "dcn30/dcn30_resource.h"
#define DC_LOGGER_INIT(logger)
@@ -1597,6 +1598,10 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc,
struct dc_state *context,
double dcfclk_from_validation =
context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
bool pstate_en =
context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]
!=
dm_dram_clock_change_unsupported;
+ unsigned int dummy_latency_index = 0;
+ int maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb;
+ unsigned int min_dram_speed_mts = context->bw_ctx.dml.vba.DRAMSpeed;
+ unsigned int min_dram_speed_mts_margin;
dc_assert_fp_enabled();
@@ -1606,6 +1611,32 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc,
struct dc_state *context,
pstate_en = true;
}
+ context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false;
+
+ if (!pstate_en) {
+ /* only when the mclk switch can not be natural, is the fw
based vblank stretch attempted */
+ context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching =
+
dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch(dc, context);
+
+ if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {
+ dummy_latency_index =
dcn30_find_dummy_latency_index_for_fw_based_mclk_switch(dc,
+ context, pipes, pipe_cnt, vlevel);
+
+ /* After calling
dcn30_find_dummy_latency_index_for_fw_based_mclk_switch
+* we reinstate the original
dram_clock_change_latency_us on the context
+* and all variables that may have changed up to this
point, except the
+* newly found dummy_latency_index
+*/
+ context->bw_ctx.dml.soc.dram_clock_change_latency_us =
+
dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;
+ dcn32_internal_validate_bw(dc, context, pipes,
_cnt, , false);
+ maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb;
+ dcfclk =
context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
+ pstate_en =
context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] !=
+ dm_dram_clock_change_unsupported;
+ }
+ }
+
/* Set B:
* For Set B calculations use clocks from clock_limits[2] when
available i.e. when SMU is present,
* otherwise use arbitrary low value from spreadsheet for DCFCLK as
lower is safer for watermark
@@ -1687,19 +1718,33 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc,
struct dc_state *context,
pipes[0].clks_cfg.socclk_mhz =
context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) {
- unsigned int min_dram_speed_mts =
context->bw_ctx.dml.vba.DRAMSpeed;
- unsigned int min_dram_speed_mts_margin = 160;
+ min_dram_speed_mts =
[PATCH 24/31] drm/amd/display: Add dc_ctx to link_enc_create() parameters
From: Aurabindo Pillai
[Why]
Preparation to enable run time initialization of register offsets to add
dc_context to the link_enc_create callback. This is needed to get the
dc_ctx handle where register offset initialization routine is called.
Reviewed-by: Rodrigo Siqueira
Acked-by: Alan Liu
Acked-by: Alex Hung
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 +-
drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c | 1 +
drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c | 1 +
drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c | 1 +
drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c | 1 +
drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c | 1 +
drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c | 1 +
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 1 +
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 1 +
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h | 1 +
drivers/gpu/drm/amd/display/dc/dcn201/dcn201_resource.c | 1 +
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 1 +
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c | 1 +
drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c | 1 +
drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c | 4 +++-
drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c | 4 +++-
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c | 1 +
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c | 1 +
drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c | 1 +
drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c | 1 +
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c | 1 +
drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c | 1 +
drivers/gpu/drm/amd/display/dc/inc/core_types.h | 1 +
23 files changed, 27 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index ef54b96affa8..9e51338441d0 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1703,7 +1703,7 @@ static bool dc_link_construct_legacy(struct dc_link *link,
enc_init_data.transmitter =
translate_encoder_to_transmitter(enc_init_data.encoder);
link->link_enc =
- link->dc->res_pool->funcs->link_enc_create(_init_data);
+ link->dc->res_pool->funcs->link_enc_create(dc_ctx,
_init_data);
if (!link->link_enc) {
DC_ERROR("Failed to create link encoder!\n");
diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
index 9ad8ad4550d9..54805802cbd5 100644
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
@@ -612,6 +612,7 @@ static const struct encoder_feature_support
link_enc_feature = {
};
static struct link_encoder *dce100_link_encoder_create(
+ struct dc_context *ctx,
const struct encoder_init_data *enc_init_data)
{
struct dce110_link_encoder *enc110 =
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
index 41804059550f..f808315b2835 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
@@ -660,6 +660,7 @@ static const struct encoder_feature_support
link_enc_feature = {
};
static struct link_encoder *dce110_link_encoder_create(
+ struct dc_context *ctx,
const struct encoder_init_data *enc_init_data)
{
struct dce110_link_encoder *enc110 =
diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
index 62da6bc3094d..e179e80667d1 100644
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
@@ -618,6 +618,7 @@ static const struct encoder_feature_support
link_enc_feature = {
};
static struct link_encoder *dce112_link_encoder_create(
+ struct dc_context *ctx,
const struct encoder_init_data *enc_init_data)
{
struct dce110_link_encoder *enc110 =
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
index c4353a03b48a..1b70b78e2fa1 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
@@ -697,6 +697,7 @@ static const struct encoder_feature_support
link_enc_feature = {
};
static struct link_encoder *dce120_link_encoder_create(
+ struct dc_context *ctx,
const struct encoder_init_data *enc_init_data)
{
struct dce110_link_encoder *enc110 =
diff --git a/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c
[PATCH 23/31] drm/amd/display: Cache cursor when cursor exceeds 64x64
From: Chris Park
[Why]
When Static screen from MALL, the cursor needs to be
cached if cursor exceeds 64x64 size.
[How]
Program the bit that cache cursor in MALL when size
of the cursor exceeds 64x64.
Reviewed-by: Jun Lei
Acked-by: Alan Liu
Acked-by: Alex Hung
Signed-off-by: Chris Park
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubp.c | 4 ++--
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubp.h | 2 +-
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c | 9 +++--
drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h | 2 +-
4 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubp.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubp.c
index 3176b04a7740..6ec1c52535b9 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubp.c
@@ -47,13 +47,13 @@ void hubp32_update_force_pstate_disallow(struct hubp *hubp,
bool pstate_disallow
DATA_UCLK_PSTATE_FORCE_VALUE, 0);
}
-void hubp32_update_mall_sel(struct hubp *hubp, uint32_t mall_sel)
+void hubp32_update_mall_sel(struct hubp *hubp, uint32_t mall_sel, bool
c_cursor)
{
struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
// Also cache cursor in MALL if using MALL for SS
REG_UPDATE_2(DCHUBP_MALL_CONFIG, USE_MALL_SEL, mall_sel,
- USE_MALL_FOR_CURSOR, mall_sel == 2 ? 1 : 0);
+ USE_MALL_FOR_CURSOR, c_cursor);
}
void hubp32_prepare_subvp_buffering(struct hubp *hubp, bool enable)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubp.h
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubp.h
index c4315d50fbb0..56ef71151536 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubp.h
@@ -52,7 +52,7 @@
void hubp32_update_force_pstate_disallow(struct hubp *hubp, bool
pstate_disallow);
-void hubp32_update_mall_sel(struct hubp *hubp, uint32_t mall_sel);
+void hubp32_update_mall_sel(struct hubp *hubp, uint32_t mall_sel, bool
c_cursor);
void hubp32_prepare_subvp_buffering(struct hubp *hubp, bool enable);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
index bf9ac9dfc7dd..1f845e9ac406 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
@@ -670,18 +670,23 @@ void dcn32_update_mall_sel(struct dc *dc, struct dc_state
*context)
{
int i;
unsigned int num_ways = dcn32_calculate_cab_allocation(dc, context);
+ bool cache_cursor = false;
for (i = 0; i < dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe = >res_ctx.pipe_ctx[i];
struct hubp *hubp = pipe->plane_res.hubp;
if (pipe->stream && pipe->plane_state && hubp &&
hubp->funcs->hubp_update_mall_sel) {
+ if (hubp->curs_attr.width * hubp->curs_attr.height * 4
> 16384)
+ cache_cursor = true;
+
if (pipe->stream->mall_stream_config.type ==
SUBVP_PHANTOM) {
- hubp->funcs->hubp_update_mall_sel(hubp,
1);
+ hubp->funcs->hubp_update_mall_sel(hubp,
1, false);
} else {
hubp->funcs->hubp_update_mall_sel(hubp,
num_ways <= dc->caps.cache_num_ways &&
-
pipe->stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED ? 2
: 0);
+
pipe->stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED ? 2
: 0,
+ cache_cursor);
}
}
}
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
index 906818e792dd..44c4578193a3 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
@@ -198,7 +198,7 @@ struct hubp_funcs {
void (*hubp_soft_reset)(struct hubp *hubp, bool reset);
void (*hubp_update_force_pstate_disallow)(struct hubp *hubp, bool
allow);
- void (*hubp_update_mall_sel)(struct hubp *hubp, uint32_t mall_sel);
+ void (*hubp_update_mall_sel)(struct hubp *hubp, uint32_t mall_sel, bool
c_cursor);
void (*hubp_prepare_subvp_buffering)(struct hubp *hubp, bool enable);
void (*hubp_set_flip_int)(struct hubp *hubp);
--
2.37.1
[PATCH 07/31] drm/amd/display: Calculate MALL cache lines based on Mblks required
From: Alvin Lee
[Description]
- Calculation for NumWays in MALL should be based on
number of MBlks
Reviewed-by: Jun Lei
Acked-by: Alex Hung
Signed-off-by: Alvin Lee
---
.../gpu/drm/amd/display/dc/dcn32/dcn32_resource.h | 1 +
.../amd/display/dc/dcn32/dcn32_resource_helpers.c | 15 ++-
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h
index efd449804d7b..1e7e6201c880 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h
@@ -29,6 +29,7 @@
#include "core_types.h"
#define DCN3_2_DET_SEG_SIZE 64
+#define DCN3_2_MALL_MBLK_SIZE_BYTES 65536 // 64 * 1024
#define TO_DCN32_RES_POOL(pool)\
container_of(pool, struct dcn32_resource_pool, base)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
index 47caa2c6d5b4..266c49884f04 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
@@ -51,6 +51,9 @@ uint32_t dcn32_helper_calculate_num_ways_for_subvp(struct dc
*dc, struct dc_stat
uint32_t cache_lines_used = 0;
uint32_t lines_per_way = 0;
uint32_t total_cache_lines = 0;
+ uint32_t bytes_in_mall = 0;
+ uint32_t num_mblks = 0;
+ uint32_t cache_lines_per_plane = 0;
uint32_t i = 0;
for (i = 0; i < dc->res_pool->pipe_count; i++) {
@@ -61,9 +64,19 @@ uint32_t dcn32_helper_calculate_num_ways_for_subvp(struct dc
*dc, struct dc_stat
pipe->stream->mall_stream_config.type ==
SUBVP_PHANTOM) {
bytes_per_pixel = pipe->plane_state->format >=
SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ? 8 : 4;
mall_region_pixels = pipe->stream->timing.h_addressable
* pipe->stream->timing.v_addressable;
+
+ // For bytes required in MALL, calculate based on
number of MBlks required
+ num_mblks = (mall_region_pixels * bytes_per_pixel +
+ DCN3_2_MALL_MBLK_SIZE_BYTES - 1) /
DCN3_2_MALL_MBLK_SIZE_BYTES;
+ bytes_in_mall = num_mblks * DCN3_2_MALL_MBLK_SIZE_BYTES;
// cache lines used is total bytes / cache_line size.
Add +2 for worst case alignment
// (MALL is 64-byte aligned)
- cache_lines_used += (bytes_per_pixel *
mall_region_pixels) / dc->caps.cache_line_size + 2;
+ cache_lines_per_plane = bytes_in_mall /
dc->caps.cache_line_size + 2;
+
+ // For DCC we must cache the meat surface, so double
cache lines required
+ if (pipe->plane_state->dcc.enable)
+ cache_lines_per_plane *= 2;
+ cache_lines_used += cache_lines_per_plane;
}
}
--
2.37.1
[PATCH 22/31] drm/amd/display: Add support for manual DMUB FAMS trigger
From: Anthony Koo
- Add is_drr parameter to indicate DRR is enabled on
the panel to determine whether SubVP MCLK switch
logic should be enabled
- Add DRR manual trigger in FW (instead of driver)
because manual trigger programming triggers DRR
update pending and can block SubVP MCLK switches
from taking place
Acked-by: Alex Hung
Signed-off-by: Anthony Koo
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index de193636d022..d7f3619352f0 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -976,7 +976,8 @@ struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 {
uint16_t vtotal;
uint8_t main_pipe_index;
uint8_t phantom_pipe_index;
- uint8_t padding[2];
+ uint8_t is_drr;
+ uint8_t padding;
} subvp_data;
struct {
@@ -1579,6 +1580,12 @@ enum dmub_cmd_fams_type {
DMUB_CMD__FAMS_SETUP_FW_CTRL= 0,
DMUB_CMD__FAMS_DRR_UPDATE = 1,
DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd
+ /**
+* For SubVP set manual trigger in FW because it
+* triggers DRR_UPDATE_PENDING which SubVP relies
+* on (for any SubVP cases that use a DRR display)
+*/
+ DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3,
};
/**
--
2.37.1
[PATCH 20/31] drm/amd/display: Add missing AUDIO_DTO_SEL reg field
From: Michael Strauss [WHY] Needed to program audio dto Reviewed-by: Nicholas Kazlauskas Acked-by: Alex Hung Signed-off-by: Michael Strauss --- drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.h index 99ba597bf9b7..9a4a9efc0203 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.h +++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.h @@ -147,7 +147,8 @@ DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P2_EN, mask_sh),\ DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P3_SRC_SEL, mask_sh),\ DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P3_EN, mask_sh),\ - DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh) + DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh),\ + DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh) struct dccg *dccg314_create( struct dc_context *ctx, -- 2.37.1
[PATCH 21/31] drm/amd/display: Fix dpstreamclk programming
From: Michael Strauss
[WHY]
Currently programming incorrect hpo inst as well as selecting incorrect source
[HOW]
Use hpo inst instead of otg inst to select dpstreamclk inst
Reviewed-by: Nicholas Kazlauskas
Acked-by: Alex Hung
Signed-off-by: Michael Strauss
---
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c | 8 +---
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h | 8 ++--
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c | 13 +++--
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c | 3 ++-
drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h| 3 ++-
.../gpu/drm/amd/display/dc/link/link_hwss_hpo_dp.c | 4 ++--
6 files changed, 20 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
index 799a383a2684..7f34418e6308 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
@@ -158,9 +158,11 @@ static void dccg31_disable_dpstreamclk(struct dccg *dccg,
int otg_inst)
}
}
-void dccg31_set_dpstreamclk(struct dccg *dccg,
- enum streamclk_source src,
- int otg_inst)
+void dccg31_set_dpstreamclk(
+ struct dccg *dccg,
+ enum streamclk_source src,
+ int otg_inst,
+ int dp_hpo_inst)
{
if (src == REFCLK)
dccg31_disable_dpstreamclk(dccg, otg_inst);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h
index 32b5593b1460..0902ce5eb8a1 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h
@@ -161,11 +161,6 @@ struct dccg *dccg31_create(
void dccg31_init(struct dccg *dccg);
-void dccg31_set_dpstreamclk(
- struct dccg *dccg,
- enum streamclk_source src,
- int otg_inst);
-
void dccg31_enable_symclk32_se(
struct dccg *dccg,
int hpo_se_inst,
@@ -207,7 +202,8 @@ void dccg31_get_dccg_ref_freq(
void dccg31_set_dpstreamclk(
struct dccg *dccg,
enum streamclk_source src,
- int otg_inst);
+ int otg_inst,
+ int dp_hpo_inst);
void dccg31_set_dtbclk_dto(
struct dccg *dccg,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c
b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c
index 3852a6d59b97..232cc15979dd 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c
@@ -184,7 +184,8 @@ void dccg314_set_dtbclk_dto(
void dccg314_set_dpstreamclk(
struct dccg *dccg,
enum streamclk_source src,
- int otg_inst)
+ int otg_inst,
+ int dp_hpo_inst)
{
struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
@@ -192,26 +193,26 @@ void dccg314_set_dpstreamclk(
dccg314_set_dtbclk_p_src(dccg, src, otg_inst);
/* enabled to select one of the DTBCLKs for pipe */
- switch (otg_inst) {
+ switch (dp_hpo_inst) {
case 0:
REG_UPDATE_2(DPSTREAMCLK_CNTL,
DPSTREAMCLK0_EN, (src == REFCLK) ? 0 :
1,
- DPSTREAMCLK0_SRC_SEL, 0);
+ DPSTREAMCLK0_SRC_SEL, otg_inst);
break;
case 1:
REG_UPDATE_2(DPSTREAMCLK_CNTL,
DPSTREAMCLK1_EN, (src == REFCLK) ? 0 :
1,
- DPSTREAMCLK1_SRC_SEL, 1);
+ DPSTREAMCLK1_SRC_SEL, otg_inst);
break;
case 2:
REG_UPDATE_2(DPSTREAMCLK_CNTL,
DPSTREAMCLK2_EN, (src == REFCLK) ? 0 :
1,
- DPSTREAMCLK2_SRC_SEL, 2);
+ DPSTREAMCLK2_SRC_SEL, otg_inst);
break;
case 3:
REG_UPDATE_2(DPSTREAMCLK_CNTL,
DPSTREAMCLK3_EN, (src == REFCLK) ? 0 :
1,
- DPSTREAMCLK3_SRC_SEL, 3);
+ DPSTREAMCLK3_SRC_SEL, otg_inst);
break;
default:
BREAK_TO_DEBUGGER();
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c
index 12fc3afd9acd..a31c64b50410 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c
@@ -211,7 +211,8 @@ static void dccg32_get_dccg_ref_freq(struct dccg *dccg,
void dccg32_set_dpstreamclk(
struct dccg *dccg,
enum streamclk_source src,
- int otg_inst)
+ int otg_inst,
+
[PATCH 19/31] drm/amd/display: Add OTG/ODM functions
From: Michael Strauss
[WHY]
Required for correct OTG_H_TIMING_CNTL programming
Reviewed-by: Nicholas Kazlauskas
Acked-by: Alex Hung
Signed-off-by: Michael Strauss
---
.../drm/amd/display/dc/dcn314/dcn314_optc.c | 34 +++
1 file changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_optc.c
b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_optc.c
index 3011f9e2f35c..0c7980266b85 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_optc.c
@@ -160,6 +160,37 @@ void optc314_phantom_crtc_post_enable(struct
timing_generator *optc)
REG_WAIT(OTG_CLOCK_CONTROL, OTG_BUSY, 0, 1, 10);
}
+static void optc314_set_odm_bypass(struct timing_generator *optc,
+ const struct dc_crtc_timing *dc_crtc_timing)
+{
+ struct optc *optc1 = DCN10TG_FROM_TG(optc);
+ enum h_timing_div_mode h_div = H_TIMING_NO_DIV;
+
+ REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,
+ OPTC_NUM_OF_INPUT_SEGMENT, 0,
+ OPTC_SEG0_SRC_SEL, optc->inst,
+ OPTC_SEG1_SRC_SEL, 0xf,
+ OPTC_SEG2_SRC_SEL, 0xf,
+ OPTC_SEG3_SRC_SEL, 0xf
+ );
+
+ h_div = optc1_is_two_pixels_per_containter(dc_crtc_timing);
+ REG_UPDATE(OTG_H_TIMING_CNTL,
+ OTG_H_TIMING_DIV_MODE, h_div);
+
+ REG_SET(OPTC_MEMORY_CONFIG, 0,
+ OPTC_MEM_SEL, 0);
+ optc1->opp_count = 1;
+}
+
+static void optc314_set_h_timing_div_manual_mode(struct timing_generator
*optc, bool manual_mode)
+{
+ struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+ REG_UPDATE(OTG_H_TIMING_CNTL,
+ OTG_H_TIMING_DIV_MODE_MANUAL, manual_mode ? 1 : 0);
+}
+
static struct timing_generator_funcs dcn314_tg_funcs = {
.validate_timing = optc1_validate_timing,
@@ -222,6 +253,9 @@ static struct timing_generator_funcs dcn314_tg_funcs = {
.setup_manual_trigger = optc2_setup_manual_trigger,
.get_hw_timing = optc1_get_hw_timing,
.init_odm = optc3_init_odm,
+ .set_odm_bypass = optc314_set_odm_bypass,
+ .set_odm_combine = optc314_set_odm_combine,
+ .set_h_timing_div_manual_mode =
optc314_set_h_timing_div_manual_mode,
};
void dcn314_timing_generator_init(struct optc *optc1)
--
2.37.1
[PATCH 18/31] drm/amd/display: Use correct clock source constructor for DCN314
From: Michael Strauss
[WHY]
Previously was pointing to DCN3 clock constructor rather than DCN31's
Reviewed-by: Nicholas Kazlauskas
Acked-by: Alex Hung
Signed-off-by: Michael Strauss
---
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
index 56ada096c89d..b5672fb90236 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
@@ -1782,7 +1782,7 @@ static struct clock_source *dcn31_clock_source_create(
if (!clk_src)
return NULL;
- if (dcn3_clk_src_construct(clk_src, ctx, bios, id,
+ if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
regs, _shift, _mask)) {
clk_src->base.dp_clk_src = dp_clk_src;
return _src->base;
--
2.37.1
[PATCH 17/31] drm/amd/display: Use correct DTO_SRC_SEL for 128b/132b encoding
From: Michael Strauss
[WHY]
DP DTO isn't used for 128b/132b encoding
[HOW]
Check current link rate to determine whether using 8b/10b or 128/132b encoding
Reviewed-by: Nicholas Kazlauskas
Acked-by: Alex Hung
Signed-off-by: Michael Strauss
---
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 1 +
.../drm/amd/display/dc/dce/dce_clock_source.c | 20 ++-
.../display/dc/dce110/dce110_hw_sequencer.c | 1 +
.../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 1 +
.../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 1 +
.../gpu/drm/amd/display/dc/inc/clock_source.h | 7 +--
6 files changed, 24 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index d380b8bc6f39..bdf6b8081716 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -7064,6 +7064,7 @@ void dp_enable_link_phy(
pipes[i].clock_source->funcs->program_pix_clk(
pipes[i].clock_source,
[i].stream_res.pix_clk_params,
+
dp_get_link_encoding_format(link_settings),
[i].pll_settings);
}
}
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
index d55da1ab1ac2..213de8cabfad 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
@@ -838,6 +838,7 @@ static void dce112_program_pixel_clk_resync(
static bool dce110_program_pix_clk(
struct clock_source *clock_source,
struct pixel_clk_params *pix_clk_params,
+ enum dp_link_encoding encoding,
struct pll_settings *pll_settings)
{
struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
@@ -911,6 +912,7 @@ static bool dce110_program_pix_clk(
static bool dce112_program_pix_clk(
struct clock_source *clock_source,
struct pixel_clk_params *pix_clk_params,
+ enum dp_link_encoding encoding,
struct pll_settings *pll_settings)
{
struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
@@ -970,6 +972,7 @@ static bool dce112_program_pix_clk(
static bool dcn31_program_pix_clk(
struct clock_source *clock_source,
struct pixel_clk_params *pix_clk_params,
+ enum dp_link_encoding encoding,
struct pll_settings *pll_settings)
{
struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
@@ -993,9 +996,14 @@ static bool dcn31_program_pix_clk(
#if defined(CONFIG_DRM_AMD_DC_DCN)
/* Enable DTO */
if (clk_src->cs_mask->PIPE0_DTO_SRC_SEL)
- REG_UPDATE_2(PIXEL_RATE_CNTL[inst],
- DP_DTO0_ENABLE, 1,
- PIPE0_DTO_SRC_SEL, 1);
+ if (encoding == DP_128b_132b_ENCODING)
+ REG_UPDATE_2(PIXEL_RATE_CNTL[inst],
+ DP_DTO0_ENABLE, 1,
+ PIPE0_DTO_SRC_SEL, 2);
+ else
+ REG_UPDATE_2(PIXEL_RATE_CNTL[inst],
+ DP_DTO0_ENABLE, 1,
+ PIPE0_DTO_SRC_SEL, 1);
else
REG_UPDATE(PIXEL_RATE_CNTL[inst],
DP_DTO0_ENABLE, 1);
@@ -1198,12 +1206,13 @@ const struct pixel_rate_range_table_entry
*look_up_in_video_optimized_rate_tlb(
static bool dcn20_program_pix_clk(
struct clock_source *clock_source,
struct pixel_clk_params *pix_clk_params,
+ enum dp_link_encoding encoding,
struct pll_settings *pll_settings)
{
struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
- dce112_program_pix_clk(clock_source, pix_clk_params, pll_settings);
+ dce112_program_pix_clk(clock_source, pix_clk_params, encoding,
pll_settings);
if (clock_source->ctx->dc->hwss.enable_vblanks_synchronization &&
clock_source->ctx->dc->config.vblank_alignment_max_frame_time_diff > 0) {
@@ -1243,6 +1252,7 @@ static const struct clock_source_funcs
dcn20_clk_src_funcs = {
static bool dcn3_program_pix_clk(
struct clock_source *clock_source,
struct pixel_clk_params *pix_clk_params,
+ enum dp_link_encoding encoding,
struct
[PATCH 16/31] drm/amd/display: Add pixel rate div calcs and programming
From: Michael Strauss
[WHY/HOW]
Need to calculate and set some pixel rate divisors on correct otg_inst
Reviewed-by: Nicholas Kazlauskas
Acked-by: Alex Hung
Signed-off-by: Michael Strauss
---
.../drm/amd/display/dc/dcn314/dcn314_dccg.c | 17 +
.../drm/amd/display/dc/dcn314/dcn314_hwseq.c | 36 +++
.../drm/amd/display/dc/dcn314/dcn314_hwseq.h | 2 ++
.../drm/amd/display/dc/dcn314/dcn314_init.c | 1 +
4 files changed, 56 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c
b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c
index ea78da9c6f8b..3852a6d59b97 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c
@@ -219,6 +219,21 @@ void dccg314_set_dpstreamclk(
}
}
+void dccg314_set_valid_pixel_rate(
+ struct dccg *dccg,
+ int ref_dtbclk_khz,
+ int otg_inst,
+ int pixclk_khz)
+{
+ struct dtbclk_dto_params dto_params = {0};
+
+ dto_params.ref_dtbclk_khz = ref_dtbclk_khz;
+ dto_params.otg_inst = otg_inst;
+ dto_params.pixclk_khz = pixclk_khz;
+
+ dccg314_set_dtbclk_dto(dccg, _params);
+}
+
static const struct dccg_funcs dccg314_funcs = {
.update_dpp_dto = dccg31_update_dpp_dto,
.get_dccg_ref_freq = dccg31_get_dccg_ref_freq,
@@ -237,6 +252,8 @@ static const struct dccg_funcs dccg314_funcs = {
.set_dispclk_change_mode = dccg31_set_dispclk_change_mode,
.disable_dsc = dccg31_disable_dscclk,
.enable_dsc = dccg31_enable_dscclk,
+ .set_pixel_rate_div = dccg314_set_pixel_rate_div,
+ .set_valid_pixel_rate = dccg314_set_valid_pixel_rate,
};
struct dccg *dccg314_create(
diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c
index 90ec76487264..755c715ad8dc 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c
@@ -338,3 +338,39 @@ void dcn314_enable_power_gating_plane(struct dce_hwseq
*hws, bool enable)
if (org_ip_request_cntl == 0)
REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
}
+
+unsigned int dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx,
unsigned int *k1_div, unsigned int *k2_div)
+{
+ struct dc_stream_state *stream = pipe_ctx->stream;
+ unsigned int odm_combine_factor = 0;
+
+ odm_combine_factor = get_odm_config(pipe_ctx, NULL);
+
+ if (is_dp_128b_132b_signal(pipe_ctx)) {
+ *k2_div = PIXEL_RATE_DIV_BY_1;
+ } else if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) ||
dc_is_dvi_signal(pipe_ctx->stream->signal)) {
+ *k1_div = PIXEL_RATE_DIV_BY_1;
+ if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
+ *k2_div = PIXEL_RATE_DIV_BY_2;
+ else
+ *k2_div = PIXEL_RATE_DIV_BY_4;
+ } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
+ if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
+ *k1_div = PIXEL_RATE_DIV_BY_1;
+ *k2_div = PIXEL_RATE_DIV_BY_2;
+ } else if (stream->timing.pixel_encoding ==
PIXEL_ENCODING_YCBCR422) {
+ *k1_div = PIXEL_RATE_DIV_BY_2;
+ *k2_div = PIXEL_RATE_DIV_BY_2;
+ } else {
+ if (odm_combine_factor == 1)
+ *k2_div = PIXEL_RATE_DIV_BY_4;
+ else if (odm_combine_factor == 2)
+ *k2_div = PIXEL_RATE_DIV_BY_2;
+ }
+ }
+
+ if ((*k1_div == PIXEL_RATE_DIV_NA) && (*k2_div == PIXEL_RATE_DIV_NA))
+ ASSERT(false);
+
+ return odm_combine_factor;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h
b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h
index dfdd0b792a52..be0f5e4d48e1 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h
@@ -37,4 +37,6 @@ void dcn314_dsc_pg_control(struct dce_hwseq *hws, unsigned
int dsc_inst, bool po
void dcn314_enable_power_gating_plane(struct dce_hwseq *hws, bool enable);
+unsigned int dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx,
unsigned int *k1_div, unsigned int *k2_div);
+
#endif /* __DC_HWSS_DCN314_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.c
b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.c
index c87b1979b2cc..b9debeb081fd 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.c
@@ -144,6 +144,7 @@ static const struct hwseq_private_funcs
dcn314_private_funcs = {
.set_blend_lut = dcn30_set_blend_lut,
.set_shaper_3dlut = dcn20_set_shaper_3dlut,
[PATCH 14/31] drm/amd/display: Create patch bounding box function for isolate FPU
From: Rodrigo Siqueira
In the DCN30 resource, we have a small patch to the bounding box struct;
this patch uses FPU operations. This commit moves that specific part to
its function under the DML folder.
Reviewed-by: Harry Wentland
Acked-by: Alex Hung
Signed-off-by: Rodrigo Siqueira
---
.../drm/amd/display/dc/dcn30/dcn30_resource.c | 19 ++
.../drm/amd/display/dc/dml/dcn30/dcn30_fpu.c | 20 +++
.../drm/amd/display/dc/dml/dcn30/dcn30_fpu.h | 2 ++
3 files changed, 24 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
index e5e54097a07d..8bdf3573610f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
@@ -1521,26 +1521,11 @@ static bool init_soc_bounding_box(struct dc *dc,
loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator;
loaded_ip->max_num_dpp = pool->base.pipe_count;
loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk;
-
- DC_FP_START();
dcn20_patch_bounding_box(dc, loaded_bb);
+ DC_FP_START();
+ patch_dcn30_soc_bounding_box(dc, _0_soc);
DC_FP_END();
- if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {
- struct bp_soc_bb_info bb_info = {0};
-
- if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios,
_info) == BP_RESULT_OK) {
- if (bb_info.dram_clock_change_latency_100ns > 0)
- dcn3_0_soc.dram_clock_change_latency_us =
bb_info.dram_clock_change_latency_100ns * 10;
-
- if (bb_info.dram_sr_enter_exit_latency_100ns > 0)
- dcn3_0_soc.sr_enter_plus_exit_time_us =
bb_info.dram_sr_enter_exit_latency_100ns * 10;
-
- if (bb_info.dram_sr_exit_latency_100ns > 0)
- dcn3_0_soc.sr_exit_time_us =
bb_info.dram_sr_exit_latency_100ns * 10;
- }
- }
-
return true;
}
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
index 9e32b45b63dc..6dd9a70314c0 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
@@ -721,3 +721,23 @@ void dcn3_fpu_build_wm_range_table(struct clk_mgr *base)
base->bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_uclk =
min_uclk_mhz;
base->bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_uclk =
0x;
}
+
+void patch_dcn30_soc_bounding_box(struct dc *dc, struct
_vcs_dpi_soc_bounding_box_st *dcn3_0_ip)
+{
+ dc_assert_fp_enabled();
+
+ if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {
+ struct bp_soc_bb_info bb_info = {0};
+
+ if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios,
_info) == BP_RESULT_OK) {
+ if (bb_info.dram_clock_change_latency_100ns > 0)
+ dcn3_0_soc.dram_clock_change_latency_us =
bb_info.dram_clock_change_latency_100ns * 10;
+
+ if (bb_info.dram_sr_enter_exit_latency_100ns > 0)
+ dcn3_0_soc.sr_enter_plus_exit_time_us =
bb_info.dram_sr_enter_exit_latency_100ns * 10;
+
+ if (bb_info.dram_sr_exit_latency_100ns > 0)
+ dcn3_0_soc.sr_exit_time_us =
bb_info.dram_sr_exit_latency_100ns * 10;
+ }
+ }
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.h
b/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.h
index 3e4221af1c1e..cab864095ce7 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.h
@@ -71,4 +71,6 @@ int
dcn30_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc,
void dcn3_fpu_build_wm_range_table(struct clk_mgr *base);
+void patch_dcn30_soc_bounding_box(struct dc *dc, struct
_vcs_dpi_soc_bounding_box_st *dcn3_0_ip);
+
#endif /* __DCN30_FPU_H__*/
--
2.37.1
[PATCH 15/31] drm/amd/display: Remove FPU flags from DCN30 Makefile
From: Rodrigo Siqueira At this stage, we must have all the FPU code for DCN30 isolated in the DML folder. Drop FPU flags from Makefile. Reviewed-by: Harry Wentland Acked-by: Alex Hung Signed-off-by: Rodrigo Siqueira --- drivers/gpu/drm/amd/display/dc/dcn30/Makefile | 30 --- 1 file changed, 30 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/Makefile b/drivers/gpu/drm/amd/display/dc/dcn30/Makefile index c20331eb62e0..b7c2ae9ddfda 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dcn30/Makefile @@ -30,36 +30,6 @@ DCN30 = dcn30_init.o dcn30_hubbub.o dcn30_hubp.o dcn30_dpp.o dcn30_optc.o \ dcn30_dpp_cm.o dcn30_dwb_cm.o dcn30_cm_common.o dcn30_mmhubbub.o \ dcn30_dio_link_encoder.o dcn30_resource.o - -ifdef CONFIG_X86 -CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_resource.o := -mhard-float -msse -CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_optc.o := -mhard-float -msse -endif - -ifdef CONFIG_PPC64 -CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_resource.o := -mhard-float -maltivec -CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_optc.o := -mhard-float -maltivec -endif - -ifdef CONFIG_CC_IS_GCC -ifeq ($(call cc-ifversion, -lt, 0701, y), y) -IS_OLD_GCC = 1 -endif -endif - -ifdef CONFIG_X86 -ifdef IS_OLD_GCC -# Stack alignment mismatch, proceed with caution. -# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3 -# (8B stack alignment). -CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_resource.o += -mpreferred-stack-boundary=4 -CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_optc.o += -mpreferred-stack-boundary=4 -else -CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_resource.o += -msse2 -CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_optc.o += -msse2 -endif -endif - AMD_DAL_DCN30 = $(addprefix $(AMDDALPATH)/dc/dcn30/,$(DCN30)) AMD_DISPLAY_FILES += $(AMD_DAL_DCN30) -- 2.37.1
[PATCH 13/31] drm/amd/display: Move mclk calculation function to DML
From: Rodrigo Siqueira
The function responsible for calculating the MCLK switching has FPU
operations. This commit moves it to the dcn30_fpu file.
Reviewed-by: Harry Wentland
Acked-by: Alex Hung
Signed-off-by: Rodrigo Siqueira
---
.../drm/amd/display/dc/dcn30/dcn30_resource.c | 38
.../drm/amd/display/dc/dml/dcn30/dcn30_fpu.c | 43 +++
.../drm/amd/display/dc/dml/dcn30/dcn30_fpu.h | 6 +++
3 files changed, 49 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
index 7f01463942fb..e5e54097a07d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
@@ -2031,44 +2031,6 @@ void
dcn30_setup_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, struct
context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 4U
* 1000U * 1000U * 1000U;
}
-/*
- * Finds dummy_latency_index when MCLK switching using firmware based
- * vblank stretch is enabled. This function will iterate through the
- * table of dummy pstate latencies until the lowest value that allows
- * dm_allow_self_refresh_and_mclk_switch to happen is found
- */
-int dcn30_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc,
struct dc_state *context,
- display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel)
-{
- const int max_latency_table_entries = 4;
- int dummy_latency_index = 0;
-
- while (dummy_latency_index < max_latency_table_entries) {
- context->bw_ctx.dml.soc.dram_clock_change_latency_us =
-
dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;
- dcn30_internal_validate_bw(dc, context, pipes, _cnt,
, false);
-
- if
(context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank
==
- dm_allow_self_refresh_and_mclk_switch)
- break;
-
- dummy_latency_index++;
- }
-
- if (dummy_latency_index == max_latency_table_entries) {
- ASSERT(dummy_latency_index != max_latency_table_entries);
- /* If the execution gets here, it means dummy p_states are
-* not possible. This should never happen and would mean
-* something is severely wrong.
-* Here we reset dummy_latency_index to 3, because it is
-* better to have underflows than system crashes.
-*/
- dummy_latency_index = 3;
- }
-
- return dummy_latency_index;
-}
-
void dcn30_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)
{
DC_FP_START();
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
index c00f759fdded..9e32b45b63dc 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
@@ -616,6 +616,49 @@ void dcn30_fpu_update_bw_bounding_box(struct dc *dc,
}
+/**
+ * Finds dummy_latency_index when MCLK switching using firmware based
+ * vblank stretch is enabled. This function will iterate through the
+ * table of dummy pstate latencies until the lowest value that allows
+ * dm_allow_self_refresh_and_mclk_switch to happen is found
+ */
+int dcn30_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc,
+ struct dc_state
*context,
+
display_e2e_pipe_params_st *pipes,
+ int pipe_cnt,
+ int vlevel)
+{
+ const int max_latency_table_entries = 4;
+ int dummy_latency_index = 0;
+
+ dc_assert_fp_enabled();
+
+ while (dummy_latency_index < max_latency_table_entries) {
+ context->bw_ctx.dml.soc.dram_clock_change_latency_us =
+
dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;
+ dcn30_internal_validate_bw(dc, context, pipes, _cnt,
, false);
+
+ if
(context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank
==
+ dm_allow_self_refresh_and_mclk_switch)
+ break;
+
+ dummy_latency_index++;
+ }
+
+ if (dummy_latency_index == max_latency_table_entries) {
+ ASSERT(dummy_latency_index != max_latency_table_entries);
+ /* If the execution gets here, it means dummy p_states are
+* not possible. This should never happen and would mean
+* something is severely wrong.
+* Here we reset dummy_latency_index to 3, because it is
+
[PATCH 12/31] drm/amd/display: Remove FPU operations from dcn201 resources
From: Rodrigo Siqueira
We have some FPU operations on the resource part of the DCN201. This
commit drops FPU flags and moves any required FPU code to the DML
folder.
Reviewed-by: Harry Wentland
Acked-by: Alex Hung
Signed-off-by: Rodrigo Siqueira
---
.../gpu/drm/amd/display/dc/dcn201/Makefile| 24 -
.../amd/display/dc/dcn201/dcn201_resource.c | 10 ++-
.../drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 87 +++
.../drm/amd/display/dc/dml/dcn20/dcn20_fpu.h | 4 +
4 files changed, 100 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/Makefile
b/drivers/gpu/drm/amd/display/dc/dcn201/Makefile
index 96cbd4ccd344..5c9ce2cebb0f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn201/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dcn201/Makefile
@@ -6,30 +6,6 @@ DCN201 = dcn201_init.o dcn201_resource.o dcn201_hwseq.o \
dcn201_mpc.o dcn201_hubp.o dcn201_opp.o dcn201_optc.o dcn201_dpp.o \
dcn201_dccg.o dcn201_link_encoder.o
-ifdef CONFIG_X86
-CFLAGS_$(AMDDALPATH)/dc/dcn201/dcn201_resource.o := -mhard-float -msse
-endif
-
-ifdef CONFIG_PPC64
-CFLAGS_$(AMDDALPATH)/dc/dcn201/dcn201_resource.o := -mhard-float -maltivec
-endif
-
-ifdef CONFIG_CC_IS_GCC
-ifeq ($(call cc-ifversion, -lt, 0701, y), y)
-IS_OLD_GCC = 1
-endif
-endif
-
-ifdef CONFIG_X86
-ifdef IS_OLD_GCC
-# Stack alignment mismatch, proceed with caution.
-# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
-# (8B stack alignment).
-CFLAGS_$(AMDDALPATH)/dc/dcn201/dcn201_resource.o +=
-mpreferred-stack-boundary=4
-else
-CFLAGS_$(AMDDALPATH)/dc/dcn201/dcn201_resource.o += -msse2
-endif
-endif
AMD_DAL_DCN201 = $(addprefix $(AMDDALPATH)/dc/dcn201/,$(DCN201))
AMD_DISPLAY_FILES += $(AMD_DAL_DCN201)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_resource.c
index 0bb7d3dd53fa..e549a79f3fe1 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_resource.c
@@ -1036,6 +1036,14 @@ static bool dcn201_get_dcc_compression_cap(const struct
dc *dc,
output);
}
+static void dcn201_populate_dml_writeback_from_context(struct dc *dc,
+ struct resource_context
*res_ctx,
+
display_e2e_pipe_params_st *pipes)
+{
+ DC_FP_START();
+ dcn201_populate_dml_writeback_from_context_fpu(dc, res_ctx, pipes);
+ DC_FP_END();
+}
static void dcn201_destroy_resource_pool(struct resource_pool **pool)
{
@@ -1067,8 +1075,8 @@ static struct resource_funcs dcn201_res_pool_funcs = {
.add_dsc_to_stream_resource = NULL,
.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
.acquire_idle_pipe_for_layer = dcn201_acquire_idle_pipe_for_layer,
+ .populate_dml_writeback_from_context =
dcn201_populate_dml_writeback_from_context,
.patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
- .populate_dml_writeback_from_context =
dcn20_populate_dml_writeback_from_context,
.set_mcif_arb_params = dcn20_set_mcif_arb_params,
.find_first_free_match_stream_enc_for_link =
dcn10_find_first_free_match_stream_enc_for_link
};
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
index eeeae52fe6fc..39428488a052 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
@@ -2303,3 +2303,90 @@ void dcn21_clk_mgr_set_bw_params_wm_table(struct
clk_bw_params *bw_params)
bw_params->wm_table.entries[WM_D].wm_type = WM_TYPE_RETRAINING;
bw_params->wm_table.entries[WM_D].valid = true;
}
+
+void dcn201_populate_dml_writeback_from_context_fpu(struct dc *dc,
+ struct resource_context
*res_ctx,
+ display_e2e_pipe_params_st
*pipes)
+{
+ int pipe_cnt, i, j;
+ double max_calc_writeback_dispclk;
+ double writeback_dispclk;
+ struct writeback_st dout_wb;
+
+ dc_assert_fp_enabled();
+
+ for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
+ struct dc_stream_state *stream = res_ctx->pipe_ctx[i].stream;
+
+ if (!stream)
+ continue;
+ max_calc_writeback_dispclk = 0;
+
+ /* Set writeback information */
+ pipes[pipe_cnt].dout.wb_enable = 0;
+ pipes[pipe_cnt].dout.num_active_wb = 0;
+ for (j = 0; j < stream->num_wb_info; j++) {
+ struct dc_writeback_info *wb_info =
>writeback_info[j];
+
+ if (wb_info->wb_enabled &&
wb_info->writeback_source_plane &&
+ (wb_info->writeback_source_plane ==
[PATCH 11/31] drm/amd/display: Fallback to SW cursor if SubVP + cursor too big
From: Alvin Lee [Description] - For SubVP cursor cannot be cached in MALL, therefore we will switch to SW cursor if the cursor size exceeds what can fit in the local DCN buffers (64x64x4) - Returning false / failure for set_cursor_attributes will fallback to SW cursor Reviewed-by: Jun Lei Acked-by: Alex Hung Signed-off-by: Alvin Lee --- drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index 6752ca44e6e0..f62d50901d92 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -328,6 +328,11 @@ bool dc_stream_set_cursor_attributes( } dc = stream->ctx->dc; + + if (attributes->height * attributes->width * 4 > 16384) + if (stream->mall_stream_config.type == SUBVP_MAIN) + return false; + stream->cursor_attributes = *attributes; dc_z10_restore(dc); -- 2.37.1
[PATCH 09/31] drm/amd/display: Reboot while unplug hdcp enabled dp from mst hub
From: hersen wu
[Why]
event_property_update does not check NULL pointer
[How]
check aconnector->base.state equals NULL
Reviewed-by: Bhawanpreet Lakha
Acked-by: Alex Hung
Signed-off-by: hersen wu
---
.../amd/display/amdgpu_dm/amdgpu_dm_hdcp.c| 34 ---
1 file changed, 22 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
index d76c8dfaf3f0..331dfb66c765 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
@@ -302,7 +302,7 @@ static void event_property_update(struct work_struct *work)
mutex_lock(_work->mutex);
- if (aconnector->base.state->commit) {
+ if (aconnector->base.state && aconnector->base.state->commit) {
ret =
wait_for_completion_interruptible_timeout(>base.state->commit->hw_done,
10 * HZ);
if (ret == 0) {
@@ -311,18 +311,26 @@ static void event_property_update(struct work_struct
*work)
}
}
- if (hdcp_work->encryption_status !=
MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF) {
- if (aconnector->base.state->hdcp_content_type ==
DRM_MODE_HDCP_CONTENT_TYPE0 &&
- hdcp_work->encryption_status <=
MOD_HDCP_ENCRYPTION_STATUS_HDCP2_TYPE0_ON)
- drm_hdcp_update_content_protection(>base,
DRM_MODE_CONTENT_PROTECTION_ENABLED);
- else if (aconnector->base.state->hdcp_content_type ==
DRM_MODE_HDCP_CONTENT_TYPE1 &&
-hdcp_work->encryption_status ==
MOD_HDCP_ENCRYPTION_STATUS_HDCP2_TYPE1_ON)
- drm_hdcp_update_content_protection(>base,
DRM_MODE_CONTENT_PROTECTION_ENABLED);
- } else {
- drm_hdcp_update_content_protection(>base,
DRM_MODE_CONTENT_PROTECTION_DESIRED);
+ if (aconnector->base.state) {
+ if (hdcp_work->encryption_status !=
MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF) {
+ if (aconnector->base.state->hdcp_content_type ==
+ DRM_MODE_HDCP_CONTENT_TYPE0 &&
+ hdcp_work->encryption_status <=
+ MOD_HDCP_ENCRYPTION_STATUS_HDCP2_TYPE0_ON)
+
drm_hdcp_update_content_protection(>base,
+ DRM_MODE_CONTENT_PROTECTION_ENABLED);
+ else if (aconnector->base.state->hdcp_content_type ==
+ DRM_MODE_HDCP_CONTENT_TYPE1 &&
+ hdcp_work->encryption_status ==
+
MOD_HDCP_ENCRYPTION_STATUS_HDCP2_TYPE1_ON)
+
drm_hdcp_update_content_protection(>base,
+ DRM_MODE_CONTENT_PROTECTION_ENABLED);
+ } else {
+ drm_hdcp_update_content_protection(>base,
+ DRM_MODE_CONTENT_PROTECTION_DESIRED);
+ }
}
-
mutex_unlock(_work->mutex);
drm_modeset_unlock(>mode_config.connection_mutex);
}
@@ -495,7 +503,9 @@ static void update_config(void *handle, struct
cp_psp_stream_config *config)
(!!aconnector->base.state) ?
aconnector->base.state->content_protection : -1,
(!!aconnector->base.state) ?
aconnector->base.state->hdcp_content_type : -1);
- hdcp_update_display(hdcp_work, link_index, aconnector,
conn_state->hdcp_content_type, false);
+ if (conn_state)
+ hdcp_update_display(hdcp_work, link_index, aconnector,
+ conn_state->hdcp_content_type, false);
}
--
2.37.1
[PATCH 10/31] drm/amd/display: Drop unnecessary FPU flags on dcn302 files
From: Rodrigo Siqueira We already isolated the DCN302 code in the DML folder, but we forgot to drop the FPU flags from the Makefile. This commit drops those flags. Reviewed-by: Harry Wentland Acked-by: Alex Hung Signed-off-by: Rodrigo Siqueira --- .../gpu/drm/amd/display/dc/dcn302/Makefile| 25 --- 1 file changed, 25 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn302/Makefile b/drivers/gpu/drm/amd/display/dc/dcn302/Makefile index e4b69ad0dde5..ebd01cb467b7 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn302/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dcn302/Makefile @@ -7,31 +7,6 @@ DCN3_02 = dcn302_init.o dcn302_hwseq.o dcn302_resource.o -ifdef CONFIG_X86 -CFLAGS_$(AMDDALPATH)/dc/dcn302/dcn302_resource.o := -mhard-float -msse -endif - -ifdef CONFIG_PPC64 -CFLAGS_$(AMDDALPATH)/dc/dcn302/dcn302_resource.o := -mhard-float -maltivec -endif - -ifdef CONFIG_X86 -ifdef CONFIG_CC_IS_GCC -ifeq ($(call cc-ifversion, -lt, 0701, y), y) -IS_OLD_GCC = 1 -endif -endif - -ifdef IS_OLD_GCC -# Stack alignment mismatch, proceed with caution. -# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3 -# (8B stack alignment). -CFLAGS_$(AMDDALPATH)/dc/dcn302/dcn302_resource.o += -mpreferred-stack-boundary=4 -else -CFLAGS_$(AMDDALPATH)/dc/dcn302/dcn302_resource.o += -msse2 -endif -endif - AMD_DAL_DCN3_02 = $(addprefix $(AMDDALPATH)/dc/dcn302/,$(DCN3_02)) AMD_DISPLAY_FILES += $(AMD_DAL_DCN3_02) -- 2.37.1
[PATCH 08/31] drm/amd/display: Reset pipe count when iterating for DET override
From: Taimur Hassan
[Why]
Coding error in DET allocation was resulting in too few DET segments
being allocated, causing underflow.
[How]
Reset pipe count each time we begin iterating through pipes for a stream.
Reviewed-by: Alvin Lee
Acked-by: Alex Hung
Signed-off-by: Taimur Hassan
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
index 266c49884f04..b3f8503cea9c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
@@ -184,7 +184,8 @@ void dcn32_determine_det_override(struct dc_state *context,
display_e2e_pipe_par
if (context->stream_count > 0) {
stream_segments = 18 / context->stream_count;
- for (i = 0, count = 0; i < context->stream_count; i++) {
+ for (i = 0; i < context->stream_count; i++) {
+ count = 0;
for (j = 0; j < pipe_cnt; j++) {
if (context->res_ctx.pipe_ctx[j].stream ==
context->streams[i]) {
count++;
--
2.37.1
[PATCH 06/31] drm/amd/display: Fix two MPO videos in single display ODM combine mode
From: Samson Tam
[Why]
In single display ODM combine mode, two MPO videos ( three
planes ) are not working
[How]
When we detect three planes, don't set odm combine 2to1 policy
for the MPO planes. Otherwise, we run out of pipes available
Add support for two MPO videos in dc_add_plane_to_context().
Don't allow both videos to be on the same side of the
display.
Add extra check when fetching free pipe for two MPO videos.
Reviewed-by: Alvin Lee
Acked-by: Alex Hung
Signed-off-by: Samson Tam
---
.../gpu/drm/amd/display/dc/core/dc_resource.c | 136 +---
.../drm/amd/display/dc/dcn32/dcn32_resource.c | 149 --
.../drm/amd/display/dc/dcn32/dcn32_resource.h | 6 +
3 files changed, 260 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 752ba4ab2b1e..ffc0f1c0ea93 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -1463,6 +1463,7 @@ bool dc_add_plane_to_context(
struct dc_stream_status *stream_status = NULL;
struct pipe_ctx *prev_right_head = NULL;
struct pipe_ctx *free_right_pipe = NULL;
+ struct pipe_ctx *prev_left_head = NULL;
DC_LOGGER_INIT(stream->ctx->logger);
for (i = 0; i < context->stream_count; i++)
@@ -1514,8 +1515,16 @@ bool dc_add_plane_to_context(
/* ODM + window MPO, where MPO window is on right half
only */
if (free_pipe->plane_state &&
- (free_pipe->plane_state->clip_rect.x >=
free_pipe->stream->src.x + free_pipe->stream->src.width/2) &&
- tail_pipe->next_odm_pipe) {
+ (free_pipe->plane_state->clip_rect.x >=
free_pipe->stream->src.x + free_pipe->stream->src.width/2) &&
+ tail_pipe->next_odm_pipe) {
+
+ /* For ODM + window MPO, in 3 plane case, if we
already have a MPO window on
+* the right side, then we will invalidate a
2nd one on the right side
+*/
+ if (head_pipe->next_odm_pipe &&
tail_pipe->next_odm_pipe->bottom_pipe) {
+ dc_plane_state_release(plane_state);
+ return false;
+ }
DC_LOG_SCALER("%s - ODM + window MPO(right).
free_pipe:%d tail_pipe->next_odm_pipe:%d\n",
__func__,
@@ -1530,20 +1539,42 @@ bool dc_add_plane_to_context(
* - If not, continue to use free_pipe
* - If the right side already has a pipe, use
that pipe instead if its available
*/
+
+ /*
+* We also want to avoid the case where with
three plane ( 2 MPO videos ), we have
+* both videos on the left side so one of the
videos is invalidated. Then we
+* move the invalidated video back to the
right side. If the order of the plane
+* states is such that the right MPO plane is
processed first, the free pipe
+* selected by the head will be the left MPO
pipe. But since there was no right
+* MPO pipe, it will assign the free pipe to
the right MPO pipe instead and
+* a pipe reallocation will occur.
+* Check the old context to see if the left
side already has a pipe allocated
+* - If not, continue to use free_pipe
+* - If the left side is already using this
pipe, then pick another pipe for right
+*/
+
prev_right_head =
>current_state->res_ctx.pipe_ctx[tail_pipe->next_odm_pipe->pipe_idx];
- if ((prev_right_head->bottom_pipe) &&
(free_pipe->pipe_idx != prev_right_head->bottom_pipe->pipe_idx)) {
+ if ((prev_right_head->bottom_pipe) &&
+ (free_pipe->pipe_idx !=
prev_right_head->bottom_pipe->pipe_idx)) {
free_right_pipe =
acquire_free_pipe_for_head(context, pool, tail_pipe->next_odm_pipe);
- if (free_right_pipe) {
- free_pipe->stream = NULL;
- memset(_pipe->stream_res,
0, sizeof(struct stream_resource));
- memset(_pipe->plane_res,
0, sizeof(struct
[PATCH 05/31] drm/amd/display: Guard against zero memory channels
From: Nicholas Kazlauskas [Why] If BIOS doesn't specify number of memory channels then bandwidth validation will fail due to insufficient BW in DML. [How] If BIOS is setting zero channels then use the default in the table. If no entry is in the table and no BIOS value is specified then throw an ASSERT for future developers to look into. Reviewed-by: Michael Strauss Acked-by: Alex Hung Signed-off-by: Nicholas Kazlauskas --- drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c index 450ebd838505..56ada096c89d 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c @@ -1916,8 +1916,11 @@ static void dcn314_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *b dcn3_14_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator; dcn3_14_ip.max_num_dpp = dc->res_pool->pipe_count; - dcn3_14_soc.num_chans = bw_params->num_channels; + if (bw_params->num_channels > 0) + dcn3_14_soc.num_chans = bw_params->num_channels; + + ASSERT(dcn3_14_soc.num_chans); ASSERT(clk_table->num_entries); /* Prepass to find max clocks independent of voltage level. */ -- 2.37.1
[PATCH 04/31] drm/amd/display: Updates SubVP and SubVP DRR cases
From: Alvin Lee
[Description]
- For any DRR cases in SubVP, don't lock for VSYNC flips
- For DCN32/321 use FW to do DRR manual trigger programming
- Add bit in SubVP cmd to indicate if the SubVP pipe is DRR
Reviewed-by: Jun Lei
Acked-by: Alex Hung
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 17 +
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h | 1 +
.../drm/amd/display/dc/dcn32/dcn32_hwseq.c| 7 +--
.../gpu/drm/amd/display/dc/dcn32/dcn32_optc.c | 63 ++-
4 files changed, 82 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
index 39b426d04037..2d61c2a91cee 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
@@ -270,6 +270,23 @@ void dc_dmub_srv_drr_update_cmd(struct dc *dc, uint32_t
tg_inst, uint32_t vtotal
dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);
}
+void dc_dmub_srv_set_drr_manual_trigger_cmd(struct dc *dc, uint32_t tg_inst)
+{
+ union dmub_rb_cmd cmd = { 0 };
+
+ cmd.drr_update.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH;
+ // TODO: Uncomment once FW headers are promoted
+ //cmd.drr_update.header.sub_type = DMUB_CMD__FAMS_SET_MANUAL_TRIGGER;
+ cmd.drr_update.dmub_optc_state_req.tg_inst = tg_inst;
+
+ cmd.drr_update.header.payload_bytes = sizeof(cmd.drr_update) -
sizeof(cmd.drr_update.header);
+
+ // Send the command to the DMCUB.
+ dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, );
+ dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
+ dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);
+}
+
static uint8_t dc_dmub_srv_get_pipes_for_stream(struct dc *dc, struct
dc_stream_state *stream)
{
uint8_t pipes = 0;
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
index 1d124a2695d5..159782cd6659 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
@@ -74,6 +74,7 @@ void dc_dmub_trace_event_control(struct dc *dc, bool enable);
void dc_dmub_srv_drr_update_cmd(struct dc *dc, uint32_t tg_inst, uint32_t
vtotal_min, uint32_t vtotal_max);
+void dc_dmub_srv_set_drr_manual_trigger_cmd(struct dc *dc, uint32_t tg_inst);
bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool enable_pstate, struct
dc_state *context);
void dc_dmub_srv_query_caps_cmd(struct dmub_srv *dmub);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
index b6bada383958..bf9ac9dfc7dd 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
@@ -424,7 +424,6 @@ void dcn32_subvp_pipe_control_lock(struct dc *dc,
unsigned int i = 0;
bool subvp_immediate_flip = false;
bool subvp_in_use = false;
- bool drr_pipe = false;
struct pipe_ctx *pipe;
for (i = 0; i < dc->res_pool->pipe_count; i++) {
@@ -440,12 +439,10 @@ void dcn32_subvp_pipe_control_lock(struct dc *dc,
if (top_pipe_to_program->stream->mall_stream_config.type ==
SUBVP_MAIN &&
top_pipe_to_program->plane_state->flip_immediate)
subvp_immediate_flip = true;
- else if (top_pipe_to_program->stream->mall_stream_config.type
== SUBVP_NONE &&
-
top_pipe_to_program->stream->ignore_msa_timing_param)
- drr_pipe = true;
}
- if ((subvp_in_use && (should_lock_all_pipes || subvp_immediate_flip ||
drr_pipe)) || (!subvp_in_use && subvp_prev_use)) {
+ // Don't need to lock for DRR VSYNC flips -- FW will wait for DRR
pending update cleared.
+ if ((subvp_in_use && (should_lock_all_pipes || subvp_immediate_flip))
|| (!subvp_in_use && subvp_prev_use)) {
union dmub_inbox0_cmd_lock_hw hw_lock_cmd = { 0 };
if (!lock) {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c
index 00ff21458a53..992e56c6907e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c
@@ -26,9 +26,11 @@
#include "dcn32_optc.h"
#include "dcn30/dcn30_optc.h"
+#include "dcn31/dcn31_optc.h"
#include "reg_helper.h"
#include "dc.h"
#include "dcn_calc_math.h"
+#include "dc_dmub_srv.h"
#define REG(reg)\
optc1->tg_regs->reg
@@ -188,6 +190,65 @@ static void optc32_set_odm_bypass(struct timing_generator
*optc,
optc1->opp_count = 1;
}
+void optc32_setup_manual_trigger(struct timing_generator *optc)
+{
+ struct optc *optc1 = DCN10TG_FROM_TG(optc);
+ struct dc *dc = optc->ctx->dc;
+
+ if (dc->caps.dmub_caps.mclk_sw && !dc->debug.disable_fams)
+ dc_dmub_srv_set_drr_manual_trigger_cmd(dc, optc->inst);
+ else {
+
[PATCH 03/31] drm/amd/display: Fix OPTC function pointers for DCN314
From: Nicholas Kazlauskas
[Why]
Access violation occurs when swapping between HDMI and FRL monitors
because we're missing the immediate_disable_crtc callback and it's
required for the DCN314 clk manager.
[How]
Update the table to match the DCN31 optc functions for ones that
should be the same:
- immediate_disable_crtc
- configure_crc
Reviewed-by: Michael Strauss
Acked-by: Alex Hung
Signed-off-by: Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c | 2 +-
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.h | 2 ++
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_optc.c | 3 ++-
3 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c
index c4304f25ce95..2f7404a97479 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c
@@ -141,7 +141,7 @@ static bool optc31_disable_crtc(struct timing_generator
*optc)
return true;
}
-static bool optc31_immediate_disable_crtc(struct timing_generator *optc)
+bool optc31_immediate_disable_crtc(struct timing_generator *optc)
{
struct optc *optc1 = DCN10TG_FROM_TG(optc);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.h
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.h
index 3706e6f7880e..30b81a448ce2 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.h
@@ -258,6 +258,8 @@
void dcn31_timing_generator_init(struct optc *optc1);
+bool optc31_immediate_disable_crtc(struct timing_generator *optc);
+
void optc31_set_drr(struct timing_generator *optc, const struct drr_params
*params);
void optc3_init_odm(struct timing_generator *optc);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_optc.c
b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_optc.c
index 436c3545a983..3011f9e2f35c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_optc.c
@@ -170,6 +170,7 @@ static struct timing_generator_funcs dcn314_tg_funcs = {
.program_global_sync = optc1_program_global_sync,
.enable_crtc = optc314_enable_crtc,
.disable_crtc = optc314_disable_crtc,
+ .immediate_disable_crtc = optc31_immediate_disable_crtc,
.phantom_crtc_post_enable = optc314_phantom_crtc_post_enable,
/* used by enable_timing_synchronization. Not need for FPGA */
.is_counter_moving = optc1_is_counter_moving,
@@ -204,7 +205,7 @@ static struct timing_generator_funcs dcn314_tg_funcs = {
.clear_optc_underflow = optc1_clear_optc_underflow,
.setup_global_swap_lock = NULL,
.get_crc = optc1_get_crc,
- .configure_crc = optc1_configure_crc,
+ .configure_crc = optc2_configure_crc,
.set_dsc_config = optc3_set_dsc_config,
.get_dsc_status = optc2_get_dsc_status,
.set_dwb_source = NULL,
--
2.37.1
[PATCH 02/31] drm/amd/display: Add enable/disable FIFO callbacks to stream setup
From: Nicholas Kazlauskas
[Why]
We don't write out attributes after disabling and re-enabling the link
on some monitors, causing some, but not all, HDMI displays to fail to
lightup on DCN314.
[How]
Firmware used to do this after DIG link setup.
Since firmware is no longer doing this to support USB4 and dynamic link
remapping we'll need to add this to driver in the equivalent paths.
New optional callbacks were created in the stream encoder interface and
implementations were added for DCN314.
Reviewed-by: Michael Strauss
Acked-by: Alex Hung
Signed-off-by: Nicholas Kazlauskas
---
.../dc/dcn314/dcn314_dio_stream_encoder.c | 38 +--
.../amd/display/dc/inc/hw/stream_encoder.h| 2 +
.../drm/amd/display/dc/link/link_hwss_dio.c | 7
3 files changed, 35 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dio_stream_encoder.c
b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dio_stream_encoder.c
index 2dbfa1c234dd..b384f30395d3 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dio_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dio_stream_encoder.c
@@ -50,6 +50,26 @@
enc1->base.ctx
+static void enc314_enable_fifo(struct stream_encoder *enc)
+{
+ struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
+
+ /* TODO: Confirm if we need to wait for DIG_SYMCLK_FE_ON */
+ REG_WAIT(DIG_FE_CNTL, DIG_SYMCLK_FE_ON, 1, 10, 5000);
+ REG_UPDATE_2(DIG_FIFO_CTRL0, DIG_FIFO_RESET, 1,
DIG_FIFO_READ_START_LEVEL, 0x7);
+ REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, 1, 10, 5000);
+ REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, 0);
+ REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, 0, 10, 5000);
+ REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, 1);
+}
+
+static void enc314_disable_fifo(struct stream_encoder *enc)
+{
+ struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
+
+ REG_UPDATE_2(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, 0,
+DIG_FIFO_READ_START_LEVEL, 0);
+}
static void enc314_dp_set_odm_combine(
struct stream_encoder *enc,
@@ -92,7 +112,7 @@ void enc314_stream_encoder_dvi_set_stream_attribute(
//DIG_SOURCE_SELECT is already set in dig_connect_to_otg
- /* DIG_START is removed from the register spec */
+ enc314_enable_fifo(enc);
}
ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB);
@@ -132,7 +152,7 @@ static void enc314_stream_encoder_hdmi_set_stream_attribute(
//DIG_SOURCE_SELECT is already set in dig_connect_to_otg
- /* DIG_START is removed from the register spec */
+ enc314_enable_fifo(enc);
}
/* Configure pixel encoding */
@@ -302,16 +322,8 @@ static void enc314_stream_encoder_dp_unblank(
REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0);
- /*
-* DIG Resync FIFO now needs to be explicitly enabled.
-* TODO: Confirm if we need to wait for DIG_SYMCLK_FE_ON
-*/
- REG_WAIT(DIG_FE_CNTL, DIG_SYMCLK_FE_ON, 1, 10, 5000);
- REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, 1);
- REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, 1, 10, 5000);
- REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, 0);
- REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, 0, 10, 5000);
- REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, 1);
+ /* DIG Resync FIFO now needs to be explicitly enabled. */
+ enc314_enable_fifo(enc);
/* wait 100us for DIG/DP logic to prime
* (i.e. a few video lines)
@@ -420,6 +432,8 @@ static const struct stream_encoder_funcs
dcn314_str_enc_funcs = {
.set_dynamic_metadata = enc2_set_dynamic_metadata,
.hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute,
+ .enable_fifo = enc314_enable_fifo,
+ .disable_fifo = enc314_disable_fifo,
.set_input_mode = enc314_set_dig_input_mode,
};
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
index 456dbe9f2264..42afa1952890 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
@@ -252,6 +252,8 @@ struct stream_encoder_funcs {
void (*set_input_mode)(
struct stream_encoder *enc, unsigned int pix_per_container);
+ void (*enable_fifo)(struct stream_encoder *enc);
+ void (*disable_fifo)(struct stream_encoder *enc);
};
struct hpo_dp_stream_encoder_state {
diff --git a/drivers/gpu/drm/amd/display/dc/link/link_hwss_dio.c
b/drivers/gpu/drm/amd/display/dc/link/link_hwss_dio.c
index 776e822abcbb..5e92019539c8 100644
--- a/drivers/gpu/drm/amd/display/dc/link/link_hwss_dio.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_hwss_dio.c
@@ -40,17 +40,24 @@ void set_dio_throttled_vcp_size(struct pipe_ctx *pipe_ctx,
void setup_dio_stream_encoder(struct
[PATCH 01/31] drm/amd/display: Avoid MPC infinite loop
From: Aric Cyr
[why]
In some cases MPC tree bottom pipe ends up point to itself. This causes
iterating from top to bottom to hang the system in an infinite loop.
[how]
When looping to next MPC bottom pipe, check that the pointer is not same
as current to avoid infinite loop.
Reviewed-by: Josip Pavic
Reviewed-by: Jun Lei
Acked-by: Alex Hung
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
index 11019c2c62cc..769974375b4b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
@@ -49,6 +49,11 @@ void mpc1_set_bg_color(struct mpc *mpc,
/* find bottommost mpcc. */
while (bottommost_mpcc->mpcc_bot) {
+ /* avoid circular linked link */
+ ASSERT(bottommost_mpcc != bottommost_mpcc->mpcc_bot);
+ if (bottommost_mpcc == bottommost_mpcc->mpcc_bot)
+ break;
+
bottommost_mpcc = bottommost_mpcc->mpcc_bot;
}
--
2.37.1
[PATCH 00/31] DC Patches July 22, 2022
This DC patchset brings improvements in multiple areas. In summary, we highlight: * Copy crc_skip_count when duplicating CRTC state * Add debug option for idle optimizations on cursor updates * Disable MPC split for DCN32/321 * Add missing ODM 2:1 policy logic * Update DCN32 and DCN321 SR latencies * Add reinstate dram in the FPO logic * Add dc_ctx to link_enc_create() parameters * Cache cursor when cursor exceeds 64x64 * Add support for manual DMUB FAMS trigger * Fix dpstreamclk programming * Add missing AUDIO_DTO_SEL reg field * Add OTG/ODM functions * Use correct clock source constructor for DCN314 * Use correct DTO_SRC_SEL for 128b/132b encoding * Add pixel rate div calcs and programming * Remove FPU flags from DCN30 Makefile * Create patch bounding box function for isolate FPU * Move mclk calculation function to DML * Remove FPU operations from dcn201 resources * Fallback to SW cursor if SubVP + cursor too big * Drop unnecessary FPU flags on dcn302 files * Reboot while unplug hdcp enabled dp from mst hub * Reset pipe count when iterating for DET override * Calculate MALL cache lines based on Mblks required * Fix two MPO videos in single display ODM combine mode * Guard against zero memory channels * Updates SubVP + SubVP DRR cases updates * Fix OPTC function pointers for DCN314 * Add enable/disable FIFO callbacks to stream setup * Avoid MPC infinite loop Alvin Lee (6): drm/amd/display: Updates SubVP and SubVP DRR cases drm/amd/display: Calculate MALL cache lines based on Mblks required drm/amd/display: Fallback to SW cursor if SubVP + cursor too big drm/amd/display: Update DCN32 and DCN321 SR latencies drm/amd/display: Disable MPC split for DCN32/321 drm/amd/display: Add debug option for idle optimizations on cursor updates Anthony Koo (2): drm/amd/display: Add support for manual DMUB FAMS trigger drm/amd/display: 3.2.196 Aric Cyr (1): drm/amd/display: Avoid MPC infinite loop Aurabindo Pillai (1): drm/amd/display: Add dc_ctx to link_enc_create() parameters Chris Park (1): drm/amd/display: Cache cursor when cursor exceeds 64x64 Leo Li (1): drm/amd/display: Copy crc_skip_count when duplicating CRTC state Michael Strauss (6): drm/amd/display: Add pixel rate div calcs and programming drm/amd/display: Use correct DTO_SRC_SEL for 128b/132b encoding drm/amd/display: Use correct clock source constructor for DCN314 drm/amd/display: Add OTG/ODM functions drm/amd/display: Add missing AUDIO_DTO_SEL reg field drm/amd/display: Fix dpstreamclk programming Nicholas Kazlauskas (3): drm/amd/display: Add enable/disable FIFO callbacks to stream setup drm/amd/display: Fix OPTC function pointers for DCN314 drm/amd/display: Guard against zero memory channels Rodrigo Siqueira (6): drm/amd/display: Drop unnecessary FPU flags on dcn302 files drm/amd/display: Remove FPU operations from dcn201 resources drm/amd/display: Move mclk calculation function to DML drm/amd/display: Create patch bounding box function for isolate FPU drm/amd/display: Remove FPU flags from DCN30 Makefile drm/amd/display: Add reinstate dram in the FPO logic Samson Tam (2): drm/amd/display: Fix two MPO videos in single display ODM combine mode drm/amd/display: Add missing ODM 2:1 policy logic Taimur Hassan (1): drm/amd/display: Reset pipe count when iterating for DET override hersen wu (1): drm/amd/display: Reboot while unplug hdcp enabled dp from mst hub .../amd/display/amdgpu_dm/amdgpu_dm_crtc.c| 1 + .../amd/display/amdgpu_dm/amdgpu_dm_hdcp.c| 34 ++-- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 +- .../gpu/drm/amd/display/dc/core/dc_link_dp.c | 1 + .../gpu/drm/amd/display/dc/core/dc_resource.c | 136 +--- .../gpu/drm/amd/display/dc/core/dc_stream.c | 5 + drivers/gpu/drm/amd/display/dc/dc.h | 2 +- drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 17 ++ drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h | 1 + .../drm/amd/display/dc/dce/dce_clock_source.c | 20 ++- .../amd/display/dc/dce100/dce100_resource.c | 1 + .../display/dc/dce110/dce110_hw_sequencer.c | 1 + .../amd/display/dc/dce110/dce110_resource.c | 1 + .../amd/display/dc/dce112/dce112_resource.c | 1 + .../amd/display/dc/dce120/dce120_resource.c | 1 + .../drm/amd/display/dc/dce60/dce60_resource.c | 1 + .../drm/amd/display/dc/dce80/dce80_resource.c | 1 + .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 1 + .../gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c | 5 + .../drm/amd/display/dc/dcn10/dcn10_resource.c | 1 + .../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 1 + .../drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +- .../drm/amd/display/dc/dcn20/dcn20_resource.h | 1 + .../gpu/drm/amd/display/dc/dcn201/Makefile| 24 --- .../amd/display/dc/dcn201/dcn201_resource.c | 11 +- .../drm/amd/display/dc/dcn21/dcn21_resource.c | 1 + drivers/gpu/drm/amd/display/dc/dcn30/Makefile | 30
[PATCH 4/4] drm/amdgpu: Document gfx_off members of struct amdgpu_gfx
Add comments to document gfx_off related members of struct amdgpu_gfx.
Signed-off-by: André Almeida
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index f06e979e2565..a552a49c1b25 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -332,12 +332,12 @@ struct amdgpu_gfx {
uint32_tsrbm_soft_reset;
/* gfx off */
- boolgfx_off_state; /* true: enabled, false:
disabled */
- struct mutexgfx_off_mutex;
- uint32_tgfx_off_req_count; /* default 1, enable
gfx off: dec 1, disable gfx off: add 1 */
- struct delayed_work gfx_off_delay_work;
- uint32_tgfx_off_residency;
- uint32_tgfx_off_entrycount;
+ boolgfx_off_state; /* true: enabled,
false: disabled */
+ struct mutexgfx_off_mutex; /* mutex to change
gfxoff state */
+ uint32_tgfx_off_req_count; /* default 1,
enable gfx off: dec 1, disable gfx off: add 1 */
+ struct delayed_work gfx_off_delay_work; /* async work to
set gfx block off */
+ uint32_tgfx_off_residency; /* last logged
residency */
+ uint32_tgfx_off_entrycount; /* count of times
GPU has get into GFXOFF state */
/* pipe reservation */
struct mutexpipe_reserve_mutex;
--
2.37.1
[PATCH 3/4] Documentation/gpu: Document GFXOFF's count and residency
Add documentation explaining those two new files. Signed-off-by: André Almeida --- Documentation/gpu/amdgpu/thermal.rst | 14 ++ 1 file changed, 14 insertions(+) diff --git a/Documentation/gpu/amdgpu/thermal.rst b/Documentation/gpu/amdgpu/thermal.rst index 997231b6adcf..c31f94c6c681 100644 --- a/Documentation/gpu/amdgpu/thermal.rst +++ b/Documentation/gpu/amdgpu/thermal.rst @@ -104,3 +104,17 @@ Read it to check current GFXOFF's status of a GPU:: If GFXOFF is enabled, the value will be transitioning around [0, 3], always getting into 0 when possible. When it's disabled, it's always at 2. Returns ``-EINVAL`` if it's not supported. + +``amdgpu_gfxoff_count`` +--- + +Read it to get the total GFXOFF entry count at the time of query since system +power-up. *Only supported in vangogh* + +``amdgpu_gfxoff_residency`` +--- + +Write 1 to amdgpu_gfxoff_residency to start logging, and 0 to stop. Read it to +get average GFXOFF residency % multiplied by 100 during the last logging +interval. E.g. a value of 7854 means 78.54% of the time in the last logging +interval the GPU was in GFXOFF mode. *Only supported in vangogh* -- 2.37.1
[PATCH 2/4] drm/amd/pm: Implement GFXOFF's entry count and residency for vangogh
Implement functions to get and set GFXOFF's entry count and residency
for vangogh.
Signed-off-by: André Almeida
---
.../pm/swsmu/inc/pmfw_if/smu_v11_5_ppsmc.h| 5 +-
drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h | 5 +-
.../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 92 +++
3 files changed, 100 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_5_ppsmc.h
b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_5_ppsmc.h
index fe130a497d6c..7471e2df2828 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_5_ppsmc.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_5_ppsmc.h
@@ -108,7 +108,10 @@
#define PPSMC_MSG_SetSlowPPTLimit 0x4A
#define PPSMC_MSG_GetFastPPTLimit 0x4B
#define PPSMC_MSG_GetSlowPPTLimit 0x4C
-#define PPSMC_Message_Count0x4D
+#define PPSMC_MSG_GetGfxOffStatus 0x50
+#define PPSMC_MSG_GetGfxOffEntryCount 0x51
+#define PPSMC_MSG_LogGfxOffResidency 0x52
+#define PPSMC_Message_Count0x53
//Argument for PPSMC_MSG_GfxDeviceDriverReset
enum {
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
index 19084a4fcb2b..76fb6cbbc09c 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
@@ -235,7 +235,10 @@
__SMU_DUMMY_MAP(UnforceGfxVid), \
__SMU_DUMMY_MAP(HeavySBR), \
__SMU_DUMMY_MAP(SetBadHBMPagesRetiredFlagsPerChannel), \
- __SMU_DUMMY_MAP(EnableGfxImu),
+ __SMU_DUMMY_MAP(EnableGfxImu), \
+ __SMU_DUMMY_MAP(GetGfxOffStatus),\
+ __SMU_DUMMY_MAP(GetGfxOffEntryCount),\
+ __SMU_DUMMY_MAP(LogGfxOffResidency),
#undef __SMU_DUMMY_MAP
#define __SMU_DUMMY_MAP(type) SMU_MSG_##type
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
index 89504ff8e9ed..fff70f58a23c 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
@@ -138,6 +138,9 @@ static struct cmn2asic_msg_mapping
vangogh_message_map[SMU_MSG_MAX_COUNT] = {
MSG_MAP(SetSlowPPTLimit,PPSMC_MSG_SetSlowPPTLimit,
0),
MSG_MAP(GetFastPPTLimit,PPSMC_MSG_GetFastPPTLimit,
0),
MSG_MAP(GetSlowPPTLimit,PPSMC_MSG_GetSlowPPTLimit,
0),
+ MSG_MAP(GetGfxOffStatus,PPSMC_MSG_GetGfxOffStatus,
0),
+ MSG_MAP(GetGfxOffEntryCount,
PPSMC_MSG_GetGfxOffEntryCount, 0),
+ MSG_MAP(LogGfxOffResidency,
PPSMC_MSG_LogGfxOffResidency, 0),
};
static struct cmn2asic_mapping vangogh_feature_mask_map[SMU_FEATURE_COUNT] = {
@@ -2200,6 +2203,92 @@ static int vangogh_set_power_limit(struct smu_context
*smu,
return ret;
}
+/**
+ * vangogh_set_gfxoff_residency
+ *
+ * @smu: amdgpu_device pointer
+ * @start: start/stop residency log
+ *
+ * This function will be used to log gfxoff residency
+ *
+ *
+ * Returns standard response codes.
+ */
+static u32 vangogh_set_gfxoff_residency(struct smu_context *smu, bool start)
+{
+ int ret = 0;
+ u32 residency;
+ struct amdgpu_device *adev = smu->adev;
+
+ switch (adev->ip_versions[MP1_HWIP][0]) {
+ case IP_VERSION(11, 5, 0):
+ if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
+ return 0;
+ ret = smu_cmn_send_smc_msg_with_param(smu,
SMU_MSG_LogGfxOffResidency,
+ start, );
+ if (!start)
+ adev->gfx.gfx_off_residency = residency;
+ break;
+ default:
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * vangogh_get_gfxoff_residency
+ *
+ * @smu: amdgpu_device pointer
+ *
+ * This function will be used to get gfxoff residency.
+ *
+ * Returns standard response codes.
+ */
+static u32 vangogh_get_gfxoff_residency(struct smu_context *smu, uint32_t
*residency)
+{
+ int ret = 0;
+ struct amdgpu_device *adev = smu->adev;
+
+ switch (adev->ip_versions[MP1_HWIP][0]) {
+ case IP_VERSION(11, 5, 0):
+ *residency = adev->gfx.gfx_off_residency;
+ break;
+ default:
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * vangogh_get_gfxoff_entrycount - get gfxoff entry count
+ *
+ * @smu: amdgpu_device pointer
+ *
+ * This function will be used to get gfxoff entry count
+ *
+ * Returns standard
[PATCH 1/4] drm/amd: Add detailed GFXOFF stats to debugfs
Add debugfs interface to log GFXOFF statistics:
- Read amdgpu_gfxoff_count to get the total GFXOFF entry count at the
time of query since system power-up
- Write 1 to amdgpu_gfxoff_residency to start logging, and 0 to stop.
Read it to get average GFXOFF residency % multiplied by 100
during the last logging interval.
Both features are designed to be keep the values persistent between
suspends.
Signed-off-by: André Almeida
---
drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 168 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 2 +
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 39
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 6 +
drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 45 +
drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h | 3 +
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 34 +++-
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 22 +++
drivers/gpu/drm/amd/pm/swsmu/smu_internal.h | 3 +
9 files changed, 321 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index e2eec985adb3..edf90a9ba980 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -1042,6 +1042,157 @@ static ssize_t amdgpu_debugfs_gpr_read(struct file *f,
char __user *buf,
return r;
}
+/**
+ * amdgpu_debugfs_gfxoff_residency_read - Read GFXOFF residency
+ *
+ * @f: open file handle
+ * @buf: User buffer to store read data in
+ * @size: Number of bytes to read
+ * @pos: Offset to seek to
+ *
+ * Read the last residency value logged. It doesn't auto update, one needs to
+ * stop logging before getting the current value.
+ */
+static ssize_t amdgpu_debugfs_gfxoff_residency_read(struct file *f, char
__user *buf,
+ size_t size, loff_t *pos)
+{
+ struct amdgpu_device *adev = file_inode(f)->i_private;
+ ssize_t result = 0;
+ int r;
+
+ if (size & 0x3 || *pos & 0x3)
+ return -EINVAL;
+
+ r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
+ if (r < 0) {
+ pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
+ return r;
+ }
+
+ while (size) {
+ uint32_t value;
+
+ r = amdgpu_get_gfx_off_residency(adev, );
+ if (r)
+ goto out;
+
+ r = put_user(value, (uint32_t *)buf);
+ if (r)
+ goto out;
+
+ result += 4;
+ buf += 4;
+ *pos += 4;
+ size -= 4;
+ }
+
+ r = result;
+out:
+ pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
+ pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
+
+ return r;
+}
+
+/**
+ * amdgpu_debugfs_gfxoff_residency_write - Log GFXOFF Residency
+ *
+ * @f: open file handle
+ * @buf: User buffer to write data from
+ * @size: Number of bytes to write
+ * @pos: Offset to seek to
+ *
+ * Write a 32-bit non-zero to start logging; write a 32-bit zero to stop
+ */
+static ssize_t amdgpu_debugfs_gfxoff_residency_write(struct file *f, const
char __user *buf,
+size_t size, loff_t *pos)
+{
+ struct amdgpu_device *adev = file_inode(f)->i_private;
+ ssize_t result = 0;
+ int r;
+
+ if (size & 0x3 || *pos & 0x3)
+ return -EINVAL;
+
+ r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
+ if (r < 0) {
+ pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
+ return r;
+ }
+
+ while (size) {
+ u32 value;
+
+ r = get_user(value, (uint32_t *)buf);
+ if (r)
+ goto out;
+
+ amdgpu_set_gfx_off_residency(adev, value ? true : false);
+
+ result += 4;
+ buf += 4;
+ *pos += 4;
+ size -= 4;
+ }
+
+ r = result;
+out:
+ pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
+ pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
+
+ return r;
+}
+
+
+/**
+ * amdgpu_debugfs_gfxoff_count_read - Read GFXOFF entry count
+ *
+ * @f: open file handle
+ * @buf: User buffer to store read data in
+ * @size: Number of bytes to read
+ * @pos: Offset to seek to
+ */
+static ssize_t amdgpu_debugfs_gfxoff_count_read(struct file *f, char __user
*buf,
+ size_t size, loff_t *pos)
+{
+ struct amdgpu_device *adev = file_inode(f)->i_private;
+ ssize_t result = 0;
+ int r;
+
+ if (size & 0x3 || *pos & 0x3)
+ return -EINVAL;
+
+ r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
+ if (r < 0) {
+ pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
+ return r;
+ }
+
+ while (size) {
+ u32 value;
+
+
[PATCH 0/4] drm/amd: Add more GFXOFF stats for vangogh
This series adds new logging features for GFXOFF available for vangogh and documentation for it. I've created a small userspace program to interact with this new debugfs interface and it can be found at: https://gitlab.freedesktop.org/andrealmeid/gfxoff_tool André Almeida (4): drm/amd: Add detailed GFXOFF stats to debugfs drm/amd/pm: Implement GFXOFF's entry count and residency for vangogh Documentation/gpu: Document GFXOFF's count and residency drm/amdgpu: Document gfx_off members of struct amdgpu_gfx Documentation/gpu/amdgpu/thermal.rst | 14 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 168 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 39 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 14 +- drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 45 + drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h | 3 + drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 34 +++- drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 22 +++ .../pm/swsmu/inc/pmfw_if/smu_v11_5_ppsmc.h| 5 +- drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h | 5 +- .../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 92 ++ drivers/gpu/drm/amd/pm/swsmu/smu_internal.h | 3 + 13 files changed, 439 insertions(+), 7 deletions(-) -- 2.37.1
Re: [PATCH v2 3/4] drm/amd/display: Remove parameters from rq_dlg_get_dlg_reg
Hi Maira,
First of all, thanks a lot for this patch. This change is really helpful
for reducing the stack size. I just have few comments inline.
On 2022-07-21 14:36, Maíra Canal wrote:
Across all DCN's (except DCN32, that has a separate
rq_dlg_get_dlg_reg), the parameters const bool vm_en, const bool
ignore_viewport_pos, and const bool immediate_flip_support are not used
on the function. Therefore, change the rq_dlg_get_dlg_reg signature
by deleting those parameters.
Signed-off-by: Maíra Canal
---
v1 -> v2:
- Replace "enum" to "enum entries" (André Almeida).
---
.../drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 3 +--
.../dc/dml/dcn20/display_rq_dlg_calc_20.c | 5 +
.../dc/dml/dcn20/display_rq_dlg_calc_20.h | 5 +
.../dc/dml/dcn20/display_rq_dlg_calc_20v2.c | 5 +
.../dc/dml/dcn20/display_rq_dlg_calc_20v2.h | 5 +
.../dc/dml/dcn21/display_rq_dlg_calc_21.c | 5 +
.../dc/dml/dcn21/display_rq_dlg_calc_21.h | 5 +
.../dc/dml/dcn30/display_rq_dlg_calc_30.c | 18 +++---
.../dc/dml/dcn30/display_rq_dlg_calc_30.h | 5 +
.../dc/dml/dcn31/display_rq_dlg_calc_31.c | 19 +++
.../dc/dml/dcn31/display_rq_dlg_calc_31.h | 5 +
.../dc/dml/dcn314/display_rq_dlg_calc_314.c | 15 ++-
.../dc/dml/dcn314/display_rq_dlg_calc_314.h | 5 +
.../drm/amd/display/dc/dml/display_mode_lib.h | 5 +
.../gpu/drm/amd/display/dc/dml/dml_wrapper.c | 3 +--
15 files changed, 20 insertions(+), 88 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
index dc60b835e938..d9cfb29a2651 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
@@ -857,8 +857,7 @@ void dcn20_calculate_dlg_params(
pipe_cnt,
pipe_idx,
cstate_en,
-
context->bw_ctx.bw.dcn.clk.p_state_change_support,
- false, false, true);
+
context->bw_ctx.bw.dcn.clk.p_state_change_support);
context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg(>bw_ctx.dml,
>res_ctx.pipe_ctx[i].rq_regs,
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
index 548cdef8a8ad..d0a4c69b47c8 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
@@ -1553,10 +1553,7 @@ void dml20_rq_dlg_get_dlg_reg(struct display_mode_lib
*mode_lib,
const unsigned int num_pipes,
const unsigned int pipe_idx,
const bool cstate_en,
- const bool pstate_en,
- const bool vm_en,
- const bool ignore_viewport_pos,
- const bool immediate_flip_support)
+ const bool pstate_en)
{
display_rq_params_st rq_param = {0};
display_dlg_sys_params_st dlg_sys_param = {0};
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.h
b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.h
index 8b23867e97c1..36c3692e53b8 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.h
@@ -65,9 +65,6 @@ void dml20_rq_dlg_get_dlg_reg(
const unsigned int num_pipes,
const unsigned int pipe_idx,
const bool cstate_en,
- const bool pstate_en,
- const bool vm_en,
- const bool ignore_viewport_pos,
- const bool immediate_flip_support);
+ const bool pstate_en);
#endif
diff --git
a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
index 0fc9f3e3ffae..17df9d31c11f 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
@@ -1554,10 +1554,7 @@ void dml20v2_rq_dlg_get_dlg_reg(struct display_mode_lib
*mode_lib,
const unsigned int num_pipes,
const unsigned int pipe_idx,
const bool cstate_en,
- const bool pstate_en,
- const bool vm_en,
- const bool ignore_viewport_pos,
- const bool immediate_flip_support)
+ const bool pstate_en)
{
display_rq_params_st rq_param = {0};
display_dlg_sys_params_st dlg_sys_param = {0};
diff --git
a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.h
b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.h
index
Re: [PATCH] drm/amd: Fix typo 'the the' in comment
Applied. Thanks!
Alex
On Thu, Jul 21, 2022 at 3:26 AM Slark Xiao wrote:
>
> Replace 'the the' with 'the' in the comment.
>
> Signed-off-by: Slark Xiao
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 2 +-
> drivers/gpu/drm/amd/include/atombios.h| 4 ++--
> 2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
> index ff659d4f772b..8adeb7469f1e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
> @@ -47,7 +47,7 @@
> * for GPU/CPU synchronization. When the fence is written,
> * it is expected that all buffers associated with that fence
> * are no longer in use by the associated ring on the GPU and
> - * that the the relevant GPU caches have been flushed.
> + * that the relevant GPU caches have been flushed.
> */
>
> struct amdgpu_fence {
> diff --git a/drivers/gpu/drm/amd/include/atombios.h
> b/drivers/gpu/drm/amd/include/atombios.h
> index 1f9df4e7509b..15943bc21bc5 100644
> --- a/drivers/gpu/drm/amd/include/atombios.h
> +++ b/drivers/gpu/drm/amd/include/atombios.h
> @@ -3255,8 +3255,8 @@ ucMaxNBVoltageHigh: Voltage regulator dependent PWM
> value. High 8 bits of t
> ucMinNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits
> of the value for the min voltage.Set this one to 0x00 if VC without PWM or no
> VC at all.
>
>
> -usInterNBVoltageLow:Voltage regulator dependent PWM value. The value
> makes the the voltage >=Min NB voltage but <=InterNBVoltageHigh. Set this to
> 0x if VC without PWM or no VC at all.
> -usInterNBVoltageHigh: Voltage regulator dependent PWM value. The value
> makes the the voltage >=InterNBVoltageLow but <=Max NB voltage.Set this to
> 0x if VC without PWM or no VC at all.
> +usInterNBVoltageLow:Voltage regulator dependent PWM value. The value
> makes the voltage >=Min NB voltage but <=InterNBVoltageHigh. Set this to
> 0x if VC without PWM or no VC at all.
> +usInterNBVoltageHigh: Voltage regulator dependent PWM value. The value
> makes the voltage >=InterNBVoltageLow but <=Max NB voltage.Set this to 0x
> if VC without PWM or no VC at all.
> */
>
>
> --
> 2.25.1
>
Re: [PATCH] drm/amd/display: Reduce stack size in the mode support function
On Fri, Jul 22, 2022 at 1:56 PM Rodrigo Siqueira
wrote:
>
> When we use the allmodconfig option we see the following error:
>
> drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c: In
> function 'dml32_ModeSupportAndSystemConfigurationFull':
> drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c:3799:1:
> error: the frame size of 2464 bytes is larger than 2048 bytes
> [-Werror=frame-larger-than=]
> 3799 | } // ModeSupportAndSystemConfigurationFull
>
> This commit fixes this issue by moving part of the mode support
> operation from ModeSupportAndSystemConfigurationFull to a dedicated
> function.
>
> Cc: Harry Wentland
> Cc: Alex Deucher
> Cc: Aurabindo Pillai
> Cc: Stephen Rothwell
> Signed-off-by: Rodrigo Siqueira
Thanks for sorting this out!
Acked-by: Alex Deucher
> ---
> .../dc/dml/dcn32/display_mode_vba_32.c| 132 ++
> 1 file changed, 70 insertions(+), 62 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
> b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
> index 573504de1789..465fd240b8fb 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
> @@ -1654,6 +1654,75 @@ static void
> DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
> #endif
> }
>
> +static void mode_support_configuration(struct vba_vars_st *v,
> + struct display_mode_lib *mode_lib)
> +{
> + int i, j;
> +
> + for (i = v->soc.num_states - 1; i >= 0; i--) {
> + for (j = 0; j < 2; j++) {
> + if (mode_lib->vba.ScaleRatioAndTapsSupport == true
> + &&
> mode_lib->vba.SourceFormatPixelAndScanSupport == true
> + && mode_lib->vba.ViewportSizeSupport[i][j] ==
> true
> + &&
> !mode_lib->vba.LinkRateDoesNotMatchDPVersion
> + &&
> !mode_lib->vba.LinkRateForMultistreamNotIndicated
> + &&
> !mode_lib->vba.BPPForMultistreamNotIndicated
> + && !mode_lib->vba.MultistreamWithHDMIOreDP
> + && !mode_lib->vba.ExceededMultistreamSlots[i]
> + && !mode_lib->vba.MSOOrODMSplitWithNonDPLink
> + && !mode_lib->vba.NotEnoughLanesForMSO
> + && mode_lib->vba.LinkCapacitySupport[i] ==
> true && !mode_lib->vba.P2IWith420
> + && !mode_lib->vba.DSCOnlyIfNecessaryWithBPP
> + && !mode_lib->vba.DSC422NativeNotSupported
> + && !mode_lib->vba.MPCCombineMethodIncompatible
> + &&
> mode_lib->vba.ODMCombine2To1SupportCheckOK[i] == true
> + &&
> mode_lib->vba.ODMCombine4To1SupportCheckOK[i] == true
> + && mode_lib->vba.NotEnoughDSCUnits[i] == false
> + && !mode_lib->vba.NotEnoughDSCSlices[i]
> + &&
> !mode_lib->vba.ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe
> + &&
> !mode_lib->vba.InvalidCombinationOfMALLUseForPStateAndStaticScreen
> + &&
> mode_lib->vba.DSCCLKRequiredMoreThanSupported[i] == false
> + &&
> mode_lib->vba.PixelsPerLinePerDSCUnitSupport[i]
> + &&
> mode_lib->vba.DTBCLKRequiredMoreThanSupported[i] == false
> + &&
> !mode_lib->vba.InvalidCombinationOfMALLUseForPState
> + &&
> !mode_lib->vba.ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified
> + && mode_lib->vba.ROBSupport[i][j] == true
> + && mode_lib->vba.DISPCLK_DPPCLK_Support[i][j]
> == true
> + &&
> mode_lib->vba.TotalAvailablePipesSupport[i][j] == true
> + && mode_lib->vba.NumberOfOTGSupport == true
> + && mode_lib->vba.NumberOfHDMIFRLSupport ==
> true
> + && mode_lib->vba.EnoughWritebackUnits == true
> + && mode_lib->vba.WritebackLatencySupport ==
> true
> + &&
> mode_lib->vba.WritebackScaleRatioAndTapsSupport == true
> + && mode_lib->vba.CursorSupport == true &&
> mode_lib->vba.PitchSupport == true
> + && mode_lib->vba.ViewportExceedsSurface ==
> false
> + && mode_lib->vba.PrefetchSupported[i][j] ==
> true
> + && mode_lib->vba.VActiveBandwithSupport[i][j]
> == true
> +
[PATCH] drm/amd/display: Reduce stack size in the mode support function
When we use the allmodconfig option we see the following error:
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c: In
function 'dml32_ModeSupportAndSystemConfigurationFull':
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c:3799:1:
error: the frame size of 2464 bytes is larger than 2048 bytes
[-Werror=frame-larger-than=]
3799 | } // ModeSupportAndSystemConfigurationFull
This commit fixes this issue by moving part of the mode support
operation from ModeSupportAndSystemConfigurationFull to a dedicated
function.
Cc: Harry Wentland
Cc: Alex Deucher
Cc: Aurabindo Pillai
Cc: Stephen Rothwell
Signed-off-by: Rodrigo Siqueira
---
.../dc/dml/dcn32/display_mode_vba_32.c| 132 ++
1 file changed, 70 insertions(+), 62 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
index 573504de1789..465fd240b8fb 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
@@ -1654,6 +1654,75 @@ static void
DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
#endif
}
+static void mode_support_configuration(struct vba_vars_st *v,
+ struct display_mode_lib *mode_lib)
+{
+ int i, j;
+
+ for (i = v->soc.num_states - 1; i >= 0; i--) {
+ for (j = 0; j < 2; j++) {
+ if (mode_lib->vba.ScaleRatioAndTapsSupport == true
+ &&
mode_lib->vba.SourceFormatPixelAndScanSupport == true
+ && mode_lib->vba.ViewportSizeSupport[i][j] ==
true
+ && !mode_lib->vba.LinkRateDoesNotMatchDPVersion
+ &&
!mode_lib->vba.LinkRateForMultistreamNotIndicated
+ && !mode_lib->vba.BPPForMultistreamNotIndicated
+ && !mode_lib->vba.MultistreamWithHDMIOreDP
+ && !mode_lib->vba.ExceededMultistreamSlots[i]
+ && !mode_lib->vba.MSOOrODMSplitWithNonDPLink
+ && !mode_lib->vba.NotEnoughLanesForMSO
+ && mode_lib->vba.LinkCapacitySupport[i] == true
&& !mode_lib->vba.P2IWith420
+ && !mode_lib->vba.DSCOnlyIfNecessaryWithBPP
+ && !mode_lib->vba.DSC422NativeNotSupported
+ && !mode_lib->vba.MPCCombineMethodIncompatible
+ &&
mode_lib->vba.ODMCombine2To1SupportCheckOK[i] == true
+ &&
mode_lib->vba.ODMCombine4To1SupportCheckOK[i] == true
+ && mode_lib->vba.NotEnoughDSCUnits[i] == false
+ && !mode_lib->vba.NotEnoughDSCSlices[i]
+ &&
!mode_lib->vba.ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe
+ &&
!mode_lib->vba.InvalidCombinationOfMALLUseForPStateAndStaticScreen
+ &&
mode_lib->vba.DSCCLKRequiredMoreThanSupported[i] == false
+ &&
mode_lib->vba.PixelsPerLinePerDSCUnitSupport[i]
+ &&
mode_lib->vba.DTBCLKRequiredMoreThanSupported[i] == false
+ &&
!mode_lib->vba.InvalidCombinationOfMALLUseForPState
+ &&
!mode_lib->vba.ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified
+ && mode_lib->vba.ROBSupport[i][j] == true
+ && mode_lib->vba.DISPCLK_DPPCLK_Support[i][j]
== true
+ &&
mode_lib->vba.TotalAvailablePipesSupport[i][j] == true
+ && mode_lib->vba.NumberOfOTGSupport == true
+ && mode_lib->vba.NumberOfHDMIFRLSupport == true
+ && mode_lib->vba.EnoughWritebackUnits == true
+ && mode_lib->vba.WritebackLatencySupport == true
+ &&
mode_lib->vba.WritebackScaleRatioAndTapsSupport == true
+ && mode_lib->vba.CursorSupport == true &&
mode_lib->vba.PitchSupport == true
+ && mode_lib->vba.ViewportExceedsSurface == false
+ && mode_lib->vba.PrefetchSupported[i][j] == true
+ && mode_lib->vba.VActiveBandwithSupport[i][j]
== true
+ && mode_lib->vba.DynamicMetadataSupported[i][j]
== true
+ &&
mode_lib->vba.TotalVerticalActiveBandwidthSupport[i][j] == true
+ &&
mode_lib->vba.VRatioInPrefetchSupported[i][j] == true
+ &&
Re: [PATCH 1/5] drm/amd/display: reduce stack size in dcn32 dml (v2)
On 2022-07-21 01:13, Alex Deucher wrote:
Move additional dummy structures off the stack and into
the dummy vars structure.
Fixes the following:
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c: In
function
'DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation':
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c:1659:1:
error: the frame size of 2144 bytes is larger than 2048 bytes
[-Werror=frame-larger-than=]
1659 | }
| ^
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c: In
function 'dml32_ModeSupportAndSystemConfigurationFull':
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c:3799:1:
error: the frame size of 2464 bytes is larger than 2048 bytes
[-Werror=frame-larger-than=]
3799 | } // ModeSupportAndSystemConfigurationFull
| ^
Hi Alex,
I tested this change via our CI and conducted some smoke tests, and
everything looks fine. However, this series does not entirely fix the
dml32_ModeSupportAndSystemConfigurationFull since Alex Hung, and I can
still reproduce this issue. I notice that
dml32_ModeSupportAndSystemConfigurationFull almost does not have local
variables, which means that moving the other variables to the struct
will not work anymore. I'm working on the fix for the missing issue;
I'll try to send it today.
Anyway, this series is:
Reviewed-by: Rodrigo Siqueira
Thanks
Siqueira
v2: move more stuff to dummy structure, fix init order (Alex)
Signed-off-by: Alex Deucher
Cc: Stephen Rothwell
---
.../dc/dml/dcn32/display_mode_vba_32.c| 411 --
.../drm/amd/display/dc/dml/display_mode_vba.h | 36 ++
2 files changed, 217 insertions(+), 230 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
index e9204c711cb9..9c2003fbe8fa 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
@@ -65,6 +65,12 @@ static void
DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
int iteration;
double MaxTotalRDBandwidth;
unsigned int NextPrefetchMode;
+ double MaxTotalRDBandwidthNoUrgentBurst = 0.0;
+ bool DestinationLineTimesForPrefetchLessThan2 = false;
+ bool VRatioPrefetchMoreThanMax = false;
+ double TWait;
+ double TotalWRBandwidth = 0;
+ double WRBandwidth = 0;
#ifdef __DML_VBA_DEBUG__
dml_print("DML::%s: --- START ---\n", __func__);
@@ -710,11 +716,6 @@ static void
DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
NextPrefetchMode =
mode_lib->vba.PrefetchModePerState[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb];
do {
- double MaxTotalRDBandwidthNoUrgentBurst = 0.0;
- bool DestinationLineTimesForPrefetchLessThan2 = false;
- bool VRatioPrefetchMoreThanMax = false;
- double dummy_unit_vector[DC__NUM_DPP__MAX];
-
MaxTotalRDBandwidth = 0;
#ifdef __DML_VBA_DEBUG__
dml_print("DML::%s: Start loop: VStartup = %d\n", __func__,
mode_lib->vba.VStartupLines);
@@ -723,41 +724,39 @@ static void
DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
/* NOTE PerfetchMode variable is invalid in DAL as per
the input received.
* Hence the direction is to use PrefetchModePerState.
*/
- double TWait = dml32_CalculateTWait(
-
mode_lib->vba.PrefetchModePerState[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb],
-
mode_lib->vba.UsesMALLForPStateChange[k],
-
mode_lib->vba.SynchronizeDRRDisplaysForUCLKPStateChangeFinal,
- mode_lib->vba.DRRDisplay[k],
- mode_lib->vba.DRAMClockChangeLatency,
- mode_lib->vba.FCLKChangeLatency,
v->UrgentLatency,
- mode_lib->vba.SREnterPlusExitTime);
-
- DmlPipe myPipe;
-
- myPipe.Dppclk = mode_lib->vba.DPPCLK[k];
- myPipe.Dispclk = mode_lib->vba.DISPCLK;
- myPipe.PixelClock = mode_lib->vba.PixelClock[k];
- myPipe.DCFClkDeepSleep = v->DCFCLKDeepSleep;
- myPipe.DPPPerSurface = mode_lib->vba.DPPPerPlane[k];
- myPipe.ScalerEnabled = mode_lib->vba.ScalerEnabled[k];
- myPipe.SourceRotation = mode_lib->vba.SourceRotation[k];
- myPipe.BlockWidth256BytesY = v->BlockWidth256BytesY[k];
- myPipe.BlockHeight256BytesY =
Re: [PATCH 1/3] Revert "drm/amdgpu: move internal vram_mgr function into the C file"
Hi Tvrtko,
scratching my head what exactly is going on here.
I've build tested drm-tip a couple of test in the last week and it
always worked flawlessly.
It looks like that some conflict resolution is sometimes not applied
correctly, but I have no idea why.
Regards,
Christian.
Am 22.07.22 um 16:46 schrieb Tvrtko Ursulin:
On 14/07/2022 09:45, Thomas Zimmermann wrote:
Hi
Am 08.07.22 um 11:30 schrieb Arunpravin Paneer Selvam:
This reverts commit 708d19d9f362766147cab79eccae60912c6d3068.
This commit is only present in drm-misc-next. Should the revert be
cherry-picked into drm-misc-next-fixes?
Seemed like an appropriate thread to raise this, in case my pings
about it on #dri-devel and #radeon go un-noticed since it is Friday
after all.
So for me dri-tip today fails to build the amdgpu driver.
I had to revert 925b6e59138cefa47275c67891c65d48d3266d57 to make it
build. This conflicts a bit but seems trivial. Without this revert
code seems confused with different versions of struct amdgpu_vram_mgr
and build fails violently (increase your scroll back buffers to see it
all).
Regards,
Tvrtko
Best regards
Thomas
This is part of a revert of the following commits:
commit 708d19d9f362 ("drm/amdgpu: move internal vram_mgr function
into the C file")
commit 5e3f1e7729ec ("drm/amdgpu: fix start calculation in
amdgpu_vram_mgr_new")
commit c9cad937c0c5 ("drm/amdgpu: add drm buddy support to amdgpu")
[WHY]
Few users reported garbaged graphics as soon as x starts,
reverting until this can be resolved.
Signed-off-by: Arunpravin Paneer Selvam
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 29
drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h | 27 ++
2 files changed, 27 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
index 7a5e8a7b4a1b..51d9d3a4456c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
@@ -50,35 +50,6 @@ to_amdgpu_device(struct amdgpu_vram_mgr *mgr)
return container_of(mgr, struct amdgpu_device, mman.vram_mgr);
}
-static inline struct drm_buddy_block *
-amdgpu_vram_mgr_first_block(struct list_head *list)
-{
- return list_first_entry_or_null(list, struct drm_buddy_block,
link);
-}
-
-static inline bool amdgpu_is_vram_mgr_blocks_contiguous(struct
list_head *head)
-{
- struct drm_buddy_block *block;
- u64 start, size;
-
- block = amdgpu_vram_mgr_first_block(head);
- if (!block)
- return false;
-
- while (head != block->link.next) {
- start = amdgpu_vram_mgr_block_start(block);
- size = amdgpu_vram_mgr_block_size(block);
-
- block = list_entry(block->link.next, struct
drm_buddy_block, link);
- if (start + size != amdgpu_vram_mgr_block_start(block))
- return false;
- }
-
- return true;
-}
-
-
-
/**
* DOC: mem_info_vram_total
*
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h
index 4b267bf1c5db..9a2db87186c7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h
@@ -53,6 +53,33 @@ static inline u64
amdgpu_vram_mgr_block_size(struct drm_buddy_block *block)
return PAGE_SIZE << drm_buddy_block_order(block);
}
+static inline struct drm_buddy_block *
+amdgpu_vram_mgr_first_block(struct list_head *list)
+{
+ return list_first_entry_or_null(list, struct drm_buddy_block,
link);
+}
+
+static inline bool amdgpu_is_vram_mgr_blocks_contiguous(struct
list_head *head)
+{
+ struct drm_buddy_block *block;
+ u64 start, size;
+
+ block = amdgpu_vram_mgr_first_block(head);
+ if (!block)
+ return false;
+
+ while (head != block->link.next) {
+ start = amdgpu_vram_mgr_block_start(block);
+ size = amdgpu_vram_mgr_block_size(block);
+
+ block = list_entry(block->link.next, struct
drm_buddy_block, link);
+ if (start + size != amdgpu_vram_mgr_block_start(block))
+ return false;
+ }
+
+ return true;
+}
+
static inline struct amdgpu_vram_mgr_resource *
to_amdgpu_vram_mgr_resource(struct ttm_resource *res)
{
Re: [PATCH 1/3] Revert "drm/amdgpu: move internal vram_mgr function into the C file"
On 14/07/2022 09:45, Thomas Zimmermann wrote:
Hi
Am 08.07.22 um 11:30 schrieb Arunpravin Paneer Selvam:
This reverts commit 708d19d9f362766147cab79eccae60912c6d3068.
This commit is only present in drm-misc-next. Should the revert be
cherry-picked into drm-misc-next-fixes?
Seemed like an appropriate thread to raise this, in case my pings about
it on #dri-devel and #radeon go un-noticed since it is Friday after all.
So for me dri-tip today fails to build the amdgpu driver.
I had to revert 925b6e59138cefa47275c67891c65d48d3266d57 to make it
build. This conflicts a bit but seems trivial. Without this revert code
seems confused with different versions of struct amdgpu_vram_mgr and
build fails violently (increase your scroll back buffers to see it all).
Regards,
Tvrtko
Best regards
Thomas
This is part of a revert of the following commits:
commit 708d19d9f362 ("drm/amdgpu: move internal vram_mgr function into
the C file")
commit 5e3f1e7729ec ("drm/amdgpu: fix start calculation in
amdgpu_vram_mgr_new")
commit c9cad937c0c5 ("drm/amdgpu: add drm buddy support to amdgpu")
[WHY]
Few users reported garbaged graphics as soon as x starts,
reverting until this can be resolved.
Signed-off-by: Arunpravin Paneer Selvam
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 29
drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h | 27 ++
2 files changed, 27 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
index 7a5e8a7b4a1b..51d9d3a4456c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
@@ -50,35 +50,6 @@ to_amdgpu_device(struct amdgpu_vram_mgr *mgr)
return container_of(mgr, struct amdgpu_device, mman.vram_mgr);
}
-static inline struct drm_buddy_block *
-amdgpu_vram_mgr_first_block(struct list_head *list)
-{
- return list_first_entry_or_null(list, struct drm_buddy_block, link);
-}
-
-static inline bool amdgpu_is_vram_mgr_blocks_contiguous(struct
list_head *head)
-{
- struct drm_buddy_block *block;
- u64 start, size;
-
- block = amdgpu_vram_mgr_first_block(head);
- if (!block)
- return false;
-
- while (head != block->link.next) {
- start = amdgpu_vram_mgr_block_start(block);
- size = amdgpu_vram_mgr_block_size(block);
-
- block = list_entry(block->link.next, struct drm_buddy_block,
link);
- if (start + size != amdgpu_vram_mgr_block_start(block))
- return false;
- }
-
- return true;
-}
-
-
-
/**
* DOC: mem_info_vram_total
*
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h
index 4b267bf1c5db..9a2db87186c7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h
@@ -53,6 +53,33 @@ static inline u64 amdgpu_vram_mgr_block_size(struct
drm_buddy_block *block)
return PAGE_SIZE << drm_buddy_block_order(block);
}
+static inline struct drm_buddy_block *
+amdgpu_vram_mgr_first_block(struct list_head *list)
+{
+ return list_first_entry_or_null(list, struct drm_buddy_block, link);
+}
+
+static inline bool amdgpu_is_vram_mgr_blocks_contiguous(struct
list_head *head)
+{
+ struct drm_buddy_block *block;
+ u64 start, size;
+
+ block = amdgpu_vram_mgr_first_block(head);
+ if (!block)
+ return false;
+
+ while (head != block->link.next) {
+ start = amdgpu_vram_mgr_block_start(block);
+ size = amdgpu_vram_mgr_block_size(block);
+
+ block = list_entry(block->link.next, struct drm_buddy_block,
link);
+ if (start + size != amdgpu_vram_mgr_block_start(block))
+ return false;
+ }
+
+ return true;
+}
+
static inline struct amdgpu_vram_mgr_resource *
to_amdgpu_vram_mgr_resource(struct ttm_resource *res)
{
Re: [PATCH] drm/amdgpu: enable swiotlb for gmc 10.0
[Public] Reviewed-by: Alex Deucher Looks like gmc11 is missing this too. Care to send a patch for that as well? Alex From: Liu, Aaron Sent: Thursday, July 21, 2022 10:22 PM To: amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander ; Huang, Ray ; Liu, Aaron Subject: [PATCH] drm/amdgpu: enable swiotlb for gmc 10.0 Enable swiotlb for gmc 10.0. Signed-off-by: Aaron Liu --- drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c index 6470290aaf7d..a1a98c7fe8e1 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c @@ -967,6 +967,8 @@ static int gmc_v10_0_sw_init(void *handle) return r; } + adev->need_swiotlb = drm_need_swiotlb(44); + r = gmc_v10_0_mc_init(adev); if (r) return r; -- 2.37.0
Re: [PATCH] amdgpu: re-enable DCN for ppc64le
On Fri, 22 Jul 2022 22:32:06 +1000 Michael Ellerman wrote: > Hi Dan, > > [ Cc += linuxppc-dev ] > > Dan Horák writes: > > Commit d11219ad53dc disabled the DCN driver for all platforms that > > define PPC64 due long build issues during "make allmodconfig" using > > cross-compilation. Cross-compilation defaults to the ppc64_defconfig > > and thus big-endian toolchain configuration. The ppc64le platform uses a > > different ABI and doesn't suffer from the build issues. > > Unfortunately it's a bit messier than that. yes, seems it is :-) > The build error occurs when the compiler is built to use a 64-bit long > double type. > > The ppc64le ABI document says that long double should be 128-bits, but > there are ppc64le compilers out there that are configured to use 64-bit > long double, notably the kernel.org crosstool compilers. > > So just testing for CPU_LITTLE_ENDIAN means we'll still get build errors > on those compilers. > > But I think we can detect the long double size and key off that. Can you > test the patch below works for you? yes, it does work, meaning it defines AMD_DC_DCN on Fedora/ppc64le (and build is OK) Dan > > cheers > > > diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig > index 7aa12e88c580..e9f8cd50af99 100644 > --- a/arch/powerpc/Kconfig > +++ b/arch/powerpc/Kconfig > @@ -281,6 +281,9 @@ config PPC > # Please keep this list sorted alphabetically. > # > > +config PCC_LONG_DOUBLE_128 > + def_bool $(success,test "$(shell,echo __LONG_DOUBLE_128__ | $(CC) -E -P > -)" = 1) > + > config PPC_BARRIER_NOSPEC > bool > default y > diff --git a/drivers/gpu/drm/amd/display/Kconfig > b/drivers/gpu/drm/amd/display/Kconfig > index b4029c0d5d8c..ec6771e87e73 100644 > --- a/drivers/gpu/drm/amd/display/Kconfig > +++ b/drivers/gpu/drm/amd/display/Kconfig > @@ -6,7 +6,7 @@ config DRM_AMD_DC > bool "AMD DC - Enable new display engine" > default y > select SND_HDA_COMPONENT if SND_HDA_CORE > - select DRM_AMD_DC_DCN if (X86 || PPC64) && !(KCOV_INSTRUMENT_ALL && > KCOV_ENABLE_COMPARISONS) > + select DRM_AMD_DC_DCN if (X86 || PPC_LONG_DOUBLE_128) && > !(KCOV_INSTRUMENT_ALL && KCOV_ENABLE_COMPARISONS) > help > Choose this option if you want to use the new display engine > support for AMDGPU. This adds required support for Vega and
Re: [PATCH 6/6] drm/amdgpu: sriov remove vcn_4_0 and jpeg_4_0
On Thu, Jul 21, 2022 at 5:52 AM Horace Chen wrote:
>
> SRIOV needs to initialize mmsch instead of multimedia engines
> directly. So currently remove them for SR-IOV until the code and
> firmwares are ready.
>
> Signed-off-by: Horace Chen
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 6 --
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> index f559fda2811f..3f7e1d683df3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> @@ -1900,8 +1900,10 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct
> amdgpu_device *adev)
> case IP_VERSION(4, 0, 0):
> case IP_VERSION(4, 0, 2):
> case IP_VERSION(4, 0, 4):
> - amdgpu_device_ip_block_add(adev, _v4_0_ip_block);
> - amdgpu_device_ip_block_add(adev, _v4_0_ip_block);
> + if (!amdgpu_sriov_vf(adev)) {
> + amdgpu_device_ip_block_add(adev,
> _v4_0_ip_block);
> + amdgpu_device_ip_block_add(adev,
> _v4_0_ip_block);
> + }
> break;
> default:
> dev_err(adev->dev,
> --
> 2.25.1
>
Re: [PATCH 5/6] drm/amdgpu: refine virtualization psp fw skip check
On Thu, Jul 21, 2022 at 5:52 AM Horace Chen wrote:
>
> SR-IOV may need to load different firmwares for different ASIC inside
> VF.
> So create a new function in amdgpu_virt to check whether FW load needs
> to be skipped.
>
> Signed-off-by: Horace Chen
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 17 +++---
> drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 29
> drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 2 ++
> 3 files changed, 34 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> index 6540582ecbf8..a601d0f67b1f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> @@ -334,11 +334,12 @@ static int psp_init_sriov_microcode(struct psp_context
> *psp)
> ret = psp_init_cap_microcode(psp, "aldebaran");
> ret &= psp_init_ta_microcode(psp, "aldebaran");
> break;
> + case IP_VERSION(13, 0, 0):
> + break;
> default:
> BUG();
> break;
> }
> -
> return ret;
> }
>
> @@ -2389,19 +2390,7 @@ static bool fw_load_skip_check(struct psp_context *psp,
> return true;
>
> if (amdgpu_sriov_vf(psp->adev) &&
> - (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0
> - || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1
> - || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2
> - || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3
> - || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4
> - || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5
> - || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6
> - || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7
> - || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G
> - || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL
> - || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM
> - || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM
> - || ucode->ucode_id == AMDGPU_UCODE_ID_SMC))
> + amdgpu_virt_fw_load_skip_check(psp->adev, ucode->ucode_id))
> /*skip ucode loading in SRIOV VF */
> return true;
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> index ab55602ff534..ba367799d087 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> @@ -807,6 +807,35 @@ enum amdgpu_sriov_vf_mode
> amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *ad
> return mode;
> }
>
> +bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev, uint32_t
> ucode_id)
> +{
> + /* this version doesn't support sriov autoload */
> + if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 0)) {
> + if (ucode_id == AMDGPU_UCODE_ID_VCN1 ||
> + ucode_id == AMDGPU_UCODE_ID_VCN)
> + return false;
> + else
> + return true;
> + }
> +
> + if (ucode_id == AMDGPU_UCODE_ID_SDMA0
> + || ucode_id == AMDGPU_UCODE_ID_SDMA1
> + || ucode_id == AMDGPU_UCODE_ID_SDMA2
> + || ucode_id == AMDGPU_UCODE_ID_SDMA3
> + || ucode_id == AMDGPU_UCODE_ID_SDMA4
> + || ucode_id == AMDGPU_UCODE_ID_SDMA5
> + || ucode_id == AMDGPU_UCODE_ID_SDMA6
> + || ucode_id == AMDGPU_UCODE_ID_SDMA7
> + || ucode_id == AMDGPU_UCODE_ID_RLC_G
> + || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL
> + || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM
> + || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM
> + || ucode_id == AMDGPU_UCODE_ID_SMC)
> + return true;
> +
> + return false;
> +}
> +
> void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev,
> struct amdgpu_video_codec_info *encode, uint32_t
> encode_array_size,
> struct amdgpu_video_codec_info *decode, uint32_t
> decode_array_size)
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
> index 239f232f9c02..cd6fce05978f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
> @@ -343,4 +343,6 @@ void amdgpu_sriov_wreg(struct amdgpu_device *adev,
>u32 acc_flags, u32 hwip);
> u32 amdgpu_sriov_rreg(struct amdgpu_device *adev,
> u32 offset, u32 acc_flags, u32 hwip);
> +bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev,
> + uint32_t ucode_id);
> #endif
> --
> 2.25.1
>
Re: [PATCH 2/6] drm/amdgpu: add sriov nbio callback structure
On Thu, Jul 21, 2022 at 5:52 AM Horace Chen wrote:
>
> [Why]
> under SR-IOV, the nbio doorbell range will be defined by PF. So VF
> nbio doorbell range registers will be blocked. It will cause violation
> if VF access those registers directly.
>
> [How]
> create an nbio_v4_3_sriov_funcs for sriov nbio_v4_3 initialization to
> skip the setting for the doorbell range registers.
>
> Signed-off-by: Horace Chen
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 5 ++-
> drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c| 44 +++
> drivers/gpu/drm/amd/amdgpu/nbio_v4_3.h| 1 +
> 3 files changed, 49 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> index 242d1847c4aa..f559fda2811f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> @@ -2232,7 +2232,10 @@ int amdgpu_discovery_set_ip_blocks(struct
> amdgpu_device *adev)
> break;
> case IP_VERSION(4, 3, 0):
> case IP_VERSION(4, 3, 1):
> - adev->nbio.funcs = _v4_3_funcs;
> + if (amdgpu_sriov_vf(adev))
> + adev->nbio.funcs = _v4_3_sriov_funcs;
> + else
> + adev->nbio.funcs = _v4_3_funcs;
> adev->nbio.hdp_flush_reg = _v4_3_hdp_flush_reg;
> break;
> case IP_VERSION(7, 7, 0):
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c
> b/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c
> index 982a89f841d5..15eb3658d70e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c
> @@ -488,3 +488,47 @@ const struct amdgpu_nbio_funcs nbio_v4_3_funcs = {
> .get_rom_offset = nbio_v4_3_get_rom_offset,
> .program_aspm = nbio_v4_3_program_aspm,
> };
> +
> +
> +static void nbio_v4_3_sriov_ih_doorbell_range(struct amdgpu_device *adev,
> + bool use_doorbell, int doorbell_index)
> +{
> +}
> +
> +static void nbio_v4_3_sriov_sdma_doorbell_range(struct amdgpu_device *adev,
> int instance,
> + bool use_doorbell, int
> doorbell_index,
> + int doorbell_size)
> +{
> +}
> +
> +static void nbio_v4_3_sriov_vcn_doorbell_range(struct amdgpu_device *adev,
> bool use_doorbell,
> +int doorbell_index, int instance)
> +{
> +}
> +
> +static void nbio_v4_3_sriov_gc_doorbell_init(struct amdgpu_device *adev)
> +{
> +}
> +
> +const struct amdgpu_nbio_funcs nbio_v4_3_sriov_funcs = {
> + .get_hdp_flush_req_offset = nbio_v4_3_get_hdp_flush_req_offset,
> + .get_hdp_flush_done_offset = nbio_v4_3_get_hdp_flush_done_offset,
> + .get_pcie_index_offset = nbio_v4_3_get_pcie_index_offset,
> + .get_pcie_data_offset = nbio_v4_3_get_pcie_data_offset,
> + .get_rev_id = nbio_v4_3_get_rev_id,
> + .mc_access_enable = nbio_v4_3_mc_access_enable,
> + .get_memsize = nbio_v4_3_get_memsize,
> + .sdma_doorbell_range = nbio_v4_3_sriov_sdma_doorbell_range,
> + .vcn_doorbell_range = nbio_v4_3_sriov_vcn_doorbell_range,
> + .gc_doorbell_init = nbio_v4_3_sriov_gc_doorbell_init,
> + .enable_doorbell_aperture = nbio_v4_3_enable_doorbell_aperture,
> + .enable_doorbell_selfring_aperture =
> nbio_v4_3_enable_doorbell_selfring_aperture,
> + .ih_doorbell_range = nbio_v4_3_sriov_ih_doorbell_range,
> + .update_medium_grain_clock_gating =
> nbio_v4_3_update_medium_grain_clock_gating,
> + .update_medium_grain_light_sleep =
> nbio_v4_3_update_medium_grain_light_sleep,
> + .get_clockgating_state = nbio_v4_3_get_clockgating_state,
> + .ih_control = nbio_v4_3_ih_control,
> + .init_registers = nbio_v4_3_init_registers,
> + .remap_hdp_registers = nbio_v4_3_remap_hdp_registers,
> + .get_rom_offset = nbio_v4_3_get_rom_offset,
> +};
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.h
> b/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.h
> index ade43661d7a9..711999ceedf4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.h
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.h
> @@ -28,5 +28,6 @@
>
> extern const struct nbio_hdp_flush_reg nbio_v4_3_hdp_flush_reg;
> extern const struct amdgpu_nbio_funcs nbio_v4_3_funcs;
> +extern const struct amdgpu_nbio_funcs nbio_v4_3_sriov_funcs;
>
> #endif
> --
> 2.25.1
>
Re: [PATCH 1/6] drm/amdgpu: add CHIP_IP_DISCOVERY support for virtualization
On Thu, Jul 21, 2022 at 11:32 PM Chen, Horace wrote:
>
> [AMD Official Use Only - General]
>
> Hi Alex,
>
> By current design, we will keep this register same for all new asics.
> Also, the amdgpu_detect_virtualization will be called before we read the IP
> discovery table (virtualization needs to send a message to host machine to
> request for the IP discovery table preparation). So we can't use any IP
> version to decide the register.
Reviewed-by: Alex Deucher
>
> Regards,
> Horace.
>
> -Original Message-
> From: Alex Deucher
> Sent: Thursday, July 21, 2022 10:37 PM
> To: Chen, Horace
> Cc: amd-gfx@lists.freedesktop.org; Grodzovsky, Andrey
> ; Xiao, Jack ; Xu, Feifei
> ; Wang, Yang(Kevin) ; Xiaojie Yuan
> ; Tuikov, Luben ; Deucher,
> Alexander ; Quan, Evan ;
> Koenig, Christian ; Liu, Monk ;
> Zhang, Hawking
> Subject: Re: [PATCH 1/6] drm/amdgpu: add CHIP_IP_DISCOVERY support for
> virtualization
>
> On Thu, Jul 21, 2022 at 5:52 AM Horace Chen wrote:
> >
> > For further chips we will use CHIP_IP_DISCOVERY, so add this support
> > for virtualization
>
> All current and future chips will use CHIP_IP_DISCOVERY. If we plan to keep
> the register the same for all new aics, this should be fine.
> If we might need to have it per asic I think you might want something more
> like this:
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> index 9be57389301b..0bdd71f9a8fb 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> @@ -709,6 +709,16 @@ void amdgpu_detect_virtualization(struct
> amdgpu_device *adev)
> case CHIP_ALDEBARAN:
> reg = RREG32(mmRCC_IOV_FUNC_IDENTIFIER);
> break;
> + case CHIP_IP_DISCOVERY:
> + switch (adev->ip_versions[GC_HWIP][0]) {
> + case IP_VERSION(11, 0, 0):
> + reg = RREG32(mmRCC_IOV_FUNC_IDENTIFIER);
> + break;
> + default:
> + reg = 0;
> + break;
> + }
> + break;
> default: /* other chip doesn't support SRIOV */
> reg = 0;
> break;
>
> Alex
>
> >
> > Signed-off-by: Horace Chen
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 2 ++
> > 1 file changed, 2 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> > index 7d7044e9de2f..ab55602ff534 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> > @@ -705,6 +705,7 @@ void amdgpu_detect_virtualization(struct amdgpu_device
> > *adev)
> > case CHIP_SIENNA_CICHLID:
> > case CHIP_ARCTURUS:
> > case CHIP_ALDEBARAN:
> > + case CHIP_IP_DISCOVERY:
> > reg = RREG32(mmRCC_IOV_FUNC_IDENTIFIER);
> > break;
> > default: /* other chip doesn't support SRIOV */ @@ -748,6
> > +749,7 @@ void amdgpu_detect_virtualization(struct amdgpu_device *adev)
> > case CHIP_NAVI10:
> > case CHIP_NAVI12:
> > case CHIP_SIENNA_CICHLID:
> > + case CHIP_IP_DISCOVERY:
> > nv_set_virt_ops(adev);
> > /* try send GPU_INIT_DATA request to host */
> > amdgpu_virt_request_init_data(adev);
> > --
> > 2.25.1
> >
Re: [PATCH 4/6] drm/amdgpu: enable WPTR_POLL_ENABLE for sriov on sdma_v6_0
On Thu, Jul 21, 2022 at 5:52 AM Horace Chen wrote: > > [Why] > Under SR-IOV, if VF is switched out then its doorbell will be disabled, > SDMA rely on WPTR_POLL to get doorbells which was sent during VF > switched-out time. > > [How] > For SR-IOV, set SDMA WPTR_POLL_ENABLE to 1. > > Signed-off-by: Horace Chen Reviewed-by: Alex Deucher > --- > drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 5 - > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c > b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c > index 0200cb3a31a4..23b01b121492 100644 > --- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c > @@ -593,7 +593,10 @@ static int sdma_v6_0_gfx_resume(struct amdgpu_device > *adev) >lower_32_bits(ring->rptr_gpu_addr) & 0xFFFC); > > rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, > RPTR_WRITEBACK_ENABLE, 1); > - rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, > WPTR_POLL_ENABLE, 0); > + if (amdgpu_sriov_vf(adev)) > + rb_cntl = REG_SET_FIELD(rb_cntl, > SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 1); > + else > + rb_cntl = REG_SET_FIELD(rb_cntl, > SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 0); > rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, > F32_WPTR_POLL_ENABLE, 1); > > WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, > regSDMA0_QUEUE0_RB_BASE), ring->gpu_addr >> 8); > -- > 2.25.1 >
Re: [PATCH 3/6] drm/amdgpu: add a compute pipe reset for SR-IOV
On Thu, Jul 21, 2022 at 5:52 AM Horace Chen wrote:
>
> [Why]
> Under SR-IOV, we are not sure whether pipe status is
> good or not when doing initialization. The compute engine
> maybe fail to bringup if pipe status is bad.
Seems like this should be safe for bare metal too. Can we just do
this for both to simplify the code?
Alex
>
> [How]
> For SR-IOV, disable the compute engine to do a pipe reset
> before we do initialization.
>
> Signed-off-by: Horace Chen
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 6 +-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> index 0d8193b30fc5..b8f197a5ee84 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> @@ -4586,8 +4586,12 @@ static int gfx_v11_0_hw_init(void *handle)
> DRM_WARN("Invalid gb_addr_config !\n");
>
> if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
> - adev->gfx.rs64_enable)
> + adev->gfx.rs64_enable) {
> + if (amdgpu_sriov_vf(adev))
> + gfx_v11_0_cp_compute_enable(adev, false);
> +
> gfx_v11_0_config_gfx_rs64(adev);
> + }
>
> r = gfx_v11_0_gfxhub_enable(adev);
> if (r)
> --
> 2.25.1
>
Re: [PATCH] amdgpu: re-enable DCN for ppc64le
On Fri, 22 Jul 2022 22:32:06 +1000 Michael Ellerman wrote: > Hi Dan, > > [ Cc += linuxppc-dev ] > > Dan Horák writes: > > Commit d11219ad53dc disabled the DCN driver for all platforms that > > define PPC64 due long build issues during "make allmodconfig" using > > cross-compilation. Cross-compilation defaults to the ppc64_defconfig > > and thus big-endian toolchain configuration. The ppc64le platform uses a > > different ABI and doesn't suffer from the build issues. > > Unfortunately it's a bit messier than that. > > The build error occurs when the compiler is built to use a 64-bit long > double type. > > The ppc64le ABI document says that long double should be 128-bits, but > there are ppc64le compilers out there that are configured to use 64-bit > long double, notably the kernel.org crosstool compilers. > > So just testing for CPU_LITTLE_ENDIAN means we'll still get build errors > on those compilers. > > But I think we can detect the long double size and key off that. Can you > test the patch below works for you? > > cheers > > > diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig > index 7aa12e88c580..e9f8cd50af99 100644 > --- a/arch/powerpc/Kconfig > +++ b/arch/powerpc/Kconfig > @@ -281,6 +281,9 @@ config PPC > # Please keep this list sorted alphabetically. > # > > +config PCC_LONG_DOUBLE_128 > + def_bool $(success,test "$(shell,echo __LONG_DOUBLE_128__ | $(CC) -E -P > -)" = 1) ^^^ there is a typo s/PCC/PPC/ :-) with that fixed, it then defines AMD_DC_DCN on Fedora 36 with gcc-12.1.1-1.fc36.ppc64le and we should be OK. Dan > + > config PPC_BARRIER_NOSPEC > bool > default y > diff --git a/drivers/gpu/drm/amd/display/Kconfig > b/drivers/gpu/drm/amd/display/Kconfig > index b4029c0d5d8c..ec6771e87e73 100644 > --- a/drivers/gpu/drm/amd/display/Kconfig > +++ b/drivers/gpu/drm/amd/display/Kconfig > @@ -6,7 +6,7 @@ config DRM_AMD_DC > bool "AMD DC - Enable new display engine" > default y > select SND_HDA_COMPONENT if SND_HDA_CORE > - select DRM_AMD_DC_DCN if (X86 || PPC64) && !(KCOV_INSTRUMENT_ALL && > KCOV_ENABLE_COMPARISONS) > + select DRM_AMD_DC_DCN if (X86 || PPC_LONG_DOUBLE_128) && > !(KCOV_INSTRUMENT_ALL && KCOV_ENABLE_COMPARISONS) > help > Choose this option if you want to use the new display engine > support for AMDGPU. This adds required support for Vega and
[PATCH] amdgpu: re-enable DCN for ppc64le
Commit d11219ad53dc disabled the DCN driver for all platforms that
define PPC64 due long build issues during "make allmodconfig" using
cross-compilation. Cross-compilation defaults to the ppc64_defconfig
and thus big-endian toolchain configuration. The ppc64le platform uses a
different ABI and doesn't suffer from the build issues. Thus keep the
DCN driver disabled only for big-endian ppc64 builds and avoid
regression for ppc64le users of the amdgpu driver. Distros are mostly
focusing on ppc64le and that's likely why it got unnoticed, because
there were no build issues related to the amdgpu driver on ppc64le in
the 5.19 development cycle.
Tested by a local rebuild on ppc64le and using make.cross from a x86_64
machines.
Fixes: d11219ad53dc ("amdgpu: disable powerpc support for the newer display
engine")
Signed-off-by: Dan Horák
Acked-by: Alex Deucher
Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2100
---
drivers/gpu/drm/amd/display/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/Kconfig
b/drivers/gpu/drm/amd/display/Kconfig
index 0ba0598eba20..778a6f58047c 100644
--- a/drivers/gpu/drm/amd/display/Kconfig
+++ b/drivers/gpu/drm/amd/display/Kconfig
@@ -6,7 +6,7 @@ config DRM_AMD_DC
bool "AMD DC - Enable new display engine"
default y
select SND_HDA_COMPONENT if SND_HDA_CORE
- select DRM_AMD_DC_DCN if X86 && !(KCOV_INSTRUMENT_ALL &&
KCOV_ENABLE_COMPARISONS)
+ select DRM_AMD_DC_DCN if (X86 || (PPC64 && CPU_LITTLE_ENDIAN)) &&
!(KCOV_INSTRUMENT_ALL && KCOV_ENABLE_COMPARISONS)
help
Choose this option if you want to use the new display engine
support for AMDGPU. This adds required support for Vega and
--
2.37.1
Re: [PATCH] drm/amd/display: reduce stack size in dcn32 dml (v2)
Am 20.07.22 um 18:05 schrieb Alex Deucher:
Move additional dummy structures off the stack and into
the dummy vars structure.
Fixes the following:
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c: In
function
'DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation':
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c:1659:1:
error: the frame size of 2144 bytes is larger than 2048 bytes
[-Werror=frame-larger-than=]
1659 | }
| ^
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c: In
function 'dml32_ModeSupportAndSystemConfigurationFull':
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c:3799:1:
error: the frame size of 2464 bytes is larger than 2048 bytes
[-Werror=frame-larger-than=]
3799 | } // ModeSupportAndSystemConfigurationFull
| ^
v2: more more stuff to dummy structure, fix init order (Alex)
Signed-off-by: Alex Deucher
Cc: Stephen Rothwell
Acked-by: Christian König
---
.../dc/dml/dcn32/display_mode_vba_32.c| 406 --
.../drm/amd/display/dc/dml/display_mode_vba.h | 35 ++
2 files changed, 214 insertions(+), 227 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
index 349e36ae9333..91450a973920 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
@@ -67,6 +67,12 @@ static void
DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
int iteration;
double MaxTotalRDBandwidth;
unsigned int NextPrefetchMode;
+ double MaxTotalRDBandwidthNoUrgentBurst = 0.0;
+ bool DestinationLineTimesForPrefetchLessThan2 = false;
+ bool VRatioPrefetchMoreThanMax = false;
+ double TWait;
+ double TotalWRBandwidth = 0;
+ double WRBandwidth = 0;
#ifdef __DML_VBA_DEBUG__
dml_print("DML::%s: --- START ---\n", __func__);
@@ -702,11 +708,6 @@ static void
DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
NextPrefetchMode =
mode_lib->vba.PrefetchModePerState[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb];
do {
- double MaxTotalRDBandwidthNoUrgentBurst = 0.0;
- bool DestinationLineTimesForPrefetchLessThan2 = false;
- bool VRatioPrefetchMoreThanMax = false;
- double dummy_unit_vector[DC__NUM_DPP__MAX];
-
MaxTotalRDBandwidth = 0;
#ifdef __DML_VBA_DEBUG__
dml_print("DML::%s: Start loop: VStartup = %d\n", __func__,
mode_lib->vba.VStartupLines);
@@ -715,41 +716,39 @@ static void
DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
/* NOTE PerfetchMode variable is invalid in DAL as per
the input received.
* Hence the direction is to use PrefetchModePerState.
*/
- double TWait = dml32_CalculateTWait(
-
mode_lib->vba.PrefetchModePerState[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb],
-
mode_lib->vba.UsesMALLForPStateChange[k],
-
mode_lib->vba.SynchronizeDRRDisplaysForUCLKPStateChangeFinal,
- mode_lib->vba.DRRDisplay[k],
- mode_lib->vba.DRAMClockChangeLatency,
- mode_lib->vba.FCLKChangeLatency,
v->UrgentLatency,
- mode_lib->vba.SREnterPlusExitTime);
-
- DmlPipe myPipe;
-
- myPipe.Dppclk = mode_lib->vba.DPPCLK[k];
- myPipe.Dispclk = mode_lib->vba.DISPCLK;
- myPipe.PixelClock = mode_lib->vba.PixelClock[k];
- myPipe.DCFClkDeepSleep = v->DCFCLKDeepSleep;
- myPipe.DPPPerSurface = mode_lib->vba.DPPPerPlane[k];
- myPipe.ScalerEnabled = mode_lib->vba.ScalerEnabled[k];
- myPipe.SourceRotation = mode_lib->vba.SourceRotation[k];
- myPipe.BlockWidth256BytesY = v->BlockWidth256BytesY[k];
- myPipe.BlockHeight256BytesY =
v->BlockHeight256BytesY[k];
- myPipe.BlockWidth256BytesC = v->BlockWidth256BytesC[k];
- myPipe.BlockHeight256BytesC =
v->BlockHeight256BytesC[k];
- myPipe.InterlaceEnable = mode_lib->vba.Interlace[k];
- myPipe.NumberOfCursors =
mode_lib->vba.NumberOfCursors[k];
- myPipe.VBlank = mode_lib->vba.VTotal[k] -
mode_lib->vba.VActive[k];
- myPipe.HTotal = mode_lib->vba.HTotal[k];
- myPipe.HActive =
Re: [PATCH 2/5] drm/amdgpu: add debugfs amdgpu_reset_level
Well NAK to the debugfs approach, stuff like that is usually a module
parameter.
Apart from that this series needs to be reviewed by Andrey.
Regards,
Christian.
Am 22.07.22 um 09:34 schrieb Victor Zhao:
Introduce amdgpu_reset_level debugfs in order to help debug and
test specific type of reset. Also helps blocking unwanted type of
resets.
By default, mode2 reset will not be enabled
Signed-off-by: Victor Zhao
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4
drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 20
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c | 6 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c| 3 +++
5 files changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 6cd1e0a6dffc..c661231a6a07 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -238,6 +238,7 @@ extern int amdgpu_si_support;
extern int amdgpu_cik_support;
#endif
extern int amdgpu_num_kcq;
+extern uint amdgpu_reset_level_mask;
#define AMDGPU_VCNFW_LOG_SIZE (32 * 1024)
extern int amdgpu_vcnfw_log;
@@ -274,6 +275,9 @@ extern int amdgpu_vcnfw_log;
#define AMDGPU_RESET_VCE (1 << 13)
#define AMDGPU_RESET_VCE1 (1 << 14)
+#define AMDGPU_RESET_LEVEL_SOFT_RECOVERY (1 << 0)
+#define AMDGPU_RESET_LEVEL_MODE2 (1 << 1)
+
/* max cursor sizes (in pixels) */
#define CIK_CURSOR_WIDTH 128
#define CIK_CURSOR_HEIGHT 128
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index e2eec985adb3..235c48e4ba4d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -1661,12 +1661,29 @@ static int amdgpu_debugfs_sclk_set(void *data, u64 val)
return ret;
}
+static int amdgpu_debugfs_reset_level_get(void *data, u64 *val)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)data;
+ *val = amdgpu_reset_level_mask;
+ return 0;
+}
+
+static int amdgpu_debugfs_reset_level_set(void *data, u64 val)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)data;
+ amdgpu_reset_level_mask = val;
+ return 0;
+}
+
DEFINE_DEBUGFS_ATTRIBUTE(fops_ib_preempt, NULL,
amdgpu_debugfs_ib_preempt, "%llu\n");
DEFINE_DEBUGFS_ATTRIBUTE(fops_sclk_set, NULL,
amdgpu_debugfs_sclk_set, "%llu\n");
+DEFINE_DEBUGFS_ATTRIBUTE(fops_reset_level, amdgpu_debugfs_reset_level_get,
+ amdgpu_debugfs_reset_level_set, "%llu\n");
+
static ssize_t amdgpu_reset_dump_register_list_read(struct file *f,
char __user *buf, size_t size, loff_t *pos)
{
@@ -1785,6 +1802,9 @@ int amdgpu_debugfs_init(struct amdgpu_device *adev)
return PTR_ERR(ent);
}
+ debugfs_create_file("amdgpu_reset_level", 0200, root, adev,
+ _reset_level);
+
/* Register debugfs entries for amdgpu_ttm */
amdgpu_ttm_debugfs_init(adev);
amdgpu_debugfs_pm_init(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index e8c6c3fe9374..fb8f3cb853a7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -198,6 +198,7 @@ struct amdgpu_watchdog_timer amdgpu_watchdog_timer = {
.timeout_fatal_disable = false,
.period = 0x0, /* default to 0x0 (timeout disable) */
};
+uint amdgpu_reset_level_mask = 0x1;
/**
* DOC: vramlimit (int)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
index 831fb222139c..f16ab1a54b70 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
@@ -74,6 +74,9 @@ int amdgpu_reset_prepare_hwcontext(struct amdgpu_device *adev,
{
struct amdgpu_reset_handler *reset_handler = NULL;
+ if (!(amdgpu_reset_level_mask & AMDGPU_RESET_LEVEL_MODE2))
+ return -ENOSYS;
+
if (test_bit(AMDGPU_SKIP_MODE2_RESET, _context->flags))
return -ENOSYS;
@@ -93,6 +96,9 @@ int amdgpu_reset_perform_reset(struct amdgpu_device *adev,
int ret;
struct amdgpu_reset_handler *reset_handler = NULL;
+ if (!(amdgpu_reset_level_mask & AMDGPU_RESET_LEVEL_MODE2))
+ return -ENOSYS;
+
if (test_bit(AMDGPU_SKIP_MODE2_RESET, _context->flags))
return -ENOSYS;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
index d3558c34d406..1ffdc050a077 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
@@ -405,6 +405,9 @@ bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring,
unsigned int vmid,
{
ktime_t deadline =
[PATCH 5/5] drm/amdgpu: reduce reset time
In multi container use case, reset time is important, so skip ring
tests and cp halt wait during ip suspending for reset as they are
going to fail and cost more time on reset
Signed-off-by: Victor Zhao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 2 +-
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 26 +++--
2 files changed, 17 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index 222d3d7ea076..f872495ccc3a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -477,7 +477,7 @@ int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev)
kiq->pmf->kiq_unmap_queues(kiq_ring, >gfx.compute_ring[i],
RESET_QUEUES, 0, 0);
- if (adev->gfx.kiq.ring.sched.ready)
+ if (adev->gfx.kiq.ring.sched.ready && !amdgpu_in_reset(adev))
r = amdgpu_ring_test_helper(kiq_ring);
spin_unlock(>gfx.kiq.ring_lock);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index fafbad3cf08d..9ae29023e38f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -5971,16 +5971,19 @@ static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device
*adev, bool enable)
WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
}
- for (i = 0; i < adev->usec_timeout; i++) {
- if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
- break;
- udelay(1);
- }
-
- if (i >= adev->usec_timeout)
- DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
+ if (!amdgpu_in_reset(adev)) {
+ for (i = 0; i < adev->usec_timeout; i++) {
+ if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
+ break;
+ udelay(1);
+ }
+ if (i >= adev->usec_timeout)
+ DRM_ERROR("failed to %s cp gfx\n",
+ enable ? "unhalt" : "halt");
+ }
return 0;
+
}
static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
@@ -7569,8 +7572,10 @@ static int gfx_v10_0_kiq_disable_kgq(struct
amdgpu_device *adev)
for (i = 0; i < adev->gfx.num_gfx_rings; i++)
kiq->pmf->kiq_unmap_queues(kiq_ring, >gfx.gfx_ring[i],
PREEMPT_QUEUES, 0, 0);
-
- return amdgpu_ring_test_helper(kiq_ring);
+ if (!amdgpu_in_reset(adev))
+ return amdgpu_ring_test_helper(kiq_ring);
+ else
+ return 0;
}
#endif
@@ -7610,6 +7615,7 @@ static int gfx_v10_0_hw_fini(void *handle)
return 0;
}
+
gfx_v10_0_cp_enable(adev, false);
gfx_v10_0_enable_gui_idle_interrupt(adev, false);
--
2.25.1
[PATCH 4/5] drm/amdgpu: revert context to stop engine before mode2 reset
For some hang caused by slow tests, engine cannot be stopped which
may cause resume failure after reset. In this case, force halt
engine by reverting context addresses
Signed-off-by: Victor Zhao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_gfxhub.h | 1 +
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c| 36 +
drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c | 2 ++
4 files changed, 40 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 5498fda8617f..833dc5e224d3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -5037,6 +5037,7 @@ static void amdgpu_device_recheck_guilty_jobs(
/* set guilty */
drm_sched_increase_karma(s_job);
+ amdgpu_reset_prepare_hwcontext(adev, reset_context);
retry:
/* do hw reset */
if (amdgpu_sriov_vf(adev)) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfxhub.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfxhub.h
index f8036f2b100e..c7b44aeb671b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfxhub.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfxhub.h
@@ -37,6 +37,7 @@ struct amdgpu_gfxhub_funcs {
void (*utcl2_harvest)(struct amdgpu_device *adev);
void (*mode2_save_regs)(struct amdgpu_device *adev);
void (*mode2_restore_regs)(struct amdgpu_device *adev);
+ void (*halt)(struct amdgpu_device *adev);
};
struct amdgpu_gfxhub {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
index 51cf8acd2d79..8cf53e039c11 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
@@ -646,6 +646,41 @@ static void gfxhub_v2_1_restore_regs(struct amdgpu_device
*adev)
WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL,
adev->gmc.MC_VM_MX_L1_TLB_CNTL);
}
+static void gfxhub_v2_1_halt(struct amdgpu_device *adev)
+{
+ struct amdgpu_vmhub *hub = >vmhub[AMDGPU_GFXHUB_0];
+ int i;
+ uint32_t tmp;
+ int time = 1000;
+
+ gfxhub_v2_1_set_fault_enable_default(adev, false);
+
+ for (i = 0; i <= 14; i++) {
+ WREG32_SOC15_OFFSET(GC, 0,
mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
+ i * hub->ctx_addr_distance, ~0);
+ WREG32_SOC15_OFFSET(GC, 0,
mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
+ i * hub->ctx_addr_distance, ~0);
+ WREG32_SOC15_OFFSET(GC, 0,
mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
+ i * hub->ctx_addr_distance,
+ 0);
+ WREG32_SOC15_OFFSET(GC, 0,
mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
+ i * hub->ctx_addr_distance,
+ 0);
+ }
+ tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
+ while ((tmp & (GRBM_STATUS2__EA_BUSY_MASK |
+ GRBM_STATUS2__EA_LINK_BUSY_MASK)) != 0 &&
+ time) {
+ udelay(100);
+ time--;
+ tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
+ }
+
+ if (!time) {
+ DRM_WARN("failed to wait for GRBM(EA) idle\n");
+ }
+}
+
const struct amdgpu_gfxhub_funcs gfxhub_v2_1_funcs = {
.get_fb_location = gfxhub_v2_1_get_fb_location,
.get_mc_fb_offset = gfxhub_v2_1_get_mc_fb_offset,
@@ -658,4 +693,5 @@ const struct amdgpu_gfxhub_funcs gfxhub_v2_1_funcs = {
.utcl2_harvest = gfxhub_v2_1_utcl2_harvest,
.mode2_save_regs = gfxhub_v2_1_save_regs,
.mode2_restore_regs = gfxhub_v2_1_restore_regs,
+ .halt = gfxhub_v2_1_halt,
};
diff --git a/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c
b/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c
index 51a5b68f77d3..fead7251292f 100644
--- a/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c
+++ b/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c
@@ -97,6 +97,8 @@ sienna_cichlid_mode2_prepare_hwcontext(struct
amdgpu_reset_control *reset_ctl,
if (!amdgpu_sriov_vf(adev)) {
if (adev->gfxhub.funcs->mode2_save_regs)
adev->gfxhub.funcs->mode2_save_regs(adev);
+ if (adev->gfxhub.funcs->halt)
+ adev->gfxhub.funcs->halt(adev);
r = sienna_cichlid_mode2_suspend_ip(adev);
}
--
2.25.1
[PATCH 2/5] drm/amdgpu: add debugfs amdgpu_reset_level
Introduce amdgpu_reset_level debugfs in order to help debug and
test specific type of reset. Also helps blocking unwanted type of
resets.
By default, mode2 reset will not be enabled
Signed-off-by: Victor Zhao
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4
drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 20
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c | 6 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c| 3 +++
5 files changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 6cd1e0a6dffc..c661231a6a07 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -238,6 +238,7 @@ extern int amdgpu_si_support;
extern int amdgpu_cik_support;
#endif
extern int amdgpu_num_kcq;
+extern uint amdgpu_reset_level_mask;
#define AMDGPU_VCNFW_LOG_SIZE (32 * 1024)
extern int amdgpu_vcnfw_log;
@@ -274,6 +275,9 @@ extern int amdgpu_vcnfw_log;
#define AMDGPU_RESET_VCE (1 << 13)
#define AMDGPU_RESET_VCE1 (1 << 14)
+#define AMDGPU_RESET_LEVEL_SOFT_RECOVERY (1 << 0)
+#define AMDGPU_RESET_LEVEL_MODE2 (1 << 1)
+
/* max cursor sizes (in pixels) */
#define CIK_CURSOR_WIDTH 128
#define CIK_CURSOR_HEIGHT 128
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index e2eec985adb3..235c48e4ba4d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -1661,12 +1661,29 @@ static int amdgpu_debugfs_sclk_set(void *data, u64 val)
return ret;
}
+static int amdgpu_debugfs_reset_level_get(void *data, u64 *val)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)data;
+ *val = amdgpu_reset_level_mask;
+ return 0;
+}
+
+static int amdgpu_debugfs_reset_level_set(void *data, u64 val)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)data;
+ amdgpu_reset_level_mask = val;
+ return 0;
+}
+
DEFINE_DEBUGFS_ATTRIBUTE(fops_ib_preempt, NULL,
amdgpu_debugfs_ib_preempt, "%llu\n");
DEFINE_DEBUGFS_ATTRIBUTE(fops_sclk_set, NULL,
amdgpu_debugfs_sclk_set, "%llu\n");
+DEFINE_DEBUGFS_ATTRIBUTE(fops_reset_level, amdgpu_debugfs_reset_level_get,
+ amdgpu_debugfs_reset_level_set, "%llu\n");
+
static ssize_t amdgpu_reset_dump_register_list_read(struct file *f,
char __user *buf, size_t size, loff_t *pos)
{
@@ -1785,6 +1802,9 @@ int amdgpu_debugfs_init(struct amdgpu_device *adev)
return PTR_ERR(ent);
}
+ debugfs_create_file("amdgpu_reset_level", 0200, root, adev,
+ _reset_level);
+
/* Register debugfs entries for amdgpu_ttm */
amdgpu_ttm_debugfs_init(adev);
amdgpu_debugfs_pm_init(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index e8c6c3fe9374..fb8f3cb853a7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -198,6 +198,7 @@ struct amdgpu_watchdog_timer amdgpu_watchdog_timer = {
.timeout_fatal_disable = false,
.period = 0x0, /* default to 0x0 (timeout disable) */
};
+uint amdgpu_reset_level_mask = 0x1;
/**
* DOC: vramlimit (int)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
index 831fb222139c..f16ab1a54b70 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
@@ -74,6 +74,9 @@ int amdgpu_reset_prepare_hwcontext(struct amdgpu_device *adev,
{
struct amdgpu_reset_handler *reset_handler = NULL;
+ if (!(amdgpu_reset_level_mask & AMDGPU_RESET_LEVEL_MODE2))
+ return -ENOSYS;
+
if (test_bit(AMDGPU_SKIP_MODE2_RESET, _context->flags))
return -ENOSYS;
@@ -93,6 +96,9 @@ int amdgpu_reset_perform_reset(struct amdgpu_device *adev,
int ret;
struct amdgpu_reset_handler *reset_handler = NULL;
+ if (!(amdgpu_reset_level_mask & AMDGPU_RESET_LEVEL_MODE2))
+ return -ENOSYS;
+
if (test_bit(AMDGPU_SKIP_MODE2_RESET, _context->flags))
return -ENOSYS;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
index d3558c34d406..1ffdc050a077 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
@@ -405,6 +405,9 @@ bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring,
unsigned int vmid,
{
ktime_t deadline = ktime_add_us(ktime_get(), 1);
+ if (!(amdgpu_reset_level_mask & AMDGPU_RESET_LEVEL_SOFT_RECOVERY))
+ return false;
+
if (amdgpu_sriov_vf(ring->adev) || !ring->funcs->soft_recovery ||
!fence)
return
[PATCH 3/5] drm/amdgpu: save and restore gc hub regs
Save and restore gfxhub regs as they will be reset during mode 2
Signed-off-by: Victor Zhao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfxhub.h| 2 +
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 26 +++
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c | 72 +++
drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c | 7 +-
.../include/asic_reg/gc/gc_10_3_0_offset.h| 4 ++
5 files changed, 110 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfxhub.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfxhub.h
index beabab515836..f8036f2b100e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfxhub.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfxhub.h
@@ -35,6 +35,8 @@ struct amdgpu_gfxhub_funcs {
void (*init)(struct amdgpu_device *adev);
int (*get_xgmi_info)(struct amdgpu_device *adev);
void (*utcl2_harvest)(struct amdgpu_device *adev);
+ void (*mode2_save_regs)(struct amdgpu_device *adev);
+ void (*mode2_restore_regs)(struct amdgpu_device *adev);
};
struct amdgpu_gfxhub {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
index 008eaca27151..0305b660cd17 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
@@ -264,6 +264,32 @@ struct amdgpu_gmc {
u64 mall_size;
/* number of UMC instances */
int num_umc;
+ /* mode2 save restore */
+ u64 VM_L2_CNTL;
+ u64 VM_L2_CNTL2;
+ u64 VM_DUMMY_PAGE_FAULT_CNTL;
+ u64 VM_DUMMY_PAGE_FAULT_ADDR_LO32;
+ u64 VM_DUMMY_PAGE_FAULT_ADDR_HI32;
+ u64 VM_L2_PROTECTION_FAULT_CNTL;
+ u64 VM_L2_PROTECTION_FAULT_CNTL2;
+ u64 VM_L2_PROTECTION_FAULT_MM_CNTL3;
+ u64 VM_L2_PROTECTION_FAULT_MM_CNTL4;
+ u64 VM_L2_PROTECTION_FAULT_ADDR_LO32;
+ u64 VM_L2_PROTECTION_FAULT_ADDR_HI32;
+ u64 VM_DEBUG;
+ u64 VM_L2_MM_GROUP_RT_CLASSES;
+ u64 VM_L2_BANK_SELECT_RESERVED_CID;
+ u64 VM_L2_BANK_SELECT_RESERVED_CID2;
+ u64 VM_L2_CACHE_PARITY_CNTL;
+ u64 VM_L2_IH_LOG_CNTL;
+ u64 VM_CONTEXT_CNTL[16];
+ u64 VM_CONTEXT_PAGE_TABLE_BASE_ADDR_LO32[16];
+ u64 VM_CONTEXT_PAGE_TABLE_BASE_ADDR_HI32[16];
+ u64 VM_CONTEXT_PAGE_TABLE_START_ADDR_LO32[16];
+ u64 VM_CONTEXT_PAGE_TABLE_START_ADDR_HI32[16];
+ u64 VM_CONTEXT_PAGE_TABLE_END_ADDR_LO32[16];
+ u64 VM_CONTEXT_PAGE_TABLE_END_ADDR_HI32[16];
+ u64 MC_VM_MX_L1_TLB_CNTL;
};
#define amdgpu_gmc_flush_gpu_tlb(adev, vmid, vmhub, type)
((adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid), (vmhub), (type)))
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
index d8c531581116..51cf8acd2d79 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
@@ -576,6 +576,76 @@ static void gfxhub_v2_1_utcl2_harvest(struct amdgpu_device
*adev)
}
}
+static void gfxhub_v2_1_save_regs(struct amdgpu_device *adev)
+{
+ int i;
+ adev->gmc.VM_L2_CNTL = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL);
+ adev->gmc.VM_L2_CNTL2 = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2);
+ adev->gmc.VM_DUMMY_PAGE_FAULT_CNTL = RREG32_SOC15(GC, 0,
mmGCVM_DUMMY_PAGE_FAULT_CNTL);
+ adev->gmc.VM_DUMMY_PAGE_FAULT_ADDR_LO32 = RREG32_SOC15(GC, 0,
mmGCVM_DUMMY_PAGE_FAULT_ADDR_LO32);
+ adev->gmc.VM_DUMMY_PAGE_FAULT_ADDR_HI32 = RREG32_SOC15(GC, 0,
mmGCVM_DUMMY_PAGE_FAULT_ADDR_HI32);
+ adev->gmc.VM_L2_PROTECTION_FAULT_CNTL = RREG32_SOC15(GC, 0,
mmGCVM_L2_PROTECTION_FAULT_CNTL);
+ adev->gmc.VM_L2_PROTECTION_FAULT_CNTL2 = RREG32_SOC15(GC, 0,
mmGCVM_L2_PROTECTION_FAULT_CNTL2);
+ adev->gmc.VM_L2_PROTECTION_FAULT_MM_CNTL3 = RREG32_SOC15(GC, 0,
mmGCVM_L2_PROTECTION_FAULT_MM_CNTL3);
+ adev->gmc.VM_L2_PROTECTION_FAULT_MM_CNTL4 = RREG32_SOC15(GC, 0,
mmGCVM_L2_PROTECTION_FAULT_MM_CNTL4);
+ adev->gmc.VM_L2_PROTECTION_FAULT_ADDR_LO32 = RREG32_SOC15(GC, 0,
mmGCVM_L2_PROTECTION_FAULT_ADDR_LO32);
+ adev->gmc.VM_L2_PROTECTION_FAULT_ADDR_HI32 = RREG32_SOC15(GC, 0,
mmGCVM_L2_PROTECTION_FAULT_ADDR_HI32);
+ adev->gmc.VM_DEBUG = RREG32_SOC15(GC, 0, mmGCVM_DEBUG);
+ adev->gmc.VM_L2_MM_GROUP_RT_CLASSES = RREG32_SOC15(GC, 0,
mmGCVM_L2_MM_GROUP_RT_CLASSES);
+ adev->gmc.VM_L2_BANK_SELECT_RESERVED_CID = RREG32_SOC15(GC, 0,
mmGCVM_L2_BANK_SELECT_RESERVED_CID);
+ adev->gmc.VM_L2_BANK_SELECT_RESERVED_CID2 = RREG32_SOC15(GC, 0,
mmGCVM_L2_BANK_SELECT_RESERVED_CID2);
+ adev->gmc.VM_L2_CACHE_PARITY_CNTL = RREG32_SOC15(GC, 0,
mmGCVM_L2_CACHE_PARITY_CNTL);
+ adev->gmc.VM_L2_IH_LOG_CNTL = RREG32_SOC15(GC, 0,
mmGCVM_L2_IH_LOG_CNTL);
+
+ for (i = 0; i <= 15; i++) {
+ adev->gmc.VM_CONTEXT_CNTL[i] = RREG32_SOC15_OFFSET(GC, 0,
mmGCVM_CONTEXT0_CNTL, i);
+ adev->gmc.VM_CONTEXT_PAGE_TABLE_BASE_ADDR_LO32[i] =
RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, i * 2);
+
[PATCH 1/5] drm/amdgpu: add mode2 reset for sienna_cichlid
To meet the requirement for multi container usecase which needs
a quicker reset and not causing VRAM lost, adding the Mode2
reset handler for sienna_cichlid. Adding a AMDGPU_SKIP_MODE2_RESET
flag so driver can fallback to default reset method when mode2
reset failed and retry.
- add mode2 reset handler for sienna_cichlid
- introduce AMDGPU_SKIP_MODE2_RESET flag
- let mode2 reset fallback to default reset method if failed
Signed-off-by: Victor Zhao
---
drivers/gpu/drm/amd/amdgpu/Makefile | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c| 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 7 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c | 13 +
drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h | 1 +
drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c | 1 +
drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c | 1 +
drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c | 1 +
drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c | 297 ++
drivers/gpu/drm/amd/amdgpu/sienna_cichlid.h | 32 ++
.../pm/swsmu/inc/pmfw_if/smu_v11_0_7_ppsmc.h | 4 +-
drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h | 3 +-
.../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 54
15 files changed, 414 insertions(+), 5 deletions(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/sienna_cichlid.h
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
b/drivers/gpu/drm/amd/amdgpu/Makefile
index c7d0cd15b5ef..7030ac2d7d2c 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -75,7 +75,7 @@ amdgpu-y += \
vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o
vega10_reg_init.o \
vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o arct_reg_init.o
mxgpu_nv.o \
nbio_v7_2.o hdp_v4_0.o hdp_v5_0.o aldebaran_reg_init.o aldebaran.o
soc21.o \
- nbio_v4_3.o hdp_v6_0.o nbio_v7_7.o hdp_v5_2.o lsdma_v6_0.o
+ sienna_cichlid.o nbio_v4_3.o hdp_v6_0.o nbio_v7_7.o hdp_v5_2.o
lsdma_v6_0.o
# add DF block
amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index 5e53a5293935..091415a4abf0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -135,6 +135,7 @@ static void amdgpu_amdkfd_reset_work(struct work_struct
*work)
reset_context.method = AMD_RESET_METHOD_NONE;
reset_context.reset_req_dev = adev;
clear_bit(AMDGPU_NEED_FULL_RESET, _context.flags);
+ clear_bit(AMDGPU_SKIP_MODE2_RESET, _context.flags);
amdgpu_device_gpu_recover(adev, NULL, _context);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index b79ee4ffb879..5498fda8617f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -5146,6 +5146,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
reset_context->job = job;
reset_context->hive = hive;
+
/*
* Build list of devices to reset.
* In case we are in XGMI hive mode, resort the device list
@@ -5265,8 +5266,11 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
amdgpu_ras_resume(adev);
} else {
r = amdgpu_do_asic_reset(device_list_handle, reset_context);
- if (r && r == -EAGAIN)
+ if (r && r == -EAGAIN) {
+ set_bit(AMDGPU_SKIP_MODE2_RESET, _context->flags);
+ adev->asic_reset_res = 0;
goto retry;
+ }
}
skip_hw_reset:
@@ -5694,6 +5698,7 @@ pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev
*pdev)
reset_context.reset_req_dev = adev;
set_bit(AMDGPU_NEED_FULL_RESET, _context.flags);
set_bit(AMDGPU_SKIP_HW_RESET, _context.flags);
+ set_bit(AMDGPU_SKIP_MODE2_RESET, _context.flags);
adev->no_hw_access = true;
r = amdgpu_device_pre_asic_reset(adev, _context);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
index 10fdd12cf853..9844d99075e9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
@@ -71,6 +71,7 @@ static enum drm_gpu_sched_stat amdgpu_job_timedout(struct
drm_sched_job *s_job)
reset_context.method = AMD_RESET_METHOD_NONE;
reset_context.reset_req_dev = adev;
clear_bit(AMDGPU_NEED_FULL_RESET, _context.flags);
+ clear_bit(AMDGPU_SKIP_MODE2_RESET, _context.flags);
r = amdgpu_device_gpu_recover(ring->adev, job, _context);
if (r)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index
