Re: Stack-frame warnings in display_mode_vba_32.c

2022-07-29 Thread Paul E. McKenney 
On Fri, Jul 29, 2022 at 11:41:55PM -0300, André Almeida wrote:
> Hi Paul,
> 
> Às 23:25 de 29/07/22, Paul E. McKenney escreveu:
> > Hello!
> > 
> > I am seeing the following in allmodconfig builds of recent -next on x86:
> > 
> > drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c: 
> > In function 
> > ‘DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation’:
> > drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c:1659:1:
> >  error: the frame size of 2144 bytes is larger than 2048 bytes 
> > [-Werror=frame-larger-than=]
> >  1659 | }
> >   | ^
> > drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c: 
> > In function ‘dml32_ModeSupportAndSystemConfigurationFull’:
> > drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c:3799:1:
> >  error: the frame size of 2480 bytes is larger than 2048 bytes 
> > [-Werror=frame-larger-than=]
> >  3799 | } // ModeSupportAndSystemConfigurationFull
> >   | ^
> 
> I think they are fixed at amd-staging-drm-next:
> 
> git log --oneline amd/amd-staging-drm-next
> drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
> 953daa61981b drm/amd/display: Reduce stack size in the mode support function
> 361e705e712d drm/amd/display: reduce stack for
> dml32_CalculatePrefetchSchedule
> f2dbf5a4dd1e drm/amd/display: reduce stack for
> dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport
> a0a68cda2ef8 drm/amd/display: reduce stack for dml32_CalculateVMRowAndSwath
> ca6730ca0f01 drm/amd/display: reduce stack for
> dml32_CalculateSwathAndDETConfiguration
> 593eef8c1a5e drm/amd/display: reduce stack size in dcn32 dml (v2)
> 
> https://gitlab.freedesktop.org/agd5f/linux/-/commits/amd-staging-drm-next/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

Very good, thank you!  I will test again on the next -next.

Thanx, Paul

> > Bisection located the commit shown below.  Doing an allmodconfig build
> > on this commit reproduces the error, its parent builds fine.
> > 
> > Thoughts?
> > 
> > Thanx, Paul
> > 
> > 
> > 
> > commit 3876a8b5e241081b2a519f848a65c00d8e6cd124
> > Author: Guenter Roeck 
> > Date:   Tue Jul 12 15:42:47 2022 -0700
> > 
> > drm/amd/display: Enable building new display engine with KCOV enabled
> > 
> > The new display engine uses floating point math, which is not supported
> > by KCOV. Commit 9d1d02ff3678 ("drm/amd/display: Don't build DCN1 when 
> > kcov
> > is enabled") tried to work around the problem by disabling
> > CONFIG_DRM_AMD_DC_DCN if KCOV_INSTRUMENT_ALL and KCOV_ENABLE_COMPARISONS
> > are enabled. The result is that KCOV can not be enabled on systems which
> > require this display engine. A much simpler and less invasive solution 
> > is
> > to disable KCOV selectively when compiling the display enagine while
> > keeping it enabled for the rest of the kernel.
> > 
> > Fixes: 9d1d02ff3678 ("drm/amd/display: Don't build DCN1 when kcov is 
> > enabled")
> > Cc: Arnd Bergmann 
> > Cc: Leo Li 
> > Reviewed-by: Harry Wentland 
> > Signed-off-by: Guenter Roeck 
> > Signed-off-by: Alex Deucher 
> > 
> > diff --git a/drivers/gpu/drm/amd/display/Kconfig 
> > b/drivers/gpu/drm/amd/display/Kconfig
> > index b4029c0d5d8c5..96cbc87f7b6b8 100644
> > --- a/drivers/gpu/drm/amd/display/Kconfig
> > +++ b/drivers/gpu/drm/amd/display/Kconfig
> > @@ -6,7 +6,7 @@ config DRM_AMD_DC
> > bool "AMD DC - Enable new display engine"
> > default y
> > select SND_HDA_COMPONENT if SND_HDA_CORE
> > -   select DRM_AMD_DC_DCN if (X86 || PPC64) && !(KCOV_INSTRUMENT_ALL && 
> > KCOV_ENABLE_COMPARISONS)
> > +   select DRM_AMD_DC_DCN if (X86 || PPC64)
> > help
> >   Choose this option if you want to use the new display engine
> >   support for AMDGPU. This adds required support for Vega and
> > diff --git a/drivers/gpu/drm/amd/display/dc/Makefile 
> > b/drivers/gpu/drm/amd/display/dc/Makefile
> > index 273f8f2c8e020..b9effadfc4bb7 100644
> > --- a/drivers/gpu/drm/amd/display/dc/Makefile
> > +++ b/drivers/gpu/drm/amd/display/dc/Makefile
> > @@ -25,6 +25,9 @@
> >  DC_LIBS = basics bios dml clk_mgr dce gpio irq link virtual
> >  
> >  ifdef CONFIG_DRM_AMD_DC_DCN
> > +
> > +KCOV_INSTRUMENT := n
> > +
> >  DC_LIBS += dcn20
> >  DC_LIBS += dsc
> >  DC_LIBS += dcn10

Re: Stack-frame warnings in display_mode_vba_32.c

2022-07-29 Thread André Almeida 
Hi Paul,

Às 23:25 de 29/07/22, Paul E. McKenney escreveu:
> Hello!
> 
> I am seeing the following in allmodconfig builds of recent -next on x86:
> 
> drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c: In 
> function 
> ‘DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation’:
> drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c:1659:1:
>  error: the frame size of 2144 bytes is larger than 2048 bytes 
> [-Werror=frame-larger-than=]
>  1659 | }
>   | ^
> drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c: In 
> function ‘dml32_ModeSupportAndSystemConfigurationFull’:
> drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c:3799:1:
>  error: the frame size of 2480 bytes is larger than 2048 bytes 
> [-Werror=frame-larger-than=]
>  3799 | } // ModeSupportAndSystemConfigurationFull
>   | ^

I think they are fixed at amd-staging-drm-next:

git log --oneline amd/amd-staging-drm-next
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
953daa61981b drm/amd/display: Reduce stack size in the mode support function
361e705e712d drm/amd/display: reduce stack for
dml32_CalculatePrefetchSchedule
f2dbf5a4dd1e drm/amd/display: reduce stack for
dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport
a0a68cda2ef8 drm/amd/display: reduce stack for dml32_CalculateVMRowAndSwath
ca6730ca0f01 drm/amd/display: reduce stack for
dml32_CalculateSwathAndDETConfiguration
593eef8c1a5e drm/amd/display: reduce stack size in dcn32 dml (v2)

https://gitlab.freedesktop.org/agd5f/linux/-/commits/amd-staging-drm-next/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

> 
> Bisection located the commit shown below.  Doing an allmodconfig build
> on this commit reproduces the error, its parent builds fine.
> 
> Thoughts?
> 
>   Thanx, Paul
> 
> 
> 
> commit 3876a8b5e241081b2a519f848a65c00d8e6cd124
> Author: Guenter Roeck 
> Date:   Tue Jul 12 15:42:47 2022 -0700
> 
> drm/amd/display: Enable building new display engine with KCOV enabled
> 
> The new display engine uses floating point math, which is not supported
> by KCOV. Commit 9d1d02ff3678 ("drm/amd/display: Don't build DCN1 when kcov
> is enabled") tried to work around the problem by disabling
> CONFIG_DRM_AMD_DC_DCN if KCOV_INSTRUMENT_ALL and KCOV_ENABLE_COMPARISONS
> are enabled. The result is that KCOV can not be enabled on systems which
> require this display engine. A much simpler and less invasive solution is
> to disable KCOV selectively when compiling the display enagine while
> keeping it enabled for the rest of the kernel.
> 
> Fixes: 9d1d02ff3678 ("drm/amd/display: Don't build DCN1 when kcov is 
> enabled")
> Cc: Arnd Bergmann 
> Cc: Leo Li 
> Reviewed-by: Harry Wentland 
> Signed-off-by: Guenter Roeck 
> Signed-off-by: Alex Deucher 
> 
> diff --git a/drivers/gpu/drm/amd/display/Kconfig 
> b/drivers/gpu/drm/amd/display/Kconfig
> index b4029c0d5d8c5..96cbc87f7b6b8 100644
> --- a/drivers/gpu/drm/amd/display/Kconfig
> +++ b/drivers/gpu/drm/amd/display/Kconfig
> @@ -6,7 +6,7 @@ config DRM_AMD_DC
>   bool "AMD DC - Enable new display engine"
>   default y
>   select SND_HDA_COMPONENT if SND_HDA_CORE
> - select DRM_AMD_DC_DCN if (X86 || PPC64) && !(KCOV_INSTRUMENT_ALL && 
> KCOV_ENABLE_COMPARISONS)
> + select DRM_AMD_DC_DCN if (X86 || PPC64)
>   help
> Choose this option if you want to use the new display engine
> support for AMDGPU. This adds required support for Vega and
> diff --git a/drivers/gpu/drm/amd/display/dc/Makefile 
> b/drivers/gpu/drm/amd/display/dc/Makefile
> index 273f8f2c8e020..b9effadfc4bb7 100644
> --- a/drivers/gpu/drm/amd/display/dc/Makefile
> +++ b/drivers/gpu/drm/amd/display/dc/Makefile
> @@ -25,6 +25,9 @@
>  DC_LIBS = basics bios dml clk_mgr dce gpio irq link virtual
>  
>  ifdef CONFIG_DRM_AMD_DC_DCN
> +
> +KCOV_INSTRUMENT := n
> +
>  DC_LIBS += dcn20
>  DC_LIBS += dsc
>  DC_LIBS += dcn10

Stack-frame warnings in display_mode_vba_32.c

2022-07-29 Thread Paul E. McKenney 
Hello!

I am seeing the following in allmodconfig builds of recent -next on x86:

drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c: In 
function 
‘DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation’:
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c:1659:1:
 error: the frame size of 2144 bytes is larger than 2048 bytes 
[-Werror=frame-larger-than=]
 1659 | }
  | ^
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c: In 
function ‘dml32_ModeSupportAndSystemConfigurationFull’:
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c:3799:1:
 error: the frame size of 2480 bytes is larger than 2048 bytes 
[-Werror=frame-larger-than=]
 3799 | } // ModeSupportAndSystemConfigurationFull
  | ^

Bisection located the commit shown below.  Doing an allmodconfig build
on this commit reproduces the error, its parent builds fine.

Thoughts?

Thanx, Paul



commit 3876a8b5e241081b2a519f848a65c00d8e6cd124
Author: Guenter Roeck 
Date:   Tue Jul 12 15:42:47 2022 -0700

drm/amd/display: Enable building new display engine with KCOV enabled

The new display engine uses floating point math, which is not supported
by KCOV. Commit 9d1d02ff3678 ("drm/amd/display: Don't build DCN1 when kcov
is enabled") tried to work around the problem by disabling
CONFIG_DRM_AMD_DC_DCN if KCOV_INSTRUMENT_ALL and KCOV_ENABLE_COMPARISONS
are enabled. The result is that KCOV can not be enabled on systems which
require this display engine. A much simpler and less invasive solution is
to disable KCOV selectively when compiling the display enagine while
keeping it enabled for the rest of the kernel.

Fixes: 9d1d02ff3678 ("drm/amd/display: Don't build DCN1 when kcov is 
enabled")
Cc: Arnd Bergmann 
Cc: Leo Li 
Reviewed-by: Harry Wentland 
Signed-off-by: Guenter Roeck 
Signed-off-by: Alex Deucher 

diff --git a/drivers/gpu/drm/amd/display/Kconfig 
b/drivers/gpu/drm/amd/display/Kconfig
index b4029c0d5d8c5..96cbc87f7b6b8 100644
--- a/drivers/gpu/drm/amd/display/Kconfig
+++ b/drivers/gpu/drm/amd/display/Kconfig
@@ -6,7 +6,7 @@ config DRM_AMD_DC
bool "AMD DC - Enable new display engine"
default y
select SND_HDA_COMPONENT if SND_HDA_CORE
-   select DRM_AMD_DC_DCN if (X86 || PPC64) && !(KCOV_INSTRUMENT_ALL && 
KCOV_ENABLE_COMPARISONS)
+   select DRM_AMD_DC_DCN if (X86 || PPC64)
help
  Choose this option if you want to use the new display engine
  support for AMDGPU. This adds required support for Vega and
diff --git a/drivers/gpu/drm/amd/display/dc/Makefile 
b/drivers/gpu/drm/amd/display/dc/Makefile
index 273f8f2c8e020..b9effadfc4bb7 100644
--- a/drivers/gpu/drm/amd/display/dc/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/Makefile
@@ -25,6 +25,9 @@
 DC_LIBS = basics bios dml clk_mgr dce gpio irq link virtual
 
 ifdef CONFIG_DRM_AMD_DC_DCN
+
+KCOV_INSTRUMENT := n
+
 DC_LIBS += dcn20
 DC_LIBS += dsc
 DC_LIBS += dcn10

[PATCH v2 3/3] drm/amd/display: include missing headers

2022-07-29 Thread Magali Lemes 
Add missing headers to solve the following warnings from sparse:

drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/dcn20_fpu.c:656:17: warning: 
symbol 'ddr4_wm_table_gs' was not declared. Should it be static?
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/dcn20_fpu.c:693:17: warning: 
symbol 'lpddr4_wm_table_gs' was not declared. Should it be static?
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/dcn20_fpu.c:730:17: warning: 
symbol 'lpddr4_wm_table_with_disabled_ppt' was not declared. Should it be 
static?
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/dcn20_fpu.c:767:17: warning: 
symbol 'ddr4_wm_table_rn' was not declared. Should it be static?
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/dcn20_fpu.c:804:17: warning: 
symbol 'ddr4_1R_wm_table_rn' was not declared. Should it be static?
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/dcn20_fpu.c:841:17: warning: 
symbol 'lpddr4_wm_table_rn' was not declared. Should it be static?
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn301/dcn301_fpu.c:217:17: 
warning: symbol 'ddr4_wm_table' was not declared. Should it be static?
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn301/dcn301_fpu.c:254:17: 
warning: symbol 'lpddr5_wm_table' was not declared. Should it be static?
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn31/dcn31_fpu.c:53:30: warning: 
symbol 'dcn3_1_ip' was not declared. Should it be static?
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn31/dcn31_fpu.c:197:30: warning: 
symbol 'dcn3_15_ip' was not declared. Should it be static?
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn31/dcn31_fpu.c:293:30: warning: 
symbol 'dcn3_16_ip' was not declared. Should it be static?

Fixes: 490d2bc889f1 ("drm/amd/display: move FPU code on dcn21 clk_mgr")
Fixes: 83916f9a32a4 ("drm/amd/display: move FPU code from dcn301 clk mgr to DML 
folder")
Fixes: 26f4712aedbd ("drm/amd/display: move FPU related code from dcn31 to 
dml/dcn31 folder")
Fixes: fa896297b31b ("drm/amd/display: move FPU related code from dcn315 to 
dml/dcn31 folder")
Fixes: 3f8951cc123f ("drm/amd/display: move FPU related code from dcn316 to 
dml/dcn31 folder")
Signed-off-by: Magali Lemes 
Reviewed-by: Maíra Canal 
Reviewed-by: Melissa Wen 
---
Changes in v2:
  - split commit (Melissa)
  - update the commit message accordingly
  - add Fixes and Reviewed-by tags.

 drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c   | 1 +
 drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c | 1 +
 drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c   | 3 +++
 3 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
index ca44df4fca74..d34e0f1314d9 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
@@ -30,6 +30,7 @@
 #include "dchubbub.h"
 #include "dcn20/dcn20_resource.h"
 #include "dcn21/dcn21_resource.h"
+#include "clk_mgr/dcn21/rn_clk_mgr.h"
 
 #include "dcn20_fpu.h"
 
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c
index 7ef66e511ec8..d211cf6d234c 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c
@@ -26,6 +26,7 @@
 #include "clk_mgr.h"
 #include "dcn20/dcn20_resource.h"
 #include "dcn301/dcn301_resource.h"
+#include "clk_mgr/dcn301/vg_clk_mgr.h"
 
 #include "dml/dcn20/dcn20_fpu.h"
 #include "dcn301_fpu.h"
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
index 5664653ba5ac..149a1b17cdf3 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
@@ -25,6 +25,9 @@
 
 #include "resource.h"
 #include "clk_mgr.h"
+#include "dcn31/dcn31_resource.h"
+#include "dcn315/dcn315_resource.h"
+#include "dcn316/dcn316_resource.h"
 
 #include "dml/dcn20/dcn20_fpu.h"
 #include "dcn31_fpu.h"
-- 
2.37.1

[PATCH v2 2/3] drm/amd/display: remove header from source file

2022-07-29 Thread Magali Lemes 
Since "rn_clk_mgr.h" needs ‘struct clk_mgr_internal’ which is declared
in "clk_mgr_internal.h", include "clk_mgr_internal.h" in "rn_clk_mgr.h"
instead of in its source file.
Because of the change above, change the order of '#include
"rn_clk_mgr.h"', so that the necessary structs are visible to
dcn20_clk_mgr.h.

Signed-off-by: Magali Lemes 
Reviewed-by: Maíra Canal 
Reviewed-by: Melissa Wen 
---
Changes in v2:
  - split commit (Melissa).

 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 3 +--
 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h | 1 +
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
index 0202dc682682..ca6dfd2d7561 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
@@ -24,10 +24,9 @@
  */
 
 #include "dccg.h"
-#include "clk_mgr_internal.h"
+#include "rn_clk_mgr.h"
 
 #include "dcn20/dcn20_clk_mgr.h"
-#include "rn_clk_mgr.h"
 #include "dml/dcn20/dcn20_fpu.h"
 
 #include "dce100/dce_clk_mgr.h"
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h
index 2e088c5171b2..f1319957e400 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h
@@ -28,6 +28,7 @@
 
 #include "clk_mgr.h"
 #include "dm_pp_smu.h"
+#include "clk_mgr_internal.h"
 
 extern struct wm_table ddr4_wm_table_gs;
 extern struct wm_table lpddr4_wm_table_gs;
-- 
2.37.1

[PATCH v2 1/3] drm/amd/display: make variables static

2022-07-29 Thread Magali Lemes 
As "dcn3_1_soc", "dcn3_15_soc", and "dcn3_16_soc" are not used outside
of their corresponding "dcn3*_fpu.c", make them static and remove their
extern declaration.

Fixes: 26f4712aedbd ("drm/amd/display: move FPU related code from dcn31 to 
dml/dcn31 folder")
Fixes: fa896297b31b ("drm/amd/display: move FPU related code from dcn315 to 
dml/dcn31 folder")
Fixes: 3f8951cc123f ("drm/amd/display: move FPU related code from dcn316 to 
dml/dcn31 folder")
Signed-off-by: Magali Lemes 
Reviewed-by: Maíra Canal 
Reviewed-by: Melissa Wen 
---
Changes in v2:
  - remove the extern declaration of "dcn3_15_soc" and "dcn3_16_soc"
  instead of just fixing their type (Melissa and André)
  - apply this fix to "dcn3_1_soc" as well
  - update the commit message accordingly
  - add Fixes and Reviewed-by tags.

 drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.h   | 1 -
 drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.h | 1 -
 drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.h | 1 -
 drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c| 6 +++---
 4 files changed, 3 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.h 
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.h
index 41f8ec99da6b..901436591ed4 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.h
@@ -32,7 +32,6 @@
container_of(pool, struct dcn31_resource_pool, base)
 
 extern struct _vcs_dpi_ip_params_st dcn3_1_ip;
-extern struct _vcs_dpi_soc_bounding_box_st dcn3_1_soc;
 
 struct dcn31_resource_pool {
struct resource_pool base;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.h 
b/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.h
index 39929fa67a51..22849eaa6f24 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.h
@@ -32,7 +32,6 @@
container_of(pool, struct dcn315_resource_pool, base)
 
 extern struct _vcs_dpi_ip_params_st dcn3_15_ip;
-extern struct _vcs_dpi_ip_params_st dcn3_15_soc;
 
 struct dcn315_resource_pool {
struct resource_pool base;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.h 
b/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.h
index 0dc5a6c13ae7..aba6d634131b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.h
@@ -32,7 +32,6 @@
container_of(pool, struct dcn316_resource_pool, base)
 
 extern struct _vcs_dpi_ip_params_st dcn3_16_ip;
-extern struct _vcs_dpi_ip_params_st dcn3_16_soc;
 
 struct dcn316_resource_pool {
struct resource_pool base;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
index e36cfa5985ea..5664653ba5ac 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
@@ -114,7 +114,7 @@ struct _vcs_dpi_ip_params_st dcn3_1_ip = {
.dcc_supported = true,
 };
 
-struct _vcs_dpi_soc_bounding_box_st dcn3_1_soc = {
+static struct _vcs_dpi_soc_bounding_box_st dcn3_1_soc = {
/*TODO: correct dispclk/dppclk voltage level determination*/
.clock_limits = {
{
@@ -259,7 +259,7 @@ struct _vcs_dpi_ip_params_st dcn3_15_ip = {
.dcc_supported = true,
 };
 
-struct _vcs_dpi_soc_bounding_box_st dcn3_15_soc = {
+static struct _vcs_dpi_soc_bounding_box_st dcn3_15_soc = {
.sr_exit_time_us = 9.0,
.sr_enter_plus_exit_time_us = 11.0,
.sr_exit_z8_time_us = 50.0,
@@ -355,7 +355,7 @@ struct _vcs_dpi_ip_params_st dcn3_16_ip = {
.dcc_supported = true,
 };
 
-struct _vcs_dpi_soc_bounding_box_st dcn3_16_soc = {
+static struct _vcs_dpi_soc_bounding_box_st dcn3_16_soc = {
/*TODO: correct dispclk/dppclk voltage level determination*/
.clock_limits = {
{
-- 
2.37.1

[PATCH] drm/amd/display: Increase frame-larger-than to 4096 in dml Makefile

2022-07-29 Thread Praful Swarnakar 
When enabling kcov and debug kernel configuration, stack frame size
exceeds set limit, resulting into build error.

Fixes the following build warnings:
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn31/display_mode_vba_31.c:3955:6:
error: stack frame size (2344) exceeds limit (2048) in
'dml31_ModeSupportAndSystemConfigurationFull' [-Werror,-Wframe-larger-than]

Fixes: 5679b6e2c887 ("drm/amd/display: Enable building new display engine with 
KCOV enabled")
Signed-off-by: Praful Swarnakar 
Signed-off-by: Tim Van Patten 
Suggested-by: Raul Rangel 
---
 drivers/gpu/drm/amd/display/dc/dml/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/Makefile 
b/drivers/gpu/drm/amd/display/dc/dml/Makefile
index 359f6e9a1da0..42b1df843a6c 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dml/Makefile
@@ -51,7 +51,7 @@ endif
 endif
 
 ifneq ($(CONFIG_FRAME_WARN),0)
-frame_warn_flag := -Wframe-larger-than=2048
+frame_warn_flag := -Wframe-larger-than=4096
 endif
 
 CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_ccflags)
-- 
2.25.1

[pull] amdgpu, amdkfd drm-next-5.20

2022-07-29 Thread Alex Deucher 
Hi Dave, Daniel,

Fixes for 5.20.  Mainly for new IPs.

The following changes since commit 2bc7ea71a73747a77e7f83bc085b0d2393235410:

  Merge tag 'topic/nouveau-misc-2022-07-27' of 
git://anongit.freedesktop.org/drm/drm into drm-next (2022-07-27 11:34:07 +1000)

are available in the Git repository at:

  https://gitlab.freedesktop.org/agd5f/linux.git 
tags/amd-drm-next-5.20-2022-07-29

for you to fetch changes up to 64f991590ff4410041a70ee7ec2db079bc953929:

  drm/amd/display: Fix a compilation failure on PowerPC caused by FPU code 
(2022-07-29 15:24:38 -0400)


amd-drm-next-5.20-2022-07-29:

amdgpu:
- Misc spelling and grammar fixes
- DC whitespace cleanups
- ACP smatch fix
- GFX 11.0 updates
- PSP 13.0 updates
- VCN 4.0 updates
- DC FP fix for PPC64
- Misc bug fixes

amdkfd:
- SVM fixes


Alex Sierra (2):
  drm/amdkfd: track unified memory reservation with xnack off
  drm/amdgpu: add debugfs for kfd system and ttm mem used

Chengming Gui (2):
  drm/amd/amdgpu: add additional page fault settings for gfx11
  drm/amd/amdgpu: add memory training support for PSP_V13

Dan Carpenter (1):
  drm/amd/display: fix signedness bug in execute_synaptics_rc_command()

Evan Quan (3):
  drm/amdgpu: drop non-necessary call trace dump
  drm/amd/pm: update driver if header for SMU 13.0.0
  drm/amd/pm: enable GFX ULV feature support for SMU13.0.0

Guchun Chen (1):
  drm/amdgpu: use adev_to_drm for consistency

Jack Xiao (1):
  drm/amdgpu: move mes self test after drm sched re-started

Jiapeng Chong (20):
  drm/amd/display: Clean up some inconsistent indenting
  drm/amd/display: Clean up some inconsistent indenting
  drm/amd/display: Clean up some inconsistent indenting
  drm/amd/display: Clean up some inconsistent indenting
  drm/amd/display: Clean up some inconsistent indenting
  drm/amd/display: Clean up some inconsistent indenting
  drm/amd/display: Clean up some inconsistent indenting
  drm/amd/display: Clean up some inconsistent indenting
  drm/amd/display: Clean up some inconsistent indenting
  drm/amd/display: Clean up some inconsistent indenting
  drm/amd/display: Clean up some inconsistent indenting
  drm/amd/display: Clean up some inconsistent indenting
  drm/amd/display: Clean up some inconsistent indenting
  drm/amd/display: Clean up some inconsistent indenting
  drm/amd/display: Clean up some inconsistent indenting
  drm/amd/display: Clean up some inconsistent indenting
  drm/amd/display: Clean up some inconsistent indenting
  drm/amd/display: Clean up some inconsistent indenting
  drm/amd/display: Clean up some inconsistent indenting
  drm/amd/display: Clean up some inconsistent indenting

Jonathan Kim (1):
  drm/amdgpu: fix hive reference leak when reflecting psp topology info

Lang Yu (2):
  drm/amdkfd: fix kgd_mem memory leak when importing dmabuf
  drm/amdkfd: remove an unnecessary amdgpu_bo_ref

Maíra Canal (1):
  drm/amd/display: Remove unused struct freesync_context

Philip Yang (3):
  drm/amdgpu: Allow TTM to evict svm bo from same process
  drm/amdkfd: Set svm range max pages
  drm/amdkfd: Split giant svm range

Rodrigo Siqueira (1):
  drm/amd/display: Fix a compilation failure on PowerPC caused by FPU code

Roy Sun (1):
  drm/amdgpu: Fix the incomplete product number

Shikai Guo (1):
  drm/amd/pm: Add get_gfx_off_status interface for yellow carp

Sonny Jiang (5):
  drm/amdgpu: fix a vcn4 boot poll bug in emulation mode
  drm/amdgpu: add VCN function in NBIO v7.7
  drm/amdgpu: add VCN_4_0_2 firmware support
  drm/amdgpu: vcn_4_0_2 video codec query
  drm/amdgpu: enable VCN cg and JPEG cg/pg

Vijendar Mukunda (1):
  drm/amdgpu: fix i2s_pdata out of bound array access

Xiaojian Du (4):
  drm/amdgpu: send msg to IMU for the front-door loading
  drm/amdgpu: add header files for MP 13.0.4
  drm/amdgpu: add files for PSP 13.0.4
  drm/amdgpu: enable support for psp 13.0.4 block

Yang Li (1):
  drm/amd/display: remove unneeded semicolon

Yifan Zhang (1):
  drm/amdgpu: correct RLC_RLCS_BOOTLOAD_STATUS offset and index

Yu Zhe (1):
  drm/amdkfd: use time_is_before_jiffies(a + b) to replace "jiffies - a > b"

wangjianli (1):
  drm/amdgpu/dc/dce: fix repeated words in comments

 drivers/gpu/drm/amd/amdgpu/Makefile|   3 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu.h|   2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c|   8 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h |   7 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c   |   9 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c   |  51 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |   4 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c  |   4 +-

Re: [PATCH] drm/amd/display: Add a missing register field for HPO DP stream encoder

2022-07-29 Thread Alex Deucher 
Acked-by: Alex Deucher 

On Fri, Jul 29, 2022 at 1:42 PM Aurabindo Pillai
 wrote:
>
> [Why]
> Add the missing definition to set the register field
> HBLANK_MINIMUM_SYMBOL_WIDTH
>
> Signed-off-by: Aurabindo Pillai 
> ---
>  .../gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_stream_encoder.h | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git 
> a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_stream_encoder.h 
> b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_stream_encoder.h
> index 7c77c71591a0..82c3b3ac1f0d 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_stream_encoder.h
> +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_stream_encoder.h
> @@ -162,7 +162,8 @@
> SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0, AIP_ENABLE, 
> mask_sh),\
> SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0, ACM_ENABLE, 
> mask_sh),\
> SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL, CRC_ENABLE, 
> mask_sh),\
> -   SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL, 
> CRC_CONT_MODE_ENABLE, mask_sh)
> +   SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL, 
> CRC_CONT_MODE_ENABLE, mask_sh),\
> +   SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL, 
> HBLANK_MINIMUM_SYMBOL_WIDTH, mask_sh)
>
>
>  #define DCN3_1_HPO_DP_STREAM_ENC_REG_FIELD_LIST(type) \
> --
> 2.37.1
>

[PATCH] drm/amd/display: Add a missing register field for HPO DP stream encoder

2022-07-29 Thread Aurabindo Pillai 
[Why]
Add the missing definition to set the register field
HBLANK_MINIMUM_SYMBOL_WIDTH

Signed-off-by: Aurabindo Pillai 
---
 .../gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_stream_encoder.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_stream_encoder.h 
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_stream_encoder.h
index 7c77c71591a0..82c3b3ac1f0d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_stream_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_stream_encoder.h
@@ -162,7 +162,8 @@
SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0, AIP_ENABLE, 
mask_sh),\
SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0, ACM_ENABLE, 
mask_sh),\
SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL, CRC_ENABLE, mask_sh),\
-   SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL, CRC_CONT_MODE_ENABLE, 
mask_sh)
+   SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL, CRC_CONT_MODE_ENABLE, 
mask_sh),\
+   SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL, 
HBLANK_MINIMUM_SYMBOL_WIDTH, mask_sh)
 
 
 #define DCN3_1_HPO_DP_STREAM_ENC_REG_FIELD_LIST(type) \
-- 
2.37.1

Re: [PATCH 2/2] drm/amdgpu: Pessimistic availability based on rounded up allocations

2022-07-29 Thread Felix Kuehling 
Your patches are missing Signed-off-by lines. If you use "git commit 
-s", git should add those automatically for your convenience. Other than 
that, the patches look good to me. With Signed-off-by added, the series is


Reviewed-by: Felix Kuehling 


Am 2022-07-28 um 23:16 schrieb Daniel Phillips:

Seperately accumulate a statistic of rounded up allocations to use
to report availability, with a view to increasing the likelihood a
buffer object can be successfully allocated at exactly the size
reported by the availability API.
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h   | 1 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 4 +++-
  2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index 73bf8b5f2aa9..781274be5f27 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -96,6 +96,7 @@ struct amdgpu_amdkfd_fence {
  struct amdgpu_kfd_dev {
struct kfd_dev *dev;
uint64_t vram_used;
+   uint64_t vram_used_aligned;
bool init_complete;
struct work_struct reset_work;
  };
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index 014a594899fb..e5ea897f56bc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -181,6 +181,7 @@ static int amdgpu_amdkfd_reserve_mem_limit(struct 
amdgpu_device *adev,
 * memory, TTM memory and GPU memory as computed above
 */
adev->kfd.vram_used += vram_needed;
+   adev->kfd.vram_used_aligned += ALIGN(vram_needed, 
VRAM_AVAILABLITY_ALIGN);
kfd_mem_limit.system_mem_used += system_mem_needed;
kfd_mem_limit.ttm_mem_used += ttm_mem_needed;
  
@@ -199,6 +200,7 @@ static void unreserve_mem_limit(struct amdgpu_device *adev,

kfd_mem_limit.ttm_mem_used -= size;
} else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
adev->kfd.vram_used -= size;
+   adev->kfd.vram_used_aligned -= ALIGN(size, 
VRAM_AVAILABLITY_ALIGN);
} else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
kfd_mem_limit.system_mem_used -= size;
} else if (!(alloc_flag &
@@ -1644,7 +1646,7 @@ size_t amdgpu_amdkfd_get_available_memory(struct 
amdgpu_device *adev)
size_t available;
spin_lock(_mem_limit.mem_limit_lock);
available = adev->gmc.real_vram_size
-   - adev->kfd.vram_used
+   - adev->kfd.vram_used_aligned
- atomic64_read(>vram_pin_size)
- reserved_for_pt;
spin_unlock(_mem_limit.mem_limit_lock);

Re: Please consider Open-source OpenCL support in amdgpu/mesa

2022-07-29 Thread Luís Mendes 
Thanks for the info!

There is also this Mesa candidate RustiCL which is already more
feature complete than the Mesa Clover:
https://www.phoronix.com/news/Mesa-OpenCL-3.0-CTS-Passes
https://www.phoronix.com/news/Rusticl-Darktable-Milestone
and it would be great if this OpenCL implementation materializes.

On Fri, Jul 29, 2022 at 1:37 PM Mike Lothian  wrote:
>
> I've recently gotten ROCm 5.1.3 working on Gentoo with the open
> drivers and using upstream llvm 14.0.6, it's enough to get LuxMark 3
> running (well with fast math disabled)
>
> You might want to look for a distro that packages ROCm for you as
> Clover is nowhere near ready
>
> On Fri, 29 Jul 2022 at 11:06, Luís Mendes  wrote:
> >
> > Hi,
> >
> > I am an Aparapi project developer that has been struggling for two
> > years to get an RX 5700 properly running OpenCL applications.
> >
> > First of all, as an end consumer, I would like to congratulate the
> > open-source amdgpu driver for its stability and performance, as well
> > as the team behind it! Unfortunately I cannot say the same for the
> > closed source, proprietary drivers which have been a nightmare in
> > terms of quality and stability and currently the only way to have
> > OpenCL... which in reality is not the case, because it does not have
> > any stability.
> >
> > The open-source driver has been superior in terms of OpenGL and Vulkan
> > stability and performance, it just misses OpenCL to be complete.
> >
> > I am not expecting any reply on this, nor that it will make the
> > Open-source OpenCL support for AMD graphics cards a reality... I just
> > want to share this reality that I am experiencing for two years, with
> > many amdgpu-pro driver versions tested and also the new deb based
> > amdgpu-install drivers. None of them provided a working solution,
> > neither legacy based, nor rocr based ones. The machine starts running
> > a few OpenCL jobs, which after a few seconds lead to a black screen,
> > followed by GPU reset and machine hanging. The same OpenCL jobs run
> > fine on a GT 1030. There is also a big issue when running the RX 5700
> > as a secondary GPU, aside with the GT 1030 as the primary card, which
> > causes the amdgpu driver to fail to load and renders the RX 5700
> > unusable. I just wanted to share my experience with this card and hope
> > for a better future.
> >
> > Please consider Open-source OpenCL support in amdgpu/mesa.
> >
> > Best regards,
> > Luís Mendes

[PATCH] drm/amd/display: Remove useless else if

2022-07-29 Thread Jiapeng Chong 
The assignment of the else and else if branches is the same, so the else
if here is redundant, so we remove it and add a comment to make the code
here readable.

Eliminate the follow coccicheck warning:

./drivers/comedi/drivers/das1800.c:1300:8-10: WARNING: possible
condition with no effect (if == else).

Reported-by: Abaci Robot 
Signed-off-by: Jiapeng Chong 
---
 drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
index 63861cdfb09f..02bea8f0c8c9 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
@@ -2132,10 +2132,10 @@ static bool dcn314_resource_construct(
 
if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
dc->debug = debug_defaults_drv;
-   else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS)
-   dc->debug = debug_defaults_diags;
else
+   /* This branch contains condition '(dc->ctx->dce_environment == 
DCE_ENV_FPGA_MAXIMUS)' */
dc->debug = debug_defaults_diags;
+
// Init the vm_helper
if (dc->vm_helper)
vm_helper_init(dc->vm_helper, 16);
-- 
2.20.1.7.g153144c

Re: [PATCH] drm/amd/display: Fix a compilation failure on PowerPC caused by FPU code

2022-07-29 Thread Michael Ellerman 
Rodrigo Siqueira  writes:
> We got a report from Stephen/Michael that the PowerPC build was failing
> with the following error:
>
> ld: drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.o uses hard float, 
> drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.o uses soft float
> ld: failed to merge target specific data of file 
> drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.o
>
> This error happened because of the function optc3_set_vrr_m_const. This
> function expects a double as a parameter in a code that is not allowed
> to have FPU operations. After further investigation, it became clear
> that optc3_set_vrr_m_const was never invoked, so we can safely drop this
> function and fix the ld issue.
>
> Cc: Alex Deucher 
> Cc: Melissa Wen 
> Reported-by: Stephen Rothwell 
> Reported-by: Michael Ellerman 
> Signed-off-by: Rodrigo Siqueira 
> ---
>  drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c| 8 
>  drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h| 3 ---
>  drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c| 1 -
>  drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h | 2 --
>  4 files changed, 14 deletions(-)

Thanks, that fixes the build issue for me.

Tested-by: Michael Ellerman 

cheers

Re: Please consider Open-source OpenCL support in amdgpu/mesa

2022-07-29 Thread Mike Lothian 
I've recently gotten ROCm 5.1.3 working on Gentoo with the open
drivers and using upstream llvm 14.0.6, it's enough to get LuxMark 3
running (well with fast math disabled)

You might want to look for a distro that packages ROCm for you as
Clover is nowhere near ready

On Fri, 29 Jul 2022 at 11:06, Luís Mendes  wrote:
>
> Hi,
>
> I am an Aparapi project developer that has been struggling for two
> years to get an RX 5700 properly running OpenCL applications.
>
> First of all, as an end consumer, I would like to congratulate the
> open-source amdgpu driver for its stability and performance, as well
> as the team behind it! Unfortunately I cannot say the same for the
> closed source, proprietary drivers which have been a nightmare in
> terms of quality and stability and currently the only way to have
> OpenCL... which in reality is not the case, because it does not have
> any stability.
>
> The open-source driver has been superior in terms of OpenGL and Vulkan
> stability and performance, it just misses OpenCL to be complete.
>
> I am not expecting any reply on this, nor that it will make the
> Open-source OpenCL support for AMD graphics cards a reality... I just
> want to share this reality that I am experiencing for two years, with
> many amdgpu-pro driver versions tested and also the new deb based
> amdgpu-install drivers. None of them provided a working solution,
> neither legacy based, nor rocr based ones. The machine starts running
> a few OpenCL jobs, which after a few seconds lead to a black screen,
> followed by GPU reset and machine hanging. The same OpenCL jobs run
> fine on a GT 1030. There is also a big issue when running the RX 5700
> as a secondary GPU, aside with the GT 1030 as the primary card, which
> causes the amdgpu driver to fail to load and renders the RX 5700
> unusable. I just wanted to share my experience with this card and hope
> for a better future.
>
> Please consider Open-source OpenCL support in amdgpu/mesa.
>
> Best regards,
> Luís Mendes

Re: [PATCH] drm/amd/display: Fix a compilation failure on PowerPC caused by FPU code

2022-07-29 Thread Maíra Canal 
Hi Siqueira

On 7/28/22 17:33, Rodrigo Siqueira wrote:
> We got a report from Stephen/Michael that the PowerPC build was failing
> with the following error:
> 
> ld: drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.o uses hard float, 
> drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.o uses soft float
> ld: failed to merge target specific data of file 
> drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.o
> 
> This error happened because of the function optc3_set_vrr_m_const. This
> function expects a double as a parameter in a code that is not allowed
> to have FPU operations. After further investigation, it became clear
> that optc3_set_vrr_m_const was never invoked, so we can safely drop this
> function and fix the ld issue.
> 
> Cc: Alex Deucher 
> Cc: Melissa Wen 
> Reported-by: Stephen Rothwell 
> Reported-by: Michael Ellerman 
> Signed-off-by: Rodrigo Siqueira 
> ---
>  drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c| 8 
>  drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h| 3 ---
>  drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c| 1 -
>  drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h | 2 --
>  4 files changed, 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c 
> b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
> index d072997477dd..1782b9c26cf4 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
> @@ -184,14 +184,6 @@ void optc3_set_dsc_config(struct timing_generator *optc,
>   REG_UPDATE(OTG_V_SYNC_A_CNTL, OTG_V_SYNC_MODE, 0);
>  }
>  
> -void optc3_set_vrr_m_const(struct timing_generator *optc,
> - double vtotal_avg)
> -{
> - DC_FP_START();
> - optc3_fpu_set_vrr_m_const(optc, vtotal_avg);

The function optc3_fpu_set_vrr_m_const is only used here, so by deleting 
it, the function optc3_fpu_set_vrr_m_const is declared but not used.
Couldn't it be dropped also?

Best Regards,
- Maíra Canal

> - DC_FP_END();
> -}
> -
>  void optc3_set_odm_bypass(struct timing_generator *optc,
>   const struct dc_crtc_timing *dc_crtc_timing)
>  {
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h 
> b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h
> index 33bd12f5dc17..dd45a5499b07 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h
> +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h
> @@ -329,9 +329,6 @@ void optc3_lock_doublebuffer_enable(struct 
> timing_generator *optc);
>  
>  void optc3_lock_doublebuffer_disable(struct timing_generator *optc);
>  
> -void optc3_set_vrr_m_const(struct timing_generator *optc,
> - double vtotal_avg);
> -
>  void optc3_set_drr_trigger_window(struct timing_generator *optc,
>   uint32_t window_start, uint32_t window_end);
>  
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c 
> b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c
> index 992e56c6907e..eff1f4e17689 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c
> @@ -281,7 +281,6 @@ static struct timing_generator_funcs dcn32_tg_funcs = {
>   .lock_doublebuffer_enable = optc3_lock_doublebuffer_enable,
>   .lock_doublebuffer_disable = optc3_lock_doublebuffer_disable,
>   .enable_optc_clock = optc1_enable_optc_clock,
> - .set_vrr_m_const = optc3_set_vrr_m_const,
>   .set_drr = optc31_set_drr, // TODO: Update to optc32_set_drr 
> once FW headers are promoted
>   .get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,
>   .set_vtotal_min_max = optc3_set_vtotal_min_max,
> diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h 
> b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
> index 62d4683f17a2..4cfa733cf96f 100644
> --- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
> +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
> @@ -302,8 +302,6 @@ struct timing_generator_funcs {
>   int group_idx,
>   uint32_t gsl_ready_signal);
>   void (*set_out_mux)(struct timing_generator *tg, enum otg_out_mux_dest 
> dest);
> - void (*set_vrr_m_const)(struct timing_generator *optc,
> - double vtotal_avg);
>   void (*set_drr_trigger_window)(struct timing_generator *optc,
>   uint32_t window_start, uint32_t window_end);
>   void (*set_vtotal_change_limit)(struct timing_generator *optc,

Please consider Open-source OpenCL support in amdgpu/mesa

2022-07-29 Thread Luís Mendes 
Hi,

I am an Aparapi project developer that has been struggling for two
years to get an RX 5700 properly running OpenCL applications.

First of all, as an end consumer, I would like to congratulate the
open-source amdgpu driver for its stability and performance, as well
as the team behind it! Unfortunately I cannot say the same for the
closed source, proprietary drivers which have been a nightmare in
terms of quality and stability and currently the only way to have
OpenCL... which in reality is not the case, because it does not have
any stability.

The open-source driver has been superior in terms of OpenGL and Vulkan
stability and performance, it just misses OpenCL to be complete.

I am not expecting any reply on this, nor that it will make the
Open-source OpenCL support for AMD graphics cards a reality... I just
want to share this reality that I am experiencing for two years, with
many amdgpu-pro driver versions tested and also the new deb based
amdgpu-install drivers. None of them provided a working solution,
neither legacy based, nor rocr based ones. The machine starts running
a few OpenCL jobs, which after a few seconds lead to a black screen,
followed by GPU reset and machine hanging. The same OpenCL jobs run
fine on a GT 1030. There is also a big issue when running the RX 5700
as a secondary GPU, aside with the GT 1030 as the primary card, which
causes the amdgpu driver to fail to load and renders the RX 5700
unusable. I just wanted to share my experience with this card and hope
for a better future.

Please consider Open-source OpenCL support in amdgpu/mesa.

Best regards,
Luís Mendes

RE: [PATCH v2 6/6] drm/amdgpu: reduce reset time

2022-07-29 Thread Lazar, Lijo 
[AMD Official Use Only - General]

XGMI connected GPUs share the same reset domain software object. If the devices 
are not connected with each other, there is one domain per device.

Thanks,
Lijo

-Original Message-
From: Zhao, Victor  
Sent: Friday, July 29, 2022 2:58 PM
To: Lazar, Lijo ; amd-gfx@lists.freedesktop.org
Cc: Deng, Emily ; Grodzovsky, Andrey 

Subject: RE: [PATCH v2 6/6] drm/amdgpu: reduce reset time

[AMD Official Use Only - General]

Hi Lijo,

Can you be more specific why other gpus can be affected? I don’t have a xgmi 
system on my side. I thought reset_domain is per device.


Thanks,
Victor



-Original Message-
From: Lazar, Lijo  
Sent: Friday, July 29, 2022 2:11 PM
To: Zhao, Victor ; amd-gfx@lists.freedesktop.org
Cc: Deng, Emily ; Grodzovsky, Andrey 

Subject: Re: [PATCH v2 6/6] drm/amdgpu: reduce reset time



On 7/28/2022 4:00 PM, Victor Zhao wrote:
> In multi container use case, reset time is important, so skip ring 
> tests and cp halt wait during ip suspending for reset as they are 
> going to fail and cost more time on reset
> 
> v2: add a hang flag to indicate the reset comes from a job timeout, 
> skip ring test and cp halt wait in this case
> 
> Signed-off-by: Victor Zhao 
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c   |  3 ++-
>   drivers/gpu/drm/amd/amdgpu/amdgpu_job.c   |  2 ++
>   drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c |  1 +
>   drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h |  1 +
>   drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c| 11 +--
>   5 files changed, 15 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> index 222d3d7ea076..c735a17c6afb 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> @@ -27,6 +27,7 @@
>   #include "amdgpu_gfx.h"
>   #include "amdgpu_rlc.h"
>   #include "amdgpu_ras.h"
> +#include "amdgpu_reset.h"
>   
>   /* delay 0.1 second to enable gfx off feature */
>   #define GFX_OFF_DELAY_ENABLE msecs_to_jiffies(100)
> @@ -477,7 +478,7 @@ int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev)
>   kiq->pmf->kiq_unmap_queues(kiq_ring, >gfx.compute_ring[i],
>  RESET_QUEUES, 0, 0);
>   
> - if (adev->gfx.kiq.ring.sched.ready)
> + if (adev->gfx.kiq.ring.sched.ready && !(amdgpu_in_reset(adev) && 
> +adev->reset_domain->hang))
>   r = amdgpu_ring_test_helper(kiq_ring);

On a system with multiple GPUs interconnected, this will affect other GPUs as 
well on which job was not really running. I guess your usecase here is device 
specific.

Thanks,
Lijo

>   spin_unlock(>gfx.kiq.ring_lock);
>   
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
> index 6c3e7290153f..bb40880a557f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
> @@ -49,6 +49,7 @@ static enum drm_gpu_sched_stat amdgpu_job_timedout(struct 
> drm_sched_job *s_job)
>   }
>   
>   memset(, 0, sizeof(struct amdgpu_task_info));
> + adev->reset_domain->hang = true;
>   
>   if (amdgpu_gpu_recovery &&
>   amdgpu_ring_soft_recovery(ring, job->vmid, 
> s_job->s_fence->parent)) { @@ -83,6 +84,7 @@ static enum drm_gpu_sched_stat 
> amdgpu_job_timedout(struct drm_sched_job *s_job)
>   }
>   
>   exit:
> + adev->reset_domain->hang = false;
>   drm_dev_exit(idx);
>   return DRM_GPU_SCHED_STAT_NOMINAL;
>   }
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
> index 9da5ead50c90..b828fe773f50 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
> @@ -155,6 +155,7 @@ struct amdgpu_reset_domain 
> *amdgpu_reset_create_reset_domain(enum amdgpu_reset_d
>   atomic_set(_domain->in_gpu_reset, 0);
>   atomic_set(_domain->reset_res, 0);
>   init_rwsem(_domain->sem);
> + reset_domain->hang = false;
>   
>   return reset_domain;
>   }
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h
> index cc4b2eeb24cf..29e324add552 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h
> @@ -84,6 +84,7 @@ struct amdgpu_reset_domain {
>   struct rw_semaphore sem;
>   atomic_t in_gpu_reset;
>   atomic_t reset_res;
> + bool hang;
>   };
>   
>   
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index fafbad3cf08d..a384e04d916c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -29,6 +29,7 @@
>   #include "amdgpu.h"
>   #include "amdgpu_gfx.h"
>   #include "amdgpu_psp.h"
> +#include "amdgpu_reset.h"
>   #include "nv.h"
>   #include "nvd.h"
>   
> @@ -5971,6 +5972,9 @@ static int gfx_v10_0_cp_gfx_enable(struct

RE: [PATCH v2 6/6] drm/amdgpu: reduce reset time

2022-07-29 Thread Zhao, Victor 
[AMD Official Use Only - General]

Hi Lijo,

Can you be more specific why other gpus can be affected? I don’t have a xgmi 
system on my side. I thought reset_domain is per device.


Thanks,
Victor



-Original Message-
From: Lazar, Lijo  
Sent: Friday, July 29, 2022 2:11 PM
To: Zhao, Victor ; amd-gfx@lists.freedesktop.org
Cc: Deng, Emily ; Grodzovsky, Andrey 

Subject: Re: [PATCH v2 6/6] drm/amdgpu: reduce reset time



On 7/28/2022 4:00 PM, Victor Zhao wrote:
> In multi container use case, reset time is important, so skip ring 
> tests and cp halt wait during ip suspending for reset as they are 
> going to fail and cost more time on reset
> 
> v2: add a hang flag to indicate the reset comes from a job timeout, 
> skip ring test and cp halt wait in this case
> 
> Signed-off-by: Victor Zhao 
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c   |  3 ++-
>   drivers/gpu/drm/amd/amdgpu/amdgpu_job.c   |  2 ++
>   drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c |  1 +
>   drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h |  1 +
>   drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c| 11 +--
>   5 files changed, 15 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> index 222d3d7ea076..c735a17c6afb 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> @@ -27,6 +27,7 @@
>   #include "amdgpu_gfx.h"
>   #include "amdgpu_rlc.h"
>   #include "amdgpu_ras.h"
> +#include "amdgpu_reset.h"
>   
>   /* delay 0.1 second to enable gfx off feature */
>   #define GFX_OFF_DELAY_ENABLE msecs_to_jiffies(100)
> @@ -477,7 +478,7 @@ int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev)
>   kiq->pmf->kiq_unmap_queues(kiq_ring, >gfx.compute_ring[i],
>  RESET_QUEUES, 0, 0);
>   
> - if (adev->gfx.kiq.ring.sched.ready)
> + if (adev->gfx.kiq.ring.sched.ready && !(amdgpu_in_reset(adev) && 
> +adev->reset_domain->hang))
>   r = amdgpu_ring_test_helper(kiq_ring);

On a system with multiple GPUs interconnected, this will affect other GPUs as 
well on which job was not really running. I guess your usecase here is device 
specific.

Thanks,
Lijo

>   spin_unlock(>gfx.kiq.ring_lock);
>   
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
> index 6c3e7290153f..bb40880a557f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
> @@ -49,6 +49,7 @@ static enum drm_gpu_sched_stat amdgpu_job_timedout(struct 
> drm_sched_job *s_job)
>   }
>   
>   memset(, 0, sizeof(struct amdgpu_task_info));
> + adev->reset_domain->hang = true;
>   
>   if (amdgpu_gpu_recovery &&
>   amdgpu_ring_soft_recovery(ring, job->vmid, 
> s_job->s_fence->parent)) { @@ -83,6 +84,7 @@ static enum drm_gpu_sched_stat 
> amdgpu_job_timedout(struct drm_sched_job *s_job)
>   }
>   
>   exit:
> + adev->reset_domain->hang = false;
>   drm_dev_exit(idx);
>   return DRM_GPU_SCHED_STAT_NOMINAL;
>   }
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
> index 9da5ead50c90..b828fe773f50 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
> @@ -155,6 +155,7 @@ struct amdgpu_reset_domain 
> *amdgpu_reset_create_reset_domain(enum amdgpu_reset_d
>   atomic_set(_domain->in_gpu_reset, 0);
>   atomic_set(_domain->reset_res, 0);
>   init_rwsem(_domain->sem);
> + reset_domain->hang = false;
>   
>   return reset_domain;
>   }
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h
> index cc4b2eeb24cf..29e324add552 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h
> @@ -84,6 +84,7 @@ struct amdgpu_reset_domain {
>   struct rw_semaphore sem;
>   atomic_t in_gpu_reset;
>   atomic_t reset_res;
> + bool hang;
>   };
>   
>   
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index fafbad3cf08d..a384e04d916c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -29,6 +29,7 @@
>   #include "amdgpu.h"
>   #include "amdgpu_gfx.h"
>   #include "amdgpu_psp.h"
> +#include "amdgpu_reset.h"
>   #include "nv.h"
>   #include "nvd.h"
>   
> @@ -5971,6 +5972,9 @@ static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device 
> *adev, bool enable)
>   WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
>   }
>   
> + if ((amdgpu_in_reset(adev) && adev->reset_domain->hang) && !enable)
> + return 0;
> +
>   for (i = 0; i < adev->usec_timeout; i++) {
>   if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
>   break;
> @@ -7569,8 +7573,10 @@ static int gfx_v10_0_kiq_disable_kgq(struct 
>

RE: [PATCH v2 1/6] drm/amdgpu: add mode2 reset for sienna_cichlid

2022-07-29 Thread Zhao, Victor 
[AMD Official Use Only - General]

Thanks for catching.


Thanks,
Victor



-Original Message-
From: Quan, Evan  
Sent: Friday, July 29, 2022 2:06 PM
To: Zhao, Victor ; amd-gfx@lists.freedesktop.org
Cc: Deng, Emily ; Zhao, Victor ; 
Grodzovsky, Andrey 
Subject: RE: [PATCH v2 1/6] drm/amdgpu: add mode2 reset for sienna_cichlid

[AMD Official Use Only - General]



> -Original Message-
> From: amd-gfx  On Behalf Of 
> Victor Zhao
> Sent: Thursday, July 28, 2022 6:30 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deng, Emily ; Zhao, Victor 
> ; Grodzovsky, Andrey 
> Subject: [PATCH v2 1/6] drm/amdgpu: add mode2 reset for sienna_cichlid
> 
> To meet the requirement for multi container usecase which needs a 
> quicker reset and not causing VRAM lost, adding the Mode2 reset 
> handler for sienna_cichlid.
> 
> v2: move skip mode2 flag part separately
> 
> Signed-off-by: Victor Zhao 
> ---
>  drivers/gpu/drm/amd/amdgpu/Makefile   |   2 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c |   7 +
>  drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c   | 297
> ++
>  drivers/gpu/drm/amd/amdgpu/sienna_cichlid.h   |  32 ++
>  .../pm/swsmu/inc/pmfw_if/smu_v11_0_7_ppsmc.h  |   4 +-
>  drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h  |   3 +-
>  .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c   |  54 
>  7 files changed, 395 insertions(+), 4 deletions(-)  create mode 
> 100644 drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c
>  create mode 100644 drivers/gpu/drm/amd/amdgpu/sienna_cichlid.h
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
> b/drivers/gpu/drm/amd/amdgpu/Makefile
> index c7d0cd15b5ef..7030ac2d7d2c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/Makefile
> +++ b/drivers/gpu/drm/amd/amdgpu/Makefile
> @@ -75,7 +75,7 @@ amdgpu-y += \
>   vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o 
> vega10_reg_init.o \
>   vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o arct_reg_init.o 
> mxgpu_nv.o \
>   nbio_v7_2.o hdp_v4_0.o hdp_v5_0.o aldebaran_reg_init.o aldebaran.o 
> soc21.o \
> - nbio_v4_3.o hdp_v6_0.o nbio_v7_7.o hdp_v5_2.o lsdma_v6_0.o
> + sienna_cichlid.o nbio_v4_3.o hdp_v6_0.o nbio_v7_7.o hdp_v5_2.o
> lsdma_v6_0.o
> 
>  # add DF block
>  amdgpu-y += \
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
> index 32c86a0b145c..f778466bb9db 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
> @@ -23,6 +23,7 @@
> 
>  #include "amdgpu_reset.h"
>  #include "aldebaran.h"
> +#include "sienna_cichlid.h"
> 
>  int amdgpu_reset_add_handler(struct amdgpu_reset_control *reset_ctl,
>struct amdgpu_reset_handler *handler) @@ -40,6 
> +41,9 @@ int 
> amdgpu_reset_init(struct amdgpu_device *adev)
>   case IP_VERSION(13, 0, 2):
>   ret = aldebaran_reset_init(adev);
>   break;
> + case IP_VERSION(11, 0, 7):
> + ret = sienna_cichlid_reset_init(adev);
> + break;
>   default:
>   break;
>   }
> @@ -55,6 +59,9 @@ int amdgpu_reset_fini(struct amdgpu_device *adev)
>   case IP_VERSION(13, 0, 2):
>   ret = aldebaran_reset_fini(adev);
>   break;
> + case IP_VERSION(11, 0, 7):
> + ret = sienna_cichlid_reset_fini(adev);
> + break;
>   default:
>   break;
>   }
> diff --git a/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c
> b/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c
> new file mode 100644
> index ..0512960bed23
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c
> @@ -0,0 +1,297 @@
> +/*
> + * Copyright 2021 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person 
> +obtaining a
> + * copy of this software and associated documentation files (the
> "Software"),
> + * to deal in the Software without restriction, including without 
> + limitation
> + * the rights to use, copy, modify, merge, publish, distribute, 
> + sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom 
> + the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be 
> + included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO
> EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM,
> DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
> OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR
> THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> + */
> +
> +#include "sienna_cichlid.h"
> +#include "amdgpu_reset.h"
> +#include

Re: [PATCH v3 6/6] drm/ttm: Switch to using the new res callback

2022-07-29 Thread Arunpravin Paneer Selvam 




On 7/28/2022 9:07 PM, Matthew Auld wrote:

On 28/07/2022 15:33, Arunpravin Paneer Selvam wrote:

Apply new intersect and compatible callback instead
of having a generic placement range verfications.

v2: Added a separate callback for compatiblilty
 checks (Christian)

Signed-off-by: Christian König 
Signed-off-by: Arunpravin Paneer Selvam 



There is also some code at the bottom of i915_ttm_buddy_man_alloc() 
playing games with res->start, which I think can be safely deleted 
with this series (now that we have proper ->compatible() hook).


Also, is the plan to remove res->start completely, or does that still 
have a use?
yes we should remove res->start completely, I am working on it, planning 
to send in a separate series as amdgpu uses it in many places, and in 
some places we set res->start to AMDGPU_BO_INVALID_OFFSET,
I should find an alternative to indicate the invalid offset BO. Also, 
res->start used in drm/drm_gem_vram_helper.c at drm_gem_vram_pg_offset() 
function. I am removing all the dependencies, I will send the
patches in a separate series. I think i915 doesn't use res->start in its 
own driver code.



---
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 45 +++--
  drivers/gpu/drm/ttm/ttm_bo.c    |  9 +++--
  drivers/gpu/drm/ttm/ttm_resource.c  |  5 +--
  3 files changed, 20 insertions(+), 39 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

index 170935c294f5..7d25a10395c0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1328,11 +1328,12 @@ uint64_t amdgpu_ttm_tt_pte_flags(struct 
amdgpu_device *adev, struct ttm_tt *ttm,
  static bool amdgpu_ttm_bo_eviction_valuable(struct 
ttm_buffer_object *bo,

  const struct ttm_place *place)
  {
-    unsigned long num_pages = bo->resource->num_pages;
  struct dma_resv_iter resv_cursor;
-    struct amdgpu_res_cursor cursor;
  struct dma_fence *f;
  +    if (!amdgpu_bo_is_amdgpu_bo(bo))
+    return ttm_bo_eviction_valuable(bo, place);
+
  /* Swapout? */
  if (bo->resource->mem_type == TTM_PL_SYSTEM)
  return true;
@@ -1351,40 +1352,20 @@ static bool 
amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,

  return false;
  }
  -    switch (bo->resource->mem_type) {
-    case AMDGPU_PL_PREEMPT:
-    /* Preemptible BOs don't own system resources managed by the
- * driver (pages, VRAM, GART space). They point to resources
- * owned by someone else (e.g. pageable memory in user mode
- * or a DMABuf). They are used in a preemptible context so we
- * can guarantee no deadlocks and good QoS in case of MMU
- * notifiers or DMABuf move notifiers from the resource owner.
- */
+    /* Preemptible BOs don't own system resources managed by the
+ * driver (pages, VRAM, GART space). They point to resources
+ * owned by someone else (e.g. pageable memory in user mode
+ * or a DMABuf). They are used in a preemptible context so we
+ * can guarantee no deadlocks and good QoS in case of MMU
+ * notifiers or DMABuf move notifiers from the resource owner.
+ */
+    if (bo->resource->mem_type == AMDGPU_PL_PREEMPT)
  return false;
-    case TTM_PL_TT:
-    if (amdgpu_bo_is_amdgpu_bo(bo) &&
-    amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo)))
-    return false;
-    return true;
  -    case TTM_PL_VRAM:
-    /* Check each drm MM node individually */
-    amdgpu_res_first(bo->resource, 0, (u64)num_pages << PAGE_SHIFT,
- );
-    while (cursor.remaining) {
-    if (place->fpfn < PFN_DOWN(cursor.start + cursor.size)
-    && !(place->lpfn &&
- place->lpfn <= PFN_DOWN(cursor.start)))
-    return true;
-
-    amdgpu_res_next(, cursor.size);
-    }
+    if (bo->resource->mem_type == TTM_PL_TT &&
+    amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo)))
  return false;
  -    default:
-    break;
-    }
-
  return ttm_bo_eviction_valuable(bo, place);
  }
  diff --git a/drivers/gpu/drm/ttm/ttm_bo.c 
b/drivers/gpu/drm/ttm/ttm_bo.c

index c1bd006a5525..03409409e43e 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -518,6 +518,9 @@ static int ttm_bo_evict(struct ttm_buffer_object 
*bo,

  bool ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
    const struct ttm_place *place)
  {
+    struct ttm_resource *res = bo->resource;
+    struct ttm_device *bdev = bo->bdev;
+
  dma_resv_assert_held(bo->base.resv);
  if (bo->resource->mem_type == TTM_PL_SYSTEM)
  return true;
@@ -525,11 +528,7 @@ bool ttm_bo_eviction_valuable(struct 
ttm_buffer_object *bo,

  /* Don't evict this BO if it's outside of the
   * requested placement range
   */
-    if (place->fpfn >= (bo->resource->start +

Re: [PATCH v3 4/6] drm/i915: Implement intersect/compatible functions

2022-07-29 Thread Arunpravin Paneer Selvam 




On 7/28/2022 8:57 PM, Matthew Auld wrote:

On 28/07/2022 15:33, Arunpravin Paneer Selvam wrote:

Implemented a new intersect and compatible callback function
fetching start offset from drm buddy allocator.

v2: move the bits that are specific to buddy_man (Matthew)

Signed-off-by: Christian König 
Signed-off-by: Arunpravin Paneer Selvam 


---
  drivers/gpu/drm/i915/gem/i915_gem_ttm.c   | 39 +---
  drivers/gpu/drm/i915/i915_ttm_buddy_manager.c | 62 +++
  2 files changed, 64 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c 
b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c

index 70e2ed4e99df..54eead15d74b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -396,43 +396,8 @@ static bool i915_ttm_eviction_valuable(struct 
ttm_buffer_object *bo,

  if (!i915_gem_object_evictable(obj))
  return false;
  -    switch (res->mem_type) {
-    case I915_PL_LMEM0: {
-    struct ttm_resource_manager *man =
-    ttm_manager_type(bo->bdev, res->mem_type);
-    struct i915_ttm_buddy_resource *bman_res =
-    to_ttm_buddy_resource(res);
-    struct drm_buddy *mm = bman_res->mm;
-    struct drm_buddy_block *block;
-
-    if (!place->fpfn && !place->lpfn)
-    return true;
-
-    GEM_BUG_ON(!place->lpfn);
-
-    /*
- * If we just want something mappable then we can quickly check
- * if the current victim resource is using any of the CPU
- * visible portion.
- */
-    if (!place->fpfn &&
-    place->lpfn == i915_ttm_buddy_man_visible_size(man))
-    return bman_res->used_visible_size > 0;
-
-    /* Real range allocation */
-    list_for_each_entry(block, _res->blocks, link) {
-    unsigned long fpfn =
-    drm_buddy_block_offset(block) >> PAGE_SHIFT;
-    unsigned long lpfn = fpfn +
-    (drm_buddy_block_size(mm, block) >> PAGE_SHIFT);
-
-    if (place->fpfn < lpfn && place->lpfn > fpfn)
-    return true;
-    }
-    return false;
-    } default:
-    break;
-    }
+    if (res->mem_type == I915_PL_LMEM0)
+    return ttm_bo_eviction_valuable(bo, place);


We should be able to drop the mem_type == I915_PL_LMEM0 check here I 
think, and just unconditionally do:


return ttm_bo_eviction_valuable(bo, place);

okay



    return true;
  }
diff --git a/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c 
b/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c

index a5109548abc0..9d2a31154d58 100644
--- a/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c
+++ b/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c
@@ -178,6 +178,66 @@ static void i915_ttm_buddy_man_free(struct 
ttm_resource_manager *man,

  kfree(bman_res);
  }
  +static bool i915_ttm_buddy_man_intersect(struct 
ttm_resource_manager *man,


Nit: intersects

ok



+ struct ttm_resource *res,
+ const struct ttm_place *place,
+ size_t size)
+{
+    struct i915_ttm_buddy_resource *bman_res = 
to_ttm_buddy_resource(res);

+    u32 start, num_pages = PFN_UP(size);
+    struct drm_buddy_block *block;
+
+    if (!place->fpfn && !place->lpfn)
+    return true;

I place bug_on check here
GEM_BUG_ON(!place->lpfn);

+
+    /*
+ * If we just want something mappable then we can quickly check
+ * if the current victim resource is using any of the CP
+ * visible portion.
+ */
+    if (!place->fpfn &&
+    place->lpfn == i915_ttm_buddy_man_visible_size(man))
+    return bman_res->used_visible_size > 0;
+
+    /* Check each drm buddy block individually */
+    list_for_each_entry(block, _res->blocks, link) {
+    start = drm_buddy_block_offset(block) >> PAGE_SHIFT;
+    /* Don't evict BOs outside of the requested placement range */
+    if (place->fpfn >= (start + num_pages) ||
+    (place->lpfn && place->lpfn <= start))
+    return false;
+    }
+
+    return true;


We need to account for the block size somewhere. Also same bug in the 
amdgpu patch it seems. We also need to do this the other way around 
and keep checking until we find something that overlaps, for example 
if the first block doesn't intersect/overlap we will incorrectly 
return false here, even if one of the other blocks does intersect.


list_for_each_entry() {
    fpfn = drm_buddy_block_size(mm, block) >> PAGE_SHIFT;
    lpfn = fpfn + drm_buddy_block_size(mm, block) >> PAGE_SHIFT);

    if (place->fpfn < lpfn && place->lpfn > fpfn)
    return true;
}

return false;

yes, here the final code looks like,
list_for_each_entry(block, _res->blocks, link) {
    unsigned long fpfn =
    drm_buddy_block_offset(block) >> PAGE_SHIFT;
    unsigned long lpfn = fpfn +
    (drm_buddy_block_size(mm, block) >> PAGE_SHIFT);
    /* Don't evict BOs

Re: [PATCH v2 6/6] drm/amdgpu: reduce reset time

2022-07-29 Thread Lazar, Lijo 




On 7/28/2022 4:00 PM, Victor Zhao wrote:

In multi container use case, reset time is important, so skip ring
tests and cp halt wait during ip suspending for reset as they are
going to fail and cost more time on reset

v2: add a hang flag to indicate the reset comes from a job timeout,
skip ring test and cp halt wait in this case

Signed-off-by: Victor Zhao 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c   |  3 ++-
  drivers/gpu/drm/amd/amdgpu/amdgpu_job.c   |  2 ++
  drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c |  1 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h |  1 +
  drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c| 11 +--
  5 files changed, 15 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index 222d3d7ea076..c735a17c6afb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -27,6 +27,7 @@
  #include "amdgpu_gfx.h"
  #include "amdgpu_rlc.h"
  #include "amdgpu_ras.h"
+#include "amdgpu_reset.h"
  
  /* delay 0.1 second to enable gfx off feature */

  #define GFX_OFF_DELAY_ENABLE msecs_to_jiffies(100)
@@ -477,7 +478,7 @@ int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev)
kiq->pmf->kiq_unmap_queues(kiq_ring, >gfx.compute_ring[i],
   RESET_QUEUES, 0, 0);
  
-	if (adev->gfx.kiq.ring.sched.ready)

+   if (adev->gfx.kiq.ring.sched.ready && !(amdgpu_in_reset(adev) && 
adev->reset_domain->hang))
r = amdgpu_ring_test_helper(kiq_ring);


On a system with multiple GPUs interconnected, this will affect other 
GPUs as well on which job was not really running. I guess your usecase 
here is device specific.


Thanks,
Lijo


spin_unlock(>gfx.kiq.ring_lock);
  
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c

index 6c3e7290153f..bb40880a557f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
@@ -49,6 +49,7 @@ static enum drm_gpu_sched_stat amdgpu_job_timedout(struct 
drm_sched_job *s_job)
}
  
  	memset(, 0, sizeof(struct amdgpu_task_info));

+   adev->reset_domain->hang = true;
  
  	if (amdgpu_gpu_recovery &&

amdgpu_ring_soft_recovery(ring, job->vmid, s_job->s_fence->parent)) 
{
@@ -83,6 +84,7 @@ static enum drm_gpu_sched_stat amdgpu_job_timedout(struct 
drm_sched_job *s_job)
}
  
  exit:

+   adev->reset_domain->hang = false;
drm_dev_exit(idx);
return DRM_GPU_SCHED_STAT_NOMINAL;
  }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
index 9da5ead50c90..b828fe773f50 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
@@ -155,6 +155,7 @@ struct amdgpu_reset_domain 
*amdgpu_reset_create_reset_domain(enum amdgpu_reset_d
atomic_set(_domain->in_gpu_reset, 0);
atomic_set(_domain->reset_res, 0);
init_rwsem(_domain->sem);
+   reset_domain->hang = false;
  
  	return reset_domain;

  }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h
index cc4b2eeb24cf..29e324add552 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h
@@ -84,6 +84,7 @@ struct amdgpu_reset_domain {
struct rw_semaphore sem;
atomic_t in_gpu_reset;
atomic_t reset_res;
+   bool hang;
  };
  
  
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

index fafbad3cf08d..a384e04d916c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -29,6 +29,7 @@
  #include "amdgpu.h"
  #include "amdgpu_gfx.h"
  #include "amdgpu_psp.h"
+#include "amdgpu_reset.h"
  #include "nv.h"
  #include "nvd.h"
  
@@ -5971,6 +5972,9 @@ static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)

WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
}
  
+	if ((amdgpu_in_reset(adev) && adev->reset_domain->hang) && !enable)

+   return 0;
+
for (i = 0; i < adev->usec_timeout; i++) {
if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
break;
@@ -7569,8 +7573,10 @@ static int gfx_v10_0_kiq_disable_kgq(struct 
amdgpu_device *adev)
for (i = 0; i < adev->gfx.num_gfx_rings; i++)
kiq->pmf->kiq_unmap_queues(kiq_ring, >gfx.gfx_ring[i],
   PREEMPT_QUEUES, 0, 0);
-
-   return amdgpu_ring_test_helper(kiq_ring);
+   if (!(amdgpu_in_reset(adev) && adev->reset_domain->hang))
+   return amdgpu_ring_test_helper(kiq_ring);
+   else
+   return 0;
  }
  #endif
  
@@ -7610,6 +7616,7 @@ static int gfx_v10_0_hw_fini(void *handle)
  
  		return 0;

}
+
gfx_v10_0_cp_enable(adev, false);

RE: [PATCH v2 1/6] drm/amdgpu: add mode2 reset for sienna_cichlid

2022-07-29 Thread Quan, Evan 
[AMD Official Use Only - General]



> -Original Message-
> From: amd-gfx  On Behalf Of
> Victor Zhao
> Sent: Thursday, July 28, 2022 6:30 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deng, Emily ; Zhao, Victor
> ; Grodzovsky, Andrey
> 
> Subject: [PATCH v2 1/6] drm/amdgpu: add mode2 reset for sienna_cichlid
> 
> To meet the requirement for multi container usecase which needs
> a quicker reset and not causing VRAM lost, adding the Mode2
> reset handler for sienna_cichlid.
> 
> v2: move skip mode2 flag part separately
> 
> Signed-off-by: Victor Zhao 
> ---
>  drivers/gpu/drm/amd/amdgpu/Makefile   |   2 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c |   7 +
>  drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c   | 297
> ++
>  drivers/gpu/drm/amd/amdgpu/sienna_cichlid.h   |  32 ++
>  .../pm/swsmu/inc/pmfw_if/smu_v11_0_7_ppsmc.h  |   4 +-
>  drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h  |   3 +-
>  .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c   |  54 
>  7 files changed, 395 insertions(+), 4 deletions(-)
>  create mode 100644 drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c
>  create mode 100644 drivers/gpu/drm/amd/amdgpu/sienna_cichlid.h
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
> b/drivers/gpu/drm/amd/amdgpu/Makefile
> index c7d0cd15b5ef..7030ac2d7d2c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/Makefile
> +++ b/drivers/gpu/drm/amd/amdgpu/Makefile
> @@ -75,7 +75,7 @@ amdgpu-y += \
>   vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o
> nbio_v7_0.o vega10_reg_init.o \
>   vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o arct_reg_init.o
> mxgpu_nv.o \
>   nbio_v7_2.o hdp_v4_0.o hdp_v5_0.o aldebaran_reg_init.o
> aldebaran.o soc21.o \
> - nbio_v4_3.o hdp_v6_0.o nbio_v7_7.o hdp_v5_2.o lsdma_v6_0.o
> + sienna_cichlid.o nbio_v4_3.o hdp_v6_0.o nbio_v7_7.o hdp_v5_2.o
> lsdma_v6_0.o
> 
>  # add DF block
>  amdgpu-y += \
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
> index 32c86a0b145c..f778466bb9db 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
> @@ -23,6 +23,7 @@
> 
>  #include "amdgpu_reset.h"
>  #include "aldebaran.h"
> +#include "sienna_cichlid.h"
> 
>  int amdgpu_reset_add_handler(struct amdgpu_reset_control *reset_ctl,
>struct amdgpu_reset_handler *handler)
> @@ -40,6 +41,9 @@ int amdgpu_reset_init(struct amdgpu_device *adev)
>   case IP_VERSION(13, 0, 2):
>   ret = aldebaran_reset_init(adev);
>   break;
> + case IP_VERSION(11, 0, 7):
> + ret = sienna_cichlid_reset_init(adev);
> + break;
>   default:
>   break;
>   }
> @@ -55,6 +59,9 @@ int amdgpu_reset_fini(struct amdgpu_device *adev)
>   case IP_VERSION(13, 0, 2):
>   ret = aldebaran_reset_fini(adev);
>   break;
> + case IP_VERSION(11, 0, 7):
> + ret = sienna_cichlid_reset_fini(adev);
> + break;
>   default:
>   break;
>   }
> diff --git a/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c
> b/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c
> new file mode 100644
> index ..0512960bed23
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c
> @@ -0,0 +1,297 @@
> +/*
> + * Copyright 2021 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the
> "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO
> EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM,
> DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
> OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR
> THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> + */
> +
> +#include "sienna_cichlid.h"
> +#include "amdgpu_reset.h"
> +#include "amdgpu_amdkfd.h"
> +#include "amdgpu_dpm.h"
> +#include "amdgpu_job.h"
> +#include "amdgpu_ring.h"
> +#include "amdgpu_ras.h"
> +#include "amdgpu_psp.h"
> +#include "amdgpu_xgmi.h"
> +
> +static struct amdgpu_reset_handler *
> +sienna_cichlid_get_reset_handler(struct amdgpu_reset_control *reset_ctl,
> + struct amdgpu_reset_context