RE: [RESEND RFC 15/18] drm/display/dp_mst: Skip releasing payloads if last connected port isn't connected

[Lin, Wayne]

[Public]



> -Original Message-
> From: Lyude Paul 
> Sent: Wednesday, August 3, 2022 6:12 AM
> To: Lin, Wayne ; dri-de...@lists.freedesktop.org;
> nouv...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org
> Cc: Ville Syrjälä ; Zuo, Jerry
> ; Jani Nikula ; Imre Deak
> ; Daniel Vetter ; Sean Paul
> ; David Airlie ; Daniel Vetter
> ; Thomas Zimmermann ; Lakha,
> Bhawanpreet ; open list  ker...@vger.kernel.org>
> Subject: Re: [RESEND RFC 15/18] drm/display/dp_mst: Skip releasing
> payloads if last connected port isn't connected
> 
> On Tue, 2022-07-05 at 08:45 +, Lin, Wayne wrote:
> > [Public]
> >
> >
> >
> > > -Original Message-
> > > From: Lyude Paul 
> > > Sent: Wednesday, June 8, 2022 3:30 AM
> > > To: dri-de...@lists.freedesktop.org; nouv...@lists.freedesktop.org;
> > > amd- g...@lists.freedesktop.org
> > > Cc: Lin, Wayne ; Ville Syrjälä
> > > ; Zuo, Jerry ;
> > > Jani Nikula ; Imre Deak
> > > ; Daniel Vetter ; Sean
> > > Paul ; David Airlie ; Daniel
> > > Vetter ; Thomas Zimmermann
> ;
> > > Lakha, Bhawanpreet ; open list
> > > 
> > > Subject: [RESEND RFC 15/18] drm/display/dp_mst: Skip releasing
> > > payloads if last connected port isn't connected
> > >
> > > In the past, we've ran into strange issues regarding errors in
> > > response to trying to destroy payloads after a port has been
> > > unplugged. We fixed this back in:
> > >
> > > This is intended to replace the workaround that was added here:
> > >
> > > commit 3769e4c0af5b ("drm/dp_mst: Avoid to mess up payload table by
> > > ports in stale topology")
> > >
> > > which was intended fix to some of the payload leaks that were
> > > observed before, where we would attempt to determine if the port was
> > > still connected to the topology before updating payloads using
> > > drm_dp_mst_port_downstream_of_branch. This wasn't a particularly
> > > good solution, since one of the points of still having port and mstb
> > > validation is to avoid sending messages to newly disconnected
> > > branches wherever possible
> > > - thus the required use of drm_dp_mst_port_downstream_of_branch
> > > would indicate something may be wrong with said validation.
> > >
> > > It seems like it may have just been races and luck that made
> > > drm_dp_mst_port_downstream_of_branch work however, as while I
> was
> > > trying to figure out the true cause of this issue when removing the
> > > legacy MST code - I discovered an important excerpt in section
> > > 2.14.2.3.3.6 of the DP
> > > 2.0
> > > specs:
> > >
> > > "BAD_PARAM - This reply is transmitted when a Message Transaction
> > > parameter is in error; for example, the next port number is invalid
> > > or /no device is connected/ to the port associated with the port number."
> > >
> > > Sure enough - removing the calls to
> > > drm_dp_mst_port_downstream_of_branch()
> > > and instead checking the ->ddps field of the parent port to see
> > > whether we should release a given payload or not seems to totally
> > > fix the issue. This does actually make sense to me, as it seems the
> > > implication is that given a topology where an MSTB is removed, the
> > > payload for the MST parent's port will be released automatically if
> > > that port is also marked as disconnected.
> > > However, if there's another parent in the chain after that which is
> > > connected
> > > - payloads must be released there with an ALLOCATE_PAYLOAD message.
> > >
> > > So, let's do that!
> > >
> > > Signed-off-by: Lyude Paul 
> > > Cc: Wayne Lin 
> > > Cc: Ville Syrjälä 
> > > Cc: Fangzhi Zuo 
> > > Cc: Jani Nikula 
> > > Cc: Imre Deak 
> > > Cc: Daniel Vetter 
> > > Cc: Sean Paul 
> > > ---
> > >  drivers/gpu/drm/display/drm_dp_mst_topology.c | 51
> > > +++
> > >  1 file changed, 17 insertions(+), 34 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c
> > > b/drivers/gpu/drm/display/drm_dp_mst_topology.c
> > > index dd314586bac3..70adb8db4335 100644
> > > --- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
> > > +++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
> > > @@ -3137,7 +3137,7 @@ static struct drm_dp_mst_port
> > > *drm_dp_get_last_connected_port_to_mstb(struct drm  static struct
> > > drm_dp_mst_branch
> *  drm_dp_get_last_connected_port_and_mstb(struct
> > > drm_dp_mst_topology_mgr *mgr,
> > > struct drm_dp_mst_branch
> > > *mstb,
> > > -   int *port_num)
> > > +   struct drm_dp_mst_port
> > > **last_port)
> > >  {
> > > struct drm_dp_mst_branch *rmstb = NULL;
> > > struct drm_dp_mst_port *found_port; @@ -3153,7 +3153,8 @@
> > > drm_dp_get_last_connected_port_and_mstb(struct
> > > drm_dp_mst_topology_mgr *mgr,
> > >
> > > if (drm_dp_mst_topology_try_get_mstb(found_port-
> > > > parent)) {
> > > rmstb = found_port->parent;
> > > -   *port_num = found_port->port_num;
> > > +

[PATCH 3/3] drm/amd/pm: add missing ->fini_xxxx interfaces for some SMU13 asics

[Evan Quan]

Without these, potential memory leak may be induced.

Signed-off-by: Evan Quan 
Change-Id: Ied7cd204d44d739dece11774c9d29e7a192fd341
---
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 2 ++
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index 1bbeceeb9e3c..df4a47acd724 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -1792,7 +1792,9 @@ static const struct pptable_funcs smu_v13_0_0_ppt_funcs = 
{
.dump_pptable = smu_v13_0_0_dump_pptable,
.init_microcode = smu_v13_0_init_microcode,
.load_microcode = smu_v13_0_load_microcode,
+   .fini_microcode = smu_v13_0_fini_microcode,
.init_smc_tables = smu_v13_0_0_init_smc_tables,
+   .fini_smc_tables = smu_v13_0_fini_smc_tables,
.init_power = smu_v13_0_init_power,
.fini_power = smu_v13_0_fini_power,
.check_fw_status = smu_v13_0_check_fw_status,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
index 9dd56e73218b..d78375d9a141 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
@@ -1574,7 +1574,9 @@ static const struct pptable_funcs smu_v13_0_7_ppt_funcs = 
{
.dump_pptable = smu_v13_0_7_dump_pptable,
.init_microcode = smu_v13_0_init_microcode,
.load_microcode = smu_v13_0_load_microcode,
+   .fini_microcode = smu_v13_0_fini_microcode,
.init_smc_tables = smu_v13_0_7_init_smc_tables,
+   .fini_smc_tables = smu_v13_0_fini_smc_tables,
.init_power = smu_v13_0_init_power,
.fini_power = smu_v13_0_fini_power,
.check_fw_status = smu_v13_0_7_check_fw_status,
-- 
2.29.0

[PATCH 2/3] drm/amd/pm: add missing ->fini_microcode interface for Sienna Cichlid

[Evan Quan]

To avoid any potential memory leak.

Signed-off-by: Evan Quan 
Change-Id: Ide94e85d862c10aae93e04e3ce64c0451e5e1570
---
 drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index a73d241bb64f..7ed4d4265797 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -4335,6 +4335,7 @@ static const struct pptable_funcs 
sienna_cichlid_ppt_funcs = {
.dump_pptable = sienna_cichlid_dump_pptable,
.init_microcode = smu_v11_0_init_microcode,
.load_microcode = smu_v11_0_load_microcode,
+   .fini_microcode = smu_v11_0_fini_microcode,
.init_smc_tables = sienna_cichlid_init_smc_tables,
.fini_smc_tables = smu_v11_0_fini_smc_tables,
.init_power = smu_v11_0_init_power,
-- 
2.29.0

[PATCH 1/3] drm/amdgpu: disable 3DCGCG/CGLS temporarily due to stability issue

[Evan Quan]

Some stability issues were reported with these features.

Signed-off-by: Evan Quan 
Change-Id: I5fccae63bd530d6ff9e4167bb1c44319830806f9
---
 drivers/gpu/drm/amd/amdgpu/soc21.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c 
b/drivers/gpu/drm/amd/amdgpu/soc21.c
index bbbf760f8ad2..77d549dbe2a8 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc21.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
@@ -546,8 +546,10 @@ static int soc21_common_early_init(void *handle)
case IP_VERSION(11, 0, 0):
adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG |
AMD_CG_SUPPORT_GFX_CGLS |
+#if 0
AMD_CG_SUPPORT_GFX_3D_CGCG |
AMD_CG_SUPPORT_GFX_3D_CGLS |
+#endif
AMD_CG_SUPPORT_GFX_MGCG |
AMD_CG_SUPPORT_REPEATER_FGCG |
AMD_CG_SUPPORT_GFX_FGCG |
-- 
2.29.0

[RFC v3] drm/display/dp_mst: Add helpers for serializing SST <-> MST transitions

[Lyude Paul]

There's another kind of situation where we could potentially race with
nonblocking modesets and MST, especially if we were to only use the locking
provided by atomic modesetting:

* Display 1 begins as enabled on DP-1 in SST mode
* Display 1 switches to MST mode, exposes one sink in MST mode
* Userspace does non-blocking modeset to disable the SST display
* Userspace does non-blocking modeset to enable the MST display with a
  different CRTC, but the SST display hasn't been fully taken down yet
* Execution order between the last two commits isn't guaranteed since they
  share no drm resources

We can fix this however, by ensuring that we always pull in the atomic
topology state whenever a connector capable of driving an MST display
performs its atomic check - and then tracking CRTC commits happening on the
SST connector in the MST topology state. So, let's add some simple helpers
for doing that and hook them up in various drivers.

v2:
* Use intel_dp_mst_source_support() to check for MST support in i915, fixes
  CI failures

Signed-off-by: Lyude Paul 
Cc: Wayne Lin 
Cc: Ville Syrjälä 
Cc: Fangzhi Zuo 
Cc: Jani Nikula 
Cc: Imre Deak 
Cc: Daniel Vetter 
Cc: Sean Paul 
Acked-by: Jani Nikula 
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  7 +++
 drivers/gpu/drm/display/drm_dp_mst_topology.c | 59 +++
 drivers/gpu/drm/i915/display/intel_dp.c   |  9 +++
 drivers/gpu/drm/nouveau/dispnv50/disp.c   |  2 +-
 drivers/gpu/drm/nouveau/dispnv50/disp.h   |  2 +
 drivers/gpu/drm/nouveau/nouveau_connector.c   | 14 +
 include/drm/display/drm_dp_mst_helper.h   |  2 +
 7 files changed, 94 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 1739710003a4..51732bd603a9 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -6318,10 +6318,17 @@ amdgpu_dm_connector_atomic_check(struct drm_connector 
*conn,
drm_atomic_get_old_connector_state(state, conn);
struct drm_crtc *crtc = new_con_state->crtc;
struct drm_crtc_state *new_crtc_state;
+   struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn);
int ret;
 
trace_amdgpu_dm_connector_atomic_check(new_con_state);
 
+   if (conn->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
+   ret = drm_dp_mst_root_conn_atomic_check(new_con_state, 
&aconn->mst_mgr);
+   if (ret < 0)
+   return ret;
+   }
+
if (!crtc)
return 0;
 
diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c 
b/drivers/gpu/drm/display/drm_dp_mst_topology.c
index 2f7c43f88d74..97e8f8a83ed4 100644
--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
@@ -4597,6 +4597,65 @@ void drm_dp_mst_atomic_wait_for_dependencies(struct 
drm_atomic_state *state)
 }
 EXPORT_SYMBOL(drm_dp_mst_atomic_wait_for_dependencies);
 
+/**
+ * drm_dp_mst_root_conn_atomic_check() - Serialize CRTC commits on MST-capable 
connectors operating
+ * in SST mode
+ * @new_conn_state: The new connector state of the &drm_connector
+ * @mgr: The MST topology manager for the &drm_connector
+ *
+ * Since MST uses fake &drm_encoder structs, the generic atomic modesetting 
code isn't able to
+ * serialize non-blocking commits happening on the real DP connector of an MST 
topology switching
+ * into/away from MST mode - as the CRTC on the real DP connector and the 
CRTCs on the connector's
+ * MST topology will never share the same &drm_encoder.
+ *
+ * This function takes care of this serialization issue, by checking a root 
MST connector's atomic
+ * state to determine if it is about to have a modeset - and then pulling in 
the MST topology state
+ * if so, along with adding any relevant CRTCs to 
&drm_dp_mst_topology_state.pending_crtc_mask.
+ *
+ * Drivers implementing MST must call this function from the
+ * &drm_connector_helper_funcs.atomic_check hook of any physical DP 
&drm_connector capable of
+ * driving MST sinks.
+ *
+ * Returns:
+ * 0 on success, negative error code otherwise
+ */
+int drm_dp_mst_root_conn_atomic_check(struct drm_connector_state 
*new_conn_state,
+ struct drm_dp_mst_topology_mgr *mgr)
+{
+   struct drm_atomic_state *state = new_conn_state->state;
+   struct drm_connector_state *old_conn_state =
+   drm_atomic_get_old_connector_state(state, 
new_conn_state->connector);
+   struct drm_crtc_state *crtc_state;
+   struct drm_dp_mst_topology_state *mst_state = NULL;
+
+   if (new_conn_state->crtc) {
+   crtc_state = drm_atomic_get_new_crtc_state(state, 
new_conn_state->crtc);
+   if (crtc_state && drm_atomic_crtc_needs_modeset(crtc_state)) {
+   mst_state = drm_atomic_get_mst_topology_state(state, 
mgr);
+   if (

Re: [PATCH v2 1/3] drm/dp_mst: add passthrough_aux to struct drm_dp_mst_port

[Lyude Paul]

Ah yes of course! Probably should have asked when I gave the r-b :). Also,
just so patchwork actually catches it I will say the magic incantation:

Reviewed-by: Lyude Paul 

Do we want to merge just this patch to drm-misc-next, or do you want to merge
the whole series through there? If you'd rather just merge this through amd's
branch I'm fine with that as well

On Tue, 2022-08-09 at 11:15 -0400, Hamza Mahfooz wrote:
> Hey Lyude,
> 
> On 2022-08-05 17:17, Lyude Paul wrote:
> > lgtm!
> > 
> 
> Any chance you can apply this to drm-misc-next?
> 
> > Reviewed-by: Lyude Paul 
> > 
> > On Fri, 2022-08-05 at 17:13 -0400, Hamza Mahfooz wrote:
> > > Currently, there is no way to identify if DSC pass-through can be
> > > enabled and what aux DSC pass-through requests ought to be sent to. So,
> > > add a variable to struct drm_dp_mst_port that keeps track of the
> > > aforementioned information.
> > > 
> > > Signed-off-by: Hamza Mahfooz 
> > > ---
> > > v2: define DP_DSC_PASSTHROUGH_IS_SUPPORTED
> > > ---
> > >   drivers/gpu/drm/display/drm_dp_mst_topology.c | 4 +++-
> > >   include/drm/display/drm_dp.h  | 1 +
> > >   include/drm/display/drm_dp_mst_helper.h   | 3 +++
> > >   3 files changed, 7 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c 
> > > b/drivers/gpu/drm/display/drm_dp_mst_topology.c
> > > index 67b3b9697da7..71915afd9892 100644
> > > --- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
> > > +++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
> > > @@ -5921,8 +5921,10 @@ struct drm_dp_aux 
> > > *drm_dp_mst_dsc_aux_for_port(struct drm_dp_mst_port *port)
> > >   /* Enpoint decompression with DP-to-DP peer device */
> > >   if ((endpoint_dsc & DP_DSC_DECOMPRESSION_IS_SUPPORTED) 
> > > &&
> > >   (endpoint_fec & DP_FEC_CAPABLE) &&
> > > - (upstream_dsc & 0x2) /* DSC passthrough */)
> > > + (upstream_dsc & DP_DSC_PASSTHROUGH_IS_SUPPORTED)) {
> > > + port->passthrough_aux = &immediate_upstream_port->aux;
> > >   return &port->aux;
> > > + }
> > >   
> > >   /* Virtual DPCD decompression with DP-to-DP peer device 
> > > */
> > >   return &immediate_upstream_port->aux;
> > > diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
> > > index 9e3aff7e68bb..4d0abe4c7ea9 100644
> > > --- a/include/drm/display/drm_dp.h
> > > +++ b/include/drm/display/drm_dp.h
> > > @@ -239,6 +239,7 @@
> > >   
> > >   #define DP_DSC_SUPPORT  0x060   /* DP 1.4 */
> > >   # define DP_DSC_DECOMPRESSION_IS_SUPPORTED  (1 << 0)
> > > +# define DP_DSC_PASSTHROUGH_IS_SUPPORTED(1 << 1)
> > >   
> > >   #define DP_DSC_REV  0x061
> > >   # define DP_DSC_MAJOR_MASK  (0xf << 0)
> > > diff --git a/include/drm/display/drm_dp_mst_helper.h 
> > > b/include/drm/display/drm_dp_mst_helper.h
> > > index 10adec068b7f..4a39c95f8afd 100644
> > > --- a/include/drm/display/drm_dp_mst_helper.h
> > > +++ b/include/drm/display/drm_dp_mst_helper.h
> > > @@ -86,6 +86,8 @@ struct drm_dp_vcpi {
> > >* @next: link to next port on this branch device
> > >* @aux: i2c aux transport to talk to device connected to this port, 
> > > protected
> > >* by &drm_dp_mst_topology_mgr.base.lock.
> > > + * @passthrough_aux: parent aux to which DSC pass-through requests 
> > > should be
> > > + * sent, only set if DSC pass-through is possible.
> > >* @parent: branch device parent of this port
> > >* @vcpi: Virtual Channel Payload info for this port.
> > >* @connector: DRM connector this port is connected to. Protected by
> > > @@ -140,6 +142,7 @@ struct drm_dp_mst_port {
> > >*/
> > >   struct drm_dp_mst_branch *mstb;
> > >   struct drm_dp_aux aux; /* i2c bus for this port? */
> > > + struct drm_dp_aux *passthrough_aux;
> > >   struct drm_dp_mst_branch *parent;
> > >   
> > >   struct drm_dp_vcpi vcpi;
> > 
> 

-- 
Cheers,
 Lyude Paul (she/her)
 Software Engineer at Red Hat

RE: [PATCH] drm/amdkfd: Handle restart of kfd_ioctl_wait_events

[Chen, Xiaogang]

[AMD Official Use Only - General]

This patch is:

Reviewed-and-Tested-by: Xiaogang Chen 

-Original Message-
From: Kuehling, Felix  
Sent: Thursday, August 4, 2022 5:29 PM
To: amd-gfx@lists.freedesktop.org
Cc: Chen, Xiaogang ; Curtis, Nicholas 

Subject: [PATCH] drm/amdkfd: Handle restart of kfd_ioctl_wait_events

When kfd_ioctl_wait_events needs to restart due to a signal, we need to update 
the timeout to account for the time already elapsed. We also need to undo 
auto_reset of events that have signaled already, so that the restarted ioctl 
will be able to count those signals again.

This fixes infinite hangs when kfd_ioctl_wait_events is interrupted by a signal.

Signed-off-by: Felix Kuehling 
---
 drivers/gpu/drm/amd/amdkfd/kfd_chardev.c |  2 +-  
drivers/gpu/drm/amd/amdkfd/kfd_events.c  | 24 
 drivers/gpu/drm/amd/amdkfd/kfd_priv.h|  2 +-
 3 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
index 907f4711abce..664e8b5d82c0 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
@@ -881,7 +881,7 @@ static int kfd_ioctl_wait_events(struct file *filp, struct 
kfd_process *p,
err = kfd_wait_on_events(p, args->num_events,
(void __user *)args->events_ptr,
(args->wait_for_all != 0),
-   args->timeout, &args->wait_result);
+   &args->timeout, &args->wait_result);
 
return err;
 }
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_events.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_events.c
index 3942a56c28bb..83e3ce9f6049 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_events.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_events.c
@@ -894,7 +894,8 @@ static long user_timeout_to_jiffies(uint32_t 
user_timeout_ms)
return msecs_to_jiffies(user_timeout_ms) + 1;  }
 
-static void free_waiters(uint32_t num_events, struct kfd_event_waiter *waiters)
+static void free_waiters(uint32_t num_events, struct kfd_event_waiter *waiters,
+bool undo_auto_reset)
 {
uint32_t i;
 
@@ -903,6 +904,9 @@ static void free_waiters(uint32_t num_events, struct 
kfd_event_waiter *waiters)
spin_lock(&waiters[i].event->lock);
remove_wait_queue(&waiters[i].event->wq,
  &waiters[i].wait);
+   if (undo_auto_reset && waiters[i].activated &&
+   waiters[i].event && waiters[i].event->auto_reset)
+   set_event(waiters[i].event);
spin_unlock(&waiters[i].event->lock);
}
 
@@ -911,7 +915,7 @@ static void free_waiters(uint32_t num_events, struct 
kfd_event_waiter *waiters)
 
 int kfd_wait_on_events(struct kfd_process *p,
   uint32_t num_events, void __user *data,
-  bool all, uint32_t user_timeout_ms,
+  bool all, uint32_t *user_timeout_ms,
   uint32_t *wait_result)
 {
struct kfd_event_data __user *events = @@ -920,7 +924,7 @@ int 
kfd_wait_on_events(struct kfd_process *p,
int ret = 0;
 
struct kfd_event_waiter *event_waiters = NULL;
-   long timeout = user_timeout_to_jiffies(user_timeout_ms);
+   long timeout = user_timeout_to_jiffies(*user_timeout_ms);
 
event_waiters = alloc_event_waiters(num_events);
if (!event_waiters) {
@@ -970,15 +974,11 @@ int kfd_wait_on_events(struct kfd_process *p,
}
 
if (signal_pending(current)) {
-   /*
-* This is wrong when a nonzero, non-infinite timeout
-* is specified. We need to use
-* ERESTARTSYS_RESTARTBLOCK, but struct restart_block
-* contains a union with data for each user and it's
-* in generic kernel code that I don't want to
-* touch yet.
-*/
ret = -ERESTARTSYS;
+   if (*user_timeout_ms != KFD_EVENT_TIMEOUT_IMMEDIATE &&
+   *user_timeout_ms != KFD_EVENT_TIMEOUT_INFINITE)
+   *user_timeout_ms = jiffies_to_msecs(
+   max(0l, timeout-1));
break;
}
 
@@ -1019,7 +1019,7 @@ int kfd_wait_on_events(struct kfd_process *p,
   event_waiters, events);
 
 out_unlock:
-   free_waiters(num_events, event_waiters);
+   free_waiters(num_events, event_waiters, ret == -ERESTARTSYS);
mutex_unlock(&p->event_mutex);
 out:
if (ret)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h 
b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
index d03a3b9c9c5d..bf610e3b683b 100644
--- a/d

Re: [PATCH] Increase tlb flush timeout for sriov

[Deucher, Alexander]

[AMD Official Use Only - General]

Please add these details to the patch description when you respin.

From: amd-gfx  on behalf of Liu, Shaoyun 

Sent: Monday, August 8, 2022 6:30 PM
To: Alex Deucher ; Milinkovic, Dusica 

Cc: amd-gfx@lists.freedesktop.org 
Subject: Re: [PATCH] Increase tlb flush timeout for sriov

As I discussed with Alice ,this change is when multi-vf running compute 
benchmark (Luxmark) at the same time, which involves multiple vf  do the tlb 
invalidation at the same time. They observed kiq timeout after submit the tlb 
invalidate command. Although each vf has the invalidate register set, but from 
hw, the invalidate requests are queue to execute.

Alice, as we discussed, we can use maximum 12*100ms for the timeout , it 
shouldn't be 6000ms. Did you see issues with 1200 ms timeout?

Regards
Shaoyun.liu

From: amd-gfx  on behalf of Alex Deucher 

Sent: August 8, 2022 4:49 PM
To: Milinkovic, Dusica 
Cc: amd-gfx@lists.freedesktop.org 
Subject: Re: [PATCH] Increase tlb flush timeout for sriov

On Wed, Aug 3, 2022 at 5:02 AM Dusica Milinkovic
 wrote:
>

Please include a patch description.  Why do you need a longer timeout?
 What problem does it fix?

> Signed-off-by: Dusica Milinkovic 
> ---
>  drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 6 +-
>  drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c  | 6 +-
>  2 files changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> index 9ae8cdaa033e..6ab7d329916f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> @@ -419,6 +419,7 @@ static int gmc_v10_0_flush_gpu_tlb_pasid(struct 
> amdgpu_device *adev,
> uint32_t seq;
> uint16_t queried_pasid;
> bool ret;
> +   uint32_t sriov_usec_timeout = 600;  /* wait for 12 * 500ms for 
> SRIOV */
> struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
> struct amdgpu_kiq *kiq = &adev->gfx.kiq;
>
> @@ -437,7 +438,10 @@ static int gmc_v10_0_flush_gpu_tlb_pasid(struct 
> amdgpu_device *adev,
>
> amdgpu_ring_commit(ring);
> spin_unlock(&adev->gfx.kiq.ring_lock);
> -   r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout);
> +   if (amdgpu_sriov_vf(adev))
> +   r = amdgpu_fence_wait_polling(ring, seq, 
> sriov_usec_timeout);
> +   else
> +   r = amdgpu_fence_wait_polling(ring, seq, 
> adev->usec_timeout);

What about something like this?
u32 usec_timeout = amdgpu_sriov_vf(adev) ? 600 :
adev->usec_timeout;  /* wait for 12 * 500ms for SRIOV */
...
r = amdgpu_fence_wait_polling(ring, seq, usec_timeout);


> if (r < 1) {
> dev_err(adev->dev, "wait for kiq fence error: 
> %ld.\n", r);
> return -ETIME;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index 22761a3bb818..941a6b52fa72 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -896,6 +896,7 @@ static int gmc_v9_0_flush_gpu_tlb_pasid(struct 
> amdgpu_device *adev,
> uint32_t seq;
> uint16_t queried_pasid;
> bool ret;
> +   uint32_t sriov_usec_timeout = 600;  /* wait for 12 * 500ms for 
> SRIOV */
> struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
> struct amdgpu_kiq *kiq = &adev->gfx.kiq;
>
> @@ -935,7 +936,10 @@ static int gmc_v9_0_flush_gpu_tlb_pasid(struct 
> amdgpu_device *adev,
>
> amdgpu_ring_commit(ring);
> spin_unlock(&adev->gfx.kiq.ring_lock);
> -   r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout);
> +   if (amdgpu_sriov_vf(adev))
> +   r = amdgpu_fence_wait_polling(ring, seq, 
> sriov_usec_timeout);
> +   else
> +   r = amdgpu_fence_wait_polling(ring, seq, 
> adev->usec_timeout);

Same comment here.

Alex

> if (r < 1) {
> dev_err(adev->dev, "wait for kiq fence error: 
> %ld.\n", r);
> up_read(&adev->reset_domain->sem);
> --
> 2.25.1
>

Re: [PATCH 0/4] Fix S3 and S4 issues related to fbdev

[Limonciello, Mario]

On 8/9/2022 10:50, Alex Deucher wrote:

On Tue, Aug 9, 2022 at 11:10 AM Mario Limonciello
 wrote:


Moving to the generic fbdev helper introduced a regression in S4 support
on Hawaii PRO graphics cards.  A workaround commit was introduced to
avoid this S4 regression until the root cause could be found, but that
workaround commit introduced a completely separate regression on S3 on
a WX3200.

This series reverts all the code to move to generic fbdev helpers to
fix both issues.


I'm not opposed to reverting this, but I fear we'll never get rid of
this old fbdev code.  


Yeah, makes sense to me.


What about just applying the workaround for
hawaii as per the attached patch?  There is always the concern that
this will lead to more workarounds, but I'd rather avoid touching the
older asic support as much as possible.


Yup that fixes S3 for me on the WX3200 (tested on top of 040370564b68) 
and I would expect keeps the W/A for S4 on the Hawaii one working 
effectively.


Reviewed-and-Tested-by: Mario Limonciello 



Alex



Mario Limonciello (4):
   Revert "drm/amdgpu/display: disable prefer_shadow for generic fb
 helpers"
   Revert "drm/amdgpu: keep fbdev buffers pinned during suspend"
   Revert "drm/amdgpu: drop amdgpu_display_gem_fb_init()"
   Revert "drm/amdgpu: use generic fb helpers instead of setting up AMD
 own's."

  drivers/gpu/drm/amd/amdgpu/Makefile   |   2 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c|  12 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_display.c   |  43 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c   |  13 -
  drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c| 388 ++
  drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c   |  30 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h  |  25 ++
  drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c  |   3 +-
  drivers/gpu/drm/amd/amdgpu/dce_v10_0.c|   3 +-
  drivers/gpu/drm/amd/amdgpu/dce_v11_0.c|   3 +-
  drivers/gpu/drm/amd/amdgpu/dce_v6_0.c |   3 +-
  drivers/gpu/drm/amd/amdgpu/dce_v8_0.c |   3 +-
  .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |   3 +-
  13 files changed, 457 insertions(+), 74 deletions(-)
  create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c

--
2.34.1

Re: [PATCH v5 00/33] DYNDBG: opt-in class'd debug for modules, use in drm.

[Daniel Vetter]

[Catching up on mails]

Did you see the feedback form Steven from tracing side of things? Does
this version have that taken into account already?

I think once we have that and acks from dyndbg maintainers then I think we
should just land this and polish from there? Maybe some acks from drm
drivrer folks (cros people where once interested), but otherwise I'm a bit
afraid this might be stuck in limbo too much for too long and we just need
to get going :-/
-Daniel


On Fri, Aug 05, 2022 at 03:53:22PM -0600, Jim Cromie wrote:
> Hi Jason, Greg, DRM-folk,
> 
> heres V5. Diffs vs V4:
> 
>   1st 9 have Jason's Ack
>   10 is new: simple var cleanup
>   11 new struct, to contain future addins. touches kernel/module/
> 
>   dyndbg-param callbacks moved to last (of dyndbg patches)
>   they're where the uncertainty is,
>   and the bulk of the API addition (class keyword is small)
> 
>   patches between the move are the guts of the "class foo" feature.
>   exposure of feature is only via >control, until sysfs parts added
>   
>   DRM chunk:
>   included here to see how patchwork's merge & test proceeds.
>   categories -> classes re-work is unchanged - feels pretty solid.
>   nouveau & LEVEL made some progress, still WIP.
> 
>   I left out tracefs bits for now.
> 
> UNCERTAINTIES / RFC:
> 
> 1st is my "sharing" technique, across DRM's multi modules.  Its
> literally duplicated decls, by each participating module, each adding
> static data in its own special section.  I didn't try at all to shrink
> or unify this any further.  There might be a perfect place to add a
> single decl, but that quest will require a pony.
> 
> Sharing by class-names lacks the compiler support that varnames get;
> "incomplete" enables will probably happen if one of the declarations
> miss-spells one of the classnames.
> 
> That said, see the how-to below: stringifying va-args in the macro
> would allow direct use of the enum-consts, and cc will insist that
> those consts are defined, eliminating part of the un-support.
> 
> I could split the _BITS,_NUM handling out from _NAMES (ie split
> drm.debug style patch); theres no user-demand for the _NAMES feature
> ATM, and theres probably some legit API-bikeshedding to do.
> 
> PATCHSET DESCRIPTION
> 
> This patchset adds 'typed' "class FOO" support to dynamic-debug, where
> 'typed' means either DISJOINT_BITS, like drm_dbg(DRM_UT_CORE,..), or
> LEVEL_NUM (like nouveau debug-levels).  Use it in DRM modules: core,
> helpers, and in drivers i915, amdgpu, nouveau.
> 
> If a module is using class'd prdbgs (pr_debug_class, dev_dbg_class, or
> adapted drm_dbg_) or similar in its code, it can "opt in" to
> allow dyndbg to manipulate those class'd prdebugs, by declaring in a
> c-file:
> 
>  DECLARE_DYNDBG_CLASSMAP(drm_debug_classes,
>   DD_CLASS_TYPE_DISJOINT_BITS, 0,
> "DRM_UT_CORE",
> "DRM_UT_DRIVER",
> "DRM_UT_KMS",
> "DRM_UT_PRIME",
> "DRM_UT_ATOMIC",
> "DRM_UT_VBL",
> "DRM_UT_STATE",
> "DRM_UT_LEASE",
> "DRM_UT_DP",
> "DRM_UT_DRMRES");
>   // how-to stringify __va_args inside the macro ?
> 
> By doing this, a module tells dyndbg that it:
> 
>- is using class-ids [0..N] in prdbg callsites
>  ( 0..N == DRM_UT_CORE..DRM_UT_DRMRES )
>- wants to refer to them by class-names [0..N]
>- is mapping those names to those class-ids
>- expects users to enable them via >control or >parameter/knob
> 
> Then, a user can enable the prdbgs by their class:
> 
>:#> echo class DRM_UT_KMS +p > /proc/dynamic_debug/control
> 
> And with another 3-line bitmap param decl/init, wrapping the
> drm_debug_classes var in a module-param-cb:
> 
>:#> echo 0x1 > /sys/module/drm/parameters/debug
> 
> and optionally using classnames:
> 
>:#> echo +DRM_UT_CORE,-DRM_UT_KMS \
>   > /sys/module/drm/parameters/debug_cats
> 
> DYNAMIC_DEBUG gets:
> 
> struct _ddebug gets a new .class_id:5 field, big enough to represent
> drm_debug_category (after squeezing).  It defaults to 31 for all
> existing prdbgs.  class_id also supports verbose uses.
> 
> classmaps (as declared by macro above) are in their own linker
> section, are loaded by kernel/module, and handled by add_module,
> which attaches classmaps to their module's ddebug table.
>  
> ddebug_change() handles a class FOO query by validating that FOO is
> known by each module in the loop.  The query is skipped unless the
> module knows FOO, so no changes are possible w/o a good classname.
> 
> Without class FOO in a query/command, only ids=31 can be changed by
> that query.  This protects all class'd prdbgs from changes by legacy
> class-less user queries.
> 
> With this support, the module opt-in approach means that:
> 
>- modules declare classnames they like, meaningful names:

Re: [PATCH 0/4] Fix S3 and S4 issues related to fbdev

[Alex Deucher]

On Tue, Aug 9, 2022 at 11:10 AM Mario Limonciello
 wrote:
>
> Moving to the generic fbdev helper introduced a regression in S4 support
> on Hawaii PRO graphics cards.  A workaround commit was introduced to
> avoid this S4 regression until the root cause could be found, but that
> workaround commit introduced a completely separate regression on S3 on
> a WX3200.
>
> This series reverts all the code to move to generic fbdev helpers to
> fix both issues.

I'm not opposed to reverting this, but I fear we'll never get rid of
this old fbdev code.  What about just applying the workaround for
hawaii as per the attached patch?  There is always the concern that
this will lead to more workarounds, but I'd rather avoid touching the
older asic support as much as possible.

Alex

>
> Mario Limonciello (4):
>   Revert "drm/amdgpu/display: disable prefer_shadow for generic fb
> helpers"
>   Revert "drm/amdgpu: keep fbdev buffers pinned during suspend"
>   Revert "drm/amdgpu: drop amdgpu_display_gem_fb_init()"
>   Revert "drm/amdgpu: use generic fb helpers instead of setting up AMD
> own's."
>
>  drivers/gpu/drm/amd/amdgpu/Makefile   |   2 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c|  12 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_display.c   |  43 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c   |  13 -
>  drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c| 388 ++
>  drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c   |  30 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h  |  25 ++
>  drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c  |   3 +-
>  drivers/gpu/drm/amd/amdgpu/dce_v10_0.c|   3 +-
>  drivers/gpu/drm/amd/amdgpu/dce_v11_0.c|   3 +-
>  drivers/gpu/drm/amd/amdgpu/dce_v6_0.c |   3 +-
>  drivers/gpu/drm/amd/amdgpu/dce_v8_0.c |   3 +-
>  .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |   3 +-
>  13 files changed, 457 insertions(+), 74 deletions(-)
>  create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
>
> --
> 2.34.1
>
From 9e04759a432adde38737fbb9da3b57db25969e18 Mon Sep 17 00:00:00 2001
From: Alex Deucher 
Date: Tue, 9 Aug 2022 11:44:05 -0400
Subject: [PATCH] drm/amdgpu: Only disable prefer_shadow on hawaii

We changed it for all asics due to a hibernation regression
on hawaii, but the workaround breaks suspend on a polaris12.
Just disable it for hawaii.

Link: https://bugzilla.kernel.org/show_bug.cgi?id=216119
Fixes: 3a4b1cc28fbd ("drm/amdgpu/display: disable prefer_shadow for generic fb helpers")
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c  | 3 +--
 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c| 3 +--
 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c| 3 +--
 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 3 +--
 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 7 +--
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 7 +--
 6 files changed, 14 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
index 327166f2f35c..d68233dc772c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
@@ -496,8 +496,7 @@ static int amdgpu_vkms_sw_init(void *handle)
 	adev_to_drm(adev)->mode_config.max_height = YRES_MAX;
 
 	adev_to_drm(adev)->mode_config.preferred_depth = 24;
-	/* disable prefer shadow for now due to hibernation issues */
-	adev_to_drm(adev)->mode_config.prefer_shadow = 0;
+	adev_to_drm(adev)->mode_config.prefer_shadow = 1;
 
 	adev_to_drm(adev)->mode_config.fb_base = adev->gmc.aper_base;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index 2e90cd828895..bdd3aef6d071 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -2796,8 +2796,7 @@ static int dce_v10_0_sw_init(void *handle)
 	adev_to_drm(adev)->mode_config.max_height = 16384;
 
 	adev_to_drm(adev)->mode_config.preferred_depth = 24;
-	/* disable prefer shadow for now due to hibernation issues */
-	adev_to_drm(adev)->mode_config.prefer_shadow = 0;
+	adev_to_drm(adev)->mode_config.prefer_shadow = 1;
 
 	adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index b32acbaad293..328d9e16668a 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -2914,8 +2914,7 @@ static int dce_v11_0_sw_init(void *handle)
 	adev_to_drm(adev)->mode_config.max_height = 16384;
 
 	adev_to_drm(adev)->mode_config.preferred_depth = 24;
-	/* disable prefer shadow for now due to hibernation issues */
-	adev_to_drm(adev)->mode_config.prefer_shadow = 0;
+	adev_to_drm(adev)->mode_config.prefer_shadow = 1;
 
 	adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
index db3f55d85d5c..d101ceb8c2a4 100644
--

Re: [PATCH v2 1/3] drm/dp_mst: add passthrough_aux to struct drm_dp_mst_port

[Hamza Mahfooz]

Hey Lyude,

On 2022-08-05 17:17, Lyude Paul wrote:

lgtm!



Any chance you can apply this to drm-misc-next?


Reviewed-by: Lyude Paul 

On Fri, 2022-08-05 at 17:13 -0400, Hamza Mahfooz wrote:

Currently, there is no way to identify if DSC pass-through can be
enabled and what aux DSC pass-through requests ought to be sent to. So,
add a variable to struct drm_dp_mst_port that keeps track of the
aforementioned information.

Signed-off-by: Hamza Mahfooz 
---
v2: define DP_DSC_PASSTHROUGH_IS_SUPPORTED
---
  drivers/gpu/drm/display/drm_dp_mst_topology.c | 4 +++-
  include/drm/display/drm_dp.h  | 1 +
  include/drm/display/drm_dp_mst_helper.h   | 3 +++
  3 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c 
b/drivers/gpu/drm/display/drm_dp_mst_topology.c
index 67b3b9697da7..71915afd9892 100644
--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
@@ -5921,8 +5921,10 @@ struct drm_dp_aux *drm_dp_mst_dsc_aux_for_port(struct 
drm_dp_mst_port *port)
/* Enpoint decompression with DP-to-DP peer device */
if ((endpoint_dsc & DP_DSC_DECOMPRESSION_IS_SUPPORTED) &&
(endpoint_fec & DP_FEC_CAPABLE) &&
-   (upstream_dsc & 0x2) /* DSC passthrough */)
+   (upstream_dsc & DP_DSC_PASSTHROUGH_IS_SUPPORTED)) {
+   port->passthrough_aux = &immediate_upstream_port->aux;
return &port->aux;
+   }
  
  		/* Virtual DPCD decompression with DP-to-DP peer device */

return &immediate_upstream_port->aux;
diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index 9e3aff7e68bb..4d0abe4c7ea9 100644
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -239,6 +239,7 @@
  
  #define DP_DSC_SUPPORT  0x060   /* DP 1.4 */

  # define DP_DSC_DECOMPRESSION_IS_SUPPORTED  (1 << 0)
+# define DP_DSC_PASSTHROUGH_IS_SUPPORTED(1 << 1)
  
  #define DP_DSC_REV  0x061

  # define DP_DSC_MAJOR_MASK  (0xf << 0)
diff --git a/include/drm/display/drm_dp_mst_helper.h 
b/include/drm/display/drm_dp_mst_helper.h
index 10adec068b7f..4a39c95f8afd 100644
--- a/include/drm/display/drm_dp_mst_helper.h
+++ b/include/drm/display/drm_dp_mst_helper.h
@@ -86,6 +86,8 @@ struct drm_dp_vcpi {
   * @next: link to next port on this branch device
   * @aux: i2c aux transport to talk to device connected to this port, protected
   * by &drm_dp_mst_topology_mgr.base.lock.
+ * @passthrough_aux: parent aux to which DSC pass-through requests should be
+ * sent, only set if DSC pass-through is possible.
   * @parent: branch device parent of this port
   * @vcpi: Virtual Channel Payload info for this port.
   * @connector: DRM connector this port is connected to. Protected by
@@ -140,6 +142,7 @@ struct drm_dp_mst_port {
 */
struct drm_dp_mst_branch *mstb;
struct drm_dp_aux aux; /* i2c bus for this port? */
+   struct drm_dp_aux *passthrough_aux;
struct drm_dp_mst_branch *parent;
  
  	struct drm_dp_vcpi vcpi;




--
Hamza

[PATCH 3/4] Revert "drm/amdgpu: drop amdgpu_display_gem_fb_init()"

[Mario Limonciello]

This reverts commit 60da2f7440f22dba48944602c2a0373068f13880.

Link: https://bugzilla.kernel.org/show_bug.cgi?id=216119
Fixes: 087451f372bf ("drm/amdgpu: use generic fb helpers instead of setting up 
AMD own's.")
Signed-off-by: Mario Limonciello 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 25 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h|  5 +
 2 files changed, 30 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index 97fff4727724..92281e57f3ac 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -1075,6 +1075,31 @@ static int amdgpu_display_get_fb_info(const struct 
amdgpu_framebuffer *amdgpu_fb
return r;
 }
 
+int amdgpu_display_gem_fb_init(struct drm_device *dev,
+  struct amdgpu_framebuffer *rfb,
+  const struct drm_mode_fb_cmd2 *mode_cmd,
+  struct drm_gem_object *obj)
+{
+   int ret;
+
+   rfb->base.obj[0] = obj;
+   drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd);
+
+   ret = amdgpu_display_framebuffer_init(dev, rfb, mode_cmd, obj);
+   if (ret)
+   goto err;
+
+   ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs);
+   if (ret)
+   goto err;
+
+   return 0;
+err:
+   drm_dbg_kms(dev, "Failed to init gem fb: %d\n", ret);
+   rfb->base.obj[0] = NULL;
+   return ret;
+}
+
 static int amdgpu_display_gem_fb_verify_and_init(struct drm_device *dev,
 struct amdgpu_framebuffer *rfb,
 struct drm_file *file_priv,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
index dbe2904e015b..fb120abeec96 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
@@ -588,6 +588,11 @@ int amdgpu_display_get_crtc_scanoutpos(struct drm_device 
*dev,
int *hpos, ktime_t *stime, ktime_t *etime,
const struct drm_display_mode *mode);
 
+int amdgpu_display_gem_fb_init(struct drm_device *dev,
+  struct amdgpu_framebuffer *rfb,
+  const struct drm_mode_fb_cmd2 *mode_cmd,
+  struct drm_gem_object *obj);
+
 int amdgpufb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
 
 void amdgpu_enc_destroy(struct drm_encoder *encoder);
-- 
2.34.1

[PATCH 4/4] Revert "drm/amdgpu: use generic fb helpers instead of setting up AMD own's."

[Mario Limonciello]

Although preferable to use the generic fb helpers there is an underlying issue
that causes problems for S4 that isn't yet identified.  As the workaround for
the S4 issue caused other problems for S3, revert the change to generic fb 
helpers.

If/when that underlying issue is identified switching back to generic fb helpers
can be brought back in for amdgpu.

Link: https://bugzilla.kernel.org/show_bug.cgi?id=216119
Fixes: 087451f372bf ("drm/amdgpu: use generic fb helpers instead of setting up 
AMD own's.")
Signed-off-by: Mario Limonciello 
---
 drivers/gpu/drm/amd/amdgpu/Makefile |   2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c  |  12 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_display.c |  11 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c |  13 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c  | 388 
 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c |  30 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h|  20 +
 7 files changed, 426 insertions(+), 50 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c

diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile 
b/drivers/gpu/drm/amd/amdgpu/Makefile
index 4bde7ff55f8a..224d2dca2b7b 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -45,7 +45,7 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
amdgpu_atombios.o atombios_crtc.o amdgpu_connectors.o \
atom.o amdgpu_fence.o amdgpu_ttm.o amdgpu_object.o amdgpu_gart.o \
amdgpu_encoders.o amdgpu_display.o amdgpu_i2c.o \
-   amdgpu_gem.o amdgpu_ring.o \
+   amdgpu_fb.o amdgpu_gem.o amdgpu_ring.o \
amdgpu_cs.o amdgpu_bios.o amdgpu_benchmark.o \
atombios_dp.o amdgpu_afmt.o amdgpu_trace_points.o \
atombios_encoders.o amdgpu_sa.o atombios_i2c.o \
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index c84fdef0ac45..a14e2c98d324 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3795,6 +3795,8 @@ int amdgpu_device_init(struct amdgpu_device *adev,
/* Get a log2 for easy divisions. */
adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));
 
+   amdgpu_fbdev_init(adev);
+
r = amdgpu_pm_sysfs_init(adev);
if (r) {
adev->pm_sysfs_en = false;
@@ -3956,6 +3958,8 @@ void amdgpu_device_fini_hw(struct amdgpu_device *adev)
/* disable ras feature must before hw fini */
amdgpu_ras_pre_fini(adev);
 
+   amdgpu_fbdev_fini(adev);
+
amdgpu_device_ip_fini_early(adev);
 
amdgpu_irq_fini_hw(adev);
@@ -4066,7 +4070,7 @@ int amdgpu_device_suspend(struct drm_device *dev, bool 
fbcon)
drm_kms_helper_poll_disable(dev);
 
if (fbcon)
-   
drm_fb_helper_set_suspend_unlocked(adev_to_drm(adev)->fb_helper, true);
+   amdgpu_fbdev_set_suspend(adev, 1);
 
cancel_delayed_work_sync(&adev->delayed_init_work);
 
@@ -4138,7 +4142,7 @@ int amdgpu_device_resume(struct drm_device *dev, bool 
fbcon)
flush_delayed_work(&adev->delayed_init_work);
 
if (fbcon)
-   
drm_fb_helper_set_suspend_unlocked(adev_to_drm(adev)->fb_helper, false);
+   amdgpu_fbdev_set_suspend(adev, 0);
 
drm_kms_helper_poll_enable(dev);
 
@@ -4856,7 +4860,7 @@ int amdgpu_do_asic_reset(struct list_head 
*device_list_handle,
if (r)
goto out;
 
-   
drm_fb_helper_set_suspend_unlocked(adev_to_drm(tmp_adev)->fb_helper, false);
+   amdgpu_fbdev_set_suspend(tmp_adev, 0);
 
/*
 * The GPU enters bad state once faulty pages
@@ -5203,7 +5207,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
 */
amdgpu_unregister_gpu_instance(tmp_adev);
 
-   
drm_fb_helper_set_suspend_unlocked(adev_to_drm(tmp_adev)->fb_helper, true);
+   amdgpu_fbdev_set_suspend(tmp_adev, 1);
 
/* disable ras on ALL IPs */
if (!need_emergency_restart &&
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index 92281e57f3ac..eea6f8e34850 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -1619,10 +1619,13 @@ int amdgpu_display_suspend_helper(struct amdgpu_device 
*adev)
continue;
}
robj = gem_to_amdgpu_bo(fb->obj[0]);
-   r = amdgpu_bo_reserve(robj, true);
-   if (r == 0) {
-   amdgpu_bo_unpin(robj);
-   amdgpu_bo_unreserve(robj);
+   /* don't unpin kernel fb objects */
+   if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
+   r = amdgpu_bo_reserve(robj, true);
+   

[PATCH 0/4] Fix S3 and S4 issues related to fbdev

[Mario Limonciello]

Moving to the generic fbdev helper introduced a regression in S4 support
on Hawaii PRO graphics cards.  A workaround commit was introduced to
avoid this S4 regression until the root cause could be found, but that
workaround commit introduced a completely separate regression on S3 on
a WX3200.

This series reverts all the code to move to generic fbdev helpers to
fix both issues.

Mario Limonciello (4):
  Revert "drm/amdgpu/display: disable prefer_shadow for generic fb
helpers"
  Revert "drm/amdgpu: keep fbdev buffers pinned during suspend"
  Revert "drm/amdgpu: drop amdgpu_display_gem_fb_init()"
  Revert "drm/amdgpu: use generic fb helpers instead of setting up AMD
own's."

 drivers/gpu/drm/amd/amdgpu/Makefile   |   2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c|  12 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_display.c   |  43 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c   |  13 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c| 388 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c   |  30 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h  |  25 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c  |   3 +-
 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c|   3 +-
 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c|   3 +-
 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c |   3 +-
 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c |   3 +-
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |   3 +-
 13 files changed, 457 insertions(+), 74 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c

-- 
2.34.1

[PATCH 2/4] Revert "drm/amdgpu: keep fbdev buffers pinned during suspend"

[Mario Limonciello]

This reverts commit da427a501e9b5e2cac8c8042df12eb203726903c.

Link: https://bugzilla.kernel.org/show_bug.cgi?id=216119
Fixes: 087451f372bf ("drm/amdgpu: use generic fb helpers instead of setting up 
AMD own's.")
Signed-off-by: Mario Limonciello 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 25 -
 1 file changed, 4 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index c20922a5af9f..97fff4727724 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -1559,21 +1559,6 @@ bool amdgpu_crtc_get_scanout_position(struct drm_crtc 
*crtc,
  stime, etime, mode);
 }
 
-static bool
-amdgpu_display_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj)
-{
-   struct drm_device *dev = adev_to_drm(adev);
-   struct drm_fb_helper *fb_helper = dev->fb_helper;
-
-   if (!fb_helper || !fb_helper->buffer)
-   return false;
-
-   if (gem_to_amdgpu_bo(fb_helper->buffer->gem) != robj)
-   return false;
-
-   return true;
-}
-
 int amdgpu_display_suspend_helper(struct amdgpu_device *adev)
 {
struct drm_device *dev = adev_to_drm(adev);
@@ -1609,12 +1594,10 @@ int amdgpu_display_suspend_helper(struct amdgpu_device 
*adev)
continue;
}
robj = gem_to_amdgpu_bo(fb->obj[0]);
-   if (!amdgpu_display_robj_is_fb(adev, robj)) {
-   r = amdgpu_bo_reserve(robj, true);
-   if (r == 0) {
-   amdgpu_bo_unpin(robj);
-   amdgpu_bo_unreserve(robj);
-   }
+   r = amdgpu_bo_reserve(robj, true);
+   if (r == 0) {
+   amdgpu_bo_unpin(robj);
+   amdgpu_bo_unreserve(robj);
}
}
return 0;
-- 
2.34.1

[PATCH 1/4] Revert "drm/amdgpu/display: disable prefer_shadow for generic fb helpers"

[Mario Limonciello]

Switching to the generic fb helpers caused a regression for S4, but the
workaround for this regression on S4 caused another regression for S3 on
a WX3200.

Link: https://bugzilla.kernel.org/show_bug.cgi?id=216119
Fixes: 3a4b1cc28fbd ("drm/amdgpu/display: disable prefer_shadow for generic fb 
helpers")
Signed-off-by: Mario Limonciello 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c  | 3 +--
 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c| 3 +--
 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c| 3 +--
 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 3 +--
 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 3 +--
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +--
 6 files changed, 6 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
index 108e8e8a1a36..576849e95296 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
@@ -496,8 +496,7 @@ static int amdgpu_vkms_sw_init(void *handle)
adev_to_drm(adev)->mode_config.max_height = YRES_MAX;
 
adev_to_drm(adev)->mode_config.preferred_depth = 24;
-   /* disable prefer shadow for now due to hibernation issues */
-   adev_to_drm(adev)->mode_config.prefer_shadow = 0;
+   adev_to_drm(adev)->mode_config.prefer_shadow = 1;
 
adev_to_drm(adev)->mode_config.fb_base = adev->gmc.aper_base;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index 9c964cd3b5d4..288fce7dc0ed 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -2796,8 +2796,7 @@ static int dce_v10_0_sw_init(void *handle)
adev_to_drm(adev)->mode_config.max_height = 16384;
 
adev_to_drm(adev)->mode_config.preferred_depth = 24;
-   /* disable prefer shadow for now due to hibernation issues */
-   adev_to_drm(adev)->mode_config.prefer_shadow = 0;
+   adev_to_drm(adev)->mode_config.prefer_shadow = 1;
 
adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 
b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index e0ad9f27dc3f..cbe5250b31cb 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -2914,8 +2914,7 @@ static int dce_v11_0_sw_init(void *handle)
adev_to_drm(adev)->mode_config.max_height = 16384;
 
adev_to_drm(adev)->mode_config.preferred_depth = 24;
-   /* disable prefer shadow for now due to hibernation issues */
-   adev_to_drm(adev)->mode_config.prefer_shadow = 0;
+   adev_to_drm(adev)->mode_config.prefer_shadow = 1;
 
adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
index 77f5e998a120..b1c44fab074f 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
@@ -2673,8 +2673,7 @@ static int dce_v6_0_sw_init(void *handle)
adev_to_drm(adev)->mode_config.max_width = 16384;
adev_to_drm(adev)->mode_config.max_height = 16384;
adev_to_drm(adev)->mode_config.preferred_depth = 24;
-   /* disable prefer shadow for now due to hibernation issues */
-   adev_to_drm(adev)->mode_config.prefer_shadow = 0;
+   adev_to_drm(adev)->mode_config.prefer_shadow = 1;
adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true;
adev_to_drm(adev)->mode_config.fb_base = adev->gmc.aper_base;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
index 802e5c753271..572b9fa7298a 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
@@ -2693,8 +2693,7 @@ static int dce_v8_0_sw_init(void *handle)
adev_to_drm(adev)->mode_config.max_height = 16384;
 
adev_to_drm(adev)->mode_config.preferred_depth = 24;
-   /* disable prefer shadow for now due to hibernation issues */
-   adev_to_drm(adev)->mode_config.prefer_shadow = 0;
+   adev_to_drm(adev)->mode_config.prefer_shadow = 1;
 
adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true;
 
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index ddcb7845f642..ee0cd2f279f2 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -3823,8 +3823,7 @@ static int amdgpu_dm_mode_config_init(struct 
amdgpu_device *adev)
adev_to_drm(adev)->mode_config.max_height = 16384;
 
adev_to_drm(adev)->mode_config.preferred_depth = 24;
-   /* disable prefer shadow for now due to hibernation issues */
-   adev_to_drm(adev)->mode_config.prefer_shadow = 0;
+   adev_to_drm(adev)->mode_config.prefer_shadow = 1;
/* indicates support for immediate flip */
adev_to_drm(adev)->mode_config.a

Re: [PATCH] drivers:gpu:drm:amd:amdgpu:amdgpu_cs.c:fix a potential use-after-free

[Christian König]

Am 28.07.22 um 14:12 schrieb Wentao_Liang:

in line 1535, "dma_fence_put(fence);" drop the reference to fence and may
cause fence to be released. However, fence is used subsequently in line
1542 "fence->error". This may result in an use-after-free bug.

It can be fixed by recording fence->error in a variable before dropping
the reference to fence and referencing it after dropping.

The bug has been confirmed by Christian König on 2021-08-16. Now, I
resend this patch with my real name. I hope the patch can be updated
in a near future.


The subject line should be something like "drm/amdgpu: fix potential use 
after free".




Signed-off-by: Wentao_Liang 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 7 ---
  1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index b28af04b0c3e..1d675a5838f2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -1518,7 +1518,7 @@ static int amdgpu_cs_wait_all_fences(struct amdgpu_device 
*adev,
 struct drm_amdgpu_fence *fences)
  {
uint32_t fence_count = wait->in.fence_count;
-   unsigned int i;
+   unsigned int i, error;



long r = 1;
  
  	for (i = 0; i < fence_count; i++) {

@@ -1533,14 +1533,15 @@ static int amdgpu_cs_wait_all_fences(struct 
amdgpu_device *adev,
  
  		r = dma_fence_wait_timeout(fence, true, timeout);

dma_fence_put(fence);
+   error = fence->error;


That's still the wrong order, you need to get the fence error before 
dropping the reference.


Christian.


if (r < 0)
return r;
  
  		if (r == 0)

break;
  
-		if (fence->error)

-   return fence->error;
+   if (error)
+   return error;
}
  
  	memset(wait, 0, sizeof(*wait));

Re: [PATCH v2 1/2] drm/amdgpu: enable GFX Power Gating for GC IP v11.0.1

[Alex Deucher]

Series is:
Reviewed-by: Alex Deucher 

On Mon, Aug 8, 2022 at 11:20 PM Tim Huang  wrote:
>
> Enable GFX Power Gating control for GC IP v11.0.1.
>
> Signed-off-by: Tim Huang 
> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 38 ++
>  1 file changed, 38 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> index e03618803a1c..158d87e6805d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> @@ -53,6 +53,7 @@
>  #define GFX11_MEC_HPD_SIZE 2048
>
>  #define RLCG_UCODE_LOADING_START_ADDRESS   0x2000L
> +#define RLC_PG_DELAY_3_DEFAULT_GC_11_0_1   0x1388
>
>  #define regCGTT_WD_CLK_CTRL0x5086
>  #define regCGTT_WD_CLK_CTRL_BASE_IDX   1
> @@ -5279,6 +5280,38 @@ static const struct amdgpu_rlc_funcs 
> gfx_v11_0_rlc_funcs = {
> .update_spm_vmid = gfx_v11_0_update_spm_vmid,
>  };
>
> +static void gfx_v11_cntl_power_gating(struct amdgpu_device *adev, bool 
> enable)
> +{
> +   u32 data = RREG32_SOC15(GC, 0, regRLC_PG_CNTL);
> +
> +   if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
> +   data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
> +   else
> +   data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
> +
> +   WREG32_SOC15(GC, 0, regRLC_PG_CNTL, data);
> +
> +   // Program RLC_PG_DELAY3 for CGPG hysteresis
> +   if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
> +   switch (adev->ip_versions[GC_HWIP][0]) {
> +   case IP_VERSION(11, 0, 1):
> +   WREG32_SOC15(GC, 0, regRLC_PG_DELAY_3, 
> RLC_PG_DELAY_3_DEFAULT_GC_11_0_1);
> +   break;
> +   default:
> +   break;
> +   }
> +   }
> +}
> +
> +static void gfx_v11_cntl_pg(struct amdgpu_device *adev, bool enable)
> +{
> +   amdgpu_gfx_rlc_enter_safe_mode(adev);
> +
> +   gfx_v11_cntl_power_gating(adev, enable);
> +
> +   amdgpu_gfx_rlc_exit_safe_mode(adev);
> +}
> +
>  static int gfx_v11_0_set_powergating_state(void *handle,
>enum amd_powergating_state state)
>  {
> @@ -5293,6 +5326,11 @@ static int gfx_v11_0_set_powergating_state(void 
> *handle,
> case IP_VERSION(11, 0, 2):
> amdgpu_gfx_off_ctrl(adev, enable);
> break;
> +   case IP_VERSION(11, 0, 1):
> +   gfx_v11_cntl_pg(adev, enable);
> +   /* TODO: Enable this when GFXOFF is ready */
> +   // amdgpu_gfx_off_ctrl(adev, enable);
> +   break;
> default:
> break;
> }
> --
> 2.25.1
>

Re: [PATCH v2] drm/amd/display: set panel orientation before drm_dev_register

[Hans de Goede]

Hi,

On 8/8/22 20:53, Melissa Wen wrote:
> On 08/04, Melissa Wen wrote:
>> To set the panel orientation property with quirk, we need the mode size
>> provided by EDID. This info is available after EDID is read by 
>> dc_link_detect()
>> and updated by amdgpu_dm_update_connector_after_detect(). The detection
>> happens at driver load in amdgpu_dm_initialize_drm_device() and,
>> therefore, we can get modes and set panel orientation before
>> drm_dev_register() to avoid DRM warns on creating the connector property
>> after device registration:
> 
> + Simon, Hans and Sean

Thanks, the patch looks good to me:

Acked-by: Hans de Goede 

Regards,

Hans

> 
>>
>> [2.563969] [ cut here ]
>> [2.563971] WARNING: CPU: 6 PID: 325 at 
>> drivers/gpu/drm/drm_mode_object.c:45 drm_mode_object_add+0x72/0x80 [drm]
>> [2.563997] Modules linked in: btusb btrtl btbcm btintel btmtk bluetooth 
>> rfkill ecdh_generic ecc usbhid crc16 amdgpu(+) drm_ttm_helper ttm agpgart 
>> gpu_sched i2c_algo_bit drm_display_helper drm_kms_helper syscopyarea 
>> sysfillrect sysimgblt fb_sys_fops drm serio_raw sdhci_pci atkbd libps2 cqhci 
>> vivaldi_fmap ccp sdhci i8042 crct10dif_pclmul crc32_pclmul hid_multitouch 
>> ghash_clmulni_intel aesni_intel crypto_simd cryptd wdat_wdt mmc_core cec 
>> xhci_pci sp5100_tco rng_core xhci_pci_renesas serio 8250_dw i2c_hid_acpi 
>> i2c_hid btrfs blake2b_generic libcrc32c crc32c_generic crc32c_intel xor 
>> raid6_pq dm_mirror dm_region_hash dm_log dm_mod pkcs8_key_parser crypto_user
>> [2.564032] CPU: 6 PID: 325 Comm: systemd-udevd Not tainted 
>> 5.18.0-amd-staging-drm-next+ #67
>> [2.564034] Hardware name: Valve Jupiter/Jupiter, BIOS F7A0105 03/21/2022
>> [2.564036] RIP: 0010:drm_mode_object_add+0x72/0x80 [drm]
>> [2.564053] Code: f0 89 c3 85 c0 78 07 89 45 00 44 89 65 04 4c 89 ef e8 
>> e2 99 04 f1 31 c0 85 db 0f 4e c3 5b 5d 41 5c 41 5d c3 80 7f 50 00 74 ac <0f> 
>> 0b eb a8 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 44 00 00 41 54 4c
>> [2.564055] RSP: 0018:b2e880413860 EFLAGS: 00010202
>> [2.564056] RAX: c0ba1440 RBX: 99508a860010 RCX: 
>> 0001
>> [2.564057] RDX: b0b0b0b0 RSI: 99508c050110 RDI: 
>> 99508a860010
>> [2.564058] RBP: 99508c050110 R08: 0020 R09: 
>> 99508c292c20
>> [2.564059] R10:  R11: 99508c0507d8 R12: 
>> b0b0b0b0
>> [2.564060] R13: 0004 R14: c068a4b6 R15: 
>> c068a47f
>> [2.564061] FS:  7fc69b5f1a40() GS:9953aff8() 
>> knlGS:
>> [2.564063] CS:  0010 DS:  ES:  CR0: 80050033
>> [2.564063] CR2: 7f9506804000 CR3: 000107f92000 CR4: 
>> 00350ee0
>> [2.564065] Call Trace:
>> [2.564068]  
>> [2.564070]  drm_property_create+0xc9/0x170 [drm]
>> [2.564088]  drm_property_create_enum+0x1f/0x70 [drm]
>> [2.564105]  drm_connector_set_panel_orientation_with_quirk+0x96/0xc0 
>> [drm]
>> [2.564123]  get_modes+0x4fb/0x530 [amdgpu]
>> [2.564378]  drm_helper_probe_single_connector_modes+0x1ad/0x850 
>> [drm_kms_helper]
>> [2.564390]  drm_client_modeset_probe+0x229/0x1400 [drm]
>> [2.564411]  ? xas_store+0x52/0x5e0
>> [2.564416]  ? kmem_cache_alloc_trace+0x177/0x2c0
>> [2.564420]  __drm_fb_helper_initial_config_and_unlock+0x44/0x4e0 
>> [drm_kms_helper]
>> [2.564430]  drm_fbdev_client_hotplug+0x173/0x210 [drm_kms_helper]
>> [2.564438]  drm_fbdev_generic_setup+0xa5/0x166 [drm_kms_helper]
>> [2.564446]  amdgpu_pci_probe+0x35e/0x370 [amdgpu]
>> [2.564621]  local_pci_probe+0x45/0x80
>> [2.564625]  ? pci_match_device+0xd7/0x130
>> [2.564627]  pci_device_probe+0xbf/0x220
>> [2.564629]  ? sysfs_do_create_link_sd+0x69/0xd0
>> [2.564633]  really_probe+0x19c/0x380
>> [2.564637]  __driver_probe_device+0xfe/0x180
>> [2.564639]  driver_probe_device+0x1e/0x90
>> [2.564641]  __driver_attach+0xc0/0x1c0
>> [2.564643]  ? __device_attach_driver+0xe0/0xe0
>> [2.564644]  ? __device_attach_driver+0xe0/0xe0
>> [2.564646]  bus_for_each_dev+0x78/0xc0
>> [2.564648]  bus_add_driver+0x149/0x1e0
>> [2.564650]  driver_register+0x8f/0xe0
>> [2.564652]  ? 0xc1023000
>> [2.564654]  do_one_initcall+0x44/0x200
>> [2.564657]  ? kmem_cache_alloc_trace+0x177/0x2c0
>> [2.564659]  do_init_module+0x4c/0x250
>> [2.564663]  __do_sys_init_module+0x12e/0x1b0
>> [2.564666]  do_syscall_64+0x3b/0x90
>> [2.564670]  entry_SYSCALL_64_after_hwframe+0x44/0xae
>> [2.564673] RIP: 0033:0x7fc69bff232e
>> [2.564674] Code: 48 8b 0d 45 0b 0c 00 f7 d8 64 89 01 48 83 c8 ff c3 66 
>> 2e 0f 1f 84 00 00 00 00 00 90 f3 0f 1e fa 49 89 ca b8 af 00 00 00 0f 05 <48> 
>> 3d 01 f0 ff ff 73 01 c3 48 8b 0d 12 0b 0c 00 f7 d8 64 89 01 48
>> [2.564676] RSP: 002b:7ffe872ba3e8 EFLAGS: 0246 ORIG_RAX: 
>> 00af
>> [2.564677] RAX: ffda RBX: 

Re: [Patch v2] drm/amdgpu: Avoid direct cast to amdgpu_ttm_tt

[Christian König]

Am 27.07.22 um 21:51 schrieb Rajneesh Bhardwaj:

For typesafety, use container_of() instead of implicit cast from struct
ttm_tt to struct amdgpu_ttm_tt.

Cc: Christian König 
Signed-off-by: Rajneesh Bhardwaj 


Reviewed-by: Christian König 


---
Changes in v2:
  * Fixed a bug that Felix pointed out in V1 by updating the macro
definition

  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 34 +
  1 file changed, 18 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index be0efaae79a9..8a6c8db31c00 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -637,6 +637,8 @@ struct amdgpu_ttm_tt {
  #endif
  };
  
+#define ttm_to_amdgpu_ttm_tt(ptr)	container_of(ptr, struct amdgpu_ttm_tt, ttm)

+
  #ifdef CONFIG_DRM_AMDGPU_USERPTR
  /*
   * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user
@@ -648,7 +650,7 @@ struct amdgpu_ttm_tt {
  int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages)
  {
struct ttm_tt *ttm = bo->tbo.ttm;
-   struct amdgpu_ttm_tt *gtt = (void *)ttm;
+   struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
unsigned long start = gtt->userptr;
struct vm_area_struct *vma;
struct mm_struct *mm;
@@ -702,7 +704,7 @@ int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, 
struct page **pages)
   */
  bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm)
  {
-   struct amdgpu_ttm_tt *gtt = (void *)ttm;
+   struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
bool r = false;
  
  	if (!gtt || !gtt->userptr)

@@ -751,7 +753,7 @@ static int amdgpu_ttm_tt_pin_userptr(struct ttm_device 
*bdev,
 struct ttm_tt *ttm)
  {
struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
-   struct amdgpu_ttm_tt *gtt = (void *)ttm;
+   struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
enum dma_data_direction direction = write ?
DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
@@ -788,7 +790,7 @@ static void amdgpu_ttm_tt_unpin_userptr(struct ttm_device 
*bdev,
struct ttm_tt *ttm)
  {
struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
-   struct amdgpu_ttm_tt *gtt = (void *)ttm;
+   struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
enum dma_data_direction direction = write ?
DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
@@ -822,7 +824,7 @@ static void amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
  {
struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
struct ttm_tt *ttm = tbo->ttm;
-   struct amdgpu_ttm_tt *gtt = (void *)ttm;
+   struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
  
  	if (amdgpu_bo_encrypted(abo))

flags |= AMDGPU_PTE_TMZ;
@@ -860,7 +862,7 @@ static int amdgpu_ttm_backend_bind(struct ttm_device *bdev,
   struct ttm_resource *bo_mem)
  {
struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
-   struct amdgpu_ttm_tt *gtt = (void*)ttm;
+   struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
uint64_t flags;
int r;
  
@@ -927,7 +929,7 @@ int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)

  {
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
struct ttm_operation_ctx ctx = { false, false };
-   struct amdgpu_ttm_tt *gtt = (void *)bo->ttm;
+   struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(bo->ttm);
struct ttm_placement placement;
struct ttm_place placements;
struct ttm_resource *tmp;
@@ -998,7 +1000,7 @@ static void amdgpu_ttm_backend_unbind(struct ttm_device 
*bdev,
  struct ttm_tt *ttm)
  {
struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
-   struct amdgpu_ttm_tt *gtt = (void *)ttm;
+   struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
  
  	/* if the pages have userptr pinning then clear that first */

if (gtt->userptr) {
@@ -1025,7 +1027,7 @@ static void amdgpu_ttm_backend_unbind(struct ttm_device 
*bdev,
  static void amdgpu_ttm_backend_destroy(struct ttm_device *bdev,
   struct ttm_tt *ttm)
  {
-   struct amdgpu_ttm_tt *gtt = (void *)ttm;
+   struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
  
  	if (gtt->usertask)

put_task_struct(gtt->usertask);
@@ -1079,7 +1081,7 @@ static int amdgpu_ttm_tt_populate(struct ttm_device *bdev,
  struct ttm_operation_ctx *ctx)
  {
struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
-   struct amdgpu_ttm_tt *gtt = (void *)ttm;
+   struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
pgoff_t i;
   

Re: [Linaro-mm-sig] [PATCH v2 2/5] drm/gem: Take reservation lock for vmap/vunmap operations

[Christian König]

Am 25.07.22 um 17:18 schrieb Dmitry Osipenko:

The new common dma-buf locking convention will require buffer importers
to hold the reservation lock around mapping operations. Make DRM GEM core
to take the lock around the vmapping operations and update QXL and i915
drivers to use the locked functions for the case where DRM core now holds
the lock. This patch prepares DRM core and drivers to transition to the
common dma-buf locking convention where vmapping of exported GEMs will
be done under the held reservation lock.

Signed-off-by: Dmitry Osipenko 


Reviewed-by: Christian König 


---
  drivers/gpu/drm/drm_client.c |  4 ++--
  drivers/gpu/drm/drm_gem.c| 24 
  drivers/gpu/drm/drm_gem_framebuffer_helper.c |  6 ++---
  drivers/gpu/drm/drm_prime.c  |  4 ++--
  drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c   |  2 +-
  drivers/gpu/drm/qxl/qxl_object.c | 17 +++---
  drivers/gpu/drm/qxl/qxl_prime.c  |  4 ++--
  include/drm/drm_gem.h|  3 +++
  8 files changed, 46 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/drm_client.c b/drivers/gpu/drm/drm_client.c
index af3b7395bf69..e9a1cd310352 100644
--- a/drivers/gpu/drm/drm_client.c
+++ b/drivers/gpu/drm/drm_client.c
@@ -323,7 +323,7 @@ drm_client_buffer_vmap(struct drm_client_buffer *buffer,
 * fd_install step out of the driver backend hooks, to make that
 * final step optional for internal users.
 */
-   ret = drm_gem_vmap(buffer->gem, map);
+   ret = drm_gem_vmap_unlocked(buffer->gem, map);
if (ret)
return ret;
  
@@ -345,7 +345,7 @@ void drm_client_buffer_vunmap(struct drm_client_buffer *buffer)

  {
struct iosys_map *map = &buffer->map;
  
-	drm_gem_vunmap(buffer->gem, map);

+   drm_gem_vunmap_unlocked(buffer->gem, map);
  }
  EXPORT_SYMBOL(drm_client_buffer_vunmap);
  
diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c

index eb0c2d041f13..8b92846112ef 100644
--- a/drivers/gpu/drm/drm_gem.c
+++ b/drivers/gpu/drm/drm_gem.c
@@ -1171,6 +1171,8 @@ int drm_gem_vmap(struct drm_gem_object *obj, struct 
iosys_map *map)
  {
int ret;
  
+	dma_resv_assert_held(obj->resv);

+
if (!obj->funcs->vmap)
return -EOPNOTSUPP;
  
@@ -1186,6 +1188,8 @@ EXPORT_SYMBOL(drm_gem_vmap);
  
  void drm_gem_vunmap(struct drm_gem_object *obj, struct iosys_map *map)

  {
+   dma_resv_assert_held(obj->resv);
+
if (iosys_map_is_null(map))
return;
  
@@ -1197,6 +1201,26 @@ void drm_gem_vunmap(struct drm_gem_object *obj, struct iosys_map *map)

  }
  EXPORT_SYMBOL(drm_gem_vunmap);
  
+int drm_gem_vmap_unlocked(struct drm_gem_object *obj, struct iosys_map *map)

+{
+   int ret;
+
+   dma_resv_lock(obj->resv, NULL);
+   ret = drm_gem_vmap(obj, map);
+   dma_resv_unlock(obj->resv);
+
+   return ret;
+}
+EXPORT_SYMBOL(drm_gem_vmap_unlocked);
+
+void drm_gem_vunmap_unlocked(struct drm_gem_object *obj, struct iosys_map *map)
+{
+   dma_resv_lock(obj->resv, NULL);
+   drm_gem_vunmap(obj, map);
+   dma_resv_unlock(obj->resv);
+}
+EXPORT_SYMBOL(drm_gem_vunmap_unlocked);
+
  /**
   * drm_gem_lock_reservations - Sets up the ww context and acquires
   * the lock on an array of GEM objects.
diff --git a/drivers/gpu/drm/drm_gem_framebuffer_helper.c 
b/drivers/gpu/drm/drm_gem_framebuffer_helper.c
index 61339a9cd010..135cd4a96ea9 100644
--- a/drivers/gpu/drm/drm_gem_framebuffer_helper.c
+++ b/drivers/gpu/drm/drm_gem_framebuffer_helper.c
@@ -354,7 +354,7 @@ int drm_gem_fb_vmap(struct drm_framebuffer *fb, struct 
iosys_map *map,
ret = -EINVAL;
goto err_drm_gem_vunmap;
}
-   ret = drm_gem_vmap(obj, &map[i]);
+   ret = drm_gem_vmap_unlocked(obj, &map[i]);
if (ret)
goto err_drm_gem_vunmap;
}
@@ -376,7 +376,7 @@ int drm_gem_fb_vmap(struct drm_framebuffer *fb, struct 
iosys_map *map,
obj = drm_gem_fb_get_obj(fb, i);
if (!obj)
continue;
-   drm_gem_vunmap(obj, &map[i]);
+   drm_gem_vunmap_unlocked(obj, &map[i]);
}
return ret;
  }
@@ -403,7 +403,7 @@ void drm_gem_fb_vunmap(struct drm_framebuffer *fb, struct 
iosys_map *map)
continue;
if (iosys_map_is_null(&map[i]))
continue;
-   drm_gem_vunmap(obj, &map[i]);
+   drm_gem_vunmap_unlocked(obj, &map[i]);
}
  }
  EXPORT_SYMBOL(drm_gem_fb_vunmap);
diff --git a/drivers/gpu/drm/drm_prime.c b/drivers/gpu/drm/drm_prime.c
index b75ef1756873..1bd234fd21a5 100644
--- a/drivers/gpu/drm/drm_prime.c
+++ b/drivers/gpu/drm/drm_prime.c
@@ -678,7 +678,7 @@ int drm_gem_dmabuf_vmap(struct dma_buf *dma_buf, struct 
iosys_map *map)
  {
struct drm_gem_object 

Re: [Linaro-mm-sig] [PATCH v2 1/5] dma-buf: Add _unlocked postfix to function names

[Christian König]

Am 25.07.22 um 17:18 schrieb Dmitry Osipenko:

Add _unlocked postfix to the dma-buf API function names in a preparation
to move all non-dynamic dma-buf users over to the dynamic locking
specification. This patch only renames API functions, preparing drivers
to the common locking convention. Later on we will make the "unlocked"
functions to take the reservation lock.

Suggested-by: Christian König 
Signed-off-by: Dmitry Osipenko 


Could be that we later say we will remove the prefix again because some 
functions should stay unlocked, but for now it makes it much clearer 
what happens here.


This patch is Acked-by: Christian König 


---
  drivers/dma-buf/dma-buf.c | 76 ++-
  drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c   |  4 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c   |  4 +-
  drivers/gpu/drm/armada/armada_gem.c   | 14 ++--
  drivers/gpu/drm/drm_gem_cma_helper.c  |  6 +-
  drivers/gpu/drm/drm_gem_shmem_helper.c|  6 +-
  drivers/gpu/drm/drm_prime.c   | 12 +--
  drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c   |  6 +-
  drivers/gpu/drm/exynos/exynos_drm_gem.c   |  2 +-
  drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c| 12 +--
  .../drm/i915/gem/selftests/i915_gem_dmabuf.c  | 20 ++---
  drivers/gpu/drm/omapdrm/omap_gem_dmabuf.c |  8 +-
  drivers/gpu/drm/tegra/gem.c   | 27 +++
  drivers/infiniband/core/umem_dmabuf.c | 11 +--
  .../common/videobuf2/videobuf2-dma-contig.c   | 15 ++--
  .../media/common/videobuf2/videobuf2-dma-sg.c | 12 +--
  .../common/videobuf2/videobuf2-vmalloc.c  |  6 +-
  .../platform/nvidia/tegra-vde/dmabuf-cache.c  | 12 +--
  drivers/misc/fastrpc.c| 12 +--
  drivers/xen/gntdev-dmabuf.c   | 14 ++--
  include/linux/dma-buf.h   | 34 +
  21 files changed, 161 insertions(+), 152 deletions(-)

diff --git a/drivers/dma-buf/dma-buf.c b/drivers/dma-buf/dma-buf.c
index 44574fbe7482..d16237a6ffaa 100644
--- a/drivers/dma-buf/dma-buf.c
+++ b/drivers/dma-buf/dma-buf.c
@@ -795,7 +795,7 @@ static struct sg_table * __map_dma_buf(struct 
dma_buf_attachment *attach,
  }
  
  /**

- * dma_buf_dynamic_attach - Add the device to dma_buf's attachments list
+ * dma_buf_dynamic_attach_unlocked - Add the device to dma_buf's attachments 
list
   * @dmabuf:   [in]buffer to attach device to.
   * @dev:  [in]device to be attached.
   * @importer_ops: [in]importer operations for the attachment
@@ -817,9 +817,9 @@ static struct sg_table * __map_dma_buf(struct 
dma_buf_attachment *attach,
   * indicated with the error code -EBUSY.
   */
  struct dma_buf_attachment *
-dma_buf_dynamic_attach(struct dma_buf *dmabuf, struct device *dev,
-  const struct dma_buf_attach_ops *importer_ops,
-  void *importer_priv)
+dma_buf_dynamic_attach_unlocked(struct dma_buf *dmabuf, struct device *dev,
+   const struct dma_buf_attach_ops *importer_ops,
+   void *importer_priv)
  {
struct dma_buf_attachment *attach;
int ret;
@@ -892,25 +892,25 @@ dma_buf_dynamic_attach(struct dma_buf *dmabuf, struct 
device *dev,
if (dma_buf_is_dynamic(attach->dmabuf))
dma_resv_unlock(attach->dmabuf->resv);
  
-	dma_buf_detach(dmabuf, attach);

+   dma_buf_detach_unlocked(dmabuf, attach);
return ERR_PTR(ret);
  }
-EXPORT_SYMBOL_NS_GPL(dma_buf_dynamic_attach, DMA_BUF);
+EXPORT_SYMBOL_NS_GPL(dma_buf_dynamic_attach_unlocked, DMA_BUF);
  
  /**

- * dma_buf_attach - Wrapper for dma_buf_dynamic_attach
+ * dma_buf_attach_unlocked - Wrapper for dma_buf_dynamic_attach
   * @dmabuf:   [in]buffer to attach device to.
   * @dev:  [in]device to be attached.
   *
- * Wrapper to call dma_buf_dynamic_attach() for drivers which still use a 
static
- * mapping.
+ * Wrapper to call dma_buf_dynamic_attach_unlocked() for drivers which still
+ * use a static mapping.
   */
-struct dma_buf_attachment *dma_buf_attach(struct dma_buf *dmabuf,
- struct device *dev)
+struct dma_buf_attachment *dma_buf_attach_unlocked(struct dma_buf *dmabuf,
+  struct device *dev)
  {
-   return dma_buf_dynamic_attach(dmabuf, dev, NULL, NULL);
+   return dma_buf_dynamic_attach_unlocked(dmabuf, dev, NULL, NULL);
  }
-EXPORT_SYMBOL_NS_GPL(dma_buf_attach, DMA_BUF);
+EXPORT_SYMBOL_NS_GPL(dma_buf_attach_unlocked, DMA_BUF);
  
  static void __unmap_dma_buf(struct dma_buf_attachment *attach,

struct sg_table *sg_table,
@@ -923,7 +923,7 @@ static void __unmap_dma_buf(struct dma_buf_attachment 
*attach,
  }
  
  /**

- * dma_buf_detach - Remove the given attachment from dmabuf's attachments list
+ * dma_buf_detach_unlocked - Remove the given attachment from dmabuf's 
attachments list
   * @dmabuf:   [in]buffe

RE: [PATCH] Increase tlb flush timeout for sriov

[Milinkovic, Dusica]

[AMD Official Use Only - General]

Hello all,

I just checked this with 1200ms for timeout, test case successfully passed 10 
loops.
If all of you agree, I will change a value in the patch.

Regards,
Dusica

From: Liu, Shaoyun 
Sent: Tuesday, August 9, 2022 12:31 AM
To: Alex Deucher ; Milinkovic, Dusica 

Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] Increase tlb flush timeout for sriov

As I discussed with Alice ,this change is when multi-vf running compute 
benchmark (Luxmark) at the same time, which involves multiple vf  do the tlb 
invalidation at the same time. They observed kiq timeout after submit the tlb 
invalidate command. Although each vf has the invalidate register set, but from 
hw, the invalidate requests are queue to execute.

Alice, as we discussed, we can use maximum 12*100ms for the timeout , it 
shouldn't be 6000ms. Did you see issues with 1200 ms timeout?

Regards
Shaoyun.liu

From: amd-gfx 
mailto:amd-gfx-boun...@lists.freedesktop.org>>
 on behalf of Alex Deucher mailto:alexdeuc...@gmail.com>>
Sent: August 8, 2022 4:49 PM
To: Milinkovic, Dusica 
mailto:dusica.milinko...@amd.com>>
Cc: amd-gfx@lists.freedesktop.org 
mailto:amd-gfx@lists.freedesktop.org>>
Subject: Re: [PATCH] Increase tlb flush timeout for sriov

On Wed, Aug 3, 2022 at 5:02 AM Dusica Milinkovic
mailto:dusica.milinko...@amd.com>> wrote:
>

Please include a patch description.  Why do you need a longer timeout?
 What problem does it fix?

> Signed-off-by: Dusica Milinkovic 
> mailto:dusica.milinko...@amd.com>>
> ---
>  drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 6 +-
>  drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c  | 6 +-
>  2 files changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> index 9ae8cdaa033e..6ab7d329916f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> @@ -419,6 +419,7 @@ static int gmc_v10_0_flush_gpu_tlb_pasid(struct 
> amdgpu_device *adev,
> uint32_t seq;
> uint16_t queried_pasid;
> bool ret;
> +   uint32_t sriov_usec_timeout = 600;  /* wait for 12 * 500ms for 
> SRIOV */
> struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
> struct amdgpu_kiq *kiq = &adev->gfx.kiq;
>
> @@ -437,7 +438,10 @@ static int gmc_v10_0_flush_gpu_tlb_pasid(struct 
> amdgpu_device *adev,
>
> amdgpu_ring_commit(ring);
> spin_unlock(&adev->gfx.kiq.ring_lock);
> -   r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout);
> +   if (amdgpu_sriov_vf(adev))
> +   r = amdgpu_fence_wait_polling(ring, seq, 
> sriov_usec_timeout);
> +   else
> +   r = amdgpu_fence_wait_polling(ring, seq, 
> adev->usec_timeout);

What about something like this?
u32 usec_timeout = amdgpu_sriov_vf(adev) ? 600 :
adev->usec_timeout;  /* wait for 12 * 500ms for SRIOV */
...
r = amdgpu_fence_wait_polling(ring, seq, usec_timeout);


> if (r < 1) {
> dev_err(adev->dev, "wait for kiq fence error: 
> %ld.\n", r);
> return -ETIME;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index 22761a3bb818..941a6b52fa72 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -896,6 +896,7 @@ static int gmc_v9_0_flush_gpu_tlb_pasid(struct 
> amdgpu_device *adev,
> uint32_t seq;
> uint16_t queried_pasid;
> bool ret;
> +   uint32_t sriov_usec_timeout = 600;  /* wait for 12 * 500ms for 
> SRIOV */
> struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
> struct amdgpu_kiq *kiq = &adev->gfx.kiq;
>
> @@ -935,7 +936,10 @@ static int gmc_v9_0_flush_gpu_tlb_pasid(struct 
> amdgpu_device *adev,
>
> amdgpu_ring_commit(ring);
> spin_unlock(&adev->gfx.kiq.ring_lock);
> -   r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout);
> +   if (amdgpu_sriov_vf(adev))
> +   r = amdgpu_fence_wait_polling(ring, seq, 
> sriov_usec_timeout);
> +   else
> +   r = amdgpu_fence_wait_polling(ring, seq, 
> adev->usec_timeout);

Same comment here.

Alex

> if (r < 1) {
> dev_err(adev->dev, "wait for kiq fence error: 
> %ld.\n", r);
> up_read(&adev->reset_domain->sem);
> --
> 2.25.1
>

[PATCH v2] drm/ttm: Fix dummy res NULL ptr deref bug

[Arunpravin Paneer Selvam]

Check the bo->resource value before accessing the resource
mem_type.

v2: Fix commit description unwrapped warning


[   40.191227][  T184] general protection fault, probably for non-canonical 
address 0xdc02:  [#1] SMP KASAN PTI
[   40.192995][  T184] KASAN: null-ptr-deref in range 
[0x0010-0x0017]
[   40.194411][  T184] CPU: 1 PID: 184 Comm: systemd-udevd Not tainted 
5.19.0-rc4-00721-gb297c22b7070 #1
[   40.196063][  T184] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), 
BIOS 1.16.0-debian-1.16.0-4 04/01/2014
[   40.199605][  T184] RIP: 0010:ttm_bo_validate+0x1b3/0x240 [ttm]
[   40.200754][  T184] Code: e8 72 c5 ff ff 83 f8 b8 74 d4 85 c0 75 54 49 8b 9e 
58 01 00 00 48 b8 00 00 00 00 00 fc ff df 48 8d 7b 10 48 89 fa 48 c1 ea 03 <0f> 
b6 04 02 84 c0 74 04 3c 03 7e 44 8b 53 10 31 c0 85 d2 0f 85 58
[   40.203685][  T184] RSP: 0018:c96df0c8 EFLAGS: 00010202
[   40.204630][  T184] RAX: dc00 RBX:  RCX: 
11102f4bb71b
[   40.205864][  T184] RDX: 0002 RSI: c96df208 RDI: 
0010
[   40.207102][  T184] RBP: 192dbe1a R08: c96df208 R09: 

[   40.208394][  T184] R10: 88817a5f R11: 0001 R12: 
c96df110
[   40.209692][  T184] R13: c96df0f0 R14: 88817a5db800 R15: 
c96df208
[   40.210862][  T184] FS:  7f6b1d16e8c0() GS:88839d70() 
knlGS:
[   40.212250][  T184] CS:  0010 DS:  ES:  CR0: 80050033
[   40.213275][  T184] CR2: 55a1001d4ff0 CR3: 0001700f4000 CR4: 
06e0
[   40.214469][  T184] Call Trace:
[   40.214974][  T184]  
[   40.215438][  T184]  ? ttm_bo_bounce_temp_buffer+0x140/0x140 [ttm]
[   40.216572][  T184]  ? mutex_spin_on_owner+0x240/0x240
[   40.217456][  T184]  ? drm_vma_offset_add+0xaa/0x100 [drm]
[   40.218457][  T184]  ttm_bo_init_reserved+0x3d6/0x540 [ttm]
[   40.219410][  T184]  ? shmem_get_inode+0x744/0x980
[   40.220231][  T184]  ttm_bo_init_validate+0xb1/0x200 [ttm]
[   40.221172][  T184]  ? bo_driver_evict_flags+0x340/0x340 [drm_vram_helper]
[   40.222530][  T184]  ? ttm_bo_init_reserved+0x540/0x540 [ttm]
[   40.223643][  T184]  ? __do_sys_finit_module+0x11a/0x1c0
[   40.224654][  T184]  ? __shmem_file_setup+0x102/0x280
[   40.234764][  T184]  drm_gem_vram_create+0x305/0x480 [drm_vram_helper]
[   40.235766][  T184]  ? bo_driver_evict_flags+0x340/0x340 [drm_vram_helper]
[   40.236846][  T184]  ? __kasan_slab_free+0x108/0x180
[   40.237650][  T184]  drm_gem_vram_fill_create_dumb+0x134/0x340 
[drm_vram_helper]
[   40.238864][  T184]  ? local_pci_probe+0xdf/0x180
[   40.239674][  T184]  ? drmm_vram_helper_init+0x400/0x400 [drm_vram_helper]
[   40.240826][  T184]  drm_client_framebuffer_create+0x19c/0x400 [drm]
[   40.241955][  T184]  ? drm_client_buffer_delete+0x200/0x200 [drm]
[   40.243001][  T184]  ? drm_client_pick_crtcs+0x554/0xb80 [drm]
[   40.244030][  T184]  drm_fb_helper_generic_probe+0x23f/0x940 [drm_kms_helper]
[   40.245226][  T184]  ? __cond_resched+0x1c/0xc0
[   40.245987][  T184]  ? drm_fb_helper_memory_range_to_clip+0x180/0x180 
[drm_kms_helper]
[   40.247316][  T184]  ? mutex_unlock+0x80/0x100
[   40.248005][  T184]  ? __mutex_unlock_slowpath+0x2c0/0x2c0
[   40.249083][  T184]  drm_fb_helper_single_fb_probe+0x907/0xf00 
[drm_kms_helper]
[   40.250314][  T184]  ? drm_fb_helper_check_var+0x1180/0x1180 [drm_kms_helper]
[   40.251540][  T184]  ? __cond_resched+0x1c/0xc0
[   40.252321][  T184]  ? mutex_lock+0x9f/0x100
[   40.253062][  T184]  __drm_fb_helper_initial_config_and_unlock+0xb9/0x2c0 
[drm_kms_helper]
[   40.254394][  T184]  drm_fbdev_client_hotplug+0x56f/0x840 [drm_kms_helper]
[   40.255477][  T184]  drm_fbdev_generic_setup+0x165/0x3c0 [drm_kms_helper]
[   40.256607][  T184]  bochs_pci_probe+0x6b7/0x900 [bochs]
[   40.257515][  T184]  ? _raw_spin_lock_irqsave+0x87/0x100
[   40.258312][  T184]  ? bochs_hw_init+0x480/0x480 [bochs]
[   40.259244][  T184]  ? bochs_hw_init+0x480/0x480 [bochs]
[   40.260186][  T184]  local_pci_probe+0xdf/0x180
[   40.260928][  T184]  pci_call_probe+0x15f/0x500
[   40.265798][  T184]  ? _raw_spin_lock+0x81/0x100
[   40.266508][  T184]  ? pci_pm_suspend_noirq+0x980/0x980
[   40.267322][  T184]  ? pci_assign_irq+0x81/0x280
[   40.268096][  T184]  ? pci_match_device+0x351/0x6c0
[   40.268883][  T184]  ? kernfs_put+0x18/0x40
[   40.269611][  T184]  pci_device_probe+0xee/0x240
[   40.270352][  T184]  really_probe+0x435/0xa80
[   40.271021][  T184]  __driver_probe_device+0x2ab/0x480
[   40.271828][  T184]  driver_probe_device+0x49/0x140
[   40.272627][  T184]  __driver_attach+0x1bd/0x4c0
[   40.273372][  T184]  ? __device_attach_driver+0x240/0x240
[   40.274273][  T184]  bus_for_each_dev+0x11e/0x1c0
[   40.275080][  T184]  ? subsys_dev_iter_exit+0x40/0x40
[   40.275951][  T184]  ? klist_add_tail+0x132/0x280
[   40.276767][  T184]  bus_add_driver+0x39b/0x580
[   40.277574][  T184]  driver_register+0x20

Re: [PATCH v5 6/6] drm/ttm: Switch to using the new res callback

[Christian König]

Am 09.08.22 um 11:22 schrieb Arunpravin Paneer Selvam:

Apply new intersect and compatible callback instead
of having a generic placement range verfications.

v2: Added a separate callback for compatiblilty
 checks (Christian)


We need to move parts of this patch earlier or the i915 will temporary 
break the driver until this here is applied.


I suggest to have most of this in the first patch and use the existing 
res->start checks as fallback when the new callbacks are not implemented 
yet.


This here can then be the last patch with cleanups and removal of those 
workarounds.


Apart from that looks like a nice cleanup to me.

Regards,
Christian.



Signed-off-by: Christian König 
Signed-off-by: Arunpravin Paneer Selvam 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 45 +++--
  drivers/gpu/drm/ttm/ttm_bo.c|  9 +++--
  drivers/gpu/drm/ttm/ttm_resource.c  |  5 +--
  3 files changed, 20 insertions(+), 39 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 170935c294f5..7d25a10395c0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1328,11 +1328,12 @@ uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device 
*adev, struct ttm_tt *ttm,
  static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
const struct ttm_place *place)
  {
-   unsigned long num_pages = bo->resource->num_pages;
struct dma_resv_iter resv_cursor;
-   struct amdgpu_res_cursor cursor;
struct dma_fence *f;
  
+	if (!amdgpu_bo_is_amdgpu_bo(bo))

+   return ttm_bo_eviction_valuable(bo, place);
+
/* Swapout? */
if (bo->resource->mem_type == TTM_PL_SYSTEM)
return true;
@@ -1351,40 +1352,20 @@ static bool amdgpu_ttm_bo_eviction_valuable(struct 
ttm_buffer_object *bo,
return false;
}
  
-	switch (bo->resource->mem_type) {

-   case AMDGPU_PL_PREEMPT:
-   /* Preemptible BOs don't own system resources managed by the
-* driver (pages, VRAM, GART space). They point to resources
-* owned by someone else (e.g. pageable memory in user mode
-* or a DMABuf). They are used in a preemptible context so we
-* can guarantee no deadlocks and good QoS in case of MMU
-* notifiers or DMABuf move notifiers from the resource owner.
-*/
+   /* Preemptible BOs don't own system resources managed by the
+* driver (pages, VRAM, GART space). They point to resources
+* owned by someone else (e.g. pageable memory in user mode
+* or a DMABuf). They are used in a preemptible context so we
+* can guarantee no deadlocks and good QoS in case of MMU
+* notifiers or DMABuf move notifiers from the resource owner.
+*/
+   if (bo->resource->mem_type == AMDGPU_PL_PREEMPT)
return false;
-   case TTM_PL_TT:
-   if (amdgpu_bo_is_amdgpu_bo(bo) &&
-   amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo)))
-   return false;
-   return true;
  
-	case TTM_PL_VRAM:

-   /* Check each drm MM node individually */
-   amdgpu_res_first(bo->resource, 0, (u64)num_pages << PAGE_SHIFT,
-&cursor);
-   while (cursor.remaining) {
-   if (place->fpfn < PFN_DOWN(cursor.start + cursor.size)
-   && !(place->lpfn &&
-place->lpfn <= PFN_DOWN(cursor.start)))
-   return true;
-
-   amdgpu_res_next(&cursor, cursor.size);
-   }
+   if (bo->resource->mem_type == TTM_PL_TT &&
+   amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo)))
return false;
  
-	default:

-   break;
-   }
-
return ttm_bo_eviction_valuable(bo, place);
  }
  
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c

index c1bd006a5525..f066e8124c50 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -518,6 +518,9 @@ static int ttm_bo_evict(struct ttm_buffer_object *bo,
  bool ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
  const struct ttm_place *place)
  {
+   struct ttm_resource *res = bo->resource;
+   struct ttm_device *bdev = bo->bdev;
+
dma_resv_assert_held(bo->base.resv);
if (bo->resource->mem_type == TTM_PL_SYSTEM)
return true;
@@ -525,11 +528,7 @@ bool ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
/* Don't evict this BO if it's outside of the
 * requested placement range
 */
-   if (place->fpfn >= (bo->resource->start + bo->resource->num_pages) ||
-   (place->lpfn && place->lpfn <= bo->resou

[PATCH v5 6/6] drm/ttm: Switch to using the new res callback

[Arunpravin Paneer Selvam]

Apply new intersect and compatible callback instead
of having a generic placement range verfications.

v2: Added a separate callback for compatiblilty
checks (Christian)

Signed-off-by: Christian König 
Signed-off-by: Arunpravin Paneer Selvam 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 45 +++--
 drivers/gpu/drm/ttm/ttm_bo.c|  9 +++--
 drivers/gpu/drm/ttm/ttm_resource.c  |  5 +--
 3 files changed, 20 insertions(+), 39 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 170935c294f5..7d25a10395c0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1328,11 +1328,12 @@ uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device 
*adev, struct ttm_tt *ttm,
 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
const struct ttm_place *place)
 {
-   unsigned long num_pages = bo->resource->num_pages;
struct dma_resv_iter resv_cursor;
-   struct amdgpu_res_cursor cursor;
struct dma_fence *f;
 
+   if (!amdgpu_bo_is_amdgpu_bo(bo))
+   return ttm_bo_eviction_valuable(bo, place);
+
/* Swapout? */
if (bo->resource->mem_type == TTM_PL_SYSTEM)
return true;
@@ -1351,40 +1352,20 @@ static bool amdgpu_ttm_bo_eviction_valuable(struct 
ttm_buffer_object *bo,
return false;
}
 
-   switch (bo->resource->mem_type) {
-   case AMDGPU_PL_PREEMPT:
-   /* Preemptible BOs don't own system resources managed by the
-* driver (pages, VRAM, GART space). They point to resources
-* owned by someone else (e.g. pageable memory in user mode
-* or a DMABuf). They are used in a preemptible context so we
-* can guarantee no deadlocks and good QoS in case of MMU
-* notifiers or DMABuf move notifiers from the resource owner.
-*/
+   /* Preemptible BOs don't own system resources managed by the
+* driver (pages, VRAM, GART space). They point to resources
+* owned by someone else (e.g. pageable memory in user mode
+* or a DMABuf). They are used in a preemptible context so we
+* can guarantee no deadlocks and good QoS in case of MMU
+* notifiers or DMABuf move notifiers from the resource owner.
+*/
+   if (bo->resource->mem_type == AMDGPU_PL_PREEMPT)
return false;
-   case TTM_PL_TT:
-   if (amdgpu_bo_is_amdgpu_bo(bo) &&
-   amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo)))
-   return false;
-   return true;
 
-   case TTM_PL_VRAM:
-   /* Check each drm MM node individually */
-   amdgpu_res_first(bo->resource, 0, (u64)num_pages << PAGE_SHIFT,
-&cursor);
-   while (cursor.remaining) {
-   if (place->fpfn < PFN_DOWN(cursor.start + cursor.size)
-   && !(place->lpfn &&
-place->lpfn <= PFN_DOWN(cursor.start)))
-   return true;
-
-   amdgpu_res_next(&cursor, cursor.size);
-   }
+   if (bo->resource->mem_type == TTM_PL_TT &&
+   amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo)))
return false;
 
-   default:
-   break;
-   }
-
return ttm_bo_eviction_valuable(bo, place);
 }
 
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index c1bd006a5525..f066e8124c50 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -518,6 +518,9 @@ static int ttm_bo_evict(struct ttm_buffer_object *bo,
 bool ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
  const struct ttm_place *place)
 {
+   struct ttm_resource *res = bo->resource;
+   struct ttm_device *bdev = bo->bdev;
+
dma_resv_assert_held(bo->base.resv);
if (bo->resource->mem_type == TTM_PL_SYSTEM)
return true;
@@ -525,11 +528,7 @@ bool ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
/* Don't evict this BO if it's outside of the
 * requested placement range
 */
-   if (place->fpfn >= (bo->resource->start + bo->resource->num_pages) ||
-   (place->lpfn && place->lpfn <= bo->resource->start))
-   return false;
-
-   return true;
+   return ttm_resource_intersects(bdev, res, place, bo->base.size);
 }
 EXPORT_SYMBOL(ttm_bo_eviction_valuable);
 
diff --git a/drivers/gpu/drm/ttm/ttm_resource.c 
b/drivers/gpu/drm/ttm/ttm_resource.c
index ea67976f1f60..a729c32a1e48 100644
--- a/drivers/gpu/drm/ttm/ttm_resource.c
+++ b/drivers/gpu/drm/ttm/ttm_resource.c
@@ -316,6 +316,8 @@ static bool ttm_resource_places_compat(struct ttm_resource 
*res,
   

[PATCH v5 4/6] drm/i915: Implement intersect/compatible functions

[Arunpravin Paneer Selvam]

Implemented a new intersect and compatible callback function
fetching start offset from drm buddy allocator.

v3: move the bits that are specific to buddy_man (Matthew)
v4: consider the block size /range (Matthew)

Signed-off-by: Christian König 
Signed-off-by: Arunpravin Paneer Selvam 
Reviewed-by: Matthew Auld 
---
 drivers/gpu/drm/i915/gem/i915_gem_ttm.c   | 41 +--
 drivers/gpu/drm/i915/i915_ttm_buddy_manager.c | 73 +++
 2 files changed, 74 insertions(+), 40 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c 
b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index 70e2ed4e99df..bf5fd6886ca0 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -379,7 +379,6 @@ static bool i915_ttm_eviction_valuable(struct 
ttm_buffer_object *bo,
   const struct ttm_place *place)
 {
struct drm_i915_gem_object *obj = i915_ttm_to_gem(bo);
-   struct ttm_resource *res = bo->resource;
 
if (!obj)
return false;
@@ -396,45 +395,7 @@ static bool i915_ttm_eviction_valuable(struct 
ttm_buffer_object *bo,
if (!i915_gem_object_evictable(obj))
return false;
 
-   switch (res->mem_type) {
-   case I915_PL_LMEM0: {
-   struct ttm_resource_manager *man =
-   ttm_manager_type(bo->bdev, res->mem_type);
-   struct i915_ttm_buddy_resource *bman_res =
-   to_ttm_buddy_resource(res);
-   struct drm_buddy *mm = bman_res->mm;
-   struct drm_buddy_block *block;
-
-   if (!place->fpfn && !place->lpfn)
-   return true;
-
-   GEM_BUG_ON(!place->lpfn);
-
-   /*
-* If we just want something mappable then we can quickly check
-* if the current victim resource is using any of the CPU
-* visible portion.
-*/
-   if (!place->fpfn &&
-   place->lpfn == i915_ttm_buddy_man_visible_size(man))
-   return bman_res->used_visible_size > 0;
-
-   /* Real range allocation */
-   list_for_each_entry(block, &bman_res->blocks, link) {
-   unsigned long fpfn =
-   drm_buddy_block_offset(block) >> PAGE_SHIFT;
-   unsigned long lpfn = fpfn +
-   (drm_buddy_block_size(mm, block) >> PAGE_SHIFT);
-
-   if (place->fpfn < lpfn && place->lpfn > fpfn)
-   return true;
-   }
-   return false;
-   } default:
-   break;
-   }
-
-   return true;
+   return ttm_bo_eviction_valuable(bo, place);
 }
 
 static void i915_ttm_evict_flags(struct ttm_buffer_object *bo,
diff --git a/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c 
b/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c
index a5109548abc0..56d017e4038b 100644
--- a/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c
+++ b/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c
@@ -178,6 +178,77 @@ static void i915_ttm_buddy_man_free(struct 
ttm_resource_manager *man,
kfree(bman_res);
 }
 
+static bool i915_ttm_buddy_man_intersects(struct ttm_resource_manager *man,
+ struct ttm_resource *res,
+ const struct ttm_place *place,
+ size_t size)
+{
+   struct i915_ttm_buddy_resource *bman_res = to_ttm_buddy_resource(res);
+   struct i915_ttm_buddy_manager *bman = to_buddy_manager(man);
+   struct drm_buddy *mm = &bman->mm;
+   struct drm_buddy_block *block;
+
+   if (!place->fpfn && !place->lpfn)
+   return true;
+
+   GEM_BUG_ON(!place->lpfn);
+
+   /*
+* If we just want something mappable then we can quickly check
+* if the current victim resource is using any of the CPU
+* visible portion.
+*/
+   if (!place->fpfn &&
+   place->lpfn == i915_ttm_buddy_man_visible_size(man))
+   return bman_res->used_visible_size > 0;
+
+   /* Check each drm buddy block individually */
+   list_for_each_entry(block, &bman_res->blocks, link) {
+   unsigned long fpfn =
+   drm_buddy_block_offset(block) >> PAGE_SHIFT;
+   unsigned long lpfn = fpfn +
+   (drm_buddy_block_size(mm, block) >> PAGE_SHIFT);
+
+   if (place->fpfn < lpfn && place->lpfn > fpfn)
+   return true;
+   }
+
+   return false;
+}
+
+static bool i915_ttm_buddy_man_compatible(struct ttm_resource_manager *man,
+ struct ttm_resource *res,
+ const struct ttm_place *place,
+ size_t size)
+{
+   struct i915_ttm_

[PATCH v5 5/6] drm/nouveau: Implement intersect/compatible functions

[Arunpravin Paneer Selvam]

Implemented a new intersect and compatible callback function
fetching the start offset from struct ttm_resource.

Signed-off-by: Christian König 
Signed-off-by: Arunpravin Paneer Selvam 
---
 drivers/gpu/drm/nouveau/nouveau_mem.c | 29 +++
 drivers/gpu/drm/nouveau/nouveau_mem.h |  6 ++
 drivers/gpu/drm/nouveau/nouveau_ttm.c | 24 ++
 3 files changed, 59 insertions(+)

diff --git a/drivers/gpu/drm/nouveau/nouveau_mem.c 
b/drivers/gpu/drm/nouveau/nouveau_mem.c
index 2e517cdc24c9..76f8edefa637 100644
--- a/drivers/gpu/drm/nouveau/nouveau_mem.c
+++ b/drivers/gpu/drm/nouveau/nouveau_mem.c
@@ -187,3 +187,32 @@ nouveau_mem_new(struct nouveau_cli *cli, u8 kind, u8 comp,
*res = &mem->base;
return 0;
 }
+
+bool
+nouveau_mem_intersects(struct ttm_resource *res,
+  const struct ttm_place *place,
+  size_t size)
+{
+   u32 num_pages = PFN_UP(size);
+
+   /* Don't evict BOs outside of the requested placement range */
+   if (place->fpfn >= (res->start + num_pages) ||
+   (place->lpfn && place->lpfn <= res->start))
+   return false;
+
+   return true;
+}
+
+bool
+nouveau_mem_compatible(struct ttm_resource *res,
+  const struct ttm_place *place,
+  size_t size)
+{
+   u32 num_pages = PFN_UP(size);
+
+   if (res->start < place->fpfn ||
+   (place->lpfn && (res->start + num_pages) > place->lpfn))
+   return false;
+
+   return true;
+}
diff --git a/drivers/gpu/drm/nouveau/nouveau_mem.h 
b/drivers/gpu/drm/nouveau/nouveau_mem.h
index 325551eba5cd..1ee6cdb9ad9b 100644
--- a/drivers/gpu/drm/nouveau/nouveau_mem.h
+++ b/drivers/gpu/drm/nouveau/nouveau_mem.h
@@ -25,6 +25,12 @@ int nouveau_mem_new(struct nouveau_cli *, u8 kind, u8 comp,
struct ttm_resource **);
 void nouveau_mem_del(struct ttm_resource_manager *man,
 struct ttm_resource *);
+bool nouveau_mem_intersects(struct ttm_resource *res,
+   const struct ttm_place *place,
+   size_t size);
+bool nouveau_mem_compatible(struct ttm_resource *res,
+   const struct ttm_place *place,
+   size_t size);
 int nouveau_mem_vram(struct ttm_resource *, bool contig, u8 page);
 int nouveau_mem_host(struct ttm_resource *, struct ttm_tt *);
 void nouveau_mem_fini(struct nouveau_mem *);
diff --git a/drivers/gpu/drm/nouveau/nouveau_ttm.c 
b/drivers/gpu/drm/nouveau/nouveau_ttm.c
index 85f1f5a0fe5d..9602c30928f2 100644
--- a/drivers/gpu/drm/nouveau/nouveau_ttm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_ttm.c
@@ -42,6 +42,24 @@ nouveau_manager_del(struct ttm_resource_manager *man,
nouveau_mem_del(man, reg);
 }
 
+static bool
+nouveau_manager_intersects(struct ttm_resource_manager *man,
+  struct ttm_resource *res,
+  const struct ttm_place *place,
+  size_t size)
+{
+   return nouveau_mem_intersects(res, place, size);
+}
+
+static bool
+nouveau_manager_compatible(struct ttm_resource_manager *man,
+  struct ttm_resource *res,
+  const struct ttm_place *place,
+  size_t size)
+{
+   return nouveau_mem_compatible(res, place, size);
+}
+
 static int
 nouveau_vram_manager_new(struct ttm_resource_manager *man,
 struct ttm_buffer_object *bo,
@@ -73,6 +91,8 @@ nouveau_vram_manager_new(struct ttm_resource_manager *man,
 const struct ttm_resource_manager_func nouveau_vram_manager = {
.alloc = nouveau_vram_manager_new,
.free = nouveau_manager_del,
+   .intersects = nouveau_manager_intersects,
+   .compatible = nouveau_manager_compatible,
 };
 
 static int
@@ -97,6 +117,8 @@ nouveau_gart_manager_new(struct ttm_resource_manager *man,
 const struct ttm_resource_manager_func nouveau_gart_manager = {
.alloc = nouveau_gart_manager_new,
.free = nouveau_manager_del,
+   .intersects = nouveau_manager_intersects,
+   .compatible = nouveau_manager_compatible,
 };
 
 static int
@@ -130,6 +152,8 @@ nv04_gart_manager_new(struct ttm_resource_manager *man,
 const struct ttm_resource_manager_func nv04_gart_manager = {
.alloc = nv04_gart_manager_new,
.free = nouveau_manager_del,
+   .intersects = nouveau_manager_intersects,
+   .compatible = nouveau_manager_compatible,
 };
 
 static int
-- 
2.25.1

[PATCH v5 3/6] drm/amdgpu: Implement intersect/compatible functions

[Arunpravin Paneer Selvam]

Implemented a new intersect and compatible callback function
fetching start offset from backend drm buddy allocator.

Signed-off-by: Christian König 
Signed-off-by: Arunpravin Paneer Selvam 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c  | 38 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 68 
 2 files changed, 106 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
index 8c6b2284cf56..1f3302aebeff 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
@@ -204,6 +204,42 @@ void amdgpu_gtt_mgr_recover(struct amdgpu_gtt_mgr *mgr)
amdgpu_gart_invalidate_tlb(adev);
 }
 
+/**
+ * amdgpu_gtt_mgr_intersects - test for intersection
+ *
+ * @man: Our manager object
+ * @res: The resource to test
+ * @place: The place for the new allocation
+ * @size: The size of the new allocation
+ *
+ * Simplified intersection test, only interesting if we need GART or not.
+ */
+static bool amdgpu_gtt_mgr_intersects(struct ttm_resource_manager *man,
+ struct ttm_resource *res,
+ const struct ttm_place *place,
+ size_t size)
+{
+   return !place->lpfn || amdgpu_gtt_mgr_has_gart_addr(res);
+}
+
+/**
+ * amdgpu_gtt_mgr_compatible - test for compatibility
+ *
+ * @man: Our manager object
+ * @res: The resource to test
+ * @place: The place for the new allocation
+ * @size: The size of the new allocation
+ *
+ * Simplified compatibility test.
+ */
+static bool amdgpu_gtt_mgr_compatible(struct ttm_resource_manager *man,
+ struct ttm_resource *res,
+ const struct ttm_place *place,
+ size_t size)
+{
+   return !place->lpfn || amdgpu_gtt_mgr_has_gart_addr(res);
+}
+
 /**
  * amdgpu_gtt_mgr_debug - dump VRAM table
  *
@@ -225,6 +261,8 @@ static void amdgpu_gtt_mgr_debug(struct 
ttm_resource_manager *man,
 static const struct ttm_resource_manager_func amdgpu_gtt_mgr_func = {
.alloc = amdgpu_gtt_mgr_new,
.free = amdgpu_gtt_mgr_del,
+   .intersects = amdgpu_gtt_mgr_intersects,
+   .compatible = amdgpu_gtt_mgr_compatible,
.debug = amdgpu_gtt_mgr_debug
 };
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
index 7a5e8a7b4a1b..dcf2a6400e8e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
@@ -720,6 +720,72 @@ uint64_t amdgpu_vram_mgr_vis_usage(struct amdgpu_vram_mgr 
*mgr)
return atomic64_read(&mgr->vis_usage);
 }
 
+/**
+ * amdgpu_vram_mgr_intersects - test each drm buddy block for intersection
+ *
+ * @man: TTM memory type manager
+ * @res: The resource to test
+ * @place: The place to test against
+ * @size: Size of the new allocation
+ *
+ * Test each drm buddy block for intersection for eviction decision.
+ */
+static bool amdgpu_vram_mgr_intersects(struct ttm_resource_manager *man,
+  struct ttm_resource *res,
+  const struct ttm_place *place,
+  size_t size)
+{
+   struct amdgpu_vram_mgr_resource *mgr = to_amdgpu_vram_mgr_resource(res);
+   struct drm_buddy_block *block;
+
+   /* Check each drm buddy block individually */
+   list_for_each_entry(block, &mgr->blocks, link) {
+   unsigned long fpfn =
+   amdgpu_vram_mgr_block_start(block) >> PAGE_SHIFT;
+   unsigned long lpfn = fpfn +
+   (amdgpu_vram_mgr_block_size(block) >> PAGE_SHIFT);
+
+   if (place->fpfn < lpfn &&
+   (place->lpfn && place->lpfn > fpfn))
+   return true;
+   }
+
+   return false;
+}
+
+/**
+ * amdgpu_vram_mgr_compatible - test each drm buddy block for compatibility
+ *
+ * @man: TTM memory type manager
+ * @res: The resource to test
+ * @place: The place to test against
+ * @size: Size of the new allocation
+ *
+ * Test each drm buddy block for placement compatibility.
+ */
+static bool amdgpu_vram_mgr_compatible(struct ttm_resource_manager *man,
+  struct ttm_resource *res,
+  const struct ttm_place *place,
+  size_t size)
+{
+   struct amdgpu_vram_mgr_resource *mgr = to_amdgpu_vram_mgr_resource(res);
+   struct drm_buddy_block *block;
+
+   /* Check each drm buddy block individually */
+   list_for_each_entry(block, &mgr->blocks, link) {
+   unsigned long fpfn =
+   amdgpu_vram_mgr_block_start(block) >> PAGE_SHIFT;
+   unsigned long lpfn = fpfn +
+   (amdgpu_vram_mgr_block_size(block) >> PAGE_SHIFT);
+
+   

[PATCH v5 2/6] drm/ttm: Implement intersect/compatible functions

[Arunpravin Paneer Selvam]

Implemented a new intersect and compatible callback functions
to ttm range manager fetching start offset from drm mm range
allocator.

Signed-off-by: Christian König 
Signed-off-by: Arunpravin Paneer Selvam 
---
 drivers/gpu/drm/ttm/ttm_range_manager.c | 33 +
 1 file changed, 33 insertions(+)

diff --git a/drivers/gpu/drm/ttm/ttm_range_manager.c 
b/drivers/gpu/drm/ttm/ttm_range_manager.c
index d91666721dc6..4cfef2b3514d 100644
--- a/drivers/gpu/drm/ttm/ttm_range_manager.c
+++ b/drivers/gpu/drm/ttm/ttm_range_manager.c
@@ -113,6 +113,37 @@ static void ttm_range_man_free(struct ttm_resource_manager 
*man,
kfree(node);
 }
 
+static bool ttm_range_man_intersects(struct ttm_resource_manager *man,
+struct ttm_resource *res,
+const struct ttm_place *place,
+size_t size)
+{
+   struct drm_mm_node *node = &to_ttm_range_mgr_node(res)->mm_nodes[0];
+   u32 num_pages = PFN_UP(size);
+
+   /* Don't evict BOs outside of the requested placement range */
+   if (place->fpfn >= (node->start + num_pages) ||
+   (place->lpfn && place->lpfn <= node->start))
+   return false;
+
+   return true;
+}
+
+static bool ttm_range_man_compatible(struct ttm_resource_manager *man,
+struct ttm_resource *res,
+const struct ttm_place *place,
+size_t size)
+{
+   struct drm_mm_node *node = &to_ttm_range_mgr_node(res)->mm_nodes[0];
+   u32 num_pages = PFN_UP(size);
+
+   if (node->start < place->fpfn ||
+   (place->lpfn && (node->start + num_pages) > place->lpfn))
+   return false;
+
+   return true;
+}
+
 static void ttm_range_man_debug(struct ttm_resource_manager *man,
struct drm_printer *printer)
 {
@@ -126,6 +157,8 @@ static void ttm_range_man_debug(struct ttm_resource_manager 
*man,
 static const struct ttm_resource_manager_func ttm_range_manager_func = {
.alloc = ttm_range_man_alloc,
.free = ttm_range_man_free,
+   .intersects = ttm_range_man_intersects,
+   .compatible = ttm_range_man_compatible,
.debug = ttm_range_man_debug
 };
 
-- 
2.25.1

[PATCH v5 1/6] drm/ttm: Add new callbacks to ttm res mgr

[Arunpravin Paneer Selvam]

We are adding two new callbacks to ttm resource manager
function to handle intersection and compatibility of
placement and resources.

v2: move the amdgpu and ttm_range_manager changes to
separate patches (Christian)
v3: rename "intersect" to "intersects" (Matthew)
v4: move !place check to the !res if and return false
in ttm_resource_compatible() function (Christian)

Signed-off-by: Christian König 
Signed-off-by: Arunpravin Paneer Selvam 
---
 drivers/gpu/drm/ttm/ttm_resource.c | 59 ++
 include/drm/ttm/ttm_resource.h | 40 
 2 files changed, 99 insertions(+)

diff --git a/drivers/gpu/drm/ttm/ttm_resource.c 
b/drivers/gpu/drm/ttm/ttm_resource.c
index 20f9adcc3235..ea67976f1f60 100644
--- a/drivers/gpu/drm/ttm/ttm_resource.c
+++ b/drivers/gpu/drm/ttm/ttm_resource.c
@@ -253,6 +253,65 @@ void ttm_resource_free(struct ttm_buffer_object *bo, 
struct ttm_resource **res)
 }
 EXPORT_SYMBOL(ttm_resource_free);
 
+/**
+ * ttm_resource_intersects - test for intersection
+ *
+ * @bdev: TTM device structure
+ * @res: The resource to test
+ * @place: The placement to test
+ * @size: How many bytes the new allocation needs.
+ *
+ * Test if @res intersects with @place and @size. Used for testing if evictions
+ * are valueable or not.
+ *
+ * Returns true if the res placement intersects with @place and @size.
+ */
+bool ttm_resource_intersects(struct ttm_device *bdev,
+struct ttm_resource *res,
+const struct ttm_place *place,
+size_t size)
+{
+   struct ttm_resource_manager *man;
+
+   if (!res)
+   return false;
+
+   man = ttm_manager_type(bdev, res->mem_type);
+   if (!place || !man->func->intersects)
+   return true;
+
+   return man->func->intersects(man, res, place, size);
+}
+
+/**
+ * ttm_resource_compatible - test for compatibility
+ *
+ * @bdev: TTM device structure
+ * @res: The resource to test
+ * @place: The placement to test
+ * @size: How many bytes the new allocation needs.
+ *
+ * Test if @res compatible with @place and @size.
+ *
+ * Returns true if the res placement compatible with @place and @size.
+ */
+bool ttm_resource_compatible(struct ttm_device *bdev,
+struct ttm_resource *res,
+const struct ttm_place *place,
+size_t size)
+{
+   struct ttm_resource_manager *man;
+
+   if (!res || !place)
+   return false;
+
+   man = ttm_manager_type(bdev, res->mem_type);
+   if (!man->func->compatible)
+   return true;
+
+   return man->func->compatible(man, res, place, size);
+}
+
 static bool ttm_resource_places_compat(struct ttm_resource *res,
   const struct ttm_place *places,
   unsigned num_placement)
diff --git a/include/drm/ttm/ttm_resource.h b/include/drm/ttm/ttm_resource.h
index ca89a48c2460..5afc6d664fde 100644
--- a/include/drm/ttm/ttm_resource.h
+++ b/include/drm/ttm/ttm_resource.h
@@ -88,6 +88,38 @@ struct ttm_resource_manager_func {
void (*free)(struct ttm_resource_manager *man,
 struct ttm_resource *res);
 
+   /**
+* struct ttm_resource_manager_func member intersects
+*
+* @man: Pointer to a memory type manager.
+* @res: Pointer to a struct ttm_resource to be checked.
+* @place: Placement to check against.
+* @size: Size of the check.
+*
+* Test if @res intersects with @place + @size. Used to judge if
+* evictions are valueable or not.
+*/
+   bool (*intersects)(struct ttm_resource_manager *man,
+  struct ttm_resource *res,
+  const struct ttm_place *place,
+  size_t size);
+
+   /**
+* struct ttm_resource_manager_func member compatible
+*
+* @man: Pointer to a memory type manager.
+* @res: Pointer to a struct ttm_resource to be checked.
+* @place: Placement to check against.
+* @size: Size of the check.
+*
+* Test if @res compatible with @place + @size. Used to check of
+* the need to move the backing store or not.
+*/
+   bool (*compatible)(struct ttm_resource_manager *man,
+  struct ttm_resource *res,
+  const struct ttm_place *place,
+  size_t size);
+
/**
 * struct ttm_resource_manager_func member debug
 *
@@ -329,6 +361,14 @@ int ttm_resource_alloc(struct ttm_buffer_object *bo,
   const struct ttm_place *place,
   struct ttm_resource **res);
 void ttm_resource_free(struct ttm_buffer_object *bo, struct ttm_resource 
**res);
+bool ttm_resource_intersects(struct ttm_device *bdev,
+   

RE: [PATCH 1/2] drm/amdgpu: modify mcbp implement for gfx9(v2)

[Zhu, Jiadong]

[AMD Official Use Only - General]

Hi,

This patch is to correct the mcbp package for gfx9, which is the basic function 
used for debugfs.
There are no logic about when to trigger mcbp.
Shall we get this reviewed?

Thanks,
Jiadong

-Original Message-
From: Zhu, Jiadong 
Sent: Tuesday, August 9, 2022 5:15 PM
To: amd-gfx@lists.freedesktop.org
Cc: Liu, Aaron ; Huang, Ray ; Zhu, 
Jiadong 
Subject: [PATCH 1/2] drm/amdgpu: modify mcbp implement for gfx9(v2)

From: "Jiadong.Zhu" 

1. Use unmap_queue package to trigger preemption on gfx9
   Add trailing fence to track the preemption done.
2. Modify emit_ce_meta emit_de_meta functions
   for the resumed ibs.
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h |   1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c| 159 ---
 drivers/gpu/drm/amd/amdgpu/soc15d.h  |   2 +
 3 files changed, 141 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 82c178a9033a..ca626f0ad7b1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -59,6 +59,7 @@ enum amdgpu_ring_priority_level {
 #define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
 #define AMDGPU_FENCE_FLAG_INT   (1 << 1)
 #define AMDGPU_FENCE_FLAG_TC_WB_ONLY(1 << 2)
+#define AMDGPU_FENCE_FLAG_EXEC  (1 << 3)

 #define to_amdgpu_ring(s) container_of((s), struct amdgpu_ring, sched)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 5332899642dc..0b7cb4cf13c4 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -751,7 +751,7 @@ static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device 
*adev);  static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
struct amdgpu_cu_info *cu_info);
 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev); 
-static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring);
+static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool
+resume);
 static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring);  static 
void gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev,
  void *ras_error_status);
@@ -824,9 +824,10 @@ static void gfx_v9_0_kiq_unmap_queues(struct amdgpu_ring 
*kiq_ring,

PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));

if (action == PREEMPT_QUEUES_NO_UNMAP) {
-   amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
-   amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
-   amdgpu_ring_write(kiq_ring, seq);
+   amdgpu_ring_write(kiq_ring, lower_32_bits(ring->wptr & 
ring->buf_mask));
+   amdgpu_ring_write(kiq_ring, 0);
+   amdgpu_ring_write(kiq_ring, 0);
+
} else {
amdgpu_ring_write(kiq_ring, 0);
amdgpu_ring_write(kiq_ring, 0);
@@ -5446,11 +5447,15 @@ static void gfx_v9_0_ring_emit_ib_gfx(struct 
amdgpu_ring *ring,

control |= ib->length_dw | (vmid << 24);

-   if (amdgpu_sriov_vf(ring->adev) && (ib->flags & 
AMDGPU_IB_FLAG_PREEMPT)) {
+   if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags &
+AMDGPU_IB_FLAG_PREEMPT)) {
control |= INDIRECT_BUFFER_PRE_ENB(1);

+   if (flags & AMDGPU_IB_PREEMPTED)
+   control |= INDIRECT_BUFFER_PRE_RESUME(1);
+
if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)
-   gfx_v9_0_ring_emit_de_meta(ring);
+   gfx_v9_0_ring_emit_de_meta(ring,
+(!amdgpu_sriov_vf(ring->adev) && flags & 
AMDGPU_IB_PREEMPTED) ?
+true : false);
}

amdgpu_ring_write(ring, header);
@@ -5505,6 +5510,7 @@ static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring 
*ring, u64 addr,
bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY;
+   bool exec = flags & AMDGPU_FENCE_FLAG_EXEC;

/* RELEASE_MEM - flush caches, send int */
amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); @@ -5515,6 
+5521,7 @@ static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring *ring, u64 
addr,
   EOP_TC_WB_ACTION_EN |
   EOP_TC_MD_ACTION_EN)) |
 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
+(exec ? EOP_EXEC : 0x0) |
 EVENT_INDEX(5)));
amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel 
? 2 : 0));

@@ -5620,33 +5627,135 @@ static void gfx_v9_ring_emit_sb(struct amdgpu_ring 
*ring)
amdgpu_ring_write(ring, 0);
 }

-static void gfx_v9_0_ring_emit_ce_met

[PATCH 1/2] drm/amdgpu: modify mcbp implement for gfx9(v2)

[jiadong.zhu]

From: "Jiadong.Zhu" 

1. Use unmap_queue package to trigger preemption on gfx9
   Add trailing fence to track the preemption done.
2. Modify emit_ce_meta emit_de_meta functions
   for the resumed ibs.
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h |   1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c| 159 ---
 drivers/gpu/drm/amd/amdgpu/soc15d.h  |   2 +
 3 files changed, 141 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 82c178a9033a..ca626f0ad7b1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -59,6 +59,7 @@ enum amdgpu_ring_priority_level {
 #define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
 #define AMDGPU_FENCE_FLAG_INT   (1 << 1)
 #define AMDGPU_FENCE_FLAG_TC_WB_ONLY(1 << 2)
+#define AMDGPU_FENCE_FLAG_EXEC  (1 << 3)
 
 #define to_amdgpu_ring(s) container_of((s), struct amdgpu_ring, sched)
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 5332899642dc..0b7cb4cf13c4 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -751,7 +751,7 @@ static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device 
*adev);
 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
struct amdgpu_cu_info *cu_info);
 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev);
-static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring);
+static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
 static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring);
 static void gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev,
  void *ras_error_status);
@@ -824,9 +824,10 @@ static void gfx_v9_0_kiq_unmap_queues(struct amdgpu_ring 
*kiq_ring,

PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
 
if (action == PREEMPT_QUEUES_NO_UNMAP) {
-   amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
-   amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
-   amdgpu_ring_write(kiq_ring, seq);
+   amdgpu_ring_write(kiq_ring, lower_32_bits(ring->wptr & 
ring->buf_mask));
+   amdgpu_ring_write(kiq_ring, 0);
+   amdgpu_ring_write(kiq_ring, 0);
+
} else {
amdgpu_ring_write(kiq_ring, 0);
amdgpu_ring_write(kiq_ring, 0);
@@ -5446,11 +5447,15 @@ static void gfx_v9_0_ring_emit_ib_gfx(struct 
amdgpu_ring *ring,
 
control |= ib->length_dw | (vmid << 24);
 
-   if (amdgpu_sriov_vf(ring->adev) && (ib->flags & 
AMDGPU_IB_FLAG_PREEMPT)) {
+   if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags & 
AMDGPU_IB_FLAG_PREEMPT)) {
control |= INDIRECT_BUFFER_PRE_ENB(1);
 
+   if (flags & AMDGPU_IB_PREEMPTED)
+   control |= INDIRECT_BUFFER_PRE_RESUME(1);
+
if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)
-   gfx_v9_0_ring_emit_de_meta(ring);
+   gfx_v9_0_ring_emit_de_meta(ring,
+(!amdgpu_sriov_vf(ring->adev) && flags & 
AMDGPU_IB_PREEMPTED) ? true : false);
}
 
amdgpu_ring_write(ring, header);
@@ -5505,6 +5510,7 @@ static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring 
*ring, u64 addr,
bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY;
+   bool exec = flags & AMDGPU_FENCE_FLAG_EXEC;
 
/* RELEASE_MEM - flush caches, send int */
amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
@@ -5515,6 +5521,7 @@ static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring 
*ring, u64 addr,
   EOP_TC_WB_ACTION_EN |
   EOP_TC_MD_ACTION_EN)) |
 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
+(exec ? EOP_EXEC : 0x0) |
 EVENT_INDEX(5)));
amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel 
? 2 : 0));
 
@@ -5620,33 +5627,135 @@ static void gfx_v9_ring_emit_sb(struct amdgpu_ring 
*ring)
amdgpu_ring_write(ring, 0);
 }
 
-static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring)
+static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)
 {
+   struct amdgpu_device *adev = ring->adev;
struct v9_ce_ib_state ce_payload = {0};
-   uint64_t csa_addr;
+   uint64_t offset, ce_payload_gpu_addr;
+   void *ce_payload_cpu_addr;
int cnt;
 
cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
-   csa_addr = amdgpu_csa_vaddr(ring->adev);
+
+   if (ring->is_mes_q

[PATCH 2/2] drm/amdgpu: add mcbp support for sdma v4.0

[jiadong.zhu]

From: "Jiadong.Zhu" 

Set register to enable mcbp according to amdgpu_mcbp.
Add sdma preempt_ib function used for debugfs test.
---
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 53 ++
 1 file changed, 53 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index d35f18536da2..bc69af4b4ada 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -1502,6 +1502,11 @@ static int sdma_v4_0_start(struct amdgpu_device *adev)
/* set utc l1 enable flag always to 1 */
temp = RREG32_SDMA(i, mmSDMA0_CNTL);
temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
+
+   if (amdgpu_mcbp){
+   /* enable MCBP */
+   temp = REG_SET_FIELD(temp, SDMA0_CNTL, 
MIDCMD_PREEMPT_ENABLE, 1);
+   }
WREG32_SDMA(i, mmSDMA0_CNTL, temp);
 
if (!amdgpu_sriov_vf(adev)) {
@@ -2102,6 +2107,53 @@ static int sdma_v4_0_soft_reset(void *handle)
return 0;
 }
 
+static int sdma_v4_0_ring_preempt_ib(struct amdgpu_ring *ring)
+{
+   int i, r = 0;
+   struct amdgpu_device *adev = ring->adev;
+   u32 index = 0;
+   u64 sdma_gfx_preempt;
+
+   amdgpu_sdma_get_index_from_ring(ring, &index);
+   if (index == 0)
+   sdma_gfx_preempt = mmSDMA0_GFX_PREEMPT;
+   else
+   sdma_gfx_preempt = mmSDMA1_GFX_PREEMPT;
+
+   /* assert preemption condition */
+   amdgpu_ring_set_preempt_cond_exec(ring, false);
+
+   /* emit the trailing fence */
+   ring->trail_seq += 1;
+   amdgpu_ring_alloc(ring, 10);
+   sdma_v4_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
+ ring->trail_seq, 0);
+   amdgpu_ring_commit(ring);
+
+   /* assert IB preemption */
+   WREG32(sdma_gfx_preempt, 1);
+
+   /* poll the trailing fence */
+   for (i = 0; i < adev->usec_timeout; i++) {
+   if (ring->trail_seq ==
+   le32_to_cpu(*(ring->trail_fence_cpu_addr)))
+   break;
+   udelay(1);
+   }
+
+   if (i >= adev->usec_timeout) {
+   r = -EINVAL;
+   DRM_ERROR("ring %d failed to be preempted\n", ring->idx);
+   }
+
+   /* deassert IB preemption */
+   WREG32(sdma_gfx_preempt, 0);
+
+   /* deassert the preemption condition */
+   amdgpu_ring_set_preempt_cond_exec(ring, true);
+   return r;
+}
+
 static int sdma_v4_0_set_trap_irq_state(struct amdgpu_device *adev,
struct amdgpu_irq_src *source,
unsigned type,
@@ -2435,6 +2487,7 @@ static const struct amdgpu_ring_funcs 
sdma_v4_0_ring_funcs = {
.emit_wreg = sdma_v4_0_ring_emit_wreg,
.emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
+   .preempt_ib = sdma_v4_0_ring_preempt_ib,
 };
 
 /*
-- 
2.25.1

Re: [PATCH v2 2/6] drm/ttm: Implement intersect/compatible functions

[Arunpravin Paneer Selvam]

On 8/8/2022 5:00 PM, Christian König wrote:



Am 25.07.22 um 13:42 schrieb Arunpravin Paneer Selvam:

Implemented a new intersect and compatible callback functions
to ttm range manager fetching start offset from drm mm range
allocator.

Signed-off-by: Christian König 
Signed-off-by: Arunpravin Paneer Selvam 


---
  drivers/gpu/drm/ttm/ttm_range_manager.c | 33 +
  1 file changed, 33 insertions(+)

diff --git a/drivers/gpu/drm/ttm/ttm_range_manager.c 
b/drivers/gpu/drm/ttm/ttm_range_manager.c

index d91666721dc6..12b8d9b36fe6 100644
--- a/drivers/gpu/drm/ttm/ttm_range_manager.c
+++ b/drivers/gpu/drm/ttm/ttm_range_manager.c
@@ -113,6 +113,37 @@ static void ttm_range_man_free(struct 
ttm_resource_manager *man,

  kfree(node);
  }
  +static bool ttm_range_man_intersect(struct ttm_resource_manager *man,
+    struct ttm_resource *res,
+    const struct ttm_place *place,
+    size_t size)
+{
+    struct drm_mm_node *node = 
&to_ttm_range_mgr_node(res)->mm_nodes[0];

+    u32 num_pages = PFN_UP(size);
+
+    /* Don't evict BOs outside of the requested placement range */
+    if (place->fpfn >= (node->start + num_pages) ||
+    (place->lpfn && place->lpfn <= node->start))
+    return false;
+
+    return true;
+}
+
+static bool ttm_range_man_compatible(struct ttm_resource_manager *man,
+ struct ttm_resource *res,
+ const struct ttm_place *place,
+ size_t size)
+{
+    struct drm_mm_node *node = 
&to_ttm_range_mgr_node(res)->mm_nodes[0];

+    u32 num_pages = PFN_UP(size);
+
+    if (node->start < place->fpfn ||


This should probably be "<=".
We are checking the false condition here, if node->start == place->fpfn, 
then the node->start

value is compatible with place->fpfn, therefore, we don't return false.

Thanks,
Arun


Regards,
Christian.


+    (place->lpfn && (node->start + num_pages) > place->lpfn))
+    return false;
+
+    return true;
+}
+
  static void ttm_range_man_debug(struct ttm_resource_manager *man,
  struct drm_printer *printer)
  {
@@ -126,6 +157,8 @@ static void ttm_range_man_debug(struct 
ttm_resource_manager *man,
  static const struct ttm_resource_manager_func 
ttm_range_manager_func = {

  .alloc = ttm_range_man_alloc,
  .free = ttm_range_man_free,
+    .intersect = ttm_range_man_intersect,
+    .compatible = ttm_range_man_compatible,
  .debug = ttm_range_man_debug
  };

RE: [PATCH] drm/amd/pm: skip pptable override for smu_v13_0_7

[Xu, Feifei]

[AMD Official Use Only - General]



Reviewed-by: Feifei Xu 



-Original Message-
From: amd-gfx  On Behalf Of Kenneth Feng
Sent: Tuesday, August 9, 2022 3:22 PM
To: amd-gfx@lists.freedesktop.org
Cc: Feng, Kenneth 
Subject: [PATCH] drm/amd/pm: skip pptable override for smu_v13_0_7

skip pptable override for smu_v13_0_7 secure boards only.

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 10 +++---
 1 file changed, 3 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index 0370482dd52b..daf4dc9811af 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -212,6 +212,9 @@ int smu_v13_0_init_pptable_microcode(struct smu_context 
*smu)
if (!adev->scpm_enabled)
return 0;
 
+   if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 7))
+   return 0;
+
/* override pptable_id from driver parameter */
if (amdgpu_smu_pptable_id >= 0) {
pptable_id = amdgpu_smu_pptable_id;
@@ -219,13 +222,6 @@ int smu_v13_0_init_pptable_microcode(struct smu_context 
*smu)
} else {
pptable_id = smu->smu_table.boot_values.pp_table_id;
 
-   if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 7) &&
-   pptable_id == 3667)
-   pptable_id = 36671;
-
-   if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 7) &&
-   pptable_id == 3688)
-   pptable_id = 36881;
/*
 * Temporary solution for SMU V13.0.0 with SCPM enabled:
 *   - use 36831 signed pptable when pp_table_id is 3683
-- 
2.25.1

[PATCH] drm/amd/pm: skip pptable override for smu_v13_0_7

[Kenneth Feng]

skip pptable override for smu_v13_0_7 secure boards only.

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 10 +++---
 1 file changed, 3 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index 0370482dd52b..daf4dc9811af 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -212,6 +212,9 @@ int smu_v13_0_init_pptable_microcode(struct smu_context 
*smu)
if (!adev->scpm_enabled)
return 0;
 
+   if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 7))
+   return 0;
+
/* override pptable_id from driver parameter */
if (amdgpu_smu_pptable_id >= 0) {
pptable_id = amdgpu_smu_pptable_id;
@@ -219,13 +222,6 @@ int smu_v13_0_init_pptable_microcode(struct smu_context 
*smu)
} else {
pptable_id = smu->smu_table.boot_values.pp_table_id;
 
-   if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 7) &&
-   pptable_id == 3667)
-   pptable_id = 36671;
-
-   if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 7) &&
-   pptable_id == 3688)
-   pptable_id = 36881;
/*
 * Temporary solution for SMU V13.0.0 with SCPM enabled:
 *   - use 36831 signed pptable when pp_table_id is 3683
-- 
2.25.1