[PATCH 33/33] drm/amd/display: Correct cursor position on horizontal mirror
From: Martin Tsai
[Why]
Incorrect cursor position will induce system hang on pipe split.
[How]
1.Handle horizontal mirror on rotation,
2.Correct cursor set on piep split.
Reviewed-by: Ariel Bernstein
Acked-by: Brian Chang
Signed-off-by: Martin Tsai
---
.../gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c | 5 +-
.../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c | 9 +--
.../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 72 ++-
.../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c | 9 +--
4 files changed, 63 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
index db7ca4b0cdb9..897f412f539e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
@@ -448,11 +448,12 @@ void dpp1_set_cursor_position(
src_y_offset = pos->y - pos->x_hotspot -
param->viewport.y;
}
} else if (param->rotation == ROTATION_ANGLE_180) {
- src_x_offset = pos->x - param->viewport.x;
+ if (!param->mirror)
+ src_x_offset = pos->x - param->viewport.x;
+
src_y_offset = pos->y - param->viewport.y;
}
-
if (src_x_offset >= (int)param->viewport.width)
cur_en = 0; /* not visible beyond right edge*/
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
index 564e061ccb58..52e201e9b091 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
@@ -1208,13 +1208,10 @@ void hubp1_cursor_set_position(
src_y_offset = pos->y - pos->x_hotspot -
param->viewport.y;
}
} else if (param->rotation == ROTATION_ANGLE_180) {
- src_x_offset = pos->x - param->viewport.x;
- src_y_offset = pos->y - param->viewport.y;
- }
+ if (!param->mirror)
+ src_x_offset = pos->x - param->viewport.x;
- if (param->mirror) {
- x_hotspot = param->viewport.width - x_hotspot;
- src_x_offset = param->viewport.x + param->viewport.width -
src_x_offset;
+ src_y_offset = pos->y - param->viewport.y;
}
dst_x_offset = (src_x_offset >= 0) ? src_x_offset : 0;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index d3f6a2609c8c..b92c14b9043f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -3470,8 +3470,7 @@ void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)
.rotation = pipe_ctx->plane_state->rotation,
.mirror = pipe_ctx->plane_state->horizontal_mirror
};
- bool pipe_split_on = (pipe_ctx->top_pipe != NULL) ||
- (pipe_ctx->bottom_pipe != NULL);
+ bool pipe_split_on = false;
bool odm_combine_on = (pipe_ctx->next_odm_pipe != NULL) ||
(pipe_ctx->prev_odm_pipe != NULL);
@@ -3480,6 +3479,13 @@ void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)
int x_pos = pos_cpy.x;
int y_pos = pos_cpy.y;
+ if ((pipe_ctx->top_pipe != NULL) || (pipe_ctx->bottom_pipe != NULL)) {
+ if ((pipe_ctx->plane_state->src_rect.width !=
pipe_ctx->plane_res.scl_data.viewport.width) ||
+ (pipe_ctx->plane_state->src_rect.height !=
pipe_ctx->plane_res.scl_data.viewport.height)) {
+ pipe_split_on = true;
+ }
+ }
+
/**
* DC cursor is stream space, HW cursor is plane space and drawn
* as part of the framebuffer.
@@ -3551,8 +3557,36 @@ void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)
if (pos_cpy.enable && dcn10_can_pipe_disable_cursor(pipe_ctx))
pos_cpy.enable = false;
+
+ if (param.rotation == ROTATION_ANGLE_0) {
+ int viewport_width =
+ pipe_ctx->plane_res.scl_data.viewport.width;
+ int viewport_x =
+ pipe_ctx->plane_res.scl_data.viewport.x;
+
+ if (param.mirror) {
+ if (pipe_split_on || odm_combine_on) {
+ if (pos_cpy.x >= viewport_width + viewport_x) {
+ pos_cpy.x = 2 * viewport_width
+ - pos_cpy.x + 2 *
viewport_x;
+ } else {
+ uint32_t temp_x = pos_cpy.x;
+
+ pos_cpy.x = 2 * viewport_x - pos_cpy.x;
+ if (temp_x >= viewport_x +
+ (int)hubp->curs_attr.width ||
[PATCH 31/33] drm/amd/display: Fix check for stream and plane
From: Ethan Wellenreiter [WHY] Function wasn't returning false when it had a no stream [HOW] Made it return false when it had no stream. Reviewed-by: Alvin Lee Acked-by: Brian Chang Signed-off-by: Ethan Wellenreiter --- drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c index 955f52e6064d..ab918fe38f6a 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c @@ -144,7 +144,7 @@ bool dcn32_all_pipes_have_stream_and_plane(struct dc *dc, struct pipe_ctx *pipe = >res_ctx.pipe_ctx[i]; if (!pipe->stream) - continue; + return false; if (!pipe->plane_state) return false; -- 2.25.1
[PATCH 32/33] drm/amd/display: Fix black flash when switching from ODM2to1 to ODMBypass
From: Vladimir Stempen
[Why]
On secondary display hotplug we switch primary
stream from ODM2to1 to ODMBypass mode. Current
logic will trigger disabling front end for this
stream.
[How]
We need to check if prev_odm_pipe is equal to NULL
in order to disable dangling planes in this scenario.
Reviewed-by: Ariel Bernstein
Acked-by: Brian Chang
Signed-off-by: Vladimir Stempen
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 1ca76708705b..6a28f3e0ceb4 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1097,7 +1097,8 @@ static void disable_dangling_plane(struct dc *dc, struct
dc_state *context)
dc->current_state->stream_count !=
context->stream_count)
should_disable = true;
- if (old_stream &&
!dc->current_state->res_ctx.pipe_ctx[i].top_pipe) {
+ if (old_stream &&
!dc->current_state->res_ctx.pipe_ctx[i].top_pipe &&
+
!dc->current_state->res_ctx.pipe_ctx[i].prev_odm_pipe) {
struct pipe_ctx *old_pipe, *new_pipe;
old_pipe = >current_state->res_ctx.pipe_ctx[i];
--
2.25.1
[PATCH 30/33] drm/amd/display: Re-initialize viewport after pipe merge
From: Ethan Wellenreiter
[Why]
Pipes get merged in preparation for SubVP but if they don't get used, and
are in ODM or some other multi pipe config, it would calculate the
voltage level with a viewport of just one pipe from when they were split
resulting in too low of a voltage level.
[How]
Made it so that the viewport and other timing settings get rebuilt and re-
initialized after the pipe merge, before calculating the voltage level so it
would calculate it correctly.
Reviewed-by: Alvin Lee
Reviewed-by: Jun Lei
Acked-by: Brian Chang
Signed-off-by: Ethan Wellenreiter
---
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index 23a661f541a5..1b62be823b59 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -1024,6 +1024,15 @@ static void dcn32_full_validate_bw_helper(struct dc *dc,
dc->debug.force_subvp_mclk_switch)) {
dcn32_merge_pipes_for_subvp(dc, context);
+ // to re-initialize viewport after the pipe merge
+ for (int i = 0; i < dc->res_pool->pipe_count; i++) {
+ struct pipe_ctx *pipe_ctx =
>res_ctx.pipe_ctx[i];
+
+ if (!pipe_ctx->plane_state || !pipe_ctx->stream)
+ continue;
+
+ resource_build_scaling_params(pipe_ctx);
+ }
while (!found_supported_config &&
dcn32_enough_pipes_for_subvp(dc, context) &&
dcn32_assign_subvp_pipe(dc, context, _pipe_idx)) {
--
2.25.1
[PATCH 29/33] drm/amd/display: Use correct plane for CAB cursor size allocation
From: Aurabindo Pillai
[Why]
plane and stream variables used for cursor size allocation calculation
were stale from previous iteration. Redo the iteration to find the
correct cursor plane for the calculation.
Reviewed-by: Alvin Lee
Acked-by: Brian Chang
Signed-off-by: Aurabindo Pillai
---
.../drm/amd/display/dc/dcn32/dcn32_hwseq.c| 32 ---
1 file changed, 21 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
index 7717d00b60dc..8587b67fe824 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
@@ -295,8 +295,8 @@ static uint32_t dcn32_calculate_cab_allocation(struct dc
*dc, struct dc_state *c
}
// Include cursor size for CAB allocation
- for (i = 0; i < dc->res_pool->pipe_count; i++) {
- struct pipe_ctx *pipe = >res_ctx.pipe_ctx[i];
+ for (j = 0; j < dc->res_pool->pipe_count; j++) {
+ struct pipe_ctx *pipe = >res_ctx.pipe_ctx[j];
struct hubp *hubp = pipe->plane_res.hubp;
if (pipe->stream && pipe->plane_state && hubp)
@@ -339,15 +339,25 @@ static uint32_t dcn32_calculate_cab_allocation(struct dc
*dc, struct dc_state *c
if (cache_lines_used % lines_per_way > 0)
num_ways++;
- if (stream->cursor_position.enable &&
- !plane->address.grph.cursor_cache_addr.quad_part &&
- cursor_size > 16384)
- /* Cursor caching is not supported since it won't be on the
same line.
-* So we need an extra line to accommodate it. With large
cursors and a single 4k monitor
-* this case triggers corruption. If we're at the edge, then
dont trigger display refresh
-* from MALL. We only need to cache cursor if its greater that
64x64 at 4 bpp.
-*/
- num_ways++;
+ for (i = 0; i < ctx->stream_count; i++) {
+ stream = ctx->streams[i];
+ for (j = 0; j < ctx->stream_status[i].plane_count; j++) {
+ plane = ctx->stream_status[i].plane_states[j];
+
+ if (stream->cursor_position.enable && plane &&
+
!plane->address.grph.cursor_cache_addr.quad_part &&
+ cursor_size > 16384) {
+ /* Cursor caching is not supported since it
won't be on the same line.
+* So we need an extra line to accommodate it.
With large cursors and a single 4k monitor
+* this case triggers corruption. If we're at
the edge, then dont trigger display refresh
+* from MALL. We only need to cache cursor if
its greater that 64x64 at 4 bpp.
+*/
+ num_ways++;
+ /* We only expect one cursor plane */
+ break;
+ }
+ }
+ }
return num_ways;
}
--
2.25.1
[PATCH 28/33] drm/amd/display: 3.2.201
From: Aric Cyr Reviewed-by: Aric Cyr Acked-by: Brian Chang Signed-off-by: Aric Cyr --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 9cde9465f5ce..75dbc665f435 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -47,7 +47,7 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.200" +#define DC_VER "3.2.201" #define MAX_SURFACES 3 #define MAX_PLANES 6 -- 2.25.1
[PATCH 27/33] drm/amd/display: [FW Promotion] Release 0.0.132.0
From: Anthony Koo
- Fix comment to indicate correct visual confirm option
Reviewed-by: Aric Cyr
Acked-by: Brian Chang
Signed-off-by: Anthony Koo
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index 1184bef22673..7cddbc431b57 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -234,8 +234,7 @@ union dmub_psr_debug_flags {
};
/**
- * DMUB feature capabilities.
- * After DMUB init, driver will query FW capabilities prior to enabling
certain features.
+ * DMUB visual confirm color
*/
struct dmub_feature_caps {
/**
--
2.25.1
[PATCH 26/33] drm/amd/display: Add comments.
From: Ian Chen
Reviewed-by: Dennis Chan
Acked-by: Brian Chang
Signed-off-by: Ian Chen
---
drivers/gpu/drm/amd/display/dc/dc_link.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h
b/drivers/gpu/drm/amd/display/dc/dc_link.h
index 43d250918fd0..3f64b3092692 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_link.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
@@ -117,6 +117,7 @@ struct psr_settings {
* Add a struct dc_panel_config under dc_link
*/
struct dc_panel_config {
+ // edp DSC
struct dsc {
bool disable_dsc_edp;
unsigned int force_dsc_edp_policy;
--
2.25.1
[PATCH 25/33] drm/amd/display: Revert "program k1/k2 divider for virtual signal for DCN32"
From: Aurabindo Pillai
[Why & How]
This reverts commit 9dd9c085ae3b since it
causes a SubVP related regression: "Switching between windowed video and
fullscreen can intermittently cause black screen"
Reviewed-by: Aric Cyr
Acked-by: Brian Chang
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
index 2d428ec48e24..7717d00b60dc 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
@@ -1157,7 +1157,7 @@ unsigned int dcn32_calculate_dccg_k1_k2_values(struct
pipe_ctx *pipe_ctx, unsign
*k2_div = PIXEL_RATE_DIV_BY_2;
else
*k2_div = PIXEL_RATE_DIV_BY_4;
- } else if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
dc_is_virtual_signal(pipe_ctx->stream->signal)) {
+ } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
if (two_pix_per_container) {
*k1_div = PIXEL_RATE_DIV_BY_1;
*k2_div = PIXEL_RATE_DIV_BY_2;
--
2.25.1
[PATCH 24/33] drm/amd/display: Fix primary EDP link detection
From: Iswara Nagulendran
[HOW]
EDP link detection must
be updated to support a primary EDP with a
link index of greater than 0.
* SWDEV-342936 - dc: DSC bringup for SAG 1.5
[WHY]
SmartAccess Graphics 1.5 (a.k.a SmartMux 1.5)
requires seamless switching between GPUs
with DSC enabled.
[HOW]
Moved DSC programming to
apply_single_control_ctx_to_hw before the stream
enablement logic to ensure the CRC checker provides valid
values for non-black frames
allowing the system to come out of forced PSR on
d2i.
Added additional logic to both generate a black
frame through setVisibility calls and keep track
of the CRCs values for this black frame when
coming out of forced PSR.
Updating logic for DalRegKey_DisableDSC to disable
DSC on EDP and all ports for systems.
[CLEANED]
dc: Moved DSC programming to before stream enablement
[HOW]
Moved DSC programming to
apply_single_control_ctx_to_hw before the stream
enablement logic.
Co-authored-by: sregolui
Reviewed-by: Jayendran Ramani
Reviewed-by: Harry Vanzylldejong
Acked-by: Brian Chang
Signed-off-by: sregolui
Signed-off-by: Iswara Nagulendran
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 12
.../drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 13 +
2 files changed, 13 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 74db87f3dc6f..38fa63d43ad9 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -4303,18 +4303,6 @@ void core_link_enable_stream(
if (pipe_ctx->stream->dpms_off)
return;
- /* Have to setup DSC before DIG FE and BE are connected (which
happens before the
-* link training). This is to make sure the bandwidth sent to
DIG BE won't be
-* bigger than what the link and/or DIG BE can handle.
VBID[6]/CompressedStream_flag
-* will be automatically set at a later time when the video is
enabled
-* (DP_VID_STREAM_EN = 1).
-*/
- if (pipe_ctx->stream->timing.flags.DSC) {
- if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
-
dc_is_virtual_signal(pipe_ctx->stream->signal))
- dp_set_dsc_enable(pipe_ctx, true);
- }
-
status = enable_link(state, pipe_ctx);
if (status != DC_OK) {
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 801206aed63a..fe346e96c2d1 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1577,6 +1577,19 @@ static enum dc_status apply_single_controller_ctx_to_hw(
if (dc_is_dp_signal(pipe_ctx->stream->signal))
dp_source_sequence_trace(link,
DPCD_SOURCE_SEQ_AFTER_CONNECT_DIG_FE_OTG);
+ /* Have to setup DSC before DIG FE and BE are connected (which happens
before the
+* link training). This is to make sure the bandwidth sent to DIG BE
won't be
+* bigger than what the link and/or DIG BE can handle.
VBID[6]/CompressedStream_flag
+* will be automatically set at a later time when the video is enabled
+* (DP_VID_STREAM_EN = 1).
+*/
+ if (pipe_ctx->stream->timing.flags.DSC) {
+ if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
+ dc_is_virtual_signal(pipe_ctx->stream->signal))
+ dp_set_dsc_enable(pipe_ctx, true);
+
+ }
+
if (!stream->dpms_off) {
if (dc->hwss.update_phy_state)
dc->hwss.update_phy_state(context, pipe_ctx,
TX_ON_SYMCLK_ON);
--
2.25.1
[PATCH 22/33] drm/amd/display: use actual cursor size instead of max for CAB allocation
From: Aurabindo Pillai
[Why]
When calculating allocation for cursor size, get the real cursor through
the HUBP instead of using the maximum cursor size for more optimal
allocation
Reviewed-by: Alvin Lee
Reviewed-by: Nicholas Kazlauskas
Acked-by: Brian Chang
Signed-off-by: Aurabindo Pillai
---
.../gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c| 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
index a54cb79e7ba0..2d428ec48e24 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
@@ -295,7 +295,20 @@ static uint32_t dcn32_calculate_cab_allocation(struct dc
*dc, struct dc_state *c
}
// Include cursor size for CAB allocation
- cursor_size = dc->caps.max_cursor_size *
dc->caps.max_cursor_size;
+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ struct pipe_ctx *pipe = >res_ctx.pipe_ctx[i];
+ struct hubp *hubp = pipe->plane_res.hubp;
+
+ if (pipe->stream && pipe->plane_state && hubp)
+ /* Find the cursor plane and use the exact size
instead of
+* using the max for calculation
+*/
+ if (hubp->curs_attr.width > 0) {
+ cursor_size = hubp->curs_attr.width *
hubp->curs_attr.height;
+ break;
+ }
+ }
+
switch (stream->cursor_attributes.color_format) {
case CURSOR_MODE_MONO:
cursor_size /= 2;
--
2.25.1
[PATCH 23/33] drm/amd/display: fix wrong register access
From: Charlene Liu
[why]
fw version check was for release branch.
for staging, it has a chance to enter wrong code path.
Reviewed-by: Hansen Dsouza
Acked-by: Brian Chang
Signed-off-by: Charlene Liu
---
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c | 3 +++
.../gpu/drm/amd/display/dc/dcn314/dcn314_dio_stream_encoder.c | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c
index a788d160953b..ab70ebd8f223 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c
@@ -104,6 +104,9 @@ static bool has_query_dp_alt(struct link_encoder *enc)
{
struct dc_dmub_srv *dc_dmub_srv = enc->ctx->dmub_srv;
+ if (enc->ctx->dce_version >= DCN_VERSION_3_15)
+ return true;
+
/* Supports development firmware and firmware >= 4.0.11 */
return dc_dmub_srv &&
!(dc_dmub_srv->dmub->fw_version >= DMUB_FW_VERSION(4, 0, 0) &&
diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dio_stream_encoder.c
b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dio_stream_encoder.c
index b384f30395d3..e3351ddc566c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dio_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dio_stream_encoder.c
@@ -317,6 +317,7 @@ static void enc314_stream_encoder_dp_unblank(
/* switch DP encoder to CRTC data, but reset it the fifo first. It may
happen
* that it overflows during mode transition, and sometimes doesn't
recover.
*/
+ REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_READ_START_LEVEL, 0x7);
REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 1);
udelay(10);
--
2.25.1
[PATCH 21/33] drm/amd/display: disable display fresh from MALL on an edge case for DCN321
From: Aurabindo Pillai
[Why]
When using a 4k monitor when cursor caching is not supported due to
framebuffer being on an uncacheable address, enabling display refresh
from MALL would trigger corruption if SS is enabled.
Prevent entering SS if we are on the edge case and cursor caching is not
possible. Do this only if cursor size larger than a 64x64@4bpp. Pull the
cursor size calculation out of if condition since cursor address may not
be set on all platforms
Reviewed-by: Alvin Lee
Reviewed-by: Nicholas Kazlauskas
Acked-by: Brian Chang
Signed-off-by: Aurabindo Pillai
---
.../drm/amd/display/dc/dcn32/dcn32_hwseq.c| 43 ---
1 file changed, 27 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
index 4e965a0c2484..a54cb79e7ba0 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
@@ -295,23 +295,24 @@ static uint32_t dcn32_calculate_cab_allocation(struct dc
*dc, struct dc_state *c
}
// Include cursor size for CAB allocation
+ cursor_size = dc->caps.max_cursor_size *
dc->caps.max_cursor_size;
+ switch (stream->cursor_attributes.color_format) {
+ case CURSOR_MODE_MONO:
+ cursor_size /= 2;
+ break;
+ case CURSOR_MODE_COLOR_1BIT_AND:
+ case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:
+ case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:
+ cursor_size *= 4;
+ break;
+
+ case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED:
+ case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED:
+ cursor_size *= 8;
+ break;
+ }
+
if (stream->cursor_position.enable &&
plane->address.grph.cursor_cache_addr.quad_part) {
- cursor_size = dc->caps.max_cursor_size *
dc->caps.max_cursor_size;
- switch (stream->cursor_attributes.color_format) {
- case CURSOR_MODE_MONO:
- cursor_size /= 2;
- break;
- case CURSOR_MODE_COLOR_1BIT_AND:
- case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:
- case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:
- cursor_size *= 4;
- break;
-
- case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED:
- case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED:
- cursor_size *= 8;
- break;
- }
cache_lines_used += dcn32_cache_lines_for_surface(dc,
cursor_size,
plane->address.grph.cursor_cache_addr.quad_part);
}
@@ -325,6 +326,16 @@ static uint32_t dcn32_calculate_cab_allocation(struct dc
*dc, struct dc_state *c
if (cache_lines_used % lines_per_way > 0)
num_ways++;
+ if (stream->cursor_position.enable &&
+ !plane->address.grph.cursor_cache_addr.quad_part &&
+ cursor_size > 16384)
+ /* Cursor caching is not supported since it won't be on the
same line.
+* So we need an extra line to accommodate it. With large
cursors and a single 4k monitor
+* this case triggers corruption. If we're at the edge, then
dont trigger display refresh
+* from MALL. We only need to cache cursor if its greater that
64x64 at 4 bpp.
+*/
+ num_ways++;
+
return num_ways;
}
--
2.25.1
[PATCH 20/33] drm/amd/display: Fix CAB cursor size allocation for DCN32/321
From: Aurabindo Pillai For calculating cursor size allocation, surface size was used, resulting in over allocation Reviewed-by: Alvin Lee Reviewed-by: Nicholas Kazlauskas Acked-by: Brian Chang Signed-off-by: Aurabindo Pillai --- drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c index 63648e2056a0..4e965a0c2484 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c @@ -312,7 +312,7 @@ static uint32_t dcn32_calculate_cab_allocation(struct dc *dc, struct dc_state *c cursor_size *= 8; break; } - cache_lines_used += dcn32_cache_lines_for_surface(dc, surface_size, + cache_lines_used += dcn32_cache_lines_for_surface(dc, cursor_size, plane->address.grph.cursor_cache_addr.quad_part); } } -- 2.25.1
[PATCH 19/33] drm/amd/display: Missing HPO instance added
From: Leo Chen
[Why & How]
Number of encoder is set to 4 but only 3 instances are created.
Reviewed-by: Charlene Liu
Acked-by: Brian Chang
Signed-off-by: Leo Chen
---
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
index 5e62527d3ab9..e7f0c7d412e7 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
@@ -454,6 +454,7 @@ static const struct dcn31_hpo_dp_stream_encoder_registers
hpo_dp_stream_enc_regs
hpo_dp_stream_encoder_reg_list(0),
hpo_dp_stream_encoder_reg_list(1),
hpo_dp_stream_encoder_reg_list(2),
+ hpo_dp_stream_encoder_reg_list(3)
};
static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
--
2.25.1
[PATCH 18/33] drm/amd/display: Refactor edp dsc codes.
From: Ian Chen
Refactor edp dsc codes.
We split out edp dsc config from "global" to "per-panel" config settings.
Reviewed-by: Mike Hsieh
Acked-by: Brian Chang
Signed-off-by: Ian Chen
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++--
.../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 19 +++
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 10 +-
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 4 ++--
drivers/gpu/drm/amd/display/dc/dc.h | 2 --
drivers/gpu/drm/amd/display/dc/dc_link.h | 10 ++
drivers/gpu/drm/amd/display/dc/dm_helpers.h | 7 ++-
7 files changed, 48 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 35b0d6a28726..62378f8694c0 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1527,7 +1527,6 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) {
adev->dm.dc->debug.disable_dsc = true;
- adev->dm.dc->debug.disable_dsc_edp = true;
}
if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING)
@@ -5627,7 +5626,8 @@ static void apply_dsc_policy_for_stream(struct
amdgpu_dm_connector *aconnector,
dc_dsc_policy_set_enable_dsc_when_not_needed(
aconnector->dsc_settings.dsc_force_enable ==
DSC_CLK_FORCE_ENABLE);
- if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_EDP &&
!dc->debug.disable_dsc_edp &&
+ if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_EDP &&
+ !aconnector->dc_link->panel_config.dsc.disable_dsc_edp &&
dc->caps.edp_dsc_support &&
aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) {
apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps,
max_dsc_target_bpp_limit_override);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index bd364d2cc4f7..0b7440b92c10 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -916,6 +916,25 @@ void dm_helpers_smu_timeout(struct dc_context *ctx,
unsigned int msg_id, unsigne
//amdgpu_device_gpu_recover(dc_context->driver-context, NULL);
}
+void dm_helpers_init_panel_settings(
+ struct dc_context *ctx,
+ struct dc_panel_config *panel_config)
+{
+ // Feature DSC
+ panel_config->dsc.disable_dsc_edp = false;
+ panel_config->dsc.force_dsc_edp_policy = 0;
+}
+
+void dm_helpers_override_panel_settings(
+ struct dc_context *ctx,
+ struct dc_panel_config *panel_config)
+{
+ // Feature DSC
+ if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) {
+ panel_config->dsc.disable_dsc_edp = true;
+ }
+}
+
void *dm_helpers_allocate_gpu_mem(
struct dc_context *ctx,
enum dc_gpu_mem_alloc_type type,
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 66d2ae7aacf5..74db87f3dc6f 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1311,6 +1311,14 @@ static bool detect_link_and_local_sink(struct dc_link
*link,
sink->edid_caps.audio_modes[i].sample_rate,
sink->edid_caps.audio_modes[i].sample_size);
}
+
+ if (link->connector_signal == SIGNAL_TYPE_EDP) {
+ // Init dc_panel_config
+ dm_helpers_init_panel_settings(dc_ctx,
>panel_config);
+ // Override dc_panel_config if system has specific
settings
+ dm_helpers_override_panel_settings(dc_ctx,
>panel_config);
+ }
+
} else {
/* From Connected-to-Disconnected. */
link->type = dc_connection_none;
@@ -4736,7 +4744,7 @@ bool dc_link_should_enable_fec(const struct dc_link *link)
else if (link->connector_signal == SIGNAL_TYPE_EDP
&& (link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.
dsc_support.DSC_SUPPORT == false
- || link->dc->debug.disable_dsc_edp
+ || link->panel_config.dsc.disable_dsc_edp
|| !link->dc->caps.edp_dsc_support))
force_disable = true;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 7e97265b76e8..11e13c45a338 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -3743,7 +3743,7 @@ static bool decide_edp_link_settings_with_dsc(struct
dc_link *link,
[PATCH 17/33] drm/amd/display: SubVP missing scaling case
From: Alvin Lee
[Description]
For SubVP scaling case we have to combine
the plane scaling and stream scaling.
Use UCLK dummy p-state WM for FCLK WM set C
[Description]
For DCN32/321 program dummy UCLK P-state watermark into FCLK
watermark set C register.
Reviewed-by: Jun Lei
Reviewed-by: Nevenko Stupar
Acked-by: Brian Chang
Signed-off-by: Alvin Lee
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 10 --
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 6 +-
2 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
index 61dfe5358d1c..81aba1f51974 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
@@ -632,7 +632,7 @@ static void populate_subvp_cmd_pipe_info(struct dc *dc,
>fw_assisted_mclk_switch_v2.config_data.pipe_data[cmd_pipe_index];
struct dc_crtc_timing *main_timing = _pipe->stream->timing;
struct dc_crtc_timing *phantom_timing =
_pipe->stream->mall_stream_config.paired_stream->timing;
- uint32_t out_num, out_den;
+ uint32_t out_num_stream, out_den_stream, out_num_plane, out_den_plane,
out_num, out_den;
pipe_data->mode = SUBVP;
pipe_data->pipe_config.subvp_data.pix_clk_100hz =
subvp_pipe->stream->timing.pix_clk_100hz;
@@ -649,8 +649,14 @@ static void populate_subvp_cmd_pipe_info(struct dc *dc,
/* Calculate the scaling factor from the src and dst height.
* e.g. If 3840x2160 being downscaled to 1920x1080, the scaling factor
is 1/2.
* Reduce the fraction 1080/2160 = 1/2 for the "scaling factor"
+*
+* Make sure to combine stream and plane scaling together.
*/
- reduce_fraction(subvp_pipe->stream->src.height,
subvp_pipe->stream->dst.height, _num, _den);
+ reduce_fraction(subvp_pipe->stream->src.height,
subvp_pipe->stream->dst.height,
+ _num_stream, _den_stream);
+ reduce_fraction(subvp_pipe->plane_state->src_rect.height,
subvp_pipe->plane_state->dst_rect.height,
+ _num_plane, _den_plane);
+ reduce_fraction(out_num_stream * out_num_plane, out_den_stream *
out_den_plane, _num, _den);
pipe_data->pipe_config.subvp_data.scale_factor_numerator = out_num;
pipe_data->pipe_config.subvp_data.scale_factor_denominator = out_den;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index e72213a20e75..23a661f541a5 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -1796,7 +1796,11 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc,
struct dc_state *context,
context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom =
get_fraction_of_urgent_bandwidth(>bw_ctx.dml, pipes, pipe_cnt) * 1000;
context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip =
get_fraction_of_urgent_bandwidth_imm_flip(>bw_ctx.dml, pipes,
pipe_cnt) * 1000;
context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns =
get_urgent_latency(>bw_ctx.dml, pipes, pipe_cnt) * 1000;
- context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.fclk_pstate_change_ns
= get_fclk_watermark(>bw_ctx.dml, pipes, pipe_cnt) * 1000;
+ /* On DCN32/321, PMFW will set PSTATE_CHANGE_TYPE = 1 (FCLK) for UCLK
dummy p-state.
+* In this case we must program FCLK WM Set C to use the UCLK dummy
p-state WM
+* value.
+*/
+ context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.fclk_pstate_change_ns
= get_wm_dram_clock_change(>bw_ctx.dml, pipes, pipe_cnt) * 1000;
context->bw_ctx.bw.dcn.watermarks.c.usr_retraining_ns =
get_usr_retraining_watermark(>bw_ctx.dml, pipes, pipe_cnt) * 1000;
if ((!pstate_en) &&
(dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid)) {
--
2.25.1
[PATCH 16/33] drm/amd/display: Add support for visual confirm color
From: "Leo (Hanghong) Ma"
[Why]
We want to get the visual confirm color of the bottom-most pipe
for test automation.
[How]
Save the visual confirm color to plane_state before program to MPC;
Reviewed-by: Anthony Koo
Reviewed-by: Aric Cyr
Acked-by: Brian Chang
Signed-off-by: Leo (Hanghong) Ma
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 31 +
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h | 1 +
.../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 4 +-
.../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 4 +-
drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 1 +
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 44 +++
7 files changed, 84 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index eef38d2e4753..a53863bddee0 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -1184,6 +1184,7 @@ struct dc_plane_state {
/* private to dc_surface.c */
enum dc_irq_source irq_source;
struct kref refcount;
+ struct tg_color visual_confirm_color;
};
struct dc_plane_info {
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
index cd7225d98b3d..61dfe5358d1c 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
@@ -387,6 +387,37 @@ void dc_dmub_srv_query_caps_cmd(struct dmub_srv *dmub)
}
}
+void dc_dmub_srv_get_visual_confirm_color_cmd(struct dc *dc, struct pipe_ctx
*pipe_ctx)
+{
+ union dmub_rb_cmd cmd = { 0 };
+ enum dmub_status status;
+ unsigned int panel_inst = 0;
+
+ dc_get_edp_link_panel_inst(dc, pipe_ctx->stream->link, _inst);
+
+ memset(, 0, sizeof(cmd));
+
+ // Prepare fw command
+ cmd.visual_confirm_color.header.type =
DMUB_CMD__GET_VISUAL_CONFIRM_COLOR;
+ cmd.visual_confirm_color.header.sub_type = 0;
+ cmd.visual_confirm_color.header.ret_status = 1;
+ cmd.visual_confirm_color.header.payload_bytes = sizeof(struct
dmub_cmd_visual_confirm_color_data);
+
cmd.visual_confirm_color.visual_confirm_color_data.visual_confirm_color.panel_inst
= panel_inst;
+
+ // Send command to fw
+ status = dmub_srv_cmd_with_reply_data(dc->ctx->dmub_srv->dmub, );
+
+ ASSERT(status == DMUB_STATUS_OK);
+
+ // If command was processed, copy feature caps to dmub srv
+ if (status == DMUB_STATUS_OK &&
+ cmd.visual_confirm_color.header.ret_status == 0) {
+ memcpy(>ctx->dmub_srv->dmub->visual_confirm_color,
+ _confirm_color.visual_confirm_color_data,
+ sizeof(struct dmub_visual_confirm_color));
+ }
+}
+
#ifdef CONFIG_DRM_AMD_DC_DCN
/**
*
***
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
index 159782cd6659..9f5b47b9a83d 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
@@ -78,6 +78,7 @@ void dc_dmub_srv_set_drr_manual_trigger_cmd(struct dc *dc,
uint32_t tg_inst);
bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool enable_pstate, struct
dc_state *context);
void dc_dmub_srv_query_caps_cmd(struct dmub_srv *dmub);
+void dc_dmub_srv_get_visual_confirm_color_cmd(struct dc *dc, struct pipe_ctx
*pipe_ctx);
void dc_dmub_srv_clear_inbox0_ack(struct dc_dmub_srv *dmub_srv);
void dc_dmub_srv_wait_for_inbox0_ack(struct dc_dmub_srv *dmub_srv);
void dc_dmub_srv_send_inbox0_cmd(struct dc_dmub_srv *dmub_srv, union
dmub_inbox0_data_register data);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 2118ad3e37d0..d3f6a2609c8c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2539,8 +2539,10 @@ void dcn10_update_visual_confirm_color(struct dc *dc,
struct pipe_ctx *pipe_ctx,
color_space_to_black_color(
dc, pipe_ctx->stream->output_color_space,
color);
- if (mpc->funcs->set_bg_color)
+ if (mpc->funcs->set_bg_color) {
+ memcpy(_ctx->plane_state->visual_confirm_color, color,
sizeof(struct tg_color));
mpc->funcs->set_bg_color(mpc, color, mpcc_id);
+ }
}
void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 4b4368456477..6271caca4d9a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -2468,8 +2468,10 @@ void
[PATCH 15/33] drm/amd/display: Add visual confirm color support for SubVP
From: "Leo (Hanghong) Ma"
[Why && How]
We would like to have visual confirm color support for SubVP.
1. Set visual confirm color to red: SubVP is enable on this
display;
2. Set visual confirm color to green: SubVP is enable on
other display and DRR is on this display;
3. Set visual confirm color to blue: SubVP is enable on
other display and DRR is off on this display;
Reviewed-by: Alvin Lee
Acked-by: Brian Chang
Signed-off-by: Leo (Hanghong) Ma
---
.../drm/amd/display/dc/core/dc_hw_sequencer.c | 38 +++
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
.../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 2 +
.../gpu/drm/amd/display/dc/inc/hw_sequencer.h | 5 +++
4 files changed, 46 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
index 2a8007928210..9dd705b985b9 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
@@ -402,6 +402,44 @@ void get_hdr_visual_confirm_color(
}
}
+void get_subvp_visual_confirm_color(
+ struct dc *dc,
+ struct pipe_ctx *pipe_ctx,
+ struct tg_color *color)
+{
+ uint32_t color_value = MAX_TG_COLOR_VALUE;
+ bool enable_subvp = false;
+ int i;
+
+ if (!dc->ctx || !dc->ctx->dmub_srv || !pipe_ctx)
+ return;
+
+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ struct pipe_ctx *pipe = >current_state->res_ctx.pipe_ctx[i];
+
+ if (pipe->stream && pipe->stream->mall_stream_config.paired_stream &&
+ pipe->stream->mall_stream_config.type ==
SUBVP_MAIN) {
+ /* SubVP enable - red */
+ color->color_r_cr = color_value;
+ enable_subvp = true;
+
+ if (pipe_ctx->stream == pipe->stream)
+ return;
+ break;
+ }
+ }
+
+ if (enable_subvp && pipe_ctx->stream->mall_stream_config.type ==
SUBVP_NONE) {
+ color->color_r_cr = 0;
+ if (pipe_ctx->stream->ignore_msa_timing_param == 1)
+ /* SubVP enable and DRR on - green */
+ color->color_g_y = color_value;
+ else
+ /* SubVP enable and No DRR - blue */
+ color->color_b_cb = color_value;
+ }
+}
+
void get_surface_tile_visual_confirm_color(
struct pipe_ctx *pipe_ctx,
struct tg_color *color)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index cffb91363b52..eef38d2e4753 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -417,6 +417,7 @@ enum visual_confirm {
VISUAL_CONFIRM_SWAPCHAIN = 6,
VISUAL_CONFIRM_FAMS = 7,
VISUAL_CONFIRM_SWIZZLE = 9,
+ VISUAL_CONFIRM_SUBVP = 14,
};
enum dc_psr_power_opts {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index cf439ed270de..4b4368456477 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -2465,6 +2465,8 @@ void dcn20_update_visual_confirm_color(struct dc *dc,
struct pipe_ctx *pipe_ctx,
get_mpctree_visual_confirm_color(pipe_ctx, color);
else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SWIZZLE)
get_surface_tile_visual_confirm_color(pipe_ctx, color);
+ else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SUBVP)
+ get_subvp_visual_confirm_color(dc, pipe_ctx, color);
if (mpc->funcs->set_bg_color)
mpc->funcs->set_bg_color(mpc, color, mpcc_id);
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index a4e02b0ace24..8df493572a9a 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -272,6 +272,11 @@ const uint16_t *find_color_matrix(
void get_surface_visual_confirm_color(
const struct pipe_ctx *pipe_ctx,
struct tg_color *color);
+
+void get_subvp_visual_confirm_color(
+ struct dc *dc,
+ struct pipe_ctx *pipe_ctx,
+ struct tg_color *color);
void get_hdr_visual_confirm_color(
struct pipe_ctx *pipe_ctx,
--
2.25.1
[PATCH 13/33] drm/amd/display: Cleanup PSR flag
From: Gabe Teeger
[Why]
enable_sw_cntl_psr flag is not needed.
For PSR1 and PSR2, we should be passing
dirty rectangle and cursor updates to FW
regardless of enable_sw_cntl_psr flag.
[How]
Remove enable_sw_cntl_psr flag from driver.
Send cursor info and dirty rectagle status to
dmub only in the case of dcn31 and above.
Reviewed-by: Anthony Koo
Reviewed-by: Robin Chen
Acked-by: Brian Chang
Signed-off-by: Gabe Teeger
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 8 +++-
drivers/gpu/drm/amd/display/dc/dc.h | 1 -
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 3 ++-
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c | 1 -
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c | 1 -
drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c | 1 -
drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c | 1 -
7 files changed, 5 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 95daee11a445..1ca76708705b 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -3113,11 +3113,9 @@ static void commit_planes_do_stream_update(struct dc *dc,
static bool dc_dmub_should_send_dirty_rect_cmd(struct dc *dc, struct
dc_stream_state *stream)
{
- if (stream->link->psr_settings.psr_version == DC_PSR_VERSION_SU_1)
- return true;
-
- if (stream->link->psr_settings.psr_version == DC_PSR_VERSION_1 &&
- dc->debug.enable_sw_cntl_psr)
+ if ((stream->link->psr_settings.psr_version == DC_PSR_VERSION_SU_1
+ || stream->link->psr_settings.psr_version ==
DC_PSR_VERSION_1)
+ && stream->ctx->dce_version >= DCN_VERSION_3_1)
return true;
return false;
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 473e6a0c3310..cffb91363b52 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -827,7 +827,6 @@ struct dc_debug_options {
int crb_alloc_policy_min_disp_count;
bool disable_z10;
bool enable_z9_disable_interface;
- bool enable_sw_cntl_psr;
union dpia_debug_options dpia_debug;
bool disable_fixed_vs_aux_timeout_wa;
bool force_disable_subvp;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 1eb3957f52a3..2118ad3e37d0 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -3343,7 +3343,8 @@ static bool dcn10_dmub_should_update_cursor_data(
if (dcn10_can_pipe_disable_cursor(pipe_ctx))
return false;
- if (pipe_ctx->stream->link->psr_settings.psr_version ==
DC_PSR_VERSION_SU_1 || pipe_ctx->stream->link->psr_settings.psr_version ==
DC_PSR_VERSION_1)
+ if ((pipe_ctx->stream->link->psr_settings.psr_version ==
DC_PSR_VERSION_SU_1 || pipe_ctx->stream->link->psr_settings.psr_version ==
DC_PSR_VERSION_1)
+ && pipe_ctx->stream->ctx->dce_version >=
DCN_VERSION_3_1)
return true;
return false;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
index aedff18aff56..8745132d6374 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
@@ -889,7 +889,6 @@ static const struct dc_debug_options debug_defaults_drv = {
},
.disable_z10 = true,
.optimize_edp_link_rate = true,
- .enable_sw_cntl_psr = true,
.enable_z9_disable_interface = true, /* Allow support for the PMFW
interface for disable Z9*/
.dml_hostvm_override = DML_HOSTVM_OVERRIDE_FALSE,
};
diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
index 3a9e3870b3a9..5e62527d3ab9 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
@@ -911,7 +911,6 @@ static const struct dc_debug_options debug_defaults_drv = {
}
},
.optimize_edp_link_rate = true,
- .enable_sw_cntl_psr = true,
.seamless_boot_odm_combine = true
};
diff --git a/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
index 7463b12ae4a3..eebb42c9ddd6 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
@@ -886,7 +886,6 @@ static const struct dc_debug_options debug_defaults_drv = {
}
},
.optimize_edp_link_rate = true,
- .enable_sw_cntl_psr = true,
.psr_power_use_phy_fsm = 0,
};
[PATCH 14/33] drm/amd/display: Allow PHY state update between same states
From: Taimur Hassan
[Why & How]
In some cases, there are calls to transition from TX_ON to TX_ON, such as
when using MST or during resolution change. This is expected, so allow HW
programming to continue.
Reviewed-by: Alvin Lee
Acked-by: Brian Chang
Signed-off-by: Taimur Hassan
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
index b7556111ee44..63648e2056a0 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
@@ -1224,9 +1224,6 @@ void dcn32_update_phy_state(struct dc_state *state,
struct pipe_ctx *pipe_ctx,
{
enum phy_state current_state = pipe_ctx->stream->link->phy_state;
- if (current_state == target_state)
- return;
-
if (target_state == TX_OFF_SYMCLK_OFF) {
core_link_disable_stream(pipe_ctx);
pipe_ctx->stream->link->phy_state = TX_OFF_SYMCLK_OFF;
--
2.25.1
[PATCH 11/33] drm/amd/display: Add DC debug option to force LTTPR mode
From: Michael Strauss
[WHY]
Useful for external teams debugging LTTPR issues
Reviewed-by: George Shen
Acked-by: Brian Chang
Signed-off-by: Michael Strauss
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 4
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 8617de559174..7e97265b76e8 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -5032,6 +5032,10 @@ static void determine_lttpr_mode(struct dc_link *link)
bool vbios_lttpr_enable = link->dc->caps.vbios_lttpr_enable;
bool vbios_lttpr_interop = link->dc->caps.vbios_lttpr_aware;
+ if (link->ctx->dc->debug.lttpr_mode_override != 0) {
+ link->lttpr_mode = link->ctx->dc->debug.lttpr_mode_override;
+ return;
+ }
if ((link->dc->config.allow_lttpr_non_transparent_mode.bits.DP2_0 &&
link->dpcd_caps.channel_coding_cap.bits.DP_128b_132b_SUPPORTED)) {
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 2362d5ee2401..473e6a0c3310 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -846,6 +846,7 @@ struct dc_debug_options {
bool exit_idle_opt_for_cursor_updates;
bool enable_single_display_2to1_odm_policy;
bool enable_dp_dig_pixel_rate_div_policy;
+ enum lttpr_mode lttpr_mode_override;
};
struct gpu_info_soc_bounding_box_v1_0;
--
2.25.1
[PATCH 10/33] drm/amd/display: add a override flag as wa for some specific dongle
From: "Chen, Leo"
[Why & How]
Add a override flag as wa for some specific dongle
Co-authored-by: Leo Chen
Reviewed-by: Charlene Liu
Reviewed-by: Charlene Liu
Acked-by: Brian Chang
Signed-off-by: Leo Chen
---
drivers/gpu/drm/amd/display/dc/dc_link.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h
b/drivers/gpu/drm/amd/display/dc/dc_link.h
index b18efe988830..d1214944839f 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_link.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
@@ -224,6 +224,7 @@ struct dc_link {
bool dpia_mst_dsc_always_on;
/* Forced DPIA into TBT3 compatibility mode. */
bool dpia_forced_tbt3_mode;
+ bool dongle_mode_timing_override;
} wa_flags;
struct link_mst_stream_allocation_table mst_stream_alloc_table;
--
2.25.1
[PATCH 12/33] drm/amd/display: Cursor lag with PSR1 eDP
From: Gabe Teeger [Why] On edp with psr1, we do not provide updates of the cursor position regularly to firmware like with PSR2. To send updates regularly, the flag enable_sw_cntl_psr has to equal 1, but cursor update should be provided regularly to FW regardless of that flag. [How] Ensure that we always send cursor updates to firmware when PSR version equals 1. Reviewed-by: Robin Chen Acked-by: Brian Chang Signed-off-by: Gabe Teeger --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 6 +- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 37246e965457..1eb3957f52a3 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -3343,11 +3343,7 @@ static bool dcn10_dmub_should_update_cursor_data( if (dcn10_can_pipe_disable_cursor(pipe_ctx)) return false; - if (pipe_ctx->stream->link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) - return true; - - if (pipe_ctx->stream->link->psr_settings.psr_version == DC_PSR_VERSION_1 && - debug->enable_sw_cntl_psr) + if (pipe_ctx->stream->link->psr_settings.psr_version == DC_PSR_VERSION_SU_1 || pipe_ctx->stream->link->psr_settings.psr_version == DC_PSR_VERSION_1) return true; return false; -- 2.25.1
[PATCH 09/33] drm/amd/display: Only commit SubVP state after pipe programming
From: Alvin Lee
[Description]
We only want to commit the SubVP config to DMCUB
after the main and phantom pipe programming has
completed. Commiting the state early can cause
issues such as P-State being allowed by the HW
early which causes the SubVP state machine to
go into a bad state
Reviewed-by: Jun Lei
Acked-by: Brian Chang
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 15 +++
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index ced09f875e58..95daee11a445 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -,10 +,6 @@ static void commit_planes_for_stream(struct dc *dc,
if (dc->hwss.program_front_end_for_ctx)
dc->hwss.program_front_end_for_ctx(dc, context);
- if (update_type != UPDATE_TYPE_FAST)
- if (dc->hwss.commit_subvp_config)
- dc->hwss.commit_subvp_config(dc, context);
-
if (should_lock_all_pipes &&
dc->hwss.interdependent_update_lock) {
dc->hwss.interdependent_update_lock(dc, context, false);
} else {
@@ -3344,6 +3340,10 @@ static void commit_planes_for_stream(struct dc *dc,
}
dc->hwss.post_unlock_program_front_end(dc, context);
+ if (update_type != UPDATE_TYPE_FAST)
+ if (dc->hwss.commit_subvp_config)
+ dc->hwss.commit_subvp_config(dc, context);
+
/* Since phantom pipe programming is moved to
post_unlock_program_front_end,
* move the SubVP lock to after the phantom pipes have been
setup
*/
@@ -3477,10 +3477,6 @@ static void commit_planes_for_stream(struct dc *dc,
}
- if (update_type != UPDATE_TYPE_FAST)
- if (dc->hwss.commit_subvp_config)
- dc->hwss.commit_subvp_config(dc, context);
-
if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) {
dc->hwss.interdependent_update_lock(dc, context, false);
} else {
@@ -3517,6 +3513,9 @@ static void commit_planes_for_stream(struct dc *dc,
if (update_type != UPDATE_TYPE_FAST)
dc->hwss.post_unlock_program_front_end(dc, context);
+ if (update_type != UPDATE_TYPE_FAST)
+ if (dc->hwss.commit_subvp_config)
+ dc->hwss.commit_subvp_config(dc, context);
/* Since phantom pipe programming is moved to
post_unlock_program_front_end,
* move the SubVP lock to after the phantom pipes have been setup
--
2.25.1
[PATCH 08/33] drm/amd/display: Remove assert from PHY state update
From: Taimur Hassan
[Why & How]
In some cases, there are calls to transition from TX_ON to TX_ON. This is
expected, so do not assert. However, these are redundant, so return
prematurely.
Reviewed-by: Alvin Lee
Acked-by: Brian Chang
Signed-off-by: Taimur Hassan
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
index 3b1c6603ae0c..b7556111ee44 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
@@ -1224,10 +1224,8 @@ void dcn32_update_phy_state(struct dc_state *state,
struct pipe_ctx *pipe_ctx,
{
enum phy_state current_state = pipe_ctx->stream->link->phy_state;
- if (current_state == target_state) {
- BREAK_TO_DEBUGGER();
+ if (current_state == target_state)
return;
- }
if (target_state == TX_OFF_SYMCLK_OFF) {
core_link_disable_stream(pipe_ctx);
--
2.25.1
[PATCH 07/33] drm/amd/display: set dig fifo read start level to 7 before dig fifo reset
From: Wang Fudong [Why] DIG_FIFO_ERROR = 1 caused mst daisy chain 2nd monitor black. [How] We need to set dig fifo read start level = 7 before dig fifo reset during dig fifo enable according to hardware designer's suggestion. If it is zero, it will cause underflow or overflow and DIG_FIFO_ERROR = 1. Reviewed-by: Alvin Lee Reviewed-by: Aric Cyr Acked-by: Brian Chang Signed-off-by: Wang Fudong --- .../gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c index 26648ce772da..38a48983f663 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c @@ -310,6 +310,11 @@ static void enc32_stream_encoder_dp_unblank( // TODO: Confirm if we need to wait for DIG_SYMCLK_FE_ON REG_WAIT(DIG_FE_CNTL, DIG_SYMCLK_FE_ON, 1, 10, 5000); + /* read start level = 0 will bring underflow / overflow and DIG_FIFO_ERROR = 1 +* so set it to 1/2 full = 7 before reset as suggested by hardware team. +*/ + REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_READ_START_LEVEL, 0x7); + REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, 1); REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, 1, 10, 5000); -- 2.25.1
[PATCH 06/33] drm/amd/display: add dcn35 basic support
From: Charlene Liu
[why]
this is to add new dcn frame work
Reviewed-by: Hansen Dsouza
Acked-by: Brian Chang
Signed-off-by: Charlene Liu
---
.../gpu/drm/amd/display/dc/clk_mgr/Makefile.rej | 17 +
drivers/gpu/drm/amd/display/dc/dce/dce_abm.h| 9 ++---
.../amd/display/dc/dcn10/dcn10_stream_encoder.h | 1 +
.../gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h| 3 ++-
.../dc/dcn31/dcn31_hpo_dp_link_encoder.h| 10 --
drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 3 ++-
drivers/gpu/drm/amd/display/include/dal_types.h | 1 +
7 files changed, 37 insertions(+), 7 deletions(-)
create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile.rej
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile.rej
b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile.rej
new file mode 100644
index ..bfbfd67a7451
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile.rej
@@ -0,0 +1,17 @@
+diff a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile (rejected hunks)
+@@ -160,6 +160,15 @@ AMD_DAL_CLK_MGR_DCN32 = $(addprefix
$(AMDDALPATH)/dc/clk_mgr/dcn32/,$(CLK_MGR_DC
+
+ AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN32)
+
++
++###
++# DCN35
++###
++CLK_MGR_DCN35 = dcn35_smu.o dcn35_clk_mgr.o
++
++AMD_DAL_CLK_MGR_DCN35 = $(addprefix
$(AMDDALPATH)/dc/clk_mgr/dcn35/,$(CLK_MGR_DCN35))
++
++AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN35)
+
###
+ # DCN3AG
+
###
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
index e6c06325742a..a3c27cbb77c8 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
@@ -183,8 +183,7 @@
ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \
ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh)
-#define ABM_MASK_SH_LIST_DCN10(mask_sh) \
- ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
+#define ABM_MASK_SH_LIST_DCN10_COMMON(mask_sh) \
ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \
ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
@@ -214,9 +213,13 @@
ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh)
-#define ABM_MASK_SH_LIST_DCN20(mask_sh) ABM_MASK_SH_LIST_DCE110(mask_sh)
+#define ABM_MASK_SH_LIST_DCN10(mask_sh) \
+ ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
+ ABM_MASK_SH_LIST_DCN10_COMMON(mask_sh)
+#define ABM_MASK_SH_LIST_DCN20(mask_sh) ABM_MASK_SH_LIST_DCE110(mask_sh)
#define ABM_MASK_SH_LIST_DCN30(mask_sh) ABM_MASK_SH_LIST_DCN10(mask_sh)
+#define ABM_MASK_SH_LIST_DCN35(mask_sh) ABM_MASK_SH_LIST_DCN10_COMMON(mask_sh)
#define ABM_MASK_SH_LIST_DCN32(mask_sh) \
ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
index 9d5e2a7848dd..3f9582b4cc79 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
@@ -188,6 +188,7 @@ struct dcn10_stream_enc_registers {
uint32_t HDMI_GENERIC_PACKET_CONTROL10;
uint32_t DIG_CLOCK_PATTERN;
uint32_t DIG_FIFO_CTRL0;
+ uint32_t DIG_FE_CLK_CNTL;
};
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h
index 6263408d71fc..815169e08e5b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h
@@ -172,7 +172,8 @@
SRI(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R, CM, id),\
SRI(CM_BLNDGAM_LUT_CONTROL, CM, id)
-
+#define DPP_REG_LIST_DCN35(id)\
+ DPP_REG_LIST_DCN30_COMMON(id)
#define DPP_REG_LIST_SH_MASK_DCN30_COMMON(mask_sh)\
TF_SF(CM0_CM_MEM_PWR_STATUS, GAMCOR_MEM_PWR_STATE, mask_sh),\
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_link_encoder.h
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_link_encoder.h
index e324e9b83136..51f5781325e8 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_link_encoder.h
@@ -104,7 +104,10 @@ struct dcn31_hpo_dp_link_encoder_registers {
uint32_t RDPCSTX_PHY_CNTL6[5];
};
-#define DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(mask_sh)\
+#define DCN3_1_HPO_DP_LINK_ENC_RDPCSTX_MASK_SH_LIST(mask_sh)\
+ SE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, mask_sh)
+
+#define DCN3_1_HPO_DP_LINK_ENC_COMMON_MASK_SH_LIST(mask_sh)\
[PATCH 05/33] drm/amd/display: Fix OTG H timing reset for dcn314
From: Duncan Ma [Why] When ODM is enabled, H timing control register reset to 0. Div mode manual field get overwritten causing no display on certain modes for dcn314. [How] Use REG_UPDATE instead of REG_SET to set div_mode field. Reviewed-by: Charlene Liu Reviewed-by: Nicholas Kazlauskas Acked-by: Brian Chang Signed-off-by: Duncan Ma --- drivers/gpu/drm/amd/display/dc/dcn314/dcn314_optc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_optc.c b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_optc.c index 0c7980266b85..38aa28ec6b13 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_optc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_optc.c @@ -98,7 +98,8 @@ static void optc314_set_odm_combine(struct timing_generator *optc, int *opp_id, REG_UPDATE(OPTC_WIDTH_CONTROL, OPTC_SEGMENT_WIDTH, mpcc_hactive); - REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_MODE, opp_cnt - 1); + REG_UPDATE(OTG_H_TIMING_CNTL, + OTG_H_TIMING_DIV_MODE, opp_cnt - 1); optc1->opp_count = opp_cnt; } -- 2.25.1
[PATCH 04/33] drm/amd/display: Refine aux transaction before retrieve caps
From: Lewis Huang
[Why]
LTTPR caps will read fail if aux channel is not active.
[How]
1.Perform 600 read upto 10 retry with 1ms delay in between.
2.If fail, return false and trigger another retry detection.
3.If pass, read LTTPR caps in retrieve link caps.
Reviewed-by: Jimmy Kizito
Acked-by: Brian Chang
Signed-off-by: Lewis Huang
---
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 45 ++-
1 file changed, 34 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 2b7bb3a796e8..8617de559174 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -5275,6 +5275,7 @@ static bool retrieve_link_cap(struct dc_link *link)
union dp_downstream_port_present ds_port = { 0 };
enum dc_status status = DC_ERROR_UNEXPECTED;
uint32_t read_dpcd_retry_cnt = 3;
+ uint32_t aux_channel_retry_cnt = 0;
int i;
struct dp_sink_hw_fw_revision dp_hw_fw_revision;
const uint32_t post_oui_delay = 30; // 30ms
@@ -5302,21 +5303,43 @@ static bool retrieve_link_cap(struct dc_link *link)
status = wa_try_to_wake_dprx(link, timeout_ms);
}
+ while (status != DC_OK && aux_channel_retry_cnt < 10) {
+ status = core_link_read_dpcd(link, DP_SET_POWER,
+ _power_state, sizeof(dpcd_power_state));
+
+ /* Delay 1 ms if AUX CH is in power down state. Based on spec
+* section 2.3.1.2, if AUX CH may be powered down due to
+* write to DPCD 600h = 2. Sink AUX CH is monitoring
differential
+* signal and may need up to 1 ms before being able to reply.
+*/
+ if (status != DC_OK || dpcd_power_state == DP_SET_POWER_D3) {
+ udelay(1000);
+ aux_channel_retry_cnt++;
+ }
+ }
+
+ /* If aux channel is not active, return false and trigger another
detect*/
+ if (status != DC_OK) {
+ dpcd_power_state = DP_SET_POWER_D0;
+ status = core_link_write_dpcd(
+ link,
+ DP_SET_POWER,
+ _power_state,
+ sizeof(dpcd_power_state));
+
+ dpcd_power_state = DP_SET_POWER_D3;
+ status = core_link_write_dpcd(
+ link,
+ DP_SET_POWER,
+ _power_state,
+ sizeof(dpcd_power_state));
+ return false;
+ }
+
is_lttpr_present = dp_retrieve_lttpr_cap(link);
/* Read DP tunneling information. */
status = dpcd_get_tunneling_device_data(link);
- status = core_link_read_dpcd(link, DP_SET_POWER,
- _power_state, sizeof(dpcd_power_state));
-
- /* Delay 1 ms if AUX CH is in power down state. Based on spec
-* section 2.3.1.2, if AUX CH may be powered down due to
-* write to DPCD 600h = 2. Sink AUX CH is monitoring differential
-* signal and may need up to 1 ms before being able to reply.
-*/
- if (status != DC_OK || dpcd_power_state == DP_SET_POWER_D3)
- udelay(1000);
-
dpcd_set_source_specific_data(link);
/* Sink may need to configure internals based on vendor, so allow some
* time before proceeding with possibly vendor specific transactions
--
2.25.1
[PATCH 03/33] drm/amd/display: Fix DCN32 DPSTREAMCLK_CNTL programming
From: George Shen [Why] Each index in the DPSTREAMCLK_CNTL register phyiscally maps 1-to-1 with HPO stream encoder instance. On the other hand, each index in DTBCLK_P_CNTL physically maps 1-to-1 with OTG instance. Current DCN32 DPSTREAMCLK_CLK programing assumes that OTG instance always maps 1-to-1 with HPO stream encoder instance. This is not always guaranteed and can result in blackscreen. [How] Program the correct dpstreamclk instance with the correct dtbclk_p source. Reviewed-by: Ariel Bernstein Acked-by: Brian Chang Signed-off-by: George Shen --- drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c | 8 drivers/gpu/drm/amd/display/dc/link/link_hwss_hpo_dp.c | 4 ++-- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c index a31c64b50410..0d5e8a441512 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c @@ -225,19 +225,19 @@ void dccg32_set_dpstreamclk( case 0: REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK0_EN, -(src == REFCLK) ? 0 : 1, DPSTREAMCLK0_SRC_SEL, 0); +(src == REFCLK) ? 0 : 1, DPSTREAMCLK0_SRC_SEL, otg_inst); break; case 1: REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK1_EN, -(src == REFCLK) ? 0 : 1, DPSTREAMCLK1_SRC_SEL, 1); +(src == REFCLK) ? 0 : 1, DPSTREAMCLK1_SRC_SEL, otg_inst); break; case 2: REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK2_EN, -(src == REFCLK) ? 0 : 1, DPSTREAMCLK2_SRC_SEL, 2); +(src == REFCLK) ? 0 : 1, DPSTREAMCLK2_SRC_SEL, otg_inst); break; case 3: REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK3_EN, -(src == REFCLK) ? 0 : 1, DPSTREAMCLK3_SRC_SEL, 3); +(src == REFCLK) ? 0 : 1, DPSTREAMCLK3_SRC_SEL, otg_inst); break; default: BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/link/link_hwss_hpo_dp.c b/drivers/gpu/drm/amd/display/dc/link/link_hwss_hpo_dp.c index db7b0b155374..226af06278ce 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_hwss_hpo_dp.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_hwss_hpo_dp.c @@ -116,7 +116,7 @@ static void setup_hpo_dp_stream_encoder(struct pipe_ctx *pipe_ctx) dto_params.timing = _ctx->stream->timing; dto_params.ref_dtbclk_khz = dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(dc->clk_mgr); - dccg->funcs->set_dpstreamclk(dccg, DTBCLK0, tg->inst, link_enc->inst); + dccg->funcs->set_dpstreamclk(dccg, DTBCLK0, tg->inst, stream_enc->inst); dccg->funcs->enable_symclk32_se(dccg, stream_enc->inst, phyd32clk); dccg->funcs->set_dtbclk_dto(dccg, _params); stream_enc->funcs->enable_stream(stream_enc); @@ -137,7 +137,7 @@ static void reset_hpo_dp_stream_encoder(struct pipe_ctx *pipe_ctx) stream_enc->funcs->disable(stream_enc); dccg->funcs->set_dtbclk_dto(dccg, _params); dccg->funcs->disable_symclk32_se(dccg, stream_enc->inst); - dccg->funcs->set_dpstreamclk(dccg, REFCLK, tg->inst, pipe_ctx->link_res.hpo_dp_link_enc->inst); + dccg->funcs->set_dpstreamclk(dccg, REFCLK, tg->inst, stream_enc->inst); } static void setup_hpo_dp_stream_attribute(struct pipe_ctx *pipe_ctx) -- 2.25.1
[PATCH 02/33] drm/amd/display: Don't choose SubVP display if ActiveMargin > 0
From: Alvin Lee
[Description]
There can be SubVP scheduling issues if a SubVP
display is chosen has ActiveDramClockChangeLatency > 0.
Block this case for now, and enable Vactive case
(later) to handle this.
Reviewed-by: Jun Lei
Acked-by: Brian Chang
Signed-off-by: Alvin Lee
---
.../drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 21 ---
.../dc/dml/dcn32/display_mode_vba_32.c| 2 +-
.../drm/amd/display/dc/dml/display_mode_vba.h | 1 +
3 files changed, 20 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index edefb3fc1c3c..e72213a20e75 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -560,6 +560,7 @@ static bool dcn32_assign_subvp_pipe(struct dc *dc,
bool valid_assignment_found = false;
unsigned int free_pipes = dcn32_get_num_free_pipes(dc, context);
bool current_assignment_freesync = false;
+ struct vba_vars_st *vba = >bw_ctx.dml.vba;
for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe = >res_ctx.pipe_ctx[i];
@@ -573,8 +574,15 @@ static bool dcn32_assign_subvp_pipe(struct dc *dc,
refresh_rate = (pipe->stream->timing.pix_clk_100hz * 100 +
pipe->stream->timing.v_total *
pipe->stream->timing.h_total - 1)
/ (double)(pipe->stream->timing.v_total *
pipe->stream->timing.h_total);
+ /* SubVP pipe candidate requirements:
+* - Refresh rate < 120hz
+* - Not able to switch in vactive naturally (switching in
active means the
+* DET provides enough buffer to hide the P-State switch
latency -- trying
+* to combine this with SubVP can cause issues with the
scheduling).
+*/
if (pipe->plane_state && !pipe->top_pipe &&
- pipe->stream->mall_stream_config.type ==
SUBVP_NONE && refresh_rate < 120) {
+ pipe->stream->mall_stream_config.type ==
SUBVP_NONE && refresh_rate < 120 &&
+
vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]]
<= 0) {
while (pipe) {
num_pipes++;
pipe = pipe->bottom_pipe;
@@ -998,8 +1006,10 @@ static void dcn32_full_validate_bw_helper(struct dc *dc,
*vlevel = dml_get_voltage_level(>bw_ctx.dml, pipes, *pipe_cnt);
/* This may adjust vlevel and maxMpcComb */
- if (*vlevel < context->bw_ctx.dml.soc.num_states)
+ if (*vlevel < context->bw_ctx.dml.soc.num_states) {
*vlevel = dcn20_validate_apply_pipe_split_flags(dc, context,
*vlevel, split, merge);
+ vba->VoltageLevel = *vlevel;
+ }
/* Conditions for setting up phantom pipes for SubVP:
* 1. Not force disable SubVP
@@ -1085,13 +1095,16 @@ static void dcn32_full_validate_bw_helper(struct dc *dc,
*vlevel = dml_get_voltage_level(>bw_ctx.dml,
pipes, *pipe_cnt);
/* This may adjust vlevel and maxMpcComb */
- if (*vlevel < context->bw_ctx.dml.soc.num_states)
+ if (*vlevel < context->bw_ctx.dml.soc.num_states) {
*vlevel =
dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge);
+ vba->VoltageLevel = *vlevel;
+ }
} else {
// only call dcn20_validate_apply_pipe_split_flags if
we found a supported config
memset(split, 0, MAX_PIPES * sizeof(int));
memset(merge, 0, MAX_PIPES * sizeof(bool));
*vlevel = dcn20_validate_apply_pipe_split_flags(dc,
context, *vlevel, split, merge);
+ vba->VoltageLevel = *vlevel;
// Most populate phantom DLG params before programming
hardware / timing for phantom pipe
DC_FP_START();
@@ -1421,6 +1434,8 @@ bool dcn32_internal_validate_bw(struct dc *dc,
memset(split, 0, sizeof(split));
memset(merge, 0, sizeof(merge));
vlevel = dcn20_validate_apply_pipe_split_flags(dc,
context, vlevel, split, merge);
+ // dcn20_validate_apply_pipe_split_flags can modify
voltage level outside of DML
+ vba->VoltageLevel = vlevel;
}
}
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
index f831855db022..3040428a7304 100644
---
[PATCH 01/33] drm/amd/display: Set ODM policy based on number of DSC slices
From: Taimur Hassan
[Why & How]
Add addtional check in CalculateODMMode for cases where the ODM combine
is needed due to number of DSC slices.
Reviewed-by: Alvin Lee
Acked-by: Brian Chang
Signed-off-by: Taimur Hassan
---
.../gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c | 2 ++
.../amd/display/dc/dml/dcn32/display_mode_vba_util_32.c| 7 +--
.../amd/display/dc/dml/dcn32/display_mode_vba_util_32.h| 1 +
3 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
index cb2025771646..f831855db022 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
@@ -2045,6 +2045,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct
display_mode_lib *mode_l
mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading,
mode_lib->vba.DISPCLKRampingMargin,
mode_lib->vba.DISPCLKDPPCLKVCOSpeed,
+
mode_lib->vba.NumberOfDSCSlices[k],
/* Output */
>dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.TotalAvailablePipesSupportNoDSC,
@@ -2066,6 +2067,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct
display_mode_lib *mode_l
mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading,
mode_lib->vba.DISPCLKRampingMargin,
mode_lib->vba.DISPCLKDPPCLKVCOSpeed,
+
mode_lib->vba.NumberOfDSCSlices[k],
/* Output */
>dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.TotalAvailablePipesSupportDSC,
diff --git
a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
index 05fc14a47fba..6b3c4dbb140b 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
@@ -1193,6 +1193,7 @@ void dml32_CalculateODMMode(
double DISPCLKDPPCLKDSCCLKDownSpreading,
double DISPCLKRampingMargin,
double DISPCLKDPPCLKVCOSpeed,
+ unsigned int NumberOfDSCSlices,
/* Output */
bool *TotalAvailablePipesSupport,
@@ -1228,7 +1229,8 @@ void dml32_CalculateODMMode(
if (!(Output == dm_hdmi || Output == dm_dp || Output == dm_edp) &&
(ODMUse == dm_odm_combine_policy_4to1 ||
((SurfaceRequiredDISPCLKWithODMCombineTwoToOne >
StateDispclk ||
- (DSCEnable && (HActive > 2 *
MaximumPixelsPerLinePerDSCUnit)) {
+ (DSCEnable && (HActive > 2 *
MaximumPixelsPerLinePerDSCUnit))
+ || NumberOfDSCSlices > 8 {
if (TotalNumberOfActiveDPP + 4 <= MaxNumDPP) {
*ODMMode = dm_odm_combine_mode_4to1;
*RequiredDISPCLKPerSurface =
SurfaceRequiredDISPCLKWithODMCombineFourToOne;
@@ -1239,7 +1241,8 @@ void dml32_CalculateODMMode(
} else if (Output != dm_hdmi && (ODMUse == dm_odm_combine_policy_2to1 ||
(((SurfaceRequiredDISPCLKWithoutODMCombine >
StateDispclk &&
SurfaceRequiredDISPCLKWithODMCombineTwoToOne <= StateDispclk) ||
- (DSCEnable && (HActive >
MaximumPixelsPerLinePerDSCUnit)) {
+ (DSCEnable && (HActive >
MaximumPixelsPerLinePerDSCUnit))
+ || (NumberOfDSCSlices <= 8 &&
NumberOfDSCSlices > 4) {
if (TotalNumberOfActiveDPP + 2 <= MaxNumDPP) {
*ODMMode = dm_odm_combine_mode_2to1;
*RequiredDISPCLKPerSurface =
SurfaceRequiredDISPCLKWithODMCombineTwoToOne;
diff --git
a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
index d293856ba906..626f6605e2d5 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
@@ -226,6 +226,7 @@ void dml32_CalculateODMMode(
double DISPCLKDPPCLKDSCCLKDownSpreading,
double DISPCLKRampingMargin,
double DISPCLKDPPCLKVCOSpeed,
+ unsigned int NumberOfDSCSlices,
[PATCH 00/33] DC Patches August 27 ,2022
This DC patchset brings improvements in multiple areas. In summary, we have: * Correct cursor position on horizontal mirror; * Fix black flash when switching from ODM2to1 to ODMBypass; * Fix plane and stream check; * Fix viewport after pipe merge; * Correct plane for CAB cursor; * Fix comment to correct visual confirm option; * Fix SubVP related regression; * Fix primary EDP link detection; * Fix wrong register access; * Fix cursor size allocation for DCN32/321; * Fix display fresh edge case from MALL for DCN321; * Add HPO instance; * Refactor EDP codes; * Add SubVP scaling case; * Add support for visual confirm color; * Fix PHY state update; * Cleanup PSR flag; * Fix cursor lag with PSR1 eDP; * Add DC debug optioon for LTTPR mode; * Add override flag for some dongle; * Fix SubVP state after pipe programming; * Remove assert from PHY state update; * Fix dig fifo read level before reset; * Add dcn35 basic suppoet; * Fix OTG H timming for dcn314; * Fix aux transaction; * Fix DCN32 DPSTREAMCLK_CNTL programming; * Fix SubVP scheduling issues; * Set ODM policy. Alvin Lee (3): drm/amd/display: Don't choose SubVP display if ActiveMargin > 0 drm/amd/display: Only commit SubVP state after pipe programming drm/amd/display: SubVP missing scaling case Anthony Koo (1): drm/amd/display: [FW Promotion] Release 0.0.132.0 Aric Cyr (1): drm/amd/display: 3.2.201 Aurabindo Pillai (5): drm/amd/display: Fix CAB cursor size allocation for DCN32/321 drm/amd/display: disable display fresh from MALL on an edge case for DCN321 drm/amd/display: use actual cursor size instead of max for CAB allocation drm/amd/display: Revert "program k1/k2 divider for virtual signal for DCN32" drm/amd/display: Use correct plane for CAB cursor size allocation Charlene Liu (2): drm/amd/display: add dcn35 basic support drm/amd/display: fix wrong register access Chen, Leo (1): drm/amd/display: add a override flag as wa for some specific dongle Duncan Ma (1): drm/amd/display: Fix OTG H timing reset for dcn314 Ethan Wellenreiter (2): drm/amd/display: Re-initialize viewport after pipe merge drm/amd/display: Fix check for stream and plane Gabe Teeger (2): drm/amd/display: Cursor lag with PSR1 eDP drm/amd/display: Cleanup PSR flag George Shen (1): drm/amd/display: Fix DCN32 DPSTREAMCLK_CNTL programming Ian Chen (2): drm/amd/display: Refactor edp dsc codes. drm/amd/display: Add comments. Iswara Nagulendran (1): drm/amd/display: Fix primary EDP link detection Leo (Hanghong) Ma (2): drm/amd/display: Add visual confirm color support for SubVP drm/amd/display: Add support for visual confirm color Leo Chen (1): drm/amd/display: Missing HPO instance added Lewis Huang (1): drm/amd/display: Refine aux transaction before retrieve caps Martin Tsai (1): drm/amd/display: Correct cursor position on horizontal mirror Michael Strauss (1): drm/amd/display: Add DC debug option to force LTTPR mode Taimur Hassan (3): drm/amd/display: Set ODM policy based on number of DSC slices drm/amd/display: Remove assert from PHY state update drm/amd/display: Allow PHY state update between same states Vladimir Stempen (1): drm/amd/display: Fix black flash when switching from ODM2to1 to ODMBypass Wang Fudong (1): drm/amd/display: set dig fifo read start level to 7 before dig fifo reset .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 +- .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 19 + .../drm/amd/display/dc/clk_mgr/Makefile.rej | 17 drivers/gpu/drm/amd/display/dc/core/dc.c | 26 +++--- .../drm/amd/display/dc/core/dc_hw_sequencer.c | 38 + drivers/gpu/drm/amd/display/dc/core/dc_link.c | 22 ++--- .../gpu/drm/amd/display/dc/core/dc_link_dp.c | 53 +--- drivers/gpu/drm/amd/display/dc/dc.h | 8 +- drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 41 - drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h | 1 + drivers/gpu/drm/amd/display/dc/dc_link.h | 12 +++ drivers/gpu/drm/amd/display/dc/dce/dce_abm.h | 9 +- .../display/dc/dce110/dce110_hw_sequencer.c | 13 +++ .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c | 5 +- .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c | 9 +- .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 83 +-- .../display/dc/dcn10/dcn10_stream_encoder.h | 1 + .../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c | 9 +- .../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 6 +- .../gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h | 3 +- .../display/dc/dcn31/dcn31_dio_link_encoder.c | 3 + .../dc/dcn31/dcn31_hpo_dp_link_encoder.h | 10 ++- .../drm/amd/display/dc/dcn31/dcn31_resource.c | 1 - .../dc/dcn314/dcn314_dio_stream_encoder.c | 1 + .../drm/amd/display/dc/dcn314/dcn314_optc.c | 3 +- .../amd/display/dc/dcn314/dcn314_resource.c | 2 +- .../amd/display/dc/dcn315/dcn315_resource.c | 1 - .../amd/display/dc/dcn316/dcn316_resource.c | 1 -
[PATCH 11/33] drm/amd/display: Add DC debug option to force LTTPR mode
From: Michael Strauss
[WHY]
Useful for external teams debugging LTTPR issues
Reviewed-by: George Shen
Acked-by: Brian Chang
Signed-off-by: Michael Strauss
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 4
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 8617de559174..7e97265b76e8 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -5032,6 +5032,10 @@ static void determine_lttpr_mode(struct dc_link *link)
bool vbios_lttpr_enable = link->dc->caps.vbios_lttpr_enable;
bool vbios_lttpr_interop = link->dc->caps.vbios_lttpr_aware;
+ if (link->ctx->dc->debug.lttpr_mode_override != 0) {
+ link->lttpr_mode = link->ctx->dc->debug.lttpr_mode_override;
+ return;
+ }
if ((link->dc->config.allow_lttpr_non_transparent_mode.bits.DP2_0 &&
link->dpcd_caps.channel_coding_cap.bits.DP_128b_132b_SUPPORTED)) {
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 2362d5ee2401..473e6a0c3310 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -846,6 +846,7 @@ struct dc_debug_options {
bool exit_idle_opt_for_cursor_updates;
bool enable_single_display_2to1_odm_policy;
bool enable_dp_dig_pixel_rate_div_policy;
+ enum lttpr_mode lttpr_mode_override;
};
struct gpu_info_soc_bounding_box_v1_0;
--
2.25.1
[PATCH 10/33] drm/amd/display: add a override flag as wa for some specific dongle
From: "Chen, Leo"
[Why & How]
Add a override flag as wa for some specific dongle
Co-authored-by: Leo Chen
Reviewed-by: Charlene Liu
Reviewed-by: Charlene Liu
Acked-by: Brian Chang
Signed-off-by: Leo Chen
---
drivers/gpu/drm/amd/display/dc/dc_link.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h
b/drivers/gpu/drm/amd/display/dc/dc_link.h
index b18efe988830..d1214944839f 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_link.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
@@ -224,6 +224,7 @@ struct dc_link {
bool dpia_mst_dsc_always_on;
/* Forced DPIA into TBT3 compatibility mode. */
bool dpia_forced_tbt3_mode;
+ bool dongle_mode_timing_override;
} wa_flags;
struct link_mst_stream_allocation_table mst_stream_alloc_table;
--
2.25.1
[PATCH 09/33] drm/amd/display: Only commit SubVP state after pipe programming
From: Alvin Lee
[Description]
We only want to commit the SubVP config to DMCUB
after the main and phantom pipe programming has
completed. Commiting the state early can cause
issues such as P-State being allowed by the HW
early which causes the SubVP state machine to
go into a bad state
Reviewed-by: Jun Lei
Acked-by: Brian Chang
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 15 +++
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index ced09f875e58..95daee11a445 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -,10 +,6 @@ static void commit_planes_for_stream(struct dc *dc,
if (dc->hwss.program_front_end_for_ctx)
dc->hwss.program_front_end_for_ctx(dc, context);
- if (update_type != UPDATE_TYPE_FAST)
- if (dc->hwss.commit_subvp_config)
- dc->hwss.commit_subvp_config(dc, context);
-
if (should_lock_all_pipes &&
dc->hwss.interdependent_update_lock) {
dc->hwss.interdependent_update_lock(dc, context, false);
} else {
@@ -3344,6 +3340,10 @@ static void commit_planes_for_stream(struct dc *dc,
}
dc->hwss.post_unlock_program_front_end(dc, context);
+ if (update_type != UPDATE_TYPE_FAST)
+ if (dc->hwss.commit_subvp_config)
+ dc->hwss.commit_subvp_config(dc, context);
+
/* Since phantom pipe programming is moved to
post_unlock_program_front_end,
* move the SubVP lock to after the phantom pipes have been
setup
*/
@@ -3477,10 +3477,6 @@ static void commit_planes_for_stream(struct dc *dc,
}
- if (update_type != UPDATE_TYPE_FAST)
- if (dc->hwss.commit_subvp_config)
- dc->hwss.commit_subvp_config(dc, context);
-
if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) {
dc->hwss.interdependent_update_lock(dc, context, false);
} else {
@@ -3517,6 +3513,9 @@ static void commit_planes_for_stream(struct dc *dc,
if (update_type != UPDATE_TYPE_FAST)
dc->hwss.post_unlock_program_front_end(dc, context);
+ if (update_type != UPDATE_TYPE_FAST)
+ if (dc->hwss.commit_subvp_config)
+ dc->hwss.commit_subvp_config(dc, context);
/* Since phantom pipe programming is moved to
post_unlock_program_front_end,
* move the SubVP lock to after the phantom pipes have been setup
--
2.25.1
[PATCH 08/33] drm/amd/display: Remove assert from PHY state update
From: Taimur Hassan
[Why & How]
In some cases, there are calls to transition from TX_ON to TX_ON. This is
expected, so do not assert. However, these are redundant, so return
prematurely.
Reviewed-by: Alvin Lee
Acked-by: Brian Chang
Signed-off-by: Taimur Hassan
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
index 3b1c6603ae0c..b7556111ee44 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
@@ -1224,10 +1224,8 @@ void dcn32_update_phy_state(struct dc_state *state,
struct pipe_ctx *pipe_ctx,
{
enum phy_state current_state = pipe_ctx->stream->link->phy_state;
- if (current_state == target_state) {
- BREAK_TO_DEBUGGER();
+ if (current_state == target_state)
return;
- }
if (target_state == TX_OFF_SYMCLK_OFF) {
core_link_disable_stream(pipe_ctx);
--
2.25.1
[PATCH 07/33] drm/amd/display: set dig fifo read start level to 7 before dig fifo reset
From: Wang Fudong [Why] DIG_FIFO_ERROR = 1 caused mst daisy chain 2nd monitor black. [How] We need to set dig fifo read start level = 7 before dig fifo reset during dig fifo enable according to hardware designer's suggestion. If it is zero, it will cause underflow or overflow and DIG_FIFO_ERROR = 1. Reviewed-by: Alvin Lee Reviewed-by: Aric Cyr Acked-by: Brian Chang Signed-off-by: Wang Fudong --- .../gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c index 26648ce772da..38a48983f663 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c @@ -310,6 +310,11 @@ static void enc32_stream_encoder_dp_unblank( // TODO: Confirm if we need to wait for DIG_SYMCLK_FE_ON REG_WAIT(DIG_FE_CNTL, DIG_SYMCLK_FE_ON, 1, 10, 5000); + /* read start level = 0 will bring underflow / overflow and DIG_FIFO_ERROR = 1 +* so set it to 1/2 full = 7 before reset as suggested by hardware team. +*/ + REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_READ_START_LEVEL, 0x7); + REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, 1); REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, 1, 10, 5000); -- 2.25.1
[PATCH 06/33] drm/amd/display: add dcn35 basic support
From: Charlene Liu
[why]
this is to add new dcn frame work
Reviewed-by: Hansen Dsouza
Acked-by: Brian Chang
Signed-off-by: Charlene Liu
---
.../gpu/drm/amd/display/dc/clk_mgr/Makefile.rej | 17 +
drivers/gpu/drm/amd/display/dc/dce/dce_abm.h| 9 ++---
.../amd/display/dc/dcn10/dcn10_stream_encoder.h | 1 +
.../gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h| 3 ++-
.../dc/dcn31/dcn31_hpo_dp_link_encoder.h| 10 --
drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 3 ++-
drivers/gpu/drm/amd/display/include/dal_types.h | 1 +
7 files changed, 37 insertions(+), 7 deletions(-)
create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile.rej
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile.rej
b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile.rej
new file mode 100644
index ..bfbfd67a7451
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile.rej
@@ -0,0 +1,17 @@
+diff a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile (rejected hunks)
+@@ -160,6 +160,15 @@ AMD_DAL_CLK_MGR_DCN32 = $(addprefix
$(AMDDALPATH)/dc/clk_mgr/dcn32/,$(CLK_MGR_DC
+
+ AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN32)
+
++
++###
++# DCN35
++###
++CLK_MGR_DCN35 = dcn35_smu.o dcn35_clk_mgr.o
++
++AMD_DAL_CLK_MGR_DCN35 = $(addprefix
$(AMDDALPATH)/dc/clk_mgr/dcn35/,$(CLK_MGR_DCN35))
++
++AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN35)
+
###
+ # DCN3AG
+
###
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
index e6c06325742a..a3c27cbb77c8 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
@@ -183,8 +183,7 @@
ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \
ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh)
-#define ABM_MASK_SH_LIST_DCN10(mask_sh) \
- ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
+#define ABM_MASK_SH_LIST_DCN10_COMMON(mask_sh) \
ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \
ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
@@ -214,9 +213,13 @@
ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh)
-#define ABM_MASK_SH_LIST_DCN20(mask_sh) ABM_MASK_SH_LIST_DCE110(mask_sh)
+#define ABM_MASK_SH_LIST_DCN10(mask_sh) \
+ ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
+ ABM_MASK_SH_LIST_DCN10_COMMON(mask_sh)
+#define ABM_MASK_SH_LIST_DCN20(mask_sh) ABM_MASK_SH_LIST_DCE110(mask_sh)
#define ABM_MASK_SH_LIST_DCN30(mask_sh) ABM_MASK_SH_LIST_DCN10(mask_sh)
+#define ABM_MASK_SH_LIST_DCN35(mask_sh) ABM_MASK_SH_LIST_DCN10_COMMON(mask_sh)
#define ABM_MASK_SH_LIST_DCN32(mask_sh) \
ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
index 9d5e2a7848dd..3f9582b4cc79 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
@@ -188,6 +188,7 @@ struct dcn10_stream_enc_registers {
uint32_t HDMI_GENERIC_PACKET_CONTROL10;
uint32_t DIG_CLOCK_PATTERN;
uint32_t DIG_FIFO_CTRL0;
+ uint32_t DIG_FE_CLK_CNTL;
};
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h
index 6263408d71fc..815169e08e5b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h
@@ -172,7 +172,8 @@
SRI(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R, CM, id),\
SRI(CM_BLNDGAM_LUT_CONTROL, CM, id)
-
+#define DPP_REG_LIST_DCN35(id)\
+ DPP_REG_LIST_DCN30_COMMON(id)
#define DPP_REG_LIST_SH_MASK_DCN30_COMMON(mask_sh)\
TF_SF(CM0_CM_MEM_PWR_STATUS, GAMCOR_MEM_PWR_STATE, mask_sh),\
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_link_encoder.h
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_link_encoder.h
index e324e9b83136..51f5781325e8 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_link_encoder.h
@@ -104,7 +104,10 @@ struct dcn31_hpo_dp_link_encoder_registers {
uint32_t RDPCSTX_PHY_CNTL6[5];
};
-#define DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(mask_sh)\
+#define DCN3_1_HPO_DP_LINK_ENC_RDPCSTX_MASK_SH_LIST(mask_sh)\
+ SE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, mask_sh)
+
+#define DCN3_1_HPO_DP_LINK_ENC_COMMON_MASK_SH_LIST(mask_sh)\
[PATCH 02/33] drm/amd/display: Don't choose SubVP display if ActiveMargin > 0
From: Alvin Lee
[Description]
There can be SubVP scheduling issues if a SubVP
display is chosen has ActiveDramClockChangeLatency > 0.
Block this case for now, and enable Vactive case
(later) to handle this.
Reviewed-by: Jun Lei
Acked-by: Brian Chang
Signed-off-by: Alvin Lee
---
.../drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 21 ---
.../dc/dml/dcn32/display_mode_vba_32.c| 2 +-
.../drm/amd/display/dc/dml/display_mode_vba.h | 1 +
3 files changed, 20 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index edefb3fc1c3c..e72213a20e75 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -560,6 +560,7 @@ static bool dcn32_assign_subvp_pipe(struct dc *dc,
bool valid_assignment_found = false;
unsigned int free_pipes = dcn32_get_num_free_pipes(dc, context);
bool current_assignment_freesync = false;
+ struct vba_vars_st *vba = >bw_ctx.dml.vba;
for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe = >res_ctx.pipe_ctx[i];
@@ -573,8 +574,15 @@ static bool dcn32_assign_subvp_pipe(struct dc *dc,
refresh_rate = (pipe->stream->timing.pix_clk_100hz * 100 +
pipe->stream->timing.v_total *
pipe->stream->timing.h_total - 1)
/ (double)(pipe->stream->timing.v_total *
pipe->stream->timing.h_total);
+ /* SubVP pipe candidate requirements:
+* - Refresh rate < 120hz
+* - Not able to switch in vactive naturally (switching in
active means the
+* DET provides enough buffer to hide the P-State switch
latency -- trying
+* to combine this with SubVP can cause issues with the
scheduling).
+*/
if (pipe->plane_state && !pipe->top_pipe &&
- pipe->stream->mall_stream_config.type ==
SUBVP_NONE && refresh_rate < 120) {
+ pipe->stream->mall_stream_config.type ==
SUBVP_NONE && refresh_rate < 120 &&
+
vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]]
<= 0) {
while (pipe) {
num_pipes++;
pipe = pipe->bottom_pipe;
@@ -998,8 +1006,10 @@ static void dcn32_full_validate_bw_helper(struct dc *dc,
*vlevel = dml_get_voltage_level(>bw_ctx.dml, pipes, *pipe_cnt);
/* This may adjust vlevel and maxMpcComb */
- if (*vlevel < context->bw_ctx.dml.soc.num_states)
+ if (*vlevel < context->bw_ctx.dml.soc.num_states) {
*vlevel = dcn20_validate_apply_pipe_split_flags(dc, context,
*vlevel, split, merge);
+ vba->VoltageLevel = *vlevel;
+ }
/* Conditions for setting up phantom pipes for SubVP:
* 1. Not force disable SubVP
@@ -1085,13 +1095,16 @@ static void dcn32_full_validate_bw_helper(struct dc *dc,
*vlevel = dml_get_voltage_level(>bw_ctx.dml,
pipes, *pipe_cnt);
/* This may adjust vlevel and maxMpcComb */
- if (*vlevel < context->bw_ctx.dml.soc.num_states)
+ if (*vlevel < context->bw_ctx.dml.soc.num_states) {
*vlevel =
dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge);
+ vba->VoltageLevel = *vlevel;
+ }
} else {
// only call dcn20_validate_apply_pipe_split_flags if
we found a supported config
memset(split, 0, MAX_PIPES * sizeof(int));
memset(merge, 0, MAX_PIPES * sizeof(bool));
*vlevel = dcn20_validate_apply_pipe_split_flags(dc,
context, *vlevel, split, merge);
+ vba->VoltageLevel = *vlevel;
// Most populate phantom DLG params before programming
hardware / timing for phantom pipe
DC_FP_START();
@@ -1421,6 +1434,8 @@ bool dcn32_internal_validate_bw(struct dc *dc,
memset(split, 0, sizeof(split));
memset(merge, 0, sizeof(merge));
vlevel = dcn20_validate_apply_pipe_split_flags(dc,
context, vlevel, split, merge);
+ // dcn20_validate_apply_pipe_split_flags can modify
voltage level outside of DML
+ vba->VoltageLevel = vlevel;
}
}
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
index f831855db022..3040428a7304 100644
---
[PATCH 05/33] drm/amd/display: Fix OTG H timing reset for dcn314
From: Duncan Ma [Why] When ODM is enabled, H timing control register reset to 0. Div mode manual field get overwritten causing no display on certain modes for dcn314. [How] Use REG_UPDATE instead of REG_SET to set div_mode field. Reviewed-by: Charlene Liu Reviewed-by: Nicholas Kazlauskas Acked-by: Brian Chang Signed-off-by: Duncan Ma --- drivers/gpu/drm/amd/display/dc/dcn314/dcn314_optc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_optc.c b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_optc.c index 0c7980266b85..38aa28ec6b13 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_optc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_optc.c @@ -98,7 +98,8 @@ static void optc314_set_odm_combine(struct timing_generator *optc, int *opp_id, REG_UPDATE(OPTC_WIDTH_CONTROL, OPTC_SEGMENT_WIDTH, mpcc_hactive); - REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_MODE, opp_cnt - 1); + REG_UPDATE(OTG_H_TIMING_CNTL, + OTG_H_TIMING_DIV_MODE, opp_cnt - 1); optc1->opp_count = opp_cnt; } -- 2.25.1
[PATCH 04/33] drm/amd/display: Refine aux transaction before retrieve caps
From: Lewis Huang
[Why]
LTTPR caps will read fail if aux channel is not active.
[How]
1.Perform 600 read upto 10 retry with 1ms delay in between.
2.If fail, return false and trigger another retry detection.
3.If pass, read LTTPR caps in retrieve link caps.
Reviewed-by: Jimmy Kizito
Acked-by: Brian Chang
Signed-off-by: Lewis Huang
---
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 45 ++-
1 file changed, 34 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 2b7bb3a796e8..8617de559174 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -5275,6 +5275,7 @@ static bool retrieve_link_cap(struct dc_link *link)
union dp_downstream_port_present ds_port = { 0 };
enum dc_status status = DC_ERROR_UNEXPECTED;
uint32_t read_dpcd_retry_cnt = 3;
+ uint32_t aux_channel_retry_cnt = 0;
int i;
struct dp_sink_hw_fw_revision dp_hw_fw_revision;
const uint32_t post_oui_delay = 30; // 30ms
@@ -5302,21 +5303,43 @@ static bool retrieve_link_cap(struct dc_link *link)
status = wa_try_to_wake_dprx(link, timeout_ms);
}
+ while (status != DC_OK && aux_channel_retry_cnt < 10) {
+ status = core_link_read_dpcd(link, DP_SET_POWER,
+ _power_state, sizeof(dpcd_power_state));
+
+ /* Delay 1 ms if AUX CH is in power down state. Based on spec
+* section 2.3.1.2, if AUX CH may be powered down due to
+* write to DPCD 600h = 2. Sink AUX CH is monitoring
differential
+* signal and may need up to 1 ms before being able to reply.
+*/
+ if (status != DC_OK || dpcd_power_state == DP_SET_POWER_D3) {
+ udelay(1000);
+ aux_channel_retry_cnt++;
+ }
+ }
+
+ /* If aux channel is not active, return false and trigger another
detect*/
+ if (status != DC_OK) {
+ dpcd_power_state = DP_SET_POWER_D0;
+ status = core_link_write_dpcd(
+ link,
+ DP_SET_POWER,
+ _power_state,
+ sizeof(dpcd_power_state));
+
+ dpcd_power_state = DP_SET_POWER_D3;
+ status = core_link_write_dpcd(
+ link,
+ DP_SET_POWER,
+ _power_state,
+ sizeof(dpcd_power_state));
+ return false;
+ }
+
is_lttpr_present = dp_retrieve_lttpr_cap(link);
/* Read DP tunneling information. */
status = dpcd_get_tunneling_device_data(link);
- status = core_link_read_dpcd(link, DP_SET_POWER,
- _power_state, sizeof(dpcd_power_state));
-
- /* Delay 1 ms if AUX CH is in power down state. Based on spec
-* section 2.3.1.2, if AUX CH may be powered down due to
-* write to DPCD 600h = 2. Sink AUX CH is monitoring differential
-* signal and may need up to 1 ms before being able to reply.
-*/
- if (status != DC_OK || dpcd_power_state == DP_SET_POWER_D3)
- udelay(1000);
-
dpcd_set_source_specific_data(link);
/* Sink may need to configure internals based on vendor, so allow some
* time before proceeding with possibly vendor specific transactions
--
2.25.1
[PATCH 03/33] drm/amd/display: Fix DCN32 DPSTREAMCLK_CNTL programming
From: George Shen [Why] Each index in the DPSTREAMCLK_CNTL register phyiscally maps 1-to-1 with HPO stream encoder instance. On the other hand, each index in DTBCLK_P_CNTL physically maps 1-to-1 with OTG instance. Current DCN32 DPSTREAMCLK_CLK programing assumes that OTG instance always maps 1-to-1 with HPO stream encoder instance. This is not always guaranteed and can result in blackscreen. [How] Program the correct dpstreamclk instance with the correct dtbclk_p source. Reviewed-by: Ariel Bernstein Acked-by: Brian Chang Signed-off-by: George Shen --- drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c | 8 drivers/gpu/drm/amd/display/dc/link/link_hwss_hpo_dp.c | 4 ++-- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c index a31c64b50410..0d5e8a441512 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c @@ -225,19 +225,19 @@ void dccg32_set_dpstreamclk( case 0: REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK0_EN, -(src == REFCLK) ? 0 : 1, DPSTREAMCLK0_SRC_SEL, 0); +(src == REFCLK) ? 0 : 1, DPSTREAMCLK0_SRC_SEL, otg_inst); break; case 1: REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK1_EN, -(src == REFCLK) ? 0 : 1, DPSTREAMCLK1_SRC_SEL, 1); +(src == REFCLK) ? 0 : 1, DPSTREAMCLK1_SRC_SEL, otg_inst); break; case 2: REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK2_EN, -(src == REFCLK) ? 0 : 1, DPSTREAMCLK2_SRC_SEL, 2); +(src == REFCLK) ? 0 : 1, DPSTREAMCLK2_SRC_SEL, otg_inst); break; case 3: REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK3_EN, -(src == REFCLK) ? 0 : 1, DPSTREAMCLK3_SRC_SEL, 3); +(src == REFCLK) ? 0 : 1, DPSTREAMCLK3_SRC_SEL, otg_inst); break; default: BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/link/link_hwss_hpo_dp.c b/drivers/gpu/drm/amd/display/dc/link/link_hwss_hpo_dp.c index db7b0b155374..226af06278ce 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_hwss_hpo_dp.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_hwss_hpo_dp.c @@ -116,7 +116,7 @@ static void setup_hpo_dp_stream_encoder(struct pipe_ctx *pipe_ctx) dto_params.timing = _ctx->stream->timing; dto_params.ref_dtbclk_khz = dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(dc->clk_mgr); - dccg->funcs->set_dpstreamclk(dccg, DTBCLK0, tg->inst, link_enc->inst); + dccg->funcs->set_dpstreamclk(dccg, DTBCLK0, tg->inst, stream_enc->inst); dccg->funcs->enable_symclk32_se(dccg, stream_enc->inst, phyd32clk); dccg->funcs->set_dtbclk_dto(dccg, _params); stream_enc->funcs->enable_stream(stream_enc); @@ -137,7 +137,7 @@ static void reset_hpo_dp_stream_encoder(struct pipe_ctx *pipe_ctx) stream_enc->funcs->disable(stream_enc); dccg->funcs->set_dtbclk_dto(dccg, _params); dccg->funcs->disable_symclk32_se(dccg, stream_enc->inst); - dccg->funcs->set_dpstreamclk(dccg, REFCLK, tg->inst, pipe_ctx->link_res.hpo_dp_link_enc->inst); + dccg->funcs->set_dpstreamclk(dccg, REFCLK, tg->inst, stream_enc->inst); } static void setup_hpo_dp_stream_attribute(struct pipe_ctx *pipe_ctx) -- 2.25.1
[PATCH 01/33] drm/amd/display: Set ODM policy based on number of DSC slices
From: Taimur Hassan
[Why & How]
Add addtional check in CalculateODMMode for cases where the ODM combine
is needed due to number of DSC slices.
Reviewed-by: Alvin Lee
Acked-by: Brian Chang
Signed-off-by: Taimur Hassan
---
.../gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c | 2 ++
.../amd/display/dc/dml/dcn32/display_mode_vba_util_32.c| 7 +--
.../amd/display/dc/dml/dcn32/display_mode_vba_util_32.h| 1 +
3 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
index cb2025771646..f831855db022 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
@@ -2045,6 +2045,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct
display_mode_lib *mode_l
mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading,
mode_lib->vba.DISPCLKRampingMargin,
mode_lib->vba.DISPCLKDPPCLKVCOSpeed,
+
mode_lib->vba.NumberOfDSCSlices[k],
/* Output */
>dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.TotalAvailablePipesSupportNoDSC,
@@ -2066,6 +2067,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct
display_mode_lib *mode_l
mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading,
mode_lib->vba.DISPCLKRampingMargin,
mode_lib->vba.DISPCLKDPPCLKVCOSpeed,
+
mode_lib->vba.NumberOfDSCSlices[k],
/* Output */
>dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.TotalAvailablePipesSupportDSC,
diff --git
a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
index 05fc14a47fba..6b3c4dbb140b 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
@@ -1193,6 +1193,7 @@ void dml32_CalculateODMMode(
double DISPCLKDPPCLKDSCCLKDownSpreading,
double DISPCLKRampingMargin,
double DISPCLKDPPCLKVCOSpeed,
+ unsigned int NumberOfDSCSlices,
/* Output */
bool *TotalAvailablePipesSupport,
@@ -1228,7 +1229,8 @@ void dml32_CalculateODMMode(
if (!(Output == dm_hdmi || Output == dm_dp || Output == dm_edp) &&
(ODMUse == dm_odm_combine_policy_4to1 ||
((SurfaceRequiredDISPCLKWithODMCombineTwoToOne >
StateDispclk ||
- (DSCEnable && (HActive > 2 *
MaximumPixelsPerLinePerDSCUnit)) {
+ (DSCEnable && (HActive > 2 *
MaximumPixelsPerLinePerDSCUnit))
+ || NumberOfDSCSlices > 8 {
if (TotalNumberOfActiveDPP + 4 <= MaxNumDPP) {
*ODMMode = dm_odm_combine_mode_4to1;
*RequiredDISPCLKPerSurface =
SurfaceRequiredDISPCLKWithODMCombineFourToOne;
@@ -1239,7 +1241,8 @@ void dml32_CalculateODMMode(
} else if (Output != dm_hdmi && (ODMUse == dm_odm_combine_policy_2to1 ||
(((SurfaceRequiredDISPCLKWithoutODMCombine >
StateDispclk &&
SurfaceRequiredDISPCLKWithODMCombineTwoToOne <= StateDispclk) ||
- (DSCEnable && (HActive >
MaximumPixelsPerLinePerDSCUnit)) {
+ (DSCEnable && (HActive >
MaximumPixelsPerLinePerDSCUnit))
+ || (NumberOfDSCSlices <= 8 &&
NumberOfDSCSlices > 4) {
if (TotalNumberOfActiveDPP + 2 <= MaxNumDPP) {
*ODMMode = dm_odm_combine_mode_2to1;
*RequiredDISPCLKPerSurface =
SurfaceRequiredDISPCLKWithODMCombineTwoToOne;
diff --git
a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
index d293856ba906..626f6605e2d5 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
@@ -226,6 +226,7 @@ void dml32_CalculateODMMode(
double DISPCLKDPPCLKDSCCLKDownSpreading,
double DISPCLKRampingMargin,
double DISPCLKDPPCLKVCOSpeed,
+ unsigned int NumberOfDSCSlices,
[PATCH 00/33] DC Patches August 27 ,2022
This DC patchset brings improvements in multiple areas. In summary, we have: * Correct cursor position on horizontal mirror; * Fix black flash when switching from ODM2to1 to ODMBypass; * Fix plane and stream check; * Fix viewport after pipe merge; * Correct plane for CAB cursor; * Fix comment to correct visual confirm option; * Fix SubVP related regression; * Fix primary EDP link detection; * Fix wrong register access; * Fix cursor size allocation for DCN32/321; * Fix display fresh edge case from MALL for DCN321; * Add HPO instance; * Refactor EDP codes; * Add SubVP scaling case; * Add support for visual confirm color; * Fix PHY state update; * Cleanup PSR flag; * Fix cursor lag with PSR1 eDP; * Add DC debug optioon for LTTPR mode; * Add override flag for some dongle; * Fix SubVP state after pipe programming; * Remove assert from PHY state update; * Fix dig fifo read level before reset; * Add dcn35 basic suppoet; * Fix OTG H timming for dcn314; * Fix aux transaction; * Fix DCN32 DPSTREAMCLK_CNTL programming; * Fix SubVP scheduling issues; * Set ODM policy. Alvin Lee (3): drm/amd/display: Don't choose SubVP display if ActiveMargin > 0 drm/amd/display: Only commit SubVP state after pipe programming drm/amd/display: SubVP missing scaling case Anthony Koo (1): drm/amd/display: [FW Promotion] Release 0.0.132.0 Aric Cyr (1): drm/amd/display: 3.2.201 Aurabindo Pillai (5): drm/amd/display: Fix CAB cursor size allocation for DCN32/321 drm/amd/display: disable display fresh from MALL on an edge case for DCN321 drm/amd/display: use actual cursor size instead of max for CAB allocation drm/amd/display: Revert "program k1/k2 divider for virtual signal for DCN32" drm/amd/display: Use correct plane for CAB cursor size allocation Charlene Liu (2): drm/amd/display: add dcn35 basic support drm/amd/display: fix wrong register access Chen, Leo (1): drm/amd/display: add a override flag as wa for some specific dongle Duncan Ma (1): drm/amd/display: Fix OTG H timing reset for dcn314 Ethan Wellenreiter (2): drm/amd/display: Re-initialize viewport after pipe merge drm/amd/display: Fix check for stream and plane Gabe Teeger (2): drm/amd/display: Cursor lag with PSR1 eDP drm/amd/display: Cleanup PSR flag George Shen (1): drm/amd/display: Fix DCN32 DPSTREAMCLK_CNTL programming Ian Chen (2): drm/amd/display: Refactor edp dsc codes. drm/amd/display: Add comments. Iswara Nagulendran (1): drm/amd/display: Fix primary EDP link detection Leo (Hanghong) Ma (2): drm/amd/display: Add visual confirm color support for SubVP drm/amd/display: Add support for visual confirm color Leo Chen (1): drm/amd/display: Missing HPO instance added Lewis Huang (1): drm/amd/display: Refine aux transaction before retrieve caps Martin Tsai (1): drm/amd/display: Correct cursor position on horizontal mirror Michael Strauss (1): drm/amd/display: Add DC debug option to force LTTPR mode Taimur Hassan (3): drm/amd/display: Set ODM policy based on number of DSC slices drm/amd/display: Remove assert from PHY state update drm/amd/display: Allow PHY state update between same states Vladimir Stempen (1): drm/amd/display: Fix black flash when switching from ODM2to1 to ODMBypass Wang Fudong (1): drm/amd/display: set dig fifo read start level to 7 before dig fifo reset .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 +- .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 19 + .../drm/amd/display/dc/clk_mgr/Makefile.rej | 17 drivers/gpu/drm/amd/display/dc/core/dc.c | 26 +++--- .../drm/amd/display/dc/core/dc_hw_sequencer.c | 38 + drivers/gpu/drm/amd/display/dc/core/dc_link.c | 22 ++--- .../gpu/drm/amd/display/dc/core/dc_link_dp.c | 53 +--- drivers/gpu/drm/amd/display/dc/dc.h | 8 +- drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 41 - drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h | 1 + drivers/gpu/drm/amd/display/dc/dc_link.h | 12 +++ drivers/gpu/drm/amd/display/dc/dce/dce_abm.h | 9 +- .../display/dc/dce110/dce110_hw_sequencer.c | 13 +++ .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c | 5 +- .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c | 9 +- .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 83 +-- .../display/dc/dcn10/dcn10_stream_encoder.h | 1 + .../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c | 9 +- .../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 6 +- .../gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h | 3 +- .../display/dc/dcn31/dcn31_dio_link_encoder.c | 3 + .../dc/dcn31/dcn31_hpo_dp_link_encoder.h | 10 ++- .../drm/amd/display/dc/dcn31/dcn31_resource.c | 1 - .../dc/dcn314/dcn314_dio_stream_encoder.c | 1 + .../drm/amd/display/dc/dcn314/dcn314_optc.c | 3 +- .../amd/display/dc/dcn314/dcn314_resource.c | 2 +- .../amd/display/dc/dcn315/dcn315_resource.c | 1 - .../amd/display/dc/dcn316/dcn316_resource.c | 1 -
Re: [PATCH 03/11] drm/edid: s/monitor_rage/vrr_range/
On Sat, Aug 27, 2022 at 12:34:53AM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Rename info->monitor_range to info->vrr_range to actually
> reflect its usage.
Okay makes sense.
Reviewed-by: Manasi Navare
Manasi
>
> Cc: Manasi Navare
> Cc: Nicholas Kazlauskas
> Cc: Harry Wentland
> Cc: Leo Li
> Cc: Rodrigo Siqueira
> Cc: amd-gfx@lists.freedesktop.org
> Signed-off-by: Ville Syrjälä
> ---
> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 12 -
> drivers/gpu/drm/drm_debugfs.c | 4 +--
> drivers/gpu/drm/drm_edid.c| 26 +--
> drivers/gpu/drm/i915/display/intel_vrr.c | 6 ++---
> include/drm/drm_connector.h | 4 +--
> 5 files changed, 26 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index e702f0d72d53..928b5b6541db 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -9921,8 +9921,8 @@ void amdgpu_dm_update_freesync_caps(struct
> drm_connector *connector,
> amdgpu_dm_connector->min_vfreq = 0;
> amdgpu_dm_connector->max_vfreq = 0;
> amdgpu_dm_connector->pixel_clock_mhz = 0;
> - connector->display_info.monitor_range.min_vfreq = 0;
> - connector->display_info.monitor_range.max_vfreq = 0;
> + connector->display_info.vrr_range.min_vfreq = 0;
> + connector->display_info.vrr_range.max_vfreq = 0;
> freesync_capable = false;
>
> goto update;
> @@ -9970,8 +9970,8 @@ void amdgpu_dm_update_freesync_caps(struct
> drm_connector *connector,
> amdgpu_dm_connector->pixel_clock_mhz =
> range->pixel_clock_mhz * 10;
>
> - connector->display_info.monitor_range.min_vfreq
> = range->min_vfreq;
> - connector->display_info.monitor_range.max_vfreq
> = range->max_vfreq;
> + connector->display_info.vrr_range.min_vfreq =
> range->min_vfreq;
> + connector->display_info.vrr_range.max_vfreq =
> range->max_vfreq;
>
> break;
> }
> @@ -9993,8 +9993,8 @@ void amdgpu_dm_update_freesync_caps(struct
> drm_connector *connector,
> if (amdgpu_dm_connector->max_vfreq -
> amdgpu_dm_connector->min_vfreq > 10)
> freesync_capable = true;
>
> - connector->display_info.monitor_range.min_vfreq =
> vsdb_info.min_refresh_rate_hz;
> - connector->display_info.monitor_range.max_vfreq =
> vsdb_info.max_refresh_rate_hz;
> + connector->display_info.vrr_range.min_vfreq =
> vsdb_info.min_refresh_rate_hz;
> + connector->display_info.vrr_range.max_vfreq =
> vsdb_info.max_refresh_rate_hz;
> }
> }
>
> diff --git a/drivers/gpu/drm/drm_debugfs.c b/drivers/gpu/drm/drm_debugfs.c
> index 01ee3febb813..1437c798b122 100644
> --- a/drivers/gpu/drm/drm_debugfs.c
> +++ b/drivers/gpu/drm/drm_debugfs.c
> @@ -377,8 +377,8 @@ static int vrr_range_show(struct seq_file *m, void *data)
> if (connector->status != connector_status_connected)
> return -ENODEV;
>
> - seq_printf(m, "Min: %u\n",
> connector->display_info.monitor_range.min_vfreq);
> - seq_printf(m, "Max: %u\n",
> connector->display_info.monitor_range.max_vfreq);
> + seq_printf(m, "Min: %u\n", connector->display_info.vrr_range.min_vfreq);
> + seq_printf(m, "Max: %u\n", connector->display_info.vrr_range.max_vfreq);
>
> return 0;
> }
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index ac662495635c..4355d73632c3 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -6020,11 +6020,11 @@ static void drm_parse_cea_ext(struct drm_connector
> *connector,
> }
>
> static
> -void get_monitor_range(const struct detailed_timing *timing, void *c)
> +void get_vrr_range(const struct detailed_timing *timing, void *c)
> {
> struct detailed_mode_closure *closure = c;
> struct drm_display_info *info = >connector->display_info;
> - struct drm_monitor_range_info *monitor_range = >monitor_range;
> + struct drm_monitor_range_info *vrr_range = >vrr_range;
> const struct detailed_non_pixel *data = >data.other_data;
> const struct detailed_data_monitor_range *range = >data.range;
> const struct edid *edid = closure->drm_edid->edid;
> @@ -6044,19 +6044,19 @@ void get_monitor_range(const struct detailed_timing
> *timing, void *c)
> if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG)
> return;
>
> - monitor_range->min_vfreq = range->min_vfreq;
> - monitor_range->max_vfreq =
Re: [PATCH 02/11] drm/edid: Clarify why we only accept the "range limits only" descriptor
On Sat, Aug 27, 2022 at 12:34:52AM +0300, Ville Syrjala wrote: > From: Ville Syrjälä > > The current comment fails to clarify why we only accept > the "range limits only" variant of the range descriptor. > Reword it to make some actual sense. > Thanks Ville for adding this description for monitor_range Reviewed-by: Manasi Navare Manasi > Cc: Manasi Navare > Cc: Nicholas Kazlauskas > Cc: Harry Wentland > Cc: Leo Li > Cc: Rodrigo Siqueira > Cc: amd-gfx@lists.freedesktop.org > Signed-off-by: Ville Syrjälä > --- > drivers/gpu/drm/drm_edid.c | 11 +++ > 1 file changed, 7 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c > index 4005dab6147d..ac662495635c 100644 > --- a/drivers/gpu/drm/drm_edid.c > +++ b/drivers/gpu/drm/drm_edid.c > @@ -6033,10 +6033,13 @@ void get_monitor_range(const struct detailed_timing > *timing, void *c) > return; > > /* > - * Check for flag range limits only. If flag == 1 then > - * no additional timing information provided. > - * Default GTF, GTF Secondary curve and CVT are not > - * supported > + * These limits are used to determine the VRR refresh > + * rate range. Only the "range limits only" variant > + * of the range descriptor seems to guarantee that > + * any and all timings are accepted by the sink, as > + * opposed to just timings conforming to the indicated > + * formula (GTF/GTF2/CVT). Thus other variants of the > + * range descriptor are not accepted here. >*/ > if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG) > return; > -- > 2.35.1 >
[PATCH] drm/amdkfd: Set pte_flags for actual BO location
BOs can be in a different location than was intended at allocation time,
for example when restoring fails after an eviction or BOs get pinned in
system memory. On some GPUs the MTYPE for coherent mappings depends on
the actual memory location.
Use the actual location to determine the pte_flags every time the page
tables are updated.
Signed-off-by: Felix Kuehling
---
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 9 -
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c| 19 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h| 1 +
3 files changed, 28 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index cbd593f7d553..5dd89f5a032f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -405,6 +405,7 @@ static int vm_update_pds(struct amdgpu_vm *vm, struct
amdgpu_sync *sync)
static uint64_t get_pte_flags(struct amdgpu_device *adev, struct kgd_mem *mem)
{
struct amdgpu_device *bo_adev = amdgpu_ttm_adev(mem->bo->tbo.bdev);
+ bool is_vram = mem->bo->tbo.resource->mem_type == TTM_PL_VRAM;
bool coherent = mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_COHERENT;
bool uncached = mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_UNCACHED;
uint32_t mapping_flags;
@@ -420,7 +421,7 @@ static uint64_t get_pte_flags(struct amdgpu_device *adev,
struct kgd_mem *mem)
switch (adev->asic_type) {
case CHIP_ARCTURUS:
case CHIP_ALDEBARAN:
- if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
+ if (is_vram) {
if (bo_adev == adev) {
if (uncached)
mapping_flags |= AMDGPU_VM_MTYPE_UC;
@@ -1236,12 +1237,18 @@ static int update_gpuvm_pte(struct kgd_mem *mem,
{
struct amdgpu_bo_va *bo_va = entry->bo_va;
struct amdgpu_device *adev = entry->adev;
+ uint64_t pte_flags = get_pte_flags(adev, mem);
int ret;
ret = kfd_mem_dmamap_attachment(mem, entry);
if (ret)
return ret;
+ if (unlikely(entry->pte_flags != pte_flags)) {
+ amdgpu_vm_bo_update_flags(bo_va, pte_flags);
+ entry->pte_flags = pte_flags;
+ }
+
/* Update the page tables */
ret = amdgpu_vm_bo_update(adev, bo_va, false);
if (ret) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 59cac347baa3..954a40d5d828 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1862,6 +1862,25 @@ void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
}
}
+/**
+ * amdgpu_vm_bo_update_flags - Update mapping flags of invalid mappings
+ *
+ * @bo_va: identifies the BO and VM
+ * @flags: new mapping flags
+ *
+ * The update is only applied to invalid mappings. This allows updating the
+ * mapping flags after a migration to maintain the desired coherence. The next
+ * call to amdgpu_vm_bo_update() will apply the new @flags to the page table.
+ */
+void amdgpu_vm_bo_update_flags(struct amdgpu_bo_va *bo_va,
+ uint64_t flags)
+{
+ struct amdgpu_bo_va_mapping *mapping;
+
+ list_for_each_entry(mapping, _va->invalids, list)
+ mapping->flags = flags;
+}
+
/**
* amdgpu_vm_get_block_size - calculate VM page table size as power of two
*
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 9ecb7f663e19..11793716cd8b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -413,6 +413,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
bool amdgpu_vm_evictable(struct amdgpu_bo *bo);
void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
struct amdgpu_bo *bo, bool evicted);
+void amdgpu_vm_bo_update_flags(struct amdgpu_bo_va *bo_va, uint64_t flags);
uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr);
struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
struct amdgpu_bo *bo);
--
2.32.0
Re: [PATCH] drm/amdgpu: ensure no PCIe peer access for CPU XGMI iolinks
On 2022-08-26 11:47, Alex Sierra wrote: [Why] Devices with CPU XGMI iolink do not support PCIe peer access. Signed-off-by: Alex Sierra --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index ce7d117efdb5..1ff66718639d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -5538,7 +5538,8 @@ bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, return pcie_p2p && p2p_access && (adev->gmc.visible_vram_size && adev->gmc.real_vram_size == adev->gmc.visible_vram_size && !(adev->gmc.aper_base & address_mask || - aper_limit & address_mask)); + aper_limit & address_mask) && + !adev->gmc.xgmi.connected_to_cpu); Maybe it would be more readable if you added this to the initialization of p2p_access. In that case you can also save yourself the call to pci_p2pdma_distance_many and all the aperture checks. Like this: bool p2p_access = !adev->gmc.xgmi.connected_to_cpu && !(pci_p2pdma_distance_many(adev->pdev, _adev->dev, 1, true) < 0); Regards, Felix #else return false; #endif
[PATCH 05/11] drm/edid: Only parse VRR range for continuous frequency displays
From: Ville Syrjälä Since we only use the parsed vrefresh range to determine if VRR should be supported we should only accept continuous frequency displays here. Cc: Manasi Navare Cc: Nicholas Kazlauskas Cc: Harry Wentland Cc: Leo Li Cc: Rodrigo Siqueira Cc: amd-gfx@lists.freedesktop.org Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/drm_edid.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index 856d304a1354..b459fdf12b58 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -6064,7 +6064,10 @@ static void drm_get_vrr_range(struct drm_connector *connector, .drm_edid = drm_edid, }; - if (!version_greater(drm_edid, 1, 1)) + if (!version_greater(drm_edid, 1, 3)) + return; + + if (!(drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ)) return; drm_for_each_detailed_block(drm_edid, get_vrr_range, ); -- 2.35.1
[PATCH 03/11] drm/edid: s/monitor_rage/vrr_range/
From: Ville Syrjälä
Rename info->monitor_range to info->vrr_range to actually
reflect its usage.
Cc: Manasi Navare
Cc: Nicholas Kazlauskas
Cc: Harry Wentland
Cc: Leo Li
Cc: Rodrigo Siqueira
Cc: amd-gfx@lists.freedesktop.org
Signed-off-by: Ville Syrjälä
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 12 -
drivers/gpu/drm/drm_debugfs.c | 4 +--
drivers/gpu/drm/drm_edid.c| 26 +--
drivers/gpu/drm/i915/display/intel_vrr.c | 6 ++---
include/drm/drm_connector.h | 4 +--
5 files changed, 26 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index e702f0d72d53..928b5b6541db 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -9921,8 +9921,8 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector
*connector,
amdgpu_dm_connector->min_vfreq = 0;
amdgpu_dm_connector->max_vfreq = 0;
amdgpu_dm_connector->pixel_clock_mhz = 0;
- connector->display_info.monitor_range.min_vfreq = 0;
- connector->display_info.monitor_range.max_vfreq = 0;
+ connector->display_info.vrr_range.min_vfreq = 0;
+ connector->display_info.vrr_range.max_vfreq = 0;
freesync_capable = false;
goto update;
@@ -9970,8 +9970,8 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector
*connector,
amdgpu_dm_connector->pixel_clock_mhz =
range->pixel_clock_mhz * 10;
- connector->display_info.monitor_range.min_vfreq
= range->min_vfreq;
- connector->display_info.monitor_range.max_vfreq
= range->max_vfreq;
+ connector->display_info.vrr_range.min_vfreq =
range->min_vfreq;
+ connector->display_info.vrr_range.max_vfreq =
range->max_vfreq;
break;
}
@@ -9993,8 +9993,8 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector
*connector,
if (amdgpu_dm_connector->max_vfreq -
amdgpu_dm_connector->min_vfreq > 10)
freesync_capable = true;
- connector->display_info.monitor_range.min_vfreq =
vsdb_info.min_refresh_rate_hz;
- connector->display_info.monitor_range.max_vfreq =
vsdb_info.max_refresh_rate_hz;
+ connector->display_info.vrr_range.min_vfreq =
vsdb_info.min_refresh_rate_hz;
+ connector->display_info.vrr_range.max_vfreq =
vsdb_info.max_refresh_rate_hz;
}
}
diff --git a/drivers/gpu/drm/drm_debugfs.c b/drivers/gpu/drm/drm_debugfs.c
index 01ee3febb813..1437c798b122 100644
--- a/drivers/gpu/drm/drm_debugfs.c
+++ b/drivers/gpu/drm/drm_debugfs.c
@@ -377,8 +377,8 @@ static int vrr_range_show(struct seq_file *m, void *data)
if (connector->status != connector_status_connected)
return -ENODEV;
- seq_printf(m, "Min: %u\n",
connector->display_info.monitor_range.min_vfreq);
- seq_printf(m, "Max: %u\n",
connector->display_info.monitor_range.max_vfreq);
+ seq_printf(m, "Min: %u\n", connector->display_info.vrr_range.min_vfreq);
+ seq_printf(m, "Max: %u\n", connector->display_info.vrr_range.max_vfreq);
return 0;
}
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index ac662495635c..4355d73632c3 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -6020,11 +6020,11 @@ static void drm_parse_cea_ext(struct drm_connector
*connector,
}
static
-void get_monitor_range(const struct detailed_timing *timing, void *c)
+void get_vrr_range(const struct detailed_timing *timing, void *c)
{
struct detailed_mode_closure *closure = c;
struct drm_display_info *info = >connector->display_info;
- struct drm_monitor_range_info *monitor_range = >monitor_range;
+ struct drm_monitor_range_info *vrr_range = >vrr_range;
const struct detailed_non_pixel *data = >data.other_data;
const struct detailed_data_monitor_range *range = >data.range;
const struct edid *edid = closure->drm_edid->edid;
@@ -6044,19 +6044,19 @@ void get_monitor_range(const struct detailed_timing
*timing, void *c)
if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG)
return;
- monitor_range->min_vfreq = range->min_vfreq;
- monitor_range->max_vfreq = range->max_vfreq;
+ vrr_range->min_vfreq = range->min_vfreq;
+ vrr_range->max_vfreq = range->max_vfreq;
if (edid->revision >= 4) {
if (data->pad2 & DRM_EDID_RANGE_OFFSET_MIN_VFREQ)
- monitor_range->min_vfreq
[PATCH 02/11] drm/edid: Clarify why we only accept the "range limits only" descriptor
From: Ville Syrjälä The current comment fails to clarify why we only accept the "range limits only" variant of the range descriptor. Reword it to make some actual sense. Cc: Manasi Navare Cc: Nicholas Kazlauskas Cc: Harry Wentland Cc: Leo Li Cc: Rodrigo Siqueira Cc: amd-gfx@lists.freedesktop.org Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/drm_edid.c | 11 +++ 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index 4005dab6147d..ac662495635c 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -6033,10 +6033,13 @@ void get_monitor_range(const struct detailed_timing *timing, void *c) return; /* -* Check for flag range limits only. If flag == 1 then -* no additional timing information provided. -* Default GTF, GTF Secondary curve and CVT are not -* supported +* These limits are used to determine the VRR refresh +* rate range. Only the "range limits only" variant +* of the range descriptor seems to guarantee that +* any and all timings are accepted by the sink, as +* opposed to just timings conforming to the indicated +* formula (GTF/GTF2/CVT). Thus other variants of the +* range descriptor are not accepted here. */ if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG) return; -- 2.35.1
Re: [PATCH -next] drm/amdgpu: add missing pci_disable_device() in amdgpu_pmops_runtime_resume()
Applied. Thanks!
Alex
On Fri, Aug 26, 2022 at 4:50 AM Yang Yingliang wrote:
>
> Add missing pci_disable_device() if amdgpu_device_resume() fails.
>
> Fixes: 8e4d5d43cc6c ("drm/amdgpu: Handling of amdgpu_device_resume return
> value for graceful teardown")
> Signed-off-by: Yang Yingliang
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 5 -
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index 429fcdf28836..de7144b06e93 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -2563,8 +2563,11 @@ static int amdgpu_pmops_runtime_resume(struct device
> *dev)
> amdgpu_device_baco_exit(drm_dev);
> }
> ret = amdgpu_device_resume(drm_dev, false);
> - if (ret)
> + if (ret) {
> + if (amdgpu_device_supports_px(drm_dev))
> + pci_disable_device(pdev);
> return ret;
> + }
>
> if (amdgpu_device_supports_px(drm_dev))
> drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
> --
> 2.25.1
>
Re: [PATCH] drm/amd/display: Fix variable dereferenced before check
Applied. Thanks! Alex On Fri, Aug 26, 2022 at 4:41 AM sunliming wrote: > > Fixes the following smatch warning: > > drivers/gpu/drm/amd/amdgpu/../display/dc/dc_dmub_srv.c:311 > dc_dmub_srv_p_state_delegate() > warn: variable dereferenced before check 'dc' (see line 309) > > Reported-by: kernel test robot > Reported-by: Dan Carpenter > Signed-off-by: sunliming > --- > drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c > b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c > index 09b304507bad..ebf99e8f93e0 100644 > --- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c > +++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c > @@ -323,11 +323,13 @@ bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool > should_manage_pstate, stru > struct dmub_cmd_fw_assisted_mclk_switch_config *config_data = > _assisted_mclk_switch.config_data; > int i = 0; > int ramp_up_num_steps = 1; // TODO: Ramp is currently disabled. > Reenable it. > - uint8_t visual_confirm_enabled = dc->debug.visual_confirm == > VISUAL_CONFIRM_FAMS; > + uint8_t visual_confirm_enabled; > > if (dc == NULL) > return false; > > + visual_confirm_enabled = dc->debug.visual_confirm == > VISUAL_CONFIRM_FAMS; > + > // Format command. > cmd.fw_assisted_mclk_switch.header.type = > DMUB_CMD__FW_ASSISTED_MCLK_SWITCH; > cmd.fw_assisted_mclk_switch.header.sub_type = > DMUB_CMD__FAMS_SETUP_FW_CTRL; > -- > 2.25.1 >
Re: [PATCH linux-next] drm/amdgpu: Remove the unneeded result variable
Applied. Thanks!
Alex
On Fri, Aug 26, 2022 at 3:24 AM wrote:
>
> From: ye xingchen
>
> Return the value sdma_v5_2_start() directly instead of storing it in
> another redundant variable.
>
> Reported-by: Zeal Robot
> Signed-off-by: ye xingchen
> ---
> drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 5 +
> 1 file changed, 1 insertion(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> index 83c6ccaaa9e4..95689ef4be10 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> @@ -1413,12 +1413,9 @@ static int sdma_v5_2_sw_fini(void *handle)
>
> static int sdma_v5_2_hw_init(void *handle)
> {
> - int r;
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> - r = sdma_v5_2_start(adev);
> -
> - return r;
> + return sdma_v5_2_start(adev);
> }
>
> static int sdma_v5_2_hw_fini(void *handle)
> --
> 2.25.1
Re: [PATCH] drm: Fix repeated word in comments
On Fri, Aug 26, 2022 at 10:03 AM Jules Maselbas wrote:
>
> Remove redundant words `the` and `this`.
>
> CC: David Airlie
> CC: Maxime Ripard
> CC: Thomas Zimmermann
> CC: amd-gfx@lists.freedesktop.org
> CC: dri-de...@lists.freedesktop.org
> Signed-off-by: Jules Maselbas
Please split this up per driver.
Thanks!
Alex
> ---
> .../gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h | 2 +-
> .../gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h | 2 +-
> drivers/gpu/drm/display/drm_dp_helper.c | 2 +-
> drivers/gpu/drm/drm_panel_orientation_quirks.c | 2 +-
> drivers/gpu/drm/i915/gvt/scheduler.c| 2 +-
> drivers/gpu/drm/i915/i915_irq.c | 2 +-
> drivers/gpu/drm/panel/panel-novatek-nt35510.c | 2 +-
> 7 files changed, 7 insertions(+), 7 deletions(-)
>
> diff --git
> a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h
> b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h
> index 43d43d6addc0..4164da83380f 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h
> +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h
> @@ -486,7 +486,7 @@ typedef struct {
>uint16_t Tvr_socLimit;// Celcius
>uint32_t FitLimit;// Failures in time (failures per
> million parts over the defined lifetime)
>
> - uint16_t PpmPowerLimit; // Switch this this power limit when
> temperature is above PpmTempThreshold
> + uint16_t PpmPowerLimit; // Switch this power limit when
> temperature is above PpmTempThreshold
>uint16_t PpmTemperatureThreshold;
>
>// SECTION: Throttler settings
> diff --git
> a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h
> b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h
> index 04752ade1016..ba7c68a20425 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h
> +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h
> @@ -544,7 +544,7 @@ typedef struct {
>uint16_t TplxLimit; // Celcius
>uint32_t FitLimit;// Failures in time (failures per
> million parts over the defined lifetime)
>
> - uint16_t PpmPowerLimit; // Switch this this power limit when
> temperature is above PpmTempThreshold
> + uint16_t PpmPowerLimit; // Switch this power limit when
> temperature is above PpmTempThreshold
>uint16_t PpmTemperatureThreshold;
>
>// SECTION: Throttler settings
> diff --git a/drivers/gpu/drm/display/drm_dp_helper.c
> b/drivers/gpu/drm/display/drm_dp_helper.c
> index e5bab236b3ae..32b295003f49 100644
> --- a/drivers/gpu/drm/display/drm_dp_helper.c
> +++ b/drivers/gpu/drm/display/drm_dp_helper.c
> @@ -1597,7 +1597,7 @@ static int drm_dp_aux_reply_duration(const struct
> drm_dp_aux_msg *msg)
>
> /*
> * Calculate the length of the i2c transfer in usec, assuming
> - * the i2c bus speed is as specified. Gives the the "worst"
> + * the i2c bus speed is as specified. Gives the "worst"
> * case estimate, ie. successful while as long as possible.
> * Doesn't account the "MOT" bit, and instead assumes each
> * message includes a START, ADDRESS and STOP. Neither does it
> diff --git a/drivers/gpu/drm/drm_panel_orientation_quirks.c
> b/drivers/gpu/drm/drm_panel_orientation_quirks.c
> index fc1728d46ac2..dde2f4c4c6cb 100644
> --- a/drivers/gpu/drm/drm_panel_orientation_quirks.c
> +++ b/drivers/gpu/drm/drm_panel_orientation_quirks.c
> @@ -349,7 +349,7 @@ static const struct dmi_system_id orientation_data[] = {
> * resolution expected by the quirk-table entry.
> *
> * Note this function is also used outside of the drm-subsys, by for example
> - * the efifb code. Because of this this function gets compiled into its own
> + * the efifb code. Because of this function gets compiled into its own
> * kernel-module when built as a module.
> *
> * Returns:
> diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c
> b/drivers/gpu/drm/i915/gvt/scheduler.c
> index d6fe94cd0fdb..7670ae4dd8fa 100644
> --- a/drivers/gpu/drm/i915/gvt/scheduler.c
> +++ b/drivers/gpu/drm/i915/gvt/scheduler.c
> @@ -193,7 +193,7 @@ static int populate_shadow_context(struct
> intel_vgpu_workload *workload)
> workload->ring_context_gpa);
>
> /* only need to ensure this context is not pinned/unpinned during the
> -* period from last submission to this this submission.
> +* period from last submission to this submission.
> * Upon reaching this function, the currently submitted context is not
> * supposed to get unpinned. If a misbehaving guest driver ever does
> * this, it would corrupt itself.
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 73cebc6aa650..783a6ca41a61 100644
> ---
Re: [PATCH] drm/amdgpu: ensure no PCIe peer access for CPU XGMI iolinks
On Fri, Aug 26, 2022 at 11:48 AM Alex Sierra wrote: > > [Why] Devices with CPU XGMI iolink do not support PCIe peer access. > > Signed-off-by: Alex Sierra Acked-by: Alex Deucher > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > index ce7d117efdb5..1ff66718639d 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > @@ -5538,7 +5538,8 @@ bool amdgpu_device_is_peer_accessible(struct > amdgpu_device *adev, > return pcie_p2p && p2p_access && (adev->gmc.visible_vram_size && > adev->gmc.real_vram_size == adev->gmc.visible_vram_size && > !(adev->gmc.aper_base & address_mask || > - aper_limit & address_mask)); > + aper_limit & address_mask) && > + !adev->gmc.xgmi.connected_to_cpu); > #else > return false; > #endif > -- > 2.32.0 >
[PATCH 3/3] drm/amdgpu: add new ip block for LSDMA 6.0
From: Hawking Zhang Add ip block support for lsdma v6_0_3. Signed-off-by: Hawking Zhang Reviewed-by: Frank Min Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index b5c979494c55..709fc61e3305 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -2336,6 +2336,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) case IP_VERSION(6, 0, 0): case IP_VERSION(6, 0, 1): case IP_VERSION(6, 0, 2): + case IP_VERSION(6, 0, 3): adev->lsdma.funcs = _v6_0_funcs; break; default: -- 2.37.1
[PATCH 2/3] drm/amdgpu: add new ip block for sdma 6.0
From: Hawking Zhang Add ip block support for sdma v6_0_3. Signed-off-by: Hawking Zhang Reviewed-by: Frank Min Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index 27b0f7facb8d..b5c979494c55 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -1826,6 +1826,7 @@ static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev) case IP_VERSION(6, 0, 0): case IP_VERSION(6, 0, 1): case IP_VERSION(6, 0, 2): + case IP_VERSION(6, 0, 3): amdgpu_device_ip_block_add(adev, _v6_0_ip_block); break; default: -- 2.37.1
[PATCH 1/3] drm/amdgpu: declare firmware for new SDMA 6.0.3
From: Hawking Zhang
To support new sdma ip block
Signed-off-by: Hawking Zhang
Reviewed-by: Frank Min
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
index 0200cb3a31a4..2bc1407e885e 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
@@ -47,6 +47,7 @@
MODULE_FIRMWARE("amdgpu/sdma_6_0_0.bin");
MODULE_FIRMWARE("amdgpu/sdma_6_0_1.bin");
MODULE_FIRMWARE("amdgpu/sdma_6_0_2.bin");
+MODULE_FIRMWARE("amdgpu/sdma_6_0_3.bin");
#define SDMA1_REG_OFFSET 0x600
#define SDMA0_HYP_DEC_REG_START 0x5880
--
2.37.1
[PATCH 4/4] drm/amdgpu: enable smu block for smu 13.0.10
From: John Clements Force to enable smu block for SMU v13.0.10 Signed-off-by: John Clements Signed-off-by: Likun Gao Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index 533e40dea5c5..27b0f7facb8d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -1684,6 +1684,7 @@ static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev) case IP_VERSION(13, 0, 5): case IP_VERSION(13, 0, 7): case IP_VERSION(13, 0, 8): + case IP_VERSION(13, 0, 10): amdgpu_device_ip_block_add(adev, _v13_0_ip_block); break; default: -- 2.37.1
[PATCH 3/4] drm/amdgpu: added supported smu 13.0.10 sw pptable
From: John Clements added sw pptable id for smu 13.0.10 Signed-off-by: John Clements Signed-off-by: Likun Gao Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c index 8e17bd5b52ab..94a2826236eb 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c @@ -500,6 +500,8 @@ int smu_v13_0_setup_pptable(struct smu_context *smu) return -EINVAL; } } + else if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 10)) + pptable_id = ; } /* force using vbios pptable in sriov mode */ -- 2.37.1
[PATCH 1/4] drm/amd/pm: add smu_v13_0_10 support
From: Yang Wang
add smu_v13_0_10 support.
Signed-off-by: Yang Wang
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 1 +
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 55b7910b4385..13c5c7f1ecb9 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -605,6 +605,7 @@ static int smu_set_funcs(struct amdgpu_device *adev)
smu->od_enabled = true;
break;
case IP_VERSION(13, 0, 0):
+ case IP_VERSION(13, 0, 10):
smu_v13_0_0_set_ppt_funcs(smu);
break;
case IP_VERSION(13, 0, 7):
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index 3651f6f75068..fa3e5d1d1d2e 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -59,6 +59,7 @@
MODULE_FIRMWARE("amdgpu/aldebaran_smc.bin");
MODULE_FIRMWARE("amdgpu/smu_13_0_0.bin");
MODULE_FIRMWARE("amdgpu/smu_13_0_7.bin");
+MODULE_FIRMWARE("amdgpu/smu_13_0_10.bin");
#define mmMP1_SMN_C2PMSG_66
0x0282
#define mmMP1_SMN_C2PMSG_66_BASE_IDX
0
--
2.37.1
[PATCH 2/4] drm/amd/pm: add smu_v13_0_10 driver if version
From: Yang Wang add smu_v13_0_10 driver if version Signed-off-by: Yang Wang Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h | 1 + drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h index ac308e72241a..950fb7c7d28d 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h @@ -32,6 +32,7 @@ #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_5 0x04 #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_0 0x2E #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_7 0x2C +#define SMU13_DRIVER_IF_VERSION_SMU_V13_0_10 0x1D #define SMU13_MODE1_RESET_WAIT_TIME_IN_MS 500 //500ms diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c index fa3e5d1d1d2e..8e17bd5b52ab 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c @@ -331,6 +331,9 @@ int smu_v13_0_check_fw_version(struct smu_context *smu) case IP_VERSION(13, 0, 5): smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_5; break; + case IP_VERSION(13, 0, 10): + smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_10; + break; default: dev_err(adev->dev, "smu unsupported IP version: 0x%x.\n", adev->ip_versions[MP1_HWIP][0]); -- 2.37.1
[PATCH 3/3] drm/amdgpu: add new ip block for PSP 13.0
From: Frank Min Add ip block support for psp v13_0_10. Signed-off-by: Frank Min Signed-off-by: Hawking Zhang Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index c2e8a9fe81f7..533e40dea5c5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -1634,6 +1634,7 @@ static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev) case IP_VERSION(13, 0, 5): case IP_VERSION(13, 0, 7): case IP_VERSION(13, 0, 8): + case IP_VERSION(13, 0, 10): amdgpu_device_ip_block_add(adev, _v13_0_ip_block); break; case IP_VERSION(13, 0, 4): -- 2.37.1
[PATCH 2/3] drm/amdgpu: added firmware module for psp 13.0.10
From: John Clements
added missing firmware module
Signed-off-by: John Clements
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/psp_v13_0.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
index 38553e8141f1..eac33d5c93e7 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
@@ -43,6 +43,7 @@ MODULE_FIRMWARE("amdgpu/psp_13_0_0_sos.bin");
MODULE_FIRMWARE("amdgpu/psp_13_0_0_ta.bin");
MODULE_FIRMWARE("amdgpu/psp_13_0_7_sos.bin");
MODULE_FIRMWARE("amdgpu/psp_13_0_7_ta.bin");
+MODULE_FIRMWARE("amdgpu/psp_13_0_10_sos.bin");
/* For large FW files the time to complete can be very long */
#define USBC_PD_POLLING_LIMIT_S 240
--
2.37.1
[PATCH 1/3] drm/amdgpu: support psp v13_0_10 ip block
From: Frank Min Add psp v13_0_10 ip block, initialize firmware and psp functions Signed-off-by: Frank Min Signed-off-by: Hawking Zhang Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 1 + drivers/gpu/drm/amd/amdgpu/psp_v13_0.c | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index c932bc148554..b007371df59c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -138,6 +138,7 @@ static int psp_early_init(void *handle) case IP_VERSION(13, 0, 3): case IP_VERSION(13, 0, 5): case IP_VERSION(13, 0, 8): + case IP_VERSION(13, 0, 10): psp_v13_0_set_psp_funcs(psp); psp->autoload_supported = true; break; diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c index c39e8b333181..38553e8141f1 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c @@ -108,6 +108,7 @@ static int psp_v13_0_init_microcode(struct psp_context *psp) break; case IP_VERSION(13, 0, 0): case IP_VERSION(13, 0, 7): + case IP_VERSION(13, 0, 10): err = psp_init_sos_microcode(psp, chip_name); if (err) return err; -- 2.37.1
[PATCH 2/3] drm/amdgpu: Enable pg/cg flags on GC11_0_3 for VCN
From: Sonny Jiang This enable VCN PG, CG, DPG and JPEG PG, CG Signed-off-by: Sonny Jiang Reviewed-by: Leo Liu Reviewed-by: John Clements Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/soc21.c | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c index f87dfae4efda..54bce19a52ec 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc21.c +++ b/drivers/gpu/drm/amd/amdgpu/soc21.c @@ -628,8 +628,11 @@ static int soc21_common_early_init(void *handle) adev->external_rev_id = adev->rev_id + 0x1; break; case IP_VERSION(11, 0, 3): - adev->cg_flags = 0; - adev->pg_flags = 0; + adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG | + AMD_CG_SUPPORT_JPEG_MGCG; + adev->pg_flags = AMD_PG_SUPPORT_VCN | + AMD_PG_SUPPORT_VCN_DPG | + AMD_PG_SUPPORT_JPEG; adev->external_rev_id = adev->rev_id + 0x20; break; default: -- 2.37.1
[PATCH 3/3] drm/amdgpu: add new ip block for SOC21
From: Hawking Zhang Add ip block support for soc21_common. Signed-off-by: Hawking Zhang Reviewed-by: Frank Min Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index 95d34590cad1..c2e8a9fe81f7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -1506,6 +1506,7 @@ static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev) case IP_VERSION(11, 0, 0): case IP_VERSION(11, 0, 1): case IP_VERSION(11, 0, 2): + case IP_VERSION(11, 0, 3): amdgpu_device_ip_block_add(adev, _common_ip_block); break; default: -- 2.37.1
[PATCH 1/3] drm/amdgpu: initialize common sw config for v11_0_3
From: Hawking Zhang init cp/pg_flags and extenal_rev_id Signed-off-by: Hawking Zhang Reviewed-by: Frank Min Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/soc21.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c index 55284b24f113..f87dfae4efda 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc21.c +++ b/drivers/gpu/drm/amd/amdgpu/soc21.c @@ -627,6 +627,11 @@ static int soc21_common_early_init(void *handle) AMD_PG_SUPPORT_JPEG; adev->external_rev_id = adev->rev_id + 0x1; break; + case IP_VERSION(11, 0, 3): + adev->cg_flags = 0; + adev->pg_flags = 0; + adev->external_rev_id = adev->rev_id + 0x20; + break; default: /* FIXME: not supported yet */ return -EINVAL; -- 2.37.1
[PATCH] drm/amdgpu: drop gc 11_0_0 golden settings
From: Hawking Zhang
driver doesn't need to program any gc 11_0_0 golden
Signed-off-by: Hawking Zhang
Reviewed-by: Likun Gao
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 41 --
1 file changed, 41 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index f6b1bb40e503..8d985004927b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -74,21 +74,6 @@ MODULE_FIRMWARE("amdgpu/gc_11_0_2_me.bin");
MODULE_FIRMWARE("amdgpu/gc_11_0_2_mec.bin");
MODULE_FIRMWARE("amdgpu/gc_11_0_2_rlc.bin");
-static const struct soc15_reg_golden golden_settings_gc_11_0[] =
-{
- /* Pending on emulation bring up */
-};
-
-static const struct soc15_reg_golden golden_settings_gc_11_0_0[] =
-{
- /* Pending on emulation bring up */
-};
-
-static const struct soc15_reg_golden golden_settings_gc_rlc_spm_11_0[] =
-{
- /* Pending on emulation bring up */
-};
-
static const struct soc15_reg_golden golden_settings_gc_11_0_1[] =
{
SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_GS_NGG_CLK_CTRL, 0x9fff8fff,
0x0010),
@@ -269,34 +254,10 @@ static void gfx_v11_0_set_kiq_pm4_funcs(struct
amdgpu_device *adev)
adev->gfx.kiq.pmf = _v11_0_kiq_pm4_funcs;
}
-static void gfx_v11_0_init_spm_golden_registers(struct amdgpu_device *adev)
-{
- switch (adev->ip_versions[GC_HWIP][0]) {
- case IP_VERSION(11, 0, 0):
- soc15_program_register_sequence(adev,
- golden_settings_gc_rlc_spm_11_0,
- (const
u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_11_0));
- break;
- default:
- break;
- }
-}
-
static void gfx_v11_0_init_golden_registers(struct amdgpu_device *adev)
{
switch (adev->ip_versions[GC_HWIP][0]) {
- case IP_VERSION(11, 0, 0):
- soc15_program_register_sequence(adev,
- golden_settings_gc_11_0,
- (const
u32)ARRAY_SIZE(golden_settings_gc_11_0));
- soc15_program_register_sequence(adev,
- golden_settings_gc_11_0_0,
- (const
u32)ARRAY_SIZE(golden_settings_gc_11_0_0));
- break;
case IP_VERSION(11, 0, 1):
- soc15_program_register_sequence(adev,
- golden_settings_gc_11_0,
- (const
u32)ARRAY_SIZE(golden_settings_gc_11_0));
soc15_program_register_sequence(adev,
golden_settings_gc_11_0_1,
(const
u32)ARRAY_SIZE(golden_settings_gc_11_0_1));
@@ -304,7 +265,6 @@ static void gfx_v11_0_init_golden_registers(struct
amdgpu_device *adev)
default:
break;
}
- gfx_v11_0_init_spm_golden_registers(adev);
}
static void gfx_v11_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
@@ -1140,7 +1100,6 @@ static const struct amdgpu_gfx_funcs gfx_v11_0_gfx_funcs
= {
.read_wave_sgprs = _v11_0_read_wave_sgprs,
.read_wave_vgprs = _v11_0_read_wave_vgprs,
.select_me_pipe_q = _v11_0_select_me_pipe_q,
- .init_spm_golden = _v11_0_init_spm_golden_registers,
.update_perfmon_mgcg = _v11_0_update_perf_clk,
};
--
2.37.1
[PATCH] drm/amdgpu: ensure no PCIe peer access for CPU XGMI iolinks
[Why] Devices with CPU XGMI iolink do not support PCIe peer access. Signed-off-by: Alex Sierra --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index ce7d117efdb5..1ff66718639d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -5538,7 +5538,8 @@ bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, return pcie_p2p && p2p_access && (adev->gmc.visible_vram_size && adev->gmc.real_vram_size == adev->gmc.visible_vram_size && !(adev->gmc.aper_base & address_mask || - aper_limit & address_mask)); + aper_limit & address_mask) && + !adev->gmc.xgmi.connected_to_cpu); #else return false; #endif -- 2.32.0
RE: [PATCH] drm/amdgpu: Handle potential NULL pointer dereference
[AMD Official Use Only - General] > -Original Message- > From: Ghannam, Yazen > Sent: Friday, August 26, 2022 11:20 AM > To: Russell, Kent > Cc: Lazar, Lijo ; amd-gfx@lists.freedesktop.org > Subject: Re: [PATCH] drm/amdgpu: Handle potential NULL pointer dereference > > On Thu, Aug 25, 2022 at 08:54:46AM -0400, Russell, Kent wrote: > > [AMD Official Use Only - General] > > > > It does indeed short-circuit on || (If the left side of an || statement is > > not 0, it > doesn't evaluate the right side and returns true). So we can ignore this > patch, > since checking for each individual field on the 2nd term is probably > overkill. We > were still investigating what got passed in and why it wasn't valid, so I'll > drop this > for now. Thanks Lijo! > > Right, the "||" will short-circuit, but not the "&&". > > ... > > > > + if (!m) > > > + return NOTIFY_DONE; > > > + > > > /* > > >* If the error was generated in UMC_V2, which belongs to GPU > > > UMCs, > > >* and error occurred in DramECC (Extended error code = 0) then > > > only > > >* process the error, else bail out. > > >*/ > > > - if (!m || !((smca_get_bank_type(m->extcpu, m->bank) == > SMCA_UMC_V2) && > > > + if (!((smca_get_bank_type(m->extcpu, m->bank) == SMCA_UMC_V2) && > > > (XEC(m->status, 0x3f) == 0x0))) > > If m is NULL, then we get (!m || "Don't care") = true. We avoid the second > operand. > > But then we have (true && "Something with 'm->' in it"). The second operand in > the && needs to be checked, and this will cause a NULL pointer dereference if > m is NULL. > > What do you guys think? > Since the 2nd field is in parentheses, it would be whatever = (smca_get_bank_type && XEC) if (!m || !(whatever)) In that case we should still jump out at !m, since the 2nd term is completely contained in that !((...)) clump. At least that's how I understand it after Lijo's original comments. Kent > Thanks, > Yazen
Re: [PATCH] drm/amdgpu: Handle potential NULL pointer dereference
On Thu, Aug 25, 2022 at 08:54:46AM -0400, Russell, Kent wrote: > [AMD Official Use Only - General] > > It does indeed short-circuit on || (If the left side of an || statement is > not 0, it doesn't evaluate the right side and returns true). So we can ignore > this patch, since checking for each individual field on the 2nd term is > probably overkill. We were still investigating what got passed in and why it > wasn't valid, so I'll drop this for now. Thanks Lijo! Right, the "||" will short-circuit, but not the "&&". ... > > + if (!m) > > + return NOTIFY_DONE; > > + > > /* > > * If the error was generated in UMC_V2, which belongs to GPU UMCs, > > * and error occurred in DramECC (Extended error code = 0) then only > > * process the error, else bail out. > > */ > > - if (!m || !((smca_get_bank_type(m->extcpu, m->bank) == SMCA_UMC_V2) && > > + if (!((smca_get_bank_type(m->extcpu, m->bank) == SMCA_UMC_V2) && > > (XEC(m->status, 0x3f) == 0x0))) If m is NULL, then we get (!m || "Don't care") = true. We avoid the second operand. But then we have (true && "Something with 'm->' in it"). The second operand in the && needs to be checked, and this will cause a NULL pointer dereference if m is NULL. What do you guys think? Thanks, Yazen
Re: [PATCH 4/4] amd/display: indicate support for atomic async page-flips on DCN
On Fri, Aug 26, 2022 at 3:38 AM Simon Ser wrote: > > On Thursday, August 25th, 2022 at 20:22, Alex Deucher > wrote: > > > On Wed, Aug 24, 2022 at 11:09 AM Simon Ser cont...@emersion.fr wrote: > > > > > amdgpu_dm_commit_planes already sets the flip_immediate flag for > > > async page-flips. This flag is used to set the UNP_FLIP_CONTROL > > > register. Thus, no additional change is required to handle async > > > page-flips with the atomic uAPI. > > > > > > Note, async page-flips are still unsupported on DCE with the atomic > > > uAPI. The mode_set_base callbacks unconditionally set the > > > GRPH_SURFACE_UPDATE_H_RETRACE_EN field of the GRPH_FLIP_CONTROL > > > register to 0, which disables async page-flips. > > > > Can you elaborate a bit on this? We don't use hsync flips at all, even > > in non-atomic, as far as I recall. The hardware can also do immediate > > flips which take effect as soon as you update the base address > > register which is what we use for async updates today IIRC. > > When user-space performs a page-flip with the legacy KMS uAPI on DCE > ASICs, amdgpu_display_crtc_page_flip_target() is called. This function > checks for the DRM_MODE_PAGE_FLIP_ASYNC flag, sets work->async, which > is then passed as an argument to adev->mode_info.funcs->page_flip() by > amdgpu_display_flip_work_func(). Looking at an implementation, for > instance dce_v10_0_page_flip(), the async flag is used to set that > GRPH_FLIP_CONTROL register: > > /* flip at hsync for async, default is vsync */ > tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); > tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL, > GRPH_SURFACE_UPDATE_H_RETRACE_EN, async ? 1 : 0); > WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); > > I don't know how the hardware works, but I assumed it would be > necessary to do the same in the atomic uAPI code-path as well. However > dce_v10_0_crtc_do_set_base() has this code block: > > /* Make sure surface address is updated at vertical blank rather than > * horizontal blank > */ > tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); > tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL, > GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0); > WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); > > Which unconditionally sets that same register. > > Either way, it's not a very big deal for this patch series, DCE and DCN > are separate, DCE can be sorted out separately. > > Am I completely mistaken here? I checked the code and it looks like only DCE11 and newer support immediate flips. E.g., /* flip immediate for async, default is vsync */ tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL, GRPH_SURFACE_UPDATE_IMMEDIATE_EN, async ? 1 : 0); in dce_v11_0.c. Either way, the non-DC display code is not atomic anyway, so I don't think this is an issue. We still support async flips via the non-atomic API. I agree this is not blocking for the patch series, just thinking out loud mostly. Alex > > Thanks, > > Simon
Re: mainline build failure for x86_64 allmodconfig with clang
On Thu, Aug 25, 2022 at 6:34 PM Nathan Chancellor wrote: > > Hi AMD folks, > > Top posting because it might not have been obvious but I was looking for > your feedback on this message (which can be viewed on lore.kernel.org if > you do not have the original [1]) so that we can try to get this fixed > in some way for 6.0/6.1. If my approach is not welcome, please consider > suggesting another one or looking to see if this is something you all > could look into. The patch looks good to me. I was hoping Harry or Rodrigo could comment more since they are more familiar with this code and trying to keep it in sync with what we get from the hardware teams. Alex > > [1]: https://lore.kernel.org/Yv5h0rb3AgTZLVJv@dev-arch.thelio-3990X/ > > Cheers, > Nathan > > On Thu, Aug 18, 2022 at 08:59:14AM -0700, Nathan Chancellor wrote: > > Hi Arnd, > > > > Doubling back around to this now since I think this is the only thing > > breaking x86_64 allmodconfig with clang 11 through 15. > > > > On Fri, Aug 05, 2022 at 09:32:13PM +0200, Arnd Bergmann wrote: > > > On Fri, Aug 5, 2022 at 8:02 PM Nathan Chancellor > > > wrote: > > > > On Fri, Aug 05, 2022 at 06:16:45PM +0200, Arnd Bergmann wrote: > > > > > On Fri, Aug 5, 2022 at 5:32 PM Harry Wentland > > > > > wrote: > > > > > While splitting out sub-functions can help reduce the maximum stack > > > > > usage, it seems that in this case it makes the actual problem worse: > > > > > I see 2168 bytes for the combined > > > > > dml32_ModeSupportAndSystemConfigurationFull(), but marking > > > > > mode_support_configuration() as noinline gives me 1992 bytes > > > > > for the outer function plus 384 bytes for the inner one. So it does > > > > > avoid the warning (barely), but not the problem that the warning tries > > > > > to point out. > > > > > > > > I haven't had a chance to take a look at splitting things up yet, would > > > > you recommend a different approach? > > > > > > Splitting up large functions can help when you have large local variables > > > that are used in different parts of the function, and the split gets the > > > compiler to reuse stack locations. > > > > > > I think in this particular function, the problem isn't actually local > > > variables > > > but either pushing variables on the stack for argument passing, > > > or something that causes the compiler to run out of registers so it > > > has to spill registers to the stack. > > > > > > In either case, one has to actually look at the generated output > > > and then try to rearrange the codes so this does not happen. > > > > > > One thing to try would be to condense a function call like > > > > > > dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport( > > > > > > >dummy_vars.dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport, > > > mode_lib->vba.USRRetrainingRequiredFinal, > > > mode_lib->vba.UsesMALLForPStateChange, > > > > > > mode_lib->vba.PrefetchModePerState[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb], > > > mode_lib->vba.NumberOfActiveSurfaces, > > > mode_lib->vba.MaxLineBufferLines, > > > mode_lib->vba.LineBufferSizeFinal, > > > mode_lib->vba.WritebackInterfaceBufferSize, > > > mode_lib->vba.DCFCLK, > > > mode_lib->vba.ReturnBW, > > > mode_lib->vba.SynchronizeTimingsFinal, > > > > > > mode_lib->vba.SynchronizeDRRDisplaysForUCLKPStateChangeFinal, > > > mode_lib->vba.DRRDisplay, > > > v->dpte_group_bytes, > > > v->meta_row_height, > > > v->meta_row_height_chroma, > > > > > > v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.mmSOCParameters, > > > mode_lib->vba.WritebackChunkSize, > > > mode_lib->vba.SOCCLK, > > > v->DCFCLKDeepSleep, > > > mode_lib->vba.DETBufferSizeY, > > > mode_lib->vba.DETBufferSizeC, > > > mode_lib->vba.SwathHeightY, > > > mode_lib->vba.SwathHeightC, > > > mode_lib->vba.LBBitPerPixel, > > > v->SwathWidthY, > > > v->SwathWidthC, > > > mode_lib->vba.HRatio, > > > mode_lib->vba.HRatioChroma, > > > mode_lib->vba.vtaps, > > > mode_lib->vba.VTAPsChroma, > > > mode_lib->vba.VRatio, > > > mode_lib->vba.VRatioChroma, > > > mode_lib->vba.HTotal, > > > mode_lib->vba.VTotal, > > > mode_lib->vba.VActive, > > >
Re: [PATCH 3/4] drm: introduce DRM_CAP_ATOMIC_ASYNC_PAGE_FLIP
On Wed, Aug 24, 2022 at 03:08:55PM +, Simon Ser wrote:
> This new kernel capability indicates whether async page-flips are
> supported via the atomic uAPI. DRM clients can use it to check
> for support before feeding DRM_MODE_PAGE_FLIP_ASYNC to the kernel.
I think we'd need to clarify the semantics of the async flag
for atomic commits.
Eg. on Intel hw only pure page flips are possible async, if you do
anything else (change plane size/pos/scaling/etc.) you will need
to do a sync update. Technically not even all page flips (from the
uapi POV) might be possible as the exact scanout source address
is specified via two registers, only one of which can be update
async. So technically the two framebuffers might be laid out
just slightly differently which could prevent an async flip.
Also only some subset of planes actually support async flips.
And on hw where multiple planes support it on the same crtc, only one
plane can do it at a time. Well, more accurately we can only select
one plane at a time to give us the "flip done" interrupt. I guess
if the user wants to async flip multiple planes at the same time
we could do them serially as opposed to in parallel to make sure
all the flips actually happened before we signal completion of the
entire commit. Async flips of multiple planes probably won't
happen atomically anyway so doing them serially seems fine.
ATM in i915 we probably don't have sufficient state checks in
place to catch all the restrictions, and instead in part we rely
on the limited scope of the legacy async flip ioctl to make sure
the operation doesn't attempt something the hw can't do.
> Make it clear that DRM_CAP_ASYNC_PAGE_FLIP is for legacy uAPI only.
>
> Signed-off-by: Simon Ser
> Cc: Daniel Vetter
> Cc: Joshua Ashton
> Cc: Melissa Wen
> Cc: Alex Deucher
> Cc: Harry Wentland
> Cc: Nicholas Kazlauskas
> ---
> drivers/gpu/drm/drm_ioctl.c | 5 +
> include/uapi/drm/drm.h | 10 +-
> 2 files changed, 14 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c
> index ca2a6e6101dc..5b1591e2b46c 100644
> --- a/drivers/gpu/drm/drm_ioctl.c
> +++ b/drivers/gpu/drm/drm_ioctl.c
> @@ -302,6 +302,11 @@ static int drm_getcap(struct drm_device *dev, void
> *data, struct drm_file *file_
> case DRM_CAP_CRTC_IN_VBLANK_EVENT:
> req->value = 1;
> break;
> + case DRM_CAP_ATOMIC_ASYNC_PAGE_FLIP:
> + req->value = drm_core_check_feature(dev, DRIVER_ATOMIC) &&
> + dev->mode_config.async_page_flip &&
> +
> !dev->mode_config.atomic_async_page_flip_not_supported;
> + break;
> default:
> return -EINVAL;
> }
> diff --git a/include/uapi/drm/drm.h b/include/uapi/drm/drm.h
> index 642808520d92..b1962628ecda 100644
> --- a/include/uapi/drm/drm.h
> +++ b/include/uapi/drm/drm.h
> @@ -706,7 +706,8 @@ struct drm_gem_open {
> /**
> * DRM_CAP_ASYNC_PAGE_FLIP
> *
> - * If set to 1, the driver supports _MODE_PAGE_FLIP_ASYNC.
> + * If set to 1, the driver supports _MODE_PAGE_FLIP_ASYNC for legacy
> + * page-flips.
> */
> #define DRM_CAP_ASYNC_PAGE_FLIP 0x7
> /**
> @@ -767,6 +768,13 @@ struct drm_gem_open {
> * Documentation/gpu/drm-mm.rst, section "DRM Sync Objects".
> */
> #define DRM_CAP_SYNCOBJ_TIMELINE 0x14
> +/**
> + * DRM_CAP_ATOMIC_ASYNC_PAGE_FLIP
> + *
> + * If set to 1, the driver supports _MODE_PAGE_FLIP_ASYNC for atomic
> + * commits.
> + */
> +#define DRM_CAP_ATOMIC_ASYNC_PAGE_FLIP 0x15
>
> /* DRM_IOCTL_GET_CAP ioctl argument type */
> struct drm_get_cap {
> --
> 2.37.2
>
--
Ville Syrjälä
Intel
Re: [PATCH 4/4] amd/display: indicate support for atomic async page-flips on DCN
On Thursday, August 25th, 2022 at 20:22, Alex Deucher wrote: > On Wed, Aug 24, 2022 at 11:09 AM Simon Ser cont...@emersion.fr wrote: > > > amdgpu_dm_commit_planes already sets the flip_immediate flag for > > async page-flips. This flag is used to set the UNP_FLIP_CONTROL > > register. Thus, no additional change is required to handle async > > page-flips with the atomic uAPI. > > > > Note, async page-flips are still unsupported on DCE with the atomic > > uAPI. The mode_set_base callbacks unconditionally set the > > GRPH_SURFACE_UPDATE_H_RETRACE_EN field of the GRPH_FLIP_CONTROL > > register to 0, which disables async page-flips. > > Can you elaborate a bit on this? We don't use hsync flips at all, even > in non-atomic, as far as I recall. The hardware can also do immediate > flips which take effect as soon as you update the base address > register which is what we use for async updates today IIRC. When user-space performs a page-flip with the legacy KMS uAPI on DCE ASICs, amdgpu_display_crtc_page_flip_target() is called. This function checks for the DRM_MODE_PAGE_FLIP_ASYNC flag, sets work->async, which is then passed as an argument to adev->mode_info.funcs->page_flip() by amdgpu_display_flip_work_func(). Looking at an implementation, for instance dce_v10_0_page_flip(), the async flag is used to set that GRPH_FLIP_CONTROL register: /* flip at hsync for async, default is vsync */ tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL, GRPH_SURFACE_UPDATE_H_RETRACE_EN, async ? 1 : 0); WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); I don't know how the hardware works, but I assumed it would be necessary to do the same in the atomic uAPI code-path as well. However dce_v10_0_crtc_do_set_base() has this code block: /* Make sure surface address is updated at vertical blank rather than * horizontal blank */ tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL, GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0); WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); Which unconditionally sets that same register. Either way, it's not a very big deal for this patch series, DCE and DCN are separate, DCE can be sorted out separately. Am I completely mistaken here? Thanks, Simon
Re: [Bug 216373] New: Uncorrected errors reported for AMD GPU
Am 25.08.22 um 19:48 schrieb Bjorn Helgaas: On Thu, Aug 25, 2022 at 10:18:28AM +0200, Christian König wrote: Am 25.08.22 um 09:54 schrieb Lazar, Lijo: On 8/25/2022 1:04 PM, Christian König wrote: Am 25.08.22 um 08:40 schrieb Stefan Roese: On 24.08.22 16:45, Tom Seewald wrote: On Wed, Aug 24, 2022 at 12:11 AM Lazar, Lijo wrote: Unfortunately, I don't have any NV platforms to test. Attached is an 'untested-patch' based on your trace logs. ... I did not follow this thread in depth, but FWICT the bug is solved now with this patch. So is it correct, that the now fully enabled AER support in the PCI subsystem in v6.0 helped detecting a bug in the AMD GPU driver? It looks like it, but I'm not 100% sure about the rational behind it. Lijo can you explain more on this? From the trace, during gmc hw_init it takes this route - gart_enable -> amdgpu_gtt_mgr_recover -> amdgpu_gart_invalidate_tlb -> amdgpu_device_flush_hdp -> amdgpu_asic_flush_hdp (non-ring based HDP flush) HDP flush is done using remapped offset which is MMIO_REG_HOLE_OFFSET (0x8 - PAGE_SIZE) WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); However, the remapping is not yet done at this point. It's done at a later point during common block initialization. Access to the unmapped offset '(0x8 - PAGE_SIZE)' seems to come back as unsupported request and reported through AER. That's interesting behavior. So far AER always indicated some kind of transmission error. When that happens as well on unmapped areas of the MMIO BAR then we need to keep that in mind. AER can log many different kinds of errors, some related to hardware issues and some related to software. PCI writes are normally posted and get no response, so AER is the main way to find out about writes to unimplemented addresses. Reads do get a response, of course, and reads to unimplemented addresses cause errors that most hardware turns into a ~0 data return (in addition to reporting via AER if enabled). The issue is that previous hardware generations reported this through a device specific interrupt. It's nice to see that this is finally standardized. I'm just wondering if we could retire our hardware specific interrupt handler for this as well. Christian. Bjorn
Re: [PATCH v5 17/31] ACPI: video: Add Nvidia WMI EC brightness control detection (v3)
On 8/25/22 9:37 AM, Hans de Goede wrote:
On some new laptop designs a new Nvidia specific WMI interface is present
which gives info about panel brightness control and may allow controlling
the brightness through this interface when the embedded controller is used
for brightness control.
When this WMI interface is present and indicates that the EC is used,
then this interface should be used for brightness control.
Changes in v2:
- Use the new shared nvidia-wmi-ec-backlight.h header for the
WMI firmware API definitions
- ACPI_VIDEO can now be enabled on non X86 too,
adjust the Kconfig changes to match this.
Changes in v3:
- Use WMI_BRIGHTNESS_GUID define
Acked-by: Rafael J. Wysocki
Signed-off-by: Hans de Goede
---
drivers/acpi/Kconfig | 1 +
drivers/acpi/video_detect.c| 37 ++
drivers/gpu/drm/gma500/Kconfig | 2 ++
drivers/gpu/drm/i915/Kconfig | 2 ++
include/acpi/video.h | 1 +
5 files changed, 43 insertions(+)
diff --git a/drivers/acpi/Kconfig b/drivers/acpi/Kconfig
index 7802d8846a8d..44ad4b6bd234 100644
--- a/drivers/acpi/Kconfig
+++ b/drivers/acpi/Kconfig
@@ -212,6 +212,7 @@ config ACPI_VIDEO
tristate "Video"
depends on BACKLIGHT_CLASS_DEVICE
depends on INPUT
+ depends on ACPI_WMI || !X86
select THERMAL
help
This driver implements the ACPI Extensions For Display Adapters
diff --git a/drivers/acpi/video_detect.c b/drivers/acpi/video_detect.c
index cc9d0d91e268..4dc7fb865083 100644
--- a/drivers/acpi/video_detect.c
+++ b/drivers/acpi/video_detect.c
@@ -32,6 +32,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -75,6 +76,36 @@ find_video(acpi_handle handle, u32 lvl, void *context, void
**rv)
return AE_OK;
}
+/* This depends on ACPI_WMI which is X86 only */
+#ifdef CONFIG_X86
This could probably also provide the { return false; } stub which you
have for non-x86 if the kernel is built without nvidia-wmi-ec-backight,
e.g.:
#if defined(CONFIG_X86) && (defined(CONFIG_NVIDIA_WMI_EC_BACKLIGHT) ||
defined(CONFIG_NVIDIA_WMI_EC_BACKLIGHT_MODULE))
Although I suppose that would break things if somebody has a kernel that
originally had NVIDIA_WMI_EC_BACKLIGHT=n in Kconfig, and then builds the
nvidia-wmi-ec-backlight driver out-of-tree later. I don't know whether
that's intended to be a supported use case, so I guess it is fine either
way.
+static bool nvidia_wmi_ec_supported(void)
+{
+ struct wmi_brightness_args args = {
+ .mode = WMI_BRIGHTNESS_MODE_GET,
+ .val = 0,
+ .ret = 0,
+ };
+ struct acpi_buffer buf = { (acpi_size)sizeof(args), };
+ acpi_status status;
+
+ status = wmi_evaluate_method(WMI_BRIGHTNESS_GUID, 0,
+WMI_BRIGHTNESS_METHOD_SOURCE, , );
+ if (ACPI_FAILURE(status))
+ return false;
+
+ /*
+* If brightness is handled by the EC then nvidia-wmi-ec-backlight
+* should be used, else the GPU driver(s) should be used.
+*/
+ return args.ret == WMI_BRIGHTNESS_SOURCE_EC;
+}
+#else
+static bool nvidia_wmi_ec_supported(void)
+{
+ return false;
+}
+#endif
+
/* Force to use vendor driver when the ACPI device is known to be
* buggy */
static int video_detect_force_vendor(const struct dmi_system_id *d)
@@ -541,6 +572,7 @@ static const struct dmi_system_id video_detect_dmi_table[]
= {
static enum acpi_backlight_type __acpi_video_get_backlight_type(bool native)
{
static DEFINE_MUTEX(init_mutex);
+ static bool nvidia_wmi_ec_present;
static bool native_available;
static bool init_done;
static long video_caps;
@@ -553,6 +585,7 @@ static enum acpi_backlight_type
__acpi_video_get_backlight_type(bool native)
acpi_walk_namespace(ACPI_TYPE_DEVICE, ACPI_ROOT_OBJECT,
ACPI_UINT32_MAX, find_video, NULL,
_caps, NULL);
+ nvidia_wmi_ec_present = nvidia_wmi_ec_supported();
init_done = true;
}
if (native)
@@ -570,6 +603,10 @@ static enum acpi_backlight_type
__acpi_video_get_backlight_type(bool native)
if (acpi_backlight_dmi != acpi_backlight_undef)
return acpi_backlight_dmi;
+ /* Special cases such as nvidia_wmi_ec and apple gmux. */
+ if (nvidia_wmi_ec_present)
+ return acpi_backlight_nvidia_wmi_ec;
+
/* On systems with ACPI video use either native or ACPI video. */
if (video_caps & ACPI_VIDEO_BACKLIGHT) {
/*
diff --git a/drivers/gpu/drm/gma500/Kconfig b/drivers/gpu/drm/gma500/Kconfig
index 0cff20265f97..807b989e3c77 100644
--- a/drivers/gpu/drm/gma500/Kconfig
+++ b/drivers/gpu/drm/gma500/Kconfig
@@ -7,6 +7,8 @@ config DRM_GMA500
select ACPI_VIDEO if ACPI
select
Re: [PATCH v5 15/31] platform/x86: nvidia-wmi-ec-backlight: Move fw interface definitions to a header (v2)
Thanks, Hans.
Reviewed-by: Daniel Dadap
On 8/25/22 9:37 AM, Hans de Goede wrote:
Move the WMI interface definitions to a header, so that the definitions
can be shared with drivers/acpi/video_detect.c .
Changes in v2:
- Add missing Nvidia copyright header
- Move WMI_BRIGHTNESS_GUID to nvidia-wmi-ec-backlight.h as well
Suggested-by: Daniel Dadap
Signed-off-by: Hans de Goede
---
MAINTAINERS | 1 +
.../platform/x86/nvidia-wmi-ec-backlight.c| 68 +
.../x86/nvidia-wmi-ec-backlight.h | 76 +++
3 files changed, 78 insertions(+), 67 deletions(-)
create mode 100644 include/linux/platform_data/x86/nvidia-wmi-ec-backlight.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 9d7f64dc0efe..d6f6b96f51f7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -14527,6 +14527,7 @@ M: Daniel Dadap
L:platform-driver-...@vger.kernel.org
S:Supported
F:drivers/platform/x86/nvidia-wmi-ec-backlight.c
+F: include/linux/platform_data/x86/nvidia-wmi-ec-backlight.h
NVM EXPRESS DRIVER
M:Keith Busch
diff --git a/drivers/platform/x86/nvidia-wmi-ec-backlight.c
b/drivers/platform/x86/nvidia-wmi-ec-backlight.c
index 61e37194df70..be803e47eac0 100644
--- a/drivers/platform/x86/nvidia-wmi-ec-backlight.c
+++ b/drivers/platform/x86/nvidia-wmi-ec-backlight.c
@@ -7,74 +7,10 @@
#include
#include
#include
+#include
#include
#include
-/**
- * enum wmi_brightness_method - WMI method IDs
- * @WMI_BRIGHTNESS_METHOD_LEVEL: Get/Set EC brightness level status
- * @WMI_BRIGHTNESS_METHOD_SOURCE: Get/Set EC Brightness Source
- */
-enum wmi_brightness_method {
- WMI_BRIGHTNESS_METHOD_LEVEL = 1,
- WMI_BRIGHTNESS_METHOD_SOURCE = 2,
- WMI_BRIGHTNESS_METHOD_MAX
-};
-
-/**
- * enum wmi_brightness_mode - Operation mode for WMI-wrapped method
- * @WMI_BRIGHTNESS_MODE_GET:Get the current brightness
level/source.
- * @WMI_BRIGHTNESS_MODE_SET:Set the brightness level.
- * @WMI_BRIGHTNESS_MODE_GET_MAX_LEVEL: Get the maximum brightness level. This
- * is only valid when the WMI method is
- * %WMI_BRIGHTNESS_METHOD_LEVEL.
- */
-enum wmi_brightness_mode {
- WMI_BRIGHTNESS_MODE_GET = 0,
- WMI_BRIGHTNESS_MODE_SET = 1,
- WMI_BRIGHTNESS_MODE_GET_MAX_LEVEL = 2,
- WMI_BRIGHTNESS_MODE_MAX
-};
-
-/**
- * enum wmi_brightness_source - Backlight brightness control source selection
- * @WMI_BRIGHTNESS_SOURCE_GPU: Backlight brightness is controlled by the GPU.
- * @WMI_BRIGHTNESS_SOURCE_EC: Backlight brightness is controlled by the
- * system's Embedded Controller (EC).
- * @WMI_BRIGHTNESS_SOURCE_AUX: Backlight brightness is controlled over the
- * DisplayPort AUX channel.
- */
-enum wmi_brightness_source {
- WMI_BRIGHTNESS_SOURCE_GPU = 1,
- WMI_BRIGHTNESS_SOURCE_EC = 2,
- WMI_BRIGHTNESS_SOURCE_AUX = 3,
- WMI_BRIGHTNESS_SOURCE_MAX
-};
-
-/**
- * struct wmi_brightness_args - arguments for the WMI-wrapped ACPI method
- * @mode:Pass in an wmi_brightness_mode value to select between
- * getting or setting a value.
- * @val: In parameter for value to set when using %WMI_BRIGHTNESS_MODE_SET
- * mode. Not used in conjunction with %WMI_BRIGHTNESS_MODE_GET or
- * %WMI_BRIGHTNESS_MODE_GET_MAX_LEVEL mode.
- * @ret: Out parameter returning retrieved value when operating in
- * %WMI_BRIGHTNESS_MODE_GET or %WMI_BRIGHTNESS_MODE_GET_MAX_LEVEL
- * mode. Not used in %WMI_BRIGHTNESS_MODE_SET mode.
- * @ignored: Padding; not used. The ACPI method expects a 24 byte params
struct.
- *
- * This is the parameters structure for the WmiBrightnessNotify ACPI method as
- * wrapped by WMI. The value passed in to @val or returned by @ret will be a
- * brightness value when the WMI method ID is %WMI_BRIGHTNESS_METHOD_LEVEL, or
- * an wmi_brightness_source value with %WMI_BRIGHTNESS_METHOD_SOURCE.
- */
-struct wmi_brightness_args {
- u32 mode;
- u32 val;
- u32 ret;
- u32 ignored[3];
-};
-
/**
* wmi_brightness_notify() - helper function for calling WMI-wrapped ACPI
method
* @w:Pointer to the struct wmi_device identified by %WMI_BRIGHTNESS_GUID
@@ -191,8 +127,6 @@ static int nvidia_wmi_ec_backlight_probe(struct wmi_device
*wdev, const void *ct
return PTR_ERR_OR_ZERO(bdev);
}
-#define WMI_BRIGHTNESS_GUID "603E9613-EF25-4338-A3D0-C46177516DB7"
-
static const struct wmi_device_id nvidia_wmi_ec_backlight_id_table[] = {
{ .guid_string = WMI_BRIGHTNESS_GUID },
{ }
diff --git a/include/linux/platform_data/x86/nvidia-wmi-ec-backlight.h
b/include/linux/platform_data/x86/nvidia-wmi-ec-backlight.h
new file mode 100644
index ..23d60130272c
--- /dev/null
+++ b/include/linux/platform_data/x86/nvidia-wmi-ec-backlight.h
@@
