[PATCH 2/4] drm/amdgpu: Add software ring callbacks for gfx9(v5)
From: "Jiadong.Zhu"
Set ring functions with software ring callbacks on gfx9.
The software ring could be tested by debugfs_test_ib case.
v2: Set sw_ring 2 to enable software ring by default.
v3: Remove the parameter for software ring enablement.
v4: Use amdgpu_ring_init/fini for software rings.
v5: Update for code format. Fix conflict.
Cc: Christian Koenig
Cc: Luben Tuikov
Cc: Andrey Grodzovsky
Signed-off-by: Jiadong.Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 2 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 7 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 3 +-
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c| 117 +--
5 files changed, 120 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 96d058c4cd4b..525df0b4d55f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -207,6 +207,7 @@ extern bool amdgpu_ignore_bad_page_threshold;
extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer;
extern int amdgpu_async_gfx_ring;
extern int amdgpu_mcbp;
+extern int amdgpu_sw_ring;
extern int amdgpu_discovery;
extern int amdgpu_mes;
extern int amdgpu_mes_kiq;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index 9996dadb39f7..93b25d9a87f9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -348,6 +348,8 @@ struct amdgpu_gfx {
boolis_poweron;
+ /* software ring */
+ unsignednum_sw_gfx_rings;
struct amdgpu_ring_mux muxer;
};
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
index 13db99d653bd..4eaf3bd332f7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
@@ -33,6 +33,7 @@
#include
#include "amdgpu.h"
+#include "amdgpu_sw_ring.h"
#include "atom.h"
/*
@@ -121,6 +122,11 @@ void amdgpu_ring_commit(struct amdgpu_ring *ring)
{
uint32_t count;
+ if (ring->is_sw_ring) {
+ amdgpu_sw_ring_commit(ring);
+ return;
+ }
+
/* We pad to match fetch size */
count = ring->funcs->align_mask + 1 -
(ring->wptr & ring->funcs->align_mask);
@@ -343,7 +349,6 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct
amdgpu_ring *ring,
*/
void amdgpu_ring_fini(struct amdgpu_ring *ring)
{
-
/* Not to finish a ring which is not initialized */
if (!(ring->adev) ||
(!ring->is_mes_queue && !(ring->adev->rings[ring->idx])))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 40b1277b4f0c..275b885363c3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -38,7 +38,8 @@ struct amdgpu_vm;
/* max number of rings */
#define AMDGPU_MAX_RINGS 28
#define AMDGPU_MAX_HWIP_RINGS 8
-#define AMDGPU_MAX_GFX_RINGS 2
+/*2 software ring and 1 real ring*/
+#define AMDGPU_MAX_GFX_RINGS 3
#define AMDGPU_MAX_COMPUTE_RINGS 8
#define AMDGPU_MAX_VCE_RINGS 3
#define AMDGPU_MAX_UVD_ENC_RINGS 2
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 5349ca4d19e3..e85565b0e52a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -47,6 +47,7 @@
#include "amdgpu_ras.h"
+#include "amdgpu_sw_ring.h"
#include "gfx_v9_4.h"
#include "gfx_v9_0.h"
#include "gfx_v9_4_2.h"
@@ -55,7 +56,8 @@
#include "asic_reg/pwr/pwr_10_0_sh_mask.h"
#include "asic_reg/gc/gc_9_0_default.h"
-#define GFX9_NUM_GFX_RINGS 1
+#define GFX9_NUM_GFX_RINGS 3
+#define GFX9_NUM_SW_GFX_RINGS 2
#define GFX9_MEC_HPD_SIZE 4096
#define RLCG_UCODE_LOADING_START_ADDRESS 0x2000L
#define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0xL
@@ -2270,6 +2272,7 @@ static int gfx_v9_0_compute_ring_init(struct
amdgpu_device *adev, int ring_id,
static int gfx_v9_0_sw_init(void *handle)
{
int i, j, k, r, ring_id;
+ unsigned int hw_prio;
struct amdgpu_ring *ring;
struct amdgpu_kiq *kiq;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -2356,13 +2359,41 @@ static int gfx_v9_0_sw_init(void *handle)
sprintf(ring->name, "gfx_%d", i);
ring->use_doorbell = true;
ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
+ ring->is_sw_ring = (adev->gfx.num_sw_gfx_rings > 1) && (i > 0);
+
+ if (adev->gfx.num_sw_gfx_rings > 1 && i == 2)
+ hw_prio = AMDGPU_RING_PRIO_2;
+ else
+ hw_prio = AMDGPU_RING_PRIO_DEFAULT;
+ if (adev->gfx.num_sw_gfx_
[PATCH] drm/amdgpu: Introduce gfx software ring(v5)
From: "Jiadong.Zhu"
The software ring is created to support priority context while there is only
one hardware queue for gfx.
Every software ring has its fence driver and could be used as an ordinary ring
for the GPU scheduler.
Multiple software rings are bound to a real ring with the ring muxer. The
packages committed on the software ring are copied to the real ring.
v2: Use array to store software ring entry.
v3: Remove unnecessary prints.
v4: Remove amdgpu_ring_sw_init/fini functions,
using gtt for sw ring buffer for later dma copy
optimization.
v5: Allocate ring entry dynamicly in the muxer.
Cc: Christian Koenig
Cc: Luben Tuikov
Cc: Andrey Grodzovsky
Signed-off-by: Jiadong.Zhu
---
drivers/gpu/drm/amd/amdgpu/Makefile | 3 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 3 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 4 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c | 176 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.h | 66 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_sw_ring.c | 60 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_sw_ring.h | 43 +
7 files changed, 354 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.h
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_sw_ring.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_sw_ring.h
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
b/drivers/gpu/drm/amd/amdgpu/Makefile
index 3e0e2eb7e235..85224bc81ce5 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -58,7 +58,8 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
amdgpu_vm_sdma.o amdgpu_discovery.o amdgpu_ras_eeprom.o amdgpu_nbio.o \
amdgpu_umc.o smu_v11_0_i2c.o amdgpu_fru_eeprom.o amdgpu_rap.o \
amdgpu_fw_attestation.o amdgpu_securedisplay.o \
- amdgpu_eeprom.o amdgpu_mca.o amdgpu_psp_ta.o amdgpu_lsdma.o
+ amdgpu_eeprom.o amdgpu_mca.o amdgpu_psp_ta.o amdgpu_lsdma.o \
+ amdgpu_sw_ring.o amdgpu_ring_mux.o
amdgpu-$(CONFIG_PROC_FS) += amdgpu_fdinfo.o
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index 53526ffb2ce1..9996dadb39f7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -33,6 +33,7 @@
#include "amdgpu_imu.h"
#include "soc15.h"
#include "amdgpu_ras.h"
+#include "amdgpu_ring_mux.h"
/* GFX current status */
#define AMDGPU_GFX_NORMAL_MODE 0xL
@@ -346,6 +347,8 @@ struct amdgpu_gfx {
struct amdgpu_gfx_ras *ras;
boolis_poweron;
+
+ struct amdgpu_ring_mux muxer;
};
#define amdgpu_gfx_get_gpu_clock_counter(adev)
(adev)->gfx.funcs->get_gpu_clock_counter((adev))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 7d89a52091c0..40b1277b4f0c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -278,6 +278,10 @@ struct amdgpu_ring {
boolis_mes_queue;
uint32_thw_queue_id;
struct amdgpu_mes_ctx_data *mes_ctx;
+
+ boolis_sw_ring;
+ unsigned intentry_index;
+
};
#define amdgpu_ring_parse_cs(r, p, job, ib) ((r)->funcs->parse_cs((p), (job),
(ib)))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c
new file mode 100644
index ..5e9c178f358b
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c
@@ -0,0 +1,176 @@
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#include
+#include
+
+#include "amdgpu_ring_mux.h"
+#include "amdgpu_ring.h"
+
+#define AMDGPU_MUX_RESUBMIT_JIFFIES_TIMEOUT (HZ/2)
+
+static void cop
RE: [PATCH 2/2] drm/amdgpu: move enable irq later to avoid race with ih resume
[AMD Official Use Only - General]
Hi Lijo,
IH resume was added to resolve an issue found during mode2 bring up on sienna
cichlid:
- close down mode2 reset and do a mode1 reset first
- open mode2 reset and do a mode2 reset. Mode2 reset was found fail in this
case.
Resume IH helps in this case
Thanks,
Victor
-Original Message-
From: Lazar, Lijo
Sent: Thursday, September 15, 2022 1:58 PM
To: Zhao, Victor ; amd-gfx@lists.freedesktop.org
Cc: Deng, Emily ; Grodzovsky, Andrey
Subject: Re: [PATCH 2/2] drm/amdgpu: move enable irq later to avoid race with
ih resume
On 9/14/2022 3:40 PM, Victor Zhao wrote:
> [background]
> On current sienna cichlid mode2 reset, on the slow job hang cases,
> since page table context was reverted to completely stop gpu, it will
> generate page fault interrupt.
>
> Since the irq are open during recovery stage, during ih resume step,
> if this interrupt was in processing, which increased ih ring rptr, and
> ih resume meanwhile will set rptr and wptr to 0. This may cause
AFAIK, only GFX/SDMA are affected by mode-2. IH is not suspended before mode-2.
Why do you resume IH after mode-2 when it is not suspended? Is it a special
case for virtualization?
Thanks,
Lijo
> rptr greater than wptr. Such case was not handled in ih process, and
> it will cause rptr continue increasing util reaches the max.
> Such case will make fence fallback situation happen.
>
> [how]
> Move the enable of irq after ih resumed and before ib test.
> Adjusting the position of enable irq on other reset paths accordingly.
>
> Signed-off-by: Victor Zhao
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8
> drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c | 1 +
> 2 files changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index c0cfae52f12b..0b658225e9ef 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -4625,8 +4625,6 @@ int amdgpu_device_pre_asic_reset(struct amdgpu_device
> *adev,
> amdgpu_fence_driver_force_completion(ring);
> }
>
> - amdgpu_fence_driver_isr_toggle(adev, false);
> -
> if (job && job->vm)
> drm_sched_increase_karma(&job->base);
>
> @@ -4758,6 +4756,10 @@ int amdgpu_do_asic_reset(struct list_head
> *device_list_handle,
> test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
> skip_hw_reset = test_bit(AMDGPU_SKIP_HW_RESET,
> &reset_context->flags);
>
> + list_for_each_entry (tmp_adev, device_list_handle, reset_list) {
> + amdgpu_fence_driver_isr_toggle(tmp_adev, false);
> + }
> +
> /*
>* ASIC reset has to be done on all XGMI hive nodes ASAP
>* to allow proper links negotiation in FW (within 1 sec) @@
> -5031,8 +5033,6 @@ static void amdgpu_device_recheck_guilty_jobs(
> /* Clear this failed job from fence array */
> amdgpu_fence_driver_clear_job_fences(ring);
>
> - amdgpu_fence_driver_isr_toggle(adev, false);
> -
> /* Since the job won't signal and we go for
>* another resubmit drop this parent pointer
>*/
> diff --git a/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c
> b/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c
> index 7aa570c1ce4a..953036482d1f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c
> @@ -240,6 +240,7 @@ sienna_cichlid_mode2_restore_hwcontext(struct
> amdgpu_reset_control *reset_ctl,
> * Add this ASIC as tracked as reset was already
> * complete successfully.
> */
> + amdgpu_fence_driver_isr_toggle(tmp_adev, false);
> amdgpu_register_gpu_instance(tmp_adev);
>
> /* Resume RAS */
>
Re: [PATCH 1/2] drm/amdgpu: fix deadlock caused by overflow
Am 15.09.22 um 06:02 schrieb Zhao, Victor:
[AMD Official Use Only - General]
Ping.
Hi @Koenig, Christian and @Grodzovsky, Andrey,
We found some reset related issues during stress test on the sequence. Please
help give some comments.
Thanks,
Victor
-Original Message-
From: Victor Zhao
Sent: Wednesday, September 14, 2022 6:10 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deng, Emily ; Grodzovsky, Andrey ;
Zhao, Victor
Subject: [PATCH 1/2] drm/amdgpu: fix deadlock caused by overflow
[background]
For a gpu recovery caused by a hang on one ring (e.g. compute), jobs from
another ring (e.g. gfx) may continue signaling during drm_sched_stop stage. The
signal bit will not be cleared.
At the resubmit stage after recovery, the job with hw fence signaled bit set
will call job done directly instead go through fence process.
This makes the hw_rq_count decrease but rcu fence pointer not cleared yet.
Then overflow happens in the fence driver slots and some jobs may be skipped
and leave the rcu pointer not cleared which makes an infinite wait for the slot
on the next fence emitted.
This infinite wait cause a job timeout on the emitting job. And driver will
stuck at the its sched stop step because kthread_park cannot be done.
[how]
1. move amdgpu_fence_driver_isr_toggle earlier to close interrupt before drm
sched stop 2. handle all fences in fence process to aviod skip when overflow
happens
Signed-off-by: Victor Zhao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 16 +---
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 6 +-
2 files changed, 14 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 943c9e750575..c0cfae52f12b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -4610,8 +4610,6 @@ int amdgpu_device_pre_asic_reset(struct amdgpu_device
*adev,
amdgpu_virt_fini_data_exchange(adev);
}
- amdgpu_fence_driver_isr_toggle(adev, true);
-
/* block all schedulers and reset given job's ring */
for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
struct amdgpu_ring *ring = adev->rings[i]; @@ -5214,6 +5212,8
@@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
amdgpu_device_ip_need_full_reset(tmp_adev))
amdgpu_ras_suspend(tmp_adev);
+ amdgpu_fence_driver_isr_toggle(tmp_adev, true);
+
for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
struct amdgpu_ring *ring = tmp_adev->rings[i];
@@ -5228,8 +5228,12 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
atomic_inc(&tmp_adev->gpu_reset_counter);
}
- if (need_emergency_restart)
+ if (need_emergency_restart) {
+ list_for_each_entry (tmp_adev, device_list_handle, reset_list) {
+ amdgpu_fence_driver_isr_toggle(tmp_adev, false);
+ }
goto skip_sched_resume;
+ }
/*
* Must check guilty signal here since after this point all old @@
-5240,6 +5244,9 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
if (job && dma_fence_is_signaled(&job->hw_fence)) {
job_signaled = true;
dev_info(adev->dev, "Guilty job already signaled, skipping HW
reset");
+ list_for_each_entry (tmp_adev, device_list_handle, reset_list) {
+ amdgpu_fence_driver_isr_toggle(tmp_adev, false);
+ }
goto skip_hw_reset;
}
@@ -5276,6 +5283,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
if (r && r == -EAGAIN) {
set_bit(AMDGPU_SKIP_MODE2_RESET, &reset_context->flags);
adev->asic_reset_res = 0;
+ amdgpu_fence_driver_isr_toggle(adev, true);
goto retry;
}
}
@@ -5711,6 +5719,8 @@ pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev
*pdev)
set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags);
set_bit(AMDGPU_SKIP_MODE2_RESET, &reset_context.flags);
+ amdgpu_fence_driver_isr_toggle(adev, true);
+
adev->no_hw_access = true;
r = amdgpu_device_pre_asic_reset(adev, &reset_context);
adev->no_hw_access = false;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
index 8adeb7469f1e..65a877e1a7fc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
@@ -287,15 +287,11 @@ bool amdgpu_fence_process(struct amdgpu_ring *ring)
if (unlikely(seq == last_seq))
return false;
- last_seq &= drv->num_fences_mask;
- seq &= drv->num_fences_mask;
-
do {
struct dma_fence *fence, **ptr;
++last_seq;
- last_seq &=
Re: [PATCH v5 1/1] drm/amdgpu: Fix amdgpu_vm_pt_free warning
Am 14.09.22 um 19:45 schrieb Felix Kuehling:
Am 2022-09-14 um 12:08 schrieb Philip Yang:
Free page table BO from vm resv unlocked context generate below
warnings.
Add a pt_free_work in vm to free page table BO from vm->pt_freed list.
pass vm resv unlock status from page table update caller, and add vm_bo
entry to vm->pt_freed list and schedule the pt_free_work if calling with
vm resv unlocked.
WARNING: CPU: 12 PID: 3238 at
drivers/gpu/drm/ttm/ttm_bo.c:106 ttm_bo_set_bulk_move+0xa1/0xc0
Call Trace:
amdgpu_vm_pt_free+0x42/0xd0 [amdgpu]
amdgpu_vm_pt_free_dfs+0xb3/0xf0 [amdgpu]
amdgpu_vm_ptes_update+0x52d/0x850 [amdgpu]
amdgpu_vm_update_range+0x2a6/0x640 [amdgpu]
svm_range_unmap_from_gpus+0x110/0x300 [amdgpu]
svm_range_cpu_invalidate_pagetables+0x535/0x600 [amdgpu]
__mmu_notifier_invalidate_range_start+0x1cd/0x230
unmap_vmas+0x9d/0x140
unmap_region+0xa8/0x110
Signed-off-by: Philip Yang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 5 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 6
drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c | 41 +--
3 files changed, 49 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 59cac347baa3..20cfc8c9635b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -2022,6 +2022,9 @@ int amdgpu_vm_init(struct amdgpu_device *adev,
struct amdgpu_vm *vm)
spin_lock_init(&vm->invalidated_lock);
INIT_LIST_HEAD(&vm->freed);
INIT_LIST_HEAD(&vm->done);
+ INIT_LIST_HEAD(&vm->pt_freed);
+ INIT_WORK(&vm->pt_free_work, amdgpu_vm_pt_free_work);
+ spin_lock_init(&vm->pt_free_lock);
/* create scheduler entities for page table updates */
r = drm_sched_entity_init(&vm->immediate,
DRM_SCHED_PRIORITY_NORMAL,
@@ -2223,6 +2226,8 @@ void amdgpu_vm_fini(struct amdgpu_device *adev,
struct amdgpu_vm *vm)
amdgpu_amdkfd_gpuvm_destroy_cb(adev, vm);
+ flush_work(&vm->pt_free_work);
+
root = amdgpu_bo_ref(vm->root.bo);
amdgpu_bo_reserve(root, true);
amdgpu_vm_set_pasid(adev, vm, 0);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 9ecb7f663e19..b77fe838c327 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -276,6 +276,11 @@ struct amdgpu_vm {
/* BOs which are invalidated, has been updated in the PTs */
struct list_head done;
+ /* PT BOs scheduled to free and fill with zero if vm_resv is
not hold */
+ struct list_head pt_freed;
+ struct work_struct pt_free_work;
+ spinlock_t pt_free_lock;
+
/* contains the page directory */
struct amdgpu_vm_bo_base root;
struct dma_fence *last_update;
@@ -471,6 +476,7 @@ int amdgpu_vm_pde_update(struct
amdgpu_vm_update_params *params,
int amdgpu_vm_ptes_update(struct amdgpu_vm_update_params *params,
uint64_t start, uint64_t end,
uint64_t dst, uint64_t flags);
+void amdgpu_vm_pt_free_work(struct work_struct *work);
#if defined(CONFIG_DEBUG_FS)
void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct
seq_file *m);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
index 88de9f0d4728..c16579471f22 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
@@ -641,6 +641,27 @@ static void amdgpu_vm_pt_free(struct
amdgpu_vm_bo_base *entry)
amdgpu_bo_unref(&entry->bo);
}
+void amdgpu_vm_pt_free_work(struct work_struct *work)
+{
+ struct amdgpu_vm_bo_base *entry, *next;
+ struct amdgpu_vm *vm;
+ LIST_HEAD(pt_freed);
+
+ vm = container_of(work, struct amdgpu_vm, pt_free_work);
+
+ spin_lock(&vm->pt_free_lock);
+ list_splice_init(&vm->pt_freed, &pt_freed);
+ spin_unlock(&vm->pt_free_lock);
+
+ // flush_work in amdgpu_vm_fini ensure vm->root.bo is valid
+ amdgpu_bo_reserve(vm->root.bo, true);
+
+ list_for_each_entry_safe(entry, next, &pt_freed, vm_status)
+ amdgpu_vm_pt_free(entry);
+
+ amdgpu_bo_unreserve(vm->root.bo);
+}
+
/**
* amdgpu_vm_pt_free_dfs - free PD/PT levels
*
@@ -652,11 +673,24 @@ static void amdgpu_vm_pt_free(struct
amdgpu_vm_bo_base *entry)
*/
static void amdgpu_vm_pt_free_dfs(struct amdgpu_device *adev,
struct amdgpu_vm *vm,
- struct amdgpu_vm_pt_cursor *start)
+ struct amdgpu_vm_pt_cursor *start,
+ bool unlocked)
{
struct amdgpu_vm_pt_cursor cursor;
struct amdgpu_vm_bo_base *entry;
+ if (unlocked) {
+ spin_lock(&vm->pt_free_lock);
+ for_each_amdgpu_vm_pt_dfs_safe(adev, vm, start, cursor, entry)
+ list_move(&entry->vm_status, &vm->pt_freed);
+
+ if (start)
+ list_move(&start->entry->vm_status, &vm->pt_freed);
+
Re: [PATCH 2/2] drm/amdgpu: move enable irq later to avoid race with ih resume
On 9/14/2022 3:40 PM, Victor Zhao wrote:
[background]
On current sienna cichlid mode2 reset, on the slow job hang cases,
since page table context was reverted to completely stop gpu, it
will generate page fault interrupt.
Since the irq are open during recovery stage, during ih resume step,
if this interrupt was in processing, which increased ih ring rptr,
and ih resume meanwhile will set rptr and wptr to 0. This may cause
AFAIK, only GFX/SDMA are affected by mode-2. IH is not suspended before
mode-2. Why do you resume IH after mode-2 when it is not suspended? Is
it a special case for virtualization?
Thanks,
Lijo
rptr greater than wptr. Such case was not handled in ih process,
and it will cause rptr continue increasing util reaches the max.
Such case will make fence fallback situation happen.
[how]
Move the enable of irq after ih resumed and before ib test.
Adjusting the position of enable irq on other reset paths accordingly.
Signed-off-by: Victor Zhao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8
drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c | 1 +
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index c0cfae52f12b..0b658225e9ef 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -4625,8 +4625,6 @@ int amdgpu_device_pre_asic_reset(struct amdgpu_device
*adev,
amdgpu_fence_driver_force_completion(ring);
}
- amdgpu_fence_driver_isr_toggle(adev, false);
-
if (job && job->vm)
drm_sched_increase_karma(&job->base);
@@ -4758,6 +4756,10 @@ int amdgpu_do_asic_reset(struct list_head *device_list_handle,
test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
skip_hw_reset = test_bit(AMDGPU_SKIP_HW_RESET, &reset_context->flags);
+ list_for_each_entry (tmp_adev, device_list_handle, reset_list) {
+ amdgpu_fence_driver_isr_toggle(tmp_adev, false);
+ }
+
/*
* ASIC reset has to be done on all XGMI hive nodes ASAP
* to allow proper links negotiation in FW (within 1 sec)
@@ -5031,8 +5033,6 @@ static void amdgpu_device_recheck_guilty_jobs(
/* Clear this failed job from fence array */
amdgpu_fence_driver_clear_job_fences(ring);
- amdgpu_fence_driver_isr_toggle(adev, false);
-
/* Since the job won't signal and we go for
* another resubmit drop this parent pointer
*/
diff --git a/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c
b/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c
index 7aa570c1ce4a..953036482d1f 100644
--- a/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c
+++ b/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c
@@ -240,6 +240,7 @@ sienna_cichlid_mode2_restore_hwcontext(struct
amdgpu_reset_control *reset_ctl,
* Add this ASIC as tracked as reset was already
* complete successfully.
*/
+ amdgpu_fence_driver_isr_toggle(tmp_adev, false);
amdgpu_register_gpu_instance(tmp_adev);
/* Resume RAS */
RE: [PATCH 1/4] drm/amdgpu: Introduce gfx software ring(v4)
[AMD Official Use Only - General]
>So, between the function names of "amdgpu_ring_get_rptr_from_mux()" and
>"amdgpu_ring_get_wptr_from_mux()",
>they are 96.6(6)% _the_same_ name to a human. How about
>"amdgpu_ring_get_readp_from_mux()" and "amdgpu_ring_get_writep_from_mux()"?
I agree with the similarity between rptr and wptr. But the function named
amdgpu_ring_get_rptr_from_mux is aligned with amdgpu_ring_get_rptr for the
same style, easier to understand.
I would rather use it currently until we replace rptr with writep in all the
other places, shall we?
Thanks,
Jiadong
-Original Message-
From: Tuikov, Luben
Sent: Thursday, September 15, 2022 12:49 AM
To: Zhu, Jiadong ; amd-gfx@lists.freedesktop.org
Cc: Huang, Ray ; Grodzovsky, Andrey
; Koenig, Christian
Subject: Re: [PATCH 1/4] drm/amdgpu: Introduce gfx software ring(v4)
It's customary to add a Cc: tag in the commit message on subsequent revisions
of a patch, once a person has reviewed and commented on it--Christian, Andrey,
me, so that subsequent patches' emails go out to those people automatically via
a CC.
Inlined:
On 2022-09-13 05:05, jiadong@amd.com wrote:
> From: "Jiadong.Zhu"
>
> The software ring is created to support priority context while there
> is only one hardware queue for gfx.
>
> Every software rings has its fence driver and could
"ring", singular.
> be used as an ordinary ring for the gpu_scheduler.
"GPU scheduler".
> Multiple software rings are binded to a real ring
The past tense of "bind" is "bound", not "binded".
> with the ring muxer. The packages committed on the software ring are
> copied to the real ring.
Use 79 column wrap setting in your editor, not 50 or 60.
Wrap at 79.
>
> v2: use array to store software ring entry.
> v3: remove unnecessary prints.
> v4: remove amdgpu_ring_sw_init/fini functions, using gtt for sw ring
> buffer for later dma copy optimization.
>
> Signed-off-by: Jiadong.Zhu
Add Cc: tags before the Signed-off-by line.
> ---
> drivers/gpu/drm/amd/amdgpu/Makefile | 3 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 3 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 3 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c | 182
> +++ drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.h |
> 67 +++ drivers/gpu/drm/amd/amdgpu/amdgpu_sw_ring.c | 60 ++
> drivers/gpu/drm/amd/amdgpu/amdgpu_sw_ring.h | 43 +
> 7 files changed, 360 insertions(+), 1 deletion(-) create mode 100644
> drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c
> create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.h
> create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_sw_ring.c
> create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_sw_ring.h
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
> b/drivers/gpu/drm/amd/amdgpu/Makefile
> index 3e0e2eb7e235..85224bc81ce5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/Makefile
> +++ b/drivers/gpu/drm/amd/amdgpu/Makefile
> @@ -58,7 +58,8 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
> amdgpu_vm_sdma.o amdgpu_discovery.o amdgpu_ras_eeprom.o amdgpu_nbio.o \
> amdgpu_umc.o smu_v11_0_i2c.o amdgpu_fru_eeprom.o amdgpu_rap.o \
> amdgpu_fw_attestation.o amdgpu_securedisplay.o \
> - amdgpu_eeprom.o amdgpu_mca.o amdgpu_psp_ta.o amdgpu_lsdma.o
> + amdgpu_eeprom.o amdgpu_mca.o amdgpu_psp_ta.o amdgpu_lsdma.o \
> + amdgpu_sw_ring.o amdgpu_ring_mux.o
>
> amdgpu-$(CONFIG_PROC_FS) += amdgpu_fdinfo.o
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> index 53526ffb2ce1..0de8e3cd0f1c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> @@ -33,6 +33,7 @@
> #include "amdgpu_imu.h"
> #include "soc15.h"
> #include "amdgpu_ras.h"
> +#include "amdgpu_ring_mux.h"
>
> /* GFX current status */
> #define AMDGPU_GFX_NORMAL_MODE 0xL
> @@ -346,6 +347,8 @@ struct amdgpu_gfx {
> struct amdgpu_gfx_ras *ras;
>
> boolis_poweron;
> +
> + struct amdgpu_ring_mux muxer;
It doesn't align, possibly because TAB chars were used between "bool" and
"is_poweron", and because TAB chars were used between "struct amdgpu_ring_mux"
and "muxer".
> };
>
> #define amdgpu_gfx_get_gpu_clock_counter(adev)
> (adev)->gfx.funcs->get_gpu_clock_counter((adev))
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> index 7d89a52091c0..fe33a683bfba 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> @@ -278,6 +278,9 @@ struct amdgpu_ring {
> boolis_mes_queue;
> uint32_thw_queue_id;
> struct amdgpu_mes_ctx_data *mes_ctx;
> +
> + boolis_sw_ring;
Use spaces to align "is_sw_ring", not TAB chars, as I mentioned in my review of
v3 of this patch.
> +
> };
>
> #define
RE: [PATCH 1/2] drm/amdgpu: fix deadlock caused by overflow
[AMD Official Use Only - General]
Ping.
Hi @Koenig, Christian and @Grodzovsky, Andrey,
We found some reset related issues during stress test on the sequence. Please
help give some comments.
Thanks,
Victor
-Original Message-
From: Victor Zhao
Sent: Wednesday, September 14, 2022 6:10 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deng, Emily ; Grodzovsky, Andrey
; Zhao, Victor
Subject: [PATCH 1/2] drm/amdgpu: fix deadlock caused by overflow
[background]
For a gpu recovery caused by a hang on one ring (e.g. compute), jobs from
another ring (e.g. gfx) may continue signaling during drm_sched_stop stage. The
signal bit will not be cleared.
At the resubmit stage after recovery, the job with hw fence signaled bit set
will call job done directly instead go through fence process.
This makes the hw_rq_count decrease but rcu fence pointer not cleared yet.
Then overflow happens in the fence driver slots and some jobs may be skipped
and leave the rcu pointer not cleared which makes an infinite wait for the slot
on the next fence emitted.
This infinite wait cause a job timeout on the emitting job. And driver will
stuck at the its sched stop step because kthread_park cannot be done.
[how]
1. move amdgpu_fence_driver_isr_toggle earlier to close interrupt before drm
sched stop 2. handle all fences in fence process to aviod skip when overflow
happens
Signed-off-by: Victor Zhao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 16 +---
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 6 +-
2 files changed, 14 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 943c9e750575..c0cfae52f12b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -4610,8 +4610,6 @@ int amdgpu_device_pre_asic_reset(struct amdgpu_device
*adev,
amdgpu_virt_fini_data_exchange(adev);
}
- amdgpu_fence_driver_isr_toggle(adev, true);
-
/* block all schedulers and reset given job's ring */
for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
struct amdgpu_ring *ring = adev->rings[i]; @@ -5214,6 +5212,8
@@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
amdgpu_device_ip_need_full_reset(tmp_adev))
amdgpu_ras_suspend(tmp_adev);
+ amdgpu_fence_driver_isr_toggle(tmp_adev, true);
+
for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
struct amdgpu_ring *ring = tmp_adev->rings[i];
@@ -5228,8 +5228,12 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
atomic_inc(&tmp_adev->gpu_reset_counter);
}
- if (need_emergency_restart)
+ if (need_emergency_restart) {
+ list_for_each_entry (tmp_adev, device_list_handle, reset_list) {
+ amdgpu_fence_driver_isr_toggle(tmp_adev, false);
+ }
goto skip_sched_resume;
+ }
/*
* Must check guilty signal here since after this point all old @@
-5240,6 +5244,9 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
if (job && dma_fence_is_signaled(&job->hw_fence)) {
job_signaled = true;
dev_info(adev->dev, "Guilty job already signaled, skipping HW
reset");
+ list_for_each_entry (tmp_adev, device_list_handle, reset_list) {
+ amdgpu_fence_driver_isr_toggle(tmp_adev, false);
+ }
goto skip_hw_reset;
}
@@ -5276,6 +5283,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
if (r && r == -EAGAIN) {
set_bit(AMDGPU_SKIP_MODE2_RESET, &reset_context->flags);
adev->asic_reset_res = 0;
+ amdgpu_fence_driver_isr_toggle(adev, true);
goto retry;
}
}
@@ -5711,6 +5719,8 @@ pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev
*pdev)
set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags);
set_bit(AMDGPU_SKIP_MODE2_RESET, &reset_context.flags);
+ amdgpu_fence_driver_isr_toggle(adev, true);
+
adev->no_hw_access = true;
r = amdgpu_device_pre_asic_reset(adev, &reset_context);
adev->no_hw_access = false;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
index 8adeb7469f1e..65a877e1a7fc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
@@ -287,15 +287,11 @@ bool amdgpu_fence_process(struct amdgpu_ring *ring)
if (unlikely(seq == last_seq))
return false;
- last_seq &= drv->num_fences_mask;
- seq &= drv->num_fences_mask;
-
do {
struct dma_fence *fence, **ptr;
++last_seq;
- last_seq &= drv->num_fenc
[PATCH -next 2/6] drm/amd/display: clean up some inconsistent indentings
clean up some inconsistent indentings
Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2178
Reported-by: Abaci Robot
Signed-off-by: Yang Li
---
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
index 10477ca52a41..47159e9a0884 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
@@ -406,14 +406,14 @@ struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct
amdgpu_device *adev)
if (adev->reset_domain->type != XGMI_HIVE) {
hive->reset_domain =
amdgpu_reset_create_reset_domain(XGMI_HIVE,
"amdgpu-reset-hive");
- if (!hive->reset_domain) {
- dev_err(adev->dev, "XGMI: failed
initializing reset domain for xgmi hive\n");
- ret = -ENOMEM;
- kobject_put(&hive->kobj);
- kfree(hive);
- hive = NULL;
- goto pro_end;
- }
+ if (!hive->reset_domain) {
+ dev_err(adev->dev, "XGMI: failed initializing
reset domain for xgmi hive\n");
+ ret = -ENOMEM;
+ kobject_put(&hive->kobj);
+ kfree(hive);
+ hive = NULL;
+ goto pro_end;
+ }
} else {
amdgpu_reset_get_reset_domain(adev->reset_domain);
hive->reset_domain = adev->reset_domain;
--
2.20.1.7.g153144c
[PATCH -next 5/6] drm/amd/display: clean up some inconsistent indentings
clean up some inconsistent indentings Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2181 Reported-by: Abaci Robot Signed-off-by: Yang Li --- .../gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c| 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c index 2829f179f982..f6ffcf1596bc 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c @@ -1362,7 +1362,7 @@ static bool CalculatePrefetchSchedule( // - ((NumberOfCursors > 0 || GPUVMEnable || DCCEnable) ? - ((GPUVMEnable || myPipe->DCCEnable) ? (*DestinationLinesToRequestVMInVBlank + 2 * *DestinationLinesToRequestRowInVBlank) : 0.0); // TODO: Did someone else add this?? #else - LinesToRequestPrefetchPixelData = *DestinationLinesForPrefetch - *DestinationLinesToRequestVMInVBlank - 2 * *DestinationLinesToRequestRowInVBlank; + LinesToRequestPrefetchPixelData = *DestinationLinesForPrefetch - *DestinationLinesToRequestVMInVBlank - 2 * *DestinationLinesToRequestRowInVBlank; #endif #ifdef __DML_VBA_DEBUG__ -- 2.20.1.7.g153144c
[PATCH -next 3/6] drm/amd/display: clean up some inconsistent indentings
clean up some inconsistent indentings Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2179 Reported-by: Abaci Robot Signed-off-by: Yang Li --- drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c index 11f1435b8c07..2aa79b832e25 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c @@ -919,10 +919,10 @@ static struct hubp *dcn32_hubp_create( #undef REG_STRUCT #define REG_STRUCT hubp_regs - hubp_regs_init(0), - hubp_regs_init(1), - hubp_regs_init(2), - hubp_regs_init(3); + hubp_regs_init(0), + hubp_regs_init(1), + hubp_regs_init(2), + hubp_regs_init(3); if (hubp32_construct(hubp2, ctx, inst, &hubp_regs[inst], &hubp_shift, &hubp_mask)) -- 2.20.1.7.g153144c
[PATCH -next 4/6] drm/amd/display: clean up some inconsistent indentings
clean up some inconsistent indentings Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2180 Reported-by: Abaci Robot Signed-off-by: Yang Li --- .../amd/display/dc/dcn321/dcn321_resource.c | 26 +-- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c index 1bbc0bdf5dc3..355b4b1d6628 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c @@ -820,11 +820,11 @@ static struct dce_i2c_hw *dcn321_i2c_hw_create( #undef REG_STRUCT #define REG_STRUCT i2c_hw_regs - i2c_inst_regs_init(1), - i2c_inst_regs_init(2), - i2c_inst_regs_init(3), - i2c_inst_regs_init(4), - i2c_inst_regs_init(5); + i2c_inst_regs_init(1), + i2c_inst_regs_init(2), + i2c_inst_regs_init(3), + i2c_inst_regs_init(4), + i2c_inst_regs_init(5); dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); @@ -922,10 +922,10 @@ static struct hubp *dcn321_hubp_create( #undef REG_STRUCT #define REG_STRUCT hubp_regs - hubp_regs_init(0), - hubp_regs_init(1), - hubp_regs_init(2), - hubp_regs_init(3); + hubp_regs_init(0), + hubp_regs_init(1), + hubp_regs_init(2), + hubp_regs_init(3); if (hubp32_construct(hubp2, ctx, inst, &hubp_regs[inst], &hubp_shift, &hubp_mask)) @@ -1670,10 +1670,10 @@ static bool dcn321_resource_construct( #undef REG_STRUCT #define REG_STRUCT abm_regs - abm_regs_init(0), - abm_regs_init(1), - abm_regs_init(2), - abm_regs_init(3); + abm_regs_init(0), + abm_regs_init(1), + abm_regs_init(2), + abm_regs_init(3); #undef REG_STRUCT #define REG_STRUCT dccg_regs -- 2.20.1.7.g153144c
[PATCH -next 6/6] drm/amd/display: clean up some inconsistent indentings
clean up some inconsistent indentings Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2182 Reported-by: Abaci Robot Signed-off-by: Yang Li --- drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c index d40d32e380f4..1d84ae50311d 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c @@ -2636,7 +2636,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman &mode_lib->vba.SrcActiveDrainRate, &mode_lib->vba.TInitXFill, &mode_lib->vba.TslvChk); - locals->XFCRemoteSurfaceFlipLatency[k] = + locals->XFCRemoteSurfaceFlipLatency[k] = dml_floor( mode_lib->vba.XFCRemoteSurfaceFlipDelay / (mode_lib->vba.HTotal[k] -- 2.20.1.7.g153144c
[PATCH -next 1/6] drm/amd/display: clean up some inconsistent indentings
clean up some inconsistent indentings Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2177 Reported-by: Abaci Robot Signed-off-by: Yang Li --- .../gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c| 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c index 4e3356d12147..8dfe639b6508 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c @@ -1051,10 +1051,10 @@ static bool CalculatePrefetchSchedule( bytes_pp = myPipe->BytePerPixelY + myPipe->BytePerPixelC; /*rev 99*/ prefetch_bw_pr = dml_min(1, bytes_pp * myPipe->PixelClock / (double) myPipe->DPPPerPlane); -max_Tsw = dml_max(PrefetchSourceLinesY, PrefetchSourceLinesC) * LineTime; + max_Tsw = dml_max(PrefetchSourceLinesY, PrefetchSourceLinesC) * LineTime; prefetch_sw_bytes = PrefetchSourceLinesY * swath_width_luma_ub * myPipe->BytePerPixelY + PrefetchSourceLinesC * swath_width_chroma_ub * myPipe->BytePerPixelC; prefetch_bw_oto = dml_max(bytes_pp * myPipe->PixelClock / myPipe->DPPPerPlane, prefetch_sw_bytes / (dml_max(PrefetchSourceLinesY, PrefetchSourceLinesC) * LineTime)); -prefetch_bw_oto = dml_max(prefetch_bw_pr, prefetch_sw_bytes / max_Tsw); + prefetch_bw_oto = dml_max(prefetch_bw_pr, prefetch_sw_bytes / max_Tsw); min_Lsw = dml_max(1, dml_max(PrefetchSourceLinesY, PrefetchSourceLinesC) / max_vratio_pre); Lsw_oto = dml_ceil(4 * dml_max(prefetch_sw_bytes / prefetch_bw_oto / LineTime, min_Lsw), 1) / 4; -- 2.20.1.7.g153144c
Re: [PATCH v3 7/8] drm/amd/display: Introduce KUnit tests to dc_dmub_srv library
Hi Maíra,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm/drm-next]
[also build test ERROR on drm-intel/for-linux-next drm-tip/drm-tip linus/master
v6.0-rc5 next-20220914]
[cannot apply to drm-misc/drm-misc-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url:
https://github.com/intel-lab-lkp/linux/commits/Ma-ra-Canal/drm-amd-display-Introduce-KUnit-to-Display-Mode-Library/20220913-000256
base: git://anongit.freedesktop.org/drm/drm drm-next
config: loongarch-randconfig-r026-20220914
(https://download.01.org/0day-ci/archive/20220915/202209150834.m0besply-...@intel.com/config)
compiler: loongarch64-linux-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
#
https://github.com/intel-lab-lkp/linux/commit/50e2391775a6552a521c783a6fcd36942b906e3f
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review
Ma-ra-Canal/drm-amd-display-Introduce-KUnit-to-Display-Mode-Library/20220913-000256
git checkout 50e2391775a6552a521c783a6fcd36942b906e3f
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1
O=build_dir ARCH=loongarch SHELL=/bin/bash
If you fix the issue, kindly add following tag where applicable
Reported-by: kernel test robot
All errors (new ones prefixed by >>):
In file included from
drivers/gpu/drm/amd/amdgpu/../display/dc/dc_dmub_srv.c:863:
drivers/gpu/drm/amd/amdgpu/../display/dc/../tests/dc/dc_dmub_srv_test.c: In
function 'populate_subvp_cmd_drr_info_test':
>> drivers/gpu/drm/amd/amdgpu/../display/dc/../tests/dc/dc_dmub_srv_test.c:260:9:
>> error: implicit declaration of function 'populate_subvp_cmd_drr_info'; did
>> you mean 'populate_subvp_cmd_drr_info_test'?
>> [-Werror=implicit-function-declaration]
260 | populate_subvp_cmd_drr_info(test_param->dc,
test_param->subvp_pipe,
| ^~~
| populate_subvp_cmd_drr_info_test
In file included from
drivers/gpu/drm/amd/amdgpu/../display/dc/inc/core_types.h:32,
from
drivers/gpu/drm/amd/amdgpu/../display/dc/dc_dmub_srv.c:31:
drivers/gpu/drm/amd/amdgpu/../display/include/ddc_service_types.h: At top
level:
drivers/gpu/drm/amd/amdgpu/../display/include/ddc_service_types.h:137:22:
warning: 'SYNAPTICS_DEVICE_ID' defined but not used [-Wunused-const-variable=]
137 | static const uint8_t SYNAPTICS_DEVICE_ID[] = "SYNA";
| ^~~
drivers/gpu/drm/amd/amdgpu/../display/include/ddc_service_types.h:134:17:
warning: 'DP_SINK_BRANCH_DEV_NAME_7580' defined but not used
[-Wunused-const-variable=]
134 | static const u8 DP_SINK_BRANCH_DEV_NAME_7580[] = "7580\x80u";
| ^~~~
drivers/gpu/drm/amd/amdgpu/../display/include/ddc_service_types.h:132:22:
warning: 'DP_SINK_DEVICE_STR_ID_2' defined but not used
[-Wunused-const-variable=]
132 | static const uint8_t DP_SINK_DEVICE_STR_ID_2[] = {7, 1, 8, 7, 5, 0};
| ^~~
drivers/gpu/drm/amd/amdgpu/../display/include/ddc_service_types.h:131:22:
warning: 'DP_SINK_DEVICE_STR_ID_1' defined but not used
[-Wunused-const-variable=]
131 | static const uint8_t DP_SINK_DEVICE_STR_ID_1[] = {7, 1, 8, 7, 3, 0};
| ^~~
cc1: some warnings being treated as errors
vim +260 drivers/gpu/drm/amd/amdgpu/../display/dc/../tests/dc/dc_dmub_srv_test.c
246
247 KUNIT_ARRAY_PARAM(populate_subvp_cmd_drr_info,
populate_subvp_cmd_drr_info_cases,
248populate_subvp_cmd_drr_info_test_to_desc);
249
250 static void populate_subvp_cmd_drr_info_test(struct kunit *test)
251 {
252 const struct populate_subvp_cmd_drr_info_test_case *test_param =
253 test->param_value;
254 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data;
255
256 pipe_data = kunit_kzalloc(test,
257sizeof(struct
dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2),
258GFP_KERNEL);
259
> 260 populate_subvp_cmd_drr_info(test_param->dc,
> test_param->subvp_pipe,
261 test_param->vblank_pipe, pipe_data);
262
263 KUNIT_EXPECT_EQ(test,
Re: [PATCH V3 46/47] drm/amd/display: Fix failures of disabling primary plans
On 2022-09-14 10:55, Michel Dänzer wrote:
[ Adding the dri-devel list ]
On 2022-09-14 18:30, Alex Hung wrote:
On 2022-09-14 07:40, Michel Dänzer wrote:
On 2022-09-14 15:31, Michel Dänzer wrote:
On 2022-09-14 07:10, Wayne Lin wrote:
From: Alex Hung
[Why & How]
This fixes kernel errors when IGT disables primary planes during the
tests kms_universal_plane::functional_test_pipe/pageflip_test_pipe.
NAK.
This essentially reverts commit b836a274b797 ("drm/amdgpu/dc: Require primary plane
to be enabled whenever the CRTC is") (except that it goes even further and
completely removes the requirement for any HW plane to be enabled when the HW cursor is),
so it would reintroduce the issues described in that commit log.
Actually not exactly the same issues, due to going even further than reverting
my fix.
Instead, the driver will claim that an atomic commit which enables the CRTC and
the cursor plane, while leaving all other KMS planes disabled, succeeds. But
the HW cursor will not actually be visible.
I did not observe problems with cursors (GNOME 42.4 - desktop and youtube/mpv
video playback: windowed/fullscreen). Are there steps to reproduce cursor
problems?
As described in my last follow-up e-mail: An atomic KMS commit which enables
the CRTC and the cursor plane, but disables all other KMS planes for the CRTC.
The commit will succeed, but will not result in the HW cursor being actually
visible. (I don't know of any specific application or test which exercises this)
Did you mean cursor plane depends on primary plane (i.e. no primary
plane = no visible HW cursor)? If there is no primary plane, what
scenario would it be required to draw a cursor?
If this is a rare case, would it still be a concern?
Also see the commit log of bc92c06525e5 ("drm/amd/display: Allow commits with no
planes active").
Does it mean dm_crtc_helper_atomic_check does not need to return -EINVAL
if there is no active cursor because there are no cursors to be shown
anyways, as shown in the below diff:
+static bool does_crtc_have_active_cursor(struct drm_crtc_state
*new_crtc_state)
+{
+ struct drm_device *dev = new_crtc_state->crtc->dev;
+ struct drm_plane *plane;
+
+ drm_for_each_plane_mask(plane, dev, new_crtc_state->plane_mask) {
+ if (plane->type == DRM_PLANE_TYPE_CURSOR)
+ return true;
+ }
+
+ return false;
+}
+
static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
struct drm_atomic_state *state)
{
@@ -383,7 +396,8 @@ static int dm_crtc_helper_atomic_check(struct
drm_crtc *crtc,
* userspace which stops using the HW cursor altogether in
response to the resulting EINVAL.
*/
if (crtc_state->enable &&
- !(crtc_state->plane_mask & drm_plane_mask(crtc->primary))) {
+ !(crtc_state->plane_mask & drm_plane_mask(crtc->primary)) &&
+ does_crtc_have_active_cursor(crtc_state)) {
Note: This would fix kms_universal_plane but not kms_cursor_legacy.
If IGT tests disable the primary plane while leaving the CRTC enabled, those
tests are broken and need to be fixed instead.
There are IGT cursor tests fixed by this:
igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions
igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size
It also reduces amdgpu workaround in IGT's kms_concurrent:
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwork.freedesktop.org%2Fpatch%2F499382%2F%3Fseries%3D107734%26rev%3D1&data=05%7C01%7Calex.hung%40amd.com%7Cc757c9e4fbda4f8474a308da9671f920%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637987713521806985%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=XRRvilVZMBALIWHAOLArxjiAcgqQ%2FwNRnuUUJCTOYzY%3D&reserved=0
The change affect multiple IGT tests. Adding amdgpu-specific workarounds to
each of the IGT tests is not an ideal solution.
It's not amdgpu specific, other atomic KMS drivers have the same restriction. IGT tests
need to be able to handle this. See e.g. 88e379cef970 ("kms_cursor_legacy: Keep
primary plane enabled for XRGB overlay fallback").
Commit 88e379cef970 adds the following change to keep primary plane enabled:
+ igt_plane_set_fb(primary, prim_fb)
but kms_universal_plane fails at testing disabling primary plane, ex.
tests/kms_universal_plane.c:
192 /* Step 5: Universal API's, disable primary plane (CRC 5) */
193 igt_plane_set_fb(primary, NULL);
194 igt_display_commit2(display, COMMIT_UNIVERSAL);
195 igt_pipe_crc_collect_crc(test.pipe_crc, &test.crc_5);
...
230 /* Step 11: Disable primary plane */
231 igt_plane_set_fb(primary, NULL);
232 igt_display_commit2(display, COMMIT_UNIVERSAL);
and so on.
P.S. Per above, this patch should never have made it this far without getting
in touch with me direct
[pull] amdgpu drm-fixes-6.0
Hi Dave, Daniel, Fixes for 6.0. A bit bigger than usual, but this is mainly caused by some regression fixes which took a while to sort out and validate. The rest is fixes for new IPs added in the 6.0 cycle. The following changes since commit 2edb79a5fb303dff577d6a0c7d571c3bab1d1455: Merge tag 'drm-intel-fixes-2022-09-08' of git://anongit.freedesktop.org/drm/drm-intel into drm-fixes (2022-09-10 01:42:47 +1000) are available in the Git repository at: https://gitlab.freedesktop.org/agd5f/linux.git tags/amd-drm-fixes-6.0-2022-09-14 for you to fetch changes up to a8671493d2074950553da3cf07d1be43185ef6c6: drm/amdgpu: make sure to init common IP before gmc (2022-09-14 14:21:49 -0400) amd-drm-fixes-6.0-2022-09-14: amdgpu: - BACO fixes for some RDNA2 boards - PCI AER fixes uncovered by a core PCI change - Properly hook up dirtyfb helper - RAS fixes for GC 11.x - TMR fix - DCN 3.2.x fixes - DCN 3.1.4 fixes - LLVM DML stack size fixes Alex Deucher (4): drm/amdgpu: add HDP remap functionality to nbio 7.7 drm/amdgpu: move nbio ih_doorbell_range() into ih code for vega drm/amdgpu: move nbio sdma_doorbell_range() into sdma code for vega drm/amdgpu: make sure to init common IP before gmc Alvin Lee (3): drm/amd/display: Update MBLK calculation for SubVP drm/amd/display: SW cursor fallback for SubVP drm/amd/display: Refactor SubVP calculation to remove FPU Aric Cyr (1): drm/amd/display: Fix divide by zero in DML Aurabindo Pillai (2): drm/amd/display: Revert "Fallback to SW cursor if SubVP + cursor too big" drm/amd/display: add workaround for subvp cursor corruption for DCN32/321 Candice Li (2): drm/amdgpu: Enable full reset when RAS is supported on gc v11_0_0 drm/amdgpu: Skip reset error status for psp v13_0_0 Duncan Ma (1): drm/amd/display: Correct dram channel width for dcn314 Guchun Chen (1): drm/amd/pm: disable BACO entry/exit completely on several sienna cichlid cards Hamza Mahfooz (1): drm/amdgpu: use dirty framebuffer helper Leo Chen (1): drm/amd/display: Fixing DIG FIFO Error Lijo Lazar (1): drm/amdgpu: Don't enable LTR if not supported Nathan Chancellor (5): drm/amd/display: Reduce number of arguments of dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport() drm/amd/display: Reduce number of arguments of dml32_CalculatePrefetchSchedule() drm/amd/display: Reduce number of arguments of dml31's CalculateWatermarksAndDRAMSpeedChangeSupport() drm/amd/display: Reduce number of arguments of dml31's CalculateFlipSchedule() drm/amd/display: Mark dml30's UseMinimumDCFCLK() as noinline for stack usage Nicholas Kazlauskas (2): drm/amd/display: Hook up DCN314 specific dml implementation drm/amd/display: Relax swizzle checks for video non-RGB formats on DCN314 Rodrigo Siqueira (2): drm/amd/display: Fix compilation errors on DCN314 drm/amd/display: Enable dlg and vba compilation for dcn314 Taimur Hassan (1): drm/amd/display: Round cursor width up for MALL allocation Yang Wang (1): drm/amdgpu: change the alignment size of TMR BO to 1M Yao Wang1 (1): drm/amd/display: Limit user regamma to a valid value drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 14 +- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c| 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c| 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h| 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c| 3 +- drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c | 9 +- drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c | 9 +- drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 9 +- drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c | 9 + drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 5 + drivers/gpu/drm/amd/amdgpu/soc15.c | 25 -- drivers/gpu/drm/amd/amdgpu/soc21.c | 1 + drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 4 + drivers/gpu/drm/amd/amdgpu/vega20_ih.c | 4 + .../amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c | 2 + drivers/gpu/drm/amd/display/dc/core/dc_stream.c| 2 +- drivers/gpu/drm/amd/display/dc/dc.h| 1 + drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 89 +++-- .../display/dc/dcn314/dcn314_dio_stream_encoder.c | 3 +- drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubp.c | 24 +- drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c | 24 +- .../gpu/drm/amd/display/dc/dcn32/dcn32_resource.c | 4 +- .../gpu/drm/amd/display/dc/dcn32/dcn32_resource.h | 3 + .../amd/display/dc/dcn32/dcn32_resource_helpers.c | 59 ++- .../drm/amd/display/dc/dcn321/dcn321_resource.c| 4 +- drivers/gpu/drm/amd/display/dc/dml/Makefile| 3 + .../amd/display/dc/dml/dcn30/displa
Re: [PATCH v5 1/1] drm/amdgpu: Fix amdgpu_vm_pt_free warning
Am 2022-09-14 um 12:08 schrieb Philip Yang:
Free page table BO from vm resv unlocked context generate below
warnings.
Add a pt_free_work in vm to free page table BO from vm->pt_freed list.
pass vm resv unlock status from page table update caller, and add vm_bo
entry to vm->pt_freed list and schedule the pt_free_work if calling with
vm resv unlocked.
WARNING: CPU: 12 PID: 3238 at
drivers/gpu/drm/ttm/ttm_bo.c:106 ttm_bo_set_bulk_move+0xa1/0xc0
Call Trace:
amdgpu_vm_pt_free+0x42/0xd0 [amdgpu]
amdgpu_vm_pt_free_dfs+0xb3/0xf0 [amdgpu]
amdgpu_vm_ptes_update+0x52d/0x850 [amdgpu]
amdgpu_vm_update_range+0x2a6/0x640 [amdgpu]
svm_range_unmap_from_gpus+0x110/0x300 [amdgpu]
svm_range_cpu_invalidate_pagetables+0x535/0x600 [amdgpu]
__mmu_notifier_invalidate_range_start+0x1cd/0x230
unmap_vmas+0x9d/0x140
unmap_region+0xa8/0x110
Signed-off-by: Philip Yang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c| 5 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h| 6
drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c | 41 +--
3 files changed, 49 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 59cac347baa3..20cfc8c9635b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -2022,6 +2022,9 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct
amdgpu_vm *vm)
spin_lock_init(&vm->invalidated_lock);
INIT_LIST_HEAD(&vm->freed);
INIT_LIST_HEAD(&vm->done);
+ INIT_LIST_HEAD(&vm->pt_freed);
+ INIT_WORK(&vm->pt_free_work, amdgpu_vm_pt_free_work);
+ spin_lock_init(&vm->pt_free_lock);
/* create scheduler entities for page table updates */
r = drm_sched_entity_init(&vm->immediate, DRM_SCHED_PRIORITY_NORMAL,
@@ -2223,6 +2226,8 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct
amdgpu_vm *vm)
amdgpu_amdkfd_gpuvm_destroy_cb(adev, vm);
+ flush_work(&vm->pt_free_work);
+
root = amdgpu_bo_ref(vm->root.bo);
amdgpu_bo_reserve(root, true);
amdgpu_vm_set_pasid(adev, vm, 0);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 9ecb7f663e19..b77fe838c327 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -276,6 +276,11 @@ struct amdgpu_vm {
/* BOs which are invalidated, has been updated in the PTs */
struct list_headdone;
+ /* PT BOs scheduled to free and fill with zero if vm_resv is not hold */
+ struct list_headpt_freed;
+ struct work_struct pt_free_work;
+ spinlock_t pt_free_lock;
+
/* contains the page directory */
struct amdgpu_vm_bo_base root;
struct dma_fence*last_update;
@@ -471,6 +476,7 @@ int amdgpu_vm_pde_update(struct amdgpu_vm_update_params
*params,
int amdgpu_vm_ptes_update(struct amdgpu_vm_update_params *params,
uint64_t start, uint64_t end,
uint64_t dst, uint64_t flags);
+void amdgpu_vm_pt_free_work(struct work_struct *work);
#if defined(CONFIG_DEBUG_FS)
void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
index 88de9f0d4728..c16579471f22 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
@@ -641,6 +641,27 @@ static void amdgpu_vm_pt_free(struct amdgpu_vm_bo_base
*entry)
amdgpu_bo_unref(&entry->bo);
}
+void amdgpu_vm_pt_free_work(struct work_struct *work)
+{
+ struct amdgpu_vm_bo_base *entry, *next;
+ struct amdgpu_vm *vm;
+ LIST_HEAD(pt_freed);
+
+ vm = container_of(work, struct amdgpu_vm, pt_free_work);
+
+ spin_lock(&vm->pt_free_lock);
+ list_splice_init(&vm->pt_freed, &pt_freed);
+ spin_unlock(&vm->pt_free_lock);
+
+ // flush_work in amdgpu_vm_fini ensure vm->root.bo is valid
+ amdgpu_bo_reserve(vm->root.bo, true);
+
+ list_for_each_entry_safe(entry, next, &pt_freed, vm_status)
+ amdgpu_vm_pt_free(entry);
+
+ amdgpu_bo_unreserve(vm->root.bo);
+}
+
/**
* amdgpu_vm_pt_free_dfs - free PD/PT levels
*
@@ -652,11 +673,24 @@ static void amdgpu_vm_pt_free(struct amdgpu_vm_bo_base
*entry)
*/
static void amdgpu_vm_pt_free_dfs(struct amdgpu_device *adev,
struct amdgpu_vm *vm,
- struct amdgpu_vm_pt_cursor *start)
+ struct amdgpu_vm_pt_cursor *start,
+ bool unlocked)
{
struct amdgpu_vm_pt_cursor cursor;
struct amdgpu_vm_bo_base *entry;
+ if (unlocked) {
+ spin_lock(&vm->pt_free_lock);
+ for_each_amdgpu_vm_pt_dfs_safe(adev, vm, start, cursor, entry)
+
[PATCH][next] drm/amdkfd: Fix spelling mistake "detroyed" -> "destroyed"
There is a spelling mistake in a pr_debug message. Fix it.
Signed-off-by: Colin Ian King
---
drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
index 7522bf2d2f57..c70c026c9a93 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
@@ -898,7 +898,7 @@ static vm_fault_t svm_migrate_to_ram(struct vm_fault *vmf)
return VM_FAULT_SIGBUS;
}
if (!mmget_not_zero(svm_bo->eviction_fence->mm)) {
- pr_debug("addr 0x%lx of process mm is detroyed\n", addr);
+ pr_debug("addr 0x%lx of process mm is destroyed\n", addr);
return VM_FAULT_SIGBUS;
}
--
2.37.1
Re: [GIT PULL] Immutable backlight-detect-refactor branch between acpi, drm-* and pdx86
Hi, On 9/14/22 12:29, Maxime Ripard wrote: > Hi Hans, > > On Mon, Sep 05, 2022 at 10:35:47AM +0200, Hans de Goede wrote: >> Hi All, >> >> Now that all patches have been reviewed/acked here is an immutable >> backlight-detect-refactor >> branch with 6.0-rc1 + the v5 patch-set, for merging into the relevant (acpi, >> drm-* and pdx86) >> subsystems. >> >> Please pull this branch into the relevant subsystems. >> >> I will merge this into the review-hans branch of the pdx86 git tree today and >> from there it will move to for-next once the builders have successfully >> build-tested >> the merge. > > I merged it into drm-misc-next, thanks! Great, thank you! Regards, Hans
Re: [PATCH 1/4] drm/amdgpu: Introduce gfx software ring(v4)
It's customary to add a Cc: tag in the commit message on subsequent revisions
of a patch, once a person has reviewed and commented on it--Christian, Andrey,
me,
so that subsequent patches' emails go out to those people automatically via a
CC.
Inlined:
On 2022-09-13 05:05, jiadong@amd.com wrote:
> From: "Jiadong.Zhu"
>
> The software ring is created to support priority
> context while there is only one hardware queue
> for gfx.
>
> Every software rings has its fence driver and could
"ring", singular.
> be used as an ordinary ring for the gpu_scheduler.
"GPU scheduler".
> Multiple software rings are binded to a real ring
The past tense of "bind" is "bound", not "binded".
> with the ring muxer. The packages committed on the
> software ring are copied to the real ring.
Use 79 column wrap setting in your editor, not 50 or 60.
Wrap at 79.
>
> v2: use array to store software ring entry.
> v3: remove unnecessary prints.
> v4: remove amdgpu_ring_sw_init/fini functions,
> using gtt for sw ring buffer for later dma copy
> optimization.
>
> Signed-off-by: Jiadong.Zhu
Add Cc: tags before the Signed-off-by line.
> ---
> drivers/gpu/drm/amd/amdgpu/Makefile | 3 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 3 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 3 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c | 182 +++
> drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.h | 67 +++
> drivers/gpu/drm/amd/amdgpu/amdgpu_sw_ring.c | 60 ++
> drivers/gpu/drm/amd/amdgpu/amdgpu_sw_ring.h | 43 +
> 7 files changed, 360 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c
> create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.h
> create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_sw_ring.c
> create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_sw_ring.h
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
> b/drivers/gpu/drm/amd/amdgpu/Makefile
> index 3e0e2eb7e235..85224bc81ce5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/Makefile
> +++ b/drivers/gpu/drm/amd/amdgpu/Makefile
> @@ -58,7 +58,8 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
> amdgpu_vm_sdma.o amdgpu_discovery.o amdgpu_ras_eeprom.o amdgpu_nbio.o \
> amdgpu_umc.o smu_v11_0_i2c.o amdgpu_fru_eeprom.o amdgpu_rap.o \
> amdgpu_fw_attestation.o amdgpu_securedisplay.o \
> - amdgpu_eeprom.o amdgpu_mca.o amdgpu_psp_ta.o amdgpu_lsdma.o
> + amdgpu_eeprom.o amdgpu_mca.o amdgpu_psp_ta.o amdgpu_lsdma.o \
> + amdgpu_sw_ring.o amdgpu_ring_mux.o
>
> amdgpu-$(CONFIG_PROC_FS) += amdgpu_fdinfo.o
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> index 53526ffb2ce1..0de8e3cd0f1c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> @@ -33,6 +33,7 @@
> #include "amdgpu_imu.h"
> #include "soc15.h"
> #include "amdgpu_ras.h"
> +#include "amdgpu_ring_mux.h"
>
> /* GFX current status */
> #define AMDGPU_GFX_NORMAL_MODE 0xL
> @@ -346,6 +347,8 @@ struct amdgpu_gfx {
> struct amdgpu_gfx_ras *ras;
>
> boolis_poweron;
> +
> + struct amdgpu_ring_mux muxer;
It doesn't align, possibly because TAB chars were used between "bool" and
"is_poweron",
and because TAB chars were used between "struct amdgpu_ring_mux" and "muxer".
> };
>
> #define amdgpu_gfx_get_gpu_clock_counter(adev)
> (adev)->gfx.funcs->get_gpu_clock_counter((adev))
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> index 7d89a52091c0..fe33a683bfba 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> @@ -278,6 +278,9 @@ struct amdgpu_ring {
> boolis_mes_queue;
> uint32_thw_queue_id;
> struct amdgpu_mes_ctx_data *mes_ctx;
> +
> + boolis_sw_ring;
Use spaces to align "is_sw_ring", not TAB chars, as I mentioned in my review of
v3 of this patch.
> +
> };
>
> #define amdgpu_ring_parse_cs(r, p, job, ib) ((r)->funcs->parse_cs((p),
> (job), (ib)))
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c
> new file mode 100644
> index ..652a6d3e0ec3
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c
> @@ -0,0 +1,182 @@
> +/*
> + * Copyright 2022 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so,
Re: [PATCH V3 46/47] drm/amd/display: Fix failures of disabling primary plans
On 2022-09-14 07:40, Michel Dänzer wrote:
On 2022-09-14 15:31, Michel Dänzer wrote:
On 2022-09-14 07:10, Wayne Lin wrote:
From: Alex Hung
[Why & How]
This fixes kernel errors when IGT disables primary planes during the
tests kms_universal_plane::functional_test_pipe/pageflip_test_pipe.
NAK.
This essentially reverts commit b836a274b797 ("drm/amdgpu/dc: Require primary plane
to be enabled whenever the CRTC is") (except that it goes even further and
completely removes the requirement for any HW plane to be enabled when the HW cursor is),
so it would reintroduce the issues described in that commit log.
Actually not exactly the same issues, due to going even further than reverting
my fix.
Instead, the driver will claim that an atomic commit which enables the CRTC and
the cursor plane, while leaving all other KMS planes disabled, succeeds. But
the HW cursor will not actually be visible.
I did not observe problems with cursors (GNOME 42.4 - desktop and
youtube/mpv video playback: windowed/fullscreen). Are there steps to
reproduce cursor problems?
If IGT tests disable the primary plane while leaving the CRTC enabled, those
tests are broken and need to be fixed instead.
There are IGT cursor tests fixed by this:
igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions
igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size
It also reduces amdgpu workaround in IGT's kms_concurrent:
https://patchwork.freedesktop.org/patch/499382/?series=107734&rev=1
The change affect multiple IGT tests. Adding amdgpu-specific workarounds
to each of the IGT tests is not an ideal solution. If the cursor
problems can be reproduced, a more specific solution can be developed.
P.S. Per above, this patch should never have made it this far without getting
in touch with me directly.
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
index c89594f3a5cb..099a226407a3 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
@@ -376,18 +376,6 @@ static int dm_crtc_helper_atomic_check(struct drm_crtc
*crtc,
return ret;
}
- /*
-* We require the primary plane to be enabled whenever the CRTC is,
otherwise
-* drm_mode_cursor_universal may end up trying to enable the cursor
plane while all other
-* planes are disabled, which is not supported by the hardware. And
there is legacy
-* userspace which stops using the HW cursor altogether in response to
the resulting EINVAL.
-*/
- if (crtc_state->enable &&
- !(crtc_state->plane_mask & drm_plane_mask(crtc->primary))) {
- DRM_DEBUG_ATOMIC("Can't enable a CRTC without enabling the primary
plane\n");
- return -EINVAL;
- }
-
/* In some use cases, like reset, no stream is attached */
if (!dm_crtc_state->stream)
return 0;
[PATCH v5 1/1] drm/amdgpu: Fix amdgpu_vm_pt_free warning
Free page table BO from vm resv unlocked context generate below
warnings.
Add a pt_free_work in vm to free page table BO from vm->pt_freed list.
pass vm resv unlock status from page table update caller, and add vm_bo
entry to vm->pt_freed list and schedule the pt_free_work if calling with
vm resv unlocked.
WARNING: CPU: 12 PID: 3238 at
drivers/gpu/drm/ttm/ttm_bo.c:106 ttm_bo_set_bulk_move+0xa1/0xc0
Call Trace:
amdgpu_vm_pt_free+0x42/0xd0 [amdgpu]
amdgpu_vm_pt_free_dfs+0xb3/0xf0 [amdgpu]
amdgpu_vm_ptes_update+0x52d/0x850 [amdgpu]
amdgpu_vm_update_range+0x2a6/0x640 [amdgpu]
svm_range_unmap_from_gpus+0x110/0x300 [amdgpu]
svm_range_cpu_invalidate_pagetables+0x535/0x600 [amdgpu]
__mmu_notifier_invalidate_range_start+0x1cd/0x230
unmap_vmas+0x9d/0x140
unmap_region+0xa8/0x110
Signed-off-by: Philip Yang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c| 5 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h| 6
drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c | 41 +--
3 files changed, 49 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 59cac347baa3..20cfc8c9635b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -2022,6 +2022,9 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct
amdgpu_vm *vm)
spin_lock_init(&vm->invalidated_lock);
INIT_LIST_HEAD(&vm->freed);
INIT_LIST_HEAD(&vm->done);
+ INIT_LIST_HEAD(&vm->pt_freed);
+ INIT_WORK(&vm->pt_free_work, amdgpu_vm_pt_free_work);
+ spin_lock_init(&vm->pt_free_lock);
/* create scheduler entities for page table updates */
r = drm_sched_entity_init(&vm->immediate, DRM_SCHED_PRIORITY_NORMAL,
@@ -2223,6 +2226,8 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct
amdgpu_vm *vm)
amdgpu_amdkfd_gpuvm_destroy_cb(adev, vm);
+ flush_work(&vm->pt_free_work);
+
root = amdgpu_bo_ref(vm->root.bo);
amdgpu_bo_reserve(root, true);
amdgpu_vm_set_pasid(adev, vm, 0);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 9ecb7f663e19..b77fe838c327 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -276,6 +276,11 @@ struct amdgpu_vm {
/* BOs which are invalidated, has been updated in the PTs */
struct list_headdone;
+ /* PT BOs scheduled to free and fill with zero if vm_resv is not hold */
+ struct list_headpt_freed;
+ struct work_struct pt_free_work;
+ spinlock_t pt_free_lock;
+
/* contains the page directory */
struct amdgpu_vm_bo_base root;
struct dma_fence*last_update;
@@ -471,6 +476,7 @@ int amdgpu_vm_pde_update(struct amdgpu_vm_update_params
*params,
int amdgpu_vm_ptes_update(struct amdgpu_vm_update_params *params,
uint64_t start, uint64_t end,
uint64_t dst, uint64_t flags);
+void amdgpu_vm_pt_free_work(struct work_struct *work);
#if defined(CONFIG_DEBUG_FS)
void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
index 88de9f0d4728..c16579471f22 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
@@ -641,6 +641,27 @@ static void amdgpu_vm_pt_free(struct amdgpu_vm_bo_base
*entry)
amdgpu_bo_unref(&entry->bo);
}
+void amdgpu_vm_pt_free_work(struct work_struct *work)
+{
+ struct amdgpu_vm_bo_base *entry, *next;
+ struct amdgpu_vm *vm;
+ LIST_HEAD(pt_freed);
+
+ vm = container_of(work, struct amdgpu_vm, pt_free_work);
+
+ spin_lock(&vm->pt_free_lock);
+ list_splice_init(&vm->pt_freed, &pt_freed);
+ spin_unlock(&vm->pt_free_lock);
+
+ // flush_work in amdgpu_vm_fini ensure vm->root.bo is valid
+ amdgpu_bo_reserve(vm->root.bo, true);
+
+ list_for_each_entry_safe(entry, next, &pt_freed, vm_status)
+ amdgpu_vm_pt_free(entry);
+
+ amdgpu_bo_unreserve(vm->root.bo);
+}
+
/**
* amdgpu_vm_pt_free_dfs - free PD/PT levels
*
@@ -652,11 +673,24 @@ static void amdgpu_vm_pt_free(struct amdgpu_vm_bo_base
*entry)
*/
static void amdgpu_vm_pt_free_dfs(struct amdgpu_device *adev,
struct amdgpu_vm *vm,
- struct amdgpu_vm_pt_cursor *start)
+ struct amdgpu_vm_pt_cursor *start,
+ bool unlocked)
{
struct amdgpu_vm_pt_cursor cursor;
struct amdgpu_vm_bo_base *entry;
+ if (unlocked) {
+ spin_lock(&vm->pt_free_lock);
+ for_each_amdgpu_vm_pt_dfs_safe(adev, vm, start, cursor, entry)
+ list_move(&entry->vm_status, &vm->pt_freed);
+
Re: [PATCH v4 1/2] drm/amdgpu: Fix amdgpu_vm_pt_free warning
On 2022-09-14 05:10, Christian König wrote:
Am 13.09.22 um 22:05 schrieb Philip Yang:
Free page table BO from vm resv unlocked context generate below
warnings.
Add a pt_free_work in vm to free page table BO from vm->pt_freed list.
pass vm resv unlock status from page table update caller, and add vm_bo
entry to vm->pt_freed list and schedule the pt_free_work if calling with
vm resv unlocked.
WARNING: CPU: 12 PID: 3238 at
drivers/gpu/drm/ttm/ttm_bo.c:106 ttm_bo_set_bulk_move+0xa1/0xc0
Call Trace:
amdgpu_vm_pt_free+0x42/0xd0 [amdgpu]
amdgpu_vm_pt_free_dfs+0xb3/0xf0 [amdgpu]
amdgpu_vm_ptes_update+0x52d/0x850 [amdgpu]
amdgpu_vm_update_range+0x2a6/0x640 [amdgpu]
svm_range_unmap_from_gpus+0x110/0x300 [amdgpu]
svm_range_cpu_invalidate_pagetables+0x535/0x600 [amdgpu]
__mmu_notifier_invalidate_range_start+0x1cd/0x230
unmap_vmas+0x9d/0x140
unmap_region+0xa8/0x110
Signed-off-by: Philip Yang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 4 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 6 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c | 47 ---
3 files changed, 51 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 59cac347baa3..27e6155053b6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -2022,6 +2022,9 @@ int amdgpu_vm_init(struct amdgpu_device *adev,
struct amdgpu_vm *vm)
spin_lock_init(&vm->invalidated_lock);
INIT_LIST_HEAD(&vm->freed);
INIT_LIST_HEAD(&vm->done);
+ INIT_LIST_HEAD(&vm->pt_freed);
+ INIT_WORK(&vm->pt_free_work, amdgpu_vm_pt_free_work);
+ spin_lock_init(&vm->pt_free_lock);
/* create scheduler entities for page table updates */
r = drm_sched_entity_init(&vm->immediate,
DRM_SCHED_PRIORITY_NORMAL,
@@ -2244,6 +2247,7 @@ void amdgpu_vm_fini(struct amdgpu_device *adev,
struct amdgpu_vm *vm)
amdgpu_vm_free_mapping(adev, vm, mapping, NULL);
}
+ cancel_work_sync(&vm->pt_free_work);
We should probably not cancel the work here, but rather just wait for
it to finish.
Good point, will change to flush_work, and move it outside
amdgpu_bo_reserve(root), as amdgpu_vm_pt_free_work takes
amdgpu_bo_reserve(root), this will cause deadlock.
amdgpu_vm_pt_free_root(adev, vm);
amdgpu_bo_unreserve(root);
amdgpu_bo_unref(&root);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 9ecb7f663e19..b77fe838c327 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -276,6 +276,11 @@ struct amdgpu_vm {
/* BOs which are invalidated, has been updated in the PTs */
struct list_head done;
+ /* PT BOs scheduled to free and fill with zero if vm_resv is
not hold */
+ struct list_head pt_freed;
+ struct work_struct pt_free_work;
+ spinlock_t pt_free_lock;
+
/* contains the page directory */
struct amdgpu_vm_bo_base root;
struct dma_fence *last_update;
@@ -471,6 +476,7 @@ int amdgpu_vm_pde_update(struct
amdgpu_vm_update_params *params,
int amdgpu_vm_ptes_update(struct amdgpu_vm_update_params *params,
uint64_t start, uint64_t end,
uint64_t dst, uint64_t flags);
+void amdgpu_vm_pt_free_work(struct work_struct *work);
#if defined(CONFIG_DEBUG_FS)
void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct
seq_file *m);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
index 88de9f0d4728..c6f91731ecfb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
@@ -624,12 +624,22 @@ static int amdgpu_vm_pt_alloc(struct
amdgpu_device *adev,
*
* @entry: PDE to free
*/
-static void amdgpu_vm_pt_free(struct amdgpu_vm_bo_base *entry)
+static void amdgpu_vm_pt_free(struct amdgpu_vm_bo_base *entry, bool
unlocked)
{
struct amdgpu_bo *shadow;
if (!entry->bo)
return;
+
+ if (unlocked) {
+ spin_lock(&entry->vm->pt_free_lock);
+ list_move(&entry->vm_status, &entry->vm->pt_freed);
+ spin_unlock(&entry->vm->pt_free_lock);
+
+ schedule_work(&entry->vm->pt_free_work);
+ return;
+ }
+
I strongly prefer to handle this in amdgpu_vm_pt_free_dfs() or even
the caller of this instead and keep this here the low level free
function.
Agree. Will send out v5 patch.
Philip
shadow = amdgpu_bo_shadowed(entry->bo);
if (shadow) {
ttm_bo_set_bulk_move(&shadow->tbo, NULL);
@@ -641,6 +651,29 @@ static void amdgpu_vm_pt_free(struct
amdgpu_vm_bo_base *entry)
amdgpu_bo_unref(&entry->bo);
}
+void amdgpu_vm_pt_free_work(struct work_struct *work)
I think we could make this one here static if we introduce a
amdgpu_vm_pt_init()/amdgpu_vm_pt_fini() function. But not a must have.
Christian.
Re: [PATCH v3 1/1] drm/amdgpu: fix amdgpu_vm_pt_free warning
On 2022-09-13 16:10, Felix Kuehling wrote:
Am 2022-09-13 um 09:19 schrieb Philip Yang:
Free page table BO from vm resv unlocked context generate below
warnings.
Add a pt_free_work in vm to free page table BO from vm->pt_freed list.
pass vm resv unlock status from page table update caller, and add vm_bo
entry to vm->pt_freed list and schedule the pt_free_work if calling with
vm resv unlocked.
WARNING: CPU: 12 PID: 3238 at
drivers/gpu/drm/ttm/ttm_bo.c:106 ttm_bo_set_bulk_move+0xa1/0xc0
Call Trace:
amdgpu_vm_pt_free+0x42/0xd0 [amdgpu]
amdgpu_vm_pt_free_dfs+0xb3/0xf0 [amdgpu]
amdgpu_vm_ptes_update+0x52d/0x850 [amdgpu]
amdgpu_vm_update_range+0x2a6/0x640 [amdgpu]
svm_range_unmap_from_gpus+0x110/0x300 [amdgpu]
svm_range_cpu_invalidate_pagetables+0x535/0x600 [amdgpu]
__mmu_notifier_invalidate_range_start+0x1cd/0x230
unmap_vmas+0x9d/0x140
unmap_region+0xa8/0x110
WARNING: CPU: 0 PID: 1475 at
drivers/dma-buf/dma-resv.c:483 dma_resv_iter_next
Call Trace:
dma_resv_iter_first+0x43/0xa0
amdgpu_vm_sdma_update+0x69/0x2d0 [amdgpu]
amdgpu_vm_ptes_update+0x29c/0x870 [amdgpu]
amdgpu_vm_update_range+0x2f6/0x6c0 [amdgpu]
svm_range_unmap_from_gpus+0x115/0x300 [amdgpu]
svm_range_cpu_invalidate_pagetables+0x510/0x5e0 [amdgpu]
__mmu_notifier_invalidate_range_start+0x1d3/0x230
unmap_vmas+0x140/0x150
unmap_region+0xa8/0x110
Signed-off-by: Philip Yang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 4 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 6 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c | 47 ---
3 files changed, 51 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 59cac347baa3..27e6155053b6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -2022,6 +2022,9 @@ int amdgpu_vm_init(struct amdgpu_device *adev,
struct amdgpu_vm *vm)
spin_lock_init(&vm->invalidated_lock);
INIT_LIST_HEAD(&vm->freed);
INIT_LIST_HEAD(&vm->done);
+ INIT_LIST_HEAD(&vm->pt_freed);
+ INIT_WORK(&vm->pt_free_work, amdgpu_vm_pt_free_work);
+ spin_lock_init(&vm->pt_free_lock);
/* create scheduler entities for page table updates */
r = drm_sched_entity_init(&vm->immediate,
DRM_SCHED_PRIORITY_NORMAL,
@@ -2244,6 +2247,7 @@ void amdgpu_vm_fini(struct amdgpu_device *adev,
struct amdgpu_vm *vm)
amdgpu_vm_free_mapping(adev, vm, mapping, NULL);
}
+ cancel_work_sync(&vm->pt_free_work);
amdgpu_vm_pt_free_root(adev, vm);
amdgpu_bo_unreserve(root);
amdgpu_bo_unref(&root);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 9ecb7f663e19..b77fe838c327 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -276,6 +276,11 @@ struct amdgpu_vm {
/* BOs which are invalidated, has been updated in the PTs */
struct list_head done;
+ /* PT BOs scheduled to free and fill with zero if vm_resv is
not hold */
+ struct list_head pt_freed;
+ struct work_struct pt_free_work;
+ spinlock_t pt_free_lock;
+
/* contains the page directory */
struct amdgpu_vm_bo_base root;
struct dma_fence *last_update;
@@ -471,6 +476,7 @@ int amdgpu_vm_pde_update(struct
amdgpu_vm_update_params *params,
int amdgpu_vm_ptes_update(struct amdgpu_vm_update_params *params,
uint64_t start, uint64_t end,
uint64_t dst, uint64_t flags);
+void amdgpu_vm_pt_free_work(struct work_struct *work);
#if defined(CONFIG_DEBUG_FS)
void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct
seq_file *m);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
index 88de9f0d4728..c6f91731ecfb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
@@ -624,12 +624,22 @@ static int amdgpu_vm_pt_alloc(struct
amdgpu_device *adev,
*
* @entry: PDE to free
*/
-static void amdgpu_vm_pt_free(struct amdgpu_vm_bo_base *entry)
+static void amdgpu_vm_pt_free(struct amdgpu_vm_bo_base *entry, bool
unlocked)
{
struct amdgpu_bo *shadow;
if (!entry->bo)
return;
+
+ if (unlocked) {
+ spin_lock(&entry->vm->pt_free_lock);
+ list_move(&entry->vm_status, &entry->vm->pt_freed);
+ spin_unlock(&entry->vm->pt_free_lock);
+
+ schedule_work(&entry->vm->pt_free_work);
+ return;
+ }
+
shadow = amdgpu_bo_shadowed(entry->bo);
if (shadow) {
ttm_bo_set_bulk_move(&shadow->tbo, NULL);
@@ -641,6 +651,29 @@ static void amdgpu_vm_pt_free(struct
amdgpu_vm_bo_base *entry)
amdgpu_bo_unref(&entry->bo);
}
+void amdgpu_vm_pt_free_work(struct work_struct *work)
+{
+ struct amdgpu_vm_bo_base *entry, *next;
+ struct amdgpu_vm *vm;
+ struct amdgpu_bo *root;
+ LIST_HEAD(pt_freed)
Re: [PATCH] drm/amdgpu: Update PTE flags with TF enabled
Am 2022-09-13 um 18:16 schrieb Mukul Joshi:
This patch updates the PTE flags when translate further (TF) is
enabled:
- With translate_further enabled, invalid PTEs can be 0. Reading
consecutive invalid PTEs as 0 is considered a fault. To prevent
this, ensure invalid PTEs have at least 1 bit set.
- The current invalid PTE flags settings to translate a retry fault
into a no-retry fault, doesn't work with TF enabled. As a result,
update invalid PTE flags settings which works for both TF enabled
and disabled case.
Fixes: 2abf2573b1c69 ("drm/amdgpu: Enable translate_further to extend UTCL2
reach")
Signed-off-by: Mukul Joshi
Reviewed-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 3 +--
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 7 +--
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 59cac347baa3..690fd4f639f1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -2484,8 +2484,7 @@ bool amdgpu_vm_handle_fault(struct amdgpu_device *adev,
u32 pasid,
/* Intentionally setting invalid PTE flag
* combination to force a no-retry-fault
*/
- flags = AMDGPU_PTE_EXECUTABLE | AMDGPU_PDE_PTE |
- AMDGPU_PTE_TF;
+ flags = AMDGPU_PTE_SNOOPED | AMDGPU_PTE_PRT;
value = 0;
} else if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_NEVER) {
/* Redirect the access to the dummy page */
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 4603653916f5..67ca16a8027c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -1103,10 +1103,13 @@ static void gmc_v9_0_get_vm_pde(struct amdgpu_device
*adev, int level,
*flags |= AMDGPU_PDE_BFS(0x9);
} else if (level == AMDGPU_VM_PDB0) {
- if (*flags & AMDGPU_PDE_PTE)
+ if (*flags & AMDGPU_PDE_PTE) {
*flags &= ~AMDGPU_PDE_PTE;
- else
+ if (!(*flags & AMDGPU_PTE_VALID))
+ *addr |= 1 << PAGE_SHIFT;
+ } else {
*flags |= AMDGPU_PTE_TF;
+ }
}
}
Re: [PATCH] drm/amd/display: fix boolconv.cocci warning
Applied. Thanks! On Wed, Sep 14, 2022 at 3:53 AM Yihao Han wrote: > > ./drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c:729:63-68: > WARNING: conversion to bool not needed here > > Generated by: scripts/coccinelle/misc/boolconv.cocci > Signed-off-by: Yihao Han > --- > drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c > b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c > index f4bc77972c4e..4edd0655965b 100644 > --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c > +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c > @@ -726,7 +726,7 @@ static bool mpc32_program_shaper( > else > next_mode = LUT_RAM_A; > > - mpc32_configure_shaper_lut(mpc, next_mode == LUT_RAM_A ? true:false, > mpcc_id); > + mpc32_configure_shaper_lut(mpc, next_mode == LUT_RAM_A, mpcc_id); > > if (next_mode == LUT_RAM_A) > mpc32_program_shaper_luta_settings(mpc, params, mpcc_id); > -- > 2.17.1 >
Re: [PATCH 8/8] drm/amd/display: make optc32_phantom_crtc_post_enable, optc32_setup_manual_trigger and optc32_set_drr static
Applied the series. Thanks!
Alex
On Wed, Sep 14, 2022 at 1:29 AM Jiapeng Chong
wrote:
>
> These three functions are not used outside the function
> dcn32_optc.c, so the modification is defined as static.
>
> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_optc.c:159:6: warning:
> no previous prototype for function 'optc32_phantom_crtc_post_enable'.
> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_optc.c:218:6: warning:
> no previous prototype for ‘optc32_set_drr’.
> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_optc.c:193:6: warning:
> no previous prototype for ‘optc32_setup_manual_trigger’.
>
> Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2140
> Reported-by: Abaci Robot
> Signed-off-by: Jiapeng Chong
> ---
> drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c
> b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c
> index 1fad7b48bd5b..ec3989d37086 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c
> @@ -156,7 +156,7 @@ static bool optc32_disable_crtc(struct timing_generator
> *optc)
> return true;
> }
>
> -void optc32_phantom_crtc_post_enable(struct timing_generator *optc)
> +static void optc32_phantom_crtc_post_enable(struct timing_generator *optc)
> {
> struct optc *optc1 = DCN10TG_FROM_TG(optc);
>
> @@ -190,7 +190,7 @@ static void optc32_set_odm_bypass(struct timing_generator
> *optc,
> optc1->opp_count = 1;
> }
>
> -void optc32_setup_manual_trigger(struct timing_generator *optc)
> +static void optc32_setup_manual_trigger(struct timing_generator *optc)
> {
> struct optc *optc1 = DCN10TG_FROM_TG(optc);
> struct dc *dc = optc->ctx->dc;
> @@ -215,7 +215,7 @@ void optc32_setup_manual_trigger(struct timing_generator
> *optc)
> }
> }
>
> -void optc32_set_drr(
> +static void optc32_set_drr(
> struct timing_generator *optc,
> const struct drr_params *params)
> {
> --
> 2.20.1.7.g153144c
>
Re: [PATCH] drm/amdgpu: Fix the lpfn checking condition in drm buddy
Am 14.09.22 um 14:53 schrieb Ma Jun: Because the value of man->size is changed during suspend/resume process, use mgr->mm.size instead of man->size here for lpfn checking. Signed-off-by: Ma Jun Suggested-by: Christian König Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c index 48e3dc28b156..0b598b510bd8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c @@ -441,7 +441,7 @@ static int amdgpu_vram_mgr_new(struct ttm_resource_manager *man, if (place->flags & TTM_PL_FLAG_TOPDOWN) vres->flags |= DRM_BUDDY_TOPDOWN_ALLOCATION; - if (fpfn || lpfn != man->size) + if (fpfn || lpfn != mgr->mm.size) /* Allocate blocks in desired range */ vres->flags |= DRM_BUDDY_RANGE_ALLOCATION;
Re: [PATCH 1/3] drm/amdgpu: move nbio ih_doorbell_range() into ih code for vega
On Wed, Sep 14, 2022 at 3:05 AM Lazar, Lijo wrote:
>
>
>
> On 9/13/2022 8:18 PM, Alex Deucher wrote:
> > This mirrors what we do for other asics and this way we are
> > sure the ih doorbell range is properly initialized.
> >
> > There is a comment about the way doorbells on gfx9 work that
> > requires that they are initialized for other IPs before GFX
> > is initialized. In this case IH is initialized before GFX,
> > so there should be no issue.
> >
>
> Not sure about the association of patch 1 and 2 with AER as in the
> comment below. I thought the access would go through (PCIE errors may
> not be reported) and the only side effect is doorbell won't be hit/routed.
>
> The comments may not be relevant to patches 1/2, apart from that -
Patches 1 and 2 don't fix the actual issue, but they are prerequisites
for patch 3. Without patches 1 and 2, patch 3 won't work on all
cards. Seemed prudent to just mark all 3, but I could clarify that 1
and 2 are just prerequisites.
Thanks,
Alex
>
> Series is:
> Reviewed-by: Lijo Lazar
>
> Thanks,
> Lijo
>
> > This fixes the Unsupported Request error reported through
> > AER during driver load. The error happens as a write happens
> > to the remap offset before real remapping is done.
> >
> > Link: https://bugzilla.kernel.org/show_bug.cgi?id=216373
> >
> > The error was unnoticed before and got visible because of the commit
> > referenced below. This doesn't fix anything in the commit below, rather
> > fixes the issue in amdgpu exposed by the commit. The reference is only
> > to associate this commit with below one so that both go together.
> >
> > Fixes: 8795e182b02d ("PCI/portdrv: Don't disable AER reporting in
> > get_port_device_capability()")
> >
> > Signed-off-by: Alex Deucher
> > ---
> > drivers/gpu/drm/amd/amdgpu/soc15.c | 3 ---
> > drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 4
> > drivers/gpu/drm/amd/amdgpu/vega20_ih.c | 4
> > 3 files changed, 8 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
> > b/drivers/gpu/drm/amd/amdgpu/soc15.c
> > index 5188da87428d..e6a4002fa67d 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> > @@ -1224,9 +1224,6 @@ static void soc15_doorbell_range_init(struct
> > amdgpu_device *adev)
> > ring->use_doorbell, ring->doorbell_index,
> > adev->doorbell_index.sdma_doorbell_range);
> > }
> > -
> > - adev->nbio.funcs->ih_doorbell_range(adev,
> > adev->irq.ih.use_doorbell,
> > - adev->irq.ih.doorbell_index);
> > }
> > }
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> > b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> > index 03b7066471f9..1e83db0c5438 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> > @@ -289,6 +289,10 @@ static int vega10_ih_irq_init(struct amdgpu_device
> > *adev)
> > }
> > }
> >
> > + if (!amdgpu_sriov_vf(adev))
> > + adev->nbio.funcs->ih_doorbell_range(adev,
> > adev->irq.ih.use_doorbell,
> > +
> > adev->irq.ih.doorbell_index);
> > +
> > pci_set_master(adev->pdev);
> >
> > /* enable interrupts */
> > diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
> > b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
> > index 2022ffbb8dba..59dfca093155 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
> > @@ -340,6 +340,10 @@ static int vega20_ih_irq_init(struct amdgpu_device
> > *adev)
> > }
> > }
> >
> > + if (!amdgpu_sriov_vf(adev))
> > + adev->nbio.funcs->ih_doorbell_range(adev,
> > adev->irq.ih.use_doorbell,
> > +
> > adev->irq.ih.doorbell_index);
> > +
> > pci_set_master(adev->pdev);
> >
> > /* enable interrupts */
> >
Re: [GIT PULL] Immutable backlight-detect-refactor branch between acpi, drm-* and pdx86
Hi Hans, On Mon, Sep 05, 2022 at 10:35:47AM +0200, Hans de Goede wrote: > Hi All, > > Now that all patches have been reviewed/acked here is an immutable > backlight-detect-refactor > branch with 6.0-rc1 + the v5 patch-set, for merging into the relevant (acpi, > drm-* and pdx86) > subsystems. > > Please pull this branch into the relevant subsystems. > > I will merge this into the review-hans branch of the pdx86 git tree today and > from there it will move to for-next once the builders have successfully > build-tested > the merge. I merged it into drm-misc-next, thanks! Maxime signature.asc Description: PGP signature
[PATCH] drm/amd/display: fix boolconv.cocci warning
./drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c:729:63-68: WARNING: conversion to bool not needed here Generated by: scripts/coccinelle/misc/boolconv.cocci Signed-off-by: Yihao Han --- drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c index f4bc77972c4e..4edd0655965b 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c @@ -726,7 +726,7 @@ static bool mpc32_program_shaper( else next_mode = LUT_RAM_A; - mpc32_configure_shaper_lut(mpc, next_mode == LUT_RAM_A ? true:false, mpcc_id); + mpc32_configure_shaper_lut(mpc, next_mode == LUT_RAM_A, mpcc_id); if (next_mode == LUT_RAM_A) mpc32_program_shaper_luta_settings(mpc, params, mpcc_id); -- 2.17.1
[PATCH] drm/amdgpu: Fix the lpfn checking condition in drm buddy
Because the value of man->size is changed during suspend/resume process, use mgr->mm.size instead of man->size here for lpfn checking. Signed-off-by: Ma Jun Suggested-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c index 48e3dc28b156..0b598b510bd8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c @@ -441,7 +441,7 @@ static int amdgpu_vram_mgr_new(struct ttm_resource_manager *man, if (place->flags & TTM_PL_FLAG_TOPDOWN) vres->flags |= DRM_BUDDY_TOPDOWN_ALLOCATION; - if (fpfn || lpfn != man->size) + if (fpfn || lpfn != mgr->mm.size) /* Allocate blocks in desired range */ vres->flags |= DRM_BUDDY_RANGE_ALLOCATION; -- 2.25.1
[PATCH 2/2] drm/amdgpu: move enable irq later to avoid race with ih resume
[background]
On current sienna cichlid mode2 reset, on the slow job hang cases,
since page table context was reverted to completely stop gpu, it
will generate page fault interrupt.
Since the irq are open during recovery stage, during ih resume step,
if this interrupt was in processing, which increased ih ring rptr,
and ih resume meanwhile will set rptr and wptr to 0. This may cause
rptr greater than wptr. Such case was not handled in ih process,
and it will cause rptr continue increasing util reaches the max.
Such case will make fence fallback situation happen.
[how]
Move the enable of irq after ih resumed and before ib test.
Adjusting the position of enable irq on other reset paths accordingly.
Signed-off-by: Victor Zhao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8
drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c | 1 +
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index c0cfae52f12b..0b658225e9ef 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -4625,8 +4625,6 @@ int amdgpu_device_pre_asic_reset(struct amdgpu_device
*adev,
amdgpu_fence_driver_force_completion(ring);
}
- amdgpu_fence_driver_isr_toggle(adev, false);
-
if (job && job->vm)
drm_sched_increase_karma(&job->base);
@@ -4758,6 +4756,10 @@ int amdgpu_do_asic_reset(struct list_head
*device_list_handle,
test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
skip_hw_reset = test_bit(AMDGPU_SKIP_HW_RESET, &reset_context->flags);
+ list_for_each_entry (tmp_adev, device_list_handle, reset_list) {
+ amdgpu_fence_driver_isr_toggle(tmp_adev, false);
+ }
+
/*
* ASIC reset has to be done on all XGMI hive nodes ASAP
* to allow proper links negotiation in FW (within 1 sec)
@@ -5031,8 +5033,6 @@ static void amdgpu_device_recheck_guilty_jobs(
/* Clear this failed job from fence array */
amdgpu_fence_driver_clear_job_fences(ring);
- amdgpu_fence_driver_isr_toggle(adev, false);
-
/* Since the job won't signal and we go for
* another resubmit drop this parent pointer
*/
diff --git a/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c
b/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c
index 7aa570c1ce4a..953036482d1f 100644
--- a/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c
+++ b/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c
@@ -240,6 +240,7 @@ sienna_cichlid_mode2_restore_hwcontext(struct
amdgpu_reset_control *reset_ctl,
* Add this ASIC as tracked as reset was already
* complete successfully.
*/
+ amdgpu_fence_driver_isr_toggle(tmp_adev, false);
amdgpu_register_gpu_instance(tmp_adev);
/* Resume RAS */
--
2.25.1
[PATCH 1/2] drm/amdgpu: fix deadlock caused by overflow
[background]
For a gpu recovery caused by a hang on one ring (e.g. compute),
jobs from another ring (e.g. gfx) may continue signaling during
drm_sched_stop stage. The signal bit will not be cleared.
At the resubmit stage after recovery, the job with hw fence signaled
bit set will call job done directly instead go through fence process.
This makes the hw_rq_count decrease but rcu fence pointer not
cleared yet.
Then overflow happens in the fence driver slots and some jobs may be
skipped and leave the rcu pointer not cleared which makes an infinite
wait for the slot on the next fence emitted.
This infinite wait cause a job timeout on the emitting job. And
driver will stuck at the its sched stop step because kthread_park
cannot be done.
[how]
1. move amdgpu_fence_driver_isr_toggle earlier to close interrupt
before drm sched stop
2. handle all fences in fence process to aviod skip when overflow
happens
Signed-off-by: Victor Zhao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 16 +---
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 6 +-
2 files changed, 14 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 943c9e750575..c0cfae52f12b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -4610,8 +4610,6 @@ int amdgpu_device_pre_asic_reset(struct amdgpu_device
*adev,
amdgpu_virt_fini_data_exchange(adev);
}
- amdgpu_fence_driver_isr_toggle(adev, true);
-
/* block all schedulers and reset given job's ring */
for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
struct amdgpu_ring *ring = adev->rings[i];
@@ -5214,6 +5212,8 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
amdgpu_device_ip_need_full_reset(tmp_adev))
amdgpu_ras_suspend(tmp_adev);
+ amdgpu_fence_driver_isr_toggle(tmp_adev, true);
+
for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
struct amdgpu_ring *ring = tmp_adev->rings[i];
@@ -5228,8 +5228,12 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
atomic_inc(&tmp_adev->gpu_reset_counter);
}
- if (need_emergency_restart)
+ if (need_emergency_restart) {
+ list_for_each_entry (tmp_adev, device_list_handle, reset_list) {
+ amdgpu_fence_driver_isr_toggle(tmp_adev, false);
+ }
goto skip_sched_resume;
+ }
/*
* Must check guilty signal here since after this point all old
@@ -5240,6 +5244,9 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
if (job && dma_fence_is_signaled(&job->hw_fence)) {
job_signaled = true;
dev_info(adev->dev, "Guilty job already signaled, skipping HW
reset");
+ list_for_each_entry (tmp_adev, device_list_handle, reset_list) {
+ amdgpu_fence_driver_isr_toggle(tmp_adev, false);
+ }
goto skip_hw_reset;
}
@@ -5276,6 +5283,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
if (r && r == -EAGAIN) {
set_bit(AMDGPU_SKIP_MODE2_RESET, &reset_context->flags);
adev->asic_reset_res = 0;
+ amdgpu_fence_driver_isr_toggle(adev, true);
goto retry;
}
}
@@ -5711,6 +5719,8 @@ pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev
*pdev)
set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags);
set_bit(AMDGPU_SKIP_MODE2_RESET, &reset_context.flags);
+ amdgpu_fence_driver_isr_toggle(adev, true);
+
adev->no_hw_access = true;
r = amdgpu_device_pre_asic_reset(adev, &reset_context);
adev->no_hw_access = false;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
index 8adeb7469f1e..65a877e1a7fc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
@@ -287,15 +287,11 @@ bool amdgpu_fence_process(struct amdgpu_ring *ring)
if (unlikely(seq == last_seq))
return false;
- last_seq &= drv->num_fences_mask;
- seq &= drv->num_fences_mask;
-
do {
struct dma_fence *fence, **ptr;
++last_seq;
- last_seq &= drv->num_fences_mask;
- ptr = &drv->fences[last_seq];
+ ptr = &drv->fences[last_seq & drv->num_fences_mask];
/* There is always exactly one thread signaling this fence slot
*/
fence = rcu_dereference_protected(*ptr, 1);
--
2.25.1
Re: [PATCH v4 2/2] drm/amdgpu: SDMA update use unlocked iterator
Am 13.09.22 um 22:05 schrieb Philip Yang:
SDMA update page table may be called from unlocked context, this
generate below warning. Use unlocked iterator to handle this case.
WARNING: CPU: 0 PID: 1475 at
drivers/dma-buf/dma-resv.c:483 dma_resv_iter_next
Call Trace:
dma_resv_iter_first+0x43/0xa0
amdgpu_vm_sdma_update+0x69/0x2d0 [amdgpu]
amdgpu_vm_ptes_update+0x29c/0x870 [amdgpu]
amdgpu_vm_update_range+0x2f6/0x6c0 [amdgpu]
svm_range_unmap_from_gpus+0x115/0x300 [amdgpu]
svm_range_cpu_invalidate_pagetables+0x510/0x5e0 [amdgpu]
__mmu_notifier_invalidate_range_start+0x1d3/0x230
unmap_vmas+0x140/0x150
unmap_region+0xa8/0x110
Signed-off-by: Philip Yang
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
index 1fd3cbca20a2..718db7d98e5a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
@@ -211,12 +211,15 @@ static int amdgpu_vm_sdma_update(struct
amdgpu_vm_update_params *p,
int r;
/* Wait for PD/PT moves to be completed */
- dma_resv_for_each_fence(&cursor, bo->tbo.base.resv,
- DMA_RESV_USAGE_KERNEL, fence) {
+ dma_resv_iter_begin(&cursor, bo->tbo.base.resv, DMA_RESV_USAGE_KERNEL);
+ dma_resv_for_each_fence_unlocked(&cursor, fence) {
r = amdgpu_sync_fence(&p->job->sync, fence);
- if (r)
+ if (r) {
+ dma_resv_iter_end(&cursor);
return r;
+ }
}
+ dma_resv_iter_end(&cursor);
do {
ndw = p->num_dw_left;
Re: [PATCH v4 1/2] drm/amdgpu: Fix amdgpu_vm_pt_free warning
Am 13.09.22 um 22:05 schrieb Philip Yang:
Free page table BO from vm resv unlocked context generate below
warnings.
Add a pt_free_work in vm to free page table BO from vm->pt_freed list.
pass vm resv unlock status from page table update caller, and add vm_bo
entry to vm->pt_freed list and schedule the pt_free_work if calling with
vm resv unlocked.
WARNING: CPU: 12 PID: 3238 at
drivers/gpu/drm/ttm/ttm_bo.c:106 ttm_bo_set_bulk_move+0xa1/0xc0
Call Trace:
amdgpu_vm_pt_free+0x42/0xd0 [amdgpu]
amdgpu_vm_pt_free_dfs+0xb3/0xf0 [amdgpu]
amdgpu_vm_ptes_update+0x52d/0x850 [amdgpu]
amdgpu_vm_update_range+0x2a6/0x640 [amdgpu]
svm_range_unmap_from_gpus+0x110/0x300 [amdgpu]
svm_range_cpu_invalidate_pagetables+0x535/0x600 [amdgpu]
__mmu_notifier_invalidate_range_start+0x1cd/0x230
unmap_vmas+0x9d/0x140
unmap_region+0xa8/0x110
Signed-off-by: Philip Yang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c| 4 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h| 6 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c | 47 ---
3 files changed, 51 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 59cac347baa3..27e6155053b6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -2022,6 +2022,9 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct
amdgpu_vm *vm)
spin_lock_init(&vm->invalidated_lock);
INIT_LIST_HEAD(&vm->freed);
INIT_LIST_HEAD(&vm->done);
+ INIT_LIST_HEAD(&vm->pt_freed);
+ INIT_WORK(&vm->pt_free_work, amdgpu_vm_pt_free_work);
+ spin_lock_init(&vm->pt_free_lock);
/* create scheduler entities for page table updates */
r = drm_sched_entity_init(&vm->immediate, DRM_SCHED_PRIORITY_NORMAL,
@@ -2244,6 +2247,7 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct
amdgpu_vm *vm)
amdgpu_vm_free_mapping(adev, vm, mapping, NULL);
}
+ cancel_work_sync(&vm->pt_free_work);
We should probably not cancel the work here, but rather just wait for it
to finish.
amdgpu_vm_pt_free_root(adev, vm);
amdgpu_bo_unreserve(root);
amdgpu_bo_unref(&root);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 9ecb7f663e19..b77fe838c327 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -276,6 +276,11 @@ struct amdgpu_vm {
/* BOs which are invalidated, has been updated in the PTs */
struct list_headdone;
+ /* PT BOs scheduled to free and fill with zero if vm_resv is not hold */
+ struct list_headpt_freed;
+ struct work_struct pt_free_work;
+ spinlock_t pt_free_lock;
+
/* contains the page directory */
struct amdgpu_vm_bo_base root;
struct dma_fence*last_update;
@@ -471,6 +476,7 @@ int amdgpu_vm_pde_update(struct amdgpu_vm_update_params
*params,
int amdgpu_vm_ptes_update(struct amdgpu_vm_update_params *params,
uint64_t start, uint64_t end,
uint64_t dst, uint64_t flags);
+void amdgpu_vm_pt_free_work(struct work_struct *work);
#if defined(CONFIG_DEBUG_FS)
void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
index 88de9f0d4728..c6f91731ecfb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
@@ -624,12 +624,22 @@ static int amdgpu_vm_pt_alloc(struct amdgpu_device *adev,
*
* @entry: PDE to free
*/
-static void amdgpu_vm_pt_free(struct amdgpu_vm_bo_base *entry)
+static void amdgpu_vm_pt_free(struct amdgpu_vm_bo_base *entry, bool unlocked)
{
struct amdgpu_bo *shadow;
if (!entry->bo)
return;
+
+ if (unlocked) {
+ spin_lock(&entry->vm->pt_free_lock);
+ list_move(&entry->vm_status, &entry->vm->pt_freed);
+ spin_unlock(&entry->vm->pt_free_lock);
+
+ schedule_work(&entry->vm->pt_free_work);
+ return;
+ }
+
I strongly prefer to handle this in amdgpu_vm_pt_free_dfs() or even the
caller of this instead and keep this here the low level free function.
shadow = amdgpu_bo_shadowed(entry->bo);
if (shadow) {
ttm_bo_set_bulk_move(&shadow->tbo, NULL);
@@ -641,6 +651,29 @@ static void amdgpu_vm_pt_free(struct amdgpu_vm_bo_base
*entry)
amdgpu_bo_unref(&entry->bo);
}
+void amdgpu_vm_pt_free_work(struct work_struct *work)
I think we could make this one here static if we introduce a
amdgpu_vm_pt_init()/amdgpu_vm_pt_fini() function. But not a must have.
Christian.
+{
+ struct amdgpu_vm_bo_base *entry, *next;
+ struct amdgpu_vm *vm;
+ struct amdgpu_bo *root;
+ LIST_H
Re: [PATCH 3/3] drm/amdgpu: make sure to init common IP before gmc
Am 13.09.22 um 16:48 schrieb Alex Deucher:
Move common IP init before GMC init so that HDP gets
remapped before GMC init which uses it.
At some point we should improve this so that we have the common and GMC
stuff in the hardware init as first thing without those hacks.
But anyway Acked-by for now since this is higher level design work.
Regards,
Christian.
This fixes the Unsupported Request error reported through
AER during driver load. The error happens as a write happens
to the remap offset before real remapping is done.
Link: https://bugzilla.kernel.org/show_bug.cgi?id=216373
The error was unnoticed before and got visible because of the commit
referenced below. This doesn't fix anything in the commit below, rather
fixes the issue in amdgpu exposed by the commit. The reference is only
to associate this commit with below one so that both go together.
Fixes: 8795e182b02d ("PCI/portdrv: Don't disable AER reporting in
get_port_device_capability()")
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 14 +++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 899564ea8b4b..4da85ce9e3b1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2375,8 +2375,16 @@ static int amdgpu_device_ip_init(struct amdgpu_device
*adev)
}
adev->ip_blocks[i].status.sw = true;
- /* need to do gmc hw init early so we can allocate gpu mem */
- if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
+ if (adev->ip_blocks[i].version->type ==
AMD_IP_BLOCK_TYPE_COMMON) {
+ /* need to do common hw init early so everything is set
up for gmc */
+ r = adev->ip_blocks[i].version->funcs->hw_init((void
*)adev);
+ if (r) {
+ DRM_ERROR("hw_init %d failed %d\n", i, r);
+ goto init_failed;
+ }
+ adev->ip_blocks[i].status.hw = true;
+ } else if (adev->ip_blocks[i].version->type ==
AMD_IP_BLOCK_TYPE_GMC) {
+ /* need to do gmc hw init early so we can allocate gpu
mem */
/* Try to reserve bad pages early */
if (amdgpu_sriov_vf(adev))
amdgpu_virt_exchange_data(adev);
@@ -3062,8 +3070,8 @@ static int amdgpu_device_ip_reinit_early_sriov(struct
amdgpu_device *adev)
int i, r;
static enum amd_ip_block_type ip_order[] = {
- AMD_IP_BLOCK_TYPE_GMC,
AMD_IP_BLOCK_TYPE_COMMON,
+ AMD_IP_BLOCK_TYPE_GMC,
AMD_IP_BLOCK_TYPE_PSP,
AMD_IP_BLOCK_TYPE_IH,
};
[PATCH AUTOSEL 5.19 20/22] drm/amdgpu: prevent toc firmware memory leak
From: Guchun Chen
[ Upstream commit aac4cec1ec45d72bd03eaf3fd772c5a609f5ed26 ]
It's missed in psp fini.
Signed-off-by: Guchun Chen
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index e9411c28d88ba..9cb7d208a09ad 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -481,11 +481,14 @@ static int psp_sw_fini(void *handle)
release_firmware(psp->ta_fw);
psp->ta_fw = NULL;
}
- if (adev->psp.cap_fw) {
+ if (psp->cap_fw) {
release_firmware(psp->cap_fw);
psp->cap_fw = NULL;
}
-
+ if (psp->toc_fw) {
+ release_firmware(psp->toc_fw);
+ psp->toc_fw = NULL;
+ }
if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) ||
adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7))
psp_sysfs_fini(adev);
--
2.35.1
Re: [PATCH 1/4] drm/amdgpu: Introduce gfx software ring(v4)
Am 13.09.22 um 11:05 schrieb jiadong@amd.com:
From: "Jiadong.Zhu"
The software ring is created to support priority
context while there is only one hardware queue
for gfx.
Every software rings has its fence driver and could
be used as an ordinary ring for the gpu_scheduler.
Multiple software rings are binded to a real ring
with the ring muxer. The packages committed on the
software ring are copied to the real ring.
v2: use array to store software ring entry.
v3: remove unnecessary prints.
v4: remove amdgpu_ring_sw_init/fini functions,
using gtt for sw ring buffer for later dma copy
optimization.
Signed-off-by: Jiadong.Zhu
---
drivers/gpu/drm/amd/amdgpu/Makefile | 3 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 3 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 3 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c | 182 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.h | 67 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_sw_ring.c | 60 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_sw_ring.h | 43 +
7 files changed, 360 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.h
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_sw_ring.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_sw_ring.h
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
b/drivers/gpu/drm/amd/amdgpu/Makefile
index 3e0e2eb7e235..85224bc81ce5 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -58,7 +58,8 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
amdgpu_vm_sdma.o amdgpu_discovery.o amdgpu_ras_eeprom.o amdgpu_nbio.o \
amdgpu_umc.o smu_v11_0_i2c.o amdgpu_fru_eeprom.o amdgpu_rap.o \
amdgpu_fw_attestation.o amdgpu_securedisplay.o \
- amdgpu_eeprom.o amdgpu_mca.o amdgpu_psp_ta.o amdgpu_lsdma.o
+ amdgpu_eeprom.o amdgpu_mca.o amdgpu_psp_ta.o amdgpu_lsdma.o \
+ amdgpu_sw_ring.o amdgpu_ring_mux.o
amdgpu-$(CONFIG_PROC_FS) += amdgpu_fdinfo.o
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index 53526ffb2ce1..0de8e3cd0f1c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -33,6 +33,7 @@
#include "amdgpu_imu.h"
#include "soc15.h"
#include "amdgpu_ras.h"
+#include "amdgpu_ring_mux.h"
/* GFX current status */
#define AMDGPU_GFX_NORMAL_MODE0xL
@@ -346,6 +347,8 @@ struct amdgpu_gfx {
struct amdgpu_gfx_ras *ras;
boolis_poweron;
+
+ struct amdgpu_ring_mux muxer;
};
#define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 7d89a52091c0..fe33a683bfba 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -278,6 +278,9 @@ struct amdgpu_ring {
boolis_mes_queue;
uint32_thw_queue_id;
struct amdgpu_mes_ctx_data *mes_ctx;
+
+ boolis_sw_ring;
+
};
#define amdgpu_ring_parse_cs(r, p, job, ib) ((r)->funcs->parse_cs((p), (job), (ib)))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c
new file mode 100644
index ..652a6d3e0ec3
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c
@@ -0,0 +1,182 @@
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include
+
+#include "amdgpu_ring_mux.h"
+#include "amdgpu_ring.h"
+
+#define AMDGPU_MUX_RESUBMIT_JIFFIES_TIMEOUT (HZ/2)
+
+static int copy_pkt_from_sw_ring(struct amdgpu_ring_mux *mux, struct
amdgpu_ring *ring,
+
[PATCH] drm/amdgpu/display: using swap() instead of temp variable
Use swap() instead of the temp variable to swap values.
Signed-off-by: Yihao Han
---
drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
index 85ed0afb74a9..7ef528c5b700 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
@@ -2907,7 +2907,6 @@ static enum bp_result construct_integrated_info(
struct atom_common_table_header *header;
struct atom_data_revision revision;
- struct clock_voltage_caps temp = {0, 0};
uint32_t i;
uint32_t j;
@@ -2983,10 +2982,7 @@ static enum bp_result construct_integrated_info(
info->disp_clk_voltage[j-1].max_supported_clk
) {
/* swap j and j - 1*/
- temp = info->disp_clk_voltage[j-1];
- info->disp_clk_voltage[j-1] =
- info->disp_clk_voltage[j];
- info->disp_clk_voltage[j] = temp;
+ swap(info->disp_clk_voltage[j-1],
info->disp_clk_voltage[j]);
}
}
}
--
2.17.1
[PATCH 4/8] drm/amd/display: make some functions static
These functions are not used outside the file dcn32_hubbub.c, so the
modification is defined as static.
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn314/dcn314_dccg.c:223:6: warning:
no previous prototype for ‘dccg314_set_valid_pixel_rate’.
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn314/dcn314_dccg.c:184:6: warning:
no previous prototype for ‘dccg314_set_dpstreamclk’.
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn314/dcn314_dccg.c:140:6: warning:
no previous prototype for ‘dccg314_set_dtbclk_dto’.
Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2144
Reported-by: Abaci Robot
Signed-off-by: Jiapeng Chong
---
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c
b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c
index 232cc15979dd..36630d532c18 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c
@@ -137,7 +137,7 @@ static void dccg314_set_dtbclk_p_src(
}
/* Controls the generation of pixel valid for OTG in (OTG -> HPO case) */
-void dccg314_set_dtbclk_dto(
+static void dccg314_set_dtbclk_dto(
struct dccg *dccg,
const struct dtbclk_dto_params *params)
{
@@ -181,7 +181,7 @@ void dccg314_set_dtbclk_dto(
}
}
-void dccg314_set_dpstreamclk(
+static void dccg314_set_dpstreamclk(
struct dccg *dccg,
enum streamclk_source src,
int otg_inst,
@@ -220,7 +220,7 @@ void dccg314_set_dpstreamclk(
}
}
-void dccg314_set_valid_pixel_rate(
+static void dccg314_set_valid_pixel_rate(
struct dccg *dccg,
int ref_dtbclk_khz,
int otg_inst,
--
2.20.1.7.g153144c
[PATCH 3/8] drm/amd/display: make optc314_phantom_crtc_post_enable static
This symbol is not used outside of dcn314_optc.c, so marks it static.
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn314/dcn314_optc.c:153:6: warning:
no previous prototype for ‘optc314_phantom_crtc_post_enable’.
Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2147
Reported-by: Abaci Robot
Signed-off-by: Jiapeng Chong
---
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_optc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_optc.c
b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_optc.c
index 38aa28ec6b13..47eb162f1a75 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_optc.c
@@ -150,7 +150,7 @@ static bool optc314_disable_crtc(struct timing_generator
*optc)
return true;
}
-void optc314_phantom_crtc_post_enable(struct timing_generator *optc)
+static void optc314_phantom_crtc_post_enable(struct timing_generator *optc)
{
struct optc *optc1 = DCN10TG_FROM_TG(optc);
--
2.20.1.7.g153144c
回复: Re: 回复: Re: [PATCH] drm:Fix the blank screen problem of some 1920x1080 75Hz monitors using R520 graphics card
Sorry to trouble you, we ran some tests on this patch and want to communicate with you.static void amdgpu_pll_get_fb_ref_div(struct amdgpu_device *adev, unsigned nom, unsigned den, unsigned post_div,unsigned fb_div_max, unsigned ref_div_max,unsigned *fb_div, unsigned *ref_div){ /* limit reference * post divider to a maximum */if (adev->family == AMDGPU_FAMILY_SI)ref_div_max = min(100 / post_div, ref_div_max);elseref_div_max = min(128 / post_div, ref_div_max); /* get matching reference and feedback divider */*ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max);*fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den); /* limit fb divider to its maximum */if (*fb_div > fb_div_max) {*ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div);*fb_div = fb_div_max;}}For R520, the max value of the ref_div_max in this function used to be 128. In order to fix the black screen problem of some monitors, it was changed to 100. From the commit message at the time, we learned that this was a temporary solution. When the value of ref_div_max is 100, it will also cause problems with some monitors.
void amdgpu_pll_compute(struct amdgpu_device *adev, struct amdgpu_pll *pll, u32 freq, u32 *dot_clock_p,u32 *fb_div_p,u32 *frac_fb_div_p,u32 *ref_div_p,u32 *post_div_p){../* now search for a post divider */if (pll->flags & AMDGPU_PLL_PREFER_MINM_OVER_MAXP)post_div_best = post_div_min;elsepost_div_best = post_div_max;diff_best = ~0;for (post_div = post_div_min; post_div <= post_div_max; ++post_div) {unsigned diff;amdgpu_pll_get_fb_ref_div(adev, nom, den, post_div, fb_div_max,ref_div_max, &fb_div, &ref_div);diff = abs(target_clock - (pll->reference_freq * fb_div) /(ref_div * post_div));if (diff < diff_best || (diff == diff_best &&!(pll->flags & AMDGPU_PLL_PREFER_MINM_OVER_MAXP))) {post_div_best = post_div;diff_best = diff;}}post_div = post_div_best;..}This piece of code in the above function is to find a post_div, so that the value of diff = abs(target_clock - (pll->reference_freq * fb_div) /(ref_div * post_div)) is the smallest. The pixel clock closest to the target frequency when the value of the diff is the smallest. The values of the reference divider(ref_div) and feedback divider(fb_div) in the above formula are affected by ref_div_max, so when the value of ref_div_max is different, the value of diff may also be different. The larger value of diff may cause the blank screen problem of some monitors.A value of 100 or 128 for ref_div_max is not suitable for all monitors. So we set it to 100 and 128 in turn to calculate the corresponding ref_div and fb_div values, and then calculate diff = abs(target_clock - (pll->reference_freq * fb_div) /(ref_div * post_div)). If the diff is smaller when the value of ref_div_max is 100, set the value of ref_div_max to 100. Otherwise, set the value of ref_div_max to 128. In this way, the value of ref_div_max can be determined according to the value of diff, in order to adapt to all monitors. After our verification on different monitors, those monitors that have a blank screen problem when the value of ref_div_max is 100 or 128 can work normally under this scheme.We believe that temporarily adopting this method to replace the previous method can improve the compatibility of the graphics card.Best Regards.
主 题：Re: 回复: Re: [PATCH] drm:Fix the blank screen problem of some 1920x1080 75Hz monitors using R520 graphics card
日 期：2022-09-05 19:12
发件人：Christian König
收件人：钟沛alexander.deuc...@amd.comxinhui.pan@amd.comairlied@linux.iedaniel@ffwll.chisabba...@riseup.net
Am 05.09.22 um 10:10 schrieb 钟沛:
Thanks for your reply!
We found that in the amdgpu_pll_compute function, when the
target_clock is the value contained in the drm_dmt_modes defined
in drm_edid.c, the diff is 0. When target_clock is some special
value, we cannot find a diff value of 0, so we need to find the
smallest diff value to fit the current target_clock. For the
monitor that has the blank screen problem here, we found that
when the ref_div_max is 128, the diff value is smaller and the
blank screen problem can be solved. We tested some other
monitors and added log printing to the code. We found that this
change did not affect those monitors, and in the analys
[PATCH 6/8] drm/amd/display: make some functions static
These functions are not used outside the file dcn32_hubbub.c, so the
modification is defined as static.
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_hubbub.c:912:6: warning:
no previous prototype for ‘hubbub32_force_wm_propagate_to_pipes’.
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_hubbub.c:823:6: warning:
no previous prototype for ‘hubbub32_wm_read_state’.
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_hubbub.c:772:6: warning:
no previous prototype for ‘hubbub32_init_watermarks’.
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_hubbub.c:712:6: warning:
no previous prototype for ‘hubbub32_force_usr_retraining_allow’.
Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2141
Reported-by: Abaci Robot
Signed-off-by: Jiapeng Chong
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c
index 99eb239bbc7b..d4963959426c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c
@@ -709,7 +709,7 @@ static bool hubbub32_program_usr_watermarks(
return wm_pending;
}
-void hubbub32_force_usr_retraining_allow(struct hubbub *hubbub, bool allow)
+static void hubbub32_force_usr_retraining_allow(struct hubbub *hubbub, bool
allow)
{
struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
@@ -769,7 +769,7 @@ static bool hubbub32_program_watermarks(
}
/* Copy values from WM set A to all other sets */
-void hubbub32_init_watermarks(struct hubbub *hubbub)
+static void hubbub32_init_watermarks(struct hubbub *hubbub)
{
struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
uint32_t reg;
@@ -820,7 +820,7 @@ void hubbub32_init_watermarks(struct hubbub *hubbub)
REG_WRITE(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D, reg);
}
-void hubbub32_wm_read_state(struct hubbub *hubbub,
+static void hubbub32_wm_read_state(struct hubbub *hubbub,
struct dcn_hubbub_wm *wm)
{
struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
@@ -909,7 +909,7 @@ void hubbub32_wm_read_state(struct hubbub *hubbub,
DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D,
&s->fclk_pstate_change);
}
-void hubbub32_force_wm_propagate_to_pipes(struct hubbub *hubbub)
+static void hubbub32_force_wm_propagate_to_pipes(struct hubbub *hubbub)
{
struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
uint32_t refclk_mhz =
hubbub->ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000;
--
2.20.1.7.g153144c
[PATCH 8/8] drm/amd/display: make optc32_phantom_crtc_post_enable, optc32_setup_manual_trigger and optc32_set_drr static
These three functions are not used outside the function
dcn32_optc.c, so the modification is defined as static.
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_optc.c:159:6: warning: no
previous prototype for function 'optc32_phantom_crtc_post_enable'.
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_optc.c:218:6: warning: no
previous prototype for ‘optc32_set_drr’.
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_optc.c:193:6: warning: no
previous prototype for ‘optc32_setup_manual_trigger’.
Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2140
Reported-by: Abaci Robot
Signed-off-by: Jiapeng Chong
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c
index 1fad7b48bd5b..ec3989d37086 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c
@@ -156,7 +156,7 @@ static bool optc32_disable_crtc(struct timing_generator
*optc)
return true;
}
-void optc32_phantom_crtc_post_enable(struct timing_generator *optc)
+static void optc32_phantom_crtc_post_enable(struct timing_generator *optc)
{
struct optc *optc1 = DCN10TG_FROM_TG(optc);
@@ -190,7 +190,7 @@ static void optc32_set_odm_bypass(struct timing_generator
*optc,
optc1->opp_count = 1;
}
-void optc32_setup_manual_trigger(struct timing_generator *optc)
+static void optc32_setup_manual_trigger(struct timing_generator *optc)
{
struct optc *optc1 = DCN10TG_FROM_TG(optc);
struct dc *dc = optc->ctx->dc;
@@ -215,7 +215,7 @@ void optc32_setup_manual_trigger(struct timing_generator
*optc)
}
}
-void optc32_set_drr(
+static void optc32_set_drr(
struct timing_generator *optc,
const struct drr_params *params)
{
--
2.20.1.7.g153144c
[PATCH 7/8] drm/amd/display: make some functions static
These functions are not used outside the file dcn32_dccg.c, so the
modification is defined as static.
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_dccg.c:257:6: warning: no
previous prototype for ‘dccg32_otg_drop_pixel’.
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_dccg.c:248:6: warning: no
previous prototype for ‘dccg32_otg_add_pixel’.
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_dccg.c:211:6: warning: no
previous prototype for ‘dccg32_set_dpstreamclk’.
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_dccg.c:136:6: warning: no
previous prototype for ‘dccg32_set_dtbclk_dto’.
Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2142
Reported-by: Abaci Robot
Signed-off-by: Jiapeng Chong
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c
index 0d5e8a441512..26eb04ea472c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c
@@ -133,7 +133,7 @@ static void dccg32_set_dtbclk_p_src(
}
/* Controls the generation of pixel valid for OTG in (OTG -> HPO case) */
-void dccg32_set_dtbclk_dto(
+static void dccg32_set_dtbclk_dto(
struct dccg *dccg,
const struct dtbclk_dto_params *params)
{
@@ -208,7 +208,7 @@ static void dccg32_get_dccg_ref_freq(struct dccg *dccg,
return;
}
-void dccg32_set_dpstreamclk(
+static void dccg32_set_dpstreamclk(
struct dccg *dccg,
enum streamclk_source src,
int otg_inst,
@@ -245,7 +245,7 @@ void dccg32_set_dpstreamclk(
}
}
-void dccg32_otg_add_pixel(struct dccg *dccg,
+static void dccg32_otg_add_pixel(struct dccg *dccg,
uint32_t otg_inst)
{
struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
@@ -254,7 +254,7 @@ void dccg32_otg_add_pixel(struct dccg *dccg,
OTG_ADD_PIXEL[otg_inst], 1);
}
-void dccg32_otg_drop_pixel(struct dccg *dccg,
+static void dccg32_otg_drop_pixel(struct dccg *dccg,
uint32_t otg_inst)
{
struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
--
2.20.1.7.g153144c
[PATCH 5/8] drm/amd/display: make mmhubbub32_config_mcif_buf static
This symbol is not used outside of dcn32_mmhubbub.c, so marks it static.
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_mmhubbub.c:103:6: warning:
no previous prototype for ‘mmhubbub32_config_mcif_buf’.
Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2145
Reported-by: Abaci Robot
Signed-off-by: Jiapeng Chong
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mmhubbub.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mmhubbub.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mmhubbub.c
index adf93cc8359c..41b0baf8e183 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mmhubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mmhubbub.c
@@ -100,7 +100,7 @@ static void mmhubbub32_warmup_mcif(struct mcif_wb *mcif_wb,
REG_UPDATE(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_EN, false);
}
-void mmhubbub32_config_mcif_buf(struct mcif_wb *mcif_wb,
+static void mmhubbub32_config_mcif_buf(struct mcif_wb *mcif_wb,
struct mcif_buf_params *params,
unsigned int dest_height)
{
--
2.20.1.7.g153144c
[PATCH 1/8] drm/amd/display: make some functions static
These functions are not used outside the file dcn30_resource.c, so the
modification is defined as static.
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_resource.c:1949:6:
warning: no previous prototype for
‘is_refresh_rate_support_mclk_switch_using_fw_based_vblank_stretch’.
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_resource.c:1919:5:
warning: no previous prototype for ‘get_frame_rate_at_max_stretch_100hz’.
Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2143
Reported-by: Abaci Robot
Signed-off-by: Jiapeng Chong
---
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
index 64320e0ca446..f6f3878c99b8 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
@@ -1916,7 +1916,7 @@ static int get_refresh_rate(struct dc_state *context)
*/
#define V_SCALE (1 / MAX_STRETCHED_V_BLANK)
-int get_frame_rate_at_max_stretch_100hz(struct dc_state *context)
+static int get_frame_rate_at_max_stretch_100hz(struct dc_state *context)
{
struct dc_crtc_timing *timing = NULL;
uint32_t sec_per_100_lines;
@@ -1946,7 +1946,7 @@ int get_frame_rate_at_max_stretch_100hz(struct dc_state
*context)
return scaled_refresh_rate;
}
-bool is_refresh_rate_support_mclk_switch_using_fw_based_vblank_stretch(struct
dc_state *context)
+static bool
is_refresh_rate_support_mclk_switch_using_fw_based_vblank_stretch(struct
dc_state *context)
{
int refresh_rate_max_stretch_100hz;
int min_refresh_100hz;
--
2.20.1.7.g153144c
[PATCH 2/8] drm/amd/display: make enc314_stream_encoder_dvi_set_stream_attribute static
This symbol is not used outside of dcn314_dio_stream_encoder.c, so marks it static. drivers/gpu/drm/amd/amdgpu/../display/dc/dcn314/dcn314_dio_stream_encoder.c:84:6: warning: no previous prototype for ‘enc314_stream_encoder_dvi_set_stream_attribute’. Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2146 Reported-by: Abaci Robot Signed-off-by: Jiapeng Chong --- .../gpu/drm/amd/display/dc/dcn314/dcn314_dio_stream_encoder.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dio_stream_encoder.c index e3351ddc566c..44e585c73785 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dio_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dio_stream_encoder.c @@ -81,7 +81,7 @@ static void enc314_dp_set_odm_combine( } /* setup stream encoder in dvi mode */ -void enc314_stream_encoder_dvi_set_stream_attribute( +static void enc314_stream_encoder_dvi_set_stream_attribute( struct stream_encoder *enc, struct dc_crtc_timing *crtc_timing, bool is_dual_link) -- 2.20.1.7.g153144c
Re: [PATCH] drm/amdgpu: Update PTE flags with TF enabled
Am 14.09.22 um 00:16 schrieb Mukul Joshi:
This patch updates the PTE flags when translate further (TF) is
enabled:
- With translate_further enabled, invalid PTEs can be 0. Reading
consecutive invalid PTEs as 0 is considered a fault. To prevent
this, ensure invalid PTEs have at least 1 bit set.
- The current invalid PTE flags settings to translate a retry fault
into a no-retry fault, doesn't work with TF enabled. As a result,
update invalid PTE flags settings which works for both TF enabled
and disabled case.
Fixes: 2abf2573b1c69 ("drm/amdgpu: Enable translate_further to extend UTCL2
reach")
Signed-off-by: Mukul Joshi
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 3 +--
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 7 +--
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 59cac347baa3..690fd4f639f1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -2484,8 +2484,7 @@ bool amdgpu_vm_handle_fault(struct amdgpu_device *adev,
u32 pasid,
/* Intentionally setting invalid PTE flag
* combination to force a no-retry-fault
*/
- flags = AMDGPU_PTE_EXECUTABLE | AMDGPU_PDE_PTE |
- AMDGPU_PTE_TF;
+ flags = AMDGPU_PTE_SNOOPED | AMDGPU_PTE_PRT;
value = 0;
} else if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_NEVER) {
/* Redirect the access to the dummy page */
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 4603653916f5..67ca16a8027c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -1103,10 +1103,13 @@ static void gmc_v9_0_get_vm_pde(struct amdgpu_device
*adev, int level,
*flags |= AMDGPU_PDE_BFS(0x9);
} else if (level == AMDGPU_VM_PDB0) {
- if (*flags & AMDGPU_PDE_PTE)
+ if (*flags & AMDGPU_PDE_PTE) {
*flags &= ~AMDGPU_PDE_PTE;
- else
+ if (!(*flags & AMDGPU_PTE_VALID))
+ *addr |= 1 << PAGE_SHIFT;
+ } else {
*flags |= AMDGPU_PTE_TF;
+ }
}
}
Re: [PATCH 5/7] drm/amdgpu: use DMA_RESV_USAGE_BOOKKEEP v2
Am 13.09.22 um 22:52 schrieb Felix Kuehling:
Am 2022-09-12 um 08:36 schrieb Christian König:
Use DMA_RESV_USAGE_BOOKKEEP for VM page table updates and KFD
preemption fence.
v2: actually update all usages for KFD
Signed-off-by: Christian König
---
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 26 ---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 3 ++-
2 files changed, 18 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index f4c49537d837..978d3970b5cc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -298,7 +298,7 @@ static int
amdgpu_amdkfd_remove_eviction_fence(struct amdgpu_bo *bo,
*/
replacement = dma_fence_get_stub();
dma_resv_replace_fences(bo->tbo.base.resv, ef->base.context,
- replacement, DMA_RESV_USAGE_READ);
+ replacement, DMA_RESV_USAGE_BOOKKEEP);
dma_fence_put(replacement);
return 0;
}
@@ -1391,8 +1391,9 @@ static int init_kfd_vm(struct amdgpu_vm *vm,
void **process_info,
ret = dma_resv_reserve_fences(vm->root.bo->tbo.base.resv, 1);
if (ret)
goto reserve_shared_fail;
- amdgpu_bo_fence(vm->root.bo,
- &vm->process_info->eviction_fence->base, true);
+ dma_resv_add_fence(vm->root.bo->tbo.base.resv,
+ &vm->process_info->eviction_fence->base,
+ DMA_RESV_USAGE_BOOKKEEP);
amdgpu_bo_unreserve(vm->root.bo);
/* Update process info */
@@ -1989,9 +1990,9 @@ int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
}
if (!amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) &&
!bo->tbo.pin_count)
- amdgpu_bo_fence(bo,
- &avm->process_info->eviction_fence->base,
- true);
+ dma_resv_add_fence(bo->tbo.base.resv,
+ &avm->process_info->eviction_fence->base,
+ DMA_RESV_USAGE_BOOKKEEP);
This removes the implicit dma_resv_reserve_fences that amdgpu_bo_fence
used to do. Do we need to add back an explicit dma_resv_reserve_fences
somewhere here?
I was pondering the same thought. The extra reserve in amdgpu_bo_fence()
is actually just a workaround. So when this here goes boom we really
need to fix it in the KFD code.
ret = unreserve_bo_and_vms(&ctx, false, false);
goto out;
@@ -2760,15 +2761,18 @@ int
amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence
**ef)
if (mem->bo->tbo.pin_count)
continue;
- amdgpu_bo_fence(mem->bo,
- &process_info->eviction_fence->base, true);
+ dma_resv_add_fence(mem->bo->tbo.base.resv,
+ &process_info->eviction_fence->base,
+ DMA_RESV_USAGE_BOOKKEEP);
Same as above.
}
/* Attach eviction fence to PD / PT BOs */
list_for_each_entry(peer_vm, &process_info->vm_list_head,
vm_list_node) {
struct amdgpu_bo *bo = peer_vm->root.bo;
- amdgpu_bo_fence(bo, &process_info->eviction_fence->base,
true);
+ dma_resv_add_fence(bo->tbo.base.resv,
+ &process_info->eviction_fence->base,
+ DMA_RESV_USAGE_BOOKKEEP);
Same as above.
}
validate_map_fail:
@@ -2822,7 +2826,9 @@ int amdgpu_amdkfd_add_gws_to_process(void
*info, void *gws, struct kgd_mem **mem
ret = dma_resv_reserve_fences(gws_bo->tbo.base.resv, 1);
if (ret)
goto reserve_shared_fail;
- amdgpu_bo_fence(gws_bo, &process_info->eviction_fence->base, true);
+ dma_resv_add_fence(gws_bo->tbo.base.resv,
+ &process_info->eviction_fence->base,
+ DMA_RESV_USAGE_BOOKKEEP);
amdgpu_bo_unreserve(gws_bo);
mutex_unlock(&(*mem)->process_info->lock);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
index 1fd3cbca20a2..03ec099d64e0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
@@ -112,7 +112,8 @@ static int amdgpu_vm_sdma_commit(struct
amdgpu_vm_update_params *p,
swap(p->vm->last_unlocked, tmp);
dma_fence_put(tmp);
} else {
- amdgpu_bo_fence(p->vm->root.bo, f, true);
+ dma_resv_add_fence(p->vm->root.bo->tbo.base.resv, f,
+ DMA_RESV_USAGE_BOOKKEEP);
Same as above.
This one here should certainly have an associated dma_fence_reserve_fence().
Regards,
Christian.
Regards,
Felix
}
if (fence && !p->immediate)
Re: [PATCH 1/3] drm/amdgpu: move nbio ih_doorbell_range() into ih code for vega
On 9/13/2022 8:18 PM, Alex Deucher wrote:
This mirrors what we do for other asics and this way we are
sure the ih doorbell range is properly initialized.
There is a comment about the way doorbells on gfx9 work that
requires that they are initialized for other IPs before GFX
is initialized. In this case IH is initialized before GFX,
so there should be no issue.
Not sure about the association of patch 1 and 2 with AER as in the
comment below. I thought the access would go through (PCIE errors may
not be reported) and the only side effect is doorbell won't be hit/routed.
The comments may not be relevant to patches 1/2, apart from that -
Series is:
Reviewed-by: Lijo Lazar
Thanks,
Lijo
This fixes the Unsupported Request error reported through
AER during driver load. The error happens as a write happens
to the remap offset before real remapping is done.
Link: https://bugzilla.kernel.org/show_bug.cgi?id=216373
The error was unnoticed before and got visible because of the commit
referenced below. This doesn't fix anything in the commit below, rather
fixes the issue in amdgpu exposed by the commit. The reference is only
to associate this commit with below one so that both go together.
Fixes: 8795e182b02d ("PCI/portdrv: Don't disable AER reporting in
get_port_device_capability()")
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 3 ---
drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 4
drivers/gpu/drm/amd/amdgpu/vega20_ih.c | 4
3 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 5188da87428d..e6a4002fa67d 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -1224,9 +1224,6 @@ static void soc15_doorbell_range_init(struct
amdgpu_device *adev)
ring->use_doorbell, ring->doorbell_index,
adev->doorbell_index.sdma_doorbell_range);
}
-
- adev->nbio.funcs->ih_doorbell_range(adev,
adev->irq.ih.use_doorbell,
- adev->irq.ih.doorbell_index);
}
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
index 03b7066471f9..1e83db0c5438 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
@@ -289,6 +289,10 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev)
}
}
+ if (!amdgpu_sriov_vf(adev))
+ adev->nbio.funcs->ih_doorbell_range(adev,
adev->irq.ih.use_doorbell,
+
adev->irq.ih.doorbell_index);
+
pci_set_master(adev->pdev);
/* enable interrupts */
diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
index 2022ffbb8dba..59dfca093155 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
@@ -340,6 +340,10 @@ static int vega20_ih_irq_init(struct amdgpu_device *adev)
}
}
+ if (!amdgpu_sriov_vf(adev))
+ adev->nbio.funcs->ih_doorbell_range(adev,
adev->irq.ih.use_doorbell,
+
adev->irq.ih.doorbell_index);
+
pci_set_master(adev->pdev);
/* enable interrupts */
