[PATCH] drm/amd/pm: Enable bad memory page/channel recording support for smu v13_0_0

[Candice Li]

Send message to SMU to update bad memory page and bad channel info.

Signed-off-by: Candice Li 
Reviewed-by: Evan Quan 
---
 .../pm/swsmu/inc/pmfw_if/smu_v13_0_0_ppsmc.h  |  8 +++-
 drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h  |  4 +-
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c  | 39 +++
 3 files changed, 49 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_0_ppsmc.h 
b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_0_ppsmc.h
index 9ebb8f39732a0e..8b8266890a1002 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_0_ppsmc.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_0_ppsmc.h
@@ -131,7 +131,13 @@
 #define PPSMC_MSG_EnableAudioStutterWA   0x44
 #define PPSMC_MSG_PowerUpUmsch   0x45
 #define PPSMC_MSG_PowerDownUmsch 0x46
-#define PPSMC_Message_Count  0x47
+#define PPSMC_MSG_SetDcsArch 0x47
+#define PPSMC_MSG_TriggerVFFLR   0x48
+#define PPSMC_MSG_SetNumBadMemoryPagesRetired0x49
+#define PPSMC_MSG_SetBadMemoryPagesRetiredFlagsPerChannel 0x4A
+#define PPSMC_MSG_SetPriorityDeltaGain   0x4B
+#define PPSMC_MSG_AllowIHHostInterrupt   0x4C
+#define PPSMC_Message_Count  0x4D
 
 //Debug Dump Message
 #define DEBUGSMC_MSG_TestMessage0x1
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h 
b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
index 58098b82df660c..a4e3425b1027c2 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
@@ -239,7 +239,9 @@
__SMU_DUMMY_MAP(DriverMode2Reset), \
__SMU_DUMMY_MAP(GetGfxOffStatus),\
__SMU_DUMMY_MAP(GetGfxOffEntryCount),\
-   __SMU_DUMMY_MAP(LogGfxOffResidency),
+   __SMU_DUMMY_MAP(LogGfxOffResidency),\
+   __SMU_DUMMY_MAP(SetNumBadMemoryPagesRetired),   \
+   __SMU_DUMMY_MAP(SetBadMemoryPagesRetiredFlagsPerChannel),
 
 #undef __SMU_DUMMY_MAP
 #define __SMU_DUMMY_MAP(type)  SMU_MSG_##type
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index 5bcb61f77e4193..87d7c66e49ef28 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -141,6 +141,9 @@ static struct cmn2asic_msg_mapping 
smu_v13_0_0_message_map[SMU_MSG_MAX_COUNT] =
MSG_MAP(PrepareMp1ForUnload,PPSMC_MSG_PrepareMp1ForUnload,  
   0),
MSG_MAP(DFCstateControl,
PPSMC_MSG_SetExternalClientDfCstateAllow, 0),
MSG_MAP(ArmD3,  PPSMC_MSG_ArmD3,
   0),
+   MSG_MAP(SetNumBadMemoryPagesRetired,
PPSMC_MSG_SetNumBadMemoryPagesRetired,   0),
+   MSG_MAP(SetBadMemoryPagesRetiredFlagsPerChannel,
+   PPSMC_MSG_SetBadMemoryPagesRetiredFlagsPerChannel,  
 0),
 };
 
 static struct cmn2asic_mapping smu_v13_0_0_clk_map[SMU_CLK_COUNT] = {
@@ -1838,6 +1841,40 @@ static void smu_v13_0_0_set_smu_mailbox_registers(struct 
smu_context *smu)
smu->debug_resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_54);
 }
 
+static int smu_v13_0_0_smu_send_bad_mem_page_num(struct smu_context *smu,
+   uint32_t size)
+{
+   int ret = 0;
+
+   /* message SMU to update the bad page number on SMUBUS */
+   ret = smu_cmn_send_smc_msg_with_param(smu,
+ SMU_MSG_SetNumBadMemoryPagesRetired,
+ size, NULL);
+   if (ret)
+   dev_err(smu->adev->dev,
+ "[%s] failed to message SMU to update bad memory 
pages number\n",
+ __func__);
+
+   return ret;
+}
+
+static int smu_v13_0_0_send_bad_mem_channel_flag(struct smu_context *smu,
+   uint32_t size)
+{
+   int ret = 0;
+
+   /* message SMU to update the bad channel info on SMUBUS */
+   ret = smu_cmn_send_smc_msg_with_param(smu,
+ 
SMU_MSG_SetBadMemoryPagesRetiredFlagsPerChannel,
+ size, NULL);
+   if (ret)
+   dev_err(smu->adev->dev,
+ "[%s] failed to message SMU to update bad memory 
pages channel info\n",
+ __func__);
+
+   return ret;
+}
+
 static const struct pptable_funcs smu_v13_0_0_ppt_funcs = {
.get_allowed_feature_mask = smu_v13_0_0_get_allowed_feature_mask,
.set_default_dpm_table = smu_v13_0_0_set_default_dpm_table,
@@ -1908,6 +1945,8 @@ static const struct pptable_funcs smu_v13_0_0_ppt_funcs = 
{
.mode1_reset = smu_v13_0_0_mode1_reset,
.set_mp1_state = smu_v13_0_0_set_mp1_state,
.set_df_cstate = smu_v13_0_0_set_df_cstate,
+   .send_hbm_bad_pages_num = 

[PATCH AUTOSEL 5.15 24/27] Revert "drm/amdgpu: Revert "drm/amdgpu: getting fan speed pwm for vega10 properly""

[Sasha Levin]

From: Asher Song 

[ Upstream commit 30b8e7b8ee3be003e0df85c857c5cd0e0bd58b82 ]

This reverts commit 4545ae2ed3f2f7c3f615a53399c9c8460ee5bca7.

The origin patch "drm/amdgpu: getting fan speed pwm for vega10 properly" works 
fine.
Test failure is caused by test case self.

Signed-off-by: Asher Song 
Reviewed-by: Guchun Chen 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 .../amd/pm/powerplay/hwmgr/vega10_thermal.c   | 25 +--
 1 file changed, 12 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c 
b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c
index dad3e3741a4e..190af79f3236 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c
@@ -67,22 +67,21 @@ int vega10_fan_ctrl_get_fan_speed_info(struct pp_hwmgr 
*hwmgr,
 int vega10_fan_ctrl_get_fan_speed_pwm(struct pp_hwmgr *hwmgr,
uint32_t *speed)
 {
-   uint32_t current_rpm;
-   uint32_t percent = 0;
-
-   if (hwmgr->thermal_controller.fanInfo.bNoFan)
-   return 0;
+   struct amdgpu_device *adev = hwmgr->adev;
+   uint32_t duty100, duty;
+   uint64_t tmp64;
 
-   if (vega10_get_current_rpm(hwmgr, _rpm))
-   return -1;
+   duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
+   CG_FDO_CTRL1, FMAX_DUTY100);
+   duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS),
+   CG_THERMAL_STATUS, FDO_PWM_DUTY);
 
-   if (hwmgr->thermal_controller.
-   advanceFanControlParameters.usMaxFanRPM != 0)
-   percent = current_rpm * 255 /
-   hwmgr->thermal_controller.
-   advanceFanControlParameters.usMaxFanRPM;
+   if (!duty100)
+   return -EINVAL;
 
-   *speed = MIN(percent, 255);
+   tmp64 = (uint64_t)duty * 255;
+   do_div(tmp64, duty100);
+   *speed = MIN((uint32_t)tmp64, 255);
 
return 0;
 }
-- 
2.35.1

[PATCH AUTOSEL 6.0 40/44] drm/amd/display: only fill dirty rectangles when PSR is enabled

[Sasha Levin]

From: Hamza Mahfooz 

[ Upstream commit 675d84621a24490e1de3d59a4992a17fa9ff92b5 ]

Currently, we are calling fill_dc_dirty_rects() even if PSR isn't
supported by the relevant link in amdgpu_dm_commit_planes(), this is
undesirable especially because when drm.debug is enabled we are printing
messages in fill_dc_dirty_rects() that are only useful for debugging PSR
(and confusing otherwise). So, we can instead limit the filling of dirty
rectangles to only when PSR is enabled.

Reviewed-by: Leo Li 
Signed-off-by: Hamza Mahfooz 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 3be70848b202..aaf7e4b22ed0 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -7639,9 +7639,10 @@ static void amdgpu_dm_commit_planes(struct 
drm_atomic_state *state,
bundle->surface_updates[planes_count].plane_info =
>plane_infos[planes_count];
 
-   fill_dc_dirty_rects(plane, old_plane_state, new_plane_state,
-   new_crtc_state,
-   >flip_addrs[planes_count]);
+   if (acrtc_state->stream->link->psr_settings.psr_feature_enabled)
+   fill_dc_dirty_rects(plane, old_plane_state,
+   new_plane_state, new_crtc_state,
+   >flip_addrs[planes_count]);
 
/*
 * Only allow immediate flips for fast updates that don't
-- 
2.35.1

[PATCH AUTOSEL 6.0 39/44] drm/amdgpu: Drop eviction lock when allocating PT BO

[Sasha Levin]

From: Philip Yang 

[ Upstream commit e034a0d9aaee5c9129d5dfdfdfcab988a953412d ]

Re-take the eviction lock immediately again after the allocation is
completed, to fix circular locking warning with drm_buddy allocator.

Move amdgpu_vm_eviction_lock/unlock/trylock to amdgpu_vm.h as they are
called from multiple files.

Signed-off-by: Philip Yang 
Reviewed-by: Christian König 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c| 26 ---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h| 26 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c |  2 ++
 3 files changed, 28 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 04130f8813ef..369c0d03e3c6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -143,32 +143,6 @@ int amdgpu_vm_set_pasid(struct amdgpu_device *adev, struct 
amdgpu_vm *vm,
return 0;
 }
 
-/*
- * vm eviction_lock can be taken in MMU notifiers. Make sure no reclaim-FS
- * happens while holding this lock anywhere to prevent deadlocks when
- * an MMU notifier runs in reclaim-FS context.
- */
-static inline void amdgpu_vm_eviction_lock(struct amdgpu_vm *vm)
-{
-   mutex_lock(>eviction_lock);
-   vm->saved_flags = memalloc_noreclaim_save();
-}
-
-static inline int amdgpu_vm_eviction_trylock(struct amdgpu_vm *vm)
-{
-   if (mutex_trylock(>eviction_lock)) {
-   vm->saved_flags = memalloc_noreclaim_save();
-   return 1;
-   }
-   return 0;
-}
-
-static inline void amdgpu_vm_eviction_unlock(struct amdgpu_vm *vm)
-{
-   memalloc_noreclaim_restore(vm->saved_flags);
-   mutex_unlock(>eviction_lock);
-}
-
 /**
  * amdgpu_vm_bo_evicted - vm_bo is evicted
  *
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 9ecb7f663e19..1f3599363481 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -488,4 +488,30 @@ static inline uint64_t amdgpu_vm_tlb_seq(struct amdgpu_vm 
*vm)
return atomic64_read(>tlb_seq);
 }
 
+/*
+ * vm eviction_lock can be taken in MMU notifiers. Make sure no reclaim-FS
+ * happens while holding this lock anywhere to prevent deadlocks when
+ * an MMU notifier runs in reclaim-FS context.
+ */
+static inline void amdgpu_vm_eviction_lock(struct amdgpu_vm *vm)
+{
+   mutex_lock(>eviction_lock);
+   vm->saved_flags = memalloc_noreclaim_save();
+}
+
+static inline bool amdgpu_vm_eviction_trylock(struct amdgpu_vm *vm)
+{
+   if (mutex_trylock(>eviction_lock)) {
+   vm->saved_flags = memalloc_noreclaim_save();
+   return true;
+   }
+   return false;
+}
+
+static inline void amdgpu_vm_eviction_unlock(struct amdgpu_vm *vm)
+{
+   memalloc_noreclaim_restore(vm->saved_flags);
+   mutex_unlock(>eviction_lock);
+}
+
 #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
index 88de9f0d4728..983899574464 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
@@ -597,7 +597,9 @@ static int amdgpu_vm_pt_alloc(struct amdgpu_device *adev,
if (entry->bo)
return 0;
 
+   amdgpu_vm_eviction_unlock(vm);
r = amdgpu_vm_pt_create(adev, vm, cursor->level, immediate, );
+   amdgpu_vm_eviction_lock(vm);
if (r)
return r;
 
-- 
2.35.1

[PATCH AUTOSEL 6.0 38/44] drm/amdgpu: Unlock bo_list_mutex after error handling

[Sasha Levin]

From: Philip Yang 

[ Upstream commit 64f65135c41a75f933d3bca236417ad8e9eb75de ]

Get below kernel WARNING backtrace when pressing ctrl-C to kill kfdtest
application.

If amdgpu_cs_parser_bos returns error after taking bo_list_mutex, as
caller amdgpu_cs_ioctl will not unlock bo_list_mutex, this generates the
kernel WARNING.

Add unlock bo_list_mutex after amdgpu_cs_parser_bos error handling to
cleanup bo_list userptr bo.

 WARNING: kfdtest/2930 still has locks held!
 1 lock held by kfdtest/2930:
  (>bo_list_mutex){+.+.}-{3:3}, at: amdgpu_cs_ioctl+0xce5/0x1f10 [amdgpu]
  stack backtrace:
   dump_stack_lvl+0x44/0x57
   get_signal+0x79f/0xd00
   arch_do_signal_or_restart+0x36/0x7b0
   exit_to_user_mode_prepare+0xfd/0x1b0
   syscall_exit_to_user_mode+0x19/0x40
   do_syscall_64+0x40/0x80

Signed-off-by: Philip Yang 
Reviewed-by: Christian König 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index b7bae833c804..9d59f83c8faa 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -655,6 +655,7 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
}
mutex_unlock(>bo_list->bo_list_mutex);
}
+   mutex_unlock(>bo_list->bo_list_mutex);
return r;
 }
 
-- 
2.35.1

[PATCH AUTOSEL 6.0 37/44] Revert "drm/amdgpu: Revert "drm/amdgpu: getting fan speed pwm for vega10 properly""

[Sasha Levin]

From: Asher Song 

[ Upstream commit 30b8e7b8ee3be003e0df85c857c5cd0e0bd58b82 ]

This reverts commit 4545ae2ed3f2f7c3f615a53399c9c8460ee5bca7.

The origin patch "drm/amdgpu: getting fan speed pwm for vega10 properly" works 
fine.
Test failure is caused by test case self.

Signed-off-by: Asher Song 
Reviewed-by: Guchun Chen 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 .../amd/pm/powerplay/hwmgr/vega10_thermal.c   | 25 +--
 1 file changed, 12 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c 
b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c
index dad3e3741a4e..190af79f3236 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c
@@ -67,22 +67,21 @@ int vega10_fan_ctrl_get_fan_speed_info(struct pp_hwmgr 
*hwmgr,
 int vega10_fan_ctrl_get_fan_speed_pwm(struct pp_hwmgr *hwmgr,
uint32_t *speed)
 {
-   uint32_t current_rpm;
-   uint32_t percent = 0;
-
-   if (hwmgr->thermal_controller.fanInfo.bNoFan)
-   return 0;
+   struct amdgpu_device *adev = hwmgr->adev;
+   uint32_t duty100, duty;
+   uint64_t tmp64;
 
-   if (vega10_get_current_rpm(hwmgr, _rpm))
-   return -1;
+   duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
+   CG_FDO_CTRL1, FMAX_DUTY100);
+   duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS),
+   CG_THERMAL_STATUS, FDO_PWM_DUTY);
 
-   if (hwmgr->thermal_controller.
-   advanceFanControlParameters.usMaxFanRPM != 0)
-   percent = current_rpm * 255 /
-   hwmgr->thermal_controller.
-   advanceFanControlParameters.usMaxFanRPM;
+   if (!duty100)
+   return -EINVAL;
 
-   *speed = MIN(percent, 255);
+   tmp64 = (uint64_t)duty * 255;
+   do_div(tmp64, duty100);
+   *speed = MIN((uint32_t)tmp64, 255);
 
return 0;
 }
-- 
2.35.1

[PATCH AUTOSEL 6.0 36/44] drm/amd/display: Fix gpio port mapping issue

[Sasha Levin]

From: Steve Su 

[ Upstream commit c0b2753f5db281b07013899c79b5f06a614055f9 ]

[Why]
1. Port of gpio has different mapping.

[How]
1. Add a dummy entry in mapping table.
2. Fix incorrect mask bit field access.

Reviewed-by: Alvin Lee 
Acked-by: Alan Liu 
Signed-off-by: Steve Su 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 .../amd/display/dc/gpio/dcn32/hw_factory_dcn32.c   | 14 ++
 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c   |  9 ++---
 2 files changed, 20 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c 
b/drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c
index d635b73af46f..0ea52ba5ac82 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c
@@ -107,6 +107,13 @@ static const struct ddc_registers ddc_data_regs_dcn[] = {
ddc_data_regs_dcn2(3),
ddc_data_regs_dcn2(4),
ddc_data_regs_dcn2(5),
+   {
+   // add a dummy entry for cases no such port
+   {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,},
+   .ddc_setup = 0,
+   .phy_aux_cntl = 0,
+   .dc_gpio_aux_ctrl_5 = 0
+   },
{
DDC_GPIO_VGA_REG_LIST(DATA),
.ddc_setup = 0,
@@ -121,6 +128,13 @@ static const struct ddc_registers ddc_clk_regs_dcn[] = {
ddc_clk_regs_dcn2(3),
ddc_clk_regs_dcn2(4),
ddc_clk_regs_dcn2(5),
+   {
+   // add a dummy entry for cases no such port
+   {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,},
+   .ddc_setup = 0,
+   .phy_aux_cntl = 0,
+   .dc_gpio_aux_ctrl_5 = 0
+   },
{
DDC_GPIO_VGA_REG_LIST(CLK),
.ddc_setup = 0,
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c 
b/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c
index 6fd38cdd68c0..525bc8881950 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c
@@ -94,11 +94,14 @@ static enum gpio_result set_config(
 * is required for detection of AUX mode */
if (hw_gpio->base.en != GPIO_DDC_LINE_VIP_PAD) {
if (!ddc_data_pd_en || !ddc_clk_pd_en) {
-
-   REG_SET_2(gpio.MASK_reg, regval,
+   if (hw_gpio->base.en == GPIO_DDC_LINE_DDC_VGA) {
+   // bit 4 of mask has different usage in 
some cases
+   REG_SET(gpio.MASK_reg, regval, 
DC_GPIO_DDC1DATA_PD_EN, 1);
+   } else {
+   REG_SET_2(gpio.MASK_reg, regval,
DC_GPIO_DDC1DATA_PD_EN, 1,
DC_GPIO_DDC1CLK_PD_EN, 1);
-
+   }
if (config_data->type ==

GPIO_CONFIG_TYPE_I2C_AUX_DUAL_MODE)
msleep(3);
-- 
2.35.1

[PATCH AUTOSEL 6.0 35/44] drm/amd/display: Fix FCLK deviation and tool compile issues

[Sasha Levin]

From: Chaitanya Dhere 

[ Upstream commit 0d5c5c210a4d4e655feb93b379647f0b179cdafe ]

[Why]
Recent backports from open source do not have header inclusion pattern
that is consistent with inclusion style in the rest of the file. This
breaks the internal tool builds as well. A recent commit erronously
modified the original DML formula for calculating
ActiveClockChangeLatencyHidingY. This resulted in a FCLK deviation
from the golden values.

[How]
Change the way in which display_mode_vba.h is included so that it is
consistent with the inclusion style in rest of the file which also fixes
the tool build. Restore the DML formula to its original state to fix the
FCLK deviation.

Reviewed-by: Aurabindo Pillai 
Reviewed-by: Jun Lei 
Acked-by: Alan Liu 
Signed-off-by: Chaitanya Dhere 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 .../gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c | 2 +-
 .../gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git 
a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
index 365d290bba99..d0f3f2414fb8 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
@@ -4396,7 +4396,7 @@ void 
dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport(
 
if (v->NumberOfActiveSurfaces > 1) {
ActiveClockChangeLatencyHidingY = 
ActiveClockChangeLatencyHidingY
-   - (1 - 1 / v->NumberOfActiveSurfaces) * 
SwathHeightY[k] * v->HTotal[k]
+   - (1.0 - 1.0 / 
v->NumberOfActiveSurfaces) * SwathHeightY[k] * v->HTotal[k]
/ v->PixelClock[k] / 
v->VRatio[k];
}
 
diff --git 
a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h 
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
index 0b427d89b3c5..f174f5c5ff92 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
@@ -30,7 +30,7 @@
 #include "os_types.h"
 #include "../dc_features.h"
 #include "../display_mode_structs.h"
-#include "dml/display_mode_vba.h"
+#include "../display_mode_vba.h"
 
 unsigned int dml32_dscceComputeDelay(
unsigned int bpc,
-- 
2.35.1

[PATCH AUTOSEL 6.0 34/44] drm/amd/display: Zeromem mypipe heap struct before using it

[Sasha Levin]

From: Aurabindo Pillai 

[ Upstream commit ab4b35008db9b7ae747679250e5c26d7c3a90cea ]

[Why]
Bug was caused when moving variable from stack to heap because it was reusable
and garbage was left over, so we need to zero mem.

Reviewed-by: Martin Leung 
Acked-by: Alan Liu 
Signed-off-by: Aurabindo Pillai 
Signed-off-by: Martin Leung 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
index 52525833a99b..96714dc6b695 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
@@ -3194,6 +3194,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct 
display_mode_lib *mode_l

mode_lib->vba.FCLKChangeLatency, mode_lib->vba.UrgLatency[i],

mode_lib->vba.SREnterPlusExitTime);
 
+   
memset(>dummy_vars.dml32_ModeSupportAndSystemConfigurationFull, 0, 
sizeof(DmlPipe));

v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.Dppclk = 
mode_lib->vba.RequiredDPPCLK[i][j][k];

v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.Dispclk = 
mode_lib->vba.RequiredDISPCLK[i][j];

v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.PixelClock = 
mode_lib->vba.PixelClock[k];
-- 
2.35.1

[PATCH AUTOSEL 6.0 27/44] drm/amdgpu: Fix the lpfn checking condition in drm buddy

[Sasha Levin]

From: Ma Jun 

[ Upstream commit e0b26b9482461e9528552f54fa662c2269f75b3f ]

Because the value of man->size is changed during suspend/resume process,
use mgr->mm.size instead of man->size here for lpfn checking.

Signed-off-by: Ma Jun 
Suggested-by: Christian König 
Link: 
https://patchwork.freedesktop.org/patch/msgid/20220914125331.2467162-1-jun@amd.com
Signed-off-by: Christian König 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
index 28ec5f8ac1c1..27159f1d112e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
@@ -435,7 +435,7 @@ static int amdgpu_vram_mgr_new(struct ttm_resource_manager 
*man,
if (place->flags & TTM_PL_FLAG_TOPDOWN)
vres->flags |= DRM_BUDDY_TOPDOWN_ALLOCATION;
 
-   if (fpfn || lpfn != man->size)
+   if (fpfn || lpfn != mgr->mm.size)
/* Allocate blocks in desired range */
vres->flags |= DRM_BUDDY_RANGE_ALLOCATION;
 
-- 
2.35.1

Re: [PATCH 22/22] SWDEV-1 - dc: 3.2.213

[Chang, Brian]

[AMD Official Use Only - General]

Ok

Get Outlook for Android

From: Alex Deucher 
Sent: Saturday, November 19, 2022 4:12:38 AM
To: Chang, Brian 
Cc: amd-gfx@lists.freedesktop.org ; Wang, 
Chao-kai (Stylon) ; Cyr, Aric ; Li, Sun 
peng (Leo) ; Wentland, Harry ; 
Zhuo, Qingqing (Lillian) ; Siqueira, Rodrigo 
; Li, Roman ; Chiu, Solomon 
; Pillai, Aurabindo ; Lin, 
Wayne ; Lakha, Bhawanpreet ; 
Gutierrez, Agustin ; Kotarac, Pavle 

Subject: Re: [PATCH 22/22] SWDEV-1 - dc: 3.2.213

Please fix the subject.  E.g., drm/amd/display: dc: 3.2.213
or something like that.

On Fri, Nov 18, 2022 at 12:02 PM brichang  wrote:
>
> From: Aric Cyr 
>
> Signed-off-by: Aric Cyr 
>
> This version brings along following fixes:
> -Add configuration 2 for ABM 2.3/2.4.
> -Add margin for HUBP for SubVp + DRR.
> -Fix no display after resume from WB/CB.
> -Limit HW cursor size to be less than 64 x 64 bytes when the stream is >= 4K.
> -Lower watermarks for enter/enter+exit latency.
> -Update support types for DCN314 to include z8 only and z8_z10 only state.
> -Add new value for soc bounding box and dummy pstate.
> -Override fclk chang latency when calculating prefetch schedule for subvp 
> with low uclk.
> -Add check for DET fetch latency for dcn32.
> -Add check if PSR enabled when entering MALL.
> -Use base MALL allocation size calculations off vewport height.
> -Add YCBCR2020 to CSC matrix.
> -Implement DP-Tx portion to interact with DPIA.
> -Add debug option for increasing phantom lines.
> -Fix phantom plane/stream retain after fail validation.
> -Fix display corruption with VSR enable.
> -Set valid divider value for virtual and FRL/DP2.
> -Add new num clk levels struct for max mclk index.
> -Fix check for phantom BPP.
> -Fix rotated cursor offset calculation.
> ---
>  drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
> b/drivers/gpu/drm/amd/display/dc/dc.h
> index e827cee94e5e..feb7a7f2734e 100644
> --- a/drivers/gpu/drm/amd/display/dc/dc.h
> +++ b/drivers/gpu/drm/amd/display/dc/dc.h
> @@ -47,7 +47,7 @@ struct aux_payload;
>  struct set_config_cmd_payload;
>  struct dmub_notification;
>
> -#define DC_VER "3.2.212"
> +#define DC_VER "3.2.213"
>
>  #define MAX_SURFACES 3
>  #define MAX_PLANES 6
> --
> 2.25.1
>

[PATCH 3/6] drm/amdkfd: Improve amdgpu_vm_handle_moved

[Felix Kuehling]

Let amdgpu_vm_handle_moved update all BO VA mappings of BOs reserved by
the caller. This will be useful for handling extra BO VA mappings in
KFD VMs that are managed through the render node API.

Signed-off-by: Felix Kuehling 
Reviewed-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c  |  6 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c  | 18 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h  |  3 ++-
 4 files changed, 21 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 275da612cd87..a80d2557edb2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -1121,6 +1121,10 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser 
*p)
return r;
}
 
+   /* TODO: Is this loop still needed, or could this be handled by
+* amdgpu_vm_handle_moved, now that it can handle all BOs that are
+* reserved under p->ticket?
+*/
amdgpu_bo_list_for_each_entry(e, p->bo_list) {
/* ignore duplicates */
bo = ttm_to_amdgpu_bo(e->tv.bo);
@@ -1140,7 +1144,7 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser 
*p)
return r;
}
 
-   r = amdgpu_vm_handle_moved(adev, vm);
+   r = amdgpu_vm_handle_moved(adev, vm, >ticket);
if (r)
return r;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
index 271e30e34d93..23a213e4ab2c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
@@ -404,7 +404,7 @@ amdgpu_dma_buf_move_notify(struct dma_buf_attachment 
*attach)
 
r = amdgpu_vm_clear_freed(adev, vm, NULL);
if (!r)
-   r = amdgpu_vm_handle_moved(adev, vm);
+   r = amdgpu_vm_handle_moved(adev, vm, ticket);
 
if (r && r != -EBUSY)
DRM_ERROR("Failed to invalidate VM page tables (%d))\n",
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 003aa9e47085..b61eb2e575d1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1278,11 +1278,12 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
  * PTs have to be reserved!
  */
 int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
-  struct amdgpu_vm *vm)
+  struct amdgpu_vm *vm,
+  struct ww_acquire_ctx *ticket)
 {
struct amdgpu_bo_va *bo_va;
struct dma_resv *resv;
-   bool clear;
+   bool clear, unlock;
int r;
 
spin_lock(>status_lock);
@@ -1305,17 +1306,24 @@ int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
spin_unlock(>status_lock);
 
/* Try to reserve the BO to avoid clearing its ptes */
-   if (!amdgpu_vm_debug && dma_resv_trylock(resv))
+   if (!amdgpu_vm_debug && dma_resv_trylock(resv)) {
clear = false;
+   unlock = true;
+   /* The caller is already holding the reservation lock */
+   } else if (ticket && dma_resv_locking_ctx(resv) == ticket) {
+   clear = false;
+   unlock = false;
/* Somebody else is using the BO right now */
-   else
+   } else {
clear = true;
+   unlock = false;
+   }
 
r = amdgpu_vm_bo_update(adev, bo_va, clear);
if (r)
return r;
 
-   if (!clear)
+   if (unlock)
dma_resv_unlock(resv);
spin_lock(>status_lock);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 6546e786bf00..53d1ac4b69db 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -404,7 +404,8 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
  struct amdgpu_vm *vm,
  struct dma_fence **fence);
 int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
-  struct amdgpu_vm *vm);
+  struct amdgpu_vm *vm,
+  struct ww_acquire_ctx *ticket);
 void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base,
struct amdgpu_vm *vm, struct amdgpu_bo *bo);
 int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm,
-- 
2.32.0

[PATCH 4/6] drm/amdgpu: Attach eviction fence on alloc

[Felix Kuehling]

Instead of attaching the eviction fence when a KFD BO is first mapped,
attach it when it is allocated or imported. This in preparation to allow
KFD BOs to be mapped using the render node API.

Signed-off-by: Felix Kuehling 
---
 .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c  | 63 ++-
 1 file changed, 32 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index bd36636a9596..e13dff75ca5c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -360,6 +360,24 @@ static int amdgpu_amdkfd_bo_validate(struct amdgpu_bo *bo, 
uint32_t domain,
return ret;
 }
 
+static int amdgpu_amdkfd_bo_validate_and_fence(struct amdgpu_bo *bo,
+  uint32_t domain,
+  struct dma_fence *fence)
+{
+   int ret = amdgpu_bo_reserve(bo, false);
+
+   if (ret)
+   return ret;
+
+   ret = amdgpu_amdkfd_bo_validate(bo, domain, true);
+   if (!ret)
+   dma_resv_add_fence(bo->tbo.base.resv, fence,
+  DMA_RESV_USAGE_BOOKKEEP);
+   amdgpu_bo_unreserve(bo);
+
+   return ret;
+}
+
 static int amdgpu_amdkfd_validate_vm_bo(void *_unused, struct amdgpu_bo *bo)
 {
return amdgpu_amdkfd_bo_validate(bo, bo->allowed_domains, false);
@@ -1709,6 +1727,11 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
}
bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;
+   } else {
+   ret = amdgpu_amdkfd_bo_validate_and_fence(bo, domain,
+   >process_info->eviction_fence->base);
+   if (ret)
+   goto err_validate_bo;
}
 
if (offset)
@@ -1718,6 +1741,7 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
 
 allocate_init_user_pages_failed:
 err_pin_bo:
+err_validate_bo:
remove_kgd_mem_from_kfd_bo_list(*mem, avm->process_info);
drm_vma_node_revoke(>vma_node, drm_priv);
 err_node_allow:
@@ -1788,10 +1812,6 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
if (unlikely(ret))
return ret;
 
-   /* The eviction fence should be removed by the last unmap.
-* TODO: Log an error condition if the bo still has the eviction fence
-* attached
-*/
amdgpu_amdkfd_remove_eviction_fence(mem->bo,
process_info->eviction_fence);
pr_debug("Release VA 0x%llx - 0x%llx\n", mem->va,
@@ -1905,19 +1925,6 @@ int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
if (unlikely(ret))
goto out_unreserve;
 
-   if (mem->mapped_to_gpu_memory == 0 &&
-   !amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
-   /* Validate BO only once. The eviction fence gets added to BO
-* the first time it is mapped. Validate will wait for all
-* background evictions to complete.
-*/
-   ret = amdgpu_amdkfd_bo_validate(bo, domain, true);
-   if (ret) {
-   pr_debug("Validate failed\n");
-   goto out_unreserve;
-   }
-   }
-
list_for_each_entry(entry, >attachments, list) {
if (entry->bo_va->base.vm != avm || entry->is_mapped)
continue;
@@ -1944,10 +1951,6 @@ int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
 mem->mapped_to_gpu_memory);
}
 
-   if (!amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) && !bo->tbo.pin_count)
-   dma_resv_add_fence(bo->tbo.base.resv,
-  >process_info->eviction_fence->base,
-  DMA_RESV_USAGE_BOOKKEEP);
ret = unreserve_bo_and_vms(, false, false);
 
goto out;
@@ -1964,7 +1967,6 @@ int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(
struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv)
 {
struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
-   struct amdkfd_process_info *process_info = avm->process_info;
unsigned long bo_size = mem->bo->tbo.base.size;
struct kfd_mem_attachment *entry;
struct bo_vm_reservation_context ctx;
@@ -2005,15 +2007,6 @@ int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(
 mem->mapped_to_gpu_memory);
}
 
-   /* If BO is unmapped from all VMs, unfence it. It can be evicted if
-* required.
-*/
-   if (mem->mapped_to_gpu_memory == 0 &&
-   !amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm) &&
-   !mem->bo->tbo.pin_count)
-   amdgpu_amdkfd_remove_eviction_fence(mem->bo,
-   process_info->eviction_fence);
-
 unreserve_out:
unreserve_bo_and_vms(, false, 

[PATCH 6/6] drm/amdgpu: Do bo_va ref counting for KFD BOs

[Felix Kuehling]

This is needed to correctly handle BOs imported into the GEM API, which
would otherwise get added twice to the same VM.

Signed-off-by: Felix Kuehling 
---
 .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c  | 28 +++
 1 file changed, 22 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index ecf81f27cb4b..68e794cad647 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -370,9 +370,17 @@ static int amdgpu_amdkfd_bo_validate_and_fence(struct 
amdgpu_bo *bo,
return ret;
 
ret = amdgpu_amdkfd_bo_validate(bo, domain, true);
-   if (!ret)
-   dma_resv_add_fence(bo->tbo.base.resv, fence,
-  DMA_RESV_USAGE_BOOKKEEP);
+   if (ret)
+   goto unreserve_out;
+
+   ret = dma_resv_reserve_fences(bo->tbo.base.resv, 1);
+   if (ret)
+   goto unreserve_out;
+
+   dma_resv_add_fence(bo->tbo.base.resv, fence,
+  DMA_RESV_USAGE_BOOKKEEP);
+
+unreserve_out:
amdgpu_bo_unreserve(bo);
 
return ret;
@@ -785,6 +793,7 @@ static int kfd_mem_attach(struct amdgpu_device *adev, 
struct kgd_mem *mem,
uint64_t va = mem->va;
struct kfd_mem_attachment *attachment[2] = {NULL, NULL};
struct amdgpu_bo *bo[2] = {NULL, NULL};
+   struct amdgpu_bo_va *bo_va;
bool same_hive = false;
int i, ret;
 
@@ -871,7 +880,12 @@ static int kfd_mem_attach(struct amdgpu_device *adev, 
struct kgd_mem *mem,
pr_debug("Unable to reserve BO during memory attach");
goto unwind;
}
-   attachment[i]->bo_va = amdgpu_vm_bo_add(adev, vm, bo[i]);
+   bo_va = amdgpu_vm_bo_find(vm, bo[i]);
+   if (!bo_va)
+   bo_va = amdgpu_vm_bo_add(adev, vm, bo[i]);
+   else
+   ++bo_va->ref_count;
+   attachment[i]->bo_va = bo_va;
amdgpu_bo_unreserve(bo[i]);
if (unlikely(!attachment[i]->bo_va)) {
ret = -ENOMEM;
@@ -895,7 +909,8 @@ static int kfd_mem_attach(struct amdgpu_device *adev, 
struct kgd_mem *mem,
continue;
if (attachment[i]->bo_va) {
amdgpu_bo_reserve(bo[i], true);
-   amdgpu_vm_bo_del(adev, attachment[i]->bo_va);
+   if (--attachment[i]->bo_va->ref_count == 0)
+   amdgpu_vm_bo_del(adev, attachment[i]->bo_va);
amdgpu_bo_unreserve(bo[i]);
list_del([i]->list);
}
@@ -912,7 +927,8 @@ static void kfd_mem_detach(struct kfd_mem_attachment 
*attachment)
 
pr_debug("\t remove VA 0x%llx in entry %p\n",
attachment->va, attachment);
-   amdgpu_vm_bo_del(attachment->adev, attachment->bo_va);
+   if (--attachment->bo_va->ref_count == 0)
+   amdgpu_vm_bo_del(attachment->adev, attachment->bo_va);
drm_gem_object_put(>tbo.base);
list_del(>list);
kfree(attachment);
-- 
2.32.0

[PATCH 2/6] drm/amdkfd: Implement DMA buf fd export from KFD

[Felix Kuehling]

Exports a DMA buf fd of a given KFD buffer handle. This is intended for
being able to import KFD BOs into GEM contexts to leverage the
amdgpu_bo_va API for more flexible virtual address mappings. It will
also be used for the new upstreamable RDMA solution coming to UCX and
RCCL.

The corresponding user mode change (Thunk API and kfdtest) is here:
https://github.com/fxkamd/ROCT-Thunk-Interface/commits/fxkamd/dmabuf

Signed-off-by: Felix Kuehling 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h|  2 +
 .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c  | 45 +++
 drivers/gpu/drm/amd/amdkfd/kfd_chardev.c  | 55 +++
 include/uapi/linux/kfd_ioctl.h| 14 -
 4 files changed, 104 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index f50e3ba4d7a5..f72d25d5dd4f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -301,6 +301,8 @@ int amdgpu_amdkfd_gpuvm_import_dmabuf(struct amdgpu_device 
*adev,
  uint64_t va, void *drm_priv,
  struct kgd_mem **mem, uint64_t *size,
  uint64_t *mmap_offset);
+int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_mem *mem,
+ struct dma_buf **dmabuf);
 int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev,
struct tile_config *config);
 void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index 67c832ae498b..bd36636a9596 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -710,6 +710,21 @@ kfd_mem_dmaunmap_attachment(struct kgd_mem *mem,
}
 }
 
+static int kfd_mem_export_dmabuf(struct kgd_mem *mem)
+{
+   if (!mem->dmabuf) {
+   struct dma_buf *ret = amdgpu_gem_prime_export(
+   >bo->tbo.base,
+   mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
+   DRM_RDWR : 0);
+   if (IS_ERR(ret))
+   return PTR_ERR(ret);
+   mem->dmabuf = ret;
+   }
+
+   return 0;
+}
+
 static int
 kfd_mem_attach_dmabuf(struct amdgpu_device *adev, struct kgd_mem *mem,
  struct amdgpu_bo **bo)
@@ -717,16 +732,9 @@ kfd_mem_attach_dmabuf(struct amdgpu_device *adev, struct 
kgd_mem *mem,
struct drm_gem_object *gobj;
int ret;
 
-   if (!mem->dmabuf) {
-   mem->dmabuf = amdgpu_gem_prime_export(>bo->tbo.base,
-   mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
-   DRM_RDWR : 0);
-   if (IS_ERR(mem->dmabuf)) {
-   ret = PTR_ERR(mem->dmabuf);
-   mem->dmabuf = NULL;
-   return ret;
-   }
-   }
+   ret = kfd_mem_export_dmabuf(mem);
+   if (ret)
+   return ret;
 
gobj = amdgpu_gem_prime_import(adev_to_drm(adev), mem->dmabuf);
if (IS_ERR(gobj))
@@ -2241,6 +2249,23 @@ int amdgpu_amdkfd_gpuvm_import_dmabuf(struct 
amdgpu_device *adev,
return ret;
 }
 
+int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_mem *mem,
+ struct dma_buf **dma_buf)
+{
+   int ret;
+
+   mutex_lock(>lock);
+   ret = kfd_mem_export_dmabuf(mem);
+   if (ret)
+   goto out;
+
+   get_dma_buf(mem->dmabuf);
+   *dma_buf = mem->dmabuf;
+out:
+   mutex_unlock(>lock);
+   return ret;
+}
+
 /* Evict a userptr BO by stopping the queues if necessary
  *
  * Runs in MMU notifier, may be in RECLAIM_FS context. This means it
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
index 6d291aa6386b..b9a9c4c9ec16 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
@@ -1567,6 +1567,58 @@ static int kfd_ioctl_import_dmabuf(struct file *filep,
return r;
 }
 
+static int kfd_ioctl_export_dmabuf(struct file *filep,
+  struct kfd_process *p, void *data)
+{
+   struct kfd_ioctl_export_dmabuf_args *args = data;
+   struct kfd_process_device *pdd;
+   struct dma_buf *dmabuf;
+   struct kfd_dev *dev;
+   void *mem;
+   int ret = 0;
+
+   dev = kfd_device_by_id(GET_GPU_ID(args->handle));
+   if (!dev)
+   return -EINVAL;
+
+   mutex_lock(>mutex);
+
+   pdd = kfd_get_process_device_data(dev, p);
+   if (!pdd) {
+   ret = -EINVAL;
+   goto err_unlock;
+   }
+
+   mem = kfd_process_device_translate_handle(pdd,
+

[PATCH 5/6] drm/amdgpu: update mappings not managed by KFD

[Felix Kuehling]

When restoring after an eviction, use amdgpu_vm_handle_moved to update
BO VA mappings in KFD VMs that are not managed through the KFD API. This
should allow using the render node API to create more flexible memory
mappings in KFD VMs.

v2: Sync with pd fence after all page table updates
v3: Update comments, remove TODOs that are no longer applicable

Signed-off-by: Felix Kuehling 
---
 .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c  | 28 +++
 1 file changed, 22 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index e13dff75ca5c..ecf81f27cb4b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -2655,12 +2655,6 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, 
struct dma_fence **ef)
if (ret)
goto validate_map_fail;
 
-   ret = process_sync_pds_resv(process_info, _obj);
-   if (ret) {
-   pr_debug("Memory eviction: Failed to sync to PD BO moving 
fence. Try again\n");
-   goto validate_map_fail;
-   }
-
/* Validate BOs and map them to GPUVM (update VM page tables). */
list_for_each_entry(mem, _info->kfd_bo_list,
validate_list.head) {
@@ -2708,6 +2702,19 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, 
struct dma_fence **ef)
if (failed_size)
pr_debug("0x%lx/0x%lx in system\n", failed_size, total_size);
 
+   /* Update mappings not managed by KFD */
+   list_for_each_entry(peer_vm, _info->vm_list_head,
+   vm_list_node) {
+   struct amdgpu_device *adev = amdgpu_ttm_adev(
+   peer_vm->root.bo->tbo.bdev);
+
+   ret = amdgpu_vm_handle_moved(adev, peer_vm, );
+   if (ret) {
+   pr_debug("Memory eviction: handle moved failed. Try 
again\n");
+   goto validate_map_fail;
+   }
+   }
+
/* Update page directories */
ret = process_update_pds(process_info, _obj);
if (ret) {
@@ -2715,6 +2722,15 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, 
struct dma_fence **ef)
goto validate_map_fail;
}
 
+   /* Sync with fences on all the page tables. They implicitly depend on 
any
+* move fences from amdgpu_vm_handle_moved above.
+*/
+   ret = process_sync_pds_resv(process_info, _obj);
+   if (ret) {
+   pr_debug("Memory eviction: Failed to sync to PD BO moving 
fence. Try again\n");
+   goto validate_map_fail;
+   }
+
/* Wait for validate and PT updates to finish */
amdgpu_sync_wait(_obj, false);
 
-- 
2.32.0

[PATCH 1/6] drm/amdgpu: Generalize KFD dmabuf import

[Felix Kuehling]

Use proper amdgpu_gem_prime_import function to handle all kinds of
imports. Remember the dmabuf reference to enable proper multi-GPU
attachment to multiple VMs without erroneously re-exporting the
underlying BO multiple times.

Signed-off-by: Felix Kuehling 
---
 .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c  | 38 ++-
 1 file changed, 21 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index 3a763916a5a1..67c832ae498b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -2183,30 +2183,27 @@ int amdgpu_amdkfd_gpuvm_import_dmabuf(struct 
amdgpu_device *adev,
struct amdgpu_bo *bo;
int ret;
 
-   if (dma_buf->ops != _dmabuf_ops)
-   /* Can't handle non-graphics buffers */
-   return -EINVAL;
-
-   obj = dma_buf->priv;
-   if (drm_to_adev(obj->dev) != adev)
-   /* Can't handle buffers from other devices */
-   return -EINVAL;
+   obj = amdgpu_gem_prime_import(adev_to_drm(adev), dma_buf);
+   if (IS_ERR(obj))
+   return PTR_ERR(obj);
 
bo = gem_to_amdgpu_bo(obj);
if (!(bo->preferred_domains & (AMDGPU_GEM_DOMAIN_VRAM |
-   AMDGPU_GEM_DOMAIN_GTT)))
+   AMDGPU_GEM_DOMAIN_GTT))) {
/* Only VRAM and GTT BOs are supported */
-   return -EINVAL;
+   ret = -EINVAL;
+   goto err_put_obj;
+   }
 
*mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL);
-   if (!*mem)
-   return -ENOMEM;
+   if (!*mem) {
+   ret = -ENOMEM;
+   goto err_put_obj;
+   }
 
ret = drm_vma_node_allow(>vma_node, drm_priv);
-   if (ret) {
-   kfree(mem);
-   return ret;
-   }
+   if (ret)
+   goto err_free_mem;
 
if (size)
*size = amdgpu_bo_size(bo);
@@ -2223,7 +2220,8 @@ int amdgpu_amdkfd_gpuvm_import_dmabuf(struct 
amdgpu_device *adev,
| KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE
| KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE;
 
-   drm_gem_object_get(>tbo.base);
+   get_dma_buf(dma_buf);
+   (*mem)->dmabuf = dma_buf;
(*mem)->bo = bo;
(*mem)->va = va;
(*mem)->domain = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ?
@@ -2235,6 +2233,12 @@ int amdgpu_amdkfd_gpuvm_import_dmabuf(struct 
amdgpu_device *adev,
(*mem)->is_imported = true;
 
return 0;
+
+err_free_mem:
+   kfree(mem);
+err_put_obj:
+   drm_gem_object_put(obj);
+   return ret;
 }
 
 /* Evict a userptr BO by stopping the queues if necessary
-- 
2.32.0

[PATCH 0/6] Enable KFD to use render node BO mappings

[Felix Kuehling]

This patch series enables KFD to interoperate more closely with DRM render
nodes. ROCm user mode already uses DRM render nodes to create its GPU VM
contexts and to CPU-map its GEM buffer objects. This patch series adds an
API to let KFD export its BOs as DMABufs, so they can be imported into
the DRM render nodes. This enables more flexible virtual memory mappings
using DRM_IOCTL_AMDGPU_GEM_VA.

Patches 1 and 2 deal with the exporting and importing of DMABufs.

The remaining patches let KFD validate and update GPUVM mappings managed
through render nodes.

The user mode side of this patch series can be seen in libhsakmt and
KFDTest where we improve integration with libdrm (initializing
amdgpu_device instances) to enable DMABuf imports into the render nodes
representing KFD GPU VM contexts. KFDTest is modified to test evictions
and validations of BOs mapped through amdgpu_bo_va_op:
https://github.com/fxkamd/ROCT-Thunk-Interface/commits/fxkamd/dmabuf

As a consequence, applications using Mesa and ROCm in the same process on
the same GPU will now share a single render node FD and GPUVM address
space.

The DMABuf export API will also be used later for upstream IPC and RDMA
implementation.

Felix Kuehling (6):
  drm/amdgpu: Generalize KFD dmabuf import
  drm/amdkfd: Implement DMA buf fd export from KFD
  drm/amdkfd: Improve amdgpu_vm_handle_moved
  drm/amdgpu: Attach eviction fence on alloc
  drm/amdgpu: update mappings not managed by KFD
  drm/amdgpu: Do bo_va ref counting for KFD BOs

 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h|   2 +
 .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c  | 196 --
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c|   6 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c   |   2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c|  18 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h|   3 +-
 drivers/gpu/drm/amd/amdkfd/kfd_chardev.c  |  55 +
 include/uapi/linux/kfd_ioctl.h|  14 +-
 8 files changed, 219 insertions(+), 77 deletions(-)

-- 
2.32.0

[PATCH v2] drm/amd/display: add FB_DAMAGE_CLIPS support

[Hamza Mahfooz]

Currently, userspace doesn't have a way to communicate selective updates
to displays. So, enable support for FB_DAMAGE_CLIPS for DCN ASICs newer
than DCN301, convert DRM damage clips to dc dirty rectangles and fill
them into dirty_rects in fill_dc_dirty_rects().

Signed-off-by: Hamza Mahfooz 
---
v2: fallback to FFU if we run into too many dirty rectangles, consider
dirty rectangles in non MPO case and always add a dirty rectangle
for the new plane if there are bb changes in the MPO case.
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 130 +++---
 .../amd/display/amdgpu_dm/amdgpu_dm_plane.c   |   4 +
 2 files changed, 88 insertions(+), 46 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 4eb8201a2608..7af94a2c6237 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4842,6 +4842,35 @@ static int fill_dc_plane_attributes(struct amdgpu_device 
*adev,
return 0;
 }
 
+static inline void fill_dc_dirty_rect(struct drm_plane *plane,
+ struct rect *dirty_rect, int32_t x,
+ int32_t y, int32_t width, int32_t height,
+ int *i, bool ffu)
+{
+   if (*i > DC_MAX_DIRTY_RECTS)
+   return;
+
+   if (*i == DC_MAX_DIRTY_RECTS)
+   goto out;
+
+   dirty_rect->x = x;
+   dirty_rect->y = y;
+   dirty_rect->width = width;
+   dirty_rect->height = height;
+
+   if (ffu)
+   drm_dbg(plane->dev,
+   "[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n",
+   plane->base.id, width, height);
+   else
+   drm_dbg(plane->dev,
+   "[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, 
%d)",
+   plane->base.id, x, y, width, height);
+
+out:
+   (*i)++;
+}
+
 /**
  * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates
  *
@@ -4862,10 +4891,6 @@ static int fill_dc_plane_attributes(struct amdgpu_device 
*adev,
  * addition, certain use cases - such as cursor and multi-plane overlay (MPO) -
  * implicitly provide damage clips without any client support via the plane
  * bounds.
- *
- * Today, amdgpu_dm only supports the MPO and cursor usecase.
- *
- * TODO: Also enable for FB_DAMAGE_CLIPS
  */
 static void fill_dc_dirty_rects(struct drm_plane *plane,
struct drm_plane_state *old_plane_state,
@@ -4876,12 +4901,11 @@ static void fill_dc_dirty_rects(struct drm_plane *plane,
struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
struct rect *dirty_rects = flip_addrs->dirty_rects;
uint32_t num_clips;
+   struct drm_mode_rect *clips;
bool bb_changed;
bool fb_changed;
uint32_t i = 0;
 
-   flip_addrs->dirty_rect_count = 0;
-
/*
 * Cursor plane has it's own dirty rect update interface. See
 * dcn10_dmub_update_cursor_data and dmub_cmd_update_cursor_info_data
@@ -4889,20 +4913,20 @@ static void fill_dc_dirty_rects(struct drm_plane *plane,
if (plane->type == DRM_PLANE_TYPE_CURSOR)
return;
 
-   /*
-* Today, we only consider MPO use-case for PSR SU. If MPO not
-* requested, and there is a plane update, do FFU.
-*/
+   num_clips = drm_plane_get_damage_clips_count(new_plane_state);
+   clips = drm_plane_get_damage_clips(new_plane_state);
+
if (!dm_crtc_state->mpo_requested) {
-   dirty_rects[0].x = 0;
-   dirty_rects[0].y = 0;
-   dirty_rects[0].width = dm_crtc_state->base.mode.crtc_hdisplay;
-   dirty_rects[0].height = dm_crtc_state->base.mode.crtc_vdisplay;
-   flip_addrs->dirty_rect_count = 1;
-   DRM_DEBUG_DRIVER("[PLANE:%d] PSR FFU dirty rect size (%d, 
%d)\n",
-new_plane_state->plane->base.id,
-dm_crtc_state->base.mode.crtc_hdisplay,
-dm_crtc_state->base.mode.crtc_vdisplay);
+   if (!num_clips || num_clips > DC_MAX_DIRTY_RECTS)
+   goto ffu;
+
+   for (; flip_addrs->dirty_rect_count < num_clips; clips++)
+   fill_dc_dirty_rect(new_plane_state->plane,
+  _rects[i], clips->x1,
+  clips->y1, clips->x2 - clips->x1,
+  clips->y2 - clips->y1,
+  _addrs->dirty_rect_count,
+  false);
return;
}
 
@@ -4913,7 +4937,6 @@ static void fill_dc_dirty_rects(struct drm_plane *plane,
 * If plane is moved or resized, also add old bounding box to dirty
 

Re: [PATCH] drm/amd/dc/dce120: Fix audio register mapping, stop triggering KASAN

[Harry Wentland]

On 11/18/22 15:25, Alex Deucher wrote:
> On Thu, Nov 17, 2022 at 4:40 PM Alex Deucher  wrote:
>>
>> On Mon, Nov 14, 2022 at 5:21 PM Lyude Paul  wrote:
>>>
>>> There's been a very long running bug that seems to have been neglected for
>>> a while, where amdgpu consistently triggers a KASAN error at start:
>>>
>>>   BUG: KASAN: global-out-of-bounds in read_indirect_azalia_reg+0x1d4/0x2a0 
>>> [amdgpu]
>>>   Read of size 4 at addr c2274b28 by task modprobe/1889
>>>
>>> After digging through amd's rather creative method for accessing registers,
>>> I eventually discovered the problem likely has to do with the fact that on
>>> my dce120 GPU there are supposedly 7 sets of audio registers. But we only
>>> define a register mapping for 6 sets.
>>>
>>> So, fix this and fix the KASAN warning finally.
>>>
>>> Signed-off-by: Lyude Paul 
>>> Cc: sta...@vger.kernel.org
>>
>> This is the correct fix for asics having 7 audio instances.  It looks
>> correct to me, assuming DCE12 actually has 7 audio instances.
>> @Wentland, Harry Do you know off hand?  If you can confirm that, the
>> patch is:
>> Reviewed-by: Alex Deucher 
> 
> The driver currently defines 7 audio instances, whether or not it
> actually has 7 remains to be seen but the code as is is broken, so
> I'll apply this.  If it turns out there are only 6 instances we can
> fix the count later.  Applied.  Thanks!
> 

Good catch. I seem to recall some DCE generations had an extra audio
device and if DCE12 defines 7 audio instances then this is the correct
fix.

Reviewed-by: Harry Wentland 

Harry

> Alex
> 
>>
>>
>>> ---
>>> Sending this one separately from the rest of my fixes since:
>>>
>>> * It's definitely completely unrelated to the Gitlab 2171 issue
>>> * I'm not sure if this is the correct fix since it's in DC
>>>
>>>  drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c | 3 ++-
>>>  1 file changed, 2 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 
>>> b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
>>> index 1b70b78e2fa15..af631085e88c5 100644
>>> --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
>>> +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
>>> @@ -359,7 +359,8 @@ static const struct dce_audio_registers audio_regs[] = {
>>> audio_regs(2),
>>> audio_regs(3),
>>> audio_regs(4),
>>> -   audio_regs(5)
>>> +   audio_regs(5),
>>> +   audio_regs(6),
>>>  };
>>>
>>>  #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
>>> --
>>> 2.37.3
>>>

Re: [PATCH] drm/amd/dc/dce120: Fix audio register mapping, stop triggering KASAN

[Alex Deucher]

On Thu, Nov 17, 2022 at 4:40 PM Alex Deucher  wrote:
>
> On Mon, Nov 14, 2022 at 5:21 PM Lyude Paul  wrote:
> >
> > There's been a very long running bug that seems to have been neglected for
> > a while, where amdgpu consistently triggers a KASAN error at start:
> >
> >   BUG: KASAN: global-out-of-bounds in read_indirect_azalia_reg+0x1d4/0x2a0 
> > [amdgpu]
> >   Read of size 4 at addr c2274b28 by task modprobe/1889
> >
> > After digging through amd's rather creative method for accessing registers,
> > I eventually discovered the problem likely has to do with the fact that on
> > my dce120 GPU there are supposedly 7 sets of audio registers. But we only
> > define a register mapping for 6 sets.
> >
> > So, fix this and fix the KASAN warning finally.
> >
> > Signed-off-by: Lyude Paul 
> > Cc: sta...@vger.kernel.org
>
> This is the correct fix for asics having 7 audio instances.  It looks
> correct to me, assuming DCE12 actually has 7 audio instances.
> @Wentland, Harry Do you know off hand?  If you can confirm that, the
> patch is:
> Reviewed-by: Alex Deucher 

The driver currently defines 7 audio instances, whether or not it
actually has 7 remains to be seen but the code as is is broken, so
I'll apply this.  If it turns out there are only 6 instances we can
fix the count later.  Applied.  Thanks!

Alex

>
>
> > ---
> > Sending this one separately from the rest of my fixes since:
> >
> > * It's definitely completely unrelated to the Gitlab 2171 issue
> > * I'm not sure if this is the correct fix since it's in DC
> >
> >  drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c | 3 ++-
> >  1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 
> > b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
> > index 1b70b78e2fa15..af631085e88c5 100644
> > --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
> > +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
> > @@ -359,7 +359,8 @@ static const struct dce_audio_registers audio_regs[] = {
> > audio_regs(2),
> > audio_regs(3),
> > audio_regs(4),
> > -   audio_regs(5)
> > +   audio_regs(5),
> > +   audio_regs(6),
> >  };
> >
> >  #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
> > --
> > 2.37.3
> >

Re: [PATCH] drm/amdgpu: fix pci device refcount leak

[Alex Deucher]

Applied.  Thanks!

Alex

On Thu, Nov 17, 2022 at 8:55 PM Quan, Evan  wrote:
>
> [AMD Official Use Only - General]
>
> Reviewed-by: Evan Quan 
>
> > -Original Message-
> > From: Yang Yingliang 
> > Sent: Thursday, November 17, 2022 11:00 PM
> > To: amd-gfx@lists.freedesktop.org
> > Cc: Deucher, Alexander ; Quan, Evan
> > ; yangyingli...@huawei.com
> > Subject: [PATCH] drm/amdgpu: fix pci device refcount leak
> >
> > As comment of pci_get_domain_bus_and_slot() says, it returns
> > a pci device with refcount increment, when finish using it,
> > the caller must decrement the reference count by calling
> > pci_dev_put().
> >
> > So before returning from amdgpu_device_resume|suspend_display_audio(),
> > pci_dev_put() is called to avoid refcount leak.
> >
> > Fixes: 3f12acc8d6d4 ("drm/amdgpu: put the audio codec into suspend state
> > before gpu reset V3")
> > Signed-off-by: Yang Yingliang 
> > ---
> >  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 
> >  1 file changed, 4 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > index 64510898eedd..69e73fef1ab2 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > @@ -5027,6 +5027,8 @@ static void
> > amdgpu_device_resume_display_audio(struct amdgpu_device *adev)
> >   pm_runtime_enable(&(p->dev));
> >   pm_runtime_resume(&(p->dev));
> >   }
> > +
> > + pci_dev_put(p);
> >  }
> >
> >  static int amdgpu_device_suspend_display_audio(struct amdgpu_device
> > *adev)
> > @@ -5065,6 +5067,7 @@ static int
> > amdgpu_device_suspend_display_audio(struct amdgpu_device *adev)
> >
> >   if (expires < ktime_get_mono_fast_ns()) {
> >   dev_warn(adev->dev, "failed to suspend display
> > audio\n");
> > + pci_dev_put(p);
> >   /* TODO: abort the succeeding gpu reset? */
> >   return -ETIMEDOUT;
> >   }
> > @@ -5072,6 +5075,7 @@ static int
> > amdgpu_device_suspend_display_audio(struct amdgpu_device *adev)
> >
> >   pm_runtime_disable(&(p->dev));
> >
> > + pci_dev_put(p);
> >   return 0;
> >  }
> >
> > --
> > 2.25.1

Re: [PATCH 22/22] SWDEV-1 - dc: 3.2.213

[Alex Deucher]

Please fix the subject.  E.g., drm/amd/display: dc: 3.2.213
or something like that.

On Fri, Nov 18, 2022 at 12:02 PM brichang  wrote:
>
> From: Aric Cyr 
>
> Signed-off-by: Aric Cyr 
>
> This version brings along following fixes:
> -Add configuration 2 for ABM 2.3/2.4.
> -Add margin for HUBP for SubVp + DRR.
> -Fix no display after resume from WB/CB.
> -Limit HW cursor size to be less than 64 x 64 bytes when the stream is >= 4K.
> -Lower watermarks for enter/enter+exit latency.
> -Update support types for DCN314 to include z8 only and z8_z10 only state.
> -Add new value for soc bounding box and dummy pstate.
> -Override fclk chang latency when calculating prefetch schedule for subvp 
> with low uclk.
> -Add check for DET fetch latency for dcn32.
> -Add check if PSR enabled when entering MALL.
> -Use base MALL allocation size calculations off vewport height.
> -Add YCBCR2020 to CSC matrix.
> -Implement DP-Tx portion to interact with DPIA.
> -Add debug option for increasing phantom lines.
> -Fix phantom plane/stream retain after fail validation.
> -Fix display corruption with VSR enable.
> -Set valid divider value for virtual and FRL/DP2.
> -Add new num clk levels struct for max mclk index.
> -Fix check for phantom BPP.
> -Fix rotated cursor offset calculation.
> ---
>  drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
> b/drivers/gpu/drm/amd/display/dc/dc.h
> index e827cee94e5e..feb7a7f2734e 100644
> --- a/drivers/gpu/drm/amd/display/dc/dc.h
> +++ b/drivers/gpu/drm/amd/display/dc/dc.h
> @@ -47,7 +47,7 @@ struct aux_payload;
>  struct set_config_cmd_payload;
>  struct dmub_notification;
>
> -#define DC_VER "3.2.212"
> +#define DC_VER "3.2.213"
>
>  #define MAX_SURFACES 3
>  #define MAX_PLANES 6
> --
> 2.25.1
>

Re: [PATCH] drm/amdgpu/dm/mst: Fix uninitialized var in pre_compute_mst_dsc_configs_for_state()

[Alex Deucher]

Applied.  Thanks!

Alex

On Fri, Nov 18, 2022 at 3:03 PM Harry Wentland  wrote:
>
> On 11/18/22 14:54, Lyude Paul wrote:
> > Coverity noticed this one, so let's fix it.
> >
> > Signed-off-by: Lyude Paul 
>
> Reviewed-by: Harry Wentland 
>
> Harry
>
> > ---
> >  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c 
> > b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> > index 59648f5ffb59..6483ba266893 100644
> > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> > @@ -1180,7 +1180,7 @@ static int 
> > pre_compute_mst_dsc_configs_for_state(struct drm_atomic_state *state,
> >   struct amdgpu_dm_connector *aconnector;
> >   struct drm_dp_mst_topology_mgr *mst_mgr;
> >   int link_vars_start_index = 0;
> > - int ret;
> > + int ret = 0;
> >
> >   for (i = 0; i < dc_state->stream_count; i++)
> >   computed_streams[i] = false;
>

Re: [PATCH v2 1/4] drm/amdgpu/mst: Stop ignoring error codes and deadlocking

[Alex Deucher]

On Fri, Nov 18, 2022 at 2:53 PM Lyude Paul  wrote:
>
> JFYI - I'm not sure of the correct commit ID to add for the Fixes: tag since
> it's in your branch, so I'll omit that and let you add it into the patch

Yeah, I'll add that.  Many thanks!

Alex

>
> On Fri, 2022-11-18 at 14:47 -0500, Lyude Paul wrote:
> > of course, will do in just a moment
> >
> > On Fri, 2022-11-18 at 14:46 -0500, Alex Deucher wrote:
> > > I've already picked this up.  Can you send a follow up patch with just
> > > the coverity fix?
> > >
> > > Alex
> > >
> > > On Fri, Nov 18, 2022 at 2:17 PM Lyude Paul  wrote:
> > > >
> > > > JFYI, Coverity pointed out one more issue with this series so I'm going 
> > > > to
> > > > send out a respin real quick to fix it. It's just a missing variable
> > > > assignment (we leave ret unassigned by mistake in
> > > > pre_compute_mst_dsc_configs()) so I will carry over your r-b on it.
> > > >
> > > > On Wed, 2022-11-16 at 04:39 +, Lin, Wayne wrote:
> > > > > [Public]
> > > > >
> > > > > All the patch set looks good to me. Feel free to add:
> > > > > Reviewed-by: Wayne Lin 
> > > > >
> > > > > Again, thank you Lyude for helping on this!!!
> > > > >
> > > > > Regards,
> > > > > Wayne
> > > > > > -Original Message-
> > > > > > From: Lyude Paul 
> > > > > > Sent: Tuesday, November 15, 2022 6:18 AM
> > > > > > To: amd-gfx@lists.freedesktop.org
> > > > > > Cc: Wentland, Harry ; 
> > > > > > sta...@vger.kernel.org;
> > > > > > Li, Sun peng (Leo) ; Siqueira, Rodrigo
> > > > > > ; Deucher, Alexander
> > > > > > ; Koenig, Christian
> > > > > > ; Pan, Xinhui ; David
> > > > > > Airlie ; Daniel Vetter ; 
> > > > > > Kazlauskas,
> > > > > > Nicholas ; Pillai, Aurabindo
> > > > > > ; Li, Roman ; Zuo, Jerry
> > > > > > ; Wu, Hersen ; Lin, Wayne
> > > > > > ; Thomas Zimmermann ;
> > > > > > Mahfooz, Hamza ; Hung, Alex
> > > > > > ; Mikita Lipski ; Liu,
> > > > > > Wenjing ; Francis, David
> > > > > > ; open list:DRM DRIVERS  > > > > > de...@lists.freedesktop.org>; open list 
> > > > > > 
> > > > > > Subject: [PATCH v2 1/4] drm/amdgpu/mst: Stop ignoring error codes 
> > > > > > and
> > > > > > deadlocking
> > > > > >
> > > > > > It appears that amdgpu makes the mistake of completely ignoring the 
> > > > > > return
> > > > > > values from the DP MST helpers, and instead just returns a simple 
> > > > > > true/false.
> > > > > > In this case, it seems to have come back to bite us because as a 
> > > > > > result of
> > > > > > simply returning false from compute_mst_dsc_configs_for_state(), 
> > > > > > amdgpu
> > > > > > had no way of telling when a deadlock happened from these helpers. 
> > > > > > This
> > > > > > could definitely result in some kernel splats.
> > > > > >
> > > > > > V2:
> > > > > > * Address Wayne's comments (fix another bunch of spots where we 
> > > > > > weren't
> > > > > >   passing down return codes)
> > > > > >
> > > > > > Signed-off-by: Lyude Paul 
> > > > > > Fixes: 8c20a1ed9b4f ("drm/amd/display: MST DSC compute fair share")
> > > > > > Cc: Harry Wentland 
> > > > > > Cc:  # v5.6+
> > > > > > ---
> > > > > >  .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  18 +-
> > > > > >  .../display/amdgpu_dm/amdgpu_dm_mst_types.c   | 235 
> > > > > > ++--
> > > > > > --
> > > > > >  .../display/amdgpu_dm/amdgpu_dm_mst_types.h   |  12 +-
> > > > > >  3 files changed, 147 insertions(+), 118 deletions(-)
> > > > > >
> > > > > > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > > > > > b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > > > > > index 0db2a88cd4d7b..852a2100c6b38 100644
> > > > > > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > > > > > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > > > > > @@ -6462,7 +6462,7 @@ static int
> > > > > > dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
> > > > > > struct drm_connector_state *new_con_state;
> > > > > > struct amdgpu_dm_connector *aconnector;
> > > > > > struct dm_connector_state *dm_conn_state;
> > > > > > -   int i, j;
> > > > > > +   int i, j, ret;
> > > > > > int vcpi, pbn_div, pbn, slot_num = 0;
> > > > > >
> > > > > > for_each_new_connector_in_state(state, connector,
> > > > > > new_con_state, i) { @@ -6509,8 +6509,11 @@ static int
> > > > > > dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
> > > > > > dm_conn_state->pbn = pbn;
> > > > > > dm_conn_state->vcpi_slots = slot_num;
> > > > > >
> > > > > > -   drm_dp_mst_atomic_enable_dsc(state, aconnector-
> > > > > > > port, dm_conn_state->pbn,
> > > > > > -false);
> > > > > > +   ret = drm_dp_mst_atomic_enable_dsc(state,
> > > > > > aconnector->port,
> > > > > > +  
> > > > > > dm_conn_state-
> > > > > > > pbn, false);
> > > > > > +   if (ret < 0)
> > > > > > +  

Re: [PATCH] drm/amdgpu/dm/mst: Fix uninitialized var in pre_compute_mst_dsc_configs_for_state()

[Harry Wentland]

On 11/18/22 14:54, Lyude Paul wrote:
> Coverity noticed this one, so let's fix it.
> 
> Signed-off-by: Lyude Paul 

Reviewed-by: Harry Wentland 

Harry

> ---
>  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c 
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> index 59648f5ffb59..6483ba266893 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> @@ -1180,7 +1180,7 @@ static int pre_compute_mst_dsc_configs_for_state(struct 
> drm_atomic_state *state,
>   struct amdgpu_dm_connector *aconnector;
>   struct drm_dp_mst_topology_mgr *mst_mgr;
>   int link_vars_start_index = 0;
> - int ret;
> + int ret = 0;
>  
>   for (i = 0; i < dc_state->stream_count; i++)
>   computed_streams[i] = false;

Re: [v3] drm/amdgpu/mst: Stop ignoring error codes and deadlocking

[Lyude Paul]

On Fri, 2022-11-18 at 13:54 -0600, Limonciello, Mario wrote:
> On 11/18/2022 13:25, Lyude Paul wrote:
> > It appears that amdgpu makes the mistake of completely ignoring the return
> > values from the DP MST helpers, and instead just returns a simple
> > true/false. In this case, it seems to have come back to bite us because as
> > a result of simply returning false from
> > compute_mst_dsc_configs_for_state(), amdgpu had no way of telling when a
> > deadlock happened from these helpers. This could definitely result in some
> > kernel splats.
> > 
> > V2:
> > * Address Wayne's comments (fix another bunch of spots where we weren't
> >passing down return codes)
> > V3:
> > * Fix uninitialized var in pre_compute_mst_dsc_configs_for_state()
> 
> FYI v2 was just merged recently, it's in the 6.2 pull request that was 
> sent out and Alex planned to add it to 6.1-fixes next week too.
> 
> Can you send just the delta from v2->v3 as another patch so it can layer 
> in cleanly?

Just did that :), it should be on the list now

> > 
> > Signed-off-by: Lyude Paul 
> > Fixes: 8c20a1ed9b4f ("drm/amd/display: MST DSC compute fair share")
> > Reviewed-by: Wayne Lin 
> > Cc: Harry Wentland 
> > Cc:  # v5.6+
> > ---
> >   .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  18 +-
> >   .../display/amdgpu_dm/amdgpu_dm_mst_types.c   | 235 ++
> >   .../display/amdgpu_dm/amdgpu_dm_mst_types.h   |  12 +-
> >   3 files changed, 147 insertions(+), 118 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
> > b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > index 0db2a88cd4d7..852a2100c6b3 100644
> > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > @@ -6462,7 +6462,7 @@ static int dm_update_mst_vcpi_slots_for_dsc(struct 
> > drm_atomic_state *state,
> > struct drm_connector_state *new_con_state;
> > struct amdgpu_dm_connector *aconnector;
> > struct dm_connector_state *dm_conn_state;
> > -   int i, j;
> > +   int i, j, ret;
> > int vcpi, pbn_div, pbn, slot_num = 0;
> >   
> > for_each_new_connector_in_state(state, connector, new_con_state, i) {
> > @@ -6509,8 +6509,11 @@ static int dm_update_mst_vcpi_slots_for_dsc(struct 
> > drm_atomic_state *state,
> > dm_conn_state->pbn = pbn;
> > dm_conn_state->vcpi_slots = slot_num;
> >   
> > -   drm_dp_mst_atomic_enable_dsc(state, aconnector->port, 
> > dm_conn_state->pbn,
> > -false);
> > +   ret = drm_dp_mst_atomic_enable_dsc(state, 
> > aconnector->port,
> > +  dm_conn_state->pbn, 
> > false);
> > +   if (ret < 0)
> > +   return ret;
> > +
> > continue;
> > }
> >   
> > @@ -9523,10 +9526,9 @@ static int amdgpu_dm_atomic_check(struct drm_device 
> > *dev,
> >   
> >   #if defined(CONFIG_DRM_AMD_DC_DCN)
> > if (dc_resource_is_dsc_encoding_supported(dc)) {
> > -   if (!pre_validate_dsc(state, _state, vars)) {
> > -   ret = -EINVAL;
> > +   ret = pre_validate_dsc(state, _state, vars);
> > +   if (ret != 0)
> > goto fail;
> > -   }
> > }
> >   #endif
> >   
> > @@ -9621,9 +9623,9 @@ static int amdgpu_dm_atomic_check(struct drm_device 
> > *dev,
> > }
> >   
> >   #if defined(CONFIG_DRM_AMD_DC_DCN)
> > -   if (!compute_mst_dsc_configs_for_state(state, 
> > dm_state->context, vars)) {
> > +   ret = compute_mst_dsc_configs_for_state(state, 
> > dm_state->context, vars);
> > +   if (ret) {
> > DRM_DEBUG_DRIVER("compute_mst_dsc_configs_for_state() 
> > failed\n");
> > -   ret = -EINVAL;
> > goto fail;
> > }
> >   
> > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c 
> > b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> > index 6ff96b4bdda5..2f72745660fb 100644
> > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> > @@ -703,13 +703,13 @@ static int bpp_x16_from_pbn(struct 
> > dsc_mst_fairness_params param, int pbn)
> > return dsc_config.bits_per_pixel;
> >   }
> >   
> > -static bool increase_dsc_bpp(struct drm_atomic_state *state,
> > -struct drm_dp_mst_topology_state *mst_state,
> > -struct dc_link *dc_link,
> > -struct dsc_mst_fairness_params *params,
> > -struct dsc_mst_fairness_vars *vars,
> > -int count,
> > -int k)
> > +static int increase_dsc_bpp(struct drm_atomic_state *state,
> > +   struct drm_dp_mst_topology_state *mst_state,
> > +

Re: [v3] drm/amdgpu/mst: Stop ignoring error codes and deadlocking

[Limonciello, Mario]

On 11/18/2022 13:25, Lyude Paul wrote:

It appears that amdgpu makes the mistake of completely ignoring the return
values from the DP MST helpers, and instead just returns a simple
true/false. In this case, it seems to have come back to bite us because as
a result of simply returning false from
compute_mst_dsc_configs_for_state(), amdgpu had no way of telling when a
deadlock happened from these helpers. This could definitely result in some
kernel splats.

V2:
* Address Wayne's comments (fix another bunch of spots where we weren't
   passing down return codes)
V3:
* Fix uninitialized var in pre_compute_mst_dsc_configs_for_state()


FYI v2 was just merged recently, it's in the 6.2 pull request that was 
sent out and Alex planned to add it to 6.1-fixes next week too.


Can you send just the delta from v2->v3 as another patch so it can layer 
in cleanly?


Signed-off-by: Lyude Paul 
Fixes: 8c20a1ed9b4f ("drm/amd/display: MST DSC compute fair share")
Reviewed-by: Wayne Lin 
Cc: Harry Wentland 
Cc:  # v5.6+
---
  .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  18 +-
  .../display/amdgpu_dm/amdgpu_dm_mst_types.c   | 235 ++
  .../display/amdgpu_dm/amdgpu_dm_mst_types.h   |  12 +-
  3 files changed, 147 insertions(+), 118 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 0db2a88cd4d7..852a2100c6b3 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -6462,7 +6462,7 @@ static int dm_update_mst_vcpi_slots_for_dsc(struct 
drm_atomic_state *state,
struct drm_connector_state *new_con_state;
struct amdgpu_dm_connector *aconnector;
struct dm_connector_state *dm_conn_state;
-   int i, j;
+   int i, j, ret;
int vcpi, pbn_div, pbn, slot_num = 0;
  
  	for_each_new_connector_in_state(state, connector, new_con_state, i) {

@@ -6509,8 +6509,11 @@ static int dm_update_mst_vcpi_slots_for_dsc(struct 
drm_atomic_state *state,
dm_conn_state->pbn = pbn;
dm_conn_state->vcpi_slots = slot_num;
  
-			drm_dp_mst_atomic_enable_dsc(state, aconnector->port, dm_conn_state->pbn,

-false);
+   ret = drm_dp_mst_atomic_enable_dsc(state, 
aconnector->port,
+  dm_conn_state->pbn, 
false);
+   if (ret < 0)
+   return ret;
+
continue;
}
  
@@ -9523,10 +9526,9 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
  
  #if defined(CONFIG_DRM_AMD_DC_DCN)

if (dc_resource_is_dsc_encoding_supported(dc)) {
-   if (!pre_validate_dsc(state, _state, vars)) {
-   ret = -EINVAL;
+   ret = pre_validate_dsc(state, _state, vars);
+   if (ret != 0)
goto fail;
-   }
}
  #endif
  
@@ -9621,9 +9623,9 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,

}
  
  #if defined(CONFIG_DRM_AMD_DC_DCN)

-   if (!compute_mst_dsc_configs_for_state(state, 
dm_state->context, vars)) {
+   ret = compute_mst_dsc_configs_for_state(state, 
dm_state->context, vars);
+   if (ret) {
DRM_DEBUG_DRIVER("compute_mst_dsc_configs_for_state() 
failed\n");
-   ret = -EINVAL;
goto fail;
}
  
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

index 6ff96b4bdda5..2f72745660fb 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -703,13 +703,13 @@ static int bpp_x16_from_pbn(struct 
dsc_mst_fairness_params param, int pbn)
return dsc_config.bits_per_pixel;
  }
  
-static bool increase_dsc_bpp(struct drm_atomic_state *state,

-struct drm_dp_mst_topology_state *mst_state,
-struct dc_link *dc_link,
-struct dsc_mst_fairness_params *params,
-struct dsc_mst_fairness_vars *vars,
-int count,
-int k)
+static int increase_dsc_bpp(struct drm_atomic_state *state,
+   struct drm_dp_mst_topology_state *mst_state,
+   struct dc_link *dc_link,
+   struct dsc_mst_fairness_params *params,
+   struct dsc_mst_fairness_vars *vars,
+   int count,
+   int k)
  {
int i;
bool bpp_increased[MAX_PIPES];
@@ -719,6 +719,7 @@ static bool increase_dsc_bpp(struct drm_atomic_state *state,
int 

[PATCH] drm/amdgpu/dm/mst: Fix uninitialized var in pre_compute_mst_dsc_configs_for_state()

[Lyude Paul]

Coverity noticed this one, so let's fix it.

Signed-off-by: Lyude Paul 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 59648f5ffb59..6483ba266893 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -1180,7 +1180,7 @@ static int pre_compute_mst_dsc_configs_for_state(struct 
drm_atomic_state *state,
struct amdgpu_dm_connector *aconnector;
struct drm_dp_mst_topology_mgr *mst_mgr;
int link_vars_start_index = 0;
-   int ret;
+   int ret = 0;
 
for (i = 0; i < dc_state->stream_count; i++)
computed_streams[i] = false;
-- 
2.38.1

Re: [PATCH v2 1/4] drm/amdgpu/mst: Stop ignoring error codes and deadlocking

[Lyude Paul]

JFYI - I'm not sure of the correct commit ID to add for the Fixes: tag since
it's in your branch, so I'll omit that and let you add it into the patch

On Fri, 2022-11-18 at 14:47 -0500, Lyude Paul wrote:
> of course, will do in just a moment
> 
> On Fri, 2022-11-18 at 14:46 -0500, Alex Deucher wrote:
> > I've already picked this up.  Can you send a follow up patch with just
> > the coverity fix?
> > 
> > Alex
> > 
> > On Fri, Nov 18, 2022 at 2:17 PM Lyude Paul  wrote:
> > > 
> > > JFYI, Coverity pointed out one more issue with this series so I'm going to
> > > send out a respin real quick to fix it. It's just a missing variable
> > > assignment (we leave ret unassigned by mistake in
> > > pre_compute_mst_dsc_configs()) so I will carry over your r-b on it.
> > > 
> > > On Wed, 2022-11-16 at 04:39 +, Lin, Wayne wrote:
> > > > [Public]
> > > > 
> > > > All the patch set looks good to me. Feel free to add:
> > > > Reviewed-by: Wayne Lin 
> > > > 
> > > > Again, thank you Lyude for helping on this!!!
> > > > 
> > > > Regards,
> > > > Wayne
> > > > > -Original Message-
> > > > > From: Lyude Paul 
> > > > > Sent: Tuesday, November 15, 2022 6:18 AM
> > > > > To: amd-gfx@lists.freedesktop.org
> > > > > Cc: Wentland, Harry ; sta...@vger.kernel.org;
> > > > > Li, Sun peng (Leo) ; Siqueira, Rodrigo
> > > > > ; Deucher, Alexander
> > > > > ; Koenig, Christian
> > > > > ; Pan, Xinhui ; David
> > > > > Airlie ; Daniel Vetter ; 
> > > > > Kazlauskas,
> > > > > Nicholas ; Pillai, Aurabindo
> > > > > ; Li, Roman ; Zuo, Jerry
> > > > > ; Wu, Hersen ; Lin, Wayne
> > > > > ; Thomas Zimmermann ;
> > > > > Mahfooz, Hamza ; Hung, Alex
> > > > > ; Mikita Lipski ; Liu,
> > > > > Wenjing ; Francis, David
> > > > > ; open list:DRM DRIVERS  > > > > de...@lists.freedesktop.org>; open list 
> > > > > Subject: [PATCH v2 1/4] drm/amdgpu/mst: Stop ignoring error codes and
> > > > > deadlocking
> > > > > 
> > > > > It appears that amdgpu makes the mistake of completely ignoring the 
> > > > > return
> > > > > values from the DP MST helpers, and instead just returns a simple 
> > > > > true/false.
> > > > > In this case, it seems to have come back to bite us because as a 
> > > > > result of
> > > > > simply returning false from compute_mst_dsc_configs_for_state(), 
> > > > > amdgpu
> > > > > had no way of telling when a deadlock happened from these helpers. 
> > > > > This
> > > > > could definitely result in some kernel splats.
> > > > > 
> > > > > V2:
> > > > > * Address Wayne's comments (fix another bunch of spots where we 
> > > > > weren't
> > > > >   passing down return codes)
> > > > > 
> > > > > Signed-off-by: Lyude Paul 
> > > > > Fixes: 8c20a1ed9b4f ("drm/amd/display: MST DSC compute fair share")
> > > > > Cc: Harry Wentland 
> > > > > Cc:  # v5.6+
> > > > > ---
> > > > >  .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  18 +-
> > > > >  .../display/amdgpu_dm/amdgpu_dm_mst_types.c   | 235 ++--
> > > > > --
> > > > >  .../display/amdgpu_dm/amdgpu_dm_mst_types.h   |  12 +-
> > > > >  3 files changed, 147 insertions(+), 118 deletions(-)
> > > > > 
> > > > > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > > > > b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > > > > index 0db2a88cd4d7b..852a2100c6b38 100644
> > > > > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > > > > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > > > > @@ -6462,7 +6462,7 @@ static int
> > > > > dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
> > > > > struct drm_connector_state *new_con_state;
> > > > > struct amdgpu_dm_connector *aconnector;
> > > > > struct dm_connector_state *dm_conn_state;
> > > > > -   int i, j;
> > > > > +   int i, j, ret;
> > > > > int vcpi, pbn_div, pbn, slot_num = 0;
> > > > > 
> > > > > for_each_new_connector_in_state(state, connector,
> > > > > new_con_state, i) { @@ -6509,8 +6509,11 @@ static int
> > > > > dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
> > > > > dm_conn_state->pbn = pbn;
> > > > > dm_conn_state->vcpi_slots = slot_num;
> > > > > 
> > > > > -   drm_dp_mst_atomic_enable_dsc(state, aconnector-
> > > > > > port, dm_conn_state->pbn,
> > > > > -false);
> > > > > +   ret = drm_dp_mst_atomic_enable_dsc(state,
> > > > > aconnector->port,
> > > > > +  dm_conn_state-
> > > > > > pbn, false);
> > > > > +   if (ret < 0)
> > > > > +   return ret;
> > > > > +
> > > > > continue;
> > > > > }
> > > > > 
> > > > > @@ -9523,10 +9526,9 @@ static int amdgpu_dm_atomic_check(struct
> > > > > drm_device *dev,
> > > > > 
> > > > >  #if defined(CONFIG_DRM_AMD_DC_DCN)
> > > > > if (dc_resource_is_dsc_encoding_supported(dc)) {
> > > > > -   if (!pre_validate_dsc(state, 

Re: [PATCH v2 1/4] drm/amdgpu/mst: Stop ignoring error codes and deadlocking

[Lyude Paul]

of course, will do in just a moment

On Fri, 2022-11-18 at 14:46 -0500, Alex Deucher wrote:
> I've already picked this up.  Can you send a follow up patch with just
> the coverity fix?
> 
> Alex
> 
> On Fri, Nov 18, 2022 at 2:17 PM Lyude Paul  wrote:
> > 
> > JFYI, Coverity pointed out one more issue with this series so I'm going to
> > send out a respin real quick to fix it. It's just a missing variable
> > assignment (we leave ret unassigned by mistake in
> > pre_compute_mst_dsc_configs()) so I will carry over your r-b on it.
> > 
> > On Wed, 2022-11-16 at 04:39 +, Lin, Wayne wrote:
> > > [Public]
> > > 
> > > All the patch set looks good to me. Feel free to add:
> > > Reviewed-by: Wayne Lin 
> > > 
> > > Again, thank you Lyude for helping on this!!!
> > > 
> > > Regards,
> > > Wayne
> > > > -Original Message-
> > > > From: Lyude Paul 
> > > > Sent: Tuesday, November 15, 2022 6:18 AM
> > > > To: amd-gfx@lists.freedesktop.org
> > > > Cc: Wentland, Harry ; sta...@vger.kernel.org;
> > > > Li, Sun peng (Leo) ; Siqueira, Rodrigo
> > > > ; Deucher, Alexander
> > > > ; Koenig, Christian
> > > > ; Pan, Xinhui ; David
> > > > Airlie ; Daniel Vetter ; Kazlauskas,
> > > > Nicholas ; Pillai, Aurabindo
> > > > ; Li, Roman ; Zuo, Jerry
> > > > ; Wu, Hersen ; Lin, Wayne
> > > > ; Thomas Zimmermann ;
> > > > Mahfooz, Hamza ; Hung, Alex
> > > > ; Mikita Lipski ; Liu,
> > > > Wenjing ; Francis, David
> > > > ; open list:DRM DRIVERS  > > > de...@lists.freedesktop.org>; open list 
> > > > Subject: [PATCH v2 1/4] drm/amdgpu/mst: Stop ignoring error codes and
> > > > deadlocking
> > > > 
> > > > It appears that amdgpu makes the mistake of completely ignoring the 
> > > > return
> > > > values from the DP MST helpers, and instead just returns a simple 
> > > > true/false.
> > > > In this case, it seems to have come back to bite us because as a result 
> > > > of
> > > > simply returning false from compute_mst_dsc_configs_for_state(), amdgpu
> > > > had no way of telling when a deadlock happened from these helpers. This
> > > > could definitely result in some kernel splats.
> > > > 
> > > > V2:
> > > > * Address Wayne's comments (fix another bunch of spots where we weren't
> > > >   passing down return codes)
> > > > 
> > > > Signed-off-by: Lyude Paul 
> > > > Fixes: 8c20a1ed9b4f ("drm/amd/display: MST DSC compute fair share")
> > > > Cc: Harry Wentland 
> > > > Cc:  # v5.6+
> > > > ---
> > > >  .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  18 +-
> > > >  .../display/amdgpu_dm/amdgpu_dm_mst_types.c   | 235 ++--
> > > > --
> > > >  .../display/amdgpu_dm/amdgpu_dm_mst_types.h   |  12 +-
> > > >  3 files changed, 147 insertions(+), 118 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > > > b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > > > index 0db2a88cd4d7b..852a2100c6b38 100644
> > > > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > > > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > > > @@ -6462,7 +6462,7 @@ static int
> > > > dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
> > > > struct drm_connector_state *new_con_state;
> > > > struct amdgpu_dm_connector *aconnector;
> > > > struct dm_connector_state *dm_conn_state;
> > > > -   int i, j;
> > > > +   int i, j, ret;
> > > > int vcpi, pbn_div, pbn, slot_num = 0;
> > > > 
> > > > for_each_new_connector_in_state(state, connector,
> > > > new_con_state, i) { @@ -6509,8 +6509,11 @@ static int
> > > > dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
> > > > dm_conn_state->pbn = pbn;
> > > > dm_conn_state->vcpi_slots = slot_num;
> > > > 
> > > > -   drm_dp_mst_atomic_enable_dsc(state, aconnector-
> > > > > port, dm_conn_state->pbn,
> > > > -false);
> > > > +   ret = drm_dp_mst_atomic_enable_dsc(state,
> > > > aconnector->port,
> > > > +  dm_conn_state-
> > > > > pbn, false);
> > > > +   if (ret < 0)
> > > > +   return ret;
> > > > +
> > > > continue;
> > > > }
> > > > 
> > > > @@ -9523,10 +9526,9 @@ static int amdgpu_dm_atomic_check(struct
> > > > drm_device *dev,
> > > > 
> > > >  #if defined(CONFIG_DRM_AMD_DC_DCN)
> > > > if (dc_resource_is_dsc_encoding_supported(dc)) {
> > > > -   if (!pre_validate_dsc(state, _state, vars)) {
> > > > -   ret = -EINVAL;
> > > > +   ret = pre_validate_dsc(state, _state, vars);
> > > > +   if (ret != 0)
> > > > goto fail;
> > > > -   }
> > > > }
> > > >  #endif
> > > > 
> > > > @@ -9621,9 +9623,9 @@ static int amdgpu_dm_atomic_check(struct
> > > > drm_device *dev,
> > > > }
> > > > 
> > > >  #if defined(CONFIG_DRM_AMD_DC_DCN)
> > > > -   if 

Re: [PATCH v2 1/4] drm/amdgpu/mst: Stop ignoring error codes and deadlocking

[Alex Deucher]

I've already picked this up.  Can you send a follow up patch with just
the coverity fix?

Alex

On Fri, Nov 18, 2022 at 2:17 PM Lyude Paul  wrote:
>
> JFYI, Coverity pointed out one more issue with this series so I'm going to
> send out a respin real quick to fix it. It's just a missing variable
> assignment (we leave ret unassigned by mistake in
> pre_compute_mst_dsc_configs()) so I will carry over your r-b on it.
>
> On Wed, 2022-11-16 at 04:39 +, Lin, Wayne wrote:
> > [Public]
> >
> > All the patch set looks good to me. Feel free to add:
> > Reviewed-by: Wayne Lin 
> >
> > Again, thank you Lyude for helping on this!!!
> >
> > Regards,
> > Wayne
> > > -Original Message-
> > > From: Lyude Paul 
> > > Sent: Tuesday, November 15, 2022 6:18 AM
> > > To: amd-gfx@lists.freedesktop.org
> > > Cc: Wentland, Harry ; sta...@vger.kernel.org;
> > > Li, Sun peng (Leo) ; Siqueira, Rodrigo
> > > ; Deucher, Alexander
> > > ; Koenig, Christian
> > > ; Pan, Xinhui ; David
> > > Airlie ; Daniel Vetter ; Kazlauskas,
> > > Nicholas ; Pillai, Aurabindo
> > > ; Li, Roman ; Zuo, Jerry
> > > ; Wu, Hersen ; Lin, Wayne
> > > ; Thomas Zimmermann ;
> > > Mahfooz, Hamza ; Hung, Alex
> > > ; Mikita Lipski ; Liu,
> > > Wenjing ; Francis, David
> > > ; open list:DRM DRIVERS  > > de...@lists.freedesktop.org>; open list 
> > > Subject: [PATCH v2 1/4] drm/amdgpu/mst: Stop ignoring error codes and
> > > deadlocking
> > >
> > > It appears that amdgpu makes the mistake of completely ignoring the return
> > > values from the DP MST helpers, and instead just returns a simple 
> > > true/false.
> > > In this case, it seems to have come back to bite us because as a result of
> > > simply returning false from compute_mst_dsc_configs_for_state(), amdgpu
> > > had no way of telling when a deadlock happened from these helpers. This
> > > could definitely result in some kernel splats.
> > >
> > > V2:
> > > * Address Wayne's comments (fix another bunch of spots where we weren't
> > >   passing down return codes)
> > >
> > > Signed-off-by: Lyude Paul 
> > > Fixes: 8c20a1ed9b4f ("drm/amd/display: MST DSC compute fair share")
> > > Cc: Harry Wentland 
> > > Cc:  # v5.6+
> > > ---
> > >  .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  18 +-
> > >  .../display/amdgpu_dm/amdgpu_dm_mst_types.c   | 235 ++--
> > > --
> > >  .../display/amdgpu_dm/amdgpu_dm_mst_types.h   |  12 +-
> > >  3 files changed, 147 insertions(+), 118 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > > b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > > index 0db2a88cd4d7b..852a2100c6b38 100644
> > > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > > @@ -6462,7 +6462,7 @@ static int
> > > dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
> > > struct drm_connector_state *new_con_state;
> > > struct amdgpu_dm_connector *aconnector;
> > > struct dm_connector_state *dm_conn_state;
> > > -   int i, j;
> > > +   int i, j, ret;
> > > int vcpi, pbn_div, pbn, slot_num = 0;
> > >
> > > for_each_new_connector_in_state(state, connector,
> > > new_con_state, i) { @@ -6509,8 +6509,11 @@ static int
> > > dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
> > > dm_conn_state->pbn = pbn;
> > > dm_conn_state->vcpi_slots = slot_num;
> > >
> > > -   drm_dp_mst_atomic_enable_dsc(state, aconnector-
> > > > port, dm_conn_state->pbn,
> > > -false);
> > > +   ret = drm_dp_mst_atomic_enable_dsc(state,
> > > aconnector->port,
> > > +  dm_conn_state-
> > > > pbn, false);
> > > +   if (ret < 0)
> > > +   return ret;
> > > +
> > > continue;
> > > }
> > >
> > > @@ -9523,10 +9526,9 @@ static int amdgpu_dm_atomic_check(struct
> > > drm_device *dev,
> > >
> > >  #if defined(CONFIG_DRM_AMD_DC_DCN)
> > > if (dc_resource_is_dsc_encoding_supported(dc)) {
> > > -   if (!pre_validate_dsc(state, _state, vars)) {
> > > -   ret = -EINVAL;
> > > +   ret = pre_validate_dsc(state, _state, vars);
> > > +   if (ret != 0)
> > > goto fail;
> > > -   }
> > > }
> > >  #endif
> > >
> > > @@ -9621,9 +9623,9 @@ static int amdgpu_dm_atomic_check(struct
> > > drm_device *dev,
> > > }
> > >
> > >  #if defined(CONFIG_DRM_AMD_DC_DCN)
> > > -   if (!compute_mst_dsc_configs_for_state(state, dm_state-
> > > > context, vars)) {
> > > +   ret = compute_mst_dsc_configs_for_state(state, dm_state-
> > > > context, vars);
> > > +   if (ret) {
> > >
> > > DRM_DEBUG_DRIVER("compute_mst_dsc_configs_for_state()
> > > failed\n");
> > > -   ret = -EINVAL;
> > > goto fail;
> > > 

[PATCH v3] drm/amdgpu/mst: Stop ignoring error codes and deadlocking

[Lyude Paul]

It appears that amdgpu makes the mistake of completely ignoring the return
values from the DP MST helpers, and instead just returns a simple
true/false. In this case, it seems to have come back to bite us because as
a result of simply returning false from
compute_mst_dsc_configs_for_state(), amdgpu had no way of telling when a
deadlock happened from these helpers. This could definitely result in some
kernel splats.

V2:
* Address Wayne's comments (fix another bunch of spots where we weren't
  passing down return codes)
V3:
* Fix uninitialized var in pre_compute_mst_dsc_configs_for_state()

Signed-off-by: Lyude Paul 
Fixes: 8c20a1ed9b4f ("drm/amd/display: MST DSC compute fair share")
Reviewed-by: Wayne Lin 
Cc: Harry Wentland 
Cc:  # v5.6+
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  18 +-
 .../display/amdgpu_dm/amdgpu_dm_mst_types.c   | 235 ++
 .../display/amdgpu_dm/amdgpu_dm_mst_types.h   |  12 +-
 3 files changed, 147 insertions(+), 118 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 0db2a88cd4d7..852a2100c6b3 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -6462,7 +6462,7 @@ static int dm_update_mst_vcpi_slots_for_dsc(struct 
drm_atomic_state *state,
struct drm_connector_state *new_con_state;
struct amdgpu_dm_connector *aconnector;
struct dm_connector_state *dm_conn_state;
-   int i, j;
+   int i, j, ret;
int vcpi, pbn_div, pbn, slot_num = 0;
 
for_each_new_connector_in_state(state, connector, new_con_state, i) {
@@ -6509,8 +6509,11 @@ static int dm_update_mst_vcpi_slots_for_dsc(struct 
drm_atomic_state *state,
dm_conn_state->pbn = pbn;
dm_conn_state->vcpi_slots = slot_num;
 
-   drm_dp_mst_atomic_enable_dsc(state, aconnector->port, 
dm_conn_state->pbn,
-false);
+   ret = drm_dp_mst_atomic_enable_dsc(state, 
aconnector->port,
+  dm_conn_state->pbn, 
false);
+   if (ret < 0)
+   return ret;
+
continue;
}
 
@@ -9523,10 +9526,9 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
 
 #if defined(CONFIG_DRM_AMD_DC_DCN)
if (dc_resource_is_dsc_encoding_supported(dc)) {
-   if (!pre_validate_dsc(state, _state, vars)) {
-   ret = -EINVAL;
+   ret = pre_validate_dsc(state, _state, vars);
+   if (ret != 0)
goto fail;
-   }
}
 #endif
 
@@ -9621,9 +9623,9 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
}
 
 #if defined(CONFIG_DRM_AMD_DC_DCN)
-   if (!compute_mst_dsc_configs_for_state(state, 
dm_state->context, vars)) {
+   ret = compute_mst_dsc_configs_for_state(state, 
dm_state->context, vars);
+   if (ret) {
DRM_DEBUG_DRIVER("compute_mst_dsc_configs_for_state() 
failed\n");
-   ret = -EINVAL;
goto fail;
}
 
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 6ff96b4bdda5..2f72745660fb 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -703,13 +703,13 @@ static int bpp_x16_from_pbn(struct 
dsc_mst_fairness_params param, int pbn)
return dsc_config.bits_per_pixel;
 }
 
-static bool increase_dsc_bpp(struct drm_atomic_state *state,
-struct drm_dp_mst_topology_state *mst_state,
-struct dc_link *dc_link,
-struct dsc_mst_fairness_params *params,
-struct dsc_mst_fairness_vars *vars,
-int count,
-int k)
+static int increase_dsc_bpp(struct drm_atomic_state *state,
+   struct drm_dp_mst_topology_state *mst_state,
+   struct dc_link *dc_link,
+   struct dsc_mst_fairness_params *params,
+   struct dsc_mst_fairness_vars *vars,
+   int count,
+   int k)
 {
int i;
bool bpp_increased[MAX_PIPES];
@@ -719,6 +719,7 @@ static bool increase_dsc_bpp(struct drm_atomic_state *state,
int remaining_to_increase = 0;
int link_timeslots_used;
int fair_pbn_alloc;
+   int ret = 0;
 
for (i = 0; i < count; i++) {
if (vars[i + k].dsc_enabled) {
@@ -757,52 +758,60 @@ static bool increase_dsc_bpp(struct drm_atomic_state 

Re: [PATCH v2 1/4] drm/amdgpu/mst: Stop ignoring error codes and deadlocking

[Lyude Paul]

JFYI, Coverity pointed out one more issue with this series so I'm going to
send out a respin real quick to fix it. It's just a missing variable
assignment (we leave ret unassigned by mistake in
pre_compute_mst_dsc_configs()) so I will carry over your r-b on it.

On Wed, 2022-11-16 at 04:39 +, Lin, Wayne wrote:
> [Public]
> 
> All the patch set looks good to me. Feel free to add:
> Reviewed-by: Wayne Lin 
> 
> Again, thank you Lyude for helping on this!!!
> 
> Regards,
> Wayne
> > -Original Message-
> > From: Lyude Paul 
> > Sent: Tuesday, November 15, 2022 6:18 AM
> > To: amd-gfx@lists.freedesktop.org
> > Cc: Wentland, Harry ; sta...@vger.kernel.org;
> > Li, Sun peng (Leo) ; Siqueira, Rodrigo
> > ; Deucher, Alexander
> > ; Koenig, Christian
> > ; Pan, Xinhui ; David
> > Airlie ; Daniel Vetter ; Kazlauskas,
> > Nicholas ; Pillai, Aurabindo
> > ; Li, Roman ; Zuo, Jerry
> > ; Wu, Hersen ; Lin, Wayne
> > ; Thomas Zimmermann ;
> > Mahfooz, Hamza ; Hung, Alex
> > ; Mikita Lipski ; Liu,
> > Wenjing ; Francis, David
> > ; open list:DRM DRIVERS  > de...@lists.freedesktop.org>; open list 
> > Subject: [PATCH v2 1/4] drm/amdgpu/mst: Stop ignoring error codes and
> > deadlocking
> > 
> > It appears that amdgpu makes the mistake of completely ignoring the return
> > values from the DP MST helpers, and instead just returns a simple 
> > true/false.
> > In this case, it seems to have come back to bite us because as a result of
> > simply returning false from compute_mst_dsc_configs_for_state(), amdgpu
> > had no way of telling when a deadlock happened from these helpers. This
> > could definitely result in some kernel splats.
> > 
> > V2:
> > * Address Wayne's comments (fix another bunch of spots where we weren't
> >   passing down return codes)
> > 
> > Signed-off-by: Lyude Paul 
> > Fixes: 8c20a1ed9b4f ("drm/amd/display: MST DSC compute fair share")
> > Cc: Harry Wentland 
> > Cc:  # v5.6+
> > ---
> >  .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  18 +-
> >  .../display/amdgpu_dm/amdgpu_dm_mst_types.c   | 235 ++--
> > --
> >  .../display/amdgpu_dm/amdgpu_dm_mst_types.h   |  12 +-
> >  3 files changed, 147 insertions(+), 118 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > index 0db2a88cd4d7b..852a2100c6b38 100644
> > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > @@ -6462,7 +6462,7 @@ static int
> > dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
> > struct drm_connector_state *new_con_state;
> > struct amdgpu_dm_connector *aconnector;
> > struct dm_connector_state *dm_conn_state;
> > -   int i, j;
> > +   int i, j, ret;
> > int vcpi, pbn_div, pbn, slot_num = 0;
> > 
> > for_each_new_connector_in_state(state, connector,
> > new_con_state, i) { @@ -6509,8 +6509,11 @@ static int
> > dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
> > dm_conn_state->pbn = pbn;
> > dm_conn_state->vcpi_slots = slot_num;
> > 
> > -   drm_dp_mst_atomic_enable_dsc(state, aconnector-
> > > port, dm_conn_state->pbn,
> > -false);
> > +   ret = drm_dp_mst_atomic_enable_dsc(state,
> > aconnector->port,
> > +  dm_conn_state-
> > > pbn, false);
> > +   if (ret < 0)
> > +   return ret;
> > +
> > continue;
> > }
> > 
> > @@ -9523,10 +9526,9 @@ static int amdgpu_dm_atomic_check(struct
> > drm_device *dev,
> > 
> >  #if defined(CONFIG_DRM_AMD_DC_DCN)
> > if (dc_resource_is_dsc_encoding_supported(dc)) {
> > -   if (!pre_validate_dsc(state, _state, vars)) {
> > -   ret = -EINVAL;
> > +   ret = pre_validate_dsc(state, _state, vars);
> > +   if (ret != 0)
> > goto fail;
> > -   }
> > }
> >  #endif
> > 
> > @@ -9621,9 +9623,9 @@ static int amdgpu_dm_atomic_check(struct
> > drm_device *dev,
> > }
> > 
> >  #if defined(CONFIG_DRM_AMD_DC_DCN)
> > -   if (!compute_mst_dsc_configs_for_state(state, dm_state-
> > > context, vars)) {
> > +   ret = compute_mst_dsc_configs_for_state(state, dm_state-
> > > context, vars);
> > +   if (ret) {
> > 
> > DRM_DEBUG_DRIVER("compute_mst_dsc_configs_for_state()
> > failed\n");
> > -   ret = -EINVAL;
> > goto fail;
> > }
> > 
> > diff --git
> > a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> > b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> > index 6ff96b4bdda5c..bba2e8aaa2c20 100644
> > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> > +++
> > b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> > @@ -703,13 +703,13 @@ 

Re: [PATCH 3/3] drm/amdgpu: WARN when freeing kernel memory during suspend

[Alex Deucher]

On Wed, Nov 16, 2022 at 11:01 AM Christian König
 wrote:
>
> When buffers are freed during suspend there is no guarantee that
> they can be re-allocated during resume.
>
> The PSP subsystem seems to be quite buggy regarding this, so add
> a WARN_ON() to point out those bugs.
>
> Signed-off-by: Christian König 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> index d0d53e83a318..063bf6f69918 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> @@ -428,6 +428,8 @@ void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 
> *gpu_addr,
> if (*bo == NULL)
> return;
>
> +   WARN_ON(amdgpu_ttm_adev((*bo)->tbo.bdev)->in_suspend);
> +
> if (likely(amdgpu_bo_reserve(*bo, true) == 0)) {
> if (cpu_addr)
> amdgpu_bo_kunmap(*bo);
> --
> 2.34.1
>

Coverity: pre_compute_mst_dsc_configs_for_state(): Uninitialized variables

[coverity-bot]

Hello!

This is an experimental semi-automated report about issues detected by
Coverity from a scan of next-20221118 as part of the linux-next scan project:
https://scan.coverity.com/projects/linux-next-weekly-scan

You're getting this email because you were associated with the identified
lines of code (noted below) that were touched by commits:

  Thu Nov 17 00:18:25 2022 -0500
7cce4cd628be ("drm/amdgpu/mst: Stop ignoring error codes and deadlocking")

Coverity reported the following:

*** CID 1527373:  Uninitialized variables  (UNINIT)
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c:1227 in 
pre_compute_mst_dsc_configs_for_state()
1221for (j = 0; j < dc_state->stream_count; j++) {
1222if (dc_state->streams[j]->link == stream->link)
1223computed_streams[j] = true;
1224}
1225}
1226
vvv CID 1527373:  Uninitialized variables  (UNINIT)
vvv Using uninitialized value "ret".
1227return ret;
1228 }
1229
1230 static int find_crtc_index_in_state_by_stream(struct drm_atomic_state 
*state,
1231  struct dc_stream_state 
*stream)
1232 {

If this is a false positive, please let us know so we can mark it as
such, or teach the Coverity rules to be smarter. If not, please make
sure fixes get into linux-next. :) For patches fixing this, please
include these lines (but double-check the "Fixes" first):

Reported-by: coverity-bot 
Addresses-Coverity-ID: 1527373 ("Uninitialized variables")
Fixes: 7cce4cd628be ("drm/amdgpu/mst: Stop ignoring error codes and 
deadlocking")

If dc_state->stream_count is 0, "ret" is undefined. Perhaps initialize
it as -EINVAL?

Thanks for your attention!

-- 
Coverity-bot

[pull] amdgpu, amdkfd, radeon drm-next-6.2

[Alex Deucher]

Hi Dave, Daniel,

More new stuff for 6.2.  This includes last week's PR, plus the fix
for ARM32, plus a few new things.

The following changes since commit a143bc517bf31c4575191efbaac216a11ec016e0:

  Merge branch '00.06-gr-ampere' of 
https://gitlab.freedesktop.org/skeggsb/nouveau into drm-next (2022-11-09 
11:18:56 +1000)

are available in the Git repository at:

  https://gitlab.freedesktop.org/agd5f/linux.git 
tags/amd-drm-next-6.2-2022-11-18

for you to fetch changes up to aec3bb3a01de09058fbebed4821ed7d07e1ed994:

  drm/amdgpu: make psp_ring_init common (2022-11-17 18:09:16 -0500)


amd-drm-next-6.2-2022-11-18:

amdgpu:
- SR-IOV fixes
- Clean up DC checks
- DCN 3.2.x fixes
- DCN 3.1.x fixes
- Don't enable degamma on asics which don't support it
- IP discovery fixes
- BACO fixes
- Fix vbios allocation handling when vkms is enabled
- Drop buggy tdr advanced mode GPU reset handling
- Fix the build when DCN is not set in kconfig
- MST DSC fixes
- Userptr fixes
- FRU and RAS EEPROM fixes
- VCN 4.x RAS support
- Aldrebaran CU occupancy reporting fix
- PSP ring cleanup

amdkfd:
- Memory limit fix
- Enable cooperative launch on gfx 10.3

amd-drm-next-6.2-2022-11-11:

amdgpu:
- SMU 13.x updates
- GPUVM TLB race fix
- DCN 3.1.4 updates
- DCN 3.2.x updates
- PSR fixes
- Kerneldoc fix
- Vega10 fan fix
- GPUVM locking fixes in error pathes
- BACO fix for Beige Goby
- EEPROM I2C address cleanup
- GFXOFF fix
- Fix DC memory leak in error pathes
- Flexible array updates
- Mtype fix for GPUVM PTEs
- Move Kconfig into amdgpu directory
- SR-IOV updates
- Fix possible memory leak in CS IOCTL error path

amdkfd:
- Fix possible memory overrun
- CRIU fixes

radeon:
- ACPI ref count fix
- HDA audio notifier support
- Move Kconfig into radeon directory

UAPI:
- Add new GEM_CREATE flags to help to transition more KFD functionality to the 
DRM UAPI.
  These are used internally in the driver to align location based memory 
coherency
  requirements from memory allocated in the KFD with how we manage GPUVM PTEs.  
They
  are currently blocked in the GEM_CREATE IOCTL as we don't have a user right 
now.
  They are just used internally in the kernel driver for now for existing KFD 
memory
  allocations. So a change to the UAPI header, but no functional change in the 
UAPI.


Alex Deucher (8):
  drm/amdgpu: use proper DC check in amdgpu_display_supported_domains()
  drm/amdgpu: rework SR-IOV virtual display handling
  drm/amdgpu: move non-DC vblank handling out of irq code
  drm/amdgpu: clarify DC checks
  drm/amdgpu: there is no vbios fb on devices with no display hw (v2)
  drm/amd/display: fix the build when DRM_AMD_DC_DCN is not set
  drm/amdgpu/psp12: move ih_reroute into ring_create
  drm/amdgpu: make psp_ring_init common

Alvin Lee (7):
  drm/amd/display: Wait for VBLANK during pipe programming
  drm/amd/display: Use min transition for SubVP into MPO
  drm/amd/display: Disable phantom OTG after enable for plane disable
  drm/amd/display: Add margin for max vblank time for SubVP + DRR
  drm/amd/display: Use min transition for all SubVP plane add/remove
  drm/amd/display: Don't check output BPP for phantom
  drm/amd/display: Fix Subvp phantom pipe transition

Andrew Davis (1):
  drm: Move radeon and amdgpu Kconfig options into their directories

Anthony Koo (1):
  drm/amd/display: [FW Promotion] Release 0.0.143.0

Aric Cyr (2):
  drm/amd/display: 3.2.211
  drm/amd/display: 3.2.212

Asher Song (1):
  Revert "drm/amdgpu: Revert "drm/amdgpu: getting fan speed pwm for vega10 
properly""

Aurabindo Pillai (3):
  drm/amd/display: Zeromem mypipe heap struct before using it
  drm/amd/display: fix array index out of bound error in bios parser
  drm/amd/display: rework macros for DWB register access

Candice Li (1):
  drm/amdgpu: Add psp_13_0_10_ta firmware to modinfo

Chaitanya Dhere (1):
  drm/amd/display: Fix FCLK deviation and tool compile issues

Charlene Liu (1):
  drm/amd/display: fix dcn3.1x mode validation on high bandwidth config

Christian König (8):
  drm/amdgpu: workaround for TLB seq race
  drm/amdgpu: revert "implement tdr advanced mode"
  drm/amdgpu: stop resubmitting jobs for GPU reset v2
  drm/amdgpu: stop resubmittting jobs in amdgpu_pci_resume
  drm/amdgpu: always register an MMU notifier for userptr
  drm/amdgpu: fix userptr HMM range handling v2
  drm/amdgpu: rename the files for HMM handling
  drm/amdgpu: cleanup amdgpu_hmm_range_get_pages

Dan Carpenter (1):
  amdgpu/pm: prevent array underflow in vega20_odn_edit_dpm_table()

David Galiffi (1):
  drm/amd/display: Update SubVP Visual Confirm

Dillon Varone (7):
  drm/amd/display: Enforce minimum prefetch time for low memclk on DCN32
  drm/amd/display: Program pipes for ODM when removing 

[PATCH 22/22] SWDEV-1 - dc: 3.2.213

[brichang]

From: Aric Cyr 

Signed-off-by: Aric Cyr 

This version brings along following fixes:
-Add configuration 2 for ABM 2.3/2.4.
-Add margin for HUBP for SubVp + DRR.
-Fix no display after resume from WB/CB.
-Limit HW cursor size to be less than 64 x 64 bytes when the stream is >= 4K.
-Lower watermarks for enter/enter+exit latency.
-Update support types for DCN314 to include z8 only and z8_z10 only state.
-Add new value for soc bounding box and dummy pstate.
-Override fclk chang latency when calculating prefetch schedule for subvp with 
low uclk.
-Add check for DET fetch latency for dcn32.
-Add check if PSR enabled when entering MALL.
-Use base MALL allocation size calculations off vewport height.
-Add YCBCR2020 to CSC matrix.
-Implement DP-Tx portion to interact with DPIA.
-Add debug option for increasing phantom lines.
-Fix phantom plane/stream retain after fail validation.
-Fix display corruption with VSR enable.
-Set valid divider value for virtual and FRL/DP2.
-Add new num clk levels struct for max mclk index.
-Fix check for phantom BPP.
-Fix rotated cursor offset calculation.
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index e827cee94e5e..feb7a7f2734e 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -47,7 +47,7 @@ struct aux_payload;
 struct set_config_cmd_payload;
 struct dmub_notification;
 
-#define DC_VER "3.2.212"
+#define DC_VER "3.2.213"
 
 #define MAX_SURFACES 3
 #define MAX_PLANES 6
-- 
2.25.1

[PATCH 19/22] drm/amd/display: Use new num clk levels struct for max mclk index

[brichang]

From: Dillon Varone 

[WHY?]
When calculating watermark and dlg values, the max mclk level index and
associated speed are needed to find the correlated dummy latency value.
Currently the incorrect index is given due to a clock manager refactor.

[HOW?]
Use num_memclk_level from num_entries_per_clk struct for getting the correct max
mem speed.

Reviewed-by: Jun Lei 
Acked-by: Brian Chang 
Signed-off-by: Dillon Varone 
---
 drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index 4222c72f5284..f8260d4d075a 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -1988,7 +1988,7 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct 
dc_state *context,
 
if 
(context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] ==
dm_dram_clock_change_unsupported) {
-   int min_dram_speed_mts_offset = 
dc->clk_mgr->bw_params->clk_table.num_entries - 1;
+   int min_dram_speed_mts_offset = 
dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels - 1;
 
min_dram_speed_mts =

dc->clk_mgr->bw_params->clk_table.entries[min_dram_speed_mts_offset].memclk_mhz 
* 16;
-- 
2.25.1

[PATCH 20/22] drm/amd/display: Revert check for phantom BPP

[brichang]

From: Alvin Lee 

[Description]
Revert change since enabling SubVP on 8K60 single cable
results in corruption

Reviewed-by: Nevenko Stupar 
Reviewed-by: Martin Leung 
Acked-by: Brian Chang 
Signed-off-by: Alvin Lee 
---
 drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
index cb801eace8f4..820042f6aaca 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
@@ -2306,7 +2306,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct 
display_mode_lib *mode_l
&& (mode_lib->vba.Output[k] == dm_dp || 
mode_lib->vba.Output[k] == dm_dp2p0
|| 
mode_lib->vba.Output[k] == dm_edp
|| 
mode_lib->vba.Output[k] == dm_hdmi)
-   && 
mode_lib->vba.OutputBppPerState[i][k] == 0 && 
(mode_lib->vba.UsesMALLForPStateChange[k] != 
dm_use_mall_pstate_change_phantom_pipe)) {
+   && 
mode_lib->vba.OutputBppPerState[i][k] == 0) {
mode_lib->vba.LinkCapacitySupport[i] = false;
}
}
-- 
2.25.1

[PATCH 21/22] drm/amd/display: Fix rotated cursor offset calculation

[brichang]

From: David Galiffi 

[Why]
Underflow is observed when cursor is still enabled when the cursor
rectangle is outside the bounds of it's surface viewport.

[How]
Update parameters used to determine when cursor should be disabled.

Reviewed-by: Martin Leung 
Acked-by: Brian Chang 
Signed-off-by: David Galiffi 
---
 .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c  | 34 +--
 .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c | 28 ++-
 .../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c | 32 +++--
 3 files changed, 64 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
index b9765b3899e1..ef52e6b6eccf 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
@@ -436,34 +436,48 @@ void dpp1_set_cursor_position(
uint32_t height)
 {
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
-   int src_x_offset = pos->x - pos->x_hotspot - param->viewport.x;
-   int src_y_offset = pos->y - pos->y_hotspot - param->viewport.y;
+   int x_pos = pos->x - param->viewport.x;
+   int y_pos = pos->y - param->viewport.y;
+   int x_hotspot = pos->x_hotspot;
+   int y_hotspot = pos->y_hotspot;
+   int src_x_offset = x_pos - pos->x_hotspot;
+   int src_y_offset = y_pos - pos->y_hotspot;
+   int cursor_height = (int)height;
+   int cursor_width = (int)width;
uint32_t cur_en = pos->enable ? 1 : 0;
 
-   // Cursor width/height and hotspots need to be rotated for offset 
calculation
+   // Transform cursor width / height and hotspots for offset calculations
if (param->rotation == ROTATION_ANGLE_90 || param->rotation == 
ROTATION_ANGLE_270) {
-   swap(width, height);
+   swap(cursor_height, cursor_width);
+   swap(x_hotspot, y_hotspot);
+
if (param->rotation == ROTATION_ANGLE_90) {
-   src_x_offset = pos->x - pos->y_hotspot - 
param->viewport.x;
-   src_y_offset = pos->y - pos->x_hotspot - 
param->viewport.y;
+   // hotspot = (-y, x)
+   src_x_offset = x_pos - (cursor_width - x_hotspot);
+   src_y_offset = y_pos - y_hotspot;
+   } else if (param->rotation == ROTATION_ANGLE_270) {
+   // hotspot = (y, -x)
+   src_x_offset = x_pos - x_hotspot;
+   src_y_offset = y_pos - (cursor_height - y_hotspot);
}
} else if (param->rotation == ROTATION_ANGLE_180) {
+   // hotspot = (-x, -y)
if (!param->mirror)
-   src_x_offset = pos->x - param->viewport.x;
+   src_x_offset = x_pos - (cursor_width - x_hotspot);
 
-   src_y_offset = pos->y - param->viewport.y;
+   src_y_offset = y_pos - (cursor_height - y_hotspot);
}
 
if (src_x_offset >= (int)param->viewport.width)
cur_en = 0;  /* not visible beyond right edge*/
 
-   if (src_x_offset + (int)width <= 0)
+   if (src_x_offset + cursor_width <= 0)
cur_en = 0;  /* not visible beyond left edge*/
 
if (src_y_offset >= (int)param->viewport.height)
cur_en = 0;  /* not visible beyond bottom edge*/
 
-   if (src_y_offset + (int)height <= 0)
+   if (src_y_offset + cursor_height <= 0)
cur_en = 0;  /* not visible beyond top edge*/
 
REG_UPDATE(CURSOR0_CONTROL,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
index 52e201e9b091..a142a00bc432 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
@@ -1179,10 +1179,12 @@ void hubp1_cursor_set_position(
const struct dc_cursor_mi_param *param)
 {
struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
-   int src_x_offset = pos->x - pos->x_hotspot - param->viewport.x;
-   int src_y_offset = pos->y - pos->y_hotspot - param->viewport.y;
+   int x_pos = pos->x - param->viewport.x;
+   int y_pos = pos->y - param->viewport.y;
int x_hotspot = pos->x_hotspot;
int y_hotspot = pos->y_hotspot;
+   int src_x_offset = x_pos - pos->x_hotspot;
+   int src_y_offset = y_pos - pos->y_hotspot;
int cursor_height = (int)hubp->curs_attr.height;
int cursor_width = (int)hubp->curs_attr.width;
uint32_t dst_x_offset;
@@ -1200,18 +1202,26 @@ void hubp1_cursor_set_position(
if (hubp->curs_attr.address.quad_part == 0)
return;
 
-   // Rotated cursor width/height and hotspots tweaks for offset 
calculation
+   // Transform cursor width / height and hotspots for offset calculations
if (param->rotation == ROTATION_ANGLE_90 || param->rotation == 

[PATCH 18/22] drm/amd/display: Avoid setting pixel rate divider to N/A

[brichang]

From: Taimur Hassan 

[Why]
Pixel rate divider values should never be set to N/A (0xF) as the K1/K2
field is only 1/2 bits wide.

[How]
Set valid divider values for virtual and FRL/DP2 cases.

Reviewed-by: Nicholas Kazlauskas 
Acked-by: Brian Chang 
Signed-off-by: Taimur Hassan 
---
 drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c  | 7 +++
 drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c | 6 ++
 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c| 4 +++-
 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c   | 4 +---
 4 files changed, 13 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c 
b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c
index 367cb6e6d074..0b769ee71405 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c
@@ -96,6 +96,13 @@ static void dccg314_set_pixel_rate_div(
struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
enum pixel_rate_div cur_k1 = PIXEL_RATE_DIV_NA, cur_k2 = 
PIXEL_RATE_DIV_NA;
 
+   // Don't program 0xF into the register field. Not valid since
+   // K1 / K2 field is only 1 / 2 bits wide
+   if (k1 == PIXEL_RATE_DIV_NA || k2 == PIXEL_RATE_DIV_NA) {
+   BREAK_TO_DEBUGGER();
+   return;
+   }
+
dccg314_get_pixel_rate_div(dccg, otg_inst, _k1, _k2);
if (k1 == cur_k1 && k2 == cur_k2)
return;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c
index 588c1c71241f..a0741794db62 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c
@@ -348,10 +348,8 @@ unsigned int dcn314_calculate_dccg_k1_k2_values(struct 
pipe_ctx *pipe_ctx, unsig
two_pix_per_container = 
optc2_is_two_pixels_per_containter(>timing);
odm_combine_factor = get_odm_config(pipe_ctx, NULL);
 
-   if (pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL)
-   return odm_combine_factor;
-
if (is_dp_128b_132b_signal(pipe_ctx)) {
+   *k1_div = PIXEL_RATE_DIV_BY_1;
*k2_div = PIXEL_RATE_DIV_BY_1;
} else if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) || 
dc_is_dvi_signal(pipe_ctx->stream->signal)) {
*k1_div = PIXEL_RATE_DIV_BY_1;
@@ -359,7 +357,7 @@ unsigned int dcn314_calculate_dccg_k1_k2_values(struct 
pipe_ctx *pipe_ctx, unsig
*k2_div = PIXEL_RATE_DIV_BY_2;
else
*k2_div = PIXEL_RATE_DIV_BY_4;
-   } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
+   } else if (dc_is_dp_signal(pipe_ctx->stream->signal) || 
dc_is_virtual_signal(pipe_ctx->stream->signal)) {
if (two_pix_per_container) {
*k1_div = PIXEL_RATE_DIV_BY_1;
*k2_div = PIXEL_RATE_DIV_BY_2;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c 
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c
index e4daed44ef5f..df4f25119142 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c
@@ -96,8 +96,10 @@ static void dccg32_set_pixel_rate_div(
 
// Don't program 0xF into the register field. Not valid since
// K1 / K2 field is only 1 / 2 bits wide
-   if (k1 == PIXEL_RATE_DIV_NA || k2 == PIXEL_RATE_DIV_NA)
+   if (k1 == PIXEL_RATE_DIV_NA || k2 == PIXEL_RATE_DIV_NA) {
+   BREAK_TO_DEBUGGER();
return;
+   }
 
dccg32_get_pixel_rate_div(dccg, otg_inst, _k1, _k2);
if (k1 == cur_k1 && k2 == cur_k2)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
index 61f129faf251..2f19f711d8be 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
@@ -1175,10 +1175,8 @@ unsigned int dcn32_calculate_dccg_k1_k2_values(struct 
pipe_ctx *pipe_ctx, unsign
two_pix_per_container = 
optc2_is_two_pixels_per_containter(>timing);
odm_combine_factor = get_odm_config(pipe_ctx, NULL);
 
-   if (pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL)
-   return odm_combine_factor;
-
if (is_dp_128b_132b_signal(pipe_ctx)) {
+   *k1_div = PIXEL_RATE_DIV_BY_1;
*k2_div = PIXEL_RATE_DIV_BY_1;
} else if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) || 
dc_is_dvi_signal(pipe_ctx->stream->signal)) {
*k1_div = PIXEL_RATE_DIV_BY_1;
-- 
2.25.1

[PATCH 15/22] drm/amd/display: Add debug options for increasing phantom lines

[brichang]

From: Alvin Lee 

[Description]
- Add debug option for increasing number of phantom lines

Reviewed-by: Nevenko Stupar 
Reviewed-by: Jun Lei 
Acked-by: Brian Chang 
Signed-off-by: Alvin Lee 
---
 drivers/gpu/drm/amd/display/dc/dc.h  | 1 +
 drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index be2a62f4df32..e827cee94e5e 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -852,6 +852,7 @@ struct dc_debug_options {
unsigned int force_subvp_num_ways;
unsigned int force_mall_ss_num_ways;
bool alloc_extra_way_for_cursor;
+   uint32_t subvp_extra_lines;
bool force_usr_allow;
/* uses value at boot and disables switch */
bool disable_dtb_ref_clk_switch;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index c881c523c37a..4222c72f5284 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -585,6 +585,9 @@ void dcn32_set_phantom_stream_timing(struct dc *dc,
num_dpp = 
vba->NoOfDPP[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]];
phantom_vactive += num_dpp > 1 ? 
vba->meta_row_height[vba->pipe_plane[pipe_idx]] : 0;
 
+   /* dc->debug.subvp_extra_lines 0 by default*/
+   phantom_vactive += dc->debug.subvp_extra_lines;
+
// For backporch of phantom pipe, use vstartup of the main pipe
phantom_bp = get_vstartup(>bw_ctx.dml, pipes, pipe_cnt, 
pipe_idx);
 
-- 
2.25.1

[PATCH 14/22] drm/amd/display: No display after resume from WB/CB[modify]

[brichang]

From: Tsung-hua Lin 

[why]
First MST sideband message returns AUX_RET_ERROR_HPD_DISCON
on certain intel platform. Aux transaction considered failure
if HPD unexpected pulled low. The actual aux transaction success
in such case, hence do not return error.

[how]
Not returning error when AUX_RET_ERROR_HPD_DISCON detected
on the first sideband message.

Reviewed-by: Jerry Zuo 
Acked-by: Brian Chang 
Signed-off-by: tsunglin 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 9 +
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 5b97723ff6fa..eff14e978e90 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1372,7 +1372,7 @@ static const struct dmi_system_id 
hpd_disconnect_quirk_table[] = {
{
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
-   DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower 7010 Plus"),
+   DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower Plus 7010"),
},
},
{
@@ -1384,7 +1384,7 @@ static const struct dmi_system_id 
hpd_disconnect_quirk_table[] = {
{
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
-   DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF 7010 Plus"),
+   DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF Plus 7010"),
},
},
{
@@ -1396,16 +1396,17 @@ static const struct dmi_system_id 
hpd_disconnect_quirk_table[] = {
{
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
-   DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex MFF 7010 Plus"),
+   DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro Plus 7010"),
},
},
{
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
-   DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex MFF 7010"),
+   DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro 7010"),
},
},
{}
+   /* TODO: refactor this from a fixed table to a dynamic option */
 };
 
 static void retrieve_dmi_info(struct amdgpu_display_manager *dm)
-- 
2.25.1

[PATCH 17/22] drm/amd/display: Fix display corruption w/ VSR enable

[brichang]

From: Ilya Bakoulin 

[Why]
Brief corruption is observed on hotplug/unplug with certain display
configurations when VSR is enabled.

[How]
Work around the issue by avoiding 2to1 ODM when stream plane_count is 0.

Reviewed-by: Dillon Varone 
Acked-by: Brian Chang 
Signed-off-by: Ilya Bakoulin 
---
 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
index 827eef7e1787..99ddd2232322 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
@@ -1924,7 +1924,7 @@ int dcn32_populate_dml_pipes_from_context(
 
pipes[pipe_cnt].pipe.dest.odm_combine_policy = 
dm_odm_combine_policy_dal;
if (context->stream_count == 1 &&
-   context->stream_status[0].plane_count <= 1 &&
+   context->stream_status[0].plane_count == 1 &&

!dc_is_hdmi_signal(res_ctx->pipe_ctx[i].stream->signal) &&

is_h_timing_divisible_by_2(res_ctx->pipe_ctx[i].stream) &&
pipe->stream->timing.pix_clk_100hz * 100 > 
DCN3_2_VMIN_DISPCLK_HZ &&
-- 
2.25.1

[PATCH 11/22] drm/amd/display: Use viewport height for subvp mall allocation size

[brichang]

From: Dillon Varone 

[WHY?]
MALL allocation size depends on the viewport height, not the addressable
vertical lines, which will not match when scaling.

[HOW?]
Base MALL allocation size calculations off viewport height.

Reviewed-by: Alvin Lee 
Reviewed-by: Martin Leung 
Acked-by: Brian Chang 
Signed-off-by: Dillon Varone 
---
 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c 
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
index b03a7814e96d..fa3778849db1 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
@@ -111,7 +111,7 @@ uint32_t dcn32_helper_calculate_num_ways_for_subvp(struct 
dc *dc, struct dc_stat
mall_alloc_width_blk_aligned = 
full_vp_width_blk_aligned;
 
/* mall_alloc_height_blk_aligned_l/c = 
CEILING(sub_vp_height_l/c - 1, blk_height_l/c) + blk_height_l/c */
-   mall_alloc_height_blk_aligned = 
(pipe->stream->timing.v_addressable - 1 + mblk_height - 1) /
+   mall_alloc_height_blk_aligned = 
(pipe->plane_res.scl_data.viewport.height - 1 + mblk_height - 1) /
mblk_height * mblk_height + mblk_height;
 
/* full_mblk_width_ub_l/c = 
mall_alloc_width_blk_aligned_l/c;
-- 
2.25.1

[PATCH 16/22] drm/amd/display: Retain phantom plane/stream if validation fails

[brichang]

From: Alvin Lee 

[Description]
- If we fail validation, we should retain the phantom
  stream/planes
- Full updates assume that phantom pipes will be fully
  removed, but if validation fails we keep the phantom
  pipes
- Therefore we have to retain the plane/stream if validation
  fails (since the refcount is decremented before validation,
  and the expectation is that it's fully freed when the  old
  dc_state is released)

Reviewed-by: Jun Lei 
Acked-by: Brian Chang 
Signed-off-by: Alvin Lee 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c  | 13 +++
 .../drm/amd/display/dc/dcn32/dcn32_resource.c | 22 +++
 .../drm/amd/display/dc/dcn32/dcn32_resource.h |  3 +++
 .../amd/display/dc/dcn321/dcn321_resource.c   |  1 +
 .../gpu/drm/amd/display/dc/inc/core_types.h   |  1 +
 5 files changed, 40 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 42840ce9bf4b..4aec13f0d5ca 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -3098,6 +3098,19 @@ static bool update_planes_and_stream_state(struct dc *dc,
 
if (update_type == UPDATE_TYPE_FULL) {
if (!dc->res_pool->funcs->validate_bandwidth(dc, context, 
false)) {
+   /* For phantom pipes we remove and create a new set of 
phantom pipes
+* for each full update (because we don't know if we'll 
need phantom
+* pipes until after the first round of validation). 
However, if validation
+* fails we need to keep the existing phantom pipes 
(because we don't update
+* the dc->current_state).
+*
+* The phantom stream/plane refcount is decremented for 
validation because
+* we assume it'll be removed (the free comes when the 
dc_state is freed),
+* but if validation fails we have to increment back 
the refcount so it's
+* consistent.
+*/
+   if (dc->res_pool->funcs->retain_phantom_pipes)
+   dc->res_pool->funcs->retain_phantom_pipes(dc, 
dc->current_state);
BREAK_TO_DEBUGGER();
goto fail;
}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
index c40dccef6843..827eef7e1787 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
@@ -1721,6 +1721,27 @@ static struct dc_stream_state 
*dcn32_enable_phantom_stream(struct dc *dc,
return phantom_stream;
 }
 
+void dcn32_retain_phantom_pipes(struct dc *dc, struct dc_state *context)
+{
+   int i;
+   struct dc_plane_state *phantom_plane = NULL;
+   struct dc_stream_state *phantom_stream = NULL;
+
+   for (i = 0; i < dc->res_pool->pipe_count; i++) {
+   struct pipe_ctx *pipe = >res_ctx.pipe_ctx[i];
+
+   if (!pipe->top_pipe && !pipe->prev_odm_pipe &&
+   pipe->plane_state && pipe->stream &&
+   pipe->stream->mall_stream_config.type == 
SUBVP_PHANTOM) {
+   phantom_plane = pipe->plane_state;
+   phantom_stream = pipe->stream;
+
+   dc_plane_state_retain(phantom_plane);
+   dc_stream_retain(phantom_stream);
+   }
+   }
+}
+
 // return true if removed piped from ctx, false otherwise
 bool dcn32_remove_phantom_pipes(struct dc *dc, struct dc_state *context)
 {
@@ -2033,6 +2054,7 @@ static struct resource_funcs dcn32_res_pool_funcs = {
.update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
.add_phantom_pipes = dcn32_add_phantom_pipes,
.remove_phantom_pipes = dcn32_remove_phantom_pipes,
+   .retain_phantom_pipes = dcn32_retain_phantom_pipes,
 };
 
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h 
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h
index f6bc9bd5da31..c50bb34b515f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h
@@ -83,6 +83,9 @@ bool dcn32_release_post_bldn_3dlut(
 bool dcn32_remove_phantom_pipes(struct dc *dc,
struct dc_state *context);
 
+void dcn32_retain_phantom_pipes(struct dc *dc,
+   struct dc_state *context);
+
 void dcn32_add_phantom_pipes(struct dc *dc,
struct dc_state *context,
display_e2e_pipe_params_st *pipes,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
index 06f144189e9d..b66fe62cbd99 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
+++ 

[PATCH 10/22] drm/amd/display: Check if PSR enabled when entering MALL

[brichang]

From: Alvin Lee 

[Description]
- When attempting to enter MALL SS when a PSR panel
  is connected, we have to check that the PSR panel
  has already entered PSR because the vsync interrupt
  call is per display index (can be called for the
  non-PSR panel first)
- Also don't override link settings when programming
  phantom stream (main and phantom pipe share the same link)

Reviewed-by: Jun Lei 
Acked-by: Brian Chang 
Signed-off-by: Alvin Lee 
---
 .../gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c  | 9 +++--
 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c   | 7 ++-
 2 files changed, 13 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index c5380ce70653..913a1fe6b3da 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1561,8 +1561,13 @@ static enum dc_status apply_single_controller_ctx_to_hw(
 
pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe 
!= NULL;
 
-   pipe_ctx->stream->link->psr_settings.psr_feature_enabled = false;
-
+   /* Phantom and main stream share the same link (because the stream
+* is constructed with the same sink). Make sure not to override
+* and link programming on the main.
+*/
+   if (pipe_ctx->stream->mall_stream_config.type != SUBVP_PHANTOM) {
+   pipe_ctx->stream->link->psr_settings.psr_feature_enabled = 
false;
+   }
return DC_OK;
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
index 763311ffb967..61f129faf251 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
@@ -227,8 +227,13 @@ static uint32_t dcn32_calculate_cab_allocation(struct dc 
*dc, struct dc_state *c
for (i = 0; i < dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe = >current_state->res_ctx.pipe_ctx[i];
 
+   /* If PSR is supported on an eDP panel that's connected, but 
that panel is
+* not in PSR at the time of trying to enter MALL SS, we have 
to include it
+* in the static screen CAB calculation
+*/
if (!pipe->stream || !pipe->plane_state ||
-   pipe->stream->link->psr_settings.psr_version != 
DC_PSR_VERSION_UNSUPPORTED ||
+   (pipe->stream->link->psr_settings.psr_version 
!= DC_PSR_VERSION_UNSUPPORTED &&
+   
pipe->stream->link->psr_settings.psr_allow_active) ||
pipe->stream->mall_stream_config.type == 
SUBVP_PHANTOM)
continue;
 
-- 
2.25.1

[PATCH 13/22] drm/amd/display: Phase 1 Add Bw Allocation source and header files

[brichang]

From: Mustapha Ghaddar 

[WHY]
To implement BW Allocation as per USB4 spec chapter 10.7

[HOW]
Implement the DP-Tx portion of the logic to interact with DPIA

Reviewed-by: Wenjing Liu 
Reviewed-by: Jun Lei 
Acked-by: Brian Chang 
Signed-off-by: Mustapha Ghaddar 
---
 drivers/gpu/drm/amd/display/dc/dc_link.h  | 14 
 .../drm/amd/display/dc/link/link_dp_dpia_bw.c | 28 
 .../drm/amd/display/dc/link/link_dp_dpia_bw.h | 69 +++
 3 files changed, 111 insertions(+)
 create mode 100644 drivers/gpu/drm/amd/display/dc/link/link_dp_dpia_bw.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/link/link_dp_dpia_bw.h

diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h 
b/drivers/gpu/drm/amd/display/dc/dc_link.h
index dc6afe33bca2..2e18bcf6b11a 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_link.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
@@ -151,6 +151,20 @@ struct dc_panel_config {
bool optimize_edp_link_rate; /* eDP ILR */
} ilr;
 };
+
+/*
+ *  USB4 DPIA BW ALLOCATION STRUCTS
+ */
+struct dc_dpia_bw_alloc {
+   int sink_verified_bw;  // The Verified BW that sink can allocated and 
use that has been verified already
+   int sink_allocated_bw; // The Actual Allocated BW that sink currently 
allocated
+   int padding_bw;// The Padding "Un-used" BW allocated by CM for 
padding reasons
+   int sink_max_bw;   // The Max BW that sink can require/support
+   int estimated_bw;  // The estimated available BW for this DPIA
+   int bw_granularity;// BW Granularity
+   bool bw_alloc_enabled; // The BW Alloc Mode Support is turned ON for 
all 3:  DP-Tx & Dpia & CM
+};
+
 /*
  * A link contains one or more sinks and their connected status.
  * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported.
diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dp_dpia_bw.c 
b/drivers/gpu/drm/amd/display/dc/link/link_dp_dpia_bw.c
new file mode 100644
index ..801a95b34e8c
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/link/link_dp_dpia_bw.c
@@ -0,0 +1,28 @@
+
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+/*/
+// USB4 DPIA BANDWIDTH ALLOCATION LOGIC
+/*/
diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dp_dpia_bw.h 
b/drivers/gpu/drm/amd/display/dc/link/link_dp_dpia_bw.h
new file mode 100644
index ..669e995f825f
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/link/link_dp_dpia_bw.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef DC_INC_LINK_DP_DPIA_BW_H_
+#define 

[PATCH 12/22] drm/amd/display: Add YCBCR2020 coefficients to CSC matrix

[brichang]

From: Rodrigo Siqueira 

When some of the IGT tests are executed in DCN31, it is possible to see
multiple occurrences of this warning:

 WARNING: CPU: 9 PID: 3482 at
 drivers/gpu/drm/amd/amdgpu/../dal-dev/dc/dcn30/dcn30_dpp.c:154
 dpp3_program_post_csc+0x196/0x220 [amdgpu]
 [..]
 PU: 9 PID: 3482 Comm: amd_hdr Tainted: G   W5.18.0+ #3
 IP: 0010:dpp3_program_post_csc+0x196/0x220 [amdgpu]
 [..]
 all Trace:
 
 dpp3_cnv_setup+0x5d9/0x5f0 [amdgpu]
 ? dcn20_blank_pixel_data+0x30a/0x330 [amdgpu]
 dcn20_program_pipe+0x259/0xb40 [amdgpu]
 ? offset_to_id+0x1b0/0x1c0 [amdgpu]
 dcn20_program_front_end_for_ctx+0x36a/0x450 [amdgpu]
 commit_planes_for_stream+0x8eb/0x13e0 [amdgpu]

This commit fix the above issue by adding YCBCR2020 coefficients to the
DPP Color Space Converter (CSC) matrix.

Reviewed-by: Nawwar Ali 
Acked-by: Brian Chang 
Signed-off-by: Rodrigo Siqueira 
---
 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h | 9 +++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h 
b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
index dcb80c4747b0..131fcfa28bca 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
@@ -83,10 +83,15 @@ static const struct dpp_input_csc_matrix __maybe_unused 
dpp_input_csc_matrix[] =
{COLOR_SPACE_YCBCR709,
{0x3265, 0x2000, 0, 0xe6ce, 0xf105, 0x2000, 0xfa01, 0xa7d, 0,
0x2000, 0x3b61, 0xe24f} },
-
{COLOR_SPACE_YCBCR709_LIMITED,
{0x39a6, 0x2568, 0, 0xe0d6, 0xeedd, 0x2568, 0xf925, 0x9a8, 0,
-   0x2568, 0x43ee, 0xdbb2} }
+   0x2568, 0x43ee, 0xdbb2} },
+   {COLOR_SPACE_2020_YCBCR,
+   {0x2F30, 0x2000, 0, 0xE869, 0xEDB7, 0x2000, 0xFABC, 0xBC6, 0,
+   0x2000, 0x3C34, 0xE1E6} },
+   {COLOR_SPACE_2020_RGB_LIMITEDRANGE,
+   {0x35E0, 0x255F, 0, 0xE2B3, 0xEB20, 0x255F, 0xF9FD, 0xB1E, 0,
+   0x255F, 0x44BD, 0xDB43} }
 };
 
 struct dpp_grph_csc_adjustment {
-- 
2.25.1

[PATCH 09/22] drm/amd/display: Add check for DET fetch latency hiding for dcn32

[brichang]

From: Dillon Varone 

[WHY?]
Some configurations are constructed with very marginal DET buffers relative to
the worst possible time required to fetch a swath.

[HOW?]
Add a check to see that the DET buffer allocated for each pipe can hide the
latency for all pipes to fetch at least one swath.

Reviewed-by: Alvin Lee 
Reviewed-by: Jun Lei 
Acked-by: Brian Chang 
Signed-off-by: Dillon Varone 
---
 .../dc/dml/dcn32/display_mode_vba_32.c| 39 +++
 .../dc/dml/dcn32/display_mode_vba_util_32.c   | 69 +++
 .../dc/dml/dcn32/display_mode_vba_util_32.h   | 18 +
 .../drm/amd/display/dc/dml/display_mode_vba.h |  2 +
 4 files changed, 128 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
index e5c8f6a71b5b..cb801eace8f4 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
@@ -670,6 +670,25 @@ static void 
DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
v->cursor_bw[k] = mode_lib->vba.NumberOfCursors[k] * 
mode_lib->vba.CursorWidth[k][0] * mode_lib->vba.CursorBPP[k][0] / 8 / 
(mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * 
mode_lib->vba.VRatio[k];
}
 
+   v->NotEnoughDETSwathFillLatencyHiding = 
dml32_CalculateDETSwathFillLatencyHiding(
+   
mode_lib->vba.NumberOfActiveSurfaces,
+   mode_lib->vba.ReturnBW,
+   v->UrgentLatency,
+   mode_lib->vba.SwathHeightY,
+   mode_lib->vba.SwathHeightC,
+   v->swath_width_luma_ub,
+   v->swath_width_chroma_ub,
+   v->BytePerPixelDETY,
+   v->BytePerPixelDETC,
+   mode_lib->vba.DETBufferSizeY,
+   mode_lib->vba.DETBufferSizeC,
+   mode_lib->vba.DPPPerPlane,
+   mode_lib->vba.HTotal,
+   mode_lib->vba.PixelClock,
+   mode_lib->vba.VRatio,
+   mode_lib->vba.VRatioChroma,
+   
mode_lib->vba.UsesMALLForPStateChange);
+
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
v->MaxVStartupLines[k] = ((mode_lib->vba.Interlace[k] &&
!mode_lib->vba.ProgressiveToInterlaceUnitInOPP) 
?
@@ -1664,6 +1683,7 @@ static void mode_support_configuration(struct vba_vars_st 
*v,
&& mode_lib->vba.PTEBufferSizeNotExceeded[i][j] 
== true
&& 
mode_lib->vba.DCCMetaBufferSizeNotExceeded[i][j] == true
&& mode_lib->vba.NonsupportedDSCInputBPC == 
false
+   && 
mode_lib->vba.NotEnoughDETSwathFillLatencyHidingPerState[i][j] == false
&& !mode_lib->vba.ExceededMALLSize
&& ((mode_lib->vba.HostVMEnable == false
&& !mode_lib->vba.ImmediateFlipRequiredFinal)
@@ -3158,6 +3178,25 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct 
display_mode_lib *mode_l
mode_lib->vba.UrgentBurstFactorChroma,
mode_lib->vba.UrgentBurstFactorCursor);
 
+   
mode_lib->vba.NotEnoughDETSwathFillLatencyHidingPerState[i][j] = 
dml32_CalculateDETSwathFillLatencyHiding(
+   mode_lib->vba.NumberOfActiveSurfaces,
+   mode_lib->vba.ReturnBWPerState[i][j],
+   mode_lib->vba.UrgLatency[i],
+   mode_lib->vba.SwathHeightYThisState,
+   mode_lib->vba.SwathHeightCThisState,
+   
mode_lib->vba.swath_width_luma_ub_this_state,
+   
mode_lib->vba.swath_width_chroma_ub_this_state,
+   mode_lib->vba.BytePerPixelInDETY,
+   mode_lib->vba.BytePerPixelInDETC,
+   mode_lib->vba.DETBufferSizeYThisState,
+   mode_lib->vba.DETBufferSizeCThisState,
+   mode_lib->vba.NoOfDPPThisState,
+   

[PATCH 07/22] drm/amd/display: Update soc bounding box for dcn32/dcn321

[brichang]

From: Dillon Varone 

[Description]
New values for soc bounding box and dummy pstate.

Reviewed-by: Jun Lei 
Acked-by: Brian Chang 
Signed-off-by: Dillon Varone 
---
 drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c   | 6 +++---
 drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c | 8 
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index 97b333b230d1..61dbfa95eaa4 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -157,7 +157,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_2_soc = {
.dispclk_dppclk_vco_speed_mhz = 4300.0,
.do_urgent_latency_adjustment = true,
.urgent_latency_adjustment_fabric_clock_component_us = 1.0,
-   .urgent_latency_adjustment_fabric_clock_reference_mhz = 1000,
+   .urgent_latency_adjustment_fabric_clock_reference_mhz = 3000,
 };
 
 void dcn32_build_wm_range_table_fpu(struct clk_mgr_internal *clk_mgr)
@@ -211,7 +211,7 @@ void dcn32_build_wm_range_table_fpu(struct clk_mgr_internal 
*clk_mgr)
/* 'DalDummyClockChangeLatencyNs' registry key option set to 0x7FFF 
can be used to disable Set C for dummy p-state */
if (clk_mgr->base.ctx->dc->bb_overrides.dummy_clock_change_latency_ns 
!= 0x7FFF) {
clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].valid = true;
-   
clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us 
= 38;
+   
clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us 
= 50;

clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.fclk_change_latency_us
 = fclk_change_latency_us;

clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us = 
sr_exit_time_us;

clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us
 = sr_enter_plus_exit_time_us;
@@ -221,7 +221,7 @@ void dcn32_build_wm_range_table_fpu(struct clk_mgr_internal 
*clk_mgr)

clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_uclk = 
min_uclk_mhz;

clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_uclk = 
0x;
clk_mgr->base.bw_params->dummy_pstate_table[0].dram_speed_mts = 
clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz * 16;
-   
clk_mgr->base.bw_params->dummy_pstate_table[0].dummy_pstate_latency_us = 38;
+   
clk_mgr->base.bw_params->dummy_pstate_table[0].dummy_pstate_latency_us = 50;
clk_mgr->base.bw_params->dummy_pstate_table[1].dram_speed_mts = 
clk_mgr->base.bw_params->clk_table.entries[1].memclk_mhz * 16;

clk_mgr->base.bw_params->dummy_pstate_table[1].dummy_pstate_latency_us = 9;
clk_mgr->base.bw_params->dummy_pstate_table[2].dram_speed_mts = 
clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz * 16;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
index 432b4ecd01a7..f4b176599be7 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
@@ -126,9 +126,9 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_21_soc = {
.sr_enter_plus_exit_z8_time_us = 320,
.writeback_latency_us = 12.0,
.round_trip_ping_latency_dcfclk_cycles = 263,
-   .urgent_latency_pixel_data_only_us = 9.35,
-   .urgent_latency_pixel_mixed_with_vm_data_us = 9.35,
-   .urgent_latency_vm_data_only_us = 9.35,
+   .urgent_latency_pixel_data_only_us = 4,
+   .urgent_latency_pixel_mixed_with_vm_data_us = 4,
+   .urgent_latency_vm_data_only_us = 4,
.fclk_change_latency_us = 20,
.usr_retraining_latency_us = 2,
.smn_latency_us = 2,
@@ -156,7 +156,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_21_soc = {
.dispclk_dppclk_vco_speed_mhz = 4300.0,
.do_urgent_latency_adjustment = true,
.urgent_latency_adjustment_fabric_clock_component_us = 1.0,
-   .urgent_latency_adjustment_fabric_clock_reference_mhz = 1000,
+   .urgent_latency_adjustment_fabric_clock_reference_mhz = 3000,
 };
 
 static void get_optimal_ntuple(struct _vcs_dpi_voltage_scaling_st *entry)
-- 
2.25.1

[PATCH 08/22] drm/amd/display: Use dummy pstate latency for subvp when needed on dcn32

[brichang]

From: Dillon Varone 

[WHY?]
Prefetch is not budgetting time for dummy pstate when using subvp and low uclk.

[HOW?]
Override fclk change latency to use dummy pstate latency when calculating
prefetch schedule for subvp configs with low uclk.

Reviewed-by: Jun Lei 
Acked-by: Brian Chang 
Signed-off-by: Dillon Varone 
---
 .../drm/amd/display/dc/dml/dcn32/dcn32_fpu.c  | 61 +++
 1 file changed, 49 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index 61dbfa95eaa4..c881c523c37a 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -256,16 +256,24 @@ int 
dcn32_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc,
int vlevel)
 {
const int max_latency_table_entries = 4;
-   const struct vba_vars_st *vba = >bw_ctx.dml.vba;
+   struct vba_vars_st *vba = >bw_ctx.dml.vba;
int dummy_latency_index = 0;
+   enum clock_change_support temp_clock_change_support = 
vba->DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
 
dc_assert_fp_enabled();
 
while (dummy_latency_index < max_latency_table_entries) {
+   if (temp_clock_change_support != 
dm_dram_clock_change_unsupported)
+   
vba->DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] = 
temp_clock_change_support;
context->bw_ctx.dml.soc.dram_clock_change_latency_us =

dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;
dcn32_internal_validate_bw(dc, context, pipes, _cnt, 
, false);
 
+   /* for subvp + DRR case, if subvp pipes are still present we 
support pstate */
+   if (vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == 
dm_dram_clock_change_unsupported &&
+   dcn32_subvp_in_use(dc, context))
+   
vba->DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] = 
temp_clock_change_support;
+
if (vlevel < context->bw_ctx.dml.vba.soc.num_states &&

vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] != 
dm_dram_clock_change_unsupported)
break;
@@ -1141,7 +1149,7 @@ static void dcn32_full_validate_bw_helper(struct dc *dc,

context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final ==

dm_prefetch_support_uclk_fclk_and_stutter) {

context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final =
-   
dm_prefetch_support_stutter;
+   
dm_prefetch_support_fclk_and_stutter;
/* There are params (such as FabricClock) that 
need to be recalculated
 * after validation fails (otherwise it will be 
0). Calculation for
 * phantom vactive requires call into DML, so 
we must ensure all the
@@ -1816,14 +1824,38 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, 
struct dc_state *context,
unsigned int dummy_latency_index = 0;
int maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb;
unsigned int min_dram_speed_mts = context->bw_ctx.dml.vba.DRAMSpeed;
+   bool subvp_in_use = dcn32_subvp_in_use(dc, context);
unsigned int min_dram_speed_mts_margin;
+   bool need_fclk_lat_as_dummy = false;
+   bool is_subvp_p_drr = true;
 
dc_assert_fp_enabled();
 
-   // Override DRAMClockChangeSupport for SubVP + DRR case where the DRR 
cannot switch without stretching it's VBLANK
-   if (!pstate_en && dcn32_subvp_in_use(dc, context)) {
-   
context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]
 = dm_dram_clock_change_vblank_w_mall_sub_vp;
-   pstate_en = true;
+   /* need to find dummy latency index for subvp */
+   if (subvp_in_use) {
+   /* Override DRAMClockChangeSupport for SubVP + DRR case where 
the DRR cannot switch without stretching it's VBLANK */
+   if (!pstate_en) {
+   
context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]
 = dm_dram_clock_change_vblank_w_mall_sub_vp;
+   pstate_en = true;
+   is_subvp_p_drr = true;
+   }
+   dummy_latency_index = 
dcn32_find_dummy_latency_index_for_fw_based_mclk_switch(dc,
+   context, pipes, pipe_cnt, 
vlevel);
+
+   /* For DCN32/321 need to validate with fclk pstate change 
latency 

[PATCH 05/22] drm/amd/display: Update Z8 watermarks for DCN314

[brichang]

From: Nicholas Kazlauskas 

[Why & How]
Update from HW, need to lower watermarks for enter/enter+exit latency.

Reviewed-by: Jun Lei 
Acked-by: Brian Chang 
Signed-off-by: Nicholas Kazlauskas 
---
 drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c
index 1dd51c4b6804..6a1cf6adea77 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c
@@ -149,8 +149,8 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_14_soc = {
.num_states = 5,
.sr_exit_time_us = 16.5,
.sr_enter_plus_exit_time_us = 18.5,
-   .sr_exit_z8_time_us = 442.0,
-   .sr_enter_plus_exit_z8_time_us = 560.0,
+   .sr_exit_z8_time_us = 280.0,
+   .sr_enter_plus_exit_z8_time_us = 350.0,
.writeback_latency_us = 12.0,
.dram_channel_width_bytes = 4,
.round_trip_ping_latency_dcfclk_cycles = 106,
-- 
2.25.1

[PATCH 06/22] drm/amd/display: Add Z8 allow states to z-state support list

[brichang]

From: Nicholas Kazlauskas 

[Why]
Even if we block Z9 based on crossover threshold it's possible to
allow for Z8.

[How]
There's support for this on DCN314, so update the support types to
include a z8 only and z8_z10 only state.

Update the decide_zstate_support function to allow for specifying
these modes based on the Z8 threshold.

DCN31 has z-state disabled, but still update the legacy code to
map z8_only = disallow and z10_z8_only = z10_only to keep the support
the same.

Reviewed-by: Jun Lei 
Acked-by: Brian Chang 
Signed-off-by: Nicholas Kazlauskas 
---
 .../gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c |  4 ++--
 .../drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c   | 12 ++--
 drivers/gpu/drm/amd/display/dc/dc.h  |  2 ++
 drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 12 +---
 4 files changed, 23 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
index 090b2c02aee1..0827c7df2855 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
@@ -333,8 +333,8 @@ void dcn31_smu_set_zstate_support(struct clk_mgr_internal 
*clk_mgr, enum dcn_zst
(support == DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY))
support = DCN_ZSTATE_SUPPORT_DISALLOW;
 
-
-   if (support == DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY)
+   if (support == DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY ||
+   support == DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY)
param = 1;
else
param = 0;
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c
index ef0795b14a1f..88fbc5aabc74 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c
@@ -339,8 +339,6 @@ void dcn314_smu_set_zstate_support(struct clk_mgr_internal 
*clk_mgr, enum dcn_zs
if (!clk_mgr->smu_present)
return;
 
-   // Arg[15:0] = 8/9/0 for Z8/Z9/disallow -> existing bits
-   // Arg[16] = Disallow Z9 -> new bit
switch (support) {
 
case DCN_ZSTATE_SUPPORT_ALLOW:
@@ -359,6 +357,16 @@ void dcn314_smu_set_zstate_support(struct clk_mgr_internal 
*clk_mgr, enum dcn_zs
param = (1 << 10);
break;
 
+   case DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY:
+   msg_id = VBIOSSMC_MSG_AllowZstatesEntry;
+   param = (1 << 10) | (1 << 8);
+   break;
+
+   case DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY:
+   msg_id = VBIOSSMC_MSG_AllowZstatesEntry;
+   param = (1 << 8);
+   break;
+
default: //DCN_ZSTATE_SUPPORT_UNKNOWN
msg_id = VBIOSSMC_MSG_AllowZstatesEntry;
param = 0;
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 1f6dff9904f3..be2a62f4df32 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -493,6 +493,8 @@ enum dcn_pwr_state {
 enum dcn_zstate_support_state {
DCN_ZSTATE_SUPPORT_UNKNOWN,
DCN_ZSTATE_SUPPORT_ALLOW,
+   DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY,
+   DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY,
DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY,
DCN_ZSTATE_SUPPORT_DISALLOW,
 };
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
index 75dbb7ee193b..c4eca10587a6 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
@@ -949,6 +949,7 @@ static enum dcn_zstate_support_state  
decide_zstate_support(struct dc *dc, struc
int plane_count;
int i;
unsigned int optimized_min_dst_y_next_start_us;
+   bool allow_z8 = context->bw_ctx.dml.vba.StutterPeriod > 1000.0;
 
plane_count = 0;
optimized_min_dst_y_next_start_us = 0;
@@ -963,6 +964,8 @@ static enum dcn_zstate_support_state  
decide_zstate_support(struct dc *dc, struc
 *  2. single eDP, on link 0, 1 plane and stutter period > 5ms
 * Z10 only cases:
 *  1. single eDP, on link 0, 1 plane and stutter period >= 5ms
+* Z8 cases:
+*  1. stutter period sufficient
 * Zstate not allowed cases:
 *  1. Everything else
 */
@@ -990,11 +993,14 @@ static enum dcn_zstate_support_state  
decide_zstate_support(struct dc *dc, struc
if (context->bw_ctx.dml.vba.StutterPeriod > 5000.0 || 
optimized_min_dst_y_next_start_us > 5000)
return DCN_ZSTATE_SUPPORT_ALLOW;
else if (link->psr_settings.psr_version == DC_PSR_VERSION_1 && 
!link->panel_config.psr.disable_psr)
-   return DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY;
+ 

[PATCH 04/22] drm/amd/display: Limit HW cursor size of >= 4k

[brichang]

From: Alvin Lee 

[Description]
- For SubVP, we cannot support HW cursor if it's
  greater than 64 x 64 x 4 bytes in size
- However, on certain config changes (i.e. pixel format)
  we can exit SubVP (then change to HW cursor) then re-enter
  SubVP without changing back to SW cursor because there is
  no SetCursorAttributes call
- To workaround this issue, limit the HW cursor size to be
  less than 64 x 64 x 4 bytes whenever the stream is >= 4K
- Also ensure this W/A only affects DCN that supports SubVP

Reviewed-by: Jun Lei 
Acked-by: Brian Chang 
Signed-off-by: Alvin Lee 
---
 drivers/gpu/drm/amd/display/dc/core/dc_stream.c  | 16 ++--
 .../drm/amd/display/dc/dcn32/dcn32_resource.c|  2 +-
 .../drm/amd/display/dc/dcn321/dcn321_resource.c  |  2 +-
 3 files changed, 16 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index 38d71b5c1f2d..20e534f73513 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -332,9 +332,21 @@ bool dc_stream_set_cursor_attributes(
 
dc = stream->ctx->dc;
 
-   if (dc->debug.allow_sw_cursor_fallback && attributes->height * 
attributes->width * 4 > 16384)
-   if (stream->mall_stream_config.type == SUBVP_MAIN)
+   /* SubVP is not compatible with HW cursor larger than 64 x 64 x 4.
+* Therefore, if cursor is greater than 64 x 64 x 4, fallback to SW 
cursor in the following case:
+* 1. For single display cases, if resolution is >= 5K and refresh rate 
< 120hz
+* 2. For multi display cases, if resolution is >= 4K and refresh rate 
< 120hz
+*
+* [< 120hz is a requirement for SubVP configs]
+*/
+   if (dc->debug.allow_sw_cursor_fallback && attributes->height * 
attributes->width * 4 > 16384) {
+   if (dc->current_state->stream_count == 1 && 
stream->timing.v_addressable >= 2880 &&
+   ((stream->timing.pix_clk_100hz * 100) / 
stream->timing.v_total / stream->timing.h_total) < 120)
return false;
+   else if (dc->current_state->stream_count > 1 && 
stream->timing.v_addressable >= 2160 &&
+   ((stream->timing.pix_clk_100hz * 100) / 
stream->timing.v_total / stream->timing.h_total) < 120)
+   return false;
+   }
 
stream->cursor_attributes = *attributes;
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
index 0c13fe0239d8..c40dccef6843 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
@@ -723,7 +723,7 @@ static const struct dc_debug_options debug_defaults_drv = {
/* Must match enable_single_display_2to1_odm_policy to support dynamic 
ODM transitions*/
.enable_double_buffered_dsc_pg_support = true,
.enable_dp_dig_pixel_rate_div_policy = 1,
-   .allow_sw_cursor_fallback = false,
+   .allow_sw_cursor_fallback = false, // Linux can't do SW cursor 
"fallback"
.alloc_extra_way_for_cursor = true,
.min_prefetch_in_strobe_ns = 6, // 60us
 };
diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
index d17d0f22be1f..06f144189e9d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
@@ -721,7 +721,7 @@ static const struct dc_debug_options debug_defaults_drv = {
/*must match enable_single_display_2to1_odm_policy to support dynamic 
ODM transitions*/
.enable_double_buffered_dsc_pg_support = true,
.enable_dp_dig_pixel_rate_div_policy = 1,
-   .allow_sw_cursor_fallback = false,
+   .allow_sw_cursor_fallback = false, // Linux can't do SW cursor 
"fallback"
.alloc_extra_way_for_cursor = true,
.min_prefetch_in_strobe_ns = 6, // 60us
 };
-- 
2.25.1

[PATCH 03/22] drm/amd/display: No display after resume from WB/CB

[brichang]

From: Tsung-hua Lin 

[why]
First MST sideband message returns AUX_RET_ERROR_HPD_DISCON
on certain intel platform. Aux transaction considered failure
if HPD unexpected pulled low. The actual aux transaction success
in such case, hence do not return error.

[how]
Not returning error when AUX_RET_ERROR_HPD_DISCON detected
on the first sideband message.

Reviewed-by: Jerry Zuo 
Acked-by: Brian Chang 
Signed-off-by: tsunglin 
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 36 +++
 1 file changed, 36 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index ad06e124aecf..5b97723ff6fa 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1369,6 +1369,42 @@ static const struct dmi_system_id 
hpd_disconnect_quirk_table[] = {
DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3460"),
},
},
+   {
+   .matches = {
+   DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
+   DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower 7010 Plus"),
+   },
+   },
+   {
+   .matches = {
+   DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
+   DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower 7010"),
+   },
+   },
+   {
+   .matches = {
+   DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
+   DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF 7010 Plus"),
+   },
+   },
+   {
+   .matches = {
+   DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
+   DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF 7010"),
+   },
+   },
+   {
+   .matches = {
+   DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
+   DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex MFF 7010 Plus"),
+   },
+   },
+   {
+   .matches = {
+   DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
+   DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex MFF 7010"),
+   },
+   },
{}
 };
 
-- 
2.25.1

[PATCH 02/22] drm/amd/display: Add margin on DRR vblank start for subvp

[brichang]

From: "Lee, Alvin" 

[Description]
- Add margin for HUBP "jitter" for SubVp + DRR case
- Also do a min transition even if MPO is added on a
  non SubVP pipe (i.e. added on DRR pipe for SubVP + DRR)

Reviewed-by: Jun Lei 
Acked-by: Brian Chang 
Signed-off-by: Alvin Lee 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c   | 18 +-
 drivers/gpu/drm/amd/display/dc/dc.h|  1 +
 drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c   |  1 +
 drivers/gpu/drm/amd/display/dc/dc_stream.h |  2 +-
 .../drm/amd/display/dc/dcn32/dcn32_resource.c  |  1 +
 .../amd/display/dc/dcn321/dcn321_resource.c|  1 +
 .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h|  3 ++-
 7 files changed, 24 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 1c3de3a1671e..42840ce9bf4b 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -3740,6 +3740,8 @@ static bool 
could_mpcc_tree_change_for_active_pipes(struct dc *dc,
 
struct dc_stream_status *cur_stream_status = 
stream_get_status(dc->current_state, stream);
bool force_minimal_pipe_splitting = false;
+   bool subvp_active = false;
+   uint32_t i;
 
*is_plane_addition = false;
 
@@ -3771,11 +3773,25 @@ static bool 
could_mpcc_tree_change_for_active_pipes(struct dc *dc,
}
}
 
+   for (i = 0; i < dc->res_pool->pipe_count; i++) {
+   struct pipe_ctx *pipe = >current_state->res_ctx.pipe_ctx[i];
+
+   if (pipe->stream && pipe->stream->mall_stream_config.type != 
SUBVP_NONE) {
+   subvp_active = true;
+   break;
+   }
+   }
+
/* For SubVP when adding or removing planes we need to add a minimal 
transition
 * (even when disabling all planes). Whenever disabling a phantom pipe, 
we
 * must use the minimal transition path to disable the pipe correctly.
+*
+* We want to use the minimal transition whenever subvp is active, not 
only if
+* a plane is being added / removed from a subvp stream (MPO plane can 
be added
+* to a DRR pipe of SubVP + DRR config, in which case we still want to 
run through
+* a min transition to disable subvp.
 */
-   if (cur_stream_status && stream->mall_stream_config.type == SUBVP_MAIN) 
{
+   if (cur_stream_status && subvp_active) {
/* determine if minimal transition is required due to SubVP*/
if (cur_stream_status->plane_count > surface_count) {
force_minimal_pipe_splitting = true;
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index b02d1f3d3e7c..1f6dff9904f3 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -267,6 +267,7 @@ struct dc_caps {
uint16_t subvp_pstate_allow_width_us;
uint16_t subvp_vertical_int_margin_us;
bool seamless_odm;
+   uint8_t subvp_drr_vblank_start_margin_us;
 };
 
 struct dc_bug_wa {
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c 
b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
index 097556f7b32c..6ccf477d1c4d 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
@@ -493,6 +493,7 @@ static void populate_subvp_cmd_drr_info(struct dc *dc,
 
pipe_data->pipe_config.vblank_data.drr_info.min_vtotal_supported = 
min_vtotal_supported;
pipe_data->pipe_config.vblank_data.drr_info.max_vtotal_supported = 
max_vtotal_supported;
+   pipe_data->pipe_config.vblank_data.drr_info.drr_vblank_start_margin = 
dc->caps.subvp_drr_vblank_start_margin_us;
 }
 
 /**
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h 
b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index f4dfd3a49b68..e0cee9666c48 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -144,7 +144,7 @@ struct test_pattern {
unsigned int cust_pattern_size;
 };
 
-#define SUBVP_DRR_MARGIN_US 500 // 500us for DRR margin (SubVP + DRR)
+#define SUBVP_DRR_MARGIN_US 600 // 600us for DRR margin (SubVP + DRR)
 
 enum mall_stream_type {
SUBVP_NONE, // subvp not in use
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
index cdeff6de725d..0c13fe0239d8 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
@@ -2124,6 +2124,7 @@ static bool dcn32_resource_construct(
dc->caps.subvp_swath_height_margin_lines = 16;
dc->caps.subvp_pstate_allow_width_us = 20;
dc->caps.subvp_vertical_int_margin_us = 30;
+   dc->caps.subvp_drr_vblank_start_margin_us = 100; // 100us margin
 
dc->caps.max_slave_planes = 2;
dc->caps.max_slave_yuv_planes = 2;
diff --git 

[PATCH 00/22] DC Patches November 19, 2022

[brichang]

This DC patchset brings improvements in multiple areas. In summary, we 
highlight:

*Add configuration 2 for ABM 2.3/2.4.
*Add margin for HUBP for SubVp + DRR.
*Fix no display after resume from WB/CB.
*Limit HW cursor size to be less than 64 x 64 bytes when the stream is >= 4K.
*Lower watermarks for enter/enter+exit latency.
*Update support types for DCN314 to include z8 only and z8_z10 only state.
*Add new value for soc bounding box and dummy pstate.
*Override fclk chang latency when calculating prefetch schedule for subvp with 
low uclk.
*Add check for DET fetch latency for dcn32.
*Add check if PSR enabled when entering MALL.
*Use base MALL allocation size calculations off vewport height.
*Add YCBCR2020 to CSC matrix.
*Implement DP-Tx portion to interact with DPIA.
*Add debug option for increasing phantom lines.
*Fix phantom plane/stream retain after fail validation.
*Fix display corruption with VSR enable.
*Set valid divider value for virtual and FRL/DP2.
*Add new num clk levels struct for max mclk index.
*Fix check for phantom BPP.

Cc: Daniel Wheeler 

Alvin Lee (5):
  drm/amd/display: Limit HW cursor size of >= 4k
  drm/amd/display: Check if PSR enabled when entering MALL
  drm/amd/display: Add debug options for increasing phantom lines
  drm/amd/display: Retain phantom plane/stream if validation fails
  drm/amd/display: Revert check for phantom BPP

Aric Cyr (1):
  SWDEV-1 - dc: 3.2.213

Camille Cho (1):
  drm/amd/display: new ABM config 2

David Galiffi (1):
  drm/amd/display: Fix rotated cursor offset calculation

Dillon Varone (5):
  drm/amd/display: Update soc bounding box for dcn32/dcn321
  drm/amd/display: Use dummy pstate latency for subvp when needed on
dcn32
  drm/amd/display: Add check for DET fetch latency hiding for dcn32
  drm/amd/display: Use viewport height for subvp mall allocation size
  drm/amd/display: Use new num clk levels struct for max mclk index

Ilya Bakoulin (1):
  drm/amd/display: Fix display corruption w/ VSR enable

Lee, Alvin (1):
  drm/amd/display: Add margin on DRR vblank start for subvp

Mustapha Ghaddar (1):
  drm/amd/display: Phase 1 Add Bw Allocation source and header files

Nicholas Kazlauskas (2):
  drm/amd/display: Update Z8 watermarks for DCN314
  drm/amd/display: Add Z8 allow states to z-state support list

Rodrigo Siqueira (1):
  drm/amd/display: Add YCBCR2020 coefficients to CSC matrix

Taimur Hassan (1):
  drm/amd/display: Avoid setting pixel rate divider to N/A

Tsung-hua Lin (2):
  drm/amd/display: No display after resume from WB/CB
  drm/amd/display: No display after resume from WB/CB[modify]

 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 37 ++
 .../amd/display/dc/clk_mgr/dcn31/dcn31_smu.c  |  4 +-
 .../display/dc/clk_mgr/dcn314/dcn314_smu.c| 12 +++-
 drivers/gpu/drm/amd/display/dc/core/dc.c  | 31 +++-
 .../gpu/drm/amd/display/dc/core/dc_stream.c   | 16 -
 drivers/gpu/drm/amd/display/dc/dc.h   |  6 +-
 drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c  |  1 +
 drivers/gpu/drm/amd/display/dc/dc_link.h  | 14 
 drivers/gpu/drm/amd/display/dc/dc_stream.h|  2 +-
 .../display/dc/dce110/dce110_hw_sequencer.c   |  9 ++-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c  | 34 ++---
 .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c | 28 +---
 .../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c | 32 ++---
 .../drm/amd/display/dc/dcn314/dcn314_dccg.c   |  7 ++
 .../drm/amd/display/dc/dcn314/dcn314_hwseq.c  |  6 +-
 .../gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c |  4 +-
 .../drm/amd/display/dc/dcn32/dcn32_hwseq.c| 11 +--
 .../drm/amd/display/dc/dcn32/dcn32_resource.c | 27 ++-
 .../drm/amd/display/dc/dcn32/dcn32_resource.h |  3 +
 .../display/dc/dcn32/dcn32_resource_helpers.c |  2 +-
 .../amd/display/dc/dcn321/dcn321_resource.c   |  4 +-
 .../drm/amd/display/dc/dml/dcn20/dcn20_fpu.c  | 12 +++-
 .../amd/display/dc/dml/dcn314/dcn314_fpu.c|  4 +-
 .../drm/amd/display/dc/dml/dcn32/dcn32_fpu.c  | 72 ++-
 .../dc/dml/dcn32/display_mode_vba_32.c| 41 ++-
 .../dc/dml/dcn32/display_mode_vba_util_32.c   | 69 ++
 .../dc/dml/dcn32/display_mode_vba_util_32.h   | 18 +
 .../amd/display/dc/dml/dcn321/dcn321_fpu.c|  8 +--
 .../drm/amd/display/dc/dml/display_mode_vba.h |  2 +
 .../gpu/drm/amd/display/dc/inc/core_types.h   |  1 +
 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h   |  9 ++-
 .../drm/amd/display/dc/link/link_dp_dpia_bw.c | 28 
 .../drm/amd/display/dc/link/link_dp_dpia_bw.h | 69 ++
 .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h   |  3 +-
 .../amd/display/modules/power/power_helpers.c |  9 +++
 35 files changed, 552 insertions(+), 83 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/display/dc/link/link_dp_dpia_bw.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/link/link_dp_dpia_bw.h

-- 
2.25.1

[PATCH 01/22] drm/amd/display: new ABM config 2

[brichang]

From: Camille Cho 

[Why & How]
Add configuration 2 for ABM 2.3/2.4 to suit customer preferences, which
is to lower the brightness curves in 80%-100% range compared to the
existing default config 0.

Reviewed-by: Josip Pavic 
Acked-by: Brian Chang 
Signed-off-by: Camille Cho 
---
 .../gpu/drm/amd/display/modules/power/power_helpers.c| 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c 
b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
index 235259d6c5a1..9b5d9b2c9a6a 100644
--- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
+++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
@@ -102,9 +102,18 @@ static const struct abm_parameters 
abm_settings_config1[abm_defines_max_level] =
{0x82,   0x4d,0x20,   0x00, 0x00,0xff, 0xb3, 
0x70, 0x70, 0x,  0x},
 };
 
+static const struct abm_parameters abm_settings_config2[abm_defines_max_level] 
= {
+//  min_red  max_red  bright_pos  dark_pos  bright_gain  contrast  dev   
min_knee  max_knee  blRedblStart
+   {0xf0,   0xbf,0x20,   0x00, 0x88,0x99, 0xb3, 
0x40, 0xe0,0x,  0x},
+   {0xd8,   0x85,0x20,   0x00, 0x70,0x90, 0xa8, 
0x40, 0xc8,0x0700,  0xb333},
+   {0xb8,   0x58,0x20,   0x00, 0x64,0x88, 0x78, 
0x70, 0xa0,0x7000,  0x},
+   {0x82,   0x40,0x20,   0x00, 0x00,0xb8, 0xb3, 
0x70, 0x70,0xc333,  0xb333},
+};
+
 static const struct abm_parameters * const abm_settings[] = {
abm_settings_config0,
abm_settings_config1,
+   abm_settings_config2,
 };
 
 #define NUM_AMBI_LEVEL5
-- 
2.25.1

Re: [PATCH] drm/amdgpu: handle gang submit before VMID

[Christian König]

Pushed to drm-misc-fixes, should be picked up for the next rc.

Let me know if you run into any more problems with that.

Thanks,
Christian.

Am 18.11.22 um 16:36 schrieb Timur Kristóf:

Can you guys please push this into the next 6.1 RC? This solves a
significant issue with gang submit.

On Fri, 2022-11-18 at 16:30 +0100, Christian König wrote:

Otherwise it can happen that not all gang members can get a VMID
assigned and we deadlock.

Signed-off-by: Christian König 
Tested-by: Timur Kristóf 
Acked-by: Timur Kristóf 
Fixes: 68ce8b242242 ("drm/amdgpu: add gang submit backend v2")
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 6 +++---
  1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
index cd968e781077..abb99cff8b4b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
@@ -254,6 +254,9 @@ static struct dma_fence
*amdgpu_job_dependency(struct drm_sched_job *sched_job,
 DRM_ERROR("Error adding fence (%d)\n", r);
 }
  
+   if (!fence && job->gang_submit)

+   fence = amdgpu_device_switch_gang(ring->adev, job-

gang_submit);

+
 while (fence == NULL && vm && !job->vmid) {
 r = amdgpu_vmid_grab(vm, ring, >sync,
  >base.s_fence->finished,
@@ -264,9 +267,6 @@ static struct dma_fence
*amdgpu_job_dependency(struct drm_sched_job *sched_job,
 fence = amdgpu_sync_get_fence(>sync);
 }
  
-   if (!fence && job->gang_submit)

-   fence = amdgpu_device_switch_gang(ring->adev, job-

gang_submit);

-
 return fence;
  }
  

Re: [PATCH] drm/amdgpu/psp: don't free PSP buffers on suspend

[Christian König]

Am 16.11.22 um 17:40 schrieb Alex Deucher:

We can reuse the same buffers on resume.

Signed-off-by: Alex Deucher 


Reviewed-by: Christian König 

But I would like to ad the WARN_ON() to not free anything during suspend 
on newer kernels as well.



---
  drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 56 +
  1 file changed, 29 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 0a8c30475dda..d9cb4c4b8289 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -172,6 +172,7 @@ void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx)
  {
amdgpu_bo_free_kernel(_ctx->shared_bo, _ctx->shared_mc_addr,
  _ctx->shared_buf);
+   mem_ctx->shared_bo = NULL;
  }
  
  static void psp_free_shared_bufs(struct psp_context *psp)

@@ -182,6 +183,7 @@ static void psp_free_shared_bufs(struct psp_context *psp)
/* free TMR memory buffer */
pptr = amdgpu_sriov_vf(psp->adev) ? _buf : NULL;
amdgpu_bo_free_kernel(>tmr_bo, >tmr_mc_addr, pptr);
+   psp->tmr_bo = NULL;
  
  	/* free xgmi shared memory */

psp_ta_free_shared_buf(>xgmi_context.context.mem_context);
@@ -743,37 +745,39 @@ static int psp_load_toc(struct psp_context *psp,
  /* Set up Trusted Memory Region */
  static int psp_tmr_init(struct psp_context *psp)
  {
-   int ret;
+   int ret = 0;
int tmr_size;
void *tmr_buf;
void **pptr;
  
-	/*

-* According to HW engineer, they prefer the TMR address be "naturally
-* aligned" , e.g. the start address be an integer divide of TMR size.
-*
-* Note: this memory need be reserved till the driver
-* uninitializes.
-*/
-   tmr_size = PSP_TMR_SIZE(psp->adev);
-
-   /* For ASICs support RLC autoload, psp will parse the toc
-* and calculate the total size of TMR needed */
-   if (!amdgpu_sriov_vf(psp->adev) &&
-   psp->toc.start_addr &&
-   psp->toc.size_bytes &&
-   psp->fw_pri_buf) {
-   ret = psp_load_toc(psp, _size);
-   if (ret) {
-   DRM_ERROR("Failed to load toc\n");
-   return ret;
+   if (!psp->tmr_bo) {
+   /*
+* According to HW engineer, they prefer the TMR address be 
"naturally
+* aligned" , e.g. the start address be an integer divide of 
TMR size.
+*
+* Note: this memory need be reserved till the driver
+* uninitializes.
+*/
+   tmr_size = PSP_TMR_SIZE(psp->adev);
+
+   /* For ASICs support RLC autoload, psp will parse the toc
+* and calculate the total size of TMR needed */
+   if (!amdgpu_sriov_vf(psp->adev) &&
+   psp->toc.start_addr &&
+   psp->toc.size_bytes &&
+   psp->fw_pri_buf) {
+   ret = psp_load_toc(psp, _size);
+   if (ret) {
+   DRM_ERROR("Failed to load toc\n");
+   return ret;
+   }
}
-   }
  
-	pptr = amdgpu_sriov_vf(psp->adev) ? _buf : NULL;

-   ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_ALIGNMENT,
- AMDGPU_GEM_DOMAIN_VRAM,
- >tmr_bo, >tmr_mc_addr, pptr);
+   pptr = amdgpu_sriov_vf(psp->adev) ? _buf : NULL;
+   ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, 
PSP_TMR_ALIGNMENT,
+ AMDGPU_GEM_DOMAIN_VRAM,
+ >tmr_bo, >tmr_mc_addr, 
pptr);
+   }
  
  	return ret;

  }
@@ -2701,8 +2705,6 @@ static int psp_suspend(void *handle)
}
  
  out:

-   psp_free_shared_bufs(psp);
-
return ret;
  }
  

Re: [PATCH] drm/amdgpu: handle gang submit before VMID

[Timur Kristóf]

Can you guys please push this into the next 6.1 RC? This solves a
significant issue with gang submit.

On Fri, 2022-11-18 at 16:30 +0100, Christian König wrote:
> Otherwise it can happen that not all gang members can get a VMID
> assigned and we deadlock.
> 
> Signed-off-by: Christian König 
> Tested-by: Timur Kristóf 
> Acked-by: Timur Kristóf 
> Fixes: 68ce8b242242 ("drm/amdgpu: add gang submit backend v2")
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
> index cd968e781077..abb99cff8b4b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
> @@ -254,6 +254,9 @@ static struct dma_fence
> *amdgpu_job_dependency(struct drm_sched_job *sched_job,
> DRM_ERROR("Error adding fence (%d)\n", r);
> }
>  
> +   if (!fence && job->gang_submit)
> +   fence = amdgpu_device_switch_gang(ring->adev, job-
> >gang_submit);
> +
> while (fence == NULL && vm && !job->vmid) {
> r = amdgpu_vmid_grab(vm, ring, >sync,
>  >base.s_fence->finished,
> @@ -264,9 +267,6 @@ static struct dma_fence
> *amdgpu_job_dependency(struct drm_sched_job *sched_job,
> fence = amdgpu_sync_get_fence(>sync);
> }
>  
> -   if (!fence && job->gang_submit)
> -   fence = amdgpu_device_switch_gang(ring->adev, job-
> >gang_submit);
> -
> return fence;
>  }
>  

Re: [PATCH] drm/amdgpu/psp: don't free PSP buffers on suspend

[Alex Deucher]

On Wed, Nov 16, 2022 at 11:40 AM Alex Deucher  wrote:
>
> We can reuse the same buffers on resume.
>
> Signed-off-by: Alex Deucher 

Anyone want to give me an RB or AB?

Thanks,

Alex

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 56 +
>  1 file changed, 29 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> index 0a8c30475dda..d9cb4c4b8289 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> @@ -172,6 +172,7 @@ void psp_ta_free_shared_buf(struct ta_mem_context 
> *mem_ctx)
>  {
> amdgpu_bo_free_kernel(_ctx->shared_bo, _ctx->shared_mc_addr,
>   _ctx->shared_buf);
> +   mem_ctx->shared_bo = NULL;
>  }
>
>  static void psp_free_shared_bufs(struct psp_context *psp)
> @@ -182,6 +183,7 @@ static void psp_free_shared_bufs(struct psp_context *psp)
> /* free TMR memory buffer */
> pptr = amdgpu_sriov_vf(psp->adev) ? _buf : NULL;
> amdgpu_bo_free_kernel(>tmr_bo, >tmr_mc_addr, pptr);
> +   psp->tmr_bo = NULL;
>
> /* free xgmi shared memory */
> psp_ta_free_shared_buf(>xgmi_context.context.mem_context);
> @@ -743,37 +745,39 @@ static int psp_load_toc(struct psp_context *psp,
>  /* Set up Trusted Memory Region */
>  static int psp_tmr_init(struct psp_context *psp)
>  {
> -   int ret;
> +   int ret = 0;
> int tmr_size;
> void *tmr_buf;
> void **pptr;
>
> -   /*
> -* According to HW engineer, they prefer the TMR address be "naturally
> -* aligned" , e.g. the start address be an integer divide of TMR size.
> -*
> -* Note: this memory need be reserved till the driver
> -* uninitializes.
> -*/
> -   tmr_size = PSP_TMR_SIZE(psp->adev);
> -
> -   /* For ASICs support RLC autoload, psp will parse the toc
> -* and calculate the total size of TMR needed */
> -   if (!amdgpu_sriov_vf(psp->adev) &&
> -   psp->toc.start_addr &&
> -   psp->toc.size_bytes &&
> -   psp->fw_pri_buf) {
> -   ret = psp_load_toc(psp, _size);
> -   if (ret) {
> -   DRM_ERROR("Failed to load toc\n");
> -   return ret;
> +   if (!psp->tmr_bo) {
> +   /*
> +* According to HW engineer, they prefer the TMR address be 
> "naturally
> +* aligned" , e.g. the start address be an integer divide of 
> TMR size.
> +*
> +* Note: this memory need be reserved till the driver
> +* uninitializes.
> +*/
> +   tmr_size = PSP_TMR_SIZE(psp->adev);
> +
> +   /* For ASICs support RLC autoload, psp will parse the toc
> +* and calculate the total size of TMR needed */
> +   if (!amdgpu_sriov_vf(psp->adev) &&
> +   psp->toc.start_addr &&
> +   psp->toc.size_bytes &&
> +   psp->fw_pri_buf) {
> +   ret = psp_load_toc(psp, _size);
> +   if (ret) {
> +   DRM_ERROR("Failed to load toc\n");
> +   return ret;
> +   }
> }
> -   }
>
> -   pptr = amdgpu_sriov_vf(psp->adev) ? _buf : NULL;
> -   ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_ALIGNMENT,
> - AMDGPU_GEM_DOMAIN_VRAM,
> - >tmr_bo, >tmr_mc_addr, pptr);
> +   pptr = amdgpu_sriov_vf(psp->adev) ? _buf : NULL;
> +   ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, 
> PSP_TMR_ALIGNMENT,
> + AMDGPU_GEM_DOMAIN_VRAM,
> + >tmr_bo, 
> >tmr_mc_addr, pptr);
> +   }
>
> return ret;
>  }
> @@ -2701,8 +2705,6 @@ static int psp_suspend(void *handle)
> }
>
>  out:
> -   psp_free_shared_bufs(psp);
> -
> return ret;
>  }
>
> --
> 2.38.1
>

Re: [PATCH] drm/amdgpu: handle gang submit before VMID

[Alex Deucher]

On Fri, Nov 18, 2022 at 10:30 AM Christian König
 wrote:
>
> Otherwise it can happen that not all gang members can get a VMID
> assigned and we deadlock.
>
> Signed-off-by: Christian König 
> Tested-by: Timur Kristóf 
> Acked-by: Timur Kristóf 
> Fixes: 68ce8b242242 ("drm/amdgpu: add gang submit backend v2")

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
> index cd968e781077..abb99cff8b4b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
> @@ -254,6 +254,9 @@ static struct dma_fence *amdgpu_job_dependency(struct 
> drm_sched_job *sched_job,
> DRM_ERROR("Error adding fence (%d)\n", r);
> }
>
> +   if (!fence && job->gang_submit)
> +   fence = amdgpu_device_switch_gang(ring->adev, 
> job->gang_submit);
> +
> while (fence == NULL && vm && !job->vmid) {
> r = amdgpu_vmid_grab(vm, ring, >sync,
>  >base.s_fence->finished,
> @@ -264,9 +267,6 @@ static struct dma_fence *amdgpu_job_dependency(struct 
> drm_sched_job *sched_job,
> fence = amdgpu_sync_get_fence(>sync);
> }
>
> -   if (!fence && job->gang_submit)
> -   fence = amdgpu_device_switch_gang(ring->adev, 
> job->gang_submit);
> -
> return fence;
>  }
>
> --
> 2.25.1
>

[PATCH] drm/amdgpu: handle gang submit before VMID

[Christian König]

Otherwise it can happen that not all gang members can get a VMID
assigned and we deadlock.

Signed-off-by: Christian König 
Tested-by: Timur Kristóf 
Acked-by: Timur Kristóf 
Fixes: 68ce8b242242 ("drm/amdgpu: add gang submit backend v2")
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
index cd968e781077..abb99cff8b4b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
@@ -254,6 +254,9 @@ static struct dma_fence *amdgpu_job_dependency(struct 
drm_sched_job *sched_job,
DRM_ERROR("Error adding fence (%d)\n", r);
}
 
+   if (!fence && job->gang_submit)
+   fence = amdgpu_device_switch_gang(ring->adev, job->gang_submit);
+
while (fence == NULL && vm && !job->vmid) {
r = amdgpu_vmid_grab(vm, ring, >sync,
 >base.s_fence->finished,
@@ -264,9 +267,6 @@ static struct dma_fence *amdgpu_job_dependency(struct 
drm_sched_job *sched_job,
fence = amdgpu_sync_get_fence(>sync);
}
 
-   if (!fence && job->gang_submit)
-   fence = amdgpu_device_switch_gang(ring->adev, job->gang_submit);
-
return fence;
 }
 
-- 
2.25.1

Re: [PATCH] drm/amd/display: add FB_DAMAGE_CLIPS support

[Hamza Mahfooz]

Hey Leo,

On 11/17/22 12:31, Leo Li wrote:



On 11/15/22 15:24, Hamza Mahfooz wrote:

Currently, userspace doesn't have a way to communicate selective updates
to displays. So, enable support for FB_DAMAGE_CLIPS for DCN ASICs newer
than DCN301, convert DRM damage clips to dc dirty rectangles and fill
them into dirty_rects in fill_dc_dirty_rects().

Signed-off-by: Hamza Mahfooz 
---
  .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 91 +++
  .../amd/display/amdgpu_dm/amdgpu_dm_plane.c   |  4 +
  2 files changed, 58 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

index 185d09c760ba..18b710ba802d 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4842,6 +4842,31 @@ static int fill_dc_plane_attributes(struct 
amdgpu_device *adev,

  return 0;
  }
+static inline void fill_dc_dirty_rect(struct drm_plane *plane,
+  struct rect *dirty_rect, int32_t x,
+  int32_t y, int32_t width, int32_t height,
+  int *i, bool ffu)
+{
+    WARN_ON(*i >= DC_MAX_DIRTY_RECTS);


Hi Hamza,

Since dc_flip_addrs->dirty_rects has a fixed length of 
DC_MAX_DIRTY_RECTS per pipe (a restriction by DMUB FW), I think it makes 
more sense to fallback to a full-frame-update (FFU) if num_clips > 
DC_MAX_DIRTY_RECTS. An alternative would be to reject the atomic commit, 
but that sounds heavy handed.




+
+    dirty_rect->x = x;
+    dirty_rect->y = y;
+    dirty_rect->width = width;
+    dirty_rect->height = height;
+
+    if (ffu)
+    drm_dbg(plane->dev,
+    "[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n",
+    plane->base.id, width, height);
+    else
+    drm_dbg(plane->dev,
+    "[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)",
+    plane->base.id, x, y, width, height);
+
+    (*i)++;
+}
+
+
  /**
   * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective 
updates

   *
@@ -4862,10 +4887,6 @@ static int fill_dc_plane_attributes(struct 
amdgpu_device *adev,
   * addition, certain use cases - such as cursor and multi-plane 
overlay (MPO) -
   * implicitly provide damage clips without any client support via 
the plane

   * bounds.
- *
- * Today, amdgpu_dm only supports the MPO and cursor usecase.
- *
- * TODO: Also enable for FB_DAMAGE_CLIPS
   */
  static void fill_dc_dirty_rects(struct drm_plane *plane,
  struct drm_plane_state *old_plane_state,
@@ -4876,12 +4897,11 @@ static void fill_dc_dirty_rects(struct 
drm_plane *plane,

  struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
  struct rect *dirty_rects = flip_addrs->dirty_rects;
  uint32_t num_clips;
+    struct drm_mode_rect *clips;
  bool bb_changed;
  bool fb_changed;
  uint32_t i = 0;
-    flip_addrs->dirty_rect_count = 0;
-
  /*
   * Cursor plane has it's own dirty rect update interface. See
   * dcn10_dmub_update_cursor_data and 
dmub_cmd_update_cursor_info_data
@@ -4894,15 +4914,11 @@ static void fill_dc_dirty_rects(struct 
drm_plane *plane,

   * requested, and there is a plane update, do FFU.
   */
  if (!dm_crtc_state->mpo_requested) {
-    dirty_rects[0].x = 0;
-    dirty_rects[0].y = 0;
-    dirty_rects[0].width = dm_crtc_state->base.mode.crtc_hdisplay;
-    dirty_rects[0].height = dm_crtc_state->base.mode.crtc_vdisplay;
-    flip_addrs->dirty_rect_count = 1;
-    DRM_DEBUG_DRIVER("[PLANE:%d] PSR FFU dirty rect size (%d, 
%d)\n",

- new_plane_state->plane->base.id,
- dm_crtc_state->base.mode.crtc_hdisplay,
- dm_crtc_state->base.mode.crtc_vdisplay);
+    fill_dc_dirty_rect(new_plane_state->plane, _rects[0], 0,
+   0, dm_crtc_state->base.mode.crtc_hdisplay,
+   dm_crtc_state->base.mode.crtc_vdisplay, ,
+   true);
+    flip_addrs->dirty_rect_count = i;
  return;
  }


Previously, we always do FFU on plane updates if no MPO has been 
requested. Now, since we want to look at user-provided DRM damage clips, 
this bit needs a bit of a rework.


In short, if there are valid clips for this plane 
(drm_plane_get_damage_clips_count() > 0), they should be added to 
dc_dirty_rects. Otherwise, fallback to old FFU logic.


With MPO, the damage clips are more interesting, since the entire 
plane's bounding box can be moved. I wonder if that is reflected in 
DRM's damage clips. Do you know if a plane bb change will be reflected 
in drm_plane_get_damage_clips()?


From what I've seen, plane bb changes are not counted as damage clips.



Thanks,
Leo
@@ -4914,6 +4930,7 @@ static void fill_dc_dirty_rects(struct drm_plane 
*plane,

   * rects.
   */
  num_clips = drm_plane_get_damage_clips_count(new_plane_state);
+    clips = 

Re: [PATCH] drm/amdgpu: update documentation of parameter amdgpu_gtt_size

[Christian König]

Reviewed-by: Christian König 

Am 18.11.22 um 15:52 schrieb Deucher, Alexander:


[Public]


Reviewed-by: Alex Deucher 

*From:* Yin, ZhenGuo (Chris) 
*Sent:* Friday, November 18, 2022 3:49 AM
*To:* amd-gfx@lists.freedesktop.org 
*Cc:* Deucher, Alexander ; Chen, Jingwen 
; Yin, ZhenGuo (Chris) 
*Subject:* [PATCH] drm/amdgpu: update documentation of parameter 
amdgpu_gtt_size

Fixes: f7ba887f606b ("drm/amdgpu: Adjust logic around GTT size (v3)")
Signed-off-by: ZhenGuo Yin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

index 72b77b3ac4fb..987914532104 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -237,8 +237,7 @@ module_param_named(gartsize, amdgpu_gart_size, 
uint, 0600);


 /**
  * DOC: gttsize (int)
- * Restrict the size of GTT domain in MiB for testing. The default is 
-1 (It's VRAM size if 3GB < VRAM < 3/4 RAM,

- * otherwise 3/4 RAM size).
+ * Restrict the size of GTT domain in MiB for testing. The default is 
-1 (Use 1/2 RAM, minimum value is 3GB).

  */
 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = 
auto)");

 module_param_named(gttsize, amdgpu_gtt_size, int, 0600);
--
2.35.1

Re: [PATCH] drm/amdgpu: update documentation of parameter amdgpu_gtt_size

[Deucher, Alexander]

[Public]

Reviewed-by: Alex Deucher 

From: Yin, ZhenGuo (Chris) 
Sent: Friday, November 18, 2022 3:49 AM
To: amd-gfx@lists.freedesktop.org 
Cc: Deucher, Alexander ; Chen, Jingwen 
; Yin, ZhenGuo (Chris) 
Subject: [PATCH] drm/amdgpu: update documentation of parameter amdgpu_gtt_size

Fixes: f7ba887f606b ("drm/amdgpu: Adjust logic around GTT size (v3)")
Signed-off-by: ZhenGuo Yin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 72b77b3ac4fb..987914532104 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -237,8 +237,7 @@ module_param_named(gartsize, amdgpu_gart_size, uint, 0600);

 /**
  * DOC: gttsize (int)
- * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's 
VRAM size if 3GB < VRAM < 3/4 RAM,
- * otherwise 3/4 RAM size).
+ * Restrict the size of GTT domain in MiB for testing. The default is -1 (Use 
1/2 RAM, minimum value is 3GB).
  */
 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)");
 module_param_named(gttsize, amdgpu_gtt_size, int, 0600);
--
2.35.1

Re: [PATCH v2] amdgpu: nbio_v7_4: Add pointer check

[Alex Deucher]

On Fri, Nov 18, 2022 at 9:11 AM Denis Arefev  wrote:
>
> Return value of a function 'amdgpu_ras_find_obj' is dereferenced
> at nbio_v7_4.c:325 without checking for null
>
> Found by Linux Verification Center (linuxtesting.org) with SVACE.
>
> Signed-off-by: Denis Arefev 
> ---
>  drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c 
> b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
> index eadc9526d33f..0f2ac99de864 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
> @@ -304,6 +304,9 @@ static void 
> nbio_v7_4_handle_ras_controller_intr_no_bifring(struct amdgpu_device
> struct ras_err_data err_data = {0, 0, 0, NULL};
> struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
>
> +   if (!obj)
> +   return;
>

I don't think we could ever get here with a NULL obj.  This is part of
the interrupt handler for NBIO RAS, so the interrupt would never be
enabled in the first place if the obj didn't exist.

Alex

> bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, 
> mmBIF_DOORBELL_INT_CNTL);
> if (REG_GET_FIELD(bif_doorbell_intr_cntl,
> BIF_DOORBELL_INT_CNTL, RAS_CNTLR_INTERRUPT_STATUS)) {
> --
> 2.25.1
>

Re: [PATCH] drm/amdgpu: add mb for si

[李真能]

在 2022/11/18 17:18, Michel Dänzer 写道:

On 11/18/22 09:01, Christian König wrote:

Am 18.11.22 um 08:48 schrieb Zhenneng Li:

During reboot test on arm64 platform, it may failure on boot,
so add this mb in smc.

The error message are as follows:
[    6.996395][ 7] [  T295] [drm:amdgpu_device_ip_late_init [amdgpu]] *ERROR*
     late_init of IP block  failed -22
[    7.006919][ 7] [  T295] amdgpu :04:00.0: amdgpu_device_ip_late_init 
failed
[    7.014224][ 7] [  T295] amdgpu :04:00.0: Fatal error during GPU init

Memory barries are not supposed to be sprinkled around like this, you need to 
give a detailed explanation why this is necessary.

Regards,
Christian.


Signed-off-by: Zhenneng Li 
---
   drivers/gpu/drm/amd/pm/legacy-dpm/si_smc.c | 2 ++
   1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_smc.c 
b/drivers/gpu/drm/amd/pm/legacy-dpm/si_smc.c
index 8f994ffa9cd1..c7656f22278d 100644
--- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_smc.c
+++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_smc.c
@@ -155,6 +155,8 @@ bool amdgpu_si_is_smc_running(struct amdgpu_device *adev)
   u32 rst = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
   u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
   +    mb();
+
   if (!(rst & RST_REG) && !(clk & CK_DISABLE))
   return true;

In particular, it makes no sense in this specific place, since it cannot directly 
affect the values of rst & clk.


I thinks so too.

But when I do reboot test using nine desktop machines,  there maybe 
report this error on one or two machines after Hundreds of times or 
Thousands of times reboot test, at the beginning, I use msleep() instead 
of mb(), these two methods are all works, but I don't know what is the 
root case.


I use this method on other verdor's oland card, this error message are 
reported again.


What could be the root reason?

test environmen:

graphics card: OLAND 0x1002:0x6611 0x1642:0x1869 0x87

driver: amdgpu

os: ubuntu 2004

platform: arm64

kernel: 5.4.18

[PATCH v2] amdgpu: nbio_v7_4: Add pointer check

[Denis Arefev]

Return value of a function 'amdgpu_ras_find_obj' is dereferenced 
at nbio_v7_4.c:325 without checking for null

Found by Linux Verification Center (linuxtesting.org) with SVACE.

Signed-off-by: Denis Arefev 
---
 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c 
b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
index eadc9526d33f..0f2ac99de864 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
@@ -304,6 +304,9 @@ static void 
nbio_v7_4_handle_ras_controller_intr_no_bifring(struct amdgpu_device
struct ras_err_data err_data = {0, 0, 0, NULL};
struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
 
+   if (!obj)
+   return;
 
bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL);
if (REG_GET_FIELD(bif_doorbell_intr_cntl,
BIF_DOORBELL_INT_CNTL, RAS_CNTLR_INTERRUPT_STATUS)) {
-- 
2.25.1

Re: [PATCH] drm/amdgpu: fix stall on CPU when allocate large system memory

[James Zhu]

On 2022-11-17 17:03, Felix Kuehling wrote:

Am 2022-11-17 um 16:38 schrieb James Zhu:

When applications try to allocate large system (more than > 128GB),
"stall cpu" is reported.

for such large system memory, walk_page_range takes more than 20s 
usually.

The warning message can be removed when splitting hmm range into smaller
ones which is not more 64GB for each walk_page_range.

[  164.437617] amdgpu:amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu:1753: 
amdgpu: create BO VA 0x7f63c7a0 size 0x2f1600 domain CPU
[  164.488847] amdgpu:amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu:1785: 
amdgpu: creating userptr BO for user_addr = 7f63c7a0

[  185.439116] rcu: INFO: rcu_sched self-detected stall on CPU
[  185.439125] rcu: 8-: (20999 ticks this GP) 
idle=e22/1/0x4000 softirq=2242/2242 fqs=5249

[  185.439137] (t=21000 jiffies g=6325 q=1215)
[  185.439141] NMI backtrace for cpu 8
[  185.439143] CPU: 8 PID: 3470 Comm: kfdtest Kdump: loaded Tainted: 
G   O 5.12.0-0_fbk5_zion_rc1_5697_g2c723fb88626 #1
[  185.439147] Hardware name: HPE ProLiant XL675d Gen10 Plus/ProLiant 
XL675d Gen10 Plus, BIOS A47 11/06/2020

[  185.439150] Call Trace:
[  185.439153]  
[  185.439157]  dump_stack+0x64/0x7c
[  185.439163]  nmi_cpu_backtrace.cold.7+0x30/0x65
[  185.439165]  ? lapic_can_unplug_cpu+0x70/0x70
[  185.439170]  nmi_trigger_cpumask_backtrace+0xf9/0x100
[  185.439174]  rcu_dump_cpu_stacks+0xc5/0xf5
[  185.439178]  rcu_sched_clock_irq.cold.97+0x112/0x38c
[  185.439182]  ? tick_sched_handle.isra.21+0x50/0x50
[  185.439185]  update_process_times+0x8c/0xc0
[  185.439189]  tick_sched_timer+0x63/0x70
[  185.439192]  __hrtimer_run_queues+0xff/0x250
[  185.439195]  hrtimer_interrupt+0xf4/0x200
[  185.439199]  __sysvec_apic_timer_interrupt+0x51/0xd0
[  185.439201]  sysvec_apic_timer_interrupt+0x69/0x90
[  185.439206]  
[  185.439207]  asm_sysvec_apic_timer_interrupt+0x12/0x20
[  185.439211] RIP: 0010:clear_page_rep+0x7/0x10
[  185.439214] Code: e8 fe 7c 51 00 44 89 e2 48 89 ee 48 89 df e8 60 
ff ff ff c6 03 00 5b 5d 41 5c c3 cc cc cc cc cc cc cc cc b9 00 02 00 
00 31 c0  48 ab c3 0f 1f 44 00 00 31 c0 b9 40 00 00 00 66 0f 1f 
84 00 00

[  185.439218] RSP: 0018:c9000f58f818 EFLAGS: 0246
[  185.439220] RAX:  RBX: 0881 RCX: 
005c
[  185.439223] RDX: 00100dca RSI:  RDI: 
88a59e0e5d20
[  185.439225] RBP: ea0096783940 R08: 888118c35280 R09: 
ea0096783940
[  185.439227] R10: 8880 R11: 1600 R12: 
ea0096783980
[  185.439228] R13: ea0096783940 R14: 88b07fdfdd00 R15: 


[  185.439232]  prep_new_page+0x81/0xc0
[  185.439236]  get_page_from_freelist+0x13be/0x16f0
[  185.439240]  ? release_pages+0x16a/0x4a0
[  185.439244]  __alloc_pages_nodemask+0x1ae/0x340
[  185.439247]  alloc_pages_vma+0x74/0x1e0
[  185.439251]  __handle_mm_fault+0xafe/0x1360
[  185.439255]  handle_mm_fault+0xc3/0x280
[  185.439257]  hmm_vma_fault.isra.22+0x49/0x90
[  185.439261]  __walk_page_range+0x692/0x9b0
[  185.439265]  walk_page_range+0x9b/0x120
[  185.439269]  hmm_range_fault+0x4f/0x90
[  185.439274]  amdgpu_hmm_range_get_pages+0x24f/0x260 [amdgpu]
[  185.439463]  amdgpu_ttm_tt_get_user_pages+0xc2/0x190 [amdgpu]
[  185.439603] amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu+0x49f/0x7a0 
[amdgpu]

[  185.439774]  kfd_ioctl_alloc_memory_of_gpu+0xfb/0x410 [amdgpu]

Signed-off-by: James Zhu 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c | 47 +
  1 file changed, 32 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c

index a48ea62b12b0..0425fc6a49aa 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c
@@ -163,6 +163,7 @@ int amdgpu_hmm_range_get_pages(struct 
mmu_interval_notifier *notifier,

 struct hmm_range **phmm_range)
  {
  struct hmm_range *hmm_range;
+    unsigned long hmm_range_end;
  unsigned long timeout;
  unsigned long i;
  unsigned long *pfns;
@@ -184,25 +185,41 @@ int amdgpu_hmm_range_get_pages(struct 
mmu_interval_notifier *notifier,

  hmm_range->default_flags |= HMM_PFN_REQ_WRITE;
  hmm_range->hmm_pfns = pfns;
  hmm_range->start = start;
-    hmm_range->end = start + npages * PAGE_SIZE;
+    hmm_range_end = start + npages * PAGE_SIZE;


This variable name is too easy to confuse with hmm_range->end. I would 
suggest calling it "end", analogous to "start".

[JZ] Sure




  hmm_range->dev_private_owner = owner;
  -    /* Assuming 512MB takes maxmium 1 second to fault page address */
-    timeout = max(npages >> 17, 1ULL) * HMM_RANGE_DEFAULT_TIMEOUT;
-    timeout = jiffies + msecs_to_jiffies(timeout);
+#define MAX_WALK_BYTE    (64ULL<<30)
+    do {
+    hmm_range->end = min(hmm_range->start + MAX_WALK_BYTE, 
hmm_range_end);

+
+    pr_debug("hmm range: start = 0x%lx, end = 0x%lx",
+

[PATCH] drm/amdgpu: fix for suspend/resume kiq fence fallback under sriov

[Shikang Fan]

- in device_resume, sriov configure interrupt should be in full access,
  so release_full_gpu should be done after kfd_resume.
- remove the previous workaround solution for sriov.

Signed-off-by: Shikang Fan 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 23 +++---
 1 file changed, 12 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 3d5d5d49cfab..22723b4492a1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -4180,21 +4180,15 @@ int amdgpu_device_resume(struct drm_device *dev, bool 
fbcon)
 
r = amdgpu_device_ip_resume(adev);
 
-   /* no matter what r is, always need to properly release full GPU */
-   if (amdgpu_sriov_vf(adev)) {
-   amdgpu_virt_init_data_exchange(adev);
-   amdgpu_virt_release_full_gpu(adev, true);
-   }
-
if (r) {
dev_err(adev->dev, "amdgpu_device_ip_resume failed (%d).\n", r);
-   return r;
+   goto exit;
}
amdgpu_fence_driver_hw_init(adev);
 
r = amdgpu_device_ip_late_init(adev);
if (r)
-   return r;
+   goto exit;
 
queue_delayed_work(system_wq, >delayed_init_work,
   msecs_to_jiffies(AMDGPU_RESUME_MS));
@@ -4202,12 +4196,19 @@ int amdgpu_device_resume(struct drm_device *dev, bool 
fbcon)
if (!adev->in_s0ix) {
r = amdgpu_amdkfd_resume(adev, adev->in_runpm);
if (r)
-   return r;
+   goto exit;
+   }
+
+exit:
+   if (amdgpu_sriov_vf(adev)) {
+   amdgpu_virt_init_data_exchange(adev);
+   amdgpu_virt_release_full_gpu(adev, true);
}
 
+   if (r)
+   return r;
+
/* Make sure IB tests flushed */
-   if (amdgpu_sriov_vf(adev))
-   amdgpu_irq_gpu_reset_resume_helper(adev);
flush_delayed_work(>delayed_init_work);
 
if (adev->in_s0ix) {
-- 
2.25.1

Re: [PATCH] drm/amdgpu: add mb for si

[Michel Dänzer]

On 11/18/22 09:01, Christian König wrote:
> Am 18.11.22 um 08:48 schrieb Zhenneng Li:
>> During reboot test on arm64 platform, it may failure on boot,
>> so add this mb in smc.
>>
>> The error message are as follows:
>> [    6.996395][ 7] [  T295] [drm:amdgpu_device_ip_late_init [amdgpu]] *ERROR*
>>     late_init of IP block  failed -22
>> [    7.006919][ 7] [  T295] amdgpu :04:00.0: amdgpu_device_ip_late_init 
>> failed
>> [    7.014224][ 7] [  T295] amdgpu :04:00.0: Fatal error during GPU init
> 
> Memory barries are not supposed to be sprinkled around like this, you need to 
> give a detailed explanation why this is necessary.
> 
> Regards,
> Christian.
> 
>>
>> Signed-off-by: Zhenneng Li 
>> ---
>>   drivers/gpu/drm/amd/pm/legacy-dpm/si_smc.c | 2 ++
>>   1 file changed, 2 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_smc.c 
>> b/drivers/gpu/drm/amd/pm/legacy-dpm/si_smc.c
>> index 8f994ffa9cd1..c7656f22278d 100644
>> --- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_smc.c
>> +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_smc.c
>> @@ -155,6 +155,8 @@ bool amdgpu_si_is_smc_running(struct amdgpu_device *adev)
>>   u32 rst = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
>>   u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
>>   +    mb();
>> +
>>   if (!(rst & RST_REG) && !(clk & CK_DISABLE))
>>   return true;

In particular, it makes no sense in this specific place, since it cannot 
directly affect the values of rst & clk.


-- 
Earthling Michel Dänzer|  https://redhat.com
Libre software enthusiast  | Mesa and Xwayland developer

[PATCH] drm/amdgpu: add mb for si

[Zhenneng Li]

During reboot test on arm64 platform, it may failure on boot,
so add this mb in smc.

The error message are as follows:
[6.996395][ 7] [  T295] [drm:amdgpu_device_ip_late_init [amdgpu]] *ERROR*
late_init of IP block  failed -22
[7.006919][ 7] [  T295] amdgpu :04:00.0: amdgpu_device_ip_late_init 
failed
[7.014224][ 7] [  T295] amdgpu :04:00.0: Fatal error during GPU init

Signed-off-by: Zhenneng Li 
---
 drivers/gpu/drm/amd/pm/legacy-dpm/si_smc.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_smc.c 
b/drivers/gpu/drm/amd/pm/legacy-dpm/si_smc.c
index 8f994ffa9cd1..c7656f22278d 100644
--- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_smc.c
+++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_smc.c
@@ -155,6 +155,8 @@ bool amdgpu_si_is_smc_running(struct amdgpu_device *adev)
u32 rst = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
 
+   mb();
+
if (!(rst & RST_REG) && !(clk & CK_DISABLE))
return true;
 
-- 
2.25.1

[PATCH] drm/amdgpu: update documentation of parameter amdgpu_gtt_size

[ZhenGuo Yin]

Fixes: f7ba887f606b ("drm/amdgpu: Adjust logic around GTT size (v3)")
Signed-off-by: ZhenGuo Yin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 72b77b3ac4fb..987914532104 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -237,8 +237,7 @@ module_param_named(gartsize, amdgpu_gart_size, uint, 0600);
 
 /**
  * DOC: gttsize (int)
- * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's 
VRAM size if 3GB < VRAM < 3/4 RAM,
- * otherwise 3/4 RAM size).
+ * Restrict the size of GTT domain in MiB for testing. The default is -1 (Use 
1/2 RAM, minimum value is 3GB).
  */
 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)");
 module_param_named(gttsize, amdgpu_gtt_size, int, 0600);
-- 
2.35.1

Re: [PATCH] drm/amdgpu: add mb for si

[Christian König]

Am 18.11.22 um 08:48 schrieb Zhenneng Li:

During reboot test on arm64 platform, it may failure on boot,
so add this mb in smc.

The error message are as follows:
[6.996395][ 7] [  T295] [drm:amdgpu_device_ip_late_init [amdgpu]] *ERROR*
late_init of IP block  failed -22
[7.006919][ 7] [  T295] amdgpu :04:00.0: amdgpu_device_ip_late_init 
failed
[7.014224][ 7] [  T295] amdgpu :04:00.0: Fatal error during GPU init


Memory barries are not supposed to be sprinkled around like this, you 
need to give a detailed explanation why this is necessary.


Regards,
Christian.



Signed-off-by: Zhenneng Li 
---
  drivers/gpu/drm/amd/pm/legacy-dpm/si_smc.c | 2 ++
  1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_smc.c 
b/drivers/gpu/drm/amd/pm/legacy-dpm/si_smc.c
index 8f994ffa9cd1..c7656f22278d 100644
--- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_smc.c
+++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_smc.c
@@ -155,6 +155,8 @@ bool amdgpu_si_is_smc_running(struct amdgpu_device *adev)
u32 rst = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
  
+	mb();

+
if (!(rst & RST_REG) && !(clk & CK_DISABLE))
return true;