[bug report] drm/amd/display: Add connector HPD trigger debugfs entry
Hello Eryk Brol,
This is a semi-automatic email about new static checker warnings.
The patch 6f77b2ac6280: "drm/amd/display: Add connector HPD trigger
debugfs entry" from Aug 10, 2020, leads to the following Smatch
complaint:
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_debugfs.c:1220
trigger_hotplug()
warn: variable dereferenced before check 'aconnector' (see line 1210)
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_debugfs.c
1204 static ssize_t trigger_hotplug(struct file *f, const char __user *buf,
1205 size_t size,
loff_t *pos)
1206 {
1207 struct amdgpu_dm_connector *aconnector =
file_inode(f)->i_private;
1208 struct drm_connector *connector = &aconnector->base;
Not a dereference.
1209 struct dc_link *link = NULL;
1210 struct drm_device *dev = connector->dev;
^^
Argh... dereference.
1211 struct amdgpu_device *adev = drm_to_adev(dev);
1212 enum dc_connection_type new_connection_type =
dc_connection_none;
1213 char *wr_buf = NULL;
1214 uint32_t wr_buf_size = 42;
1215 int max_param_num = 1;
1216 long param[1] = {0};
1217 uint8_t param_nums = 0;
1218 bool ret = false;
1219
1220 if (!aconnector || !aconnector->dc_link)
^^^
Too late. Dead already.
1221 return -EINVAL;
1222
1223 if (size == 0)
regards,
dan carpenter
[PATCH] drm/amd/pm: add missing NotifyPowerSource message mapping for SMU13.0.7
Otherwise, the power source switching will fail due to message
unavailable.
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
index 1b6116cf8b4c..cf6827179fd1 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
@@ -125,6 +125,7 @@ static struct cmn2asic_msg_mapping
smu_v13_0_7_message_map[SMU_MSG_MAX_COUNT] =
MSG_MAP(ArmD3, PPSMC_MSG_ArmD3,
0),
MSG_MAP(AllowGpo, PPSMC_MSG_SetGpoAllow,
0),
MSG_MAP(GetPptLimit,PPSMC_MSG_GetPptLimit,
0),
+ MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource,
0),
};
static struct cmn2asic_mapping smu_v13_0_7_clk_map[SMU_CLK_COUNT] = {
--
2.34.1
RE: [PATCH] drm/amdgpu: Fix uninitialized variable in gfxhub_v1_2_xcp_resume
[AMD Official Use Only - General]
Reviewed-by: Lijo Lazar
Thanks,
Lijo
-Original Message-
From: SHANMUGAM, SRINIVASAN
Sent: Friday, May 19, 2023 10:28 AM
To: Koenig, Christian ; Deucher, Alexander
; Tuikov, Luben ; Lazar, Lijo
; Zhang, Hawking
Cc: amd-gfx@lists.freedesktop.org; SHANMUGAM, SRINIVASAN
Subject: [PATCH] drm/amdgpu: Fix uninitialized variable in
gfxhub_v1_2_xcp_resume
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c:657:6: error: variable 'ret' is used
uninitialized whenever 'if' condition is false
[-Werror,-Wsometimes-uninitialized]
if (!amdgpu_sriov_vf(adev))
^~
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c:660:9: note: uninitialized use occurs
here
return ret;
^~~
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c:657:2: note: remove the 'if' if its
condition is always true
if (!amdgpu_sriov_vf(adev))
^~~
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c:648:9: note: initialize the variable
'ret' to silence this warning
int ret;
^
= 0
1 error generated.
Cc: Luben Tuikov
Cc: Alex Deucher
Cc: Christian König
Cc: Lijo Lazar
Cc: Hawking Zhang
Signed-off-by: Srinivasan Shanmugam
---
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c
b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c
index 8901e73fd700..4dabf910334b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c
@@ -645,7 +645,6 @@ static int gfxhub_v1_2_xcp_resume(void *handle, uint32_t
inst_mask) {
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
bool value;
- int ret;
if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
value = false;
@@ -655,9 +654,9 @@ static int gfxhub_v1_2_xcp_resume(void *handle, uint32_t
inst_mask)
gfxhub_v1_2_xcc_set_fault_enable_default(adev, value, inst_mask);
if (!amdgpu_sriov_vf(adev))
- ret = gfxhub_v1_2_xcc_gart_enable(adev, inst_mask);
+ return gfxhub_v1_2_xcc_gart_enable(adev, inst_mask);
- return ret;
+ return 0;
}
static int gfxhub_v1_2_xcp_suspend(void *handle, uint32_t inst_mask)
--
2.25.1
[PATCH] drm/amd/amdgpu: Fix errors & warnings in mmhub_v1_8.c
Fix below errors & warnings reported by checkpatch:
ERROR: code indent should use tabs where possible
WARNING: please, no space before tabs
WARNING: please, no spaces at the start of a line
WARNING: Prefer 'unsigned int' to bare use of 'unsigned'
ERROR: space prohibited before that '++' (ctx:WxB)
WARNING: Block comments use a trailing */ on a separate line
Cc: Alex Deucher
Cc: Christian König
Signed-off-by: Srinivasan Shanmugam
---
drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c
b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c
index 3648994724c2..8600e42434e7 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c
@@ -271,7 +271,7 @@ static void mmhub_v1_8_init_cache_regs(struct amdgpu_device
*adev)
VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
}
WREG32_SOC15(MMHUB, i, regVM_L2_CNTL4, tmp);
- }
+ }
}
static void mmhub_v1_8_enable_system_domain(struct amdgpu_device *adev)
@@ -328,7 +328,7 @@ static void mmhub_v1_8_disable_identity_aperture(struct
amdgpu_device *adev)
static void mmhub_v1_8_setup_vmid_config(struct amdgpu_device *adev)
{
struct amdgpu_vmhub *hub;
- unsigned num_level, block_size;
+ unsigned int num_level, block_size;
uint32_t tmp, inst_mask;
int i, j;
@@ -776,9 +776,10 @@ static void mmhub_v1_8_inst_reset_ras_err_status(struct
amdgpu_device *adev,
/* reset mmea ras err status */
mmea_cgtt_clk_cntl_addr_dist = regMMEA1_CGTT_CLK_CTRL -
regMMEA0_CGTT_CLK_CTRL;
mmea_err_status_addr_dist = regMMEA1_ERR_STATUS - regMMEA0_ERR_STATUS;
- for (i = 0; i < ARRAY_SIZE(mmhub_v1_8_mmea_err_status_reg); i ++) {
+ for (i = 0; i < ARRAY_SIZE(mmhub_v1_8_mmea_err_status_reg); i++) {
/* force clk branch on for response path
-* set MMEA0_CGTT_CLK_CTRL.SOFT_OVERRIDE_RETURN = 1 */
+* set MMEA0_CGTT_CLK_CTRL.SOFT_OVERRIDE_RETURN = 1
+*/
reg_value = RREG32_SOC15_OFFSET(MMHUB, mmhub_inst,
regMMEA0_CGTT_CLK_CTRL,
i *
mmea_cgtt_clk_cntl_addr_dist);
@@ -814,7 +815,8 @@ static void mmhub_v1_8_inst_reset_ras_err_status(struct
amdgpu_device *adev,
/* reset mm_cane ras err status
* force clk branch on for response path
-* set MM_CANE_ICG_CTRL.SOFT_OVERRIDE_ATRET = 1 */
+* set MM_CANE_ICG_CTRL.SOFT_OVERRIDE_ATRET = 1
+*/
reg_value = RREG32_SOC15(MMHUB, mmhub_inst, regMM_CANE_ICG_CTRL);
reg_value = REG_SET_FIELD(reg_value, MM_CANE_ICG_CTRL,
SOFT_OVERRIDE_ATRET, 1);
--
2.25.1
FW: [PATCH 1/2] drm/amdgpu: fix vga_set_state NULL pointer issue
[AMD Official Use Only - General] From: Likun Gao Fix NULL pointer issue for vga_set_state function as not all the ASIC need this operation. Signed-off-by: Likun Gao --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index ce196badf42d..5af954abd5ba 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1260,7 +1260,8 @@ int emu_soc_asic_init(struct amdgpu_device *adev); /* * ASICs macro. */ -#define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) +#define amdgpu_asic_set_vga_state(adev, state) \ +((adev)->asic_funcs->set_vga_state ? +(adev)->asic_funcs->set_vga_state((adev), (state)) : 0) #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) -- 2.34.1
[PATCH 2/2] drm/amdgpu: retire set_vga_state for some ASIC
[AMD Official Use Only - General]
From: Likun Gao
set_vga_state operation only allowed on SI generation ASIC, retire the realted
function on those ASIC which did not do anything.
Signed-off-by: Likun Gao
---
drivers/gpu/drm/amd/amdgpu/nv.c| 6 --
drivers/gpu/drm/amd/amdgpu/soc15.c | 8
drivers/gpu/drm/amd/amdgpu/soc21.c | 6 --
drivers/gpu/drm/amd/amdgpu/vi.c| 6 --
4 files changed, 26 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index a5f76c9538c4..51523b27a186 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -341,11 +341,6 @@ void nv_grbm_select(struct amdgpu_device *adev,
WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl); }
-static void nv_vga_set_state(struct amdgpu_device *adev, bool state) -{
- /* todo */
-}
-
static bool nv_read_disabled_bios(struct amdgpu_device *adev) {
/* todo */
@@ -654,7 +649,6 @@ static const struct amdgpu_asic_funcs nv_asic_funcs =
.read_register = &nv_read_register,
.reset = &nv_asic_reset,
.reset_method = &nv_asic_reset_method,
- .set_vga_state = &nv_vga_set_state,
.get_xclk = &nv_get_xclk,
.set_uvd_clocks = &nv_set_uvd_clocks,
.set_vce_clocks = &nv_set_vce_clocks,
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 122ba1a505c3..135440b5afe9 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -346,11 +346,6 @@ void soc15_grbm_select(struct amdgpu_device *adev,
WREG32_SOC15_RLC_SHADOW(GC, xcc_id, mmGRBM_GFX_CNTL, grbm_gfx_cntl); }
-static void soc15_vga_set_state(struct amdgpu_device *adev, bool state) -{
- /* todo */
-}
-
static bool soc15_read_disabled_bios(struct amdgpu_device *adev) {
/* todo */
@@ -849,7 +844,6 @@ static const struct amdgpu_asic_funcs soc15_asic_funcs =
.read_register = &soc15_read_register,
.reset = &soc15_asic_reset,
.reset_method = &soc15_asic_reset_method,
- .set_vga_state = &soc15_vga_set_state,
.get_xclk = &soc15_get_xclk,
.set_uvd_clocks = &soc15_set_uvd_clocks,
.set_vce_clocks = &soc15_set_vce_clocks, @@ -871,7 +865,6 @@ static
const struct amdgpu_asic_funcs vega20_asic_funcs =
.read_register = &soc15_read_register,
.reset = &soc15_asic_reset,
.reset_method = &soc15_asic_reset_method,
- .set_vga_state = &soc15_vga_set_state,
.get_xclk = &soc15_get_xclk,
.set_uvd_clocks = &soc15_set_uvd_clocks,
.set_vce_clocks = &soc15_set_vce_clocks, @@ -893,7 +886,6 @@ static
const struct amdgpu_asic_funcs aqua_vanjaram_asic_funcs =
.read_register = &soc15_read_register,
.reset = &soc15_asic_reset,
.reset_method = &soc15_asic_reset_method,
- .set_vga_state = &soc15_vga_set_state,
.get_xclk = &soc15_get_xclk,
.set_uvd_clocks = &soc15_set_uvd_clocks,
.set_vce_clocks = &soc15_set_vce_clocks, diff --git
a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c
index 6bff936a6e55..e5e5d68a4d70 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc21.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
@@ -248,11 +248,6 @@ void soc21_grbm_select(struct amdgpu_device *adev,
WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, grbm_gfx_cntl); }
-static void soc21_vga_set_state(struct amdgpu_device *adev, bool state) -{
- /* todo */
-}
-
static bool soc21_read_disabled_bios(struct amdgpu_device *adev) {
/* todo */
@@ -559,7 +554,6 @@ static const struct amdgpu_asic_funcs soc21_asic_funcs =
.read_register = &soc21_read_register,
.reset = &soc21_asic_reset,
.reset_method = &soc21_asic_reset_method,
- .set_vga_state = &soc21_vga_set_state,
.get_xclk = &soc21_get_xclk,
.set_uvd_clocks = &soc21_set_uvd_clocks,
.set_vce_clocks = &soc21_set_vce_clocks, diff --git
a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index
8e70581960fb..770f2d7a371f 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -580,11 +580,6 @@ void vi_srbm_select(struct amdgpu_device *adev,
WREG32(mmSRBM_GFX_CNTL, srbm_gfx_cntl); }
-static void vi_vga_set_state(struct amdgpu_device *adev, bool state) -{
- /* todo */
-}
-
static bool vi_read_disabled_bios(struct amdgpu_device *adev) {
u32 bus_cntl;
@@ -1435,7 +1430,6 @@ static const struct amdgpu_asic_funcs vi_asic_funcs =
.read_register = &vi_read_register,
.reset = &vi_asic_reset,
.reset_method = &vi_asic_reset_method,
- .set_vga_state = &vi_vga_set_state,
.get_xclk = &vi_get_xclk,
.set_uvd_clocks = &vi_set_uvd_clocks,
.set_vce_clocks = &vi_set_vce_clocks,
--
2.34.1
RE: [PATCH 2/2] drm/amdgpu: retire set_vga_state for some ASIC
[AMD Official Use Only - General]
Series is
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: Gao, Likun
Sent: Friday, May 19, 2023 19:17
To: amd-gfx list
Cc: Zhang, Hawking
Subject: [PATCH 2/2] drm/amdgpu: retire set_vga_state for some ASIC
[AMD Official Use Only - General]
From: Likun Gao
set_vga_state operation only allowed on SI generation ASIC, retire the realted
function on those ASIC which did not do anything.
Signed-off-by: Likun Gao
---
drivers/gpu/drm/amd/amdgpu/nv.c| 6 --
drivers/gpu/drm/amd/amdgpu/soc15.c | 8
drivers/gpu/drm/amd/amdgpu/soc21.c | 6 --
drivers/gpu/drm/amd/amdgpu/vi.c| 6 --
4 files changed, 26 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index a5f76c9538c4..51523b27a186 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -341,11 +341,6 @@ void nv_grbm_select(struct amdgpu_device *adev,
WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl); }
-static void nv_vga_set_state(struct amdgpu_device *adev, bool state) -{
- /* todo */
-}
-
static bool nv_read_disabled_bios(struct amdgpu_device *adev) {
/* todo */
@@ -654,7 +649,6 @@ static const struct amdgpu_asic_funcs nv_asic_funcs =
.read_register = &nv_read_register,
.reset = &nv_asic_reset,
.reset_method = &nv_asic_reset_method,
- .set_vga_state = &nv_vga_set_state,
.get_xclk = &nv_get_xclk,
.set_uvd_clocks = &nv_set_uvd_clocks,
.set_vce_clocks = &nv_set_vce_clocks, diff --git
a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 122ba1a505c3..135440b5afe9 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -346,11 +346,6 @@ void soc15_grbm_select(struct amdgpu_device *adev,
WREG32_SOC15_RLC_SHADOW(GC, xcc_id, mmGRBM_GFX_CNTL, grbm_gfx_cntl); }
-static void soc15_vga_set_state(struct amdgpu_device *adev, bool state) -{
- /* todo */
-}
-
static bool soc15_read_disabled_bios(struct amdgpu_device *adev) {
/* todo */
@@ -849,7 +844,6 @@ static const struct amdgpu_asic_funcs soc15_asic_funcs =
.read_register = &soc15_read_register,
.reset = &soc15_asic_reset,
.reset_method = &soc15_asic_reset_method,
- .set_vga_state = &soc15_vga_set_state,
.get_xclk = &soc15_get_xclk,
.set_uvd_clocks = &soc15_set_uvd_clocks,
.set_vce_clocks = &soc15_set_vce_clocks, @@ -871,7 +865,6 @@ static
const struct amdgpu_asic_funcs vega20_asic_funcs =
.read_register = &soc15_read_register,
.reset = &soc15_asic_reset,
.reset_method = &soc15_asic_reset_method,
- .set_vga_state = &soc15_vga_set_state,
.get_xclk = &soc15_get_xclk,
.set_uvd_clocks = &soc15_set_uvd_clocks,
.set_vce_clocks = &soc15_set_vce_clocks, @@ -893,7 +886,6 @@ static
const struct amdgpu_asic_funcs aqua_vanjaram_asic_funcs =
.read_register = &soc15_read_register,
.reset = &soc15_asic_reset,
.reset_method = &soc15_asic_reset_method,
- .set_vga_state = &soc15_vga_set_state,
.get_xclk = &soc15_get_xclk,
.set_uvd_clocks = &soc15_set_uvd_clocks,
.set_vce_clocks = &soc15_set_vce_clocks, diff --git
a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c
index 6bff936a6e55..e5e5d68a4d70 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc21.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
@@ -248,11 +248,6 @@ void soc21_grbm_select(struct amdgpu_device *adev,
WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, grbm_gfx_cntl); }
-static void soc21_vga_set_state(struct amdgpu_device *adev, bool state) -{
- /* todo */
-}
-
static bool soc21_read_disabled_bios(struct amdgpu_device *adev) {
/* todo */
@@ -559,7 +554,6 @@ static const struct amdgpu_asic_funcs soc21_asic_funcs =
.read_register = &soc21_read_register,
.reset = &soc21_asic_reset,
.reset_method = &soc21_asic_reset_method,
- .set_vga_state = &soc21_vga_set_state,
.get_xclk = &soc21_get_xclk,
.set_uvd_clocks = &soc21_set_uvd_clocks,
.set_vce_clocks = &soc21_set_vce_clocks, diff --git
a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index
8e70581960fb..770f2d7a371f 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -580,11 +580,6 @@ void vi_srbm_select(struct amdgpu_device *adev,
WREG32(mmSRBM_GFX_CNTL, srbm_gfx_cntl); }
-static void vi_vga_set_state(struct amdgpu_device *adev, bool state) -{
- /* todo */
-}
-
static bool vi_read_disabled_bios(struct amdgpu_device *adev) {
u32 bus_cntl;
@@ -1435,7 +1430,6 @@ static const struct amdgpu_asic_funcs vi_asic_funcs =
.read_register = &vi_read_register,
.reset = &vi_asic_reset,
.reset_method = &vi_asic_reset_method,
- .set_vga_state = &vi_vga_set
[PATCH v2] drm/amdgpu: Fix the EPERM error when get user pages
Check and pass the readonly flags when set amdgpu_ttm_tt flags
for readonly ptr pages. Otherwise, there is EPERM error returned
during the KFDExceptionTest.PermissionFaultUserPointer test on
ploaris10.
Signed-off-by: Ma Jun
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index d426333e865a..85d1087439c0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -1036,10 +1036,17 @@ static int init_user_pages(struct kgd_mem *mem,
uint64_t user_addr,
struct ttm_operation_ctx ctx = { true, false };
struct hmm_range *range;
int ret = 0;
+ uint32_t tt_flags = 0;
mutex_lock(&process_info->lock);
- ret = amdgpu_ttm_tt_set_userptr(&bo->tbo, user_addr, 0);
+ if (!(mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE))
+ tt_flags |= AMDGPU_GEM_USERPTR_READONLY;
+ else
+ tt_flags = 0;
+
+
+ ret = amdgpu_ttm_tt_set_userptr(&bo->tbo, user_addr, tt_flags);
if (ret) {
pr_err("%s: Failed to set userptr: %d\n", __func__, ret);
goto out;
--
2.34.1
RE: [PATCH] drm/amd/pm: add missing NotifyPowerSource message mapping for SMU13.0.7
[Public]
Looks it's better to add a Fixes tag like Fixes: 4dd9b5392c57 ("drm/amd/pm: fix
possible power mode mismatch between driver and PMFW"), if I understand it
correctly.
Regards,
Guchun
> -Original Message-
> From: amd-gfx On Behalf Of Evan
> Quan
> Sent: Friday, May 19, 2023 3:53 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Quan, Evan
>
> Subject: [PATCH] drm/amd/pm: add missing NotifyPowerSource message
> mapping for SMU13.0.7
>
> Otherwise, the power source switching will fail due to message unavailable.
>
> Signed-off-by: Evan Quan
> ---
> drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
> index 1b6116cf8b4c..cf6827179fd1 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
> @@ -125,6 +125,7 @@ static struct cmn2asic_msg_mapping
> smu_v13_0_7_message_map[SMU_MSG_MAX_COUNT] =
> MSG_MAP(ArmD3, PPSMC_MSG_ArmD3,
> 0),
> MSG_MAP(AllowGpo, PPSMC_MSG_SetGpoAllow,
> 0),
> MSG_MAP(GetPptLimit,
> PPSMC_MSG_GetPptLimit, 0),
> + MSG_MAP(NotifyPowerSource,
> PPSMC_MSG_NotifyPowerSource, 0),
> };
>
> static struct cmn2asic_mapping smu_v13_0_7_clk_map[SMU_CLK_COUNT] =
> {
> --
> 2.34.1
Re: [PATCH 06/29] drm/amdgpu: keep amdgpu_ctx_mgr in ctx structure
On Wed, 10 May 2023 at 22:24, Alex Deucher wrote:
>
> From: James Zhu
>
> Keep amdgpu_ctx_mgr in ctx structure to track fpriv.
>
> Signed-off-by: James Zhu
> Acked-by: Lijo Lazar
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 1 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h | 1 +
> 2 files changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
> index e3d047663d61..06d68a08251a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
> @@ -332,6 +332,7 @@ static int amdgpu_ctx_init(struct amdgpu_ctx_mgr *mgr,
> int32_t priority,
> else
> ctx->stable_pstate = current_stable_pstate;
>
> + ctx->ctx_mgr = &(fpriv->ctx_mgr);
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
> index 5fd79f94e2d0..85376baaa92f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
> @@ -57,6 +57,7 @@ struct amdgpu_ctx {
> unsigned long ras_counter_ce;
> unsigned long ras_counter_ue;
> uint32_tstable_pstate;
> + struct amdgpu_ctx_mgr *ctx_mgr;
> };
>
> struct amdgpu_ctx_mgr {
> --
> 2.40.1
>
Hi
This isn't compiling for me with clang 16
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c:348:19: error: use of
undeclared identifier 'fpriv'
ctx->ctx_mgr = &(fpriv->ctx_mgr);
^
1 error generated.
Cheers
Mike
[PATCH] drm/amdgpu: Fix unused amdgpu_acpi_get_numa_info function in amdgpu_acpi_get_node_id()
Fix the below compiler complaining error:
drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c:860:33: error: unused function
'amdgpu_acpi_get_numa_info' [-Werror,-Wunused-function]
static struct amdgpu_numa_info *amdgpu_acpi_get_numa_info(uint32_t pxm)
^
1 error generated.
By guarding amdgpu_acpi_get_numa_info function,
only when CONFIG_ACPI_NUMA is enabled.
Cc: Christian König
Cc: Lijo Lazar
Cc: Luben Tuikov
Cc: Alex Deucher
Signed-off-by: Srinivasan Shanmugam
---
drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
index 7150c09933cf..9433596076d0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
@@ -857,6 +857,7 @@ static inline uint64_t amdgpu_acpi_get_numa_size(int nid)
return managed_pages * PAGE_SIZE;
}
+#ifdef CONFIG_ACPI_NUMA
static struct amdgpu_numa_info *amdgpu_acpi_get_numa_info(uint32_t pxm)
{
struct amdgpu_numa_info *numa_info;
@@ -886,6 +887,7 @@ static struct amdgpu_numa_info
*amdgpu_acpi_get_numa_info(uint32_t pxm)
return numa_info;
}
+#endif
/**
* amdgpu_acpi_get_node_id - obtain the NUMA node id for corresponding amdgpu
--
2.25.1
[PATCH] drm/amdgpu: Mark mmhub_v1_8_mmea_err_status_reg as __maybe_unused
Silencing the compiler from below compilation error:
drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c:704:23: error: variable
'mmhub_v1_8_mmea_err_status_reg' is not needed and will not be emitted
[-Werror,-Wunneeded-internal-declaration]
static const uint32_t mmhub_v1_8_mmea_err_status_reg[] = {
^
1 error generated.
Mark the variable as __maybe_unused to make it clear to clang that this
is expected, so there is no more warning.
Cc: Christian König
Cc: Lijo Lazar
Cc: Luben Tuikov
Cc: Alex Deucher
Signed-off-by: Srinivasan Shanmugam
---
drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c
b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c
index 3648994724c2..cba087e529c0 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c
@@ -701,6 +701,7 @@ static void mmhub_v1_8_reset_ras_error_count(struct
amdgpu_device *adev)
mmhub_v1_8_inst_reset_ras_error_count(adev, i);
}
+__maybe_unused
static const uint32_t mmhub_v1_8_mmea_err_status_reg[] = {
regMMEA0_ERR_STATUS,
regMMEA1_ERR_STATUS,
--
2.25.1
RE: [PATCH] drm/amdgpu: Fix unused amdgpu_acpi_get_numa_info function in amdgpu_acpi_get_node_id()
[AMD Official Use Only - General]
Thanks for the fix. Please use move the +#ifdef CONFIG_ACPI_NUMA up a bit to
cover amdgpu_acpi_get_numa_size as well.
Thanks,
Lijo
-Original Message-
From: SHANMUGAM, SRINIVASAN
Sent: Friday, May 19, 2023 5:51 PM
To: Koenig, Christian ; Deucher, Alexander
; Tuikov, Luben ; Lazar, Lijo
Cc: amd-gfx@lists.freedesktop.org; SHANMUGAM, SRINIVASAN
Subject: [PATCH] drm/amdgpu: Fix unused amdgpu_acpi_get_numa_info function in
amdgpu_acpi_get_node_id()
Fix the below compiler complaining error:
drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c:860:33: error: unused function
'amdgpu_acpi_get_numa_info' [-Werror,-Wunused-function] static struct
amdgpu_numa_info *amdgpu_acpi_get_numa_info(uint32_t pxm)
^
1 error generated.
By guarding amdgpu_acpi_get_numa_info function, only when CONFIG_ACPI_NUMA is
enabled.
Cc: Christian König
Cc: Lijo Lazar
Cc: Luben Tuikov
Cc: Alex Deucher
Signed-off-by: Srinivasan Shanmugam
---
drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
index 7150c09933cf..9433596076d0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
@@ -857,6 +857,7 @@ static inline uint64_t amdgpu_acpi_get_numa_size(int nid)
return managed_pages * PAGE_SIZE;
}
+#ifdef CONFIG_ACPI_NUMA
static struct amdgpu_numa_info *amdgpu_acpi_get_numa_info(uint32_t pxm) {
struct amdgpu_numa_info *numa_info;
@@ -886,6 +887,7 @@ static struct amdgpu_numa_info
*amdgpu_acpi_get_numa_info(uint32_t pxm)
return numa_info;
}
+#endif
/**
* amdgpu_acpi_get_node_id - obtain the NUMA node id for corresponding amdgpu
--
2.25.1
[PATCH v2] drm/amdgpu: Fix unused amdgpu_acpi_get_numa_info function in amdgpu_acpi_get_node_id()
Fix the below compiler complaining error:
drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c:860:33: error: unused function
'amdgpu_acpi_get_numa_info' [-Werror,-Wunused-function]
static struct amdgpu_numa_info *amdgpu_acpi_get_numa_info(uint32_t pxm)
^
1 error generated.
By guarding amdgpu_acpi_get_numa_info & amdgpu_acpi_get_numa_size
function, only when CONFIG_ACPI_NUMA is enabled.
Suggested-by: Lijo Lazar
Cc: Christian König
Cc: Lijo Lazar
Cc: Luben Tuikov
Cc: Alex Deucher
Signed-off-by: Srinivasan Shanmugam
---
v2:
- Guard even amdgpu_acpi_get_numa_size under CONFIG_ACPI_NUMA (Lijo)
drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
index 7150c09933cf..1a66febf6981 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
@@ -841,6 +841,7 @@ int amdgpu_acpi_smart_shift_update(struct drm_device *dev,
enum amdgpu_ss ss_sta
return r;
}
+#ifdef CONFIG_ACPI_NUMA
static inline uint64_t amdgpu_acpi_get_numa_size(int nid)
{
/* This is directly using si_meminfo_node implementation as the
@@ -886,6 +887,7 @@ static struct amdgpu_numa_info
*amdgpu_acpi_get_numa_info(uint32_t pxm)
return numa_info;
}
+#endif
/**
* amdgpu_acpi_get_node_id - obtain the NUMA node id for corresponding amdgpu
--
2.25.1
RE: [PATCH v2] drm/amdgpu: Fix unused amdgpu_acpi_get_numa_info function in amdgpu_acpi_get_node_id()
[AMD Official Use Only - General]
Reviewed-by: Lijo Lazar
Thanks,
Lijo
-Original Message-
From: SHANMUGAM, SRINIVASAN
Sent: Friday, May 19, 2023 6:53 PM
To: Koenig, Christian ; Deucher, Alexander
; Tuikov, Luben ; Lazar, Lijo
Cc: amd-gfx@lists.freedesktop.org; SHANMUGAM, SRINIVASAN
Subject: [PATCH v2] drm/amdgpu: Fix unused amdgpu_acpi_get_numa_info function
in amdgpu_acpi_get_node_id()
Fix the below compiler complaining error:
drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c:860:33: error: unused function
'amdgpu_acpi_get_numa_info' [-Werror,-Wunused-function] static struct
amdgpu_numa_info *amdgpu_acpi_get_numa_info(uint32_t pxm)
^
1 error generated.
By guarding amdgpu_acpi_get_numa_info & amdgpu_acpi_get_numa_size function,
only when CONFIG_ACPI_NUMA is enabled.
Suggested-by: Lijo Lazar
Cc: Christian König
Cc: Lijo Lazar
Cc: Luben Tuikov
Cc: Alex Deucher
Signed-off-by: Srinivasan Shanmugam
---
v2:
- Guard even amdgpu_acpi_get_numa_size under CONFIG_ACPI_NUMA (Lijo)
drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
index 7150c09933cf..1a66febf6981 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
@@ -841,6 +841,7 @@ int amdgpu_acpi_smart_shift_update(struct drm_device *dev,
enum amdgpu_ss ss_sta
return r;
}
+#ifdef CONFIG_ACPI_NUMA
static inline uint64_t amdgpu_acpi_get_numa_size(int nid) {
/* This is directly using si_meminfo_node implementation as the @@
-886,6 +887,7 @@ static struct amdgpu_numa_info
*amdgpu_acpi_get_numa_info(uint32_t pxm)
return numa_info;
}
+#endif
/**
* amdgpu_acpi_get_node_id - obtain the NUMA node id for corresponding amdgpu
--
2.25.1
Re: [PATCH 06/29] drm/amdgpu: keep amdgpu_ctx_mgr in ctx structure
On Fri, May 19, 2023 at 8:16 AM Mike Lothian wrote:
>
> On Wed, 10 May 2023 at 22:24, Alex Deucher wrote:
> >
> > From: James Zhu
> >
> > Keep amdgpu_ctx_mgr in ctx structure to track fpriv.
> >
> > Signed-off-by: James Zhu
> > Acked-by: Lijo Lazar
> > Signed-off-by: Alex Deucher
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 1 +
> > drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h | 1 +
> > 2 files changed, 2 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
> > index e3d047663d61..06d68a08251a 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
> > @@ -332,6 +332,7 @@ static int amdgpu_ctx_init(struct amdgpu_ctx_mgr *mgr,
> > int32_t priority,
> > else
> > ctx->stable_pstate = current_stable_pstate;
> >
> > + ctx->ctx_mgr = &(fpriv->ctx_mgr);
> > return 0;
> > }
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
> > index 5fd79f94e2d0..85376baaa92f 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
> > @@ -57,6 +57,7 @@ struct amdgpu_ctx {
> > unsigned long ras_counter_ce;
> > unsigned long ras_counter_ue;
> > uint32_tstable_pstate;
> > + struct amdgpu_ctx_mgr *ctx_mgr;
> > };
> >
> > struct amdgpu_ctx_mgr {
> > --
> > 2.40.1
> >
>
> Hi
>
> This isn't compiling for me with clang 16
>
> drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c:348:19: error: use of
> undeclared identifier 'fpriv'
>ctx->ctx_mgr = &(fpriv->ctx_mgr);
> ^
> 1 error generated.
When this patch was originally written the function had fpriv defined,
but it got missed after a rebase. Fixed up now.
Alex
>
> Cheers
>
> Mike
Re: [PATCH 2/2] drm/amdgpu: Disable interrupt tracker on NBIOv7.9
Series is:
Reviewed-by: Alex Deucher
On Fri, May 19, 2023 at 12:42 AM Shiwu Zhang wrote:
>
> From: Lijo Lazar
>
> Enabling nBIF interrupt history tracker prevents LCLK deep sleep,
> hence disable it
>
> Signed-off-by: Lijo Lazar
> Reviewed-by: Hawking Zhang
> ---
> drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c| 2 ++
> drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_9_0_offset.h | 2 ++
> 2 files changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c
> b/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c
> index ad70086de9b5..e082f6343d20 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c
> @@ -432,6 +432,8 @@ static void nbio_v7_9_init_registers(struct amdgpu_device
> *adev)
> WREG32_SOC15(NBIO, 0, regXCC_DOORBELL_FENCE,
> 0xff & ~(adev->gfx.xcc_mask));
>
> + WREG32_SOC15(NBIO, 0, regBIFC_GFX_INT_MONITOR_MASK, 0x7ff);
> +
> inst_mask = adev->aid_mask & ~1U;
> for_each_inst(i, inst_mask) {
> WREG32_SOC15_EXT(NBIO, i, regXCC_DOORBELL_FENCE, i,
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_9_0_offset.h
> b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_9_0_offset.h
> index 033f2796c1e3..c8a15c8f4822 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_9_0_offset.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_9_0_offset.h
> @@ -6201,6 +6201,8 @@
> #define regNBIF_SHUB_TODET_SYNCFLOOD_CTRL2_BASE_IDX 8
> #define regBIFC_BME_ERR_LOG_HB
>0xe8ab
> #define regBIFC_BME_ERR_LOG_HB_BASE_IDX 8
> +#define regBIFC_GFX_INT_MONITOR_MASK
>0xe8ad
> +#define regBIFC_GFX_INT_MONITOR_MASK_BASE_IDX 8
> #define regBIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC
>0xe8c0
> #define regBIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC_BASE_IDX 8
> #define regBIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC
>0xe8c1
> --
> 2.17.1
>
[PATCH] drm/amdkfd: Align partition memory size to page size
The compute partition memory size calculated from KFD_XCP_MEMORY_SIZE
may not align to page size if xcp_mgr->num_xcp_per_mem_partition is 6.
Change the KFD_XCP_MEMORY_SIZE macro to return page align size, so KFD
node memory size reported in sysfs is page align size, to avoid
application VRAM allocation failure because application may use the size
directly and Thunk requires the memory allocation size is page size
align.
Signed-off-by: Philip Yang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index 5de92c9ab18f..66f80b9ab0c5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -804,7 +804,7 @@ u64 amdgpu_amdkfd_xcp_memory_size(struct amdgpu_device
*adev, int xcp_id)
if (adev->gmc.num_mem_partitions && xcp_id >= 0 && mem_id >= 0) {
tmp = adev->gmc.mem_partitions[mem_id].size;
do_div(tmp, adev->xcp_mgr->num_xcp_per_mem_partition);
- return tmp;
+ return ALIGN_DOWN(tmp, PAGE_SIZE);
} else {
return adev->gmc.real_vram_size;
}
--
2.35.1
[linux-next:master] BUILD SUCCESS WITH WARNING dbd91ef4e91c1ce3a24429f5fb3876b7a0306733
tree/branch: INFO setup_repo_specs: /db/releases/20230519164737/lkp-src/repo/*/linux-next https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master branch HEAD: dbd91ef4e91c1ce3a24429f5fb3876b7a0306733 Add linux-next specific files for 20230519 Warning reports: https://lore.kernel.org/oe-kbuild-all/202304220118.nyuw8ip0-...@intel.com https://lore.kernel.org/oe-kbuild-all/202305132244.dwzbucud-...@intel.com https://lore.kernel.org/oe-kbuild-all/202305182345.ltmlwg84-...@intel.com https://lore.kernel.org/oe-kbuild-all/202305190358.iefjnrau-...@intel.com Warning: (recently discovered and may have been fixed) drivers/base/regmap/regcache-maple.c:113:23: warning: 'lower_index' is used uninitialized [-Wuninitialized] drivers/base/regmap/regcache-maple.c:113:36: warning: 'lower_last' is used uninitialized [-Wuninitialized] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:6396:21: warning: variable 'count' set but not used [-Wunused-but-set-variable] drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c:499:13: warning: variable 'j' set but not used [-Wunused-but-set-variable] drivers/net/arcnet/com20020.c:74:7: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic] Unverified Warning (likely false positive, please contact us if interested): fs/ext4/verity.c:316 ext4_get_verity_descriptor_location() error: uninitialized symbol 'desc_size_disk'. fs/xfs/scrub/fscounters.c:459 xchk_fscounters() warn: ignoring unreachable code. kernel/events/uprobes.c:478 uprobe_write_opcode() warn: passing zero to 'PTR_ERR' Warning ids grouped by kconfigs: gcc_recent_errors |-- alpha-allyesconfig | |-- drivers-gpu-drm-amd-amdgpu-..-display-amdgpu_dm-amdgpu_dm.c:warning:variable-count-set-but-not-used | `-- drivers-gpu-drm-amd-amdgpu-amdgpu_gfx.c:warning:variable-j-set-but-not-used |-- alpha-randconfig-r036-20230517 | `-- drivers-gpu-drm-amd-amdgpu-amdgpu_gfx.c:warning:variable-j-set-but-not-used |-- arc-allyesconfig | |-- drivers-base-regmap-regcache-maple.c:warning:lower_index-is-used-uninitialized | |-- drivers-base-regmap-regcache-maple.c:warning:lower_last-is-used-uninitialized | |-- drivers-gpu-drm-amd-amdgpu-..-display-amdgpu_dm-amdgpu_dm.c:warning:variable-count-set-but-not-used | `-- drivers-gpu-drm-amd-amdgpu-amdgpu_gfx.c:warning:variable-j-set-but-not-used |-- arc-vdk_hs38_defconfig | |-- drivers-base-regmap-regcache-maple.c:warning:lower_index-is-used-uninitialized | `-- drivers-base-regmap-regcache-maple.c:warning:lower_last-is-used-uninitialized |-- arm-allmodconfig | |-- drivers-gpu-drm-amd-amdgpu-..-display-amdgpu_dm-amdgpu_dm.c:warning:variable-count-set-but-not-used | `-- drivers-gpu-drm-amd-amdgpu-amdgpu_gfx.c:warning:variable-j-set-but-not-used |-- arm-allyesconfig | |-- drivers-gpu-drm-amd-amdgpu-..-display-amdgpu_dm-amdgpu_dm.c:warning:variable-count-set-but-not-used | `-- drivers-gpu-drm-amd-amdgpu-amdgpu_gfx.c:warning:variable-j-set-but-not-used |-- arm64-allyesconfig | |-- drivers-gpu-drm-amd-amdgpu-..-display-amdgpu_dm-amdgpu_dm.c:warning:variable-count-set-but-not-used | `-- drivers-gpu-drm-amd-amdgpu-amdgpu_gfx.c:warning:variable-j-set-but-not-used |-- arm64-randconfig-r015-20230517 | `-- drivers-gpu-drm-amd-amdgpu-amdgpu_gfx.c:warning:variable-j-set-but-not-used |-- i386-allyesconfig | |-- drivers-gpu-drm-amd-amdgpu-..-display-amdgpu_dm-amdgpu_dm.c:warning:variable-count-set-but-not-used | `-- drivers-gpu-drm-amd-amdgpu-amdgpu_gfx.c:warning:variable-j-set-but-not-used |-- i386-randconfig-m021 | |-- kernel-events-uprobes.c-uprobe_write_opcode()-warn:passing-zero-to-PTR_ERR | `-- lib-stackdepot.c-stack_print()-warn:unsigned-stack-size-is-never-less-than-zero. |-- i386-randconfig-s001 | |-- mm-page_owner.c:sparse:sparse:symbol-page_owner_threshold_get-was-not-declared.-Should-it-be-static | `-- mm-page_owner.c:sparse:sparse:symbol-page_owner_threshold_set-was-not-declared.-Should-it-be-static |-- i386-randconfig-s002 | |-- mm-page_owner.c:sparse:sparse:symbol-page_owner_threshold_get-was-not-declared.-Should-it-be-static | `-- mm-page_owner.c:sparse:sparse:symbol-page_owner_threshold_set-was-not-declared.-Should-it-be-static |-- i386-randconfig-s003 | |-- mm-page_owner.c:sparse:sparse:symbol-page_owner_threshold_get-was-not-declared.-Should-it-be-static | `-- mm-page_owner.c:sparse:sparse:symbol-page_owner_threshold_set-was-not-declared.-Should-it-be-static |-- ia64-allmodconfig | |-- drivers-gpu-drm-amd-amdgpu-..-display-amdgpu_dm-amdgpu_dm.c:warning:variable-count-set-but-not-used | `-- drivers-gpu-drm-amd-amdgpu-amdgpu_gfx.c:warning:variable-j-set-but-not-used |-- ia64-allyesconfig | |-- drivers-gpu-drm-amd-amdgpu-..-display-amdgpu_dm-amdgpu_dm.c:warning:variable-count-set-but-not-used | `-- drivers-gpu-drm-amd-amdgpu-amdgpu_gfx.c:warning:variable-j-set-but-not-used |-
[PATCH] drm/radeon: fix possible division-by-zero errors
Function rv740_get_decoded_reference_divider() may return 0 due to
unpredictable reference divider value calculated in
radeon_atom_get_clock_dividers(). This will lead to
division-by-zero error once that value is used as a divider
in calculating 'clk_s'.
While unlikely, this issue should nonetheless be prevented so add a
sanity check for such cases by testing 'decoded_ref' value against 0.
Found by Linux Verification Center (linuxtesting.org) with static
analysis tool SVACE.
Fixes: 66229b200598 ("drm/radeon/kms: add dpm support for rv7xx (v4)")
Signed-off-by: Nikita Zhandarovich
---
drivers/gpu/drm/radeon/cypress_dpm.c | 7 +--
drivers/gpu/drm/radeon/ni_dpm.c | 7 +--
drivers/gpu/drm/radeon/rv740_dpm.c | 7 +--
3 files changed, 15 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/radeon/cypress_dpm.c
b/drivers/gpu/drm/radeon/cypress_dpm.c
index fdddbbaecbb7..3678b7e384e1 100644
--- a/drivers/gpu/drm/radeon/cypress_dpm.c
+++ b/drivers/gpu/drm/radeon/cypress_dpm.c
@@ -555,10 +555,13 @@ static int cypress_populate_mclk_value(struct
radeon_device *rdev,
if (radeon_atombios_get_asic_ss_info(rdev, &ss,
ASIC_INTERNAL_MEMORY_SS,
vco_freq)) {
+ u32 clk_s, clk_v;
u32 reference_clock = rdev->clock.mpll.reference_freq;
u32 decoded_ref =
rv740_get_decoded_reference_divider(dividers.ref_div);
- u32 clk_s = reference_clock * 5 / (decoded_ref *
ss.rate);
- u32 clk_v = ss.percentage *
+ if (!decoded_ref)
+ return -EINVAL;
+ clk_s = reference_clock * 5 / (decoded_ref * ss.rate);
+ clk_v = ss.percentage *
(0x4000 * dividers.whole_fb_div + 0x800 *
dividers.frac_fb_div) / (clk_s * 625);
mpll_ss1 &= ~CLKV_MASK;
diff --git a/drivers/gpu/drm/radeon/ni_dpm.c b/drivers/gpu/drm/radeon/ni_dpm.c
index 672d2239293e..9ce3e5635efc 100644
--- a/drivers/gpu/drm/radeon/ni_dpm.c
+++ b/drivers/gpu/drm/radeon/ni_dpm.c
@@ -2239,10 +2239,13 @@ static int ni_populate_mclk_value(struct radeon_device
*rdev,
if (radeon_atombios_get_asic_ss_info(rdev, &ss,
ASIC_INTERNAL_MEMORY_SS,
vco_freq)) {
+ u32 clk_s, clk_v;
u32 reference_clock = rdev->clock.mpll.reference_freq;
u32 decoded_ref =
rv740_get_decoded_reference_divider(dividers.ref_div);
- u32 clk_s = reference_clock * 5 / (decoded_ref *
ss.rate);
- u32 clk_v = ss.percentage *
+ if (!decoded_ref)
+ return -EINVAL;
+ clk_s = reference_clock * 5 / (decoded_ref * ss.rate);
+ clk_v = ss.percentage *
(0x4000 * dividers.whole_fb_div + 0x800 *
dividers.frac_fb_div) / (clk_s * 625);
mpll_ss1 &= ~CLKV_MASK;
diff --git a/drivers/gpu/drm/radeon/rv740_dpm.c
b/drivers/gpu/drm/radeon/rv740_dpm.c
index d57a3e1df8d6..ca76efa0f59d 100644
--- a/drivers/gpu/drm/radeon/rv740_dpm.c
+++ b/drivers/gpu/drm/radeon/rv740_dpm.c
@@ -247,10 +247,13 @@ int rv740_populate_mclk_value(struct radeon_device *rdev,
if (radeon_atombios_get_asic_ss_info(rdev, &ss,
ASIC_INTERNAL_MEMORY_SS,
vco_freq)) {
+ u32 clk_s, clk_v;
u32 reference_clock = rdev->clock.mpll.reference_freq;
u32 decoded_ref =
rv740_get_decoded_reference_divider(dividers.ref_div);
- u32 clk_s = reference_clock * 5 / (decoded_ref *
ss.rate);
- u32 clk_v = 0x4 * ss.percentage *
+ if (!decoded_ref)
+ return -EINVAL;
+ clk_s = reference_clock * 5 / (decoded_ref * ss.rate);
+ clk_v = 0x4 * ss.percentage *
(dividers.whole_fb_div + (dividers.frac_fb_div
/ 8)) / (clk_s * 1);
mpll_ss1 &= ~CLKV_MASK;
--
2.25.1
Re: [PATCH] drm/amd/amdgpu: Fix errors & warnings in mmhub_v1_8.c
On Fri, May 19, 2023 at 6:59 AM Srinivasan Shanmugam
wrote:
>
> Fix below errors & warnings reported by checkpatch:
>
> ERROR: code indent should use tabs where possible
> WARNING: please, no space before tabs
> WARNING: please, no spaces at the start of a line
> WARNING: Prefer 'unsigned int' to bare use of 'unsigned'
> ERROR: space prohibited before that '++' (ctx:WxB)
> WARNING: Block comments use a trailing */ on a separate line
>
> Cc: Alex Deucher
> Cc: Christian König
> Signed-off-by: Srinivasan Shanmugam
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c | 12 +++-
> 1 file changed, 7 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c
> b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c
> index 3648994724c2..8600e42434e7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c
> @@ -271,7 +271,7 @@ static void mmhub_v1_8_init_cache_regs(struct
> amdgpu_device *adev)
> VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
> }
> WREG32_SOC15(MMHUB, i, regVM_L2_CNTL4, tmp);
> - }
> + }
> }
>
> static void mmhub_v1_8_enable_system_domain(struct amdgpu_device *adev)
> @@ -328,7 +328,7 @@ static void mmhub_v1_8_disable_identity_aperture(struct
> amdgpu_device *adev)
> static void mmhub_v1_8_setup_vmid_config(struct amdgpu_device *adev)
> {
> struct amdgpu_vmhub *hub;
> - unsigned num_level, block_size;
> + unsigned int num_level, block_size;
> uint32_t tmp, inst_mask;
> int i, j;
>
> @@ -776,9 +776,10 @@ static void mmhub_v1_8_inst_reset_ras_err_status(struct
> amdgpu_device *adev,
> /* reset mmea ras err status */
> mmea_cgtt_clk_cntl_addr_dist = regMMEA1_CGTT_CLK_CTRL -
> regMMEA0_CGTT_CLK_CTRL;
> mmea_err_status_addr_dist = regMMEA1_ERR_STATUS - regMMEA0_ERR_STATUS;
> - for (i = 0; i < ARRAY_SIZE(mmhub_v1_8_mmea_err_status_reg); i ++) {
> + for (i = 0; i < ARRAY_SIZE(mmhub_v1_8_mmea_err_status_reg); i++) {
> /* force clk branch on for response path
> -* set MMEA0_CGTT_CLK_CTRL.SOFT_OVERRIDE_RETURN = 1 */
> +* set MMEA0_CGTT_CLK_CTRL.SOFT_OVERRIDE_RETURN = 1
> +*/
> reg_value = RREG32_SOC15_OFFSET(MMHUB, mmhub_inst,
> regMMEA0_CGTT_CLK_CTRL,
> i *
> mmea_cgtt_clk_cntl_addr_dist);
> @@ -814,7 +815,8 @@ static void mmhub_v1_8_inst_reset_ras_err_status(struct
> amdgpu_device *adev,
>
> /* reset mm_cane ras err status
> * force clk branch on for response path
> -* set MM_CANE_ICG_CTRL.SOFT_OVERRIDE_ATRET = 1 */
> +* set MM_CANE_ICG_CTRL.SOFT_OVERRIDE_ATRET = 1
> +*/
> reg_value = RREG32_SOC15(MMHUB, mmhub_inst, regMM_CANE_ICG_CTRL);
> reg_value = REG_SET_FIELD(reg_value, MM_CANE_ICG_CTRL,
> SOFT_OVERRIDE_ATRET, 1);
> --
> 2.25.1
>
Re: [PATCH] drm/amdgpu: Fix uninitalized variable in jpeg_v4_0_3_is_idle & jpeg_v4_0_3_wait_for_idle
On Fri, May 19, 2023 at 1:06 AM Srinivasan Shanmugam
wrote:
>
> drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c:752:4: error: variable 'ret' is
> uninitialized when used here [-Werror,-Wuninitialized]
> ret &= ((RREG32_SOC15_OFFSET(
> ^~~
> drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c:745:10: note: initialize the
> variable 'ret' to silence this warning
> bool ret;
> ^
> = 0
> drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c:774:4: error: variable 'ret' is
> uninitialized when used here [-Werror,-Wuninitialized]
> ret &= SOC15_WAIT_ON_RREG_OFFSET(
> ^~~
> drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c:767:9: note: initialize the variable
> 'ret' to silence this warning
> int ret;
>^
> = 0
> 2 errors generated.
>
> Cc: Luben Tuikov
> Cc: Alex Deucher
> Cc: Christian König
> Cc: James Zhu
> Cc: Leo Liu
> Signed-off-by: Srinivasan Shanmugam
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
> b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
> index ede15a3a4701..ce2b22f7e4e4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
> @@ -742,7 +742,7 @@ static void jpeg_v4_0_3_dec_ring_nop(struct amdgpu_ring
> *ring, uint32_t count)
> static bool jpeg_v4_0_3_is_idle(void *handle)
> {
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> - bool ret;
> + bool ret = false;
> int i, j;
>
> for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
> @@ -764,7 +764,7 @@ static bool jpeg_v4_0_3_is_idle(void *handle)
> static int jpeg_v4_0_3_wait_for_idle(void *handle)
> {
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> - int ret;
> + int ret = 0;
> int i, j;
>
> for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
> --
> 2.25.1
>
Re: [PATCH] drm/amdgpu: Fix uninitalized variable in kgd2kfd_device_init
Reviewed-by: Alex Deucher
On Fri, May 19, 2023 at 1:17 AM Srinivasan Shanmugam
wrote:
>
> drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device.c:613:4: error: variable
> 'num_xcd' is uninitialized when used here [-Werror,-Wuninitialized]
> num_xcd, kfd->adev->gfx.num_xcc_per_xcp);
> ^~~
> include/linux/dev_printk.h:144:65: note: expanded from macro 'dev_err'
> dev_printk_index_wrap(_dev_err, KERN_ERR, dev, dev_fmt(fmt),
> ##__VA_ARGS__)
>
> ^~~
> include/linux/dev_printk.h:110:23: note: expanded from macro
> 'dev_printk_index_wrap'
> _p_func(dev, fmt, ##__VA_ARGS__); \
> ^~~
> drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device.c:597:13: note: initialize
> the variable 'num_xcd' to silence this warning
> int num_xcd, partition_mode;
>^
> = 0
> 1 error generated.
>
> Cc: Luben Tuikov
> Cc: Alex Deucher
> Cc: Christian König
> Cc: Felix Kuehling
> Cc: Mukul Joshi
> Signed-off-by: Srinivasan Shanmugam
> ---
> drivers/gpu/drm/amd/amdkfd/kfd_device.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
> b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
> index 986543a000bf..e92b93b2c14c 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
> @@ -594,7 +594,7 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd,
> struct kfd_node *node;
> uint32_t first_vmid_kfd, last_vmid_kfd, vmid_num_kfd;
> unsigned int max_proc_per_quantum;
> - int num_xcd, partition_mode;
> + int partition_mode;
> int xcp_idx;
>
> kfd->mec_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev,
> @@ -609,8 +609,8 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd,
>
> if (kfd->num_nodes == 0) {
> dev_err(kfd_device,
> - "KFD num nodes cannot be 0, GC inst: %d,
> num_xcc_in_node: %d\n",
> - num_xcd, kfd->adev->gfx.num_xcc_per_xcp);
> + "KFD num nodes cannot be 0, num_xcc_in_node: %d\n",
> + kfd->adev->gfx.num_xcc_per_xcp);
> goto out;
> }
>
> --
> 2.25.1
>
Re: [PATCH] drm/amdgpu: stop including swiotlb.h
Applied. Thanks! On Thu, May 18, 2023 at 9:52 AM Christoph Hellwig wrote: > > amdgpu does not need swiotlb.h, so stop including it. > > Signed-off-by: Christoph Hellwig > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c > index 2cd081cbf70621..385e04612e4e9b 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c > @@ -38,7 +38,6 @@ > #include > #include > #include > -#include > #include > #include > #include > -- > 2.39.2 >
Re: [PATCH] drm/radeon: stop including swiotlb.h
Applied. Thanks! On Thu, May 18, 2023 at 9:52 AM Christoph Hellwig wrote: > > radeon does not need swiotlb.h, so stop including it. > > Signed-off-by: Christoph Hellwig > --- > drivers/gpu/drm/radeon/radeon_ttm.c | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c > b/drivers/gpu/drm/radeon/radeon_ttm.c > index 2220cdf6a3f680..04df08356d553f 100644 > --- a/drivers/gpu/drm/radeon/radeon_ttm.c > +++ b/drivers/gpu/drm/radeon/radeon_ttm.c > @@ -36,7 +36,6 @@ > #include > #include > #include > -#include > > #include > #include > -- > 2.39.2 >
Re: [PATCH] drm/radeon: fix possible division-by-zero errors
In practice this should never happen. Applied with some minor coding
style fixes.
Alex
On Fri, May 19, 2023 at 11:33 AM Nikita Zhandarovich
wrote:
>
> Function rv740_get_decoded_reference_divider() may return 0 due to
> unpredictable reference divider value calculated in
> radeon_atom_get_clock_dividers(). This will lead to
> division-by-zero error once that value is used as a divider
> in calculating 'clk_s'.
> While unlikely, this issue should nonetheless be prevented so add a
> sanity check for such cases by testing 'decoded_ref' value against 0.
>
> Found by Linux Verification Center (linuxtesting.org) with static
> analysis tool SVACE.
>
> Fixes: 66229b200598 ("drm/radeon/kms: add dpm support for rv7xx (v4)")
> Signed-off-by: Nikita Zhandarovich
>
> ---
> drivers/gpu/drm/radeon/cypress_dpm.c | 7 +--
> drivers/gpu/drm/radeon/ni_dpm.c | 7 +--
> drivers/gpu/drm/radeon/rv740_dpm.c | 7 +--
> 3 files changed, 15 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/cypress_dpm.c
> b/drivers/gpu/drm/radeon/cypress_dpm.c
> index fdddbbaecbb7..3678b7e384e1 100644
> --- a/drivers/gpu/drm/radeon/cypress_dpm.c
> +++ b/drivers/gpu/drm/radeon/cypress_dpm.c
> @@ -555,10 +555,13 @@ static int cypress_populate_mclk_value(struct
> radeon_device *rdev,
>
> if (radeon_atombios_get_asic_ss_info(rdev, &ss,
> ASIC_INTERNAL_MEMORY_SS,
> vco_freq)) {
> + u32 clk_s, clk_v;
> u32 reference_clock = rdev->clock.mpll.reference_freq;
> u32 decoded_ref =
> rv740_get_decoded_reference_divider(dividers.ref_div);
> - u32 clk_s = reference_clock * 5 / (decoded_ref *
> ss.rate);
> - u32 clk_v = ss.percentage *
> + if (!decoded_ref)
> + return -EINVAL;
> + clk_s = reference_clock * 5 / (decoded_ref * ss.rate);
> + clk_v = ss.percentage *
> (0x4000 * dividers.whole_fb_div + 0x800 *
> dividers.frac_fb_div) / (clk_s * 625);
>
> mpll_ss1 &= ~CLKV_MASK;
> diff --git a/drivers/gpu/drm/radeon/ni_dpm.c b/drivers/gpu/drm/radeon/ni_dpm.c
> index 672d2239293e..9ce3e5635efc 100644
> --- a/drivers/gpu/drm/radeon/ni_dpm.c
> +++ b/drivers/gpu/drm/radeon/ni_dpm.c
> @@ -2239,10 +2239,13 @@ static int ni_populate_mclk_value(struct
> radeon_device *rdev,
>
> if (radeon_atombios_get_asic_ss_info(rdev, &ss,
> ASIC_INTERNAL_MEMORY_SS,
> vco_freq)) {
> + u32 clk_s, clk_v;
> u32 reference_clock = rdev->clock.mpll.reference_freq;
> u32 decoded_ref =
> rv740_get_decoded_reference_divider(dividers.ref_div);
> - u32 clk_s = reference_clock * 5 / (decoded_ref *
> ss.rate);
> - u32 clk_v = ss.percentage *
> + if (!decoded_ref)
> + return -EINVAL;
> + clk_s = reference_clock * 5 / (decoded_ref * ss.rate);
> + clk_v = ss.percentage *
> (0x4000 * dividers.whole_fb_div + 0x800 *
> dividers.frac_fb_div) / (clk_s * 625);
>
> mpll_ss1 &= ~CLKV_MASK;
> diff --git a/drivers/gpu/drm/radeon/rv740_dpm.c
> b/drivers/gpu/drm/radeon/rv740_dpm.c
> index d57a3e1df8d6..ca76efa0f59d 100644
> --- a/drivers/gpu/drm/radeon/rv740_dpm.c
> +++ b/drivers/gpu/drm/radeon/rv740_dpm.c
> @@ -247,10 +247,13 @@ int rv740_populate_mclk_value(struct radeon_device
> *rdev,
>
> if (radeon_atombios_get_asic_ss_info(rdev, &ss,
> ASIC_INTERNAL_MEMORY_SS,
> vco_freq)) {
> + u32 clk_s, clk_v;
> u32 reference_clock = rdev->clock.mpll.reference_freq;
> u32 decoded_ref =
> rv740_get_decoded_reference_divider(dividers.ref_div);
> - u32 clk_s = reference_clock * 5 / (decoded_ref *
> ss.rate);
> - u32 clk_v = 0x4 * ss.percentage *
> + if (!decoded_ref)
> + return -EINVAL;
> + clk_s = reference_clock * 5 / (decoded_ref * ss.rate);
> + clk_v = 0x4 * ss.percentage *
> (dividers.whole_fb_div +
> (dividers.frac_fb_div / 8)) / (clk_s * 1);
>
> mpll_ss1 &= ~CLKV_MASK;
> --
> 2.25.1
>
Re: [PATCH v4] drm/amd: Flush any delayed gfxoff on suspend entry
[AMD Official Use Only - General]
GFX PG is a pre-requisite for gfxoff IIRC. We shouldn't disable it on s2idle I
think.
Alex
From: amd-gfx on behalf of Mario
Limonciello
Sent: Friday, May 19, 2023 12:24 AM
To: Quan, Evan ; amd-gfx@lists.freedesktop.org
Cc: Tsao, Anson ; Martinez, Juan ;
Gong, Richard ; Huang, Tim
Subject: Re: [PATCH v4] drm/amd: Flush any delayed gfxoff on suspend entry
Yeah; that seems like a reasonable way to accomplish the same result.
I'll experiment with this.
On 5/18/23 22:33, Quan, Evan wrote:
> [AMD Official Use Only - General]
>
> If I understand correctly, similar job is already performed in
> "amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);"
> Maybe you just need to undo the "skip PG for GFX on S0ix"?
>
> /* skip PG for GFX, SDMA on S0ix */
> if (adev->in_s0ix &&
> (adev->ip_blocks[i].version->type ==
> AMD_IP_BLOCK_TYPE_GFX ||
> adev->ip_blocks[i].version->type ==
> AMD_IP_BLOCK_TYPE_SDMA))
> continue;
>
> Evan
>> -Original Message-
>> From: amd-gfx On Behalf Of Mario
>> Limonciello
>> Sent: Friday, May 19, 2023 12:53 AM
>> To: amd-gfx@lists.freedesktop.org
>> Cc: Tsao, Anson ; Huang, Tim
>> ; Martinez, Juan ;
>> Limonciello, Mario ; Gong, Richard
>>
>> Subject: [PATCH v4] drm/amd: Flush any delayed gfxoff on suspend entry
>>
>> DCN 3.1.4 is reported to hang on s2idle entry if graphics activity
>> is happening during entry. This is because GFXOFF was scheduled as
>> delayed but RLC gets disabled in s2idle entry sequence which will
>> hang GFX IP if not already in GFXOFF.
>>
>> To help this problem, flush any delayed work for GFXOFF early in
>> s2idle entry sequence to ensure that it's off when RLC is changed.
>>
>> commit 3964b0c2e843 ("drm/amdgpu: complete gfxoff allow signal during
>> suspend without delay") modified power gating flow so that if called
>> in s0ix that it ensured that GFXOFF wasn't put in work queue but
>> instead processed immediately.
>>
>> This is dead code due to commit 5d70a549d00d ("drm/amdgpu: skip
>> CG/PG for gfx during S0ix") because GFXOFF will now not be explicitly
>> called as part of the suspend entry code. Remove that dead code.
>>
>> Cc: sta...@vger.kernel.org # 6.1+
>> Suggested-by: Tim Huang
>> Signed-off-by: Mario Limonciello
>> ---
>> v3->v4:
>> * Drop patches 2-4
>> ---
>> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 +
>> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c| 9 +
>> 2 files changed, 2 insertions(+), 8 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> index a9d9bbe8586b..059139f1f973 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> @@ -4316,6 +4316,7 @@ int amdgpu_device_suspend(struct drm_device
>> *dev, bool fbcon)
>>drm_fb_helper_set_suspend_unlocked(adev_to_drm(adev)-
>>> fb_helper, true);
>>
>>cancel_delayed_work_sync(&adev->delayed_init_work);
>> + flush_delayed_work(&adev->gfx.gfx_off_delay_work);
>>
>>amdgpu_ras_suspend(adev);
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
>> index f2d0b1d55d77..b1190eb0e9c7 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
>> @@ -692,15 +692,8 @@ void amdgpu_gfx_off_ctrl(struct amdgpu_device
>> *adev, bool enable)
>>
>>if (adev->gfx.gfx_off_req_count == 0 &&
>>!adev->gfx.gfx_off_state) {
>> - /* If going to s2idle, no need to wait */
>> - if (adev->in_s0ix) {
>> - if
>> (!amdgpu_dpm_set_powergating_by_smu(adev,
>> - AMD_IP_BLOCK_TYPE_GFX,
>> true))
>> - adev->gfx.gfx_off_state = true;
>> - } else {
>> - schedule_delayed_work(&adev-
>>> gfx.gfx_off_delay_work,
>> + schedule_delayed_work(&adev-
>>> gfx.gfx_off_delay_work,
>> delay);
>> - }
>>}
>>} else {
>>if (adev->gfx.gfx_off_req_count == 0) {
>> --
>> 2.34.1
>
Re: [PATCH] drm/amd/pm: Fix output of pp_od_clk_voltage
On Mon, Nov 14, 2022 at 8:57 PM Jonatas Esteves wrote:
>
> Printing the other clock types should not be conditioned on being able
> to print OD_SCLK. Some GPUs currently have limited capability of only
> printing a subset of these.
>
> Since this condition was introduced in v5.18-rc1, reading from
> `pp_od_clk_voltage` has been returning empty on the Asus ROG Strix G15
> (2021).
>
> Fixes: 79c65f3fcbb1 ("drm/amd/pm: do not expose power implementation details
> to amdgpu_pm.c")
Can you provide your signed-off-by? Once I get that I can apply the
patch. Thanks.
Thanks,
Alex
> ---
> drivers/gpu/drm/amd/pm/amdgpu_pm.c | 12 +---
> 1 file changed, 5 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> index 236657eece47..9d364bbc78e1 100644
> --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> @@ -869,13 +869,11 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct
> device *dev,
> }
> if (ret == -ENOENT) {
> size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
> - if (size > 0) {
> - size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK,
> buf + size);
> - size += amdgpu_dpm_print_clock_levels(adev,
> OD_VDDC_CURVE, buf + size);
> - size += amdgpu_dpm_print_clock_levels(adev,
> OD_VDDGFX_OFFSET, buf + size);
> - size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE,
> buf + size);
> - size += amdgpu_dpm_print_clock_levels(adev, OD_CCLK,
> buf + size);
> - }
> + size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf +
> size);
> + size += amdgpu_dpm_print_clock_levels(adev, OD_VDDC_CURVE,
> buf + size);
> + size += amdgpu_dpm_print_clock_levels(adev, OD_VDDGFX_OFFSET,
> buf + size);
> + size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf +
> size);
> + size += amdgpu_dpm_print_clock_levels(adev, OD_CCLK, buf +
> size);
> }
>
> if (size == 0)
> --
> 2.30.2
>
Re: [PATCH] drm/amdkfd: Align partition memory size to page size
On 2023-05-19 10:19, Philip Yang wrote:
The compute partition memory size calculated from KFD_XCP_MEMORY_SIZE
may not align to page size if xcp_mgr->num_xcp_per_mem_partition is 6.
Change the KFD_XCP_MEMORY_SIZE macro to return page align size, so KFD
node memory size reported in sysfs is page align size, to avoid
application VRAM allocation failure because application may use the size
directly and Thunk requires the memory allocation size is page size
align.
Signed-off-by: Philip Yang
Reviewed-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index 5de92c9ab18f..66f80b9ab0c5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -804,7 +804,7 @@ u64 amdgpu_amdkfd_xcp_memory_size(struct amdgpu_device
*adev, int xcp_id)
if (adev->gmc.num_mem_partitions && xcp_id >= 0 && mem_id >= 0) {
tmp = adev->gmc.mem_partitions[mem_id].size;
do_div(tmp, adev->xcp_mgr->num_xcp_per_mem_partition);
- return tmp;
+ return ALIGN_DOWN(tmp, PAGE_SIZE);
} else {
return adev->gmc.real_vram_size;
}
Re: [PATCH v2] drm/amdgpu: Fix the EPERM error when get user pages
On 2023-05-19 08:02, Ma Jun wrote:
Check and pass the readonly flags when set amdgpu_ttm_tt flags
for readonly ptr pages. Otherwise, there is EPERM error returned
during the KFDExceptionTest.PermissionFaultUserPointer test on
ploaris10.
I remember you asked me about this maybe 2 weeks ago. I'm still not sure
how your test is supposed to work correctly. Someone needs to decide
whether to set KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE when registering the
userptr. How does this happen? I think you need some code that checks
that the VMA is read-only and then clears the WRITABLE flag from
mem->alloc_flags. But I don't see that anywhere. I don't think we ever
added proper support for read-only userptrs in KFD. Your patch is a
partial fix at best, and I don't see how this helps.
Two more nit-picks inline.
Signed-off-by: Ma Jun
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index d426333e865a..85d1087439c0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -1036,10 +1036,17 @@ static int init_user_pages(struct kgd_mem *mem,
uint64_t user_addr,
struct ttm_operation_ctx ctx = { true, false };
struct hmm_range *range;
int ret = 0;
+ uint32_t tt_flags = 0;
mutex_lock(&process_info->lock);
- ret = amdgpu_ttm_tt_set_userptr(&bo->tbo, user_addr, 0);
+ if (!(mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE))
+ tt_flags |= AMDGPU_GEM_USERPTR_READONLY;
+ else
+ tt_flags = 0;
This else-branch is unnecessary because you initialized tt_flags to 0 above.
+
+
Double blank lines. One is enough.
Regards,
Felix
+ ret = amdgpu_ttm_tt_set_userptr(&bo->tbo, user_addr, tt_flags);
if (ret) {
pr_err("%s: Failed to set userptr: %d\n", __func__, ret);
goto out;
Re: [PATCH v4 01/10] drm/amdgpu: UAPI for user queue management
On Mon, Apr 24, 2023 at 1:39 PM Shashank Sharma wrote:
>
> From: Alex Deucher
>
> This patch intorduces new UAPI/IOCTL for usermode graphics
> queue. The userspace app will fill this structure and request
> the graphics driver to add a graphics work queue for it. The
> output of this UAPI is a queue id.
>
> This UAPI maps the queue into GPU, so the graphics app can start
> submitting work to the queue as soon as the call returns.
>
> V2: Addressed review comments from Alex and Christian
> - Make the doorbell offset's comment clearer
> - Change the output parameter name to queue_id
>
> V3: Integration with doorbell manager
>
> V4:
> - Updated the UAPI doc (Pierre-Eric)
> - Created a Union for engine specific MQDs (Alex)
> - Added Christian's R-B
>
> Cc: Alex Deucher
> Cc: Christian Koenig
> Reviewed-by: Christian König
> Signed-off-by: Alex Deucher
> Signed-off-by: Shashank Sharma
> ---
> include/uapi/drm/amdgpu_drm.h | 95 +++
> 1 file changed, 95 insertions(+)
>
> diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
> index 4038abe8505a..083a1df8e8ef 100644
> --- a/include/uapi/drm/amdgpu_drm.h
> +++ b/include/uapi/drm/amdgpu_drm.h
> @@ -54,6 +54,7 @@ extern "C" {
> #define DRM_AMDGPU_VM 0x13
> #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14
> #define DRM_AMDGPU_SCHED 0x15
> +#define DRM_AMDGPU_USERQ 0x16
>
> #define DRM_IOCTL_AMDGPU_GEM_CREATEDRM_IOWR(DRM_COMMAND_BASE +
> DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
> #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE +
> DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
> @@ -71,6 +72,7 @@ extern "C" {
> #define DRM_IOCTL_AMDGPU_VMDRM_IOWR(DRM_COMMAND_BASE +
> DRM_AMDGPU_VM, union drm_amdgpu_vm)
> #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE +
> DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle)
> #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE +
> DRM_AMDGPU_SCHED, union drm_amdgpu_sched)
> +#define DRM_IOCTL_AMDGPU_USERQ DRM_IOW(DRM_COMMAND_BASE +
> DRM_AMDGPU_USERQ, union drm_amdgpu_userq)
>
> /**
> * DOC: memory domains
> @@ -302,6 +304,99 @@ union drm_amdgpu_ctx {
> union drm_amdgpu_ctx_out out;
> };
>
> +/* user queue IOCTL */
> +#define AMDGPU_USERQ_OP_CREATE 1
> +#define AMDGPU_USERQ_OP_FREE 2
> +
> +#define AMDGPU_USERQ_MQD_FLAGS_SECURE (1 << 0)
> +#define AMDGPU_USERQ_MQD_FLAGS_AQL (1 << 1)
> +
> +/*
> + * MQD (memory queue descriptor) is a set of parameters which allow
> + * the GPU to uniquely define and identify a usermode queue.
> + */
> +struct drm_amdgpu_userq_mqd_gfx {
> + /**
> +* @flags: flags to indicate special function for queue like secure
> +* buffer (TMZ). Unused for now.
> +*/
> + __u32 flags;
> + /**
> +* @doorbell_handle: the handle of doorbell GEM object
> +* associated to this client.
> +*/
> + __u32 doorbell_handle;
> + /**
> +* @doorbell_offset: 32-bit offset of the doorbell in the doorbell bo.
> +* Kernel will generate absolute doorbell offset using doorbell_handle
> +* and doorbell_offset in the doorbell bo.
> +*/
> + __u32 doorbell_offset;
> + /**
> +* @queue_va: Virtual address of the GPU memory which holds the queue
> +* object. The queue holds the workload packets.
> +*/
> + __u64 queue_va;
> + /**
> +* @queue_size: Size of the queue in bytes, this needs to be 256-byte
> +* aligned.
> +*/
> + __u64 queue_size;
> + /**
> +* @rptr_va : Virtual address of the GPU memory which holds the ring
> RPTR.
> +* This object must be at least 8 byte in size and aligned to 8-byte
> offset.
> +*/
> + __u64 rptr_va;
> + /**
> +* @wptr_va : Virtual address of the GPU memory which holds the ring
> WPTR.
> +* This object must be at least 8 byte in size and aligned to 8-byte
> offset.
> +*
> +* Queue, RPTR and WPTR can come from the same object, as long as the
> size
> +* and alignment related requirements are met.
> +*/
> + __u64 wptr_va;
> + /**
> +* @shadow_va: Virtual address of the GPU memory to hold the shadow
> buffer.
> +* This must be a from a separate GPU object, and must be at least
> 4-page
> +* sized.
> +*/
> + __u64 shadow_va;
You were planning to add the other pointers here as well for gds and csa right?
> +};
> +
> + /*
> + * MQD can be different for different GPU IP/engine. This union will
> + * contain structures of MQDs corresponding to different engines.
> + */
> +union drm_amdgpu_userq_mqd {
> + struct drm_amdgpu_userq_mqd_gfx gfx;
> +};
> +
> +struct drm_amdgpu_userq_in {
> + /** AMDGPU_USERQ_OP_* */
> +
Re: [PATCH v4 04/10] drm/amdgpu: create GFX-gen11 MQD for userqueue
On Mon, Apr 24, 2023 at 1:39 PM Shashank Sharma wrote:
>
> A Memory queue descriptor (MQD) of a userqueue defines it in
> the hw's context. As MQD format can vary between different
> graphics IPs, we need gfx GEN specific handlers to create MQDs.
>
> This patch:
> - Introduces MQD handler functions for the usermode queues.
> - Adds new functions to create and destroy userqueue MQD for
> GFX-GEN-11 IP
>
> V1: Worked on review comments from Alex:
> - Make MQD functions GEN and IP specific
>
> V2: Worked on review comments from Alex:
> - Reuse the existing adev->mqd[ip] for MQD creation
> - Formatting and arrangement of code
>
> V3:
> - Integration with doorbell manager
>
> V4: Review comments addressed:
> - Do not create a new file for userq, reuse gfx_v11_0.c (Alex)
> - Align name of structure members (Luben)
> - Don't break up the Cc tag list and the Sob tag list in commit
> message (Luben)
>
> Cc: Alex Deucher
> Cc: Christian Koenig
> Signed-off-by: Shashank Sharma
> Signed-off-by: Arvind Yadav
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c | 25
> drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c| 57 +++
> .../gpu/drm/amd/include/amdgpu_userqueue.h| 7 +++
> 3 files changed, 89 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c
> index 333f31efbe7b..e95fb35b0cb5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c
> @@ -81,6 +81,14 @@ static int amdgpu_userqueue_create_gfx(struct drm_file
> *filp, union drm_amdgpu_u
> goto free_queue;
> }
>
> + if (uq_mgr->userq_funcs[queue->queue_type]->mqd_create) {
> + r =
> uq_mgr->userq_funcs[queue->queue_type]->mqd_create(uq_mgr, queue);
> + if (r) {
> + DRM_ERROR("Failed to create/map userqueue MQD\n");
> + goto free_queue;
> + }
> + }
> +
> args->out.queue_id = queue->queue_id;
> args->out.flags = 0;
> mutex_unlock(&uq_mgr->userq_mutex);
> @@ -119,6 +127,8 @@ static void amdgpu_userqueue_destroy(struct drm_file
> *filp, int queue_id)
> }
>
> mutex_lock(&uq_mgr->userq_mutex);
> + if (uq_mgr->userq_funcs[queue->queue_type]->mqd_destroy)
> + uq_mgr->userq_funcs[queue->queue_type]->mqd_destroy(uq_mgr,
> queue);
> amdgpu_userqueue_free_index(uq_mgr, queue->queue_id);
> mutex_unlock(&uq_mgr->userq_mutex);
> kfree(queue);
> @@ -149,6 +159,20 @@ int amdgpu_userq_ioctl(struct drm_device *dev, void
> *data,
> return r;
> }
>
> +extern const struct amdgpu_userq_funcs userq_gfx_v11_funcs;
> +
> +static void
> +amdgpu_userqueue_setup_ip_funcs(struct amdgpu_userq_mgr *uq_mgr)
> +{
> + int maj;
> + struct amdgpu_device *adev = uq_mgr->adev;
> + uint32_t version = adev->ip_versions[GC_HWIP][0];
> +
> + /* We support usermode queue only for GFX IP as of now */
> + maj = IP_VERSION_MAJ(version);
> + if (maj == 11)
> + uq_mgr->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_gfx_v11_funcs;
Do we need to keep function pointers in uq_mgr? It would be nice to
keep the logic in the IPs directly. E.g, in gfx_v11_0.c, we could set
adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_gfx_v11_funcs;
then the userq code can just check
if (adev->userq_funcs[queue->queue_type]->mqd_destroy)
adev->userq_funcs[queue->queue_type]->mqd_destroy(adev, queue);
etc.
> +}
>
> int amdgpu_userq_mgr_init(struct amdgpu_userq_mgr *userq_mgr, struct
> amdgpu_device *adev)
> {
> @@ -156,6 +180,7 @@ int amdgpu_userq_mgr_init(struct amdgpu_userq_mgr
> *userq_mgr, struct amdgpu_devi
> idr_init_base(&userq_mgr->userq_idr, 1);
> userq_mgr->adev = adev;
>
> + amdgpu_userqueue_setup_ip_funcs(userq_mgr);
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> index a56c6e106d00..9f7b14966ac8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> @@ -30,6 +30,7 @@
> #include "amdgpu_psp.h"
> #include "amdgpu_smu.h"
> #include "amdgpu_atomfirmware.h"
> +#include "amdgpu_userqueue.h"
> #include "imu_v11_0.h"
> #include "soc21.h"
> #include "nvd.h"
> @@ -6404,3 +6405,59 @@ const struct amdgpu_ip_block_version
> gfx_v11_0_ip_block =
> .rev = 0,
> .funcs = &gfx_v11_0_ip_funcs,
> };
> +
> +static int
> +gfx_v11_userq_mqd_create(struct amdgpu_userq_mgr *uq_mgr, struct
> amdgpu_usermode_queue *queue)
> +{
> + struct amdgpu_device *adev = uq_mgr->adev;
> + struct amdgpu_userq_ctx_space *mqd = &queue->mqd;
> + struct amdgpu_mqd *gfx_v11_mqd = &adev->mqds[queue->queue_type];
> + int size = gfx_v11_mqd->mqd_size;
> + int r;
> +
> + r = amdg
Re: [PATCH v4 05/10] drm/amdgpu: create context space for usermode queue
On Mon, Apr 24, 2023 at 1:39 PM Shashank Sharma wrote:
>
> The FW expects us to allocate at least one page as context
> space to process gang, process, GDS and FW related work.
> This patch creates a joint object for the same, and calculates
> GPU space offsets for each of these spaces.
>
> V1: Addressed review comments on RFC patch:
> Alex: Make this function IP specific
>
> V2: Addressed review comments from Christian
> - Allocate only one object for total FW space, and calculate
> offsets for each of these objects.
>
> V3: Integration with doorbell manager
> V4: Review comments:
> - Remove shadow from FW space list from cover letter (Alex)
> - Alignment of macro (Luben)
>
> Cc: Alex Deucher
> Cc: Christian Koenig
> Signed-off-by: Shashank Sharma
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c| 57 ++-
> .../gpu/drm/amd/include/amdgpu_userqueue.h| 6 ++
> 2 files changed, 61 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> index 9f7b14966ac8..f6b33faea86f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> @@ -53,6 +53,11 @@
> #define GFX11_NUM_GFX_RINGS1
> #define GFX11_MEC_HPD_SIZE 2048
>
> +#define AMDGPU_USERQ_PROC_CTX_SZ PAGE_SIZE
> +#define AMDGPU_USERQ_GANG_CTX_SZ PAGE_SIZE
> +#define AMDGPU_USERQ_FW_CTX_SZ PAGE_SIZE
> +#define AMDGPU_USERQ_GDS_CTX_SZPAGE_SIZE
> +
> #define RLCG_UCODE_LOADING_START_ADDRESS 0x2000L
> #define RLC_PG_DELAY_3_DEFAULT_GC_11_0_1 0x1388
>
> @@ -6406,6 +6411,44 @@ const struct amdgpu_ip_block_version
> gfx_v11_0_ip_block =
> .funcs = &gfx_v11_0_ip_funcs,
> };
>
> +static int gfx_v11_userq_create_ctx_space(struct amdgpu_userq_mgr *uq_mgr,
> + struct amdgpu_usermode_queue *queue)
> +{
> + struct amdgpu_device *adev = uq_mgr->adev;
> + struct amdgpu_userq_ctx_space *ctx = &queue->fw_space;
> + int r, size;
> +
> + /*
> +* The FW expects at least one page space allocated for
> +* process ctx, gang ctx, gds ctx, fw ctx each.
> +*/
> + size = AMDGPU_USERQ_PROC_CTX_SZ + AMDGPU_USERQ_FW_CTX_SZ +
> + AMDGPU_USERQ_GANG_CTX_SZ + AMDGPU_USERQ_GDS_CTX_SZ;
> + r = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE,
> + AMDGPU_GEM_DOMAIN_GTT,
> + &ctx->obj,
> + &ctx->gpu_addr,
> + &ctx->cpu_ptr);
> + if (r) {
> + DRM_ERROR("Failed to allocate ctx space bo for userqueue,
> err:%d\n", r);
> + return r;
> + }
> +
> + queue->proc_ctx_gpu_addr = ctx->gpu_addr;
> + queue->gang_ctx_gpu_addr = queue->proc_ctx_gpu_addr +
> AMDGPU_USERQ_PROC_CTX_SZ;
> + queue->fw_ctx_gpu_addr = queue->gang_ctx_gpu_addr +
> AMDGPU_USERQ_GANG_CTX_SZ;
> + queue->gds_ctx_gpu_addr = queue->fw_ctx_gpu_addr +
> AMDGPU_USERQ_FW_CTX_SZ;
> + return 0;
> +}
Please use gfx_v11_0_ naming for consistency.
Alex
> +
> +static void gfx_v11_userq_destroy_ctx_space(struct amdgpu_userq_mgr *uq_mgr,
> + struct amdgpu_usermode_queue
> *queue)
> +{
> + struct amdgpu_userq_ctx_space *ctx = &queue->fw_space;
> +
> + amdgpu_bo_free_kernel(&ctx->obj, &ctx->gpu_addr, &ctx->cpu_ptr);
> +}
> +
> static int
> gfx_v11_userq_mqd_create(struct amdgpu_userq_mgr *uq_mgr, struct
> amdgpu_usermode_queue *queue)
> {
> @@ -6426,10 +6469,16 @@ gfx_v11_userq_mqd_create(struct amdgpu_userq_mgr
> *uq_mgr, struct amdgpu_usermode
> }
>
> memset(mqd->cpu_ptr, 0, size);
> + r = gfx_v11_userq_create_ctx_space(uq_mgr, queue);
> + if (r) {
> + DRM_ERROR("Failed to create CTX space for userqueue (%d)\n",
> r);
> + goto free_mqd;
> + }
> +
> r = amdgpu_bo_reserve(mqd->obj, false);
> if (unlikely(r != 0)) {
> DRM_ERROR("Failed to reserve mqd for userqueue (%d)", r);
> - goto free_mqd;
> + goto free_ctx;
> }
>
> queue->userq_prop.use_doorbell = true;
> @@ -6438,12 +6487,15 @@ gfx_v11_userq_mqd_create(struct amdgpu_userq_mgr
> *uq_mgr, struct amdgpu_usermode
> amdgpu_bo_unreserve(mqd->obj);
> if (r) {
> DRM_ERROR("Failed to init MQD for queue\n");
> - goto free_mqd;
> + goto free_ctx;
> }
>
> DRM_DEBUG_DRIVER("MQD for queue %d created\n", queue->queue_id);
> return 0;
>
> +free_ctx:
> + gfx_v11_userq_destroy_ctx_space(uq_mgr, queue);
> +
> free_mqd:
> amdgpu_bo_free_kernel(&mqd->obj, &mqd->gpu_addr, &mqd->cpu_ptr);
> return r;
> @@ -6454,6 +6506,7 @@ gfx_v11_userq_mqd_destroy(struct amdgpu_userq_mgr
> *uq_mg
Re: [PATCH v4 06/10] drm/amdgpu: set FW parameters in v11_struct
On Mon, Apr 24, 2023 at 1:39 PM Shashank Sharma wrote:
>
> From: Arvind Yadav
>
> This patch sets new parameters defined in v11_struct for
> usermode queue with the respective allocated gpu context
> space addresses.
>
> V4: Split the patch into two parts, keep only the set parameter
> part in this series (Alex).
>
> Cc: Alex Deucher
> Cc: Christian Koenig
> Cc: Shashank Sharma
> Signed-off-by: Arvind Yadav
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 19 ++-
> 1 file changed, 18 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> index f6b33faea86f..86de35292f69 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> @@ -6411,6 +6411,21 @@ const struct amdgpu_ip_block_version
> gfx_v11_0_ip_block =
> .funcs = &gfx_v11_0_ip_funcs,
> };
>
> +static void gfx_v11_userq_set_ctx_space(struct amdgpu_userq_mgr *uq_mgr,
gfx_v11_0_ for consistency.
Alex
> + struct amdgpu_usermode_queue *queue)
> +{
> + struct v11_gfx_mqd *mqd = queue->mqd.cpu_ptr;
> +
> + mqd->shadow_base_lo = queue->shadow_ctx_gpu_addr & 0xfffc;
> + mqd->shadow_base_hi = upper_32_bits(queue->shadow_ctx_gpu_addr);
> +
> + mqd->gds_bkup_base_lo = queue->gds_ctx_gpu_addr & 0xfffc;
> + mqd->gds_bkup_base_hi = upper_32_bits(queue->gds_ctx_gpu_addr);
> +
> + mqd->fw_work_area_base_lo = queue->fw_ctx_gpu_addr & 0xfffc;
> + mqd->fw_work_area_base_lo = upper_32_bits(queue->fw_ctx_gpu_addr);
> +}
> +
> static int gfx_v11_userq_create_ctx_space(struct amdgpu_userq_mgr *uq_mgr,
> struct amdgpu_usermode_queue *queue)
> {
> @@ -6484,12 +6499,14 @@ gfx_v11_userq_mqd_create(struct amdgpu_userq_mgr
> *uq_mgr, struct amdgpu_usermode
> queue->userq_prop.use_doorbell = true;
> queue->userq_prop.mqd_gpu_addr = mqd->gpu_addr;
> r = gfx_v11_mqd->init_mqd(adev, (void *)mqd->cpu_ptr,
> &queue->userq_prop);
> - amdgpu_bo_unreserve(mqd->obj);
> if (r) {
> + amdgpu_bo_unreserve(mqd->obj);
> DRM_ERROR("Failed to init MQD for queue\n");
> goto free_ctx;
> }
>
> + gfx_v11_userq_set_ctx_space(uq_mgr, queue);
> + amdgpu_bo_unreserve(mqd->obj);
> DRM_DEBUG_DRIVER("MQD for queue %d created\n", queue->queue_id);
> return 0;
>
> --
> 2.40.0
>
Re: [PATCH v4 07/10] drm/amdgpu: map usermode queue into MES
On Mon, Apr 24, 2023 at 1:39 PM Shashank Sharma wrote:
>
> This patch adds new functions to map/unmap a usermode queue into
> the FW, using the MES ring. As soon as this mapping is done, the
> queue would be considered ready to accept the workload.
>
> V1: Addressed review comments from Alex on the RFC patch series
> - Map/Unmap should be IP specific.
> V2:
> Addressed review comments from Christian:
> - Fix the wptr_mc_addr calculation (moved into another patch)
> Addressed review comments from Alex:
> - Do not add fptrs for map/unmap
>
> V3: Integration with doorbell manager
> V4: Rebase
>
> Cc: Alex Deucher
> Cc: Christian Koenig
> Signed-off-by: Shashank Sharma
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 67 ++
> 1 file changed, 67 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> index 86de35292f69..7a45d68091ec 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> @@ -31,6 +31,7 @@
> #include "amdgpu_smu.h"
> #include "amdgpu_atomfirmware.h"
> #include "amdgpu_userqueue.h"
> +#include "amdgpu_mes.h"
> #include "imu_v11_0.h"
> #include "soc21.h"
> #include "nvd.h"
> @@ -6411,6 +6412,64 @@ const struct amdgpu_ip_block_version
> gfx_v11_0_ip_block =
> .funcs = &gfx_v11_0_ip_funcs,
> };
>
> +static int gfx_v11_userq_map(struct amdgpu_userq_mgr *uq_mgr,
> +struct amdgpu_usermode_queue *queue)
> +{
> + struct amdgpu_device *adev = uq_mgr->adev;
> + struct mes_add_queue_input queue_input;
> + int r;
> +
> + memset(&queue_input, 0x0, sizeof(struct mes_add_queue_input));
> +
> + queue_input.process_va_start = 0;
> + queue_input.process_va_end = (adev->vm_manager.max_pfn - 1) <<
> AMDGPU_GPU_PAGE_SHIFT;
> + queue_input.process_quantum = 10; /* 10ms */
> + queue_input.gang_quantum = 1; /* 1ms */
> + queue_input.paging = false;
> +
> + queue_input.gang_context_addr = queue->gang_ctx_gpu_addr;
> + queue_input.process_context_addr = queue->proc_ctx_gpu_addr;
> + queue_input.inprocess_gang_priority =
> AMDGPU_MES_PRIORITY_LEVEL_NORMAL;
> + queue_input.gang_global_priority_level =
> AMDGPU_MES_PRIORITY_LEVEL_NORMAL;
> +
> + queue_input.process_id = queue->vm->pasid;
> + queue_input.queue_type = queue->queue_type;
> + queue_input.mqd_addr = queue->mqd.gpu_addr;
> + queue_input.wptr_addr = queue->userq_prop.wptr_gpu_addr;
> + queue_input.queue_size = queue->userq_prop.queue_size >> 2;
> + queue_input.doorbell_offset = queue->userq_prop.doorbell_index;
> + queue_input.page_table_base_addr =
> amdgpu_gmc_pd_addr(queue->vm->root.bo);
> +
> + amdgpu_mes_lock(&adev->mes);
> + r = adev->mes.funcs->add_hw_queue(&adev->mes, &queue_input);
> + amdgpu_mes_unlock(&adev->mes);
> + if (r) {
> + DRM_ERROR("Failed to map queue in HW, err (%d)\n", r);
> + return r;
> + }
> +
> + DRM_DEBUG_DRIVER("Queue %d mapped successfully\n", queue->queue_id);
> + return 0;
> +}
> +
> +static void gfx_v11_userq_unmap(struct amdgpu_userq_mgr *uq_mgr,
> + struct amdgpu_usermode_queue *queue)
> +{
> + struct amdgpu_device *adev = uq_mgr->adev;
> + struct mes_remove_queue_input queue_input;
> + int r;
> +
> + memset(&queue_input, 0x0, sizeof(struct mes_remove_queue_input));
> + queue_input.doorbell_offset = queue->userq_prop.doorbell_index;
> + queue_input.gang_context_addr = queue->gang_ctx_gpu_addr;
> +
> + amdgpu_mes_lock(&adev->mes);
> + r = adev->mes.funcs->remove_hw_queue(&adev->mes, &queue_input);
> + amdgpu_mes_unlock(&adev->mes);
> + if (r)
> + DRM_ERROR("Failed to unmap queue in HW, err (%d)\n", r);
> +}
gfx_v11_0_ for consistency.
Alex
> +
> static void gfx_v11_userq_set_ctx_space(struct amdgpu_userq_mgr *uq_mgr,
> struct amdgpu_usermode_queue *queue)
> {
> @@ -6507,6 +6566,13 @@ gfx_v11_userq_mqd_create(struct amdgpu_userq_mgr
> *uq_mgr, struct amdgpu_usermode
>
> gfx_v11_userq_set_ctx_space(uq_mgr, queue);
> amdgpu_bo_unreserve(mqd->obj);
> +
> + /* Map the queue in HW using MES ring */
> + r = gfx_v11_userq_map(uq_mgr, queue);
> + if (r) {
> + DRM_ERROR("Failed to map userqueue (%d)\n", r);
> + goto free_ctx;
> + }
> DRM_DEBUG_DRIVER("MQD for queue %d created\n", queue->queue_id);
> return 0;
>
> @@ -6523,6 +6589,7 @@ gfx_v11_userq_mqd_destroy(struct amdgpu_userq_mgr
> *uq_mgr, struct amdgpu_usermod
> {
> struct amdgpu_userq_ctx_space *mqd = &queue->mqd;
>
> + gfx_v11_userq_unmap(uq_mgr, queue);
> gfx_v11_userq_destroy_ctx_space(uq_mgr, queue);
> amdgpu_bo_free_kernel(
[QUESTION] gfvhub_v2_1 updates CNTL regs before initialize related page table address
Hi, I'm looking at the initialization sequences in gfxhub_v2_1.c. I'm confused on whether the GCVM_CONTEXT1_CNTL CNTL reg can be written before the corresponding GCVM_CONTEXT1_PAGE_TABLE_START_ADDR and GCVM_CONTEXT1_PAGE_TABLE_END_ADDR reg is written. Here is the background: * gfxhub_v2_1_setup_vmid_config() enables GPU clients to use GPUVM VMIDs to access memory. The code related to this questions is below: 324 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, 325 i * hub->ctx_distance, tmp); 326 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, 327 i * hub->ctx_addr_distance, 0); 328 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, 329 i * hub->ctx_addr_distance, 0); 330 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, 331 i * hub->ctx_addr_distance, 332 lower_32_bits(adev->vm_manager.max_pfn - 1)); 333 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, 334 i * hub->ctx_addr_distance, 335 upper_32_bits(adev->vm_manager.max_pfn - 1)); Just wondering, is the behavior expected or is it a bug? Thanks, Zibin Liu
