[PATCH] drm/amdgpu: Reset CP_VMID_PREEMPT after trailing fence signaled
From: Jiadong Zhu
When MEC executes unmap_queue for mid command buffer preemption, it will
kick the write pointer of the gfx ring, set CP_VMID_PREEMPT to trigger the
preemption and wait for CP_VMID_PREEMPT becomes zero after the preemption
done. There is a race condition that PFP may excute the resetting command
before MEC set CP_VMID_PREEMPT. As a result, hang happens as
CP_VMID_PREEMPT is always 0x.
To avoid this, we send resetting CP_VMID_PREEMPT command after the trailing
fence is siganled and update gfx write pointer explicitly.
Signed-off-by: Jiadong Zhu
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 8bf95a6b0767..cbdd9918b3e7 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -5402,10 +5402,6 @@ static int gfx_v9_0_ring_preempt_ib(struct amdgpu_ring
*ring)
amdgpu_ring_alloc(ring, 13);
gfx_v9_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
ring->trail_seq, AMDGPU_FENCE_FLAG_EXEC |
AMDGPU_FENCE_FLAG_INT);
- /*reset the CP_VMID_PREEMPT after trailing fence*/
- amdgpu_ring_emit_wreg(ring,
- SOC15_REG_OFFSET(GC, 0, mmCP_VMID_PREEMPT),
- 0x0);
/* assert IB preemption, emit the trailing fence */
kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
@@ -5428,6 +5424,10 @@ static int gfx_v9_0_ring_preempt_ib(struct amdgpu_ring
*ring)
DRM_WARN("ring %d timeout to preempt ib\n", ring->idx);
}
+ /*reset the CP_VMID_PREEMPT after trailing fence*/
+ amdgpu_ring_emit_wreg(ring,
+ SOC15_REG_OFFSET(GC, 0, mmCP_VMID_PREEMPT),
+ 0x0);
amdgpu_ring_commit(ring);
/* deassert preemption condition */
--
2.25.1
RE: [PATCH v3] drm/amdgpu: resove reboot exception for si oland
[Public]
This patch did not land at all? Well, please add your SOB in commit message,
and I will push it to amd-staging-drm-next branch with my RB.
Regards,
Guchun
> -Original Message-
> From: Zhenneng Li
> Sent: Wednesday, May 24, 2023 9:10 AM
> To: Chen, Guchun
> Cc: Deucher, Alexander ; Koenig, Christian
> ; Pan, Xinhui ; David
> Airlie ; Daniel Vetter ; amd-
> g...@lists.freedesktop.org; Zhenneng Li
> Subject: [PATCH v3] drm/amdgpu: resove reboot exception for si oland
>
> During reboot test on arm64 platform, it may failure on boot.
>
> The error message are as follows:
> [1.706570][ 3] [ T273] [drm:si_thermal_enable_alert [amdgpu]] *ERROR*
> Could not enable thermal interrupts.
> [1.716547][ 3] [ T273] [drm:amdgpu_device_ip_late_init [amdgpu]]
> *ERROR* late_init of IP block failed -22
> [1.727064][ 3] [ T273] amdgpu :02:00.0: amdgpu_device_ip_late_init
> failed
> [1.734367][ 3] [ T273] amdgpu :02:00.0: Fatal error during GPU init
> ---
> drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 12
> 1 file changed, 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
> b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
> index d6d9e3b1b2c0..ca9bce895dbe 100644
> --- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
> +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
> @@ -7626,18 +7626,6 @@ static int si_dpm_process_interrupt(struct
> amdgpu_device *adev,
>
> static int si_dpm_late_init(void *handle) {
> - int ret;
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> -
> - if (!adev->pm.dpm_enabled)
> - return 0;
> -
> - ret = si_set_temperature_range(adev);
> - if (ret)
> - return ret;
> -#if 0 //TODO ?
> - si_dpm_powergate_uvd(adev, true);
> -#endif
> return 0;
> }
>
> --
> 2.25.1
>
>
> No virus found
> Checked by Hillstone Network AntiVirus
[PATCH v2] amdgpu: validate drm_amdgpu_gem_va addrs
Validate drm_amdgpu_gem_va addrs in amdgpu_gem_va_ioctl.
amdgpu_vm_bo_replace_map no longer needs to validate (and its
validations were insufficient either). amdgpu_vm_bo_map has internal
users and its validations are kept.
This is motivated by OOB access in amdgpu_vm_update_range when
offset_in_bo+map_size overflows.
Userspace (radeonsi and radv) seems fine as well.
v2: keep the validations in amdgpu_vm_bo_map
Fixes: 9f7eb5367d00 ("drm/amdgpu: actually use the VM map parameters")
Signed-off-by: Chia-I Wu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 15 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 8 +---
2 files changed, 16 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index d8e683688daab..36d5adfdf0f69 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -681,6 +681,21 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
uint64_t vm_size;
int r = 0;
+ if (args->va_address & ~PAGE_MASK || args->offset_in_bo & ~PAGE_MASK ||
+ args->map_size & ~PAGE_MASK) {
+ dev_dbg(dev->dev, "unaligned va_address 0x%LX, offset_in_bo
0x%LX, or map_size 0x%LX\n",
+ args->va_address, args->offset_in_bo, args->map_size);
+ return -EINVAL;
+ }
+
+ if (args->map_size == 0 ||
+ args->va_address + args->map_size < args->va_address ||
+ args->offset_in_bo + args->map_size < args->offset_in_bo) {
+ dev_dbg(dev->dev, "invalid map_size 0x%LX (va_address 0x%LX,
offset_in_bo 0x%LX)\n",
+ args->map_size, args->va_address, args->offset_in_bo);
+ return -EINVAL;
+ }
+
if (args->va_address < AMDGPU_VA_RESERVED_SIZE) {
dev_dbg(dev->dev,
"va_address 0x%LX is in reserved area 0x%LX\n",
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index b9441ab457ea7..6307baaa136cf 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1501,15 +1501,9 @@ int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
uint64_t eaddr;
int r;
- /* validate the parameters */
- if (saddr & ~PAGE_MASK || offset & ~PAGE_MASK ||
- size == 0 || size & ~PAGE_MASK)
- return -EINVAL;
-
/* make sure object fit at this offset */
eaddr = saddr + size - 1;
- if (saddr >= eaddr ||
- (bo && offset + size > amdgpu_bo_size(bo)) ||
+ if ((bo && offset + size > amdgpu_bo_size(bo)) ||
(eaddr >= adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT))
return -EINVAL;
--
2.40.1.698.g37aff9b760-goog
Re: [PATCH 1/2] amdgpu: validate drm_amdgpu_gem_va addrs for all ops
On Mon, May 22, 2023 at 12:12 PM Christian König wrote: > > Am 21.05.23 um 20:49 schrieb Chia-I Wu: > > On Thu, May 18, 2023 at 1:12 PM Alex Deucher wrote: > >> On Wed, May 17, 2023 at 5:27 PM Chia-I Wu wrote: > >>> On Tue, May 9, 2023 at 11:33 AM Chia-I Wu wrote: > Extend the address and size validations to AMDGPU_VA_OP_UNMAP and > AMDGPU_VA_OP_CLEAR by moving the validations to amdgpu_gem_va_ioctl. > > Internal users of amdgpu_vm_bo_map are no longer validated but they > should be fine. > > Userspace (radeonsi and radv) seems fine as well. > >>> Does this series make sense? > >> I think so, I haven't had a chance to go through this too closely yet, > >> but amdgpu_vm_bo_map() is used by ROCm as well so we'd need to make > >> sure that removing the checks in patch 1 wouldn't affect that path as > >> well. The changes in patch 2 look good. Also, these patches are > >> missing your SOB. > > Indeed. kfd_ioctl_alloc_memory_of_gpu, for example, does not validate > > va. I need to keep the validation in amdgpu_vm_bo_map for it at > > least. I guess it is more ideal for kfd_ioctl_alloc_memory_of_gpu to > > validate, but I am not familiar with amdkfd.. > > > > I can keep the existing validations, and duplicate them in > > amdgpu_gem_va_ioctl to cover AMDGPU_VA_OP_UNMAP/AMDGPU_VA_OP_CLEAR. > > The key point is that unmap and clear don't need those validations. > > It's perfectly valid to request unmap of an unaligned mapping, it will > just fail because we can't find that mapping. unmap and clear_mappings convert addresses to gpu pages so unaligned addresses are treated as if they were aligned. That's likely fine except that might be an unintentional inconsistency between va ops? When args->map_size is 0, eaddr can be smaller than saddr in clear_mappings. We are also at the mercy of how interval trees are implemented. > > Regards, > Christian. > > > > >> Thanks, > >> > >> Alex > >> > >> > >> Alex >
Re: [PATCH 01/36] drm/drm_mode_object: increase max objects to accommodate new color props
Reviewed-by: Simon Ser
[PATCH 26/36] drm/amd/display: mark plane as needing reset if plane color mgmt changes
We took a similar path for CRTC color mgmt changes, since we remap CRTC degamma to plane/DPP block. Here we can use the status of `plane->color_mgmt_changed` to detect when a plane color property changed and recreate the plane accordingly. Co-developed-by: Joshua Ashton Signed-off-by: Joshua Ashton Signed-off-by: Melissa Wen --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index a6dd982d7e77..b048c0267670 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -9471,6 +9471,9 @@ static bool should_reset_plane(struct drm_atomic_state *state, if (drm_atomic_crtc_needs_modeset(new_crtc_state)) return true; + if (new_plane_state->color_mgmt_changed) + return true; + /* * If there are any new primary or overlay planes being added or * removed then the z-order can potentially change. To ensure -- 2.39.2
[PATCH 30/36] drm/amd/display: add dc_fixpt_from_s3132 helper
From: Joshua Ashton
Detach value translation from CTM to reuse it for programming HDR
multiplier property.
Signed-off-by: Joshua Ashton
Signed-off-by: Melissa Wen
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | 8 +---
drivers/gpu/drm/amd/display/include/fixed31_32.h | 12
2 files changed, 13 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
index 8452519cabe8..629ba10fbee9 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
@@ -183,7 +183,6 @@ static void __drm_lut_to_dc_gamma(const struct
drm_color_lut *lut,
static void __drm_ctm_to_dc_matrix(const struct drm_color_ctm *ctm,
struct fixed31_32 *matrix)
{
- int64_t val;
int i;
/*
@@ -202,12 +201,7 @@ static void __drm_ctm_to_dc_matrix(const struct
drm_color_ctm *ctm,
}
/* gamut_remap_matrix[i] = ctm[i - floor(i/4)] */
- val = ctm->matrix[i - (i / 4)];
- /* If negative, convert to 2's complement. */
- if (val & (1ULL << 63))
- val = -(val & ~(1ULL << 63));
-
- matrix[i].value = val;
+ matrix[i] = dc_fixpt_from_s3132(ctm->matrix[i - (i / 4)]);
}
}
diff --git a/drivers/gpu/drm/amd/display/include/fixed31_32.h
b/drivers/gpu/drm/amd/display/include/fixed31_32.h
index ece97ae0e826..f4cc7f97329f 100644
--- a/drivers/gpu/drm/amd/display/include/fixed31_32.h
+++ b/drivers/gpu/drm/amd/display/include/fixed31_32.h
@@ -69,6 +69,18 @@ static const struct fixed31_32 dc_fixpt_epsilon = { 1LL };
static const struct fixed31_32 dc_fixpt_half = { 0x8000LL };
static const struct fixed31_32 dc_fixpt_one = { 0x1LL };
+static inline struct fixed31_32 dc_fixpt_from_s3132(__u64 x)
+{
+ struct fixed31_32 val;
+
+ /* If negative, convert to 2's complement. */
+ if (x & (1ULL << 63))
+ x = -(x & ~(1ULL << 63));
+
+ val.value = x;
+ return val;
+}
+
/*
* @brief
* Initialization routines
--
2.39.2
[PATCH 36/36] drm/amd/display: allow newer DC hardware to use degamma ROM for PQ/HLG
From: Joshua Ashton
Need to funnel the color caps through to these functions so it can check
that the hardware is capable.
Signed-off-by: Joshua Ashton
Signed-off-by: Melissa Wen
---
.../amd/display/amdgpu_dm/amdgpu_dm_color.c | 35 ---
1 file changed, 23 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
index 4a2b66568451..714f07bb9c9c 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
@@ -338,6 +338,7 @@ static int amdgpu_dm_set_atomic_regamma(struct
dc_stream_state *stream,
/**
* __set_input_tf - calculates the input transfer function based on expected
* input space.
+ * @caps: dc color capabilities
* @func: transfer function
* @lut: lookup table that defines the color space
* @lut_size: size of respective lut.
@@ -345,7 +346,7 @@ static int amdgpu_dm_set_atomic_regamma(struct
dc_stream_state *stream,
* Returns:
* 0 in case of success. -ENOMEM if fails.
*/
-static int __set_input_tf(struct dc_transfer_func *func,
+static int __set_input_tf(struct dc_color_caps *caps, struct dc_transfer_func
*func,
const struct drm_color_lut *lut, uint32_t lut_size)
{
struct dc_gamma *gamma = NULL;
@@ -362,7 +363,7 @@ static int __set_input_tf(struct dc_transfer_func *func,
__drm_lut_to_dc_gamma(lut, gamma, false);
}
- res = mod_color_calculate_degamma_params(NULL, func, gamma, gamma !=
NULL);
+ res = mod_color_calculate_degamma_params(caps, func, gamma, gamma !=
NULL);
if (gamma)
dc_gamma_release(&gamma);
@@ -511,7 +512,7 @@ static int amdgpu_dm_atomic_blend_lut(const struct
drm_color_lut *blend_lut,
func_blend->tf = tf;
func_blend->sdr_ref_white_level = SDR_WHITE_LEVEL_INIT_VALUE;
- ret = __set_input_tf(func_blend, blend_lut, blend_size);
+ ret = __set_input_tf(NULL, func_blend, blend_lut, blend_size);
} else {
func_blend->type = TF_TYPE_BYPASS;
func_blend->tf = TRANSFER_FUNCTION_LINEAR;
@@ -818,7 +819,8 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state
*crtc,
static int
map_crtc_degamma_to_dc_plane(struct dm_crtc_state *crtc,
-struct dc_plane_state *dc_plane_state)
+struct dc_plane_state *dc_plane_state,
+struct dc_color_caps *caps)
{
const struct drm_color_lut *degamma_lut;
enum dc_transfer_func_predefined tf = TRANSFER_FUNCTION_SRGB;
@@ -873,7 +875,7 @@ map_crtc_degamma_to_dc_plane(struct dm_crtc_state *crtc,
dc_plane_state->in_transfer_func->tf =
TRANSFER_FUNCTION_LINEAR;
- r = __set_input_tf(dc_plane_state->in_transfer_func,
+ r = __set_input_tf(caps, dc_plane_state->in_transfer_func,
degamma_lut, degamma_size);
if (r)
return r;
@@ -886,7 +888,7 @@ map_crtc_degamma_to_dc_plane(struct dm_crtc_state *crtc,
dc_plane_state->in_transfer_func->tf = tf;
if (tf != TRANSFER_FUNCTION_SRGB &&
- !mod_color_calculate_degamma_params(NULL,
+ !mod_color_calculate_degamma_params(caps,
dc_plane_state->in_transfer_func,
NULL, false))
return -ENOMEM;
@@ -897,7 +899,8 @@ map_crtc_degamma_to_dc_plane(struct dm_crtc_state *crtc,
static int
__set_dm_plane_degamma(struct drm_plane_state *plane_state,
- struct dc_plane_state *dc_plane_state)
+ struct dc_plane_state *dc_plane_state,
+ struct dc_color_caps *color_caps)
{
struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane_state);
const struct drm_color_lut *degamma_lut;
@@ -906,6 +909,9 @@ __set_dm_plane_degamma(struct drm_plane_state *plane_state,
bool has_degamma_lut;
int ret;
+ if (dc_plane_state->ctx && dc_plane_state->ctx->dc)
+ color_caps = &dc_plane_state->ctx->dc->caps.color;
+
degamma_lut = __extract_blob_lut(dm_plane_state->degamma_lut,
°amma_size);
@@ -928,7 +934,7 @@ __set_dm_plane_degamma(struct drm_plane_state *plane_state,
dc_plane_state->in_transfer_func->type =
TF_TYPE_DISTRIBUTED_POINTS;
- ret = __set_input_tf(dc_plane_state->in_transfer_func,
+ ret = __set_input_tf(color_caps,
dc_plane_state->in_transfer_func,
degamma_lut, degamma_size);
if (ret)
[PATCH 35/36] drm/amd/display: add DRM plane blend LUT and TF support
From: Joshua Ashton
Map DRM plane blend properties to DPP blend gamma. Plane blend is a
post-3D LUT curve that linearizes color space for blending. It may be
defined by a user-blob LUT and/or predefined transfer function. As
hardcoded curve (ROM) is not supported on blend gamma, we use AMD color
module to fill parameters when setting non-linear TF with empty LUT.
Signed-off-by: Joshua Ashton
Signed-off-by: Melissa Wen
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 +
.../amd/display/amdgpu_dm/amdgpu_dm_color.c | 58 ++-
2 files changed, 56 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 2674ecdad717..1a979bcf5651 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -8024,6 +8024,7 @@ static void amdgpu_dm_commit_planes(struct
drm_atomic_state *state,
bundle->surface_updates[planes_count].hdr_mult =
dc_plane->hdr_mult;
bundle->surface_updates[planes_count].func_shaper =
dc_plane->in_shaper_func;
bundle->surface_updates[planes_count].lut3d_func =
dc_plane->lut3d_func;
+ bundle->surface_updates[planes_count].blend_tf =
dc_plane->blend_tf;
}
amdgpu_dm_plane_fill_dc_scaling_info(dm->adev, new_plane_state,
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
index a441c02380f2..4a2b66568451 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
@@ -492,6 +492,34 @@ static int amdgpu_dm_atomic_shaper_lut(const struct
drm_color_lut *shaper_lut,
return ret;
}
+static int amdgpu_dm_atomic_blend_lut(const struct drm_color_lut *blend_lut,
+ bool has_rom,
+ enum dc_transfer_func_predefined tf,
+ uint32_t blend_size,
+ struct dc_transfer_func *func_blend)
+{
+ int ret = 0;
+
+ if (blend_size || tf != TRANSFER_FUNCTION_LINEAR) {
+ /* DRM plane gamma LUT or TF means we are linearizing color
+* space before blending (similar to degamma programming). As
+* we don't have hardcoded curve support, or we use AMD color
+* module to fill the parameters that will be translated to HW
+* points.
+*/
+ func_blend->type = TF_TYPE_DISTRIBUTED_POINTS;
+ func_blend->tf = tf;
+ func_blend->sdr_ref_white_level = SDR_WHITE_LEVEL_INIT_VALUE;
+
+ ret = __set_input_tf(func_blend, blend_lut, blend_size);
+ } else {
+ func_blend->type = TF_TYPE_BYPASS;
+ func_blend->tf = TRANSFER_FUNCTION_LINEAR;
+ }
+
+ return ret;
+}
+
/* amdgpu_dm_atomic_shaper_lut3d - set DRM CRTC shaper LUT and 3D LUT to DC
* interface
* @dc: Display Core control structure
@@ -921,8 +949,10 @@ amdgpu_dm_plane_set_color_properties(struct
drm_plane_state *plane_state,
{
struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane_state);
enum drm_transfer_function shaper_tf = DRM_TRANSFER_FUNCTION_DEFAULT;
- const struct drm_color_lut *shaper_lut, *lut3d;
- uint32_t lut3d_size, shaper_size;
+ enum drm_transfer_function blend_tf = DRM_TRANSFER_FUNCTION_DEFAULT;
+ const struct drm_color_lut *shaper_lut, *lut3d, *blend_lut;
+ uint32_t lut3d_size, shaper_size, blend_size;
+ int ret;
/* We have nothing to do here, return */
if (!plane_state->color_mgmt_changed)
@@ -940,8 +970,30 @@ amdgpu_dm_plane_set_color_properties(struct
drm_plane_state *plane_state,
ret = amdgpu_dm_atomic_shaper_lut(shaper_lut, false,
drm_tf_to_dc_tf(shaper_tf),
shaper_size,
dc_plane_state->in_shaper_func);
+ if (ret) {
+ drm_dbg_kms(plane_state->plane->dev,
+ "setting plane %d shaper/3d lut failed.\n",
+ plane_state->plane->index);
- return ret;
+ return ret;
+ }
+
+ blend_tf = dm_plane_state->blend_tf;
+ blend_lut = __extract_blob_lut(dm_plane_state->blend_lut, &blend_size);
+ blend_size = blend_lut != NULL ? blend_size : 0;
+
+ ret = amdgpu_dm_atomic_blend_lut(blend_lut, false,
+drm_tf_to_dc_tf(blend_tf),
+blend_size, dc_plane_state->blend_tf);
+ if (ret) {
+ drm_dbg_kms(plane_state->plane->dev,
+ "setting plane %d gamma lut failed.\n",
+
[PATCH 32/36] drm/amd/display: program DPP shaper and 3D LUT if updated
If shaper and 3D LUT data updates, lut_3d bit in update_flag is updated and we need to call set_input_transfer_func to program DPP shaper and 3D LUTs. Small cleanup of code style in the related if-condition. Signed-off-by: Melissa Wen --- drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c index e74c3ce561ab..e347316d0a5e 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c @@ -1764,8 +1764,9 @@ static void dcn20_program_pipe( hws->funcs.set_hdr_multiplier(pipe_ctx); if (pipe_ctx->update_flags.bits.enable || - pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change || - pipe_ctx->plane_state->update_flags.bits.gamma_change) + pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change || + pipe_ctx->plane_state->update_flags.bits.gamma_change || + pipe_ctx->plane_state->update_flags.bits.lut_3d) hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state); /* dcn10_translate_regamma_to_hw_format takes 750us to finish -- 2.39.2
[PATCH 34/36] drm/amd/display: handle empty LUTs in __set_input_tf
From: Joshua Ashton
Unlike degamma, blend gamma doesn't support hardcoded curve
(predefined/ROM), but we can use AMD color module to fill blend gamma
parameters when we have non-linear plane gamma TF without plane gamma
LUT. The regular degamma path doesn't hit this.
Signed-off-by: Joshua Ashton
Signed-off-by: Melissa Wen
---
.../amd/display/amdgpu_dm/amdgpu_dm_color.c | 20 +++
1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
index b075c9f6e717..a441c02380f2 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
@@ -351,17 +351,21 @@ static int __set_input_tf(struct dc_transfer_func *func,
struct dc_gamma *gamma = NULL;
bool res;
- gamma = dc_create_gamma();
- if (!gamma)
- return -ENOMEM;
+ if (lut_size) {
+ gamma = dc_create_gamma();
+ if (!gamma)
+ return -ENOMEM;
- gamma->type = GAMMA_CUSTOM;
- gamma->num_entries = lut_size;
+ gamma->type = GAMMA_CUSTOM;
+ gamma->num_entries = lut_size;
- __drm_lut_to_dc_gamma(lut, gamma, false);
+ __drm_lut_to_dc_gamma(lut, gamma, false);
+ }
- res = mod_color_calculate_degamma_params(NULL, func, gamma, true);
- dc_gamma_release(&gamma);
+ res = mod_color_calculate_degamma_params(NULL, func, gamma, gamma !=
NULL);
+
+ if (gamma)
+ dc_gamma_release(&gamma);
return res ? 0 : -ENOMEM;
}
--
2.39.2
[PATCH 31/36] drm/adm/display: add HDR multiplier support
From: Joshua Ashton
With `dc_fixpt_from_s3132()` translation, we can just use it to set
hdr_mult.
Signed-off-by: Joshua Ashton
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 +
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | 3 +++
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 4f3597ea9873..11135c3db6cc 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -8021,6 +8021,7 @@ static void amdgpu_dm_commit_planes(struct
drm_atomic_state *state,
bundle->surface_updates[planes_count].gamma =
dc_plane->gamma_correction;
bundle->surface_updates[planes_count].in_transfer_func
= dc_plane->in_transfer_func;
bundle->surface_updates[planes_count].gamut_remap_matrix =
&dc_plane->gamut_remap_matrix;
+ bundle->surface_updates[planes_count].hdr_mult =
dc_plane->hdr_mult;
}
amdgpu_dm_plane_fill_dc_scaling_info(dm->adev, new_plane_state,
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
index 629ba10fbee9..57d6aab76295 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
@@ -928,6 +928,7 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state
*crtc,
struct drm_plane_state *plane_state,
struct dc_plane_state *dc_plane_state)
{
+ struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane_state);
bool has_crtc_cm_degamma;
int ret;
@@ -938,6 +939,8 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state
*crtc,
/* After, we start to update values according to color props */
has_crtc_cm_degamma = (crtc->cm_has_degamma ||
crtc->cm_is_degamma_srgb);
+ dc_plane_state->hdr_mult =
dc_fixpt_from_s3132(dm_plane_state->hdr_mult);
+
ret = __set_dm_plane_degamma(plane_state, dc_plane_state);
if (ret == -ENOMEM)
return ret;
--
2.39.2
[PATCH 33/36] drm/amd/display: add plane shaper/3D LUT and shaper TF support
We already have the steps to program post-blending shaper/3D LUT on AMD
display driver, but unlike MPC 3D LUT, we don't need to acquire/release
DPP 3D LUT. We can reuse programming steps to map plane properties to
DC plane for pre-blending (plane) shaper/3D LUT setup.
Signed-off-by: Melissa Wen
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++
.../amd/display/amdgpu_dm/amdgpu_dm_color.c | 35 ---
2 files changed, 33 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 11135c3db6cc..2674ecdad717 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -8022,6 +8022,8 @@ static void amdgpu_dm_commit_planes(struct
drm_atomic_state *state,
bundle->surface_updates[planes_count].in_transfer_func
= dc_plane->in_transfer_func;
bundle->surface_updates[planes_count].gamut_remap_matrix =
&dc_plane->gamut_remap_matrix;
bundle->surface_updates[planes_count].hdr_mult =
dc_plane->hdr_mult;
+ bundle->surface_updates[planes_count].func_shaper =
dc_plane->in_shaper_func;
+ bundle->surface_updates[planes_count].lut3d_func =
dc_plane->lut3d_func;
}
amdgpu_dm_plane_fill_dc_scaling_info(dm->adev, new_plane_state,
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
index 57d6aab76295..b075c9f6e717 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
@@ -911,6 +911,35 @@ __set_dm_plane_degamma(struct drm_plane_state *plane_state,
return 0;
}
+static int
+amdgpu_dm_plane_set_color_properties(struct drm_plane_state *plane_state,
+struct dc_plane_state *dc_plane_state)
+{
+ struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane_state);
+ enum drm_transfer_function shaper_tf = DRM_TRANSFER_FUNCTION_DEFAULT;
+ const struct drm_color_lut *shaper_lut, *lut3d;
+ uint32_t lut3d_size, shaper_size;
+
+ /* We have nothing to do here, return */
+ if (!plane_state->color_mgmt_changed)
+ return 0;
+
+ dc_plane_state->hdr_mult =
dc_fixpt_from_s3132(dm_plane_state->hdr_mult);
+
+ shaper_tf = dm_plane_state->shaper_tf;
+ shaper_lut = __extract_blob_lut(dm_plane_state->shaper_lut,
&shaper_size);
+ lut3d = __extract_blob_lut(dm_plane_state->lut3d, &lut3d_size);
+ lut3d_size = lut3d != NULL ? lut3d_size : 0;
+ shaper_size = shaper_lut != NULL ? shaper_size : 0;
+
+ amdgpu_dm_atomic_lut3d(lut3d, lut3d_size, dc_plane_state->lut3d_func);
+ ret = amdgpu_dm_atomic_shaper_lut(shaper_lut, false,
+ drm_tf_to_dc_tf(shaper_tf),
+ shaper_size,
dc_plane_state->in_shaper_func);
+
+ return ret;
+}
+
/**
* amdgpu_dm_update_plane_color_mgmt: Maps DRM color management to DC plane.
* @crtc: amdgpu_dm crtc state
@@ -928,7 +957,6 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state
*crtc,
struct drm_plane_state *plane_state,
struct dc_plane_state *dc_plane_state)
{
- struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane_state);
bool has_crtc_cm_degamma;
int ret;
@@ -939,8 +967,6 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state
*crtc,
/* After, we start to update values according to color props */
has_crtc_cm_degamma = (crtc->cm_has_degamma ||
crtc->cm_is_degamma_srgb);
- dc_plane_state->hdr_mult =
dc_fixpt_from_s3132(dm_plane_state->hdr_mult);
-
ret = __set_dm_plane_degamma(plane_state, dc_plane_state);
if (ret == -ENOMEM)
return ret;
@@ -972,5 +998,6 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state
*crtc,
return ret;
}
- return 0;
+ return amdgpu_dm_plane_set_color_properties(plane_state,
+ dc_plane_state);
}
--
2.39.2
[PATCH 29/36] drm/amd/display: reject atomic commit if setting both plane and CRTC degamma
DC only has pre-blending degamma caps (plane/DPP) that is currently in
use for CRTC/post-blending degamma, so that we don't have HW caps to
perform plane and CRTC degamma at the same time. Reject atomic updates
when serspace sets both plane and CRTC degamma properties.
Signed-off-by: Melissa Wen
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
index 89178b7f636f..8452519cabe8 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
@@ -945,9 +945,20 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state
*crtc,
has_crtc_cm_degamma = (crtc->cm_has_degamma ||
crtc->cm_is_degamma_srgb);
ret = __set_dm_plane_degamma(plane_state, dc_plane_state);
- if (ret != -EINVAL)
+ if (ret == -ENOMEM)
return ret;
+ /* We only have one degamma block available (pre-blending) for the
+* whole color correction pipeline, so that we can't actually perform
+* plane and CRTC degamma at the same time. Explicitly reject atomic
+* updates when userspace sets both plane and CRTC degamma properties.
+*/
+ if (has_crtc_cm_degamma && ret != -EINVAL){
+ drm_dbg_kms(crtc->base.crtc->dev,
+ "doesn't support plane and CRTC degamma at the same
time\n");
+ return -EINVAL;
+ }
+
/* If we are here, it means we don't have plane degamma settings, check
* if we have CRTC degamma waiting for mapping to pre-blending degamma
* block
--
2.39.2
[PATCH 28/36] drm/amd/display: add support for plane degamma TF and LUT properties
From: Joshua Ashton
Set DC plane with user degamma LUT or predefined TF from driver-specific
plane color properties. If plane and CRTC degamma are set in the same
time, plane degamma has priority. That means, we only set CRTC degamma
if we don't have plane degamma LUT or TF to configure. We return -EINVAL
if we don't have plane degamma settings, so we can continue and check
CRTC degamma.
Signed-off-by: Joshua Ashton
Signed-off-by: Melissa Wen
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 +-
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 1 +
.../amd/display/amdgpu_dm/amdgpu_dm_color.c | 70 +--
3 files changed, 69 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index b048c0267670..4f3597ea9873 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -5038,7 +5038,9 @@ static int fill_dc_plane_attributes(struct amdgpu_device
*adev,
* Always set input transfer function, since plane state is refreshed
* every time.
*/
- ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state);
+ ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state,
+ plane_state,
+ dc_plane_state);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index ea76c2957848..bf4a1d6be99e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -902,6 +902,7 @@ int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state
*crtc_state);
int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc,
struct dc_state *ctx);
int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc,
+ struct drm_plane_state *plane_state,
struct dc_plane_state *dc_plane_state);
void amdgpu_dm_update_connector_after_detect(
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
index 246f12532c48..89178b7f636f 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
@@ -869,9 +869,58 @@ map_crtc_degamma_to_dc_plane(struct dm_crtc_state *crtc,
return 0;
}
+static int
+__set_dm_plane_degamma(struct drm_plane_state *plane_state,
+ struct dc_plane_state *dc_plane_state)
+{
+ struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane_state);
+ const struct drm_color_lut *degamma_lut;
+ enum drm_transfer_function drm_tf = DRM_TRANSFER_FUNCTION_DEFAULT;
+ uint32_t degamma_size;
+ bool has_degamma_lut;
+ int ret;
+
+ degamma_lut = __extract_blob_lut(dm_plane_state->degamma_lut,
+°amma_size);
+
+ has_degamma_lut = degamma_lut &&
+ !__is_lut_linear(degamma_lut, degamma_size);
+
+ drm_tf = dm_plane_state->degamma_tf;
+
+ /* If we don't have plane degamma LUT nor TF to set on DC, we have
+* nothing to do here, return.
+*/
+ if (!has_degamma_lut && drm_tf == DRM_TRANSFER_FUNCTION_DEFAULT)
+ return -EINVAL;
+
+ dc_plane_state->in_transfer_func->tf = drm_tf_to_dc_tf(drm_tf);
+
+ if (has_degamma_lut) {
+ ASSERT(degamma_size == MAX_COLOR_LUT_ENTRIES);
+
+ dc_plane_state->in_transfer_func->type =
+ TF_TYPE_DISTRIBUTED_POINTS;
+
+ ret = __set_input_tf(dc_plane_state->in_transfer_func,
+degamma_lut, degamma_size);
+ if (ret)
+ return ret;
+ } else {
+ dc_plane_state->in_transfer_func->type =
+ TF_TYPE_PREDEFINED;
+
+ if (!mod_color_calculate_degamma_params(NULL,
+ dc_plane_state->in_transfer_func, NULL, false))
+ return -ENOMEM;
+ }
+ return 0;
+}
+
/**
* amdgpu_dm_update_plane_color_mgmt: Maps DRM color management to DC plane.
* @crtc: amdgpu_dm crtc state
+ * @plane_state: DRM plane state
* @dc_plane_state: target DC surface
*
* Update the underlying dc_stream_state's input transfer function (ITF) in
@@ -882,13 +931,28 @@ map_crtc_degamma_to_dc_plane(struct dm_crtc_state *crtc,
* 0 on success. -ENOMEM if mem allocation fails.
*/
int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc,
+ struct drm_plane_state *plane_state,
struct dc_plane_state *dc_plane_state)
{
[PATCH 27/36] drm/amd/display: decouple steps for mapping CRTC degamma to DC plane
The next patch adds pre-blending degamma to AMD color mgmt pipeline, but
pre-blending degamma caps (DPP) is currently in use to provide DRM CRTC
atomic degamma or implict degamma on legacy gamma. Detach degamma usage
regarging CRTC color properties to manage plane and CRTC color
correction combinations.
Signed-off-by: Melissa Wen
---
.../amd/display/amdgpu_dm/amdgpu_dm_color.c | 59 +--
1 file changed, 41 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
index 5650b85cc28e..246f12532c48 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
@@ -790,20 +790,9 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state
*crtc,
return 0;
}
-/**
- * amdgpu_dm_update_plane_color_mgmt: Maps DRM color management to DC plane.
- * @crtc: amdgpu_dm crtc state
- * @dc_plane_state: target DC surface
- *
- * Update the underlying dc_stream_state's input transfer function (ITF) in
- * preparation for hardware commit. The transfer function used depends on
- * the preparation done on the stream for color management.
- *
- * Returns:
- * 0 on success. -ENOMEM if mem allocation fails.
- */
-int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc,
- struct dc_plane_state *dc_plane_state)
+static int
+map_crtc_degamma_to_dc_plane(struct dm_crtc_state *crtc,
+struct dc_plane_state *dc_plane_state)
{
const struct drm_color_lut *degamma_lut;
enum dc_transfer_func_predefined tf = TRANSFER_FUNCTION_SRGB;
@@ -826,8 +815,7 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state
*crtc,
°amma_size);
ASSERT(degamma_size == MAX_COLOR_LUT_ENTRIES);
- dc_plane_state->in_transfer_func->type =
- TF_TYPE_DISTRIBUTED_POINTS;
+ dc_plane_state->in_transfer_func->type =
TF_TYPE_DISTRIBUTED_POINTS;
/*
* This case isn't fully correct, but also fairly
@@ -863,7 +851,7 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state
*crtc,
degamma_lut, degamma_size);
if (r)
return r;
- } else if (crtc->cm_is_degamma_srgb) {
+ } else {
/*
* For legacy gamma support we need the regamma input
* in linear space. Assume that the input is sRGB.
@@ -873,8 +861,43 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state
*crtc,
if (tf != TRANSFER_FUNCTION_SRGB &&
!mod_color_calculate_degamma_params(NULL,
- dc_plane_state->in_transfer_func, NULL, false))
+
dc_plane_state->in_transfer_func,
+ NULL, false))
return -ENOMEM;
+ }
+
+ return 0;
+}
+
+/**
+ * amdgpu_dm_update_plane_color_mgmt: Maps DRM color management to DC plane.
+ * @crtc: amdgpu_dm crtc state
+ * @dc_plane_state: target DC surface
+ *
+ * Update the underlying dc_stream_state's input transfer function (ITF) in
+ * preparation for hardware commit. The transfer function used depends on
+ * the preparation done on the stream for color management.
+ *
+ * Returns:
+ * 0 on success. -ENOMEM if mem allocation fails.
+ */
+int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc,
+ struct dc_plane_state *dc_plane_state)
+{
+ bool has_crtc_cm_degamma;
+ int ret;
+
+ has_crtc_cm_degamma = (crtc->cm_has_degamma ||
crtc->cm_is_degamma_srgb);
+ if (has_crtc_cm_degamma){
+ /* AMD HW doesn't have post-blending degamma caps. When DRM
+* CRTC atomic degamma is set, we maps it to DPP degamma block
+* (pre-blending) or, on legacy gamma, we use DPP degamma to
+* linearize (implicit degamma) from sRGB/BT709 according to
+* the input space.
+*/
+ ret = map_crtc_degamma_to_dc_plane(crtc, dc_plane_state);
+ if (ret)
+ return ret;
} else {
/* ...Otherwise we can just bypass the DGM block. */
dc_plane_state->in_transfer_func->type = TF_TYPE_BYPASS;
--
2.39.2
[PATCH 25/36] drm/amd/display: add CRTC shaper TF support
Inspired by regamma TF, follow similar steps to add TF + 1D LUT for
shaper func. Reuse regamma_tf property, since the driver doesn't support
shaper and out gamma at the same time. Only set shaper TF if setting
shaper LUT or 3D LUT. We could rename regamma_tf - if necessary to avoid
misunderstandings - or add a specific property for shaper TF when.
Signed-off-by: Melissa Wen
---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_color.c| 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
index 7cf35ac3fad3..5650b85cc28e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
@@ -470,19 +470,22 @@ static void amdgpu_dm_atomic_lut3d(const struct
drm_color_lut *drm_lut,
}
static int amdgpu_dm_atomic_shaper_lut(const struct drm_color_lut *shaper_lut,
+ bool has_rom,
+ enum dc_transfer_func_predefined tf,
uint32_t shaper_size,
struct dc_transfer_func *func_shaper)
{
int ret = 0;
- if (shaper_size) {
+ if (shaper_size || tf != TRANSFER_FUNCTION_LINEAR) {
/* If DRM shaper LUT is set, we assume a linear color space
* (linearized by DRM degamma 1D LUT or not)
*/
func_shaper->type = TF_TYPE_DISTRIBUTED_POINTS;
- func_shaper->tf = TRANSFER_FUNCTION_LINEAR;
+ func_shaper->tf = tf;
+ func_shaper->sdr_ref_white_level = SDR_WHITE_LEVEL_INIT_VALUE;
- ret = __set_output_tf(func_shaper, shaper_lut, shaper_size,
false);
+ ret = __set_output_tf(func_shaper, shaper_lut, shaper_size,
has_rom);
} else {
func_shaper->type = TF_TYPE_BYPASS;
func_shaper->tf = TRANSFER_FUNCTION_LINEAR;
@@ -509,6 +512,8 @@ static int amdgpu_dm_atomic_shaper_lut3d(struct dc *dc,
struct dc_stream_state *stream,
const struct drm_color_lut
*drm_shaper_lut,
uint32_t drm_shaper_size,
+bool has_rom,
+enum dc_transfer_func_predefined tf,
const struct drm_color_lut *drm_lut3d,
uint32_t drm_lut3d_size)
{
@@ -536,7 +541,7 @@ static int amdgpu_dm_atomic_shaper_lut3d(struct dc *dc,
amdgpu_dm_atomic_lut3d(drm_lut3d, drm_lut3d_size, lut3d_func);
- return amdgpu_dm_atomic_shaper_lut(drm_shaper_lut,
+ return amdgpu_dm_atomic_shaper_lut(drm_shaper_lut, has_rom, tf,
drm_shaper_size, func_shaper);
}
@@ -734,6 +739,7 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state
*crtc,
shaper_size = shaper_lut != NULL ? shaper_size : 0;
r = amdgpu_dm_atomic_shaper_lut3d(adev->dm.dc, ctx, stream,
shaper_lut, shaper_size,
+ has_rom, tf,
lut3d, lut3d_size);
if (r) {
drm_dbg(&adev->ddev, "Failed on shaper/3D LUTs
setup\n");
--
2.39.2
[PATCH 22/36] drm/amd/display: add CRTC shaper LUT support
Map DC shaper LUT to DM CRTC color management. Shaper LUT can be used to
delinearize and/or normalize the color space for computational
efficiency and achiving specific visual styles. Blending usually occurs
in linear space and if a CRTC degamma 1D LUT is set to linearize the
color space, a custom shaper 1D LUT can be used just before applying 3D
LUT.
Signed-off-by: Melissa Wen
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 7 +++
.../amd/display/amdgpu_dm/amdgpu_dm_color.c | 54 ++-
2 files changed, 47 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index eebe12c353ad..ea76c2957848 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -803,6 +803,13 @@ struct dm_crtc_state {
* has a larger set of post-blending color calibration. Here, DC MPC
* color caps are wired up to DM CRTC state:
*/
+ /**
+* @shaper_lut:
+*
+* Post-blending 1D Lookup table used to de-linearize pixel data for 3D
+* LUT. The blob (if not NULL) is an array of &struct drm_color_lut.
+*/
+ struct drm_property_blob *shaper_lut;
/**
* @lut3d:
*
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
index cef8d0d7f37b..934636d7b8d3 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
@@ -443,15 +443,26 @@ static void amdgpu_dm_atomic_lut3d(const struct
drm_color_lut *drm_lut,
}
}
-static int amdgpu_dm_atomic_shaper_lut(struct dc_transfer_func *func_shaper)
+static int amdgpu_dm_atomic_shaper_lut(const struct drm_color_lut *shaper_lut,
+ uint32_t shaper_size,
+ struct dc_transfer_func *func_shaper)
{
- /* We don't get DRM shaper LUT yet. We assume the input color space is
already
-* delinearized, so we don't need a shaper LUT and we can just BYPASS
-*/
- func_shaper->type = TF_TYPE_BYPASS;
- func_shaper->tf = TRANSFER_FUNCTION_LINEAR;
+ int ret = 0;
- return 0;
+ if (shaper_size) {
+ /* If DRM shaper LUT is set, we assume a linear color space
+* (linearized by DRM degamma 1D LUT or not)
+*/
+ func_shaper->type = TF_TYPE_DISTRIBUTED_POINTS;
+ func_shaper->tf = TRANSFER_FUNCTION_LINEAR;
+
+ ret = __set_output_tf(func_shaper, shaper_lut, shaper_size,
false);
+ } else {
+ func_shaper->type = TF_TYPE_BYPASS;
+ func_shaper->tf = TRANSFER_FUNCTION_LINEAR;
+ }
+
+ return ret;
}
/* amdgpu_dm_atomic_shaper_lut3d - set DRM CRTC shaper LUT and 3D LUT to DC
@@ -499,7 +510,8 @@ static int amdgpu_dm_atomic_shaper_lut3d(struct dc *dc,
amdgpu_dm_atomic_lut3d(drm_lut3d, drm_lut3d_size, lut3d_func);
- return amdgpu_dm_atomic_shaper_lut(func_shaper);
+ return amdgpu_dm_atomic_shaper_lut(drm_shaper_lut,
+ drm_shaper_size, func_shaper);
}
/**
@@ -531,12 +543,22 @@ static uint32_t amdgpu_dm_get_lut3d_size(struct
amdgpu_device *adev,
int amdgpu_dm_verify_lut3d_size(struct amdgpu_device *adev,
const struct drm_crtc_state *crtc_state)
{
- const struct drm_color_lut *lut3d = NULL;
struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc_state);
+ const struct drm_color_lut *shaper = NULL, *lut3d = NULL;
uint32_t exp_size, size;
- exp_size = amdgpu_dm_get_lut3d_size(adev, MAX_COLOR_3DLUT_ENTRIES);
+ /* shaper LUT is only available if 3D LUT color caps*/
+ exp_size = amdgpu_dm_get_lut3d_size(adev, MAX_COLOR_LUT_ENTRIES);
+ shaper = __extract_blob_lut(acrtc_state->shaper_lut, &size);
+ if (shaper && size != exp_size) {
+ drm_dbg(&adev->ddev,
+ "Invalid Shaper LUT size. Should be %u but got %u.\n",
+ exp_size, size);
+ return -EINVAL;
+ }
+
+ exp_size = amdgpu_dm_get_lut3d_size(adev, MAX_COLOR_3DLUT_ENTRIES);
lut3d = __extract_blob_lut(acrtc_state->lut3d, &size);
if (lut3d && size != exp_size) {
@@ -618,15 +640,16 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state
*crtc,
uint32_t degamma_size, regamma_size;
bool has_regamma, has_degamma;
bool is_legacy;
+ const struct drm_color_lut *shaper_lut, *lut3d;
+ uint32_t shaper_size, lut3d_size;
int r;
- const struct drm_color_lut *lut3d;
- uint32_t lut3d_size;
r = amdgpu_dm_verify_lut3d_size(adev, &crtc->base);
if (r)
return r;
lut3d = __
[PATCH 16/36] drm/amd/display: update lut3d and shaper lut to stream
It follows the same path of out_transfer_func for stream updates, since shaper LUT and 3D LUT is programmed in funcs.set_output_transfer_func() and this function is called in the atomic commit_tail when update_flags.bits.out_tf is set. Signed-off-by: Melissa Wen --- drivers/gpu/drm/amd/display/dc/core/dc.c | 10 +- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index f864fd3b6f29..8e8da8c0f8cc 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -2609,7 +2609,7 @@ static enum surface_update_type check_update_surfaces_for_stream( stream_update->integer_scaling_update) su_flags->bits.scaling = 1; - if (stream_update->out_transfer_func) + if (stream_update->out_transfer_func || stream_update->lut3d_func) su_flags->bits.out_tf = 1; if (stream_update->abm_level) @@ -2961,6 +2961,14 @@ static void copy_stream_update_to_stream(struct dc *dc, sizeof(struct dc_transfer_func_distributed_points)); } + if (update->func_shaper && + stream->func_shaper != update->func_shaper) + stream->func_shaper = update->func_shaper; + + if (update->lut3d_func && + stream->lut3d_func != update->lut3d_func) + stream->lut3d_func = update->lut3d_func; + if (update->hdr_static_metadata) stream->hdr_static_metadata = *update->hdr_static_metadata; -- 2.39.2
[PATCH 21/36] drm/amd/display: add CRTC 3D LUT support
Wire up DC 3D LUT to DM CRTC color management (post-blending). On AMD
display HW, we have to set a shaper LUT to delinearize or normalize the
color space before applying a 3D LUT (since we have a reduced number of
LUT entries). Therefore, we map DC shaper LUT to DM CRTC color mgmt in
the next patch.
Signed-off-by: Melissa Wen
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 +
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 17 ++
.../amd/display/amdgpu_dm/amdgpu_dm_color.c | 158 +-
3 files changed, 180 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 0be62fe436b0..a6dd982d7e77 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -9976,6 +9976,12 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
goto fail;
}
+ ret = amdgpu_dm_verify_lut3d_size(adev, new_crtc_state);
+ if (ret) {
+ drm_dbg_driver(dev, "amdgpu_dm_verify_lut_sizes()
failed\n");
+ goto fail;
+ }
+
if (!new_crtc_state->enable)
continue;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index e5f9db5a43f4..eebe12c353ad 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -797,6 +797,21 @@ struct dm_crtc_state {
int abm_level;
+ /* AMD driver-private CRTC color management
+*
+* DRM provides CRTC degamma/ctm/gamma color mgmt features, but AMD HW
+* has a larger set of post-blending color calibration. Here, DC MPC
+* color caps are wired up to DM CRTC state:
+*/
+ /**
+* @lut3d:
+*
+* Post-blending 3D Lookup table for converting pixel data. When
+* supported by HW (DCN 3+), it is positioned just before post-blending
+* regamma and always assumes a preceding shaper LUT. The blob (if not
+* NULL) is an array of &struct drm_color_lut.
+*/
+ struct drm_property_blob *lut3d;
/**
* @regamma_tf:
*
@@ -868,6 +883,8 @@ void amdgpu_dm_trigger_timing_sync(struct drm_device *dev);
/* 3D LUT max size is 17x17x17 */
#define MAX_COLOR_3DLUT_ENTRIES 4913
#define MAX_COLOR_3DLUT_BITDEPTH 12
+int amdgpu_dm_verify_lut3d_size(struct amdgpu_device *adev,
+ const struct drm_crtc_state *crtc_state);
/* 1D LUT size */
#define MAX_COLOR_LUT_ENTRIES 4096
/* Legacy gamm LUT users such as X doesn't like large LUT sizes */
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
index 161807e19886..cef8d0d7f37b 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
@@ -364,6 +364,96 @@ static int __set_input_tf(struct dc_transfer_func *func,
return res ? 0 : -ENOMEM;
}
+static void __to_dc_lut3d_color(struct dc_rgb *rgb,
+ const struct drm_color_lut lut,
+ int bit_precision)
+{
+ rgb->red = drm_color_lut_extract(lut.red, bit_precision);
+ rgb->green = drm_color_lut_extract(lut.green, bit_precision);
+ rgb->blue = drm_color_lut_extract(lut.blue, bit_precision);
+}
+
+static void __drm_3dlut_to_dc_3dlut(const struct drm_color_lut *lut,
+ uint32_t lut3d_size,
+ struct tetrahedral_params *params,
+ bool use_tetrahedral_9,
+ int bit_depth)
+{
+ struct dc_rgb *lut0;
+ struct dc_rgb *lut1;
+ struct dc_rgb *lut2;
+ struct dc_rgb *lut3;
+ int lut_i, i;
+
+
+ if (use_tetrahedral_9) {
+ lut0 = params->tetrahedral_9.lut0;
+ lut1 = params->tetrahedral_9.lut1;
+ lut2 = params->tetrahedral_9.lut2;
+ lut3 = params->tetrahedral_9.lut3;
+ } else {
+ lut0 = params->tetrahedral_17.lut0;
+ lut1 = params->tetrahedral_17.lut1;
+ lut2 = params->tetrahedral_17.lut2;
+ lut3 = params->tetrahedral_17.lut3;
+ }
+
+ for (lut_i = 0, i = 0; i < lut3d_size - 4; lut_i++, i += 4) {
+ /* We should consider the 3dlut RGB values are distributed
+* along four arrays lut0-3 where the first sizes 1229 and the
+* other 1228. The bit depth supported for 3dlut channel is
+* 12-bit, but DC also supports 10-bit.
+*
+* TODO: improve color pipeline API to enable the userspace set
+* bit depth
[PATCH 24/36] drm/amd/display: set sdr_ref_white_level to 80 for out_transfer_func
From: Joshua Ashton
Otherwise this is just initialized to 0. This needs to actually have a
value so that compute_curve can work for PQ EOTF.
Signed-off-by: Joshua Ashton
Co-developed-by: Melissa Wen
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
index 146363363ef0..7cf35ac3fad3 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
@@ -72,6 +72,7 @@
*/
#define MAX_DRM_LUT_VALUE 0x
+#define SDR_WHITE_LEVEL_INIT_VALUE 80
/**
* amdgpu_dm_init_color_mod - Initialize the color module.
@@ -325,6 +326,7 @@ static int amdgpu_dm_set_atomic_regamma(struct
dc_stream_state *stream,
*/
out_tf->type = TF_TYPE_DISTRIBUTED_POINTS;
out_tf->tf = tf;
+ out_tf->sdr_ref_white_level = SDR_WHITE_LEVEL_INIT_VALUE;
ret = __set_output_tf(out_tf, regamma_lut, regamma_size,
has_rom);
} else {
--
2.39.2
[PATCH 23/36] drm/amd/display: add CRTC regamma TF support
From: Joshua Ashton
Add predefined transfer function programming. There is no out gamma ROM,
but we can use AMD color modules to program LUT parameters from a
predefined TF and an empty regamma LUT (or bump up LUT parameters with
predefined TF setup).
Signed-off-by: Joshua Ashton
Signed-off-by: Melissa Wen
---
.../amd/display/amdgpu_dm/amdgpu_dm_color.c | 58 ++-
1 file changed, 42 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
index 934636d7b8d3..146363363ef0 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
@@ -268,16 +268,18 @@ static int __set_output_tf(struct dc_transfer_func *func,
struct calculate_buffer cal_buffer = {0};
bool res;
- ASSERT(lut && lut_size == MAX_COLOR_LUT_ENTRIES);
-
cal_buffer.buffer_index = -1;
- gamma = dc_create_gamma();
- if (!gamma)
- return -ENOMEM;
+ if (lut_size) {
+ ASSERT(lut && lut_size == MAX_COLOR_LUT_ENTRIES);
- gamma->num_entries = lut_size;
- __drm_lut_to_dc_gamma(lut, gamma, false);
+ gamma = dc_create_gamma();
+ if (!gamma)
+ return -ENOMEM;
+
+ gamma->num_entries = lut_size;
+ __drm_lut_to_dc_gamma(lut, gamma, false);
+ }
if (func->tf == TRANSFER_FUNCTION_LINEAR) {
/*
@@ -285,32 +287,36 @@ static int __set_output_tf(struct dc_transfer_func *func,
* on top of a linear input. But degamma params can be used
* instead to simulate this.
*/
- gamma->type = GAMMA_CUSTOM;
+ if (gamma)
+ gamma->type = GAMMA_CUSTOM;
res = mod_color_calculate_degamma_params(NULL, func,
- gamma, true);
+gamma, gamma != NULL);
} else {
/*
* Assume sRGB. The actual mapping will depend on whether the
* input was legacy or not.
*/
- gamma->type = GAMMA_CS_TFM_1D;
- res = mod_color_calculate_regamma_params(func, gamma, false,
+ if (gamma)
+ gamma->type = GAMMA_CS_TFM_1D;
+ res = mod_color_calculate_regamma_params(func, gamma, gamma !=
NULL,
has_rom, NULL,
&cal_buffer);
}
- dc_gamma_release(&gamma);
+ if (gamma)
+ dc_gamma_release(&gamma);
return res ? 0 : -ENOMEM;
}
static int amdgpu_dm_set_atomic_regamma(struct dc_stream_state *stream,
const struct drm_color_lut *regamma_lut,
- uint32_t regamma_size, bool has_rom)
+ uint32_t regamma_size, bool has_rom,
+ enum dc_transfer_func_predefined tf)
{
struct dc_transfer_func *out_tf = stream->out_transfer_func;
int ret = 0;
- if (regamma_size) {
+ if (regamma_size || tf != TRANSFER_FUNCTION_LINEAR) {
/* CRTC RGM goes into RGM LUT.
*
* Note: there is no implicit sRGB regamma here. We are using
@@ -318,7 +324,7 @@ static int amdgpu_dm_set_atomic_regamma(struct
dc_stream_state *stream,
* from a linear base.
*/
out_tf->type = TF_TYPE_DISTRIBUTED_POINTS;
- out_tf->tf = TRANSFER_FUNCTION_LINEAR;
+ out_tf->tf = tf;
ret = __set_output_tf(out_tf, regamma_lut, regamma_size,
has_rom);
} else {
@@ -364,6 +370,24 @@ static int __set_input_tf(struct dc_transfer_func *func,
return res ? 0 : -ENOMEM;
}
+static enum dc_transfer_func_predefined drm_tf_to_dc_tf(enum
drm_transfer_function drm_tf)
+{
+ switch (drm_tf)
+ {
+ default:
+ case DRM_TRANSFER_FUNCTION_DEFAULT: return TRANSFER_FUNCTION_LINEAR;
+ case DRM_TRANSFER_FUNCTION_SRGB:return TRANSFER_FUNCTION_SRGB;
+ case DRM_TRANSFER_FUNCTION_BT709: return TRANSFER_FUNCTION_BT709;
+ case DRM_TRANSFER_FUNCTION_PQ: return TRANSFER_FUNCTION_PQ;
+ case DRM_TRANSFER_FUNCTION_LINEAR: return TRANSFER_FUNCTION_LINEAR;
+ case DRM_TRANSFER_FUNCTION_UNITY: return TRANSFER_FUNCTION_UNITY;
+ case DRM_TRANSFER_FUNCTION_HLG: return TRANSFER_FUNCTION_HLG;
+ case DRM_TRANSFER_FUNCTION_GAMMA22: return
TRANSFER_FUNCTION_GAMMA22;
+ case DRM_TRANSFER_FUNCTION_GAMMA24: return
TRANSFER_FUNCTION_GAMMA24;
+ case DRM_TRANSFER_FUNCTION_GAMMA26: return
TRANSFER_FUNCTION_GAM
[PATCH 20/36] drm/amd/display: dynamically acquire 3DLUT resources for color changes
From: Joshua Ashton
dc_acquire_release_mpc_3dlut_for_ctx initializes the bits required to
program 3DLUT in DC MPC hw block, applied in set_output_transfer_func().
Since acquire/release can fail, we should check resources availability
during atomic check considering the new context created. We dynamically
acquire 3D LUT resources when we actually use them, so we don't limit
ourselves with the stream count.
Signed-off-by: Joshua Ashton
Co-developed-by: Melissa Wen
Signed-off-by: Melissa Wen
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 7 ++-
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 3 +-
.../amd/display/amdgpu_dm/amdgpu_dm_color.c | 55 ++-
.../amd/display/dc/dcn301/dcn301_resource.c | 26 -
4 files changed, 87 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index fc5b9a25e22f..0be62fe436b0 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -9410,7 +9410,12 @@ static int dm_update_crtc_state(struct
amdgpu_display_manager *dm,
*/
if (dm_new_crtc_state->base.color_mgmt_changed ||
drm_atomic_crtc_needs_modeset(new_crtc_state)) {
- ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state);
+ if (!dm_state) {
+ ret = dm_atomic_get_state(state, &dm_state);
+ if (ret)
+ goto fail;
+ }
+ ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state,
dm_state->context);
if (ret)
goto fail;
}
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index ac430a23d3e1..e5f9db5a43f4 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -875,7 +875,8 @@ void amdgpu_dm_trigger_timing_sync(struct drm_device *dev);
void amdgpu_dm_init_color_mod(void);
int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state);
-int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc);
+int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc,
+struct dc_state *ctx);
int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc,
struct dc_plane_state *dc_plane_state);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
index fe03f1ec326e..161807e19886 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
@@ -364,6 +364,49 @@ static int __set_input_tf(struct dc_transfer_func *func,
return res ? 0 : -ENOMEM;
}
+/* amdgpu_dm_atomic_shaper_lut3d - set DRM CRTC shaper LUT and 3D LUT to DC
+ * interface
+ * @dc: Display Core control structure
+ * @ctx: new DC state information
+ * @stream: DC stream state to set shaper LUT and 3D LUT
+ * @drm_shaper_lut: DRM CRTC (user) shaper LUT
+ * @drm_shaper_size: size of shaper LUT
+ * @drm_lut3d: DRM CRTC (user) 3D LUT
+ * @drm_lut3d_size: size of 3D LUT
+ *
+ * Returns:
+ * 0 on success.
+ */
+static int amdgpu_dm_atomic_shaper_lut3d(struct dc *dc,
+struct dc_state *ctx,
+struct dc_stream_state *stream,
+const struct drm_color_lut
*drm_shaper_lut,
+uint32_t drm_shaper_size,
+const struct drm_color_lut *drm_lut3d,
+uint32_t drm_lut3d_size)
+{
+ struct dc_3dlut *lut3d_func;
+ struct dc_transfer_func *func_shaper;
+ bool acquire = drm_shaper_size || drm_lut3d_size;
+
+ lut3d_func = (struct dc_3dlut *)stream->lut3d_func;
+ func_shaper = (struct dc_transfer_func *)stream->func_shaper;
+
+ ASSERT((lut3d_func && func_shaper) || (!lut3d_func && !func_shaper));
+ if ((acquire && !lut3d_func && !func_shaper) ||
+ (!acquire && lut3d_func && func_shaper))
+ {
+ if (!dc_acquire_release_mpc_3dlut_for_ctx(dc, acquire, ctx,
stream,
+ &lut3d_func,
&func_shaper))
+ return DC_ERROR_UNEXPECTED;
+ }
+
+ stream->func_shaper = func_shaper;
+ stream->lut3d_func = lut3d_func;
+
+ return 0;
+}
+
/**
* amdgpu_dm_verify_lut_sizes - verifies if DRM luts match the hw supported
sizes
* @crtc_state: the DRM CRTC state
@@ -403,6 +446,7 @@ int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state
*crtc_state)
/**
* amdgpu_dm_update_crtc_color_mgmt: Maps DRM color management to DC stream.
* @crtc: amdgpu_dm
[PATCH 12/36] drm/amd/display: add plane shaper TF driver-private property
Add property to set predefined transfer function to enable delinearizing
content with or without shaper LUT. Drivers should advertize this
property acoording to HW caps.
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 9 +
drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 6 ++
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h| 6 ++
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 12
4 files changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index 258dfc66c2ac..d52bed00bbdb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -1318,6 +1318,15 @@ amdgpu_display_create_color_properties(struct
amdgpu_device *adev)
return -ENOMEM;
adev->mode_info.plane_shaper_lut_size_property = prop;
+ prop = drm_property_create_enum(adev_to_drm(adev),
+ DRM_MODE_PROP_ENUM,
+ "AMD_PLANE_SHAPER_TF",
+ drm_transfer_function_enum_list,
+
ARRAY_SIZE(drm_transfer_function_enum_list));
+ if (!prop)
+ return -ENOMEM;
+ adev->mode_info.plane_shaper_tf_property = prop;
+
prop = drm_property_create(adev_to_drm(adev),
DRM_MODE_PROP_BLOB,
"AMD_PLANE_LUT3D", 0);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
index 44306557a905..a41c3a39c367 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
@@ -379,6 +379,12 @@ struct amdgpu_mode_info {
* pre-blending shaper LUT as supported by the driver (read-only).
*/
struct drm_property *plane_shaper_lut_size_property;
+ /**
+* @plane_shaper_tf_property: Plane property to set a predefined
+* transfer function for pre-blending shaper (before applying 3D LUT)
+* with or without LUT.
+*/
+ struct drm_property *plane_shaper_tf_property;
/**
* @plane_lut3d_property: Plane property for gamma correction using a
* 3D LUT (pre-blending).
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index fa0bb6a5c598..663ffc7d648e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -749,6 +749,12 @@ struct dm_plane_state {
* array of &struct drm_color_lut.
*/
struct drm_property_blob *shaper_lut;
+ /**
+* @shaper_tf:
+*
+* Predefined transfer function to delinearize color space.
+*/
+ enum drm_transfer_function shaper_tf;
/**
* @lut3d: 3D lookup table blob. The blob (if not NULL) is an array of
* &struct drm_color_lut.
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
index abc5b9a353a0..61e47bdecde4 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
@@ -1323,6 +1323,7 @@ static void dm_drm_plane_reset(struct drm_plane *plane)
__drm_atomic_helper_plane_reset(plane, &amdgpu_state->base);
amdgpu_state->degamma_tf = DRM_TRANSFER_FUNCTION_DEFAULT;
amdgpu_state->hdr_mult = AMDGPU_HDR_MULT_DEFAULT;
+ amdgpu_state->shaper_tf = DRM_TRANSFER_FUNCTION_DEFAULT;
}
static struct drm_plane_state *
@@ -1351,6 +1352,7 @@ dm_drm_plane_duplicate_state(struct drm_plane *plane)
dm_plane_state->degamma_tf = old_dm_plane_state->degamma_tf;
dm_plane_state->hdr_mult = old_dm_plane_state->hdr_mult;
+ dm_plane_state->shaper_tf = old_dm_plane_state->shaper_tf;
return &dm_plane_state->base;
}
@@ -1471,6 +1473,9 @@ dm_atomic_plane_attach_color_mgmt_properties(struct
amdgpu_display_manager *dm,
drm_object_attach_property(&plane->base,
dm->adev->mode_info.plane_shaper_lut_size_property,
MAX_COLOR_LUT_ENTRIES);
+ drm_object_attach_property(&plane->base,
+
dm->adev->mode_info.plane_shaper_tf_property,
+ DRM_TRANSFER_FUNCTION_DEFAULT);
drm_object_attach_property(&plane->base,
dm->adev->mode_info.plane_lut3d_property, 0);
drm_object_attach_property(&plane->base,
@@ -1516,6 +1521,11 @@ dm_atomic_plane_set_property(struct drm_plane *plane,
&replaced);
dm_plane_state
[PATCH 19/36] drm/amd/display: handle MPC 3D LUT resources for a given context
In the original dc_acquire_release_mpc_3dlut(), only current ctx is
considered, which doesn't fit the steps for atomic checking new ctx.
Therefore, create a function to handle 3D LUT resource for a given
context, so that we can check resources availability in atomic_check
time and handle failures properly.
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 39
drivers/gpu/drm/amd/display/dc/dc.h | 8 +
2 files changed, 47 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 8e8da8c0f8cc..542a8fb26c24 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2129,6 +2129,45 @@ bool dc_acquire_release_mpc_3dlut(
return ret;
}
+bool
+dc_acquire_release_mpc_3dlut_for_ctx(struct dc *dc,
+bool acquire,
+struct dc_state *state,
+struct dc_stream_state *stream,
+struct dc_3dlut **lut,
+struct dc_transfer_func **shaper)
+{
+ int pipe_idx;
+ bool ret = false;
+ bool found_pipe_idx = false;
+ const struct resource_pool *pool = dc->res_pool;
+ struct resource_context *res_ctx = &state->res_ctx;
+ int mpcc_id = 0;
+
+ if (pool && res_ctx) {
+ if (acquire) {
+ /*find pipe idx for the given stream*/
+ for (pipe_idx = 0; pipe_idx < pool->pipe_count;
pipe_idx++) {
+ if (res_ctx->pipe_ctx[pipe_idx].stream ==
stream) {
+ found_pipe_idx = true;
+ mpcc_id =
res_ctx->pipe_ctx[pipe_idx].plane_res.hubp->inst;
+ break;
+ }
+ }
+ } else
+ found_pipe_idx = true;/*for release pipe_idx is not
required*/
+
+ if (found_pipe_idx) {
+ if (acquire && pool->funcs->acquire_post_bldn_3dlut)
+ ret =
pool->funcs->acquire_post_bldn_3dlut(res_ctx, pool, mpcc_id, lut, shaper);
+ else if (!acquire &&
pool->funcs->release_post_bldn_3dlut)
+ ret =
pool->funcs->release_post_bldn_3dlut(res_ctx, pool, lut, shaper);
+ }
+ }
+ return ret;
+}
+
+
static bool is_flip_pending_in_pipes(struct dc *dc, struct dc_state *context)
{
int i;
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 2dff1a5cf3b1..b307d95f5dd4 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -1365,6 +1365,14 @@ bool dc_acquire_release_mpc_3dlut(
struct dc_3dlut **lut,
struct dc_transfer_func **shaper);
+bool
+dc_acquire_release_mpc_3dlut_for_ctx(struct dc *dc,
+bool acquire,
+struct dc_state *state,
+struct dc_stream_state *stream,
+struct dc_3dlut **lut,
+struct dc_transfer_func **shaper);
+
void dc_resource_state_copy_construct(
const struct dc_state *src_ctx,
struct dc_state *dst_ctx);
--
2.39.2
[PATCH 07/36] drm/amd/display: add plane driver-specific properties for degamma LUT
Create and attach driver-private properties for plane color management.
First add plane degamma LUT properties that means user-blob and its
size. We will add more plane color properties in the next commits. In
addition, we keep these driver-private plane properties limited by
defining AMD_PRIVATE_COLOR.
Co-developed-by: Joshua Ashton
Signed-off-by: Joshua Ashton
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 14
drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 8 ++
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 9 +++
.../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 77 +++
4 files changed, 108 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index 88af075e6c18..fa67c84f5994 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -1275,6 +1275,20 @@ amdgpu_display_create_color_properties(struct
amdgpu_device *adev)
return -ENOMEM;
adev->mode_info.regamma_tf_property = prop;
+ prop = drm_property_create(adev_to_drm(adev),
+ DRM_MODE_PROP_BLOB,
+ "AMD_PLANE_DEGAMMA_LUT", 0);
+ if (!prop)
+ return -ENOMEM;
+ adev->mode_info.plane_degamma_lut_property = prop;
+
+ prop = drm_property_create_range(adev_to_drm(adev),
+DRM_MODE_PROP_IMMUTABLE,
+"AMD_PLANE_DEGAMMA_LUT_SIZE", 0,
UINT_MAX);
+ if (!prop)
+ return -ENOMEM;
+ adev->mode_info.plane_degamma_lut_size_property = prop;
+
return 0;
}
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
index 881446c51b36..6c165ad9bdf0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
@@ -352,6 +352,14 @@ struct amdgpu_mode_info {
* drm_transfer_function`.
*/
struct drm_property *regamma_tf_property;
+ /* @plane_degamma_lut_property: Plane property to set a degamma LUT to
+* convert color space before blending.
+*/
+ struct drm_property *plane_degamma_lut_property;
+ /* @plane_degamma_lut_size_property: Plane property to define the max
+* size of degamma LUT as supported by the driver (read-only).
+*/
+ struct drm_property *plane_degamma_lut_size_property;
};
#define AMDGPU_MAX_BL_LEVEL 0xFF
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index ad5ee28b83dc..22e126654767 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -716,6 +716,15 @@ enum drm_transfer_function {
struct dm_plane_state {
struct drm_plane_state base;
struct dc_plane_state *dc_state;
+
+ /* Plane color mgmt */
+ /**
+* @degamma_lut:
+*
+* LUT for converting plane pixel data before going into plane merger.
+* The blob (if not NULL) is an array of &struct drm_color_lut.
+*/
+ struct drm_property_blob *degamma_lut;
};
struct dm_crtc_state {
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
index 322668973747..e9cedc4068f1 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
@@ -1338,6 +1338,9 @@ dm_drm_plane_duplicate_state(struct drm_plane *plane)
dc_plane_state_retain(dm_plane_state->dc_state);
}
+ if (dm_plane_state->degamma_lut)
+ drm_property_blob_get(dm_plane_state->degamma_lut);
+
return &dm_plane_state->base;
}
@@ -1405,12 +1408,79 @@ static void dm_drm_plane_destroy_state(struct drm_plane
*plane,
{
struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
+ if (dm_plane_state->degamma_lut)
+ drm_property_blob_put(dm_plane_state->degamma_lut);
+
if (dm_plane_state->dc_state)
dc_plane_state_release(dm_plane_state->dc_state);
drm_atomic_helper_plane_destroy_state(plane, state);
}
+#ifdef AMD_PRIVATE_COLOR
+static void
+dm_atomic_plane_attach_color_mgmt_properties(struct amdgpu_display_manager *dm,
+struct drm_plane *plane)
+{
+ if (dm->dc->caps.color.dpp.dgam_ram ||
dm->dc->caps.color.dpp.gamma_corr ) {
+ drm_object_attach_property(&plane->base,
+
dm->adev->mode_info.plane_degamma_lut_property, 0);
+ drm_object_attach_property(&plane->base,
+
dm->adev->mode_info.plane_degamma_lut_size_property,
+ MA
[PATCH 18/36] drm/amd/display: allow BYPASS 3D LUT but keep shaper LUT settings
HW allows us to program shaper LUT without 3D LUT settings and it is
also good for testing shaper LUT behavior, therefore, DC driver should
allow acquiring both 3D and shaper LUT, but programing shaper LUT
without 3D LUT (not initialized).
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
index 3303c9aae068..bacb0a001d68 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
@@ -113,7 +113,6 @@ static bool dcn30_set_mpc_shaper_3dlut(struct pipe_ctx
*pipe_ctx,
}
if (stream->lut3d_func &&
- stream->lut3d_func->state.bits.initialized == 1 &&
stream->lut3d_func->state.bits.rmu_idx_valid == 1) {
if (stream->lut3d_func->state.bits.rmu_mux_num == 0)
mpcc_id_projected =
stream->lut3d_func->state.bits.mpc_rmu0_mux;
@@ -131,8 +130,12 @@ static bool dcn30_set_mpc_shaper_3dlut(struct pipe_ctx
*pipe_ctx,
if (acquired_rmu != stream->lut3d_func->state.bits.rmu_mux_num)
BREAK_TO_DEBUGGER();
- result = mpc->funcs->program_3dlut(mpc,
&stream->lut3d_func->lut_3d,
-
stream->lut3d_func->state.bits.rmu_mux_num);
+ if (stream->lut3d_func->state.bits.initialized == 1)
+ result = mpc->funcs->program_3dlut(mpc,
&stream->lut3d_func->lut_3d,
+
stream->lut3d_func->state.bits.rmu_mux_num);
+ else
+ result = mpc->funcs->program_3dlut(mpc, NULL,
+
stream->lut3d_func->state.bits.rmu_mux_num);
result = mpc->funcs->program_shaper(mpc, shaper_lut,
stream->lut3d_func->state.bits.rmu_mux_num);
} else {
--
2.39.2
[PATCH 17/36] drm/amd/display: copy 3D LUT settings from crtc state to stream_update
From: Joshua Ashton When commiting planes, we copy color mgmt resources to the stream state. Do the same for shaper and 3D LUTs. Co-developed-by: Melissa Wen Signed-off-by: Melissa Wen Signed-off-by: Joshua Ashton --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 14b296e1d0f6..fc5b9a25e22f 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8220,6 +8220,10 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, &acrtc_state->stream->csc_color_matrix; bundle->stream_update.out_transfer_func = acrtc_state->stream->out_transfer_func; + bundle->stream_update.lut3d_func = + (struct dc_3dlut *) acrtc_state->stream->lut3d_func; + bundle->stream_update.func_shaper = + (struct dc_transfer_func *) acrtc_state->stream->func_shaper; } acrtc_state->stream->abm_level = acrtc_state->abm_level; -- 2.39.2
[PATCH 15/36] drm/amd/display: encapsulate atomic regamma operation
We will wire up MPC 3D LUT to DM CRTC color pipeline in the next patch,
but so far, only for atomic interface. By checking
set_output_transfer_func in DC drivers with MPC 3D LUT support, we can
verify that regamma is only programmed when 3D LUT programming fails. As
a groundwork to introduce 3D LUT programming and better understand each
step, detach atomic regamma programming from the crtc colocr updating
code.
Signed-off-by: Melissa Wen
---
.../amd/display/amdgpu_dm/amdgpu_dm_color.c | 53 ---
1 file changed, 34 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
index fe779d10834e..fe03f1ec326e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
@@ -303,6 +303,36 @@ static int __set_output_tf(struct dc_transfer_func *func,
return res ? 0 : -ENOMEM;
}
+static int amdgpu_dm_set_atomic_regamma(struct dc_stream_state *stream,
+ const struct drm_color_lut *regamma_lut,
+ uint32_t regamma_size, bool has_rom)
+{
+ struct dc_transfer_func *out_tf = stream->out_transfer_func;
+ int ret = 0;
+
+ if (regamma_size) {
+ /* CRTC RGM goes into RGM LUT.
+*
+* Note: there is no implicit sRGB regamma here. We are using
+* degamma calculation from color module to calculate the curve
+* from a linear base.
+*/
+ out_tf->type = TF_TYPE_DISTRIBUTED_POINTS;
+ out_tf->tf = TRANSFER_FUNCTION_LINEAR;
+
+ ret = __set_output_tf(out_tf, regamma_lut, regamma_size,
has_rom);
+ } else {
+ /*
+* No CRTC RGM means we can just put the block into bypass
+* since we don't have any plane level adjustments using it.
+*/
+ out_tf->type = TF_TYPE_BYPASS;
+ out_tf->tf = TRANSFER_FUNCTION_LINEAR;
+ }
+
+ return ret;
+}
+
/**
* __set_input_tf - calculates the input transfer function based on expected
* input space.
@@ -450,27 +480,12 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state
*crtc)
regamma_size, has_rom);
if (r)
return r;
- } else if (has_regamma) {
- /* CRTC RGM goes into RGM LUT.
-*
-* Note: there is no implicit sRGB regamma here. We are using
-* degamma calculation from color module to calculate the curve
-* from a linear base.
-*/
- stream->out_transfer_func->type = TF_TYPE_DISTRIBUTED_POINTS;
- stream->out_transfer_func->tf = TRANSFER_FUNCTION_LINEAR;
-
- r = __set_output_tf(stream->out_transfer_func, regamma_lut,
- regamma_size, has_rom);
+ } else {
+ regamma_size = has_regamma ? regamma_size : 0;
+ r = amdgpu_dm_set_atomic_regamma(stream, regamma_lut,
+regamma_size, has_rom);
if (r)
return r;
- } else {
- /*
-* No CRTC RGM means we can just put the block into bypass
-* since we don't have any plane level adjustments using it.
-*/
- stream->out_transfer_func->type = TF_TYPE_BYPASS;
- stream->out_transfer_func->tf = TRANSFER_FUNCTION_LINEAR;
}
/*
--
2.39.2
[PATCH 08/36] drm/amd/display: add plane degamma TF driver-specific property
From: Joshua Ashton
Allow userspace to tell the kernel driver the input space and,
therefore, uses correct predefined transfer function (TF) to delinearize
content with or without LUT.
Signed-off-by: Joshua Ashton
Co-developed-by: Melissa Wen
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 9 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 5 +++
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 7
.../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 32 +--
4 files changed, 51 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index fa67c84f5994..fd6c4078c53a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -1289,6 +1289,15 @@ amdgpu_display_create_color_properties(struct
amdgpu_device *adev)
return -ENOMEM;
adev->mode_info.plane_degamma_lut_size_property = prop;
+ prop = drm_property_create_enum(adev_to_drm(adev),
+ DRM_MODE_PROP_ENUM,
+ "AMD_PLANE_DEGAMMA_TF",
+ drm_transfer_function_enum_list,
+
ARRAY_SIZE(drm_transfer_function_enum_list));
+ if (!prop)
+ return -ENOMEM;
+ adev->mode_info.plane_degamma_tf_property = prop;
+
return 0;
}
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
index 6c165ad9bdf0..9d7f47fe6303 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
@@ -360,6 +360,11 @@ struct amdgpu_mode_info {
* size of degamma LUT as supported by the driver (read-only).
*/
struct drm_property *plane_degamma_lut_size_property;
+ /**
+* @plane_degamma_tf_property: Predefined transfer function to
+* linearize content with or without LUT.
+*/
+ struct drm_property *plane_degamma_tf_property;
};
#define AMDGPU_MAX_BL_LEVEL 0xFF
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index 22e126654767..b8e432cc8078 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -725,6 +725,13 @@ struct dm_plane_state {
* The blob (if not NULL) is an array of &struct drm_color_lut.
*/
struct drm_property_blob *degamma_lut;
+ /**
+* @degamma_tf:
+*
+* Predefined transfer function to tell DC driver the input space to
+* linearize.
+*/
+ enum drm_transfer_function degamma_tf;
};
struct dm_crtc_state {
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
index e9cedc4068f1..6b71777a525c 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
@@ -1317,8 +1317,11 @@ static void dm_drm_plane_reset(struct drm_plane *plane)
amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);
WARN_ON(amdgpu_state == NULL);
- if (amdgpu_state)
- __drm_atomic_helper_plane_reset(plane, &amdgpu_state->base);
+ if (!amdgpu_state)
+ return;
+
+ __drm_atomic_helper_plane_reset(plane, &amdgpu_state->base);
+ amdgpu_state->degamma_tf = DRM_TRANSFER_FUNCTION_DEFAULT;
}
static struct drm_plane_state *
@@ -1341,6 +1344,8 @@ dm_drm_plane_duplicate_state(struct drm_plane *plane)
if (dm_plane_state->degamma_lut)
drm_property_blob_get(dm_plane_state->degamma_lut);
+ dm_plane_state->degamma_tf = old_dm_plane_state->degamma_tf;
+
return &dm_plane_state->base;
}
@@ -1417,6 +1422,19 @@ static void dm_drm_plane_destroy_state(struct drm_plane
*plane,
drm_atomic_helper_plane_destroy_state(plane, state);
}
+static const struct drm_prop_enum_list drm_transfer_function_enum_list[] = {
+ { DRM_TRANSFER_FUNCTION_DEFAULT, "Default" },
+ { DRM_TRANSFER_FUNCTION_SRGB, "sRGB" },
+ { DRM_TRANSFER_FUNCTION_BT709, "BT.709" },
+ { DRM_TRANSFER_FUNCTION_PQ, "PQ (Perceptual Quantizer)" },
+ { DRM_TRANSFER_FUNCTION_LINEAR, "Linear" },
+ { DRM_TRANSFER_FUNCTION_UNITY, "Unity" },
+ { DRM_TRANSFER_FUNCTION_HLG, "HLG (Hybrid Log Gamma)" },
+ { DRM_TRANSFER_FUNCTION_GAMMA22, "Gamma 2.2" },
+ { DRM_TRANSFER_FUNCTION_GAMMA24, "Gamma 2.4" },
+ { DRM_TRANSFER_FUNCTION_GAMMA26, "Gamma 2.6" },
+};
+
#ifdef AMD_PRIVATE_COLOR
static void
dm_atomic_plane_attach_color_mgmt_properties(struct amdgpu_display_manager *dm,
@@ -1428,6 +1446,9 @@ dm_atomic_plane_attach_color_mgmt_properties(struct
amdgpu_display_manager *dm,
drm_object_attach_prop
[PATCH 13/36] drm/amd/display: add plane blend LUT and TF driver-specific properties
From: Joshua Ashton
Blend 1D LUT or a predefined transfer function can be set to linearize
content before blending, so that it's positioned just before blending
planes in the AMD color mgmt pipeline, and after 3D LUT (non-linear
space). Shaper and Blend LUTs are 1D LUTs that sandwich 3D LUT. Drivers
should advertize blend properties according to HW caps.
Signed-off-by: Joshua Ashton
Co-developed-by: Melissa Wen
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 23
drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 18 ++
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 12 +++
.../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 36 +++
4 files changed, 89 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index d52bed00bbdb..193e453beedf 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -1341,6 +1341,29 @@ amdgpu_display_create_color_properties(struct
amdgpu_device *adev)
return -ENOMEM;
adev->mode_info.plane_lut3d_size_property = prop;
+ prop = drm_property_create(adev_to_drm(adev),
+ DRM_MODE_PROP_BLOB,
+ "AMD_PLANE_BLEND_LUT", 0);
+ if (!prop)
+ return -ENOMEM;
+ adev->mode_info.plane_blend_lut_property = prop;
+
+ prop = drm_property_create_range(adev_to_drm(adev),
+DRM_MODE_PROP_IMMUTABLE,
+"AMD_PLANE_BLEND_LUT_SIZE", 0,
UINT_MAX);
+ if (!prop)
+ return -ENOMEM;
+ adev->mode_info.plane_blend_lut_size_property = prop;
+
+ prop = drm_property_create_enum(adev_to_drm(adev),
+ DRM_MODE_PROP_ENUM,
+ "AMD_PLANE_BLEND_TF",
+ drm_transfer_function_enum_list,
+
ARRAY_SIZE(drm_transfer_function_enum_list));
+ if (!prop)
+ return -ENOMEM;
+ adev->mode_info.plane_blend_tf_property = prop;
+
return 0;
}
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
index a41c3a39c367..69dd1ae068c5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
@@ -395,6 +395,24 @@ struct amdgpu_mode_info {
* size of 3D LUT as supported by the driver (read-only).
*/
struct drm_property *plane_lut3d_size_property;
+ /**
+* @plane_blend_lut_property: Plane property for output gamma before
+* blending. Userspace set a blend LUT to convert colors after 3D LUT
+* conversion. It works as a post-3D LUT 1D LUT, with shaper LUT, they
+* are sandwiching 3D LUT with two 1D LUT.
+*/
+ struct drm_property *plane_blend_lut_property;
+ /**
+* @plane_blend_lut_size_property: Plane property to define the max
+* size of blend LUT as supported by the driver (read-only).
+*/
+ struct drm_property *plane_blend_lut_size_property;
+ /**
+* @plane_blend_tf_property: Plane property to set a predefined
+* transfer function for pre-blending blend (before applying 3D LUT)
+* with or without LUT.
+*/
+ struct drm_property *plane_blend_tf_property;
};
#define AMDGPU_MAX_BL_LEVEL 0xFF
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index 663ffc7d648e..ac430a23d3e1 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -760,6 +760,18 @@ struct dm_plane_state {
* &struct drm_color_lut.
*/
struct drm_property_blob *lut3d;
+ /**
+* @blend_lut: blend lut lookup table blob. The blob (if not NULL) is an
+* array of &struct drm_color_lut.
+*/
+ struct drm_property_blob *blend_lut;
+ /**
+* @blend_tf:
+*
+* Pre-defined transfer function for converting plane pixel data before
+* applying blend LUT.
+*/
+ enum drm_transfer_function blend_tf;
};
struct dm_crtc_state {
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
index 61e47bdecde4..ea13b49fa021 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
@@ -1324,6 +1324,7 @@ static void dm_drm_plane_reset(struct drm_plane *plane)
amdgpu_state->degamma_tf = DRM_TRANSFER_FUNCTION_DEFAULT;
amdgpu_state->hdr_mult = AMDGPU_HDR_MULT_DEFAULT;
amdgpu_state->shaper_tf = DRM_TRANSFER_FUNCTION_DEFAULT;
+ amdgpu_state->blend_tf = DRM_TR
[PATCH 14/36] drm/amd/display: add comments to describe DM crtc color mgmt behavior
Describe some expected behavior of the AMD DM color mgmt programming.
Signed-off-by: Melissa Wen
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
index a4cb23d059bd..fe779d10834e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
@@ -440,12 +440,23 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state
*crtc)
stream->out_transfer_func->type = TF_TYPE_DISTRIBUTED_POINTS;
stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
+ /* Note: although we pass has_rom as parameter here, we never
+* actually use ROM because the color module only takes the ROM
+* path if transfer_func->type == PREDEFINED.
+*
+* See more in mod_color_calculate_regamma_params()
+*/
r = __set_legacy_tf(stream->out_transfer_func, regamma_lut,
regamma_size, has_rom);
if (r)
return r;
} else if (has_regamma) {
- /* If atomic regamma, CRTC RGM goes into RGM LUT. */
+ /* CRTC RGM goes into RGM LUT.
+*
+* Note: there is no implicit sRGB regamma here. We are using
+* degamma calculation from color module to calculate the curve
+* from a linear base.
+*/
stream->out_transfer_func->type = TF_TYPE_DISTRIBUTED_POINTS;
stream->out_transfer_func->tf = TRANSFER_FUNCTION_LINEAR;
--
2.39.2
[PATCH 09/36] drm/amd/display: add plane HDR multiplier driver-specific property
From: Joshua Ashton
Multiplier to 'gain' the plane. When PQ is decoded using the fixed func
transfer function to the internal FP16 fb, 1.0 -> 80 nits (on AMD at
least) When sRGB is decoded, 1.0 -> 1.0. Therefore, 1.0 multiplier = 80
nits for SDR content. So if you want, 203 nits for SDR content, pass in
(203.0 / 80.0).
Signed-off-by: Joshua Ashton
Co-developed-by: Melissa Wen
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 6 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h| 4
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 12
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 13 +
4 files changed, 35 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index fd6c4078c53a..f0e12cca295d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -1298,6 +1298,12 @@ amdgpu_display_create_color_properties(struct
amdgpu_device *adev)
return -ENOMEM;
adev->mode_info.plane_degamma_tf_property = prop;
+ prop = drm_property_create_range(adev_to_drm(adev),
+0, "AMD_PLANE_HDR_MULT", 0, U64_MAX);
+ if (!prop)
+ return -ENOMEM;
+ adev->mode_info.plane_hdr_mult_property = prop;
+
return 0;
}
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
index 9d7f47fe6303..c105f51b7b6d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
@@ -365,6 +365,10 @@ struct amdgpu_mode_info {
* linearize content with or without LUT.
*/
struct drm_property *plane_degamma_tf_property;
+ /**
+* @plane_hdr_mult_property:
+*/
+ struct drm_property *plane_hdr_mult_property;
};
#define AMDGPU_MAX_BL_LEVEL 0xFF
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index b8e432cc8078..dadbef561606 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -51,6 +51,7 @@
#define AMDGPU_DMUB_NOTIFICATION_MAX 5
+#define AMDGPU_HDR_MULT_DEFAULT (0x1LL)
/*
#include "include/amdgpu_dal_power_if.h"
#include "amdgpu_dm_irq.h"
@@ -732,6 +733,17 @@ struct dm_plane_state {
* linearize.
*/
enum drm_transfer_function degamma_tf;
+ /**
+* @hdr_mult:
+*
+* Multiplier to 'gain' the plane. When PQ is decoded using the fixed
+* func transfer function to the internal FP16 fb, 1.0 -> 80 nits (on
+* AMD at least). When sRGB is decoded, 1.0 -> 1.0, obviously.
+* Therefore, 1.0 multiplier = 80 nits for SDR content. So if you
+* want, 203 nits for SDR content, pass in (203.0 / 80.0). Format is
+* S31.32 sign-magnitude.
+*/
+ __u64 hdr_mult;
};
struct dm_crtc_state {
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
index 6b71777a525c..bbbf25dd2515 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
@@ -1322,6 +1322,7 @@ static void dm_drm_plane_reset(struct drm_plane *plane)
__drm_atomic_helper_plane_reset(plane, &amdgpu_state->base);
amdgpu_state->degamma_tf = DRM_TRANSFER_FUNCTION_DEFAULT;
+ amdgpu_state->hdr_mult = AMDGPU_HDR_MULT_DEFAULT;
}
static struct drm_plane_state *
@@ -1345,6 +1346,7 @@ dm_drm_plane_duplicate_state(struct drm_plane *plane)
drm_property_blob_get(dm_plane_state->degamma_lut);
dm_plane_state->degamma_tf = old_dm_plane_state->degamma_tf;
+ dm_plane_state->hdr_mult = old_dm_plane_state->hdr_mult;
return &dm_plane_state->base;
}
@@ -1450,6 +1452,10 @@ dm_atomic_plane_attach_color_mgmt_properties(struct
amdgpu_display_manager *dm,
dm->adev->mode_info.plane_degamma_tf_property,
DRM_TRANSFER_FUNCTION_DEFAULT);
}
+ /* HDR MULT is always available */
+ drm_object_attach_property(&plane->base,
+ dm->adev->mode_info.plane_hdr_mult_property,
+ AMDGPU_HDR_MULT_DEFAULT);
}
static int
@@ -1476,6 +1482,11 @@ dm_atomic_plane_set_property(struct drm_plane *plane,
dm_plane_state->degamma_tf = val;
dm_plane_state->base.color_mgmt_changed = 1;
}
+ } else if (property == adev->mode_info.plane_hdr_mult_property) {
+ if (dm_plane_state->hdr_mult != val) {
+ dm_plane_state->hdr_mult = val;
+ dm_plane_state->base.color_
[PATCH 11/36] drm/amd/display: add plane shaper LUT driver-specific properties
On AMD HW, 3D LUT always assumes a preceding shaper 1D LUT used for
delinearizing and/or normalizing the color space before applying a 3D
LUT.
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 14 +
drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 10 ++
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 5 +
.../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 20 +++
4 files changed, 49 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index 9954643cb928..258dfc66c2ac 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -1304,6 +1304,20 @@ amdgpu_display_create_color_properties(struct
amdgpu_device *adev)
return -ENOMEM;
adev->mode_info.plane_hdr_mult_property = prop;
+ prop = drm_property_create(adev_to_drm(adev),
+ DRM_MODE_PROP_BLOB,
+ "AMD_PLANE_SHAPER_LUT", 0);
+ if (!prop)
+ return -ENOMEM;
+ adev->mode_info.plane_shaper_lut_property = prop;
+
+ prop = drm_property_create_range(adev_to_drm(adev),
+DRM_MODE_PROP_IMMUTABLE,
+"AMD_PLANE_SHAPER_LUT_SIZE", 0,
UINT_MAX);
+ if (!prop)
+ return -ENOMEM;
+ adev->mode_info.plane_shaper_lut_size_property = prop;
+
prop = drm_property_create(adev_to_drm(adev),
DRM_MODE_PROP_BLOB,
"AMD_PLANE_LUT3D", 0);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
index 93ec4a60f6e9..44306557a905 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
@@ -369,6 +369,16 @@ struct amdgpu_mode_info {
* @plane_hdr_mult_property:
*/
struct drm_property *plane_hdr_mult_property;
+ /**
+* @shaper_lut_property: Plane property to set pre-blending shaper LUT
+* that converts color content before 3D LUT.
+*/
+ struct drm_property *plane_shaper_lut_property;
+ /**
+* @shaper_lut_size_property: Plane property for the size of
+* pre-blending shaper LUT as supported by the driver (read-only).
+*/
+ struct drm_property *plane_shaper_lut_size_property;
/**
* @plane_lut3d_property: Plane property for gamma correction using a
* 3D LUT (pre-blending).
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index 7e4978c2f253..fa0bb6a5c598 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -744,6 +744,11 @@ struct dm_plane_state {
* S31.32 sign-magnitude.
*/
__u64 hdr_mult;
+ /**
+* @shaper_lut: shaper lookup table blob. The blob (if not NULL) is an
+* array of &struct drm_color_lut.
+*/
+ struct drm_property_blob *shaper_lut;
/**
* @lut3d: 3D lookup table blob. The blob (if not NULL) is an array of
* &struct drm_color_lut.
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
index 5fc3855448d0..abc5b9a353a0 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
@@ -1344,6 +1344,8 @@ dm_drm_plane_duplicate_state(struct drm_plane *plane)
if (dm_plane_state->degamma_lut)
drm_property_blob_get(dm_plane_state->degamma_lut);
+ if (dm_plane_state->shaper_lut)
+ drm_property_blob_get(dm_plane_state->shaper_lut);
if (dm_plane_state->lut3d)
drm_property_blob_get(dm_plane_state->lut3d);
@@ -1421,6 +1423,8 @@ static void dm_drm_plane_destroy_state(struct drm_plane
*plane,
drm_property_blob_put(dm_plane_state->degamma_lut);
if (dm_plane_state->lut3d)
drm_property_blob_put(dm_plane_state->lut3d);
+ if (dm_plane_state->shaper_lut)
+ drm_property_blob_put(dm_plane_state->shaper_lut);
if (dm_plane_state->dc_state)
dc_plane_state_release(dm_plane_state->dc_state);
@@ -1462,6 +1466,11 @@ dm_atomic_plane_attach_color_mgmt_properties(struct
amdgpu_display_manager *dm,
AMDGPU_HDR_MULT_DEFAULT);
if (dm->dc->caps.color.dpp.hw_3d_lut) {
+ drm_object_attach_property(&plane->base,
+
dm->adev->mode_info.plane_shaper_lut_property, 0);
+ drm_object_attach_property(&plane->base,
+
dm->adev->mode_info.plane_shaper_lut_size_property,
+
[PATCH 10/36] drm/amd/display: add plane 3D LUT driver-specific properties
Add 3D LUT property for plane gamma correction using a 3D lookup table.
Since a 3D LUT has a limited number of entries in each dimension we want
to use them in an optimal fashion. This means using the 3D LUT in a
colorspace that is optimized for human vision, such as sRGB, PQ, or
another non-linear space. Therefore, userpace may need one 1D LUT
(shaper) before it to delinearize content and another 1D LUT after 3D
LUT (blend) to linearize content again for blending. The next patches
add these 1D LUTs to the plane color mgmt pipeline.
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 14 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 10
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 9
.../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 23 +++
4 files changed, 56 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index f0e12cca295d..9954643cb928 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -1304,6 +1304,20 @@ amdgpu_display_create_color_properties(struct
amdgpu_device *adev)
return -ENOMEM;
adev->mode_info.plane_hdr_mult_property = prop;
+ prop = drm_property_create(adev_to_drm(adev),
+ DRM_MODE_PROP_BLOB,
+ "AMD_PLANE_LUT3D", 0);
+ if (!prop)
+ return -ENOMEM;
+ adev->mode_info.plane_lut3d_property = prop;
+
+ prop = drm_property_create_range(adev_to_drm(adev),
+DRM_MODE_PROP_IMMUTABLE,
+"AMD_PLANE_LUT3D_SIZE", 0, UINT_MAX);
+ if (!prop)
+ return -ENOMEM;
+ adev->mode_info.plane_lut3d_size_property = prop;
+
return 0;
}
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
index c105f51b7b6d..93ec4a60f6e9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
@@ -369,6 +369,16 @@ struct amdgpu_mode_info {
* @plane_hdr_mult_property:
*/
struct drm_property *plane_hdr_mult_property;
+ /**
+* @plane_lut3d_property: Plane property for gamma correction using a
+* 3D LUT (pre-blending).
+*/
+ struct drm_property *plane_lut3d_property;
+ /**
+* @plane_degamma_lut_size_property: Plane property to define the max
+* size of 3D LUT as supported by the driver (read-only).
+*/
+ struct drm_property *plane_lut3d_size_property;
};
#define AMDGPU_MAX_BL_LEVEL 0xFF
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index dadbef561606..7e4978c2f253 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -744,6 +744,11 @@ struct dm_plane_state {
* S31.32 sign-magnitude.
*/
__u64 hdr_mult;
+ /**
+* @lut3d: 3D lookup table blob. The blob (if not NULL) is an array of
+* &struct drm_color_lut.
+*/
+ struct drm_property_blob *lut3d;
};
struct dm_crtc_state {
@@ -837,6 +842,10 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector
*connector,
void amdgpu_dm_trigger_timing_sync(struct drm_device *dev);
+/* 3D LUT max size is 17x17x17 */
+#define MAX_COLOR_3DLUT_ENTRIES 4913
+#define MAX_COLOR_3DLUT_BITDEPTH 12
+/* 1D LUT size */
#define MAX_COLOR_LUT_ENTRIES 4096
/* Legacy gamm LUT users such as X doesn't like large LUT sizes */
#define MAX_COLOR_LEGACY_LUT_ENTRIES 256
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
index bbbf25dd2515..5fc3855448d0 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
@@ -1344,6 +1344,8 @@ dm_drm_plane_duplicate_state(struct drm_plane *plane)
if (dm_plane_state->degamma_lut)
drm_property_blob_get(dm_plane_state->degamma_lut);
+ if (dm_plane_state->lut3d)
+ drm_property_blob_get(dm_plane_state->lut3d);
dm_plane_state->degamma_tf = old_dm_plane_state->degamma_tf;
dm_plane_state->hdr_mult = old_dm_plane_state->hdr_mult;
@@ -1417,6 +1419,8 @@ static void dm_drm_plane_destroy_state(struct drm_plane
*plane,
if (dm_plane_state->degamma_lut)
drm_property_blob_put(dm_plane_state->degamma_lut);
+ if (dm_plane_state->lut3d)
+ drm_property_blob_put(dm_plane_state->lut3d);
if (dm_plane_state->dc_state)
dc_plane_state_release(dm_plane_state->dc_state);
@@ -1456,6 +1460,14 @@ dm_atomic_plane_attach_color_mgmt_properties(struct
amdgpu_display_manager *dm,
drm_object
[PATCH 06/36] drm/amd/display: add CRTC driver-specific property for gamma TF
Hook up driver-specific atomic operations for managing AMD color
properties and create AMD driver-specific color management properties
and attach them according to HW capabilities defined by `struct
dc_color_caps`. Add enumerated transfer function property to DRM CRTC
gamma to convert to wire encoding with or without a user gamma LUT.
Enumerated TFs are not supported yet by the DRM color pipeline,
therefore, create a DRM enum list with the predefined TFs supported by
the AMD display driver.
Co-developed-by: Joshua Ashton
Signed-off-by: Joshua Ashton
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 36 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 8 +++
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 22 ++
.../amd/display/amdgpu_dm/amdgpu_dm_crtc.c| 72 ++-
4 files changed, 137 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index 389396eac222..88af075e6c18 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -1247,6 +1247,38 @@ amdgpu_display_user_framebuffer_create(struct drm_device
*dev,
return &amdgpu_fb->base;
}
+static const struct drm_prop_enum_list drm_transfer_function_enum_list[] = {
+ { DRM_TRANSFER_FUNCTION_DEFAULT, "Default" },
+ { DRM_TRANSFER_FUNCTION_SRGB, "sRGB" },
+ { DRM_TRANSFER_FUNCTION_BT709, "BT.709" },
+ { DRM_TRANSFER_FUNCTION_PQ, "PQ (Perceptual Quantizer)" },
+ { DRM_TRANSFER_FUNCTION_LINEAR, "Linear" },
+ { DRM_TRANSFER_FUNCTION_UNITY, "Unity" },
+ { DRM_TRANSFER_FUNCTION_HLG, "HLG (Hybrid Log Gamma)" },
+ { DRM_TRANSFER_FUNCTION_GAMMA22, "Gamma 2.2" },
+ { DRM_TRANSFER_FUNCTION_GAMMA24, "Gamma 2.4" },
+ { DRM_TRANSFER_FUNCTION_GAMMA26, "Gamma 2.6" },
+};
+
+#ifdef AMD_PRIVATE_COLOR
+static int
+amdgpu_display_create_color_properties(struct amdgpu_device *adev)
+{
+ struct drm_property *prop;
+
+ prop = drm_property_create_enum(adev_to_drm(adev),
+ DRM_MODE_PROP_ENUM,
+ "AMD_REGAMMA_TF",
+ drm_transfer_function_enum_list,
+
ARRAY_SIZE(drm_transfer_function_enum_list));
+ if (!prop)
+ return -ENOMEM;
+ adev->mode_info.regamma_tf_property = prop;
+
+ return 0;
+}
+#endif
+
const struct drm_mode_config_funcs amdgpu_mode_funcs = {
.fb_create = amdgpu_display_user_framebuffer_create,
};
@@ -1323,6 +1355,10 @@ int amdgpu_display_modeset_create_props(struct
amdgpu_device *adev)
return -ENOMEM;
}
+#ifdef AMD_PRIVATE_COLOR
+ if (amdgpu_display_create_color_properties(adev))
+ return -ENOMEM;
+#endif
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
index b8633df418d4..881446c51b36 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
@@ -344,6 +344,14 @@ struct amdgpu_mode_info {
int disp_priority;
const struct amdgpu_display_funcs *funcs;
const enum drm_plane_type *plane_type;
+
+ /* Driver-private color mgmt props */
+
+ /* @regamma_tf_property: Transfer function for CRTC regamma
+* (post-blending). Possible values are defined by `enum
+* drm_transfer_function`.
+*/
+ struct drm_property *regamma_tf_property;
};
#define AMDGPU_MAX_BL_LEVEL 0xFF
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index 2e2413fd73a4..ad5ee28b83dc 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -699,6 +699,20 @@ static inline void amdgpu_dm_set_mst_status(uint8_t
*status,
extern const struct amdgpu_ip_block_version dm_ip_block;
+enum drm_transfer_function {
+ DRM_TRANSFER_FUNCTION_DEFAULT,
+ DRM_TRANSFER_FUNCTION_SRGB,
+ DRM_TRANSFER_FUNCTION_BT709,
+ DRM_TRANSFER_FUNCTION_PQ,
+ DRM_TRANSFER_FUNCTION_LINEAR,
+ DRM_TRANSFER_FUNCTION_UNITY,
+ DRM_TRANSFER_FUNCTION_HLG,
+ DRM_TRANSFER_FUNCTION_GAMMA22,
+ DRM_TRANSFER_FUNCTION_GAMMA24,
+ DRM_TRANSFER_FUNCTION_GAMMA26,
+ DRM_TRANSFER_FUNCTION_MAX,
+};
+
struct dm_plane_state {
struct drm_plane_state base;
struct dc_plane_state *dc_state;
@@ -726,6 +740,14 @@ struct dm_crtc_state {
struct dc_info_packet vrr_infopacket;
int abm_level;
+
+/**
+* @regamma_tf:
+*
+* Pre-defined transfer function for converting internal FB -> wire
+* encoding.
+*/
+ enum drm_transfer_function regamma_tf;
};
#define to_dm_crtc_state(x) contai
[PATCH 05/36] drm/amd/display: fix the delta clamping for shaper LUT
From: Harry Wentland
The shaper LUT requires a 10-bit value of the delta between
segments. We were using dc_fixpt_clamp_u0d10() to do that
but it doesn't do what we want it to do. It will preserve
10-bit precision after the decimal point, but that's not
quite what we want. We want 14-bit precision and discard
the 4 most-significant bytes.
To do that we'll do dc_fixpt_clamp_u0d14() & 0x3ff instead.
Signed-off-by: Harry Wentland
Signed-off-by: Melissa Wen
---
.../gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c | 14 +++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
index f27413e94280..efa6cee649d0 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
@@ -539,10 +539,18 @@ bool cm_helper_translate_curve_to_hw_format(
rgb->delta_green = dc_fixpt_sub(rgb_plus_1->green, rgb->green);
rgb->delta_blue = dc_fixpt_sub(rgb_plus_1->blue, rgb->blue);
+
if (fixpoint == true) {
- rgb->delta_red_reg =
dc_fixpt_clamp_u0d10(rgb->delta_red);
- rgb->delta_green_reg =
dc_fixpt_clamp_u0d10(rgb->delta_green);
- rgb->delta_blue_reg =
dc_fixpt_clamp_u0d10(rgb->delta_blue);
+ uint32_t red_clamp =
dc_fixpt_clamp_u0d14(rgb->delta_red);
+ uint32_t green_clamp =
dc_fixpt_clamp_u0d14(rgb->delta_green);
+ uint32_t blue_clamp =
dc_fixpt_clamp_u0d14(rgb->delta_blue);
+
+ if (red_clamp >> 10 || green_clamp >> 10 || blue_clamp
>> 10)
+ DC_LOG_WARNING("Losing delta precision while
programming shaper LUT.");
+
+ rgb->delta_red_reg = red_clamp & 0x3ff;
+ rgb->delta_green_reg = green_clamp & 0x3ff;
+ rgb->delta_blue_reg = blue_clamp & 0x3ff;
rgb->red_reg = dc_fixpt_clamp_u0d14(rgb->red);
rgb->green_reg = dc_fixpt_clamp_u0d14(rgb->green);
rgb->blue_reg= dc_fixpt_clamp_u0d14(rgb->blue);
--
2.39.2
[PATCH 03/36] drm/drm_plane: track color mgmt changes per plane
We will add color mgmt properties to DRM planes in the next patches and
we want to track when one of this properties change to define atomic
commit behaviors. Using a similar approach from CRTC color props, we set
a color_mgmt_changed boolean whenever a plane color prop changes.
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/drm_atomic.c | 1 +
drivers/gpu/drm/drm_atomic_state_helper.c | 1 +
include/drm/drm_plane.h | 7 +++
3 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index c0dc5858a723..da2429470c4f 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -724,6 +724,7 @@ static void drm_atomic_plane_print_state(struct drm_printer
*p,
drm_get_color_encoding_name(state->color_encoding));
drm_printf(p, "\tcolor-range=%s\n",
drm_get_color_range_name(state->color_range));
+ drm_printf(p, "\tcolor_mgmt_changed=%d\n", state->color_mgmt_changed);
if (plane->funcs->atomic_print_state)
plane->funcs->atomic_print_state(p, state);
diff --git a/drivers/gpu/drm/drm_atomic_state_helper.c
b/drivers/gpu/drm/drm_atomic_state_helper.c
index dfb57217253b..3df4c96a902e 100644
--- a/drivers/gpu/drm/drm_atomic_state_helper.c
+++ b/drivers/gpu/drm/drm_atomic_state_helper.c
@@ -338,6 +338,7 @@ void __drm_atomic_helper_plane_duplicate_state(struct
drm_plane *plane,
state->fence = NULL;
state->commit = NULL;
state->fb_damage_clips = NULL;
+ state->color_mgmt_changed = false;
}
EXPORT_SYMBOL(__drm_atomic_helper_plane_duplicate_state);
diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h
index 447e664e49d5..6c97380b8c76 100644
--- a/include/drm/drm_plane.h
+++ b/include/drm/drm_plane.h
@@ -237,6 +237,13 @@ struct drm_plane_state {
/** @state: backpointer to global drm_atomic_state */
struct drm_atomic_state *state;
+
+ /**
+* @color_mgmt_changed: Color management properties have changed. Used
+* by the atomic helpers and drivers to steer the atomic commit control
+* flow.
+*/
+ bool color_mgmt_changed : 1;
};
static inline struct drm_rect
--
2.39.2
[PATCH 04/36] drm/amd/display: fix segment distribution for linear LUTs
From: Harry Wentland
The region and segment calculation was incapable of dealing
with regions of more than 16 segments. We first fix this.
Now that we can support regions up to 256 elements we can
define a better segment distribution for near-linear LUTs
for our maximum of 256 HW-supported points.
With these changes an "identity" LUT looks visually
indistinguishable from bypass and allows us to use
our 3DLUT.
Signed-off-by: Harry Wentland
Signed-off-by: Melissa Wen
---
.../amd/display/dc/dcn10/dcn10_cm_common.c| 93 +++
1 file changed, 75 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
index 7a00fe525dfb..f27413e94280 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
@@ -346,20 +346,37 @@ bool cm_helper_translate_curve_to_hw_format(
* segment is from 2^-10 to 2^1
* There are less than 256 points, for optimization
*/
- seg_distr[0] = 3;
- seg_distr[1] = 4;
- seg_distr[2] = 4;
- seg_distr[3] = 4;
- seg_distr[4] = 4;
- seg_distr[5] = 4;
- seg_distr[6] = 4;
- seg_distr[7] = 4;
- seg_distr[8] = 4;
- seg_distr[9] = 4;
- seg_distr[10] = 1;
+ if (output_tf->tf == TRANSFER_FUNCTION_LINEAR) {
+ seg_distr[0] = 0; /* 2 */
+ seg_distr[1] = 1; /* 4 */
+ seg_distr[2] = 2; /* 4 */
+ seg_distr[3] = 3; /* 8 */
+ seg_distr[4] = 4; /* 16 */
+ seg_distr[5] = 5; /* 32 */
+ seg_distr[6] = 6; /* 64 */
+ seg_distr[7] = 7; /* 128 */
+
+ region_start = -8;
+ region_end = 1;
+ } else {
+ seg_distr[0] = 3; /* 8 */
+ seg_distr[1] = 4; /* 16 */
+ seg_distr[2] = 4;
+ seg_distr[3] = 4;
+ seg_distr[4] = 4;
+ seg_distr[5] = 4;
+ seg_distr[6] = 4;
+ seg_distr[7] = 4;
+ seg_distr[8] = 4;
+ seg_distr[9] = 4;
+ seg_distr[10] = 1; /* 2 */
+ /* total = 8*16 + 8 + 64 + 2 = */
+
+ region_start = -10;
+ region_end = 1;
+ }
+
- region_start = -10;
- region_end = 1;
}
for (i = region_end - region_start; i < MAX_REGIONS_NUMBER ; i++)
@@ -372,16 +389,56 @@ bool cm_helper_translate_curve_to_hw_format(
j = 0;
for (k = 0; k < (region_end - region_start); k++) {
- increment = NUMBER_SW_SEGMENTS / (1 << seg_distr[k]);
+ /*
+* We're using an ugly-ish hack here. Our HW allows for
+* 256 segments per region but SW_SEGMENTS is 16.
+* SW_SEGMENTS has some undocumented relationship to
+* the number of points in the tf_pts struct, which
+* is 512, unlike what's suggested TRANSFER_FUNC_POINTS.
+*
+* In order to work past this dilemma we'll scale our
+* increment by (1 << 4) and then do the inverse (1 >> 4)
+* when accessing the elements in tf_pts.
+*
+* TODO: find a better way using SW_SEGMENTS and
+* TRANSFER_FUNC_POINTS definitions
+*/
+ increment = (NUMBER_SW_SEGMENTS << 4) / (1 << seg_distr[k]);
start_index = (region_start + k + MAX_LOW_POINT) *
NUMBER_SW_SEGMENTS;
- for (i = start_index; i < start_index + NUMBER_SW_SEGMENTS;
+ for (i = (start_index << 4); i < (start_index << 4) +
(NUMBER_SW_SEGMENTS << 4);
i += increment) {
+ struct fixed31_32 in_plus_one, in;
+ struct fixed31_32 value, red_value, green_value,
blue_value;
+ uint32_t t = i & 0xf;
+
if (j == hw_points - 1)
break;
- rgb_resulted[j].red = output_tf->tf_pts.red[i];
- rgb_resulted[j].green = output_tf->tf_pts.green[i];
- rgb_resulted[j].blue = output_tf->tf_pts.blue[i];
+
+ in_plus_one = output_tf->tf_pts.red[(i >> 4) + 1];
+ in = output_tf->tf_pts.red[i >> 4];
+ value = dc_fixpt_sub(in_plus_one, in);
+ value = dc_fixpt_shr(dc_fixpt_
[PATCH 00/36] drm/amd/display: add AMD driver-specific properties for color mgmt
This series is a refined version of our RFC [1] for AMD driver-specific color management properties. It is a collection of contributions from Joshua, Harry and I to enhance AMD KMS color pipeline for Steam Deck/SteamOS by exposing the large set of color caps available in AMD display HW. Considering RFC feedback, this patchset differs from the previous one by removing the KConfig option and just guarding driver-specific properties with `AMD_PRIVATE_COLOR` - but we also removed the guards from internal elements and operations. We stopped to advertise CRTC shaper and 3D LUTs properties since they aren't in use in the Steam Deck color pipeline[2]. On the other hand, we keep mapping CRTC shaper and 3D LUTs (DM) to DC MPC setup. We also improved curve calculations to take into account HW color caps. In short, for pre-blending, we added the following properties: - plane degamma LUT and predefined transfer function; - plane HDR multiplier - plane shaper LUT/transfer function; - plane 3D LUT; and finally, - plane blend LUT/transfer function, just before blending. After blending, we already have DRM CRTC degamma/gamma LUTs and CTM, therefore, we extend post-blending color pipeline with CRTC gamma transfer function. The first three patches are on DRM KMS side. We expose DRM property helper for blob lookup and replacement so that we can use it for managing driver-specific properties. We add a tracked for plane color mgmt changes and increase the maximum number of properties to accommodate this expansion. The userspace case here is Gamescope which is the compositor for SteamOS. It's already using all of this functionality to implement its color management pipeline right now [3]. Current IGT tests kms_color and amdgpu/amd_color on DCN301 and DCN21 HW preserve the same results with and without the guard. Finally, I may have missed something, please let me know if that's the case. Best Regards, Melissa Wen [1] https://lore.kernel.org/dri-devel/20230423141051.702990-1-m...@igalia.com [2] https://github.com/ValveSoftware/gamescope/blob/master/src/docs/Steam%20Deck%20Display%20Pipeline.png [3] https://github.com/ValveSoftware/gamescope Harry Wentland (2): drm/amd/display: fix segment distribution for linear LUTs drm/amd/display: fix the delta clamping for shaper LUT Joshua Ashton (13): drm/amd/display: add plane degamma TF driver-specific property drm/amd/display: add plane HDR multiplier driver-specific property drm/amd/display: add plane blend LUT and TF driver-specific properties drm/amd/display: copy 3D LUT settings from crtc state to stream_update drm/amd/display: dynamically acquire 3DLUT resources for color changes drm/amd/display: add CRTC regamma TF support drm/amd/display: set sdr_ref_white_level to 80 for out_transfer_func drm/amd/display: add support for plane degamma TF and LUT properties drm/amd/display: add dc_fixpt_from_s3132 helper drm/adm/display: add HDR multiplier support drm/amd/display: handle empty LUTs in __set_input_tf drm/amd/display: add DRM plane blend LUT and TF support drm/amd/display: allow newer DC hardware to use degamma ROM for PQ/HLG Melissa Wen (21): drm/drm_mode_object: increase max objects to accommodate new color props drm/drm_property: make replace_property_blob_from_id a DRM helper drm/drm_plane: track color mgmt changes per plane drm/amd/display: add CRTC driver-specific property for gamma TF drm/amd/display: add plane driver-specific properties for degamma LUT drm/amd/display: add plane 3D LUT driver-specific properties drm/amd/display: add plane shaper LUT driver-specific properties drm/amd/display: add plane shaper TF driver-private property drm/amd/display: add comments to describe DM crtc color mgmt behavior drm/amd/display: encapsulate atomic regamma operation drm/amd/display: update lut3d and shaper lut to stream drm/amd/display: allow BYPASS 3D LUT but keep shaper LUT settings drm/amd/display: handle MPC 3D LUT resources for a given context drm/amd/display: add CRTC 3D LUT support drm/amd/display: add CRTC shaper LUT support drm/amd/display: add CRTC shaper TF support drm/amd/display: mark plane as needing reset if plane color mgmt changes drm/amd/display: decouple steps for mapping CRTC degamma to DC plane drm/amd/display: reject atomic commit if setting both plane and CRTC degamma drm/amd/display: program DPP shaper and 3D LUT if updated drm/amd/display: add plane shaper/3D LUT and shaper TF support drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 125 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 69 ++ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 28 +- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 110 +++- .../amd/display/amdgpu_dm/amdgpu_dm_color.c | 612 -- .../amd/display/amdgpu_dm/amdgpu_dm_crtc.c| 72 ++- .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 213 +- drivers/gpu/drm/amd/display/dc/core/dc.c | 49 +- drivers/gp
[PATCH 01/36] drm/drm_mode_object: increase max objects to accommodate new color props
DRM_OBJECT_MAX_PROPERTY limits the number of properties to be attached
and we are increasing that value all time we add a new property (generic
or driver-specific).
In this series, we are adding 13 new KMS driver-specific properties for
AMD color manage:
- CRTC Gamma enumerated Transfer Function
- Plane: Degamma LUT+size+TF, HDR multiplier, shaper LUT+size+TF, 3D
LUT+size, blend LUT+size+TF (12)
Therefore, just increase DRM_OBJECT_MAX_PROPERTY to a number (64) that
accomodates these new properties and gives some room for others,
avoiding change this number everytime we add a new KMS property.
Signed-off-by: Melissa Wen
---
include/drm/drm_mode_object.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/drm/drm_mode_object.h b/include/drm/drm_mode_object.h
index 912f1e415685..08d7a7f0188f 100644
--- a/include/drm/drm_mode_object.h
+++ b/include/drm/drm_mode_object.h
@@ -60,7 +60,7 @@ struct drm_mode_object {
void (*free_cb)(struct kref *kref);
};
-#define DRM_OBJECT_MAX_PROPERTY 24
+#define DRM_OBJECT_MAX_PROPERTY 64
/**
* struct drm_object_properties - property tracking for &drm_mode_object
*/
--
2.39.2
[PATCH 02/36] drm/drm_property: make replace_property_blob_from_id a DRM helper
Place it in drm_property where drm_property_replace_blob and
drm_property_lookup_blob live. Then we can use the DRM helper for
driver-specific KMS properties too.
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/arm/malidp_crtc.c | 2 +-
drivers/gpu/drm/drm_atomic_uapi.c | 43 ---
drivers/gpu/drm/drm_property.c| 49 +++
include/drm/drm_property.h| 6
4 files changed, 61 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/arm/malidp_crtc.c
b/drivers/gpu/drm/arm/malidp_crtc.c
index dc01c43f6193..d72c22dcf685 100644
--- a/drivers/gpu/drm/arm/malidp_crtc.c
+++ b/drivers/gpu/drm/arm/malidp_crtc.c
@@ -221,7 +221,7 @@ static int malidp_crtc_atomic_check_ctm(struct drm_crtc
*crtc,
/*
* The size of the ctm is checked in
-* drm_atomic_replace_property_blob_from_id.
+* drm_property_replace_blob_from_id.
*/
ctm = (struct drm_color_ctm *)state->ctm->data;
for (i = 0; i < ARRAY_SIZE(ctm->matrix); ++i) {
diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
b/drivers/gpu/drm/drm_atomic_uapi.c
index c06d0639d552..b76d50ae244c 100644
--- a/drivers/gpu/drm/drm_atomic_uapi.c
+++ b/drivers/gpu/drm/drm_atomic_uapi.c
@@ -362,39 +362,6 @@ static s32 __user *get_out_fence_for_connector(struct
drm_atomic_state *state,
return fence_ptr;
}
-static int
-drm_atomic_replace_property_blob_from_id(struct drm_device *dev,
-struct drm_property_blob **blob,
-uint64_t blob_id,
-ssize_t expected_size,
-ssize_t expected_elem_size,
-bool *replaced)
-{
- struct drm_property_blob *new_blob = NULL;
-
- if (blob_id != 0) {
- new_blob = drm_property_lookup_blob(dev, blob_id);
- if (new_blob == NULL)
- return -EINVAL;
-
- if (expected_size > 0 &&
- new_blob->length != expected_size) {
- drm_property_blob_put(new_blob);
- return -EINVAL;
- }
- if (expected_elem_size > 0 &&
- new_blob->length % expected_elem_size != 0) {
- drm_property_blob_put(new_blob);
- return -EINVAL;
- }
- }
-
- *replaced |= drm_property_replace_blob(blob, new_blob);
- drm_property_blob_put(new_blob);
-
- return 0;
-}
-
static int drm_atomic_crtc_set_property(struct drm_crtc *crtc,
struct drm_crtc_state *state, struct drm_property *property,
uint64_t val)
@@ -415,7 +382,7 @@ static int drm_atomic_crtc_set_property(struct drm_crtc
*crtc,
} else if (property == config->prop_vrr_enabled) {
state->vrr_enabled = val;
} else if (property == config->degamma_lut_property) {
- ret = drm_atomic_replace_property_blob_from_id(dev,
+ ret = drm_property_replace_blob_from_id(dev,
&state->degamma_lut,
val,
-1, sizeof(struct drm_color_lut),
@@ -423,7 +390,7 @@ static int drm_atomic_crtc_set_property(struct drm_crtc
*crtc,
state->color_mgmt_changed |= replaced;
return ret;
} else if (property == config->ctm_property) {
- ret = drm_atomic_replace_property_blob_from_id(dev,
+ ret = drm_property_replace_blob_from_id(dev,
&state->ctm,
val,
sizeof(struct drm_color_ctm), -1,
@@ -431,7 +398,7 @@ static int drm_atomic_crtc_set_property(struct drm_crtc
*crtc,
state->color_mgmt_changed |= replaced;
return ret;
} else if (property == config->gamma_lut_property) {
- ret = drm_atomic_replace_property_blob_from_id(dev,
+ ret = drm_property_replace_blob_from_id(dev,
&state->gamma_lut,
val,
-1, sizeof(struct drm_color_lut),
@@ -563,7 +530,7 @@ static int drm_atomic_plane_set_property(struct drm_plane
*plane,
} else if (property == plane->color_range_property) {
state->color_range = val;
} else if (property == config->prop_fb_damage_clips) {
- ret = drm_atomic_replace_property_blob_from_id(dev,
+ ret = drm_property_replace_blob_from_id(dev,
&state->fb_damage_clips,
val,
-1,
@@ -727,7 +694,7 @@ static int drm_atomic_connector_set_property(struct
drm_con
[linux-next:master] BUILD REGRESSION 9f925874281f7e8855855d6210d6e29d844e4307
tree/branch: INFO setup_repo_specs: /db/releases/20230524001904/lkp-src/repo/*/linux-next https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master branch HEAD: 9f925874281f7e8855855d6210d6e29d844e4307 Add linux-next specific files for 20230523 Error/Warning reports: https://lore.kernel.org/oe-kbuild-all/202305230552.wobyqyya-...@intel.com https://lore.kernel.org/oe-kbuild-all/202305231949.2mkdgzpn-...@intel.com Error/Warning: (recently discovered and may have been fixed) drivers/base/regmap/regcache-maple.c:113:23: warning: 'lower_index' is used uninitialized [-Wuninitialized] drivers/base/regmap/regcache-maple.c:113:36: warning: 'lower_last' is used uninitialized [-Wuninitialized] drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_hw_sequencer.c:2292:31: error: 'struct hwseq_private_funcs' has no member named 'resync_fifo_dccg_dio' drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_hw_sequencer.c:2295:31: error: 'struct hwseq_private_funcs' has no member named 'resync_fifo_dccg_dio' drivers/gpu/drm/i915/display/intel_display.c:6012:3: warning: unannotated fall-through between switch labels [-Wimplicit-fallthrough] Unverified Error/Warning (likely false positive, please contact us if interested): drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c:540 amdgpu_debugfs_mqd_read() warn: ignoring unreachable code. drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c:68 amdgpu_xcp_run_transition() error: buffer overflow 'xcp_mgr->xcp' 8 <= 8 kernel/events/uprobes.c:478 uprobe_write_opcode() warn: passing zero to 'PTR_ERR' kernel/watchdog.c:40:19: sparse: sparse: symbol 'watchdog_hardlockup_user_enabled' was not declared. Should it be static? kernel/watchdog.c:41:19: sparse: sparse: symbol 'watchdog_softlockup_user_enabled' was not declared. Should it be static? Error/Warning ids grouped by kconfigs: gcc_recent_errors |-- arc-allyesconfig | |-- drivers-base-regmap-regcache-maple.c:warning:lower_index-is-used-uninitialized | `-- drivers-base-regmap-regcache-maple.c:warning:lower_last-is-used-uninitialized |-- arc-axs103_smp_defconfig | |-- drivers-base-regmap-regcache-maple.c:warning:lower_index-is-used-uninitialized | `-- drivers-base-regmap-regcache-maple.c:warning:lower_last-is-used-uninitialized |-- arc-randconfig-c44-20230523 | |-- drivers-base-regmap-regcache-maple.c:warning:lower_index-is-used-uninitialized | `-- drivers-base-regmap-regcache-maple.c:warning:lower_last-is-used-uninitialized |-- arc-randconfig-m041-20230521 | |-- drivers-base-regmap-regcache-maple.c:warning:lower_index-is-used-uninitialized | `-- drivers-base-regmap-regcache-maple.c:warning:lower_last-is-used-uninitialized |-- arm-allmodconfig | `-- drivers-gpu-drm-amd-amdgpu-..-display-dc-dce110-dce110_hw_sequencer.c:error:struct-hwseq_private_funcs-has-no-member-named-resync_fifo_dccg_dio |-- arm-allyesconfig | `-- drivers-gpu-drm-amd-amdgpu-..-display-dc-dce110-dce110_hw_sequencer.c:error:struct-hwseq_private_funcs-has-no-member-named-resync_fifo_dccg_dio |-- arm-randconfig-s031-20230521 | |-- kernel-watchdog.c:sparse:sparse:symbol-watchdog_hardlockup_user_enabled-was-not-declared.-Should-it-be-static | `-- kernel-watchdog.c:sparse:sparse:symbol-watchdog_softlockup_user_enabled-was-not-declared.-Should-it-be-static |-- arm-randconfig-s041-20230521 | |-- kernel-watchdog.c:sparse:sparse:symbol-watchdog_hardlockup_user_enabled-was-not-declared.-Should-it-be-static | `-- kernel-watchdog.c:sparse:sparse:symbol-watchdog_softlockup_user_enabled-was-not-declared.-Should-it-be-static |-- i386-randconfig-m021 | `-- kernel-events-uprobes.c-uprobe_write_opcode()-warn:passing-zero-to-PTR_ERR |-- i386-randconfig-s001 | |-- kernel-watchdog.c:sparse:sparse:symbol-watchdog_hardlockup_user_enabled-was-not-declared.-Should-it-be-static | `-- kernel-watchdog.c:sparse:sparse:symbol-watchdog_softlockup_user_enabled-was-not-declared.-Should-it-be-static |-- i386-randconfig-s002 | |-- kernel-watchdog.c:sparse:sparse:symbol-watchdog_hardlockup_user_enabled-was-not-declared.-Should-it-be-static | `-- kernel-watchdog.c:sparse:sparse:symbol-watchdog_softlockup_user_enabled-was-not-declared.-Should-it-be-static |-- i386-randconfig-s003 | |-- kernel-watchdog.c:sparse:sparse:symbol-watchdog_hardlockup_user_enabled-was-not-declared.-Should-it-be-static | `-- kernel-watchdog.c:sparse:sparse:symbol-watchdog_softlockup_user_enabled-was-not-declared.-Should-it-be-static |-- ia64-randconfig-m041-20230522 | `-- drivers-gpu-drm-amd-amdgpu-..-display-dc-dce110-dce110_hw_sequencer.c:error:struct-hwseq_private_funcs-has-no-member-named-resync_fifo_dccg_dio |-- ia64-randconfig-r026-20230522 | `-- drivers-gpu-drm-amd-amdgpu-..-display-dc-dce110-dce110_hw_sequencer.c:error:struct-hwseq_private_funcs-has-no-member-named-resync_fifo_dccg_dio |-- m68k-randconfig-s042-20230521 | |-- ker
Re: [PATCH] drm/amd/amdgpu: Fix warnings in amdgpu_irq.c
Reviewed-by: Alex Deucher
On Tue, May 23, 2023 at 3:51 PM Srinivasan Shanmugam
wrote:
>
> WARNING: Prefer 'unsigned int' to bare use of 'unsigned'
> WARNING: braces {} are not necessary for any arm of this statement
> + if (nvec <= 0) {
> [...]
> + } else {
> [...]
> WARNING: Block comments use a trailing */ on a separate line
>
> Cc: Christian König
> Cc: Alex Deucher
> Signed-off-by: Srinivasan Shanmugam
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 27 +
> 1 file changed, 14 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> index ad5368e15114..00f2106c17b9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> @@ -125,7 +125,7 @@ const int node_id_to_phys_map[NODEID_MAX] = {
> void amdgpu_irq_disable_all(struct amdgpu_device *adev)
> {
> unsigned long irqflags;
> - unsigned i, j, k;
> + unsigned int i, j, k;
> int r;
>
> spin_lock_irqsave(&adev->irq.lock, irqflags);
> @@ -284,11 +284,11 @@ int amdgpu_irq_init(struct amdgpu_device *adev)
> int nvec = pci_msix_vec_count(adev->pdev);
> unsigned int flags;
>
> - if (nvec <= 0) {
> + if (nvec <= 0)
> flags = PCI_IRQ_MSI;
> - } else {
> + else
> flags = PCI_IRQ_MSI | PCI_IRQ_MSIX;
> - }
> +
> /* we only need one vector */
> nvec = pci_alloc_irq_vectors(adev->pdev, 1, 1, flags);
> if (nvec > 0) {
> @@ -347,7 +347,7 @@ void amdgpu_irq_fini_hw(struct amdgpu_device *adev)
> */
> void amdgpu_irq_fini_sw(struct amdgpu_device *adev)
> {
> - unsigned i, j;
> + unsigned int i, j;
>
> for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
> if (!adev->irq.client[i].sources)
> @@ -381,7 +381,7 @@ void amdgpu_irq_fini_sw(struct amdgpu_device *adev)
> * 0 on success or error code otherwise
> */
> int amdgpu_irq_add_id(struct amdgpu_device *adev,
> - unsigned client_id, unsigned src_id,
> + unsigned int client_id, unsigned int src_id,
> struct amdgpu_irq_src *source)
> {
> if (client_id >= AMDGPU_IRQ_CLIENTID_MAX)
> @@ -433,7 +433,7 @@ void amdgpu_irq_dispatch(struct amdgpu_device *adev,
> {
> u32 ring_index = ih->rptr >> 2;
> struct amdgpu_iv_entry entry;
> - unsigned client_id, src_id;
> + unsigned int client_id, src_id;
> struct amdgpu_irq_src *src;
> bool handled = false;
> int r;
> @@ -508,7 +508,7 @@ void amdgpu_irq_delegate(struct amdgpu_device *adev,
> * Updates interrupt state for the specific source (all ASICs).
> */
> int amdgpu_irq_update(struct amdgpu_device *adev,
> -struct amdgpu_irq_src *src, unsigned type)
> +struct amdgpu_irq_src *src, unsigned int type)
> {
> unsigned long irqflags;
> enum amdgpu_interrupt_state state;
> @@ -517,7 +517,8 @@ int amdgpu_irq_update(struct amdgpu_device *adev,
> spin_lock_irqsave(&adev->irq.lock, irqflags);
>
> /* We need to determine after taking the lock, otherwise
> - we might disable just enabled interrupts again */
> +* we might disable just enabled interrupts again
> +*/
> if (amdgpu_irq_enabled(adev, src, type))
> state = AMDGPU_IRQ_STATE_ENABLE;
> else
> @@ -571,7 +572,7 @@ void amdgpu_irq_gpu_reset_resume_helper(struct
> amdgpu_device *adev)
> * 0 on success or error code otherwise
> */
> int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
> - unsigned type)
> + unsigned int type)
> {
> if (!adev->irq.installed)
> return -ENOENT;
> @@ -601,7 +602,7 @@ int amdgpu_irq_get(struct amdgpu_device *adev, struct
> amdgpu_irq_src *src,
> * 0 on success or error code otherwise
> */
> int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
> - unsigned type)
> + unsigned int type)
> {
> if (!adev->irq.installed)
> return -ENOENT;
> @@ -635,7 +636,7 @@ int amdgpu_irq_put(struct amdgpu_device *adev, struct
> amdgpu_irq_src *src,
> * invalid parameters
> */
> bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src
> *src,
> - unsigned type)
> + unsigned int type)
> {
> if (!adev->irq.installed)
> return false;
> @@ -748,7 +749,7 @@ void amdgpu_irq_remove_domain(struct amdgpu_device *adev)
> * Returns:
> * Linux IRQ
> */
> -unsigned amdgpu_irq_create_mapping(struct amdgpu_device *adev, unsigned
> src_id)
> +unsigned int amdgpu_irq
[PATCH] drm/amd/amdgpu: Fix warnings in amdgpu_irq.c
WARNING: Prefer 'unsigned int' to bare use of 'unsigned'
WARNING: braces {} are not necessary for any arm of this statement
+ if (nvec <= 0) {
[...]
+ } else {
[...]
WARNING: Block comments use a trailing */ on a separate line
Cc: Christian König
Cc: Alex Deucher
Signed-off-by: Srinivasan Shanmugam
---
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 27 +
1 file changed, 14 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
index ad5368e15114..00f2106c17b9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
@@ -125,7 +125,7 @@ const int node_id_to_phys_map[NODEID_MAX] = {
void amdgpu_irq_disable_all(struct amdgpu_device *adev)
{
unsigned long irqflags;
- unsigned i, j, k;
+ unsigned int i, j, k;
int r;
spin_lock_irqsave(&adev->irq.lock, irqflags);
@@ -284,11 +284,11 @@ int amdgpu_irq_init(struct amdgpu_device *adev)
int nvec = pci_msix_vec_count(adev->pdev);
unsigned int flags;
- if (nvec <= 0) {
+ if (nvec <= 0)
flags = PCI_IRQ_MSI;
- } else {
+ else
flags = PCI_IRQ_MSI | PCI_IRQ_MSIX;
- }
+
/* we only need one vector */
nvec = pci_alloc_irq_vectors(adev->pdev, 1, 1, flags);
if (nvec > 0) {
@@ -347,7 +347,7 @@ void amdgpu_irq_fini_hw(struct amdgpu_device *adev)
*/
void amdgpu_irq_fini_sw(struct amdgpu_device *adev)
{
- unsigned i, j;
+ unsigned int i, j;
for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
if (!adev->irq.client[i].sources)
@@ -381,7 +381,7 @@ void amdgpu_irq_fini_sw(struct amdgpu_device *adev)
* 0 on success or error code otherwise
*/
int amdgpu_irq_add_id(struct amdgpu_device *adev,
- unsigned client_id, unsigned src_id,
+ unsigned int client_id, unsigned int src_id,
struct amdgpu_irq_src *source)
{
if (client_id >= AMDGPU_IRQ_CLIENTID_MAX)
@@ -433,7 +433,7 @@ void amdgpu_irq_dispatch(struct amdgpu_device *adev,
{
u32 ring_index = ih->rptr >> 2;
struct amdgpu_iv_entry entry;
- unsigned client_id, src_id;
+ unsigned int client_id, src_id;
struct amdgpu_irq_src *src;
bool handled = false;
int r;
@@ -508,7 +508,7 @@ void amdgpu_irq_delegate(struct amdgpu_device *adev,
* Updates interrupt state for the specific source (all ASICs).
*/
int amdgpu_irq_update(struct amdgpu_device *adev,
-struct amdgpu_irq_src *src, unsigned type)
+struct amdgpu_irq_src *src, unsigned int type)
{
unsigned long irqflags;
enum amdgpu_interrupt_state state;
@@ -517,7 +517,8 @@ int amdgpu_irq_update(struct amdgpu_device *adev,
spin_lock_irqsave(&adev->irq.lock, irqflags);
/* We need to determine after taking the lock, otherwise
- we might disable just enabled interrupts again */
+* we might disable just enabled interrupts again
+*/
if (amdgpu_irq_enabled(adev, src, type))
state = AMDGPU_IRQ_STATE_ENABLE;
else
@@ -571,7 +572,7 @@ void amdgpu_irq_gpu_reset_resume_helper(struct
amdgpu_device *adev)
* 0 on success or error code otherwise
*/
int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
- unsigned type)
+ unsigned int type)
{
if (!adev->irq.installed)
return -ENOENT;
@@ -601,7 +602,7 @@ int amdgpu_irq_get(struct amdgpu_device *adev, struct
amdgpu_irq_src *src,
* 0 on success or error code otherwise
*/
int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
- unsigned type)
+ unsigned int type)
{
if (!adev->irq.installed)
return -ENOENT;
@@ -635,7 +636,7 @@ int amdgpu_irq_put(struct amdgpu_device *adev, struct
amdgpu_irq_src *src,
* invalid parameters
*/
bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
- unsigned type)
+ unsigned int type)
{
if (!adev->irq.installed)
return false;
@@ -748,7 +749,7 @@ void amdgpu_irq_remove_domain(struct amdgpu_device *adev)
* Returns:
* Linux IRQ
*/
-unsigned amdgpu_irq_create_mapping(struct amdgpu_device *adev, unsigned src_id)
+unsigned int amdgpu_irq_create_mapping(struct amdgpu_device *adev, unsigned
int src_id)
{
adev->irq.virq[src_id] = irq_create_mapping(adev->irq.domain, src_id);
--
2.25.1
Re: [PATCH] drm/amdgpu: Fix unused variable in amdgpu_gfx.c
Reviewed-by: Alex Deucher
On Tue, May 23, 2023 at 3:07 PM Srinivasan Shanmugam
wrote:
>
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c: In function ‘amdgpu_gfx_disable_kcq’:
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c:497:6: warning: variable ‘j’ set but
> not used [-Wunused-but-set-variable]
> 497 | int j;
> | ^
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c: In function ‘amdgpu_gfx_disable_kgq’:
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c:528:6: warning: variable ‘j’ set but
> not used [-Wunused-but-set-variable]
> 528 | int j;
> | ^
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c: In function ‘amdgpu_gfx_enable_kgq’:
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c:630:12: warning: variable ‘j’ set but
> not used [-Wunused-but-set-variable]
> 630 | int r, i, j;
> |
>
> Cc: Alex Deucher
> Cc: Christian König
> Signed-off-by: Srinivasan Shanmugam
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> index 2b4bf6c11ae4..a33d4bc34cee 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> @@ -509,7 +509,7 @@ int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev,
> int xcc_id)
> for (i = 0; i < adev->gfx.num_compute_rings; i++) {
> j = i + xcc_id * adev->gfx.num_compute_rings;
> kiq->pmf->kiq_unmap_queues(kiq_ring,
> - &adev->gfx.compute_ring[i],
> + &adev->gfx.compute_ring[j],
>RESET_QUEUES, 0, 0);
> }
>
> @@ -541,7 +541,7 @@ int amdgpu_gfx_disable_kgq(struct amdgpu_device *adev,
> int xcc_id)
> for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
> j = i + xcc_id * adev->gfx.num_gfx_rings;
> kiq->pmf->kiq_unmap_queues(kiq_ring,
> - &adev->gfx.gfx_ring[i],
> + &adev->gfx.gfx_ring[j],
>PREEMPT_QUEUES, 0, 0);
> }
> }
> @@ -648,7 +648,7 @@ int amdgpu_gfx_enable_kgq(struct amdgpu_device *adev, int
> xcc_id)
> for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
> j = i + xcc_id * adev->gfx.num_gfx_rings;
> kiq->pmf->kiq_map_queues(kiq_ring,
> -&adev->gfx.gfx_ring[i]);
> +&adev->gfx.gfx_ring[j]);
> }
> }
>
> --
> 2.25.1
>
Re: [Freedreno] [PATCH v3 11/12] drm/fbdev-generic: Implement dedicated fbdev I/O helpers
Am 22.05.23 um 20:46 schrieb Thomas Zimmermann:
[...]
Looking at this patch makes me wonder if we should have implemented
fb_dirty for the MSM driver. We have drm_framebuffer_funcs::dirty()
implemented (by wrapping the drm_atomic_helper_dirtyfb()).
I think so. You'd need something similar to the generic fbdev emulation.
But it's for a separate patchset. Apparently no one has complained so far.
I have another revision of these patches in the works and will add
initial support for damage handling.
Best regards
Thomas
diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index 77fb10ddd8a2..92a782827b7b 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -95,6 +95,7 @@ config DRM_KUNIT_TEST
config DRM_KMS_HELPER
tristate
depends on DRM
+ select FB_SYS_HELPERS_DEFERRED if DRM_FBDEV_EMULATION
help
CRTC helpers for KMS drivers.
@@ -135,11 +136,6 @@ config DRM_FBDEV_EMULATION
select FB_CFB_FILLRECT
select FB_CFB_COPYAREA
select FB_CFB_IMAGEBLIT
- select FB_DEFERRED_IO
- select FB_SYS_FOPS
- select FB_SYS_FILLRECT
- select FB_SYS_COPYAREA
- select FB_SYS_IMAGEBLIT
select FRAMEBUFFER_CONSOLE if !EXPERT
select FRAMEBUFFER_CONSOLE_DETECT_PRIMARY if
FRAMEBUFFER_CONSOLE
default y
diff --git a/drivers/gpu/drm/drm_fb_helper.c
b/drivers/gpu/drm/drm_fb_helper.c
index 8724e08c518b..ba0a808f14ee 100644
--- a/drivers/gpu/drm/drm_fb_helper.c
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -729,113 +729,6 @@ void drm_fb_helper_deferred_io(struct fb_info
*info, struct list_head *pagerefli
}
EXPORT_SYMBOL(drm_fb_helper_deferred_io);
-/**
- * drm_fb_helper_sys_read - Implements struct &fb_ops.fb_read for
system memory
- * @info: fb_info struct pointer
- * @buf: userspace buffer to read from framebuffer memory
- * @count: number of bytes to read from framebuffer memory
- * @ppos: read offset within framebuffer memory
- *
- * Returns:
- * The number of bytes read on success, or an error code otherwise.
- */
-ssize_t drm_fb_helper_sys_read(struct fb_info *info, char __user *buf,
- size_t count, loff_t *ppos)
-{
- return fb_sys_read(info, buf, count, ppos);
-}
-EXPORT_SYMBOL(drm_fb_helper_sys_read);
-
-/**
- * drm_fb_helper_sys_write - Implements struct &fb_ops.fb_write for
system memory
- * @info: fb_info struct pointer
- * @buf: userspace buffer to write to framebuffer memory
- * @count: number of bytes to write to framebuffer memory
- * @ppos: write offset within framebuffer memory
- *
- * Returns:
- * The number of bytes written on success, or an error code otherwise.
- */
-ssize_t drm_fb_helper_sys_write(struct fb_info *info, const char
__user *buf,
- size_t count, loff_t *ppos)
-{
- struct drm_fb_helper *helper = info->par;
- loff_t pos = *ppos;
- ssize_t ret;
- struct drm_rect damage_area;
-
- ret = fb_sys_write(info, buf, count, ppos);
- if (ret <= 0)
- return ret;
-
- if (helper->funcs->fb_dirty) {
- drm_fb_helper_memory_range_to_clip(info, pos, ret,
&damage_area);
- drm_fb_helper_damage(helper, damage_area.x1,
damage_area.y1,
- drm_rect_width(&damage_area),
- drm_rect_height(&damage_area));
- }
-
- return ret;
-}
-EXPORT_SYMBOL(drm_fb_helper_sys_write);
-
-/**
- * drm_fb_helper_sys_fillrect - wrapper around sys_fillrect
- * @info: fbdev registered by the helper
- * @rect: info about rectangle to fill
- *
- * A wrapper around sys_fillrect implemented by fbdev core
- */
-void drm_fb_helper_sys_fillrect(struct fb_info *info,
- const struct fb_fillrect *rect)
-{
- struct drm_fb_helper *helper = info->par;
-
- sys_fillrect(info, rect);
-
- if (helper->funcs->fb_dirty)
- drm_fb_helper_damage(helper, rect->dx, rect->dy,
rect->width, rect->height);
-}
-EXPORT_SYMBOL(drm_fb_helper_sys_fillrect);
-
-/**
- * drm_fb_helper_sys_copyarea - wrapper around sys_copyarea
- * @info: fbdev registered by the helper
- * @area: info about area to copy
- *
- * A wrapper around sys_copyarea implemented by fbdev core
- */
-void drm_fb_helper_sys_copyarea(struct fb_info *info,
- const struct fb_copyarea *area)
-{
- struct drm_fb_helper *helper = info->par;
-
- sys_copyarea(info, area);
-
- if (helper->funcs->fb_dirty)
- drm_fb_helper_damage(helper, area->dx, area->dy,
area->width, area->height);
-}
-EXPORT_SYMBOL(drm_fb_helper_sys_copyarea);
-
-/**
- * drm_fb_helper_sys_imageblit - wrapper around sys_imageblit
- * @info: fbdev registered by the helper
- * @image: info about image to blit
- *
- * A wrapper around sys_imageblit implemented by fbdev core
- */
-void drm_fb_helper_sys_imageblit(struct fb_info *info,
[PATCH] drm/amdgpu: Fix unused variable in amdgpu_gfx.c
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c: In function ‘amdgpu_gfx_disable_kcq’:
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c:497:6: warning: variable ‘j’ set but
not used [-Wunused-but-set-variable]
497 | int j;
| ^
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c: In function ‘amdgpu_gfx_disable_kgq’:
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c:528:6: warning: variable ‘j’ set but
not used [-Wunused-but-set-variable]
528 | int j;
| ^
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c: In function ‘amdgpu_gfx_enable_kgq’:
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c:630:12: warning: variable ‘j’ set but
not used [-Wunused-but-set-variable]
630 | int r, i, j;
|
Cc: Alex Deucher
Cc: Christian König
Signed-off-by: Srinivasan Shanmugam
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index 2b4bf6c11ae4..a33d4bc34cee 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -509,7 +509,7 @@ int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev, int
xcc_id)
for (i = 0; i < adev->gfx.num_compute_rings; i++) {
j = i + xcc_id * adev->gfx.num_compute_rings;
kiq->pmf->kiq_unmap_queues(kiq_ring,
- &adev->gfx.compute_ring[i],
+ &adev->gfx.compute_ring[j],
RESET_QUEUES, 0, 0);
}
@@ -541,7 +541,7 @@ int amdgpu_gfx_disable_kgq(struct amdgpu_device *adev, int
xcc_id)
for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
j = i + xcc_id * adev->gfx.num_gfx_rings;
kiq->pmf->kiq_unmap_queues(kiq_ring,
- &adev->gfx.gfx_ring[i],
+ &adev->gfx.gfx_ring[j],
PREEMPT_QUEUES, 0, 0);
}
}
@@ -648,7 +648,7 @@ int amdgpu_gfx_enable_kgq(struct amdgpu_device *adev, int
xcc_id)
for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
j = i + xcc_id * adev->gfx.num_gfx_rings;
kiq->pmf->kiq_map_queues(kiq_ring,
-&adev->gfx.gfx_ring[i]);
+&adev->gfx.gfx_ring[j]);
}
}
--
2.25.1
Re: [PATCH] Revert "drm/amdgpu: remove TOPDOWN flags when allocating VRAM in large bar system"
Hi Felix, On 5/21/2023 12:09 AM, Felix Kuehling wrote: Am 2023-05-20 um 05:25 schrieb Arunpravin Paneer Selvam: This reverts commit c105518679b6e87232874ffc989ec403bee59664. This patch disables the TOPDOWN flag for APU and few dGPU cards which has the VRAM size equal to the BAR size. With resizable BARs it's not that rare. When we enable the TOPDOWN flag, we get the free blocks at the highest available memory region and we don't split the lower order blocks. This change is required to keep off the fragmentation related issues particularly in ASIC which has VRAM space <= 500MiB If TOPDOWN has these general benefits, then would it make sense to allocate visible memory TOPDOWN as well, on large-BAR GPUs? Without knowing too much about the internals of the allocator, my intuition tells me that using only one allocation strategy has a better chance of minimizing fragmentation than mixing two allocation strategies for no good reason. We have 2 allocation strategies for visible memory and non-visible memory. For visible memory we are going with tree based search as we should limit our allocation within a specified range limit. The TOPDOWN flag is not applicable for tree based search allocation. For non-visible memory we pick free blocks from the free list and here the TOPDOWN flag is applicable. For large-BAR GPUs visible memory, we don't go with tree based search since the BAR == VRAM size, and if this AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED flag is set for every allocation on large-BAR GPUs, we don't set TOPDOWN flag and this could create fragmentation issue in case of heavy load. I will check the behavior on large BAR GPUs and set the TOPDOWN flag if not set. Thanks, Arun. Regards, Felix Hence, we are reverting this patch. Gitlab issue link - https://gitlab.freedesktop.org/drm/amd/-/issues/2270 Signed-off-by: Arunpravin Paneer Selvam --- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index 2bd1a54ee866..ca5fc07faf6c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -139,7 +139,7 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain) if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) places[c].lpfn = visible_pfn; - else if (adev->gmc.real_vram_size != adev->gmc.visible_vram_size) + else places[c].flags |= TTM_PL_FLAG_TOPDOWN; if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)
Re: [PATCH] drm/amdgpu: Remove unused variable in amdgpu_gfx.c
On Tue, May 23, 2023 at 2:31 PM Srinivasan Shanmugam
wrote:
>
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c: In function ‘amdgpu_gfx_disable_kcq’:
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c:497:6: warning: variable ‘j’ set but
> not used [-Wunused-but-set-variable]
> 497 | int j;
> | ^
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c: In function ‘amdgpu_gfx_disable_kgq’:
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c:528:6: warning: variable ‘j’ set but
> not used [-Wunused-but-set-variable]
> 528 | int j;
> | ^
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c: In function ‘amdgpu_gfx_enable_kgq’:
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c:630:12: warning: variable ‘j’ set but
> not used [-Wunused-but-set-variable]
> 630 | int r, i, j;
> |
>
> This variable is not used so remove them.
>
> Cc: Alex Deucher
> Cc: Christian König
> Signed-off-by: Srinivasan Shanmugam
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 16
> 1 file changed, 4 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> index 2b4bf6c11ae4..c7c16d6c476a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> @@ -494,7 +494,6 @@ int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev,
> int xcc_id)
> struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
> struct amdgpu_ring *kiq_ring = &kiq->ring;
> int i, r = 0;
> - int j;
>
> if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
> return -EINVAL;
> @@ -506,12 +505,10 @@ int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev,
> int xcc_id)
> return -ENOMEM;
> }
>
> - for (i = 0; i < adev->gfx.num_compute_rings; i++) {
> - j = i + xcc_id * adev->gfx.num_compute_rings;
> + for (i = 0; i < adev->gfx.num_compute_rings; i++)
> kiq->pmf->kiq_unmap_queues(kiq_ring,
>&adev->gfx.compute_ring[i],
I think this should probably be j here rather than i. Same for the
functions below. I swear I saw a patch which fixed this, but maybe it
never landed?
Alex
>RESET_QUEUES, 0, 0);
> - }
>
> if (kiq_ring->sched.ready && !adev->job_hang)
> r = amdgpu_ring_test_helper(kiq_ring);
> @@ -525,7 +522,6 @@ int amdgpu_gfx_disable_kgq(struct amdgpu_device *adev,
> int xcc_id)
> struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
> struct amdgpu_ring *kiq_ring = &kiq->ring;
> int i, r = 0;
> - int j;
>
> if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
> return -EINVAL;
> @@ -538,12 +534,10 @@ int amdgpu_gfx_disable_kgq(struct amdgpu_device *adev,
> int xcc_id)
> return -ENOMEM;
> }
>
> - for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
> - j = i + xcc_id * adev->gfx.num_gfx_rings;
> + for (i = 0; i < adev->gfx.num_gfx_rings; i++)
> kiq->pmf->kiq_unmap_queues(kiq_ring,
>&adev->gfx.gfx_ring[i],
>PREEMPT_QUEUES, 0, 0);
> - }
> }
>
> if (adev->gfx.kiq[0].ring.sched.ready && !adev->job_hang)
> @@ -627,7 +621,7 @@ int amdgpu_gfx_enable_kgq(struct amdgpu_device *adev, int
> xcc_id)
> {
> struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
> struct amdgpu_ring *kiq_ring = &kiq->ring;
> - int r, i, j;
> + int r, i;
>
> if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
> return -EINVAL;
> @@ -645,11 +639,9 @@ int amdgpu_gfx_enable_kgq(struct amdgpu_device *adev,
> int xcc_id)
> return r;
> }
>
> - for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
> - j = i + xcc_id * adev->gfx.num_gfx_rings;
> + for (i = 0; i < adev->gfx.num_gfx_rings; i++)
> kiq->pmf->kiq_map_queues(kiq_ring,
> &adev->gfx.gfx_ring[i]);
> - }
> }
>
> r = amdgpu_ring_test_helper(kiq_ring);
> --
> 2.25.1
>
[PATCH] drm/amdgpu: Remove unused variable in amdgpu_gfx.c
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c: In function ‘amdgpu_gfx_disable_kcq’:
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c:497:6: warning: variable ‘j’ set but
not used [-Wunused-but-set-variable]
497 | int j;
| ^
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c: In function ‘amdgpu_gfx_disable_kgq’:
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c:528:6: warning: variable ‘j’ set but
not used [-Wunused-but-set-variable]
528 | int j;
| ^
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c: In function ‘amdgpu_gfx_enable_kgq’:
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c:630:12: warning: variable ‘j’ set but
not used [-Wunused-but-set-variable]
630 | int r, i, j;
|
This variable is not used so remove them.
Cc: Alex Deucher
Cc: Christian König
Signed-off-by: Srinivasan Shanmugam
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 16
1 file changed, 4 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index 2b4bf6c11ae4..c7c16d6c476a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -494,7 +494,6 @@ int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev, int
xcc_id)
struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
struct amdgpu_ring *kiq_ring = &kiq->ring;
int i, r = 0;
- int j;
if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
return -EINVAL;
@@ -506,12 +505,10 @@ int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev,
int xcc_id)
return -ENOMEM;
}
- for (i = 0; i < adev->gfx.num_compute_rings; i++) {
- j = i + xcc_id * adev->gfx.num_compute_rings;
+ for (i = 0; i < adev->gfx.num_compute_rings; i++)
kiq->pmf->kiq_unmap_queues(kiq_ring,
&adev->gfx.compute_ring[i],
RESET_QUEUES, 0, 0);
- }
if (kiq_ring->sched.ready && !adev->job_hang)
r = amdgpu_ring_test_helper(kiq_ring);
@@ -525,7 +522,6 @@ int amdgpu_gfx_disable_kgq(struct amdgpu_device *adev, int
xcc_id)
struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
struct amdgpu_ring *kiq_ring = &kiq->ring;
int i, r = 0;
- int j;
if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
return -EINVAL;
@@ -538,12 +534,10 @@ int amdgpu_gfx_disable_kgq(struct amdgpu_device *adev,
int xcc_id)
return -ENOMEM;
}
- for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
- j = i + xcc_id * adev->gfx.num_gfx_rings;
+ for (i = 0; i < adev->gfx.num_gfx_rings; i++)
kiq->pmf->kiq_unmap_queues(kiq_ring,
&adev->gfx.gfx_ring[i],
PREEMPT_QUEUES, 0, 0);
- }
}
if (adev->gfx.kiq[0].ring.sched.ready && !adev->job_hang)
@@ -627,7 +621,7 @@ int amdgpu_gfx_enable_kgq(struct amdgpu_device *adev, int
xcc_id)
{
struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
struct amdgpu_ring *kiq_ring = &kiq->ring;
- int r, i, j;
+ int r, i;
if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
return -EINVAL;
@@ -645,11 +639,9 @@ int amdgpu_gfx_enable_kgq(struct amdgpu_device *adev, int
xcc_id)
return r;
}
- for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
- j = i + xcc_id * adev->gfx.num_gfx_rings;
+ for (i = 0; i < adev->gfx.num_gfx_rings; i++)
kiq->pmf->kiq_map_queues(kiq_ring,
&adev->gfx.gfx_ring[i]);
- }
}
r = amdgpu_ring_test_helper(kiq_ring);
--
2.25.1
Re: [PATCH] drm/amdkfd: Set event interrupt class for GFX 9.4.3
[AMD Official Use Only - General] Acked-by: Alex Deucher From: Joshi, Mukul Sent: Tuesday, May 23, 2023 2:12 PM To: amd-gfx@lists.freedesktop.org Cc: Kuehling, Felix ; Deucher, Alexander ; Joshi, Mukul Subject: [PATCH] drm/amdkfd: Set event interrupt class for GFX 9.4.3 Fix the warning during driver load because the event interrupt class is not set for GFX9.4.3. Signed-off-by: Mukul Joshi --- drivers/gpu/drm/amd/amdkfd/kfd_device.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index e92b93b2c14c..862a50f7b490 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -139,6 +139,7 @@ static void kfd_device_info_set_event_interrupt_class(struct kfd_dev *kfd) case IP_VERSION(9, 4, 0): /* VEGA20 */ case IP_VERSION(9, 4, 1): /* ARCTURUS */ case IP_VERSION(9, 4, 2): /* ALDEBARAN */ + case IP_VERSION(9, 4, 3): /* GC 9.4.3 */ case IP_VERSION(10, 3, 1): /* VANGOGH */ case IP_VERSION(10, 3, 3): /* YELLOW_CARP */ case IP_VERSION(10, 3, 6): /* GC 10.3.6 */ -- 2.35.1
[PATCH] drm/amdkfd: Set event interrupt class for GFX 9.4.3
Fix the warning during driver load because the event interrupt class is not set for GFX9.4.3. Signed-off-by: Mukul Joshi --- drivers/gpu/drm/amd/amdkfd/kfd_device.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index e92b93b2c14c..862a50f7b490 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -139,6 +139,7 @@ static void kfd_device_info_set_event_interrupt_class(struct kfd_dev *kfd) case IP_VERSION(9, 4, 0): /* VEGA20 */ case IP_VERSION(9, 4, 1): /* ARCTURUS */ case IP_VERSION(9, 4, 2): /* ALDEBARAN */ + case IP_VERSION(9, 4, 3): /* GC 9.4.3 */ case IP_VERSION(10, 3, 1): /* VANGOGH */ case IP_VERSION(10, 3, 3): /* YELLOW_CARP */ case IP_VERSION(10, 3, 6): /* GC 10.3.6 */ -- 2.35.1
Re: [PATCH 1/2] Revert "drm/amd/display: Block optimize on consecutive FAMS enables"
On 5/22/23 09:08, Michel Dänzer wrote:
From: Michel Dänzer
This reverts commit ce560ac40272a5c8b5b68a9d63a75edd9e66aed2.
It depends on its parent commit, which we want to revert.
Signed-off-by: Michel Dänzer
I have applied the series, thanks!
---
.../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 3 ---
.../drm/amd/display/dc/dcn30/dcn30_hwseq.c| 22 +++
2 files changed, 3 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 422fbf79da64..6ce10fd4bb1a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -2117,9 +2117,6 @@ void dcn20_optimize_bandwidth(
dc_dmub_srv_p_state_delegate(dc,
true, context);
context->bw_ctx.bw.dcn.clk.p_state_change_support = true;
- dc->clk_mgr->clks.fw_based_mclk_switching = true;
- } else {
- dc->clk_mgr->clks.fw_based_mclk_switching = false;
}
dc->clk_mgr->funcs->update_clocks(
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
index 8263a07f265f..0411867654dd 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
@@ -983,13 +983,9 @@ void dcn30_set_disp_pattern_generator(const struct dc *dc,
}
void dcn30_prepare_bandwidth(struct dc *dc,
- struct dc_state *context)
+ struct dc_state *context)
{
- bool p_state_change_support =
context->bw_ctx.bw.dcn.clk.p_state_change_support;
- /* Any transition into an FPO config should disable MCLK switching
first to avoid
-* driver and FW P-State synchronization issues.
-*/
- if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching ||
dc->clk_mgr->clks.fw_based_mclk_switching) {
+ if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {
dc->optimized_required = true;
context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
}
@@ -1000,19 +996,7 @@ void dcn30_prepare_bandwidth(struct dc *dc,
dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr,
dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries -
1].memclk_mhz);
dcn20_prepare_bandwidth(dc, context);
- /*
-* enabled -> enabled: do not disable
-* enabled -> disabled: disable
-* disabled -> enabled: don't care
-* disabled -> disabled: don't care
-*/
- if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching)
- dc_dmub_srv_p_state_delegate(dc, false, context);
- if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dc->clk_mgr->clks.fw_based_mclk_switching) {
- /* After disabling P-State, restore the original value to
ensure we get the correct P-State
-* on the next optimize. */
- context->bw_ctx.bw.dcn.clk.p_state_change_support =
p_state_change_support;
- }
+ dc_dmub_srv_p_state_delegate(dc, false, context);
}
--
Hamza
Re: [PATCH 2/2] Revert "drm/amd/display: Do not set drr on pipe commit"
[AMD Official Use Only - General]
Yep, we shall, thanks Alex.
--
Regards,
Jay
From: Alex Deucher
Sent: Tuesday, May 23, 2023 11:47 AM
To: Pillai, Aurabindo ; Mahfooz, Hamza
Cc: Michel Dänzer ; Deucher, Alexander
; Chalmers, Wesley ; Li,
Sun peng (Leo) ; Zhuo, Qingqing (Lillian)
; Siqueira, Rodrigo ;
amd-gfx@lists.freedesktop.org ; Wentland, Harry
Subject: Re: [PATCH 2/2] Revert "drm/amd/display: Do not set drr on pipe commit"
Acked-by: Alex Deucher
for the series.
Jay, I assume you or Hamza will pick these up?
Thanks,
Alex
On Tue, May 23, 2023 at 11:31 AM Aurabindo Pillai
wrote:
>
> Reviewed-by: Aurabindo Pillai
>
> On 5/22/23 09:08, Michel Dänzer wrote:
> > From: Michel Dänzer
> >
> > This reverts commit 474f01015ffdb74e01c2eb3584a2822c64e7b2be.
> >
> > Caused a regression:
> >
> > Samsung Odyssey Neo G9, running at 5120x1440@240/VRR, connected to Navi
> > 21 via DisplayPort, blanks and the GPU hangs while starting the Steam
> > game Assetto Corsa Competizione (via Proton 7.0).
> >
> > Example dmesg excerpt:
> >
> > amdgpu :0c:00.0: [drm] ERROR [CRTC:82:crtc-0] flip_done timed out
> > NMI watchdog: Watchdog detected hard LOCKUP on cpu 6
> > [...]
> > RIP: 0010:amdgpu_device_rreg.part.0+0x2f/0xf0 [amdgpu]
> > Code: 41 54 44 8d 24 b5 00 00 00 00 55 89 f5 53 48 89 fb 4c 3b a7 60 0b 00
> > 00 73 6a 83 e2 02 74 29 4c 03 a3 68 0b 00 00 45 8b 24 24 <48> 8b 43 08 0f
> > b7 70 3e 66 90 44 89 e0 5b 5d 41 5c 31 d2 31 c9 31
> > RSP: :b39a119dfb88 EFLAGS: 0086
> > RAX: c0eb96a0 RBX: 9e7963dc RCX: 7fff
> > RDX: RSI: 4ff6 RDI: 9e7963dc
> > RBP: 4ff6 R08: b39a119dfc40 R09: 0010
> > R10: b39a119dfc40 R11: b39a119dfc44 R12: 000e05ae
> > R13: R14: 9e7963dc0010 R15:
> > FS: 1012f6c0() GS:9e805eb8()
> > knlGS:7fd4
> > CS: 0010 DS: ES: CR0: 80050033
> > CR2: 461ca000 CR3: 0002a8a2 CR4: 00350ee0
> > Call Trace:
> >
> > dm_read_reg_func+0x37/0xc0 [amdgpu]
> > generic_reg_get2+0x22/0x60 [amdgpu]
> > optc1_get_crtc_scanoutpos+0x6a/0xc0 [amdgpu]
> > dc_stream_get_scanoutpos+0x74/0x90 [amdgpu]
> > dm_crtc_get_scanoutpos+0x82/0xf0 [amdgpu]
> > amdgpu_display_get_crtc_scanoutpos+0x91/0x190 [amdgpu]
> > ? dm_read_reg_func+0x37/0xc0 [amdgpu]
> > amdgpu_get_vblank_counter_kms+0xb4/0x1a0 [amdgpu]
> > dm_pflip_high_irq+0x213/0x2f0 [amdgpu]
> > amdgpu_dm_irq_handler+0x8a/0x200 [amdgpu]
> > amdgpu_irq_dispatch+0xd4/0x220 [amdgpu]
> > amdgpu_ih_process+0x7f/0x110 [amdgpu]
> > amdgpu_irq_handler+0x1f/0x70 [amdgpu]
> > __handle_irq_event_percpu+0x46/0x1b0
> > handle_irq_event+0x34/0x80
> > handle_edge_irq+0x9f/0x240
> > __common_interrupt+0x66/0x110
> > common_interrupt+0x5c/0xd0
> > asm_common_interrupt+0x22/0x40
> >
> > Signed-off-by: Michel Dänzer
> > ---
> > drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 6 --
> > drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c | 7 ---
> > 2 files changed, 13 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
> > b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
> > index 6ce10fd4bb1a..5403e9399a46 100644
> > --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
> > +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
> > @@ -2113,12 +2113,6 @@ void dcn20_optimize_bandwidth(
> > if (hubbub->funcs->program_compbuf_size)
> > hubbub->funcs->program_compbuf_size(hubbub,
> > context->bw_ctx.bw.dcn.compbuf_size_kb, true);
> >
> > - if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {
> > - dc_dmub_srv_p_state_delegate(dc,
> > - true, context);
> > - context->bw_ctx.bw.dcn.clk.p_state_change_support = true;
> > - }
> > -
> > dc->clk_mgr->funcs->update_clocks(
> > dc->clk_mgr,
> > context,
> > diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> > b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> > index 0411867654dd..0e071fbc9154 100644
> > --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> > +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> > @@ -985,18 +985,11 @@ void dcn30_set_disp_pattern_generator(const struct dc
> > *dc,
> > void dcn30_prepare_bandwidth(struct dc *dc,
> > struct dc_state *context)
> > {
> > - if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {
> > - dc->optimized_required = true;
> > - context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
> > - }
> > -
> > if (dc->clk_mgr->dc_mode_softmax_enabled)
> > if (dc->clk_mgr->clks.dramclk_khz <=
> > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 &&
> > context->bw_ctx
Re: [PATCH] drm/amdgpu/vcn: Modify mismatched function name
Applied. Thanks! Alex On Mon, May 22, 2023 at 11:32 PM Jiapeng Chong wrote: > > No functional modification involved. > > drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c:374: warning: expecting prototype for > vcn_v4_0_mc_resume_dpg_mode(). Prototype was for > vcn_v4_0_3_mc_resume_dpg_mode() instead. > drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c:631: warning: expecting prototype for > vcn_v4_0_enable_clock_gating(). Prototype was for > vcn_v4_0_3_enable_clock_gating() instead. > > Reported-by: Abaci Robot > Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=5284 > Signed-off-by: Jiapeng Chong > --- > drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c > b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c > index 339842382a1e..5d67b8b8a3d6 100644 > --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c > +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c > @@ -362,7 +362,7 @@ static void vcn_v4_0_3_mc_resume(struct amdgpu_device > *adev, int inst_idx) > } > > /** > - * vcn_v4_0_mc_resume_dpg_mode - memory controller programming for dpg mode > + * vcn_v4_0_3_mc_resume_dpg_mode - memory controller programming for dpg mode > * > * @adev: amdgpu_device pointer > * @inst_idx: instance number index > @@ -620,7 +620,7 @@ static void > vcn_v4_0_3_disable_clock_gating_dpg_mode(struct amdgpu_device *adev, > } > > /** > - * vcn_v4_0_enable_clock_gating - enable VCN clock gating > + * vcn_v4_0_3_enable_clock_gating - enable VCN clock gating > * > * @adev: amdgpu_device pointer > * @inst_idx: instance number > -- > 2.20.1.7.g153144c >
Re: [PATCH] drm/amdgpu: Modify mismatched function name
Applied. Thanks! On Mon, May 22, 2023 at 11:17 PM Jiapeng Chong wrote: > > No functional modification involved. > > drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c:426: warning: expecting prototype > for sdma_v4_4_2_gfx_stop(). Prototype was for sdma_v4_4_2_inst_gfx_stop() > instead. > drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c:457: warning: expecting prototype > for sdma_v4_4_2_rlc_stop(). Prototype was for sdma_v4_4_2_inst_rlc_stop() > instead. > drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c:470: warning: expecting prototype > for sdma_v4_4_2_page_stop(). Prototype was for sdma_v4_4_2_inst_page_stop() > instead. > drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c:506: warning: expecting prototype > for sdma_v4_4_2_ctx_switch_enable(). Prototype was for > sdma_v4_4_2_inst_ctx_switch_enable() instead. > drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c:561: warning: expecting prototype > for sdma_v4_4_2_enable(). Prototype was for sdma_v4_4_2_inst_enable() instead. > drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c:798: warning: expecting prototype > for sdma_v4_4_2_rlc_resume(). Prototype was for sdma_v4_4_2_inst_rlc_resume() > instead. > drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c:814: warning: expecting prototype > for sdma_v4_4_2_load_microcode(). Prototype was for > sdma_v4_4_2_inst_load_microcode() instead. > > Reported-by: Abaci Robot > Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=5283 > Signed-off-by: Jiapeng Chong > --- > drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 14 +++--- > 1 file changed, 7 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c > b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c > index bf47eb33c12e..590b08585901 100644 > --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c > +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c > @@ -415,7 +415,7 @@ static void sdma_v4_4_2_ring_emit_fence(struct > amdgpu_ring *ring, u64 addr, u64 > > > /** > - * sdma_v4_4_2_gfx_stop - stop the gfx async dma engines > + * sdma_v4_4_2_inst_gfx_stop - stop the gfx async dma engines > * > * @adev: amdgpu_device pointer > * > @@ -446,7 +446,7 @@ static void sdma_v4_4_2_inst_gfx_stop(struct > amdgpu_device *adev, > } > > /** > - * sdma_v4_4_2_rlc_stop - stop the compute async dma engines > + * sdma_v4_4_2_inst_rlc_stop - stop the compute async dma engines > * > * @adev: amdgpu_device pointer > * > @@ -459,7 +459,7 @@ static void sdma_v4_4_2_inst_rlc_stop(struct > amdgpu_device *adev, > } > > /** > - * sdma_v4_4_2_page_stop - stop the page async dma engines > + * sdma_v4_4_2_inst_page_stop - stop the page async dma engines > * > * @adev: amdgpu_device pointer > * > @@ -494,7 +494,7 @@ static void sdma_v4_4_2_inst_page_stop(struct > amdgpu_device *adev, > } > > /** > - * sdma_v4_4_2_ctx_switch_enable - stop the async dma engines context switch > + * sdma_v4_4_2_inst_ctx_switch_enable - stop the async dma engines context > switch > * > * @adev: amdgpu_device pointer > * @enable: enable/disable the DMA MEs context switch. > @@ -548,7 +548,7 @@ static void sdma_v4_4_2_inst_ctx_switch_enable(struct > amdgpu_device *adev, > } > > /** > - * sdma_v4_4_2_enable - stop the async dma engines > + * sdma_v4_4_2_inst_enable - stop the async dma engines > * > * @adev: amdgpu_device pointer > * @enable: enable/disable the DMA MEs. > @@ -786,7 +786,7 @@ static void sdma_v4_4_2_init_pg(struct amdgpu_device > *adev) > } > > /** > - * sdma_v4_4_2_rlc_resume - setup and start the async dma engines > + * sdma_v4_4_2_inst_rlc_resume - setup and start the async dma engines > * > * @adev: amdgpu_device pointer > * > @@ -802,7 +802,7 @@ static int sdma_v4_4_2_inst_rlc_resume(struct > amdgpu_device *adev, > } > > /** > - * sdma_v4_4_2_load_microcode - load the sDMA ME ucode > + * sdma_v4_4_2_inst_load_microcode - load the sDMA ME ucode > * > * @adev: amdgpu_device pointer > * > -- > 2.20.1.7.g153144c >
Re: [PATCH] drm/amdgpu: Remove duplicate include
Applied. Thanks! On Mon, May 22, 2023 at 10:18 PM Jiapeng Chong wrote: > > ./drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c: amdgpu_xcp.h is included more than > once. > > Reported-by: Abaci Robot > Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=5281 > Signed-off-by: Jiapeng Chong > --- > drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c > index e5cfb3adb3b3..7fb2d38b010a 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c > @@ -23,7 +23,6 @@ > #include > > #include "amdgpu.h" > -#include "amdgpu_xcp.h" > #include "amdgpu_gfx.h" > #include "soc15.h" > #include "soc15d.h" > -- > 2.20.1.7.g153144c >
Re: [PATCH 3/3] drm/amdgpu: use amdxcp platform device as spatial partition
Series is:
Acked-by: Alex Deucher
On Tue, May 23, 2023 at 9:29 AM James Zhu wrote:
>
> Use amdxcp platform device as spatial partition device.
>
> Signed-off-by: James Zhu
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 ++
> drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c | 12 ++--
> 2 files changed, 8 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index 3d91e123f9bd..852c98dd40ea 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -51,6 +51,7 @@
> #include "amdgpu_ras.h"
> #include "amdgpu_xgmi.h"
> #include "amdgpu_reset.h"
> +#include "../amdxcp/amdgpu_xcp_drv.h"
>
> /*
> * KMS wrapper.
> @@ -2944,6 +2945,7 @@ static void __exit amdgpu_exit(void)
> amdgpu_sync_fini();
> amdgpu_fence_slab_fini();
> mmu_notifier_synchronize();
> + amdgpu_xcp_drv_release();
> }
>
> module_init(amdgpu_init);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c
> index 6ab5713ff741..9e3a7efaf584 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c
> @@ -25,6 +25,7 @@
> #include "amdgpu_drv.h"
>
> #include
> +#include "../amdxcp/amdgpu_xcp_drv.h"
>
> static int __amdgpu_xcp_run(struct amdgpu_xcp_mgr *xcp_mgr,
> struct amdgpu_xcp_ip *xcp_ip, int xcp_state)
> @@ -228,21 +229,20 @@ static int amdgpu_xcp_dev_alloc(struct amdgpu_device
> *adev)
> struct drm_device *p_ddev;
> struct pci_dev *pdev;
> struct drm_device *ddev;
> - int i;
> + int i, ret;
>
> pdev = adev->pdev;
> ddev = adev_to_drm(adev);
>
> for (i = 0; i < MAX_XCP; i++) {
> - p_ddev = drm_dev_alloc(&amdgpu_partition_driver,
> - &pci_upstream_bridge(pdev)->dev);
> - if (IS_ERR(p_ddev))
> - return PTR_ERR(p_ddev);
> + ret = amdgpu_xcp_drm_dev_alloc(&p_ddev);
> + if (ret)
> + return ret;
>
> /* Redirect all IOCTLs to the primary device */
> adev->xcp_mgr->xcp[i].rdev = p_ddev->render->dev;
> adev->xcp_mgr->xcp[i].pdev = p_ddev->primary->dev;
> - adev->xcp_mgr->xcp[i].driver = p_ddev->driver;
> + adev->xcp_mgr->xcp[i].driver = (struct drm_driver
> *)p_ddev->driver;
> adev->xcp_mgr->xcp[i].vma_offset_manager =
> p_ddev->vma_offset_manager;
> p_ddev->render->dev = ddev;
> p_ddev->primary->dev = ddev;
> --
> 2.34.1
>
Re: [PATCH 2/2] Revert "drm/amd/display: Do not set drr on pipe commit"
Acked-by: Alex Deucher
for the series.
Jay, I assume you or Hamza will pick these up?
Thanks,
Alex
On Tue, May 23, 2023 at 11:31 AM Aurabindo Pillai
wrote:
>
> Reviewed-by: Aurabindo Pillai
>
> On 5/22/23 09:08, Michel Dänzer wrote:
> > From: Michel Dänzer
> >
> > This reverts commit 474f01015ffdb74e01c2eb3584a2822c64e7b2be.
> >
> > Caused a regression:
> >
> > Samsung Odyssey Neo G9, running at 5120x1440@240/VRR, connected to Navi
> > 21 via DisplayPort, blanks and the GPU hangs while starting the Steam
> > game Assetto Corsa Competizione (via Proton 7.0).
> >
> > Example dmesg excerpt:
> >
> > amdgpu :0c:00.0: [drm] ERROR [CRTC:82:crtc-0] flip_done timed out
> > NMI watchdog: Watchdog detected hard LOCKUP on cpu 6
> > [...]
> > RIP: 0010:amdgpu_device_rreg.part.0+0x2f/0xf0 [amdgpu]
> > Code: 41 54 44 8d 24 b5 00 00 00 00 55 89 f5 53 48 89 fb 4c 3b a7 60 0b 00
> > 00 73 6a 83 e2 02 74 29 4c 03 a3 68 0b 00 00 45 8b 24 24 <48> 8b 43 08 0f
> > b7 70 3e 66 90 44 89 e0 5b 5d 41 5c 31 d2 31 c9 31
> > RSP: :b39a119dfb88 EFLAGS: 0086
> > RAX: c0eb96a0 RBX: 9e7963dc RCX: 7fff
> > RDX: RSI: 4ff6 RDI: 9e7963dc
> > RBP: 4ff6 R08: b39a119dfc40 R09: 0010
> > R10: b39a119dfc40 R11: b39a119dfc44 R12: 000e05ae
> > R13: R14: 9e7963dc0010 R15:
> > FS: 1012f6c0() GS:9e805eb8()
> > knlGS:7fd4
> > CS: 0010 DS: ES: CR0: 80050033
> > CR2: 461ca000 CR3: 0002a8a2 CR4: 00350ee0
> > Call Trace:
> >
> > dm_read_reg_func+0x37/0xc0 [amdgpu]
> > generic_reg_get2+0x22/0x60 [amdgpu]
> > optc1_get_crtc_scanoutpos+0x6a/0xc0 [amdgpu]
> > dc_stream_get_scanoutpos+0x74/0x90 [amdgpu]
> > dm_crtc_get_scanoutpos+0x82/0xf0 [amdgpu]
> > amdgpu_display_get_crtc_scanoutpos+0x91/0x190 [amdgpu]
> > ? dm_read_reg_func+0x37/0xc0 [amdgpu]
> > amdgpu_get_vblank_counter_kms+0xb4/0x1a0 [amdgpu]
> > dm_pflip_high_irq+0x213/0x2f0 [amdgpu]
> > amdgpu_dm_irq_handler+0x8a/0x200 [amdgpu]
> > amdgpu_irq_dispatch+0xd4/0x220 [amdgpu]
> > amdgpu_ih_process+0x7f/0x110 [amdgpu]
> > amdgpu_irq_handler+0x1f/0x70 [amdgpu]
> > __handle_irq_event_percpu+0x46/0x1b0
> > handle_irq_event+0x34/0x80
> > handle_edge_irq+0x9f/0x240
> > __common_interrupt+0x66/0x110
> > common_interrupt+0x5c/0xd0
> > asm_common_interrupt+0x22/0x40
> >
> > Signed-off-by: Michel Dänzer
> > ---
> > drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 6 --
> > drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c | 7 ---
> > 2 files changed, 13 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
> > b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
> > index 6ce10fd4bb1a..5403e9399a46 100644
> > --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
> > +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
> > @@ -2113,12 +2113,6 @@ void dcn20_optimize_bandwidth(
> > if (hubbub->funcs->program_compbuf_size)
> > hubbub->funcs->program_compbuf_size(hubbub,
> > context->bw_ctx.bw.dcn.compbuf_size_kb, true);
> >
> > - if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {
> > - dc_dmub_srv_p_state_delegate(dc,
> > - true, context);
> > - context->bw_ctx.bw.dcn.clk.p_state_change_support = true;
> > - }
> > -
> > dc->clk_mgr->funcs->update_clocks(
> > dc->clk_mgr,
> > context,
> > diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> > b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> > index 0411867654dd..0e071fbc9154 100644
> > --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> > +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> > @@ -985,18 +985,11 @@ void dcn30_set_disp_pattern_generator(const struct dc
> > *dc,
> > void dcn30_prepare_bandwidth(struct dc *dc,
> > struct dc_state *context)
> > {
> > - if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {
> > - dc->optimized_required = true;
> > - context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
> > - }
> > -
> > if (dc->clk_mgr->dc_mode_softmax_enabled)
> > if (dc->clk_mgr->clks.dramclk_khz <=
> > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 &&
> > context->bw_ctx.bw.dcn.clk.dramclk_khz >
> > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)
> > dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr,
> > dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries
> > - 1].memclk_mhz);
> >
> > dcn20_prepare_bandwidth(dc, context);
> > -
> > - dc_dmub_srv_p_state_delegate(dc, false, context);
> > }
> >
Re: [PATCH 2/2] Revert "drm/amd/display: Do not set drr on pipe commit"
Reviewed-by: Aurabindo Pillai
On 5/22/23 09:08, Michel Dänzer wrote:
> From: Michel Dänzer
>
> This reverts commit 474f01015ffdb74e01c2eb3584a2822c64e7b2be.
>
> Caused a regression:
>
> Samsung Odyssey Neo G9, running at 5120x1440@240/VRR, connected to Navi
> 21 via DisplayPort, blanks and the GPU hangs while starting the Steam
> game Assetto Corsa Competizione (via Proton 7.0).
>
> Example dmesg excerpt:
>
> amdgpu :0c:00.0: [drm] ERROR [CRTC:82:crtc-0] flip_done timed out
> NMI watchdog: Watchdog detected hard LOCKUP on cpu 6
> [...]
> RIP: 0010:amdgpu_device_rreg.part.0+0x2f/0xf0 [amdgpu]
> Code: 41 54 44 8d 24 b5 00 00 00 00 55 89 f5 53 48 89 fb 4c 3b a7 60 0b 00
> 00 73 6a 83 e2 02 74 29 4c 03 a3 68 0b 00 00 45 8b 24 24 <48> 8b 43 08 0f b7
> 70 3e 66 90 44 89 e0 5b 5d 41 5c 31 d2 31 c9 31
> RSP: :b39a119dfb88 EFLAGS: 0086
> RAX: c0eb96a0 RBX: 9e7963dc RCX: 7fff
> RDX: RSI: 4ff6 RDI: 9e7963dc
> RBP: 4ff6 R08: b39a119dfc40 R09: 0010
> R10: b39a119dfc40 R11: b39a119dfc44 R12: 000e05ae
> R13: R14: 9e7963dc0010 R15:
> FS: 1012f6c0() GS:9e805eb8() knlGS:7fd4
> CS: 0010 DS: ES: CR0: 80050033
> CR2: 461ca000 CR3: 0002a8a2 CR4: 00350ee0
> Call Trace:
>
> dm_read_reg_func+0x37/0xc0 [amdgpu]
> generic_reg_get2+0x22/0x60 [amdgpu]
> optc1_get_crtc_scanoutpos+0x6a/0xc0 [amdgpu]
> dc_stream_get_scanoutpos+0x74/0x90 [amdgpu]
> dm_crtc_get_scanoutpos+0x82/0xf0 [amdgpu]
> amdgpu_display_get_crtc_scanoutpos+0x91/0x190 [amdgpu]
> ? dm_read_reg_func+0x37/0xc0 [amdgpu]
> amdgpu_get_vblank_counter_kms+0xb4/0x1a0 [amdgpu]
> dm_pflip_high_irq+0x213/0x2f0 [amdgpu]
> amdgpu_dm_irq_handler+0x8a/0x200 [amdgpu]
> amdgpu_irq_dispatch+0xd4/0x220 [amdgpu]
> amdgpu_ih_process+0x7f/0x110 [amdgpu]
> amdgpu_irq_handler+0x1f/0x70 [amdgpu]
> __handle_irq_event_percpu+0x46/0x1b0
> handle_irq_event+0x34/0x80
> handle_edge_irq+0x9f/0x240
> __common_interrupt+0x66/0x110
> common_interrupt+0x5c/0xd0
> asm_common_interrupt+0x22/0x40
>
> Signed-off-by: Michel Dänzer
> ---
> drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 6 --
> drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c | 7 ---
> 2 files changed, 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
> b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
> index 6ce10fd4bb1a..5403e9399a46 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
> @@ -2113,12 +2113,6 @@ void dcn20_optimize_bandwidth(
> if (hubbub->funcs->program_compbuf_size)
> hubbub->funcs->program_compbuf_size(hubbub,
> context->bw_ctx.bw.dcn.compbuf_size_kb, true);
>
> - if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {
> - dc_dmub_srv_p_state_delegate(dc,
> - true, context);
> - context->bw_ctx.bw.dcn.clk.p_state_change_support = true;
> - }
> -
> dc->clk_mgr->funcs->update_clocks(
> dc->clk_mgr,
> context,
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> index 0411867654dd..0e071fbc9154 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> @@ -985,18 +985,11 @@ void dcn30_set_disp_pattern_generator(const struct dc
> *dc,
> void dcn30_prepare_bandwidth(struct dc *dc,
> struct dc_state *context)
> {
> - if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {
> - dc->optimized_required = true;
> - context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
> - }
> -
> if (dc->clk_mgr->dc_mode_softmax_enabled)
> if (dc->clk_mgr->clks.dramclk_khz <=
> dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 &&
> context->bw_ctx.bw.dcn.clk.dramclk_khz >
> dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)
> dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr,
> dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries
> - 1].memclk_mhz);
>
> dcn20_prepare_bandwidth(dc, context);
> -
> - dc_dmub_srv_p_state_delegate(dc, false, context);
> }
>
Re: [PATCH] drm/amd/pm: reverse mclk and fclk clocks levels for renoir
[AMD Official Use Only - General]
Reviewed-by: Alex Deucher
From: Huang, Tim
Sent: Tuesday, May 23, 2023 1:02 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Zhang, Yifan
; Huang, Tim
Subject: [PATCH] drm/amd/pm: reverse mclk and fclk clocks levels for renoir
This patch reverses the DPM clocks levels output of pp_dpm_mclk
and pp_dpm_fclk for renoir.
On dGPUs and older APUs we expose the levels from lowest clocks
to highest clocks. But for some APUs, the clocks levels are
given the reversed orders by PMFW. Like the memory DPM clocks
that are exposed by pp_dpm_mclk.
It's not intuitive that they are reversed on these APUs. All tools
and software that talks to the driver then has to know different ways
to interpret the data depending on the asic.
So we need to reverse them to expose the clocks levels from the
driver consistently.
Signed-off-by: Tim Huang
---
drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
index 5cdc07165480..8a8ba25c9ad7 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
@@ -494,7 +494,7 @@ static int renoir_set_fine_grain_gfx_freq_parameters(struct
smu_context *smu)
static int renoir_print_clk_levels(struct smu_context *smu,
enum smu_clk_type clk_type, char *buf)
{
- int i, size = 0, ret = 0;
+ int i, idx, size = 0, ret = 0;
uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0;
SmuMetrics_t metrics;
struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
@@ -594,7 +594,8 @@ static int renoir_print_clk_levels(struct smu_context *smu,
case SMU_VCLK:
case SMU_DCLK:
for (i = 0; i < count; i++) {
- ret = renoir_get_dpm_clk_limited(smu, clk_type, i,
&value);
+ idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ?
(count - i - 1) : i;
+ ret = renoir_get_dpm_clk_limited(smu, clk_type, idx,
&value);
if (ret)
return ret;
if (!value)
--
2.34.1
Re: [PATCH] drm/amd/display: avoid calling missing .resync_fifo_dccg_dio()
On 5/23/23 04:34, Arnd Bergmann wrote:
From: Arnd Bergmann
The .resync_fifo_dccg_dio() callback pointer was added in an #ifdef block,
but is called unconditionally:
drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_hw_sequencer.c:2292:31:
error: 'struct hwseq_private_funcs' has no member named 'resync_fifo_dccg_dio'
Add the same #ifdef around the caller as well.
Fixes: 6354b0dc3a7a ("drm/amd/display: Trigger DIO FIFO resync on commit
streams")
Signed-off-by: Arnd Bergmann
Applied, thanks!
---
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index c6fe2c00aedb..d4cacb8df631 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -2289,8 +2289,10 @@ enum dc_status dce110_apply_ctx_to_hw(
if (DC_OK != status)
return status;
+#ifdef CONFIG_DRM_AMD_DC_FP
if (hws->funcs.resync_fifo_dccg_dio)
hws->funcs.resync_fifo_dccg_dio(hws, dc, context);
+#endif
}
if (dc->fbc_compressor)
--
Hamza
Re: [PATCH] drm/amd/display: remove unused variables res_create_maximus_funcs and debug_defaults_diags
On 5/23/23 07:49, Tom Rix wrote:
gcc with W=1 reports
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:1069:43: error:
‘res_create_maximus_funcs’ defined but not used
[-Werror=unused-const-variable=]
1069 | static const struct resource_create_funcs res_create_maximus_funcs = {
| ^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:727:38: error:
‘debug_defaults_diags’ defined but not used [-Werror=unused-const-variable=]
727 | static const struct dc_debug_options debug_defaults_diags = {
| ^~~~
These variables are not used so remove them.
Signed-off-by: Tom Rix
Fixes: 00df97e1df57 ("drm/amd/display: Clean FPGA code in dc")
Applied, thanks!
---
.../drm/amd/display/dc/dcn20/dcn20_resource.c | 23 ---
1 file changed, 23 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 7dcae3183e07..6ef7e2634991 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -724,22 +724,6 @@ static const struct dc_debug_options debug_defaults_drv = {
.underflow_assert_delay_us = 0x,
};
-static const struct dc_debug_options debug_defaults_diags = {
- .disable_dmcu = false,
- .force_abm_enable = false,
- .timing_trace = true,
- .clock_trace = true,
- .disable_dpp_power_gate = true,
- .disable_hubp_power_gate = true,
- .disable_clock_gate = true,
- .disable_pplib_clock_request = true,
- .disable_pplib_wm_range = true,
- .disable_stutter = true,
- .scl_reset_length10 = true,
- .underflow_assert_delay_us = 0x,
- .enable_tri_buf = true,
-};
-
void dcn20_dpp_destroy(struct dpp **dpp)
{
kfree(TO_DCN20_DPP(*dpp));
@@ -1066,13 +1050,6 @@ static const struct resource_create_funcs
res_create_funcs = {
.create_hwseq = dcn20_hwseq_create,
};
-static const struct resource_create_funcs res_create_maximus_funcs = {
- .read_dce_straps = NULL,
- .create_audio = NULL,
- .create_stream_encoder = NULL,
- .create_hwseq = dcn20_hwseq_create,
-};
-
static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
void dcn20_clock_source_destroy(struct clock_source **clk_src)
--
Hamza
Re: [PATCH] drm/amdgpu: add the accelerator pcie class
On Tue, May 23, 2023 at 5:25 AM Christoph Hellwig wrote:
>
> On Tue, May 23, 2023 at 12:02:32PM +0800, Shiwu Zhang wrote:
> > + { PCI_DEVICE(0x1002, PCI_ANY_ID),
> > + .class = PCI_CLASS_ACCELERATOR_PROCESSING << 8,
> > + .class_mask = 0xff,
> > + .driver_data = CHIP_IP_DISCOVERY },
>
> Probing for every single device of a given class for a single vendor
> to a driver is just fundamentaly wrong. Please list the actual IDs
> that the driver can handle.
How so? The driver handles all devices of that class. We already do
that for PCI_CLASS_DISPLAY_VGA and PCI_CLASS_DISPLAY_OTHER. Other
drivers do similar things. The hda audio driver does the same thing
for PCI_CLASS_MULTIMEDIA_HD_AUDIO for example.
Alex
Re: [PATCH] drm/amdgpu: Mark amdgpu_acpi_get_node_id & amdgpu_acpi_get_dev functions as static
On Tue, May 23, 2023 at 6:17 AM Srinivasan Shanmugam
wrote:
>
> Below two functions cause a warning because they lack a prototype:
>
> drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c:904:13: warning: no previous
> prototype for ‘amdgpu_acpi_get_node_id’ [-Wmissing-prototypes]
> drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c:930:30: warning: no previous
> prototype for ‘amdgpu_acpi_get_dev’ [-Wmissing-prototypes]
>
> There are no callers from other files, so just mark them as 'static'.
>
> Cc: Christian König
> Cc: Alex Deucher
> Signed-off-by: Srinivasan Shanmugam
Arnd sent a similar patch yesterday. Already queued up.
Alex
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
> index 1a66febf6981..82653f8496bc 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
> @@ -901,8 +901,8 @@ static struct amdgpu_numa_info
> *amdgpu_acpi_get_numa_info(uint32_t pxm)
> *
> * Returns ACPI STATUS OK with Node ID on success or the corresponding
> failure reason
> */
> -acpi_status amdgpu_acpi_get_node_id(acpi_handle handle,
> - struct amdgpu_numa_info **numa_info)
> +static acpi_status amdgpu_acpi_get_node_id(acpi_handle handle,
> + struct amdgpu_numa_info
> **numa_info)
> {
> #ifdef CONFIG_ACPI_NUMA
> u64 pxm;
> @@ -927,7 +927,7 @@ acpi_status amdgpu_acpi_get_node_id(acpi_handle handle,
> #endif
> }
>
> -struct amdgpu_acpi_dev_info *amdgpu_acpi_get_dev(u16 bdf)
> +static struct amdgpu_acpi_dev_info *amdgpu_acpi_get_dev(u16 bdf)
> {
> struct amdgpu_acpi_dev_info *acpi_dev;
>
> --
> 2.25.1
>
[PATCH 3/3] drm/amdgpu: use amdxcp platform device as spatial partition
Use amdxcp platform device as spatial partition device.
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c | 12 ++--
2 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 3d91e123f9bd..852c98dd40ea 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -51,6 +51,7 @@
#include "amdgpu_ras.h"
#include "amdgpu_xgmi.h"
#include "amdgpu_reset.h"
+#include "../amdxcp/amdgpu_xcp_drv.h"
/*
* KMS wrapper.
@@ -2944,6 +2945,7 @@ static void __exit amdgpu_exit(void)
amdgpu_sync_fini();
amdgpu_fence_slab_fini();
mmu_notifier_synchronize();
+ amdgpu_xcp_drv_release();
}
module_init(amdgpu_init);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c
index 6ab5713ff741..9e3a7efaf584 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c
@@ -25,6 +25,7 @@
#include "amdgpu_drv.h"
#include
+#include "../amdxcp/amdgpu_xcp_drv.h"
static int __amdgpu_xcp_run(struct amdgpu_xcp_mgr *xcp_mgr,
struct amdgpu_xcp_ip *xcp_ip, int xcp_state)
@@ -228,21 +229,20 @@ static int amdgpu_xcp_dev_alloc(struct amdgpu_device
*adev)
struct drm_device *p_ddev;
struct pci_dev *pdev;
struct drm_device *ddev;
- int i;
+ int i, ret;
pdev = adev->pdev;
ddev = adev_to_drm(adev);
for (i = 0; i < MAX_XCP; i++) {
- p_ddev = drm_dev_alloc(&amdgpu_partition_driver,
- &pci_upstream_bridge(pdev)->dev);
- if (IS_ERR(p_ddev))
- return PTR_ERR(p_ddev);
+ ret = amdgpu_xcp_drm_dev_alloc(&p_ddev);
+ if (ret)
+ return ret;
/* Redirect all IOCTLs to the primary device */
adev->xcp_mgr->xcp[i].rdev = p_ddev->render->dev;
adev->xcp_mgr->xcp[i].pdev = p_ddev->primary->dev;
- adev->xcp_mgr->xcp[i].driver = p_ddev->driver;
+ adev->xcp_mgr->xcp[i].driver = (struct drm_driver
*)p_ddev->driver;
adev->xcp_mgr->xcp[i].vma_offset_manager =
p_ddev->vma_offset_manager;
p_ddev->render->dev = ddev;
p_ddev->primary->dev = ddev;
--
2.34.1
[PATCH 2/3] drm/amdxcp: add platform device driver for amdxcp
Add platform device driver for amdxcp to support
amdgpu spatial partition.
Signed-off-by: James Zhu
---
drivers/gpu/drm/Makefile| 1 +
drivers/gpu/drm/amd/amdxcp/Makefile | 25 +
drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.c | 108
drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.h | 29 ++
4 files changed, 163 insertions(+)
create mode 100644 drivers/gpu/drm/amd/amdxcp/Makefile
create mode 100644 drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.c
create mode 100644 drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.h
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index cc637343d87b..a74789eb2fd0 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -138,6 +138,7 @@ obj-$(CONFIG_DRM_TDFX) += tdfx/
obj-$(CONFIG_DRM_R128) += r128/
obj-$(CONFIG_DRM_RADEON)+= radeon/
obj-$(CONFIG_DRM_AMDGPU)+= amd/amdgpu/
+obj-$(CONFIG_DRM_AMDGPU)+= amd/amdxcp/
obj-$(CONFIG_DRM_MGA) += mga/
obj-$(CONFIG_DRM_I810) += i810/
obj-$(CONFIG_DRM_I915) += i915/
diff --git a/drivers/gpu/drm/amd/amdxcp/Makefile
b/drivers/gpu/drm/amd/amdxcp/Makefile
new file mode 100644
index ..5e1bd70748d4
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdxcp/Makefile
@@ -0,0 +1,25 @@
+#
+# Copyright 2023 Advanced Micro Devices, Inc.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+# OTHER DEALINGS IN THE SOFTWARE.
+#
+
+amdgpu-y := amdgpu_xcp_drv.o
+
+obj-$(CONFIG_DRM_AMDGPU) += amdgpu_xcp_drv.o
diff --git a/drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.c
b/drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.c
new file mode 100644
index ..d975160c0fa4
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.c
@@ -0,0 +1,108 @@
+/*
+ * Copyright 2023 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include
+#include
+#include
+
+#include
+
+#define MAX_XCP_PLATFORM_DEVICE 64
+
+struct xcp_device {
+ struct drm_device drm;
+ struct platform_device *pdev;
+};
+
+static const struct drm_driver amdgpu_xcp_driver = {
+ .driver_features = DRIVER_GEM | DRIVER_RENDER,
+ .name = "amdgpu_xcp_drv",
+ .major = 1,
+ .minor = 0,
+};
+
+static int pdev_num;
+static struct xcp_device *xcp_dev[MAX_XCP_PLATFORM_DEVICE];
+
+int amdgpu_xcp_drm_dev_alloc(struct drm_device **ddev)
+{
+ struct platform_device *pdev;
+ struct xcp_device *pxcp_dev;
+ int ret;
+
+ if (pdev_num >= MAX_XCP_PLATFORM_DEVICE)
+ return -ENODEV;
+
+ pdev = platform_device_register_simple("amdgpu_xcp", pdev_num, NULL, 0);
+ if (IS_ERR(pdev))
+ return PTR_ERR(pdev);
+
+ if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) {
+ ret = -ENOMEM;
+ goto out_unregister;
+ }
+
+ pxcp_dev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_xcp_driver, struct
xcp_device, drm);
+ if (IS_ERR(pxcp_dev)) {
+ ret =
[PATCH 1/3] drm/amdgpu: save/restore part of xcp drm_device fields
Redirect xcp allocated drm_device::rdev/pdev/driver with
amdgpu pci_device/drm_device setting. They need be saved
before redirect and restored after unregister xcp drm_device.
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c | 16 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h | 4
2 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c
index daeb6bcc9245..6ab5713ff741 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c
@@ -240,9 +240,14 @@ static int amdgpu_xcp_dev_alloc(struct amdgpu_device *adev)
return PTR_ERR(p_ddev);
/* Redirect all IOCTLs to the primary device */
+ adev->xcp_mgr->xcp[i].rdev = p_ddev->render->dev;
+ adev->xcp_mgr->xcp[i].pdev = p_ddev->primary->dev;
+ adev->xcp_mgr->xcp[i].driver = p_ddev->driver;
+ adev->xcp_mgr->xcp[i].vma_offset_manager =
p_ddev->vma_offset_manager;
p_ddev->render->dev = ddev;
p_ddev->primary->dev = ddev;
p_ddev->vma_offset_manager = ddev->vma_offset_manager;
+ p_ddev->driver = &amdgpu_partition_driver;
adev->xcp_mgr->xcp[i].ddev = p_ddev;
}
@@ -330,13 +335,20 @@ int amdgpu_xcp_dev_register(struct amdgpu_device *adev,
void amdgpu_xcp_dev_unplug(struct amdgpu_device *adev)
{
+ struct drm_device *p_ddev;
int i;
if (!adev->xcp_mgr)
return;
- for (i = 0; i < MAX_XCP; i++)
- drm_dev_unplug(adev->xcp_mgr->xcp[i].ddev);
+ for (i = 0; i < MAX_XCP; i++) {
+ p_ddev = adev->xcp_mgr->xcp[i].ddev;
+ drm_dev_unplug(p_ddev);
+ p_ddev->render->dev = adev->xcp_mgr->xcp[i].rdev;
+ p_ddev->primary->dev = adev->xcp_mgr->xcp[i].pdev;
+ p_ddev->driver = adev->xcp_mgr->xcp[i].driver;
+ p_ddev->vma_offset_manager =
adev->xcp_mgr->xcp[i].vma_offset_manager;
+ }
}
int amdgpu_xcp_open_device(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h
index 9c5912b9d8bd..0f8026d64ea5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h
@@ -77,6 +77,10 @@ struct amdgpu_xcp {
bool valid;
atomic_tref_cnt;
struct drm_device *ddev;
+ struct drm_device *rdev;
+ struct drm_device *pdev;
+ struct drm_driver *driver;
+ struct drm_vma_offset_manager *vma_offset_manager;
struct amdgpu_sched
gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX];
};
--
2.34.1
[PATCH] drm/amd/display: remove unused variables res_create_maximus_funcs and debug_defaults_diags
gcc with W=1 reports
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:1069:43: error:
‘res_create_maximus_funcs’ defined but not used
[-Werror=unused-const-variable=]
1069 | static const struct resource_create_funcs res_create_maximus_funcs = {
| ^~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:727:38: error:
‘debug_defaults_diags’ defined but not used [-Werror=unused-const-variable=]
727 | static const struct dc_debug_options debug_defaults_diags = {
| ^~~~
These variables are not used so remove them.
Signed-off-by: Tom Rix
---
.../drm/amd/display/dc/dcn20/dcn20_resource.c | 23 ---
1 file changed, 23 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 7dcae3183e07..6ef7e2634991 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -724,22 +724,6 @@ static const struct dc_debug_options debug_defaults_drv = {
.underflow_assert_delay_us = 0x,
};
-static const struct dc_debug_options debug_defaults_diags = {
- .disable_dmcu = false,
- .force_abm_enable = false,
- .timing_trace = true,
- .clock_trace = true,
- .disable_dpp_power_gate = true,
- .disable_hubp_power_gate = true,
- .disable_clock_gate = true,
- .disable_pplib_clock_request = true,
- .disable_pplib_wm_range = true,
- .disable_stutter = true,
- .scl_reset_length10 = true,
- .underflow_assert_delay_us = 0x,
- .enable_tri_buf = true,
-};
-
void dcn20_dpp_destroy(struct dpp **dpp)
{
kfree(TO_DCN20_DPP(*dpp));
@@ -1066,13 +1050,6 @@ static const struct resource_create_funcs
res_create_funcs = {
.create_hwseq = dcn20_hwseq_create,
};
-static const struct resource_create_funcs res_create_maximus_funcs = {
- .read_dce_straps = NULL,
- .create_audio = NULL,
- .create_stream_encoder = NULL,
- .create_hwseq = dcn20_hwseq_create,
-};
-
static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
void dcn20_clock_source_destroy(struct clock_source **clk_src)
--
2.27.0
Re: [PATCH 01/18] drm/amd/display: improve the message printed when loading DC
Hi,
On 17/05/23 5:07 pm, Tom Chung wrote:
From: Aurabindo Pillai
[Why&How]
Change how DC version and hardware version is printed when driver is
loaded.
- Remove exclamation
- Add DC version and hardware version to both success and failure cases
- Add version in between appropriate filler words to make a complete
statement.
Reviewed-by: Harry Wentland
Acked-by: Tom Chung
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 14b296e1d0f6..45b778631430 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1666,10 +1666,11 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
adev->dm.dc = dc_create(&init_data);
if (adev->dm.dc) {
// Check for NULL
- DRM_INFO("Display Core initialized with v%s! %s\n", DC_VER,
+ DRM_INFO("Display Core v%s initialized on %s\n", DC_VER,
dce_version_to_string(adev->dm.dc->ctx->dce_version));
} else {
// adev->dm.dc is NULL here
- DRM_INFO("Display Core failed to initialize with v%s!\n",
DC_VER);
+ DRM_INFO("Display Core v%s failed to initialize on %s\n",
DC_VER,
+dce_version_to_string(adev->dm.dc->ctx->dce_version));
NULL deref bug here.
I found this using static analysis with smatch.
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:1673
amdgpu_dm_init() error: we previously assumed 'adev->dm.dc' could be
null (see line 1669)
If you fix this could you please consider adding:
Reported-by: Harshit Mogalapalli
Thanks,
Harshit
goto error;
}
RE: [PATCH] drm/amdgpu: Fix warnings
[AMD Official Use Only - General] Reviewed-by: Hawking Zhang Regards, Hawking -Original Message- From: amd-gfx On Behalf Of Lijo Lazar Sent: Tuesday, May 23, 2023 16:00 To: amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander ; Dan Carpenter ; kernel test robot ; Zhang, Hawking Subject: [PATCH] drm/amdgpu: Fix warnings Fix warnings reported by kernel test bot/smatch smatch warnings: drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c:65 amdgpu_xcp_run_transition() error: buffer overflow 'xcp_mgr->xcp' 8 <= 8 Reported-by: kernel test robot Reported-by: Dan Carpenter Closes: https://lore.kernel.org/r/202305231453.i0bxngyn-...@intel.com/ Signed-off-by: Lijo Lazar --- drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c index e9586a0dc335..fcdc0862d258 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c @@ -65,7 +65,7 @@ static int amdgpu_xcp_run_transition(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id, struct amdgpu_xcp *xcp; int i, ret; - if (xcp_id > MAX_XCP || !xcp_mgr->xcp[xcp_id].valid) + if (xcp_id >= MAX_XCP || !xcp_mgr->xcp[xcp_id].valid) return -EINVAL; xcp = &xcp_mgr->xcp[xcp_id]; -- 2.25.1
[PATCH] drm/amdgpu: Mark amdgpu_acpi_get_node_id & amdgpu_acpi_get_dev functions as static
Below two functions cause a warning because they lack a prototype:
drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c:904:13: warning: no previous prototype
for ‘amdgpu_acpi_get_node_id’ [-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c:930:30: warning: no previous prototype
for ‘amdgpu_acpi_get_dev’ [-Wmissing-prototypes]
There are no callers from other files, so just mark them as 'static'.
Cc: Christian König
Cc: Alex Deucher
Signed-off-by: Srinivasan Shanmugam
---
drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
index 1a66febf6981..82653f8496bc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
@@ -901,8 +901,8 @@ static struct amdgpu_numa_info
*amdgpu_acpi_get_numa_info(uint32_t pxm)
*
* Returns ACPI STATUS OK with Node ID on success or the corresponding failure
reason
*/
-acpi_status amdgpu_acpi_get_node_id(acpi_handle handle,
- struct amdgpu_numa_info **numa_info)
+static acpi_status amdgpu_acpi_get_node_id(acpi_handle handle,
+ struct amdgpu_numa_info **numa_info)
{
#ifdef CONFIG_ACPI_NUMA
u64 pxm;
@@ -927,7 +927,7 @@ acpi_status amdgpu_acpi_get_node_id(acpi_handle handle,
#endif
}
-struct amdgpu_acpi_dev_info *amdgpu_acpi_get_dev(u16 bdf)
+static struct amdgpu_acpi_dev_info *amdgpu_acpi_get_dev(u16 bdf)
{
struct amdgpu_acpi_dev_info *acpi_dev;
--
2.25.1
Re: [PATCH] drm/amdgpu: add the accelerator pcie class
On Tue, May 23, 2023 at 12:02:32PM +0800, Shiwu Zhang wrote:
> + { PCI_DEVICE(0x1002, PCI_ANY_ID),
> + .class = PCI_CLASS_ACCELERATOR_PROCESSING << 8,
> + .class_mask = 0xff,
> + .driver_data = CHIP_IP_DISCOVERY },
Probing for every single device of a given class for a single vendor
to a driver is just fundamentaly wrong. Please list the actual IDs
that the driver can handle.
[PATCH] drm/amdgpu: Modify mismatched function name
No functional modification involved. drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c:426: warning: expecting prototype for sdma_v4_4_2_gfx_stop(). Prototype was for sdma_v4_4_2_inst_gfx_stop() instead. drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c:457: warning: expecting prototype for sdma_v4_4_2_rlc_stop(). Prototype was for sdma_v4_4_2_inst_rlc_stop() instead. drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c:470: warning: expecting prototype for sdma_v4_4_2_page_stop(). Prototype was for sdma_v4_4_2_inst_page_stop() instead. drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c:506: warning: expecting prototype for sdma_v4_4_2_ctx_switch_enable(). Prototype was for sdma_v4_4_2_inst_ctx_switch_enable() instead. drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c:561: warning: expecting prototype for sdma_v4_4_2_enable(). Prototype was for sdma_v4_4_2_inst_enable() instead. drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c:798: warning: expecting prototype for sdma_v4_4_2_rlc_resume(). Prototype was for sdma_v4_4_2_inst_rlc_resume() instead. drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c:814: warning: expecting prototype for sdma_v4_4_2_load_microcode(). Prototype was for sdma_v4_4_2_inst_load_microcode() instead. Reported-by: Abaci Robot Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=5283 Signed-off-by: Jiapeng Chong --- drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c index bf47eb33c12e..590b08585901 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c @@ -415,7 +415,7 @@ static void sdma_v4_4_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 /** - * sdma_v4_4_2_gfx_stop - stop the gfx async dma engines + * sdma_v4_4_2_inst_gfx_stop - stop the gfx async dma engines * * @adev: amdgpu_device pointer * @@ -446,7 +446,7 @@ static void sdma_v4_4_2_inst_gfx_stop(struct amdgpu_device *adev, } /** - * sdma_v4_4_2_rlc_stop - stop the compute async dma engines + * sdma_v4_4_2_inst_rlc_stop - stop the compute async dma engines * * @adev: amdgpu_device pointer * @@ -459,7 +459,7 @@ static void sdma_v4_4_2_inst_rlc_stop(struct amdgpu_device *adev, } /** - * sdma_v4_4_2_page_stop - stop the page async dma engines + * sdma_v4_4_2_inst_page_stop - stop the page async dma engines * * @adev: amdgpu_device pointer * @@ -494,7 +494,7 @@ static void sdma_v4_4_2_inst_page_stop(struct amdgpu_device *adev, } /** - * sdma_v4_4_2_ctx_switch_enable - stop the async dma engines context switch + * sdma_v4_4_2_inst_ctx_switch_enable - stop the async dma engines context switch * * @adev: amdgpu_device pointer * @enable: enable/disable the DMA MEs context switch. @@ -548,7 +548,7 @@ static void sdma_v4_4_2_inst_ctx_switch_enable(struct amdgpu_device *adev, } /** - * sdma_v4_4_2_enable - stop the async dma engines + * sdma_v4_4_2_inst_enable - stop the async dma engines * * @adev: amdgpu_device pointer * @enable: enable/disable the DMA MEs. @@ -786,7 +786,7 @@ static void sdma_v4_4_2_init_pg(struct amdgpu_device *adev) } /** - * sdma_v4_4_2_rlc_resume - setup and start the async dma engines + * sdma_v4_4_2_inst_rlc_resume - setup and start the async dma engines * * @adev: amdgpu_device pointer * @@ -802,7 +802,7 @@ static int sdma_v4_4_2_inst_rlc_resume(struct amdgpu_device *adev, } /** - * sdma_v4_4_2_load_microcode - load the sDMA ME ucode + * sdma_v4_4_2_inst_load_microcode - load the sDMA ME ucode * * @adev: amdgpu_device pointer * -- 2.20.1.7.g153144c
[PATCH] drm/amdgpu/vcn: Modify mismatched function name
No functional modification involved. drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c:374: warning: expecting prototype for vcn_v4_0_mc_resume_dpg_mode(). Prototype was for vcn_v4_0_3_mc_resume_dpg_mode() instead. drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c:631: warning: expecting prototype for vcn_v4_0_enable_clock_gating(). Prototype was for vcn_v4_0_3_enable_clock_gating() instead. Reported-by: Abaci Robot Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=5284 Signed-off-by: Jiapeng Chong --- drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c index 339842382a1e..5d67b8b8a3d6 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c @@ -362,7 +362,7 @@ static void vcn_v4_0_3_mc_resume(struct amdgpu_device *adev, int inst_idx) } /** - * vcn_v4_0_mc_resume_dpg_mode - memory controller programming for dpg mode + * vcn_v4_0_3_mc_resume_dpg_mode - memory controller programming for dpg mode * * @adev: amdgpu_device pointer * @inst_idx: instance number index @@ -620,7 +620,7 @@ static void vcn_v4_0_3_disable_clock_gating_dpg_mode(struct amdgpu_device *adev, } /** - * vcn_v4_0_enable_clock_gating - enable VCN clock gating + * vcn_v4_0_3_enable_clock_gating - enable VCN clock gating * * @adev: amdgpu_device pointer * @inst_idx: instance number -- 2.20.1.7.g153144c
[PATCH] drm/amdgpu: Remove duplicate include
./drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c: amdgpu_xcp.h is included more than once. Reported-by: Abaci Robot Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=5281 Signed-off-by: Jiapeng Chong --- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index e5cfb3adb3b3..7fb2d38b010a 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -23,7 +23,6 @@ #include #include "amdgpu.h" -#include "amdgpu_xcp.h" #include "amdgpu_gfx.h" #include "soc15.h" #include "soc15d.h" -- 2.20.1.7.g153144c
[PATCH] drm/amd/display: avoid calling missing .resync_fifo_dccg_dio()
From: Arnd Bergmann
The .resync_fifo_dccg_dio() callback pointer was added in an #ifdef block,
but is called unconditionally:
drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_hw_sequencer.c:2292:31:
error: 'struct hwseq_private_funcs' has no member named 'resync_fifo_dccg_dio'
Add the same #ifdef around the caller as well.
Fixes: 6354b0dc3a7a ("drm/amd/display: Trigger DIO FIFO resync on commit
streams")
Signed-off-by: Arnd Bergmann
---
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index c6fe2c00aedb..d4cacb8df631 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -2289,8 +2289,10 @@ enum dc_status dce110_apply_ctx_to_hw(
if (DC_OK != status)
return status;
+#ifdef CONFIG_DRM_AMD_DC_FP
if (hws->funcs.resync_fifo_dccg_dio)
hws->funcs.resync_fifo_dccg_dio(hws, dc, context);
+#endif
}
if (dc->fbc_compressor)
--
2.39.2
[PATCH] drm/amdgpu: Fix warnings
Fix warnings reported by kernel test bot/smatch smatch warnings: drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c:65 amdgpu_xcp_run_transition() error: buffer overflow 'xcp_mgr->xcp' 8 <= 8 Reported-by: kernel test robot Reported-by: Dan Carpenter Closes: https://lore.kernel.org/r/202305231453.i0bxngyn-...@intel.com/ Signed-off-by: Lijo Lazar --- drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c index e9586a0dc335..fcdc0862d258 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c @@ -65,7 +65,7 @@ static int amdgpu_xcp_run_transition(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id, struct amdgpu_xcp *xcp; int i, ret; - if (xcp_id > MAX_XCP || !xcp_mgr->xcp[xcp_id].valid) + if (xcp_id >= MAX_XCP || !xcp_mgr->xcp[xcp_id].valid) return -EINVAL; xcp = &xcp_mgr->xcp[xcp_id]; -- 2.25.1
