RE: [PATCH] drm/amdgpu: change reserved vram info print

[Chai, Thomas]

[AMD Official Use Only - General]

OK, thanks!


-
Best Regards,
Thomas

From: Christian König 
Sent: Thursday, June 1, 2023 2:25 PM
To: Paneer Selvam, Arunpravin ; Chai, Thomas 
; amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao ; Yang, Stanley ; Chai, 
Thomas ; Li, Candice ; Koenig, 
Christian ; Zhang, Hawking 
Subject: Re: [PATCH] drm/amdgpu: change reserved vram info print

If you haven't already pushed it Reviewed-by: Christian König 
 as well.

You might want to add a CC: stable... tag so that it gets backported.

Regards,
Christian.
Am 01.06.23 um 08:13 schrieb Arunpravin Paneer Selvam:

Reviewed-by: Arunpravin Paneer Selvam 
mailto:arunpravin.paneersel...@amd.com>>

On 5/25/2023 2:20 PM, YiPeng Chai wrote

The link object of mgr->reserved_pages is the blocks

variable in struct amdgpu_vram_reservation, not the

link variable in struct drm_buddy_block.



Signed-off-by: YiPeng Chai 

---

 drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 7 ---

 1 file changed, 4 insertions(+), 3 deletions(-)



diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c

index 89d35d194f2c..c7085a747b03 100644

--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c

+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c

@@ -839,7 +839,7 @@ static void amdgpu_vram_mgr_debug(struct 
ttm_resource_manager *man,

 {

   struct amdgpu_vram_mgr *mgr = to_vram_mgr(man);

   struct drm_buddy *mm = &mgr->mm;

-  struct drm_buddy_block *block;

+  struct amdgpu_vram_reservation *rsv;



   drm_printf(printer, "  vis usage:%llu\n",

  amdgpu_vram_mgr_vis_usage(mgr));

@@ -851,8 +851,9 @@ static void amdgpu_vram_mgr_debug(struct 
ttm_resource_manager *man,

   drm_buddy_print(mm, printer);



   drm_printf(printer, "reserved:\n");

-  list_for_each_entry(block, &mgr->reserved_pages, link)

- drm_buddy_block_print(mm, block, printer);

+  list_for_each_entry(rsv, &mgr->reserved_pages, blocks)

+  drm_printf(printer, "%#018llx-%#018llx: %llu\n",

+  rsv->start, rsv->start + rsv->size, rsv->size);

   mutex_unlock(&mgr->lock);

 }

Re: [PATCH] drm/amdgpu: change reserved vram info print

[Christian König]

If you haven't already pushed it Reviewed-by: Christian König 
 as well.


You might want to add a CC: stable... tag so that it gets backported.

Regards,
Christian.

Am 01.06.23 um 08:13 schrieb Arunpravin Paneer Selvam:


Reviewed-by: Arunpravin Paneer Selvam 


On 5/25/2023 2:20 PM, YiPeng Chai wrote

The link object of mgr->reserved_pages is the blocks
variable in struct amdgpu_vram_reservation, not the
link variable in struct drm_buddy_block.

Signed-off-by: YiPeng Chai
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 7 ---
  1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
index 89d35d194f2c..c7085a747b03 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
@@ -839,7 +839,7 @@ static void amdgpu_vram_mgr_debug(struct 
ttm_resource_manager *man,
  {
struct amdgpu_vram_mgr *mgr = to_vram_mgr(man);
struct drm_buddy *mm = &mgr->mm;
-   struct drm_buddy_block *block;
+   struct amdgpu_vram_reservation *rsv;
  
  	drm_printf(printer, "  vis usage:%llu\n",

   amdgpu_vram_mgr_vis_usage(mgr));
@@ -851,8 +851,9 @@ static void amdgpu_vram_mgr_debug(struct 
ttm_resource_manager *man,
drm_buddy_print(mm, printer);
  
  	drm_printf(printer, "reserved:\n");

-   list_for_each_entry(block, &mgr->reserved_pages, link)
-   drm_buddy_block_print(mm, block, printer);
+   list_for_each_entry(rsv, &mgr->reserved_pages, blocks)
+   drm_printf(printer, "%#018llx-%#018llx: %llu\n",
+   rsv->start, rsv->start + rsv->size, rsv->size);
mutex_unlock(&mgr->lock);
  }
  

Re: [PATCH] drm/amdgpu: change reserved vram info print

[Arunpravin Paneer Selvam]

Reviewed-by: Arunpravin Paneer Selvam 


On 5/25/2023 2:20 PM, YiPeng Chai wrote

The link object of mgr->reserved_pages is the blocks
variable in struct amdgpu_vram_reservation, not the
link variable in struct drm_buddy_block.

Signed-off-by: YiPeng Chai
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 7 ---
  1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
index 89d35d194f2c..c7085a747b03 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
@@ -839,7 +839,7 @@ static void amdgpu_vram_mgr_debug(struct 
ttm_resource_manager *man,
  {
struct amdgpu_vram_mgr *mgr = to_vram_mgr(man);
struct drm_buddy *mm = &mgr->mm;
-   struct drm_buddy_block *block;
+   struct amdgpu_vram_reservation *rsv;
  
  	drm_printf(printer, "  vis usage:%llu\n",

   amdgpu_vram_mgr_vis_usage(mgr));
@@ -851,8 +851,9 @@ static void amdgpu_vram_mgr_debug(struct 
ttm_resource_manager *man,
drm_buddy_print(mm, printer);
  
  	drm_printf(printer, "reserved:\n");

-   list_for_each_entry(block, &mgr->reserved_pages, link)
-   drm_buddy_block_print(mm, block, printer);
+   list_for_each_entry(rsv, &mgr->reserved_pages, blocks)
+   drm_printf(printer, "%#018llx-%#018llx: %llu\n",
+   rsv->start, rsv->start + rsv->size, rsv->size);
mutex_unlock(&mgr->lock);
  }
  

[pull] amdgpu drm-fixes-6.4

[Alex Deucher]

Hi Dave, Daniel,

Fixes for 6.4.

The following changes since commit 7877cb91f1081754a1487c144d85dc0d2e2e7fc4:

  Linux 6.4-rc4 (2023-05-28 07:49:00 -0400)

are available in the Git repository at:

  https://gitlab.freedesktop.org/agd5f/linux.git 
tags/amd-drm-fixes-6.4-2023-05-31

for you to fetch changes up to 663b930e24842f3d3bb79418bb5cd8d01b40c559:

  drm/amdgpu: enable tmz by default for GC 11.0.1 (2023-05-31 22:28:43 -0400)


amd-drm-fixes-6.4-2023-05-31:

amdgpu:
- Fix mclk and fclk output ordering on some APUs
- Fix display regression with 5K VRR
- VCN, JPEG spurious interrupt warning fixes
- Fix SI DPM on some ARM64 platforms
- Fix missing TMZ enablement on GC 11.0.1


Guchun Chen (1):
  drm/amd/pm: resolve reboot exception for si oland

Horatio Zhang (6):
  drm/amdgpu: separate ras irq from vcn instance irq for UVD_POISON
  drm/amdgpu: add RAS POISON interrupt funcs for vcn_v2_6
  drm/amdgpu: add RAS POISON interrupt funcs for vcn_v4_0
  drm/amdgpu: separate ras irq from jpeg instance irq for UVD_POISON
  drm/amdgpu: add RAS POISON interrupt funcs for jpeg_v2_6
  drm/amdgpu: add RAS POISON interrupt funcs for jpeg_v4_0

Ikshwaku Chauhan (1):
  drm/amdgpu: enable tmz by default for GC 11.0.1

Michel Dänzer (2):
  Revert "drm/amd/display: Block optimize on consecutive FAMS enables"
  Revert "drm/amd/display: Do not set drr on pipe commit"

Tim Huang (5):
  drm/amd/pm: reverse mclk and fclk clocks levels for SMU v13.0.4
  drm/amd/pm: reverse mclk clocks levels for SMU v13.0.5
  drm/amd/pm: reverse mclk and fclk clocks levels for yellow carp
  drm/amd/pm: reverse mclk and fclk clocks levels for vangogh
  drm/amd/pm: reverse mclk and fclk clocks levels for renoir

 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c|  3 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c   | 27 +++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h   |  3 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c| 27 +++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h|  3 ++
 drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c | 28 +
 drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c | 28 -
 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c  | 25 ---
 drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c  | 36 ++
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c |  9 --
 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c | 25 +--
 drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 29 -
 drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c   | 10 +++---
 drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c|  5 +--
 .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c   |  5 +--
 .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c   |  5 +--
 .../gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c   |  5 +--
 17 files changed, 173 insertions(+), 100 deletions(-)

Re: [PATCH v2 1/2] drm/amd: Disallow s0ix without BIOS support again

[Alex Deucher]

On Wed, May 31, 2023 at 9:26 AM Alex Deucher  wrote:
>
> On Tue, May 30, 2023 at 6:34 PM Mario Limonciello
>  wrote:
> >
> > commit cf488dcd0ab7 ("drm/amd: Allow s0ix without BIOS support") showed
> > improvements to power consumption over suspend when s0ix wasn't enabled in
> > BIOS and the system didn't support S3.
> >
> > This patch however was misguided because the reason the system didn't
> > support S3 was because SMT was disabled in OEM BIOS setup.
> > This prevented the BIOS from allowing S3.
> >
> > Also allowing GPUs to use the s2idle path actually causes problems if
> > they're invoked on systems that may not support s2idle in the platform
> > firmware. `systemd` has a tendency to try to use `s2idle` if `deep` fails
> > for any reason, which could lead to unexpected flows.
> >
> > The original commit also fixed a problem during resume from suspend to idle
> > without hardware support, but this is no longer necessary with commit
> > ca4751866397 ("drm/amd: Don't allow s0ix on APUs older than Raven")
> >
> > Revert commit cf488dcd0ab7 ("drm/amd: Allow s0ix without BIOS support")
> > to make it match the expected behavior again.
> >
> > Cc: Rafael Ávila de Espíndola 
> > Link: 
> > https://github.com/torvalds/linux/blob/v6.1/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c#L1060
> > Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/2599
> > Signed-off-by: Mario Limonciello 
>
> Patch 1 is:
> Reviewed-by: Alex Deucher 
> Patch 2 seems a bit much, but I could be convinced if you think it
> will actually help more than a warn would.  Users already assume warn
> is a kernel crash.  I'm not sure the average user makes a distinction
> between warn and err.
>

You'll need to revert d2a197a45daacd ("drm/amd: Only run s3 or s0ix if
system is configured properly") as well, otherwise, we'll break
runtime pm.

Alex

> Alex
>
> > ---
> >  drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 8 ++--
> >  1 file changed, 6 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c 
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
> > index aeeec211861c..e1b01554e323 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
> > @@ -1092,16 +1092,20 @@ bool amdgpu_acpi_is_s0ix_active(struct 
> > amdgpu_device *adev)
> >  * S0ix even though the system is suspending to idle, so return 
> > false
> >  * in that case.
> >  */
> > -   if (!(acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0))
> > +   if (!(acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0)) {
> > dev_warn_once(adev->dev,
> >   "Power consumption will be higher as BIOS has 
> > not been configured for suspend-to-idle.\n"
> >   "To use suspend-to-idle change the sleep mode 
> > in BIOS setup.\n");
> > +   return false;
> > +   }
> >
> >  #if !IS_ENABLED(CONFIG_AMD_PMC)
> > dev_warn_once(adev->dev,
> >   "Power consumption will be higher as the kernel has 
> > not been compiled with CONFIG_AMD_PMC.\n");
> > -#endif /* CONFIG_AMD_PMC */
> > +   return false;
> > +#else
> > return true;
> > +#endif /* CONFIG_AMD_PMC */
> >  }
> >
> >  #endif /* CONFIG_SUSPEND */
> > --
> > 2.34.1
> >

[PATCH 4/4] drm/amd/pm: fulfill the OD support for SMU13.0.7

[Evan Quan]

Fulfill the interfaces for OD settings retrieving and setting.

Signed-off-by: Evan Quan 
---
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c  | 445 --
 1 file changed, 402 insertions(+), 43 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
index 3ba88033c766..8d4a0c3cedbc 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
@@ -1027,16 +1027,118 @@ static int 
smu_v13_0_7_get_current_clk_freq_by_table(struct smu_context *smu,
value);
 }
 
+static bool smu_v13_0_7_is_od_feature_supported(struct smu_context *smu,
+   int od_feature_bit)
+{
+   PPTable_t *pptable = smu->smu_table.driver_pptable;
+   const OverDriveLimits_t * const overdrive_upperlimits =
+   &pptable->SkuTable.OverDriveLimitsBasicMax;
+
+   return overdrive_upperlimits->FeatureCtrlMask & (1U << od_feature_bit);
+}
+
+static void smu_v13_0_7_get_od_setting_limits(struct smu_context *smu,
+ int od_feature_bit,
+ bool lower_boundary,
+ int32_t *min,
+ int32_t *max)
+{
+   PPTable_t *pptable = smu->smu_table.driver_pptable;
+   const OverDriveLimits_t * const overdrive_upperlimits =
+   &pptable->SkuTable.OverDriveLimitsBasicMax;
+   const OverDriveLimits_t * const overdrive_lowerlimits =
+   &pptable->SkuTable.OverDriveLimitsMin;
+   int32_t od_min_setting, od_max_setting;
+
+   switch (od_feature_bit) {
+   case PP_OD_FEATURE_GFXCLK_BIT:
+   if (lower_boundary) {
+   od_min_setting = overdrive_lowerlimits->GfxclkFmin;
+   od_max_setting = overdrive_upperlimits->GfxclkFmin;
+   } else {
+   od_min_setting = overdrive_lowerlimits->GfxclkFmax;
+   od_max_setting = overdrive_upperlimits->GfxclkFmax;
+   }
+   break;
+   case PP_OD_FEATURE_UCLK_BIT:
+   if (lower_boundary) {
+   od_min_setting = overdrive_lowerlimits->UclkFmin;
+   od_max_setting = overdrive_upperlimits->UclkFmin;
+   } else {
+   od_min_setting = overdrive_lowerlimits->UclkFmax;
+   od_max_setting = overdrive_upperlimits->UclkFmax;
+   }
+   break;
+   case PP_OD_FEATURE_GFX_VF_CURVE_BIT:
+   od_min_setting = 
overdrive_lowerlimits->VoltageOffsetPerZoneBoundary;
+   od_max_setting = 
overdrive_upperlimits->VoltageOffsetPerZoneBoundary;
+   break;
+   default:
+   break;
+   }
+
+   if (min)
+   *min = od_min_setting;
+   if (max)
+   *max = od_max_setting;
+}
+
+static void smu_v13_0_7_dump_od_table(struct smu_context *smu,
+ OverDriveTableExternal_t *od_table)
+{
+   struct amdgpu_device *adev = smu->adev;
+
+   dev_dbg(adev->dev, "OD: Gfxclk: (%d, %d)\n", 
od_table->OverDriveTable.GfxclkFmin,
+
od_table->OverDriveTable.GfxclkFmax);
+   dev_dbg(adev->dev, "OD: Uclk: (%d, %d)\n", 
od_table->OverDriveTable.UclkFmin,
+  
od_table->OverDriveTable.UclkFmax);
+}
+
+static int smu_v13_0_7_get_overdrive_table(struct smu_context *smu,
+  OverDriveTableExternal_t *od_table)
+{
+   int ret = 0;
+
+   ret = smu_cmn_update_table(smu,
+  SMU_TABLE_OVERDRIVE,
+  0,
+  (void *)od_table,
+  false);
+   if (ret)
+   dev_err(smu->adev->dev, "Failed to get overdrive table!\n");
+
+   return ret;
+}
+
+static int smu_v13_0_7_upload_overdrive_table(struct smu_context *smu,
+ OverDriveTableExternal_t 
*od_table)
+{
+   int ret = 0;
+
+   ret = smu_cmn_update_table(smu,
+  SMU_TABLE_OVERDRIVE,
+  0,
+  (void *)od_table,
+  true);
+   if (ret)
+   dev_err(smu->adev->dev, "Failed to upload overdrive table!\n");
+
+   return ret;
+}
+
 static int smu_v13_0_7_print_clk_levels(struct smu_context *smu,
enum smu_clk_type clk_type,
char *buf)
 {
struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
   

[PATCH 3/4] drm/amd/pm: fulfill the OD support for SMU13.0.0

[Evan Quan]

Fulfill the interfaces for OD settings retrieving and setting.

Signed-off-by: Evan Quan 
---
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c  | 445 --
 1 file changed, 402 insertions(+), 43 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index 2a9840c54f72..e7eb517ed5f1 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -1037,17 +1037,119 @@ static int 
smu_v13_0_0_get_current_clk_freq_by_table(struct smu_context *smu,
value);
 }
 
+static bool smu_v13_0_0_is_od_feature_supported(struct smu_context *smu,
+   int od_feature_bit)
+{
+   PPTable_t *pptable = smu->smu_table.driver_pptable;
+   const OverDriveLimits_t * const overdrive_upperlimits =
+   &pptable->SkuTable.OverDriveLimitsBasicMax;
+
+   return overdrive_upperlimits->FeatureCtrlMask & (1U << od_feature_bit);
+}
+
+static void smu_v13_0_0_get_od_setting_limits(struct smu_context *smu,
+ int od_feature_bit,
+ bool lower_boundary,
+ int32_t *min,
+ int32_t *max)
+{
+   PPTable_t *pptable = smu->smu_table.driver_pptable;
+   const OverDriveLimits_t * const overdrive_upperlimits =
+   &pptable->SkuTable.OverDriveLimitsBasicMax;
+   const OverDriveLimits_t * const overdrive_lowerlimits =
+   &pptable->SkuTable.OverDriveLimitsMin;
+   int32_t od_min_setting, od_max_setting;
+
+   switch (od_feature_bit) {
+   case PP_OD_FEATURE_GFXCLK_BIT:
+   if (lower_boundary) {
+   od_min_setting = overdrive_lowerlimits->GfxclkFmin;
+   od_max_setting = overdrive_upperlimits->GfxclkFmin;
+   } else {
+   od_min_setting = overdrive_lowerlimits->GfxclkFmax;
+   od_max_setting = overdrive_upperlimits->GfxclkFmax;
+   }
+   break;
+   case PP_OD_FEATURE_UCLK_BIT:
+   if (lower_boundary) {
+   od_min_setting = overdrive_lowerlimits->UclkFmin;
+   od_max_setting = overdrive_upperlimits->UclkFmin;
+   } else {
+   od_min_setting = overdrive_lowerlimits->UclkFmax;
+   od_max_setting = overdrive_upperlimits->UclkFmax;
+   }
+   break;
+   case PP_OD_FEATURE_GFX_VF_CURVE_BIT:
+   od_min_setting = 
overdrive_lowerlimits->VoltageOffsetPerZoneBoundary;
+   od_max_setting = 
overdrive_upperlimits->VoltageOffsetPerZoneBoundary;
+   break;
+   default:
+   break;
+   }
+
+   if (min)
+   *min = od_min_setting;
+   if (max)
+   *max = od_max_setting;
+}
+
+static void smu_v13_0_0_dump_od_table(struct smu_context *smu,
+ OverDriveTableExternal_t *od_table)
+{
+   struct amdgpu_device *adev = smu->adev;
+
+   dev_dbg(adev->dev, "OD: Gfxclk: (%d, %d)\n", 
od_table->OverDriveTable.GfxclkFmin,
+
od_table->OverDriveTable.GfxclkFmax);
+   dev_dbg(adev->dev, "OD: Uclk: (%d, %d)\n", 
od_table->OverDriveTable.UclkFmin,
+  
od_table->OverDriveTable.UclkFmax);
+}
+
+static int smu_v13_0_0_get_overdrive_table(struct smu_context *smu,
+  OverDriveTableExternal_t *od_table)
+{
+   int ret = 0;
+
+   ret = smu_cmn_update_table(smu,
+  SMU_TABLE_OVERDRIVE,
+  0,
+  (void *)od_table,
+  false);
+   if (ret)
+   dev_err(smu->adev->dev, "Failed to get overdrive table!\n");
+
+   return ret;
+}
+
+static int smu_v13_0_0_upload_overdrive_table(struct smu_context *smu,
+ OverDriveTableExternal_t 
*od_table)
+{
+   int ret = 0;
+
+   ret = smu_cmn_update_table(smu,
+  SMU_TABLE_OVERDRIVE,
+  0,
+  (void *)od_table,
+  true);
+   if (ret)
+   dev_err(smu->adev->dev, "Failed to upload overdrive table!\n");
+
+   return ret;
+}
+
 static int smu_v13_0_0_print_clk_levels(struct smu_context *smu,
enum smu_clk_type clk_type,
char *buf)
 {
struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
   

[PATCH 2/4] drm/amd/pm: fulfill SMU13 OD settings init and restore

[Evan Quan]

Gfxclk fmin/fmax, Uclk fmin/fmax and Gfx v/f curve voltage offset
OD settings are supported for SMU13.

Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/pm/amdgpu_pm.c|  26 +++-
 .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c|  13 +-
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c  | 129 +-
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c  | 128 -
 4 files changed, 286 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c 
b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index da0da03569e8..a57952b93e73 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -678,7 +678,12 @@ static ssize_t amdgpu_set_pp_table(struct device *dev,
  *   clock labeled OD_MCLK
  *
  * - three  points labeled OD_VDDC_CURVE.
- *   They can be used to calibrate the sclk voltage curve.
+ *   They can be used to calibrate the sclk voltage curve. This is
+ *   available for Vega20 and NV1X.
+ *
+ * - voltage offset for the six anchor points of the v/f curve labeled
+ *   OD_VDDC_CURVE. They can be used to calibrate the v/f curve. This
+ *   is only availabe for some SMU13 ASICs.
  *
  * - voltage offset(in mV) applied on target voltage calculation.
  *   This is available for Sienna Cichlid, Navy Flounder and Dimgrey
@@ -719,12 +724,19 @@ static ssize_t amdgpu_set_pp_table(struct device *dev,
  *   E.g., "p 2 0 800" would set the minimum core clock on core
  *   2 to 800Mhz.
  *
- *   For sclk voltage curve, enter the new values by writing a
- *   string that contains "vc point clock voltage" to the file. The
- *   points are indexed by 0, 1 and 2. E.g., "vc 0 300 600" will
- *   update point1 with clock set as 300Mhz and voltage as
- *   600mV. "vc 2 1000 1000" will update point3 with clock set
- *   as 1000Mhz and voltage 1000mV.
+ *   For sclk voltage curve,
+ * - For NV1X, enter the new values by writing a string that
+ *   contains "vc point clock voltage" to the file. The points
+ *   are indexed by 0, 1 and 2. E.g., "vc 0 300 600" will update
+ *   point1 with clock set as 300Mhz and voltage as 600mV. "vc 2
+ *   1000 1000" will update point3 with clock set as 1000Mhz and
+ *   voltage 1000mV.
+ * - For SMU13 ASICs, enter the new values by writing a string that
+ *   contains "vc anchor_point_index voltage_offset" to the file.
+ *   There are total six anchor points defined on the v/f curve with
+ *   index as 0 - 5.
+ *   - "vc 0 10" will update the voltage offset for point1 as 10mv.
+ *   - "vc 5 -10" will update the voltage offset for point6 as -10mv.
  *
  *   To update the voltage offset applied for gfxclk/voltage calculation,
  *   enter the new value by writing a string that contains "vo offset".
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index 54b9930ff599..9295dbe06200 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -467,17 +467,26 @@ int smu_v13_0_init_smc_tables(struct smu_context *smu)
ret = -ENOMEM;
goto err3_out;
}
+
+   smu_table->user_overdrive_table =
+   kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
+   if (!smu_table->user_overdrive_table) {
+   ret = -ENOMEM;
+   goto err4_out;
+   }
}
 
smu_table->combo_pptable =
kzalloc(tables[SMU_TABLE_COMBO_PPTABLE].size, GFP_KERNEL);
if (!smu_table->combo_pptable) {
ret = -ENOMEM;
-   goto err4_out;
+   goto err5_out;
}
 
return 0;
 
+err5_out:
+   kfree(smu_table->user_overdrive_table);
 err4_out:
kfree(smu_table->boot_overdrive_table);
 err3_out:
@@ -497,12 +506,14 @@ int smu_v13_0_fini_smc_tables(struct smu_context *smu)
 
kfree(smu_table->gpu_metrics_table);
kfree(smu_table->combo_pptable);
+   kfree(smu_table->user_overdrive_table);
kfree(smu_table->boot_overdrive_table);
kfree(smu_table->overdrive_table);
kfree(smu_table->max_sustainable_clocks);
kfree(smu_table->driver_pptable);
smu_table->gpu_metrics_table = NULL;
smu_table->combo_pptable = NULL;
+   smu_table->user_overdrive_table = NULL;
smu_table->boot_overdrive_table = NULL;
smu_table->overdrive_table = NULL;
smu_table->max_sustainable_clocks = NULL;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index 3fd6d10eac25..2a9840c54f72 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -239,6 +239,7 @@ static struct cmn2asic_mapping 
smu_v13_0_0_table_map[SMU_TABLE_COUNT] = {
TAB_MAP(WIFIBAND),
TAB_MAP(I2C_COMMAN

[PATCH 1/4] drm/amd/pm: update SMU13 header files for coming OD support

[Evan Quan]

Correct the data structures for OD feature support.

Signed-off-by: Evan Quan 
---
 .../gpu/drm/amd/pm/inc/smu_v13_0_0_pptable.h  | 16 +-
 .../inc/pmfw_if/smu13_driver_if_v13_0_0.h | 18 +++-
 .../inc/pmfw_if/smu13_driver_if_v13_0_7.h | 29 ---
 .../amd/pm/swsmu/inc/smu_v13_0_7_pptable.h| 16 +-
 4 files changed, 34 insertions(+), 45 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v13_0_0_pptable.h 
b/drivers/gpu/drm/amd/pm/inc/smu_v13_0_0_pptable.h
index 566a0da59e53..1dc7a065a6d4 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_v13_0_0_pptable.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v13_0_0_pptable.h
@@ -38,13 +38,12 @@
 #define SMU_13_0_0_PP_THERMALCONTROLLER_NONE 0
 #define SMU_13_0_0_PP_THERMALCONTROLLER_NAVI21 28
 
-#define SMU_13_0_0_PP_OVERDRIVE_VERSION 0x81// OverDrive 8 Table 
Version 0.2
+#define SMU_13_0_0_PP_OVERDRIVE_VERSION 0x83// OverDrive 8 Table 
Version 0.2
 #define SMU_13_0_0_PP_POWERSAVINGCLOCK_VERSION 0x01 // Power Saving Clock 
Table Version 1.00
 
 enum SMU_13_0_0_ODFEATURE_CAP
 {
 SMU_13_0_0_ODCAP_GFXCLK_LIMITS = 0,
-SMU_13_0_0_ODCAP_GFXCLK_CURVE,
 SMU_13_0_0_ODCAP_UCLK_LIMITS,
 SMU_13_0_0_ODCAP_POWER_LIMIT,
 SMU_13_0_0_ODCAP_FAN_ACOUSTIC_LIMIT,
@@ -59,13 +58,13 @@ enum SMU_13_0_0_ODFEATURE_CAP
 SMU_13_0_0_ODCAP_FAN_CURVE,
 SMU_13_0_0_ODCAP_AUTO_FAN_ACOUSTIC_LIMIT,
 SMU_13_0_0_ODCAP_POWER_MODE,
+SMU_13_0_0_ODCAP_PER_ZONE_GFX_VOLTAGE_OFFSET,
 SMU_13_0_0_ODCAP_COUNT,
 };
 
 enum SMU_13_0_0_ODFEATURE_ID
 {
 SMU_13_0_0_ODFEATURE_GFXCLK_LIMITS   = 1 << 
SMU_13_0_0_ODCAP_GFXCLK_LIMITS,   //GFXCLK Limit feature
-SMU_13_0_0_ODFEATURE_GFXCLK_CURVE= 1 << 
SMU_13_0_0_ODCAP_GFXCLK_CURVE,//GFXCLK Curve feature
 SMU_13_0_0_ODFEATURE_UCLK_LIMITS = 1 << 
SMU_13_0_0_ODCAP_UCLK_LIMITS, //UCLK Limit feature
 SMU_13_0_0_ODFEATURE_POWER_LIMIT = 1 << 
SMU_13_0_0_ODCAP_POWER_LIMIT, //Power Limit feature
 SMU_13_0_0_ODFEATURE_FAN_ACOUSTIC_LIMIT  = 1 << 
SMU_13_0_0_ODCAP_FAN_ACOUSTIC_LIMIT,  //Fan Acoustic RPM feature
@@ -80,6 +79,7 @@ enum SMU_13_0_0_ODFEATURE_ID
 SMU_13_0_0_ODFEATURE_FAN_CURVE   = 1 << 
SMU_13_0_0_ODCAP_FAN_CURVE,   //Fan Curve feature
 SMU_13_0_0_ODFEATURE_AUTO_FAN_ACOUSTIC_LIMIT = 1 << 
SMU_13_0_0_ODCAP_AUTO_FAN_ACOUSTIC_LIMIT, //Auto Fan Acoustic RPM feature
 SMU_13_0_0_ODFEATURE_POWER_MODE  = 1 << 
SMU_13_0_0_ODCAP_POWER_MODE,  //Optimized GPU Power Mode feature
+SMU_13_0_0_ODFEATURE_PER_ZONE_GFX_VOLTAGE_OFFSET  = 1 << 
SMU_13_0_0_ODCAP_PER_ZONE_GFX_VOLTAGE_OFFSET,  //Perzone voltage offset feature
 SMU_13_0_0_ODFEATURE_COUNT   = 16,
 };
 
@@ -89,10 +89,6 @@ enum SMU_13_0_0_ODSETTING_ID
 {
 SMU_13_0_0_ODSETTING_GFXCLKFMAX = 0,
 SMU_13_0_0_ODSETTING_GFXCLKFMIN,
-SMU_13_0_0_ODSETTING_CUSTOM_GFX_VF_CURVE_A,
-SMU_13_0_0_ODSETTING_CUSTOM_GFX_VF_CURVE_B,
-SMU_13_0_0_ODSETTING_CUSTOM_GFX_VF_CURVE_C,
-SMU_13_0_0_ODSETTING_CUSTOM_CURVE_VFT_FMIN,
 SMU_13_0_0_ODSETTING_UCLKFMIN,
 SMU_13_0_0_ODSETTING_UCLKFMAX,
 SMU_13_0_0_ODSETTING_POWERPERCENTAGE,
@@ -117,6 +113,12 @@ enum SMU_13_0_0_ODSETTING_ID
 SMU_13_0_0_ODSETTING_FAN_CURVE_SPEED_5,
 SMU_13_0_0_ODSETTING_AUTO_FAN_ACOUSTIC_LIMIT,
 SMU_13_0_0_ODSETTING_POWER_MODE,
+SMU_13_0_0_ODSETTING_PER_ZONE_GFX_VOLTAGE_OFFSET_POINT_1,
+SMU_13_0_0_ODSETTING_PER_ZONE_GFX_VOLTAGE_OFFSET_POINT_2,
+SMU_13_0_0_ODSETTING_PER_ZONE_GFX_VOLTAGE_OFFSET_POINT_3,
+SMU_13_0_0_ODSETTING_PER_ZONE_GFX_VOLTAGE_OFFSET_POINT_4,
+SMU_13_0_0_ODSETTING_PER_ZONE_GFX_VOLTAGE_OFFSET_POINT_5,
+SMU_13_0_0_ODSETTING_PER_ZONE_GFX_VOLTAGE_OFFSET_POINT_6,
 SMU_13_0_0_ODSETTING_COUNT,
 };
 #define SMU_13_0_0_MAX_ODSETTING 64 //Maximum Number of ODSettings
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h 
b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h
index fdcc99ebd050..91e0f3f7c80a 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h
@@ -678,7 +678,14 @@ typedef enum {
 
 #define PP_NUM_RTAVFS_PWL_ZONES 5
 
-
+#define PP_OD_FEATURE_GFX_VF_CURVE_BIT  0
+#define PP_OD_FEATURE_PPT_BIT   2
+#define PP_OD_FEATURE_FAN_CURVE_BIT 3
+#define PP_OD_FEATURE_GFXCLK_BIT  7
+#define PP_OD_FEATURE_UCLK_BIT  8
+#define PP_OD_FEATURE_ZERO_FAN_BIT  9
+#define PP_OD_FEATURE_TEMPERATURE_BIT 10
+#define PP_OD_FEATURE_COUNT 13
 
 // VBIOS or PPLIB configures telemetry slope and offset. Only slope expected 
to be set for SVI3
 // Slope Q1.7, Offset Q1.2
@@ -700,10 +707,8 @@ typedef struct {
 
   //Voltage control
   int16_t
VoltageOffsetPerZoneBoundary[PP_NUM_OD_VF_CURVE_POINTS];
-  uint16_t   VddGfxVmax; // in mV
 
-  uint8_t   

[PATCH 0/4] Enable legacy OD support for SMU13

[Evan Quan]

Enable the following OD features support for SMU13:
- Maxinum and minimum gfxclk frequency settings
- Maxinum and minimum uclk frequency settings
- Voltage offset settings for gfxclk v/f curve line
  - This is quite different from previous generations/ASICs. For SMU13,
there are six anchor points defined on the v/f curve. And what user
configurable are the voltage offsets for those anchor points.

Evan Quan (4):
  drm/amd/pm: update SMU13 header files for coming OD support
  drm/amd/pm: fulfill SMU13 OD settings init and restore
  drm/amd/pm: fulfill the OD support for SMU13.0.0
  drm/amd/pm: fulfill the OD support for SMU13.0.7

 drivers/gpu/drm/amd/pm/amdgpu_pm.c|  26 +-
 .../gpu/drm/amd/pm/inc/smu_v13_0_0_pptable.h  |  16 +-
 .../inc/pmfw_if/smu13_driver_if_v13_0_0.h |  18 +-
 .../inc/pmfw_if/smu13_driver_if_v13_0_7.h |  29 +-
 .../amd/pm/swsmu/inc/smu_v13_0_7_pptable.h|  16 +-
 .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c|  13 +-
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c  | 488 +-
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c  | 487 -
 8 files changed, 1038 insertions(+), 55 deletions(-)

-- 
2.34.1

[PATCH] drm/amd/pm: Vangogh: Add new gpu_metrics_v2_4 to acquire gpu_metrics

[Wenyou Yang]

To acquire the voltage and current info from gpu_metrics interface,
but gpu_metrics_v2_3 doesn't contain them, and to be backward compatible,
add new gpu_metrics_v2_4 structure.

Acked-by: Evan Quan 
Signed-off-by: Wenyou Yang 
---
 .../gpu/drm/amd/include/kgd_pp_interface.h|  69 +++
 .../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c  | 109 --
 drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c|   3 +
 3 files changed, 172 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h 
b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index 9f542f6e19ed..0f37dafafcf9 100644
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -892,4 +892,73 @@ struct gpu_metrics_v2_3 {
uint16_taverage_temperature_core[8]; // average 
CPU core temperature on APUs
uint16_taverage_temperature_l3[2];
 };
+
+struct gpu_metrics_v2_4 {
+   struct metrics_table_header common_header;
+
+   /* Temperature */
+   uint16_ttemperature_gfx;
+   uint16_ttemperature_soc;
+   uint16_ttemperature_core[8];
+   uint16_ttemperature_l3[2];
+
+   /* Utilization */
+   uint16_taverage_gfx_activity;
+   uint16_taverage_mm_activity;
+
+   /* Driver attached timestamp (in ns) */
+   uint64_tsystem_clock_counter;
+
+   /* Power/Energy */
+   uint16_taverage_socket_power;
+   uint16_taverage_cpu_power;
+   uint16_taverage_soc_power;
+   uint16_taverage_gfx_power;
+   uint16_taverage_core_power[8];
+
+   /* Average clocks */
+   uint16_taverage_gfxclk_frequency;
+   uint16_taverage_socclk_frequency;
+   uint16_taverage_uclk_frequency;
+   uint16_taverage_fclk_frequency;
+   uint16_taverage_vclk_frequency;
+   uint16_taverage_dclk_frequency;
+
+   /* Current clocks */
+   uint16_tcurrent_gfxclk;
+   uint16_tcurrent_socclk;
+   uint16_tcurrent_uclk;
+   uint16_tcurrent_fclk;
+   uint16_tcurrent_vclk;
+   uint16_tcurrent_dclk;
+   uint16_tcurrent_coreclk[8];
+   uint16_tcurrent_l3clk[2];
+
+   /* Throttle status (ASIC dependent) */
+   uint32_tthrottle_status;
+
+   /* Fans */
+   uint16_tfan_pwm;
+
+   uint16_tpadding[3];
+
+   /* Throttle status (ASIC independent) */
+   uint64_tindep_throttle_status;
+
+   /* Average Temperature */
+   uint16_taverage_temperature_gfx;
+   uint16_taverage_temperature_soc;
+   uint16_taverage_temperature_core[8];
+   uint16_taverage_temperature_l3[2];
+
+   /* Power/Voltage */
+   uint16_taverage_cpu_voltage;
+   uint16_taverage_soc_voltage;
+   uint16_taverage_gfx_voltage;
+
+   /* Power/Current */
+   uint16_taverage_cpu_current;
+   uint16_taverage_soc_current;
+   uint16_taverage_gfx_current;
+};
 #endif
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
index 067b4e0b026c..185d0b50ee8e 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
@@ -1854,6 +1854,86 @@ static ssize_t vangogh_get_gpu_metrics_v2_3(struct 
smu_context *smu,
return sizeof(struct gpu_metrics_v2_3);
 }
 
+static ssize_t vangogh_get_gpu_metrics_v2_4(struct smu_context *smu,
+   void **table)
+{
+   SmuMetrics_t metrics;
+   struct smu_table_context *smu_table = &smu->smu_table;
+   struct gpu_metrics_v2_4 *gpu_metrics =
+   (struct gpu_metrics_v2_4 
*)smu_table->gpu_metrics_table;
+   int ret = 0;
+
+   ret = smu_cmn_get_metrics_table(smu, &metrics, true);
+   if (ret)
+   return ret;
+
+   smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 4);
+
+   gpu_metrics->temperature_gfx = metrics.Current.GfxTemperature;
+   gpu_metrics->temperature_soc = metrics.Current.SocTemperature;
+   memcp

RE: [PATCH 01/33] drm/amdkfd: add debug and runtime enable interface

[Kim, Jonathan]

[Public]

> -Original Message-
> From: Alex Deucher 
> Sent: Wednesday, May 31, 2023 2:15 PM
> To: Kuehling, Felix 
> Cc: Kim, Jonathan ; amd-
> g...@lists.freedesktop.org; dri-de...@lists.freedesktop.org; Huang, JinHuiEric
> 
> Subject: Re: [PATCH 01/33] drm/amdkfd: add debug and runtime enable
> interface
>
> Caution: This message originated from an External Source. Use proper
> caution when opening attachments, clicking links, or responding.
>
>
> On Tue, May 30, 2023 at 3:17 PM Felix Kuehling 
> wrote:
> >
> > Am 2023-05-25 um 13:27 schrieb Jonathan Kim:
> > > Introduce the GPU debug operations interface.
> > >
> > > For ROCm-GDB to extend the GNU Debugger's ability to inspect the AMD
> GPU
> > > instruction set, provide the necessary interface to allow the debugger
> > > to HW debug-mode set and query exceptions per HSA queue, process or
> > > device.
> > >
> > > The runtime_enable interface coordinates exception handling with the
> > > HSA runtime.
> > >
> > > Usage is available in the kern docs at uapi/linux/kfd_ioctl.h.
> > >
> > > v2: add num_xcc to device snapshot entry.
> > > fixup missing EC_QUEUE_PACKET_RESERVED mask.
> > >
> > > Signed-off-by: Jonathan Kim 
> >
> > Reviewed-by: Felix Kuehling 
>
> Can you provide a link to the userspace which uses this?

Hi Alex,

Current WIP user space link is here -> 
https://github.com/ROCm-Developer-Tools/ROCdbgapi/tree/wip-dbgapi.
This will eventually go to amd-master.

Thanks,

Jon

>
> Alex
>
> >
> >
> > > ---
> > >   drivers/gpu/drm/amd/amdkfd/kfd_chardev.c |  48 ++
> > >   include/uapi/linux/kfd_ioctl.h   | 668 ++-
> > >   2 files changed, 715 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
> b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
> > > index 88fe1f31739d..f4b50b74818e 100644
> > > --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
> > > +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
> > > @@ -2729,6 +2729,48 @@ static int kfd_ioctl_criu(struct file *filep, 
> > > struct
> kfd_process *p, void *data)
> > >   return ret;
> > >   }
> > >
> > > +static int kfd_ioctl_runtime_enable(struct file *filep, struct 
> > > kfd_process
> *p, void *data)
> > > +{
> > > + return 0;
> > > +}
> > > +
> > > +static int kfd_ioctl_set_debug_trap(struct file *filep, struct 
> > > kfd_process
> *p, void *data)
> > > +{
> > > + struct kfd_ioctl_dbg_trap_args *args = data;
> > > + int r = 0;
> > > +
> > > + if (sched_policy == KFD_SCHED_POLICY_NO_HWS) {
> > > + pr_err("Debugging does not support sched_policy %i",
> sched_policy);
> > > + return -EINVAL;
> > > + }
> > > +
> > > + switch (args->op) {
> > > + case KFD_IOC_DBG_TRAP_ENABLE:
> > > + case KFD_IOC_DBG_TRAP_DISABLE:
> > > + case KFD_IOC_DBG_TRAP_SEND_RUNTIME_EVENT:
> > > + case KFD_IOC_DBG_TRAP_SET_EXCEPTIONS_ENABLED:
> > > + case KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_OVERRIDE:
> > > + case KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_MODE:
> > > + case KFD_IOC_DBG_TRAP_SUSPEND_QUEUES:
> > > + case KFD_IOC_DBG_TRAP_RESUME_QUEUES:
> > > + case KFD_IOC_DBG_TRAP_SET_NODE_ADDRESS_WATCH:
> > > + case KFD_IOC_DBG_TRAP_CLEAR_NODE_ADDRESS_WATCH:
> > > + case KFD_IOC_DBG_TRAP_SET_FLAGS:
> > > + case KFD_IOC_DBG_TRAP_QUERY_DEBUG_EVENT:
> > > + case KFD_IOC_DBG_TRAP_QUERY_EXCEPTION_INFO:
> > > + case KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT:
> > > + case KFD_IOC_DBG_TRAP_GET_DEVICE_SNAPSHOT:
> > > + pr_warn("Debugging not supported yet\n");
> > > + r = -EACCES;
> > > + break;
> > > + default:
> > > + pr_err("Invalid option: %i\n", args->op);
> > > + r = -EINVAL;
> > > + }
> > > +
> > > + return r;
> > > +}
> > > +
> > >   #define AMDKFD_IOCTL_DEF(ioctl, _func, _flags) \
> > >   [_IOC_NR(ioctl)] = {.cmd = ioctl, .func = _func, .flags = _flags, \
> > >   .cmd_drv = 0, .name = #ioctl}
> > > @@ -2841,6 +2883,12 @@ static const struct amdkfd_ioctl_desc
> amdkfd_ioctls[] = {
> > >
> > >   AMDKFD_IOCTL_DEF(AMDKFD_IOC_EXPORT_DMABUF,
> > >   kfd_ioctl_export_dmabuf, 0),
> > > +
> > > + AMDKFD_IOCTL_DEF(AMDKFD_IOC_RUNTIME_ENABLE,
> > > + kfd_ioctl_runtime_enable, 0),
> > > +
> > > + AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_TRAP,
> > > + kfd_ioctl_set_debug_trap, 0),
> > >   };
> > >
> > >   #define AMDKFD_CORE_IOCTL_COUNT ARRAY_SIZE(amdkfd_ioctls)
> > > diff --git a/include/uapi/linux/kfd_ioctl.h 
> > > b/include/uapi/linux/kfd_ioctl.h
> > > index 2a9671e1ddb5..dfe745ee427e 100644
> > > --- a/include/uapi/linux/kfd_ioctl.h
> > > +++ b/include/uapi/linux/kfd_ioctl.h
> > > @@ -110,6 +110,32 @@ struct kfd_ioctl_get_available_memory_args {
> > >   __u32 pad;
> > >   };
> > >
> > > +struct kfd_dbg_device_info_entry {
> > > + __u64 exception_status;
> > > + __u64 lds_base;
> > > + __u6

Re: [PATCH] drm/amdkfd: remove unused sq_int_priv variable

[Alex Deucher]

On Thu, Mar 30, 2023 at 12:04 PM Kim, Jonathan  wrote:
>
> [Public]
>
> Hi Felix,
>
> That is correct.  The debugger will need sq_int_priv to work.

I'll just apply this for now.  We can squash the revert into the
debugger changes once those land.

Alex

>
> Thanks,
>
> Jon
>
> > -Original Message-
> > From: Kuehling, Felix 
> > Sent: Thursday, March 30, 2023 11:39 AM
> > To: Tom Rix ; Deucher, Alexander
> > ; Koenig, Christian
> > ; Pan, Xinhui ;
> > airl...@gmail.com; dan...@ffwll.ch; nat...@kernel.org;
> > ndesaulni...@google.com; Kim, Jonathan 
> > Cc: amd-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org; linux-
> > ker...@vger.kernel.org; l...@lists.linux.dev
> > Subject: Re: [PATCH] drm/amdkfd: remove unused sq_int_priv variable
> >
> > Am 2023-03-30 um 11:20 schrieb Tom Rix:
> > > clang with W=1 reports
> > > drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_int_process_v11.c:282:38:
> > error: variable
> > >'sq_int_priv' set but not used [-Werror,-Wunused-but-set-variable]
> > >  uint8_t sq_int_enc, sq_int_errtype, sq_int_priv;
> > >  ^
> > > This variable is not used so remove it.
> >
> > Hi Jon,
> >
> > I think your debugger patches are going to start using this. Can you
> > comment?
> >
> > I'd prefer not to apply this patch now, as Jon's patches are expected to
> > land soon, once Alex is done upstreaming GFX 9.4.3 support.
> >
> > Regards,
> >Felix
> >
> >
> > >
> > > Signed-off-by: Tom Rix 
> > > ---
> > >   drivers/gpu/drm/amd/amdkfd/kfd_int_process_v11.c | 9 +
> > >   1 file changed, 1 insertion(+), 8 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v11.c
> > b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v11.c
> > > index 0d53f6067422..bbd646c0dee7 100644
> > > --- a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v11.c
> > > +++ b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v11.c
> > > @@ -279,7 +279,7 @@ static void event_interrupt_wq_v11(struct kfd_dev
> > *dev,
> > >   {
> > > uint16_t source_id, client_id, ring_id, pasid, vmid;
> > > uint32_t context_id0, context_id1;
> > > -   uint8_t sq_int_enc, sq_int_errtype, sq_int_priv;
> > > +   uint8_t sq_int_enc, sq_int_errtype;
> > > struct kfd_vm_fault_info info = {0};
> > > struct kfd_hsa_memory_exception_data exception_data;
> > >
> > > @@ -348,13 +348,6 @@ static void event_interrupt_wq_v11(struct kfd_dev
> > *dev,
> > > break;
> > > case SQ_INTERRUPT_WORD_ENCODING_INST:
> > > print_sq_intr_info_inst(context_id0,
> > context_id1);
> > > -   sq_int_priv = REG_GET_FIELD(context_id0,
> > > -
> >   SQ_INTERRUPT_WORD_WAVE_CTXID0, PRIV);
> > > -   /*if (sq_int_priv &&
> > (kfd_set_dbg_ev_from_interrupt(dev, pasid,
> > > -
> >   KFD_CTXID0_DOORBELL_ID(context_id0),
> > > -
> >   KFD_CTXID0_TRAP_CODE(context_id0),
> > > -   NULL, 0)))
> > > -   return;*/
> > > break;
> > > case SQ_INTERRUPT_WORD_ENCODING_ERROR:
> > > print_sq_intr_info_error(context_id0,
> > context_id1);

Re: [PATCH] drm/amdgpu: Add function parameter 'event' to kdoc in svm_range_evict()

[Felix Kuehling]

Am 2023-05-31 um 14:10 schrieb Srinivasan Shanmugam:

Fixes the following gcc with W=1:

drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_svm.c:1841: warning: Function 
parameter or member 'event' not described in 'svm_range_evict'

Cc: Felix Kuehling 
Cc: Christian König 
Cc: Alex Deucher 
Signed-off-by: Srinivasan Shanmugam 


Reviewed-by: Felix Kuehling 



---
  drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 1 +
  1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
index 84bb5bc6e731..338d7df04773 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
@@ -1825,6 +1825,7 @@ static void svm_range_restore_work(struct work_struct 
*work)
   * @mm: current process mm_struct
   * @start: starting process queue number
   * @last: last process queue number
+ * @event: mmu notifier event when range is evicted or migrated
   *
   * Stop all queues of the process to ensure GPU doesn't access the memory, 
then
   * return to let CPU evict the buffer and proceed CPU pagetable update.

Re: [PATCH 01/33] drm/amdkfd: add debug and runtime enable interface

[Alex Deucher]

On Tue, May 30, 2023 at 3:17 PM Felix Kuehling  wrote:
>
> Am 2023-05-25 um 13:27 schrieb Jonathan Kim:
> > Introduce the GPU debug operations interface.
> >
> > For ROCm-GDB to extend the GNU Debugger's ability to inspect the AMD GPU
> > instruction set, provide the necessary interface to allow the debugger
> > to HW debug-mode set and query exceptions per HSA queue, process or
> > device.
> >
> > The runtime_enable interface coordinates exception handling with the
> > HSA runtime.
> >
> > Usage is available in the kern docs at uapi/linux/kfd_ioctl.h.
> >
> > v2: add num_xcc to device snapshot entry.
> > fixup missing EC_QUEUE_PACKET_RESERVED mask.
> >
> > Signed-off-by: Jonathan Kim 
>
> Reviewed-by: Felix Kuehling 

Can you provide a link to the userspace which uses this?

Alex

>
>
> > ---
> >   drivers/gpu/drm/amd/amdkfd/kfd_chardev.c |  48 ++
> >   include/uapi/linux/kfd_ioctl.h   | 668 ++-
> >   2 files changed, 715 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c 
> > b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
> > index 88fe1f31739d..f4b50b74818e 100644
> > --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
> > +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
> > @@ -2729,6 +2729,48 @@ static int kfd_ioctl_criu(struct file *filep, struct 
> > kfd_process *p, void *data)
> >   return ret;
> >   }
> >
> > +static int kfd_ioctl_runtime_enable(struct file *filep, struct kfd_process 
> > *p, void *data)
> > +{
> > + return 0;
> > +}
> > +
> > +static int kfd_ioctl_set_debug_trap(struct file *filep, struct kfd_process 
> > *p, void *data)
> > +{
> > + struct kfd_ioctl_dbg_trap_args *args = data;
> > + int r = 0;
> > +
> > + if (sched_policy == KFD_SCHED_POLICY_NO_HWS) {
> > + pr_err("Debugging does not support sched_policy %i", 
> > sched_policy);
> > + return -EINVAL;
> > + }
> > +
> > + switch (args->op) {
> > + case KFD_IOC_DBG_TRAP_ENABLE:
> > + case KFD_IOC_DBG_TRAP_DISABLE:
> > + case KFD_IOC_DBG_TRAP_SEND_RUNTIME_EVENT:
> > + case KFD_IOC_DBG_TRAP_SET_EXCEPTIONS_ENABLED:
> > + case KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_OVERRIDE:
> > + case KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_MODE:
> > + case KFD_IOC_DBG_TRAP_SUSPEND_QUEUES:
> > + case KFD_IOC_DBG_TRAP_RESUME_QUEUES:
> > + case KFD_IOC_DBG_TRAP_SET_NODE_ADDRESS_WATCH:
> > + case KFD_IOC_DBG_TRAP_CLEAR_NODE_ADDRESS_WATCH:
> > + case KFD_IOC_DBG_TRAP_SET_FLAGS:
> > + case KFD_IOC_DBG_TRAP_QUERY_DEBUG_EVENT:
> > + case KFD_IOC_DBG_TRAP_QUERY_EXCEPTION_INFO:
> > + case KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT:
> > + case KFD_IOC_DBG_TRAP_GET_DEVICE_SNAPSHOT:
> > + pr_warn("Debugging not supported yet\n");
> > + r = -EACCES;
> > + break;
> > + default:
> > + pr_err("Invalid option: %i\n", args->op);
> > + r = -EINVAL;
> > + }
> > +
> > + return r;
> > +}
> > +
> >   #define AMDKFD_IOCTL_DEF(ioctl, _func, _flags) \
> >   [_IOC_NR(ioctl)] = {.cmd = ioctl, .func = _func, .flags = _flags, \
> >   .cmd_drv = 0, .name = #ioctl}
> > @@ -2841,6 +2883,12 @@ static const struct amdkfd_ioctl_desc 
> > amdkfd_ioctls[] = {
> >
> >   AMDKFD_IOCTL_DEF(AMDKFD_IOC_EXPORT_DMABUF,
> >   kfd_ioctl_export_dmabuf, 0),
> > +
> > + AMDKFD_IOCTL_DEF(AMDKFD_IOC_RUNTIME_ENABLE,
> > + kfd_ioctl_runtime_enable, 0),
> > +
> > + AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_TRAP,
> > + kfd_ioctl_set_debug_trap, 0),
> >   };
> >
> >   #define AMDKFD_CORE_IOCTL_COUNT ARRAY_SIZE(amdkfd_ioctls)
> > diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h
> > index 2a9671e1ddb5..dfe745ee427e 100644
> > --- a/include/uapi/linux/kfd_ioctl.h
> > +++ b/include/uapi/linux/kfd_ioctl.h
> > @@ -110,6 +110,32 @@ struct kfd_ioctl_get_available_memory_args {
> >   __u32 pad;
> >   };
> >
> > +struct kfd_dbg_device_info_entry {
> > + __u64 exception_status;
> > + __u64 lds_base;
> > + __u64 lds_limit;
> > + __u64 scratch_base;
> > + __u64 scratch_limit;
> > + __u64 gpuvm_base;
> > + __u64 gpuvm_limit;
> > + __u32 gpu_id;
> > + __u32 location_id;
> > + __u32 vendor_id;
> > + __u32 device_id;
> > + __u32 revision_id;
> > + __u32 subsystem_vendor_id;
> > + __u32 subsystem_device_id;
> > + __u32 fw_version;
> > + __u32 gfx_target_version;
> > + __u32 simd_count;
> > + __u32 max_waves_per_simd;
> > + __u32 array_count;
> > + __u32 simd_arrays_per_engine;
> > + __u32 num_xcc;
> > + __u32 capability;
> > + __u32 debug_prop;
> > +};
> > +
> >   /* For kfd_ioctl_set_memory_policy_args.default_policy and 
> > alternate_policy */
> >   #define KFD_IOC_CACHE_POLICY_COHERENT 0
> >   #define KFD_IOC_CACHE_POLICY_NONCOHERENT 1
> > @@ -775,6 +801,640 @@ struct kfd_ioctl_set_x

Re: [PATCH] drm/amdgpu: Fix up kdoc in amdgpu_device.c

[Alex Deucher]

Reviewed-by: Alex Deucher 

On Thu, May 25, 2023 at 1:29 PM Srinivasan Shanmugam
 wrote:
>
> Fix these warnings by deleting the deviant arguments.
>
> gcc with W=1
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:799: warning: Excess function 
> parameter 'pcie_index' description in 'amdgpu_device_indirect_wreg'
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:799: warning: Excess function 
> parameter 'pcie_data' description in 'amdgpu_device_indirect_wreg'
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:870: warning: Excess function 
> parameter 'pcie_index' description in 'amdgpu_device_indirect_wreg64'
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:870: warning: Excess function 
> parameter 'pcie_data' description in 'amdgpu_device_indirect_wreg64'
>
> Cc: Christian König 
> Cc: Alex Deucher 
> Signed-off-by: Srinivasan Shanmugam 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 
>  1 file changed, 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index c1e9ed26b7bf..301abfb7a0d3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -788,8 +788,6 @@ u64 amdgpu_device_indirect_rreg64(struct amdgpu_device 
> *adev,
>   * amdgpu_device_indirect_wreg - write an indirect register address
>   *
>   * @adev: amdgpu_device pointer
> - * @pcie_index: mmio register offset
> - * @pcie_data: mmio register offset
>   * @reg_addr: indirect register offset
>   * @reg_data: indirect register data
>   *
> @@ -859,8 +857,6 @@ void amdgpu_device_indirect_wreg_ext(struct amdgpu_device 
> *adev,
>   * amdgpu_device_indirect_wreg64 - write a 64bits indirect register address
>   *
>   * @adev: amdgpu_device pointer
> - * @pcie_index: mmio register offset
> - * @pcie_data: mmio register offset
>   * @reg_addr: indirect register offset
>   * @reg_data: indirect register data
>   *
> --
> 2.25.1
>

[PATCH] drm/amdgpu: Add function parameter 'event' to kdoc in svm_range_evict()

[Srinivasan Shanmugam]

Fixes the following gcc with W=1:

drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_svm.c:1841: warning: Function 
parameter or member 'event' not described in 'svm_range_evict'

Cc: Felix Kuehling 
Cc: Christian König 
Cc: Alex Deucher 
Signed-off-by: Srinivasan Shanmugam 
---
 drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
index 84bb5bc6e731..338d7df04773 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
@@ -1825,6 +1825,7 @@ static void svm_range_restore_work(struct work_struct 
*work)
  * @mm: current process mm_struct
  * @start: starting process queue number
  * @last: last process queue number
+ * @event: mmu notifier event when range is evicted or migrated
  *
  * Stop all queues of the process to ensure GPU doesn't access the memory, then
  * return to let CPU evict the buffer and proceed CPU pagetable update.
-- 
2.25.1

Re: [PATCH] drm/amdgpu: Fix up kdoc 'ring' parameter in sdma_v6_0_ring_pad_ib

[Alex Deucher]

Reviewed-by: Alex Deucher 

On Tue, May 30, 2023 at 2:49 PM Srinivasan Shanmugam
 wrote:
>
> Fix this warning by adding 'ring' arguments to kdoc.
>
> gcc with W=1
> drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c:1128: warning: Function parameter or 
> member 'ring' not described in 'sdma_v6_0_ring_pad_ib'
>
> Cc: Felix Kuehling 
> Cc: Christian König 
> Cc: Alex Deucher 
> Signed-off-by: Srinivasan Shanmugam 
> ---
>  drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c 
> b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
> index 967849c59ebe..3b03dda854fd 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
> @@ -1121,6 +1121,7 @@ static void sdma_v6_0_vm_set_pte_pde(struct amdgpu_ib 
> *ib,
>  /**
>   * sdma_v6_0_ring_pad_ib - pad the IB
>   * @ib: indirect buffer to fill with padding
> + * @ring: amdgpu ring pointer
>   *
>   * Pad the IB with NOPs to a boundary multiple of 8.
>   */
> --
> 2.25.1
>

[PATCH v2] drm/amd/display: Drop unused DCN_BASE variable in dcn314_resource.c

[Srinivasan Shanmugam]

Fixes the following W=1 kernel build warning:

drivers/gpu/drm/amd/amdgpu/../display/dc/dcn314/dcn314_resource.c:128:29: 
warning: ‘DCN_BASE’ defined but not used [-Wunused-const-variable=]
  128 | static const struct IP_BASE DCN_BASE = { { { { 0x0012, 0x00C0, 
0x34C0, 0x9000, 0x02403C00, 0, 0, 0 } },
  | ^~~~

Suggested-by: Roman Li 
Cc: Hamza Mahfooz 
Cc: Rodrigo Siqueira 
Cc: Harry Wentland 
Cc: Aurabindo Pillai 
Signed-off-by: Srinivasan Shanmugam 
---

v2:
 - Remove even unused IP_BASE_INSTANCE and IP_BASE struct definitions
   altogether (Roman)

 .../drm/amd/display/dc/dcn314/dcn314_resource.c | 17 -
 1 file changed, 17 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
index 3592efcc7fae..837884c4f03a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
@@ -117,23 +117,6 @@
 #define regBIF_BX2_BIOS_SCRATCH_6  0x003e
 #define regBIF_BX2_BIOS_SCRATCH_6_BASE_IDX 1
 
-struct IP_BASE_INSTANCE {
-   unsigned int segment[MAX_SEGMENT];
-};
-
-struct IP_BASE {
-   struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
-};
-
-static const struct IP_BASE DCN_BASE = { { { { 0x0012, 0x00C0, 
0x34C0, 0x9000, 0x02403C00, 0, 0, 0 } },
-   { { 0, 0, 0, 0, 0, 0, 0, 0 } },
-   { { 0, 0, 0, 0, 0, 0, 0, 0 } },
-   { { 0, 0, 0, 0, 0, 0, 0, 0 } },
-   { { 0, 0, 0, 0, 0, 0, 0, 0 } },
-   { { 0, 0, 0, 0, 0, 0, 0, 0 } },
-   { { 0, 0, 0, 0, 0, 0, 0, 0 } } } };
-
-
 #define DC_LOGGER_INIT(logger)
 
 enum dcn31_clk_src_array_id {
-- 
2.25.1

Re: [PATCH] drm/amdgpu/gfx9: switch to golden tsc registers for raven/raven2

[Michel Dänzer]

On 5/31/23 16:01, Alex Deucher wrote:
> On Mon, May 29, 2023 at 5:45 AM Michel Dänzer  wrote:
>>
>> On 4/12/23 03:23, Zhang, Jesse(Jie) wrote:
>>>
>>>   Due to raven/raven2 maybe enable  sclk slow down,
>>> they cannot get clock count by the RLC at the auto level of dpm 
>>> performance.
>>> So switch to golden tsc register.
>>
>> At least on this ThinkPad E595 with Picasso, the issue with this change (and 
>> the corresponding fbc24293ca16 "drm/amdgpu: change the reference clock for 
>> raven/raven2" & 9d2d1827af29 "drm/amdgpu: Differentiate between Raven2 and 
>> Raven/Picasso according to revision id") is that the GPU timestamps reported 
>> via the AMDGPU_INFO ioctl are no longer consistent with those reported via 
>> asynchronous GPU queries (e.g. via glQuery with GL_TIMESTAMP). The latter 
>> are still affected by clock changes, and even when the clock doesn't stop 
>> altogether, they still tick at 25 MHz, so the two kinds of GPU timestamps 
>> keep diverging further.
> 
> fbc24293ca16 "drm/amdgpu: change the reference clock for raven/raven2"
> would also affect that.  Were you seeing the same results with that
> patch as well?

Yes. That one is problematic because user space uses the reference clock for 
converting the results of asynchronous GPU queries from clock ticks to seconds. 
Since that clock still ticks at 25 MHz, the computed values in seconds are 
incorrect and keep diverging further from the corresponding values from the 
AMDGPU_INFO ioctl.


>> This makes it impossible to determine the wall clock time at which a certain 
>> GPU job finished. GNOME's mutter uses this for adaptive frame scheduling.
>>
>> You can see the issue with the piglit test arb_timer_query-timestamp-get or 
>> with the Vulkan CTS tests 
>> dEQP-VK.pipeline.monolithic.timestamp.calibrated.*. (Note that some of these 
>> tests could already fail before with GFXOFF enabled, the symptoms are 
>> slightly different though)
>>
>>
>> An ideal long-term solution for this might be to modify the GPU microcode to 
>> use the golden registers for asynchronous timestamp queries as well.

Any thoughts on whether or not this might be feasible?


>> In the meantime though, these changes need to be reverted for 6.4, at least 
>> for Picasso.


-- 
Earthling Michel Dänzer|  https://redhat.com
Libre software enthusiast  | Mesa and Xwayland developer

Re: [PATCH] drm/amd: SVM flag error added at svm_range flags

[Felix Kuehling]

This flag was never meant for user mode. Alex ended up implementing it 
differently in a way that doesn't need to change the flags exposed to 
user mode. See his patch "drm/amdkfd: flag added to handle errors from 
svm validate and map". This patch is no longer needed.



Regards,
  Felix


Am 2023-05-31 um 10:09 schrieb Deucher, Alexander:


[Public]


Where is the userspace code which uses this new interface? Can you add 
a link to the relevant branch to the commit message?


Alex

*From:* amd-gfx  on behalf of 
Alex Sierra 

*Sent:* Monday, May 29, 2023 4:09 PM
*To:* amd-gfx@lists.freedesktop.org ; 
Kuehling, Felix 
*Cc:* Sierra Guiza, Alejandro (Alex) ; Yang, 
Philip 

*Subject:* [PATCH] drm/amd: SVM flag error added at svm_range flags
If a return error is raised during validation and mapping of a
prange, this flag is set. It is a rare occurrence, but it could happen
when `amdgpu_hmm_range_get_pages_done` returns true. In such cases,
the caller should retry. However, it is important to ensure that the
prange is updated correctly during the retry.

Signed-off-by: Alex Sierra 
---
 drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 12 +++-
 include/uapi/linux/kfd_ioctl.h   |  2 ++
 2 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c

index fcfde9140bce..96abae515bcf 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
@@ -756,10 +756,12 @@ svm_range_apply_attrs(struct kfd_process *p, 
struct svm_range *prange,

 break;
 case KFD_IOCTL_SVM_ATTR_SET_FLAGS:
 *update_mapping = true;
+   attrs[i].value &= ~KFD_IOCTL_SVM_FLAG_ERROR;
 prange->flags |= attrs[i].value;
 break;
 case KFD_IOCTL_SVM_ATTR_CLR_FLAGS:
 *update_mapping = true;
+   attrs[i].value &= ~KFD_IOCTL_SVM_FLAG_ERROR;
 prange->flags &= ~attrs[i].value;
 break;
 case KFD_IOCTL_SVM_ATTR_GRANULARITY:
@@ -778,6 +780,9 @@ svm_range_is_same_attrs(struct kfd_process *p, 
struct svm_range *prange,

 uint32_t i;
 int gpuidx;

+   if (prange->flags & KFD_IOCTL_SVM_FLAG_ERROR)
+   return false;
+
 for (i = 0; i < nattr; i++) {
 switch (attrs[i].type) {
 case KFD_IOCTL_SVM_ATTR_PREFERRED_LOC:
@@ -1657,8 +1662,11 @@ static int svm_range_validate_and_map(struct 
mm_struct *mm,

 unreserve_out:
 svm_range_unreserve_bos(&ctx);

-   if (!r)
+   prange->flags |= KFD_IOCTL_SVM_FLAG_ERROR;
+   if (!r) {
+   prange->flags &= ~KFD_IOCTL_SVM_FLAG_ERROR;
 prange->validate_timestamp = ktime_get_boottime();
+   }

 return r;
 }
@@ -3674,9 +3682,11 @@ svm_range_get_attr(struct kfd_process *p, 
struct mm_struct *mm,

 break;
 case KFD_IOCTL_SVM_ATTR_SET_FLAGS:
 attrs[i].value = flags_and;
+   attrs[i].value &= ~KFD_IOCTL_SVM_FLAG_ERROR;
 break;
 case KFD_IOCTL_SVM_ATTR_CLR_FLAGS:
 attrs[i].value = ~flags_or;
+   attrs[i].value &= ~KFD_IOCTL_SVM_FLAG_ERROR;
 break;
 case KFD_IOCTL_SVM_ATTR_GRANULARITY:
 attrs[i].value = (uint32_t)granularity;
diff --git a/include/uapi/linux/kfd_ioctl.h 
b/include/uapi/linux/kfd_ioctl.h

index 7e19a2d1e907..2b6f68bd06da 100644
--- a/include/uapi/linux/kfd_ioctl.h
+++ b/include/uapi/linux/kfd_ioctl.h
@@ -1125,6 +1125,8 @@ struct kfd_ioctl_cross_memory_copy_deprecated_args {
 #define KFD_IOCTL_SVM_FLAG_GPU_READ_MOSTLY 0x0020
 /* Keep GPU memory mapping always valid as if XNACK is disable */
 #define KFD_IOCTL_SVM_FLAG_GPU_ALWAYS_MAPPED 0x0040
+/* Set during svm validation and map error */
+#define KFD_IOCTL_SVM_FLAG_ERROR   0x8000

 /**
  * kfd_ioctl_svm_op - SVM ioctl operations
--
2.32.0

Re: [PATCH v2] drm/amd/display: Fix up kdoc formatting in dcn32_resource_helpers.c

[Aurabindo Pillai]

Reviewed-by: Aurabindo Pillai 

On 5/31/23 05:22, Srinivasan Shanmugam wrote:
> Fixes the following W=1 kernel build warning:
> 
> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_resource_helpers.c:97: 
> warning: Cannot understand  * 
> **
> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_resource_helpers.c:264: 
> warning: Cannot understand  * 
> *
> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_resource_helpers.c:435: 
> warning: Cannot understand  * 
> *
> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_resource_helpers.c:475: 
> warning: Cannot understand  * 
> *
> 
> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_resource_helpers.c:599:
> warning: Function parameter or member 'dc' not described in
> 'dcn32_can_support_mclk_switch_using_fw_based_vblank_stretch'
> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_resource_helpers.c:599:
> warning: Function parameter or member 'context' not described in
> 'dcn32_can_support_mclk_switch_using_fw_based_vblank_stretch'
> 
> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_resource_helpers.c:587:
> warning: Function parameter or member 'dc' not described in
> 'dcn32_can_support_mclk_switch_using_fw_based_vblank_stretch'
> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_resource_helpers.c:587:
> warning: Function parameter or member 'context' not described in
> 'dcn32_can_support_mclk_switch_using_fw_based_vblank_stretch'
> 
> Cc: Hamza Mahfooz 
> Cc: Rodrigo Siqueira 
> Cc: Harry Wentland 
> Cc: Aurabindo Pillai 
> Signed-off-by: Srinivasan Shanmugam 
> ---
> 
> v2: 
>  - Fixes added for line no. 587 also.
> 
>  .../display/dc/dcn32/dcn32_resource_helpers.c | 57 ---
>  1 file changed, 23 insertions(+), 34 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c 
> b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
> index a8082580df92..1d13fd797212 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
> @@ -94,18 +94,15 @@ uint32_t dcn32_helper_calculate_mall_bytes_for_cursor(
>  }
>  
>  /**
> - * 
> 
> - * dcn32_helper_calculate_num_ways_for_subvp: Calculate number of ways 
> needed for SubVP
> + * dcn32_helper_calculate_num_ways_for_subvp(): Calculate number of ways 
> needed for SubVP
>   *
>   * Gets total allocation required for the phantom viewport calculated by DML 
> in bytes and
>   * converts to number of cache ways.
>   *
> - * @param [in] dc: current dc state
> - * @param [in] context: new dc state
> + * @dc: current dc state
> + * @context: new dc state
>   *
> - * @return: number of ways required for SubVP
> - *
> - * 
> 
> + * Return: number of ways required for SubVP
>   */
>  uint32_t dcn32_helper_calculate_num_ways_for_subvp(
>   struct dc *dc,
> @@ -261,8 +258,7 @@ bool dcn32_is_psr_capable(struct pipe_ctx *pipe)
>  #define DCN3_2_NEW_DET_OVERRIDE_MIN_MULTIPLIER 7
>  
>  /**
> - * 
> ***
> - * dcn32_determine_det_override: Determine DET allocation for each pipe
> + * dcn32_determine_det_override(): Determine DET allocation for each pipe
>   *
>   * This function determines how much DET to allocate for each pipe. The 
> total number of
>   * DET segments will be split equally among each of the streams, and after 
> that the DET
> @@ -290,13 +286,11 @@ bool dcn32_is_psr_capable(struct pipe_ctx *pipe)
>   * 3. Assign smaller DET size for lower pixel display and higher DET size for
>   *higher pixel display
>   *
> - * @param [in]: dc: Current DC state
> - * @param [in]: context: New DC state to be programmed
> - * @param [in]: pipes: Array of DML pipes
> - *
> - * @return: void
> + * @dc: Current DC state
> + * @context: New DC state to be programmed
> + * @pipes: Array of DML pipes
>   *
> - * 
> ***
> + * Return: void
>   */
>  void dcn32_determine_det_override(struct dc *dc,
>   struct dc_state *context,
> @@ -432,8 +426,7 @@ void dcn32_set_det_allocations(struct dc *dc, struct 
> dc_state *context,
>  }
>  
>  /**
> - * 
> ***
> - * dcn32_save_mall_state: Save MALL (SubVP) state for fast validation cases
> + * dcn32_save_mall_state(): Save MALL (SubVP) state for fast validation cases
>   *
>  

Re: [PATCH v2] drm/amd/display: Fix up missing 'dc' & 'pipe_ctx' kdoc parameters in delay_cursor_until_vupdate()

[Aurabindo Pillai]

Reviewed-by: Aurabindo Pillai 

On 5/31/23 01:11, Srinivasan Shanmugam wrote:
> Fixes the following gcc with W=1:
> 
> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:1904: 
> warning: Function parameter or member 'dc' not described in 
> 'delay_cursor_until_vupdate'
> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:1904: 
> warning: Function parameter or member 'pipe_ctx' not described in 
> 'delay_cursor_until_vupdate'
> 
> Cc: Rodrigo Siqueira 
> Cc: Harry Wentland 
> Cc: Aurabindo Pillai 
> Signed-off-by: Srinivasan Shanmugam 
> ---
>  drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 5 +
>  1 file changed, 5 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
> b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
> index 13b4e5118459..20a1582be0b1 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
> @@ -1899,6 +1899,11 @@ void dcn10_pipe_control_lock(
>   *
>   * TODO: Optimize cursor programming to be once per frame before VUPDATE
>   *   to avoid the need for this workaround.
> + *
> + * @dc: Current DC state
> + * @pipe_ctx: Pipe_ctx pointer for delayed cursor update
> + *
> + * Return: void
>   */
>  static void delay_cursor_until_vupdate(struct dc *dc, struct pipe_ctx 
> *pipe_ctx)
>  {

Re: [PATCH] drm/amd/display: Correct kdoc formatting for DCN32_CRB_SEGMENT_SIZE_KB in dcn32_hubbub.c

[Aurabindo Pillai]

Reviewed-by: Aurabindo Pillai 

On 5/30/23 23:52, Srinivasan Shanmugam wrote:
> Fixes the following W=1 kernel build warning:
> 
> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_hubbub.c:45: warning: 
> Cannot understand  * @DCN32_CRB_SEGMENT_SIZE_KB: Maximum Configurable Return 
> Buffer size for
>  on line 45 - I thought it was a doc line
> 
> Cc: Hamza Mahfooz 
> Cc: Rodrigo Siqueira 
> Cc: Harry Wentland 
> Cc: Aurabindo Pillai 
> Signed-off-by: Srinivasan Shanmugam 
> ---
>  drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c 
> b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c
> index eb08ccc38e79..a18b9c0c5709 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c
> @@ -42,8 +42,8 @@
>   hubbub2->shifts->field_name, hubbub2->masks->field_name
>  
>  /**
> - * @DCN32_CRB_SEGMENT_SIZE_KB: Maximum Configurable Return Buffer size for
> - * DCN32
> + * DCN32_CRB_SEGMENT_SIZE_KB: Maximum Configurable Return Buffer size for
> + *DCN32

I think the length limit was increased to 120 characters, so you could put it 
in the same line itself. But with or without it fixed, the patch is:

Reviewed-by: Aurabindo Pillai 

>   */
>  #define DCN32_CRB_SEGMENT_SIZE_KB 64
>  

[PATCH] Revert "drm/amdgpu: Enable VM_CONTEXT1_CNTL after page table addr is set."

[Alex Deucher]

This reverts commit f57a74f5b42d1627bd5366f88952d42819e91146.

After talking this over with Christian, the original programming
sequence was correct.  The enable bit needs to be set before
programming the rest of the context.

Signed-off-by: Alex Deucher 
Cc: Zibin Liu 
---
 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c   | 5 +
 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c   | 5 +
 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c   | 5 +
 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c   | 5 +
 drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c   | 5 +
 drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c | 5 +
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c| 5 +
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c| 5 +
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c| 6 +-
 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c| 5 +
 drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c| 5 +
 drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c| 5 +
 drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c  | 5 +
 drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c  | 5 +
 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c| 7 +--
 15 files changed, 15 insertions(+), 63 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index 52a1e79ee4d8..d94cc1ec7242 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -261,7 +261,7 @@ static void gfxhub_v1_0_setup_vmid_config(struct 
amdgpu_device *adev)
 
for (i = 0; i <= 14; i++) {
tmp = RREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i);
-   tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 0);
+   tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
num_level);
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
@@ -302,9 +302,6 @@ static void gfxhub_v1_0_setup_vmid_config(struct 
amdgpu_device *adev)
WREG32_SOC15_OFFSET(GC, 0, 
mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
i * hub->ctx_addr_distance,
upper_32_bits(adev->vm_manager.max_pfn - 
1));
-   tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
-   WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL,
-   i * hub->ctx_distance, tmp);
}
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c 
b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c
index 108674f6eef0..4dabf910334b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c
@@ -330,7 +330,7 @@ static void gfxhub_v1_2_xcc_setup_vmid_config(struct 
amdgpu_device *adev,
hub = &adev->vmhub[AMDGPU_GFXHUB(j)];
for (i = 0; i <= 14; i++) {
tmp = RREG32_SOC15_OFFSET(GC, GET_INST(GC, j), 
regVM_CONTEXT1_CNTL, i);
-   tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 
ENABLE_CONTEXT, 0);
+   tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 
ENABLE_CONTEXT, 1);
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 
PAGE_TABLE_DEPTH,
num_level);
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
@@ -377,9 +377,6 @@ static void gfxhub_v1_2_xcc_setup_vmid_config(struct 
amdgpu_device *adev,

regVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
i * hub->ctx_addr_distance,

upper_32_bits(adev->vm_manager.max_pfn - 1));
-   tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 
ENABLE_CONTEXT, 1);
-   WREG32_SOC15_OFFSET(GC, GET_INST(GC, j), 
regVM_CONTEXT1_CNTL,
-   i * hub->ctx_distance, tmp);
}
}
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
index 502cb6e1fe84..f173a61c6c15 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
@@ -288,7 +288,7 @@ static void gfxhub_v2_0_setup_vmid_config(struct 
amdgpu_device *adev)
 
for (i = 0; i <= 14; i++) {
tmp = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i);
-   tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 0);
+   tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
adev->vm_manager.num_level);
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
@@ -324,9 +324,6 @@ static void gfxhub_v2_0_setup_vmid_config(struct 
amdgpu_device *adev)
WREG32_SOC15_OFFSET(GC, 0, 
mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
   

Re: [PATCH v2 1/2] drm/amd: Disallow s0ix without BIOS support again

[Alex Deucher]

On Wed, May 31, 2023 at 10:20 AM Mario Limonciello
 wrote:
>
> On 5/31/23 08:26, Alex Deucher wrote:
> > On Tue, May 30, 2023 at 6:34 PM Mario Limonciello
> >  wrote:
> >>
> >> commit cf488dcd0ab7 ("drm/amd: Allow s0ix without BIOS support") showed
> >> improvements to power consumption over suspend when s0ix wasn't enabled in
> >> BIOS and the system didn't support S3.
> >>
> >> This patch however was misguided because the reason the system didn't
> >> support S3 was because SMT was disabled in OEM BIOS setup.
> >> This prevented the BIOS from allowing S3.
> >>
> >> Also allowing GPUs to use the s2idle path actually causes problems if
> >> they're invoked on systems that may not support s2idle in the platform
> >> firmware. `systemd` has a tendency to try to use `s2idle` if `deep` fails
> >> for any reason, which could lead to unexpected flows.
> >>
> >> The original commit also fixed a problem during resume from suspend to idle
> >> without hardware support, but this is no longer necessary with commit
> >> ca4751866397 ("drm/amd: Don't allow s0ix on APUs older than Raven")
> >>
> >> Revert commit cf488dcd0ab7 ("drm/amd: Allow s0ix without BIOS support")
> >> to make it match the expected behavior again.
> >>
> >> Cc: Rafael Ávila de Espíndola 
> >> Link: 
> >> https://github.com/torvalds/linux/blob/v6.1/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c#L1060
> >> Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/2599
> >> Signed-off-by: Mario Limonciello 
> >
> > Patch 1 is:
> > Reviewed-by: Alex Deucher 
>
> Thx.
>
> > Patch 2 seems a bit much, but I could be convinced if you think it
> > will actually help more than a warn would.  Users already assume warn
> > is a kernel crash.  I'm not sure the average user makes a distinction
> > between warn and err.
>
> warn and WARN are two different things.  I think you're right about
> WARN, that does look like a crash to most people.
>
> Modern versions of both util-linux (for dmesg command) and systemd (for
> journalctl command) will apply coloring for different message levels.
>
> For both specifically there is red coloring when there is an 'err' and
> "bold" white coloring when it's 'warn'.

Ah, right.  Thanks for the reminder.  You can add my RB to patch 2 as well.

Alex

>
> >
> > Alex
> >
> >> ---
> >>   drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 8 ++--
> >>   1 file changed, 6 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c 
> >> b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
> >> index aeeec211861c..e1b01554e323 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
> >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
> >> @@ -1092,16 +1092,20 @@ bool amdgpu_acpi_is_s0ix_active(struct 
> >> amdgpu_device *adev)
> >>   * S0ix even though the system is suspending to idle, so return 
> >> false
> >>   * in that case.
> >>   */
> >> -   if (!(acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0))
> >> +   if (!(acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0)) {
> >>  dev_warn_once(adev->dev,
> >>"Power consumption will be higher as BIOS 
> >> has not been configured for suspend-to-idle.\n"
> >>"To use suspend-to-idle change the sleep 
> >> mode in BIOS setup.\n");
> >> +   return false;
> >> +   }
> >>
> >>   #if !IS_ENABLED(CONFIG_AMD_PMC)
> >>  dev_warn_once(adev->dev,
> >>"Power consumption will be higher as the kernel has 
> >> not been compiled with CONFIG_AMD_PMC.\n");
> >> -#endif /* CONFIG_AMD_PMC */
> >> +   return false;
> >> +#else
> >>  return true;
> >> +#endif /* CONFIG_AMD_PMC */
> >>   }
> >>
> >>   #endif /* CONFIG_SUSPEND */
> >> --
> >> 2.34.1
> >>
>

Re: [PATCH v2 1/2] drm/amd: Disallow s0ix without BIOS support again

[Mario Limonciello]

On 5/31/23 08:26, Alex Deucher wrote:

On Tue, May 30, 2023 at 6:34 PM Mario Limonciello
 wrote:


commit cf488dcd0ab7 ("drm/amd: Allow s0ix without BIOS support") showed
improvements to power consumption over suspend when s0ix wasn't enabled in
BIOS and the system didn't support S3.

This patch however was misguided because the reason the system didn't
support S3 was because SMT was disabled in OEM BIOS setup.
This prevented the BIOS from allowing S3.

Also allowing GPUs to use the s2idle path actually causes problems if
they're invoked on systems that may not support s2idle in the platform
firmware. `systemd` has a tendency to try to use `s2idle` if `deep` fails
for any reason, which could lead to unexpected flows.

The original commit also fixed a problem during resume from suspend to idle
without hardware support, but this is no longer necessary with commit
ca4751866397 ("drm/amd: Don't allow s0ix on APUs older than Raven")

Revert commit cf488dcd0ab7 ("drm/amd: Allow s0ix without BIOS support")
to make it match the expected behavior again.

Cc: Rafael Ávila de Espíndola 
Link: 
https://github.com/torvalds/linux/blob/v6.1/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c#L1060
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/2599
Signed-off-by: Mario Limonciello 


Patch 1 is:
Reviewed-by: Alex Deucher 


Thx.


Patch 2 seems a bit much, but I could be convinced if you think it
will actually help more than a warn would.  Users already assume warn
is a kernel crash.  I'm not sure the average user makes a distinction
between warn and err.


warn and WARN are two different things.  I think you're right about 
WARN, that does look like a crash to most people.


Modern versions of both util-linux (for dmesg command) and systemd (for 
journalctl command) will apply coloring for different message levels.


For both specifically there is red coloring when there is an 'err' and 
"bold" white coloring when it's 'warn'.




Alex


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 8 ++--
  1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
index aeeec211861c..e1b01554e323 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
@@ -1092,16 +1092,20 @@ bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device 
*adev)
  * S0ix even though the system is suspending to idle, so return false
  * in that case.
  */
-   if (!(acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0))
+   if (!(acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0)) {
 dev_warn_once(adev->dev,
   "Power consumption will be higher as BIOS has not 
been configured for suspend-to-idle.\n"
   "To use suspend-to-idle change the sleep mode in BIOS 
setup.\n");
+   return false;
+   }

  #if !IS_ENABLED(CONFIG_AMD_PMC)
 dev_warn_once(adev->dev,
   "Power consumption will be higher as the kernel has not been 
compiled with CONFIG_AMD_PMC.\n");
-#endif /* CONFIG_AMD_PMC */
+   return false;
+#else
 return true;
+#endif /* CONFIG_AMD_PMC */
  }

  #endif /* CONFIG_SUSPEND */
--
2.34.1

Re: [PATCH] drm/amd/display: Fix up kdoc formatting in display_mode_vba.c

[Aurabindo Pillai]

Reviewed-by: Aurabindo Pillai 

On 5/30/23 15:08, Srinivasan Shanmugam wrote:
> Fixes the following W=1 kernel build warning:
> 
> drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_vba.c:936: warning: 
> Cannot understand  * 
> *
> 
> Cc: Aurabindo Pillai 
> Signed-off-by: Srinivasan Shanmugam 
> ---
>  drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c | 6 ++
>  1 file changed, 2 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c 
> b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
> index 2f63ae954826..9a3ded311195 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
> +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
> @@ -933,18 +933,16 @@ static void fetch_pipe_params(struct display_mode_lib 
> *mode_lib)
>  }
>  
>  /**
> - * 
> 
>   * cache_debug_params: Cache any params that needed to be maintained from 
> the initial validation
>   * for debug purposes.
>   *
>   * The DML getters can modify some of the VBA params that we are interested 
> in (for example when
>   * calculating with dummy p-state latency), so cache any params here that we 
> want for debugging
>   *
> - * @param [in] mode_lib: mode_lib input/output of validate call
> + * @mode_lib: mode_lib input/output of validate call
>   *
> - * @return: void
> + * Return: void
>   *
> - * 
> 
>   */
>  static void cache_debug_params(struct display_mode_lib *mode_lib)
>  {

Re: [PATCH] drm/amd: SVM flag error added at svm_range flags

[Deucher, Alexander]

[Public]

Where is the userspace code which uses this new interface?  Can you add a link 
to the relevant branch to the commit message?

Alex

From: amd-gfx  on behalf of Alex Sierra 

Sent: Monday, May 29, 2023 4:09 PM
To: amd-gfx@lists.freedesktop.org ; Kuehling, 
Felix 
Cc: Sierra Guiza, Alejandro (Alex) ; Yang, Philip 

Subject: [PATCH] drm/amd: SVM flag error added at svm_range flags

If a return error is raised during validation and mapping of a
prange, this flag is set. It is a rare occurrence, but it could happen
when `amdgpu_hmm_range_get_pages_done` returns true. In such cases,
the caller should retry. However, it is important to ensure that the
prange is updated correctly during the retry.

Signed-off-by: Alex Sierra 
---
 drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 12 +++-
 include/uapi/linux/kfd_ioctl.h   |  2 ++
 2 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
index fcfde9140bce..96abae515bcf 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
@@ -756,10 +756,12 @@ svm_range_apply_attrs(struct kfd_process *p, struct 
svm_range *prange,
 break;
 case KFD_IOCTL_SVM_ATTR_SET_FLAGS:
 *update_mapping = true;
+   attrs[i].value &= ~KFD_IOCTL_SVM_FLAG_ERROR;
 prange->flags |= attrs[i].value;
 break;
 case KFD_IOCTL_SVM_ATTR_CLR_FLAGS:
 *update_mapping = true;
+   attrs[i].value &= ~KFD_IOCTL_SVM_FLAG_ERROR;
 prange->flags &= ~attrs[i].value;
 break;
 case KFD_IOCTL_SVM_ATTR_GRANULARITY:
@@ -778,6 +780,9 @@ svm_range_is_same_attrs(struct kfd_process *p, struct 
svm_range *prange,
 uint32_t i;
 int gpuidx;

+   if (prange->flags & KFD_IOCTL_SVM_FLAG_ERROR)
+   return false;
+
 for (i = 0; i < nattr; i++) {
 switch (attrs[i].type) {
 case KFD_IOCTL_SVM_ATTR_PREFERRED_LOC:
@@ -1657,8 +1662,11 @@ static int svm_range_validate_and_map(struct mm_struct 
*mm,
 unreserve_out:
 svm_range_unreserve_bos(&ctx);

-   if (!r)
+   prange->flags |= KFD_IOCTL_SVM_FLAG_ERROR;
+   if (!r) {
+   prange->flags &= ~KFD_IOCTL_SVM_FLAG_ERROR;
 prange->validate_timestamp = ktime_get_boottime();
+   }

 return r;
 }
@@ -3674,9 +3682,11 @@ svm_range_get_attr(struct kfd_process *p, struct 
mm_struct *mm,
 break;
 case KFD_IOCTL_SVM_ATTR_SET_FLAGS:
 attrs[i].value = flags_and;
+   attrs[i].value &= ~KFD_IOCTL_SVM_FLAG_ERROR;
 break;
 case KFD_IOCTL_SVM_ATTR_CLR_FLAGS:
 attrs[i].value = ~flags_or;
+   attrs[i].value &= ~KFD_IOCTL_SVM_FLAG_ERROR;
 break;
 case KFD_IOCTL_SVM_ATTR_GRANULARITY:
 attrs[i].value = (uint32_t)granularity;
diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h
index 7e19a2d1e907..2b6f68bd06da 100644
--- a/include/uapi/linux/kfd_ioctl.h
+++ b/include/uapi/linux/kfd_ioctl.h
@@ -1125,6 +1125,8 @@ struct kfd_ioctl_cross_memory_copy_deprecated_args {
 #define KFD_IOCTL_SVM_FLAG_GPU_READ_MOSTLY 0x0020
 /* Keep GPU memory mapping always valid as if XNACK is disable */
 #define KFD_IOCTL_SVM_FLAG_GPU_ALWAYS_MAPPED   0x0040
+/* Set during svm validation and map error */
+#define KFD_IOCTL_SVM_FLAG_ERROR   0x8000

 /**
  * kfd_ioctl_svm_op - SVM ioctl operations
--
2.32.0

RE: [PATCH] drm/amd/pm: add unique serial number support for smu_v13_0_6

[Zhang, Hawking]

[AMD Official Use Only - General]

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: Kamal, Asad 
Sent: Wednesday, May 31, 2023 21:16
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Lazar, Lijo ; 
Ma, Le ; Zhang, Morris ; Wang, Yang(Kevin) 

Subject: [PATCH] drm/amd/pm: add unique serial number support for smu_v13_0_6

From: Yang Wang 

add unique serial number support for smu_v13_0_6.
(use aid0 serial number by default)

Signed-off-by: Yang Wang 
Signed-off-by: Asad Kamal 
Reviewed-by: Lijo Lazar 
---
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c  | 20 ---
 1 file changed, 8 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
index b9f32e0364db..75255e0baf91 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
@@ -192,6 +192,7 @@ struct PPTable_t {
uint32_t LclkFrequencyTable[4];
uint32_t MaxLclkDpmRange;
uint32_t MinLclkDpmRange;
+   uint64_t PublicSerialNumber_AID;
bool Init;
 };

@@ -352,6 +353,9 @@ static int smu_v13_0_6_setup_driver_pptable(struct 
smu_context *smu)
SMUQ10_TO_UINT(metrics->LclkFrequencyTable[i]);
}

+   /* use AID0 serial number by default */
+   pptable->PublicSerialNumber_AID = 
metrics->PublicSerialNumber_AID[0];
+
pptable->Init = true;
}

@@ -1856,19 +1860,11 @@ static void smu_v13_0_6_i2c_control_fini(struct 
smu_context *smu)  static void smu_v13_0_6_get_unique_id(struct smu_context 
*smu)  {
struct amdgpu_device *adev = smu->adev;
-   //SmuMetrics_t *metrics = smu->smu_table.metrics_table;
-   uint32_t upper32 = 0, lower32 = 0;
-   int ret;
-
-   ret = smu_cmn_get_metrics_table(smu, NULL, false);
-   if (ret)
-   goto out;
-
-   //upper32 = metrics->PublicSerialNumUpper32;
-   //lower32 = metrics->PublicSerialNumLower32;
+   struct smu_table_context *smu_table = &smu->smu_table;
+   struct PPTable_t *pptable =
+   (struct PPTable_t *)smu_table->driver_pptable;

-out:
-   adev->unique_id = ((uint64_t)upper32 << 32) | lower32;
+   adev->unique_id = pptable->PublicSerialNumber_AID;
if (adev->serial[0] == '\0')
sprintf(adev->serial, "%016llx", adev->unique_id);  }
--
2.34.1

Re: [PATCH] drm/amdgpu/gfx9: switch to golden tsc registers for raven/raven2

[Alex Deucher]

On Mon, May 29, 2023 at 5:45 AM Michel Dänzer  wrote:
>
> On 4/12/23 03:23, Zhang, Jesse(Jie) wrote:
> >
> >   Due to raven/raven2 maybe enable  sclk slow down,
> > they cannot get clock count by the RLC at the auto level of dpm 
> > performance.
> > So switch to golden tsc register.
>
> At least on this ThinkPad E595 with Picasso, the issue with this change (and 
> the corresponding fbc24293ca16 "drm/amdgpu: change the reference clock for 
> raven/raven2" & 9d2d1827af29 "drm/amdgpu: Differentiate between Raven2 and 
> Raven/Picasso according to revision id") is that the GPU timestamps reported 
> via the AMDGPU_INFO ioctl are no longer consistent with those reported via 
> asynchronous GPU queries (e.g. via glQuery with GL_TIMESTAMP). The latter are 
> still affected by clock changes, and even when the clock doesn't stop 
> altogether, they still tick at 25 MHz, so the two kinds of GPU timestamps 
> keep diverging further.
>

fbc24293ca16 "drm/amdgpu: change the reference clock for raven/raven2"
would also affect that.  Were you seeing the same results with that
patch as well?

Alex


> This makes it impossible to determine the wall clock time at which a certain 
> GPU job finished. GNOME's mutter uses this for adaptive frame scheduling.
>
> You can see the issue with the piglit test arb_timer_query-timestamp-get or 
> with the Vulkan CTS tests dEQP-VK.pipeline.monolithic.timestamp.calibrated.*. 
> (Note that some of these tests could already fail before with GFXOFF enabled, 
> the symptoms are slightly different though)
>
>
> An ideal long-term solution for this might be to modify the GPU microcode to 
> use the golden registers for asynchronous timestamp queries as well.
>
> In the meantime though, these changes need to be reverted for 6.4, at least 
> for Picasso.
>
>
> --
> Earthling Michel Dänzer|  https://redhat.com
> Libre software enthusiast  | Mesa and Xwayland developer
>

Re: [PATCH v2] drm/ttm: Remove redundant code in ttm_tt_init_fields

[Ma, Jun]

On 5/31/2023 4:45 PM, Christian König wrote:
> Am 31.05.23 um 08:20 schrieb Chen, Guchun:
>> [Public]
>>
>>> -Original Message-
>>> From: amd-gfx  On Behalf Of Ma
>>> Jun
>>> Sent: Wednesday, May 31, 2023 1:31 PM
>>> To: amd-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org; Koenig,
>>> Christian 
>>> Cc: Ma, Jun 
>>> Subject: [PATCH v2] drm/ttm: Remove redundant code in ttm_tt_init_fields
>>>
>>> Remove redundant assignment code for ttm->caching as it's overwritten
>>>
>>> just a few lines later.
>> Please drop the blank line in above message. With it fixed, the patch is: 
>> Reviewed-by: Guchun Chen 
> 
> Seconded, I'm going to pick that patch up and submit it to drm-misc-next 
> with the commit message fixed.
> 

Thanks for help.

Regards,
Ma Jun
> Regards,
> Christian.
> 
>>
>> Regards,
>> Guchun
>>
>>> v2:
>>>   - Update the commit message.
>>>
>>> Signed-off-by: Ma Jun 
>>> ---
>>>   drivers/gpu/drm/ttm/ttm_tt.c | 1 -
>>>   1 file changed, 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c
>>> index 02b812dacc5d..45a44544b656 100644
>>> --- a/drivers/gpu/drm/ttm/ttm_tt.c
>>> +++ b/drivers/gpu/drm/ttm/ttm_tt.c
>>> @@ -143,7 +143,6 @@ static void ttm_tt_init_fields(struct ttm_tt *ttm,
>>>   unsigned long extra_pages)
>>>   {
>>>ttm->num_pages = (PAGE_ALIGN(bo->base.size) >> PAGE_SHIFT) +
>>> extra_pages;
>>> - ttm->caching = ttm_cached;
>>>ttm->page_flags = page_flags;
>>>ttm->dma_address = NULL;
>>>ttm->swap_storage = NULL;
>>> --
>>> 2.34.1
> 

[PATCH AUTOSEL 5.4 17/17] drm:amd:amdgpu: Fix missing buffer object unlock in failure path

[Sasha Levin]

From: Sukrut Bellary 

[ Upstream commit 60ecaaf54886b0642d5c4744f7fbf1ff0d6b3e42 ]

smatch warning -
1) drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3615 gfx_v9_0_kiq_resume()
warn: inconsistent returns 'ring->mqd_obj->tbo.base.resv'.

2) drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c:6901 gfx_v10_0_kiq_resume()
warn: inconsistent returns 'ring->mqd_obj->tbo.base.resv'.

Signed-off-by: Sukrut Bellary 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 4 +++-
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c  | 4 +++-
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 1d8739a4fbcad..a84deb3c79a30 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -3527,8 +3527,10 @@ static int gfx_v10_0_kiq_resume(struct amdgpu_device 
*adev)
return r;
 
r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
-   if (unlikely(r != 0))
+   if (unlikely(r != 0)) {
+   amdgpu_bo_unreserve(ring->mqd_obj);
return r;
+   }
 
gfx_v10_0_kiq_init_queue(ring);
amdgpu_bo_kunmap(ring->mqd_obj);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 762a407a4997a..4eba6b2d9cdec 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3748,8 +3748,10 @@ static int gfx_v9_0_kiq_resume(struct amdgpu_device 
*adev)
return r;
 
r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
-   if (unlikely(r != 0))
+   if (unlikely(r != 0)) {
+   amdgpu_bo_unreserve(ring->mqd_obj);
return r;
+   }
 
gfx_v9_0_kiq_init_queue(ring);
amdgpu_bo_kunmap(ring->mqd_obj);
-- 
2.39.2

[PATCH AUTOSEL 5.10 21/21] drm:amd:amdgpu: Fix missing buffer object unlock in failure path

[Sasha Levin]

From: Sukrut Bellary 

[ Upstream commit 60ecaaf54886b0642d5c4744f7fbf1ff0d6b3e42 ]

smatch warning -
1) drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3615 gfx_v9_0_kiq_resume()
warn: inconsistent returns 'ring->mqd_obj->tbo.base.resv'.

2) drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c:6901 gfx_v10_0_kiq_resume()
warn: inconsistent returns 'ring->mqd_obj->tbo.base.resv'.

Signed-off-by: Sukrut Bellary 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 4 +++-
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c  | 4 +++-
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 0e3ff5c3766ed..72410a2d4e6bf 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -6702,8 +6702,10 @@ static int gfx_v10_0_kiq_resume(struct amdgpu_device 
*adev)
return r;
 
r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
-   if (unlikely(r != 0))
+   if (unlikely(r != 0)) {
+   amdgpu_bo_unreserve(ring->mqd_obj);
return r;
+   }
 
gfx_v10_0_kiq_init_queue(ring);
amdgpu_bo_kunmap(ring->mqd_obj);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 629671f66b319..acef2227d992b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3800,8 +3800,10 @@ static int gfx_v9_0_kiq_resume(struct amdgpu_device 
*adev)
return r;
 
r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
-   if (unlikely(r != 0))
+   if (unlikely(r != 0)) {
+   amdgpu_bo_unreserve(ring->mqd_obj);
return r;
+   }
 
gfx_v9_0_kiq_init_queue(ring);
amdgpu_bo_kunmap(ring->mqd_obj);
-- 
2.39.2

[PATCH AUTOSEL 5.15 23/24] drm:amd:amdgpu: Fix missing buffer object unlock in failure path

[Sasha Levin]

From: Sukrut Bellary 

[ Upstream commit 60ecaaf54886b0642d5c4744f7fbf1ff0d6b3e42 ]

smatch warning -
1) drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3615 gfx_v9_0_kiq_resume()
warn: inconsistent returns 'ring->mqd_obj->tbo.base.resv'.

2) drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c:6901 gfx_v10_0_kiq_resume()
warn: inconsistent returns 'ring->mqd_obj->tbo.base.resv'.

Signed-off-by: Sukrut Bellary 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 4 +++-
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c  | 4 +++-
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 970d59a21005a..daff4da1a8bb9 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -7197,8 +7197,10 @@ static int gfx_v10_0_kiq_resume(struct amdgpu_device 
*adev)
return r;
 
r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
-   if (unlikely(r != 0))
+   if (unlikely(r != 0)) {
+   amdgpu_bo_unreserve(ring->mqd_obj);
return r;
+   }
 
gfx_v10_0_kiq_init_queue(ring);
amdgpu_bo_kunmap(ring->mqd_obj);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 5f325ded7f752..de1fab165041f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3871,8 +3871,10 @@ static int gfx_v9_0_kiq_resume(struct amdgpu_device 
*adev)
return r;
 
r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
-   if (unlikely(r != 0))
+   if (unlikely(r != 0)) {
+   amdgpu_bo_unreserve(ring->mqd_obj);
return r;
+   }
 
gfx_v9_0_kiq_init_queue(ring);
amdgpu_bo_kunmap(ring->mqd_obj);
-- 
2.39.2

[PATCH AUTOSEL 6.1 31/33] drm:amd:amdgpu: Fix missing buffer object unlock in failure path

[Sasha Levin]

From: Sukrut Bellary 

[ Upstream commit 60ecaaf54886b0642d5c4744f7fbf1ff0d6b3e42 ]

smatch warning -
1) drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3615 gfx_v9_0_kiq_resume()
warn: inconsistent returns 'ring->mqd_obj->tbo.base.resv'.

2) drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c:6901 gfx_v10_0_kiq_resume()
warn: inconsistent returns 'ring->mqd_obj->tbo.base.resv'.

Signed-off-by: Sukrut Bellary 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 4 +++-
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c  | 4 +++-
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 2127aab74a68f..84a36b50ddd87 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -6969,8 +6969,10 @@ static int gfx_v10_0_kiq_resume(struct amdgpu_device 
*adev)
return r;
 
r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
-   if (unlikely(r != 0))
+   if (unlikely(r != 0)) {
+   amdgpu_bo_unreserve(ring->mqd_obj);
return r;
+   }
 
gfx_v10_0_kiq_init_queue(ring);
amdgpu_bo_kunmap(ring->mqd_obj);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 1f3fdf6cb903e..fe371022e5104 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3650,8 +3650,10 @@ static int gfx_v9_0_kiq_resume(struct amdgpu_device 
*adev)
return r;
 
r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
-   if (unlikely(r != 0))
+   if (unlikely(r != 0)) {
+   amdgpu_bo_unreserve(ring->mqd_obj);
return r;
+   }
 
gfx_v9_0_kiq_init_queue(ring);
amdgpu_bo_kunmap(ring->mqd_obj);
-- 
2.39.2

[PATCH AUTOSEL 6.3 35/37] drm:amd:amdgpu: Fix missing buffer object unlock in failure path

[Sasha Levin]

From: Sukrut Bellary 

[ Upstream commit 60ecaaf54886b0642d5c4744f7fbf1ff0d6b3e42 ]

smatch warning -
1) drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:3615 gfx_v9_0_kiq_resume()
warn: inconsistent returns 'ring->mqd_obj->tbo.base.resv'.

2) drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c:6901 gfx_v10_0_kiq_resume()
warn: inconsistent returns 'ring->mqd_obj->tbo.base.resv'.

Signed-off-by: Sukrut Bellary 
Signed-off-by: Alex Deucher 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 4 +++-
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c  | 4 +++-
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index b1428068fef7f..8144d6693541e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -6890,8 +6890,10 @@ static int gfx_v10_0_kiq_resume(struct amdgpu_device 
*adev)
return r;
 
r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
-   if (unlikely(r != 0))
+   if (unlikely(r != 0)) {
+   amdgpu_bo_unreserve(ring->mqd_obj);
return r;
+   }
 
gfx_v10_0_kiq_init_queue(ring);
amdgpu_bo_kunmap(ring->mqd_obj);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index c54d05bdc2d8c..7b1a359ab0849 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3604,8 +3604,10 @@ static int gfx_v9_0_kiq_resume(struct amdgpu_device 
*adev)
return r;
 
r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
-   if (unlikely(r != 0))
+   if (unlikely(r != 0)) {
+   amdgpu_bo_unreserve(ring->mqd_obj);
return r;
+   }
 
gfx_v9_0_kiq_init_queue(ring);
amdgpu_bo_kunmap(ring->mqd_obj);
-- 
2.39.2

Re: [PATCH] drm/amdgpu: Rearrange WREG32 operations in gfxhub_v2_1.c

[Christian König]

Am 20.05.23 um 13:59 schrieb ghostfly233:

In gfxhub_v2_1_setup_vmid_config(), the GCVM_CONTEXT1_CNTL reg is
written before related GCVM_CONTEXT1_PAGE_TABLE_START_ADDR and
GCVM_CONTEXT1_PAGE_TABLE_END_ADDR regs are written, which may
cause undefined behavior.


In which hw documentation did you found that?



This patch rearranges WREG32 operations in gfxhub_v2_1_setup_vmid_config(),
so that it can ensure the addresses are initialized before CNTL is enabled
and reduce the risk of encountering undefined behavior.


I have absolutely no idea how you came to this conclusion, but as far as 
I know this is just bluntly incorrect.


The control register must be written before the other parameters are set 
or otherwise the hw wouldn't know what to do with those values and might 
even block writes to the registers or hang.


Regards,
Christian.



Signed-off-by: Zibin Liu 
---
  drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c 
b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
index 4aacbbec31e2..6d094e7315eb 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
@@ -321,8 +321,6 @@ static void gfxhub_v2_1_setup_vmid_config(struct 
amdgpu_device *adev)
tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
!adev->gmc.noretry);
-   WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL,
-   i * hub->ctx_distance, tmp);
WREG32_SOC15_OFFSET(GC, 0, 
mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
i * hub->ctx_addr_distance, 0);
WREG32_SOC15_OFFSET(GC, 0, 
mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
@@ -333,6 +331,8 @@ static void gfxhub_v2_1_setup_vmid_config(struct 
amdgpu_device *adev)
WREG32_SOC15_OFFSET(GC, 0, 
mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
i * hub->ctx_addr_distance,
upper_32_bits(adev->vm_manager.max_pfn - 
1));
+   WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL,
+   i * hub->ctx_distance, tmp);
}
  
  	hub->vm_cntx_cntl = tmp;

Re: [PATCH v2 1/2] drm/amd: Disallow s0ix without BIOS support again

[Alex Deucher]

On Tue, May 30, 2023 at 6:34 PM Mario Limonciello
 wrote:
>
> commit cf488dcd0ab7 ("drm/amd: Allow s0ix without BIOS support") showed
> improvements to power consumption over suspend when s0ix wasn't enabled in
> BIOS and the system didn't support S3.
>
> This patch however was misguided because the reason the system didn't
> support S3 was because SMT was disabled in OEM BIOS setup.
> This prevented the BIOS from allowing S3.
>
> Also allowing GPUs to use the s2idle path actually causes problems if
> they're invoked on systems that may not support s2idle in the platform
> firmware. `systemd` has a tendency to try to use `s2idle` if `deep` fails
> for any reason, which could lead to unexpected flows.
>
> The original commit also fixed a problem during resume from suspend to idle
> without hardware support, but this is no longer necessary with commit
> ca4751866397 ("drm/amd: Don't allow s0ix on APUs older than Raven")
>
> Revert commit cf488dcd0ab7 ("drm/amd: Allow s0ix without BIOS support")
> to make it match the expected behavior again.
>
> Cc: Rafael Ávila de Espíndola 
> Link: 
> https://github.com/torvalds/linux/blob/v6.1/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c#L1060
> Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/2599
> Signed-off-by: Mario Limonciello 

Patch 1 is:
Reviewed-by: Alex Deucher 
Patch 2 seems a bit much, but I could be convinced if you think it
will actually help more than a warn would.  Users already assume warn
is a kernel crash.  I'm not sure the average user makes a distinction
between warn and err.

Alex

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 8 ++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
> index aeeec211861c..e1b01554e323 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
> @@ -1092,16 +1092,20 @@ bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device 
> *adev)
>  * S0ix even though the system is suspending to idle, so return false
>  * in that case.
>  */
> -   if (!(acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0))
> +   if (!(acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0)) {
> dev_warn_once(adev->dev,
>   "Power consumption will be higher as BIOS has 
> not been configured for suspend-to-idle.\n"
>   "To use suspend-to-idle change the sleep mode 
> in BIOS setup.\n");
> +   return false;
> +   }
>
>  #if !IS_ENABLED(CONFIG_AMD_PMC)
> dev_warn_once(adev->dev,
>   "Power consumption will be higher as the kernel has not 
> been compiled with CONFIG_AMD_PMC.\n");
> -#endif /* CONFIG_AMD_PMC */
> +   return false;
> +#else
> return true;
> +#endif /* CONFIG_AMD_PMC */
>  }
>
>  #endif /* CONFIG_SUSPEND */
> --
> 2.34.1
>

[PATCH] drm/amd/pm: add unique serial number support for smu_v13_0_6

[Asad Kamal]

From: Yang Wang 

add unique serial number support for smu_v13_0_6.
(use aid0 serial number by default)

Signed-off-by: Yang Wang 
Signed-off-by: Asad Kamal 
Reviewed-by: Lijo Lazar 
---
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c  | 20 ---
 1 file changed, 8 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
index b9f32e0364db..75255e0baf91 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
@@ -192,6 +192,7 @@ struct PPTable_t {
uint32_t LclkFrequencyTable[4];
uint32_t MaxLclkDpmRange;
uint32_t MinLclkDpmRange;
+   uint64_t PublicSerialNumber_AID;
bool Init;
 };
 
@@ -352,6 +353,9 @@ static int smu_v13_0_6_setup_driver_pptable(struct 
smu_context *smu)
SMUQ10_TO_UINT(metrics->LclkFrequencyTable[i]);
}
 
+   /* use AID0 serial number by default */
+   pptable->PublicSerialNumber_AID = 
metrics->PublicSerialNumber_AID[0];
+
pptable->Init = true;
}
 
@@ -1856,19 +1860,11 @@ static void smu_v13_0_6_i2c_control_fini(struct 
smu_context *smu)
 static void smu_v13_0_6_get_unique_id(struct smu_context *smu)
 {
struct amdgpu_device *adev = smu->adev;
-   //SmuMetrics_t *metrics = smu->smu_table.metrics_table;
-   uint32_t upper32 = 0, lower32 = 0;
-   int ret;
-
-   ret = smu_cmn_get_metrics_table(smu, NULL, false);
-   if (ret)
-   goto out;
-
-   //upper32 = metrics->PublicSerialNumUpper32;
-   //lower32 = metrics->PublicSerialNumLower32;
+   struct smu_table_context *smu_table = &smu->smu_table;
+   struct PPTable_t *pptable =
+   (struct PPTable_t *)smu_table->driver_pptable;
 
-out:
-   adev->unique_id = ((uint64_t)upper32 << 32) | lower32;
+   adev->unique_id = pptable->PublicSerialNumber_AID;
if (adev->serial[0] == '\0')
sprintf(adev->serial, "%016llx", adev->unique_id);
 }
-- 
2.34.1

[PATCH 3/3] drm/amd/pm: Add throttle status in power context

[Asad Kamal]

From: Lijo Lazar 

Keep throttle status indicator in SMUv13 power context

Signed-off-by: Lijo Lazar 
Reviewed-by: Hawking Zhang 
---
 drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h 
b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
index 7c736f1817fd..5e8063ee3dad 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
@@ -119,6 +119,7 @@ struct smu_13_0_power_context {
uint32_tpower_source;
uint8_t in_power_limit_boost_mode;
enum smu_13_0_power_state power_state;
+   atomic_tthrottle_status;
 };
 
 #if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3)
-- 
2.34.1

[PATCH 2/3] drm/amd/pm: Fix SMUv13.0.6 throttle status report

[Asad Kamal]

From: Lijo Lazar 

Instead of accumulated counters, PMFW will pass the throttle reason
along with throttle interrupt. Use that context information to report the
exact reason for throttling.

Signed-off-by: Lijo Lazar 
Reviewed-by: Hawking Zhang 
---
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c  | 93 +--
 1 file changed, 45 insertions(+), 48 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
index 41b49cc827cd..b9f32e0364db 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
@@ -172,17 +172,12 @@ static const struct cmn2asic_mapping 
smu_v13_0_6_table_map[SMU_TABLE_COUNT] = {
TAB_MAP(I2C_COMMANDS),
 };
 
-#define THROTTLER_PROCHOT_GFX_BIT  0
-#define THROTTLER_PPT_BIT 1
-#define THROTTLER_TEMP_SOC_BIT 2
-#define THROTTLER_TEMP_VR_GFX_BIT 3
-
 static const uint8_t smu_v13_0_6_throttler_map[] = {
[THROTTLER_PPT_BIT] = (SMU_THROTTLER_PPT0_BIT),
-   [THROTTLER_TEMP_SOC_BIT]= (SMU_THROTTLER_TEMP_GPU_BIT),
-   [THROTTLER_TEMP_HBM_BIT]= (SMU_THROTTLER_TEMP_MEM_BIT),
-   [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
-   [THROTTLER_PROCHOT_GFX_BIT] = (SMU_THROTTLER_PROCHOT_GFX_BIT),
+   [THROTTLER_THERMAL_SOCKET_BIT]  = (SMU_THROTTLER_TEMP_GPU_BIT),
+   [THROTTLER_THERMAL_HBM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT),
+   [THROTTLER_THERMAL_VR_BIT]  = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
+   [THROTTLER_PROCHOT_BIT] = (SMU_THROTTLER_PROCHOT_GFX_BIT),
 };
 
 struct PPTable_t {
@@ -640,16 +635,14 @@ static int smu_v13_0_6_freqs_in_same_level(int32_t 
frequency1,
return (abs(frequency1 - frequency2) <= EPSILON);
 }
 
-static uint32_t smu_v13_0_6_get_throttler_status(struct smu_context *smu,
-MetricsTable_t *metrics)
+static uint32_t smu_v13_0_6_get_throttler_status(struct smu_context *smu)
 {
+   struct smu_power_context *smu_power = &smu->smu_power;
+   struct smu_13_0_power_context *power_context = smu_power->power_context;
uint32_t  throttler_status = 0;
 
-   throttler_status |= metrics->ProchotResidencyAcc > 0 ? 1U << 
THROTTLER_PROCHOT_GFX_BIT : 0;
-   throttler_status |= metrics->PptResidencyAcc > 0 ? 1U << 
THROTTLER_PPT_BIT : 0;
-   throttler_status |= metrics->SocketThmResidencyAcc > 0 ?  1U << 
THROTTLER_TEMP_SOC_BIT : 0;
-   throttler_status |= metrics->VrThmResidencyAcc > 0 ? 1U << 
THROTTLER_TEMP_VR_GFX_BIT : 0;
-   throttler_status |= metrics->HbmThmResidencyAcc > 0 ? 1U << 
THROTTLER_TEMP_HBM_BIT : 0;
+   throttler_status = atomic_read(&power_context->throttle_status);
+   dev_dbg(smu->adev->dev, "SMU Throttler status: %u", throttler_status);
 
return throttler_status;
 }
@@ -719,9 +712,6 @@ static int smu_v13_0_6_get_smu_metrics_data(struct 
smu_context *smu,
case METRICS_TEMPERATURE_VRSOC:
*value = SMUQ10_TO_UINT(metrics->MaxVrTemperature);
break;
-   case METRICS_THROTTLER_STATUS:
-   *value = smu_v13_0_6_get_throttler_status(smu, metrics);
-   break;
default:
*value = UINT_MAX;
break;
@@ -1288,13 +1278,11 @@ static int smu_v13_0_6_irq_process(struct amdgpu_device 
*adev,
   struct amdgpu_iv_entry *entry)
 {
struct smu_context *smu = adev->powerplay.pp_handle;
+   struct smu_power_context *smu_power = &smu->smu_power;
+   struct smu_13_0_power_context *power_context = smu_power->power_context;
uint32_t client_id = entry->client_id;
-   uint32_t src_id = entry->src_id;
-   /*
-* ctxid is used to distinguish different
-* events for SMCToHost interrupt
-*/
uint32_t ctxid = entry->src_data[0];
+   uint32_t src_id = entry->src_id;
uint32_t data;
 
if (client_id == SOC15_IH_CLIENTID_MP1) {
@@ -1303,7 +1291,10 @@ static int smu_v13_0_6_irq_process(struct amdgpu_device 
*adev,
data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, 
INT_ACK, 1);
WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, data);
-
+   /*
+* ctxid is used to distinguish different events for 
SMCToHost
+* interrupt.
+*/
switch (ctxid) {
case IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING:
/*
@@ -1314,8 +1305,17 @@ static int smu_v13_0_6_irq_process(struct amdgpu_device 
*adev,
if 
(!atomic_read(&adev->throttling_logging_enabled))
return 0;
 
-   if (__rat

[PATCH 1/3] drm/amd/pm: Update SMUv13.0.6 PMFW headers

[Asad Kamal]

From: Lijo Lazar 

Update PMFW interface headers to for new metrics table format and
throttling information.

Signed-off-by: Lijo Lazar 
Reviewed-by: Hawking Zhang 
---
 .../inc/pmfw_if/smu13_driver_if_v13_0_6.h | 31 ++-
 .../pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h   | 13 +---
 2 files changed, 33 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_6.h 
b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_6.h
index de84fff39799..ca4a5e99ccd1 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_6.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_6.h
@@ -26,7 +26,7 @@
 // *** IMPORTANT ***
 // PMFW TEAM: Always increment the interface version if
 // anything is changed in this file
-#define SMU13_0_6_DRIVER_IF_VERSION 0x08042023
+#define SMU13_0_6_DRIVER_IF_VERSION 0x08042024
 
 //I2C Interface
 #define NUM_I2C_CONTROLLERS8
@@ -125,11 +125,28 @@ typedef struct {
 #define IH_INTERRUPT_ID_TO_DRIVER   0xFE
 #define IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING  0x7
 
-//thermal over-temp mask defines
-#define THROTTLER_TEMP_CCD_BIT 5
-#define THROTTLER_TEMP_XCD_BIT 6
-#define THROTTLER_TEMP_HBM_BIT 7
-#define THROTTLER_TEMP_AID_BIT 8
-#define THROTTLER_VRHOT_BIT9
+//thermal over-temp mask defines for IH interrupt to host
+#define THROTTLER_PROCHOT_BIT   0
+#define THROTTLER_PPT_BIT   1
+#define THROTTLER_THERMAL_SOCKET_BIT2//AID, XCD, CCD throttling
+#define THROTTLER_THERMAL_VR_BIT3//VRHOT
+#define THROTTLER_THERMAL_HBM_BIT   4
+
+// These defines are used with the following messages:
+// SMC_MSG_TransferTableDram2Smu
+// SMC_MSG_TransferTableSmu2Dram
+// #define TABLE_PPTABLE 0
+// #define TABLE_AVFS_PSM_DEBUG  1
+// #define TABLE_AVFS_FUSE_OVERRIDE  2
+// #define TABLE_PMSTATUSLOG 3
+// #define TABLE_SMU_METRICS 4
+// #define TABLE_DRIVER_SMU_CONFIG   5
+// #define TABLE_I2C_COMMANDS6
+// #define TABLE_COUNT   7
+
+// // Table transfer status
+// #define TABLE_TRANSFER_OK 0x0
+// #define TABLE_TRANSFER_FAILED 0xFF
+// #define TABLE_TRANSFER_PENDING0xAB
 
 #endif
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h 
b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h
index 3fe403615d86..252aef190c5c 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h
@@ -123,9 +123,9 @@ typedef enum {
   VOLTAGE_GUARDBAND_COUNT
 } GFX_GUARDBAND_e;
 
-#define SMU_METRICS_TABLE_VERSION 0x3
+#define SMU_METRICS_TABLE_VERSION 0x5
 
-typedef struct {
+typedef struct __attribute__((packed, aligned(4))) {
   uint32_t AccumulationCounter;
 
   //TEMPERATURE
@@ -202,11 +202,16 @@ typedef struct {
 
   // New Items at end to maintain driver compatibility
   uint32_t GfxclkFrequency[8];
+
+  //PSNs
+  uint64_t PublicSerialNumber_AID[4];
+  uint64_t PublicSerialNumber_XCD[8];
+  uint64_t PublicSerialNumber_CCD[12];
 } MetricsTable_t;
 
-#define SMU_VF_METRICS_TABLE_VERSION 0x1
+#define SMU_VF_METRICS_TABLE_VERSION 0x3
 
-typedef struct {
+typedef struct __attribute__((packed, aligned(4))) {
   uint32_t AccumulationCounter;
   uint32_t InstGfxclk_TargFreq;
   uint64_t AccGfxclk_TargFreq;
-- 
2.34.1

Re: [PATCH v2] drm/amd/display: Fix up kdoc formatting in dcn32_resource_helpers.c

[Deucher, Alexander]

[Public]

Reviewed-by: Alex Deucher 

From: amd-gfx  on behalf of Srinivasan 
Shanmugam 
Sent: Wednesday, May 31, 2023 5:22 AM
To: Pillai, Aurabindo ; Mahfooz, Hamza 
; Siqueira, Rodrigo ; 
Wentland, Harry 
Cc: SHANMUGAM, SRINIVASAN ; 
amd-gfx@lists.freedesktop.org 
Subject: [PATCH v2] drm/amd/display: Fix up kdoc formatting in 
dcn32_resource_helpers.c

Fixes the following W=1 kernel build warning:

drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_resource_helpers.c:97: 
warning: Cannot understand  * 
**
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_resource_helpers.c:264: 
warning: Cannot understand  * 
*
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_resource_helpers.c:435: 
warning: Cannot understand  * 
*
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_resource_helpers.c:475: 
warning: Cannot understand  * 
*

drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_resource_helpers.c:599:
warning: Function parameter or member 'dc' not described in
'dcn32_can_support_mclk_switch_using_fw_based_vblank_stretch'
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_resource_helpers.c:599:
warning: Function parameter or member 'context' not described in
'dcn32_can_support_mclk_switch_using_fw_based_vblank_stretch'

drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_resource_helpers.c:587:
warning: Function parameter or member 'dc' not described in
'dcn32_can_support_mclk_switch_using_fw_based_vblank_stretch'
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_resource_helpers.c:587:
warning: Function parameter or member 'context' not described in
'dcn32_can_support_mclk_switch_using_fw_based_vblank_stretch'

Cc: Hamza Mahfooz 
Cc: Rodrigo Siqueira 
Cc: Harry Wentland 
Cc: Aurabindo Pillai 
Signed-off-by: Srinivasan Shanmugam 
---

v2:
 - Fixes added for line no. 587 also.

 .../display/dc/dcn32/dcn32_resource_helpers.c | 57 ---
 1 file changed, 23 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c 
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
index a8082580df92..1d13fd797212 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
@@ -94,18 +94,15 @@ uint32_t dcn32_helper_calculate_mall_bytes_for_cursor(
 }

 /**
- * 

- * dcn32_helper_calculate_num_ways_for_subvp: Calculate number of ways needed 
for SubVP
+ * dcn32_helper_calculate_num_ways_for_subvp(): Calculate number of ways 
needed for SubVP
  *
  * Gets total allocation required for the phantom viewport calculated by DML 
in bytes and
  * converts to number of cache ways.
  *
- * @param [in] dc: current dc state
- * @param [in] context: new dc state
+ * @dc: current dc state
+ * @context: new dc state
  *
- * @return: number of ways required for SubVP
- *
- * 

+ * Return: number of ways required for SubVP
  */
 uint32_t dcn32_helper_calculate_num_ways_for_subvp(
 struct dc *dc,
@@ -261,8 +258,7 @@ bool dcn32_is_psr_capable(struct pipe_ctx *pipe)
 #define DCN3_2_NEW_DET_OVERRIDE_MIN_MULTIPLIER 7

 /**
- * 
***
- * dcn32_determine_det_override: Determine DET allocation for each pipe
+ * dcn32_determine_det_override(): Determine DET allocation for each pipe
  *
  * This function determines how much DET to allocate for each pipe. The total 
number of
  * DET segments will be split equally among each of the streams, and after 
that the DET
@@ -290,13 +286,11 @@ bool dcn32_is_psr_capable(struct pipe_ctx *pipe)
  * 3. Assign smaller DET size for lower pixel display and higher DET size for
  *higher pixel display
  *
- * @param [in]: dc: Current DC state
- * @param [in]: context: New DC state to be programmed
- * @param [in]: pipes: Array of DML pipes
- *
- * @return: void
+ * @dc: Current DC state
+ * @context: New DC state to be programmed
+ * @pipes: Array of DML pipes
  *
- * 
***
+ * Return: void
  */
 void dcn32_determine_det_override(struct dc *dc,
 struct dc_state *context,
@@ -432,8 +426,7 @@ void dcn32_set_det_allocations(struct dc *dc, struct 
dc_state *context,
 }

 /**
- * 
***
- * dcn32_save_mall_state: Save MALL (SubVP) state for fast validation cases
+ * dcn

Re: [PATCH v2] drm/amdgpu: skip force complete fences when ring is uninitialized

[Christian König]

Am 31.05.23 um 11:34 schrieb Bob Zhou:

uvd ring in uvd_v7_0_sw_init only initializes ring in bare metal case,
so when executing amdgpu_uvd_resume to restore fence seq in SRIOV,
a null pointer dereference will occur. This patch correct this.


Mhm, taking a higher level look at this why isn't the ring initialized 
when the VCPU BO is allocated?


Adding Leo as well since that looks more like a design issue to me.

Regards,
Christian.



Fixes: 043f2271e2d0 ("drm/amdgpu: mark force completed fences with -ECANCELED")

BUG: kernel NULL pointer dereference, address: 
Oops:  [#1] PREEMPT SMP PTI
RIP: 0010:amdgpu_fence_driver_set_error+0x3f/0xc0 [amdgpu]
Call Trace:
  
  amdgpu_fence_driver_force_completion+0x18/0x50 [amdgpu]
  amdgpu_uvd_resume+0x1b2/0x380 [amdgpu]
  ? amdgpu_ring_init+0x73c/0x820 [amdgpu]
  uvd_v7_0_sw_init+0x358/0x450 [amdgpu]
  amdgpu_device_init.cold+0x198c/0x1fdf [amdgpu]
  ? pci_bus_read_config_byte+0x40/0x80
  ? pci_read_config_byte+0x27/0x50
  amdgpu_driver_load_kms+0x1a/0x160 [amdgpu]
  amdgpu_pci_probe+0x186/0x3c0 [amdgpu]

Signed-off-by: Bob Zhou 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 3 ++-
  1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
index b7441654e6fa..70e7e9585d3c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
@@ -506,7 +506,8 @@ int amdgpu_uvd_resume(struct amdgpu_device *adev)
}
memset_io(ptr, 0, size);
/* to restore uvd fence seq */
-   
amdgpu_fence_driver_force_completion(&adev->uvd.inst[i].ring);
+   if (adev->uvd.inst[i].ring.fence_drv.irq_src)
+   
amdgpu_fence_driver_force_completion(&adev->uvd.inst[i].ring);
}
}
return 0;

Re: [PATCH] drm/amd/pm: conditionally disable pcie lane switching for some sienna_cichlid SKUs

[Alex Deucher]

Reviewed-by: Alex Deucher 

On Wed, May 31, 2023 at 8:12 AM Alex Deucher  wrote:
>
> Sure.  Please go ahead.
>
> Alex
>
> On Wed, May 31, 2023 at 5:54 AM Quan, Evan  wrote:
> >
> > [AMD Official Use Only - General]
> >
> > Hi Alex,
> >
> > Can we land this as a temporary solution while we are seeking a more proper 
> > one?
> > This is gating our customer and I was pushed for a solution.
> >
> > BR,
> > Evan
> > > -Original Message-
> > > From: Quan, Evan
> > > Sent: Friday, April 21, 2023 3:32 PM
> > > To: amd-gfx@lists.freedesktop.org
> > > Cc: Deucher, Alexander ; Limonciello, Mario
> > > 
> > > Subject: RE: [PATCH] drm/amd/pm: conditionally disable pcie lane switching
> > > for some sienna_cichlid SKUs
> > >
> > > [AMD Official Use Only - General]
> > >
> > > This seems able to address some audio noise issue observed per customer's
> > > feedback.
> > >
> > > Evan
> > > > -Original Message-
> > > > From: Quan, Evan 
> > > > Sent: Friday, April 21, 2023 3:29 PM
> > > > To: amd-gfx@lists.freedesktop.org
> > > > Cc: Deucher, Alexander ; Limonciello, Mario
> > > > ; Quan, Evan 
> > > > Subject: [PATCH] drm/amd/pm: conditionally disable pcie lane switching
> > > > for some sienna_cichlid SKUs
> > > >
> > > > Disable the pcie lane switching for some sienna_cichlid SKUs since it
> > > > might not work well on some platforms.
> > > >
> > > > Signed-off-by: Evan Quan 
> > > > Change-Id: Iea9ceaa146c8706768ee077c10e5d33bce9bc1c2
> > > > ---
> > > >  .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c   | 92 +++-
> > > --
> > > > -
> > > >  1 file changed, 74 insertions(+), 18 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > > > b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > > > index 4b91cdc3eaa0..e7223513e384 100644
> > > > --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > > > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > > > @@ -2067,33 +2067,94 @@ static int
> > > > sienna_cichlid_display_disable_memory_clock_switch(struct smu_context
> > > > return ret;
> > > >  }
> > > >
> > > > +static void sienna_cichlid_get_override_pcie_settings(struct
> > > > +smu_context
> > > > *smu,
> > > > + uint32_t
> > > > *gen_speed_override,
> > > > + uint32_t
> > > > *lane_width_override)
> > > > +{
> > > > +   struct amdgpu_device *adev = smu->adev;
> > > > +
> > > > +   *gen_speed_override = 0xff;
> > > > +   *lane_width_override = 0xff;
> > > > +
> > > > +   switch (adev->pdev->device) {
> > > > +   case 0x73A0:
> > > > +   case 0x73A1:
> > > > +   case 0x73A2:
> > > > +   case 0x73A3:
> > > > +   case 0x73AB:
> > > > +   case 0x73AE:
> > > > +   /* Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to 
> > > > x32 */
> > > > +   *lane_width_override = 6;
> > > > +   break;
> > > > +   case 0x73E0:
> > > > +   case 0x73E1:
> > > > +   case 0x73E3:
> > > > +   *lane_width_override = 4;
> > > > +   break;
> > > > +   case 0x7420:
> > > > +   case 0x7421:
> > > > +   case 0x7422:
> > > > +   case 0x7423:
> > > > +   case 0x7424:
> > > > +   *lane_width_override = 3;
> > > > +   break;
> > > > +   default:
> > > > +   break;
> > > > +   }
> > > > +}
> > > > +
> > > > +#define MAX(a, b)  ((a) > (b) ? (a) : (b))
> > > > +
> > > >  static int sienna_cichlid_update_pcie_parameters(struct smu_context 
> > > > *smu,
> > > >  uint32_t pcie_gen_cap,
> > > >  uint32_t pcie_width_cap)
> > > >  {
> > > > struct smu_11_0_dpm_context *dpm_context = smu-
> > > > >smu_dpm.dpm_context;
> > > > -
> > > > -   uint32_t smu_pcie_arg;
> > > > +   struct smu_11_0_pcie_table *pcie_table = &dpm_context-
> > > > >dpm_tables.pcie_table;
> > > > +   uint32_t gen_speed_override, lane_width_override;
> > > > uint8_t *table_member1, *table_member2;
> > > > +   uint32_t min_gen_speed, max_gen_speed;
> > > > +   uint32_t min_lane_width, max_lane_width;
> > > > +   uint32_t smu_pcie_arg;
> > > > int ret, i;
> > > >
> > > > GET_PPTABLE_MEMBER(PcieGenSpeed, &table_member1);
> > > > GET_PPTABLE_MEMBER(PcieLaneCount, &table_member2);
> > > >
> > > > -   /* lclk dpm table setup */
> > > > -   for (i = 0; i < MAX_PCIE_CONF; i++) {
> > > > -   dpm_context->dpm_tables.pcie_table.pcie_gen[i] =
> > > > table_member1[i];
> > > > -   dpm_context->dpm_tables.pcie_table.pcie_lane[i] =
> > > > table_member2[i];
> > > > +   sienna_cichlid_get_override_pcie_settings(smu,
> > > > + &gen_speed_override,
> > > > + &lane_width_override);
> > > > +
> > > > +   /* PCIE gen speed override */
> > > > +   if (gen_speed_override != 0xff) {
> > > > +   min_gen_speed = MIN(pcie_gen_cap, gen_speed_override)

Re: [PATCH] drm/dp_mst: Clear MSG_RDY flag before sending new message

[Alex Deucher]

+ dri-devel

On Wed, May 31, 2023 at 12:01 AM Wayne Lin  wrote:
>
> [Why]
> The sequence for collecting down_reply from source perspective should
> be:
>
> Request_n->repeat (get partial reply of Request_n->clear message ready
> flag to ack DPRX that the message is received) till all partial
> replies for Request_n are received->new Request_n+1.
>
> Now there is chance that drm_dp_mst_hpd_irq() will fire new down
> request in the tx queue when the down reply is incomplete. Source is
> restricted to generate interveleaved message transactions so we should
> avoid it.
>
> Also, while assembling partial reply packets, reading out DPCD DOWN_REP
> Sideband MSG buffer + clearing DOWN_REP_MSG_RDY flag should be
> wrapped up as a complete operation for reading out a reply packet.
> Kicking off a new request before clearing DOWN_REP_MSG_RDY flag might
> be risky. e.g. If the reply of the new request has overwritten the
> DPRX DOWN_REP Sideband MSG buffer before source writing one to clear
> DOWN_REP_MSG_RDY flag, source then unintentionally flushes the reply
> for the new request. Should handle the up request in the same way.
>
> [How]
> Separete drm_dp_mst_hpd_irq() into 2 steps. After acking the MST IRQ
> event, driver calls drm_dp_mst_hpd_irq_send_new_request() and might
> trigger drm_dp_mst_kick_tx() only when there is no on going message
> transaction.
>
> Changes since v1:
> * Reworked on review comments received
> -> Adjust the fix to let driver explicitly kick off new down request
> when mst irq event is handled and acked
> -> Adjust the commit message
>
> Changes since v2:
> * Adjust the commit message
> * Adjust the naming of the divided 2 functions and add a new input
>   parameter "ack".
> * Adjust code flow as per review comments.
>
> Signed-off-by: Wayne Lin 
> Cc: sta...@vger.kernel.org
> ---
>  .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 33 +---
>  drivers/gpu/drm/display/drm_dp_mst_topology.c | 39 +--
>  drivers/gpu/drm/i915/display/intel_dp.c   |  7 ++--
>  drivers/gpu/drm/nouveau/dispnv50/disp.c   | 12 --
>  include/drm/display/drm_dp_mst_helper.h   |  7 +++-
>  5 files changed, 70 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index d5cec03eaa8d..597c3368bcfb 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -3236,6 +3236,7 @@ static void dm_handle_mst_sideband_msg(struct 
> amdgpu_dm_connector *aconnector)
>  {
> u8 esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
> u8 dret;
> +   u8 ack;
> bool new_irq_handled = false;
> int dpcd_addr;
> int dpcd_bytes_to_read;
> @@ -3265,34 +3266,36 @@ static void dm_handle_mst_sideband_msg(struct 
> amdgpu_dm_connector *aconnector)
> process_count < max_process_count) {
> u8 retry;
> dret = 0;
> +   ack = 0;
>
> process_count++;
>
> DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], 
> esi[2]);
> /* handle HPD short pulse irq */
> if (aconnector->mst_mgr.mst_state)
> -   drm_dp_mst_hpd_irq(
> -   &aconnector->mst_mgr,
> -   esi,
> -   &new_irq_handled);
> +   drm_dp_mst_hpd_irq_handle_event(&aconnector->mst_mgr,
> +   esi,
> +   &ack,
> +   &new_irq_handled);
>
> if (new_irq_handled) {
> /* ACK at DPCD to notify down stream */
> -   const int ack_dpcd_bytes_to_write =
> -   dpcd_bytes_to_read - 1;
> -
> for (retry = 0; retry < 3; retry++) {
> -   u8 wret;
> -
> -   wret = drm_dp_dpcd_write(
> -   &aconnector->dm_dp_aux.aux,
> -   dpcd_addr + 1,
> -   &esi[1],
> -   ack_dpcd_bytes_to_write);
> -   if (wret == ack_dpcd_bytes_to_write)
> +   ssize_t wret;
> +
> +   wret = 
> drm_dp_dpcd_writeb(&aconnector->dm_dp_aux.aux,
> + dpcd_addr + 1,
> + ack);
> +   if (wret == 1)
> break;
> }
>
> +   if (retry == 3) {
> +   DRM_ERROR("Failed to ack MST eve

Re: [PATCH v5 08/13] drm/omapdrm: Use regular fbdev I/O helpers

[Tomi Valkeinen]

On 30/05/2023 18:02, Thomas Zimmermann wrote:

Use the regular fbdev helpers for framebuffer I/O instead of DRM's
helpers. Omapdrm does not use damage handling, so DRM's fbdev helpers
are mere wrappers around the fbdev code.

By using fbdev helpers directly within each DRM fbdev emulation,
we can eventually remove DRM's wrapper functions entirely.

v4:
* use initializer macros for struct fb_ops
v2:
* use FB_SYS_HELPERS option

Signed-off-by: Thomas Zimmermann 
Acked-by: Sam Ravnborg 
Cc: Tomi Valkeinen 
---
  drivers/gpu/drm/omapdrm/Kconfig  |  1 +
  drivers/gpu/drm/omapdrm/omap_fbdev.c | 11 +++
  2 files changed, 4 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/omapdrm/Kconfig b/drivers/gpu/drm/omapdrm/Kconfig
index 76ded1568bd0..b4ac76c9f31b 100644
--- a/drivers/gpu/drm/omapdrm/Kconfig
+++ b/drivers/gpu/drm/omapdrm/Kconfig
@@ -4,6 +4,7 @@ config DRM_OMAP
depends on DRM && OF
depends on ARCH_OMAP2PLUS
select DRM_KMS_HELPER
+   select FB_SYS_HELPERS if DRM_FBDEV_EMULATION
select VIDEOMODE_HELPERS
select HDMI
default n
diff --git a/drivers/gpu/drm/omapdrm/omap_fbdev.c 
b/drivers/gpu/drm/omapdrm/omap_fbdev.c
index b950e93b3846..b7ccce0704a3 100644
--- a/drivers/gpu/drm/omapdrm/omap_fbdev.c
+++ b/drivers/gpu/drm/omapdrm/omap_fbdev.c
@@ -4,6 +4,8 @@
   * Author: Rob Clark 
   */
  
+#include 

+
  #include 
  #include 
  #include 
@@ -95,20 +97,13 @@ static void omap_fbdev_fb_destroy(struct fb_info *info)
  
  static const struct fb_ops omap_fb_ops = {

.owner = THIS_MODULE,
-
+   FB_DEFAULT_SYS_OPS,
.fb_check_var   = drm_fb_helper_check_var,
.fb_set_par = drm_fb_helper_set_par,
.fb_setcmap = drm_fb_helper_setcmap,
.fb_blank   = drm_fb_helper_blank,
.fb_pan_display = omap_fbdev_pan_display,
.fb_ioctl   = drm_fb_helper_ioctl,
-
-   .fb_read = drm_fb_helper_sys_read,
-   .fb_write = drm_fb_helper_sys_write,
-   .fb_fillrect = drm_fb_helper_sys_fillrect,
-   .fb_copyarea = drm_fb_helper_sys_copyarea,
-   .fb_imageblit = drm_fb_helper_sys_imageblit,
-
.fb_destroy = omap_fbdev_fb_destroy,
  };
  


Reviewed-by: Tomi Valkeinen 

 Tomi

Re: [PATCH] drm/amd/pm: conditionally disable pcie lane switching for some sienna_cichlid SKUs

[Alex Deucher]

Sure.  Please go ahead.

Alex

On Wed, May 31, 2023 at 5:54 AM Quan, Evan  wrote:
>
> [AMD Official Use Only - General]
>
> Hi Alex,
>
> Can we land this as a temporary solution while we are seeking a more proper 
> one?
> This is gating our customer and I was pushed for a solution.
>
> BR,
> Evan
> > -Original Message-
> > From: Quan, Evan
> > Sent: Friday, April 21, 2023 3:32 PM
> > To: amd-gfx@lists.freedesktop.org
> > Cc: Deucher, Alexander ; Limonciello, Mario
> > 
> > Subject: RE: [PATCH] drm/amd/pm: conditionally disable pcie lane switching
> > for some sienna_cichlid SKUs
> >
> > [AMD Official Use Only - General]
> >
> > This seems able to address some audio noise issue observed per customer's
> > feedback.
> >
> > Evan
> > > -Original Message-
> > > From: Quan, Evan 
> > > Sent: Friday, April 21, 2023 3:29 PM
> > > To: amd-gfx@lists.freedesktop.org
> > > Cc: Deucher, Alexander ; Limonciello, Mario
> > > ; Quan, Evan 
> > > Subject: [PATCH] drm/amd/pm: conditionally disable pcie lane switching
> > > for some sienna_cichlid SKUs
> > >
> > > Disable the pcie lane switching for some sienna_cichlid SKUs since it
> > > might not work well on some platforms.
> > >
> > > Signed-off-by: Evan Quan 
> > > Change-Id: Iea9ceaa146c8706768ee077c10e5d33bce9bc1c2
> > > ---
> > >  .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c   | 92 +++-
> > --
> > > -
> > >  1 file changed, 74 insertions(+), 18 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > > b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > > index 4b91cdc3eaa0..e7223513e384 100644
> > > --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > > @@ -2067,33 +2067,94 @@ static int
> > > sienna_cichlid_display_disable_memory_clock_switch(struct smu_context
> > > return ret;
> > >  }
> > >
> > > +static void sienna_cichlid_get_override_pcie_settings(struct
> > > +smu_context
> > > *smu,
> > > + uint32_t
> > > *gen_speed_override,
> > > + uint32_t
> > > *lane_width_override)
> > > +{
> > > +   struct amdgpu_device *adev = smu->adev;
> > > +
> > > +   *gen_speed_override = 0xff;
> > > +   *lane_width_override = 0xff;
> > > +
> > > +   switch (adev->pdev->device) {
> > > +   case 0x73A0:
> > > +   case 0x73A1:
> > > +   case 0x73A2:
> > > +   case 0x73A3:
> > > +   case 0x73AB:
> > > +   case 0x73AE:
> > > +   /* Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 
> > > */
> > > +   *lane_width_override = 6;
> > > +   break;
> > > +   case 0x73E0:
> > > +   case 0x73E1:
> > > +   case 0x73E3:
> > > +   *lane_width_override = 4;
> > > +   break;
> > > +   case 0x7420:
> > > +   case 0x7421:
> > > +   case 0x7422:
> > > +   case 0x7423:
> > > +   case 0x7424:
> > > +   *lane_width_override = 3;
> > > +   break;
> > > +   default:
> > > +   break;
> > > +   }
> > > +}
> > > +
> > > +#define MAX(a, b)  ((a) > (b) ? (a) : (b))
> > > +
> > >  static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu,
> > >  uint32_t pcie_gen_cap,
> > >  uint32_t pcie_width_cap)
> > >  {
> > > struct smu_11_0_dpm_context *dpm_context = smu-
> > > >smu_dpm.dpm_context;
> > > -
> > > -   uint32_t smu_pcie_arg;
> > > +   struct smu_11_0_pcie_table *pcie_table = &dpm_context-
> > > >dpm_tables.pcie_table;
> > > +   uint32_t gen_speed_override, lane_width_override;
> > > uint8_t *table_member1, *table_member2;
> > > +   uint32_t min_gen_speed, max_gen_speed;
> > > +   uint32_t min_lane_width, max_lane_width;
> > > +   uint32_t smu_pcie_arg;
> > > int ret, i;
> > >
> > > GET_PPTABLE_MEMBER(PcieGenSpeed, &table_member1);
> > > GET_PPTABLE_MEMBER(PcieLaneCount, &table_member2);
> > >
> > > -   /* lclk dpm table setup */
> > > -   for (i = 0; i < MAX_PCIE_CONF; i++) {
> > > -   dpm_context->dpm_tables.pcie_table.pcie_gen[i] =
> > > table_member1[i];
> > > -   dpm_context->dpm_tables.pcie_table.pcie_lane[i] =
> > > table_member2[i];
> > > +   sienna_cichlid_get_override_pcie_settings(smu,
> > > + &gen_speed_override,
> > > + &lane_width_override);
> > > +
> > > +   /* PCIE gen speed override */
> > > +   if (gen_speed_override != 0xff) {
> > > +   min_gen_speed = MIN(pcie_gen_cap, gen_speed_override);
> > > +   max_gen_speed = MIN(pcie_gen_cap,
> > > gen_speed_override);
> > > +   } else {
> > > +   min_gen_speed = MAX(0, table_member1[0]);
> > > +   max_gen_speed = MIN(pcie_gen_cap, table_member1[1]);
> > > +   min_gen_speed = min_gen_speed > max_gen_speed ?
> > > +   max_gen_speed : min_gen_speed;
> 

RE: [PATCH] drm/amd/pm: conditionally disable pcie lane switching for some sienna_cichlid SKUs

[Quan, Evan]

[AMD Official Use Only - General]

Hi Alex,

Can we land this as a temporary solution while we are seeking a more proper one?
This is gating our customer and I was pushed for a solution.

BR,
Evan
> -Original Message-
> From: Quan, Evan
> Sent: Friday, April 21, 2023 3:32 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Limonciello, Mario
> 
> Subject: RE: [PATCH] drm/amd/pm: conditionally disable pcie lane switching
> for some sienna_cichlid SKUs
>
> [AMD Official Use Only - General]
>
> This seems able to address some audio noise issue observed per customer's
> feedback.
>
> Evan
> > -Original Message-
> > From: Quan, Evan 
> > Sent: Friday, April 21, 2023 3:29 PM
> > To: amd-gfx@lists.freedesktop.org
> > Cc: Deucher, Alexander ; Limonciello, Mario
> > ; Quan, Evan 
> > Subject: [PATCH] drm/amd/pm: conditionally disable pcie lane switching
> > for some sienna_cichlid SKUs
> >
> > Disable the pcie lane switching for some sienna_cichlid SKUs since it
> > might not work well on some platforms.
> >
> > Signed-off-by: Evan Quan 
> > Change-Id: Iea9ceaa146c8706768ee077c10e5d33bce9bc1c2
> > ---
> >  .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c   | 92 +++-
> --
> > -
> >  1 file changed, 74 insertions(+), 18 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > index 4b91cdc3eaa0..e7223513e384 100644
> > --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > @@ -2067,33 +2067,94 @@ static int
> > sienna_cichlid_display_disable_memory_clock_switch(struct smu_context
> > return ret;
> >  }
> >
> > +static void sienna_cichlid_get_override_pcie_settings(struct
> > +smu_context
> > *smu,
> > + uint32_t
> > *gen_speed_override,
> > + uint32_t
> > *lane_width_override)
> > +{
> > +   struct amdgpu_device *adev = smu->adev;
> > +
> > +   *gen_speed_override = 0xff;
> > +   *lane_width_override = 0xff;
> > +
> > +   switch (adev->pdev->device) {
> > +   case 0x73A0:
> > +   case 0x73A1:
> > +   case 0x73A2:
> > +   case 0x73A3:
> > +   case 0x73AB:
> > +   case 0x73AE:
> > +   /* Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 */
> > +   *lane_width_override = 6;
> > +   break;
> > +   case 0x73E0:
> > +   case 0x73E1:
> > +   case 0x73E3:
> > +   *lane_width_override = 4;
> > +   break;
> > +   case 0x7420:
> > +   case 0x7421:
> > +   case 0x7422:
> > +   case 0x7423:
> > +   case 0x7424:
> > +   *lane_width_override = 3;
> > +   break;
> > +   default:
> > +   break;
> > +   }
> > +}
> > +
> > +#define MAX(a, b)  ((a) > (b) ? (a) : (b))
> > +
> >  static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu,
> >  uint32_t pcie_gen_cap,
> >  uint32_t pcie_width_cap)
> >  {
> > struct smu_11_0_dpm_context *dpm_context = smu-
> > >smu_dpm.dpm_context;
> > -
> > -   uint32_t smu_pcie_arg;
> > +   struct smu_11_0_pcie_table *pcie_table = &dpm_context-
> > >dpm_tables.pcie_table;
> > +   uint32_t gen_speed_override, lane_width_override;
> > uint8_t *table_member1, *table_member2;
> > +   uint32_t min_gen_speed, max_gen_speed;
> > +   uint32_t min_lane_width, max_lane_width;
> > +   uint32_t smu_pcie_arg;
> > int ret, i;
> >
> > GET_PPTABLE_MEMBER(PcieGenSpeed, &table_member1);
> > GET_PPTABLE_MEMBER(PcieLaneCount, &table_member2);
> >
> > -   /* lclk dpm table setup */
> > -   for (i = 0; i < MAX_PCIE_CONF; i++) {
> > -   dpm_context->dpm_tables.pcie_table.pcie_gen[i] =
> > table_member1[i];
> > -   dpm_context->dpm_tables.pcie_table.pcie_lane[i] =
> > table_member2[i];
> > +   sienna_cichlid_get_override_pcie_settings(smu,
> > + &gen_speed_override,
> > + &lane_width_override);
> > +
> > +   /* PCIE gen speed override */
> > +   if (gen_speed_override != 0xff) {
> > +   min_gen_speed = MIN(pcie_gen_cap, gen_speed_override);
> > +   max_gen_speed = MIN(pcie_gen_cap,
> > gen_speed_override);
> > +   } else {
> > +   min_gen_speed = MAX(0, table_member1[0]);
> > +   max_gen_speed = MIN(pcie_gen_cap, table_member1[1]);
> > +   min_gen_speed = min_gen_speed > max_gen_speed ?
> > +   max_gen_speed : min_gen_speed;
> > }
> > +   pcie_table->pcie_gen[0] = min_gen_speed;
> > +   pcie_table->pcie_gen[1] = max_gen_speed;
> > +
> > +   /* PCIE lane width override */
> > +   if (lane_width_override != 0xff) {
> > +   min_lane_width = MIN(pcie_width_cap,
> > lane_width_override);
> > +   max_lane_width = MIN(pcie_width_cap,
> > lane_width_override);
> > +   } e

[PATCH v2] drm/amdgpu: skip force complete fences when ring is uninitialized

[Bob Zhou]

uvd ring in uvd_v7_0_sw_init only initializes ring in bare metal case,
so when executing amdgpu_uvd_resume to restore fence seq in SRIOV,
a null pointer dereference will occur. This patch correct this.

Fixes: 043f2271e2d0 ("drm/amdgpu: mark force completed fences with -ECANCELED")

BUG: kernel NULL pointer dereference, address: 
Oops:  [#1] PREEMPT SMP PTI
RIP: 0010:amdgpu_fence_driver_set_error+0x3f/0xc0 [amdgpu]
Call Trace:
 
 amdgpu_fence_driver_force_completion+0x18/0x50 [amdgpu]
 amdgpu_uvd_resume+0x1b2/0x380 [amdgpu]
 ? amdgpu_ring_init+0x73c/0x820 [amdgpu]
 uvd_v7_0_sw_init+0x358/0x450 [amdgpu]
 amdgpu_device_init.cold+0x198c/0x1fdf [amdgpu]
 ? pci_bus_read_config_byte+0x40/0x80
 ? pci_read_config_byte+0x27/0x50
 amdgpu_driver_load_kms+0x1a/0x160 [amdgpu]
 amdgpu_pci_probe+0x186/0x3c0 [amdgpu]

Signed-off-by: Bob Zhou 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
index b7441654e6fa..70e7e9585d3c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
@@ -506,7 +506,8 @@ int amdgpu_uvd_resume(struct amdgpu_device *adev)
}
memset_io(ptr, 0, size);
/* to restore uvd fence seq */
-   
amdgpu_fence_driver_force_completion(&adev->uvd.inst[i].ring);
+   if (adev->uvd.inst[i].ring.fence_drv.irq_src)
+   
amdgpu_fence_driver_force_completion(&adev->uvd.inst[i].ring);
}
}
return 0;
-- 
2.34.1

[PATCH v2] drm/amd/display: Fix up kdoc formatting in dcn32_resource_helpers.c

[Srinivasan Shanmugam]

Fixes the following W=1 kernel build warning:

drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_resource_helpers.c:97: 
warning: Cannot understand  * 
**
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_resource_helpers.c:264: 
warning: Cannot understand  * 
*
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_resource_helpers.c:435: 
warning: Cannot understand  * 
*
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_resource_helpers.c:475: 
warning: Cannot understand  * 
*

drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_resource_helpers.c:599:
warning: Function parameter or member 'dc' not described in
'dcn32_can_support_mclk_switch_using_fw_based_vblank_stretch'
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_resource_helpers.c:599:
warning: Function parameter or member 'context' not described in
'dcn32_can_support_mclk_switch_using_fw_based_vblank_stretch'

drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_resource_helpers.c:587:
warning: Function parameter or member 'dc' not described in
'dcn32_can_support_mclk_switch_using_fw_based_vblank_stretch'
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_resource_helpers.c:587:
warning: Function parameter or member 'context' not described in
'dcn32_can_support_mclk_switch_using_fw_based_vblank_stretch'

Cc: Hamza Mahfooz 
Cc: Rodrigo Siqueira 
Cc: Harry Wentland 
Cc: Aurabindo Pillai 
Signed-off-by: Srinivasan Shanmugam 
---

v2: 
 - Fixes added for line no. 587 also.

 .../display/dc/dcn32/dcn32_resource_helpers.c | 57 ---
 1 file changed, 23 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c 
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
index a8082580df92..1d13fd797212 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
@@ -94,18 +94,15 @@ uint32_t dcn32_helper_calculate_mall_bytes_for_cursor(
 }
 
 /**
- * 

- * dcn32_helper_calculate_num_ways_for_subvp: Calculate number of ways needed 
for SubVP
+ * dcn32_helper_calculate_num_ways_for_subvp(): Calculate number of ways 
needed for SubVP
  *
  * Gets total allocation required for the phantom viewport calculated by DML 
in bytes and
  * converts to number of cache ways.
  *
- * @param [in] dc: current dc state
- * @param [in] context: new dc state
+ * @dc: current dc state
+ * @context: new dc state
  *
- * @return: number of ways required for SubVP
- *
- * 

+ * Return: number of ways required for SubVP
  */
 uint32_t dcn32_helper_calculate_num_ways_for_subvp(
struct dc *dc,
@@ -261,8 +258,7 @@ bool dcn32_is_psr_capable(struct pipe_ctx *pipe)
 #define DCN3_2_NEW_DET_OVERRIDE_MIN_MULTIPLIER 7
 
 /**
- * 
***
- * dcn32_determine_det_override: Determine DET allocation for each pipe
+ * dcn32_determine_det_override(): Determine DET allocation for each pipe
  *
  * This function determines how much DET to allocate for each pipe. The total 
number of
  * DET segments will be split equally among each of the streams, and after 
that the DET
@@ -290,13 +286,11 @@ bool dcn32_is_psr_capable(struct pipe_ctx *pipe)
  * 3. Assign smaller DET size for lower pixel display and higher DET size for
  *higher pixel display
  *
- * @param [in]: dc: Current DC state
- * @param [in]: context: New DC state to be programmed
- * @param [in]: pipes: Array of DML pipes
- *
- * @return: void
+ * @dc: Current DC state
+ * @context: New DC state to be programmed
+ * @pipes: Array of DML pipes
  *
- * 
***
+ * Return: void
  */
 void dcn32_determine_det_override(struct dc *dc,
struct dc_state *context,
@@ -432,8 +426,7 @@ void dcn32_set_det_allocations(struct dc *dc, struct 
dc_state *context,
 }
 
 /**
- * 
***
- * dcn32_save_mall_state: Save MALL (SubVP) state for fast validation cases
+ * dcn32_save_mall_state(): Save MALL (SubVP) state for fast validation cases
  *
  * This function saves the MALL (SubVP) case for fast validation cases. For 
fast validation,
  * there are situations where a shallow copy of the dc->current_state is 
created for the
@@ -446,13 +439,11 @@ void dcn32_set_det_allocations(struct dc *dc, struct 
dc_state *context,
  * NOTE: This function ONLY w

RE: [PATCH] drm/amdgpu: skip force complete fences when ring is uninitialized

[Zhou, Bob]

[AMD Official Use Only - General]

Hi Christian,

Thanks for your suggestion.  I will apply it and send out the v2 patch for 
review.

Regards,
Bob

-Original Message-
From: Koenig, Christian 
Sent: Wednesday, May 31, 2023 4:33 PM
To: Zhou, Bob ; amd-gfx@lists.freedesktop.org; Min, Frank 

Cc: Chen, Guchun 
Subject: Re: [PATCH] drm/amdgpu: skip force complete fences when ring is 
uninitialized



Am 31.05.23 um 06:48 schrieb Bob Zhou:
> uvd ring in uvd_v7_0_sw_init only initializes ring in bare metal case,
> so when executing amdgpu_uvd_resume to restore fence seq in SRIOV, a
> null pointer dereference will occur. This patch correct this.

Ah! I was already wondering how this bug reports came to be.

In this case please fix the UVD code to not call
amdgpu_fence_driver_force_completion() in the first place instead of hacking 
around that in the fence code.

Regards,
Christian.

>
> Fixes: 043f2271e2d0a ("drm/amdgpu: mark force completed fences with
> -ECANCELED")
>
> BUG: kernel NULL pointer dereference, address: 
> Oops:  [#1] PREEMPT SMP PTI
> RIP: 0010:amdgpu_fence_driver_set_error+0x3f/0xc0 [amdgpu] Call Trace:
>   
>   amdgpu_fence_driver_force_completion+0x18/0x50 [amdgpu]
>   amdgpu_uvd_resume+0x1b2/0x380 [amdgpu]
>   ? amdgpu_ring_init+0x73c/0x820 [amdgpu]
>   uvd_v7_0_sw_init+0x358/0x450 [amdgpu]
>   amdgpu_device_init.cold+0x198c/0x1fdf [amdgpu]
>   ? pci_bus_read_config_byte+0x40/0x80
>   ? pci_read_config_byte+0x27/0x50
>   amdgpu_driver_load_kms+0x1a/0x160 [amdgpu]
>   amdgpu_pci_probe+0x186/0x3c0 [amdgpu]
>
> Signed-off-by: Bob Zhou 
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 2 ++
>   1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
> index c694b41f6461..d2c5484309a6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
> @@ -723,6 +723,8 @@ void amdgpu_fence_driver_set_error(struct amdgpu_ring 
> *ring, int error)
>*/
>   void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring)
>   {
> + if (ring->fence_drv.irq_src)
> + return;
>   amdgpu_fence_driver_set_error(ring, -ECANCELED);
>   amdgpu_fence_write(ring, ring->fence_drv.sync_seq);
>   amdgpu_fence_process(ring);

Re: [PATCH v2] drm/ttm: Remove redundant code in ttm_tt_init_fields

[Christian König]

Am 31.05.23 um 08:20 schrieb Chen, Guchun:

[Public]


-Original Message-
From: amd-gfx  On Behalf Of Ma
Jun
Sent: Wednesday, May 31, 2023 1:31 PM
To: amd-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org; Koenig,
Christian 
Cc: Ma, Jun 
Subject: [PATCH v2] drm/ttm: Remove redundant code in ttm_tt_init_fields

Remove redundant assignment code for ttm->caching as it's overwritten

just a few lines later.

Please drop the blank line in above message. With it fixed, the patch is: 
Reviewed-by: Guchun Chen 


Seconded, I'm going to pick that patch up and submit it to drm-misc-next 
with the commit message fixed.


Regards,
Christian.



Regards,
Guchun


v2:
  - Update the commit message.

Signed-off-by: Ma Jun 
---
  drivers/gpu/drm/ttm/ttm_tt.c | 1 -
  1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c
index 02b812dacc5d..45a44544b656 100644
--- a/drivers/gpu/drm/ttm/ttm_tt.c
+++ b/drivers/gpu/drm/ttm/ttm_tt.c
@@ -143,7 +143,6 @@ static void ttm_tt_init_fields(struct ttm_tt *ttm,
  unsigned long extra_pages)
  {
   ttm->num_pages = (PAGE_ALIGN(bo->base.size) >> PAGE_SHIFT) +
extra_pages;
- ttm->caching = ttm_cached;
   ttm->page_flags = page_flags;
   ttm->dma_address = NULL;
   ttm->swap_storage = NULL;
--
2.34.1

Re: [PATCH] drm/amdgpu: skip force complete fences when ring is uninitialized

[Christian König]

Am 31.05.23 um 06:48 schrieb Bob Zhou:

uvd ring in uvd_v7_0_sw_init only initializes ring in bare metal case,
so when executing amdgpu_uvd_resume to restore fence seq in SRIOV,
a null pointer dereference will occur. This patch correct this.


Ah! I was already wondering how this bug reports came to be.

In this case please fix the UVD code to not call 
amdgpu_fence_driver_force_completion() in the first place instead of 
hacking around that in the fence code.


Regards,
Christian.



Fixes: 043f2271e2d0a ("drm/amdgpu: mark force completed fences with -ECANCELED")

BUG: kernel NULL pointer dereference, address: 
Oops:  [#1] PREEMPT SMP PTI
RIP: 0010:amdgpu_fence_driver_set_error+0x3f/0xc0 [amdgpu]
Call Trace:
  
  amdgpu_fence_driver_force_completion+0x18/0x50 [amdgpu]
  amdgpu_uvd_resume+0x1b2/0x380 [amdgpu]
  ? amdgpu_ring_init+0x73c/0x820 [amdgpu]
  uvd_v7_0_sw_init+0x358/0x450 [amdgpu]
  amdgpu_device_init.cold+0x198c/0x1fdf [amdgpu]
  ? pci_bus_read_config_byte+0x40/0x80
  ? pci_read_config_byte+0x27/0x50
  amdgpu_driver_load_kms+0x1a/0x160 [amdgpu]
  amdgpu_pci_probe+0x186/0x3c0 [amdgpu]

Signed-off-by: Bob Zhou 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 2 ++
  1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
index c694b41f6461..d2c5484309a6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
@@ -723,6 +723,8 @@ void amdgpu_fence_driver_set_error(struct amdgpu_ring 
*ring, int error)
   */
  void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring)
  {
+   if (ring->fence_drv.irq_src)
+   return;
amdgpu_fence_driver_set_error(ring, -ECANCELED);
amdgpu_fence_write(ring, ring->fence_drv.sync_seq);
amdgpu_fence_process(ring);

Re: [PATCH v2] drm/ttm: Remove redundant code in ttm_tt_init_fields

[Ma, Jun]

On 5/31/2023 2:20 PM, Chen, Guchun wrote:
> [Public]
> 
>> -Original Message-
>> From: amd-gfx  On Behalf Of Ma
>> Jun
>> Sent: Wednesday, May 31, 2023 1:31 PM
>> To: amd-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org; Koenig,
>> Christian 
>> Cc: Ma, Jun 
>> Subject: [PATCH v2] drm/ttm: Remove redundant code in ttm_tt_init_fields
>>
>> Remove redundant assignment code for ttm->caching as it's overwritten
>>
>> just a few lines later.
> 
> Please drop the blank line in above message. With it fixed, the patch is: 
> Reviewed-by: Guchun Chen 
> 
Thanks for review. Will fix it when push.

Regards,
Ma Jun
> Regards,
> Guchun
> 
>> v2:
>>  - Update the commit message.
>>
>> Signed-off-by: Ma Jun 
>> ---
>>  drivers/gpu/drm/ttm/ttm_tt.c | 1 -
>>  1 file changed, 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c
>> index 02b812dacc5d..45a44544b656 100644
>> --- a/drivers/gpu/drm/ttm/ttm_tt.c
>> +++ b/drivers/gpu/drm/ttm/ttm_tt.c
>> @@ -143,7 +143,6 @@ static void ttm_tt_init_fields(struct ttm_tt *ttm,
>>  unsigned long extra_pages)
>>  {
>>   ttm->num_pages = (PAGE_ALIGN(bo->base.size) >> PAGE_SHIFT) +
>> extra_pages;
>> - ttm->caching = ttm_cached;
>>   ttm->page_flags = page_flags;
>>   ttm->dma_address = NULL;
>>   ttm->swap_storage = NULL;
>> --
>> 2.34.1
> 

RE: [PATCH 1/3] drm/amdgpu/sdma: set sched.ready status after ring/IB test in sdma

[Chen, Guchun]

[Public]

Thanks for your review, Christian.  I have pushed them to amd-staging-drm-next 
branch with Alex's Acked-by last week.

Regards,
Guchun

> -Original Message-
> From: Koenig, Christian 
> Sent: Wednesday, May 31, 2023 2:39 PM
> To: Alex Deucher ; Chen, Guchun
> 
> Cc: amd-gfx@lists.freedesktop.org; Deucher, Alexander
> ; Zhang, Hawking
> ; Pan, Xinhui 
> Subject: Re: [PATCH 1/3] drm/amdgpu/sdma: set sched.ready status after
> ring/IB test in sdma
>
> If you haven't already pushed it: Reviewed-by: Christian König
>  for the entire series.
>
> Thanks for looking into that,
> Christian.
>
> Am 22.05.23 um 16:47 schrieb Alex Deucher:
> > Series is:
> > Acked-by: Alex Deucher 
> >
> > On Thu, May 18, 2023 at 3:04 AM Guchun Chen 
> wrote:
> >> sched.ready is nothing with ring initialization, it needs to set to
> >> be true after ring/IB test in amdgpu_ring_test_helper to tell the
> >> ring is ready for submission.
> >>
> >> Signed-off-by: Guchun Chen 
> >> ---
> >>   drivers/gpu/drm/amd/amdgpu/cik_sdma.c| 2 --
> >>   drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c   | 2 --
> >>   drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c   | 2 --
> >>   drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c   | 4 
> >>   drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 4 
> >>   drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c   | 2 --
> >>   drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c   | 4 ++--
> >>   drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c   | 6 +-
> >>   drivers/gpu/drm/amd/amdgpu/si_dma.c  | 2 --
> >>   9 files changed, 3 insertions(+), 25 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
> >> b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
> >> index 67d16236b216..52598fbc9b39 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
> >> +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
> >> @@ -489,8 +489,6 @@ static int cik_sdma_gfx_resume(struct
> amdgpu_device *adev)
> >>   #endif
> >>  /* enable DMA IBs */
> >>  WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i],
> >> ib_cntl);
> >> -
> >> -   ring->sched.ready = true;
> >>  }
> >>
> >>  cik_sdma_enable(adev, true); diff --git
> >> a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
> >> b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
> >> index fd2a7b66ac56..51afc92994a8 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
> >> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
> >> @@ -466,8 +466,6 @@ static int sdma_v2_4_gfx_resume(struct
> amdgpu_device *adev)
> >>   #endif
> >>  /* enable DMA IBs */
> >>  WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i],
> >> ib_cntl);
> >> -
> >> -   ring->sched.ready = true;
> >>  }
> >>
> >>  sdma_v2_4_enable(adev, true); diff --git
> >> a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> >> b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> >> index e572389089d2..344202870aeb 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> >> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> >> @@ -734,8 +734,6 @@ static int sdma_v3_0_gfx_resume(struct
> amdgpu_device *adev)
> >>   #endif
> >>  /* enable DMA IBs */
> >>  WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i],
> >> ib_cntl);
> >> -
> >> -   ring->sched.ready = true;
> >>  }
> >>
> >>  /* unhalt the MEs */
> >> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> >> b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> >> index 9295ac7edd56..e3581852ed9c 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> >> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> >> @@ -1114,8 +1114,6 @@ static void sdma_v4_0_gfx_resume(struct
> amdgpu_device *adev, unsigned int i)
> >>   #endif
> >>  /* enable DMA IBs */
> >>  WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl);
> >> -
> >> -   ring->sched.ready = true;
> >>   }
> >>
> >>   /**
> >> @@ -1202,8 +1200,6 @@ static void sdma_v4_0_page_resume(struct
> amdgpu_device *adev, unsigned int i)
> >>   #endif
> >>  /* enable DMA IBs */
> >>  WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl);
> >> -
> >> -   ring->sched.ready = true;
> >>   }
> >>
> >>   static void
> >> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
> >> b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
> >> index 64dcaa2670dd..c3517d9fc38c 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
> >> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
> >> @@ -659,8 +659,6 @@ static void sdma_v4_4_2_gfx_resume(struct
> amdgpu_device *adev, unsigned int i)
> >>   #endif
> >>  /* enable DMA IBs */
> >>  WREG32_SDMA(i, regSDMA_GFX_IB_CNTL, ib_cntl);
> >> -
> >> -   ring->sched.ready = true;
> >>   }
> >>
> >>   /**
> >> @@ -750,8 +748,6 @@ static void sdma_v4_4_2_page_resume(struct
> amdgpu_device *adev, unsigned int i)
> >>   #endif
> >>  /* enable DMA IBs */
> >>  WREG32_SDMA(i, regSDMA_PAGE_IB_CNTL, ib_cntl);
> >> -
> >> -   ring->sched.ready = true;
> >>   }
> >>
> >>   static void sdma_v4_4_2

RE: [PATCH 1/2] drm/amd: Disallow s0ix without BIOS support again

[Rafael Ávila de Espíndola]

As far as I know the "no S3 if SMT off" is just an oddity of the
particular BIOS I got on the "B550I AORUS PRO AX".

Also, what has changed that would prevent the same issue I was hitting
before?:

https://gitlab.freedesktop.org/drm/amd/-/issues/2364#note_1735422

Cheers,
Rafael

"Limonciello, Mario"  writes:

> [AMD Official Use Only - General]
>
>> -Original Message-
>> From: Alex Deucher 
>> Sent: Tuesday, May 30, 2023 1:16 PM
>> To: Limonciello, Mario 
>> Cc: amd-gfx@lists.freedesktop.org; Rafael Ávila de Espíndola
>> 
>> Subject: Re: [PATCH 1/2] drm/amd: Disallow s0ix without BIOS support again
>>
>> On Tue, May 30, 2023 at 1:53 PM Mario Limonciello
>>  wrote:
>> >
>> > commit cf488dcd0ab7 ("drm/amd: Allow s0ix without BIOS support")
>> showed
>> > improvements to power consumption over suspend when s0ix wasn't
>> enabled in
>> > BIOS and the system didn't support S3.
>> >
>> > This patch however was misguided because the reason the system didn't
>> > support S3 was because SMT was disabled in OEM BIOS setup.
>> > This prevented the BIOS from allowing S3.
>> >
>> > Also allowing GPUs to use the s2idle path actually causes problems if
>> > they're invoked on systems that may not support s2idle in the platform
>> > firmware. `systemd` has a tendency to try to use `s2idle` if `deep` fails
>> > for any reason, which could lead to unexpected flows.
>> >
>> > To make this the behavior discoverable and expected, revert commit
>> > cf488dcd0ab7 ("drm/amd: Allow s0ix without BIOS support") and offer
>> > a message if SMT appears to be disabled.
>> >
>> > Cc: Rafael Ávila de Espíndola 
>> > Link:
>> https://github.com/torvalds/linux/blob/v6.1/drivers/gpu/drm/amd/amdgpu
>> /amdgpu_acpi.c#L1060
>> > Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/2599
>> > Signed-off-by: Mario Limonciello 
>> > ---
>> >  drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 16 ++--
>> >  1 file changed, 14 insertions(+), 2 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
>> > index 3a6b2e2089f6..a3523d03d769 100644
>> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
>> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
>> > @@ -28,6 +28,7 @@
>> >  #include 
>> >  #include 
>> >  #include 
>> > +#include 
>> >  #include 
>> >  #include 
>> >  #include 
>> > @@ -1473,6 +1474,13 @@ void amdgpu_acpi_release(void)
>> >   */
>> >  bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev)
>> >  {
>> > +#ifdef CONFIG_X86
>> > +   if (!sched_smt_active()) {
>> > +   dev_warn_once(adev->dev,
>> > + "SMT is disabled by the BIOS.\n"
>> > + "To use suspend-to-ram enable SMT in BIOS 
>> > setup.\n");
>> > +   }
>> > +#endif
>>
>> Will this generate a spurious warning on platforms that are natively non-SMT?
>
> Yeah; it could.  I'm not sure how we can reliably detect this.  I thought 
> about looking for
> the 'ht' flag, but that probably wouldn't work for this case.
>
> Are there AMD Zen CPUs or APUs that are non-SMT?  Could gate the 
> sched_smt_active()
> check to only run when it's an AMD x86 Zen SoC.
>
>>
>> Alex
>>
>> > return !(adev->flags & AMD_IS_APU) ||
>> > (pm_suspend_target_state == PM_SUSPEND_MEM);
>> >  }
>> > @@ -1499,16 +1507,20 @@ bool amdgpu_acpi_is_s0ix_active(struct
>> amdgpu_device *adev)
>> >  * S0ix even though the system is suspending to idle, so return 
>> > false
>> >  * in that case.
>> >  */
>> > -   if (!(acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0))
>> > +   if (!(acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0)) {
>> > dev_warn_once(adev->dev,
>> >   "Power consumption will be higher as BIOS 
>> > has not been
>> configured for suspend-to-idle.\n"
>> >   "To use suspend-to-idle change the sleep 
>> > mode in BIOS
>> setup.\n");
>> > +   return false;
>> > +   }
>> >
>> >  #if !IS_ENABLED(CONFIG_AMD_PMC)
>> > dev_warn_once(adev->dev,
>> >   "Power consumption will be higher as the kernel has 
>> > not been
>> compiled with CONFIG_AMD_PMC.\n");
>> > -#endif /* CONFIG_AMD_PMC */
>> > +   return false;
>> > +#else
>> > return true;
>> > +#endif /* CONFIG_AMD_PMC */
>> >  }
>> >
>> >  #endif /* CONFIG_SUSPEND */
>> > --
>> > 2.34.1
>> >

Re: [PATCH][next] drm/amdgpu/discovery: Replace fake flex-arrays with flexible-array members

[Kees Cook]

On Sun, May 28, 2023 at 02:26:37PM -0600, Gustavo A. R. Silva wrote:
> Zero-length and one-element arrays are deprecated, and we are moving
> towards adopting C99 flexible-array members, instead.
> 
> Use the DECLARE_FLEX_ARRAY() helper macro to transform zero-length
> arrays in a union into flexible-array members. And replace a one-element
> array with a C99 flexible-array member.
> 
> Address the following warnings found with GCC-13 and
> -fstrict-flex-arrays=3 enabled:
> drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c:1009:89: warning: array 
> subscript kk is outside array bounds of ‘uint32_t[0]’ {aka ‘unsigned int[]’} 
> [-Warray-bounds=]
> drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c:1007:94: warning: array 
> subscript kk is outside array bounds of ‘uint64_t[0]’ {aka ‘long long 
> unsigned int[]’} [-Warray-bounds=]
> drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c:1310:94: warning: array 
> subscript k is outside array bounds of ‘uint64_t[0]’ {aka ‘long long unsigned 
> int[]’} [-Warray-bounds=]
> drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c:1309:57: warning: array 
> subscript k is outside array bounds of ‘uint32_t[0]’ {aka ‘unsigned int[]’} 
> [-Warray-bounds=]
> 
> This helps with the ongoing efforts to tighten the FORTIFY_SOURCE
> routines on memcpy() and help us make progress towards globally
> enabling -fstrict-flex-arrays=3 [1].
> 
> This results in no differences in binary output.
> 
> Link: https://github.com/KSPP/linux/issues/21
> Link: https://github.com/KSPP/linux/issues/193
> Link: https://github.com/KSPP/linux/issues/300
> Link: https://gcc.gnu.org/pipermail/gcc-patches/2022-October/602902.html [1]
> Signed-off-by: Gustavo A. R. Silva 

Reviewed-by: Kees Cook 

-- 
Kees Cook

[PATCH -next] drm/amdkfd: clean up one inconsistent indenting

[Yang Li]

drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device.c:1036 kgd2kfd_interrupt() 
warn: inconsistent indenting

Signed-off-by: Yang Li 
---
 drivers/gpu/drm/amd/amdkfd/kfd_device.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index 862a50f7b490..0398a8c52a44 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -1033,7 +1033,7 @@ void kgd2kfd_interrupt(struct kfd_dev *kfd, const void 
*ih_ring_entry)
is_patched ? patched_ihre : ih_ring_entry)) {
kfd_queue_work(node->ih_wq, &node->interrupt_work);
spin_unlock_irqrestore(&node->interrupt_lock, flags);
-   return;
+   return;
}
spin_unlock_irqrestore(&node->interrupt_lock, flags);
}
-- 
2.20.1.7.g153144c