[PATCH] drm/amdkfd: to fix cwsr hang issue
From: Ruili Ji Starting from GC_11_0_4, flag trap_en should be enabled for trap handler. Signed-off-by: Ruili Ji Signed-off-by: Aaron Liu Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index 0c1be91a87c6..b695d7a3058c 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -227,7 +227,7 @@ static int add_queue_mes(struct device_queue_manager *dqm, struct queue *q, queue_input.tba_addr = qpd->tba_addr; queue_input.tma_addr = qpd->tma_addr; queue_input.trap_en = KFD_GC_VERSION(q->device) < IP_VERSION(11, 0, 0) || - KFD_GC_VERSION(q->device) >= IP_VERSION(12, 0, 0) || + KFD_GC_VERSION(q->device) > IP_VERSION(11, 0, 3) || q->properties.is_dbg_wa; queue_input.skip_process_ctx_clear = qpd->pqm->process->debug_trap_enabled; @@ -1808,7 +1808,7 @@ static int create_queue_cpsch(struct device_queue_manager *dqm, struct queue *q, q->properties.is_evicted = !!qpd->evicted; q->properties.is_dbg_wa = qpd->pqm->process->debug_trap_enabled && KFD_GC_VERSION(q->device) >= IP_VERSION(11, 0, 0) && - KFD_GC_VERSION(q->device) < IP_VERSION(12, 0, 0); + KFD_GC_VERSION(q->device) <= IP_VERSION(11, 0, 3); if (qd) mqd_mgr->restore_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj, &q->gart_mqd_addr, -- 2.40.1
[PATCH] drm/amdgpu: unmap and remove csa_va properly
Root PD BO should be reserved before unmap and remove
a bo_va from VM otherwise lockdep will complain.
v2: check fpriv->csa_va is not NULL instead of amdgpu_mcbp (christian)
[14616.936827] WARNING: CPU: 6 PID: 1711 at
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1762 amdgpu_vm_bo_del+0x399/0x3f0
[amdgpu]
[14616.937096] Call Trace:
[14616.937097]
[14616.937102] amdgpu_driver_postclose_kms+0x249/0x2f0 [amdgpu]
[14616.937187] drm_file_free+0x1d6/0x300 [drm]
[14616.937207] drm_close_helper.isra.0+0x62/0x70 [drm]
[14616.937220] drm_release+0x5e/0x100 [drm]
[14616.937234] __fput+0x9f/0x280
[14616.937239] fput+0xe/0x20
[14616.937241] task_work_run+0x61/0x90
[14616.937246] exit_to_user_mode_prepare+0x215/0x220
[14616.937251] syscall_exit_to_user_mode+0x2a/0x60
[14616.937254] do_syscall_64+0x48/0x90
[14616.937257] entry_SYSCALL_64_after_hwframe+0x63/0xcd
Signed-off-by: Lang Yu
Acked-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c | 38 +
drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h | 3 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 10 +++
3 files changed, 46 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
index c6d4d41c4393..23d054526e7c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
@@ -106,3 +106,41 @@ int amdgpu_map_static_csa(struct amdgpu_device *adev,
struct amdgpu_vm *vm,
ttm_eu_backoff_reservation(&ticket, &list);
return 0;
}
+
+int amdgpu_unmap_static_csa(struct amdgpu_device *adev, struct amdgpu_vm *vm,
+ struct amdgpu_bo *bo, struct amdgpu_bo_va *bo_va,
+ uint64_t csa_addr)
+{
+ struct ww_acquire_ctx ticket;
+ struct list_head list;
+ struct amdgpu_bo_list_entry pd;
+ struct ttm_validate_buffer csa_tv;
+ int r;
+
+ INIT_LIST_HEAD(&list);
+ INIT_LIST_HEAD(&csa_tv.head);
+ csa_tv.bo = &bo->tbo;
+ csa_tv.num_shared = 1;
+
+ list_add(&csa_tv.head, &list);
+ amdgpu_vm_get_pd_bo(vm, &list, &pd);
+
+ r = ttm_eu_reserve_buffers(&ticket, &list, true, NULL);
+ if (r) {
+ DRM_ERROR("failed to reserve CSA,PD BOs: err=%d\n", r);
+ return r;
+ }
+
+ r = amdgpu_vm_bo_unmap(adev, bo_va, csa_addr);
+ if (r) {
+ DRM_ERROR("failed to do bo_unmap on static CSA, err=%d\n", r);
+ ttm_eu_backoff_reservation(&ticket, &list);
+ return r;
+ }
+
+ amdgpu_vm_bo_del(adev, bo_va);
+
+ ttm_eu_backoff_reservation(&ticket, &list);
+
+ return 0;
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h
index 524b4437a021..7dfc1f2012eb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.h
@@ -34,6 +34,9 @@ int amdgpu_allocate_static_csa(struct amdgpu_device *adev,
struct amdgpu_bo **bo
int amdgpu_map_static_csa(struct amdgpu_device *adev, struct amdgpu_vm *vm,
struct amdgpu_bo *bo, struct amdgpu_bo_va **bo_va,
uint64_t csa_addr, uint32_t size);
+int amdgpu_unmap_static_csa(struct amdgpu_device *adev, struct amdgpu_vm *vm,
+ struct amdgpu_bo *bo, struct amdgpu_bo_va *bo_va,
+ uint64_t csa_addr);
void amdgpu_free_static_csa(struct amdgpu_bo **bo);
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 41d047e5de69..e3531aa3c8bd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -1311,12 +1311,12 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev,
if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL)
amdgpu_vce_free_handles(adev, file_priv);
- if (amdgpu_mcbp) {
- /* TODO: how to handle reserve failure */
- BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true));
- amdgpu_vm_bo_del(adev, fpriv->csa_va);
+ if (fpriv->csa_va) {
+ uint64_t csa_addr = amdgpu_csa_vaddr(adev) &
AMDGPU_GMC_HOLE_MASK;
+
+ WARN_ON(amdgpu_unmap_static_csa(adev, &fpriv->vm,
adev->virt.csa_obj,
+ fpriv->csa_va, csa_addr));
fpriv->csa_va = NULL;
- amdgpu_bo_unreserve(adev->virt.csa_obj);
}
pasid = fpriv->vm.pasid;
--
2.25.1
[PATCH 1/3] drm/amd/pm: fix vclk setting failed for SMU v13.0.4
PMFW use the left-shifted 16 bits argument to set the VCLK
DPM frequency for SMU v13.0.4.
Signed-off-by: Tim Huang
---
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h | 2 ++
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c | 11 +--
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
index 5a99a091965e..6a0ac0bbaace 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
@@ -51,6 +51,8 @@
#define CTF_OFFSET_HOTSPOT 5
#define CTF_OFFSET_MEM 5
+#define SMU_13_VCLK_SHIFT 16
+
extern const int pmfw_decoded_link_speed[5];
extern const int pmfw_decoded_link_width[7];
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
index 46a8a366f287..999b07db862e 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
@@ -831,6 +831,8 @@ static int smu_v13_0_4_set_soft_freq_limited_range(struct
smu_context *smu,
uint32_t max)
{
enum smu_message_type msg_set_min, msg_set_max;
+ uint32_t min_clk = min;
+ uint32_t max_clk = max;
int ret = 0;
if (!smu_v13_0_4_clk_dpm_is_enabled(smu, clk_type))
@@ -859,12 +861,17 @@ static int smu_v13_0_4_set_soft_freq_limited_range(struct
smu_context *smu,
return -EINVAL;
}
- ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_min, min, NULL);
+ if (clk_type == SMU_VCLK) {
+ min_clk = min << SMU_13_VCLK_SHIFT;
+ max_clk = max << SMU_13_VCLK_SHIFT;
+ }
+
+ ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_min, min_clk, NULL);
if (ret)
return ret;
return smu_cmn_send_smc_msg_with_param(smu, msg_set_max,
- max, NULL);
+ max_clk, NULL);
}
static int smu_v13_0_4_force_clk_levels(struct smu_context *smu,
--
2.34.1
[PATCH 3/3] drm/amd/pm: enable more Pstates profile levels for SMU v13.0.4
This patch enables following UMD stable Pstates profile
levels for power_dpm_force_performance_level interface.
- profile_peak
- profile_min_mclk
- profile_min_sclk
- profile_standard
Signed-off-by: Tim Huang
---
.../drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c | 54 ++-
1 file changed, 53 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
index 315a6d8bde2e..ef37dda9908f 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
@@ -54,6 +54,10 @@
#define FEATURE_MASK(feature) (1ULL << feature)
+#define SMU_13_0_4_UMD_PSTATE_GFXCLK 938
+#define SMU_13_0_4_UMD_PSTATE_SOCCLK 938
+#define SMU_13_0_4_UMD_PSTATE_FCLK 1875
+
#define SMC_DPM_FEATURE ( \
FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \
FEATURE_MASK(FEATURE_VCN_DPM_BIT)| \
@@ -908,6 +912,50 @@ static int smu_v13_0_4_force_clk_levels(struct smu_context
*smu,
return ret;
}
+static int smu_v13_0_4_get_dpm_profile_freq(struct smu_context *smu,
+ enum amd_dpm_forced_level level,
+ enum smu_clk_type clk_type,
+ uint32_t *min_clk,
+ uint32_t *max_clk)
+{
+ int ret = 0;
+ uint32_t clk_limit = 0;
+
+ switch (clk_type) {
+ case SMU_GFXCLK:
+ case SMU_SCLK:
+ clk_limit = SMU_13_0_4_UMD_PSTATE_GFXCLK;
+ if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
+ smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL,
&clk_limit);
+ else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK)
+ smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SCLK,
&clk_limit, NULL);
+ break;
+ case SMU_SOCCLK:
+ clk_limit = SMU_13_0_4_UMD_PSTATE_SOCCLK;
+ if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
+ smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SOCCLK,
NULL, &clk_limit);
+ break;
+ case SMU_FCLK:
+ clk_limit = SMU_13_0_4_UMD_PSTATE_FCLK;
+ if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
+ smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL,
&clk_limit);
+ else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK)
+ smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_FCLK,
&clk_limit, NULL);
+ break;
+ case SMU_VCLK:
+ smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL,
&clk_limit);
+ break;
+ case SMU_DCLK:
+ smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL,
&clk_limit);
+ break;
+ default:
+ ret = -EINVAL;
+ break;
+ }
+ *min_clk = *max_clk = clk_limit;
+ return ret;
+}
+
static int smu_v13_0_4_set_performance_level(struct smu_context *smu,
enum amd_dpm_forced_level level)
{
@@ -955,7 +1003,11 @@ static int smu_v13_0_4_set_performance_level(struct
smu_context *smu,
case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
- /* Temporarily do nothing since the optimal clocks haven't been
provided yet */
+ smu_v13_0_4_get_dpm_profile_freq(smu, level, SMU_SCLK,
&sclk_min, &sclk_max);
+ smu_v13_0_4_get_dpm_profile_freq(smu, level, SMU_FCLK,
&fclk_min, &fclk_max);
+ smu_v13_0_4_get_dpm_profile_freq(smu, level, SMU_SOCCLK,
&socclk_min, &socclk_max);
+ smu_v13_0_4_get_dpm_profile_freq(smu, level, SMU_VCLK,
&vclk_min, &vclk_max);
+ smu_v13_0_4_get_dpm_profile_freq(smu, level, SMU_DCLK,
&dclk_min, &dclk_max);
break;
case AMD_DPM_FORCED_LEVEL_MANUAL:
case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
--
2.34.1
[PATCH 2/3] drm/amd/pm: enable vclk and dclk Pstates for SMU v13.0.4
Add the ability to control the vclk and dclk frequency by
power_dpm_force_performance_level interface.
Signed-off-by: Tim Huang
---
.../drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c | 29 +++
1 file changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
index 999b07db862e..315a6d8bde2e 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
@@ -915,6 +915,8 @@ static int smu_v13_0_4_set_performance_level(struct
smu_context *smu,
uint32_t sclk_min = 0, sclk_max = 0;
uint32_t fclk_min = 0, fclk_max = 0;
uint32_t socclk_min = 0, socclk_max = 0;
+ uint32_t vclk_min = 0, vclk_max = 0;
+ uint32_t dclk_min = 0, dclk_max = 0;
int ret = 0;
switch (level) {
@@ -922,22 +924,32 @@ static int smu_v13_0_4_set_performance_level(struct
smu_context *smu,
smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL,
&sclk_max);
smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL,
&fclk_max);
smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL,
&socclk_max);
+ smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL,
&vclk_max);
+ smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL,
&dclk_max);
sclk_min = sclk_max;
fclk_min = fclk_max;
socclk_min = socclk_max;
+ vclk_min = vclk_max;
+ dclk_min = dclk_max;
break;
case AMD_DPM_FORCED_LEVEL_LOW:
smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min,
NULL);
smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_FCLK, &fclk_min,
NULL);
smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SOCCLK, &socclk_min,
NULL);
+ smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_VCLK, &vclk_min,
NULL);
+ smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_DCLK, &dclk_min,
NULL);
sclk_max = sclk_min;
fclk_max = fclk_min;
socclk_max = socclk_min;
+ vclk_max = vclk_min;
+ dclk_max = dclk_min;
break;
case AMD_DPM_FORCED_LEVEL_AUTO:
smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min,
&sclk_max);
smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_FCLK, &fclk_min,
&fclk_max);
smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SOCCLK, &socclk_min,
&socclk_max);
+ smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_VCLK, &vclk_min,
&vclk_max);
+ smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_DCLK, &dclk_min,
&dclk_max);
break;
case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
@@ -983,6 +995,23 @@ static int smu_v13_0_4_set_performance_level(struct
smu_context *smu,
return ret;
}
+ if (vclk_min && vclk_max) {
+ ret = smu_v13_0_4_set_soft_freq_limited_range(smu,
+ SMU_VCLK,
+ vclk_min,
+ vclk_max);
+ if (ret)
+ return ret;
+ }
+
+ if (dclk_min && dclk_max) {
+ ret = smu_v13_0_4_set_soft_freq_limited_range(smu,
+ SMU_DCLK,
+ dclk_min,
+ dclk_max);
+ if (ret)
+ return ret;
+ }
return ret;
}
--
2.34.1
RE: [PATCH] drm/amdgpu: display/Kconfig: replace leading spaces with tab
[Public] It's https://gitlab.freedesktop.org/agd5f/linux/-/tree/amd-staging-drm-next?ref_type=heads. Latest patches including yours's will be pushed to this branch after a while. Regards, Guchun > -Original Message- > From: amd-gfx On Behalf Of Sui > Jingfeng > Sent: Wednesday, June 7, 2023 2:34 PM > To: Alex Deucher > Cc: Li, Sun peng (Leo) ; David Airlie > ; Pan, Xinhui ; Siqueira, Rodrigo > ; linux-ker...@vger.kernel.org; dri- > de...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org; Daniel Vetter > ; Deucher, Alexander ; > Wentland, Harry ; Koenig, Christian > > Subject: Re: [PATCH] drm/amdgpu: display/Kconfig: replace leading spaces > with tab > > https://cgit.freedesktop.org/amd/drm-amd/ > > > This one has a long time with no update. > > > On 2023/6/7 14:31, Sui Jingfeng wrote: > > Hi, > > > > On 2023/6/7 03:15, Alex Deucher wrote: > >> Applied. Thanks! > > > > Where is the official branch of drm/amdgpu, I can't find it on the > > internet. > > > > Sorry for asking this silly question. > > > > >> Alex > >> > >> On Tue, Jun 6, 2023 at 9:33 AM Sui Jingfeng > >> wrote: > >>> This patch replace the leading spaces with tab, make them keep > >>> aligned with the rest of the config options. No functional change. > >>> > >>> Signed-off-by: Sui Jingfeng > >>> --- > >>> drivers/gpu/drm/amd/display/Kconfig | 17 +++-- > >>> 1 file changed, 7 insertions(+), 10 deletions(-) > >>> > >>> diff --git a/drivers/gpu/drm/amd/display/Kconfig > >>> b/drivers/gpu/drm/amd/display/Kconfig > >>> index 2d8e55e29637..04ccfc70d583 100644 > >>> --- a/drivers/gpu/drm/amd/display/Kconfig > >>> +++ b/drivers/gpu/drm/amd/display/Kconfig > >>> @@ -42,16 +42,13 @@ config DEBUG_KERNEL_DC > >>>Choose this option if you want to hit kdgb_break in assert. > >>> > >>> config DRM_AMD_SECURE_DISPLAY > >>> -bool "Enable secure display support" > >>> -depends on DEBUG_FS > >>> -depends on DRM_AMD_DC_FP > >>> -help > >>> -Choose this option if you want to > >>> -support secure display > >>> - > >>> -This option enables the calculation > >>> -of crc of specific region via debugfs. > >>> -Cooperate with specific DMCU FW. > >>> + bool "Enable secure display support" > >>> + depends on DEBUG_FS > >>> + depends on DRM_AMD_DC_FP > >>> + help > >>> + Choose this option if you want to support secure display > >>> > >>> + This option enables the calculation of crc of specific > >>> region via > >>> + debugfs. Cooperate with specific DMCU FW. > >>> > >>> endmenu > >>> -- > >>> 2.25.1 > >>> > -- > Jingfeng
RE: [PATCH 1/3] drm/amdgpu: add cached GPU fault structure to vm struct
[Public]
3 nitpick comments.
> -Original Message-
> From: amd-gfx On Behalf Of Alex
> Deucher
> Sent: Friday, May 26, 2023 12:52 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ;
> samuel.pitoi...@gmail.com
> Subject: [PATCH 1/3] drm/amdgpu: add cached GPU fault structure to vm
> struct
>
> When we get a GPU pge fault, cache the fault for later analysis.
A spelling typo, s/pge/page
> Cc: samuel.pitoi...@gmail.com
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 31
> ++
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 18 +++
> 2 files changed, 49 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index 22f9a65ca0fc..73e022f3daa4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -2631,3 +2631,34 @@ void amdgpu_debugfs_vm_bo_info(struct
> amdgpu_vm *vm, struct seq_file *m)
> total_done_objs);
> }
> #endif
> +
> +/**
> + * amdgpu_vm_update_fault_cache - update cached fault into.
> + * @adev: amdgpu device pointer
> + * @pasid: PASID of the VM
> + * @addr: Address of the fault
> + * @status: fault status register
I guess this 'status' means the status from fault status register.
> + * @vmhub: which vmhub got the fault
> + *
> + * Cache the fault info for later use by userspace in debuggging.
A spelling typo, s/debuggging/debugging.
Regards,
Guchun
> + */
> +void amdgpu_vm_update_fault_cache(struct amdgpu_device *adev,
> + unsigned int pasid,
> + uint64_t addr,
> + uint32_t status,
> + unsigned int vmhub)
> +{
> + struct amdgpu_vm *vm;
> + unsigned long flags;
> +
> + xa_lock_irqsave(&adev->vm_manager.pasids, flags);
> +
> + vm = xa_load(&adev->vm_manager.pasids, pasid);
> + if (vm) {
> + vm->fault_info.addr = addr;
> + vm->fault_info.status = status;
> + vm->fault_info.vmhub = vmhub;
> + }
> + xa_unlock_irqrestore(&adev->vm_manager.pasids, flags); }
> +
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> index 14f9a2bf3acb..fb66a413110c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> @@ -244,6 +244,15 @@ struct amdgpu_vm_update_funcs {
> struct dma_fence **fence);
> };
>
> +struct amdgpu_vm_fault_info {
> + /* fault address */
> + uint64_taddr;
> + /* fault status register */
> + uint32_tstatus;
> + /* which vmhub? gfxhub, mmhub, etc. */
> + unsigned intvmhub;
> +};
> +
> struct amdgpu_vm {
> /* tree of virtual addresses mapped */
> struct rb_root_cached va;
> @@ -332,6 +341,9 @@ struct amdgpu_vm {
>
> /* Memory partition number, -1 means any partition */
> int8_t mem_id;
> +
> + /* cached fault info */
> + struct amdgpu_vm_fault_info fault_info;
> };
>
> struct amdgpu_vm_manager {
> @@ -540,4 +552,10 @@ static inline void
> amdgpu_vm_eviction_unlock(struct amdgpu_vm *vm)
> mutex_unlock(&vm->eviction_lock);
> }
>
> +void amdgpu_vm_update_fault_cache(struct amdgpu_device *adev,
> + unsigned int pasid,
> + uint64_t addr,
> + uint32_t status,
> + unsigned int vmhub);
> +
> #endif
> --
> 2.40.1
RE: [PATCH 0/3] Add GPU page fault query interface
[Public] With the 3 nitpicks fixed in patch 1, the series are: Acked-by: Guchun Chen Regards, Guchun > -Original Message- > From: amd-gfx On Behalf Of Alex > Deucher > Sent: Tuesday, June 6, 2023 11:40 PM > To: Deucher, Alexander > Cc: samuel.pitoi...@gmail.com; amd-gfx@lists.freedesktop.org > Subject: Re: [PATCH 0/3] Add GPU page fault query interface > > Ping on this series? > > Alex > > On Thu, May 25, 2023 at 12:52 PM Alex Deucher > wrote: > > > > This patch set adds support for an application to query GPU page > > faults. It's useful for debugging and there are vulkan extensions > > that could make use of this. Preliminary user space code which uses > > this can be found here: > > https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23238 > > https://gitlab.freedesktop.org/mesa/drm/-/merge_requests/298 > > > > Note, that I made a small change to the vmhub definition to decouple > > it from how the kernel tracks vmhubs so that we have a consistent user > > view even if we decide to add more vmhubs like we recently did for gfx > > 9.4.3. > > > > I've also pushed the changed to: > > https://gitlab.freedesktop.org/agd5f/linux/-/commits/gpu_fault_info_io > > ctl > > > > > > Alex Deucher (3): > > drm/amdgpu: add cached GPU fault structure to vm struct > > drm/amdgpu: cache gpuvm fault information for gmc7+ > > drm/amdgpu: add new INFO ioctl query for the last GPU page fault > > > > drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 +- > > drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 16 + > > drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 45 > + > > drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 31 +++-- > > drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 3 ++ > > drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 3 ++ > > drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 3 ++ > > drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 3 ++ > > drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 11 +++--- > > include/uapi/drm/amdgpu_drm.h | 16 + > > 10 files changed, 126 insertions(+), 8 deletions(-) > > > > -- > > 2.40.1 > >
Re: [PATCH v5 04/13] drm/connector: Use common colorspace_names array
On Tuesday, June 6th, 2023 at 22:25, Harry Wentland wrote: > We an use bitfields to track the support ones for HDMI Typo: "We can"
Re: [PATCH v5 06/13] drm/connector: Allow drivers to pass list of supported colorspaces
On Tuesday, June 6th, 2023 at 22:26, Harry Wentland
wrote:
> -int drm_mode_create_hdmi_colorspace_property(struct drm_connector *connector)
> +int drm_mode_create_hdmi_colorspace_property(struct drm_connector *connector,
> + u32 supported_colorspaces)
> {
> - return drm_mode_create_colorspace_property(connector, hdmi_colorspaces);
> + u32 colorspaces = supported_colorspaces & hdmi_colorspaces;
This creates a potentially weird situation where the driver passes a
non-0 supported_colorspaces, but the intersection with hdmi_colorspaces
ends up being empty, and all colorspaces end up being advertised.
Re: PROBLEM: AMD Ryzen 9 7950X iGPU - Blinking Issue
Hi Guys, so I checked, the kernel I am running has this commit (https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git /commit/?id=08da182175db4c7f80850354849d95f2670e8cd9) applied already! https://github.com/ju6ge/linux/commit/917680e6056aa288cac288d3afd2745d372beb61u And the bug of display flickering persists with or without the amdgpu.sg_display=0 variable applied! Kind regards, Felix Richter On 6/5/23 16:11, Alex Deucher wrote: + Hamza This is a known issue. You can workaround it by setting amdgpu.sg_display=0. It should be issue should be fixed in: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=08da182175db4c7f80850354849d95f2670e8cd9 Alex Now if this is the desired long term fix I do not know … Kind regards, Felix Richter On 02.05.23 16:12, Linux regression tracking (Thorsten Leemhuis) wrote: On 02.05.23 15:48, Felix Richter wrote: On 5/2/23 15:34, Linux regression tracking (Thorsten Leemhuis) wrote: On 02.05.23 15:13, Alex Deucher wrote: On Tue, May 2, 2023 at 7:45 AM Linux regression tracking (Thorsten Leemhuis) wrote: On 30.04.23 13:44, Felix Richter wrote: Hi, I am running into an issue with the integrated GPU of the Ryzen 9 7950X. It seems to be a regression from kernel version 6.1 to 6.2. The bug materializes in from of my monitor blinking, meaning it turns full white shortly. This happens very often so that the system becomes unpleasant to use. I am running the Archlinux Kernel: The Issue happens on the bleeding edge kernel: 6.2.13 Switching back to the LTS kernel resolves the issue: 6.1.26 I have two monitors attached to the system. One 42 inch 4k Display and a 24 inch 1080p Display and am running sway as my desktop. Let me know if there is more information I could provide to help narrow down the issue. Thanks for the report. To be sure the issue doesn't fall through the cracks unnoticed, I'm adding it to regzbot, the Linux kernel regression tracking bot: #regzbot ^introduced v6.1..v6.2 #regzbot title drm: amdgpu: system becomes unpleasant to use after monitor starts blinking and turns full white #regzbot ignore-activity This isn't a regression? This issue or a fix for it are already discussed somewhere else? It was fixed already? You want to clarify when the regression started to happen? Or point out I got the title or something else totally wrong? Then just reply and tell me -- ideally while also telling regzbot about it, as explained by the page listed in the footer of this mail. Developers: When fixing the issue, remember to add 'Link:' tags pointing to the report (the parent of this mail). See page linked in footer for details. This sounds exactly like the issue that was fixed in this patch which is already on it's way to Linus: https://gitlab.freedesktop.org/agd5f/linux/-/commit/08da182175db4c7f80850354849d95f2670e8cd9 FWIW, you in the flood of emails likely missed that this is the same thread where you yesterday replied "If the module parameter didn't help then perhaps you are seeing some other issue. Can you bisect?". That's why I decided to add this to the tracking. Or am I missing something obvious here? /me looks around again and can't see anything, but that doesn't have to mean anything... Felix, btw, this guide might help you with the bisection, even if it's just for kernel compilation: https://docs.kernel.org/next/admin-guide/quickly-build-trimmed-linux.html And to indirectly reply to your mail from yesterday[1]. You might want to ignore the arch linux kernel git repo and just do a bisection between 6.1 and the latest 6.2.y kernel using upstream repos; and if I were you I'd also try 6.3 or even mainline before that, in case the issue was fixed already. [1] https://lore.kernel.org/all/04749ee4-0728-92fe-bcb0-a7320279e...@felixrichter.tech/ Thanks for the pointers, I'll do a bisection on my desktop from 6.1 to the newest commit. FWIW, I wonder what you actually mean with "newest commit" here: a bisection between 6.1 and mainline HEAD might be a waste of time, *if* this is something that only happens in 6.2.y (say due to a broken or incomplete backport) That was the part I was mostly unsure about … where to start from. I was planning to use PKGBUILD scripts from arch to achieve the same configuration as I would when installing the package and just rewrite the script to use a local copy of the source code instead of the repository. That way I can just use the bisect command, rebuild the package and test again. In my experience trying to deal with Linux distro's package managers creates more trouble than it's worth. But I probably won't be able to finish it this week, since I am on vacation starting tomorrow and will not have access to the computer in question. I will be back next week, by that time the patch Alex is talking about might already be in mainline. So if that fixes it, I will notice and let you know. If not I will do the bisection to figure out what the actual issue is. Enjoy
Re: [PATCH v5 04/13] drm/connector: Use common colorspace_names array
On Tuesday, June 6th, 2023 at 22:25, Harry Wentland wrote: > + if (supported_colorspaces != 0 && (colorspaces & BIT(i)) == 0) This patch actually also introduces a change in behavior: passing no colorspace will make the function advertise all colorspaces. I have a hard time understanding how this can be useful: we want to either advertise all DP colorspaces, or all HDMI colorspaces, but not both? One way to fix this would be to handle the "zero means everything" behavior in the specific DP/HDMI callers. But I wonder, is it really worth the magic if we can expose a simple const variable with all DP/HDMI colorspaces?
Re: [PATCH] drm/amdgpu: display/Kconfig: replace leading spaces with tab
Hi, On 2023/6/7 17:09, Chen, Guchun wrote: [Public] It's https://gitlab.freedesktop.org/agd5f/linux/-/tree/amd-staging-drm-next?ref_type=heads. Latest patches including yours's will be pushed to this branch after a while. Now I know, thanks for your kindness reply. Regards, Guchun -Original Message- From: amd-gfx On Behalf Of Sui Jingfeng Sent: Wednesday, June 7, 2023 2:34 PM To: Alex Deucher Cc: Li, Sun peng (Leo) ; David Airlie ; Pan, Xinhui ; Siqueira, Rodrigo ; linux-ker...@vger.kernel.org; dri- de...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org; Daniel Vetter ; Deucher, Alexander ; Wentland, Harry ; Koenig, Christian Subject: Re: [PATCH] drm/amdgpu: display/Kconfig: replace leading spaces with tab https://cgit.freedesktop.org/amd/drm-amd/ This one has a long time with no update. On 2023/6/7 14:31, Sui Jingfeng wrote: Hi, On 2023/6/7 03:15, Alex Deucher wrote: Applied. Thanks! Where is the official branch of drm/amdgpu, I can't find it on the internet. Sorry for asking this silly question. Alex On Tue, Jun 6, 2023 at 9:33 AM Sui Jingfeng wrote: This patch replace the leading spaces with tab, make them keep aligned with the rest of the config options. No functional change. Signed-off-by: Sui Jingfeng --- drivers/gpu/drm/amd/display/Kconfig | 17 +++-- 1 file changed, 7 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/display/Kconfig index 2d8e55e29637..04ccfc70d583 100644 --- a/drivers/gpu/drm/amd/display/Kconfig +++ b/drivers/gpu/drm/amd/display/Kconfig @@ -42,16 +42,13 @@ config DEBUG_KERNEL_DC Choose this option if you want to hit kdgb_break in assert. config DRM_AMD_SECURE_DISPLAY -bool "Enable secure display support" -depends on DEBUG_FS -depends on DRM_AMD_DC_FP -help -Choose this option if you want to -support secure display - -This option enables the calculation -of crc of specific region via debugfs. -Cooperate with specific DMCU FW. + bool "Enable secure display support" + depends on DEBUG_FS + depends on DRM_AMD_DC_FP + help + Choose this option if you want to support secure display + This option enables the calculation of crc of specific region via + debugfs. Cooperate with specific DMCU FW. endmenu -- 2.25.1 -- Jingfeng -- Jingfeng
[PATCH v2 06/07] drm/amdgpu: add option params to enforce process isolation between graphics and compute
enforce process isolation between graphics and compute via using the same
reserved vmid.
v2: remove params "struct amdgpu_vm *vm" from
amdgpu_vmid_alloc_reserved and amdgpu_vmid_free_reserved.
Signed-off-by: Chong Li
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 10 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c | 17 +++--
drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h | 6 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 22 +-
5 files changed, 36 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index ce196badf42d..ef098a7287d0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -215,6 +215,7 @@ extern int amdgpu_force_asic_type;
extern int amdgpu_smartshift_bias;
extern int amdgpu_use_xgmi_p2p;
extern int amdgpu_mtype_local;
+extern bool enforce_isolation;
#ifdef CONFIG_HSA_AMD
extern int sched_policy;
extern bool debug_evictions;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 3d91e123f9bd..fdb6fb8229ab 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -153,7 +153,7 @@ uint amdgpu_pg_mask = 0x;
uint amdgpu_sdma_phase_quantum = 32;
char *amdgpu_disable_cu;
char *amdgpu_virtual_display;
-
+bool enforce_isolation;
/*
* OverDrive(bit 14) disabled by default
* GFX DCS(bit 19) disabled by default
@@ -973,6 +973,14 @@ MODULE_PARM_DESC(
4 =
AMDGPU_CPX_PARTITION_MODE)");
module_param_named(user_partt_mode, amdgpu_user_partt_mode, uint, 0444);
+
+/**
+ * DOC: enforce_isolation (bool)
+ * enforce process isolation between graphics and compute via using the same
reserved vmid.
+ */
+module_param(enforce_isolation, bool, 0444);
+MODULE_PARM_DESC(enforce_isolation, "enforce process isolation between
graphics and compute . enforce_isolation = on");
+
/* These devices are not supported by amdgpu.
* They are supported by the mach64, r128, radeon drivers
*/
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
index c991ca0b7a1c..ff1ea99292fb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
@@ -409,7 +409,7 @@ int amdgpu_vmid_grab(struct amdgpu_vm *vm, struct
amdgpu_ring *ring,
if (r || !idle)
goto error;
- if (vm->reserved_vmid[vmhub]) {
+ if (vm->reserved_vmid[vmhub] || (enforce_isolation && (vmhub ==
AMDGPU_GFXHUB(0 {
r = amdgpu_vmid_grab_reserved(vm, ring, job, &id, fence);
if (r || !id)
goto error;
@@ -460,14 +460,11 @@ int amdgpu_vmid_grab(struct amdgpu_vm *vm, struct
amdgpu_ring *ring,
}
int amdgpu_vmid_alloc_reserved(struct amdgpu_device *adev,
- struct amdgpu_vm *vm,
unsigned vmhub)
{
struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
mutex_lock(&id_mgr->lock);
- if (vm->reserved_vmid[vmhub])
- goto unlock;
++id_mgr->reserved_use_count;
if (!id_mgr->reserved) {
@@ -479,27 +476,23 @@ int amdgpu_vmid_alloc_reserved(struct amdgpu_device *adev,
list_del_init(&id->list);
id_mgr->reserved = id;
}
- vm->reserved_vmid[vmhub] = true;
-unlock:
mutex_unlock(&id_mgr->lock);
return 0;
}
void amdgpu_vmid_free_reserved(struct amdgpu_device *adev,
- struct amdgpu_vm *vm,
unsigned vmhub)
{
struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
mutex_lock(&id_mgr->lock);
- if (vm->reserved_vmid[vmhub] &&
- !--id_mgr->reserved_use_count) {
+ if (!--id_mgr->reserved_use_count) {
/* give the reserved ID back to normal round robin */
list_add(&id_mgr->reserved->list, &id_mgr->ids_lru);
id_mgr->reserved = NULL;
}
- vm->reserved_vmid[vmhub] = false;
+
mutex_unlock(&id_mgr->lock);
}
@@ -578,6 +571,10 @@ void amdgpu_vmid_mgr_init(struct amdgpu_device *adev)
list_add_tail(&id_mgr->ids[j].list, &id_mgr->ids_lru);
}
}
+ /* alloc a default reserved vmid to enforce isolation */
+ if (enforce_isolation)
+ amdgpu_vmid_alloc_reserved(adev, AMDGPU_GFXHUB(0));
+
}
/**
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h
index d1cc09b45da4..68add23dc87c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h
@@ -79,11 +79,9 @@ void amdgpu_pasid_free_delayed(struct dma_resv *resv,
bool amdgpu_vmid_had_gpu_reset(struct amdgpu_device *ade
[PATCH] drm/amd/pm: enable more Pstates profile levels for yellow_carp
This patch enables following UMD stable Pstates profile levels for
power_dpm_force_performance_level interface.
- profile_peak
- profile_min_mclk
- profile_min_sclk
- profile_standard
Signed-off-by: shikaguo
---
.../drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c | 94 ++-
.../drm/amd/pm/swsmu/smu13/yellow_carp_ppt.h | 8 +-
2 files changed, 98 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
index a92da336ecec..5c968ab2ea8d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
@@ -957,6 +957,9 @@ static int yellow_carp_set_soft_freq_limited_range(struct
smu_context *smu,
uint32_t max)
{
enum smu_message_type msg_set_min, msg_set_max;
+ uint32_t min_clk = min;
+ uint32_t max_clk = max;
+
int ret = 0;
if (!yellow_carp_clk_dpm_is_enabled(smu, clk_type))
@@ -985,11 +988,17 @@ static int yellow_carp_set_soft_freq_limited_range(struct
smu_context *smu,
return -EINVAL;
}
- ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_min, min, NULL);
+ if (clk_type == SMU_VCLK) {
+ min_clk = min << SMU_13_VCLK_SHIFT;
+ max_clk = max << SMU_13_VCLK_SHIFT;
+ }
+
+ ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_min, min_clk, NULL);
+
if (ret)
goto out;
- ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_max, max, NULL);
+ ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_max, max_clk, NULL);
if (ret)
goto out;
@@ -1107,6 +1116,50 @@ static int yellow_carp_force_clk_levels(struct
smu_context *smu,
return ret;
}
+static int yellow_carp_get_dpm_profile_freq(struct smu_context *smu,
+ enum amd_dpm_forced_level level,
+ enum smu_clk_type clk_type,
+ uint32_t *min_clk,
+ uint32_t *max_clk)
+{
+ int ret = 0;
+ uint32_t clk_limit = 0;
+
+ switch (clk_type) {
+ case SMU_GFXCLK:
+ case SMU_SCLK:
+ clk_limit = YELLOW_CARP_UMD_PSTATE_GFXCLK;
+ if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
+ yellow_carp_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL,
&clk_limit);
+ else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK)
+ yellow_carp_get_dpm_ultimate_freq(smu, SMU_SCLK,
&clk_limit, NULL);
+ break;
+ case SMU_SOCCLK:
+ clk_limit = YELLOW_CARP_UMD_PSTATE_SOCCLK;
+ if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
+ yellow_carp_get_dpm_ultimate_freq(smu, SMU_SOCCLK,
NULL, &clk_limit);
+ break;
+ case SMU_FCLK:
+ clk_limit = YELLOW_CARP_UMD_PSTATE_FCLK;
+ if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
+ yellow_carp_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL,
&clk_limit);
+ else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK)
+ yellow_carp_get_dpm_ultimate_freq(smu, SMU_FCLK,
&clk_limit, NULL);
+ break;
+ case SMU_VCLK:
+ yellow_carp_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL,
&clk_limit);
+ break;
+ case SMU_DCLK:
+ yellow_carp_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL,
&clk_limit);
+ break;
+ default:
+ ret = -EINVAL;
+ break;
+ }
+ *min_clk = *max_clk = clk_limit;
+ return ret;
+}
+
static int yellow_carp_set_performance_level(struct smu_context *smu,
enum amd_dpm_forced_level level)
{
@@ -1114,6 +1167,9 @@ static int yellow_carp_set_performance_level(struct
smu_context *smu,
uint32_t sclk_min = 0, sclk_max = 0;
uint32_t fclk_min = 0, fclk_max = 0;
uint32_t socclk_min = 0, socclk_max = 0;
+ uint32_t vclk_min = 0, vclk_max = 0;
+ uint32_t dclk_min = 0, dclk_max = 0;
+
int ret = 0;
switch (level) {
@@ -1121,28 +1177,42 @@ static int yellow_carp_set_performance_level(struct
smu_context *smu,
yellow_carp_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL,
&sclk_max);
yellow_carp_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL,
&fclk_max);
yellow_carp_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL,
&socclk_max);
+ yellow_carp_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL,
&vclk_max);
+ yellow_carp_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL,
&dclk_max);
sclk_min = sclk_max;
fclk_min = fclk_max;
socclk_min = socclk_max;
+
Re: [PATCH v2 06/07] drm/amdgpu: add option params to enforce process isolation between graphics and compute
Am 07.06.23 um 12:57 schrieb Chong Li:
enforce process isolation between graphics and compute via using the same
reserved vmid.
v2: remove params "struct amdgpu_vm *vm" from
amdgpu_vmid_alloc_reserved and amdgpu_vmid_free_reserved.
Signed-off-by: Chong Li
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 10 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c | 17 +++--
drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h | 6 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 22 +-
5 files changed, 36 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index ce196badf42d..ef098a7287d0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -215,6 +215,7 @@ extern int amdgpu_force_asic_type;
extern int amdgpu_smartshift_bias;
extern int amdgpu_use_xgmi_p2p;
extern int amdgpu_mtype_local;
+extern bool enforce_isolation;
#ifdef CONFIG_HSA_AMD
extern int sched_policy;
extern bool debug_evictions;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 3d91e123f9bd..fdb6fb8229ab 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -153,7 +153,7 @@ uint amdgpu_pg_mask = 0x;
uint amdgpu_sdma_phase_quantum = 32;
char *amdgpu_disable_cu;
char *amdgpu_virtual_display;
-
+bool enforce_isolation;
/*
* OverDrive(bit 14) disabled by default
* GFX DCS(bit 19) disabled by default
@@ -973,6 +973,14 @@ MODULE_PARM_DESC(
4 =
AMDGPU_CPX_PARTITION_MODE)");
module_param_named(user_partt_mode, amdgpu_user_partt_mode, uint, 0444);
+
+/**
+ * DOC: enforce_isolation (bool)
+ * enforce process isolation between graphics and compute via using the same
reserved vmid.
+ */
+module_param(enforce_isolation, bool, 0444);
+MODULE_PARM_DESC(enforce_isolation, "enforce process isolation between graphics and
compute . enforce_isolation = on");
+
/* These devices are not supported by amdgpu.
* They are supported by the mach64, r128, radeon drivers
*/
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
index c991ca0b7a1c..ff1ea99292fb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
@@ -409,7 +409,7 @@ int amdgpu_vmid_grab(struct amdgpu_vm *vm, struct
amdgpu_ring *ring,
if (r || !idle)
goto error;
- if (vm->reserved_vmid[vmhub]) {
+ if (vm->reserved_vmid[vmhub] || (enforce_isolation && (vmhub ==
AMDGPU_GFXHUB(0 {
r = amdgpu_vmid_grab_reserved(vm, ring, job, &id, fence);
if (r || !id)
goto error;
@@ -460,14 +460,11 @@ int amdgpu_vmid_grab(struct amdgpu_vm *vm, struct
amdgpu_ring *ring,
}
int amdgpu_vmid_alloc_reserved(struct amdgpu_device *adev,
- struct amdgpu_vm *vm,
unsigned vmhub)
{
struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
mutex_lock(&id_mgr->lock);
- if (vm->reserved_vmid[vmhub])
- goto unlock;
++id_mgr->reserved_use_count;
if (!id_mgr->reserved) {
@@ -479,27 +476,23 @@ int amdgpu_vmid_alloc_reserved(struct amdgpu_device *adev,
list_del_init(&id->list);
id_mgr->reserved = id;
}
- vm->reserved_vmid[vmhub] = true;
-unlock:
mutex_unlock(&id_mgr->lock);
return 0;
}
void amdgpu_vmid_free_reserved(struct amdgpu_device *adev,
- struct amdgpu_vm *vm,
unsigned vmhub)
{
struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
mutex_lock(&id_mgr->lock);
- if (vm->reserved_vmid[vmhub] &&
- !--id_mgr->reserved_use_count) {
+ if (!--id_mgr->reserved_use_count) {
/* give the reserved ID back to normal round robin */
list_add(&id_mgr->reserved->list, &id_mgr->ids_lru);
id_mgr->reserved = NULL;
}
- vm->reserved_vmid[vmhub] = false;
+
mutex_unlock(&id_mgr->lock);
}
@@ -578,6 +571,10 @@ void amdgpu_vmid_mgr_init(struct amdgpu_device *adev)
list_add_tail(&id_mgr->ids[j].list, &id_mgr->ids_lru);
}
}
+ /* alloc a default reserved vmid to enforce isolation */
+ if (enforce_isolation)
+ amdgpu_vmid_alloc_reserved(adev, AMDGPU_GFXHUB(0));
+
}
/**
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h
index d1cc09b45da4..68add23dc87c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h
@@ -79,11 +79,9 @@ void
[PATCH 00/20] DC Patches June 9, 2023
This DC patchset brings improvements in multiple areas. In summary, we highlight: - Improvement on eDP - PSR bug fixes - SubVP bug fixes - Improvements on pipe handling to address potential issues - Freesync bug fix - DPIA bug fix - Fix multi-display issues Cc: Daniel Wheeler Alvin Lee (4): drm/amd/display: SubVP high refresh only if all displays >= 120hz drm/amd/display: Re-enable SubVP high refresh drm/amd/display: Block SubVP + DRR if the DRR is PSR capable drm/amd/display: Include CSC updates in new fast update path Aric Cyr (2): drm/amd/display: Promote DAL to 3.2.238 drm/amd/display: 3.2.239 Artem Grishin (1): drm/amd/display: Bug fix in dcn315_populate_dml_pipes_from_context Austin Zheng (2): drm/amd/display: Add DP2 Metrics drm/amd/display: Limit Minimum FreeSync Refresh Rate Daniel Miess (2): drm/amd/display: Re-enable DPP/HUBP Power Gating Revert "drm/amd/display: Move DCN314 DOMAIN power control to DMCUB" Dmytro Laktyushkin (1): drm/amd/display: fix pixel rate update sequence Fangzhi Zuo (1): drm/amd/display: Add Error Code for Dml Validation Failure Hersen Wu (2): drm/amd/display: edp do not add non-edid timings drm/amd/display: add debugfs for allow_edp_hotplug_detection Peichen Huang (1): drm/amd/display: limit DPIA link rate to HBR3 Saaem Rizvi (1): drm/amd/display: Do not disable phantom pipes in driver Samson Tam (1): Revert "drm/amd/display: reallocate DET for dual displays with high pixel rate ratio" Tom Chung (2): drm/amd/display: fix the system hang while disable PSR drm/amd/display: Fix disbling PSR slow response issue .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 18 +- .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 32 .../drm/amd/display/dc/core/dc_hw_sequencer.c | 70 +++ drivers/gpu/drm/amd/display/dc/dc.h | 9 +- drivers/gpu/drm/amd/display/dc/dc_dp_types.h | 2 +- drivers/gpu/drm/amd/display/dc/dc_types.h | 1 + drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 2 + .../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 11 -- .../drm/amd/display/dc/dcn30/dcn30_resource.c | 1 + .../amd/display/dc/dcn302/dcn302_resource.c | 1 + .../amd/display/dc/dcn303/dcn303_resource.c | 1 + .../drm/amd/display/dc/dcn314/dcn314_hwseq.c | 30 +-- .../drm/amd/display/dc/dcn314/dcn314_hwseq.h | 4 +- .../drm/amd/display/dc/dcn314/dcn314_init.c | 2 +- .../amd/display/dc/dcn314/dcn314_resource.c | 11 +- .../amd/display/dc/dcn315/dcn315_resource.c | 1 + .../drm/amd/display/dc/dcn32/dcn32_hwseq.c| 11 +- .../drm/amd/display/dc/dcn32/dcn32_hwseq.h| 2 +- .../drm/amd/display/dc/dcn32/dcn32_resource.c | 3 +- .../drm/amd/display/dc/dcn32/dcn32_resource.h | 4 + .../display/dc/dcn32/dcn32_resource_helpers.c | 158 +++- .../amd/display/dc/dcn321/dcn321_resource.c | 3 +- .../dc/dml/dcn314/display_mode_vba_314.c | 59 ++ .../drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 178 +++--- .../amd/display/dc/dml/display_mode_enums.h | 8 + .../gpu/drm/amd/display/dc/inc/hw_sequencer.h | 32 .../amd/display/dc/inc/hw_sequencer_private.h | 2 +- .../drm/amd/display/dc/link/link_detection.c | 5 + .../amd/display/modules/freesync/freesync.c | 11 +- 29 files changed, 493 insertions(+), 179 deletions(-) -- 2.40.1
[PATCH 01/20] drm/amd/display: edp do not add non-edid timings
From: Hersen Wu
[Why] most edp support only timings from edid. applying
non-edid timings, especially those timings out of edp
bandwidth, may damage edp.
[How] do not add non-edid timings for edp.
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Acked-by: Stylon Wang
Signed-off-by: Hersen Wu
Reviewed-by: Roman Li
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 59badb125736..9279c1d474f2 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -7236,7 +7236,13 @@ static int amdgpu_dm_connector_get_modes(struct
drm_connector *connector)
drm_add_modes_noedid(connector, 1920, 1080);
} else {
amdgpu_dm_connector_ddc_get_modes(connector, edid);
- amdgpu_dm_connector_add_common_modes(encoder, connector);
+ /* most eDP supports only timings from its edid,
+* usually only detailed timings are available
+* from eDP edid. timings which are not from edid
+* may damage eDP
+*/
+ if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
+ amdgpu_dm_connector_add_common_modes(encoder,
connector);
amdgpu_dm_connector_add_freesync_modes(connector, edid);
}
amdgpu_dm_fbc_init(connector);
--
2.40.1
[PATCH 02/20] drm/amd/display: add debugfs for allow_edp_hotplug_detection
From: Hersen Wu
[Why] within dc_link_detect, edp edid is read only for the first time
and saved. edid will not be read after the first time read. to run edp
edid read test, need read edp edid for each dc_link_detect. dc->config
flag allow_edp_hotplug_detection could be used for edp edid test.
[How] add debugfs for dc->config.allow_edp_hotplug_detection
Acked-by: Stylon Wang
Signed-off-by: Hersen Wu
Reviewed-by: Aurabindo Pillai
---
.../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 32 +++
1 file changed, 32 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index 82234397dd44..2ff88562c27a 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -2705,6 +2705,32 @@ static int psr_read_residency(void *data, u64 *val)
return 0;
}
+/* read allow_edp_hotplug_detection */
+static int allow_edp_hotplug_detection_get(void *data, u64 *val)
+{
+ struct amdgpu_dm_connector *aconnector = data;
+ struct drm_connector *connector = &aconnector->base;
+ struct drm_device *dev = connector->dev;
+ struct amdgpu_device *adev = drm_to_adev(dev);
+
+ *val = adev->dm.dc->config.allow_edp_hotplug_detection;
+
+ return 0;
+}
+
+/* set allow_edp_hotplug_detection */
+static int allow_edp_hotplug_detection_set(void *data, u64 val)
+{
+ struct amdgpu_dm_connector *aconnector = data;
+ struct drm_connector *connector = &aconnector->base;
+ struct drm_device *dev = connector->dev;
+ struct amdgpu_device *adev = drm_to_adev(dev);
+
+ adev->dm.dc->config.allow_edp_hotplug_detection = (uint32_t) val;
+
+ return 0;
+}
+
/*
* Set dmcub trace event IRQ enable or disable.
* Usage to enable dmcub trace event IRQ: echo 1 >
/sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en
@@ -2743,6 +2769,10 @@ DEFINE_DEBUGFS_ATTRIBUTE(psr_fops, psr_get, NULL,
"%llu\n");
DEFINE_DEBUGFS_ATTRIBUTE(psr_residency_fops, psr_read_residency, NULL,
"%llu\n");
+DEFINE_DEBUGFS_ATTRIBUTE(allow_edp_hotplug_detection_fops,
+ allow_edp_hotplug_detection_get,
+ allow_edp_hotplug_detection_set, "%llu\n");
+
DEFINE_SHOW_ATTRIBUTE(current_backlight);
DEFINE_SHOW_ATTRIBUTE(target_backlight);
@@ -2913,6 +2943,8 @@ void connector_debugfs_init(struct amdgpu_dm_connector
*connector)
&target_backlight_fops);
debugfs_create_file("ilr_setting", 0644, dir, connector,
&edp_ilr_debugfs_fops);
+ debugfs_create_file("allow_edp_hotplug_detection", 0644, dir,
connector,
+ &allow_edp_hotplug_detection_fops);
}
for (i = 0; i < ARRAY_SIZE(connector_debugfs_entries); i++) {
--
2.40.1
[PATCH 03/20] drm/amd/display: Add DP2 Metrics
From: Austin Zheng
Why:
Log DP2 data to be used for debugging purposes
How:
Check the reported link rate of the DP connection and
translate it to the DP version.
Acked-by: Stylon Wang
Signed-off-by: Austin Zheng
Reviewed-by: Martin Leung
---
drivers/gpu/drm/amd/display/dc/dc.h | 6 --
drivers/gpu/drm/amd/display/dc/dc_dp_types.h | 2 +-
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 360dd83b1a7a..7cf3e9510043 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2012-14 Advanced Micro Devices, Inc.
+ * Copyright 2012-2023 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -60,7 +60,9 @@ struct dc_versions {
};
enum dp_protocol_version {
- DP_VERSION_1_4,
+ DP_VERSION_1_4 = 0,
+ DP_VERSION_2_1,
+ DP_VERSION_UNKNOWN,
};
enum dc_plane_type {
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
index 4a7f6497dc5a..55139d7bf422 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
@@ -61,7 +61,7 @@ enum dc_link_rate {
*/
LINK_RATE_UHBR10 = 1000,// UHBR10 - 10.0 Gbps/Lane
LINK_RATE_UHBR13_5 = 1350, // UHBR13.5 - 13.5 Gbps/Lane
- LINK_RATE_UHBR20 = 2000,// UHBR10 - 20.0 Gbps/Lane
+ LINK_RATE_UHBR20 = 2000,// UHBR20 - 20.0 Gbps/Lane
};
enum dc_link_spread {
--
2.40.1
[PATCH 04/20] drm/amd/display: Add Error Code for Dml Validation Failure
From: Fangzhi Zuo
Any invalid mode from hw perspective should be given corresponding
error code, otherwise it leads to confusing warning message
"[drm] Mode Validation Warning: Validation OK failed validation."
Acked-by: Stylon Wang
Signed-off-by: Fangzhi Zuo
Reviewed-by: Dmytro Laktyushkin
---
.../dc/dml/dcn314/display_mode_vba_314.c | 59 +++
.../amd/display/dc/dml/display_mode_enums.h | 8 +++
2 files changed, 67 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
index 1532a7e0ed6c..9010c47476e9 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
@@ -5557,6 +5557,65 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct
display_mode_lib *mode_
}
}
}
+ for (i = v->soc.num_states; i >= 0; i--) {
+ for (j = 0; j < 2; j++) {
+ enum dm_validation_status status = DML_VALIDATION_OK;
+
+ if (!v->ScaleRatioAndTapsSupport) {
+ status = DML_FAIL_SCALE_RATIO_TAP;
+ } else if (!v->SourceFormatPixelAndScanSupport) {
+ status = DML_FAIL_SOURCE_PIXEL_FORMAT;
+ } else if (!v->ViewportSizeSupport[i][j]) {
+ status = DML_FAIL_VIEWPORT_SIZE;
+ } else if (P2IWith420) {
+ status = DML_FAIL_P2I_WITH_420;
+ } else if (DSCOnlyIfNecessaryWithBPP) {
+ status =
DML_FAIL_DSC_ONLY_IF_NECESSARY_WITH_BPP;
+ } else if (DSC422NativeNotSupported) {
+ status = DML_FAIL_NOT_DSC422_NATIVE;
+ } else if (!v->ODMCombine4To1SupportCheckOK[i]) {
+ status = DML_FAIL_ODM_COMBINE4TO1;
+ } else if (v->NotEnoughDSCUnits[i]) {
+ status = DML_FAIL_NOT_ENOUGH_DSC;
+ } else if (!v->ROBSupport[i][j]) {
+ status = DML_FAIL_REORDERING_BUFFER;
+ } else if (!v->DISPCLK_DPPCLK_Support[i][j]) {
+ status = DML_FAIL_DISPCLK_DPPCLK;
+ } else if (!v->TotalAvailablePipesSupport[i][j]) {
+ status = DML_FAIL_TOTAL_AVAILABLE_PIPES;
+ } else if (!EnoughWritebackUnits) {
+ status = DML_FAIL_ENOUGH_WRITEBACK_UNITS;
+ } else if (!v->WritebackLatencySupport) {
+ status = DML_FAIL_WRITEBACK_LATENCY;
+ } else if (!v->WritebackScaleRatioAndTapsSupport) {
+ status = DML_FAIL_WRITEBACK_SCALE_RATIO_TAP;
+ } else if (!v->CursorSupport) {
+ status = DML_FAIL_CURSOR_SUPPORT;
+ } else if (!v->PitchSupport) {
+ status = DML_FAIL_PITCH_SUPPORT;
+ } else if (ViewportExceedsSurface) {
+ status = DML_FAIL_VIEWPORT_EXCEEDS_SURFACE;
+ } else if (!v->PrefetchSupported[i][j]) {
+ status = DML_FAIL_PREFETCH_SUPPORT;
+ } else if (!v->DynamicMetadataSupported[i][j]) {
+ status = DML_FAIL_DYNAMIC_METADATA;
+ } else if
(!v->TotalVerticalActiveBandwidthSupport[i][j]) {
+ status = DML_FAIL_TOTAL_V_ACTIVE_BW;
+ } else if (!v->VRatioInPrefetchSupported[i][j]) {
+ status = DML_FAIL_V_RATIO_PREFETCH;
+ } else if (!v->PTEBufferSizeNotExceeded[i][j]) {
+ status = DML_FAIL_PTE_BUFFER_SIZE;
+ } else if (v->NonsupportedDSCInputBPC) {
+ status = DML_FAIL_DSC_INPUT_BPC;
+ } else if ((v->HostVMEnable
+ &&
!v->ImmediateFlipSupportedForState[i][j])) {
+ status = DML_FAIL_HOST_VM_IMMEDIATE_FLIP;
+ } else if (FMTBufferExceeded) {
+ status = DML_FAIL_FMT_BUFFER_EXCEEDED;
+ }
+ mode_lib->vba.ValidationStatus[i] = status;
+ }
+ }
{
unsigned int MaximumMPCCombine = 0;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
index 0bffae95f3a2..d5831a34f5a1 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_en
[PATCH 05/20] drm/amd/display: Promote DAL to 3.2.238
From: Aric Cyr Acked-by: Stylon Wang Signed-off-by: Aric Cyr --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 7cf3e9510043..5c906b007e4d 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -45,7 +45,7 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.237" +#define DC_VER "3.2.238" #define MAX_SURFACES 3 #define MAX_PLANES 6 -- 2.40.1
[PATCH 06/20] drm/amd/display: fix the system hang while disable PSR
From: Tom Chung [Why] When the PSR enabled. If you try to adjust the timing parameters, it may cause system hang. Because the timing mismatch with the DMCUB settings. [How] Disable the PSR before adjusting timing parameters. Cc: Mario Limonciello Cc: Alex Deucher Cc: sta...@vger.kernel.org Acked-by: Stylon Wang Signed-off-by: Tom Chung Reviewed-by: Wayne Lin --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 10 ++ 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 9279c1d474f2..cfd1a67cf7d0 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8244,6 +8244,12 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, if (acrtc_state->abm_level != dm_old_crtc_state->abm_level) bundle->stream_update.abm_level = &acrtc_state->abm_level; + mutex_lock(&dm->dc_lock); + if ((acrtc_state->update_type > UPDATE_TYPE_FAST) && + acrtc_state->stream->link->psr_settings.psr_allow_active) + amdgpu_dm_psr_disable(acrtc_state->stream); + mutex_unlock(&dm->dc_lock); + /* * If FreeSync state on the stream has changed then we need to * re-adjust the min/max bounds now that DC doesn't handle this @@ -8257,10 +8263,6 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); } mutex_lock(&dm->dc_lock); - if ((acrtc_state->update_type > UPDATE_TYPE_FAST) && - acrtc_state->stream->link->psr_settings.psr_allow_active) - amdgpu_dm_psr_disable(acrtc_state->stream); - update_planes_and_stream_adapter(dm->dc, acrtc_state->update_type, planes_count, -- 2.40.1
[PATCH 07/20] drm/amd/display: Fix disbling PSR slow response issue
From: Tom Chung
[Why]
dmub_psr_get_state() return an invalid PSR state while disable
the PSR because convert_psr_state() doesn't recognize the state
that return from DMCUB.
[How]
Add a PSR state to make the dmub_psr_get_state() return a
correct PSR state.
Acked-by: Stylon Wang
Signed-off-by: Tom Chung
Reviewed-by: Wayne Lin
---
drivers/gpu/drm/amd/display/dc/dc_types.h | 1 +
drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h
b/drivers/gpu/drm/amd/display/dc/dc_types.h
index 6b4731b5e975..0ce7728a5a4b 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -597,6 +597,7 @@ enum dc_psr_state {
PSR_STATE4b_FULL_FRAME,
PSR_STATE4c_FULL_FRAME,
PSR_STATE4_FULL_FRAME_POWERUP,
+ PSR_STATE4_FULL_FRAME_HW_LOCK,
PSR_STATE5,
PSR_STATE5a,
PSR_STATE5b,
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
index 4000a834592c..0f24b6fbd220 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
@@ -87,6 +87,8 @@ static enum dc_psr_state convert_psr_state(uint32_t raw_state)
state = PSR_STATE4c_FULL_FRAME;
else if (raw_state == 0x4E)
state = PSR_STATE4_FULL_FRAME_POWERUP;
+ else if (raw_state == 0x4F)
+ state = PSR_STATE4_FULL_FRAME_HW_LOCK;
else if (raw_state == 0x60)
state = PSR_STATE_HWLOCK_MGR;
else if (raw_state == 0x61)
--
2.40.1
[PATCH 08/20] drm/amd/display: SubVP high refresh only if all displays >= 120hz
From: Alvin Lee
[Description]
- SubVP high refresh should only be enabled if all displays
are >= 120hz. We do not want to accidentally enables configs
such as 60hz[SubVP] + 120hz[SubVP]
- Ensure that the SubVP config generation code does not produce
configs such as 60hz[SubVP] + 120hz[SubVP]
- Also add admissibility checks to ensure these configs do not
pass as valid configs
Acked-by: Stylon Wang
Signed-off-by: Alvin Lee
Reviewed-by: Dillon Varone
---
.../drm/amd/display/dc/dcn32/dcn32_resource.h | 4 +
.../display/dc/dcn32/dcn32_resource_helpers.c | 101 ++
.../drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 178 +++---
3 files changed, 217 insertions(+), 66 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h
index 2f34f01b3ea1..81e443170829 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h
@@ -169,6 +169,10 @@ double dcn32_determine_max_vratio_prefetch(struct dc *dc,
struct dc_state *conte
bool dcn32_check_native_scaling_for_res(struct pipe_ctx *pipe, unsigned int
width, unsigned int height);
+bool dcn32_subvp_drr_admissable(struct dc *dc, struct dc_state *context);
+
+bool dcn32_subvp_vblank_admissable(struct dc *dc, struct dc_state *context,
int vlevel);
+
/* definitions for run time init of reg offsets */
/* CLK SRC */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
index 1d13fd797212..578070e7d44b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
@@ -660,3 +660,104 @@ bool dcn32_check_native_scaling_for_res(struct pipe_ctx
*pipe, unsigned int widt
return is_native_scaling;
}
+
+/**
+ *
+ * dcn32_subvp_drr_admissable: Determine if SubVP + DRR config is admissible
+ *
+ * @param [in]: dc: Current DC state
+ * @param [in]: context: New DC state to be programmed
+ *
+ * SubVP + DRR is admissible under the following conditions:
+ * - Config must have 2 displays (i.e., 2 non-phantom master pipes)
+ * - One display is SubVP
+ * - Other display must have Freesync enabled
+ *
+ * @return: True if admissible, false otherwise
+ *
+ *
+ */
+bool dcn32_subvp_drr_admissable(struct dc *dc, struct dc_state *context)
+{
+ bool result = false;
+ uint32_t i;
+ uint8_t subvp_count = 0;
+ uint8_t non_subvp_pipes = 0;
+ bool drr_pipe_found = false;
+
+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+
+ if (!pipe->stream)
+ continue;
+
+ if (pipe->plane_state && !pipe->top_pipe) {
+ if (pipe->stream->mall_stream_config.type == SUBVP_MAIN)
+ subvp_count++;
+ if (pipe->stream->mall_stream_config.type ==
SUBVP_NONE) {
+ non_subvp_pipes++;
+ if (pipe->stream->ignore_msa_timing_param &&
+ (pipe->stream->allow_freesync
|| pipe->stream->vrr_active_variable)) {
+ drr_pipe_found = true;
+ }
+ }
+ }
+ }
+
+ if (subvp_count == 1 && non_subvp_pipes == 1 && drr_pipe_found)
+ result = true;
+
+ return result;
+}
+
+/**
+ *
+ * dcn32_subvp_vblank_admissable: Determine if SubVP + Vblank config is
admissible
+ *
+ * @param [in]: dc: Current DC state
+ * @param [in]: context: New DC state to be programmed
+ *
+ * SubVP + Vblank is admissible under the following conditions:
+ * - Config must have 2 displays (i.e., 2 non-phantom master pipes)
+ * - One display is SubVP
+ * - Other display must not have Freesync capability
+ * - DML must have output DRAM clock change support as SubVP + Vblank
+ *
+ * @return: True if admissible, false otherwise
+ *
+ *
+ */
+bool dcn32_subvp_vblank_admissable(struct dc *dc, struct dc_state *context,
int vlevel)
+{
+ bool result = false;
+ uint32_t i;
+ uint8_t subvp_count = 0;
+ uint8_t non_subvp_pipes = 0;
+ bool drr_pipe_found = false;
+ struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
+
+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+
+
[PATCH 09/20] drm/amd/display: Re-enable DPP/HUBP Power Gating
From: Daniel Miess
[Why & How]
Bugs preventing DPP/HUBP power gating have been addressed
so this should be reenabled on dcn314 for sufficient
hardware rev versions
Acked-by: Stylon Wang
Signed-off-by: Daniel Miess
Reviewed-by: Nicholas Kazlauskas
---
.../gpu/drm/amd/display/dc/dcn314/dcn314_resource.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
index 7957ad4d6a34..a840b008d660 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
@@ -874,8 +874,8 @@ static const struct dc_debug_options debug_defaults_drv = {
.force_abm_enable = false,
.timing_trace = false,
.clock_trace = true,
- .disable_dpp_power_gate = true,
- .disable_hubp_power_gate = true,
+ .disable_dpp_power_gate = false,
+ .disable_hubp_power_gate = false,
.disable_pplib_clock_request = false,
.pipe_split_policy = MPC_SPLIT_DYNAMIC,
.force_single_disp_pipe_split = false,
@@ -1883,6 +1883,13 @@ static bool dcn314_resource_construct(
/* Use pipe context based otg sync logic */
dc->config.use_pipe_ctx_sync_logic = true;
+ /* Disable pipe power gating when unsupported */
+ if (ctx->asic_id.hw_internal_rev == 0x01 ||
+ ctx->asic_id.hw_internal_rev == 0x80) {
+ dc->debug.disable_dpp_power_gate = true;
+ dc->debug.disable_hubp_power_gate = true;
+ }
+
/* read VBIOS LTTPR caps */
{
if (ctx->dc_bios->funcs->get_lttpr_caps) {
--
2.40.1
[PATCH 10/20] drm/amd/display: Re-enable SubVP high refresh
From: Alvin Lee
Re-enable SubVP high refresh now that it is fixed
for displays with high refresh rates.
Acked-by: Stylon Wang
Signed-off-by: Alvin Lee
Reviewed-by: Saaem Rizvi
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c | 2 +-
drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
index 2e6b39fe2613..8c9e15952a49 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
@@ -728,7 +728,7 @@ static const struct dc_debug_options debug_defaults_drv = {
.fpo_vactive_margin_us = 2000, // 2000us
.disable_fpo_vactive = false,
.disable_boot_optimizations = false,
- .disable_subvp_high_refresh = true,
+ .disable_subvp_high_refresh = false,
.disable_dp_plus_plus_wa = true,
.fpo_vactive_min_active_margin_us = 200,
.fpo_vactive_max_blank_us = 1000,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
index bbcd3579fea6..ee07ee340171 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
@@ -727,7 +727,7 @@ static const struct dc_debug_options debug_defaults_drv = {
.fpo_vactive_margin_us = 2000, // 2000us
.disable_fpo_vactive = false,
.disable_boot_optimizations = false,
- .disable_subvp_high_refresh = true,
+ .disable_subvp_high_refresh = false,
.fpo_vactive_min_active_margin_us = 200,
.fpo_vactive_max_blank_us = 1000,
};
--
2.40.1
[PATCH 11/20] drm/amd/display: Do not disable phantom pipes in driver
From: Saaem Rizvi
[Why and How]
We should not disable phantom pipes in this sequence, as this should be
controlled by FW. Furthermore, the previous programming sequence would
have enabled the phantom pipe in driver as well, causing corruption.
This change should avoid this from occuring.
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Acked-by: Stylon Wang
Signed-off-by: Saaem Rizvi
Reviewed-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
index 00f32ffe0079..e5bd76c6b1d3 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
@@ -1211,7 +1211,8 @@ void dcn32_resync_fifo_dccg_dio(struct dce_hwseq *hws,
struct dc *dc, struct dc_
if (pipe->top_pipe || pipe->prev_odm_pipe)
continue;
- if (pipe->stream && (pipe->stream->dpms_off ||
dc_is_virtual_signal(pipe->stream->signal))) {
+ if (pipe->stream && (pipe->stream->dpms_off ||
dc_is_virtual_signal(pipe->stream->signal))
+ && pipe->stream->mall_stream_config.type !=
SUBVP_PHANTOM) {
pipe->stream_res.tg->funcs->disable_crtc(pipe->stream_res.tg);
reset_sync_context_for_pipe(dc, context, i);
otg_disabled[i] = true;
--
2.40.1
[PATCH 12/20] drm/amd/display: Block SubVP + DRR if the DRR is PSR capable
From: Alvin Lee
[Description]
PSR implementation in FW has inline polling which can poll for up
to 1ms. This will interfere with SubVP because SubVP is timing
sensitive and can't tolerate up to 1ms worth of delay before
handling vertical or VLINE interrupts. Therefore block SubVP + DRR
cases if DRR is PSR capable
Acked-by: Stylon Wang
Signed-off-by: Alvin Lee
Reviewed-by: Saaem Rizvi
---
.../drm/amd/display/dc/dcn32/dcn32_resource_helpers.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
index 578070e7d44b..7eec39576e2c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
@@ -672,6 +672,7 @@ bool dcn32_check_native_scaling_for_res(struct pipe_ctx
*pipe, unsigned int widt
* - Config must have 2 displays (i.e., 2 non-phantom master pipes)
* - One display is SubVP
* - Other display must have Freesync enabled
+ * - The potential DRR display must not be PSR capable
*
* @return: True if admissible, false otherwise
*
@@ -684,6 +685,7 @@ bool dcn32_subvp_drr_admissable(struct dc *dc, struct
dc_state *context)
uint8_t subvp_count = 0;
uint8_t non_subvp_pipes = 0;
bool drr_pipe_found = false;
+ bool drr_psr_capable = false;
for (i = 0; i < dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
@@ -696,6 +698,7 @@ bool dcn32_subvp_drr_admissable(struct dc *dc, struct
dc_state *context)
subvp_count++;
if (pipe->stream->mall_stream_config.type ==
SUBVP_NONE) {
non_subvp_pipes++;
+ drr_psr_capable = (drr_psr_capable ||
dcn32_is_psr_capable(pipe));
if (pipe->stream->ignore_msa_timing_param &&
(pipe->stream->allow_freesync
|| pipe->stream->vrr_active_variable)) {
drr_pipe_found = true;
@@ -704,7 +707,7 @@ bool dcn32_subvp_drr_admissable(struct dc *dc, struct
dc_state *context)
}
}
- if (subvp_count == 1 && non_subvp_pipes == 1 && drr_pipe_found)
+ if (subvp_count == 1 && non_subvp_pipes == 1 && drr_pipe_found &&
!drr_psr_capable)
result = true;
return result;
@@ -722,6 +725,7 @@ bool dcn32_subvp_drr_admissable(struct dc *dc, struct
dc_state *context)
* - One display is SubVP
* - Other display must not have Freesync capability
* - DML must have output DRAM clock change support as SubVP + Vblank
+ * - The potential vblank display must not be PSR capable
*
* @return: True if admissible, false otherwise
*
@@ -735,6 +739,7 @@ bool dcn32_subvp_vblank_admissable(struct dc *dc, struct
dc_state *context, int
uint8_t non_subvp_pipes = 0;
bool drr_pipe_found = false;
struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
+ bool vblank_psr_capable = false;
for (i = 0; i < dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
@@ -747,6 +752,7 @@ bool dcn32_subvp_vblank_admissable(struct dc *dc, struct
dc_state *context, int
subvp_count++;
if (pipe->stream->mall_stream_config.type ==
SUBVP_NONE) {
non_subvp_pipes++;
+ vblank_psr_capable = (vblank_psr_capable ||
dcn32_is_psr_capable(pipe));
if (pipe->stream->ignore_msa_timing_param &&
(pipe->stream->allow_freesync
|| pipe->stream->vrr_active_variable)) {
drr_pipe_found = true;
@@ -755,7 +761,7 @@ bool dcn32_subvp_vblank_admissable(struct dc *dc, struct
dc_state *context, int
}
}
- if (subvp_count == 1 && non_subvp_pipes == 1 && !drr_pipe_found &&
+ if (subvp_count == 1 && non_subvp_pipes == 1 && !drr_pipe_found &&
!vblank_psr_capable &&
vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] ==
dm_dram_clock_change_vblank_w_mall_sub_vp)
result = true;
--
2.40.1
[PATCH 13/20] Revert "drm/amd/display: Move DCN314 DOMAIN power control to DMCUB"
From: Daniel Miess
Revert commit 6c2c207e4a24 ("drm/amd/display: Move DCN314 DOMAIN power control
to DMCUB")
[Why]
Controling hubp power gating using the DMCUB isn't stable so we
are reverting this change to move control back into the driver
Acked-by: Stylon Wang
Signed-off-by: Daniel Miess
Reviewed-by: Nicholas Kazlauskas
---
.../drm/amd/display/dc/dcn314/dcn314_hwseq.c | 21 ---
.../drm/amd/display/dc/dcn314/dcn314_hwseq.h | 2 --
.../drm/amd/display/dc/dcn314/dcn314_init.c | 2 +-
3 files changed, 1 insertion(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c
index ce7e6f20b31f..4d2820ffe468 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c
@@ -429,27 +429,6 @@ void dcn314_dpp_root_clock_control(struct dce_hwseq *hws,
unsigned int dpp_inst,
hws->ctx->dc->res_pool->dccg, dpp_inst, clock_on);
}
-void dcn314_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst,
bool power_on)
-{
- struct dc_context *ctx = hws->ctx;
- union dmub_rb_cmd cmd;
-
- if (hws->ctx->dc->debug.disable_hubp_power_gate)
- return;
-
- PERF_TRACE();
-
- memset(&cmd, 0, sizeof(cmd));
- cmd.domain_control.header.type = DMUB_CMD__VBIOS;
- cmd.domain_control.header.sub_type = DMUB_CMD__VBIOS_DOMAIN_CONTROL;
- cmd.domain_control.header.payload_bytes =
sizeof(cmd.domain_control.data);
- cmd.domain_control.data.inst = hubp_inst;
- cmd.domain_control.data.power_gate = !power_on;
-
- dm_execute_dmub_cmd(ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
-
- PERF_TRACE();
-}
static void apply_symclk_on_tx_off_wa(struct dc_link *link)
{
/* There are use cases where SYMCLK is referenced by OTG. For instance
diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h
b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h
index 559d71002e8a..eafcc4ea6d24 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h
@@ -43,8 +43,6 @@ void dcn314_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx);
void dcn314_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct
dc_state *context);
-void dcn314_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst,
bool power_on);
-
void dcn314_dpp_root_clock_control(struct dce_hwseq *hws, unsigned int
dpp_inst, bool clock_on);
void dcn314_disable_link_output(struct dc_link *link, const struct
link_resource *link_res, enum signal_type signal);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.c
b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.c
index 86d6a514dec0..ca8fe55c33b8 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.c
@@ -139,7 +139,7 @@ static const struct hwseq_private_funcs
dcn314_private_funcs = {
.plane_atomic_power_down = dcn10_plane_atomic_power_down,
.enable_power_gating_plane = dcn314_enable_power_gating_plane,
.dpp_root_clock_control = dcn314_dpp_root_clock_control,
- .hubp_pg_control = dcn314_hubp_pg_control,
+ .hubp_pg_control = dcn31_hubp_pg_control,
.program_all_writeback_pipes_in_tree =
dcn30_program_all_writeback_pipes_in_tree,
.update_odm = dcn314_update_odm,
.dsc_pg_control = dcn314_dsc_pg_control,
--
2.40.1
[PATCH 14/20] drm/amd/display: Bug fix in dcn315_populate_dml_pipes_from_context
From: Artem Grishin
[Why]
When iterating over all pipes in the loop, the CRB allocation algorithm
may potentially skip some of the pipes. Previously, the current pipe
index didn't get updated in this case, causing incorrect outcome.
[How]
Increment the pipe index when skipping over a pipe in the loop.
Acked-by: Stylon Wang
Signed-off-by: Artem Grishin
Reviewed-by: Dmytro Laktyushkin
---
drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
index 0cc853964781..f1153941907e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
@@ -1742,6 +1742,7 @@ static int dcn315_populate_dml_pipes_from_context(
/* Do not use asymetric crb if not enough for pstate
support */
if (remaining_det_segs < 0) {
pipes[pipe_cnt].pipe.src.det_size_override = 0;
+ pipe_cnt++;
continue;
}
--
2.40.1
[PATCH 15/20] drm/amd/display: Limit Minimum FreeSync Refresh Rate
From: Austin Zheng
Why:
Some EDIDs report a minimum refresh rate lower than what HW can support
How:
Add a check to calculate minimum supported refresh rate with current timing
and use that as the minimum if a lower one is passed in
Acked-by: Stylon Wang
Signed-off-by: Austin Zheng
Reviewed-by: Anthony Koo
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c | 1 +
.../gpu/drm/amd/display/dc/dcn302/dcn302_resource.c | 1 +
.../gpu/drm/amd/display/dc/dcn303/dcn303_resource.c | 1 +
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c | 1 +
.../gpu/drm/amd/display/dc/dcn321/dcn321_resource.c | 1 +
.../gpu/drm/amd/display/modules/freesync/freesync.c | 11 +--
7 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 5c906b007e4d..a239dcd8e9fb 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -266,6 +266,7 @@ struct dc_caps {
uint16_t subvp_pstate_allow_width_us;
uint16_t subvp_vertical_int_margin_us;
bool seamless_odm;
+ uint32_t max_v_total;
uint8_t subvp_drr_vblank_start_margin_us;
};
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
index f4ee4b3df596..1a0284a068b2 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
@@ -2328,6 +2328,7 @@ static bool dcn30_resource_construct(
dc->caps.color.mpc.ocsc = 1;
dc->caps.dp_hdmi21_pcon_support = true;
+ dc->caps.max_v_total = (1 << 15) - 1;
/* read VBIOS LTTPR caps */
{
diff --git a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
index 93f42132c900..7dc065ea247a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
@@ -1227,6 +1227,7 @@ static bool dcn302_resource_construct(
dc->caps.force_dp_tps4_for_cp2520 = true;
dc->caps.extended_aux_timeout_support = true;
dc->caps.dmcub_support = true;
+ dc->caps.max_v_total = (1 << 15) - 1;
/* Color pipeline capabilities */
dc->caps.color.dpp.dcn_arch = 1;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c
index f35514188a5c..6d9761395288 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c
@@ -1152,6 +1152,7 @@ static bool dcn303_resource_construct(
dc->caps.force_dp_tps4_for_cp2520 = true;
dc->caps.extended_aux_timeout_support = true;
dc->caps.dmcub_support = true;
+ dc->caps.max_v_total = (1 << 15) - 1;
/* Color pipeline capabilities */
dc->caps.color.dpp.dcn_arch = 1;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
index 8c9e15952a49..19f134caa8ad 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
@@ -2175,6 +2175,7 @@ static bool dcn32_resource_construct(
dc->caps.extended_aux_timeout_support = true;
dc->caps.dmcub_support = true;
dc->caps.seamless_odm = true;
+ dc->caps.max_v_total = (1 << 15) - 1;
/* Color pipeline capabilities */
dc->caps.color.dpp.dcn_arch = 1;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
index ee07ee340171..ea204742ad35 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
@@ -1718,6 +1718,7 @@ static bool dcn321_resource_construct(
dc->caps.edp_dsc_support = true;
dc->caps.extended_aux_timeout_support = true;
dc->caps.dmcub_support = true;
+ dc->caps.max_v_total = (1 << 15) - 1;
/* Color pipeline capabilities */
dc->caps.color.dpp.dcn_arch = 1;
diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
index 5798c0eafa1f..dbd60811f95d 100644
--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2016 Advanced Micro Devices, Inc.
+ * Copyright 2016-2023 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -989,6 +989,7 @@ void mod_freesync_build_vrr_params(struct mod_freesync
*mod_freesync,
unsigned int refresh_range = 0;
unsigned long l
[PATCH 16/20] drm/amd/display: Include CSC updates in new fast update path
From: Alvin Lee
[Description]
- Missed color / CSC updates in fast update path
which caused Custom Color to break.
- Add color / CSC updates to new fast update path
to fix custom color
Acked-by: Stylon Wang
Signed-off-by: Alvin Lee
Reviewed-by: Jun Lei
---
.../drm/amd/display/dc/core/dc_hw_sequencer.c | 70 +++
.../gpu/drm/amd/display/dc/inc/hw_sequencer.h | 32 +
2 files changed, 102 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
index 182c42c63bc5..d7d00fefaab9 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
@@ -562,6 +562,29 @@ void hwss_build_fast_sequence(struct dc *dc,
(*num_steps)++;
}
+ if
(current_mpc_pipe->stream->update_flags.bits.out_csc) {
+
block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.mpc =
dc->res_pool->mpc;
+
block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.mpcc_id =
current_mpc_pipe->plane_res.hubp->inst;
+
block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.power_on = true;
+ block_sequence[*num_steps].func =
MPC_POWER_ON_MPC_MEM_PWR;
+ (*num_steps)++;
+
+ if
(current_mpc_pipe->stream->csc_color_matrix.enable_adjustment == true) {
+
block_sequence[*num_steps].params.set_output_csc_params.mpc = dc->res_pool->mpc;
+
block_sequence[*num_steps].params.set_output_csc_params.opp_id =
current_mpc_pipe->stream_res.opp->inst;
+
block_sequence[*num_steps].params.set_output_csc_params.regval =
current_mpc_pipe->stream->csc_color_matrix.matrix;
+
block_sequence[*num_steps].params.set_output_csc_params.ocsc_mode =
MPC_OUTPUT_CSC_COEF_A;
+ block_sequence[*num_steps].func =
MPC_SET_OUTPUT_CSC;
+ (*num_steps)++;
+ } else {
+
block_sequence[*num_steps].params.set_ocsc_default_params.mpc =
dc->res_pool->mpc;
+
block_sequence[*num_steps].params.set_ocsc_default_params.opp_id =
current_mpc_pipe->stream_res.opp->inst;
+
block_sequence[*num_steps].params.set_ocsc_default_params.color_space =
current_mpc_pipe->stream->output_color_space;
+
block_sequence[*num_steps].params.set_ocsc_default_params.ocsc_mode =
MPC_OUTPUT_CSC_COEF_A;
+ block_sequence[*num_steps].func =
MPC_SET_OCSC_DEFAULT;
+ (*num_steps)++;
+ }
+ }
current_mpc_pipe = current_mpc_pipe->bottom_pipe;
}
current_pipe = current_pipe->next_odm_pipe;
@@ -661,6 +684,15 @@ void hwss_execute_sequence(struct dc *dc,
params->update_visual_confirm_params.pipe_ctx,
params->update_visual_confirm_params.mpcc_id);
break;
+ case MPC_POWER_ON_MPC_MEM_PWR:
+ hwss_power_on_mpc_mem_pwr(params);
+ break;
+ case MPC_SET_OUTPUT_CSC:
+ hwss_set_output_csc(params);
+ break;
+ case MPC_SET_OCSC_DEFAULT:
+ hwss_set_ocsc_default(params);
+ break;
case DMUB_SEND_DMCUB_CMD:
hwss_send_dmcub_cmd(params);
break;
@@ -718,6 +750,44 @@ void hwss_program_bias_and_scale(union
block_sequence_params *params)
dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);
}
+void hwss_power_on_mpc_mem_pwr(union block_sequence_params *params)
+{
+ struct mpc *mpc = params->power_on_mpc_mem_pwr_params.mpc;
+ int mpcc_id = params->power_on_mpc_mem_pwr_params.mpcc_id;
+ bool power_on = params->power_on_mpc_mem_pwr_params.power_on;
+
+ if (mpc->funcs->power_on_mpc_mem_pwr)
+ mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, power_on);
+}
+
+void hwss_set_output_csc(union block_sequence_params *params)
+{
+ struct mpc *mpc = params->set_output_csc_params.mpc;
+ int opp_id = params->set_output_csc_params.opp_id;
+ const uint16_t *matrix = params->set_output_csc_params.regval;
+ enum mpc_output_csc_mode ocsc_mode =
params->set_output_csc_params.ocsc_mode;
+
+ if (mpc->funcs->set
[PATCH 17/20] drm/amd/display: limit DPIA link rate to HBR3
From: Peichen Huang [Why] DPIA doesn't support UHBR, driver should not enable UHBR for dp tunneling [How] limit DPIA link rate to HBR3 Cc: Mario Limonciello Cc: Alex Deucher Cc: sta...@vger.kernel.org Acked-by: Stylon Wang Signed-off-by: Peichen Huang Reviewed-by: Mustapha Ghaddar --- drivers/gpu/drm/amd/display/dc/link/link_detection.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/link/link_detection.c b/drivers/gpu/drm/amd/display/dc/link/link_detection.c index 17904de4f155..8041b8369e45 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_detection.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_detection.c @@ -984,6 +984,11 @@ static bool detect_link_and_local_sink(struct dc_link *link, (link->dpcd_caps.dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER)) converter_disable_audio = true; + + /* limited link rate to HBR3 for DPIA until we implement USB4 V2 */ + if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && + link->reported_link_cap.link_rate > LINK_RATE_HIGH3) + link->reported_link_cap.link_rate = LINK_RATE_HIGH3; break; } -- 2.40.1
[PATCH 18/20] Revert "drm/amd/display: reallocate DET for dual displays with high pixel rate ratio"
From: Samson Tam
Revert commit b957de69c4c8 ("drm/amd/display: reallocate DET for dual displays
with high pixel rate ratio")
[Why]
Previously had modified DET allocation algorithm to allocate less DET
segments for lower pixel rate display and more DET segments for higher
pixel rate display. But noticed it is causing underflow when higher
pixel rate display is not displaying at higher mode
[How]
Roll back change
Acked-by: Stylon Wang
Signed-off-by: Samson Tam
Reviewed-by: Alvin Lee
---
.../display/dc/dcn32/dcn32_resource_helpers.c | 51 ++-
1 file changed, 5 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
index 7eec39576e2c..4882c3684b82 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
@@ -255,8 +255,6 @@ bool dcn32_is_psr_capable(struct pipe_ctx *pipe)
return psr_capable;
}
-#define DCN3_2_NEW_DET_OVERRIDE_MIN_MULTIPLIER 7
-
/**
* dcn32_determine_det_override(): Determine DET allocation for each pipe
*
@@ -267,6 +265,7 @@ bool dcn32_is_psr_capable(struct pipe_ctx *pipe)
* If there is a plane that's driven by more than 1 pipe (i.e. pipe split),
then the
* number of DET for that given plane will be split among the pipes driving
that plane.
*
+ *
* High level algorithm:
* 1. Split total DET among number of streams
* 2. For each stream, split DET among the planes
@@ -274,21 +273,9 @@ bool dcn32_is_psr_capable(struct pipe_ctx *pipe)
*among those pipes.
* 4. Assign the DET override to the DML pipes.
*
- * Special cases:
- *
- * For two displays that have a large difference in pixel rate, we may
experience
- * underflow on the larger display when we divide the DET equally. For this,
we
- * will implement a modified algorithm to assign more DET to larger display.
- *
- * 1. Calculate difference in pixel rates ( multiplier ) between two displays
- * 2. If the multiplier exceeds DCN3_2_NEW_DET_OVERRIDE_MIN_MULTIPLIER, then
- *implement the modified DET override algorithm.
- * 3. Assign smaller DET size for lower pixel display and higher DET size for
- *higher pixel display
- *
- * @dc: Current DC state
- * @context: New DC state to be programmed
- * @pipes: Array of DML pipes
+ * @param [in]: dc: Current DC state
+ * @param [in]: context: New DC state to be programmed
+ * @param [in]: pipes: Array of DML pipes
*
* Return: void
*/
@@ -303,31 +290,10 @@ void dcn32_determine_det_override(struct dc *dc,
struct dc_plane_state *current_plane = NULL;
uint8_t stream_count = 0;
- int phy_pix_clk_mult, lower_mode_stream_index;
- int phy_pix_clk[MAX_PIPES] = {0};
- bool use_new_det_override_algorithm = false;
-
for (i = 0; i < context->stream_count; i++) {
/* Don't count SubVP streams for DET allocation */
- if (context->streams[i]->mall_stream_config.type !=
SUBVP_PHANTOM) {
- phy_pix_clk[i] = context->streams[i]->phy_pix_clk;
+ if (context->streams[i]->mall_stream_config.type !=
SUBVP_PHANTOM)
stream_count++;
- }
- }
-
- /* Check for special case with two displays, one with much higher pixel
rate */
- if (stream_count == 2) {
- ASSERT((phy_pix_clk[0] > 0) && (phy_pix_clk[1] > 0));
- if (phy_pix_clk[0] < phy_pix_clk[1]) {
- lower_mode_stream_index = 0;
- phy_pix_clk_mult = phy_pix_clk[1] / phy_pix_clk[0];
- } else {
- lower_mode_stream_index = 1;
- phy_pix_clk_mult = phy_pix_clk[0] / phy_pix_clk[1];
- }
-
- if (phy_pix_clk_mult >= DCN3_2_NEW_DET_OVERRIDE_MIN_MULTIPLIER)
- use_new_det_override_algorithm = true;
}
if (stream_count > 0) {
@@ -336,13 +302,6 @@ void dcn32_determine_det_override(struct dc *dc,
if (context->streams[i]->mall_stream_config.type ==
SUBVP_PHANTOM)
continue;
- if (use_new_det_override_algorithm) {
- if (i == lower_mode_stream_index)
- stream_segments = 4;
- else
- stream_segments = 14;
- }
-
if (context->stream_status[i].plane_count > 0)
plane_segments = stream_segments /
context->stream_status[i].plane_count;
else
--
2.40.1
[PATCH 19/20] drm/amd/display: fix pixel rate update sequence
From: Dmytro Laktyushkin
The k1/k2 pixel rate dividers in dccg should only be updated on stream enable
and do not actually depend on whether odm combine is active.
This removes an on flip update of these and fixes the calculate function
to ignore odm status for dp steams.
Acked-by: Stylon Wang
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Ariel Bernstein
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c| 11 ---
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c | 9 ++---
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h | 2 +-
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c| 8 ++--
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.h| 2 +-
.../gpu/drm/amd/display/dc/inc/hw_sequencer_private.h | 2 +-
6 files changed, 7 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 20f668d28364..eaf9e9ccad2a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1741,17 +1741,6 @@ static void dcn20_program_pipe(
if (hws->funcs.setup_vupdate_interrupt)
hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
-
- if (hws->funcs.calculate_dccg_k1_k2_values &&
dc->res_pool->dccg->funcs->set_pixel_rate_div) {
- unsigned int k1_div, k2_div;
-
- hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx,
&k1_div, &k2_div);
-
- dc->res_pool->dccg->funcs->set_pixel_rate_div(
- dc->res_pool->dccg,
- pipe_ctx->stream_res.tg->inst,
- k1_div, k2_div);
- }
}
if (pipe_ctx->update_flags.bits.odm)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c
index 4d2820ffe468..32a1c3105089 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c
@@ -337,14 +337,13 @@ void dcn314_enable_power_gating_plane(struct dce_hwseq
*hws, bool enable)
REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
}
-unsigned int dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx,
unsigned int *k1_div, unsigned int *k2_div)
+void dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned
int *k1_div, unsigned int *k2_div)
{
struct dc_stream_state *stream = pipe_ctx->stream;
- unsigned int odm_combine_factor = 0;
bool two_pix_per_container = false;
two_pix_per_container =
optc2_is_two_pixels_per_containter(&stream->timing);
- odm_combine_factor = get_odm_config(pipe_ctx, NULL);
+ get_odm_config(pipe_ctx, NULL);
if (stream->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
*k1_div = PIXEL_RATE_DIV_BY_1;
@@ -362,15 +361,11 @@ unsigned int dcn314_calculate_dccg_k1_k2_values(struct
pipe_ctx *pipe_ctx, unsig
} else {
*k1_div = PIXEL_RATE_DIV_BY_1;
*k2_div = PIXEL_RATE_DIV_BY_4;
- if (odm_combine_factor == 2)
- *k2_div = PIXEL_RATE_DIV_BY_2;
}
}
if ((*k1_div == PIXEL_RATE_DIV_NA) && (*k2_div == PIXEL_RATE_DIV_NA))
ASSERT(false);
-
- return odm_combine_factor;
}
void dcn314_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h
b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h
index eafcc4ea6d24..3841da67a737 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h
@@ -37,7 +37,7 @@ void dcn314_dsc_pg_control(struct dce_hwseq *hws, unsigned
int dsc_inst, bool po
void dcn314_enable_power_gating_plane(struct dce_hwseq *hws, bool enable);
-unsigned int dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx,
unsigned int *k1_div, unsigned int *k2_div);
+void dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned
int *k1_div, unsigned int *k2_div);
void dcn314_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
index e5bd76c6b1d3..c586468872e2 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
@@ -1141,10 +1141,9 @@ void dcn32_update_odm(struct dc *dc, struct dc_state
*context, struct pipe_ctx *
}
}
-unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx,
unsigned int *k1_div, unsigned int *k2_div)
+void dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int
*k1_div, unsigned int *k2_div)
{
struc
[PATCH 20/20] drm/amd/display: 3.2.239
From: Aric Cyr This version brings along following fixes: - Improvement on eDP - PSR bug fixes - SubVP bug fixes - Improvements on pipe handling to address potential issues - Freesync bug fix - DPIA bug fix - Fix multi-display issues Acked-by: Stylon Wang Signed-off-by: Aric Cyr --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index a239dcd8e9fb..26d05e225088 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -45,7 +45,7 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.238" +#define DC_VER "3.2.239" #define MAX_SURFACES 3 #define MAX_PLANES 6 -- 2.40.1
RE: [PATCH] drm/dp_mst: Clear MSG_RDY flag before sending new message
[AMD Official Use Only - General]
Hi Lyude,
Much appreciated!
Will update and send out another version.
Thanks,
Wayne Lin
> -Original Message-
> From: Lyude Paul
> Sent: Wednesday, June 7, 2023 6:03 AM
> To: Lin, Wayne ; amd-gfx@lists.freedesktop.org
> Cc: ville.syrj...@linux.intel.com; jani.nik...@intel.com; imre.d...@intel.com;
> Wentland, Harry ; Zuo, Jerry
> ; sta...@vger.kernel.org
> Subject: Re: [PATCH] drm/dp_mst: Clear MSG_RDY flag before sending new
> message
>
> My apologies for taking so long to reply to this. I'll be honest - the last
> MST
> fiasco seriously burned me out big time, and I had to take a big step back
> from
> working on MST for a while. Comments below
>
> On Wed, 2023-05-31 at 12:00 +0800, Wayne Lin wrote:
> > [Why]
> > The sequence for collecting down_reply from source perspective should
> > be:
> >
> > Request_n->repeat (get partial reply of Request_n->clear message ready
> > flag to ack DPRX that the message is received) till all partial
> > replies for Request_n are received->new Request_n+1.
> >
> > Now there is chance that drm_dp_mst_hpd_irq() will fire new down
> > request in the tx queue when the down reply is incomplete. Source is
> > restricted to generate interveleaved message transactions so we should
> > avoid it.
> >
> > Also, while assembling partial reply packets, reading out DPCD
> > DOWN_REP Sideband MSG buffer + clearing DOWN_REP_MSG_RDY flag
> should
> > be wrapped up as a complete operation for reading out a reply packet.
> > Kicking off a new request before clearing DOWN_REP_MSG_RDY flag might
> > be risky. e.g. If the reply of the new request has overwritten the
> > DPRX DOWN_REP Sideband MSG buffer before source writing one to clear
> > DOWN_REP_MSG_RDY flag, source then unintentionally flushes the reply
> > for the new request. Should handle the up request in the same way.
> >
> > [How]
> > Separete drm_dp_mst_hpd_irq() into 2 steps. After acking the MST IRQ
> > event, driver calls drm_dp_mst_hpd_irq_send_new_request() and might
> > trigger drm_dp_mst_kick_tx() only when there is no on going message
> > transaction.
> >
> > Changes since v1:
> > * Reworked on review comments received
> > -> Adjust the fix to let driver explicitly kick off new down request
> > when mst irq event is handled and acked
> > -> Adjust the commit message
> >
> > Changes since v2:
> > * Adjust the commit message
> > * Adjust the naming of the divided 2 functions and add a new input
> > parameter "ack".
> > * Adjust code flow as per review comments.
> >
> > Signed-off-by: Wayne Lin
> > Cc: sta...@vger.kernel.org
> > ---
> > .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 33 +-
> --
> > drivers/gpu/drm/display/drm_dp_mst_topology.c | 39
> +--
> > drivers/gpu/drm/i915/display/intel_dp.c | 7 ++--
> > drivers/gpu/drm/nouveau/dispnv50/disp.c | 12 --
> > include/drm/display/drm_dp_mst_helper.h | 7 +++-
> > 5 files changed, 70 insertions(+), 28 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > index d5cec03eaa8d..597c3368bcfb 100644
> > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > @@ -3236,6 +3236,7 @@ static void dm_handle_mst_sideband_msg(struct
> > amdgpu_dm_connector *aconnector) {
> > u8 esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
> > u8 dret;
> > + u8 ack;
> > bool new_irq_handled = false;
> > int dpcd_addr;
> > int dpcd_bytes_to_read;
> > @@ -3265,34 +3266,36 @@ static void
> dm_handle_mst_sideband_msg(struct amdgpu_dm_connector *aconnector)
> > process_count < max_process_count) {
> > u8 retry;
> > dret = 0;
> > + ack = 0;
> >
> > process_count++;
> >
> > DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0],
> esi[1], esi[2]);
> > /* handle HPD short pulse irq */
> > if (aconnector->mst_mgr.mst_state)
> > - drm_dp_mst_hpd_irq(
> > - &aconnector->mst_mgr,
> > - esi,
> > - &new_irq_handled);
> > + drm_dp_mst_hpd_irq_handle_event(&aconnector-
> >mst_mgr,
> > + esi,
> > + &ack,
> > + &new_irq_handled);
> >
> > if (new_irq_handled) {
> > /* ACK at DPCD to notify down stream */
> > - const int ack_dpcd_bytes_to_write =
> > - dpcd_bytes_to_read - 1;
> > -
> > for (retry = 0; retry < 3; retry++) {
> > - u8 wret;
> > -
> > - wret = drm_dp_dpcd_write(
> > - &aconnector->dm_dp_aux.aux,
> > -
Re: [PATCH] drm/amdgpu: add missing radeon secondary PCI ID
On 6/6/23 17:36, Alex Deucher wrote:
> 0x5b70 is a missing RV370 secondary id. Add it so
> we don't try and probe it with amdgpu.
>
> Cc: mic...@daenzer.net
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index 7489b2b1a0d0..b8a1e4571cd9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -1640,6 +1640,7 @@ static const u16 amdgpu_unsupported_pciidlist[] = {
> 0x5874,
> 0x5940,
> 0x5941,
> + 0x5b70,
> 0x5b72,
> 0x5b73,
> 0x5b74,
Reviewed-by: Michel Dänzer
Tested-by: Michel Dänzer
Thanks!
--
Earthling Michel Dänzer| https://redhat.com
Libre software enthusiast | Mesa and Xwayland developer
Re: [PATCH v2] drm/amdgpu: Increase hmm range get pages timeout
Am 2023-06-06 um 18:53 schrieb Philip Yang:
If hmm_range_fault returns -EBUSY, we should call hmm_range_fault again
to validate the remaining pages. On one system with NUMA auto balancing
enabled, hmm_range_fault takes 6 seconds for 1GB range because CPU
migrate the range one page at a time. To be safe, increase timeout value
to 1 second for 128MB range.
Signed-off-by: Philip Yang
Reviewed-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c
index 2dadcfe43d03..081267161d40 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c
@@ -190,8 +190,8 @@ int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier
*notifier,
pr_debug("hmm range: start = 0x%lx, end = 0x%lx",
hmm_range->start, hmm_range->end);
- /* Assuming 512MB takes maxmium 1 second to fault page address */
- timeout = max((hmm_range->end - hmm_range->start) >> 29, 1UL);
+ /* Assuming 128MB takes maximum 1 second to fault page address
*/
+ timeout = max((hmm_range->end - hmm_range->start) >> 27, 1UL);
timeout *= HMM_RANGE_DEFAULT_TIMEOUT;
timeout = jiffies + msecs_to_jiffies(timeout);
Re: [PATCH] drm/amd/pm: enable more Pstates profile levels for yellow_carp
[AMD Official Use Only - General]
Hi Shikai,
Comments inline.
From: Guo, Shikai
Sent: Wednesday, June 7, 2023 7:07 PM
To: amd-gfx@lists.freedesktop.org
Cc: Liang, Prike ; Liu, Aaron ; Huang,
Tim ; Guo, Shikai
Subject: [PATCH] drm/amd/pm: enable more Pstates profile levels for yellow_carp
This patch enables following UMD stable Pstates profile levels for
power_dpm_force_performance_level interface.
- profile_peak
- profile_min_mclk
- profile_min_sclk
- profile_standard
Signed-off-by: shikaguo
---
.../drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c | 94 ++-
.../drm/amd/pm/swsmu/smu13/yellow_carp_ppt.h | 8 +-
2 files changed, 98 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
index a92da336ecec..5c968ab2ea8d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
@@ -957,6 +957,9 @@ static int yellow_carp_set_soft_freq_limited_range(struct
smu_context *smu,
uint32_t max)
{
enum smu_message_type msg_set_min, msg_set_max;
+ uint32_t min_clk = min;
+ uint32_t max_clk = max;
+
int ret = 0;
if (!yellow_carp_clk_dpm_is_enabled(smu, clk_type))
@@ -985,11 +988,17 @@ static int yellow_carp_set_soft_freq_limited_range(struct
smu_context *smu,
return -EINVAL;
}
- ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_min, min, NULL);
+ if (clk_type == SMU_VCLK) {
+ min_clk = min << SMU_13_VCLK_SHIFT;
+ max_clk = max << SMU_13_VCLK_SHIFT;
+ }
+
+ ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_min, min_clk, NULL);
+
if (ret)
goto out;
- ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_max, max, NULL);
+ ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_max, max_clk, NULL);
if (ret)
goto out;
@@ -1107,6 +1116,50 @@ static int yellow_carp_force_clk_levels(struct
smu_context *smu,
return ret;
}
+static int yellow_carp_get_dpm_profile_freq(struct smu_context *smu,
+ enum amd_dpm_forced_level level,
+ enum smu_clk_type clk_type,
+ uint32_t *min_clk,
+ uint32_t *max_clk)
+{
+ int ret = 0;
+ uint32_t clk_limit = 0;
+
+ switch (clk_type) {
+ case SMU_GFXCLK:
+ case SMU_SCLK:
+ clk_limit = YELLOW_CARP_UMD_PSTATE_GFXCLK;
+ if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
+ yellow_carp_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL,
&clk_limit);
+ else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK)
+ yellow_carp_get_dpm_ultimate_freq(smu, SMU_SCLK,
&clk_limit, NULL);
+ break;
+ case SMU_SOCCLK:
+ clk_limit = YELLOW_CARP_UMD_PSTATE_SOCCLK;
+ if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
+ yellow_carp_get_dpm_ultimate_freq(smu, SMU_SOCCLK,
NULL, &clk_limit);
+ break;
+ case SMU_FCLK:
+ clk_limit = YELLOW_CARP_UMD_PSTATE_FCLK;
+ if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
+ yellow_carp_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL,
&clk_limit);
+ else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK)
+ yellow_carp_get_dpm_ultimate_freq(smu, SMU_FCLK,
&clk_limit, NULL);
+ break;
+ case SMU_VCLK:
+ yellow_carp_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL,
&clk_limit);
+ break;
+ case SMU_DCLK:
+ yellow_carp_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL,
&clk_limit);
+ break;
+ default:
+ ret = -EINVAL;
+ break;
+ }
+ *min_clk = *max_clk = clk_limit;
+ return ret;
+}
+
static int yellow_carp_set_performance_level(struct smu_context *smu,
enum amd_dpm_forced_level
level)
{
@@ -1114,6 +1167,9 @@ static int yellow_carp_set_performance_level(struct
smu_context *smu,
uint32_t sclk_min = 0, sclk_max = 0;
uint32_t fclk_min = 0, fclk_max = 0;
uint32_t socclk_min = 0, socclk_max = 0;
+ uint32_t vclk_min = 0, vclk_max = 0;
+ uint32_t dclk_min = 0, dclk_max = 0;
+
int ret = 0;
switch (level) {
@@ -1121,28 +1177,42 @@ static int yellow_carp_set_performance_level(struct
smu_context *smu,
yellow_carp_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL,
&sclk_max);
yellow_carp_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL,
&fclk_max);
yellow_carp_get_
Re: [PATCH v2 06/07] drm/amdgpu: add option params to enforce process isolation between graphics and compute
I can't see the other patches in this series, so I'm missing some
context. I don't understand what "process isolation between graphics and
compute" means here. It seems to be unrelated to KFD compute. This patch
seems to be mostly about handling of reserved VMIDs. Maybe you're trying
to avoid running Vulcan graphics and compute concurrently? But this does
not prevent concurrency with KFD compute.
Can you clarify what this is for?
Thanks,
Felix
Am 2023-06-07 um 06:57 schrieb Chong Li:
enforce process isolation between graphics and compute via using the same
reserved vmid.
v2: remove params "struct amdgpu_vm *vm" from
amdgpu_vmid_alloc_reserved and amdgpu_vmid_free_reserved.
Signed-off-by: Chong Li
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 10 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c | 17 +++--
drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h | 6 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 22 +-
5 files changed, 36 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index ce196badf42d..ef098a7287d0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -215,6 +215,7 @@ extern int amdgpu_force_asic_type;
extern int amdgpu_smartshift_bias;
extern int amdgpu_use_xgmi_p2p;
extern int amdgpu_mtype_local;
+extern bool enforce_isolation;
#ifdef CONFIG_HSA_AMD
extern int sched_policy;
extern bool debug_evictions;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 3d91e123f9bd..fdb6fb8229ab 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -153,7 +153,7 @@ uint amdgpu_pg_mask = 0x;
uint amdgpu_sdma_phase_quantum = 32;
char *amdgpu_disable_cu;
char *amdgpu_virtual_display;
-
+bool enforce_isolation;
/*
* OverDrive(bit 14) disabled by default
* GFX DCS(bit 19) disabled by default
@@ -973,6 +973,14 @@ MODULE_PARM_DESC(
4 =
AMDGPU_CPX_PARTITION_MODE)");
module_param_named(user_partt_mode, amdgpu_user_partt_mode, uint, 0444);
+
+/**
+ * DOC: enforce_isolation (bool)
+ * enforce process isolation between graphics and compute via using the same
reserved vmid.
+ */
+module_param(enforce_isolation, bool, 0444);
+MODULE_PARM_DESC(enforce_isolation, "enforce process isolation between graphics and
compute . enforce_isolation = on");
+
/* These devices are not supported by amdgpu.
* They are supported by the mach64, r128, radeon drivers
*/
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
index c991ca0b7a1c..ff1ea99292fb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
@@ -409,7 +409,7 @@ int amdgpu_vmid_grab(struct amdgpu_vm *vm, struct
amdgpu_ring *ring,
if (r || !idle)
goto error;
- if (vm->reserved_vmid[vmhub]) {
+ if (vm->reserved_vmid[vmhub] || (enforce_isolation && (vmhub ==
AMDGPU_GFXHUB(0 {
r = amdgpu_vmid_grab_reserved(vm, ring, job, &id, fence);
if (r || !id)
goto error;
@@ -460,14 +460,11 @@ int amdgpu_vmid_grab(struct amdgpu_vm *vm, struct
amdgpu_ring *ring,
}
int amdgpu_vmid_alloc_reserved(struct amdgpu_device *adev,
- struct amdgpu_vm *vm,
unsigned vmhub)
{
struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
mutex_lock(&id_mgr->lock);
- if (vm->reserved_vmid[vmhub])
- goto unlock;
++id_mgr->reserved_use_count;
if (!id_mgr->reserved) {
@@ -479,27 +476,23 @@ int amdgpu_vmid_alloc_reserved(struct amdgpu_device *adev,
list_del_init(&id->list);
id_mgr->reserved = id;
}
- vm->reserved_vmid[vmhub] = true;
-unlock:
mutex_unlock(&id_mgr->lock);
return 0;
}
void amdgpu_vmid_free_reserved(struct amdgpu_device *adev,
- struct amdgpu_vm *vm,
unsigned vmhub)
{
struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
mutex_lock(&id_mgr->lock);
- if (vm->reserved_vmid[vmhub] &&
- !--id_mgr->reserved_use_count) {
+ if (!--id_mgr->reserved_use_count) {
/* give the reserved ID back to normal round robin */
list_add(&id_mgr->reserved->list, &id_mgr->ids_lru);
id_mgr->reserved = NULL;
}
- vm->reserved_vmid[vmhub] = false;
+
mutex_unlock(&id_mgr->lock);
}
@@ -578,6 +571,10 @@ void amdgpu_vmid_mgr_init(struct amdgpu_device *adev)
list_add_tail(&id_mgr->ids[j].list, &id_mgr->ids_lru);
}
}
+
[PATCH] drm/amdgpu: Fix memcpy() in sienna_cichlid_append_powerplay_table function.
Fixes the following gcc with W=1:
In file included from ./include/linux/string.h:253,
from ./include/linux/bitmap.h:11,
from ./include/linux/cpumask.h:12,
from ./arch/x86/include/asm/cpumask.h:5,
from ./arch/x86/include/asm/msr.h:11,
from ./arch/x86/include/asm/processor.h:22,
from ./arch/x86/include/asm/cpufeature.h:5,
from ./arch/x86/include/asm/thread_info.h:53,
from ./include/linux/thread_info.h:60,
from ./arch/x86/include/asm/preempt.h:7,
from ./include/linux/preempt.h:78,
from ./include/linux/spinlock.h:56,
from ./include/linux/mmzone.h:8,
from ./include/linux/gfp.h:7,
from ./include/linux/firmware.h:7,
from
drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/sienna_cichlid_ppt.c:26:
In function ‘fortify_memcpy_chk’,
inlined from ‘sienna_cichlid_append_powerplay_table’ at
drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/sienna_cichlid_ppt.c:444:2,
inlined from ‘sienna_cichlid_setup_pptable’ at
drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/sienna_cichlid_ppt.c:506:8,
inlined from ‘sienna_cichlid_setup_pptable’ at
drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/sienna_cichlid_ppt.c:494:12:
./include/linux/fortify-string.h:413:4: warning: call to
‘__read_overflow2_field’ declared with attribute warning: detected read beyond
size of field (2nd parameter); maybe use struct_group()? [-Wattribute-warning]
413 |__read_overflow2_field(q_size_field, size);
|^~
^~
the compiler complains about the size calculation in the memcpy() -
"sizeof(*smc_dpm_table) - sizeof(smc_dpm_table->table_header)" is much
larger than what fits into table_member.
proposing "sizeof(smc_dpm_table->I2cControllers)", instead of
"sizeof(*smc_dpm_table) - sizeof(smc_dpm_table->table_header)"
'Fixes: 7077b19a38240 ("drm/amd/pm: use macro to get pptable members")'
Cc: Chengming Gui
Cc: Christian König
Cc: Alex Deucher
Signed-off-by: Srinivasan Shanmugam
---
drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 85d53597eb07..29a34160dedb 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -442,7 +442,7 @@ static int sienna_cichlid_append_powerplay_table(struct
smu_context *smu)
return ret;
GET_PPTABLE_MEMBER(I2cControllers, &table_member);
memcpy(table_member, smc_dpm_table->I2cControllers,
- sizeof(*smc_dpm_table) -
sizeof(smc_dpm_table->table_header));
+ sizeof(smc_dpm_table->I2cControllers));
return 0;
}
--
2.25.1
[PATCH] drm/amdkfd: fix vmfault signalling with additional data.
Exception handling for vmfaults should be raised with additional data.
Reported-by: Mukul Joshi
Signed-off-by: Jonathan Kim
---
drivers/gpu/drm/amd/amdkfd/kfd_events.c | 34 +++--
1 file changed, 20 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_events.c
b/drivers/gpu/drm/amd/amdkfd/kfd_events.c
index 7ff5c4e1b7e2..c069ef77daa5 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_events.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_events.c
@@ -1240,19 +1240,24 @@ void kfd_signal_vm_fault_event(struct kfd_node *dev,
u32 pasid,
return;
}
- memset(&memory_exception_data, 0, sizeof(memory_exception_data));
- memory_exception_data.gpu_id = user_gpu_id;
- memory_exception_data.failure.imprecise = true;
- /* Set failure reason */
- if (info) {
- memory_exception_data.va = (info->page_addr) << PAGE_SHIFT;
- memory_exception_data.failure.NotPresent =
- info->prot_valid ? 1 : 0;
- memory_exception_data.failure.NoExecute =
- info->prot_exec ? 1 : 0;
- memory_exception_data.failure.ReadOnly =
- info->prot_write ? 1 : 0;
- memory_exception_data.failure.imprecise = 0;
+ /* SoC15 chips and onwards will pass in data from now on. */
+ if (!data) {
+ memset(&memory_exception_data, 0,
sizeof(memory_exception_data));
+ memory_exception_data.gpu_id = user_gpu_id;
+ memory_exception_data.failure.imprecise = true;
+
+ /* Set failure reason */
+ if (info) {
+ memory_exception_data.va = (info->page_addr) <<
+ PAGE_SHIFT;
+ memory_exception_data.failure.NotPresent =
+ info->prot_valid ? 1 : 0;
+ memory_exception_data.failure.NoExecute =
+ info->prot_exec ? 1 : 0;
+ memory_exception_data.failure.ReadOnly =
+ info->prot_write ? 1 : 0;
+ memory_exception_data.failure.imprecise = 0;
+ }
}
rcu_read_lock();
@@ -1261,7 +1266,8 @@ void kfd_signal_vm_fault_event(struct kfd_node *dev, u32
pasid,
idr_for_each_entry_continue(&p->event_idr, ev, id)
if (ev->type == KFD_EVENT_TYPE_MEMORY) {
spin_lock(&ev->lock);
- ev->memory_exception_data = memory_exception_data;
+ ev->memory_exception_data = data ? *data :
+ memory_exception_data;
set_event(ev);
spin_unlock(&ev->lock);
}
--
2.25.1
RE: [PATCH] drm/amdkfd: fix vmfault signalling with additional data.
[AMD Official Use Only - General]
Reviewed-by: Mukul Joshi
> -Original Message-
> From: Kim, Jonathan
> Sent: Wednesday, June 7, 2023 10:39 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Joshi, Mukul ; Kuehling, Felix
> ; Kim, Jonathan ;
> Joshi, Mukul
> Subject: [PATCH] drm/amdkfd: fix vmfault signalling with additional data.
>
> Exception handling for vmfaults should be raised with additional data.
>
> Reported-by: Mukul Joshi
> Signed-off-by: Jonathan Kim
> ---
> drivers/gpu/drm/amd/amdkfd/kfd_events.c | 34 +++
> --
> 1 file changed, 20 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_events.c
> b/drivers/gpu/drm/amd/amdkfd/kfd_events.c
> index 7ff5c4e1b7e2..c069ef77daa5 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_events.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_events.c
> @@ -1240,19 +1240,24 @@ void kfd_signal_vm_fault_event(struct kfd_node
> *dev, u32 pasid,
> return;
> }
>
> - memset(&memory_exception_data, 0,
> sizeof(memory_exception_data));
> - memory_exception_data.gpu_id = user_gpu_id;
> - memory_exception_data.failure.imprecise = true;
> - /* Set failure reason */
> - if (info) {
> - memory_exception_data.va = (info->page_addr) <<
> PAGE_SHIFT;
> - memory_exception_data.failure.NotPresent =
> - info->prot_valid ? 1 : 0;
> - memory_exception_data.failure.NoExecute =
> - info->prot_exec ? 1 : 0;
> - memory_exception_data.failure.ReadOnly =
> - info->prot_write ? 1 : 0;
> - memory_exception_data.failure.imprecise = 0;
> + /* SoC15 chips and onwards will pass in data from now on. */
> + if (!data) {
> + memset(&memory_exception_data, 0,
> sizeof(memory_exception_data));
> + memory_exception_data.gpu_id = user_gpu_id;
> + memory_exception_data.failure.imprecise = true;
> +
> + /* Set failure reason */
> + if (info) {
> + memory_exception_data.va = (info->page_addr) <<
> + PAGE_SHIFT;
> + memory_exception_data.failure.NotPresent =
> + info->prot_valid ? 1 : 0;
> + memory_exception_data.failure.NoExecute =
> + info->prot_exec ? 1 : 0;
> + memory_exception_data.failure.ReadOnly =
> + info->prot_write ? 1 : 0;
> + memory_exception_data.failure.imprecise = 0;
> + }
> }
>
> rcu_read_lock();
> @@ -1261,7 +1266,8 @@ void kfd_signal_vm_fault_event(struct kfd_node
> *dev, u32 pasid,
> idr_for_each_entry_continue(&p->event_idr, ev, id)
> if (ev->type == KFD_EVENT_TYPE_MEMORY) {
> spin_lock(&ev->lock);
> - ev->memory_exception_data =
> memory_exception_data;
> + ev->memory_exception_data = data ? *data :
> +
> memory_exception_data;
> set_event(ev);
> spin_unlock(&ev->lock);
> }
> --
> 2.25.1
[PATCH v6 01/13] drm/connector: Convert DRM_MODE_COLORIMETRY to enum
This allows us to use strongly typed arguments.
v2:
- Bring NO_DATA back
- Provide explicit enum values
v3:
- Drop unnecessary '&' from kerneldoc (emersion)
v4:
- Fix Normal Colorimetry comment
Signed-off-by: Harry Wentland
Reviewed-by: Simon Ser
Reviewed-by: Sebastian Wick
Reviewed-by: Pekka Paalanen
Reviewed-by: Joshua Ashton
Cc: Pekka Paalanen
Cc: Sebastian Wick
Cc: vitaly.pros...@amd.com
Cc: Uma Shankar
Cc: Ville Syrjälä
Cc: Joshua Ashton
Cc: Simon Ser
Cc: Ville Syrjälä
Cc: Melissa Wen
Cc: dri-de...@lists.freedesktop.org
Cc: amd-gfx@lists.freedesktop.org
---
include/drm/display/drm_dp.h | 2 +-
include/drm/drm_connector.h | 49 ++--
2 files changed, 26 insertions(+), 25 deletions(-)
diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index f1be179c5f1f..7f858352cb43 100644
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -1626,7 +1626,7 @@ enum dp_pixelformat {
*
* This enum is used to indicate DP VSC SDP Colorimetry formats.
* It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
- * DB18] and a name of enum member follows DRM_MODE_COLORIMETRY definition.
+ * DB18] and a name of enum member follows enum drm_colorimetry definition.
*
* @DP_COLORIMETRY_DEFAULT: sRGB (IEC 61966-2-1) or
* ITU-R BT.601 colorimetry format
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index 565cf9d3c550..77401e425341 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -371,29 +371,30 @@ enum drm_privacy_screen_status {
* a colorspace property which will be created and exposed to
* userspace.
*/
-
-/* For Default case, driver will set the colorspace */
-#define DRM_MODE_COLORIMETRY_DEFAULT 0
-/* CEA 861 Normal Colorimetry options */
-#define DRM_MODE_COLORIMETRY_NO_DATA 0
-#define DRM_MODE_COLORIMETRY_SMPTE_170M_YCC1
-#define DRM_MODE_COLORIMETRY_BT709_YCC 2
-/* CEA 861 Extended Colorimetry Options */
-#define DRM_MODE_COLORIMETRY_XVYCC_601 3
-#define DRM_MODE_COLORIMETRY_XVYCC_709 4
-#define DRM_MODE_COLORIMETRY_SYCC_601 5
-#define DRM_MODE_COLORIMETRY_OPYCC_601 6
-#define DRM_MODE_COLORIMETRY_OPRGB 7
-#define DRM_MODE_COLORIMETRY_BT2020_CYCC 8
-#define DRM_MODE_COLORIMETRY_BT2020_RGB9
-#define DRM_MODE_COLORIMETRY_BT2020_YCC10
-/* Additional Colorimetry extension added as part of CTA 861.G */
-#define DRM_MODE_COLORIMETRY_DCI_P3_RGB_D6511
-#define DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER12
-/* Additional Colorimetry Options added for DP 1.4a VSC Colorimetry Format */
-#define DRM_MODE_COLORIMETRY_RGB_WIDE_FIXED13
-#define DRM_MODE_COLORIMETRY_RGB_WIDE_FLOAT14
-#define DRM_MODE_COLORIMETRY_BT601_YCC 15
+enum drm_colorspace {
+ /* For Default case, driver will set the colorspace */
+ DRM_MODE_COLORIMETRY_DEFAULT= 0,
+ /* CEA 861 Normal Colorimetry options */
+ DRM_MODE_COLORIMETRY_NO_DATA= 0,
+ DRM_MODE_COLORIMETRY_SMPTE_170M_YCC = 1,
+ DRM_MODE_COLORIMETRY_BT709_YCC = 2,
+ /* CEA 861 Extended Colorimetry Options */
+ DRM_MODE_COLORIMETRY_XVYCC_601 = 3,
+ DRM_MODE_COLORIMETRY_XVYCC_709 = 4,
+ DRM_MODE_COLORIMETRY_SYCC_601 = 5,
+ DRM_MODE_COLORIMETRY_OPYCC_601 = 6,
+ DRM_MODE_COLORIMETRY_OPRGB = 7,
+ DRM_MODE_COLORIMETRY_BT2020_CYCC= 8,
+ DRM_MODE_COLORIMETRY_BT2020_RGB = 9,
+ DRM_MODE_COLORIMETRY_BT2020_YCC = 10,
+ /* Additional Colorimetry extension added as part of CTA 861.G */
+ DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65 = 11,
+ DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER = 12,
+ /* Additional Colorimetry Options added for DP 1.4a VSC Colorimetry
Format */
+ DRM_MODE_COLORIMETRY_RGB_WIDE_FIXED = 13,
+ DRM_MODE_COLORIMETRY_RGB_WIDE_FLOAT = 14,
+ DRM_MODE_COLORIMETRY_BT601_YCC = 15,
+};
/**
* enum drm_bus_flags - bus_flags info for &drm_display_info
@@ -828,7 +829,7 @@ struct drm_connector_state {
* colorspace change on Sink. This is most commonly used to switch
* to wider color gamuts like BT2020.
*/
- u32 colorspace;
+ enum drm_colorspace colorspace;
/**
* @writeback_job: Writeback job for writeback connectors
--
2.41.0
[PATCH v6 00/13] Enable Colorspace connector property in amdgpu
This patchset is based on Joshua's previous patchset [1], as well as my previous patchset [2]. It is - enabling support for the colorspace property in amdgpu, as well as - allowing drivers to specify the supported set of colorspaces, and Colorspace, Infoframes, and YCbCr matrix --- Even though the initial intent of the colorspace property was to set the colorspace field in the respective HDMI AVI and DP SDP infoframes that is not sufficient in all scenarios. For DP the colorspace information also affects the MSA (main stream attribute) packet. For YUV output the colorspace affects the RGB-to-YCbCr conversion matrix. The colorspace field of the infopackets also depends on the encoding used, which is something that is decided by the driver and not known to userspace. For these reasons a driver will need to be able to select the supported colorspaces at property creation. Note: There seems to be an understanding that the colorspace property should ONLY modify the infoframe. While this is current behavior and sufficient in some cases it is nowhere specified that this should be the only use of this property. As outlined above this limitation is not going to work in all cases. This patchset does not affect current behavior for the drivers that implement this property: i915 and vc4. In the future we might want to give userspace control over the encoding format on the wire, in particular to avoid use of YUV420 when image fidelity is important. This work would likely go hand in hand with a min_bpc property and wouldn't conflict with the work done in this patchset. I would expect this future work to tag along with a drm_crtc or drm_connector's Color Pipeline, similar to the one propsed for drm_plane [3]. Colorspace on crtc or connector? There have been suggestions of programming 'colorspace' on the drm_crtc but I don't think the crtc is the right place for this property. The drm_plane and drm_crtc will be used to offload color processing that would normally be done via the GFX or other pipelines. The drm_connector controls the signalling with the display and ensures the wire format is appropriate for the encoding by programming the RGB-to-YCbCr matrix. [1] https://patchwork.freedesktop.org/series/113632/ [2] https://patchwork.freedesktop.org/series/111865/ [3] https://lists.freedesktop.org/archives/dri-devel/2023-May/403173.html v2: - Tested with DP and HDMI analyzers - Confirmed driver will fallback to lower bpc when needed - Dropped hunk to set HDMI AVI infoframe as it was a no-op - Fixed BT.2020 YCbCr colorimetry (JoshuaAshton) - Simplify initialization of supported colorspaces (Jani) - Fix kerneldoc (kernel test robot) v3: - Added documentation for colorspaces (Pekka, Joshua) - Split 'Allow drivers to pass list of supported colorspaces' patch to pull out code to create common colorspace array and keep it separate from change to create only supported colorspaces v4: - Don't "deprecate" existing enum values - Fixes based on review comments throughout - Dropped Josh's RBs v5: - Add documentation that drivers are free to pick appropriate RGB or YCC variant v6: - Remove magic when drivers pass '0' as supported_colorspaces to indicate default support for all DP/HDMI colorspaces Cc: Pekka Paalanen Cc: Sebastian Wick Cc: vitaly.pros...@amd.com Cc: Uma Shankar Cc: Ville Syrjälä Cc: Joshua Ashton Cc: Jani Nikula Cc: Michel Dänzer Cc: Simon Ser Cc: Melissa Wen Cc: dri-de...@lists.freedesktop.org Cc: amd-gfx@lists.freedesktop.org Harry Wentland (10): drm/connector: Convert DRM_MODE_COLORIMETRY to enum drm/connector: Pull out common create_colorspace_property code drm/connector: Use common colorspace_names array drm/connector: Print connector colorspace in state debugfs drm/connector: Allow drivers to pass list of supported colorspaces drm/amd/display: Always pass connector_state to stream validation drm/amd/display: Register Colorspace property for DP and HDMI drm/amd/display: Signal mode_changed if colorspace changed drm/amd/display: Send correct DP colorspace infopacket drm/amd/display: Add debugfs for testing output colorspace Joshua Ashton (3): drm/connector: Add enum documentation to drm_colorspace drm/amd/display: Always set crtcinfo from create_stream_for_sink drm/amd/display: Refactor avi_info_frame colorimetry determination .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 84 +--- .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 57 ++ .../gpu/drm/amd/display/dc/core/dc_resource.c | 28 ++- drivers/gpu/drm/drm_atomic.c | 1 + drivers/gpu/drm/drm_connector.c | 189 +++--- .../gpu/drm/i915/display/intel_connector.c| 4 +- drivers/gpu/drm/vc4/vc4_hdmi.c| 2 +- include/drm/display/drm_dp.h | 2 +- include/drm/drm_connector.h | 129 +--- 9 files changed, 363 insertions(
[PATCH v6 02/13] drm/connector: Add enum documentation to drm_colorspace
From: Joshua Ashton
To match the other enums, and add more information about these values.
v2:
- Specify where an enum entry comes from
- Clarify DEFAULT and NO_DATA behavior
- BT.2020 CYCC is "constant luminance"
- correct type for BT.601
v4:
- drop DP/HDMI clarifications that might create
more questions than answers
v5:
- Add note on YCC and RGB variants
Signed-off-by: Joshua Ashton
Signed-off-by: Harry Wentland
Reviewed-by: Harry Wentland
Reviewed-by: Sebastian Wick
Acked-by: Pekka Paalanen
Cc: Pekka Paalanen
Cc: Sebastian Wick
Cc: vitaly.pros...@amd.com
Cc: Uma Shankar
Cc: Ville Syrjälä
Cc: Joshua Ashton
Cc: Simon Ser
Cc: Ville Syrjälä
Cc: Melissa Wen
Cc: dri-de...@lists.freedesktop.org
Cc: amd-gfx@lists.freedesktop.org
---
include/drm/drm_connector.h | 70 +++--
1 file changed, 68 insertions(+), 2 deletions(-)
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index 77401e425341..907f40851e80 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -363,13 +363,79 @@ enum drm_privacy_screen_status {
PRIVACY_SCREEN_ENABLED_LOCKED,
};
-/*
- * This is a consolidated colorimetry list supported by HDMI and
+/**
+ * enum drm_colorspace - color space
+ *
+ * This enum is a consolidated colorimetry list supported by HDMI and
* DP protocol standard. The respective connectors will register
* a property with the subset of this list (supported by that
* respective protocol). Userspace will set the colorspace through
* a colorspace property which will be created and exposed to
* userspace.
+ *
+ * DP definitions come from the DP v2.0 spec
+ * HDMI definitions come from the CTA-861-H spec
+ *
+ * A note on YCC and RGB variants:
+ *
+ * Since userspace is not aware of the encoding on the wire
+ * (RGB or YCbCr), drivers are free to pick the appropriate
+ * variant, regardless of what userspace selects. E.g., if
+ * BT2020_RGB is selected by userspace a driver will pick
+ * BT2020_YCC if the encoding on the wire is YUV444 or YUV420.
+ *
+ * @DRM_MODE_COLORIMETRY_DEFAULT:
+ * Driver specific behavior.
+ * @DRM_MODE_COLORIMETRY_NO_DATA:
+ * Driver specific behavior.
+ * @DRM_MODE_COLORIMETRY_SMPTE_170M_YCC:
+ * (HDMI)
+ * SMPTE ST 170M colorimetry format
+ * @DRM_MODE_COLORIMETRY_BT709_YCC:
+ * (HDMI, DP)
+ * ITU-R BT.709 colorimetry format
+ * @DRM_MODE_COLORIMETRY_XVYCC_601:
+ * (HDMI, DP)
+ * xvYCC601 colorimetry format
+ * @DRM_MODE_COLORIMETRY_XVYCC_709:
+ * (HDMI, DP)
+ * xvYCC709 colorimetry format
+ * @DRM_MODE_COLORIMETRY_SYCC_601:
+ * (HDMI, DP)
+ * sYCC601 colorimetry format
+ * @DRM_MODE_COLORIMETRY_OPYCC_601:
+ * (HDMI, DP)
+ * opYCC601 colorimetry format
+ * @DRM_MODE_COLORIMETRY_OPRGB:
+ * (HDMI, DP)
+ * opRGB colorimetry format
+ * @DRM_MODE_COLORIMETRY_BT2020_CYCC:
+ * (HDMI, DP)
+ * ITU-R BT.2020 Y'c C'bc C'rc (constant luminance) colorimetry format
+ * @DRM_MODE_COLORIMETRY_BT2020_RGB:
+ * (HDMI, DP)
+ * ITU-R BT.2020 R' G' B' colorimetry format
+ * @DRM_MODE_COLORIMETRY_BT2020_YCC:
+ * (HDMI, DP)
+ * ITU-R BT.2020 Y' C'b C'r colorimetry format
+ * @DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
+ * (HDMI)
+ * SMPTE ST 2113 P3D65 colorimetry format
+ * @DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
+ * (HDMI)
+ * SMPTE ST 2113 P3DCI colorimetry format
+ * @DRM_MODE_COLORIMETRY_RGB_WIDE_FIXED:
+ * (DP)
+ * RGB wide gamut fixed point colorimetry format
+ * @DRM_MODE_COLORIMETRY_RGB_WIDE_FLOAT:
+ * (DP)
+ * RGB wide gamut floating point
+ * (scRGB (IEC 61966-2-2)) colorimetry format
+ * @DRM_MODE_COLORIMETRY_BT601_YCC:
+ * (DP)
+ * ITU-R BT.601 colorimetry format
+ * The DP spec does not say whether this is the 525 or the 625
+ * line version.
*/
enum drm_colorspace {
/* For Default case, driver will set the colorspace */
--
2.41.0
[PATCH v6 04/13] drm/connector: Use common colorspace_names array
We an use bitfields to track the support ones for HDMI
and DP. This allows us to print colorspaces in a consistent
manner without needing to know whether we're dealing with
DP or HDMI.
v4:
- Rename _MAX to _COUNT and leave comment to indicate
it's not a valid value
- Fix misplaced function doc
v6:
- Drop magic in drm_mode_create_colorspace_property for
dealing with "0" supported_colorspaces. Expect the caller
to always provide a non-zero supported_colorspaces.
- Improve error checking and logging
Signed-off-by: Harry Wentland
Reviewed-by: Sebastian Wick
Reviewed-by: Joshua Ashton
Cc: Pekka Paalanen
Cc: Sebastian Wick
Cc: vitaly.pros...@amd.com
Cc: Uma Shankar
Cc: Ville Syrjälä
Cc: Joshua Ashton
Cc: Jani Nikula
Cc: Simon Ser
Cc: Ville Syrjälä
Cc: Melissa Wen
Cc: dri-de...@lists.freedesktop.org
Cc: amd-gfx@lists.freedesktop.org
---
drivers/gpu/drm/drm_connector.c | 130 +++-
include/drm/drm_connector.h | 2 +
2 files changed, 79 insertions(+), 53 deletions(-)
diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index 9c087d6f5691..484effc731df 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -1016,64 +1016,70 @@ static const struct drm_prop_enum_list
drm_dp_subconnector_enum_list[] = {
DRM_ENUM_NAME_FN(drm_get_dp_subconnector_name,
drm_dp_subconnector_enum_list)
-static const struct drm_prop_enum_list hdmi_colorspaces[] = {
+
+static const char * const colorspace_names[] = {
/* For Default case, driver will set the colorspace */
- { DRM_MODE_COLORIMETRY_DEFAULT, "Default" },
+ [DRM_MODE_COLORIMETRY_DEFAULT] = "Default",
/* Standard Definition Colorimetry based on CEA 861 */
- { DRM_MODE_COLORIMETRY_SMPTE_170M_YCC, "SMPTE_170M_YCC" },
- { DRM_MODE_COLORIMETRY_BT709_YCC, "BT709_YCC" },
+ [DRM_MODE_COLORIMETRY_SMPTE_170M_YCC] = "SMPTE_170M_YCC",
+ [DRM_MODE_COLORIMETRY_BT709_YCC] = "BT709_YCC",
/* Standard Definition Colorimetry based on IEC 61966-2-4 */
- { DRM_MODE_COLORIMETRY_XVYCC_601, "XVYCC_601" },
+ [DRM_MODE_COLORIMETRY_XVYCC_601] = "XVYCC_601",
/* High Definition Colorimetry based on IEC 61966-2-4 */
- { DRM_MODE_COLORIMETRY_XVYCC_709, "XVYCC_709" },
+ [DRM_MODE_COLORIMETRY_XVYCC_709] = "XVYCC_709",
/* Colorimetry based on IEC 61966-2-1/Amendment 1 */
- { DRM_MODE_COLORIMETRY_SYCC_601, "SYCC_601" },
+ [DRM_MODE_COLORIMETRY_SYCC_601] = "SYCC_601",
/* Colorimetry based on IEC 61966-2-5 [33] */
- { DRM_MODE_COLORIMETRY_OPYCC_601, "opYCC_601" },
+ [DRM_MODE_COLORIMETRY_OPYCC_601] = "opYCC_601",
/* Colorimetry based on IEC 61966-2-5 */
- { DRM_MODE_COLORIMETRY_OPRGB, "opRGB" },
+ [DRM_MODE_COLORIMETRY_OPRGB] = "opRGB",
/* Colorimetry based on ITU-R BT.2020 */
- { DRM_MODE_COLORIMETRY_BT2020_CYCC, "BT2020_CYCC" },
+ [DRM_MODE_COLORIMETRY_BT2020_CYCC] = "BT2020_CYCC",
/* Colorimetry based on ITU-R BT.2020 */
- { DRM_MODE_COLORIMETRY_BT2020_RGB, "BT2020_RGB" },
+ [DRM_MODE_COLORIMETRY_BT2020_RGB] = "BT2020_RGB",
/* Colorimetry based on ITU-R BT.2020 */
- { DRM_MODE_COLORIMETRY_BT2020_YCC, "BT2020_YCC" },
+ [DRM_MODE_COLORIMETRY_BT2020_YCC] = "BT2020_YCC",
/* Added as part of Additional Colorimetry Extension in 861.G */
- { DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65, "DCI-P3_RGB_D65" },
- { DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER, "DCI-P3_RGB_Theater" },
+ [DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65] = "DCI-P3_RGB_D65",
+ [DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER] = "DCI-P3_RGB_Theater",
+ [DRM_MODE_COLORIMETRY_RGB_WIDE_FIXED] = "RGB_WIDE_FIXED",
+ /* Colorimetry based on scRGB (IEC 61966-2-2) */
+ [DRM_MODE_COLORIMETRY_RGB_WIDE_FLOAT] = "RGB_WIDE_FLOAT",
+ [DRM_MODE_COLORIMETRY_BT601_YCC] = "BT601_YCC",
};
+static const u32 hdmi_colorspaces =
+ BIT(DRM_MODE_COLORIMETRY_SMPTE_170M_YCC) |
+ BIT(DRM_MODE_COLORIMETRY_BT709_YCC) |
+ BIT(DRM_MODE_COLORIMETRY_XVYCC_601) |
+ BIT(DRM_MODE_COLORIMETRY_XVYCC_709) |
+ BIT(DRM_MODE_COLORIMETRY_SYCC_601) |
+ BIT(DRM_MODE_COLORIMETRY_OPYCC_601) |
+ BIT(DRM_MODE_COLORIMETRY_OPRGB) |
+ BIT(DRM_MODE_COLORIMETRY_BT2020_CYCC) |
+ BIT(DRM_MODE_COLORIMETRY_BT2020_RGB) |
+ BIT(DRM_MODE_COLORIMETRY_BT2020_YCC) |
+ BIT(DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65) |
+ BIT(DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER);
+
/*
* As per DP 1.4a spec, 2.2.5.7.5 VSC SDP Payload for Pixel
Encoding/Colorimetry
* Format Table 2-120
*/
-static const struct drm_prop_enum_list dp_colorspaces[] = {
- /* For Default case, driver will set the colorspace */
- { DRM_MODE_COLORIMETRY_DEFAULT, "Default" },
- { DRM_MODE_COLORIMETRY_RGB_WIDE_FIXED, "RGB_Wide_Gamut_Fixed_Point" },
- /* Colorimetry based on scRGB (IEC 61966-2-2)
[PATCH v6 03/13] drm/connector: Pull out common create_colorspace_property code
Signed-off-by: Harry Wentland
Reviewed-by: Sebastian Wick
Reviewed-by: Joshua Ashton
Cc: Pekka Paalanen
Cc: Sebastian Wick
Cc: vitaly.pros...@amd.com
Cc: Uma Shankar
Cc: Ville Syrjälä
Cc: Joshua Ashton
Cc: Jani Nikula
Cc: Simon Ser
Cc: Ville Syrjälä
Cc: Melissa Wen
Cc: dri-de...@lists.freedesktop.org
Cc: amd-gfx@lists.freedesktop.org
---
drivers/gpu/drm/drm_connector.c | 54 -
1 file changed, 27 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index 547356e00341..9c087d6f5691 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -1975,33 +1975,44 @@ EXPORT_SYMBOL(drm_mode_create_aspect_ratio_property);
* drm_mode_create_dp_colorspace_property() is used for DP connector.
*/
-/**
- * drm_mode_create_hdmi_colorspace_property - create hdmi colorspace property
- * @connector: connector to create the Colorspace property on.
- *
- * Called by a driver the first time it's needed, must be attached to desired
- * HDMI connectors.
- *
- * Returns:
- * Zero on success, negative errno on failure.
- */
-int drm_mode_create_hdmi_colorspace_property(struct drm_connector *connector)
+static int drm_mode_create_colorspace_property(struct drm_connector *connector,
+ const struct drm_prop_enum_list
*colorspaces,
+ int size)
{
struct drm_device *dev = connector->dev;
if (connector->colorspace_property)
return 0;
+ if (!colorspaces)
+ return 0;
+
connector->colorspace_property =
drm_property_create_enum(dev, DRM_MODE_PROP_ENUM, "Colorspace",
-hdmi_colorspaces,
-ARRAY_SIZE(hdmi_colorspaces));
+ colorspaces,
+ size);
if (!connector->colorspace_property)
return -ENOMEM;
return 0;
}
+/**
+ * drm_mode_create_hdmi_colorspace_property - create hdmi colorspace property
+ * @connector: connector to create the Colorspace property on.
+ *
+ * Called by a driver the first time it's needed, must be attached to desired
+ * HDMI connectors.
+ *
+ * Returns:
+ * Zero on success, negative errno on failure.
+ */
+int drm_mode_create_hdmi_colorspace_property(struct drm_connector *connector)
+{
+ return drm_mode_create_colorspace_property(connector,
+ hdmi_colorspaces,
+
ARRAY_SIZE(hdmi_colorspaces));
+}
EXPORT_SYMBOL(drm_mode_create_hdmi_colorspace_property);
/**
@@ -2016,20 +2027,9 @@ EXPORT_SYMBOL(drm_mode_create_hdmi_colorspace_property);
*/
int drm_mode_create_dp_colorspace_property(struct drm_connector *connector)
{
- struct drm_device *dev = connector->dev;
-
- if (connector->colorspace_property)
- return 0;
-
- connector->colorspace_property =
- drm_property_create_enum(dev, DRM_MODE_PROP_ENUM, "Colorspace",
-dp_colorspaces,
-ARRAY_SIZE(dp_colorspaces));
-
- if (!connector->colorspace_property)
- return -ENOMEM;
-
- return 0;
+ return drm_mode_create_colorspace_property(connector,
+ dp_colorspaces,
+ ARRAY_SIZE(dp_colorspaces));
}
EXPORT_SYMBOL(drm_mode_create_dp_colorspace_property);
--
2.41.0
[PATCH v6 08/13] drm/amd/display: Register Colorspace property for DP and HDMI
We want compositors to be able to set the output
colorspace on DP and HDMI outputs, based on the
caps reported from the receiver via EDID.
Signed-off-by: Harry Wentland
Reviewed-by: Joshua Ashton
Cc: Pekka Paalanen
Cc: Sebastian Wick
Cc: vitaly.pros...@amd.com
Cc: Joshua Ashton
Cc: Simon Ser
Cc: Ville Syrjälä
Cc: Melissa Wen
Cc: dri-de...@lists.freedesktop.org
Cc: amd-gfx@lists.freedesktop.org
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 27868dbb09f6..bdda136235af 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -7246,6 +7246,12 @@ static int amdgpu_dm_connector_get_modes(struct
drm_connector *connector)
return amdgpu_dm_connector->num_modes;
}
+static const u32 supported_colorspaces =
+ BIT(DRM_MODE_COLORIMETRY_BT709_YCC) |
+ BIT(DRM_MODE_COLORIMETRY_OPRGB) |
+ BIT(DRM_MODE_COLORIMETRY_BT2020_RGB) |
+ BIT(DRM_MODE_COLORIMETRY_BT2020_YCC);
+
void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
struct amdgpu_dm_connector *aconnector,
int connector_type,
@@ -7326,6 +7332,15 @@ void amdgpu_dm_connector_init_helper(struct
amdgpu_display_manager *dm,
adev->mode_info.abm_level_property, 0);
}
+ if (connector_type == DRM_MODE_CONNECTOR_HDMIA) {
+ if
(!drm_mode_create_hdmi_colorspace_property(&aconnector->base,
supported_colorspaces))
+
drm_connector_attach_colorspace_property(&aconnector->base);
+ } else if (connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
+ connector_type == DRM_MODE_CONNECTOR_eDP) {
+ if (!drm_mode_create_dp_colorspace_property(&aconnector->base,
supported_colorspaces))
+
drm_connector_attach_colorspace_property(&aconnector->base);
+ }
+
if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
connector_type == DRM_MODE_CONNECTOR_eDP) {
--
2.41.0
[PATCH v6 09/13] drm/amd/display: Signal mode_changed if colorspace changed
We need to signal mode_changed to make sure we update the output
colorspace.
v2: No need to call drm_hdmi_avi_infoframe_colorimetry as DC does its
own infoframe packing.
Signed-off-by: Harry Wentland
Reviewed-by: Leo Li
Reviewed-by: Joshua Ashton
Cc: Pekka Paalanen
Cc: Sebastian Wick
Cc: vitaly.pros...@amd.com
Cc: Uma Shankar
Cc: Joshua Ashton
Cc: Simon Ser
Cc: Melissa Wen
Cc: dri-de...@lists.freedesktop.org
Cc: amd-gfx@lists.freedesktop.org
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index bdda136235af..793ea29b4cfe 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -6699,6 +6699,14 @@ amdgpu_dm_connector_atomic_check(struct drm_connector
*conn,
if (!crtc)
return 0;
+ if (new_con_state->colorspace != old_con_state->colorspace) {
+ new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
+ if (IS_ERR(new_crtc_state))
+ return PTR_ERR(new_crtc_state);
+
+ new_crtc_state->mode_changed = true;
+ }
+
if (!drm_connector_atomic_hdr_metadata_equal(old_con_state,
new_con_state)) {
struct dc_info_packet hdr_infopacket;
@@ -6721,7 +6729,7 @@ amdgpu_dm_connector_atomic_check(struct drm_connector
*conn,
* set is permissible, however. So only force a
* modeset if we're entering or exiting HDR.
*/
- new_crtc_state->mode_changed =
+ new_crtc_state->mode_changed = new_crtc_state->mode_changed ||
!old_con_state->hdr_output_metadata ||
!new_con_state->hdr_output_metadata;
}
--
2.41.0
[PATCH v6 06/13] drm/connector: Allow drivers to pass list of supported colorspaces
Drivers might not support all colorspaces defined in
dp_colorspaces and hdmi_colorspaces. This results in
undefined behavior when userspace is setting an
unsupported colorspace.
Allow drivers to pass the list of supported colorspaces
when creating the colorspace property.
v2:
- Use 0 to indicate support for all colorspaces (Jani)
- Print drm_dbg_kms message when drivers pass 0
to signal that drivers should specify supported
colorspaecs explicity (Jani)
v3:
- Move changes to create a common colorspace_names array
to separate patch
v6:
- Avoid magic when passing 0 for supported_colorspaces;
be explicit in treating it as "all DP/HDMI"
Signed-off-by: Harry Wentland
Reviewed-by: Sebastian Wick
Reviewed-by: Joshua Ashton
Cc: Pekka Paalanen
Cc: Sebastian Wick
Cc: vitaly.pros...@amd.com
Cc: Uma Shankar
Cc: Ville Syrjälä
Cc: Joshua Ashton
Cc: Jani Nikula
Cc: Simon Ser
Cc: Ville Syrjälä
Cc: Melissa Wen
Cc: dri-de...@lists.freedesktop.org
Cc: amd-gfx@lists.freedesktop.org
---
drivers/gpu/drm/drm_connector.c | 24 +++
.../gpu/drm/i915/display/intel_connector.c| 4 ++--
drivers/gpu/drm/vc4/vc4_hdmi.c| 2 +-
include/drm/drm_connector.h | 7 --
4 files changed, 28 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index 46bf1f2ad535..8fe695047ced 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -2050,9 +2050,17 @@ static int drm_mode_create_colorspace_property(struct
drm_connector *connector,
* Returns:
* Zero on success, negative errno on failure.
*/
-int drm_mode_create_hdmi_colorspace_property(struct drm_connector *connector)
+int drm_mode_create_hdmi_colorspace_property(struct drm_connector *connector,
+u32 supported_colorspaces)
{
- return drm_mode_create_colorspace_property(connector, hdmi_colorspaces);
+ u32 colorspaces;
+
+ if (supported_colorspaces)
+ colorspaces = supported_colorspaces & hdmi_colorspaces;
+ else
+ colorspaces = hdmi_colorspaces;
+
+ return drm_mode_create_colorspace_property(connector, colorspaces);
}
EXPORT_SYMBOL(drm_mode_create_hdmi_colorspace_property);
@@ -2066,9 +2074,17 @@ EXPORT_SYMBOL(drm_mode_create_hdmi_colorspace_property);
* Returns:
* Zero on success, negative errno on failure.
*/
-int drm_mode_create_dp_colorspace_property(struct drm_connector *connector)
+int drm_mode_create_dp_colorspace_property(struct drm_connector *connector,
+ u32 supported_colorspaces)
{
- return drm_mode_create_colorspace_property(connector, dp_colorspaces);
+ u32 colorspaces;
+
+ if (supported_colorspaces)
+ colorspaces = supported_colorspaces & dp_colorspaces;
+ else
+ colorspaces = dp_colorspaces;
+
+ return drm_mode_create_colorspace_property(connector, colorspaces);
}
EXPORT_SYMBOL(drm_mode_create_dp_colorspace_property);
diff --git a/drivers/gpu/drm/i915/display/intel_connector.c
b/drivers/gpu/drm/i915/display/intel_connector.c
index 6205ddd3ded0..e8b4a352a7a6 100644
--- a/drivers/gpu/drm/i915/display/intel_connector.c
+++ b/drivers/gpu/drm/i915/display/intel_connector.c
@@ -283,14 +283,14 @@ intel_attach_aspect_ratio_property(struct drm_connector
*connector)
void
intel_attach_hdmi_colorspace_property(struct drm_connector *connector)
{
- if (!drm_mode_create_hdmi_colorspace_property(connector))
+ if (!drm_mode_create_hdmi_colorspace_property(connector, 0))
drm_connector_attach_colorspace_property(connector);
}
void
intel_attach_dp_colorspace_property(struct drm_connector *connector)
{
- if (!drm_mode_create_dp_colorspace_property(connector))
+ if (!drm_mode_create_dp_colorspace_property(connector, 0))
drm_connector_attach_colorspace_property(connector);
}
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index 55744216392b..eee53e841701 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -618,7 +618,7 @@ static int vc4_hdmi_connector_init(struct drm_device *dev,
if (ret)
return ret;
- ret = drm_mode_create_hdmi_colorspace_property(connector);
+ ret = drm_mode_create_hdmi_colorspace_property(connector, 0);
if (ret)
return ret;
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index 9d9e4d6f0449..f799cbd755a3 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -30,6 +30,7 @@
#include
#include
#include
+#include
#include
@@ -1904,8 +1905,10 @@ int
drm_connector_attach_hdr_output_metadata_property(struct drm_connector *conn
bool drm_connector_atomic_hdr_metadata_equal(struct drm_connector_state
*old_state,
[PATCH v6 05/13] drm/connector: Print connector colorspace in state debugfs
v3: Fix kerneldocs (kernel test robot)
v4: Avoid returning NULL from drm_get_colorspace_name
Signed-off-by: Harry Wentland
Reviewed-by: Sebastian Wick
Reviewed-by: Joshua Ashton
Cc: Pekka Paalanen
Cc: Sebastian Wick
Cc: vitaly.pros...@amd.com
Cc: Uma Shankar
Cc: Ville Syrjälä
Cc: Joshua Ashton
Cc: Jani Nikula
Cc: Simon Ser
Cc: Ville Syrjälä
Cc: Melissa Wen
Cc: dri-de...@lists.freedesktop.org
Cc: amd-gfx@lists.freedesktop.org
---
drivers/gpu/drm/drm_atomic.c| 1 +
drivers/gpu/drm/drm_connector.c | 15 +++
include/drm/drm_connector.h | 1 +
3 files changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index c0dc5858a723..d6d04c4ccfc0 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -1071,6 +1071,7 @@ static void drm_atomic_connector_print_state(struct
drm_printer *p,
drm_printf(p, "\tcrtc=%s\n", state->crtc ? state->crtc->name :
"(null)");
drm_printf(p, "\tself_refresh_aware=%d\n", state->self_refresh_aware);
drm_printf(p, "\tmax_requested_bpc=%d\n", state->max_requested_bpc);
+ drm_printf(p, "\tcolorspace=%s\n",
drm_get_colorspace_name(state->colorspace));
if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
if (state->writeback_job && state->writeback_job->fb)
diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index 484effc731df..46bf1f2ad535 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -1048,6 +1048,21 @@ static const char * const colorspace_names[] = {
[DRM_MODE_COLORIMETRY_BT601_YCC] = "BT601_YCC",
};
+/**
+ * drm_get_colorspace_name - return a string for color encoding
+ * @colorspace: color space to compute name of
+ *
+ * In contrast to the other drm_get_*_name functions this one here returns a
+ * const pointer and hence is threadsafe.
+ */
+const char *drm_get_colorspace_name(enum drm_colorspace colorspace)
+{
+ if (colorspace < ARRAY_SIZE(colorspace_names) &&
colorspace_names[colorspace])
+ return colorspace_names[colorspace];
+ else
+ return "(null)";
+}
+
static const u32 hdmi_colorspaces =
BIT(DRM_MODE_COLORIMETRY_SMPTE_170M_YCC) |
BIT(DRM_MODE_COLORIMETRY_BT709_YCC) |
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index fad38cdf4f79..9d9e4d6f0449 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -1988,6 +1988,7 @@ void drm_connector_list_iter_end(struct
drm_connector_list_iter *iter);
bool drm_connector_has_possible_encoder(struct drm_connector *connector,
struct drm_encoder *encoder);
+const char *drm_get_colorspace_name(enum drm_colorspace colorspace);
/**
* drm_for_each_connector_iter - connector_list iterator macro
--
2.41.0
[PATCH v6 07/13] drm/amd/display: Always pass connector_state to stream validation
We need the connector_state for colorspace and scaling information
and can get it from connector->state.
Signed-off-by: Harry Wentland
Reviewed-by: Joshua Ashton
Cc: Pekka Paalanen
Cc: Sebastian Wick
Cc: vitaly.pros...@amd.com
Cc: Joshua Ashton
Cc: Simon Ser
Cc: Melissa Wen
Cc: dri-de...@lists.freedesktop.org
Cc: amd-gfx@lists.freedesktop.org
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 90de0d37f1d2..27868dbb09f6 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -5954,15 +5954,14 @@ create_stream_for_sink(struct amdgpu_dm_connector
*aconnector,
{
struct drm_display_mode *preferred_mode = NULL;
struct drm_connector *drm_connector;
- const struct drm_connector_state *con_state =
- dm_state ? &dm_state->base : NULL;
+ const struct drm_connector_state *con_state = &dm_state->base;
struct dc_stream_state *stream = NULL;
struct drm_display_mode mode;
struct drm_display_mode saved_mode;
struct drm_display_mode *freesync_mode = NULL;
bool native_mode_found = false;
bool recalculate_timing = false;
- bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false;
+ bool scale = dm_state->scaling != RMX_OFF;
int mode_refresh;
int preferred_refresh = 0;
enum color_transfer_func tf = TRANSFER_FUNC_UNKNOWN;
@@ -6604,7 +6603,9 @@ enum drm_mode_status
amdgpu_dm_connector_mode_valid(struct drm_connector *connec
goto fail;
}
- stream = create_validate_stream_for_sink(aconnector, mode, NULL, NULL);
+ stream = create_validate_stream_for_sink(aconnector, mode,
+
to_dm_connector_state(connector->state),
+NULL);
if (stream) {
dc_stream_release(stream);
result = MODE_OK;
--
2.41.0
[PATCH v6 12/13] drm/amd/display: Add debugfs for testing output colorspace
In order to IGT test colorspace we'll want to print
the currently enabled colorspace on a stream. We add
a new debugfs to do so, using the same scheme as
current bpc reporting.
This might also come in handy when debugging display
issues.
v4:
- Fix function doc comment
- Fix sRGB debug print
Signed-off-by: Harry Wentland
Reviewed-by: Joshua Ashton
Cc: Pekka Paalanen
Cc: Sebastian Wick
Cc: vitaly.pros...@amd.com
Cc: Joshua Ashton
Cc: Simon Ser
Cc: Melissa Wen
Cc: dri-de...@lists.freedesktop.org
Cc: amd-gfx@lists.freedesktop.org
---
.../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 57 +++
1 file changed, 57 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index 82234397dd44..caf13b2e8cb6 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -906,6 +906,61 @@ static int amdgpu_current_bpc_show(struct seq_file *m,
void *data)
}
DEFINE_SHOW_ATTRIBUTE(amdgpu_current_bpc);
+/*
+ * Returns the current colorspace for the crtc.
+ * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/amdgpu_current_colorspace
+ */
+static int amdgpu_current_colorspace_show(struct seq_file *m, void *data)
+{
+ struct drm_crtc *crtc = m->private;
+ struct drm_device *dev = crtc->dev;
+ struct dm_crtc_state *dm_crtc_state = NULL;
+ int res = -ENODEV;
+
+ mutex_lock(&dev->mode_config.mutex);
+ drm_modeset_lock(&crtc->mutex, NULL);
+ if (crtc->state == NULL)
+ goto unlock;
+
+ dm_crtc_state = to_dm_crtc_state(crtc->state);
+ if (dm_crtc_state->stream == NULL)
+ goto unlock;
+
+ switch (dm_crtc_state->stream->output_color_space) {
+ case COLOR_SPACE_SRGB:
+ seq_printf(m, "sRGB");
+ break;
+ case COLOR_SPACE_YCBCR601:
+ case COLOR_SPACE_YCBCR601_LIMITED:
+ seq_printf(m, "BT601_YCC");
+ break;
+ case COLOR_SPACE_YCBCR709:
+ case COLOR_SPACE_YCBCR709_LIMITED:
+ seq_printf(m, "BT709_YCC");
+ break;
+ case COLOR_SPACE_ADOBERGB:
+ seq_printf(m, "opRGB");
+ break;
+ case COLOR_SPACE_2020_RGB_FULLRANGE:
+ seq_printf(m, "BT2020_RGB");
+ break;
+ case COLOR_SPACE_2020_YCBCR:
+ seq_printf(m, "BT2020_YCC");
+ break;
+ default:
+ goto unlock;
+ }
+ res = 0;
+
+unlock:
+ drm_modeset_unlock(&crtc->mutex);
+ mutex_unlock(&dev->mode_config.mutex);
+
+ return res;
+}
+DEFINE_SHOW_ATTRIBUTE(amdgpu_current_colorspace);
+
+
/*
* Example usage:
* Disable dsc passthrough, i.e.,: have dsc decoding at converver, not
external RX
@@ -3139,6 +3194,8 @@ void crtc_debugfs_init(struct drm_crtc *crtc)
#endif
debugfs_create_file("amdgpu_current_bpc", 0644, crtc->debugfs_entry,
crtc, &amdgpu_current_bpc_fops);
+ debugfs_create_file("amdgpu_current_colorspace", 0644,
crtc->debugfs_entry,
+ crtc, &amdgpu_current_colorspace_fops);
}
/*
--
2.41.0
[PATCH v6 13/13] drm/amd/display: Refactor avi_info_frame colorimetry determination
From: Joshua Ashton
Replace the messy two if-else chains here that were
on the same value with a switch on the enum.
Signed-off-by: Joshua Ashton
Signed-off-by: Harry Wentland
Reviewed-by: Harry Wentland
Cc: Pekka Paalanen
Cc: Sebastian Wick
Cc: vitaly.pros...@amd.com
Cc: Joshua Ashton
Cc: Simon Ser
Cc: Melissa Wen
Cc: dri-de...@lists.freedesktop.org
Cc: amd-gfx@lists.freedesktop.org
---
.../gpu/drm/amd/display/dc/core/dc_resource.c | 28 +++
1 file changed, 17 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index c72540d37aef..2f3d9a698486 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -3035,23 +3035,29 @@ static void set_avi_info_frame(
hdmi_info.bits.S0_S1 = scan_type;
/* C0, C1 : Colorimetry */
- if (color_space == COLOR_SPACE_YCBCR709 ||
- color_space == COLOR_SPACE_YCBCR709_LIMITED)
+ switch (color_space) {
+ case COLOR_SPACE_YCBCR709:
+ case COLOR_SPACE_YCBCR709_LIMITED:
hdmi_info.bits.C0_C1 = COLORIMETRY_ITU709;
- else if (color_space == COLOR_SPACE_YCBCR601 ||
- color_space == COLOR_SPACE_YCBCR601_LIMITED)
+ break;
+ case COLOR_SPACE_YCBCR601:
+ case COLOR_SPACE_YCBCR601_LIMITED:
hdmi_info.bits.C0_C1 = COLORIMETRY_ITU601;
- else {
- hdmi_info.bits.C0_C1 = COLORIMETRY_NO_DATA;
- }
- if (color_space == COLOR_SPACE_2020_RGB_FULLRANGE ||
- color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE ||
- color_space == COLOR_SPACE_2020_YCBCR) {
+ break;
+ case COLOR_SPACE_2020_RGB_FULLRANGE:
+ case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
+ case COLOR_SPACE_2020_YCBCR:
hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_BT2020RGBYCBCR;
hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED;
- } else if (color_space == COLOR_SPACE_ADOBERGB) {
+ break;
+ case COLOR_SPACE_ADOBERGB:
hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_ADOBERGB;
hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED;
+ break;
+ case COLOR_SPACE_SRGB:
+ default:
+ hdmi_info.bits.C0_C1 = COLORIMETRY_NO_DATA;
+ break;
}
if (pixel_encoding && color_space == COLOR_SPACE_2020_YCBCR &&
--
2.41.0
[PATCH v6 11/13] drm/amd/display: Always set crtcinfo from create_stream_for_sink
From: Joshua Ashton Given that we always pass dm_state into here now, this won't ever trigger anymore. This is needed for we will always fail mode validation with invalid clocks or link bandwidth errors. Signed-off-by: Joshua Ashton Signed-off-by: Harry Wentland Reviewed-by: Harry Wentland Cc: Pekka Paalanen Cc: Sebastian Wick Cc: vitaly.pros...@amd.com Cc: Joshua Ashton Cc: Simon Ser Cc: Melissa Wen Cc: dri-de...@lists.freedesktop.org Cc: amd-gfx@lists.freedesktop.org --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 060a975f9885..e17c8afce2f4 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -6054,7 +6054,7 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector, if (recalculate_timing) drm_mode_set_crtcinfo(&saved_mode, 0); - else if (!dm_state) + else drm_mode_set_crtcinfo(&mode, 0); /* -- 2.41.0
[PATCH v6 10/13] drm/amd/display: Send correct DP colorspace infopacket
Look at connector->colorimetry to determine output colorspace.
We don't want to impact current SDR behavior, so
DRM_MODE_COLORIMETRY_DEFAULT preserves current behavior.
Also add support to explicitly set BT601 and BT709.
v4:
- Roll support for BT709 and BT601 into this patch
- Add default case to avoid warnings for unhandled
enum values
Signed-off-by: Harry Wentland
Reviewed-by: Joshua Ashton
Cc: Pekka Paalanen
Cc: Sebastian Wick
Cc: vitaly.pros...@amd.com
Cc: Joshua Ashton
Cc: Simon Ser
Cc: Melissa Wen
Cc: dri-de...@lists.freedesktop.org
Cc: amd-gfx@lists.freedesktop.org
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 48 ---
1 file changed, 31 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 793ea29b4cfe..060a975f9885 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -5338,21 +5338,44 @@ get_aspect_ratio(const struct drm_display_mode *mode_in)
}
static enum dc_color_space
-get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
+get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing,
+ const struct drm_connector_state *connector_state)
{
enum dc_color_space color_space = COLOR_SPACE_SRGB;
- switch (dc_crtc_timing->pixel_encoding) {
- case PIXEL_ENCODING_YCBCR422:
- case PIXEL_ENCODING_YCBCR444:
- case PIXEL_ENCODING_YCBCR420:
- {
+ switch (connector_state->colorspace) {
+ case DRM_MODE_COLORIMETRY_BT601_YCC:
+ if (dc_crtc_timing->flags.Y_ONLY)
+ color_space = COLOR_SPACE_YCBCR601_LIMITED;
+ else
+ color_space = COLOR_SPACE_YCBCR601;
+ break;
+ case DRM_MODE_COLORIMETRY_BT709_YCC:
+ if (dc_crtc_timing->flags.Y_ONLY)
+ color_space = COLOR_SPACE_YCBCR709_LIMITED;
+ else
+ color_space = COLOR_SPACE_YCBCR709;
+ break;
+ case DRM_MODE_COLORIMETRY_OPRGB:
+ color_space = COLOR_SPACE_ADOBERGB;
+ break;
+ case DRM_MODE_COLORIMETRY_BT2020_RGB:
+ case DRM_MODE_COLORIMETRY_BT2020_YCC:
+ if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB)
+ color_space = COLOR_SPACE_2020_RGB_FULLRANGE;
+ else
+ color_space = COLOR_SPACE_2020_YCBCR;
+ break;
+ case DRM_MODE_COLORIMETRY_DEFAULT: // ITU601
+ default:
+ if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB) {
+ color_space = COLOR_SPACE_SRGB;
/*
* 27030khz is the separation point between HDTV and SDTV
* according to HDMI spec, we use YCbCr709 and YCbCr601
* respectively
*/
- if (dc_crtc_timing->pix_clk_100hz > 270300) {
+ } else if (dc_crtc_timing->pix_clk_100hz > 270300) {
if (dc_crtc_timing->flags.Y_ONLY)
color_space =
COLOR_SPACE_YCBCR709_LIMITED;
@@ -5365,15 +5388,6 @@ get_output_color_space(const struct dc_crtc_timing
*dc_crtc_timing)
else
color_space = COLOR_SPACE_YCBCR601;
}
-
- }
- break;
- case PIXEL_ENCODING_RGB:
- color_space = COLOR_SPACE_SRGB;
- break;
-
- default:
- WARN_ON(1);
break;
}
@@ -5512,7 +5526,7 @@ static void fill_stream_properties_from_drm_display_mode(
}
}
- stream->output_color_space = get_output_color_space(timing_out);
+ stream->output_color_space = get_output_color_space(timing_out,
connector_state);
}
static void fill_audio_info(struct audio_info *audio_info,
--
2.41.0
[PATCH] drm/amdgpu: Raname DRM schedulers in amdgpu TTM
Rename mman.entity to mman.high_pr to make the distinction
clearer that this is a high priority scheduler. Similarly,
rename the recently added mman.delayed to mman.low_pr to
make it clear it is a low priority scheduler.
No functional change in this patch.
Signed-off-by: Mukul Joshi
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 18 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 8
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 2 +-
drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 2 +-
4 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 8884c043cf76..8a4ed69a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -228,7 +228,7 @@ static int amdgpu_ttm_map_buffer(struct ttm_buffer_object
*bo,
num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
num_bytes = num_pages * 8 * AMDGPU_GPU_PAGES_IN_CPU_PAGE;
- r = amdgpu_job_alloc_with_ib(adev, &adev->mman.entity,
+ r = amdgpu_job_alloc_with_ib(adev, &adev->mman.high_pr,
AMDGPU_FENCE_OWNER_UNDEFINED,
num_dw * 4 + num_bytes,
AMDGPU_IB_POOL_DELAYED, &job);
@@ -1460,7 +1460,7 @@ static int amdgpu_ttm_access_memory_sdma(struct
ttm_buffer_object *bo,
memcpy(adev->mman.sdma_access_ptr, buf, len);
num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
- r = amdgpu_job_alloc_with_ib(adev, &adev->mman.entity,
+ r = amdgpu_job_alloc_with_ib(adev, &adev->mman.high_pr,
AMDGPU_FENCE_OWNER_UNDEFINED,
num_dw * 4, AMDGPU_IB_POOL_DELAYED,
&job);
@@ -2036,7 +2036,7 @@ void amdgpu_ttm_set_buffer_funcs_status(struct
amdgpu_device *adev, bool enable)
ring = adev->mman.buffer_funcs_ring;
sched = &ring->sched;
- r = drm_sched_entity_init(&adev->mman.entity,
+ r = drm_sched_entity_init(&adev->mman.high_pr,
DRM_SCHED_PRIORITY_KERNEL, &sched,
1, NULL);
if (r) {
@@ -2045,7 +2045,7 @@ void amdgpu_ttm_set_buffer_funcs_status(struct
amdgpu_device *adev, bool enable)
return;
}
- r = drm_sched_entity_init(&adev->mman.delayed,
+ r = drm_sched_entity_init(&adev->mman.low_pr,
DRM_SCHED_PRIORITY_NORMAL, &sched,
1, NULL);
if (r) {
@@ -2054,8 +2054,8 @@ void amdgpu_ttm_set_buffer_funcs_status(struct
amdgpu_device *adev, bool enable)
goto error_free_entity;
}
} else {
- drm_sched_entity_destroy(&adev->mman.entity);
- drm_sched_entity_destroy(&adev->mman.delayed);
+ drm_sched_entity_destroy(&adev->mman.high_pr);
+ drm_sched_entity_destroy(&adev->mman.low_pr);
dma_fence_put(man->move);
man->move = NULL;
}
@@ -2071,7 +2071,7 @@ void amdgpu_ttm_set_buffer_funcs_status(struct
amdgpu_device *adev, bool enable)
return;
error_free_entity:
- drm_sched_entity_destroy(&adev->mman.entity);
+ drm_sched_entity_destroy(&adev->mman.high_pr);
}
static int amdgpu_ttm_prepare_job(struct amdgpu_device *adev,
@@ -2086,8 +2086,8 @@ static int amdgpu_ttm_prepare_job(struct amdgpu_device
*adev,
AMDGPU_IB_POOL_DIRECT :
AMDGPU_IB_POOL_DELAYED;
int r;
- struct drm_sched_entity *entity = delayed ? &adev->mman.delayed :
- &adev->mman.entity;
+ struct drm_sched_entity *entity = delayed ? &adev->mman.low_pr :
+ &adev->mman.high_pr;
r = amdgpu_job_alloc_with_ib(adev, entity,
AMDGPU_FENCE_OWNER_UNDEFINED,
num_dw * 4, pool, job);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
index e82b1edee7a4..6d0d66e40db9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
@@ -59,10 +59,10 @@ struct amdgpu_mman {
boolbuffer_funcs_enabled;
struct mutexgtt_window_lock;
- /* Scheduler entity for buffer moves */
- struct drm_sched_entity entity;
- /* Scheduler entity for VRAM clearing */
- struct drm_sched_entity delayed;
+ /* High priority scheduler entity for buffer moves */
+ struct drm_sched_entity hi
[PATCH] drm/amdkfd: Fix reserved SDMA queues handling
This patch fixes a regression caused by a bad merge where
the handling of reserved SDMA queues was accidentally removed.
With the fix, the reserved SDMA queues are again correctly
marked as unavailable for allocation.
Fixes: c27842c84a848 ("drm/amdkfd: Update SDMA queue management for GFX9.4.3")
Signed-off-by: Mukul Joshi
---
drivers/gpu/drm/amd/amdkfd/kfd_device.c | 13 ++---
.../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 10 +-
drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 2 +-
3 files changed, 12 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index 9fc9d32cb579..9d4abfd8b55e 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -106,20 +106,19 @@ static void kfd_device_info_set_sdma_info(struct kfd_dev
*kfd)
kfd->device_info.num_sdma_queues_per_engine = 8;
}
+ bitmap_zero(kfd->device_info.reserved_sdma_queues_bitmap,
KFD_MAX_SDMA_QUEUES);
+
switch (sdma_version) {
case IP_VERSION(6, 0, 0):
+ case IP_VERSION(6, 0, 1):
case IP_VERSION(6, 0, 2):
case IP_VERSION(6, 0, 3):
/* Reserve 1 for paging and 1 for gfx */
kfd->device_info.num_reserved_sdma_queues_per_engine = 2;
/* BIT(0)=engine-0 queue-0; BIT(1)=engine-1 queue-0;
BIT(2)=engine-0 queue-1; ... */
- kfd->device_info.reserved_sdma_queues_bitmap = 0xFULL;
- break;
- case IP_VERSION(6, 0, 1):
- /* Reserve 1 for paging and 1 for gfx */
- kfd->device_info.num_reserved_sdma_queues_per_engine = 2;
- /* BIT(0)=engine-0 queue-0; BIT(1)=engine-0 queue-1; ... */
- kfd->device_info.reserved_sdma_queues_bitmap = 0x3ULL;
+ bitmap_set(kfd->device_info.reserved_sdma_queues_bitmap, 0,
+ kfd->adev->sdma.num_instances *
+
kfd->device_info.num_reserved_sdma_queues_per_engine);
break;
default:
break;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index 0c1be91a87c6..498ad7d4e7d9 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -123,11 +123,6 @@ unsigned int get_num_xgmi_sdma_queues(struct
device_queue_manager *dqm)
dqm->dev->kfd->device_info.num_sdma_queues_per_engine;
}
-static inline uint64_t get_reserved_sdma_queues_bitmap(struct
device_queue_manager *dqm)
-{
- return dqm->dev->kfd->device_info.reserved_sdma_queues_bitmap;
-}
-
static void init_sdma_bitmaps(struct device_queue_manager *dqm)
{
bitmap_zero(dqm->sdma_bitmap, KFD_MAX_SDMA_QUEUES);
@@ -135,6 +130,11 @@ static void init_sdma_bitmaps(struct device_queue_manager
*dqm)
bitmap_zero(dqm->xgmi_sdma_bitmap, KFD_MAX_SDMA_QUEUES);
bitmap_set(dqm->xgmi_sdma_bitmap, 0, get_num_xgmi_sdma_queues(dqm));
+
+ /* Mask out the reserved queues */
+ bitmap_andnot(dqm->sdma_bitmap, dqm->sdma_bitmap,
+ dqm->dev->kfd->device_info.reserved_sdma_queues_bitmap,
+ KFD_MAX_SDMA_QUEUES);
}
void program_sh_mem_settings(struct device_queue_manager *dqm,
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
index 023b17e0116b..7364a5d77c6e 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
@@ -239,7 +239,7 @@ struct kfd_device_info {
uint32_t no_atomic_fw_version;
unsigned int num_sdma_queues_per_engine;
unsigned int num_reserved_sdma_queues_per_engine;
- uint64_t reserved_sdma_queues_bitmap;
+ DECLARE_BITMAP(reserved_sdma_queues_bitmap, KFD_MAX_SDMA_QUEUES);
};
unsigned int kfd_get_num_sdma_engines(struct kfd_node *kdev);
--
2.35.1
Re: [PATCH] drm/amdkfd: Fix reserved SDMA queues handling
On 2023-06-07 11:27, Mukul Joshi wrote:
This patch fixes a regression caused by a bad merge where
the handling of reserved SDMA queues was accidentally removed.
With the fix, the reserved SDMA queues are again correctly
marked as unavailable for allocation.
Fixes: c27842c84a848 ("drm/amdkfd: Update SDMA queue management for GFX9.4.3")
Signed-off-by: Mukul Joshi
Reviewed-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdkfd/kfd_device.c | 13 ++---
.../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 10 +-
drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 2 +-
3 files changed, 12 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index 9fc9d32cb579..9d4abfd8b55e 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -106,20 +106,19 @@ static void kfd_device_info_set_sdma_info(struct kfd_dev
*kfd)
kfd->device_info.num_sdma_queues_per_engine = 8;
}
+ bitmap_zero(kfd->device_info.reserved_sdma_queues_bitmap, KFD_MAX_SDMA_QUEUES);
+
switch (sdma_version) {
case IP_VERSION(6, 0, 0):
+ case IP_VERSION(6, 0, 1):
case IP_VERSION(6, 0, 2):
case IP_VERSION(6, 0, 3):
/* Reserve 1 for paging and 1 for gfx */
kfd->device_info.num_reserved_sdma_queues_per_engine = 2;
/* BIT(0)=engine-0 queue-0; BIT(1)=engine-1 queue-0;
BIT(2)=engine-0 queue-1; ... */
- kfd->device_info.reserved_sdma_queues_bitmap = 0xFULL;
- break;
- case IP_VERSION(6, 0, 1):
- /* Reserve 1 for paging and 1 for gfx */
- kfd->device_info.num_reserved_sdma_queues_per_engine = 2;
- /* BIT(0)=engine-0 queue-0; BIT(1)=engine-0 queue-1; ... */
- kfd->device_info.reserved_sdma_queues_bitmap = 0x3ULL;
+ bitmap_set(kfd->device_info.reserved_sdma_queues_bitmap, 0,
+ kfd->adev->sdma.num_instances *
+
kfd->device_info.num_reserved_sdma_queues_per_engine);
break;
default:
break;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index 0c1be91a87c6..498ad7d4e7d9 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -123,11 +123,6 @@ unsigned int get_num_xgmi_sdma_queues(struct
device_queue_manager *dqm)
dqm->dev->kfd->device_info.num_sdma_queues_per_engine;
}
-static inline uint64_t get_reserved_sdma_queues_bitmap(struct device_queue_manager *dqm)
-{
- return dqm->dev->kfd->device_info.reserved_sdma_queues_bitmap;
-}
-
static void init_sdma_bitmaps(struct device_queue_manager *dqm)
{
bitmap_zero(dqm->sdma_bitmap, KFD_MAX_SDMA_QUEUES);
@@ -135,6 +130,11 @@ static void init_sdma_bitmaps(struct device_queue_manager
*dqm)
bitmap_zero(dqm->xgmi_sdma_bitmap, KFD_MAX_SDMA_QUEUES);
bitmap_set(dqm->xgmi_sdma_bitmap, 0, get_num_xgmi_sdma_queues(dqm));
+
+ /* Mask out the reserved queues */
+ bitmap_andnot(dqm->sdma_bitmap, dqm->sdma_bitmap,
+ dqm->dev->kfd->device_info.reserved_sdma_queues_bitmap,
+ KFD_MAX_SDMA_QUEUES);
}
void program_sh_mem_settings(struct device_queue_manager *dqm,
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
index 023b17e0116b..7364a5d77c6e 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
@@ -239,7 +239,7 @@ struct kfd_device_info {
uint32_t no_atomic_fw_version;
unsigned int num_sdma_queues_per_engine;
unsigned int num_reserved_sdma_queues_per_engine;
- uint64_t reserved_sdma_queues_bitmap;
+ DECLARE_BITMAP(reserved_sdma_queues_bitmap, KFD_MAX_SDMA_QUEUES);
};
unsigned int kfd_get_num_sdma_engines(struct kfd_node *kdev);
Re: [PATCH] drm/amd/pm: enable more Pstates profile levels for yellow_carp
Acked-by: Alex Deucher
On Wed, Jun 7, 2023 at 7:09 AM shikaguo wrote:
>
> This patch enables following UMD stable Pstates profile levels for
> power_dpm_force_performance_level interface.
>
> - profile_peak
> - profile_min_mclk
> - profile_min_sclk
> - profile_standard
>
> Signed-off-by: shikaguo
> ---
> .../drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c | 94 ++-
> .../drm/amd/pm/swsmu/smu13/yellow_carp_ppt.h | 8 +-
> 2 files changed, 98 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
> index a92da336ecec..5c968ab2ea8d 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
> @@ -957,6 +957,9 @@ static int yellow_carp_set_soft_freq_limited_range(struct
> smu_context *smu,
> uint32_t max)
> {
> enum smu_message_type msg_set_min, msg_set_max;
> + uint32_t min_clk = min;
> + uint32_t max_clk = max;
> +
> int ret = 0;
>
> if (!yellow_carp_clk_dpm_is_enabled(smu, clk_type))
> @@ -985,11 +988,17 @@ static int
> yellow_carp_set_soft_freq_limited_range(struct smu_context *smu,
> return -EINVAL;
> }
>
> - ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_min, min, NULL);
> + if (clk_type == SMU_VCLK) {
> + min_clk = min << SMU_13_VCLK_SHIFT;
> + max_clk = max << SMU_13_VCLK_SHIFT;
> + }
> +
> + ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_min, min_clk,
> NULL);
> +
> if (ret)
> goto out;
>
> - ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_max, max, NULL);
> + ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_max, max_clk,
> NULL);
> if (ret)
> goto out;
>
> @@ -1107,6 +1116,50 @@ static int yellow_carp_force_clk_levels(struct
> smu_context *smu,
> return ret;
> }
>
> +static int yellow_carp_get_dpm_profile_freq(struct smu_context *smu,
> + enum amd_dpm_forced_level level,
> + enum smu_clk_type clk_type,
> + uint32_t *min_clk,
> + uint32_t *max_clk)
> +{
> + int ret = 0;
> + uint32_t clk_limit = 0;
> +
> + switch (clk_type) {
> + case SMU_GFXCLK:
> + case SMU_SCLK:
> + clk_limit = YELLOW_CARP_UMD_PSTATE_GFXCLK;
> + if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
> + yellow_carp_get_dpm_ultimate_freq(smu, SMU_SCLK,
> NULL, &clk_limit);
> + else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK)
> + yellow_carp_get_dpm_ultimate_freq(smu, SMU_SCLK,
> &clk_limit, NULL);
> + break;
> + case SMU_SOCCLK:
> + clk_limit = YELLOW_CARP_UMD_PSTATE_SOCCLK;
> + if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
> + yellow_carp_get_dpm_ultimate_freq(smu, SMU_SOCCLK,
> NULL, &clk_limit);
> + break;
> + case SMU_FCLK:
> + clk_limit = YELLOW_CARP_UMD_PSTATE_FCLK;
> + if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
> + yellow_carp_get_dpm_ultimate_freq(smu, SMU_FCLK,
> NULL, &clk_limit);
> + else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK)
> + yellow_carp_get_dpm_ultimate_freq(smu, SMU_FCLK,
> &clk_limit, NULL);
> + break;
> + case SMU_VCLK:
> + yellow_carp_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL,
> &clk_limit);
> + break;
> + case SMU_DCLK:
> + yellow_carp_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL,
> &clk_limit);
> + break;
> + default:
> + ret = -EINVAL;
> + break;
> + }
> + *min_clk = *max_clk = clk_limit;
> + return ret;
> +}
> +
> static int yellow_carp_set_performance_level(struct smu_context *smu,
> enum amd_dpm_forced_level
> level)
> {
> @@ -1114,6 +1167,9 @@ static int yellow_carp_set_performance_level(struct
> smu_context *smu,
> uint32_t sclk_min = 0, sclk_max = 0;
> uint32_t fclk_min = 0, fclk_max = 0;
> uint32_t socclk_min = 0, socclk_max = 0;
> + uint32_t vclk_min = 0, vclk_max = 0;
> + uint32_t dclk_min = 0, dclk_max = 0;
> +
> int ret = 0;
>
> switch (level) {
> @@ -1121,28 +1177,42 @@ static int yellow_carp_set_performance_level(struct
> smu_context *smu,
> yellow_carp_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL,
> &sclk_max);
> yellow_carp_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL,
> &fclk_max);
> yellow_carp_get_dpm_ultimate_freq(sm
Re: [PATCH v6 00/13] Enable Colorspace connector property in amdgpu
Thanks! All of the core DRM patches (1-6) are Reviewed-by: Simon Ser
Re: [PATCH] drm/amdgpu/mmsch: Correct the definition for mmsch init header
[AMD Official Use Only - General]
Acked-by: Alex Deucher
From: amd-gfx on behalf of Deng, Emily
Sent: Tuesday, June 6, 2023 9:16 PM
To: Deng, Emily ; amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH] drm/amdgpu/mmsch: Correct the definition for mmsch init
header
[AMD Official Use Only - General]
[AMD Official Use Only - General]
Ping..
Best wishes
Emily Deng
>-Original Message-
>From: Emily Deng
>Sent: Tuesday, June 6, 2023 2:52 PM
>To: amd-gfx@lists.freedesktop.org
>Cc: Deng, Emily
>Subject: [PATCH] drm/amdgpu/mmsch: Correct the definition for mmsch init
>header
>
>For the header, it is version related, shouldn't use MAX_VCN_INSTANCES.
>
>Signed-off-by: Emily Deng
>---
> drivers/gpu/drm/amd/amdgpu/mmsch_v3_0.h | 4 +++-
>drivers/gpu/drm/amd/amdgpu/mmsch_v4_0.h | 4 +++-
> drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 2 +-
> 4 files changed, 8 insertions(+), 4 deletions(-)
>
>diff --git a/drivers/gpu/drm/amd/amdgpu/mmsch_v3_0.h
>b/drivers/gpu/drm/amd/amdgpu/mmsch_v3_0.h
>index 3e4e858a6965..a773ef61b78c 100644
>--- a/drivers/gpu/drm/amd/amdgpu/mmsch_v3_0.h
>+++ b/drivers/gpu/drm/amd/amdgpu/mmsch_v3_0.h
>@@ -30,6 +30,8 @@
> #define MMSCH_VERSION_MINOR 0
> #define MMSCH_VERSION (MMSCH_VERSION_MAJOR << 16 |
>MMSCH_VERSION_MINOR)
>
>+#define MMSCH_V3_0_VCN_INSTANCES 0x2
>+
> enum mmsch_v3_0_command_type {
> MMSCH_COMMAND__DIRECT_REG_WRITE = 0,
> MMSCH_COMMAND__DIRECT_REG_POLLING = 2, @@ -47,7 +49,7
>@@ struct mmsch_v3_0_table_info { struct mmsch_v3_0_init_header {
> uint32_t version;
> uint32_t total_size;
>- struct mmsch_v3_0_table_info inst[AMDGPU_MAX_VCN_INSTANCES];
>+ struct mmsch_v3_0_table_info inst[MMSCH_V3_0_VCN_INSTANCES];
> };
>
> struct mmsch_v3_0_cmd_direct_reg_header { diff --git
>a/drivers/gpu/drm/amd/amdgpu/mmsch_v4_0.h
>b/drivers/gpu/drm/amd/amdgpu/mmsch_v4_0.h
>index 83653a50a1a2..796d4f8791e5 100644
>--- a/drivers/gpu/drm/amd/amdgpu/mmsch_v4_0.h
>+++ b/drivers/gpu/drm/amd/amdgpu/mmsch_v4_0.h
>@@ -43,6 +43,8 @@
> #define MMSCH_VF_MAILBOX_RESP__OK 0x1
> #define MMSCH_VF_MAILBOX_RESP__INCOMPLETE 0x2
>
>+#define MMSCH_V4_0_VCN_INSTANCES 0x2
>+
> enum mmsch_v4_0_command_type {
> MMSCH_COMMAND__DIRECT_REG_WRITE = 0,
> MMSCH_COMMAND__DIRECT_REG_POLLING = 2, @@ -60,7 +62,7
>@@ struct mmsch_v4_0_table_info { struct mmsch_v4_0_init_header {
> uint32_t version;
> uint32_t total_size;
>- struct mmsch_v4_0_table_info inst[AMDGPU_MAX_VCN_INSTANCES];
>+ struct mmsch_v4_0_table_info inst[MMSCH_V4_0_VCN_INSTANCES];
> struct mmsch_v4_0_table_info jpegdec;
> };
>
>diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
>b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
>index 70fefbf26c48..c8f63b3c6f69 100644
>--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
>+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
>@@ -1313,7 +1313,7 @@ static int vcn_v3_0_start_sriov(struct
>amdgpu_device *adev)
>
> header.version = MMSCH_VERSION;
> header.total_size = sizeof(struct mmsch_v3_0_init_header) >> 2;
>- for (i = 0; i < AMDGPU_MAX_VCN_INSTANCES; i++) {
>+ for (i = 0; i < MMSCH_V3_0_VCN_INSTANCES; i++) {
> header.inst[i].init_status = 0;
> header.inst[i].table_offset = 0;
> header.inst[i].table_size = 0;
>diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
>b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
>index 60c3fd20e8ce..8d371faaa2b3 100644
>--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
>+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
>@@ -1239,7 +1239,7 @@ static int vcn_v4_0_start_sriov(struct
>amdgpu_device *adev)
>
> header.version = MMSCH_VERSION;
> header.total_size = sizeof(struct mmsch_v4_0_init_header) >> 2;
>- for (i = 0; i < AMDGPU_MAX_VCN_INSTANCES; i++) {
>+ for (i = 0; i < MMSCH_V4_0_VCN_INSTANCES; i++) {
> header.inst[i].init_status = 0;
> header.inst[i].table_offset = 0;
> header.inst[i].table_size = 0;
>--
>2.36.1
Re: [PATCH 3/3] drm/amd/pm: enable more Pstates profile levels for SMU v13.0.4
[Public]
Series is:
Acked-by: Alex Deucher
From: Huang, Tim
Sent: Wednesday, June 7, 2023 4:02 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Zhang, Yifan
; Liu, Aaron ; Guo, Shikai
; Huang, Tim
Subject: [PATCH 3/3] drm/amd/pm: enable more Pstates profile levels for SMU
v13.0.4
This patch enables following UMD stable Pstates profile
levels for power_dpm_force_performance_level interface.
- profile_peak
- profile_min_mclk
- profile_min_sclk
- profile_standard
Signed-off-by: Tim Huang
---
.../drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c | 54 ++-
1 file changed, 53 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
index 315a6d8bde2e..ef37dda9908f 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
@@ -54,6 +54,10 @@
#define FEATURE_MASK(feature) (1ULL << feature)
+#define SMU_13_0_4_UMD_PSTATE_GFXCLK 938
+#define SMU_13_0_4_UMD_PSTATE_SOCCLK 938
+#define SMU_13_0_4_UMD_PSTATE_FCLK 1875
+
#define SMC_DPM_FEATURE ( \
FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \
FEATURE_MASK(FEATURE_VCN_DPM_BIT)| \
@@ -908,6 +912,50 @@ static int smu_v13_0_4_force_clk_levels(struct smu_context
*smu,
return ret;
}
+static int smu_v13_0_4_get_dpm_profile_freq(struct smu_context *smu,
+ enum amd_dpm_forced_level level,
+ enum smu_clk_type clk_type,
+ uint32_t *min_clk,
+ uint32_t *max_clk)
+{
+ int ret = 0;
+ uint32_t clk_limit = 0;
+
+ switch (clk_type) {
+ case SMU_GFXCLK:
+ case SMU_SCLK:
+ clk_limit = SMU_13_0_4_UMD_PSTATE_GFXCLK;
+ if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
+ smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL,
&clk_limit);
+ else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK)
+ smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SCLK,
&clk_limit, NULL);
+ break;
+ case SMU_SOCCLK:
+ clk_limit = SMU_13_0_4_UMD_PSTATE_SOCCLK;
+ if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
+ smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SOCCLK,
NULL, &clk_limit);
+ break;
+ case SMU_FCLK:
+ clk_limit = SMU_13_0_4_UMD_PSTATE_FCLK;
+ if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
+ smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL,
&clk_limit);
+ else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK)
+ smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_FCLK,
&clk_limit, NULL);
+ break;
+ case SMU_VCLK:
+ smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL,
&clk_limit);
+ break;
+ case SMU_DCLK:
+ smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL,
&clk_limit);
+ break;
+ default:
+ ret = -EINVAL;
+ break;
+ }
+ *min_clk = *max_clk = clk_limit;
+ return ret;
+}
+
static int smu_v13_0_4_set_performance_level(struct smu_context *smu,
enum amd_dpm_forced_level level)
{
@@ -955,7 +1003,11 @@ static int smu_v13_0_4_set_performance_level(struct
smu_context *smu,
case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
- /* Temporarily do nothing since the optimal clocks haven't been
provided yet */
+ smu_v13_0_4_get_dpm_profile_freq(smu, level, SMU_SCLK,
&sclk_min, &sclk_max);
+ smu_v13_0_4_get_dpm_profile_freq(smu, level, SMU_FCLK,
&fclk_min, &fclk_max);
+ smu_v13_0_4_get_dpm_profile_freq(smu, level, SMU_SOCCLK,
&socclk_min, &socclk_max);
+ smu_v13_0_4_get_dpm_profile_freq(smu, level, SMU_VCLK,
&vclk_min, &vclk_max);
+ smu_v13_0_4_get_dpm_profile_freq(smu, level, SMU_DCLK,
&dclk_min, &dclk_max);
break;
case AMD_DPM_FORCED_LEVEL_MANUAL:
case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
--
2.34.1
[PATCH] drm/amdgpu/sdma4: set align mask to 255
The wptr needs to be incremented at at least 64 dword intervals,
use 256 to align with windows. This should fix potential hangs
with unaligned updates.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 1f83eebfc8a7..cd37f45e01a1 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -2312,7 +2312,7 @@ const struct amd_ip_funcs sdma_v4_0_ip_funcs = {
static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = {
.type = AMDGPU_RING_TYPE_SDMA,
- .align_mask = 0xf,
+ .align_mask = 0xff,
.nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
.support_64bit_ptrs = true,
.secure_submission_supported = true,
@@ -2344,7 +2344,7 @@ static const struct amdgpu_ring_funcs
sdma_v4_0_ring_funcs = {
static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs = {
.type = AMDGPU_RING_TYPE_SDMA,
- .align_mask = 0xf,
+ .align_mask = 0xff,
.nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
.support_64bit_ptrs = true,
.secure_submission_supported = true,
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
index 8eebf9c2bbcd..05bb0691ee0e 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
@@ -1823,7 +1823,7 @@ const struct amd_ip_funcs sdma_v4_4_2_ip_funcs = {
static const struct amdgpu_ring_funcs sdma_v4_4_2_ring_funcs = {
.type = AMDGPU_RING_TYPE_SDMA,
- .align_mask = 0xf,
+ .align_mask = 0xff,
.nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
.support_64bit_ptrs = true,
.get_rptr = sdma_v4_4_2_ring_get_rptr,
@@ -1854,7 +1854,7 @@ static const struct amdgpu_ring_funcs
sdma_v4_4_2_ring_funcs = {
static const struct amdgpu_ring_funcs sdma_v4_4_2_page_ring_funcs = {
.type = AMDGPU_RING_TYPE_SDMA,
- .align_mask = 0xf,
+ .align_mask = 0xff,
.nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
.support_64bit_ptrs = true,
.get_rptr = sdma_v4_4_2_ring_get_rptr,
--
2.40.1
[PATCH] drm/amdgpu/atomfirmware: fix DDR5 width reporting
DDR5 channels are 32 bit rather than 64, report the width properly in the log. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2468 Signed-off-by: Alex Deucher --- .../gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | 20 +-- 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c index ef4b9a41f20a..6b3bdc27f778 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c @@ -327,10 +327,14 @@ amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev, mem_channel_number = igp_info->v11.umachannelnumber; if (!mem_channel_number) mem_channel_number = 1; - /* channel width is 64 */ - if (vram_width) - *vram_width = mem_channel_number * 64; mem_type = igp_info->v11.memorytype; + if ((mem_type == Ddr5MemType) || + (mem_type == LpDdr5MemType)) + mem_channel_width = 32; + else + mem_channel_width = 64; + if (vram_width) + *vram_width = mem_channel_number * mem_channel_width; if (vram_type) *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); break; @@ -345,10 +349,14 @@ amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev, mem_channel_number = igp_info->v21.umachannelnumber; if (!mem_channel_number) mem_channel_number = 1; - /* channel width is 64 */ - if (vram_width) - *vram_width = mem_channel_number * 64; mem_type = igp_info->v21.memorytype; + if ((mem_type == Ddr5MemType) || + (mem_type == LpDdr5MemType)) + mem_channel_width = 32; + else + mem_channel_width = 64; + if (vram_width) + *vram_width = mem_channel_number * mem_channel_width; if (vram_type) *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); break; -- 2.40.1
Re: [PATCH 10/66] drm/amd/display: Do not set drr on pipe commit
On 6/6/23 20:01, Pillai, Aurabindo wrote: > > I'm attaching another DMCUB firmware which has the bug fix for the hang we > saw at our end and some added tracing enabled. Still runs into the newer hang when starting a KDE Plasma Wayland session. Should I try this for starting the game without the program OTG patch as well? > Could you please grab the dmesg with the following added to the kernel > cmdline: "drm.debug=0x156 log_buf_len=20M" using stock gnome/kde when you > have all 3 patches merged ? > > Also attach the contents of /sys/kernel/debug/dri/0/amdgpu_dm_dmub_tracebuffer Both files attached. -- Earthling Michel Dänzer| https://redhat.com Libre software enthusiast | Mesa and Xwayland developer trace_code=14 tick_count=803999866 param0=278 param1=385593 trace_code=1 tick_count=3671977301 param0=10 param1=0 trace_code=1 tick_count=3671977329 param0=10 param1=1 trace_code=1 tick_count=3671977641 param0=10 param1=3 trace_code=1 tick_count=3671977821 param0=10 param1=4 trace_code=252 tick_count=3671978129 param0=1844 param1=2 trace_code=1 tick_count=3671978793 param0=10 param1=1 trace_code=1 tick_count=3671978825 param0=10 param1=1 trace_code=1 tick_count=3671978857 param0=10 param1=1 trace_code=1 tick_count=3671978885 param0=10 param1=1 trace_code=1 tick_count=3671978917 param0=10 param1=1 trace_code=248 tick_count=3671979201 param0=39399 param1=1454 trace_code=1 tick_count=3671979237 param0=15 param1=1 trace_code=1 tick_count=3671979265 param0=9 param1=0 trace_code=1 tick_count=3671979293 param0=11 param1=1 trace_code=1 tick_count=3671979325 param0=11 param1=2 trace_code=1 tick_count=3672322941 param0=14 param1=0 trace_code=1 tick_count=3672322973 param0=14 param1=4 trace_code=1 tick_count=3672323705 param0=13 param1=4 trace_code=1 tick_count=3672324361 param0=14 param1=0 trace_code=1 tick_count=3672324397 param0=14 param1=1 trace_code=1 tick_count=3672324437 param0=14 param1=2 trace_code=250 tick_count=3672324497 param0=39399 param1=1454 trace_code=1 tick_count=3672355113 param0=14 param1=4 trace_code=1 tick_count=3672355353 param0=13 param1=1 trace_code=249 tick_count=3672362293 param0=39399 param1=1454 trace_code=1 tick_count=3672362325 param0=15 param1=1 trace_code=251 tick_count=3672362389 param0=39399 param1=1454 trace_code=1 tick_count=3672362541 param0=12 param1=2 trace_code=1 tick_count=3672362809 param0=12 param1=3 trace_code=1 tick_count=3672362845 param0=12 param1=3 trace_code=1 tick_count=3672362877 param0=12 param1=3 trace_code=1 tick_count=3672362909 param0=12 param1=3 trace_code=1 tick_count=3672362941 param0=12 param1=3 trace_code=249 tick_count=3672363241 param0=39399 param1=1454 trace_code=1 tick_count=3672363273 param0=15 param1=1 trace_code=1 tick_count=3672363305 param0=12 param1=1 trace_code=1 tick_count=3672434629 param0=14 param1=0 trace_code=1 tick_count=3672434657 param0=14 param1=4 trace_code=1 tick_count=3672434897 param0=13 param1=3 trace_code=252 tick_count=3672435049 param0=0 param1=3 trace_code=248 tick_count=3672958573 param0=39817 param1=1454 trace_code=1 tick_count=3672958605 param0=15 param1=1 trace_code=1 tick_count=3672958637 param0=9 param1=0 trace_code=1 tick_count=3672958665 param0=11 param1=1 trace_code=1 tick_count=3672958981 param0=11 param1=4 trace_code=1 tick_count=3672959013 param0=10 param1=0 trace_code=1 tick_count=3672959041 param0=10 param1=1 trace_code=1 tick_count=3672959141 param0=10 param1=3 trace_code=1 tick_count=3672959229 param0=10 param1=4 trace_code=252 tick_count=3672959273 param0=1844 param1=2 trace_code=1 tick_count=3672959461 param0=10 param1=1 trace_code=1 tick_count=3672959493 param0=10 param1=1 trace_code=1 tick_count=3672959529 param0=10 param1=1 trace_code=1 tick_count=3672959557 param0=10 param1=1 trace_code=1 tick_count=3672959589 param0=10 param1=1 trace_code=248 tick_count=3672959973 param0=39822 param1=1454 trace_code=1 tick_count=3672960005 param0=15 param1=1 trace_code=1 tick_count=3672960033 param0=9 param1=0 trace_code=1 tick_count=3672960061 param0=11 param1=1 trace_code=1 tick_count=3672960089 param0=11 param1=2 trace_code=0 tick_count=0 param0=0 param1=0 trace_code=0 tick_count=0 param0=0 param1=0 trace_code=0 tick_count=0 param0=0 param1=0 trace_code=0 tick_count=0 param0=0 param1=0 trace_code=0 tick_count=0 param0=0 param1=0 trace_code=0 tick_count=0 param0=0 param1=0 dmesg-amdgpu-dc-hang.txt.gz Description: application/gzip
[PATCH] drm/amdgpu: expand runpm parameter
Allow the user to specify -2 as auto enabled with displays.
By default we don't enter runtime suspend when there are
displays attached because it does not work well in some
desktop environments due to the driver sending hotplug
events on resume in case any new displays were attached
while the GPU was powered down. Some users still want
this functionality though, so this lets you enable it.
Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2428
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 37 +
1 file changed, 20 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 62cca1edcc32..0d9adcc4a4e3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -350,8 +350,9 @@ module_param_named(aspm, amdgpu_aspm, int, 0444);
* Override for runtime power management control for dGPUs. The amdgpu driver
can dynamically power down
* the dGPUs when they are idle if supported. The default is -1 (auto enable).
* Setting the value to 0 disables this functionality.
+ * Setting the value to -2 is auto enabled with power down when displays are
attached.
*/
-MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 =
force enable with BACO, 0 = disable, -1 = auto)");
+MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 =
force enable with BACO, 0 = disable, -1 = auto, -2 = autowith displays)");
module_param_named(runpm, amdgpu_runtime_pm, int, 0444);
/**
@@ -2649,24 +2650,26 @@ static int amdgpu_runtime_idle_check_display(struct
device *dev)
struct drm_connector_list_iter iter;
int ret = 0;
- /* XXX: Return busy if any displays are connected to avoid
-* possible display wakeups after runtime resume due to
-* hotplug events in case any displays were connected while
-* the GPU was in suspend. Remove this once that is fixed.
-*/
- mutex_lock(&drm_dev->mode_config.mutex);
- drm_connector_list_iter_begin(drm_dev, &iter);
- drm_for_each_connector_iter(list_connector, &iter) {
- if (list_connector->status ==
connector_status_connected) {
- ret = -EBUSY;
- break;
+ if (amdgpu_runtime_pm != -2) {
+ /* XXX: Return busy if any displays are connected to
avoid
+* possible display wakeups after runtime resume due to
+* hotplug events in case any displays were connected
while
+* the GPU was in suspend. Remove this once that is
fixed.
+*/
+ mutex_lock(&drm_dev->mode_config.mutex);
+ drm_connector_list_iter_begin(drm_dev, &iter);
+ drm_for_each_connector_iter(list_connector, &iter) {
+ if (list_connector->status ==
connector_status_connected) {
+ ret = -EBUSY;
+ break;
+ }
}
- }
- drm_connector_list_iter_end(&iter);
- mutex_unlock(&drm_dev->mode_config.mutex);
+ drm_connector_list_iter_end(&iter);
+ mutex_unlock(&drm_dev->mode_config.mutex);
- if (ret)
- return ret;
+ if (ret)
+ return ret;
+ }
if (adev->dc_enabled) {
struct drm_crtc *crtc;
--
2.40.1
Re: [PATCH v2 1/3] drm/amdkfd: add event age tracking
On 2023-06-06 12:24, James Zhu wrote:
Add event age tracking
Signed-off-by: James Zhu
---
include/uapi/linux/kfd_ioctl.h | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h
index 1781e7669982..eeb2fdcbdcb7 100644
--- a/include/uapi/linux/kfd_ioctl.h
+++ b/include/uapi/linux/kfd_ioctl.h
@@ -39,9 +39,10 @@
* - 1.11 - Add unified memory for ctx save/restore area
* - 1.12 - Add DMA buf export ioctl
* - 1.13 - Add debugger API
+ * - 1.14 - Update kfd_event_data
*/
#define KFD_IOCTL_MAJOR_VERSION 1
-#define KFD_IOCTL_MINOR_VERSION 13
+#define KFD_IOCTL_MINOR_VERSION 14
Bumping the version number should be done in the last patch in the
series, once the feature is fully enabled.
Regards,
Felix
struct kfd_ioctl_get_version_args {
__u32 major_version;/* from KFD */
@@ -320,12 +321,20 @@ struct kfd_hsa_hw_exception_data {
__u32 gpu_id;
};
+/* hsa signal event data */
+struct kfd_hsa_signal_event_data {
+ __u64 last_event_age; /* to and from KFD */
+};
+
/* Event data */
struct kfd_event_data {
union {
+ /* From KFD */
struct kfd_hsa_memory_exception_data memory_exception_data;
struct kfd_hsa_hw_exception_data hw_exception_data;
- }; /* From KFD */
+ /* To and From KFD */
+ struct kfd_hsa_signal_event_data signal_event_data;
+ };
__u64 kfd_event_data_ext; /* pointer to an extension structure
for future exception types */
__u32 event_id; /* to KFD */
Re: [PATCH v2 1/3] drm/amdkfd: add event age tracking
On 2023-06-07 13:17, Felix Kuehling wrote:
On 2023-06-06 12:24, James Zhu wrote:
Add event age tracking
Signed-off-by: James Zhu
---
include/uapi/linux/kfd_ioctl.h | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/include/uapi/linux/kfd_ioctl.h
b/include/uapi/linux/kfd_ioctl.h
index 1781e7669982..eeb2fdcbdcb7 100644
--- a/include/uapi/linux/kfd_ioctl.h
+++ b/include/uapi/linux/kfd_ioctl.h
@@ -39,9 +39,10 @@
* - 1.11 - Add unified memory for ctx save/restore area
* - 1.12 - Add DMA buf export ioctl
* - 1.13 - Add debugger API
+ * - 1.14 - Update kfd_event_data
*/
#define KFD_IOCTL_MAJOR_VERSION 1
-#define KFD_IOCTL_MINOR_VERSION 13
+#define KFD_IOCTL_MINOR_VERSION 14
Bumping the version number should be done in the last patch in the
series, once the feature is fully enabled.
[JZ] Noted, Thanks!
Regards,
Felix
struct kfd_ioctl_get_version_args {
__u32 major_version; /* from KFD */
@@ -320,12 +321,20 @@ struct kfd_hsa_hw_exception_data {
__u32 gpu_id;
};
+/* hsa signal event data */
+struct kfd_hsa_signal_event_data {
+ __u64 last_event_age; /* to and from KFD */
+};
+
/* Event data */
struct kfd_event_data {
union {
+ /* From KFD */
struct kfd_hsa_memory_exception_data memory_exception_data;
struct kfd_hsa_hw_exception_data hw_exception_data;
- }; /* From KFD */
+ /* To and From KFD */
+ struct kfd_hsa_signal_event_data signal_event_data;
+ };
__u64 kfd_event_data_ext; /* pointer to an extension structure
for future exception types */
__u32 event_id; /* to KFD */
[PATCH] drm/amdkfd: fix and enable debugging for gfx11
There are a few fixes required to enable gfx11 debugging.
First, ADD_QUEUE.trap_en is an inappropriate place to toggle
a per-process register so move it to SET_SHADER_DEBUGGER.trap_en.
When ADD_QUEUE.skip_process_ctx_clear is set, MES will prioritize
the SET_SHADER_DEBUGGER.trap_en setting.
Second, to preserve correct save/restore priviledged wave states
in coordination with the trap enablement setting, resume suspended
waves early in the disable call.
Finally, displaced single stepping can cause non-fatal illegal
instructions during process termination on debug disable. To work
around this, stall the waves prior to disable and allow clean
up to happen naturally on process termination.
NOTE: The AMDGPU_MES_VERSION_MASK check is a place holder as
MES FW updates have been reviewed but is awaiting binary
creation. Once the binaries have been created, this check may
be subject to change.
Signed-off-by: Jonathan Kim
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 5 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 4 ++-
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c| 1 +
drivers/gpu/drm/amd/amdkfd/kfd_debug.c| 31 ++-
.../drm/amd/amdkfd/kfd_device_queue_manager.c | 3 +-
drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 12 ---
drivers/gpu/drm/amd/include/mes_v11_api_def.h | 1 +
7 files changed, 40 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
index 20cc3fffe921..95d69f9c7361 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
@@ -928,7 +928,8 @@ int amdgpu_mes_set_shader_debugger(struct amdgpu_device
*adev,
uint64_t process_context_addr,
uint32_t spi_gdbg_per_vmid_cntl,
const uint32_t *tcp_watch_cntl,
- uint32_t flags)
+ uint32_t flags,
+ bool trap_en)
{
struct mes_misc_op_input op_input = {0};
int r;
@@ -945,6 +946,8 @@ int amdgpu_mes_set_shader_debugger(struct amdgpu_device
*adev,
memcpy(op_input.set_shader_debugger.tcp_watch_cntl, tcp_watch_cntl,
sizeof(op_input.set_shader_debugger.tcp_watch_cntl));
+ op_input.set_shader_debugger.trap_en = trap_en;
+
amdgpu_mes_lock(&adev->mes);
r = adev->mes.funcs->misc_op(&adev->mes, &op_input);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
index b5f5eed2b5ef..2d6ac30b7135 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
@@ -294,6 +294,7 @@ struct mes_misc_op_input {
} flags;
uint32_t spi_gdbg_per_vmid_cntl;
uint32_t tcp_watch_cntl[4];
+ uint32_t trap_en;
} set_shader_debugger;
};
};
@@ -361,7 +362,8 @@ int amdgpu_mes_set_shader_debugger(struct amdgpu_device
*adev,
uint64_t process_context_addr,
uint32_t spi_gdbg_per_vmid_cntl,
const uint32_t *tcp_watch_cntl,
- uint32_t flags);
+ uint32_t flags,
+ bool trap_en);
int amdgpu_mes_add_ring(struct amdgpu_device *adev, int gang_id,
int queue_type, int idx,
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
index c4e3cb8d44de..1bdaa00c0b46 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
@@ -347,6 +347,7 @@ static int mes_v11_0_misc_op(struct amdgpu_mes *mes,
memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl,
input->set_shader_debugger.tcp_watch_cntl,
sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl));
+ misc_pkt.set_shader_debugger.trap_en =
input->set_shader_debugger.trap_en;
break;
default:
DRM_ERROR("unsupported misc op (%d) \n", input->op);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
b/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
index 125274445f43..e7bc07068eed 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
@@ -349,12 +349,30 @@ int kfd_dbg_set_mes_debug_mode(struct kfd_process_device
*pdd)
{
uint32_t spi_dbg_cntl = pdd->spi_dbg_override |
pdd->spi_dbg_launch_mode;
uint32_t flags = pdd->process->dbg_flags;
+ bool sq_trap_en = !!spi_dbg_cntl;
if (!kfd_dbg_is_per_vmid_supported(pdd->dev))
return 0;
+ /*
+* For displaced single stepping, the debugger inserts s_trap
instructions
+* from user space.
+* This ca
Re: [PATCH v2 3/3] drm/amdkfd: don't sleep when event age unmatch
On 2023-06-06 12:24, James Zhu wrote:
Don't sleep when event age unmatch, and update last_event_age.
It is only for KFD_EVENT_TYPE_SIGNAL which is checked by user space.
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdkfd/kfd_events.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_events.c
b/drivers/gpu/drm/amd/amdkfd/kfd_events.c
index c7689181cc22..f4ceb5be78ed 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_events.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_events.c
@@ -952,6 +952,21 @@ int kfd_wait_on_events(struct kfd_process *p,
event_data.event_id);
if (ret)
goto out_unlock;
+
+ /* last_event_age = 0 reserved for backward compatible */
+ if (event_data.signal_event_data.last_event_age &&
+ event_waiters[i].event->event_age !=
+ event_data.signal_event_data.last_event_age) {
+ event_data.signal_event_data.last_event_age =
+ event_waiters[i].event->event_age;
The event_age is updated in set_event under the event->spin_lock. You
need to take that lock for this check here as well.
I think the easiest way to do this would be to move the check into
init_event_waiter. That way you can initialize the waiter as activated
if the event age is not up to date.
+ WRITE_ONCE(event_waiters[i].activated, true);
+
+ if (copy_to_user(&events[i], &event_data,
+ sizeof(struct kfd_event_data))) {
+ ret = -EFAULT;
+ goto out_unlock;
+ }
+ }
I think we also need to update the event age in event data after an
event has signaled. You should probably move updating and copying of the
event age to user mode into copy_signaled_event_data. That way it would
handle all the cases.
Regards,
Felix
}
/* Check condition once. */
[PATCH] drm/amdkfd: optimize gfx off enable toggle for debugging
Legacy debug devices limited to pinning a single debug VMID for debugging
are the only devices that require disabling GFX OFF while accessing
debug registers. Debug devices that support multi-process debugging
rely on the hardware scheduler to update debug registers and do not run
into GFX OFF access issues.
Remove KFD GFX OFF enable toggle clutter by moving these calls into the
KGD debug calls themselves.
v2: toggle gfx off around address watch hi/lo settings as well.
Signed-off-by: Jonathan Kim
---
.../drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c | 4 +++
.../drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c | 7
.../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c| 33 ++-
.../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c| 4 +++
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 24 ++
drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 22 +++--
drivers/gpu/drm/amd/amdkfd/kfd_debug.c| 21 +---
7 files changed, 77 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c
index 60f9e027fb66..1f0e6ec56618 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c
@@ -150,6 +150,8 @@ static uint32_t kgd_gfx_aldebaran_set_address_watch(
VALID,
1);
+ amdgpu_gfx_off_ctrl(adev, false);
+
WREG32_RLC((SOC15_REG_OFFSET(GC, 0, regTCP_WATCH0_ADDR_H) +
(watch_id * TCP_WATCH_STRIDE)),
watch_address_high);
@@ -158,6 +160,8 @@ static uint32_t kgd_gfx_aldebaran_set_address_watch(
(watch_id * TCP_WATCH_STRIDE)),
watch_address_low);
+ amdgpu_gfx_off_ctrl(adev, true);
+
return watch_address_cntl;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
index 625db444df1c..a4e28d547173 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
@@ -350,6 +350,8 @@ static uint32_t kgd_arcturus_enable_debug_trap(struct
amdgpu_device *adev,
bool restore_dbg_registers,
uint32_t vmid)
{
+ amdgpu_gfx_off_ctrl(adev, false);
+
mutex_lock(&adev->grbm_idx_mutex);
kgd_gfx_v9_set_wave_launch_stall(adev, vmid, true);
@@ -362,6 +364,8 @@ static uint32_t kgd_arcturus_enable_debug_trap(struct
amdgpu_device *adev,
mutex_unlock(&adev->grbm_idx_mutex);
+ amdgpu_gfx_off_ctrl(adev, true);
+
return 0;
}
@@ -375,6 +379,7 @@ static uint32_t kgd_arcturus_disable_debug_trap(struct
amdgpu_device *adev,
bool keep_trap_enabled,
uint32_t vmid)
{
+ amdgpu_gfx_off_ctrl(adev, false);
mutex_lock(&adev->grbm_idx_mutex);
@@ -388,6 +393,8 @@ static uint32_t kgd_arcturus_disable_debug_trap(struct
amdgpu_device *adev,
mutex_unlock(&adev->grbm_idx_mutex);
+ amdgpu_gfx_off_ctrl(adev, true);
+
return 0;
}
const struct kfd2kgd_calls arcturus_kfd2kgd = {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
index 8ad7a7779e14..415928139861 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
@@ -754,12 +754,13 @@ uint32_t kgd_gfx_v10_enable_debug_trap(struct
amdgpu_device *adev,
bool restore_dbg_registers,
uint32_t vmid)
{
+ amdgpu_gfx_off_ctrl(adev, false);
mutex_lock(&adev->grbm_idx_mutex);
kgd_gfx_v10_set_wave_launch_stall(adev, vmid, true);
- /* assume gfx off is disabled for the debug session if rlc restore not
supported. */
+ /* keep gfx off disabled for the debug session if rlc restore not
supported. */
if (restore_dbg_registers) {
uint32_t data = 0;
@@ -784,6 +785,8 @@ uint32_t kgd_gfx_v10_enable_debug_trap(struct amdgpu_device
*adev,
mutex_unlock(&adev->grbm_idx_mutex);
+ amdgpu_gfx_off_ctrl(adev, true);
+
return 0;
}
@@ -791,6 +794,8 @@ uint32_t kgd_gfx_v10_disable_debug_trap(struct
amdgpu_device *adev,
bool keep_trap_enabled,
uint32_t vmid)
{
+ amdgpu_gfx_off_ctrl(adev, false);
+
mutex_lock(&adev->grbm_idx_mutex);
kgd_gfx_v10_set_wave_launch_stall(adev, vmid, true);
@@ -801,6 +806,16 @@ uint32_t kgd_gfx_v10_disable_debug_trap(struct
amdgpu_device *adev,
mutex_unlock(&adev->grbm_idx_mutex);
+ amdgpu_gfx_off_ctrl(adev, true);
+
+ /*
+* Remove the extra gfx off disable reference from debug
RE: [PATCH] drm/amdkfd: fix and enable debugging for gfx11
[Public]
+ Felix (typo on email)
> -Original Message-
> From: Kim, Jonathan
> Sent: Wednesday, June 7, 2023 1:27 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: felix.kuel...@amd.com; Huang, JinHuiEric ;
> Kim, Jonathan
> Subject: [PATCH] drm/amdkfd: fix and enable debugging for gfx11
>
> There are a few fixes required to enable gfx11 debugging.
>
> First, ADD_QUEUE.trap_en is an inappropriate place to toggle
> a per-process register so move it to SET_SHADER_DEBUGGER.trap_en.
> When ADD_QUEUE.skip_process_ctx_clear is set, MES will prioritize
> the SET_SHADER_DEBUGGER.trap_en setting.
>
> Second, to preserve correct save/restore priviledged wave states
> in coordination with the trap enablement setting, resume suspended
> waves early in the disable call.
>
> Finally, displaced single stepping can cause non-fatal illegal
> instructions during process termination on debug disable. To work
> around this, stall the waves prior to disable and allow clean
> up to happen naturally on process termination.
>
> NOTE: The AMDGPU_MES_VERSION_MASK check is a place holder as
> MES FW updates have been reviewed but is awaiting binary
> creation. Once the binaries have been created, this check may
> be subject to change.
>
> Signed-off-by: Jonathan Kim
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 5 ++-
> drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 4 ++-
> drivers/gpu/drm/amd/amdgpu/mes_v11_0.c| 1 +
> drivers/gpu/drm/amd/amdkfd/kfd_debug.c| 31 ++-
> .../drm/amd/amdkfd/kfd_device_queue_manager.c | 3 +-
> drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 12 ---
> drivers/gpu/drm/amd/include/mes_v11_api_def.h | 1 +
> 7 files changed, 40 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> index 20cc3fffe921..95d69f9c7361 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> @@ -928,7 +928,8 @@ int amdgpu_mes_set_shader_debugger(struct
> amdgpu_device *adev,
> uint64_t process_context_addr,
> uint32_t spi_gdbg_per_vmid_cntl,
> const uint32_t *tcp_watch_cntl,
> - uint32_t flags)
> + uint32_t flags,
> + bool trap_en)
> {
> struct mes_misc_op_input op_input = {0};
> int r;
> @@ -945,6 +946,8 @@ int amdgpu_mes_set_shader_debugger(struct
> amdgpu_device *adev,
> memcpy(op_input.set_shader_debugger.tcp_watch_cntl,
> tcp_watch_cntl,
>
> sizeof(op_input.set_shader_debugger.tcp_watch_cntl));
>
> + op_input.set_shader_debugger.trap_en = trap_en;
> +
> amdgpu_mes_lock(&adev->mes);
>
> r = adev->mes.funcs->misc_op(&adev->mes, &op_input);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
> index b5f5eed2b5ef..2d6ac30b7135 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
> @@ -294,6 +294,7 @@ struct mes_misc_op_input {
> } flags;
> uint32_t spi_gdbg_per_vmid_cntl;
> uint32_t tcp_watch_cntl[4];
> + uint32_t trap_en;
> } set_shader_debugger;
> };
> };
> @@ -361,7 +362,8 @@ int amdgpu_mes_set_shader_debugger(struct
> amdgpu_device *adev,
> uint64_t process_context_addr,
> uint32_t spi_gdbg_per_vmid_cntl,
> const uint32_t *tcp_watch_cntl,
> - uint32_t flags);
> + uint32_t flags,
> + bool trap_en);
>
> int amdgpu_mes_add_ring(struct amdgpu_device *adev, int gang_id,
> int queue_type, int idx,
> diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
> b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
> index c4e3cb8d44de..1bdaa00c0b46 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
> @@ -347,6 +347,7 @@ static int mes_v11_0_misc_op(struct amdgpu_mes
> *mes,
> memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl,
> input->set_shader_debugger.tcp_watch_cntl,
>
> sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl));
> + misc_pkt.set_shader_debugger.trap_en = input-
> >set_shader_debugger.trap_en;
> break;
> default:
> DRM_ERROR("unsupported misc op (%d) \n", input->op);
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
> b/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
> index 125274445f43..e7bc07068eed 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
> @@ -349,12 +349,30 @@ int kfd_dbg_set_mes_debug_mode(struct
> kfd_process_device *pdd)
> {
> uint32
RE: [PATCH] drm/amdkfd: optimize gfx off enable toggle for debugging
[Public]
+ Felix (typo on email)
> -Original Message-
> From: Kim, Jonathan
> Sent: Wednesday, June 7, 2023 1:32 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: felix.kuel...@amd.com; Huang, JinHuiEric ;
> Kim, Jonathan
> Subject: [PATCH] drm/amdkfd: optimize gfx off enable toggle for debugging
>
> Legacy debug devices limited to pinning a single debug VMID for debugging
> are the only devices that require disabling GFX OFF while accessing
> debug registers. Debug devices that support multi-process debugging
> rely on the hardware scheduler to update debug registers and do not run
> into GFX OFF access issues.
>
> Remove KFD GFX OFF enable toggle clutter by moving these calls into the
> KGD debug calls themselves.
>
> v2: toggle gfx off around address watch hi/lo settings as well.
>
> Signed-off-by: Jonathan Kim
> ---
> .../drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c | 4 +++
> .../drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c | 7
> .../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c| 33
> ++-
> .../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c| 4 +++
> .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 24 ++
> drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 22 +++--
> drivers/gpu/drm/amd/amdkfd/kfd_debug.c| 21 +---
> 7 files changed, 77 insertions(+), 38 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c
> index 60f9e027fb66..1f0e6ec56618 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c
> @@ -150,6 +150,8 @@ static uint32_t
> kgd_gfx_aldebaran_set_address_watch(
> VALID,
> 1);
>
> + amdgpu_gfx_off_ctrl(adev, false);
> +
> WREG32_RLC((SOC15_REG_OFFSET(GC, 0, regTCP_WATCH0_ADDR_H)
> +
> (watch_id * TCP_WATCH_STRIDE)),
> watch_address_high);
> @@ -158,6 +160,8 @@ static uint32_t
> kgd_gfx_aldebaran_set_address_watch(
> (watch_id * TCP_WATCH_STRIDE)),
> watch_address_low);
>
> + amdgpu_gfx_off_ctrl(adev, true);
> +
> return watch_address_cntl;
> }
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
> index 625db444df1c..a4e28d547173 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
> @@ -350,6 +350,8 @@ static uint32_t
> kgd_arcturus_enable_debug_trap(struct amdgpu_device *adev,
> bool restore_dbg_registers,
> uint32_t vmid)
> {
> + amdgpu_gfx_off_ctrl(adev, false);
> +
> mutex_lock(&adev->grbm_idx_mutex);
>
> kgd_gfx_v9_set_wave_launch_stall(adev, vmid, true);
> @@ -362,6 +364,8 @@ static uint32_t
> kgd_arcturus_enable_debug_trap(struct amdgpu_device *adev,
>
> mutex_unlock(&adev->grbm_idx_mutex);
>
> + amdgpu_gfx_off_ctrl(adev, true);
> +
> return 0;
> }
>
> @@ -375,6 +379,7 @@ static uint32_t
> kgd_arcturus_disable_debug_trap(struct amdgpu_device *adev,
> bool keep_trap_enabled,
> uint32_t vmid)
> {
> + amdgpu_gfx_off_ctrl(adev, false);
>
> mutex_lock(&adev->grbm_idx_mutex);
>
> @@ -388,6 +393,8 @@ static uint32_t
> kgd_arcturus_disable_debug_trap(struct amdgpu_device *adev,
>
> mutex_unlock(&adev->grbm_idx_mutex);
>
> + amdgpu_gfx_off_ctrl(adev, true);
> +
> return 0;
> }
> const struct kfd2kgd_calls arcturus_kfd2kgd = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
> index 8ad7a7779e14..415928139861 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
> @@ -754,12 +754,13 @@ uint32_t kgd_gfx_v10_enable_debug_trap(struct
> amdgpu_device *adev,
> bool restore_dbg_registers,
> uint32_t vmid)
> {
> + amdgpu_gfx_off_ctrl(adev, false);
>
> mutex_lock(&adev->grbm_idx_mutex);
>
> kgd_gfx_v10_set_wave_launch_stall(adev, vmid, true);
>
> - /* assume gfx off is disabled for the debug session if rlc restore not
> supported. */
> + /* keep gfx off disabled for the debug session if rlc restore not
> supported. */
> if (restore_dbg_registers) {
> uint32_t data = 0;
>
> @@ -784,6 +785,8 @@ uint32_t kgd_gfx_v10_enable_debug_trap(struct
> amdgpu_device *adev,
>
> mutex_unlock(&adev->grbm_idx_mutex);
>
> + amdgpu_gfx_off_ctrl(adev, true);
> +
> return 0;
> }
>
> @@ -791,6 +794,8 @@ uint32_t kgd_gfx_v10_disable_debug_trap(struct
> amdgpu_device *adev,
> bool keep_trap_enabled,
>
Re: [PATCH 10/66] drm/amd/display: Do not set drr on pipe commit
[Public]
Thanks Michel.
Do you see the issue if you force disable FAMS? The following diff should do:
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
index f4ee4b3df596..475c16aab518 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
@@ -725,7 +725,8 @@ static const struct dc_debug_options debug_defaults_drv = {
.dwb_fi_phase = -1, // -1 = disable,
.dmub_command_table = true,
.use_max_lb = true,
- .exit_idle_opt_for_cursor_updates = true
+ .exit_idle_opt_for_cursor_updates = true,
+ .disable_fams=true
};
static const struct dc_panel_config panel_config_defaults = {
--
Regards,
Jay
From: Michel Dänzer
Sent: Wednesday, June 7, 2023 1:00 PM
To: Pillai, Aurabindo ; Zhuo, Qingqing (Lillian)
; Chalmers, Wesley
Cc: Wang, Chao-kai (Stylon) ; Li, Sun peng (Leo)
; Wentland, Harry ; Siqueira,
Rodrigo ; Li, Roman ; Chiu, Solomon
; Lin, Wayne ; Lakha, Bhawanpreet
; Gutierrez, Agustin ;
Kotarac, Pavle ; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 10/66] drm/amd/display: Do not set drr on pipe commit
On 6/6/23 20:01, Pillai, Aurabindo wrote:
>
> I'm attaching another DMCUB firmware which has the bug fix for the hang we
> saw at our end and some added tracing enabled.
Still runs into the newer hang when starting a KDE Plasma Wayland session.
Should I try this for starting the game without the program OTG patch as well?
> Could you please grab the dmesg with the following added to the kernel
> cmdline: "drm.debug=0x156 log_buf_len=20M" using stock gnome/kde when you
> have all 3 patches merged ?
>
> Also attach the contents of /sys/kernel/debug/dri/0/amdgpu_dm_dmub_tracebuffer
Both files attached.
--
Earthling Michel Dänzer| https://redhat.com
Libre software enthusiast | Mesa and Xwayland developer
Re: [PATCH v2 3/3] drm/amdkfd: don't sleep when event age unmatch
On 2023-06-07 13:27, Felix Kuehling wrote:
On 2023-06-06 12:24, James Zhu wrote:
Don't sleep when event age unmatch, and update last_event_age.
It is only for KFD_EVENT_TYPE_SIGNAL which is checked by user space.
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdkfd/kfd_events.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_events.c
b/drivers/gpu/drm/amd/amdkfd/kfd_events.c
index c7689181cc22..f4ceb5be78ed 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_events.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_events.c
@@ -952,6 +952,21 @@ int kfd_wait_on_events(struct kfd_process *p,
event_data.event_id);
if (ret)
goto out_unlock;
+
+ /* last_event_age = 0 reserved for backward compatible */
+ if (event_data.signal_event_data.last_event_age &&
+ event_waiters[i].event->event_age !=
+ event_data.signal_event_data.last_event_age) {
+ event_data.signal_event_data.last_event_age =
+ event_waiters[i].event->event_age;
The event_age is updated in set_event under the event->spin_lock. You
need to take that lock for this check here as well.
I think the easiest way to do this would be to move the check into
init_event_waiter. That way you can initialize the waiter as activated
if the event age is not up to date.
[JZ] Sure
+ WRITE_ONCE(event_waiters[i].activated, true);
+
+ if (copy_to_user(&events[i], &event_data,
+ sizeof(struct kfd_event_data))) {
+ ret = -EFAULT;
+ goto out_unlock;
+ }
+ }
I think we also need to update the event age in event data after an
event has signaled. You should probably move updating and copying of
the event age to user mode into copy_signaled_event_data. That way it
would handle all the cases.
[JZ] Sure
Regards,
Felix
}
/* Check condition once. */
Re: PROBLEM: AMD Ryzen 9 7950X iGPU - Blinking Issue
On Wed, Jun 7, 2023 at 4:42 AM Felix Richter wrote: > > Hi Guys, > > so I checked, the kernel I am running has this commit > (https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git > /commit/?id=08da182175db4c7f80850354849d95f2670e8cd9) applied already! > > https://github.com/ju6ge/linux/commit/917680e6056aa288cac288d3afd2745d372beb61u > > And the bug of display flickering persists with or without the > amdgpu.sg_display=0 variable applied! That is unexpected. Setting sg_display=0 should be equivalent to reverting 81d0bcf9900932633d270d5bc4a54ff599c6ebdb. Does the attached patch (with sg_display=0 set) make any difference? Alex > > Kind regards, > Felix Richter > > > On 6/5/23 16:11, Alex Deucher wrote: > > + Hamza > > This is a known issue. You can workaround it by setting > > amdgpu.sg_display=0. It should be issue should be fixed in: > > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=08da182175db4c7f80850354849d95f2670e8cd9 > > > > Alex > > > > > > > >> Now if this is the desired long term fix I do not know … > >> > >> Kind regards, > >> Felix Richter > >> > >> On 02.05.23 16:12, Linux regression tracking (Thorsten Leemhuis) wrote: > >>> On 02.05.23 15:48, Felix Richter wrote: > On 5/2/23 15:34, Linux regression tracking (Thorsten Leemhuis) wrote: > > On 02.05.23 15:13, Alex Deucher wrote: > >> On Tue, May 2, 2023 at 7:45 AM Linux regression tracking (Thorsten > >> Leemhuis) wrote: > >> > >>> On 30.04.23 13:44, Felix Richter wrote: > Hi, > > I am running into an issue with the integrated GPU of the Ryzen 9 > 7950X. It seems to be a regression from kernel version 6.1 to 6.2. > The bug materializes in from of my monitor blinking, meaning it > turns full white shortly. This happens very often so that the > system becomes unpleasant to use. > > I am running the Archlinux Kernel: > The Issue happens on the bleeding edge kernel: 6.2.13 > Switching back to the LTS kernel resolves the issue: 6.1.26 > > I have two monitors attached to the system. One 42 inch 4k Display > and a 24 inch 1080p Display and am running sway as my desktop. > > Let me know if there is more information I could provide to help > narrow down the issue. > >>> Thanks for the report. To be sure the issue doesn't fall through the > >>> cracks unnoticed, I'm adding it to regzbot, the Linux kernel > >>> regression > >>> tracking bot: > >>> > >>> #regzbot ^introduced v6.1..v6.2 > >>> #regzbot title drm: amdgpu: system becomes unpleasant to use after > >>> monitor starts blinking and turns full white > >>> #regzbot ignore-activity > >>> > >>> This isn't a regression? This issue or a fix for it are already > >>> discussed somewhere else? It was fixed already? You want to clarify > >>> when > >>> the regression started to happen? Or point out I got the title or > >>> something else totally wrong? Then just reply and tell me -- ideally > >>> while also telling regzbot about it, as explained by the page listed > >>> in > >>> the footer of this mail. > >>> > >>> Developers: When fixing the issue, remember to add 'Link:' tags > >>> pointing > >>> to the report (the parent of this mail). See page linked in footer for > >>> details. > >> This sounds exactly like the issue that was fixed in this patch which > >> is already on it's way to Linus: > >> https://gitlab.freedesktop.org/agd5f/linux/-/commit/08da182175db4c7f80850354849d95f2670e8cd9 > > FWIW, you in the flood of emails likely missed that this is the same > > thread where you yesterday replied "If the module parameter didn't help > > then perhaps you are seeing some other issue. Can you bisect?". That's > > why I decided to add this to the tracking. Or am I missing something > > obvious here? > > > > /me looks around again and can't see anything, but that doesn't have to > > mean anything... > > > > Felix, btw, this guide might help you with the bisection, even if it's > > just for kernel compilation: > > > > https://docs.kernel.org/next/admin-guide/quickly-build-trimmed-linux.html > > > > And to indirectly reply to your mail from yesterday[1]. You might want > > to ignore the arch linux kernel git repo and just do a bisection between > > 6.1 and the latest 6.2.y kernel using upstream repos; and if I were you > > I'd also try 6.3 or even mainline before that, in case the issue was > > fixed already. > > > > [1] > > https://lore.kernel.org/all/04749ee4-0728-92fe-bcb0-a7320279e...@felixrichter.tech/ > > > Thanks for the pointers, I'll do a bisection on my desktop from 6.1 to > the newest commit. > >>> FWIW, I wonder what you actually mean with "newest commit" here: a >
Re: [PATCH] drm/amdkfd: fix and enable debugging for gfx11
On 2023-06-07 13:26, Jonathan Kim wrote:
There are a few fixes required to enable gfx11 debugging.
First, ADD_QUEUE.trap_en is an inappropriate place to toggle
a per-process register so move it to SET_SHADER_DEBUGGER.trap_en.
When ADD_QUEUE.skip_process_ctx_clear is set, MES will prioritize
the SET_SHADER_DEBUGGER.trap_en setting.
I see you have a firmware version check for enabling debugging. But is
the struct SET_SHADER_DEBUGGER change safe with older firmware when
debugging is disabled?
Second, to preserve correct save/restore priviledged wave states
in coordination with the trap enablement setting, resume suspended
waves early in the disable call.
Finally, displaced single stepping can cause non-fatal illegal
instructions during process termination on debug disable. To work
around this, stall the waves prior to disable and allow clean
up to happen naturally on process termination.
NOTE: The AMDGPU_MES_VERSION_MASK check is a place holder as
MES FW updates have been reviewed but is awaiting binary
creation. Once the binaries have been created, this check may
be subject to change.
Signed-off-by: Jonathan Kim
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 5 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 4 ++-
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c| 1 +
drivers/gpu/drm/amd/amdkfd/kfd_debug.c| 31 ++-
.../drm/amd/amdkfd/kfd_device_queue_manager.c | 3 +-
drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 12 ---
drivers/gpu/drm/amd/include/mes_v11_api_def.h | 1 +
7 files changed, 40 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
index 20cc3fffe921..95d69f9c7361 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
@@ -928,7 +928,8 @@ int amdgpu_mes_set_shader_debugger(struct amdgpu_device
*adev,
uint64_t process_context_addr,
uint32_t spi_gdbg_per_vmid_cntl,
const uint32_t *tcp_watch_cntl,
- uint32_t flags)
+ uint32_t flags,
+ bool trap_en)
{
struct mes_misc_op_input op_input = {0};
int r;
@@ -945,6 +946,8 @@ int amdgpu_mes_set_shader_debugger(struct amdgpu_device
*adev,
memcpy(op_input.set_shader_debugger.tcp_watch_cntl, tcp_watch_cntl,
sizeof(op_input.set_shader_debugger.tcp_watch_cntl));
+ op_input.set_shader_debugger.trap_en = trap_en;
+
amdgpu_mes_lock(&adev->mes);
r = adev->mes.funcs->misc_op(&adev->mes, &op_input);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
index b5f5eed2b5ef..2d6ac30b7135 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
@@ -294,6 +294,7 @@ struct mes_misc_op_input {
} flags;
uint32_t spi_gdbg_per_vmid_cntl;
uint32_t tcp_watch_cntl[4];
+ uint32_t trap_en;
} set_shader_debugger;
};
};
@@ -361,7 +362,8 @@ int amdgpu_mes_set_shader_debugger(struct amdgpu_device
*adev,
uint64_t process_context_addr,
uint32_t spi_gdbg_per_vmid_cntl,
const uint32_t *tcp_watch_cntl,
- uint32_t flags);
+ uint32_t flags,
+ bool trap_en);
int amdgpu_mes_add_ring(struct amdgpu_device *adev, int gang_id,
int queue_type, int idx,
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
index c4e3cb8d44de..1bdaa00c0b46 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
@@ -347,6 +347,7 @@ static int mes_v11_0_misc_op(struct amdgpu_mes *mes,
memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl,
input->set_shader_debugger.tcp_watch_cntl,
sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl));
+ misc_pkt.set_shader_debugger.trap_en =
input->set_shader_debugger.trap_en;
break;
default:
DRM_ERROR("unsupported misc op (%d) \n", input->op);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
b/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
index 125274445f43..e7bc07068eed 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
@@ -349,12 +349,30 @@ int kfd_dbg_set_mes_debug_mode(struct kfd_process_device
*pdd)
{
uint32_t spi_dbg_cntl = pdd->spi_dbg_override |
pdd->spi_dbg_launch_mode;
uint32_t flags = pdd->process->dbg_flags;
+ bool sq_trap_en = !!spi_dbg_cntl;
RE: [PATCH] drm/amdkfd: fix and enable debugging for gfx11
[Public]
> -Original Message-
> From: Kuehling, Felix
> Sent: Wednesday, June 7, 2023 2:20 PM
> To: amd-gfx@lists.freedesktop.org; Kim, Jonathan
> Cc: Huang, JinHuiEric
> Subject: Re: [PATCH] drm/amdkfd: fix and enable debugging for gfx11
>
>
> On 2023-06-07 13:26, Jonathan Kim wrote:
> > There are a few fixes required to enable gfx11 debugging.
> >
> > First, ADD_QUEUE.trap_en is an inappropriate place to toggle
> > a per-process register so move it to SET_SHADER_DEBUGGER.trap_en.
> > When ADD_QUEUE.skip_process_ctx_clear is set, MES will prioritize
> > the SET_SHADER_DEBUGGER.trap_en setting.
>
> I see you have a firmware version check for enabling debugging. But is
> the struct SET_SHADER_DEBUGGER change safe with older firmware when
> debugging is disabled?
Right. It changes the shape of MISC_OPs.
I'll have to figure out something that's backwards compatible.
>
>
> >
> > Second, to preserve correct save/restore priviledged wave states
> > in coordination with the trap enablement setting, resume suspended
> > waves early in the disable call.
> >
> > Finally, displaced single stepping can cause non-fatal illegal
> > instructions during process termination on debug disable. To work
> > around this, stall the waves prior to disable and allow clean
> > up to happen naturally on process termination.
> >
> > NOTE: The AMDGPU_MES_VERSION_MASK check is a place holder as
> > MES FW updates have been reviewed but is awaiting binary
> > creation. Once the binaries have been created, this check may
> > be subject to change.
> >
> > Signed-off-by: Jonathan Kim
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 5 ++-
> > drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 4 ++-
> > drivers/gpu/drm/amd/amdgpu/mes_v11_0.c| 1 +
> > drivers/gpu/drm/amd/amdkfd/kfd_debug.c| 31 ++-
> > .../drm/amd/amdkfd/kfd_device_queue_manager.c | 3 +-
> > drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 12 ---
> > drivers/gpu/drm/amd/include/mes_v11_api_def.h | 1 +
> > 7 files changed, 40 insertions(+), 17 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> > index 20cc3fffe921..95d69f9c7361 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> > @@ -928,7 +928,8 @@ int amdgpu_mes_set_shader_debugger(struct
> amdgpu_device *adev,
> > uint64_t process_context_addr,
> > uint32_t spi_gdbg_per_vmid_cntl,
> > const uint32_t *tcp_watch_cntl,
> > - uint32_t flags)
> > + uint32_t flags,
> > + bool trap_en)
> > {
> > struct mes_misc_op_input op_input = {0};
> > int r;
> > @@ -945,6 +946,8 @@ int amdgpu_mes_set_shader_debugger(struct
> amdgpu_device *adev,
> > memcpy(op_input.set_shader_debugger.tcp_watch_cntl,
> tcp_watch_cntl,
> >
> sizeof(op_input.set_shader_debugger.tcp_watch_cntl));
> >
> > + op_input.set_shader_debugger.trap_en = trap_en;
> > +
> > amdgpu_mes_lock(&adev->mes);
> >
> > r = adev->mes.funcs->misc_op(&adev->mes, &op_input);
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
> > index b5f5eed2b5ef..2d6ac30b7135 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
> > @@ -294,6 +294,7 @@ struct mes_misc_op_input {
> > } flags;
> > uint32_t spi_gdbg_per_vmid_cntl;
> > uint32_t tcp_watch_cntl[4];
> > + uint32_t trap_en;
> > } set_shader_debugger;
> > };
> > };
> > @@ -361,7 +362,8 @@ int amdgpu_mes_set_shader_debugger(struct
> amdgpu_device *adev,
> > uint64_t process_context_addr,
> > uint32_t spi_gdbg_per_vmid_cntl,
> > const uint32_t *tcp_watch_cntl,
> > - uint32_t flags);
> > + uint32_t flags,
> > + bool trap_en);
> >
> > int amdgpu_mes_add_ring(struct amdgpu_device *adev, int gang_id,
> > int queue_type, int idx,
> > diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
> b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
> > index c4e3cb8d44de..1bdaa00c0b46 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
> > @@ -347,6 +347,7 @@ static int mes_v11_0_misc_op(struct amdgpu_mes
> *mes,
> > memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl,
> > input->set_shader_debugger.tcp_watch_cntl,
> >
> sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl));
> > + misc_pkt.set_shader_debugger.trap_en = input-
> >set_shader_debugger.trap_en;
> > break;
> > default:
>
Re: [PATCH] drm/amdkfd: optimize gfx off enable toggle for debugging
On 2023-06-07 13:32, Jonathan Kim wrote:
Legacy debug devices limited to pinning a single debug VMID for debugging
are the only devices that require disabling GFX OFF while accessing
debug registers. Debug devices that support multi-process debugging
rely on the hardware scheduler to update debug registers and do not run
into GFX OFF access issues.
Remove KFD GFX OFF enable toggle clutter by moving these calls into the
KGD debug calls themselves.
v2: toggle gfx off around address watch hi/lo settings as well.
Signed-off-by: Jonathan Kim
---
.../drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c | 4 +++
.../drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c | 7
.../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c| 33 ++-
.../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c| 4 +++
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 24 ++
drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 22 +++--
drivers/gpu/drm/amd/amdkfd/kfd_debug.c| 21 +---
Looks like you missed one amdgpu_amdkfd_gfx_off_ctrl call in kfd_process.c.
7 files changed, 77 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c
index 60f9e027fb66..1f0e6ec56618 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c
@@ -150,6 +150,8 @@ static uint32_t kgd_gfx_aldebaran_set_address_watch(
VALID,
1);
+ amdgpu_gfx_off_ctrl(adev, false);
+
Aldebaran doesn't use automatic gfxoff, so this should not be needed.
WREG32_RLC((SOC15_REG_OFFSET(GC, 0, regTCP_WATCH0_ADDR_H) +
(watch_id * TCP_WATCH_STRIDE)),
watch_address_high);
@@ -158,6 +160,8 @@ static uint32_t kgd_gfx_aldebaran_set_address_watch(
(watch_id * TCP_WATCH_STRIDE)),
watch_address_low);
+ amdgpu_gfx_off_ctrl(adev, true);
+
return watch_address_cntl;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
index 625db444df1c..a4e28d547173 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
@@ -350,6 +350,8 @@ static uint32_t kgd_arcturus_enable_debug_trap(struct
amdgpu_device *adev,
bool restore_dbg_registers,
uint32_t vmid)
{
+ amdgpu_gfx_off_ctrl(adev, false);
+
I would need to double check, but I believe Arcturus also doesn't
support gfxoff.
mutex_lock(&adev->grbm_idx_mutex);
kgd_gfx_v9_set_wave_launch_stall(adev, vmid, true);
@@ -362,6 +364,8 @@ static uint32_t kgd_arcturus_enable_debug_trap(struct
amdgpu_device *adev,
mutex_unlock(&adev->grbm_idx_mutex);
+ amdgpu_gfx_off_ctrl(adev, true);
+
return 0;
}
@@ -375,6 +379,7 @@ static uint32_t kgd_arcturus_disable_debug_trap(struct amdgpu_device *adev,
bool keep_trap_enabled,
uint32_t vmid)
{
+ amdgpu_gfx_off_ctrl(adev, false);
mutex_lock(&adev->grbm_idx_mutex);
@@ -388,6 +393,8 @@ static uint32_t kgd_arcturus_disable_debug_trap(struct amdgpu_device *adev,
mutex_unlock(&adev->grbm_idx_mutex);
+ amdgpu_gfx_off_ctrl(adev, true);
+
return 0;
}
const struct kfd2kgd_calls arcturus_kfd2kgd = {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
index 8ad7a7779e14..415928139861 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
@@ -754,12 +754,13 @@ uint32_t kgd_gfx_v10_enable_debug_trap(struct
amdgpu_device *adev,
bool restore_dbg_registers,
uint32_t vmid)
{
+ amdgpu_gfx_off_ctrl(adev, false);
mutex_lock(&adev->grbm_idx_mutex);
kgd_gfx_v10_set_wave_launch_stall(adev, vmid, true);
- /* assume gfx off is disabled for the debug session if rlc restore not supported. */
+ /* keep gfx off disabled for the debug session if rlc restore not
supported. */
if (restore_dbg_registers) {
uint32_t data = 0;
@@ -784,6 +785,8 @@ uint32_t kgd_gfx_v10_enable_debug_trap(struct amdgpu_device *adev,
mutex_unlock(&adev->grbm_idx_mutex);
+ amdgpu_gfx_off_ctrl(adev, true);
+
return 0;
}
@@ -791,6 +794,8 @@ uint32_t kgd_gfx_v10_disable_debug_trap(struct amdgpu_device *adev,
bool keep_trap_enabled,
uint32_t vmid)
{
+ amdgpu_gfx_off_ctrl(adev, false);
+
mutex_lock(&adev->grbm_idx_mutex);
kgd_gfx_v10_set_wave_launch_stall(adev, vmid, true);
@@
[PATCH 1/2] drm/amd: Make sure image is written to trigger VBIOS image update flow
The VBIOS image update flow requires userspace to:
1) Write the image to `psp_vbflash`
2) Read `psp_vbflash`
3) Poll `psp_vbflash_status` to check for completion
If userspace reads `psp_vbflash` before writing an image, it's
possible that it causes problems that can put the dGPU into an invalid
state.
Explicitly check that an image has been written before letting a read
succeed.
Fixes: 8424f2ccb3c0 ("drm/amdgpu/psp: Add vbflash sysfs interface support")
Reviewed-by: Alex Deucher
Signed-off-by: Mario Limonciello
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 27559a05a67b..8c60db176119 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -3617,6 +3617,9 @@ static ssize_t amdgpu_psp_vbflash_read(struct file *filp,
struct kobject *kobj,
void *fw_pri_cpu_addr;
int ret;
+ if (adev->psp.vbflash_image_size == 0)
+ return -EINVAL;
+
dev_info(adev->dev, "VBIOS flash to PSP started");
ret = amdgpu_bo_create_kernel(adev, adev->psp.vbflash_image_size,
--
2.34.1
[PATCH 2/2] drm/amd: Tighten permissions on VBIOS flashing attributes
Non-root users shouldn't be able to try to trigger a VBIOS flash
or query the flashing status. This should be reserved for users with the
appropriate permissions.
Fixes: 8424f2ccb3c0 ("drm/amdgpu/psp: Add vbflash sysfs interface support")
Reviewed-by: Alex Deucher
Signed-off-by: Mario Limonciello
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 8c60db176119..488d5b7ab97c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -3671,13 +3671,13 @@ static ssize_t amdgpu_psp_vbflash_status(struct device
*dev,
}
static const struct bin_attribute psp_vbflash_bin_attr = {
- .attr = {.name = "psp_vbflash", .mode = 0664},
+ .attr = {.name = "psp_vbflash", .mode = 0220},
.size = 0,
.write = amdgpu_psp_vbflash_write,
.read = amdgpu_psp_vbflash_read,
};
-static DEVICE_ATTR(psp_vbflash_status, 0444, amdgpu_psp_vbflash_status, NULL);
+static DEVICE_ATTR(psp_vbflash_status, 0440, amdgpu_psp_vbflash_status, NULL);
int amdgpu_psp_sysfs_init(struct amdgpu_device *adev)
{
--
2.34.1
RE: [PATCH] drm/amdkfd: fix and enable debugging for gfx11
[Public]
> -Original Message-
> From: Kim, Jonathan
> Sent: Wednesday, June 7, 2023 3:28 PM
> To: Kuehling, Felix ; amd-
> g...@lists.freedesktop.org
> Cc: Huang, JinHuiEric
> Subject: RE: [PATCH] drm/amdkfd: fix and enable debugging for gfx11
>
>
>
> > -Original Message-
> > From: Kuehling, Felix
> > Sent: Wednesday, June 7, 2023 2:20 PM
> > To: amd-gfx@lists.freedesktop.org; Kim, Jonathan
>
> > Cc: Huang, JinHuiEric
> > Subject: Re: [PATCH] drm/amdkfd: fix and enable debugging for gfx11
> >
> >
> > On 2023-06-07 13:26, Jonathan Kim wrote:
> > > There are a few fixes required to enable gfx11 debugging.
> > >
> > > First, ADD_QUEUE.trap_en is an inappropriate place to toggle
> > > a per-process register so move it to SET_SHADER_DEBUGGER.trap_en.
> > > When ADD_QUEUE.skip_process_ctx_clear is set, MES will prioritize
> > > the SET_SHADER_DEBUGGER.trap_en setting.
> >
> > I see you have a firmware version check for enabling debugging. But is
> > the struct SET_SHADER_DEBUGGER change safe with older firmware when
> > debugging is disabled?
>
> Right. It changes the shape of MISC_OPs.
> I'll have to figure out something that's backwards compatible.
Actually, I think we should be okay. MISC_OPs allows a max data packet of 20
D-WORDs.
So adding another D-WORD to SET_SHADER_DEBUGGER should be well under that limit.
The writing to an unused D-WORD is likely not harmful but I can version check
the trap_en setting in the MES KGD call itself just to be safe.
Thanks,
Jon
>
> >
> >
> > >
> > > Second, to preserve correct save/restore priviledged wave states
> > > in coordination with the trap enablement setting, resume suspended
> > > waves early in the disable call.
> > >
> > > Finally, displaced single stepping can cause non-fatal illegal
> > > instructions during process termination on debug disable. To work
> > > around this, stall the waves prior to disable and allow clean
> > > up to happen naturally on process termination.
> > >
> > > NOTE: The AMDGPU_MES_VERSION_MASK check is a place holder as
> > > MES FW updates have been reviewed but is awaiting binary
> > > creation. Once the binaries have been created, this check may
> > > be subject to change.
> > >
> > > Signed-off-by: Jonathan Kim
> > > ---
> > > drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 5 ++-
> > > drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 4 ++-
> > > drivers/gpu/drm/amd/amdgpu/mes_v11_0.c| 1 +
> > > drivers/gpu/drm/amd/amdkfd/kfd_debug.c| 31 ++
> -
> > > .../drm/amd/amdkfd/kfd_device_queue_manager.c | 3 +-
> > > drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 12 ---
> > > drivers/gpu/drm/amd/include/mes_v11_api_def.h | 1 +
> > > 7 files changed, 40 insertions(+), 17 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> > > index 20cc3fffe921..95d69f9c7361 100644
> > > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> > > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> > > @@ -928,7 +928,8 @@ int amdgpu_mes_set_shader_debugger(struct
> > amdgpu_device *adev,
> > > uint64_t process_context_addr,
> > > uint32_t spi_gdbg_per_vmid_cntl,
> > > const uint32_t *tcp_watch_cntl,
> > > - uint32_t flags)
> > > + uint32_t flags,
> > > + bool trap_en)
> > > {
> > > struct mes_misc_op_input op_input = {0};
> > > int r;
> > > @@ -945,6 +946,8 @@ int amdgpu_mes_set_shader_debugger(struct
> > amdgpu_device *adev,
> > > memcpy(op_input.set_shader_debugger.tcp_watch_cntl,
> > tcp_watch_cntl,
> > >
> > sizeof(op_input.set_shader_debugger.tcp_watch_cntl));
> > >
> > > + op_input.set_shader_debugger.trap_en = trap_en;
> > > +
> > > amdgpu_mes_lock(&adev->mes);
> > >
> > > r = adev->mes.funcs->misc_op(&adev->mes, &op_input);
> > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
> > > index b5f5eed2b5ef..2d6ac30b7135 100644
> > > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
> > > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
> > > @@ -294,6 +294,7 @@ struct mes_misc_op_input {
> > > } flags;
> > > uint32_t spi_gdbg_per_vmid_cntl;
> > > uint32_t tcp_watch_cntl[4];
> > > + uint32_t trap_en;
> > > } set_shader_debugger;
> > > };
> > > };
> > > @@ -361,7 +362,8 @@ int amdgpu_mes_set_shader_debugger(struct
> > amdgpu_device *adev,
> > > uint64_t process_context_addr,
> > > uint32_t spi_gdbg_per_vmid_cntl,
> > > const uint32_t *tcp_watch_cntl,
> > > - uint32_t flags);
> > > +
[PATCH] drm/amdkfd: fix and enable debugging for gfx11
There are a couple of fixes required to enable gfx11 debugging.
First, ADD_QUEUE.trap_en is an inappropriate place to toggle
a per-process register so move it to SET_SHADER_DEBUGGER.trap_en.
When ADD_QUEUE.skip_process_ctx_clear is set, MES will prioritize
the SET_SHADER_DEBUGGER.trap_en setting.
Second, to preserve correct save/restore priviledged wave states
in coordination with the trap enablement setting, resume suspended
waves early in the disable call.
NOTE: The AMDGPU_MES_VERSION_MASK check is a place holder as
MES FW updates have been reviewed but is awaiting binary
creation. Once the binaries have been created, this check may
be subject to change.
v2: do a trap_en safety check in case old mes doesn't accept
unused trap_en d-word.
remove unnecessary process termination work around.
Signed-off-by: Jonathan Kim
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c| 7 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h| 4 +++-
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 1 +
drivers/gpu/drm/amd/amdkfd/kfd_debug.c | 14 ++
.../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 3 +--
drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 12 +++-
drivers/gpu/drm/amd/include/mes_v11_api_def.h | 1 +
7 files changed, 25 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
index 20cc3fffe921..e9091ebfe230 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
@@ -928,7 +928,8 @@ int amdgpu_mes_set_shader_debugger(struct amdgpu_device
*adev,
uint64_t process_context_addr,
uint32_t spi_gdbg_per_vmid_cntl,
const uint32_t *tcp_watch_cntl,
- uint32_t flags)
+ uint32_t flags,
+ bool trap_en)
{
struct mes_misc_op_input op_input = {0};
int r;
@@ -945,6 +946,10 @@ int amdgpu_mes_set_shader_debugger(struct amdgpu_device
*adev,
memcpy(op_input.set_shader_debugger.tcp_watch_cntl, tcp_watch_cntl,
sizeof(op_input.set_shader_debugger.tcp_watch_cntl));
+ if (((adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) >>
+ AMDGPU_MES_API_VERSION_SHIFT) >= 14)
+ op_input.set_shader_debugger.trap_en = trap_en;
+
amdgpu_mes_lock(&adev->mes);
r = adev->mes.funcs->misc_op(&adev->mes, &op_input);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
index b5f5eed2b5ef..2d6ac30b7135 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
@@ -294,6 +294,7 @@ struct mes_misc_op_input {
} flags;
uint32_t spi_gdbg_per_vmid_cntl;
uint32_t tcp_watch_cntl[4];
+ uint32_t trap_en;
} set_shader_debugger;
};
};
@@ -361,7 +362,8 @@ int amdgpu_mes_set_shader_debugger(struct amdgpu_device
*adev,
uint64_t process_context_addr,
uint32_t spi_gdbg_per_vmid_cntl,
const uint32_t *tcp_watch_cntl,
- uint32_t flags);
+ uint32_t flags,
+ bool trap_en);
int amdgpu_mes_add_ring(struct amdgpu_device *adev, int gang_id,
int queue_type, int idx,
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
index c4e3cb8d44de..1bdaa00c0b46 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
@@ -347,6 +347,7 @@ static int mes_v11_0_misc_op(struct amdgpu_mes *mes,
memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl,
input->set_shader_debugger.tcp_watch_cntl,
sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl));
+ misc_pkt.set_shader_debugger.trap_en =
input->set_shader_debugger.trap_en;
break;
default:
DRM_ERROR("unsupported misc op (%d) \n", input->op);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
b/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
index 125274445f43..cd34e7aaead4 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
@@ -349,12 +349,13 @@ int kfd_dbg_set_mes_debug_mode(struct kfd_process_device
*pdd)
{
uint32_t spi_dbg_cntl = pdd->spi_dbg_override |
pdd->spi_dbg_launch_mode;
uint32_t flags = pdd->process->dbg_flags;
+ bool sq_trap_en = !!spi_dbg_cntl;
if (!kfd_dbg_is_per_vmid_supported(pdd->dev))
return 0;
return amdgpu_mes_set_shader_debugger(pdd->dev-
[pull] amdgpu, radeon drm-fixes-6.4
Hi Dave, Daniel, Fixes for 6.4. The following changes since commit 9561de3a55bed6bdd44a12820ba81ec416e705a7: Linux 6.4-rc5 (2023-06-04 14:04:27 -0400) are available in the Git repository at: https://gitlab.freedesktop.org/agd5f/linux.git tags/amd-drm-fixes-6.4-2023-06-07 for you to fetch changes up to e1a600208286c197c2696e51fc313e49889315bd: drm/amd/display: Reduce sdp bw after urgent to 90% (2023-06-07 17:02:25 -0400) amd-drm-fixes-6.4-2023-06-07: amdgpu: - S0ix fixes - GPU reset fixes - SMU13 fixes - SMU11 fixes - Misc Display fixes - Revert RV/RV2/PCO clock counter changes - Fix Stoney xclk value - Fix reserved vram debug info radeon: - Fix a potential use after free Alex Deucher (3): Revert "drm/amdgpu: change the reference clock for raven/raven2" Revert "drm/amdgpu: Differentiate between Raven2 and Raven/Picasso according to revision id" Revert "drm/amdgpu: switch to golden tsc registers for raven/raven2" Alvin Lee (1): drm/amd/display: Reduce sdp bw after urgent to 90% Chia-I Wu (1): drm/amdgpu: fix xclk freq on CHIP_STONEY Evan Quan (1): drm/amd/pm: conditionally disable pcie lane switching for some sienna_cichlid SKUs Horatio Zhang (1): drm/amdgpu: fix Null pointer dereference error in amdgpu_device_recover_vram Lijo Lazar (1): drm/amd/pm: Fix power context allocation in SMU13 Mario Limonciello (2): drm/amd: Disallow s0ix without BIOS support again drm/amd: Make lack of `ACPI_FADT_LOW_POWER_S0` or `CONFIG_AMD_PMC` louder during suspend path Min Li (1): drm/radeon: fix race condition UAF in radeon_gem_set_domain_ioctl Samson Tam (1): drm/amd/display: add ODM case when looking for first split pipe YiPeng Chai (1): drm/amdgpu: change reserved vram info print drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 12 ++- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 10 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c | 1 - drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 7 +- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 35 drivers/gpu/drm/amd/amdgpu/soc15.c | 7 +- drivers/gpu/drm/amd/amdgpu/vi.c| 11 ++- drivers/gpu/drm/amd/display/dc/core/dc.c | 36 - drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 20 + .../gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 2 +- .../drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c| 92 +- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 4 +- drivers/gpu/drm/radeon/radeon_gem.c| 4 +- 13 files changed, 162 insertions(+), 79 deletions(-)
Re: [PATCH] drm/amdkfd: fix and enable debugging for gfx11
On 2023-06-07 16:20, Jonathan Kim wrote:
There are a couple of fixes required to enable gfx11 debugging.
First, ADD_QUEUE.trap_en is an inappropriate place to toggle
a per-process register so move it to SET_SHADER_DEBUGGER.trap_en.
When ADD_QUEUE.skip_process_ctx_clear is set, MES will prioritize
the SET_SHADER_DEBUGGER.trap_en setting.
Second, to preserve correct save/restore priviledged wave states
in coordination with the trap enablement setting, resume suspended
waves early in the disable call.
NOTE: The AMDGPU_MES_VERSION_MASK check is a place holder as
MES FW updates have been reviewed but is awaiting binary
creation. Once the binaries have been created, this check may
be subject to change.
v2: do a trap_en safety check in case old mes doesn't accept
unused trap_en d-word.
remove unnecessary process termination work around.
Signed-off-by: Jonathan Kim
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c| 7 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h| 4 +++-
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 1 +
drivers/gpu/drm/amd/amdkfd/kfd_debug.c | 14 ++
.../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 3 +--
drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 12 +++-
drivers/gpu/drm/amd/include/mes_v11_api_def.h | 1 +
7 files changed, 25 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
index 20cc3fffe921..e9091ebfe230 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
@@ -928,7 +928,8 @@ int amdgpu_mes_set_shader_debugger(struct amdgpu_device
*adev,
uint64_t process_context_addr,
uint32_t spi_gdbg_per_vmid_cntl,
const uint32_t *tcp_watch_cntl,
- uint32_t flags)
+ uint32_t flags,
+ bool trap_en)
{
struct mes_misc_op_input op_input = {0};
int r;
@@ -945,6 +946,10 @@ int amdgpu_mes_set_shader_debugger(struct amdgpu_device
*adev,
memcpy(op_input.set_shader_debugger.tcp_watch_cntl, tcp_watch_cntl,
sizeof(op_input.set_shader_debugger.tcp_watch_cntl));
+ if (((adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) >>
+ AMDGPU_MES_API_VERSION_SHIFT) >= 14)
+ op_input.set_shader_debugger.trap_en = trap_en;
+
It's probably too late to change the GFX11 MES API at this point. But
why didn't they just add a trap_en bit in the existing flags field? That
could have avoided the need for the compatibility checks.
Anyway, the patch is
Reviewed-by: Felix Kuehling
amdgpu_mes_lock(&adev->mes);
r = adev->mes.funcs->misc_op(&adev->mes, &op_input);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
index b5f5eed2b5ef..2d6ac30b7135 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
@@ -294,6 +294,7 @@ struct mes_misc_op_input {
} flags;
uint32_t spi_gdbg_per_vmid_cntl;
uint32_t tcp_watch_cntl[4];
+ uint32_t trap_en;
} set_shader_debugger;
};
};
@@ -361,7 +362,8 @@ int amdgpu_mes_set_shader_debugger(struct amdgpu_device
*adev,
uint64_t process_context_addr,
uint32_t spi_gdbg_per_vmid_cntl,
const uint32_t *tcp_watch_cntl,
- uint32_t flags);
+ uint32_t flags,
+ bool trap_en);
int amdgpu_mes_add_ring(struct amdgpu_device *adev, int gang_id,
int queue_type, int idx,
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
index c4e3cb8d44de..1bdaa00c0b46 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
@@ -347,6 +347,7 @@ static int mes_v11_0_misc_op(struct amdgpu_mes *mes,
memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl,
input->set_shader_debugger.tcp_watch_cntl,
sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl));
+ misc_pkt.set_shader_debugger.trap_en =
input->set_shader_debugger.trap_en;
break;
default:
DRM_ERROR("unsupported misc op (%d) \n", input->op);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
b/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
index 125274445f43..cd34e7aaead4 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_debug.c
@@ -349,12 +349,13 @@ int kfd_dbg_set_mes_debug_mode(struct kfd_process_device
*pdd)
{
RE: [PATCH] drm/amdkfd: fix and enable debugging for gfx11
[Public]
> -Original Message-
> From: Kuehling, Felix
> Sent: Wednesday, June 7, 2023 6:23 PM
> To: Kim, Jonathan ; amd-gfx@lists.freedesktop.org
> Cc: Huang, JinHuiEric
> Subject: Re: [PATCH] drm/amdkfd: fix and enable debugging for gfx11
>
>
> On 2023-06-07 16:20, Jonathan Kim wrote:
> > There are a couple of fixes required to enable gfx11 debugging.
> >
> > First, ADD_QUEUE.trap_en is an inappropriate place to toggle
> > a per-process register so move it to SET_SHADER_DEBUGGER.trap_en.
> > When ADD_QUEUE.skip_process_ctx_clear is set, MES will prioritize
> > the SET_SHADER_DEBUGGER.trap_en setting.
> >
> > Second, to preserve correct save/restore priviledged wave states
> > in coordination with the trap enablement setting, resume suspended
> > waves early in the disable call.
> >
> > NOTE: The AMDGPU_MES_VERSION_MASK check is a place holder as
> > MES FW updates have been reviewed but is awaiting binary
> > creation. Once the binaries have been created, this check may
> > be subject to change.
> >
> > v2: do a trap_en safety check in case old mes doesn't accept
> > unused trap_en d-word.
> > remove unnecessary process termination work around.
> >
> > Signed-off-by: Jonathan Kim
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c| 7 ++-
> > drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h| 4 +++-
> > drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 1 +
> > drivers/gpu/drm/amd/amdkfd/kfd_debug.c | 14 ++
> > .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 3 +--
> > drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 12 +++-
> > drivers/gpu/drm/amd/include/mes_v11_api_def.h | 1 +
> > 7 files changed, 25 insertions(+), 17 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> > index 20cc3fffe921..e9091ebfe230 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> > @@ -928,7 +928,8 @@ int amdgpu_mes_set_shader_debugger(struct
> amdgpu_device *adev,
> > uint64_t process_context_addr,
> > uint32_t spi_gdbg_per_vmid_cntl,
> > const uint32_t *tcp_watch_cntl,
> > - uint32_t flags)
> > + uint32_t flags,
> > + bool trap_en)
> > {
> > struct mes_misc_op_input op_input = {0};
> > int r;
> > @@ -945,6 +946,10 @@ int amdgpu_mes_set_shader_debugger(struct
> amdgpu_device *adev,
> > memcpy(op_input.set_shader_debugger.tcp_watch_cntl,
> tcp_watch_cntl,
> >
> sizeof(op_input.set_shader_debugger.tcp_watch_cntl));
> >
> > + if (((adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK)
> >>
> > + AMDGPU_MES_API_VERSION_SHIFT) >= 14)
> > + op_input.set_shader_debugger.trap_en = trap_en;
> > +
>
> It's probably too late to change the GFX11 MES API at this point. But
> why didn't they just add a trap_en bit in the existing flags field? That
> could have avoided the need for the compatibility checks.
Thanks for the review. That was a decision I made.
The flags line up with the SQ_DEBUG register and will line up with the
set_flags API.
Right now, they're a small selection but could expand to the full 32-bit width
in the future (or even skip bit places and HW is much harder to change).
Also, trap_en really only needs to toggle for GFX11 as a work around. It
should always be set for non-GFX11.
So the flags should probably be reserved for things we actually want to toggle
on an ongoing conditional basis.
Thanks,
Jon
>
> Anyway, the patch is
>
> Reviewed-by: Felix Kuehling
>
>
> > amdgpu_mes_lock(&adev->mes);
> >
> > r = adev->mes.funcs->misc_op(&adev->mes, &op_input);
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
> > index b5f5eed2b5ef..2d6ac30b7135 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
> > @@ -294,6 +294,7 @@ struct mes_misc_op_input {
> > } flags;
> > uint32_t spi_gdbg_per_vmid_cntl;
> > uint32_t tcp_watch_cntl[4];
> > + uint32_t trap_en;
> > } set_shader_debugger;
> > };
> > };
> > @@ -361,7 +362,8 @@ int amdgpu_mes_set_shader_debugger(struct
> amdgpu_device *adev,
> > uint64_t process_context_addr,
> > uint32_t spi_gdbg_per_vmid_cntl,
> > const uint32_t *tcp_watch_cntl,
> > - uint32_t flags);
> > + uint32_t flags,
> > + bool trap_en);
> >
> > int amdgpu_mes_add_ring(struct amdgpu_device *adev, int gang_id,
> > int queue_type, int idx,
> > diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
>
RE: [PATCH v2 06/07] drm/amdgpu: add option params to enforce process isolation between graphics and compute
[AMD Official Use Only - General]
Hi Felix
Yes. This patch is aiming to avoid concurrent running of kernel graphics queue
and kernel compute queue.
Previously we might get wrong guilty job if a bad compute job and a good gfx
job submitted concurrently.
Like Xorg might be crashed if we submitted a bad compute job in another process
at the same time.
Advanced TDR can resolve this issue by the extra job resubmission to identify
the real bad job.
After removing advanced TDR(commit 06a2d7cc3f0476be4682ef90eb09a28fa3daed37),
we need another method to fix this issue.
As suggested from Christian, we can use the reserved vmid to prevent the
concurrency of compute and gfx to enforce isolation.
Here we only focus on KGQ/KCQ, not considering KFD compute since it is using
another set of VMID.
Christian, do you have any comments?
Best,
Zhenguo
-Original Message-
From: Kuehling, Felix
Sent: Wednesday, June 7, 2023 9:35 PM
To: Li, Chong(Alan) ; amd-gfx@lists.freedesktop.org
Cc: Koenig, Christian ; Yin, ZhenGuo (Chris)
Subject: Re: [PATCH v2 06/07] drm/amdgpu: add option params to enforce process
isolation between graphics and compute
I can't see the other patches in this series, so I'm missing some context. I
don't understand what "process isolation between graphics and compute" means
here. It seems to be unrelated to KFD compute. This patch seems to be mostly
about handling of reserved VMIDs. Maybe you're trying to avoid running Vulcan
graphics and compute concurrently? But this does not prevent concurrency with
KFD compute.
Can you clarify what this is for?
Thanks,
Felix
Am 2023-06-07 um 06:57 schrieb Chong Li:
> enforce process isolation between graphics and compute via using the same
> reserved vmid.
>
> v2: remove params "struct amdgpu_vm *vm" from
> amdgpu_vmid_alloc_reserved and amdgpu_vmid_free_reserved.
>
> Signed-off-by: Chong Li
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 10 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c | 17 +++--
> drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h | 6 ++
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 22 +-
> 5 files changed, 36 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index ce196badf42d..ef098a7287d0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -215,6 +215,7 @@ extern int amdgpu_force_asic_type;
> extern int amdgpu_smartshift_bias;
> extern int amdgpu_use_xgmi_p2p;
> extern int amdgpu_mtype_local;
> +extern bool enforce_isolation;
> #ifdef CONFIG_HSA_AMD
> extern int sched_policy;
> extern bool debug_evictions;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index 3d91e123f9bd..fdb6fb8229ab 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -153,7 +153,7 @@ uint amdgpu_pg_mask = 0x;
> uint amdgpu_sdma_phase_quantum = 32;
> char *amdgpu_disable_cu;
> char *amdgpu_virtual_display;
> -
> +bool enforce_isolation;
> /*
>* OverDrive(bit 14) disabled by default
>* GFX DCS(bit 19) disabled by default @@ -973,6 +973,14 @@
> MODULE_PARM_DESC(
> 4 =
> AMDGPU_CPX_PARTITION_MODE)");
> module_param_named(user_partt_mode, amdgpu_user_partt_mode, uint,
> 0444);
>
> +
> +/**
> + * DOC: enforce_isolation (bool)
> + * enforce process isolation between graphics and compute via using the same
> reserved vmid.
> + */
> +module_param(enforce_isolation, bool, 0444);
> +MODULE_PARM_DESC(enforce_isolation, "enforce process isolation
> +between graphics and compute . enforce_isolation = on");
> +
> /* These devices are not supported by amdgpu.
>* They are supported by the mach64, r128, radeon drivers
>*/
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
> index c991ca0b7a1c..ff1ea99292fb 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
> @@ -409,7 +409,7 @@ int amdgpu_vmid_grab(struct amdgpu_vm *vm, struct
> amdgpu_ring *ring,
> if (r || !idle)
> goto error;
>
> - if (vm->reserved_vmid[vmhub]) {
> + if (vm->reserved_vmid[vmhub] || (enforce_isolation && (vmhub ==
> +AMDGPU_GFXHUB(0 {
> r = amdgpu_vmid_grab_reserved(vm, ring, job, &id, fence);
> if (r || !id)
> goto error;
> @@ -460,14 +460,11 @@ int amdgpu_vmid_grab(struct amdgpu_vm *vm, struct
> amdgpu_ring *ring,
> }
>
> int amdgpu_vmid_alloc_reserved(struct amdgpu_device *adev,
> -struct amdgpu_vm *vm,
> unsigned vmhub)
> {
> struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
>
> mutex_lock(&id_mgr-
RE: [PATCH 2/2] drm/amd: Tighten permissions on VBIOS flashing attributes
[AMD Official Use Only - General]
> -Original Message-
> From: Limonciello, Mario
> Sent: Wednesday, June 7, 2023 1:53 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Limonciello, Mario
> Subject: [PATCH 2/2] drm/amd: Tighten permissions on VBIOS flashing
> attributes
>
> Non-root users shouldn't be able to try to trigger a VBIOS flash
> or query the flashing status. This should be reserved for users with the
> appropriate permissions.
>
> Fixes: 8424f2ccb3c0 ("drm/amdgpu/psp: Add vbflash sysfs interface
> support")
> Reviewed-by: Alex Deucher
> Signed-off-by: Mario Limonciello
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> index 8c60db176119..488d5b7ab97c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> @@ -3671,13 +3671,13 @@ static ssize_t
> amdgpu_psp_vbflash_status(struct device *dev,
> }
>
> static const struct bin_attribute psp_vbflash_bin_attr = {
> - .attr = {.name = "psp_vbflash", .mode = 0664},
> + .attr = {.name = "psp_vbflash", .mode = 0220},
I noticed a mistake with this, it should be 0660.
If no other feedback I'll correct it when committing.
> .size = 0,
> .write = amdgpu_psp_vbflash_write,
> .read = amdgpu_psp_vbflash_read,
> };
>
> -static DEVICE_ATTR(psp_vbflash_status, 0444, amdgpu_psp_vbflash_status,
> NULL);
> +static DEVICE_ATTR(psp_vbflash_status, 0440, amdgpu_psp_vbflash_status,
> NULL);
>
> int amdgpu_psp_sysfs_init(struct amdgpu_device *adev)
> {
> --
> 2.34.1
Re: [PATCH 3/3] drm/amd/pm: enable more Pstates profile levels for SMU v13.0.4
[AMD Official Use Only - General]
Series is:
Reviewed-by: Yifan Zhang
From: Huang, Tim
Sent: Wednesday, June 7, 2023 4:02 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Zhang, Yifan
; Liu, Aaron ; Guo, Shikai
; Huang, Tim
Subject: [PATCH 3/3] drm/amd/pm: enable more Pstates profile levels for SMU
v13.0.4
This patch enables following UMD stable Pstates profile
levels for power_dpm_force_performance_level interface.
- profile_peak
- profile_min_mclk
- profile_min_sclk
- profile_standard
Signed-off-by: Tim Huang
---
.../drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c | 54 ++-
1 file changed, 53 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
index 315a6d8bde2e..ef37dda9908f 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
@@ -54,6 +54,10 @@
#define FEATURE_MASK(feature) (1ULL << feature)
+#define SMU_13_0_4_UMD_PSTATE_GFXCLK 938
+#define SMU_13_0_4_UMD_PSTATE_SOCCLK 938
+#define SMU_13_0_4_UMD_PSTATE_FCLK 1875
+
#define SMC_DPM_FEATURE ( \
FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \
FEATURE_MASK(FEATURE_VCN_DPM_BIT)| \
@@ -908,6 +912,50 @@ static int smu_v13_0_4_force_clk_levels(struct smu_context
*smu,
return ret;
}
+static int smu_v13_0_4_get_dpm_profile_freq(struct smu_context *smu,
+ enum amd_dpm_forced_level level,
+ enum smu_clk_type clk_type,
+ uint32_t *min_clk,
+ uint32_t *max_clk)
+{
+ int ret = 0;
+ uint32_t clk_limit = 0;
+
+ switch (clk_type) {
+ case SMU_GFXCLK:
+ case SMU_SCLK:
+ clk_limit = SMU_13_0_4_UMD_PSTATE_GFXCLK;
+ if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
+ smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL,
&clk_limit);
+ else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK)
+ smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SCLK,
&clk_limit, NULL);
+ break;
+ case SMU_SOCCLK:
+ clk_limit = SMU_13_0_4_UMD_PSTATE_SOCCLK;
+ if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
+ smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SOCCLK,
NULL, &clk_limit);
+ break;
+ case SMU_FCLK:
+ clk_limit = SMU_13_0_4_UMD_PSTATE_FCLK;
+ if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
+ smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL,
&clk_limit);
+ else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK)
+ smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_FCLK,
&clk_limit, NULL);
+ break;
+ case SMU_VCLK:
+ smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL,
&clk_limit);
+ break;
+ case SMU_DCLK:
+ smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL,
&clk_limit);
+ break;
+ default:
+ ret = -EINVAL;
+ break;
+ }
+ *min_clk = *max_clk = clk_limit;
+ return ret;
+}
+
static int smu_v13_0_4_set_performance_level(struct smu_context *smu,
enum amd_dpm_forced_level level)
{
@@ -955,7 +1003,11 @@ static int smu_v13_0_4_set_performance_level(struct
smu_context *smu,
case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
- /* Temporarily do nothing since the optimal clocks haven't been
provided yet */
+ smu_v13_0_4_get_dpm_profile_freq(smu, level, SMU_SCLK,
&sclk_min, &sclk_max);
+ smu_v13_0_4_get_dpm_profile_freq(smu, level, SMU_FCLK,
&fclk_min, &fclk_max);
+ smu_v13_0_4_get_dpm_profile_freq(smu, level, SMU_SOCCLK,
&socclk_min, &socclk_max);
+ smu_v13_0_4_get_dpm_profile_freq(smu, level, SMU_VCLK,
&vclk_min, &vclk_max);
+ smu_v13_0_4_get_dpm_profile_freq(smu, level, SMU_DCLK,
&dclk_min, &dclk_max);
break;
case AMD_DPM_FORCED_LEVEL_MANUAL:
case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
--
2.34.1
[PATCH v2] drm/amd/pm: enable more Pstates profile levels for yellow_carp
This patch enables following UMD stable Pstates profile levels for
power_dpm_force_performance_level interface.
- profile_peak
- profile_min_mclk
- profile_min_sclk
- profile_standard
Signed-off-by: shikaguo
---
.../drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c | 94 ++-
.../drm/amd/pm/swsmu/smu13/yellow_carp_ppt.h | 5 +-
2 files changed, 95 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
index a92da336ecec..5c968ab2ea8d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
@@ -957,6 +957,9 @@ static int yellow_carp_set_soft_freq_limited_range(struct
smu_context *smu,
uint32_t max)
{
enum smu_message_type msg_set_min, msg_set_max;
+ uint32_t min_clk = min;
+ uint32_t max_clk = max;
+
int ret = 0;
if (!yellow_carp_clk_dpm_is_enabled(smu, clk_type))
@@ -985,11 +988,17 @@ static int yellow_carp_set_soft_freq_limited_range(struct
smu_context *smu,
return -EINVAL;
}
- ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_min, min, NULL);
+ if (clk_type == SMU_VCLK) {
+ min_clk = min << SMU_13_VCLK_SHIFT;
+ max_clk = max << SMU_13_VCLK_SHIFT;
+ }
+
+ ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_min, min_clk, NULL);
+
if (ret)
goto out;
- ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_max, max, NULL);
+ ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_max, max_clk, NULL);
if (ret)
goto out;
@@ -1107,6 +1116,50 @@ static int yellow_carp_force_clk_levels(struct
smu_context *smu,
return ret;
}
+static int yellow_carp_get_dpm_profile_freq(struct smu_context *smu,
+ enum amd_dpm_forced_level level,
+ enum smu_clk_type clk_type,
+ uint32_t *min_clk,
+ uint32_t *max_clk)
+{
+ int ret = 0;
+ uint32_t clk_limit = 0;
+
+ switch (clk_type) {
+ case SMU_GFXCLK:
+ case SMU_SCLK:
+ clk_limit = YELLOW_CARP_UMD_PSTATE_GFXCLK;
+ if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
+ yellow_carp_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL,
&clk_limit);
+ else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK)
+ yellow_carp_get_dpm_ultimate_freq(smu, SMU_SCLK,
&clk_limit, NULL);
+ break;
+ case SMU_SOCCLK:
+ clk_limit = YELLOW_CARP_UMD_PSTATE_SOCCLK;
+ if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
+ yellow_carp_get_dpm_ultimate_freq(smu, SMU_SOCCLK,
NULL, &clk_limit);
+ break;
+ case SMU_FCLK:
+ clk_limit = YELLOW_CARP_UMD_PSTATE_FCLK;
+ if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
+ yellow_carp_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL,
&clk_limit);
+ else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK)
+ yellow_carp_get_dpm_ultimate_freq(smu, SMU_FCLK,
&clk_limit, NULL);
+ break;
+ case SMU_VCLK:
+ yellow_carp_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL,
&clk_limit);
+ break;
+ case SMU_DCLK:
+ yellow_carp_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL,
&clk_limit);
+ break;
+ default:
+ ret = -EINVAL;
+ break;
+ }
+ *min_clk = *max_clk = clk_limit;
+ return ret;
+}
+
static int yellow_carp_set_performance_level(struct smu_context *smu,
enum amd_dpm_forced_level level)
{
@@ -1114,6 +1167,9 @@ static int yellow_carp_set_performance_level(struct
smu_context *smu,
uint32_t sclk_min = 0, sclk_max = 0;
uint32_t fclk_min = 0, fclk_max = 0;
uint32_t socclk_min = 0, socclk_max = 0;
+ uint32_t vclk_min = 0, vclk_max = 0;
+ uint32_t dclk_min = 0, dclk_max = 0;
+
int ret = 0;
switch (level) {
@@ -1121,28 +1177,42 @@ static int yellow_carp_set_performance_level(struct
smu_context *smu,
yellow_carp_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL,
&sclk_max);
yellow_carp_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL,
&fclk_max);
yellow_carp_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL,
&socclk_max);
+ yellow_carp_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL,
&vclk_max);
+ yellow_carp_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL,
&dclk_max);
sclk_min = sclk_max;
fclk_min = fclk_max;
socclk_min = socclk_max;
+
[PATCH] drm/amdgpu: expose num_hops and num_links xgmi info through dev attr
Add these two dev attrs for xgmi info details which is helpful for
developers checking the xgmi topology by catting the sys file directly.
Take 4 cards with xgmi connection as an example, get the num_hops for each
device or node through xmig_hive_info dir like,
cat /sys/bus/pci/devices/:41:00.0/xgmi_hive_info/node1/num_hops
will return "00 41 41 41" where "00" stands for the hops to node1 itself
and "41" is the hops in hex format to every other node in the same hive.
There are node1/node2/node3/node4 representing 4 cards in the hive.
The same for num_links dev attr.
Signed-off-by: Shiwu Zhang
Acked-by: Le Ma
Reviewed-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 46
1 file changed, 46 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
index 44822dd98e5e..9c0fc23ed5b4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
@@ -331,6 +331,36 @@ static ssize_t amdgpu_xgmi_show_device_id(struct device
*dev,
}
+static ssize_t amdgpu_xgmi_show_num_hops(struct device *dev,
+struct device_attribute *attr,
+char *buf)
+{
+ struct drm_device *ddev = dev_get_drvdata(dev);
+ struct amdgpu_device *adev = drm_to_adev(ddev);
+ struct psp_xgmi_topology_info *top = &adev->psp.xgmi_context.top_info;
+ int i;
+ for (i=0; i < top->num_nodes; i++) {
+ sprintf(buf + 3*i, "%02x ", top->nodes[i].num_hops);
+ }
+
+ return sysfs_emit(buf, "%s\n", buf);
+}
+
+static ssize_t amdgpu_xgmi_show_num_links(struct device *dev,
+struct device_attribute *attr,
+char *buf)
+{
+ struct drm_device *ddev = dev_get_drvdata(dev);
+ struct amdgpu_device *adev = drm_to_adev(ddev);
+ struct psp_xgmi_topology_info *top = &adev->psp.xgmi_context.top_info;
+ int i;
+ for (i=0; i < top->num_nodes; i++) {
+ sprintf(buf + 3*i, "%02x ", top->nodes[i].num_links);
+ }
+
+ return sysfs_emit(buf, "%s\n", buf);
+}
+
#define AMDGPU_XGMI_SET_FICAA(o) ((o) | 0x456801)
static ssize_t amdgpu_xgmi_show_error(struct device *dev,
struct device_attribute *attr,
@@ -367,6 +397,8 @@ static ssize_t amdgpu_xgmi_show_error(struct device *dev,
static DEVICE_ATTR(xgmi_device_id, S_IRUGO, amdgpu_xgmi_show_device_id, NULL);
static DEVICE_ATTR(xgmi_error, S_IRUGO, amdgpu_xgmi_show_error, NULL);
+static DEVICE_ATTR(xgmi_num_hops, S_IRUGO, amdgpu_xgmi_show_num_hops, NULL);
+static DEVICE_ATTR(xgmi_num_links, S_IRUGO, amdgpu_xgmi_show_num_links, NULL);
static int amdgpu_xgmi_sysfs_add_dev_info(struct amdgpu_device *adev,
struct amdgpu_hive_info *hive)
@@ -386,6 +418,15 @@ static int amdgpu_xgmi_sysfs_add_dev_info(struct
amdgpu_device *adev,
if (ret)
pr_err("failed to create xgmi_error\n");
+ /* Create xgmi num hops file */
+ ret = device_create_file(adev->dev, &dev_attr_xgmi_num_hops);
+ if (ret)
+ pr_err("failed to create xgmi_num_hops\n");
+
+ /* Create xgmi num links file */
+ ret = device_create_file(adev->dev, &dev_attr_xgmi_num_links);
+ if (ret)
+ pr_err("failed to create xgmi_num_links\n");
/* Create sysfs link to hive info folder on the first device */
if (hive->kobj.parent != (&adev->dev->kobj)) {
@@ -413,6 +454,9 @@ static int amdgpu_xgmi_sysfs_add_dev_info(struct
amdgpu_device *adev,
remove_file:
device_remove_file(adev->dev, &dev_attr_xgmi_device_id);
+ device_remove_file(adev->dev, &dev_attr_xgmi_error);
+ device_remove_file(adev->dev, &dev_attr_xgmi_num_hops);
+ device_remove_file(adev->dev, &dev_attr_xgmi_num_links);
success:
return ret;
@@ -426,6 +470,8 @@ static void amdgpu_xgmi_sysfs_rem_dev_info(struct
amdgpu_device *adev,
device_remove_file(adev->dev, &dev_attr_xgmi_device_id);
device_remove_file(adev->dev, &dev_attr_xgmi_error);
+ device_remove_file(adev->dev, &dev_attr_xgmi_num_hops);
+ device_remove_file(adev->dev, &dev_attr_xgmi_num_links);
if (hive->kobj.parent != (&adev->dev->kobj))
sysfs_remove_link(&adev->dev->kobj,"xgmi_hive_info");
--
2.17.1
