[PATCH] drm/amd: Drop USB-C PD F/W flashing support

[Mario Limonciello]

This support was introduced for pre-navi3x dGPUS.  The interface that
this was wired up to isn't usable by fwupd, and no devices had a need
to release firmware into the wild.

Navi3x dGPUs introduce an interface that can flash the entire IFWI
image that is acceptable by userspace software like fwupd.

Signed-off-by: Mario Limonciello 
---
 Documentation/gpu/amdgpu/flashing.rst   | 12 
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 91 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 10 ---
 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c  | 60 
 drivers/gpu/drm/amd/amdgpu/psp_v13_0.c  | 60 
 5 files changed, 233 deletions(-)

diff --git a/Documentation/gpu/amdgpu/flashing.rst 
b/Documentation/gpu/amdgpu/flashing.rst
index bd745c42a538f..4556d58866e8e 100644
--- a/Documentation/gpu/amdgpu/flashing.rst
+++ b/Documentation/gpu/amdgpu/flashing.rst
@@ -16,18 +16,6 @@ The IFWI flash process is:
 3. "Read" from the `psp_vbflash` sysfs file to initiate the flash process.
 4. Poll the `psp_vbflash_status` sysfs file to determine when the flash 
process completes.
 
-USB-C PD F/W
-
-On GPUs that support flashing an updated USB-C PD firmware image, the process
-is done using the `usbc_pd_fw` sysfs file.
-
-* Reading the file will provide the current firmware version.
-* Writing the name of a firmware payload stored in `/lib/firmware/amdgpu` to 
the sysfs file will initiate the flash process.
-
-The firmware payload stored in `/lib/firmware/amdgpu` can be named any name
-as long as it doesn't conflict with other existing binaries that are used by
-`amdgpu`.
-
 sysfs files
 ---
 .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 8fdca54bb8a11..15450b9aabdae 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -3471,88 +3471,6 @@ static int psp_set_powergating_state(void *handle,
return 0;
 }
 
-static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev,
-struct device_attribute *attr,
-char *buf)
-{
-   struct drm_device *ddev = dev_get_drvdata(dev);
-   struct amdgpu_device *adev = drm_to_adev(ddev);
-   uint32_t fw_ver;
-   int ret;
-
-   if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
-   DRM_INFO("PSP block is not ready yet.");
-   return -EBUSY;
-   }
-
-   mutex_lock(>psp.mutex);
-   ret = psp_read_usbc_pd_fw(>psp, _ver);
-   mutex_unlock(>psp.mutex);
-
-   if (ret) {
-   DRM_ERROR("Failed to read USBC PD FW, err = %d", ret);
-   return ret;
-   }
-
-   return sysfs_emit(buf, "%x\n", fw_ver);
-}
-
-static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev,
-  struct device_attribute 
*attr,
-  const char *buf,
-  size_t count)
-{
-   struct drm_device *ddev = dev_get_drvdata(dev);
-   struct amdgpu_device *adev = drm_to_adev(ddev);
-   int ret, idx;
-   char fw_name[100];
-   const struct firmware *usbc_pd_fw;
-   struct amdgpu_bo *fw_buf_bo = NULL;
-   uint64_t fw_pri_mc_addr;
-   void *fw_pri_cpu_addr;
-
-   if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
-   DRM_INFO("PSP block is not ready yet.");
-   return -EBUSY;
-   }
-
-   if (!drm_dev_enter(ddev, ))
-   return -ENODEV;
-
-   snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf);
-   ret = request_firmware(_pd_fw, fw_name, adev->dev);
-   if (ret)
-   goto fail;
-
-   /* LFB address which is aligned to 1MB boundary per PSP request */
-   ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x10,
- AMDGPU_GEM_DOMAIN_VRAM |
- AMDGPU_GEM_DOMAIN_GTT,
- _buf_bo, _pri_mc_addr,
- _pri_cpu_addr);
-   if (ret)
-   goto rel_buf;
-
-   memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size);
-
-   mutex_lock(>psp.mutex);
-   ret = psp_load_usbc_pd_fw(>psp, fw_pri_mc_addr);
-   mutex_unlock(>psp.mutex);
-
-   amdgpu_bo_free_kernel(_buf_bo, _pri_mc_addr, _pri_cpu_addr);
-
-rel_buf:
-   release_firmware(usbc_pd_fw);
-fail:
-   if (ret) {
-   DRM_ERROR("Failed to load USBC PD FW, err = %d", ret);
-   count = ret;
-   }
-
-   drm_dev_exit(idx);
-   return count;
-}
-
 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t 
bin_size)
 {
int idx;
@@ -3566,15 +3484,6 @@ void psp_copy_fw(struct psp_context 

[PATCH 2/2] drm/amd: flush any delayed gfxoff on suspend entry

[Tim Huang]

From: Mario Limonciello 

DCN 3.1.4 is reported to hang on s2idle entry if graphics activity
is happening during entry.  This is because GFXOFF was scheduled as
delayed but RLC gets disabled in s2idle entry sequence which will
hang GFX IP if not already in GFXOFF.

To help this problem, flush any delayed work for GFXOFF early in
s2idle entry sequence to ensure that it's off when RLC is changed.

commit 3964b0c2e843 ("drm/amdgpu: complete gfxoff allow signal during
suspend without delay") modified power gating flow so that if called
in s0ix that it ensured that GFXOFF wasn't put in work queue but
instead processed immediately.

This is dead code due to commit 5d70a549d00d ("drm/amdgpu: skip
CG/PG for gfx during S0ix") because GFXOFF will now not be explicitly
called as part of the suspend entry code.  Remove that dead code.

Signed-off-by: Mario Limonciello 
Signed-off-by: Tim Huang 
Reviewed-by: Lijo Lazar 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c| 9 +
 2 files changed, 2 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 1b3bd77d82da..e77f048c99d8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -4160,6 +4160,7 @@ int amdgpu_device_suspend(struct drm_device *dev, bool 
fbcon)

drm_fb_helper_set_suspend_unlocked(adev_to_drm(adev)->fb_helper, true);
 
cancel_delayed_work_sync(>delayed_init_work);
+   flush_delayed_work(>gfx.gfx_off_delay_work);
 
amdgpu_ras_suspend(adev);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index c76b6bfc4dab..2382921710ec 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -700,15 +700,8 @@ void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool 
enable)
 
if (adev->gfx.gfx_off_req_count == 0 &&
!adev->gfx.gfx_off_state) {
-   /* If going to s2idle, no need to wait */
-   if (adev->in_s0ix) {
-   if (!amdgpu_dpm_set_powergating_by_smu(adev,
-   AMD_IP_BLOCK_TYPE_GFX, true))
-   adev->gfx.gfx_off_state = true;
-   } else {
-   
schedule_delayed_work(>gfx.gfx_off_delay_work,
+   schedule_delayed_work(>gfx.gfx_off_delay_work,
  delay);
-   }
}
} else {
if (adev->gfx.gfx_off_req_count == 0) {
-- 
2.34.1

[PATCH 1/2] drm/amdgpu: skip fence GFX interrupts disable/enable for S0ix

[Tim Huang]

GFX v11.0.1 reported fence fallback timer expired issue on
SDMA and GFX rings after S0ix resume. This is generated by
EOP interrupts are disabled when S0ix suspend but fails to
re-enable when resume because of the GFX is in GFXOFF.

[  203.349571] [drm] Fence fallback timer expired on ring sdma0
[  203.349572] [drm] Fence fallback timer expired on ring gfx_0.0.0
[  203.861635] [drm] Fence fallback timer expired on ring gfx_0.0.0

For S0ix, GFX is in GFXOFF state, avoid to touch the GFX registers
to configure the fence driver interrupts for rings that belong to GFX.
The interrupts configuration will be restored by GFXOFF exit.

Signed-off-by: Tim Huang 
Reviewed-by: Mario Limonciello 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 41 +--
 1 file changed, 39 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
index c694b41f6461..7537f5aa76f0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
@@ -551,6 +551,41 @@ int amdgpu_fence_driver_sw_init(struct amdgpu_device *adev)
return 0;
 }
 
+/**
+ * amdgpu_fence_need_ring_interrupt_restore - helper function to check whether
+ * fence driver interrupts need to be restored.
+ *
+ * @ring: ring that to be checked
+ *
+ * Interrupts for rings that belong to GFX IP don't need to be restored
+ * when the target power state is s0ix.
+ *
+ * Return true if need to restore interrupts, false otherwise.
+ */
+static bool amdgpu_fence_need_ring_interrupt_restore(struct amdgpu_ring *ring)
+{
+   struct amdgpu_device *adev = ring->adev;
+   bool is_gfx_power_domain = false;
+
+   switch (ring->funcs->type) {
+   case AMDGPU_RING_TYPE_SDMA:
+   /* SDMA 5.x+ is part of GFX power domain so it's covered by GFXOFF */
+   if (adev->ip_versions[SDMA0_HWIP][0] >= IP_VERSION(5, 0, 0))
+   is_gfx_power_domain = true;
+   break;
+   case AMDGPU_RING_TYPE_GFX:
+   case AMDGPU_RING_TYPE_COMPUTE:
+   case AMDGPU_RING_TYPE_KIQ:
+   case AMDGPU_RING_TYPE_MES:
+   is_gfx_power_domain = true;
+   break;
+   default:
+   break;
+   }
+
+   return !(adev->in_s0ix && is_gfx_power_domain);
+}
+
 /**
  * amdgpu_fence_driver_hw_fini - tear down the fence driver
  * for all possible rings.
@@ -579,7 +614,8 @@ void amdgpu_fence_driver_hw_fini(struct amdgpu_device *adev)
amdgpu_fence_driver_force_completion(ring);
 
if (!drm_dev_is_unplugged(adev_to_drm(adev)) &&
-   ring->fence_drv.irq_src)
+   ring->fence_drv.irq_src &&
+   amdgpu_fence_need_ring_interrupt_restore(ring))
amdgpu_irq_put(adev, ring->fence_drv.irq_src,
   ring->fence_drv.irq_type);
 
@@ -655,7 +691,8 @@ void amdgpu_fence_driver_hw_init(struct amdgpu_device *adev)
continue;
 
/* enable the interrupt */
-   if (ring->fence_drv.irq_src)
+   if (ring->fence_drv.irq_src &&
+   amdgpu_fence_need_ring_interrupt_restore(ring))
amdgpu_irq_get(adev, ring->fence_drv.irq_src,
   ring->fence_drv.irq_type);
}
-- 
2.34.1

[PATCH] drm/amd/display: If HPD fails probe EDID to decide if monitor is present

[Mario Limonciello]

Some monitors return that they're disconnected while powered off
but the EDID can still be accessed.  Before determining that a
link is not available, try to access the EDID.

Reported-and-suggested-by: dark_syl...@yahoo.com.ar
Link: https://gitlab.freedesktop.org/drm/amd/-/issues/461
Signed-off-by: Mario Limonciello 
---
Cc: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/link/link_detection.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/link/link_detection.c 
b/drivers/gpu/drm/amd/display/dc/link/link_detection.c
index c9b6676eaf53..26a739128dd3 100644
--- a/drivers/gpu/drm/amd/display/dc/link/link_detection.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_detection.c
@@ -1233,6 +1233,8 @@ bool link_detect_connection_type(struct dc_link *link, 
enum dc_connection_type *
if (is_hpd_high) {
*type = dc_connection_single;
/* TODO: need to do the actual detection */
+   } else if (dm_helpers_read_local_edid(link->ctx, link, 
link->local_sink) == EDID_OK) {
+   *type = dc_connection_single;
} else {
*type = dc_connection_none;
if (link->connector_signal == SIGNAL_TYPE_EDP) {
-- 
2.34.1

Re: [PATCH] drm/radeon: Use pci_dev_id() to simplify the code

[Alex Deucher]

Applied.  Thanks!

On Fri, Aug 11, 2023 at 9:45 AM Zheng Zengkai  wrote:
>
> PCI core API pci_dev_id() can be used to get the BDF number for a pci
> device. We don't need to compose it mannually. Use pci_dev_id() to
> simplify the code a little bit.
>
> Signed-off-by: Zheng Zengkai 
> ---
>  drivers/gpu/drm/radeon/radeon_acpi.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/radeon/radeon_acpi.c 
> b/drivers/gpu/drm/radeon/radeon_acpi.c
> index 5771d1fcb073..603a78e41ba5 100644
> --- a/drivers/gpu/drm/radeon/radeon_acpi.c
> +++ b/drivers/gpu/drm/radeon/radeon_acpi.c
> @@ -618,7 +618,7 @@ int radeon_acpi_pcie_performance_request(struct 
> radeon_device *rdev,
>
> atcs_input.size = sizeof(struct atcs_pref_req_input);
> /* client id (bit 2-0: func num, 7-3: dev num, 15-8: bus num) */
> -   atcs_input.client_id = rdev->pdev->devfn | (rdev->pdev->bus->number 
> << 8);
> +   atcs_input.client_id = pci_dev_id(rdev->pdev);
> atcs_input.valid_flags_mask = ATCS_VALID_FLAGS_MASK;
> atcs_input.flags = ATCS_WAIT_FOR_COMPLETION;
> if (advertise)
> --
> 2.20.1
>

Re: [PATCH -next] drm/amdgpu: Remove duplicated includes

[Alex Deucher]

Applied.  Thanks!

On Thu, Aug 10, 2023 at 8:33 AM GUO Zihua  wrote:
>
> Remove duplicated includes in amdgpu_amdkfd_gpuvm.c and amdgpu_ttm.c.
> Resolves checkincludes message.
>
> Signed-off-by: GUO Zihua 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 1 -
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c  | 1 -
>  2 files changed, 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> index a136fba9f29b..7d6daf8d2bfa 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> @@ -39,7 +39,6 @@
>  #include "amdgpu_xgmi.h"
>  #include "kfd_priv.h"
>  #include "kfd_smi_events.h"
> -#include 
>
>  /* Userptr restore delay, just long enough to allow consecutive VM
>   * changes to accumulate
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index dea848bb55c1..f5aa1362c818 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -49,7 +49,6 @@
>  #include 
>
>  #include 
> -#include 
>
>  #include "amdgpu.h"
>  #include "amdgpu_object.h"
> --
> 2.17.1
>

Re: [PATCH] drm/amd/pm: Clean up errors in amdgpu_smu.h

[Alex Deucher]

Applied.  Thanks!

On Mon, Jul 31, 2023 at 5:30 AM Ran Sun  wrote:
>
> Fix the following errors reported by checkpatch:
>
> ERROR: open brace '{' following enum go on the same line
> ERROR: open brace '{' following struct go on the same line
>
> Signed-off-by: Ran Sun 
> ---
>  drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 36 +++
>  1 file changed, 12 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h 
> b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
> index 6e2069dcb6b9..190a90b24d74 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
> +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
> @@ -200,29 +200,25 @@ struct smu_power_state {
> struct smu_hw_power_state hardware;
>  };
>
> -enum smu_power_src_type
> -{
> +enum smu_power_src_type {
> SMU_POWER_SOURCE_AC,
> SMU_POWER_SOURCE_DC,
> SMU_POWER_SOURCE_COUNT,
>  };
>
> -enum smu_ppt_limit_type
> -{
> +enum smu_ppt_limit_type {
> SMU_DEFAULT_PPT_LIMIT = 0,
> SMU_FAST_PPT_LIMIT,
>  };
>
> -enum smu_ppt_limit_level
> -{
> +enum smu_ppt_limit_level {
> SMU_PPT_LIMIT_MIN = -1,
> SMU_PPT_LIMIT_CURRENT,
> SMU_PPT_LIMIT_DEFAULT,
> SMU_PPT_LIMIT_MAX,
>  };
>
> -enum smu_memory_pool_size
> -{
> +enum smu_memory_pool_size {
>  SMU_MEMORY_POOL_SIZE_ZERO   = 0,
>  SMU_MEMORY_POOL_SIZE_256_MB = 0x1000,
>  SMU_MEMORY_POOL_SIZE_512_MB = 0x2000,
> @@ -282,8 +278,7 @@ struct smu_clock_info {
> uint32_t max_bus_bandwidth;
>  };
>
> -struct smu_bios_boot_up_values
> -{
> +struct smu_bios_boot_up_values {
> uint32_trevision;
> uint32_tgfxclk;
> uint32_tuclk;
> @@ -305,8 +300,7 @@ struct smu_bios_boot_up_values
> uint32_tfirmware_caps;
>  };
>
> -enum smu_table_id
> -{
> +enum smu_table_id {
> SMU_TABLE_PPTABLE = 0,
> SMU_TABLE_WATERMARKS,
> SMU_TABLE_CUSTOM_DPM,
> @@ -326,8 +320,7 @@ enum smu_table_id
> SMU_TABLE_COUNT,
>  };
>
> -struct smu_table_context
> -{
> +struct smu_table_context {
> void*power_play_table;
> uint32_tpower_play_table_size;
> void*hardcode_pptable;
> @@ -390,8 +383,7 @@ struct smu_power_context {
>  };
>
>  #define SMU_FEATURE_MAX(64)
> -struct smu_feature
> -{
> +struct smu_feature {
> uint32_t feature_num;
> DECLARE_BITMAP(supported, SMU_FEATURE_MAX);
> DECLARE_BITMAP(allowed, SMU_FEATURE_MAX);
> @@ -416,21 +408,18 @@ struct mclock_latency_table {
> struct mclk_latency_entries  entries[MAX_REGULAR_DPM_NUM];
>  };
>
> -enum smu_reset_mode
> -{
> +enum smu_reset_mode {
>  SMU_RESET_MODE_0,
>  SMU_RESET_MODE_1,
>  SMU_RESET_MODE_2,
>  };
>
> -enum smu_baco_state
> -{
> +enum smu_baco_state {
> SMU_BACO_STATE_ENTER = 0,
> SMU_BACO_STATE_EXIT,
>  };
>
> -struct smu_baco_context
> -{
> +struct smu_baco_context {
> uint32_t state;
> bool platform_support;
> bool maco_support;
> @@ -478,8 +467,7 @@ struct stb_context {
>
>  #define WORKLOAD_POLICY_MAX 7
>
> -struct smu_context
> -{
> +struct smu_context {
> struct amdgpu_device*adev;
> struct amdgpu_irq_src   irq_source;
>
> --
> 2.17.1
>

Re: [PATCH] drm/amd/pm: Clean up errors in smu_v11_0_pptable.h

[Alex Deucher]

Applied.  Thanks!

On Mon, Jul 31, 2023 at 5:22 AM Ran Sun  wrote:
>
> Fix the following errors reported by checkpatch:
>
> ERROR: trailing whitespace
> ERROR: open brace '{' following struct go on the same line
> ERROR: code indent should use tabs where possible
>
> Signed-off-by: Ran Sun 
> ---
>  .../gpu/drm/amd/pm/swsmu/inc/smu_v11_0_pptable.h  | 15 ++-
>  1 file changed, 6 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0_pptable.h 
> b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0_pptable.h
> index 0116e3d04fad..df7430876e0c 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0_pptable.h
> +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0_pptable.h
> @@ -101,8 +101,7 @@ enum SMU_11_0_ODSETTING_ID {
>  };
>  #define SMU_11_0_MAX_ODSETTING32  //Maximum Number of ODSettings
>
> -struct smu_11_0_overdrive_table
> -{
> +struct smu_11_0_overdrive_table {
>  uint8_t  revision;//Revision = 
> SMU_11_0_PP_OVERDRIVE_VERSION
>  uint8_t  reserve[3];  //Zero filled 
> field reserved for future use
>  uint32_t feature_count;   //Total number 
> of supported features
> @@ -127,8 +126,7 @@ enum SMU_11_0_PPCLOCK_ID {
>  };
>  #define SMU_11_0_MAX_PPCLOCK  16  //Maximum Number of PP Clocks
>
> -struct smu_11_0_power_saving_clock_table
> -{
> +struct smu_11_0_power_saving_clock_table {
>  uint8_t  revision;//Revision = 
> SMU_11_0_PP_POWERSAVINGCLOCK_VERSION
>  uint8_t  reserve[3];  //Zero filled 
> field reserved for future use
>  uint32_t count;   
> //power_saving_clock_count = SMU_11_0_PPCLOCK_COUNT
> @@ -136,8 +134,7 @@ struct smu_11_0_power_saving_clock_table
>  uint32_t min[SMU_11_0_MAX_PPCLOCK];   
> //PowerSavingClock Mode Clock Minimum array In MHz
>  };
>
> -struct smu_11_0_powerplay_table
> -{
> +struct smu_11_0_powerplay_table {
>struct atom_common_table_header header;
>uint8_t  table_revision;
>uint16_t table_size;  //Driver portion table 
> size. The offset to smc_pptable including header size
> @@ -145,14 +142,14 @@ struct smu_11_0_powerplay_table
>uint32_t golden_revision;
>uint16_t format_id;
>uint32_t platform_caps;   
> //POWERPLAYABLE::ulPlatformCaps
> -
> +
>uint8_t  thermal_controller_type; //one of 
> SMU_11_0_PP_THERMALCONTROLLER
>
>uint16_t small_power_limit1;
>uint16_t small_power_limit2;
>uint16_t boost_power_limit;
> -  uint16_t od_turbo_power_limit;//Power limit setting 
> for Turbo mode in Performance UI Tuning.
> -  uint16_t od_power_save_power_limit;   //Power limit setting 
> for PowerSave/Optimal mode in Performance UI Tuning.
> +  uint16_t od_turbo_power_limit;//Power limit setting 
> for Turbo mode in Performance UI Tuning.
> +  uint16_t od_power_save_power_limit;   //Power limit setting 
> for PowerSave/Optimal mode in Performance UI Tuning.
>uint16_t software_shutdown_temp;
>
>uint16_t reserve[6];  //Zero filled field 
> reserved for future use
> --
> 2.17.1
>

Re: [PATCH 3/3] Revert "drm/amd/amdgpu: switch on/off vcn power profile mode"

[Shashank Sharma]

Ah, Thanks for pointing that out Alex.

@Arvind, please refer to the patch 
(https://patchwork.freedesktop.org/patch/504854/?series=109060=4) in 
previous series of SMU workload hints with UAPI (here: 
https://patchwork.freedesktop.org/series/109060/)


Regards

Shashank

On 14/08/2023 17:20, Alex Deucher wrote:

KFD also changes the profile when queues are active.  Please make sure
that is properly taken into account as well.

Alex

On Mon, Aug 14, 2023 at 3:36 AM Arvind Yadav  wrote:

This reverts commit 5ce71f59bb9bd3d8a09b96afdbc92975cb6dc303.

Reason for revert: New amdgpu_smu* api is added to switch
on/off profile mode. These new api will allow to change the
GPU power profile based on a submitted job.

Cc: Shashank Sharma 
Cc: Christian Koenig 
Cc: Alex Deucher 
Signed-off-by: Arvind Yadav 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 14 ++
  1 file changed, 2 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 2d94f1b63bd6..70777fcfa626 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -363,7 +363,6 @@ static void amdgpu_vcn_idle_work_handler(struct work_struct 
*work)
 container_of(work, struct amdgpu_device, vcn.idle_work.work);
 unsigned int fences = 0, fence[AMDGPU_MAX_VCN_INSTANCES] = {0};
 unsigned int i, j;
-   int r = 0;

 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
 if (adev->vcn.harvest_config & (1 << j))
@@ -392,10 +391,6 @@ static void amdgpu_vcn_idle_work_handler(struct 
work_struct *work)
 if (!fences && !atomic_read(>vcn.total_submission_cnt)) {
 amdgpu_device_ip_set_powergating_state(adev, 
AMD_IP_BLOCK_TYPE_VCN,
AMD_PG_STATE_GATE);
-   r = amdgpu_dpm_switch_power_profile(adev, 
PP_SMC_POWER_PROFILE_VIDEO,
-   false);
-   if (r)
-   dev_warn(adev->dev, "(%d) failed to disable video power 
profile mode\n", r);
 } else {
 schedule_delayed_work(>vcn.idle_work, VCN_IDLE_TIMEOUT);
 }
@@ -404,16 +399,11 @@ static void amdgpu_vcn_idle_work_handler(struct 
work_struct *work)
  void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
  {
 struct amdgpu_device *adev = ring->adev;
-   int r = 0;

 atomic_inc(>vcn.total_submission_cnt);

-   if (!cancel_delayed_work_sync(>vcn.idle_work)) {
-   r = amdgpu_dpm_switch_power_profile(adev, 
PP_SMC_POWER_PROFILE_VIDEO,
-   true);
-   if (r)
-   dev_warn(adev->dev, "(%d) failed to switch to video power 
profile mode\n", r);
-   }
+   if (!cancel_delayed_work_sync(>vcn.idle_work))
+   amdgpu_gfx_off_ctrl(adev, false);

 mutex_lock(>vcn.vcn_pg_lock);
 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
--
2.34.1

Re: [PATCH 3/3] Revert "drm/amd/amdgpu: switch on/off vcn power profile mode"

[Alex Deucher]

KFD also changes the profile when queues are active.  Please make sure
that is properly taken into account as well.

Alex

On Mon, Aug 14, 2023 at 3:36 AM Arvind Yadav  wrote:
>
> This reverts commit 5ce71f59bb9bd3d8a09b96afdbc92975cb6dc303.
>
> Reason for revert: New amdgpu_smu* api is added to switch
> on/off profile mode. These new api will allow to change the
> GPU power profile based on a submitted job.
>
> Cc: Shashank Sharma 
> Cc: Christian Koenig 
> Cc: Alex Deucher 
> Signed-off-by: Arvind Yadav 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 14 ++
>  1 file changed, 2 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> index 2d94f1b63bd6..70777fcfa626 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> @@ -363,7 +363,6 @@ static void amdgpu_vcn_idle_work_handler(struct 
> work_struct *work)
> container_of(work, struct amdgpu_device, vcn.idle_work.work);
> unsigned int fences = 0, fence[AMDGPU_MAX_VCN_INSTANCES] = {0};
> unsigned int i, j;
> -   int r = 0;
>
> for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
> if (adev->vcn.harvest_config & (1 << j))
> @@ -392,10 +391,6 @@ static void amdgpu_vcn_idle_work_handler(struct 
> work_struct *work)
> if (!fences && !atomic_read(>vcn.total_submission_cnt)) {
> amdgpu_device_ip_set_powergating_state(adev, 
> AMD_IP_BLOCK_TYPE_VCN,
>AMD_PG_STATE_GATE);
> -   r = amdgpu_dpm_switch_power_profile(adev, 
> PP_SMC_POWER_PROFILE_VIDEO,
> -   false);
> -   if (r)
> -   dev_warn(adev->dev, "(%d) failed to disable video 
> power profile mode\n", r);
> } else {
> schedule_delayed_work(>vcn.idle_work, VCN_IDLE_TIMEOUT);
> }
> @@ -404,16 +399,11 @@ static void amdgpu_vcn_idle_work_handler(struct 
> work_struct *work)
>  void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
>  {
> struct amdgpu_device *adev = ring->adev;
> -   int r = 0;
>
> atomic_inc(>vcn.total_submission_cnt);
>
> -   if (!cancel_delayed_work_sync(>vcn.idle_work)) {
> -   r = amdgpu_dpm_switch_power_profile(adev, 
> PP_SMC_POWER_PROFILE_VIDEO,
> -   true);
> -   if (r)
> -   dev_warn(adev->dev, "(%d) failed to switch to video 
> power profile mode\n", r);
> -   }
> +   if (!cancel_delayed_work_sync(>vcn.idle_work))
> +   amdgpu_gfx_off_ctrl(adev, false);
>
> mutex_lock(>vcn.vcn_pg_lock);
> amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
> --
> 2.34.1
>

Re: [PATCH 1/3] drm/amdgpu: Add new api to switch on/off power profile mode

[Shashank Sharma]

Hey Arvind,

On 14/08/2023 09:34, Arvind Yadav wrote:

This patch adds a function which will allow to
change the GPU power profile based on a submitted job.
This can optimize the power performance when the
workload is on.

Cc: Shashank Sharma 
Cc: Christian Koenig 
Cc: Alex Deucher 
Signed-off-by: Arvind Yadav 
---
  drivers/gpu/drm/amd/amdgpu/Makefile   |   2 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu.h   |   3 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c|   2 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_workload.c  | 156 ++
  drivers/gpu/drm/amd/include/amdgpu_workload.h |  44 +
  5 files changed, 206 insertions(+), 1 deletion(-)
  create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_workload.c
  create mode 100644 drivers/gpu/drm/amd/include/amdgpu_workload.h

diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile 
b/drivers/gpu/drm/amd/amdgpu/Makefile
index 415a7fa395c4..6a9e187d61e1 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -60,7 +60,7 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
amdgpu_umc.o smu_v11_0_i2c.o amdgpu_fru_eeprom.o amdgpu_rap.o \
amdgpu_fw_attestation.o amdgpu_securedisplay.o \
amdgpu_eeprom.o amdgpu_mca.o amdgpu_psp_ta.o amdgpu_lsdma.o \
-   amdgpu_ring_mux.o
+   amdgpu_ring_mux.o amdgpu_workload.o
  
  amdgpu-$(CONFIG_PROC_FS) += amdgpu_fdinfo.o
  
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h

index 02b827785e39..1939fa1af8a6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -107,6 +107,7 @@
  #include "amdgpu_fdinfo.h"
  #include "amdgpu_mca.h"
  #include "amdgpu_ras.h"
+#include "amdgpu_workload.h"
  
  #define MAX_GPU_INSTANCE		16
  
@@ -1050,6 +1051,8 @@ struct amdgpu_device {
  
  	booljob_hang;

booldc_enabled;
+
+   struct amdgpu_smu_workload  smu_workload;
  };
  
  static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 5c7d40873ee2..0ec18b8fe29f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3672,6 +3672,8 @@ int amdgpu_device_init(struct amdgpu_device *adev,
  
  	INIT_WORK(>xgmi_reset_work, amdgpu_device_xgmi_reset_func);
  
+	amdgpu_smu_workload_init(adev);

+
adev->gfx.gfx_off_req_count = 1;
adev->gfx.gfx_off_residency = 0;
adev->gfx.gfx_off_entrycount = 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_workload.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_workload.c
new file mode 100644
index ..ce0339d75c12
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_workload.c
@@ -0,0 +1,156 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright 2023 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include "amdgpu.h"
+
+/* 100 millsecond timeout */
+#define SMU_IDLE_TIMEOUT   msecs_to_jiffies(100)
+
+static enum PP_SMC_POWER_PROFILE
+ring_to_power_profile(uint32_t ring_type)
+{
+   switch (ring_type) {
+   case AMDGPU_RING_TYPE_GFX:
+   return PP_SMC_POWER_PROFILE_FULLSCREEN3D;
+   case AMDGPU_RING_TYPE_COMPUTE:
+   return PP_SMC_POWER_PROFILE_COMPUTE;
+   case AMDGPU_RING_TYPE_UVD:
+   case AMDGPU_RING_TYPE_VCE:
+   case AMDGPU_RING_TYPE_UVD_ENC:
+   case AMDGPU_RING_TYPE_VCN_DEC:
+   case AMDGPU_RING_TYPE_VCN_ENC:
+   case AMDGPU_RING_TYPE_VCN_JPEG:
+   return PP_SMC_POWER_PROFILE_VIDEO;
+   default:
+   return PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
+   }
+}
+
+static void
+amdgpu_power_profile_set(struct amdgpu_device *adev,
+enum PP_SMC_POWER_PROFILE profile)
This function expects the caller to hold the 

Re: [PATCH V7 4/9] wifi: mac80211: Add support for ACPI WBRF

[Andrew Lunn]

On Mon, Aug 14, 2023 at 09:50:49AM +, Quan, Evan wrote:
> [AMD Official Use Only - General]
> 
> Hi Andrew,
> 
> I sent out a new V8 series last week.
> A kernel parameter `wbrf` was introduced there to decide the policy.
> Please help to check whether that makes sense to you.
> Please share your insights there.

netdev has a pretty strong policy of not adding new kernel
parameters. It is a really painful interface to use, and there are
generally better configuration interfaces within netdev.

However, as far as i can see, it is outside of netdev, so this policy
does not necessarily apply.

 Andrew

Re: [PATCH 1/3] drm/amdgpu: Add new api to switch on/off power profile mode

[Alex Deucher]

On Mon, Aug 14, 2023 at 3:35 AM Arvind Yadav  wrote:
>
> This patch adds a function which will allow to
> change the GPU power profile based on a submitted job.
> This can optimize the power performance when the
> workload is on.

A few minor comments inline below.  One thing to double check is that
we properly cancel this work before a suspend or driver unload.  We
need to make sure this is taken care of before we take down the SMU.

Alex

>
> Cc: Shashank Sharma 
> Cc: Christian Koenig 
> Cc: Alex Deucher 
> Signed-off-by: Arvind Yadav 
> ---
>  drivers/gpu/drm/amd/amdgpu/Makefile   |   2 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h   |   3 +
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c|   2 +
>  drivers/gpu/drm/amd/amdgpu/amdgpu_workload.c  | 156 ++
>  drivers/gpu/drm/amd/include/amdgpu_workload.h |  44 +
>  5 files changed, 206 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_workload.c
>  create mode 100644 drivers/gpu/drm/amd/include/amdgpu_workload.h
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile 
> b/drivers/gpu/drm/amd/amdgpu/Makefile
> index 415a7fa395c4..6a9e187d61e1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/Makefile
> +++ b/drivers/gpu/drm/amd/amdgpu/Makefile
> @@ -60,7 +60,7 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
> amdgpu_umc.o smu_v11_0_i2c.o amdgpu_fru_eeprom.o amdgpu_rap.o \
> amdgpu_fw_attestation.o amdgpu_securedisplay.o \
> amdgpu_eeprom.o amdgpu_mca.o amdgpu_psp_ta.o amdgpu_lsdma.o \
> -   amdgpu_ring_mux.o
> +   amdgpu_ring_mux.o amdgpu_workload.o
>
>  amdgpu-$(CONFIG_PROC_FS) += amdgpu_fdinfo.o
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 02b827785e39..1939fa1af8a6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -107,6 +107,7 @@
>  #include "amdgpu_fdinfo.h"
>  #include "amdgpu_mca.h"
>  #include "amdgpu_ras.h"
> +#include "amdgpu_workload.h"
>
>  #define MAX_GPU_INSTANCE   16
>
> @@ -1050,6 +1051,8 @@ struct amdgpu_device {
>
> booljob_hang;
> booldc_enabled;
> +
> +   struct amdgpu_smu_workload  smu_workload;
>  };
>
>  static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 5c7d40873ee2..0ec18b8fe29f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -3672,6 +3672,8 @@ int amdgpu_device_init(struct amdgpu_device *adev,
>
> INIT_WORK(>xgmi_reset_work, amdgpu_device_xgmi_reset_func);
>
> +   amdgpu_smu_workload_init(adev);
> +
> adev->gfx.gfx_off_req_count = 1;
> adev->gfx.gfx_off_residency = 0;
> adev->gfx.gfx_off_entrycount = 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_workload.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_workload.c
> new file mode 100644
> index ..ce0339d75c12
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_workload.c
> @@ -0,0 +1,156 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright 2023 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> + */
> +
> +#include "amdgpu.h"
> +
> +/* 100 millsecond timeout */
> +#define SMU_IDLE_TIMEOUT   msecs_to_jiffies(100)
> +
> +static enum PP_SMC_POWER_PROFILE
> +ring_to_power_profile(uint32_t ring_type)
> +{
> +   switch (ring_type) {
> +   case AMDGPU_RING_TYPE_GFX:
> +   return PP_SMC_POWER_PROFILE_FULLSCREEN3D;
> +   case AMDGPU_RING_TYPE_COMPUTE:
> +   return PP_SMC_POWER_PROFILE_COMPUTE;
> +   case AMDGPU_RING_TYPE_UVD:
> +   case AMDGPU_RING_TYPE_VCE:
> +   case AMDGPU_RING_TYPE_UVD_ENC:
> +   

RE: [PATCH] drm/amdgpu: Remove gfxoff check in GFX v9.4.3

[Zhang, Hawking]

[AMD Official Use Only - General]

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: Lazar, Lijo 
Sent: Monday, August 14, 2023 22:28
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Deucher, Alexander 

Subject: [PATCH] drm/amdgpu: Remove gfxoff check in GFX v9.4.3

GFXOFF feature is not there for GFX 9.4.3 ASICs.

Signed-off-by: Lijo Lazar 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index 564770c3875e..4bbe9c5ed87f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
@@ -337,13 +337,11 @@ static uint64_t gfx_v9_4_3_get_gpu_clock_counter(struct 
amdgpu_device *adev)  {
uint64_t clock;

-   amdgpu_gfx_off_ctrl(adev, false);
mutex_lock(>gfx.gpu_clock_mutex);
WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
clock = (uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), 
regRLC_GPU_CLOCK_COUNT_LSB) |
((uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), 
regRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
mutex_unlock(>gfx.gpu_clock_mutex);
-   amdgpu_gfx_off_ctrl(adev, true);

return clock;
 }
--
2.25.1

[PATCH] drm/amdgpu: Remove gfxoff check in GFX v9.4.3

[Lijo Lazar]

GFXOFF feature is not there for GFX 9.4.3 ASICs.

Signed-off-by: Lijo Lazar 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index 564770c3875e..4bbe9c5ed87f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
@@ -337,13 +337,11 @@ static uint64_t gfx_v9_4_3_get_gpu_clock_counter(struct 
amdgpu_device *adev)
 {
uint64_t clock;
 
-   amdgpu_gfx_off_ctrl(adev, false);
mutex_lock(>gfx.gpu_clock_mutex);
WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
clock = (uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), 
regRLC_GPU_CLOCK_COUNT_LSB) |
((uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), 
regRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
mutex_unlock(>gfx.gpu_clock_mutex);
-   amdgpu_gfx_off_ctrl(adev, true);
 
return clock;
 }
-- 
2.25.1

Re: [PATCH v3] drm/amdgpu: skip xcp drm device allocation when out of drm resource

[Lazar, Lijo]

On 8/14/2023 7:28 PM, James Zhu wrote:


On 2023-08-12 13:00, Lazar, Lijo wrote:



On 8/12/2023 6:14 PM, James Zhu wrote:


On 2023-08-11 21:39, Lazar, Lijo wrote:


[AMD Official Use Only - General]


A dynamic partition switch could happen later.  The switch could 
still be successful in terms of hardware,
[JZ] Only ignore render node assignment, and remove visibility in 
user space, xcp continues to be generated as usual. so switch should 
work as usual


Switch is not useful for the user unless the apps can make use of the 
render nodes. A 'success' from hardware perspective doesn't turn out 
to be a 'success' for users eventually to make use of the extra 
partition.
[JZ] Yes, After switch, app can use the render nodes (no more than 64 
nodes in one system), Like 8P MI300X CPX mode,  with no external VGA 
device,all 64 nodes can be used. with one  external VGA device, 63 nodes 
can be used.


Understood. What I meant is we should be having the 'warn message' with 
partition switch (when user really wants to make use of partitions) 
rather than on driver load (as with this patch). Technically, some of 
those nodes are usable only after a partition switch.




and hence gives a false feeling of success even if there are no 
render nodes available for any app to make use of the partition.
[JZ] from driver prospective, the switch is real success, treat the 
last one harvested in user space.. there is warning in kernel log, 
and final solution for more than 64 nodes is on-going


The render nodes are allocated during driver load and the message will 
go unnoticed. We could still allow the switch, but the message should 
be there during a partition switch like 'only x/y (x out of y nodes) 
are usable'. The worst case is - only 1 out of N meaning no benefit - 
and in that case user may switch back to normal mode to make use of 
full compute power.




Also, a kfd node is not expected to have a valid xcp pointer on 
devices without partition.

[JZ] won't affect xcp pointer, only ddev.

This access could break then gpu->xcp->ddev.

[JZ] added skip when ddev==NULL


What I meant is xcp in kfd node could be NULL on SOCs like NV series. 
There should be a check for xcp before accessing ddev -
https://elixir.bootlin.com/linux/v6.5-rc5/source/drivers/gpu/drm/amd/amdkfd/kfd_device.c#L794 

[JZ] So it is potential bug before this patch. then we need review 
current code to add all necessary xcp check.


We already have checks - 
https://elixir.bootlin.com/linux/v6.5-rc5/source/drivers/gpu/drm/amd/amdkfd/kfd_topology.c#L2027


Thanks,
Lijo



Thanks,
Lijo



Thanks,
Lijo
 

*From:* amd-gfx  on behalf of 
James Zhu 

*Sent:* Saturday, August 12, 2023 2:36:27 AM
*To:* amd-gfx@lists.freedesktop.org 
*Cc:* Lin, Amber ; Zhu, James 
; Kasiviswanathan, Harish 
; Koenig, Christian 

*Subject:* [PATCH v3] drm/amdgpu: skip xcp drm device allocation 
when out of drm resource

Return 0 when drm device alloc failed with -ENOSPC in
order to  allow amdgpu drive loading. But the xcp without
drm device node assigned won't be visiable in user space.
This helps amdgpu driver loading on system which has more
than 64 nodes, the current limitation.

The proposal to add more drm nodes is discussed in public,
which will support up to 2^20 nodes totally.
kernel drm:
https://lore.kernel.org/lkml/20230724211428.3831636-1-michal.winiar...@intel.com/T/ 


libdrm:
https://gitlab.freedesktop.org/mesa/drm/-/merge_requests/305

Signed-off-by: James Zhu 
Acked-by: Christian König 

-v2: added warning message
-v3: use dev_warn
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c   | 13 -
 drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 10 +-
 2 files changed, 21 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c

index 9c9cca129498..565a1fa436d4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c
@@ -239,8 +239,13 @@ static int amdgpu_xcp_dev_alloc(struct 
amdgpu_device *adev)


 for (i = 1; i < MAX_XCP; i++) {
 ret = amdgpu_xcp_drm_dev_alloc(_ddev);
-   if (ret)
+   if (ret == -ENOSPC) {
+   dev_warn(adev->dev,
+   "Skip xcp node #%d when out of drm node 
resource.", i);

+   return 0;
+   } else if (ret) {
 return ret;
+   }

 /* Redirect all IOCTLs to the primary device */
 adev->xcp_mgr->xcp[i].rdev = p_ddev->render->dev;
@@ -328,6 +333,9 @@ int amdgpu_xcp_dev_register(struct amdgpu_device 
*adev,

 return 0;

 for (i = 1; i < MAX_XCP; i++) {
+   if (!adev->xcp_mgr->xcp[i].ddev)
+   break;
+
 ret = drm_dev_register(adev->xcp_mgr->xcp[i].ddev, 
ent->driver_data);

 if (ret)
 

Re: [PATCH v3] drm/amdgpu: skip xcp drm device allocation when out of drm resource

[James Zhu]

On 2023-08-12 13:00, Lazar, Lijo wrote:



On 8/12/2023 6:14 PM, James Zhu wrote:


On 2023-08-11 21:39, Lazar, Lijo wrote:


[AMD Official Use Only - General]


A dynamic partition switch could happen later.  The switch could 
still be successful in terms of hardware,
[JZ] Only ignore render node assignment, and remove visibility in 
user space, xcp continues to be generated as usual. so switch should 
work as usual


Switch is not useful for the user unless the apps can make use of the 
render nodes. A 'success' from hardware perspective doesn't turn out 
to be a 'success' for users eventually to make use of the extra 
partition.
[JZ] Yes, After switch, app can use the render nodes (no more than 64 
nodes in one system), Like 8P MI300X CPX mode,  with no external VGA 
device,all 64 nodes can be used. with one  external VGA device, 63 nodes 
can be used.


and hence gives a false feeling of success even if there are no 
render nodes available for any app to make use of the partition.
[JZ] from driver prospective, the switch is real success, treat the 
last one harvested in user space.. there is warning in kernel log, 
and final solution for more than 64 nodes is on-going


The render nodes are allocated during driver load and the message will 
go unnoticed. We could still allow the switch, but the message should 
be there during a partition switch like 'only x/y (x out of y nodes) 
are usable'. The worst case is - only 1 out of N meaning no benefit - 
and in that case user may switch back to normal mode to make use of 
full compute power.




Also, a kfd node is not expected to have a valid xcp pointer on 
devices without partition.

[JZ] won't affect xcp pointer, only ddev.

This access could break then gpu->xcp->ddev.

[JZ] added skip when ddev==NULL


What I meant is xcp in kfd node could be NULL on SOCs like NV series. 
There should be a check for xcp before accessing ddev -
https://elixir.bootlin.com/linux/v6.5-rc5/source/drivers/gpu/drm/amd/amdkfd/kfd_device.c#L794 

[JZ] So it is potential bug before this patch. then we need review 
current code to add all necessary xcp check.


Thanks,
Lijo



Thanks,
Lijo
 

*From:* amd-gfx  on behalf of 
James Zhu 

*Sent:* Saturday, August 12, 2023 2:36:27 AM
*To:* amd-gfx@lists.freedesktop.org 
*Cc:* Lin, Amber ; Zhu, James 
; Kasiviswanathan, Harish 
; Koenig, Christian 

*Subject:* [PATCH v3] drm/amdgpu: skip xcp drm device allocation 
when out of drm resource

Return 0 when drm device alloc failed with -ENOSPC in
order to  allow amdgpu drive loading. But the xcp without
drm device node assigned won't be visiable in user space.
This helps amdgpu driver loading on system which has more
than 64 nodes, the current limitation.

The proposal to add more drm nodes is discussed in public,
which will support up to 2^20 nodes totally.
kernel drm:
https://lore.kernel.org/lkml/20230724211428.3831636-1-michal.winiar...@intel.com/T/ 


libdrm:
https://gitlab.freedesktop.org/mesa/drm/-/merge_requests/305

Signed-off-by: James Zhu 
Acked-by: Christian König 

-v2: added warning message
-v3: use dev_warn
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c   | 13 -
 drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 10 +-
 2 files changed, 21 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c

index 9c9cca129498..565a1fa436d4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c
@@ -239,8 +239,13 @@ static int amdgpu_xcp_dev_alloc(struct 
amdgpu_device *adev)


 for (i = 1; i < MAX_XCP; i++) {
 ret = amdgpu_xcp_drm_dev_alloc(_ddev);
-   if (ret)
+   if (ret == -ENOSPC) {
+   dev_warn(adev->dev,
+   "Skip xcp node #%d when out of drm node 
resource.", i);

+   return 0;
+   } else if (ret) {
 return ret;
+   }

 /* Redirect all IOCTLs to the primary device */
 adev->xcp_mgr->xcp[i].rdev = p_ddev->render->dev;
@@ -328,6 +333,9 @@ int amdgpu_xcp_dev_register(struct amdgpu_device 
*adev,

 return 0;

 for (i = 1; i < MAX_XCP; i++) {
+   if (!adev->xcp_mgr->xcp[i].ddev)
+   break;
+
 ret = drm_dev_register(adev->xcp_mgr->xcp[i].ddev, 
ent->driver_data);

 if (ret)
 return ret;
@@ -345,6 +353,9 @@ void amdgpu_xcp_dev_unplug(struct amdgpu_device 
*adev)

 return;

 for (i = 1; i < MAX_XCP; i++) {
+   if (!adev->xcp_mgr->xcp[i].ddev)
+   break;
+
 p_ddev = adev->xcp_mgr->xcp[i].ddev;
 drm_dev_unplug(p_ddev);
 p_ddev->render->dev = adev->xcp_mgr->xcp[i].rdev;
diff --git 

Re: [PATCH V7 4/9] wifi: mac80211: Add support for ACPI WBRF

[Johannes Berg]

On Tue, 2023-07-25 at 22:09 +0200, Andrew Lunn wrote:
> 
> 
> It could well be that AMD based machine has a different ACPI extension
> to indicate this policy to what Intel machine has. As far as i
> understand it, you have not submitted this yet for formal approval,
> this is all vendor specific, so Intel could do it completely
> differently.

Already do, without the host software being involved in the same way.
There, I believe the ACPI tables just indicate what's needed and the
WiFi firmware sorts out the rest.

johannes

Re: [PATCH 1/3] drm/amdgpu: Add new api to switch on/off power profile mode

[Yadav, Arvind]

On 8/14/2023 5:35 PM, Christian König wrote:

Am 14.08.23 um 09:34 schrieb Arvind Yadav:

This patch adds a function which will allow to
change the GPU power profile based on a submitted job.
This can optimize the power performance when the
workload is on.

Cc: Shashank Sharma 
Cc: Christian Koenig 
Cc: Alex Deucher 
Signed-off-by: Arvind Yadav 
---
  drivers/gpu/drm/amd/amdgpu/Makefile   |   2 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu.h   |   3 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c    |   2 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_workload.c  | 156 ++
  drivers/gpu/drm/amd/include/amdgpu_workload.h |  44 +
  5 files changed, 206 insertions(+), 1 deletion(-)
  create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_workload.c
  create mode 100644 drivers/gpu/drm/amd/include/amdgpu_workload.h

diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile 
b/drivers/gpu/drm/amd/amdgpu/Makefile

index 415a7fa395c4..6a9e187d61e1 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -60,7 +60,7 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
  amdgpu_umc.o smu_v11_0_i2c.o amdgpu_fru_eeprom.o amdgpu_rap.o \
  amdgpu_fw_attestation.o amdgpu_securedisplay.o \
  amdgpu_eeprom.o amdgpu_mca.o amdgpu_psp_ta.o amdgpu_lsdma.o \
-    amdgpu_ring_mux.o
+    amdgpu_ring_mux.o amdgpu_workload.o
    amdgpu-$(CONFIG_PROC_FS) += amdgpu_fdinfo.o
  diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h

index 02b827785e39..1939fa1af8a6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -107,6 +107,7 @@
  #include "amdgpu_fdinfo.h"
  #include "amdgpu_mca.h"
  #include "amdgpu_ras.h"
+#include "amdgpu_workload.h"
    #define MAX_GPU_INSTANCE    16
  @@ -1050,6 +1051,8 @@ struct amdgpu_device {
    bool    job_hang;
  bool    dc_enabled;
+
+    struct amdgpu_smu_workload    smu_workload;
  };
    static inline struct amdgpu_device *drm_to_adev(struct drm_device 
*ddev)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

index 5c7d40873ee2..0ec18b8fe29f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3672,6 +3672,8 @@ int amdgpu_device_init(struct amdgpu_device *adev,
    INIT_WORK(>xgmi_reset_work, 
amdgpu_device_xgmi_reset_func);

  +    amdgpu_smu_workload_init(adev);
+
  adev->gfx.gfx_off_req_count = 1;
  adev->gfx.gfx_off_residency = 0;
  adev->gfx.gfx_off_entrycount = 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_workload.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_workload.c

new file mode 100644
index ..ce0339d75c12
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_workload.c
@@ -0,0 +1,156 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright 2023 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person 
obtaining a
+ * copy of this software and associated documentation files (the 
"Software"),
+ * to deal in the Software without restriction, including without 
limitation
+ * the rights to use, copy, modify, merge, publish, distribute, 
sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom 
the

+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be 
included in

+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 
EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 
MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO 
EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, 
DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 
OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 
USE OR

+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include "amdgpu.h"
+
+/* 100 millsecond timeout */
+#define SMU_IDLE_TIMEOUT    msecs_to_jiffies(100)
+
+static enum PP_SMC_POWER_PROFILE
+ring_to_power_profile(uint32_t ring_type)
+{
+    switch (ring_type) {
+    case AMDGPU_RING_TYPE_GFX:
+    return PP_SMC_POWER_PROFILE_FULLSCREEN3D;
+    case AMDGPU_RING_TYPE_COMPUTE:
+    return PP_SMC_POWER_PROFILE_COMPUTE;
+    case AMDGPU_RING_TYPE_UVD:
+    case AMDGPU_RING_TYPE_VCE:
+    case AMDGPU_RING_TYPE_UVD_ENC:
+    case AMDGPU_RING_TYPE_VCN_DEC:
+    case AMDGPU_RING_TYPE_VCN_ENC:
+    case AMDGPU_RING_TYPE_VCN_JPEG:
+    return PP_SMC_POWER_PROFILE_VIDEO;
+    default:
+    return PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
+    }
+}
+
+static void
+amdgpu_power_profile_set(struct amdgpu_device *adev,
+ enum PP_SMC_POWER_PROFILE profile)
+{
+    int ret = amdgpu_dpm_switch_power_profile(adev, profile, true);
+
+    if (ret == 

Re: [PATCH 1/3] drm/amdgpu: Add new api to switch on/off power profile mode

[Christian König]

Am 14.08.23 um 09:34 schrieb Arvind Yadav:

This patch adds a function which will allow to
change the GPU power profile based on a submitted job.
This can optimize the power performance when the
workload is on.

Cc: Shashank Sharma 
Cc: Christian Koenig 
Cc: Alex Deucher 
Signed-off-by: Arvind Yadav 
---
  drivers/gpu/drm/amd/amdgpu/Makefile   |   2 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu.h   |   3 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c|   2 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_workload.c  | 156 ++
  drivers/gpu/drm/amd/include/amdgpu_workload.h |  44 +
  5 files changed, 206 insertions(+), 1 deletion(-)
  create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_workload.c
  create mode 100644 drivers/gpu/drm/amd/include/amdgpu_workload.h

diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile 
b/drivers/gpu/drm/amd/amdgpu/Makefile
index 415a7fa395c4..6a9e187d61e1 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -60,7 +60,7 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
amdgpu_umc.o smu_v11_0_i2c.o amdgpu_fru_eeprom.o amdgpu_rap.o \
amdgpu_fw_attestation.o amdgpu_securedisplay.o \
amdgpu_eeprom.o amdgpu_mca.o amdgpu_psp_ta.o amdgpu_lsdma.o \
-   amdgpu_ring_mux.o
+   amdgpu_ring_mux.o amdgpu_workload.o
  
  amdgpu-$(CONFIG_PROC_FS) += amdgpu_fdinfo.o
  
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h

index 02b827785e39..1939fa1af8a6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -107,6 +107,7 @@
  #include "amdgpu_fdinfo.h"
  #include "amdgpu_mca.h"
  #include "amdgpu_ras.h"
+#include "amdgpu_workload.h"
  
  #define MAX_GPU_INSTANCE		16
  
@@ -1050,6 +1051,8 @@ struct amdgpu_device {
  
  	booljob_hang;

booldc_enabled;
+
+   struct amdgpu_smu_workload  smu_workload;
  };
  
  static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 5c7d40873ee2..0ec18b8fe29f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3672,6 +3672,8 @@ int amdgpu_device_init(struct amdgpu_device *adev,
  
  	INIT_WORK(>xgmi_reset_work, amdgpu_device_xgmi_reset_func);
  
+	amdgpu_smu_workload_init(adev);

+
adev->gfx.gfx_off_req_count = 1;
adev->gfx.gfx_off_residency = 0;
adev->gfx.gfx_off_entrycount = 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_workload.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_workload.c
new file mode 100644
index ..ce0339d75c12
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_workload.c
@@ -0,0 +1,156 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright 2023 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include "amdgpu.h"
+
+/* 100 millsecond timeout */
+#define SMU_IDLE_TIMEOUT   msecs_to_jiffies(100)
+
+static enum PP_SMC_POWER_PROFILE
+ring_to_power_profile(uint32_t ring_type)
+{
+   switch (ring_type) {
+   case AMDGPU_RING_TYPE_GFX:
+   return PP_SMC_POWER_PROFILE_FULLSCREEN3D;
+   case AMDGPU_RING_TYPE_COMPUTE:
+   return PP_SMC_POWER_PROFILE_COMPUTE;
+   case AMDGPU_RING_TYPE_UVD:
+   case AMDGPU_RING_TYPE_VCE:
+   case AMDGPU_RING_TYPE_UVD_ENC:
+   case AMDGPU_RING_TYPE_VCN_DEC:
+   case AMDGPU_RING_TYPE_VCN_ENC:
+   case AMDGPU_RING_TYPE_VCN_JPEG:
+   return PP_SMC_POWER_PROFILE_VIDEO;
+   default:
+   return PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
+   }
+}
+
+static void
+amdgpu_power_profile_set(struct amdgpu_device *adev,
+enum PP_SMC_POWER_PROFILE profile)
+{
+   int ret = amdgpu_dpm_switch_power_profile(adev, 

Re: [PATCH 0/5] Add work pool to reset domain

[Christian König]

Am 12.08.23 um 19:08 schrieb Lazar, Lijo:

On 8/12/2023 1:53 PM, Christian König wrote:

Am 11.08.23 um 08:02 schrieb Lijo Lazar:
Presently, there are multiple clients of reset like RAS, job 
timeout, KFD hang
detection and debug method. Instead of each client maintaining a 
work item,
reset work pool is moved to reset domain. When a client makes a 
recovery request,
a work item is allocated by the reset domain and queued for 
execution. For the
case of job timeout, each ring has its own TDR queue to which tdr 
work is
scheduled. From there, it's further queued to a reset domain based 
on the device

configuration.

This allows flexibility to have multiple reset domains. For example, 
when
there are partitions, each partition can maintain its own reset 
domain and a job
timeout on one partition doesn't affect jobs on the other partition 
(when the

jobs don't have any interdependency). The reset logic will select the
appropriate reset domain based on the current device configuration.


Well completely NAK to that design.

We intentionally added the workqueue to serialize *all* reset work 
and I absolutely don't see any reason to change that.




This is for the case where there are multiple spatial partitions and a 
reset is possible by hardware design on one partition without 
affecting other partitions on the same device. The partition scenario 
can be considered equivalent to a multi-gpu case (not interconnected 
through XGMI) where each gpu gets its own reset domain and can be 
reset independently.


Well, this is not even remotely correct. Multiple spatial partitions are 
not fully separated, for example they share a common IRQ block.


So you need to be very careful if you want to reset multiple things at 
the same time. Because of this we already rejected the idea you are 
trying to implement here from the SW side.




BTW, this design doesn't restrict from keeping only one reset domain 
as in the case of legacy ASICs like Aldebaran. The reset work is 
always serialized within a domain. This allows to have multiple reset 
domains or you could also fall back to reset_domain1 -> reset_domain2 
for hierarchical resets, if required (though that is not planned now).


Yeah, beside the points noted above this infrastructure here is 
absolutely not necessary. The reset domain is already what you try to add.


In general if you get requirements like this please come to me first. 
I'm the owner of the amdgpu component, so all design regarding the 
kernel module must go over my desk.


Regards,
Christian.



Thanks,
Lijo


Regards,
Christian.



Lijo Lazar (5):
   drm/amdgpu: Add work pool to reset domain
   drm/amdgpu: Move to reset_schedule_work
   drm/amdgpu: Set flags to cancel all pending resets
   drm/amdgpu: Add API to queue and do reset work
   drm/amdgpu: Add TDR queue for ring

  drivers/gpu/drm/amd/amdgpu/amdgpu.h    |   2 -
  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c |  32 +++---
  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h |   1 -
  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  24 +---
  drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c  |  40 +++
  drivers/gpu/drm/amd/amdgpu/amdgpu_job.c    |  16 ++-
  drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c    |  71 ++--
  drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c  | 122 
-

  drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h  |  32 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c   |   5 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h   |   1 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h   |   1 -
  drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c  |  38 +++
  drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c  |  44 
  drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c  |  33 +++---
  15 files changed, 285 insertions(+), 177 deletions(-)

Re: [PATCH] drm/amd/display: Replace ternary operator with min() in 'dm_helpers_parse_edid_caps'

[Hamza Mahfooz]

On 8/13/23 04:46, Srinivasan Shanmugam wrote:

Fixes the following coccicheck:

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c:120:41-42: WARNING 
opportunity for min()

Cc: Harry Wentland 
Cc: Rodrigo Siqueira 
Cc: Aurabindo Pillai 
Cc: Alex Deucher 
Signed-off-by: Srinivasan Shanmugam 


Reviewed-by: Hamza Mahfooz 


---
  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index e94eeeb97688..4b230933b28e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -117,7 +117,7 @@ enum dc_edid_status dm_helpers_parse_edid_caps(
if (sad_count <= 0)
return result;
  
-	edid_caps->audio_mode_count = sad_count < DC_MAX_AUDIO_DESC_COUNT ? sad_count : DC_MAX_AUDIO_DESC_COUNT;

+   edid_caps->audio_mode_count = min(sad_count, DC_MAX_AUDIO_DESC_COUNT);
for (i = 0; i < edid_caps->audio_mode_count; ++i) {
struct cea_sad *sad = [i];
  

--
Hamza

Re: [PATCH] drm/amd/display: Fix unnecessary conversion to bool in 'amdgpu_dm_setup_replay'

[Christian König]

Am 13.08.23 um 10:36 schrieb Srinivasan Shanmugam:

Fixes the following coccicheck:

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c:94:102-107: WARNING: 
conversion to bool not needed here
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c:102:72-77: WARNING: 
conversion to bool not needed here

Cc: Bhawanpreet Lakha 
Cc: Harry Wentland 
Cc: Rodrigo Siqueira 
Cc: Aurabindo Pillai 
Cc: Alex Deucher 
Signed-off-by: Srinivasan Shanmugam 


Reviewed-by: Christian König 


---
  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c
index 32d3086c4cb7..5ce542b1f860 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c
@@ -91,7 +91,7 @@ bool amdgpu_dm_setup_replay(struct dc_link *link, struct 
amdgpu_dm_connector *ac
pr_config.replay_supported = true;
pr_config.replay_power_opt_supported = 0;
pr_config.replay_enable_option |= pr_enable_option_static_screen;
-   pr_config.replay_timing_sync_supported = aconnector->max_vfreq >= 2 * 
aconnector->min_vfreq ? true : false;
+   pr_config.replay_timing_sync_supported = aconnector->max_vfreq >= 2 * 
aconnector->min_vfreq;
  
  	if (!pr_config.replay_timing_sync_supported)

pr_config.replay_enable_option &= ~pr_enable_option_general_ui;
@@ -99,7 +99,7 @@ bool amdgpu_dm_setup_replay(struct dc_link *link, struct 
amdgpu_dm_connector *ac
debug_flags = (union replay_debug_flags *)_config.debug_flags;
debug_flags->u32All = 0;
debug_flags->bitfields.visual_confirm =
-   link->ctx->dc->debug.visual_confirm == VISUAL_CONFIRM_REPLAY ? 
true : false;
+   link->ctx->dc->debug.visual_confirm == VISUAL_CONFIRM_REPLAY;
  
  	link->replay_settings.replay_feature_enabled = true;
  

Re: [PATCH v3 2/2] drm/amd/pm: Update pci link speed for smu v13.0.6

[Lazar, Lijo]

On 8/14/2023 3:47 PM, Asad Kamal wrote:

Update pcie link speed registers for smu v13.0.6 &
populate gpu metric table with pcie link speed rather than
gen for smu v13_0_0, smu v13_0_6 & smu v13_0_7

v2:
Update ESM register address
Used macro to convert pcie gen to speed

v3:
Chaged macro to inline function for pcie gen to speed

Signed-off-by: Asad Kamal 
---
  drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h |  1 -
  drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c   |  1 -
  .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c |  7 ++-
  .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 16 ++--
  .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c |  7 ++-
  drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c   |  2 ++
  drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h   |  8 
  7 files changed, 36 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h 
b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h
index 1b4e0e4716ea..a0e5ad0381d6 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h
@@ -64,7 +64,6 @@
  #define LINK_SPEED_MAX3
  
  static const __maybe_unused uint16_t link_width[] = {0, 1, 2, 4, 8, 12, 16};

-static const __maybe_unused uint16_t link_speed[] = {25, 50, 80, 160};
  
  static const

  struct smu_temperature_range __maybe_unused smu11_thermal_policy[] = {
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index 895cda8e6934..6863186937f7 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -83,7 +83,6 @@ MODULE_FIRMWARE("amdgpu/smu_13_0_10.bin");
  #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xE
  
  static const int link_width[] = {0, 1, 2, 4, 8, 12, 16};

-static const int link_speed[] = {25, 50, 80, 160};
  
  const int pmfw_decoded_link_speed[5] = {1, 2, 3, 4, 5};

  const int pmfw_decoded_link_width[7] = {0, 1, 2, 4, 8, 12, 16};
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index 48b03524a52d..f4e2ac4a8713 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -102,6 +102,8 @@
  #define PP_OD_FEATURE_UCLK_FMAX   3
  #define PP_OD_FEATURE_GFX_VF_CURVE4
  
+#define LINK_SPEED_MAX	3

+
  static struct cmn2asic_msg_mapping smu_v13_0_0_message_map[SMU_MSG_MAX_COUNT] 
= {
MSG_MAP(TestMessage,PPSMC_MSG_TestMessage,  
   1),
MSG_MAP(GetSmuVersion,  PPSMC_MSG_GetSmuVersion,
   1),
@@ -1759,7 +1761,10 @@ static ssize_t smu_v13_0_0_get_gpu_metrics(struct 
smu_context *smu,
gpu_metrics->current_fan_speed = metrics->AvgFanRpm;
  
  	gpu_metrics->pcie_link_width = metrics->PcieWidth;

-   gpu_metrics->pcie_link_speed = metrics->PcieRate;
+   if ((metrics->PcieRate - 1) > LINK_SPEED_MAX)
+   gpu_metrics->pcie_link_speed = pcie_gen_to_speed(1);
+   else
+   gpu_metrics->pcie_link_speed = 
pcie_gen_to_speed(metrics->PcieRate);
  
  	gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
  
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

index 21275e496852..d1a9be37bece 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
@@ -80,12 +80,17 @@
  /* possible frequency drift (1Mhz) */
  #define EPSILON 1
  
-#define smnPCIE_ESM_CTRL 0x193D0

+#define smnPCIE_ESM_CTRL 0x93D0
  #define smnPCIE_LC_LINK_WIDTH_CNTL 0x1a340288
  #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x0070L
  #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
  #define MAX_LINK_WIDTH 6
  
+#define smnPCIE_LC_SPEED_CNTL   0x1a340290

+#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xE0
+#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0x5
+#define LINK_SPEED_MAX 4
+
  static const struct cmn2asic_msg_mapping 
smu_v13_0_6_message_map[SMU_MSG_MAX_COUNT] = {
MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 
0),
MSG_MAP(GetSmuVersion,   PPSMC_MSG_GetSmuVersion,   
1),
@@ -1936,6 +1941,7 @@ smu_v13_0_6_get_current_pcie_link_width_level(struct 
smu_context *smu)
  static int smu_v13_0_6_get_current_pcie_link_speed(struct smu_context *smu)
  {
struct amdgpu_device *adev = smu->adev;
+   uint32_t speed_level;
uint32_t esm_ctrl;
  
  	/* TODO: confirm this on real target */

@@ -1943,7 +1949,13 @@ static int 
smu_v13_0_6_get_current_pcie_link_speed(struct smu_context *smu)
if ((esm_ctrl >> 15) & 0x1)
return 

[PATCH v3 2/2] drm/amd/pm: Update pci link speed for smu v13.0.6

[Asad Kamal]

Update pcie link speed registers for smu v13.0.6 &
populate gpu metric table with pcie link speed rather than
gen for smu v13_0_0, smu v13_0_6 & smu v13_0_7

v2:
Update ESM register address
Used macro to convert pcie gen to speed

v3:
Chaged macro to inline function for pcie gen to speed

Signed-off-by: Asad Kamal 
---
 drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h |  1 -
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c   |  1 -
 .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c |  7 ++-
 .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 16 ++--
 .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c |  7 ++-
 drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c   |  2 ++
 drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h   |  8 
 7 files changed, 36 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h 
b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h
index 1b4e0e4716ea..a0e5ad0381d6 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h
@@ -64,7 +64,6 @@
 #define LINK_SPEED_MAX 3
 
 static const __maybe_unused uint16_t link_width[] = {0, 1, 2, 4, 8, 12, 16};
-static const __maybe_unused uint16_t link_speed[] = {25, 50, 80, 160};
 
 static const
 struct smu_temperature_range __maybe_unused smu11_thermal_policy[] = {
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index 895cda8e6934..6863186937f7 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -83,7 +83,6 @@ MODULE_FIRMWARE("amdgpu/smu_13_0_10.bin");
 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xE
 
 static const int link_width[] = {0, 1, 2, 4, 8, 12, 16};
-static const int link_speed[] = {25, 50, 80, 160};
 
 const int pmfw_decoded_link_speed[5] = {1, 2, 3, 4, 5};
 const int pmfw_decoded_link_width[7] = {0, 1, 2, 4, 8, 12, 16};
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index 48b03524a52d..f4e2ac4a8713 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -102,6 +102,8 @@
 #define PP_OD_FEATURE_UCLK_FMAX3
 #define PP_OD_FEATURE_GFX_VF_CURVE 4
 
+#define LINK_SPEED_MAX 3
+
 static struct cmn2asic_msg_mapping smu_v13_0_0_message_map[SMU_MSG_MAX_COUNT] 
= {
MSG_MAP(TestMessage,PPSMC_MSG_TestMessage,  
   1),
MSG_MAP(GetSmuVersion,  PPSMC_MSG_GetSmuVersion,
   1),
@@ -1759,7 +1761,10 @@ static ssize_t smu_v13_0_0_get_gpu_metrics(struct 
smu_context *smu,
gpu_metrics->current_fan_speed = metrics->AvgFanRpm;
 
gpu_metrics->pcie_link_width = metrics->PcieWidth;
-   gpu_metrics->pcie_link_speed = metrics->PcieRate;
+   if ((metrics->PcieRate - 1) > LINK_SPEED_MAX)
+   gpu_metrics->pcie_link_speed = pcie_gen_to_speed(1);
+   else
+   gpu_metrics->pcie_link_speed = 
pcie_gen_to_speed(metrics->PcieRate);
 
gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
 
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
index 21275e496852..d1a9be37bece 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
@@ -80,12 +80,17 @@
 /* possible frequency drift (1Mhz) */
 #define EPSILON 1
 
-#define smnPCIE_ESM_CTRL 0x193D0
+#define smnPCIE_ESM_CTRL 0x93D0
 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x1a340288
 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x0070L
 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
 #define MAX_LINK_WIDTH 6
 
+#define smnPCIE_LC_SPEED_CNTL   0x1a340290
+#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xE0
+#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0x5
+#define LINK_SPEED_MAX 4
+
 static const struct cmn2asic_msg_mapping 
smu_v13_0_6_message_map[SMU_MSG_MAX_COUNT] = {
MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 
0),
MSG_MAP(GetSmuVersion,   PPSMC_MSG_GetSmuVersion,   
1),
@@ -1936,6 +1941,7 @@ smu_v13_0_6_get_current_pcie_link_width_level(struct 
smu_context *smu)
 static int smu_v13_0_6_get_current_pcie_link_speed(struct smu_context *smu)
 {
struct amdgpu_device *adev = smu->adev;
+   uint32_t speed_level;
uint32_t esm_ctrl;
 
/* TODO: confirm this on real target */
@@ -1943,7 +1949,13 @@ static int 
smu_v13_0_6_get_current_pcie_link_speed(struct smu_context *smu)
if ((esm_ctrl >> 15) & 0x1)
return (((esm_ctrl >> 8) & 0x3F) + 128);
 
-   return 

[PATCH v3 1/2] drm/amd/pm: Update pci link width for smu v13.0.6

[Asad Kamal]

Update addresses of PCIE link width registers,
& link width format used to populate gpu metrics
table for smu v13.0.6

v2:
Removed ESM register update

v3:
Updated patch subject and message

Signed-off-by: Asad Kamal 
---
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 10 --
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
index 362acbb242bb..21275e496852 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
@@ -81,9 +81,10 @@
 #define EPSILON 1
 
 #define smnPCIE_ESM_CTRL 0x193D0
-#define smnPCIE_LC_LINK_WIDTH_CNTL 0x1ab40288
+#define smnPCIE_LC_LINK_WIDTH_CNTL 0x1a340288
 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x0070L
 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
+#define MAX_LINK_WIDTH 6
 
 static const struct cmn2asic_msg_mapping 
smu_v13_0_6_message_map[SMU_MSG_MAX_COUNT] = {
MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 
0),
@@ -1953,6 +1954,7 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct 
smu_context *smu, void **table
struct amdgpu_device *adev = smu->adev;
int ret = 0, inst0, xcc0;
MetricsTable_t *metrics;
+   u16 link_width_level;
 
inst0 = adev->sdma.instance[0].aid_id;
xcc0 = GET_INST(GC, 0);
@@ -2003,8 +2005,12 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct 
smu_context *smu, void **table
gpu_metrics->throttle_status = 0;
 
if (!(adev->flags & AMD_IS_APU)) {
+   link_width_level = 
smu_v13_0_6_get_current_pcie_link_width_level(smu);
+   if (link_width_level > MAX_LINK_WIDTH)
+   link_width_level = 0;
+
gpu_metrics->pcie_link_width =
-   smu_v13_0_6_get_current_pcie_link_width_level(smu);
+   DECODE_LANE_WIDTH(link_width_level);
gpu_metrics->pcie_link_speed =
smu_v13_0_6_get_current_pcie_link_speed(smu);
}
-- 
2.34.1

Re: [PATCH v6] drm/doc: Document DRM device reset expectations

[Michel Dänzer]

On 8/11/23 20:55, André Almeida wrote:
> Create a section that specifies how to deal with DRM device resets for
> kernel and userspace drivers.
> 
> Signed-off-by: André Almeida 

[...]

> +Robustness
> +--
> +
> +The only way to try to keep an application working after a reset is if it
> +complies with the robustness aspects of the graphical API that it is using.

"The only way to try to keep a graphical API context working after a device 
reset [...]"

If a graphical API context stops working properly, it doesn't necessarily mean 
that the application as a whole stops working.


-- 
Earthling Michel Dänzer|  https://redhat.com
Libre software enthusiast  | Mesa and Xwayland developer

RE: [PATCH V7 4/9] wifi: mac80211: Add support for ACPI WBRF

[Quan, Evan]

[AMD Official Use Only - General]

Hi Andrew,

I sent out a new V8 series last week.
A kernel parameter `wbrf` was introduced there to decide the policy.
Please help to check whether that makes sense to you.
Please share your insights there.

BR,
Evan
> -Original Message-
> From: Andrew Lunn 
> Sent: Wednesday, July 26, 2023 4:10 AM
> To: Limonciello, Mario 
> Cc: Quan, Evan ; raf...@kernel.org; l...@kernel.org;
> Deucher, Alexander ; Koenig, Christian
> ; Pan, Xinhui ;
> airl...@gmail.com; dan...@ffwll.ch; johan...@sipsolutions.net;
> da...@davemloft.net; eduma...@google.com; k...@kernel.org;
> pab...@redhat.com; mdaen...@redhat.com;
> maarten.lankho...@linux.intel.com; tzimmerm...@suse.de;
> hdego...@redhat.com; jingyuwang_...@163.com; Lazar, Lijo
> ; jim.cro...@gmail.com; bellosili...@gmail.com;
> andrealm...@igalia.com; t...@redhat.com; j...@jsg.id.au; a...@arndb.de;
> linux-ker...@vger.kernel.org; linux-a...@vger.kernel.org; amd-
> g...@lists.freedesktop.org; dri-de...@lists.freedesktop.org; linux-
> wirel...@vger.kernel.org; net...@vger.kernel.org
> Subject: Re: [PATCH V7 4/9] wifi: mac80211: Add support for ACPI WBRF
> 
> > This comes back to the point that was mentioned by Johannes - you need
> > to have deep design understanding of the hardware to know whether or
> > not you will have producers that a consumer need to react to.
> 
> Yes, this is the policy is keep referring to. I would expect that there is 
> something
> somewhere in ACPI which says for this machine, the policy is Yes/No.
> 
> It could well be that AMD based machine has a different ACPI extension to
> indicate this policy to what Intel machine has. As far as i understand it, you
> have not submitted this yet for formal approval, this is all vendor specific, 
> so
> Intel could do it completely differently. Hence i would expect a generic API 
> to
> tell the core what the policy is, and your glue code can call into ACPI to 
> find out
> that information, and then tell the core.
> 
> > If all producers indicate their frequency and all consumers react to
> > it you may have activated mitigations that are unnecessary. The
> > hardware designer may have added extra shielding or done the layout
> > such that they're not needed.
> 
> And the policy will indicate No, nothing needs to be done. The core can then
> tell produces and consumes not to bother telling the core anything.
> 
> > So I don't think we're ever going to be in a situation that the
> > generic implementation should be turned on by default.  It's a "developer
> knob".
> 
> Wrong. You should have a generic core, which your AMD CPU DDR device
> plugs into. The Intel CPU DDR device can plug into, the nvidea GPU can plug
> into, your Radeon GPU can plug into, the intel ARC can plug into, the generic
> WiFi core plugs into, etc.
> 
> > If needed these can then be enabled using the AMD ACPI interface, a DT
> > one if one is developed or maybe even an allow-list of SMBIOS strings.
> 
> Notice i've not mentioned DT for a while. I just want a generic core, which
> AMD, Intel, nvidea, Ampare, Graviton, Qualcomm, Marvell, ..., etc can use. We
> should be solving this problem once, for everybody, not adding a solution for
> just one vendor.
> 
>   Andrew

Re: [PATCH] drm/amdgpu: Replace ternary operator with min() in 'amdgpu_iomem_read'

[SHANMUGAM, SRINIVASAN]

On 8/14/2023 2:45 PM, Christian König wrote:

Am 12.08.23 um 16:47 schrieb Srinivasan Shanmugam:

Fixes the following coccicheck:

drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c:2427:16-17: WARNING 
opportunity for min()


min() macro is defined in include/linux/minmax.h. It avoids multiple
evaluations of the arguments when non-constant and performs strict
type-checking.

Cc: Guchun Chen 
Cc: Christian König 
Cc: Alex Deucher 
Cc: "Pan, Xinhui" 
Signed-off-by: Srinivasan Shanmugam 


Please double check that we don't need min_t() here.


Thanks a lot Christian for your reviews! Highly appreciate for your help!

min_t() is needed if there is any explict typecasting for any of the 
variables passed to min() please.


For ex: some references pls:

1.

commit 3434392da74953727f6c27bcf24aa7d8ae789c80
Author: Srinivasan Shanmugam 
Date:   Sun Jul 23 12:29:14 2023 +0530

    drm/amdgpu: Update min() to min_t() in 'amdgpu_info_ioctl'

2.

https://patchwork.kernel.org/project/linux-omap/patch/1307877290-26672-1-git-send-email-tlin...@codeaurora.org/#1917462

Best regards,

Srini



With that done this patch and the _write variant are Reviewed-by: 
Christian König .


Regards,
Christian.


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

index df32785a8b36..c03fe7ee555b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -2424,7 +2424,7 @@ static ssize_t amdgpu_iomem_read(struct file 
*f, char __user *buf,

  struct page *p;
  void *ptr;
  -    bytes = bytes < size ? bytes : size;
+    bytes = min(bytes, size);
    /* Translate the bus address to a physical address. If
   * the domain is NULL it means there is no IOMMU active

Re: [PATCH] drm/amdgpu: Replace ternary operator with min() in 'amdgpu_iomem_read'

[Christian König]

Am 12.08.23 um 16:47 schrieb Srinivasan Shanmugam:

Fixes the following coccicheck:

drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c:2427:16-17: WARNING opportunity for 
min()

min() macro is defined in include/linux/minmax.h. It avoids multiple
evaluations of the arguments when non-constant and performs strict
type-checking.

Cc: Guchun Chen 
Cc: Christian König 
Cc: Alex Deucher 
Cc: "Pan, Xinhui" 
Signed-off-by: Srinivasan Shanmugam 


Please double check that we don't need min_t() here.

With that done this patch and the _write variant are Reviewed-by: 
Christian König .


Regards,
Christian.


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index df32785a8b36..c03fe7ee555b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -2424,7 +2424,7 @@ static ssize_t amdgpu_iomem_read(struct file *f, char 
__user *buf,
struct page *p;
void *ptr;
  
-		bytes = bytes < size ? bytes : size;

+   bytes = min(bytes, size);
  
  		/* Translate the bus address to a physical address.  If

 * the domain is NULL it means there is no IOMMU active

RE: [PATCH V8 3/9] cfg80211: expose nl80211_chan_width_to_mhz for wide sharing

[Quan, Evan]

[AMD Official Use Only - General]



> -Original Message-
> From: Jeff Johnson 
> Sent: Thursday, August 10, 2023 10:06 PM
> To: Quan, Evan ; raf...@kernel.org; l...@kernel.org;
> Deucher, Alexander ; Koenig, Christian
> ; Pan, Xinhui ;
> airl...@gmail.com; dan...@ffwll.ch; johan...@sipsolutions.net;
> da...@davemloft.net; eduma...@google.com; k...@kernel.org;
> pab...@redhat.com; Limonciello, Mario ;
> mdaen...@redhat.com; maarten.lankho...@linux.intel.com;
> tzimmerm...@suse.de; hdego...@redhat.com; jingyuwang_...@163.com;
> Lazar, Lijo ; jim.cro...@gmail.com;
> bellosili...@gmail.com; andrealm...@igalia.com; t...@redhat.com;
> j...@jsg.id.au; a...@arndb.de; and...@lunn.ch
> Cc: linux-ker...@vger.kernel.org; linux-a...@vger.kernel.org; amd-
> g...@lists.freedesktop.org; dri-de...@lists.freedesktop.org; linux-
> wirel...@vger.kernel.org; net...@vger.kernel.org
> Subject: Re: [PATCH V8 3/9] cfg80211: expose nl80211_chan_width_to_mhz
> for wide sharing
> 
> On 8/10/2023 12:37 AM, Evan Quan wrote:
> > The newly added WBRF feature needs this interface for channel width
> > calculation.
> >
> > Signed-off-by: Evan Quan 
> > ---
> >   include/net/cfg80211.h | 8 
> >   net/wireless/chan.c| 3 ++-
> >   2 files changed, 10 insertions(+), 1 deletion(-)
> >
> > diff --git a/include/net/cfg80211.h b/include/net/cfg80211.h index
> > 7c7d03aa9d06..f50508e295db 100644
> > --- a/include/net/cfg80211.h
> > +++ b/include/net/cfg80211.h
> > @@ -920,6 +920,14 @@ const struct cfg80211_chan_def *
> >   cfg80211_chandef_compatible(const struct cfg80211_chan_def
> *chandef1,
> > const struct cfg80211_chan_def *chandef2);
> >
> > +/**
> > + * nl80211_chan_width_to_mhz - get the channel width in Mhz
> > + * @chan_width: the channel width from  nl80211_chan_width
> > + * Return: channel width in Mhz if the chan_width from 
> > +nl80211_chan_width
> > + * is valid. -1 otherwise.
> 
> SI nit: s/Mhz/MHz/ in both places
Thanks, will update them accordingly.

Evan
> 
> > + */
> > +int nl80211_chan_width_to_mhz(enum nl80211_chan_width
> chan_width);
> > +
> >   /**
> >* cfg80211_chandef_valid - check if a channel definition is valid
> >* @chandef: the channel definition to check diff --git
> > a/net/wireless/chan.c b/net/wireless/chan.c index
> > 0b7e81db383d..227db04eac42 100644
> > --- a/net/wireless/chan.c
> > +++ b/net/wireless/chan.c
> > @@ -141,7 +141,7 @@ static bool cfg80211_edmg_chandef_valid(const
> struct cfg80211_chan_def *chandef)
> > return true;
> >   }
> >
> > -static int nl80211_chan_width_to_mhz(enum nl80211_chan_width
> > chan_width)
> > +int nl80211_chan_width_to_mhz(enum nl80211_chan_width chan_width)
> >   {
> > int mhz;
> >
> > @@ -190,6 +190,7 @@ static int nl80211_chan_width_to_mhz(enum
> nl80211_chan_width chan_width)
> > }
> > return mhz;
> >   }
> > +EXPORT_SYMBOL(nl80211_chan_width_to_mhz);
> >
> >   static int cfg80211_chandef_get_width(const struct cfg80211_chan_def
> *c)
> >   {

RE: [PATCH V8 1/9] drivers core: Add support for Wifi band RF mitigations

[Quan, Evan]

[AMD Official Use Only - General]



> -Original Message-
> From: Randy Dunlap 
> Sent: Thursday, August 10, 2023 11:41 PM
> To: Quan, Evan ; raf...@kernel.org; l...@kernel.org;
> Deucher, Alexander ; Koenig, Christian
> ; Pan, Xinhui ;
> airl...@gmail.com; dan...@ffwll.ch; johan...@sipsolutions.net;
> da...@davemloft.net; eduma...@google.com; k...@kernel.org;
> pab...@redhat.com; Limonciello, Mario ;
> mdaen...@redhat.com; maarten.lankho...@linux.intel.com;
> tzimmerm...@suse.de; hdego...@redhat.com; jingyuwang_...@163.com;
> Lazar, Lijo ; jim.cro...@gmail.com;
> bellosili...@gmail.com; andrealm...@igalia.com; t...@redhat.com;
> j...@jsg.id.au; a...@arndb.de; and...@lunn.ch
> Cc: linux-ker...@vger.kernel.org; linux-a...@vger.kernel.org; amd-
> g...@lists.freedesktop.org; dri-de...@lists.freedesktop.org; linux-
> wirel...@vger.kernel.org; net...@vger.kernel.org
> Subject: Re: [PATCH V8 1/9] drivers core: Add support for Wifi band RF
> mitigations
> 
> 
> 
> On 8/10/23 00:37, Evan Quan wrote:
> > diff --git a/Documentation/admin-guide/kernel-parameters.txt
> > b/Documentation/admin-guide/kernel-parameters.txt
> > index a1457995fd41..21f73a0bbd0b 100644
> > --- a/Documentation/admin-guide/kernel-parameters.txt
> > +++ b/Documentation/admin-guide/kernel-parameters.txt
> > @@ -7152,3 +7152,12 @@
> > xmon commands.
> > off xmon is disabled.
> >
> > +   wbrf=   [KNL]
> > +   Format: { on | auto | off }
> > +   Controls if WBRF features should be enabled or
> disabled
> > +   forcely. Default is auto.
> 
> "forcely" is not a word. "forcedly" is a word, but it's not used very much 
> AFAIK.
> I would probably write "Controls if WBRF features should be forced on or off."
Yeah, that sounds better. Will update this as suggested.

Evan
> 
> > +   on  Force enable the WBRF features.
> > +   autoUp to the system to do proper checks to
> > +   determine the WBRF features should be
> enabled
> > +   or not.
> > +   off Force disable the WBRF features.
> 
> --
> ~Randy

RE: [PATCH V8 6/9] drm/amd/pm: setup the framework to support Wifi RFI mitigation feature

[Quan, Evan]

[AMD Official Use Only - General]



> -Original Message-
> From: Simon Horman 
> Sent: Friday, August 11, 2023 5:35 PM
> To: Quan, Evan 
> Cc: raf...@kernel.org; l...@kernel.org; Deucher, Alexander
> ; Koenig, Christian
> ; Pan, Xinhui ;
> airl...@gmail.com; dan...@ffwll.ch; johan...@sipsolutions.net;
> da...@davemloft.net; eduma...@google.com; k...@kernel.org;
> pab...@redhat.com; Limonciello, Mario ;
> mdaen...@redhat.com; maarten.lankho...@linux.intel.com;
> tzimmerm...@suse.de; hdego...@redhat.com; jingyuwang_...@163.com;
> Lazar, Lijo ; jim.cro...@gmail.com;
> bellosili...@gmail.com; andrealm...@igalia.com; t...@redhat.com;
> j...@jsg.id.au; a...@arndb.de; and...@lunn.ch; linux-
> ker...@vger.kernel.org; linux-a...@vger.kernel.org; amd-
> g...@lists.freedesktop.org; dri-de...@lists.freedesktop.org; linux-
> wirel...@vger.kernel.org; net...@vger.kernel.org
> Subject: Re: [PATCH V8 6/9] drm/amd/pm: setup the framework to support
> Wifi RFI mitigation feature
> 
> On Thu, Aug 10, 2023 at 03:38:00PM +0800, Evan Quan wrote:
> > With WBRF feature supported, as a driver responding to the frequencies,
> > amdgpu driver is able to do shadow pstate switching to mitigate possible
> > interference(between its (G-)DDR memory clocks and local radio module
> > frequency bands used by Wifi 6/6e/7).
> >
> > Signed-off-by: Evan Quan 
> > Reviewed-by: Mario Limonciello 
> 
> ...
> 
> > +/**
> > + * smu_wbrf_event_handler - handle notify events
> > + *
> > + * @nb: notifier block
> > + * @action: event type
> > + * @data: event data
> 
> Hi Evan,
> 
> a minor nit from my side: although it is documented here,
> smu_wbrf_event_handler has no @data parameter, while
> it does have an undocumented _arg parameter.
Thanks for pointing this out. I will fix this.

Evan
> 
> > + *
> > + * Calls relevant amdgpu function in response to wbrf event
> > + * notification from kernel.
> > + */
> > +static int smu_wbrf_event_handler(struct notifier_block *nb,
> > + unsigned long action, void *_arg)
> > +{
> > +   struct smu_context *smu = container_of(nb, struct smu_context,
> > +  wbrf_notifier);
> > +
> > +   switch (action) {
> > +   case WBRF_CHANGED:
> > +   smu_wbrf_handle_exclusion_ranges(smu);
> > +   break;
> > +   default:
> > +   return NOTIFY_DONE;
> > +   };
> > +
> > +   return NOTIFY_OK;
> > +}
> 
> ...

RE: [PATCH V8 2/9] drivers core: add ACPI based WBRF mechanism introduced by AMD

[Quan, Evan]

[AMD Official Use Only - General]



> -Original Message-
> From: Simon Horman 
> Sent: Friday, August 11, 2023 5:38 PM
> To: Quan, Evan 
> Cc: raf...@kernel.org; l...@kernel.org; Deucher, Alexander
> ; Koenig, Christian
> ; Pan, Xinhui ;
> airl...@gmail.com; dan...@ffwll.ch; johan...@sipsolutions.net;
> da...@davemloft.net; eduma...@google.com; k...@kernel.org;
> pab...@redhat.com; Limonciello, Mario ;
> mdaen...@redhat.com; maarten.lankho...@linux.intel.com;
> tzimmerm...@suse.de; hdego...@redhat.com; jingyuwang_...@163.com;
> Lazar, Lijo ; jim.cro...@gmail.com;
> bellosili...@gmail.com; andrealm...@igalia.com; t...@redhat.com;
> j...@jsg.id.au; a...@arndb.de; and...@lunn.ch; linux-
> ker...@vger.kernel.org; linux-a...@vger.kernel.org; amd-
> g...@lists.freedesktop.org; dri-de...@lists.freedesktop.org; linux-
> wirel...@vger.kernel.org; net...@vger.kernel.org
> Subject: Re: [PATCH V8 2/9] drivers core: add ACPI based WBRF mechanism
> introduced by AMD
> 
> On Thu, Aug 10, 2023 at 03:37:56PM +0800, Evan Quan wrote:
> > AMD has introduced an ACPI based mechanism to support WBRF for some
> > platforms with AMD dGPU + WLAN. This needs support from BIOS equipped
> > with necessary AML implementations and dGPU firmwares.
> >
> > For those systems without the ACPI mechanism and developing solutions,
> > user can use/fall-back the generic WBRF solution for diagnosing potential
> > interference issues.
> >
> > And for the platform which does not equip with the necessary AMD ACPI
> > implementations but with CONFIG_WBRF_AMD_ACPI built as 'y', it will
> > fall back to generic WBRF solution if the `wbrf` is set as "on".
> >
> > Co-developed-by: Mario Limonciello 
> > Signed-off-by: Mario Limonciello 
> > Co-developed-by: Evan Quan 
> > Signed-off-by: Evan Quan 
> 
> ...
> 
> > diff --git a/drivers/acpi/amd_wbrf.c b/drivers/acpi/amd_wbrf.c
> 
> ...
> 
> > +static bool check_acpi_wbrf(acpi_handle handle, u64 rev, u64 funcs)
> > +{
> > +   int i;
> > +   u64 mask = 0;
> > +   union acpi_object *obj;
> > +
> > +   if (funcs == 0)
> > +   return false;
> > +
> > +   obj = acpi_evaluate_wbrf(handle, rev, 0);
> > +   if (!obj)
> > +   return false;
> > +
> > +   if (obj->type != ACPI_TYPE_BUFFER)
> > +   return false;
> > +
> > +   /*
> > +* Bit vector providing supported functions information.
> > +* Each bit marks support for one specific function of the WBRF
> method.
> > +*/
> > +   for (i = 0; i < obj->buffer.length && i < 8; i++)
> > +   mask |= (((u64)obj->buffer.pointer[i]) << (i * 8));
> > +
> > +   ACPI_FREE(obj);
> > +
> > +   if ((mask & BIT(WBRF_ENABLED)) &&
> > +(mask & funcs) == funcs)
> 
> Hi Evan,
> 
> a minor nit from my side: the indentation of the line above seems odd.
Thanks. Will update this.

Evan
> 
>   if ((mask & BIT(WBRF_ENABLED)) &&
>   (mask & funcs) == funcs)
> 
> > +   return true;
> > +
> > +   return false;
> > +}
> 
> ...

[PATCH 3/3] Revert "drm/amd/amdgpu: switch on/off vcn power profile mode"

[Arvind Yadav]

This reverts commit 5ce71f59bb9bd3d8a09b96afdbc92975cb6dc303.

Reason for revert: New amdgpu_smu* api is added to switch
on/off profile mode. These new api will allow to change the
GPU power profile based on a submitted job.

Cc: Shashank Sharma 
Cc: Christian Koenig 
Cc: Alex Deucher 
Signed-off-by: Arvind Yadav 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 14 ++
 1 file changed, 2 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 2d94f1b63bd6..70777fcfa626 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -363,7 +363,6 @@ static void amdgpu_vcn_idle_work_handler(struct work_struct 
*work)
container_of(work, struct amdgpu_device, vcn.idle_work.work);
unsigned int fences = 0, fence[AMDGPU_MAX_VCN_INSTANCES] = {0};
unsigned int i, j;
-   int r = 0;
 
for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
if (adev->vcn.harvest_config & (1 << j))
@@ -392,10 +391,6 @@ static void amdgpu_vcn_idle_work_handler(struct 
work_struct *work)
if (!fences && !atomic_read(>vcn.total_submission_cnt)) {
amdgpu_device_ip_set_powergating_state(adev, 
AMD_IP_BLOCK_TYPE_VCN,
   AMD_PG_STATE_GATE);
-   r = amdgpu_dpm_switch_power_profile(adev, 
PP_SMC_POWER_PROFILE_VIDEO,
-   false);
-   if (r)
-   dev_warn(adev->dev, "(%d) failed to disable video power 
profile mode\n", r);
} else {
schedule_delayed_work(>vcn.idle_work, VCN_IDLE_TIMEOUT);
}
@@ -404,16 +399,11 @@ static void amdgpu_vcn_idle_work_handler(struct 
work_struct *work)
 void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
 {
struct amdgpu_device *adev = ring->adev;
-   int r = 0;
 
atomic_inc(>vcn.total_submission_cnt);
 
-   if (!cancel_delayed_work_sync(>vcn.idle_work)) {
-   r = amdgpu_dpm_switch_power_profile(adev, 
PP_SMC_POWER_PROFILE_VIDEO,
-   true);
-   if (r)
-   dev_warn(adev->dev, "(%d) failed to switch to video 
power profile mode\n", r);
-   }
+   if (!cancel_delayed_work_sync(>vcn.idle_work))
+   amdgpu_gfx_off_ctrl(adev, false);
 
mutex_lock(>vcn.vcn_pg_lock);
amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
-- 
2.34.1

[PATCH 2/3] drm/amdgpu: Switch on/off GPU workload profile

[Arvind Yadav]

This patch is to switch the GPU workload profile based
on the submitted job. The workload profile is reset to
default when the job is done.

Cc: Shashank Sharma 
Cc: Christian Koenig 
Cc: Alex Deucher 
Signed-off-by: Arvind Yadav 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
index c3d9d75143f4..8457d2468fd8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
@@ -176,6 +176,9 @@ void amdgpu_job_free_resources(struct amdgpu_job *job)
 static void amdgpu_job_free_cb(struct drm_sched_job *s_job)
 {
struct amdgpu_job *job = to_amdgpu_job(s_job);
+   struct amdgpu_ring *ring = to_amdgpu_ring(s_job->sched);
+
+   amdgpu_put_workload_profile(ring->adev, ring->funcs->type);
 
drm_sched_job_cleanup(s_job);
 
@@ -295,6 +298,8 @@ static struct dma_fence *amdgpu_job_run(struct 
drm_sched_job *sched_job)
DRM_ERROR("Error scheduling IBs (%d)\n", r);
}
 
+   amdgpu_set_workload_profile(ring->adev, ring->funcs->type);
+
job->job_run_counter++;
amdgpu_job_free_resources(job);
 
-- 
2.34.1

[PATCH 0/3] GPU workload hints for better performance

[Arvind Yadav]

AMDGPU SOCs supports dynamic workload based power profiles, which can
provide fine-tuned performance for a particular type of workload.
This patch series adds an interface to set/reset these power profiles
based on the submitted job. The driver can dynamically switch
the power profiles based on submitted job. This can optimize the power
performance when the particular workload is on.

Arvind Yadav (3):
  drm/amdgpu: Add new api to switch on/off power profile mode
  drm/amdgpu: Switch on/off GPU workload profile
  Revert "drm/amd/amdgpu: switch on/off vcn power profile mode"

 drivers/gpu/drm/amd/amdgpu/Makefile   |   2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu.h   |   3 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c|   2 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_job.c   |   5 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c   |  14 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_workload.c  | 156 ++
 drivers/gpu/drm/amd/include/amdgpu_workload.h |  44 +
 7 files changed, 213 insertions(+), 13 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_workload.c
 create mode 100644 drivers/gpu/drm/amd/include/amdgpu_workload.h

-- 
2.34.1

[PATCH 1/3] drm/amdgpu: Add new api to switch on/off power profile mode

[Arvind Yadav]

This patch adds a function which will allow to
change the GPU power profile based on a submitted job.
This can optimize the power performance when the
workload is on.

Cc: Shashank Sharma 
Cc: Christian Koenig 
Cc: Alex Deucher 
Signed-off-by: Arvind Yadav 
---
 drivers/gpu/drm/amd/amdgpu/Makefile   |   2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu.h   |   3 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c|   2 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_workload.c  | 156 ++
 drivers/gpu/drm/amd/include/amdgpu_workload.h |  44 +
 5 files changed, 206 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_workload.c
 create mode 100644 drivers/gpu/drm/amd/include/amdgpu_workload.h

diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile 
b/drivers/gpu/drm/amd/amdgpu/Makefile
index 415a7fa395c4..6a9e187d61e1 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -60,7 +60,7 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
amdgpu_umc.o smu_v11_0_i2c.o amdgpu_fru_eeprom.o amdgpu_rap.o \
amdgpu_fw_attestation.o amdgpu_securedisplay.o \
amdgpu_eeprom.o amdgpu_mca.o amdgpu_psp_ta.o amdgpu_lsdma.o \
-   amdgpu_ring_mux.o
+   amdgpu_ring_mux.o amdgpu_workload.o
 
 amdgpu-$(CONFIG_PROC_FS) += amdgpu_fdinfo.o
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 02b827785e39..1939fa1af8a6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -107,6 +107,7 @@
 #include "amdgpu_fdinfo.h"
 #include "amdgpu_mca.h"
 #include "amdgpu_ras.h"
+#include "amdgpu_workload.h"
 
 #define MAX_GPU_INSTANCE   16
 
@@ -1050,6 +1051,8 @@ struct amdgpu_device {
 
booljob_hang;
booldc_enabled;
+
+   struct amdgpu_smu_workload  smu_workload;
 };
 
 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 5c7d40873ee2..0ec18b8fe29f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3672,6 +3672,8 @@ int amdgpu_device_init(struct amdgpu_device *adev,
 
INIT_WORK(>xgmi_reset_work, amdgpu_device_xgmi_reset_func);
 
+   amdgpu_smu_workload_init(adev);
+
adev->gfx.gfx_off_req_count = 1;
adev->gfx.gfx_off_residency = 0;
adev->gfx.gfx_off_entrycount = 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_workload.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_workload.c
new file mode 100644
index ..ce0339d75c12
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_workload.c
@@ -0,0 +1,156 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright 2023 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include "amdgpu.h"
+
+/* 100 millsecond timeout */
+#define SMU_IDLE_TIMEOUT   msecs_to_jiffies(100)
+
+static enum PP_SMC_POWER_PROFILE
+ring_to_power_profile(uint32_t ring_type)
+{
+   switch (ring_type) {
+   case AMDGPU_RING_TYPE_GFX:
+   return PP_SMC_POWER_PROFILE_FULLSCREEN3D;
+   case AMDGPU_RING_TYPE_COMPUTE:
+   return PP_SMC_POWER_PROFILE_COMPUTE;
+   case AMDGPU_RING_TYPE_UVD:
+   case AMDGPU_RING_TYPE_VCE:
+   case AMDGPU_RING_TYPE_UVD_ENC:
+   case AMDGPU_RING_TYPE_VCN_DEC:
+   case AMDGPU_RING_TYPE_VCN_ENC:
+   case AMDGPU_RING_TYPE_VCN_JPEG:
+   return PP_SMC_POWER_PROFILE_VIDEO;
+   default:
+   return PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
+   }
+}
+
+static void
+amdgpu_power_profile_set(struct amdgpu_device *adev,
+enum PP_SMC_POWER_PROFILE profile)
+{
+   int ret = amdgpu_dpm_switch_power_profile(adev, profile, true);
+
+   if (ret == 0) {
+

Re: [PATCH -next 5/7] drm/virtio: Remove an unnecessary NULL value

[Dmitry Osipenko]

On 8/9/23 06:44, Ruan Jinjie wrote:
> The NULL initialization of the pointer assigned by kzalloc() first is
> not necessary, because if the kzalloc() failed, the pointer will be
> assigned NULL, otherwise it works as usual. so remove it.
> 
> Signed-off-by: Ruan Jinjie 
> ---
>  drivers/gpu/drm/virtio/virtgpu_submit.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/virtio/virtgpu_submit.c 
> b/drivers/gpu/drm/virtio/virtgpu_submit.c
> index 3c00135ead45..82563dbec2ab 100644
> --- a/drivers/gpu/drm/virtio/virtgpu_submit.c
> +++ b/drivers/gpu/drm/virtio/virtgpu_submit.c
> @@ -274,7 +274,7 @@ static int virtio_gpu_fence_event_create(struct 
> drm_device *dev,
>struct virtio_gpu_fence *fence,
>u32 ring_idx)
>  {
> - struct virtio_gpu_fence_event *e = NULL;
> + struct virtio_gpu_fence_event *e;
>   int ret;
>  
>   e = kzalloc(sizeof(*e), GFP_KERNEL);

Reviewed-by: Dmitry Osipenko 

-- 
Best regards,
Dmitry