[PATCH] drm/amdkfd: Add missing gfx11 MQD manager callbacks

[Harish Kasiviswanathan]

From: Jay Cornwall 

mqd_stride function was introduced in commit 129c7b6a0217
("drm/amdkfd: Update MQD management on multi XCC setup")
but not assigned for gfx11. Fixes a NULL dereference in debugfs.

Signed-off-by: Jay Cornwall 
Signed-off-by: Harish Kasiviswanathan 
---
 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c
index 2319467d2d95..0bbf0edbabd4 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c
@@ -457,6 +457,7 @@ struct mqd_manager *mqd_manager_init_v11(enum KFD_MQD_TYPE 
type,
mqd->is_occupied = kfd_is_occupied_cp;
mqd->mqd_size = sizeof(struct v11_compute_mqd);
mqd->get_wave_state = get_wave_state;
+   mqd->mqd_stride = kfd_mqd_stride;
 #if defined(CONFIG_DEBUG_FS)
mqd->debugfs_show_mqd = debugfs_show_mqd;
 #endif
@@ -472,6 +473,7 @@ struct mqd_manager *mqd_manager_init_v11(enum KFD_MQD_TYPE 
type,
mqd->destroy_mqd = destroy_hiq_mqd;
mqd->is_occupied = kfd_is_occupied_cp;
mqd->mqd_size = sizeof(struct v11_compute_mqd);
+   mqd->mqd_stride = kfd_mqd_stride;
 #if defined(CONFIG_DEBUG_FS)
mqd->debugfs_show_mqd = debugfs_show_mqd;
 #endif
@@ -501,6 +503,7 @@ struct mqd_manager *mqd_manager_init_v11(enum KFD_MQD_TYPE 
type,
mqd->destroy_mqd = kfd_destroy_mqd_sdma;
mqd->is_occupied = kfd_is_occupied_sdma;
mqd->mqd_size = sizeof(struct v11_sdma_mqd);
+   mqd->mqd_stride = kfd_mqd_stride;
 #if defined(CONFIG_DEBUG_FS)
mqd->debugfs_show_mqd = debugfs_show_mqd_sdma;
 #endif
-- 
2.34.1

Re: drm/amd/pm: workaround for the wrong ac power detection on smu 13.0.0

[Mario Limonciello]

On 8/24/2023 22:19, Kenneth Feng wrote:

workaround for the wrong ac power detection on smu 13.0.0

Signed-off-by: Kenneth Feng 


This workaround appears to be only necessary if you're missing these 
commits.


a7fbfd44c020 ("usb: typec: ucsi: Mark dGPUs as DEVICE scope")
95339f40a8b6 ("power: supply: Fix logic checking if system is running 
from battery")


If this is run on a kernel with those commits then it's going to be 
broken in reverse.


I suspect the reason that you want to do this workaround is because 
you're trying to run on a kernel without them and which you can't add them.


If that's the case I think a better/safer temporary workaround is to add 
a module parameter or a debugfs entry to use.



---
  drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c   | 3 +--
  drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 1 -
  2 files changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index 0232adb95df3..fd1798fd716e 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -1021,8 +1021,7 @@ static int smu_v13_0_process_pending_interrupt(struct 
smu_context *smu)
  {
int ret = 0;
  
-	if (smu->dc_controlled_by_gpio &&

-   smu_cmn_feature_is_enabled(smu, SMU_FEATURE_ACDC_BIT))
+   if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_ACDC_BIT))
ret = smu_v13_0_allow_ih_interrupt(smu);
  
  	return ret;

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index 3903a47669e4..128468355375 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -2664,7 +2664,6 @@ static const struct pptable_funcs smu_v13_0_0_ppt_funcs = 
{
.enable_mgpu_fan_boost = smu_v13_0_0_enable_mgpu_fan_boost,
.get_power_limit = smu_v13_0_0_get_power_limit,
.set_power_limit = smu_v13_0_set_power_limit,
-   .set_power_source = smu_v13_0_set_power_source,
.get_power_profile_mode = smu_v13_0_0_get_power_profile_mode,
.set_power_profile_mode = smu_v13_0_0_set_power_profile_mode,
.run_btc = smu_v13_0_run_btc,

[PATCH] drm/amdkfd: Checkpoint and restore queues on GFX11

[David Francis]

The code in kfd_mqd_manager_v11.c to support criu dump and
restore of queue state was missing.

Added it; should be equivalent to kfd_mqd_manager_v10.c.

CC: Felix Kuehling 
Signed-off-by: David Francis 
---
 .../gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c  | 41 +++
 1 file changed, 41 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c
index 2319467d2d95..2a79d37da95d 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c
@@ -321,6 +321,43 @@ static int get_wave_state(struct mqd_manager *mm, void 
*mqd,
return 0;
 }
 
+static void checkpoint_mqd(struct mqd_manager *mm, void *mqd, void *mqd_dst, 
void *ctl_stack_dst)
+{
+   struct v11_compute_mqd *m;
+
+   m = get_mqd(mqd);
+
+   memcpy(mqd_dst, m, sizeof(struct v11_compute_mqd));
+}
+
+static void restore_mqd(struct mqd_manager *mm, void **mqd,
+   struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
+   struct queue_properties *qp,
+   const void *mqd_src,
+   const void *ctl_stack_src, const u32 ctl_stack_size)
+{
+   uint64_t addr;
+   struct v11_compute_mqd *m;
+
+   m = (struct v11_compute_mqd *) mqd_mem_obj->cpu_ptr;
+   addr = mqd_mem_obj->gpu_addr;
+
+   memcpy(m, mqd_src, sizeof(*m));
+
+   *mqd = m;
+   if (gart_addr)
+   *gart_addr = addr;
+
+   m->cp_hqd_pq_doorbell_control =
+   qp->doorbell_off <<
+   CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT;
+   pr_debug("cp_hqd_pq_doorbell_control 0x%x\n",
+   m->cp_hqd_pq_doorbell_control);
+
+   qp->is_active = 0;
+}
+
+
 static void init_mqd_hiq(struct mqd_manager *mm, void **mqd,
struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
struct queue_properties *q)
@@ -457,6 +494,8 @@ struct mqd_manager *mqd_manager_init_v11(enum KFD_MQD_TYPE 
type,
mqd->is_occupied = kfd_is_occupied_cp;
mqd->mqd_size = sizeof(struct v11_compute_mqd);
mqd->get_wave_state = get_wave_state;
+   mqd->checkpoint_mqd = checkpoint_mqd;
+   mqd->restore_mqd = restore_mqd;
 #if defined(CONFIG_DEBUG_FS)
mqd->debugfs_show_mqd = debugfs_show_mqd;
 #endif
@@ -500,6 +539,8 @@ struct mqd_manager *mqd_manager_init_v11(enum KFD_MQD_TYPE 
type,
mqd->update_mqd = update_mqd_sdma;
mqd->destroy_mqd = kfd_destroy_mqd_sdma;
mqd->is_occupied = kfd_is_occupied_sdma;
+   mqd->checkpoint_mqd = checkpoint_mqd;
+   mqd->restore_mqd = restore_mqd;
mqd->mqd_size = sizeof(struct v11_sdma_mqd);
 #if defined(CONFIG_DEBUG_FS)
mqd->debugfs_show_mqd = debugfs_show_mqd_sdma;
-- 
2.34.1

Re: [PATCH] drm/amd/display: Fix up kdoc format for 'dc_set_edp_power'

[Harry Wentland]

On 2023-08-25 06:38, Srinivasan Shanmugam wrote:

Fixes the following W=1 kernel build warning:

drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:5261: warning: Cannot 
understand  ***

Cc: Ian Chen 
Cc: Rodrigo Siqueira 
Cc: Harry Wentland 
Cc: Aurabindo Pillai 
Cc: Alex Deucher 
Signed-off-by: Srinivasan Shanmugam 


Reviewed-by: Harry Wentland 

Harry


---
  drivers/gpu/drm/amd/display/dc/core/dc.c | 7 +--
  1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 025e0fdf486d..ed225e1a1299 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -5258,13 +5258,16 @@ void dc_query_current_properties(struct dc *dc, struct 
dc_current_properties *pr
  }
  
  /**

- *
   * dc_set_edp_power() - DM controls eDP power to be ON/OFF
   *
   * Called when DM wants to power on/off eDP.
   * Only work on links with flag skip_implict_edp_power_control is set.
   *
- *
+ * @dc: Current DC state
+ * @edp_link: a link with eDP connector signal type
+ * @powerOn: power on/off eDP
+ *
+ * Return: void
   */
  void dc_set_edp_power(const struct dc *dc, struct dc_link *edp_link,
 bool powerOn)

[PATCH] drm/amdkfd: Replace pr_err with dev_err

[Asad Kamal]

Replace pr_err with dev_err to show the bus-id of
failing device with kfd queue errors

Signed-off-by: Asad Kamal 
Reviewed-by: Lijo Lazar 
---
 .../drm/amd/amdkfd/kfd_device_queue_manager.c | 116 +++---
 drivers/gpu/drm/amd/amdkfd/kfd_priv.h |   2 +-
 2 files changed, 71 insertions(+), 47 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index b166f30f083e..23acb959d841 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -232,8 +232,8 @@ static int add_queue_mes(struct device_queue_manager *dqm, 
struct queue *q,
 
queue_type = convert_to_mes_queue_type(q->properties.type);
if (queue_type < 0) {
-   pr_err("Queue type not supported with MES, queue:%d\n",
-   q->properties.type);
+   dev_err(adev->dev, "Queue type not supported with MES, 
queue:%d\n",
+   q->properties.type);
return -EINVAL;
}
queue_input.queue_type = (uint32_t)queue_type;
@@ -244,9 +244,9 @@ static int add_queue_mes(struct device_queue_manager *dqm, 
struct queue *q,
r = adev->mes.funcs->add_hw_queue(&adev->mes, &queue_input);
amdgpu_mes_unlock(&adev->mes);
if (r) {
-   pr_err("failed to add hardware queue to MES, doorbell=0x%x\n",
+   dev_err(adev->dev, "failed to add hardware queue to MES, 
doorbell=0x%x\n",
q->properties.doorbell_off);
-   pr_err("MES might be in unrecoverable state, issue a GPU 
reset\n");
+   dev_err(adev->dev, "MES might be in unrecoverable state, issue 
a GPU reset\n");
kfd_hws_hang(dqm);
}
 
@@ -272,9 +272,9 @@ static int remove_queue_mes(struct device_queue_manager 
*dqm, struct queue *q,
amdgpu_mes_unlock(&adev->mes);
 
if (r) {
-   pr_err("failed to remove hardware queue from MES, 
doorbell=0x%x\n",
+   dev_err(adev->dev, "failed to remove hardware queue from MES, 
doorbell=0x%x\n",
q->properties.doorbell_off);
-   pr_err("MES might be in unrecoverable state, issue a GPU 
reset\n");
+   dev_err(adev->dev, "MES might be in unrecoverable state, issue 
a GPU reset\n");
kfd_hws_hang(dqm);
}
 
@@ -284,6 +284,7 @@ static int remove_queue_mes(struct device_queue_manager 
*dqm, struct queue *q,
 static int remove_all_queues_mes(struct device_queue_manager *dqm)
 {
struct device_process_node *cur;
+   struct kfd_node *dev = dqm->dev;
struct qcm_process_device *qpd;
struct queue *q;
int retval = 0;
@@ -294,7 +295,7 @@ static int remove_all_queues_mes(struct 
device_queue_manager *dqm)
if (q->properties.is_active) {
retval = remove_queue_mes(dqm, q, qpd);
if (retval) {
-   pr_err("%s: Failed to remove queue %d 
for dev %d",
+   dev_err(dev->adev->dev, "%s: Failed to 
remove queue %d for dev %d",
__func__,
q->properties.queue_id,
dqm->dev->id);
@@ -443,6 +444,7 @@ static int allocate_vmid(struct device_queue_manager *dqm,
struct qcm_process_device *qpd,
struct queue *q)
 {
+   struct kfd_node *dev = dqm->dev;
int allocated_vmid = -1, i;
 
for (i = dqm->dev->vm_info.first_vmid_kfd;
@@ -454,7 +456,7 @@ static int allocate_vmid(struct device_queue_manager *dqm,
}
 
if (allocated_vmid < 0) {
-   pr_err("no more vmid to allocate\n");
+   dev_err(dev->adev->dev, "no more vmid to allocate\n");
return -ENOSPC;
}
 
@@ -510,10 +512,12 @@ static void deallocate_vmid(struct device_queue_manager 
*dqm,
struct qcm_process_device *qpd,
struct queue *q)
 {
+   struct kfd_node *dev = dqm->dev;
+
/* On GFX v7, CP doesn't flush TC at dequeue */
if (q->device->adev->asic_type == CHIP_HAWAII)
if (flush_texture_cache_nocpsch(q->device, qpd))
-   pr_err("Failed to flush TC\n");
+   dev_err(dev->adev->dev, "Failed to flush TC\n");
 
kfd_flush_tlb(qpd_to_pdd(qpd), TLB_FLUSH_LEGACY);
 
@@ -708,7 +712,7 @@ static int dbgdev_wave_reset_wavefronts(struct kfd_node 
*dev, struct kfd_process
pr_debug("Killing all process wavefronts\n");
 
if (!dev->kfd2kgd->get_atc_vmid_pasid_mapping_info) {
-   pr_err("no vmid pasid mapping supported \n");
+   dev_err(dev->adev->dev, "no vmid pa

Re: [PATCH v2 31/34] drm/amd/display: set stream gamut remap matrix to MPC for DCN301

[Melissa Wen]

On 08/22, Pekka Paalanen wrote:
> On Thu, 10 Aug 2023 15:03:11 -0100
> Melissa Wen  wrote:
> 
> > dc->caps.color.mpc.gamut_remap says there is a post-blending color block
> > for gamut remap matrix for DCN3 HW family and newer versions. However,
> > those drivers still follow DCN10 programming that remap stream
> > gamut_remap_matrix to DPP (pre-blending).
> 
> That's ok only as long as CRTC degamma is pass-through. Blending itself
> is a linear operation, so it doesn't matter if a matrix is applied to
> the blending result or to all blending inputs. But you cannot move a
> matrix operation to the other side of a non-linear operation, and you
> cannot move a non-linear operation across blending.

Oh, I'm not moving it, what I'm doing here is the opposite and fixing
it. This patch puts each pre- and post-blending CTM in their right
place, since we have the HW caps for it on DCN3+... Or are you just
pointing out the implementation mistake on old driver versions?

> 
> 
> Thanks,
> pq
> 
> > To enable pre-blending and post-blending gamut_remap matrix supports at
> > the same time, set stream gamut_remap to MPC and plane gamut_remap to
> > DPP for DCN301 that support both.
> > 
> > It was tested using IGT KMS color tests for DRM CRTC CTM property and it
> > preserves test results.
> > 
> > Signed-off-by: Melissa Wen 
> > ---
> >  .../drm/amd/display/dc/dcn30/dcn30_hwseq.c| 37 +++
> >  .../drm/amd/display/dc/dcn30/dcn30_hwseq.h|  3 ++
> >  .../drm/amd/display/dc/dcn301/dcn301_init.c   |  2 +-
> >  3 files changed, 41 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c 
> > b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> > index 4cd4ae07d73d..4fb4e9ec03f1 100644
> > --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> > +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> > @@ -186,6 +186,43 @@ bool dcn30_set_input_transfer_func(struct dc *dc,
> > return result;
> >  }
> >  
> > +void dcn30_program_gamut_remap(struct pipe_ctx *pipe_ctx)
> > +{
> > +   int i = 0;
> > +   struct dpp_grph_csc_adjustment dpp_adjust;
> > +   struct mpc_grph_gamut_adjustment mpc_adjust;
> > +   int mpcc_id = pipe_ctx->plane_res.hubp->inst;
> > +   struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
> > +
> > +   memset(&dpp_adjust, 0, sizeof(dpp_adjust));
> > +   dpp_adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
> > +
> > +   if (pipe_ctx->plane_state &&
> > +   pipe_ctx->plane_state->gamut_remap_matrix.enable_remap == true) {
> > +   dpp_adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
> > +   for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
> > +   dpp_adjust.temperature_matrix[i] =
> > +   
> > pipe_ctx->plane_state->gamut_remap_matrix.matrix[i];
> > +   }
> > +
> > +   
> > pipe_ctx->plane_res.dpp->funcs->dpp_set_gamut_remap(pipe_ctx->plane_res.dpp,
> > +   &dpp_adjust);
> > +
> > +   memset(&mpc_adjust, 0, sizeof(mpc_adjust));
> > +   mpc_adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
> > +
> > +   if (pipe_ctx->top_pipe == NULL) {
> > +   if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
> > +   mpc_adjust.gamut_adjust_type = 
> > GRAPHICS_GAMUT_ADJUST_TYPE_SW;
> > +   for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
> > +   mpc_adjust.temperature_matrix[i] =
> > +   
> > pipe_ctx->stream->gamut_remap_matrix.matrix[i];
> > +   }
> > +   }
> > +
> > +   mpc->funcs->set_gamut_remap(mpc, mpcc_id, &mpc_adjust);
> > +}
> > +
> >  bool dcn30_set_output_transfer_func(struct dc *dc,
> > struct pipe_ctx *pipe_ctx,
> > const struct dc_stream_state *stream)
> > diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h 
> > b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h
> > index a24a8e33a3d2..cb34ca932a5f 100644
> > --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h
> > +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h
> > @@ -58,6 +58,9 @@ bool dcn30_set_blend_lut(struct pipe_ctx *pipe_ctx,
> >  bool dcn30_set_input_transfer_func(struct dc *dc,
> > struct pipe_ctx *pipe_ctx,
> > const struct dc_plane_state *plane_state);
> > +
> > +void dcn30_program_gamut_remap(struct pipe_ctx *pipe_ctx);
> > +
> >  bool dcn30_set_output_transfer_func(struct dc *dc,
> > struct pipe_ctx *pipe_ctx,
> > const struct dc_stream_state *stream);
> > diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.c 
> > b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.c
> > index 257df8660b4c..81fd50ee97c3 100644
> > --- a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.c
> > +++ b/drivers/

Re: [PATCH v2 19/34] drm/amd/display: decouple steps for mapping CRTC degamma to DC plane

[Melissa Wen]

On 08/22, Pekka Paalanen wrote:
> On Thu, 10 Aug 2023 15:02:59 -0100
> Melissa Wen  wrote:
> 
> > The next patch adds pre-blending degamma to AMD color mgmt pipeline, but
> > pre-blending degamma caps (DPP) is currently in use to provide DRM CRTC
> > atomic degamma or implict degamma on legacy gamma. Detach degamma usage
> > regarging CRTC color properties to manage plane and CRTC color
> > correction combinations.
> > 
> > Reviewed-by: Harry Wentland 
> > Signed-off-by: Melissa Wen 
> > ---
> >  .../amd/display/amdgpu_dm/amdgpu_dm_color.c   | 59 +--
> >  1 file changed, 41 insertions(+), 18 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c 
> > b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
> > index 68e9f2c62f2e..74eb02655d96 100644
> > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
> > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
> > @@ -764,20 +764,9 @@ int amdgpu_dm_update_crtc_color_mgmt(struct 
> > dm_crtc_state *crtc)
> > return 0;
> >  }
> >  
> > -/**
> > - * amdgpu_dm_update_plane_color_mgmt: Maps DRM color management to DC 
> > plane.
> > - * @crtc: amdgpu_dm crtc state
> > - * @dc_plane_state: target DC surface
> > - *
> > - * Update the underlying dc_stream_state's input transfer function (ITF) in
> > - * preparation for hardware commit. The transfer function used depends on
> > - * the preparation done on the stream for color management.
> > - *
> > - * Returns:
> > - * 0 on success. -ENOMEM if mem allocation fails.
> > - */
> > -int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc,
> > - struct dc_plane_state *dc_plane_state)
> > +static int
> > +map_crtc_degamma_to_dc_plane(struct dm_crtc_state *crtc,
> > +struct dc_plane_state *dc_plane_state)
> >  {
> > const struct drm_color_lut *degamma_lut;
> > enum dc_transfer_func_predefined tf = TRANSFER_FUNCTION_SRGB;
> > @@ -800,8 +789,7 @@ int amdgpu_dm_update_plane_color_mgmt(struct 
> > dm_crtc_state *crtc,
> >  °amma_size);
> > ASSERT(degamma_size == MAX_COLOR_LUT_ENTRIES);
> >  
> > -   dc_plane_state->in_transfer_func->type =
> > -   TF_TYPE_DISTRIBUTED_POINTS;
> > +   dc_plane_state->in_transfer_func->type = 
> > TF_TYPE_DISTRIBUTED_POINTS;
> >  
> > /*
> >  * This case isn't fully correct, but also fairly
> > @@ -837,7 +825,7 @@ int amdgpu_dm_update_plane_color_mgmt(struct 
> > dm_crtc_state *crtc,
> >degamma_lut, degamma_size);
> > if (r)
> > return r;
> > -   } else if (crtc->cm_is_degamma_srgb) {
> > +   } else {
> > /*
> >  * For legacy gamma support we need the regamma input
> >  * in linear space. Assume that the input is sRGB.
> > @@ -847,8 +835,43 @@ int amdgpu_dm_update_plane_color_mgmt(struct 
> > dm_crtc_state *crtc,
> >  
> > if (tf != TRANSFER_FUNCTION_SRGB &&
> > !mod_color_calculate_degamma_params(NULL,
> > -   dc_plane_state->in_transfer_func, NULL, false))
> > +   
> > dc_plane_state->in_transfer_func,
> > +   NULL, false))
> > return -ENOMEM;
> > +   }
> > +
> > +   return 0;
> > +}
> > +
> > +/**
> > + * amdgpu_dm_update_plane_color_mgmt: Maps DRM color management to DC 
> > plane.
> > + * @crtc: amdgpu_dm crtc state
> > + * @dc_plane_state: target DC surface
> > + *
> > + * Update the underlying dc_stream_state's input transfer function (ITF) in
> > + * preparation for hardware commit. The transfer function used depends on
> > + * the preparation done on the stream for color management.
> > + *
> > + * Returns:
> > + * 0 on success. -ENOMEM if mem allocation fails.
> > + */
> > +int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc,
> > + struct dc_plane_state *dc_plane_state)
> > +{
> > +   bool has_crtc_cm_degamma;
> > +   int ret;
> > +
> > +   has_crtc_cm_degamma = (crtc->cm_has_degamma || 
> > crtc->cm_is_degamma_srgb);
> > +   if (has_crtc_cm_degamma){
> > +   /* AMD HW doesn't have post-blending degamma caps. When DRM
> > +* CRTC atomic degamma is set, we maps it to DPP degamma block
> > +* (pre-blending) or, on legacy gamma, we use DPP degamma to
> > +* linearize (implicit degamma) from sRGB/BT709 according to
> > +* the input space.
> 
> Uhh, you can't just move degamma before blending if KMS userspace
> wants it after blending. That would be incorrect behaviour. If you
> can't implement it correctly, reject it.
> 
> I hope that magical unexpected linearization is not done with atomic,
> either.
> 
> Or maybe this is all a lost cause, and only the new color-op pipelin

Re: [PATCH v2 07/34] drm/amd/display: explicitly define EOTF and inverse EOTF

[Melissa Wen]

On 08/22, Pekka Paalanen wrote:
> On Thu, 10 Aug 2023 15:02:47 -0100
> Melissa Wen  wrote:
> 
> > Instead of relying on color block names to get the transfer function
> > intention regarding encoding pixel's luminance, define supported
> > Electro-Optical Transfer Functions (EOTFs) and inverse EOTFs, that
> > includes pure gamma or standardized transfer functions.
> > 
> > Suggested-by: Harry Wentland 
> > Signed-off-by: Melissa Wen 
> > ---
> >  .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 19 +++--
> >  .../amd/display/amdgpu_dm/amdgpu_dm_color.c   | 69 +++
> >  2 files changed, 67 insertions(+), 21 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h 
> > b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
> > index c749c9cb3d94..f6251ed89684 100644
> > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
> > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
> > @@ -718,14 +718,21 @@ extern const struct amdgpu_ip_block_version 
> > dm_ip_block;
> >  
> >  enum amdgpu_transfer_function {
> > AMDGPU_TRANSFER_FUNCTION_DEFAULT,
> > -   AMDGPU_TRANSFER_FUNCTION_SRGB,
> > -   AMDGPU_TRANSFER_FUNCTION_BT709,
> > -   AMDGPU_TRANSFER_FUNCTION_PQ,
> > +   AMDGPU_TRANSFER_FUNCTION_SRGB_EOTF,
> > +   AMDGPU_TRANSFER_FUNCTION_BT709_EOTF,
> > +   AMDGPU_TRANSFER_FUNCTION_PQ_EOTF,
> > AMDGPU_TRANSFER_FUNCTION_LINEAR,
> > AMDGPU_TRANSFER_FUNCTION_UNITY,
> > -   AMDGPU_TRANSFER_FUNCTION_GAMMA22,
> > -   AMDGPU_TRANSFER_FUNCTION_GAMMA24,
> > -   AMDGPU_TRANSFER_FUNCTION_GAMMA26,
> > +   AMDGPU_TRANSFER_FUNCTION_GAMMA22_EOTF,
> > +   AMDGPU_TRANSFER_FUNCTION_GAMMA24_EOTF,
> > +   AMDGPU_TRANSFER_FUNCTION_GAMMA26_EOTF,
> > +   AMDGPU_TRANSFER_FUNCTION_SRGB_INV_EOTF,
> > +   AMDGPU_TRANSFER_FUNCTION_BT709_INV_EOTF,
> > +   AMDGPU_TRANSFER_FUNCTION_PQ_INV_EOTF,
> > +   AMDGPU_TRANSFER_FUNCTION_GAMMA22_INV_EOTF,
> > +   AMDGPU_TRANSFER_FUNCTION_GAMMA24_INV_EOTF,
> > +   AMDGPU_TRANSFER_FUNCTION_GAMMA26_INV_EOTF,
> > +AMDGPU_TRANSFER_FUNCTION_COUNT
> >  };
> >  
> >  struct dm_plane_state {
> > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c 
> > b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
> > index 56ce008b9095..cc2187c0879a 100644
> > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
> > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
> > @@ -85,18 +85,59 @@ void amdgpu_dm_init_color_mod(void)
> >  }
> >  
> >  #ifdef AMD_PRIVATE_COLOR
> > -static const struct drm_prop_enum_list 
> > amdgpu_transfer_function_enum_list[] = {
> > -   { AMDGPU_TRANSFER_FUNCTION_DEFAULT, "Default" },
> > -   { AMDGPU_TRANSFER_FUNCTION_SRGB, "sRGB" },
> > -   { AMDGPU_TRANSFER_FUNCTION_BT709, "BT.709" },
> > -   { AMDGPU_TRANSFER_FUNCTION_PQ, "PQ (Perceptual Quantizer)" },
> > -   { AMDGPU_TRANSFER_FUNCTION_LINEAR, "Linear" },
> > -   { AMDGPU_TRANSFER_FUNCTION_UNITY, "Unity" },
> > -   { AMDGPU_TRANSFER_FUNCTION_GAMMA22, "Gamma 2.2" },
> > -   { AMDGPU_TRANSFER_FUNCTION_GAMMA24, "Gamma 2.4" },
> > -   { AMDGPU_TRANSFER_FUNCTION_GAMMA26, "Gamma 2.6" },
> > +static const char * const
> > +amdgpu_transfer_function_names[] = {
> > +   [AMDGPU_TRANSFER_FUNCTION_DEFAULT]  = "Default",
> > +   [AMDGPU_TRANSFER_FUNCTION_LINEAR]   = "Linear",
> 
> Hi,
> 
> if the below is identity, then what is linear? Is there a coefficient
> (multiplier) somewhere? Offset?
> 
> > +   [AMDGPU_TRANSFER_FUNCTION_UNITY]= "Unity",
> 
> Should "Unity" be called "Identity"?

AFAIU, AMD treats Linear and Unity as the same: Identity. So, IIUC,
indeed merging both as identity sounds the best approach.   
> 
> Doesn't unity mean that the output is always 1.0 regardless of input?
> 
> > +   [AMDGPU_TRANSFER_FUNCTION_SRGB_EOTF]= "sRGB EOTF",
> > +   [AMDGPU_TRANSFER_FUNCTION_BT709_EOTF]   = "BT.709 EOTF",
> 
> BT.709 says about "Overall opto-electronic transfer characteristics at
> source":
> 
>   In typical production practice the encoding function of image
>   sources is adjusted so that the final picture has the desired
>   look, as viewed on a reference monitor having the reference
>   decoding function of Recommendation ITU-R BT.1886, in the
>   reference viewing environment defined in Recommendation ITU-R
>   BT.2035.
> 
> IOW, typically people tweak the encoding function instead of using
> BT.709 OETF as is, which means that inverting the BT.709 OETF produces
> something slightly unknown. The note about BT.1886 means that that
> something is also not quite how it's supposed to be turned into light.
> 
> Should this enum item be "BT.709 inverse OETF" and respectively below a
> "BT.709 OETF"?
> 
> What curve does the hardware actually implement?

H.. I think I got confused in using OETF here since it's done within
a camera. Looking at the coefficients used by AMD color module when not
using ROM but build encoding and decoding curves[1] on pre-defined TF

Re: [V10 7/8] drm/amd/pm: enable Wifi RFI mitigation feature support for SMU13.0.0

[Lazar, Lijo]

On 8/25/2023 2:08 PM, Evan Quan wrote:

Fulfill the SMU13.0.0 support for Wifi RFI mitigation feature.

Signed-off-by: Evan Quan 
Reviewed-by: Mario Limonciello 
---
  drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h |  3 +
  drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h  |  3 +-
  drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h  |  3 +
  .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c|  9 +++
  .../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c  | 60 +++
  5 files changed, 77 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h 
b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
index 60d595344c45..a081e6bb27c4 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
@@ -325,6 +325,7 @@ enum smu_table_id
SMU_TABLE_PACE,
SMU_TABLE_ECCINFO,
SMU_TABLE_COMBO_PPTABLE,
+   SMU_TABLE_WIFIBAND,
SMU_TABLE_COUNT,
  };
  
@@ -1501,6 +1502,8 @@ enum smu_baco_seq {

 __dst_size);  \
  })
  
+#define HZ_IN_MHZ		100U

+
  #if !defined(SWSMU_CODE_LAYER_L2) && !defined(SWSMU_CODE_LAYER_L3) && 
!defined(SWSMU_CODE_LAYER_L4)
  int smu_get_power_limit(void *handle,
uint32_t *limit,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h 
b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
index 297b70b9388f..5bbb60289a79 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
@@ -245,7 +245,8 @@
__SMU_DUMMY_MAP(AllowGpo),  \
__SMU_DUMMY_MAP(Mode2Reset),\
__SMU_DUMMY_MAP(RequestI2cTransaction), \
-   __SMU_DUMMY_MAP(GetMetricsTable),
+   __SMU_DUMMY_MAP(GetMetricsTable), \
+   __SMU_DUMMY_MAP(EnableUCLKShadow),
  
  #undef __SMU_DUMMY_MAP

  #define __SMU_DUMMY_MAP(type) SMU_MSG_##type
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h 
b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
index 355c156d871a..dd70b56aa71e 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
@@ -299,5 +299,8 @@ int smu_v13_0_update_pcie_parameters(struct smu_context 
*smu,
 uint32_t pcie_gen_cap,
 uint32_t pcie_width_cap);
  
+int smu_v13_0_enable_uclk_shadow(struct smu_context *smu,

+bool enablement);
+
  #endif
  #endif
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index 9b62b45ebb7f..6a5cb582aa92 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -2472,3 +2472,12 @@ int smu_v13_0_update_pcie_parameters(struct smu_context 
*smu,
  
  	return 0;

  }
+
+int smu_v13_0_enable_uclk_shadow(struct smu_context *smu,
+bool enablement)
+{
+   return smu_cmn_send_smc_msg_with_param(smu,
+  SMU_MSG_EnableUCLKShadow,
+  enablement,
+  NULL);
+}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index 3d188616ba24..fd3ac18653ed 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -154,6 +154,7 @@ static struct cmn2asic_msg_mapping 
smu_v13_0_0_message_map[SMU_MSG_MAX_COUNT] =
MSG_MAP(AllowGpo,   PPSMC_MSG_SetGpoAllow,  
 0),
MSG_MAP(AllowIHHostInterrupt,   PPSMC_MSG_AllowIHHostInterrupt, 
  0),
MSG_MAP(ReenableAcDcInterrupt,  
PPSMC_MSG_ReenableAcDcInterrupt,   0),
+   MSG_MAP(EnableUCLKShadow,   PPSMC_MSG_EnableUCLKShadow, 
   0),
  };
  
  static struct cmn2asic_mapping smu_v13_0_0_clk_map[SMU_CLK_COUNT] = {

@@ -237,6 +238,7 @@ static struct cmn2asic_mapping 
smu_v13_0_0_table_map[SMU_TABLE_COUNT] = {
TAB_MAP(I2C_COMMANDS),
TAB_MAP(ECCINFO),
TAB_MAP(OVERDRIVE),
+   TAB_MAP(WIFIBAND),
  };
  
  static struct cmn2asic_mapping smu_v13_0_0_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {

@@ -481,6 +483,9 @@ static int smu_v13_0_0_tables_init(struct smu_context *smu)
PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
SMU_TABLE_INIT(tables, SMU_TABLE_ECCINFO, sizeof(EccInfoTable_t),
PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
+   SMU_TABLE_INIT(tables, SMU_TABLE_WIFIBAND,
+  sizeof(WifiBandEntryTable_t), PAGE_SIZE,
+  AMDGPU_GEM_DOMAIN_VRAM);
  
  	smu_table->metrics_table = kzalloc(sizeof(SmuMetricsExternal_t), GFP_KERNEL);

if (!smu_table->metrics_table)
@@ -2593,6 +2598,58 @@ static ssize_t smu_v13_0_0_get_ecc_info(struct 
smu_context *smu,
return 

Re: [V10 5/8] drm/amd/pm: setup the framework to support Wifi RFI mitigation feature

[Lazar, Lijo]

On 8/25/2023 2:08 PM, Evan Quan wrote:

With WBRF feature supported, as a driver responding to the frequencies,
amdgpu driver is able to do shadow pstate switching to mitigate possible
interference(between its (G-)DDR memory clocks and local radio module
frequency bands used by Wifi 6/6e/7).

Signed-off-by: Evan Quan 
Reviewed-by: Mario Limonciello 
--
v1->v2:
   - update the prompt for feature support(Lijo)
v8->v9:
   - update parameter document for smu_wbrf_event_handler(Simon)
v9->v10:
  - correct the logics for wbrf range sorting(Lijo)
---
  drivers/gpu/drm/amd/amdgpu/amdgpu.h   |   2 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c   |  17 ++
  drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 195 ++
  drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h |  23 +++
  drivers/gpu/drm/amd/pm/swsmu/smu_internal.h   |   3 +
  5 files changed, 240 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index a3b86b86dc47..2bfc9111ab00 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -247,6 +247,8 @@ extern int amdgpu_sg_display;
  
  extern int amdgpu_user_partt_mode;
  
+extern int amdgpu_wbrf;

+
  #define AMDGPU_VM_MAX_NUM_CTX 4096
  #define AMDGPU_SG_THRESHOLD   (256*1024*1024)
  #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS3000
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 0593ef8fe0a6..1c574bd3b60d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -195,6 +195,7 @@ int amdgpu_use_xgmi_p2p = 1;
  int amdgpu_vcnfw_log;
  int amdgpu_sg_display = -1; /* auto */
  int amdgpu_user_partt_mode = AMDGPU_AUTO_COMPUTE_PARTITION_MODE;
+int amdgpu_wbrf = -1;
  
  static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work);
  
@@ -981,6 +982,22 @@ module_param_named(user_partt_mode, amdgpu_user_partt_mode, uint, 0444);

  module_param(enforce_isolation, bool, 0444);
  MODULE_PARM_DESC(enforce_isolation, "enforce process isolation between graphics 
and compute . enforce_isolation = on");
  
+/**

+ * DOC: wbrf (int)
+ * Enable Wifi RFI interference mitigation feature.
+ * Due to electrical and mechanical constraints there may be likely 
interference of
+ * relatively high-powered harmonics of the (G-)DDR memory clocks with local 
radio
+ * module frequency bands used by Wifi 6/6e/7. To mitigate the possible RFI 
interference,
+ * with this feature enabled, PMFW will use either “shadowed P-State” or 
“P-State” based
+ * on active list of frequencies in-use (to be avoided) as part of initial 
setting or
+ * P-state transition. However, there may be potential performance impact with 
this
+ * feature enabled.
+ * (0 = disabled, 1 = enabled, -1 = auto (default setting, will be enabled if 
supported))
+ */
+MODULE_PARM_DESC(wbrf,
+   "Enable Wifi RFI interference mitigation (0 = disabled, 1 = enabled, -1 = 
auto(default)");
+module_param_named(wbrf, amdgpu_wbrf, int, 0444);
+
  /* These devices are not supported by amdgpu.
   * They are supported by the mach64, r128, radeon drivers
   */
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c 
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index ce41a8309582..bdfd234d1558 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -1228,6 +1228,174 @@ static int smu_get_thermal_temperature_range(struct 
smu_context *smu)
return ret;
  }
  
+/**

+ * smu_wbrf_handle_exclusion_ranges - consume the wbrf exclusion ranges
+ *
+ * @smu: smu_context pointer
+ *
+ * Retrieve the wbrf exclusion ranges and send them to PMFW for proper 
handling.
+ * Returns 0 on success, error on failure.
+ */
+static int smu_wbrf_handle_exclusion_ranges(struct smu_context *smu)
+{
+   struct wbrf_ranges_in_out wbrf_exclusion = {0};
+   struct exclusion_range *wifi_bands = wbrf_exclusion.band_list;
+   struct amdgpu_device *adev = smu->adev;
+   uint32_t num_of_wbrf_ranges = MAX_NUM_OF_WBRF_RANGES;
+   uint64_t start, end;
+   int ret, i, j;
+
+   ret = acpi_amd_wbrf_retrieve_exclusions(adev->dev, &wbrf_exclusion);
+   if (ret) {
+   dev_err(adev->dev, "Failed to retrieve exclusion ranges!\n");
+   return ret;
+   }
+
+   /*
+* The exclusion ranges array we got might be filled with holes and 
duplicate
+* entries. For example:
+* {(2400, 2500), (0, 0), (6882, 6962), (2400, 2500), (0, 0), (6117, 
6189), (0, 0)...}
+* We need to do some sortups to eliminate those holes and duplicate 
entries.
+* Expected output: {(2400, 2500), (6117, 6189), (6882, 6962), (0, 
0)...}
+*/
+   for (i = 0; i < num_of_wbrf_ranges; i++) {
+   start = wifi_bands[i].start;
+   end = wifi_bands[i].end;
+
+   /* get the last valid entry to fill the interm

Re: [PATCH 3/3] drm/mst: adjust the function drm_dp_remove_payload_part2()

[Imre Deak]

On Wed, Aug 23, 2023 at 03:16:44AM +, Lin, Wayne wrote:
> [AMD Official Use Only - General]
> 
> > -Original Message-
> > From: Imre Deak 
> > Sent: Saturday, August 19, 2023 1:46 AM
> > To: Lin, Wayne 
> > Cc: dri-de...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org;
> > ly...@redhat.com; jani.nik...@intel.com; ville.syrj...@linux.intel.com;
> > Wentland, Harry ; Zuo, Jerry
> > 
> > Subject: Re: [PATCH 3/3] drm/mst: adjust the function
> > drm_dp_remove_payload_part2()
> >
> > On Tue, Aug 08, 2023 at 03:47:47AM +, Lin, Wayne wrote:
> > > [AMD Official Use Only - General]
> > >
> > > > -Original Message-
> > > > From: Imre Deak 
> > > > Sent: Tuesday, August 8, 2023 12:00 AM
> > > > To: Lin, Wayne 
> > > > Cc: dri-de...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org;
> > > > ly...@redhat.com; jani.nik...@intel.com;
> > > > ville.syrj...@linux.intel.com; Wentland, Harry
> > > > ; Zuo, Jerry 
> > > > Subject: Re: [PATCH 3/3] drm/mst: adjust the function
> > > > drm_dp_remove_payload_part2()
> > > >
> > > > On Mon, Aug 07, 2023 at 02:43:02AM +, Lin, Wayne wrote:
> > > > > [AMD Official Use Only - General]
> > > > >
> > > > > > -Original Message-
> > > > > > From: Imre Deak 
> > > > > > Sent: Friday, August 4, 2023 11:32 PM
> > > > > > To: Lin, Wayne 
> > > > > > Cc: dri-de...@lists.freedesktop.org;
> > > > > > amd-gfx@lists.freedesktop.org; ly...@redhat.com;
> > > > > > jani.nik...@intel.com; ville.syrj...@linux.intel.com; Wentland,
> > > > > > Harry ; Zuo, Jerry 
> > > > > > Subject: Re: [PATCH 3/3] drm/mst: adjust the function
> > > > > > drm_dp_remove_payload_part2()
> > > > > >
> > > > > > On Fri, Aug 04, 2023 at 02:20:29PM +0800, Wayne Lin wrote:
> > > > > > > [...]
> > > > > > > diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c
> > > > > > > b/drivers/gpu/drm/display/drm_dp_mst_topology.c
> > > > > > > index e04f87ff755a..4270178f95f6 100644
> > > > > > > --- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
> > > > > > > +++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
> > > > > > > @@ -3382,8 +3382,7 @@
> > > > > > EXPORT_SYMBOL(drm_dp_remove_payload_part1);
> > > > > > >   * drm_dp_remove_payload_part2() - Remove an MST payload
> > locally
> > > > > > >   * @mgr: Manager to use.
> > > > > > >   * @mst_state: The MST atomic state
> > > > > > > - * @old_payload: The payload with its old state
> > > > > > > - * @new_payload: The payload with its latest state
> > > > > > > + * @payload: The payload with its latest state
> > > > > > >   *
> > > > > > >   * Updates the starting time slots of all other payloads
> > > > > > > which would have
> > > > > > been shifted towards
> > > > > > >   * the start of the payload ID table as a result of removing
> > > > > > > a payload. Driver should call this @@ -3392,25 +3391,36 @@
> > > > > > EXPORT_SYMBOL(drm_dp_remove_payload_part1);
> > > > > > >   */
> > > > > > >  void drm_dp_remove_payload_part2(struct
> > > > drm_dp_mst_topology_mgr
> > > > > > *mgr,
> > > > > > >  struct drm_dp_mst_topology_state
> > > > > > *mst_state,
> > > > > > > -const struct 
> > > > > > > drm_dp_mst_atomic_payload
> > > > > > *old_payload,
> > > > > > > -struct drm_dp_mst_atomic_payload
> > > > > > *new_payload)
> > > > > > > +struct drm_dp_mst_atomic_payload
> > > > > > *payload)
> > > > > > >  {
> > > > > > > struct drm_dp_mst_atomic_payload *pos;
> > > > > > > +   u8 time_slots_to_remove;
> > > > > > > +   u8 next_payload_vc_start = mgr->next_start_slot;
> > > > > > > +
> > > > > > > +   /* Find the current allocated time slot number of the payload 
> > > > > > > */
> > > > > > > +   list_for_each_entry(pos, &mst_state->payloads, next) {
> > > > > > > +   if (pos != payload &&
> > > > > > > +   pos->vc_start_slot > payload->vc_start_slot &&
> > > > > > > +   pos->vc_start_slot < next_payload_vc_start)
> > > > > > > +   next_payload_vc_start = pos->vc_start_slot;
> > > > > > > +   }
> > > > > > > +
> > > > > > > +   time_slots_to_remove = next_payload_vc_start -
> > > > > > > +payload->vc_start_slot;
> > > > > >
> > > > > > Imo, the intuitive way would be to pass the old payload state to
> > > > > > this function - which already contains the required time_slots
> > > > > > param
> > > > > > - and refactor things instead moving vc_start_slot from the
> > > > > > payload state to mgr suggested by Ville earlier.
> > > > > >
> > > > > > --Imre
> > > > >
> > > > > Hi Imre,
> > > > > Thanks for your feedback!
> > > > >
> > > > > I understand it's functionally correct. But IMHO, it's still a bit
> > > > > conceptually different between the time slot in old state and the
> > > > > time slot in current payload table. My thought is the time slot at
> > > > > the moment when we are removing the payload would be a better
> > choice.
> > > >
> > > > Yes, they are different. The o

RE: [PATCH 0/5] Add the pci_get_base_class() helper and use it

[Deucher, Alexander]

[Public]

> -Original Message-
> From: amd-gfx  On Behalf Of Sui
> Jingfeng
> Sent: Friday, August 25, 2023 2:27 AM
> To: Bjorn Helgaas 
> Cc: alsa-de...@alsa-project.org; Sui Jingfeng ;
> nouv...@lists.freedesktop.org; linux-ker...@vger.kernel.org; dri-
> de...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org; linux-
> p...@vger.kernel.org
> Subject: [PATCH 0/5] Add the pci_get_base_class() helper and use it
>
> From: Sui Jingfeng 
>
> There is no function that can be used to get all PCI(e) devices in a system by
> matching against its the PCI base class code only, while keep the sub-class 
> code
> and the programming interface ignored. Therefore, add the
> pci_get_base_class() function to suit the need.
>
> For example, if an application want to process all PCI(e) display devices in a
> system, it can achieve such goal by writing the code as following:
>
> pdev = NULL;
> do {
> pdev = pci_get_base_class(PCI_BASE_CLASS_DISPLAY, pdev);
> if (!pdev)
> break;
>
> do_something_for_pci_display_device(pdev);
> } while (1);
>
> Sui Jingfeng (5):
>   PCI: Add the pci_get_base_class() helper
>   ALSA: hda/intel: Use pci_get_base_class() to reduce duplicated code
>   drm/nouveau: Use pci_get_base_class() to reduce duplicated code
>   drm/amdgpu: Use pci_get_base_class() to reduce duplicated code
>   drm/radeon: Use pci_get_base_class() to reduce duplicated code
>

Series is:
Reviewed-by: Alex Deucher 

>  drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 11 +++--
> drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c | 20 ---
>  drivers/gpu/drm/nouveau/nouveau_acpi.c   | 11 +++--
>  drivers/gpu/drm/radeon/radeon_bios.c | 20 ---
>  drivers/pci/search.c | 31 
>  include/linux/pci.h  |  5 
>  sound/pci/hda/hda_intel.c| 16 
>  7 files changed, 59 insertions(+), 55 deletions(-)
>
> --
> 2.34.1

Re: [PATCH] drm/amd/pm: workaround for the wrong ac power detection on smu 13.0.0

[Alex Deucher]

On Fri, Aug 25, 2023 at 3:35 AM Kenneth Feng  wrote:
>
> workaround for the wrong ac power detection on smu 13.0.0

Is this to work around the bug in the power supply code for USB
controllers or something else?  If so that was already fixed upstream
so this is really more of a candidate for stable rather than -next.

Alex


>
> Signed-off-by: Kenneth Feng 
> ---
>  drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c   | 3 +--
>  drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 1 -
>  2 files changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c 
> b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
> index 0232adb95df3..fd1798fd716e 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
> @@ -1021,8 +1021,7 @@ static int smu_v13_0_process_pending_interrupt(struct 
> smu_context *smu)
>  {
> int ret = 0;
>
> -   if (smu->dc_controlled_by_gpio &&
> -   smu_cmn_feature_is_enabled(smu, SMU_FEATURE_ACDC_BIT))
> +   if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_ACDC_BIT))
> ret = smu_v13_0_allow_ih_interrupt(smu);
>
> return ret;
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c 
> b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
> index 3903a47669e4..128468355375 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
> @@ -2664,7 +2664,6 @@ static const struct pptable_funcs smu_v13_0_0_ppt_funcs 
> = {
> .enable_mgpu_fan_boost = smu_v13_0_0_enable_mgpu_fan_boost,
> .get_power_limit = smu_v13_0_0_get_power_limit,
> .set_power_limit = smu_v13_0_set_power_limit,
> -   .set_power_source = smu_v13_0_set_power_source,
> .get_power_profile_mode = smu_v13_0_0_get_power_profile_mode,
> .set_power_profile_mode = smu_v13_0_0_set_power_profile_mode,
> .run_btc = smu_v13_0_run_btc,
> --
> 2.34.1
>

[PATCH 0/5] Add the pci_get_base_class() helper and use it

[Sui Jingfeng]

From: Sui Jingfeng 

There is no function that can be used to get all PCI(e) devices in a
system by matching against its the PCI base class code only, while keep
the sub-class code and the programming interface ignored. Therefore, add
the pci_get_base_class() function to suit the need.

For example, if an application want to process all PCI(e) display devices
in a system, it can achieve such goal by writing the code as following:

pdev = NULL;
do {
pdev = pci_get_base_class(PCI_BASE_CLASS_DISPLAY, pdev);
if (!pdev)
break;

do_something_for_pci_display_device(pdev);
} while (1);

Sui Jingfeng (5):
  PCI: Add the pci_get_base_class() helper
  ALSA: hda/intel: Use pci_get_base_class() to reduce duplicated code
  drm/nouveau: Use pci_get_base_class() to reduce duplicated code
  drm/amdgpu: Use pci_get_base_class() to reduce duplicated code
  drm/radeon: Use pci_get_base_class() to reduce duplicated code

 drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 11 +++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c | 20 ---
 drivers/gpu/drm/nouveau/nouveau_acpi.c   | 11 +++--
 drivers/gpu/drm/radeon/radeon_bios.c | 20 ---
 drivers/pci/search.c | 31 
 include/linux/pci.h  |  5 
 sound/pci/hda/hda_intel.c| 16 
 7 files changed, 59 insertions(+), 55 deletions(-)

-- 
2.34.1

[PATCH 4/5] drm/amdgpu: Use pci_get_base_class() to reduce duplicated code

[Sui Jingfeng]

From: Sui Jingfeng 

Should be no functional change.

Cc: Alex Deucher 
Signed-off-by: Sui Jingfeng 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 11 ---
 drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c | 20 +---
 2 files changed, 9 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
index a5a2b06c6588..4f18af877105 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
@@ -1389,14 +1389,11 @@ void amdgpu_acpi_detect(void)
struct pci_dev *pdev = NULL;
int ret;
 
-   while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != 
NULL) {
-   if (!atif->handle)
-   amdgpu_atif_pci_probe_handle(pdev);
-   if (!atcs->handle)
-   amdgpu_atcs_pci_probe_handle(pdev);
-   }
+   while ((pdev = pci_get_base_class(PCI_BASE_CLASS_DISPLAY, pdev))) {
+   if ((pdev->class != PCI_CLASS_DISPLAY_VGA << 8) &&
+   (pdev->class != PCI_CLASS_DISPLAY_OTHER << 8))
+   continue;
 
-   while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != 
NULL) {
if (!atif->handle)
amdgpu_atif_pci_probe_handle(pdev);
if (!atcs->handle)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
index 38ccec913f00..5bbb23e102ba 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
@@ -287,7 +287,11 @@ static bool amdgpu_atrm_get_bios(struct amdgpu_device 
*adev)
if (adev->flags & AMD_IS_APU)
return false;
 
-   while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != 
NULL) {
+   while ((pdev = pci_get_base_class(PCI_BASE_CLASS_DISPLAY, pdev))) {
+   if ((pdev->class != PCI_CLASS_DISPLAY_VGA << 8) &&
+   (pdev->class != PCI_CLASS_DISPLAY_OTHER << 8))
+   continue;
+
dhandle = ACPI_HANDLE(&pdev->dev);
if (!dhandle)
continue;
@@ -299,20 +303,6 @@ static bool amdgpu_atrm_get_bios(struct amdgpu_device 
*adev)
}
}
 
-   if (!found) {
-   while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, 
pdev)) != NULL) {
-   dhandle = ACPI_HANDLE(&pdev->dev);
-   if (!dhandle)
-   continue;
-
-   status = acpi_get_handle(dhandle, "ATRM", &atrm_handle);
-   if (ACPI_SUCCESS(status)) {
-   found = true;
-   break;
-   }
-   }
-   }
-
if (!found)
return false;
pci_dev_put(pdev);
-- 
2.34.1

[PATCH 1/5] PCI: Add the pci_get_base_class() helper

[Sui Jingfeng]

From: Sui Jingfeng 

There is no function that can be used to get all PCI(e) devices in a
system by matching against its the PCI base class code only, while keep
the sub-class code and the programming interface ignored. Therefore, add
the pci_get_base_class() function to suit the need.

For example, if an application want to process all PCI(e) display devices
in a system, it can achieve such goal by writing the code as following:

pdev = NULL;
do {
pdev = pci_get_base_class(PCI_BASE_CLASS_DISPLAY, pdev);
if (!pdev)
break;

do_something_for_pci_display_device(pdev);
} while (1);

Cc: Bjorn Helgaas 
Signed-off-by: Sui Jingfeng 
---
 drivers/pci/search.c | 31 +++
 include/linux/pci.h  |  5 +
 2 files changed, 36 insertions(+)

diff --git a/drivers/pci/search.c b/drivers/pci/search.c
index b4c138a6ec02..53840634fbfc 100644
--- a/drivers/pci/search.c
+++ b/drivers/pci/search.c
@@ -363,6 +363,37 @@ struct pci_dev *pci_get_class(unsigned int class, struct 
pci_dev *from)
 }
 EXPORT_SYMBOL(pci_get_class);
 
+/**
+ * pci_get_base_class - searching for a PCI device by matching against the 
base class code only
+ * @class: search for a PCI device with this base class code
+ * @from: Previous PCI device found in search, or %NULL for new search.
+ *
+ * Iterates through the list of known PCI devices. If a PCI device is found
+ * with a matching base class code, the reference count to the device is
+ * incremented. See pci_match_one_device() to figure out how does this works.
+ * A new search is initiated by passing %NULL as the @from argument.
+ * Otherwise if @from is not %NULL, searches continue from next device on the
+ * global list. The reference count for @from is always decremented if it is
+ * not %NULL.
+ *
+ * Returns:
+ * A pointer to a matched PCI device, %NULL Otherwise.
+ */
+struct pci_dev *pci_get_base_class(unsigned int class, struct pci_dev *from)
+{
+   struct pci_device_id id = {
+   .vendor = PCI_ANY_ID,
+   .device = PCI_ANY_ID,
+   .subvendor = PCI_ANY_ID,
+   .subdevice = PCI_ANY_ID,
+   .class_mask = 0xFF,
+   .class = class << 16,
+   };
+
+   return pci_get_dev_by_id(&id, from);
+}
+EXPORT_SYMBOL(pci_get_base_class);
+
 /**
  * pci_dev_present - Returns 1 if device matching the device list is present, 
0 if not.
  * @ids: A pointer to a null terminated list of struct pci_device_id structures
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 71c85380676c..486ad959e1f9 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -1180,6 +1180,8 @@ struct pci_dev *pci_get_slot(struct pci_bus *bus, 
unsigned int devfn);
 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
unsigned int devfn);
 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
+struct pci_dev *pci_get_base_class(unsigned int class, struct pci_dev *from);
+
 int pci_dev_present(const struct pci_device_id *ids);
 
 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
@@ -1896,6 +1898,9 @@ static inline struct pci_dev *pci_get_class(unsigned int 
class,
struct pci_dev *from)
 { return NULL; }
 
+static inline struct pci_dev *pci_get_base_class(unsigned int class,
+struct pci_dev *from)
+{ return NULL; }
 
 static inline int pci_dev_present(const struct pci_device_id *ids)
 { return 0; }
-- 
2.34.1

[PATCH 2/5] ALSA: hda/intel: Use pci_get_base_class() to reduce duplicated code

[Sui Jingfeng]

From: Sui Jingfeng 

Should be no functional change

Cc: Jaroslav Kysela 
Cc: Takashi Iwai 
Cc: Fred Oh 
Cc: Pierre-Louis Bossart 
Cc: Kai Vehmanen 
Cc: Bjorn Helgaas 
Signed-off-by: Sui Jingfeng 
---
 sound/pci/hda/hda_intel.c | 16 +---
 1 file changed, 5 insertions(+), 11 deletions(-)

diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c
index a21b61ad08d1..811a149584f2 100644
--- a/sound/pci/hda/hda_intel.c
+++ b/sound/pci/hda/hda_intel.c
@@ -1429,17 +1429,11 @@ static bool atpx_present(void)
acpi_handle dhandle, atpx_handle;
acpi_status status;
 
-   while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != 
NULL) {
-   dhandle = ACPI_HANDLE(&pdev->dev);
-   if (dhandle) {
-   status = acpi_get_handle(dhandle, "ATPX", &atpx_handle);
-   if (ACPI_SUCCESS(status)) {
-   pci_dev_put(pdev);
-   return true;
-   }
-   }
-   }
-   while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != 
NULL) {
+   while ((pdev = pci_get_base_class(PCI_BASE_CLASS_DISPLAY, pdev))) {
+   if ((pdev->class != PCI_CLASS_DISPLAY_VGA << 8) &&
+   (pdev->class != PCI_CLASS_DISPLAY_OTHER << 8))
+   continue;
+
dhandle = ACPI_HANDLE(&pdev->dev);
if (dhandle) {
status = acpi_get_handle(dhandle, "ATPX", &atpx_handle);
-- 
2.34.1

[PATCH 3/5] drm/nouveau: Use pci_get_base_class() to reduce duplicated code

[Sui Jingfeng]

From: Sui Jingfeng 

Should be no functional change.

Cc: Ben Skeggs 
Cc: Karol Herbst 
Cc: Lyude Paul 
Cc: David Airlie 
Cc: Daniel Vetter 
Signed-off-by: Sui Jingfeng 
---
 drivers/gpu/drm/nouveau/nouveau_acpi.c | 11 ---
 1 file changed, 4 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/nouveau/nouveau_acpi.c 
b/drivers/gpu/drm/nouveau/nouveau_acpi.c
index a2ae8c21e4dc..8f0c69aad248 100644
--- a/drivers/gpu/drm/nouveau/nouveau_acpi.c
+++ b/drivers/gpu/drm/nouveau/nouveau_acpi.c
@@ -284,14 +284,11 @@ static bool nouveau_dsm_detect(void)
printk("MXM: GUID detected in BIOS\n");
 
/* now do DSM detection */
-   while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != 
NULL) {
-   vga_count++;
-
-   nouveau_dsm_pci_probe(pdev, &dhandle, &has_mux, &has_optimus,
- &has_optimus_flags, &has_power_resources);
-   }
+   while ((pdev = pci_get_base_class(PCI_BASE_CLASS_DISPLAY, pdev))) {
+   if ((pdev->class != PCI_CLASS_DISPLAY_VGA << 8) &&
+   (pdev->class != PCI_CLASS_DISPLAY_3D << 8))
+   continue;
 
-   while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_3D << 8, pdev)) != NULL) 
{
vga_count++;
 
nouveau_dsm_pci_probe(pdev, &dhandle, &has_mux, &has_optimus,
-- 
2.34.1

[PATCH 5/5] drm/radeon: Use pci_get_base_class() to reduce duplicated code

[Sui Jingfeng]

From: Sui Jingfeng 

Should be no functional change.

Cc: Alex Deucher 
Signed-off-by: Sui Jingfeng 
---
 drivers/gpu/drm/radeon/radeon_bios.c | 20 +---
 1 file changed, 5 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/radeon/radeon_bios.c 
b/drivers/gpu/drm/radeon/radeon_bios.c
index 63bdc9f6fc24..3a8c5199a0fe 100644
--- a/drivers/gpu/drm/radeon/radeon_bios.c
+++ b/drivers/gpu/drm/radeon/radeon_bios.c
@@ -199,7 +199,11 @@ static bool radeon_atrm_get_bios(struct radeon_device 
*rdev)
if (rdev->flags & RADEON_IS_IGP)
return false;
 
-   while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != 
NULL) {
+   while ((pdev = pci_get_base_class(PCI_BASE_CLASS_DISPLAY, pdev))) {
+   if ((pdev->class != PCI_CLASS_DISPLAY_VGA << 8) &&
+   (pdev->class != PCI_CLASS_DISPLAY_OTHER << 8))
+   continue;
+
dhandle = ACPI_HANDLE(&pdev->dev);
if (!dhandle)
continue;
@@ -211,20 +215,6 @@ static bool radeon_atrm_get_bios(struct radeon_device 
*rdev)
}
}
 
-   if (!found) {
-   while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, 
pdev)) != NULL) {
-   dhandle = ACPI_HANDLE(&pdev->dev);
-   if (!dhandle)
-   continue;
-
-   status = acpi_get_handle(dhandle, "ATRM", &atrm_handle);
-   if (ACPI_SUCCESS(status)) {
-   found = true;
-   break;
-   }
-   }
-   }
-
if (!found)
return false;
pci_dev_put(pdev);
-- 
2.34.1

Re: [V2 3/8] drm/amd/pm: add fan mode OD setting support for SMU13

[Alex Deucher]

On Thu, Aug 24, 2023 at 10:02 PM Quan, Evan  wrote:
>
> [AMD Official Use Only - General]
>
> > -Original Message-
> > From: Alex Deucher 
> > Sent: Thursday, August 24, 2023 10:51 PM
> > To: Quan, Evan 
> > Cc: amd-gfx@lists.freedesktop.org; Deucher, Alexander
> > 
> > Subject: Re: [V2 3/8] drm/amd/pm: add fan mode OD setting support for
> > SMU13
> >
> > On Wed, Aug 23, 2023 at 10:28 PM Quan, Evan 
> > wrote:
> > >
> > > [AMD Official Use Only - General]
> > >
> > > > -Original Message-
> > > > From: Alex Deucher 
> > > > Sent: Wednesday, August 23, 2023 9:29 PM
> > > > To: Quan, Evan 
> > > > Cc: amd-gfx@lists.freedesktop.org; Deucher, Alexander
> > > > 
> > > > Subject: Re: [V2 3/8] drm/amd/pm: add fan mode OD setting support
> > > > for
> > > > SMU13
> > > >
> > > > On Wed, Aug 23, 2023 at 2:45 AM Evan Quan 
> > > > wrote:
> > > > >
> > > > > Add SMU13 fan mode OD setting support.
> > > > >
> > > > > Signed-off-by: Evan Quan 
> > > > > --
> > > > > v1->v2:
> > > > >   - add missing kerneldoc for the new interface(Alex)
> > > > > ---
> > > > >  Documentation/gpu/amdgpu/thermal.rst  |   6 +
> > > > >  .../gpu/drm/amd/include/kgd_pp_interface.h|   4 +-
> > > > >  drivers/gpu/drm/amd/pm/amdgpu_pm.c| 200
> > > > +-
> > > > >  drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h   |   4 +
> > > > >  drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c |   2 +
> > > > >  drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h  |   1 +
> > > > >  .../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c  |  35 ++-
> > > > > .../drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c  |  35 ++-
> > > > >  8 files changed, 279 insertions(+), 8 deletions(-)
> > > > >
> > > > > diff --git a/Documentation/gpu/amdgpu/thermal.rst
> > > > > b/Documentation/gpu/amdgpu/thermal.rst
> > > > > index 5e27e4eb3959..8757ec7f0136 100644
> > > > > --- a/Documentation/gpu/amdgpu/thermal.rst
> > > > > +++ b/Documentation/gpu/amdgpu/thermal.rst
> > > > > @@ -64,6 +64,12 @@ gpu_metrics
> > > > >  .. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
> > > > > :doc: gpu_metrics
> > > > >
> > > > > +fan_mode
> > > > > +
> > > > > +
> > > > > +.. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
> > > > > +   :doc: fan_mode
> > > > > +
> > > > >  GFXOFF
> > > > >  ==
> > > > >
> > > > > diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> > > > > b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> > > > > index 84c5224d994c..020c9ce1f735 100644
> > > > > --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> > > > > +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> > > > > @@ -113,6 +113,7 @@ enum pp_clock_type {
> > > > > OD_RANGE,
> > > > > OD_VDDGFX_OFFSET,
> > > > > OD_CCLK,
> > > > > +   OD_FAN_MODE,
> > > > >  };
> > > > >
> > > > >  enum amd_pp_sensors {
> > > > > @@ -186,7 +187,8 @@ enum PP_OD_DPM_TABLE_COMMAND {
> > > > > PP_OD_EDIT_VDDC_CURVE,
> > > > > PP_OD_RESTORE_DEFAULT_TABLE,
> > > > > PP_OD_COMMIT_DPM_TABLE,
> > > > > -   PP_OD_EDIT_VDDGFX_OFFSET
> > > > > +   PP_OD_EDIT_VDDGFX_OFFSET,
> > > > > +   PP_OD_EDIT_FAN_MODE,
> > > > >  };
> > > > >
> > > > >  struct pp_states_info {
> > > > > diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> > > > > b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> > > > > index beb3303fc832..d53d60903fe9 100644
> > > > > --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> > > > > +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> > > > > @@ -3383,7 +3383,205 @@ static const struct attribute_group
> > > > *hwmon_groups[] = {
> > > > > NULL
> > > > >  };
> > > > >
> > > > > -static struct od_feature_set amdgpu_od_set;
> > > > > +static int amdgpu_retrieve_od_settings(struct amdgpu_device *adev,
> > > > > +  enum pp_clock_type od_type,
> > > > > +  char *buf) {
> > > > > +   int size = 0;
> > > > > +   int ret;
> > > > > +
> > > > > +   if (amdgpu_in_reset(adev))
> > > > > +   return -EPERM;
> > > > > +   if (adev->in_suspend && !adev->in_runpm)
> > > > > +   return -EPERM;
> > > > > +
> > > > > +   ret = pm_runtime_get_sync(adev->dev);
> > > > > +   if (ret < 0) {
> > > > > +   pm_runtime_put_autosuspend(adev->dev);
> > > > > +   return ret;
> > > > > +   }
> > > > > +
> > > > > +   size = amdgpu_dpm_print_clock_levels(adev, od_type, buf);
> > > > > +   if (size == 0)
> > > > > +   size = sysfs_emit(buf, "\n");
> > > > > +
> > > > > +   pm_runtime_mark_last_busy(adev->dev);
> > > > > +   pm_runtime_put_autosuspend(adev->dev);
> > > > > +
> > > > > +   return size;
> > > > > +}
> > > > > +
> > > > > +static int parse_input_od_command_lines(const char *buf,
> > > > > +   size_t count,
> > > > > +   u32 *type,
> > > > > +   long *params,
> > 

Re: [PATCH 1/2] drm/amdgpu: Merge debug module parameters

[Christian König]

Am 25.08.23 um 14:34 schrieb André Almeida:

Em 25/08/2023 09:29, Christian König escreveu:

Am 25.08.23 um 14:24 schrieb André Almeida:

Em 25/08/2023 03:56, Christian König escreveu:
> Am 24.08.23 um 18:25 schrieb André Almeida:
>> Merge all developer debug options available as separated module
>> parameters in one, making it obvious that are for developers.
>>
>> Signed-off-by: André Almeida 
>> ---
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c  | 24 


>>   drivers/gpu/drm/amd/include/amd_shared.h |  9 +
>>   2 files changed, 33 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>> index f5856b82605e..d53e4097acc0 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>> @@ -194,6 +194,7 @@ int amdgpu_use_xgmi_p2p = 1;
>>   int amdgpu_vcnfw_log;
>>   int amdgpu_sg_display = -1; /* auto */
>>   int amdgpu_user_partt_mode = AMDGPU_AUTO_COMPUTE_PARTITION_MODE;
>> +uint amdgpu_debug_mask;
>>   static void amdgpu_drv_delayed_reset_work_handler(struct 
work_struct

>> *work);
>> @@ -938,6 +939,9 @@ module_param_named(user_partt_mode,
>> amdgpu_user_partt_mode, uint, 0444);
>>   module_param(enforce_isolation, bool, 0444);
>>   MODULE_PARM_DESC(enforce_isolation, "enforce process isolation
>> between graphics and compute . enforce_isolation = on");
>> +MODULE_PARM_DESC(debug_mask, "debug options for amdgpu, disabled by
>> default");
>> +module_param_named(debug_mask, amdgpu_debug_mask, uint, 0444);
>> +
>>   /* These devices are not supported by amdgpu.
>>    * They are supported by the mach64, r128, radeon drivers
>>    */
>> @@ -2871,6 +2875,24 @@ static struct pci_driver 
amdgpu_kms_pci_driver = {

>>   .dev_groups = amdgpu_sysfs_groups,
>>   };
>> +static void amdgpu_init_debug_options(void)
>> +{
>> +    if (amdgpu_debug_mask & DEBUG_VERBOSE_EVICTIONS) {
>> +    pr_info("debug: eviction debug messages enabled\n");
>> +    debug_evictions = true;
>> +    }
>> +
>> +    if (amdgpu_debug_mask & DEBUG_VM) {
>> +    pr_info("debug: VM handling debug enabled\n");
>> +    amdgpu_vm_debug = true;
>> +    }
>> +
>> +    if (amdgpu_debug_mask & DEBUG_LARGEBAR) {
>> +    pr_info("debug: enabled simulating large-bar capability on
>> non-large bar system\n");
>> +    debug_largebar = true;
>
> How should that work???

Ops, I thought it was a boolean. It should be

+    debug_largebar = 1;



That's not the problem, the question is since when do we have a 
debug_largebar option and what should that one do?




It should work exactly like the other one, but instead of using 
amdgpu.large_bar=1, one would use amdgpu.debug_mask=0x4 to activate 
it, as the plan is to merge all current debug options in a single one 
right?


Ah! That's the KFD debug_largebar option! Now I got what this is.

Probably best to move the booleans into amdgpu_device and deprecate the 
old options.


Not really a good approach to overwrite the globals here.

Regards,
Christian.




Regards,
Christian.

Re: [PATCH 1/2] drm/amdgpu: Merge debug module parameters

[André Almeida]

Em 25/08/2023 09:29, Christian König escreveu:

Am 25.08.23 um 14:24 schrieb André Almeida:

Em 25/08/2023 03:56, Christian König escreveu:
> Am 24.08.23 um 18:25 schrieb André Almeida:
>> Merge all developer debug options available as separated module
>> parameters in one, making it obvious that are for developers.
>>
>> Signed-off-by: André Almeida 
>> ---
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c  | 24 


>>   drivers/gpu/drm/amd/include/amd_shared.h |  9 +
>>   2 files changed, 33 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>> index f5856b82605e..d53e4097acc0 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>> @@ -194,6 +194,7 @@ int amdgpu_use_xgmi_p2p = 1;
>>   int amdgpu_vcnfw_log;
>>   int amdgpu_sg_display = -1; /* auto */
>>   int amdgpu_user_partt_mode = AMDGPU_AUTO_COMPUTE_PARTITION_MODE;
>> +uint amdgpu_debug_mask;
>>   static void amdgpu_drv_delayed_reset_work_handler(struct work_struct
>> *work);
>> @@ -938,6 +939,9 @@ module_param_named(user_partt_mode,
>> amdgpu_user_partt_mode, uint, 0444);
>>   module_param(enforce_isolation, bool, 0444);
>>   MODULE_PARM_DESC(enforce_isolation, "enforce process isolation
>> between graphics and compute . enforce_isolation = on");
>> +MODULE_PARM_DESC(debug_mask, "debug options for amdgpu, disabled by
>> default");
>> +module_param_named(debug_mask, amdgpu_debug_mask, uint, 0444);
>> +
>>   /* These devices are not supported by amdgpu.
>>    * They are supported by the mach64, r128, radeon drivers
>>    */
>> @@ -2871,6 +2875,24 @@ static struct pci_driver 
amdgpu_kms_pci_driver = {

>>   .dev_groups = amdgpu_sysfs_groups,
>>   };
>> +static void amdgpu_init_debug_options(void)
>> +{
>> +    if (amdgpu_debug_mask & DEBUG_VERBOSE_EVICTIONS) {
>> +    pr_info("debug: eviction debug messages enabled\n");
>> +    debug_evictions = true;
>> +    }
>> +
>> +    if (amdgpu_debug_mask & DEBUG_VM) {
>> +    pr_info("debug: VM handling debug enabled\n");
>> +    amdgpu_vm_debug = true;
>> +    }
>> +
>> +    if (amdgpu_debug_mask & DEBUG_LARGEBAR) {
>> +    pr_info("debug: enabled simulating large-bar capability on
>> non-large bar system\n");
>> +    debug_largebar = true;
>
> How should that work???

Ops, I thought it was a boolean. It should be

+    debug_largebar = 1;



That's not the problem, the question is since when do we have a 
debug_largebar option and what should that one do?




It should work exactly like the other one, but instead of using 
amdgpu.large_bar=1, one would use amdgpu.debug_mask=0x4 to activate it, 
as the plan is to merge all current debug options in a single one right?



Regards,
Christian.

Re: [PATCH 1/2] drm/amdgpu: Merge debug module parameters

[Christian König]

Am 25.08.23 um 14:24 schrieb André Almeida:

Em 25/08/2023 03:56, Christian König escreveu:
> Am 24.08.23 um 18:25 schrieb André Almeida:
>> Merge all developer debug options available as separated module
>> parameters in one, making it obvious that are for developers.
>>
>> Signed-off-by: André Almeida 
>> ---
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c  | 24 


>>   drivers/gpu/drm/amd/include/amd_shared.h |  9 +
>>   2 files changed, 33 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>> index f5856b82605e..d53e4097acc0 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>> @@ -194,6 +194,7 @@ int amdgpu_use_xgmi_p2p = 1;
>>   int amdgpu_vcnfw_log;
>>   int amdgpu_sg_display = -1; /* auto */
>>   int amdgpu_user_partt_mode = AMDGPU_AUTO_COMPUTE_PARTITION_MODE;
>> +uint amdgpu_debug_mask;
>>   static void amdgpu_drv_delayed_reset_work_handler(struct work_struct
>> *work);
>> @@ -938,6 +939,9 @@ module_param_named(user_partt_mode,
>> amdgpu_user_partt_mode, uint, 0444);
>>   module_param(enforce_isolation, bool, 0444);
>>   MODULE_PARM_DESC(enforce_isolation, "enforce process isolation
>> between graphics and compute . enforce_isolation = on");
>> +MODULE_PARM_DESC(debug_mask, "debug options for amdgpu, disabled by
>> default");
>> +module_param_named(debug_mask, amdgpu_debug_mask, uint, 0444);
>> +
>>   /* These devices are not supported by amdgpu.
>>    * They are supported by the mach64, r128, radeon drivers
>>    */
>> @@ -2871,6 +2875,24 @@ static struct pci_driver 
amdgpu_kms_pci_driver = {

>>   .dev_groups = amdgpu_sysfs_groups,
>>   };
>> +static void amdgpu_init_debug_options(void)
>> +{
>> +    if (amdgpu_debug_mask & DEBUG_VERBOSE_EVICTIONS) {
>> +    pr_info("debug: eviction debug messages enabled\n");
>> +    debug_evictions = true;
>> +    }
>> +
>> +    if (amdgpu_debug_mask & DEBUG_VM) {
>> +    pr_info("debug: VM handling debug enabled\n");
>> +    amdgpu_vm_debug = true;
>> +    }
>> +
>> +    if (amdgpu_debug_mask & DEBUG_LARGEBAR) {
>> +    pr_info("debug: enabled simulating large-bar capability on
>> non-large bar system\n");
>> +    debug_largebar = true;
>
> How should that work???

Ops, I thought it was a boolean. It should be

+    debug_largebar = 1;



That's not the problem, the question is since when do we have a 
debug_largebar option and what should that one do?


Regards,
Christian.



>
>> +    }
>> +}
>> +
>>   static int __init amdgpu_init(void)
>>   {
>>   int r;
>> @@ -2893,6 +2915,8 @@ static int __init amdgpu_init(void)
>>   /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not
>> set. */
>>   amdgpu_amdkfd_init();
>> +    amdgpu_init_debug_options();
>> +
>>   /* let modprobe override vga console setting */
>>   return pci_register_driver(&amdgpu_kms_pci_driver);
>> diff --git a/drivers/gpu/drm/amd/include/amd_shared.h
>> b/drivers/gpu/drm/amd/include/amd_shared.h
>> index 67d7b7ee8a2a..6fa644c249a5 100644
>> --- a/drivers/gpu/drm/amd/include/amd_shared.h
>> +++ b/drivers/gpu/drm/amd/include/amd_shared.h
>> @@ -257,6 +257,15 @@ enum DC_DEBUG_MASK {
>>   enum amd_dpm_forced_level;
>> +/*
>> + * amdgpu.debug module options. Are all disabled by default
>> + */
>> +enum AMDGPU_DEBUG_MASK {
>> +    DEBUG_VERBOSE_EVICTIONS = (1 << 0),    // 0x1
>> +    DEBUG_VM = (1 << 1),    // 0x2
>> +    DEBUG_LARGEBAR = (1 << 2),    // 0x4
>
> Good start, but please give the symbol names an AMDGPU_ prefix. Stuff
> like DEBUG_VM is just way to general and could clash.
>
> Apart from that comments on the same line and using // style comments
> are frowned upon. You should probably rather use the BIT() macro here.
>

Ack, I'll change that for next version

> Regards,
> Christian.
>
>> +
>>   /**
>>    * struct amd_ip_funcs - general hooks for managing amdgpu IP Blocks
>>    * @name: Name of IP block
>
>

Re: [PATCH 1/2] drm/amdgpu: Merge debug module parameters

[André Almeida]

Em 25/08/2023 03:56, Christian König escreveu:
> Am 24.08.23 um 18:25 schrieb André Almeida:
>> Merge all developer debug options available as separated module
>> parameters in one, making it obvious that are for developers.
>>
>> Signed-off-by: André Almeida 
>> ---
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c  | 24 
>>   drivers/gpu/drm/amd/include/amd_shared.h |  9 +
>>   2 files changed, 33 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>> index f5856b82605e..d53e4097acc0 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>> @@ -194,6 +194,7 @@ int amdgpu_use_xgmi_p2p = 1;
>>   int amdgpu_vcnfw_log;
>>   int amdgpu_sg_display = -1; /* auto */
>>   int amdgpu_user_partt_mode = AMDGPU_AUTO_COMPUTE_PARTITION_MODE;
>> +uint amdgpu_debug_mask;
>>   static void amdgpu_drv_delayed_reset_work_handler(struct work_struct
>> *work);
>> @@ -938,6 +939,9 @@ module_param_named(user_partt_mode,
>> amdgpu_user_partt_mode, uint, 0444);
>>   module_param(enforce_isolation, bool, 0444);
>>   MODULE_PARM_DESC(enforce_isolation, "enforce process isolation
>> between graphics and compute . enforce_isolation = on");
>> +MODULE_PARM_DESC(debug_mask, "debug options for amdgpu, disabled by
>> default");
>> +module_param_named(debug_mask, amdgpu_debug_mask, uint, 0444);
>> +
>>   /* These devices are not supported by amdgpu.
>>* They are supported by the mach64, r128, radeon drivers
>>*/
>> @@ -2871,6 +2875,24 @@ static struct pci_driver 
amdgpu_kms_pci_driver = {

>>   .dev_groups = amdgpu_sysfs_groups,
>>   };
>> +static void amdgpu_init_debug_options(void)
>> +{
>> +if (amdgpu_debug_mask & DEBUG_VERBOSE_EVICTIONS) {
>> +pr_info("debug: eviction debug messages enabled\n");
>> +debug_evictions = true;
>> +}
>> +
>> +if (amdgpu_debug_mask & DEBUG_VM) {
>> +pr_info("debug: VM handling debug enabled\n");
>> +amdgpu_vm_debug = true;
>> +}
>> +
>> +if (amdgpu_debug_mask & DEBUG_LARGEBAR) {
>> +pr_info("debug: enabled simulating large-bar capability on
>> non-large bar system\n");
>> +debug_largebar = true;
>
> How should that work???

Ops, I thought it was a boolean. It should be

+debug_largebar = 1;

>
>> +}
>> +}
>> +
>>   static int __init amdgpu_init(void)
>>   {
>>   int r;
>> @@ -2893,6 +2915,8 @@ static int __init amdgpu_init(void)
>>   /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not
>> set. */
>>   amdgpu_amdkfd_init();
>> +amdgpu_init_debug_options();
>> +
>>   /* let modprobe override vga console setting */
>>   return pci_register_driver(&amdgpu_kms_pci_driver);
>> diff --git a/drivers/gpu/drm/amd/include/amd_shared.h
>> b/drivers/gpu/drm/amd/include/amd_shared.h
>> index 67d7b7ee8a2a..6fa644c249a5 100644
>> --- a/drivers/gpu/drm/amd/include/amd_shared.h
>> +++ b/drivers/gpu/drm/amd/include/amd_shared.h
>> @@ -257,6 +257,15 @@ enum DC_DEBUG_MASK {
>>   enum amd_dpm_forced_level;
>> +/*
>> + * amdgpu.debug module options. Are all disabled by default
>> + */
>> +enum AMDGPU_DEBUG_MASK {
>> +DEBUG_VERBOSE_EVICTIONS = (1 << 0),// 0x1
>> +DEBUG_VM = (1 << 1),// 0x2
>> +DEBUG_LARGEBAR = (1 << 2),// 0x4
>
> Good start, but please give the symbol names an AMDGPU_ prefix. Stuff
> like DEBUG_VM is just way to general and could clash.
>
> Apart from that comments on the same line and using // style comments
> are frowned upon. You should probably rather use the BIT() macro here.
>

Ack, I'll change that for next version

> Regards,
> Christian.
>
>> +
>>   /**
>>* struct amd_ip_funcs - general hooks for managing amdgpu IP Blocks
>>* @name: Name of IP block
>
>

RE: [PATCH] drm/amdgpu: Add only valid firmware version nodes

[Kamal, Asad]

[AMD Official Use Only - General]

Reviewed-by: Asad Kamal asad.ka...@amd.com

Thanks & Regards
Asad

From: amd-gfx  On Behalf Of Wang, 
Yang(Kevin)
Sent: Friday, August 25, 2023 4:46 PM
To: amd-gfx@lists.freedesktop.org; Lazar, Lijo 
Cc: Deucher, Alexander ; Zhang, Hawking 

Subject: Re: [PATCH] drm/amdgpu: Add only valid firmware version nodes


[AMD Official Use Only - General]


[AMD Official Use Only - General]

Reviewed-by: Yang Wang mailto:kevinyang.w...@amd.com>>

Best Regards,
Kevin

发件人: amd-gfx 
mailto:amd-gfx-boun...@lists.freedesktop.org>>
 代表 Lijo Lazar mailto:lijo.la...@amd.com>>
发送时间: 星期五, 八月 25, 2023 17:29
收件人: amd-gfx@lists.freedesktop.org 
mailto:amd-gfx@lists.freedesktop.org>>
抄送: Deucher, Alexander 
mailto:alexander.deuc...@amd.com>>; Zhang, Hawking 
mailto:hawking.zh...@amd.com>>
主题: [PATCH] drm/amdgpu: Add only valid firmware version nodes

Show only firmware version attributes that have valid version. Hide
others.

Signed-off-by: Lijo Lazar mailto:lijo.la...@amd.com>>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 33 ---
 1 file changed, 29 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index 8beefc045e14..b0b37c056c36 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -669,15 +669,25 @@ const char *amdgpu_ucode_name(enum AMDGPU_UCODE_ID 
ucode_id)
 }
 }

+static inline int amdgpu_ucode_is_valid(uint32_t fw_version)
+{
+   if (!fw_version)
+   return -EINVAL;
+
+   return 0;
+}
+
 #define FW_VERSION_ATTR(name, mode, field)  \
 static ssize_t show_##name(struct device *dev,  \
- struct device_attribute *attr, \
- char *buf) \
+  struct device_attribute *attr, char *buf) \
 {   \
 struct drm_device *ddev = dev_get_drvdata(dev); \
 struct amdgpu_device *adev = drm_to_adev(ddev); \
 \
-   return sysfs_emit(buf, "0x%08x\n", adev->field);\
+   if (!buf)   \
+   return amdgpu_ucode_is_valid(adev->field);  \
+   \
+   return sysfs_emit(buf, "0x%08x\n", adev->field);\
 }   \
 static DEVICE_ATTR(name, mode, show_##name, NULL)

@@ -722,9 +732,24 @@ static struct attribute *fw_attrs[] = {
 NULL
 };

+#define to_dev_attr(x) container_of(x, struct device_attribute, attr)
+
+static umode_t amdgpu_ucode_sys_visible(struct kobject *kobj,
+   struct attribute *attr, int idx)
+{
+   struct device_attribute *dev_attr = to_dev_attr(attr);
+   struct device *dev = kobj_to_dev(kobj);
+
+   if (dev_attr->show(dev, dev_attr, NULL) == -EINVAL)
+   return 0;
+
+   return attr->mode;
+}
+
 static const struct attribute_group fw_attr_group = {
 .name = "fw_version",
-   .attrs = fw_attrs
+   .attrs = fw_attrs,
+   .is_visible = amdgpu_ucode_sys_visible
 };

 int amdgpu_ucode_sysfs_init(struct amdgpu_device *adev)
--
2.25.1

Re: [PATCH v2 3/7] drm/amdgpu: Add new function to put GPU power profile

[Lazar, Lijo]

On 8/25/2023 4:48 PM, Yadav, Arvind wrote:


On 8/22/2023 6:16 PM, Lazar, Lijo wrote:



On 8/22/2023 5:41 PM, Yadav, Arvind wrote:

Hi Lijo,

The *_set function will set the GPU power profile and the *_put 
function will  schedule the
smu_delayed_work task after 100ms delay. This smu_delayed_work task 
will clear a GPU
power profile if any new jobs are not scheduled within 100 ms. But if 
any new job  comes within 100ms
then the *_workload_profile_set function  will cancel this work and 
set the GPU power profile based on

preferences.

Please see the below case.

case 1 - only same profile jobs run. It will take 100ms to clear the 
profile once all jobs complete.


                                        wl = VIDEO <100ms>
workload _|`|

Jobs (VIDEO) |```|__|```|___||___


Case2 - two jobs of two different profile. job1 profile will be set 
but when job2 will arrive it will be moved

     to higher profile.

                  wl = VIDEO  ->    wl = COMPUTE <100ms>
workload 
___|``| 



Jobs (VIDEO) ___|```|__|```|___||___||___

Jobs (COMPUTE) __|```|___||___||_



Case3 - two jobs of two different profile. job1 profile will be set 
but when job2 will arrive it will not be moved
to lower profile. When compute job2 will complete then only it will 
move to lower profile.


                                      wl = COMPUTE 
->   wl = VIDEO  <100ms>
workload 
_|``| 



Jobs (COMPUTE)    |```|__|```|___||___||___

Jobs (VIDEO) 
___|```|___||___||___||___




swsmu layer maintains a workload mask based on priority. So once you 
have set the mask, until you unset it (i.e when refcount = 0), the 
mask will be set in the lower layer. swsmu layer will take care of 
requesting FW the highest priority. I don't think that needs to be 
repeated at this level.


At this layer, all you need is to refcount the requests and make the 
request.


When refcount of a profile becomes non-zero (only one-time), place one 
request for that profile. As swsmu layer maintains the workload mask, 
it will take the new profile also into consideration while requesting 
for the one  with the highest priority.


When refcount of a profile becomes zero, place a request to clear it. 
This is controlled by your idle work. As I see, it keeps an additional 
100ms tolerance before placing a clear request. In that way, there is 
no need to cancel that work.


Inside idle work handler -
Loop through the profiles that are set and clear those profiles whose 
refcount is zero.


Thus if a job starts during the 100ms delay, idle work won't see the 
ref count as zero and then it won't place a request to clear out that 
profile.



Hi Liji,

Thank you for your comment. We would be considering your comment but we 
would retain the same design.




All things aside, the entire idea of switching power profile for every 
job submission on a ring looks like an 'abuse' of the power profile 
design. The goal of power profile is to keep a specific profile for a 
sustained workload - like gaming mode, cinema mode etc. It's not meant 
for like switch profile with every job submission which lasts ms or 
lesser (though you may argue it takes only highest priority profile). 
This design is to keep interrupting FW every now and then thinking 
driver is doing better. For any normal/mixed use scenarios, FW 
algorithms could handle it better with all the activity monitors they have.


If you are going ahead, please also make sure to post the improved 
performance numbers you are getting with this.


Thanks,
Lijo


~Arvind.


On 8/22/2023 10:21 AM, Lazar, Lijo wrote:



On 8/21/2023 12:17 PM, Arvind Yadav wrote:

This patch adds a function which will clear the GPU
power profile after job finished.

This is how it works:
- schedular will set the GPU power profile based on ring_type.
- Schedular will clear the GPU Power profile once job finished.
- Here, the *_workload_profile_set function will set the GPU
   power profile and the *_workload_profile_put function will
   schedule the smu_delayed_work task after 100ms delay. This
   smu_delayed_work task will clear a GPU power profile if any
   new jobs are not scheduled within 100 ms. But if any new job
   comes within 100ms then the *_workload_profile_set function
   will cancel this work and set the GPU power profile based on
   preferences.

v2:
- Splitting workload_profile_set and workload_profile_put
   into two separate patches.
- Addressed review comment.

Cc: Shashank Sharma 
Cc: Christian Koenig 
Cc: Alex Deucher 
Signed-off-by: Arvind Yadav 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_workload.c  | 97 
+++

  drivers/gpu/drm/amd/include/amdgpu_workload.h |

Re: [PATCH v2 3/7] drm/amdgpu: Add new function to put GPU power profile

[Yadav, Arvind]

On 8/22/2023 6:16 PM, Lazar, Lijo wrote:



On 8/22/2023 5:41 PM, Yadav, Arvind wrote:

Hi Lijo,

The *_set function will set the GPU power profile and the *_put 
function will  schedule the
smu_delayed_work task after 100ms delay. This smu_delayed_work task 
will clear a GPU
power profile if any new jobs are not scheduled within 100 ms. But if 
any new job  comes within 100ms
then the *_workload_profile_set function  will cancel this work and 
set the GPU power profile based on

preferences.

Please see the below case.

case 1 - only same profile jobs run. It will take 100ms to clear the 
profile once all jobs complete.


                                        wl = VIDEO <100ms>
workload _|`|

Jobs (VIDEO) |```|__|```|___||___


Case2 - two jobs of two different profile. job1 profile will be set 
but when job2 will arrive it will be moved

     to higher profile.

                  wl = VIDEO  ->    wl = COMPUTE   
<100ms>
workload 
___|``|


Jobs (VIDEO) ___|```|__|```|___||___||___

Jobs (COMPUTE) __|```|___||___||_



Case3 - two jobs of two different profile. job1 profile will be set 
but when job2 will arrive it will not be moved
to lower profile. When compute job2 will complete then only it will 
move to lower profile.


                                      wl = COMPUTE 
->   wl = VIDEO  <100ms>
workload 
_|``| 



Jobs (COMPUTE)    |```|__|```|___||___||___

Jobs (VIDEO) 
___|```|___||___||___||___




swsmu layer maintains a workload mask based on priority. So once you 
have set the mask, until you unset it (i.e when refcount = 0), the 
mask will be set in the lower layer. swsmu layer will take care of 
requesting FW the highest priority. I don't think that needs to be 
repeated at this level.


At this layer, all you need is to refcount the requests and make the 
request.


When refcount of a profile becomes non-zero (only one-time), place one 
request for that profile. As swsmu layer maintains the workload mask, 
it will take the new profile also into consideration while requesting 
for the one  with the highest priority.


When refcount of a profile becomes zero, place a request to clear it. 
This is controlled by your idle work. As I see, it keeps an additional 
100ms tolerance before placing a clear request. In that way, there is 
no need to cancel that work.


Inside idle work handler -
Loop through the profiles that are set and clear those profiles whose 
refcount is zero.


Thus if a job starts during the 100ms delay, idle work won't see the 
ref count as zero and then it won't place a request to clear out that 
profile.



Hi Liji,

Thank you for your comment. We would be considering your comment but we 
would retain the same design.


~Arvind.


On 8/22/2023 10:21 AM, Lazar, Lijo wrote:



On 8/21/2023 12:17 PM, Arvind Yadav wrote:

This patch adds a function which will clear the GPU
power profile after job finished.

This is how it works:
- schedular will set the GPU power profile based on ring_type.
- Schedular will clear the GPU Power profile once job finished.
- Here, the *_workload_profile_set function will set the GPU
   power profile and the *_workload_profile_put function will
   schedule the smu_delayed_work task after 100ms delay. This
   smu_delayed_work task will clear a GPU power profile if any
   new jobs are not scheduled within 100 ms. But if any new job
   comes within 100ms then the *_workload_profile_set function
   will cancel this work and set the GPU power profile based on
   preferences.

v2:
- Splitting workload_profile_set and workload_profile_put
   into two separate patches.
- Addressed review comment.

Cc: Shashank Sharma 
Cc: Christian Koenig 
Cc: Alex Deucher 
Signed-off-by: Arvind Yadav 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_workload.c  | 97 
+++

  drivers/gpu/drm/amd/include/amdgpu_workload.h |  3 +
  2 files changed, 100 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_workload.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_workload.c

index e661cc5b3d92..6367eb88a44d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_workload.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_workload.c
@@ -24,6 +24,9 @@
    #include "amdgpu.h"
  +/* 100 millsecond timeout */
+#define SMU_IDLE_TIMEOUT    msecs_to_jiffies(100)
+
  static enum PP_SMC_POWER_PROFILE
  ring_to_power_profile(uint32_t ring_type)
  {
@@ -59,6 +62,80 @@ amdgpu_power_profile_set(struct amdgpu_device 
*adev,

  return ret;
  }
  +static int
+amdgpu_power_profile_clear(struct amdgpu_device *adev,
+   enum PP_SMC_POWER_PROFILE profile)
+{
+    int ret = amdgpu_dpm_switch_power_profile(adev, profile, false);
+
+    if (!ret) {
+

Re: [PATCH] drm/amdgpu: Add only valid firmware version nodes

[Wang, Yang(Kevin)]

[AMD Official Use Only - General]

Reviewed-by: Yang Wang 

Best Regards,
Kevin

发件人: amd-gfx  代表 Lijo Lazar 

发送时间: 星期五, 八月 25, 2023 17:29
收件人: amd-gfx@lists.freedesktop.org 
抄送: Deucher, Alexander ; Zhang, Hawking 

主题: [PATCH] drm/amdgpu: Add only valid firmware version nodes

Show only firmware version attributes that have valid version. Hide
others.

Signed-off-by: Lijo Lazar 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 33 ---
 1 file changed, 29 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index 8beefc045e14..b0b37c056c36 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -669,15 +669,25 @@ const char *amdgpu_ucode_name(enum AMDGPU_UCODE_ID 
ucode_id)
 }
 }

+static inline int amdgpu_ucode_is_valid(uint32_t fw_version)
+{
+   if (!fw_version)
+   return -EINVAL;
+
+   return 0;
+}
+
 #define FW_VERSION_ATTR(name, mode, field)  \
 static ssize_t show_##name(struct device *dev,  \
- struct device_attribute *attr, \
- char *buf) \
+  struct device_attribute *attr, char *buf) \
 {   \
 struct drm_device *ddev = dev_get_drvdata(dev); \
 struct amdgpu_device *adev = drm_to_adev(ddev); \
 \
-   return sysfs_emit(buf, "0x%08x\n", adev->field);\
+   if (!buf)   \
+   return amdgpu_ucode_is_valid(adev->field);  \
+   \
+   return sysfs_emit(buf, "0x%08x\n", adev->field);\
 }   \
 static DEVICE_ATTR(name, mode, show_##name, NULL)

@@ -722,9 +732,24 @@ static struct attribute *fw_attrs[] = {
 NULL
 };

+#define to_dev_attr(x) container_of(x, struct device_attribute, attr)
+
+static umode_t amdgpu_ucode_sys_visible(struct kobject *kobj,
+   struct attribute *attr, int idx)
+{
+   struct device_attribute *dev_attr = to_dev_attr(attr);
+   struct device *dev = kobj_to_dev(kobj);
+
+   if (dev_attr->show(dev, dev_attr, NULL) == -EINVAL)
+   return 0;
+
+   return attr->mode;
+}
+
 static const struct attribute_group fw_attr_group = {
 .name = "fw_version",
-   .attrs = fw_attrs
+   .attrs = fw_attrs,
+   .is_visible = amdgpu_ucode_sys_visible
 };

 int amdgpu_ucode_sysfs_init(struct amdgpu_device *adev)
--
2.25.1

[PATCH] drm/amd/display: Fix up kdoc format for 'dc_set_edp_power'

[Srinivasan Shanmugam]

Fixes the following W=1 kernel build warning:

drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:5261: warning: Cannot 
understand  ***

Cc: Ian Chen 
Cc: Rodrigo Siqueira 
Cc: Harry Wentland 
Cc: Aurabindo Pillai 
Cc: Alex Deucher 
Signed-off-by: Srinivasan Shanmugam 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 025e0fdf486d..ed225e1a1299 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -5258,13 +5258,16 @@ void dc_query_current_properties(struct dc *dc, struct 
dc_current_properties *pr
 }
 
 /**
- *
  * dc_set_edp_power() - DM controls eDP power to be ON/OFF
  *
  * Called when DM wants to power on/off eDP.
  * Only work on links with flag skip_implict_edp_power_control is set.
  *
- *
+ * @dc: Current DC state
+ * @edp_link: a link with eDP connector signal type
+ * @powerOn: power on/off eDP
+ *
+ * Return: void
  */
 void dc_set_edp_power(const struct dc *dc, struct dc_link *edp_link,
 bool powerOn)
-- 
2.25.1

[PATCH] drm/amdgpu: Add only valid firmware version nodes

[Lijo Lazar]

Show only firmware version attributes that have valid version. Hide
others.

Signed-off-by: Lijo Lazar 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 33 ---
 1 file changed, 29 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index 8beefc045e14..b0b37c056c36 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -669,15 +669,25 @@ const char *amdgpu_ucode_name(enum AMDGPU_UCODE_ID 
ucode_id)
}
 }
 
+static inline int amdgpu_ucode_is_valid(uint32_t fw_version)
+{
+   if (!fw_version)
+   return -EINVAL;
+
+   return 0;
+}
+
 #define FW_VERSION_ATTR(name, mode, field) \
 static ssize_t show_##name(struct device *dev, \
- struct device_attribute *attr,\
- char *buf)\
+  struct device_attribute *attr, char *buf)\
 {  \
struct drm_device *ddev = dev_get_drvdata(dev); \
struct amdgpu_device *adev = drm_to_adev(ddev); \
\
-   return sysfs_emit(buf, "0x%08x\n", adev->field);\
+   if (!buf)   \
+   return amdgpu_ucode_is_valid(adev->field);  \
+   \
+   return sysfs_emit(buf, "0x%08x\n", adev->field);\
 }  \
 static DEVICE_ATTR(name, mode, show_##name, NULL)
 
@@ -722,9 +732,24 @@ static struct attribute *fw_attrs[] = {
NULL
 };
 
+#define to_dev_attr(x) container_of(x, struct device_attribute, attr)
+
+static umode_t amdgpu_ucode_sys_visible(struct kobject *kobj,
+   struct attribute *attr, int idx)
+{
+   struct device_attribute *dev_attr = to_dev_attr(attr);
+   struct device *dev = kobj_to_dev(kobj);
+
+   if (dev_attr->show(dev, dev_attr, NULL) == -EINVAL)
+   return 0;
+
+   return attr->mode;
+}
+
 static const struct attribute_group fw_attr_group = {
.name = "fw_version",
-   .attrs = fw_attrs
+   .attrs = fw_attrs,
+   .is_visible = amdgpu_ucode_sys_visible
 };
 
 int amdgpu_ucode_sysfs_init(struct amdgpu_device *adev)
-- 
2.25.1

RE: [V9 6/9] drm/amd/pm: setup the framework to support Wifi RFI mitigation feature

[Quan, Evan]

[AMD Official Use Only - General]

> -Original Message-
> From: Lazar, Lijo 
> Sent: Friday, August 18, 2023 5:12 PM
> To: Quan, Evan ; gre...@linuxfoundation.org;
> raf...@kernel.org; l...@kernel.org; johan...@sipsolutions.net;
> da...@davemloft.net; eduma...@google.com; k...@kernel.org;
> pab...@redhat.com; Deucher, Alexander ;
> and...@lunn.ch; rdun...@infradead.org; quic_jjohn...@quicinc.com;
> ho...@kernel.org
> Cc: linux-...@vger.kernel.org; net...@vger.kernel.org; linux-
> wirel...@vger.kernel.org; linux-ker...@vger.kernel.org; amd-
> g...@lists.freedesktop.org; linux-a...@vger.kernel.org; Limonciello, Mario
> 
> Subject: Re: [V9 6/9] drm/amd/pm: setup the framework to support Wifi RFI
> mitigation feature
>
>
>
> On 8/18/2023 8:56 AM, Evan Quan wrote:
> > With WBRF feature supported, as a driver responding to the
> > frequencies, amdgpu driver is able to do shadow pstate switching to
> > mitigate possible interference(between its (G-)DDR memory clocks and
> > local radio module frequency bands used by Wifi 6/6e/7).
> >
> > Signed-off-by: Evan Quan 
> > Reviewed-by: Mario Limonciello 
> > --
> > v1->v2:
> >- update the prompt for feature support(Lijo)
> > v8->v9:
> >- update parameter document for smu_wbrf_event_handler(Simon)
> > ---
> >   drivers/gpu/drm/amd/amdgpu/amdgpu.h   |   2 +
> >   drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c   |  17 ++
> >   drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 194
> ++
> >   drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h |  23 +++
> >   drivers/gpu/drm/amd/pm/swsmu/smu_internal.h   |   3 +
> >   5 files changed, 239 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > index a3b86b86dc47..2bfc9111ab00 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > @@ -247,6 +247,8 @@ extern int amdgpu_sg_display;
> >
> >   extern int amdgpu_user_partt_mode;
> >
> > +extern int amdgpu_wbrf;
> > +
> >   #define AMDGPU_VM_MAX_NUM_CTX 4096
> >   #define AMDGPU_SG_THRESHOLD   (256*1024*1024)
> >   #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS3000
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> > index 0593ef8fe0a6..1c574bd3b60d 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> > @@ -195,6 +195,7 @@ int amdgpu_use_xgmi_p2p = 1;
> >   int amdgpu_vcnfw_log;
> >   int amdgpu_sg_display = -1; /* auto */
> >   int amdgpu_user_partt_mode =
> AMDGPU_AUTO_COMPUTE_PARTITION_MODE;
> > +int amdgpu_wbrf = -1;
> >
> >   static void amdgpu_drv_delayed_reset_work_handler(struct work_struct
> > *work);
> >
> > @@ -981,6 +982,22 @@ module_param_named(user_partt_mode,
> amdgpu_user_partt_mode, uint, 0444);
> >   module_param(enforce_isolation, bool, 0444);
> >   MODULE_PARM_DESC(enforce_isolation, "enforce process isolation
> > between graphics and compute . enforce_isolation = on");
> >
> > +/**
> > + * DOC: wbrf (int)
> > + * Enable Wifi RFI interference mitigation feature.
> > + * Due to electrical and mechanical constraints there may be likely
> > +interference of
> > + * relatively high-powered harmonics of the (G-)DDR memory clocks
> > +with local radio
> > + * module frequency bands used by Wifi 6/6e/7. To mitigate the
> > +possible RFI interference,
> > + * with this feature enabled, PMFW will use either “shadowed P-State”
> > +or “P-State” based
> > + * on active list of frequencies in-use (to be avoided) as part of
> > +initial setting or
> > + * P-state transition. However, there may be potential performance
> > +impact with this
> > + * feature enabled.
> > + * (0 = disabled, 1 = enabled, -1 = auto (default setting, will be
> > +enabled if supported))  */ MODULE_PARM_DESC(wbrf,
> > +   "Enable Wifi RFI interference mitigation (0 = disabled, 1 = enabled,
> > +-1 = auto(default)"); module_param_named(wbrf, amdgpu_wbrf, int,
> > +0444);
> > +
> >   /* These devices are not supported by amdgpu.
> >* They are supported by the mach64, r128, radeon drivers
> >*/
> > diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> > b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> > index ce41a8309582..704442ce1da3 100644
> > --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> > +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> > @@ -1228,6 +1228,173 @@ static int
> smu_get_thermal_temperature_range(struct smu_context *smu)
> > return ret;
> >   }
> >
> > +/**
> > + * smu_wbrf_handle_exclusion_ranges - consume the wbrf exclusion
> > +ranges
> > + *
> > + * @smu: smu_context pointer
> > + *
> > + * Retrieve the wbrf exclusion ranges and send them to PMFW for proper
> handling.
> > + * Returns 0 on success, error on failure.
> > + */
> > +static int smu_wbrf_handle_exclusion_ranges(struct smu_context *smu)
> > +{
> > +   struct wbrf_ranges_out wbrf_exclusion = {0};
> > +   struct exclusi

RE: [V9 4/9] wifi: mac80211: Add support for WBRF features

[Quan, Evan]

[AMD Official Use Only - General]

> -Original Message-
> From: Johannes Berg 
> Sent: Monday, August 21, 2023 5:44 PM
> To: Quan, Evan ; gre...@linuxfoundation.org;
> raf...@kernel.org; l...@kernel.org; da...@davemloft.net;
> eduma...@google.com; k...@kernel.org; pab...@redhat.com; Deucher,
> Alexander ; and...@lunn.ch;
> rdun...@infradead.org; quic_jjohn...@quicinc.com; ho...@kernel.org
> Cc: linux-...@vger.kernel.org; linux-ker...@vger.kernel.org; linux-
> a...@vger.kernel.org; amd-gfx@lists.freedesktop.org; linux-
> wirel...@vger.kernel.org; net...@vger.kernel.org; Limonciello, Mario
> 
> Subject: Re: [V9 4/9] wifi: mac80211: Add support for WBRF features
>
> On Fri, 2023-08-18 at 11:26 +0800, Evan Quan wrote:
> > To support the WBRF mechanism, Wifi adapters utilized in the system
> > must register the frequencies in use(or unregister those frequencies
> > no longer
> > used) via the dedicated calls. So that, other drivers responding to
> > the frequencies can take proper actions to mitigate possible interference.
> >
> > Co-developed-by: Mario Limonciello 
> > Signed-off-by: Mario Limonciello 
> > Co-developed-by: Evan Quan 
> > Signed-off-by: Evan Quan 
>
> From WiFi POV, this looks _almost_ fine to me.
>
> > +static void wbrf_get_ranges_from_chandef(struct cfg80211_chan_def
> *chandef,
> > +struct wbrf_ranges_in *ranges_in) {
> > +   u64 start_freq1, end_freq1;
> > +   u64 start_freq2, end_freq2;
> > +   int bandwidth;
> > +
> > +   bandwidth = nl80211_chan_width_to_mhz(chandef->width);
> > +
> > +   get_chan_freq_boundary(chandef->center_freq1,
> > +  bandwidth,
> > +  &start_freq1,
> > +  &end_freq1);
> > +
> > +   ranges_in->band_list[0].start = start_freq1;
> > +   ranges_in->band_list[0].end = end_freq1;
> > +
> > +   if (chandef->width == NL80211_CHAN_WIDTH_80P80) {
> > +   get_chan_freq_boundary(chandef->center_freq2,
> > +  bandwidth,
> > +  &start_freq2,
> > +  &end_freq2);
> > +
> > +   ranges_in->band_list[1].start = start_freq2;
> > +   ranges_in->band_list[1].end = end_freq2;
> > +   }
> > +}
>
> This has to setup ranges_in->num_of_ranges, no?
Yes, better to have that. I add this in V10.
> (Also no real good reason for num_of_ranges to be a u64, btw, since it can
> only go up to 11)
Mainly for data structure alignment. Since other members come with u64.
So, to make the data structure naturally aligned, 'num_of_ranges' also comes 
with u64.

Evan
>
> With that fixed, you can add
>
> Reviewed-by: Johannes Berg 
>
> johannes

[V10 7/8] drm/amd/pm: enable Wifi RFI mitigation feature support for SMU13.0.0

[Evan Quan]

Fulfill the SMU13.0.0 support for Wifi RFI mitigation feature.

Signed-off-by: Evan Quan 
Reviewed-by: Mario Limonciello 
---
 drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h |  3 +
 drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h  |  3 +-
 drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h  |  3 +
 .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c|  9 +++
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c  | 60 +++
 5 files changed, 77 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h 
b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
index 60d595344c45..a081e6bb27c4 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
@@ -325,6 +325,7 @@ enum smu_table_id
SMU_TABLE_PACE,
SMU_TABLE_ECCINFO,
SMU_TABLE_COMBO_PPTABLE,
+   SMU_TABLE_WIFIBAND,
SMU_TABLE_COUNT,
 };
 
@@ -1501,6 +1502,8 @@ enum smu_baco_seq {
 __dst_size);  \
 })
 
+#define HZ_IN_MHZ  100U
+
 #if !defined(SWSMU_CODE_LAYER_L2) && !defined(SWSMU_CODE_LAYER_L3) && 
!defined(SWSMU_CODE_LAYER_L4)
 int smu_get_power_limit(void *handle,
uint32_t *limit,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h 
b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
index 297b70b9388f..5bbb60289a79 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
@@ -245,7 +245,8 @@
__SMU_DUMMY_MAP(AllowGpo),  \
__SMU_DUMMY_MAP(Mode2Reset),\
__SMU_DUMMY_MAP(RequestI2cTransaction), \
-   __SMU_DUMMY_MAP(GetMetricsTable),
+   __SMU_DUMMY_MAP(GetMetricsTable), \
+   __SMU_DUMMY_MAP(EnableUCLKShadow),
 
 #undef __SMU_DUMMY_MAP
 #define __SMU_DUMMY_MAP(type)  SMU_MSG_##type
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h 
b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
index 355c156d871a..dd70b56aa71e 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
@@ -299,5 +299,8 @@ int smu_v13_0_update_pcie_parameters(struct smu_context 
*smu,
 uint32_t pcie_gen_cap,
 uint32_t pcie_width_cap);
 
+int smu_v13_0_enable_uclk_shadow(struct smu_context *smu,
+bool enablement);
+
 #endif
 #endif
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index 9b62b45ebb7f..6a5cb582aa92 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -2472,3 +2472,12 @@ int smu_v13_0_update_pcie_parameters(struct smu_context 
*smu,
 
return 0;
 }
+
+int smu_v13_0_enable_uclk_shadow(struct smu_context *smu,
+bool enablement)
+{
+   return smu_cmn_send_smc_msg_with_param(smu,
+  SMU_MSG_EnableUCLKShadow,
+  enablement,
+  NULL);
+}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index 3d188616ba24..fd3ac18653ed 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -154,6 +154,7 @@ static struct cmn2asic_msg_mapping 
smu_v13_0_0_message_map[SMU_MSG_MAX_COUNT] =
MSG_MAP(AllowGpo,   PPSMC_MSG_SetGpoAllow,  
 0),
MSG_MAP(AllowIHHostInterrupt,   PPSMC_MSG_AllowIHHostInterrupt, 
  0),
MSG_MAP(ReenableAcDcInterrupt,  
PPSMC_MSG_ReenableAcDcInterrupt,   0),
+   MSG_MAP(EnableUCLKShadow,   PPSMC_MSG_EnableUCLKShadow, 
   0),
 };
 
 static struct cmn2asic_mapping smu_v13_0_0_clk_map[SMU_CLK_COUNT] = {
@@ -237,6 +238,7 @@ static struct cmn2asic_mapping 
smu_v13_0_0_table_map[SMU_TABLE_COUNT] = {
TAB_MAP(I2C_COMMANDS),
TAB_MAP(ECCINFO),
TAB_MAP(OVERDRIVE),
+   TAB_MAP(WIFIBAND),
 };
 
 static struct cmn2asic_mapping smu_v13_0_0_pwr_src_map[SMU_POWER_SOURCE_COUNT] 
= {
@@ -481,6 +483,9 @@ static int smu_v13_0_0_tables_init(struct smu_context *smu)
PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
SMU_TABLE_INIT(tables, SMU_TABLE_ECCINFO, sizeof(EccInfoTable_t),
PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
+   SMU_TABLE_INIT(tables, SMU_TABLE_WIFIBAND,
+  sizeof(WifiBandEntryTable_t), PAGE_SIZE,
+  AMDGPU_GEM_DOMAIN_VRAM);
 
smu_table->metrics_table = kzalloc(sizeof(SmuMetricsExternal_t), 
GFP_KERNEL);
if (!smu_table->metrics_table)
@@ -2593,6 +2598,58 @@ static ssize_t smu_v13_0_0_get_ecc_info(struct 
smu_context *smu,
return ret;
 }
 
+static bool smu_v13_0_0_wbrf_support_check(

[V10 8/8] drm/amd/pm: enable Wifi RFI mitigation feature support for SMU13.0.7

[Evan Quan]

Fulfill the SMU13.0.7 support for Wifi RFI mitigation feature.

Signed-off-by: Evan Quan 
Reviewed-by: Mario Limonciello 
---
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c  | 59 +++
 1 file changed, 59 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
index b1f0937ccade..d02fe284b05d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
@@ -126,6 +126,7 @@ static struct cmn2asic_msg_mapping 
smu_v13_0_7_message_map[SMU_MSG_MAX_COUNT] =
MSG_MAP(AllowGpo,   PPSMC_MSG_SetGpoAllow,  
 0),
MSG_MAP(GetPptLimit,PPSMC_MSG_GetPptLimit,  
   0),
MSG_MAP(NotifyPowerSource,  PPSMC_MSG_NotifyPowerSource,
   0),
+   MSG_MAP(EnableUCLKShadow,   PPSMC_MSG_EnableUCLKShadow, 
   0),
 };
 
 static struct cmn2asic_mapping smu_v13_0_7_clk_map[SMU_CLK_COUNT] = {
@@ -207,6 +208,7 @@ static struct cmn2asic_mapping 
smu_v13_0_7_table_map[SMU_TABLE_COUNT] = {
TAB_MAP(ACTIVITY_MONITOR_COEFF),
[SMU_TABLE_COMBO_PPTABLE] = {1, TABLE_COMBO_PPTABLE},
TAB_MAP(OVERDRIVE),
+   TAB_MAP(WIFIBAND),
 };
 
 static struct cmn2asic_mapping smu_v13_0_7_pwr_src_map[SMU_POWER_SOURCE_COUNT] 
= {
@@ -497,6 +499,9 @@ static int smu_v13_0_7_tables_init(struct smu_context *smu)
   AMDGPU_GEM_DOMAIN_VRAM);
SMU_TABLE_INIT(tables, SMU_TABLE_COMBO_PPTABLE, 
MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE,
PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
+   SMU_TABLE_INIT(tables, SMU_TABLE_WIFIBAND,
+  sizeof(WifiBandEntryTable_t), PAGE_SIZE,
+  AMDGPU_GEM_DOMAIN_VRAM);
 
smu_table->metrics_table = kzalloc(sizeof(SmuMetricsExternal_t), 
GFP_KERNEL);
if (!smu_table->metrics_table)
@@ -2173,6 +2178,57 @@ static int smu_v13_0_7_set_df_cstate(struct smu_context 
*smu,
   NULL);
 }
 
+static bool smu_v13_0_7_wbrf_support_check(struct smu_context *smu)
+{
+   return smu->smc_fw_version > 0x00524600;
+}
+
+static int smu_v13_0_7_set_wbrf_exclusion_ranges(struct smu_context *smu,
+struct exclusion_range 
*exclusion_ranges)
+{
+   WifiBandEntryTable_t wifi_bands;
+   int valid_entries = 0;
+   int ret, i;
+
+   memset(&wifi_bands, 0, sizeof(wifi_bands));
+   for (i = 0; i < ARRAY_SIZE(wifi_bands.WifiBandEntry); i++) {
+   if (!exclusion_ranges[i].start &&
+   !exclusion_ranges[i].end)
+   break;
+
+   /* PMFW expects the inputs to be in Mhz unit */
+   wifi_bands.WifiBandEntry[valid_entries].LowFreq =
+   DIV_ROUND_DOWN_ULL(exclusion_ranges[i].start, 
HZ_IN_MHZ);
+   wifi_bands.WifiBandEntry[valid_entries++].HighFreq =
+   DIV_ROUND_UP_ULL(exclusion_ranges[i].end, HZ_IN_MHZ);
+   }
+   wifi_bands.WifiBandEntryNum = valid_entries;
+
+   /*
+* Per confirm with PMFW team, WifiBandEntryNum = 0 is a valid setting.
+* Considering the scenarios below:
+* - At first the wifi device adds an exclusion range e.g. (2400,2500) 
to
+*   BIOS and our driver gets notified. We will set WifiBandEntryNum = 1
+*   and pass the WifiBandEntry (2400, 2500) to PMFW.
+*
+* - Later the wifi device removes the wifiband list added above and
+*   our driver gets notified again. At this time, driver will set
+*   WifiBandEntryNum = 0 and pass an empty WifiBandEntry list to PMFW.
+*   - PMFW may still need to do some uclk shadow update(e.g. switching
+* from shadow clock back to primary clock) on receiving this.
+*/
+
+   ret = smu_cmn_update_table(smu,
+  SMU_TABLE_WIFIBAND,
+  0,
+  (void *)(&wifi_bands),
+  true);
+   if (ret)
+   dev_err(smu->adev->dev, "Failed to set wifiband!");
+
+   return ret;
+}
+
 static const struct pptable_funcs smu_v13_0_7_ppt_funcs = {
.get_allowed_feature_mask = smu_v13_0_7_get_allowed_feature_mask,
.set_default_dpm_table = smu_v13_0_7_set_default_dpm_table,
@@ -2241,6 +2297,9 @@ static const struct pptable_funcs smu_v13_0_7_ppt_funcs = 
{
.set_mp1_state = smu_v13_0_7_set_mp1_state,
.set_df_cstate = smu_v13_0_7_set_df_cstate,
.gpo_control = smu_v13_0_gpo_control,
+   .is_asic_wbrf_supported = smu_v13_0_7_wbrf_support_check,
+   .enable_uclk_shadow = smu_v13_0_enable_uclk_shadow,
+   .set_wbrf_exclusion_ranges = smu_v13_0_7_set_wbrf_exclusion_ranges,
 };
 
 void smu_v13_0_7_set_ppt_funcs(struct smu_context *smu

[V10 6/8] drm/amd/pm: add flood detection for wbrf events

[Evan Quan]

To protect PMFW from being overloaded.

Signed-off-by: Evan Quan 
Reviewed-by: Mario Limonciello 
---
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 31 +++
 drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h |  7 +
 2 files changed, 32 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c 
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index bdfd234d1558..7519dc6b0f5d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -1319,7 +1319,8 @@ static int smu_wbrf_event_handler(struct notifier_block 
*nb,
 
switch (action) {
case WBRF_CHANGED:
-   smu_wbrf_handle_exclusion_ranges(smu);
+   schedule_delayed_work(&smu->wbrf_delayed_work,
+ 
msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE));
break;
default:
return NOTIFY_DONE;
@@ -1328,6 +1329,21 @@ static int smu_wbrf_event_handler(struct notifier_block 
*nb,
return NOTIFY_OK;
 }
 
+/**
+ * smu_wbrf_delayed_work_handler - callback on delayed work timer expired
+ *
+ * @work: struct work_struct pointer
+ *
+ * Flood is over and driver will consume the latest exclusion ranges.
+ */
+static void smu_wbrf_delayed_work_handler(struct work_struct *work)
+{
+   struct smu_context *smu =
+   container_of(work, struct smu_context, wbrf_delayed_work.work);
+
+   smu_wbrf_handle_exclusion_ranges(smu);
+}
+
 /**
  * smu_wbrf_support_check - check wbrf support
  *
@@ -1358,12 +1374,14 @@ static void smu_wbrf_support_check(struct smu_context 
*smu)
  */
 static int smu_wbrf_init(struct smu_context *smu)
 {
-   struct amdgpu_device *adev = smu->adev;
int ret;
 
if (!smu->wbrf_supported)
return 0;
 
+   INIT_DELAYED_WORK(&smu->wbrf_delayed_work,
+ smu_wbrf_delayed_work_handler);
+
smu->wbrf_notifier.notifier_call = smu_wbrf_event_handler;
ret = acpi_amd_wbrf_register_notifier(&smu->wbrf_notifier);
if (ret)
@@ -1374,11 +1392,10 @@ static int smu_wbrf_init(struct smu_context *smu)
 * before our driver loaded. To make sure our driver
 * is awared of those exclusion ranges.
 */
-   ret = smu_wbrf_handle_exclusion_ranges(smu);
-   if (ret)
-   dev_err(adev->dev, "Failed to handle wbrf exclusion ranges\n");
+   schedule_delayed_work(&smu->wbrf_delayed_work,
+ msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE));
 
-   return ret;
+   return 0;
 }
 
 /**
@@ -1394,6 +1411,8 @@ static void smu_wbrf_fini(struct smu_context *smu)
return;
 
acpi_amd_wbrf_unregister_notifier(&smu->wbrf_notifier);
+
+   cancel_delayed_work_sync(&smu->wbrf_delayed_work);
 }
 
 static int smu_smc_hw_setup(struct smu_context *smu)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h 
b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
index 3eb1c72a76f1..60d595344c45 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
@@ -480,6 +480,12 @@ struct stb_context {
 
 #define WORKLOAD_POLICY_MAX 7
 
+/*
+ * Configure wbrf event handling pace as there can be only one
+ * event processed every SMU_WBRF_EVENT_HANDLING_PACE ms.
+ */
+#define SMU_WBRF_EVENT_HANDLING_PACE   10
+
 struct smu_context
 {
struct amdgpu_device*adev;
@@ -581,6 +587,7 @@ struct smu_context
/* data structures for wbrf feature support */
boolwbrf_supported;
struct notifier_block   wbrf_notifier;
+   struct delayed_work wbrf_delayed_work;
 };
 
 struct i2c_adapter;
-- 
2.34.1

[V10 5/8] drm/amd/pm: setup the framework to support Wifi RFI mitigation feature

[Evan Quan]

With WBRF feature supported, as a driver responding to the frequencies,
amdgpu driver is able to do shadow pstate switching to mitigate possible
interference(between its (G-)DDR memory clocks and local radio module
frequency bands used by Wifi 6/6e/7).

Signed-off-by: Evan Quan 
Reviewed-by: Mario Limonciello 
--
v1->v2:
  - update the prompt for feature support(Lijo)
v8->v9:
  - update parameter document for smu_wbrf_event_handler(Simon)
v9->v10:
 - correct the logics for wbrf range sorting(Lijo)
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h   |   2 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c   |  17 ++
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 195 ++
 drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h |  23 +++
 drivers/gpu/drm/amd/pm/swsmu/smu_internal.h   |   3 +
 5 files changed, 240 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index a3b86b86dc47..2bfc9111ab00 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -247,6 +247,8 @@ extern int amdgpu_sg_display;
 
 extern int amdgpu_user_partt_mode;
 
+extern int amdgpu_wbrf;
+
 #define AMDGPU_VM_MAX_NUM_CTX  4096
 #define AMDGPU_SG_THRESHOLD(256*1024*1024)
 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 0593ef8fe0a6..1c574bd3b60d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -195,6 +195,7 @@ int amdgpu_use_xgmi_p2p = 1;
 int amdgpu_vcnfw_log;
 int amdgpu_sg_display = -1; /* auto */
 int amdgpu_user_partt_mode = AMDGPU_AUTO_COMPUTE_PARTITION_MODE;
+int amdgpu_wbrf = -1;
 
 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work);
 
@@ -981,6 +982,22 @@ module_param_named(user_partt_mode, 
amdgpu_user_partt_mode, uint, 0444);
 module_param(enforce_isolation, bool, 0444);
 MODULE_PARM_DESC(enforce_isolation, "enforce process isolation between 
graphics and compute . enforce_isolation = on");
 
+/**
+ * DOC: wbrf (int)
+ * Enable Wifi RFI interference mitigation feature.
+ * Due to electrical and mechanical constraints there may be likely 
interference of
+ * relatively high-powered harmonics of the (G-)DDR memory clocks with local 
radio
+ * module frequency bands used by Wifi 6/6e/7. To mitigate the possible RFI 
interference,
+ * with this feature enabled, PMFW will use either “shadowed P-State” or 
“P-State” based
+ * on active list of frequencies in-use (to be avoided) as part of initial 
setting or
+ * P-state transition. However, there may be potential performance impact with 
this
+ * feature enabled.
+ * (0 = disabled, 1 = enabled, -1 = auto (default setting, will be enabled if 
supported))
+ */
+MODULE_PARM_DESC(wbrf,
+   "Enable Wifi RFI interference mitigation (0 = disabled, 1 = enabled, -1 
= auto(default)");
+module_param_named(wbrf, amdgpu_wbrf, int, 0444);
+
 /* These devices are not supported by amdgpu.
  * They are supported by the mach64, r128, radeon drivers
  */
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c 
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index ce41a8309582..bdfd234d1558 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -1228,6 +1228,174 @@ static int smu_get_thermal_temperature_range(struct 
smu_context *smu)
return ret;
 }
 
+/**
+ * smu_wbrf_handle_exclusion_ranges - consume the wbrf exclusion ranges
+ *
+ * @smu: smu_context pointer
+ *
+ * Retrieve the wbrf exclusion ranges and send them to PMFW for proper 
handling.
+ * Returns 0 on success, error on failure.
+ */
+static int smu_wbrf_handle_exclusion_ranges(struct smu_context *smu)
+{
+   struct wbrf_ranges_in_out wbrf_exclusion = {0};
+   struct exclusion_range *wifi_bands = wbrf_exclusion.band_list;
+   struct amdgpu_device *adev = smu->adev;
+   uint32_t num_of_wbrf_ranges = MAX_NUM_OF_WBRF_RANGES;
+   uint64_t start, end;
+   int ret, i, j;
+
+   ret = acpi_amd_wbrf_retrieve_exclusions(adev->dev, &wbrf_exclusion);
+   if (ret) {
+   dev_err(adev->dev, "Failed to retrieve exclusion ranges!\n");
+   return ret;
+   }
+
+   /*
+* The exclusion ranges array we got might be filled with holes and 
duplicate
+* entries. For example:
+* {(2400, 2500), (0, 0), (6882, 6962), (2400, 2500), (0, 0), (6117, 
6189), (0, 0)...}
+* We need to do some sortups to eliminate those holes and duplicate 
entries.
+* Expected output: {(2400, 2500), (6117, 6189), (6882, 6962), (0, 
0)...}
+*/
+   for (i = 0; i < num_of_wbrf_ranges; i++) {
+   start = wifi_bands[i].start;
+   end = wifi_bands[i].end;
+
+   /* get the last valid entry to fill the intermediate hole */
+   if (!start && !end) {
+   for 

[V10 3/8] wifi: mac80211: Add support for WBRF features

[Evan Quan]

To support the WBRF mechanism, Wifi adapters utilized in the system must
register the frequencies in use(or unregister those frequencies no longer
used) via the dedicated calls. So that, other drivers responding to the
frequencies can take proper actions to mitigate possible interference.

Co-developed-by: Mario Limonciello 
Signed-off-by: Mario Limonciello 
Co-developed-by: Evan Quan 
Signed-off-by: Evan Quan 
--
v1->v2:
  - place the new added member(`wbrf_supported`) in
ieee80211_local(Johannes)
  - handle chandefs change scenario properly(Johannes)
  - some minor fixes around code sharing and possible invalid input
checks(Johannes)
v2->v3:
  - drop unnecessary input checks and intermediate APIs(Mario)
  - Separate some mac80211 common code(Mario, Johannes)
v3->v4:
  - some minor fixes around return values(Johannes)
v9->v10:
  - get ranges_in->num_of_ranges set and passed in(Johannes)
---
 include/linux/ieee80211.h  |   1 +
 net/mac80211/Makefile  |   2 +
 net/mac80211/chan.c|   9 
 net/mac80211/ieee80211_i.h |   9 
 net/mac80211/main.c|   2 +
 net/mac80211/wbrf.c| 105 +
 6 files changed, 128 insertions(+)
 create mode 100644 net/mac80211/wbrf.c

diff --git a/include/linux/ieee80211.h b/include/linux/ieee80211.h
index 4b998090898e..f995d06da87f 100644
--- a/include/linux/ieee80211.h
+++ b/include/linux/ieee80211.h
@@ -4335,6 +4335,7 @@ static inline int ieee80211_get_tdls_action(struct 
sk_buff *skb, u32 hdr_size)
 /* convert frequencies */
 #define MHZ_TO_KHZ(freq) ((freq) * 1000)
 #define KHZ_TO_MHZ(freq) ((freq) / 1000)
+#define KHZ_TO_HZ(freq)  ((freq) * 1000)
 #define PR_KHZ(f) KHZ_TO_MHZ(f), f % 1000
 #define KHZ_F "%d.%03d"
 
diff --git a/net/mac80211/Makefile b/net/mac80211/Makefile
index b8de44da1fb8..d46c36f55fd3 100644
--- a/net/mac80211/Makefile
+++ b/net/mac80211/Makefile
@@ -65,4 +65,6 @@ rc80211_minstrel-$(CONFIG_MAC80211_DEBUGFS) += \
 
 mac80211-$(CONFIG_MAC80211_RC_MINSTREL) += $(rc80211_minstrel-y)
 
+mac80211-y += wbrf.o
+
 ccflags-y += -DDEBUG
diff --git a/net/mac80211/chan.c b/net/mac80211/chan.c
index 68952752b599..458469c224ae 100644
--- a/net/mac80211/chan.c
+++ b/net/mac80211/chan.c
@@ -506,11 +506,16 @@ static void _ieee80211_change_chanctx(struct 
ieee80211_local *local,
 
WARN_ON(!cfg80211_chandef_compatible(&ctx->conf.def, chandef));
 
+   ieee80211_remove_wbrf(local, &ctx->conf.def);
+
ctx->conf.def = *chandef;
 
/* check if min chanctx also changed */
changed = IEEE80211_CHANCTX_CHANGE_WIDTH |
  _ieee80211_recalc_chanctx_min_def(local, ctx, rsvd_for);
+
+   ieee80211_add_wbrf(local, &ctx->conf.def);
+
drv_change_chanctx(local, ctx, changed);
 
if (!local->use_chanctx) {
@@ -668,6 +673,8 @@ static int ieee80211_add_chanctx(struct ieee80211_local 
*local,
lockdep_assert_held(&local->mtx);
lockdep_assert_held(&local->chanctx_mtx);
 
+   ieee80211_add_wbrf(local, &ctx->conf.def);
+
if (!local->use_chanctx)
local->hw.conf.radar_enabled = ctx->conf.radar_enabled;
 
@@ -748,6 +755,8 @@ static void ieee80211_del_chanctx(struct ieee80211_local 
*local,
}
 
ieee80211_recalc_idle(local);
+
+   ieee80211_remove_wbrf(local, &ctx->conf.def);
 }
 
 static void ieee80211_free_chanctx(struct ieee80211_local *local,
diff --git a/net/mac80211/ieee80211_i.h b/net/mac80211/ieee80211_i.h
index 91633a0b723e..719f2c892132 100644
--- a/net/mac80211/ieee80211_i.h
+++ b/net/mac80211/ieee80211_i.h
@@ -1600,6 +1600,8 @@ struct ieee80211_local {
 
/* extended capabilities provided by mac80211 */
u8 ext_capa[8];
+
+   bool wbrf_supported;
 };
 
 static inline struct ieee80211_sub_if_data *
@@ -2638,4 +2640,11 @@ ieee80211_eht_cap_ie_to_sta_eht_cap(struct 
ieee80211_sub_if_data *sdata,
const struct ieee80211_eht_cap_elem 
*eht_cap_ie_elem,
u8 eht_cap_len,
struct link_sta_info *link_sta);
+
+void ieee80211_check_wbrf_support(struct ieee80211_local *local);
+void ieee80211_add_wbrf(struct ieee80211_local *local,
+   struct cfg80211_chan_def *chandef);
+void ieee80211_remove_wbrf(struct ieee80211_local *local,
+  struct cfg80211_chan_def *chandef);
+
 #endif /* IEEE80211_I_H */
diff --git a/net/mac80211/main.c b/net/mac80211/main.c
index 24315d7b3126..b20bdaac84db 100644
--- a/net/mac80211/main.c
+++ b/net/mac80211/main.c
@@ -1396,6 +1396,8 @@ int ieee80211_register_hw(struct ieee80211_hw *hw)
debugfs_hw_add(local);
rate_control_add_debugfs(local);
 
+   ieee80211_check_wbrf_support(local);
+
rtnl_lock();
wiphy_lock(hw->wiphy);
 
diff --git a/net/mac80211/wbrf.c b/net/mac80211/wbrf.c
new file mode 100644
index ..63978c7d2bcb
--- /dev/null
+++ b/net/mac80211/wbrf.c
@@ -0,0 +1,105

[V10 4/8] drm/amd/pm: update driver_if and ppsmc headers for coming wbrf feature

[Evan Quan]

Add those data structures to support Wifi RFI mitigation feature.

Signed-off-by: Evan Quan 
Reviewed-by: Mario Limonciello 
---
 .../pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h | 14 +-
 .../pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h | 14 +-
 .../amd/pm/swsmu/inc/pmfw_if/smu_v13_0_0_ppsmc.h   |  3 ++-
 .../amd/pm/swsmu/inc/pmfw_if/smu_v13_0_7_ppsmc.h   |  3 ++-
 4 files changed, 30 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h 
b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h
index 9dd1ed5b8940..e481407b6584 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h
@@ -391,6 +391,17 @@ typedef struct {
   EccInfo_t  EccInfo[24];
 } EccInfoTable_t;
 
+typedef struct {
+  uint16_t LowFreq;
+  uint16_t HighFreq;
+} WifiOneBand_t;
+
+typedef struct {
+  uint32_t WifiBandEntryNum;
+  WifiOneBand_tWifiBandEntry[11];
+  uint32_t MmHubPadding[8];
+} WifiBandEntryTable_t;
+
 //D3HOT sequences
 typedef enum {
   BACO_SEQUENCE,
@@ -1615,7 +1626,8 @@ typedef struct {
 #define TABLE_I2C_COMMANDS9
 #define TABLE_DRIVER_INFO 10
 #define TABLE_ECCINFO 11
-#define TABLE_COUNT   12
+#define TABLE_WIFIBAND12
+#define TABLE_COUNT   13
 
 //IH Interupt ID
 #define IH_INTERRUPT_ID_TO_DRIVER   0xFE
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h 
b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h
index 62b7c0daff68..1530ca002c6c 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h
@@ -392,6 +392,17 @@ typedef struct {
   EccInfo_t  EccInfo[24];
 } EccInfoTable_t;
 
+typedef struct {
+  uint16_t LowFreq;
+  uint16_t HighFreq;
+} WifiOneBand_t;
+
+typedef struct {
+  uint32_t WifiBandEntryNum;
+  WifiOneBand_tWifiBandEntry[11];
+  uint32_t MmHubPadding[8];
+} WifiBandEntryTable_t;
+
 //D3HOT sequences
 typedef enum {
   BACO_SEQUENCE,
@@ -1605,7 +1616,8 @@ typedef struct {
 #define TABLE_I2C_COMMANDS9
 #define TABLE_DRIVER_INFO 10
 #define TABLE_ECCINFO 11
-#define TABLE_COUNT   12
+#define TABLE_WIFIBAND12
+#define TABLE_COUNT   13
 
 //IH Interupt ID
 #define IH_INTERRUPT_ID_TO_DRIVER   0xFE
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_0_ppsmc.h 
b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_0_ppsmc.h
index 10cff75b44d5..c98cc32d11bd 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_0_ppsmc.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_0_ppsmc.h
@@ -138,7 +138,8 @@
 #define PPSMC_MSG_SetBadMemoryPagesRetiredFlagsPerChannel 0x4A
 #define PPSMC_MSG_SetPriorityDeltaGain   0x4B
 #define PPSMC_MSG_AllowIHHostInterrupt   0x4C
-#define PPSMC_Message_Count  0x4D
+#define PPSMC_MSG_EnableUCLKShadow   0x51
+#define PPSMC_Message_Count  0x52
 
 //Debug Dump Message
 #define DEBUGSMC_MSG_TestMessage0x1
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_7_ppsmc.h 
b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_7_ppsmc.h
index 6aaefca9b595..a6bf9cdd130e 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_7_ppsmc.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_7_ppsmc.h
@@ -134,6 +134,7 @@
 #define PPSMC_MSG_SetBadMemoryPagesRetiredFlagsPerChannel 0x4A
 #define PPSMC_MSG_SetPriorityDeltaGain   0x4B
 #define PPSMC_MSG_AllowIHHostInterrupt   0x4C
-#define PPSMC_Message_Count  0x4D
+#define PPSMC_MSG_EnableUCLKShadow   0x51
+#define PPSMC_Message_Count  0x52
 
 #endif
-- 
2.34.1

[V10 2/8] cfg80211: expose nl80211_chan_width_to_mhz for wide sharing

[Evan Quan]

The newly added WBRF feature needs this interface for channel
width calculation.

Signed-off-by: Evan Quan 
--
v8->v9:
  - correct typo(Mhz -> MHz) (Johnson)
---
 include/net/cfg80211.h | 8 
 net/wireless/chan.c| 3 ++-
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/include/net/cfg80211.h b/include/net/cfg80211.h
index 7c7d03aa9d06..8c2a9b748621 100644
--- a/include/net/cfg80211.h
+++ b/include/net/cfg80211.h
@@ -920,6 +920,14 @@ const struct cfg80211_chan_def *
 cfg80211_chandef_compatible(const struct cfg80211_chan_def *chandef1,
const struct cfg80211_chan_def *chandef2);
 
+/**
+ * nl80211_chan_width_to_mhz - get the channel width in MHz
+ * @chan_width: the channel width from &enum nl80211_chan_width
+ * Return: channel width in MHz if the chan_width from &enum nl80211_chan_width
+ * is valid. -1 otherwise.
+ */
+int nl80211_chan_width_to_mhz(enum nl80211_chan_width chan_width);
+
 /**
  * cfg80211_chandef_valid - check if a channel definition is valid
  * @chandef: the channel definition to check
diff --git a/net/wireless/chan.c b/net/wireless/chan.c
index 0b7e81db383d..227db04eac42 100644
--- a/net/wireless/chan.c
+++ b/net/wireless/chan.c
@@ -141,7 +141,7 @@ static bool cfg80211_edmg_chandef_valid(const struct 
cfg80211_chan_def *chandef)
return true;
 }
 
-static int nl80211_chan_width_to_mhz(enum nl80211_chan_width chan_width)
+int nl80211_chan_width_to_mhz(enum nl80211_chan_width chan_width)
 {
int mhz;
 
@@ -190,6 +190,7 @@ static int nl80211_chan_width_to_mhz(enum 
nl80211_chan_width chan_width)
}
return mhz;
 }
+EXPORT_SYMBOL(nl80211_chan_width_to_mhz);
 
 static int cfg80211_chandef_get_width(const struct cfg80211_chan_def *c)
 {
-- 
2.34.1

[V10 1/8] ACPI: Add support for AMD ACPI based Wifi band RFI mitigation feature

[Evan Quan]

Due to electrical and mechanical constraints in certain platform designs
there may be likely interference of relatively high-powered harmonics of
the (G-)DDR memory clocks with local radio module frequency bands used
by Wifi 6/6e/7.

To mitigate this, AMD has introduced a mechanism that devices can use to
notify active use of particular frequencies so that other devices can make
relative internal adjustments as necessary to avoid this resonance.

Signed-off-by: Evan Quan 
---
 drivers/acpi/Kconfig  |  17 ++
 drivers/acpi/Makefile |   2 +
 drivers/acpi/amd_wbrf.c   | 414 ++
 include/linux/acpi_amd_wbrf.h | 140 
 4 files changed, 573 insertions(+)
 create mode 100644 drivers/acpi/amd_wbrf.c
 create mode 100644 include/linux/acpi_amd_wbrf.h

diff --git a/drivers/acpi/Kconfig b/drivers/acpi/Kconfig
index 00dd309b6682..a092ea72d152 100644
--- a/drivers/acpi/Kconfig
+++ b/drivers/acpi/Kconfig
@@ -594,6 +594,23 @@ config ACPI_PRMT
  substantially increase computational overhead related to the
  initialization of some server systems.
 
+config WBRF_AMD_ACPI
+   bool "ACPI based WBRF mechanism introduced by AMD"
+   depends on ACPI
+   default n
+   help
+ Wifi band RFI mitigation mechanism allows multiple drivers from
+ different domains to notify the frequencies in use so that hardware
+ can be reconfigured to avoid harmonic conflicts.
+
+ AMD has introduced an ACPI based mechanism to support WBRF for some
+ platforms with AMD dGPU and WLAN. This needs support from BIOS 
equipped
+ with necessary AML implementations and dGPU firmwares.
+
+ Before enabling this ACPI based mechanism, it is suggested to confirm
+ with the hardware designer/provider first whether your platform
+ equipped with necessary BIOS and firmwares.
+
 endif  # ACPI
 
 config X86_PM_TIMER
diff --git a/drivers/acpi/Makefile b/drivers/acpi/Makefile
index 3fc5a0d54f6e..9185d16e4495 100644
--- a/drivers/acpi/Makefile
+++ b/drivers/acpi/Makefile
@@ -133,3 +133,5 @@ obj-$(CONFIG_ARM64) += arm64/
 obj-$(CONFIG_ACPI_VIOT)+= viot.o
 
 obj-$(CONFIG_RISCV)+= riscv/
+
+obj-$(CONFIG_WBRF_AMD_ACPI)+= amd_wbrf.o
diff --git a/drivers/acpi/amd_wbrf.c b/drivers/acpi/amd_wbrf.c
new file mode 100644
index ..98663b2bfd54
--- /dev/null
+++ b/drivers/acpi/amd_wbrf.c
@@ -0,0 +1,414 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Wifi Band Exclusion Interface (AMD ACPI Implementation)
+ * Copyright (C) 2023 Advanced Micro Devices
+ *
+ */
+
+#include 
+#include 
+
+#define ACPI_AMD_WBRF_METHOD   "\\WBRF"
+
+/*
+ * Functions bit vector for WBRF method
+ *
+ * Bit 0: Supported for any functions other than function 0.
+ * Bit 1: Function 1 (Add / Remove frequency) is supported.
+ * Bit 2: Function 2 (Get frequency list) is supported.
+ */
+#define WBRF_ENABLED   0x0
+#define WBRF_RECORD0x1
+#define WBRF_RETRIEVE  0x2
+
+/* record actions */
+#define WBRF_RECORD_ADD0x0
+#define WBRF_RECORD_REMOVE 0x1
+
+#define WBRF_REVISION  0x1
+
+/*
+ * The data structure used for WBRF_RETRIEVE is not naturally aligned.
+ * And unfortunately the design has been settled down.
+ */
+struct amd_wbrf_ranges_out {
+   u32 num_of_ranges;
+   struct exclusion_range  band_list[MAX_NUM_OF_WBRF_RANGES];
+} __packed;
+
+static const guid_t wifi_acpi_dsm_guid =
+   GUID_INIT(0x7b7656cf, 0xdc3d, 0x4c1c,
+ 0x83, 0xe9, 0x66, 0xe7, 0x21, 0xde, 0x30, 0x70);
+
+static BLOCKING_NOTIFIER_HEAD(wbrf_chain_head);
+
+static int wbrf_dsm(struct acpi_device *adev,
+   u8 fn,
+   union acpi_object *argv4)
+{
+   union acpi_object *obj;
+   int rc;
+
+   obj = acpi_evaluate_dsm(adev->handle, &wifi_acpi_dsm_guid,
+   WBRF_REVISION, fn, argv4);
+   if (!obj)
+   return -ENXIO;
+
+   switch (obj->type) {
+   case ACPI_TYPE_INTEGER:
+   rc = obj->integer.value ? -EINVAL : 0;
+   break;
+   default:
+   rc = -EOPNOTSUPP;
+   }
+
+   ACPI_FREE(obj);
+
+   return rc;
+}
+
+static int wbrf_record(struct acpi_device *adev, uint8_t action,
+  struct wbrf_ranges_in_out *in)
+{
+   union acpi_object argv4;
+   union acpi_object *tmp;
+   u32 num_of_ranges = 0;
+   u32 num_of_elements;
+   u32 arg_idx = 0;
+   u32 loop_idx;
+   int ret;
+
+   if (!in)
+   return -EINVAL;
+
+   for (loop_idx = 0; loop_idx < ARRAY_SIZE(in->band_list);
+loop_idx++)
+   if (in->band_list[loop_idx].start &&
+   in->band_list[loop_idx].end)
+   num_of_ranges++;
+
+   /*
+* The valid entry counter does 

[V10 0/8] Enable Wifi RFI interference mitigation feature support

[Evan Quan]

Due to electrical and mechanical constraints in certain platform designs there
may be likely interference of relatively high-powered harmonics of the (G-)DDR
memory clocks with local radio module frequency bands used by Wifi 6/6e/7. To
mitigate possible RFI interference producers can advertise the frequencies in
use and consumers can use this information to avoid using these frequencies for
sensitive features.

The whole patch set is based on Linux 6.5-rc5. With some brief introductions
as below:
Patch1:  Core functionality setup for WBRF feature support
Patch2 - 3:  Bring WBRF support to wifi subsystem.
Patch4 - 8:  Bring WBRF support to AMD graphics driver.

Evan Quan (8):
  ACPI: Add support for AMD ACPI based Wifi band RFI mitigation feature
  cfg80211: expose nl80211_chan_width_to_mhz for wide sharing
  wifi: mac80211: Add support for WBRF features
  drm/amd/pm: update driver_if and ppsmc headers for coming wbrf feature
  drm/amd/pm: setup the framework to support Wifi RFI mitigation feature
  drm/amd/pm: add flood detection for wbrf events
  drm/amd/pm: enable Wifi RFI mitigation feature support for SMU13.0.0
  drm/amd/pm: enable Wifi RFI mitigation feature support for SMU13.0.7

 drivers/acpi/Kconfig  |  17 +
 drivers/acpi/Makefile |   2 +
 drivers/acpi/amd_wbrf.c   | 414 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu.h   |   2 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c   |  17 +
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 214 +
 drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h |  33 ++
 .../inc/pmfw_if/smu13_driver_if_v13_0_0.h |  14 +-
 .../inc/pmfw_if/smu13_driver_if_v13_0_7.h |  14 +-
 .../pm/swsmu/inc/pmfw_if/smu_v13_0_0_ppsmc.h  |   3 +-
 .../pm/swsmu/inc/pmfw_if/smu_v13_0_7_ppsmc.h  |   3 +-
 drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h  |   3 +-
 drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h  |   3 +
 .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c|   9 +
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c  |  60 +++
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c  |  59 +++
 drivers/gpu/drm/amd/pm/swsmu/smu_internal.h   |   3 +
 include/linux/acpi_amd_wbrf.h | 140 ++
 include/linux/ieee80211.h |   1 +
 include/net/cfg80211.h|   8 +
 net/mac80211/Makefile |   2 +
 net/mac80211/chan.c   |   9 +
 net/mac80211/ieee80211_i.h|   9 +
 net/mac80211/main.c   |   2 +
 net/mac80211/wbrf.c   | 105 +
 net/wireless/chan.c   |   3 +-
 26 files changed, 1143 insertions(+), 6 deletions(-)
 create mode 100644 drivers/acpi/amd_wbrf.c
 create mode 100644 include/linux/acpi_amd_wbrf.h
 create mode 100644 net/mac80211/wbrf.c

-- 
2.34.1

Re: [PATCH] drm/amd: Simplify the size check funciton

[Christian König]

Am 25.08.23 um 07:22 schrieb Ma Jun:

Simplify the code logic of size check function amdgpu_bo_validate_size

Signed-off-by: Ma Jun 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 28 +-
  1 file changed, 11 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 807ea74ece25..4c95db954a76 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -480,7 +480,7 @@ void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 
*gpu_addr,
*cpu_addr = NULL;
  }
  
-/* Validate bo size is bit bigger then the request domain */

+/* Validate bo size is bit bigger than the request domain */
  static bool amdgpu_bo_validate_size(struct amdgpu_device *adev,
  unsigned long size, u32 domain)
  {
@@ -490,29 +490,23 @@ static bool amdgpu_bo_validate_size(struct amdgpu_device 
*adev,
 * If GTT is part of requested domains the check must succeed to
 * allow fall back to GTT.
 */
-   if (domain & AMDGPU_GEM_DOMAIN_GTT) {
+   if (domain & AMDGPU_GEM_DOMAIN_GTT)
man = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT);
-
-   if (man && size < man->size)
-   return true;
-   else if (!man)
-   WARN_ON_ONCE("GTT domain requested but GTT mem manager 
uninitialized");
-   goto fail;
-   } else if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
+   else if (domain & AMDGPU_GEM_DOMAIN_VRAM)
man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
+   else
+   return true;
  
-		if (man && size < man->size)

-   return true;
-   goto fail;
+   if (!man) {
+   WARN_ON_ONCE("Mem mananger of mem domain %d is uninitialized", 
domain);
+   return false;
}


That change here is not correct. It's perfectly valid for userspace to 
request VRAM even if VRAM isn't initialized.


Only the GTT manager is mandatory. That's why the code previously looked 
like it does.


regards,
Christian.

  
  	/* TODO add more domains checks, such as AMDGPU_GEM_DOMAIN_CPU, _DOMAIN_DOORBELL */

-   return true;
+   if (size < man->size)
+   return true;
  
-fail:

-   if (man)
-   DRM_DEBUG("BO size %lu > total memory in domain: %llu\n", size,
- man->size);
+   DRM_DEBUG("BO size %lu > total memory in domain: %llu\n", size, 
man->size);
return false;
  }
  

Re: [PATCH 2/5] ALSA: hda/intel: Use pci_get_base_class() to reduce duplicated code

[Takashi Iwai]

On Fri, 25 Aug 2023 08:27:11 +0200,
Sui Jingfeng wrote:
> 
> From: Sui Jingfeng 
> 
> Should be no functional change
> 
> Cc: Jaroslav Kysela 
> Cc: Takashi Iwai 
> Cc: Fred Oh 
> Cc: Pierre-Louis Bossart 
> Cc: Kai Vehmanen 
> Cc: Bjorn Helgaas 
> Signed-off-by: Sui Jingfeng 
> ---
>  sound/pci/hda/hda_intel.c | 16 +---
>  1 file changed, 5 insertions(+), 11 deletions(-)
> 
> diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c
> index a21b61ad08d1..811a149584f2 100644
> --- a/sound/pci/hda/hda_intel.c
> +++ b/sound/pci/hda/hda_intel.c
> @@ -1429,17 +1429,11 @@ static bool atpx_present(void)
>   acpi_handle dhandle, atpx_handle;
>   acpi_status status;
>  
> - while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != 
> NULL) {
> - dhandle = ACPI_HANDLE(&pdev->dev);
> - if (dhandle) {
> - status = acpi_get_handle(dhandle, "ATPX", &atpx_handle);
> - if (ACPI_SUCCESS(status)) {
> - pci_dev_put(pdev);
> - return true;
> - }
> - }
> - }
> - while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != 
> NULL) {
> + while ((pdev = pci_get_base_class(PCI_BASE_CLASS_DISPLAY, pdev))) {
> + if ((pdev->class != PCI_CLASS_DISPLAY_VGA << 8) &&
> + (pdev->class != PCI_CLASS_DISPLAY_OTHER << 8))
> + continue;
> +
>   dhandle = ACPI_HANDLE(&pdev->dev);
>   if (dhandle) {
>   status = acpi_get_handle(dhandle, "ATPX", &atpx_handle);

Reviewed-by: Takashi Iwai 


thanks,

Takashi

RE: [PATCH] drm/amdgpu: use read-modify-write mode for gfx v9_4_3 SQ setting

[Zhang, Hawking]

[AMD Official Use Only - General]

Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: Zhou1, Tao 
Sent: Friday, August 25, 2023 15:24
To: amd-gfx@lists.freedesktop.org; Zhang, Hawking ; 
Yang, Stanley 
Cc: Zhou1, Tao 
Subject: [PATCH] drm/amdgpu: use read-modify-write mode for gfx v9_4_3 SQ 
setting

Instead of using direct update, avoid touching unrelated fields.

Signed-off-by: Tao Zhou 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index b4fdb269f856..f24a5474db35 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
@@ -4042,7 +4042,8 @@ static void gfx_v9_4_3_inst_enable_watchdog_timer(struct 
amdgpu_device *adev,
uint32_t i;
uint32_t data;

-   data = REG_SET_FIELD(0, SQ_TIMEOUT_CONFIG, TIMEOUT_FATAL_DISABLE,
+   data = RREG32_SOC15(GC, GET_INST(GC, 0), regSQ_TIMEOUT_CONFIG);
+   data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, TIMEOUT_FATAL_DISABLE,
 amdgpu_watchdog_timer.timeout_fatal_disable ? 1 : 
0);

if (amdgpu_watchdog_timer.timeout_fatal_disable &&
--
2.35.1

[PATCH] drm/amdgpu: use read-modify-write mode for gfx v9_4_3 SQ setting

[Tao Zhou]

Instead of using direct update, avoid touching unrelated fields.

Signed-off-by: Tao Zhou 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index b4fdb269f856..f24a5474db35 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
@@ -4042,7 +4042,8 @@ static void gfx_v9_4_3_inst_enable_watchdog_timer(struct 
amdgpu_device *adev,
uint32_t i;
uint32_t data;
 
-   data = REG_SET_FIELD(0, SQ_TIMEOUT_CONFIG, TIMEOUT_FATAL_DISABLE,
+   data = RREG32_SOC15(GC, GET_INST(GC, 0), regSQ_TIMEOUT_CONFIG);
+   data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, TIMEOUT_FATAL_DISABLE,
 amdgpu_watchdog_timer.timeout_fatal_disable ? 1 : 
0);
 
if (amdgpu_watchdog_timer.timeout_fatal_disable &&
-- 
2.35.1