Re: [PATCH] drm/amd/pm: denote S to the deep sleep clock
On 2/8/2024 11:04 AM, Kenneth Feng wrote:
> denote S to the deep sleep clock for the clock output on smu
> v13.0.0/v13.0.7/v13.0.10
>
> Signed-off-by: Kenneth Feng
> ---
> .../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 27 +--
> .../drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 27 +--
> 2 files changed, 38 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
> index 2e7518f4ae1a..fd33646970a4 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
> @@ -109,6 +109,7 @@
> #define PP_OD_FEATURE_FAN_MINIMUM_PWM10
>
> #define LINK_SPEED_MAX 3
> +#define SMU_13_0_0_DSCLK_THRESHOLD 100
>
> static struct cmn2asic_msg_mapping
> smu_v13_0_0_message_map[SMU_MSG_MAX_COUNT] = {
> MSG_MAP(TestMessage,PPSMC_MSG_TestMessage,
>1),
> @@ -1269,20 +1270,30 @@ static int smu_v13_0_0_print_clk_levels(struct
> smu_context *smu,
>* - level 0 -> min clock freq
>* - level 1 -> max clock freq
>* And the current clock frequency can be any value
> between them.
> - * So, if the current clock frequency is not at level 0
> or level 1,
> - * we will fake it as three dpm levels:
> + * So, if the current clock frequency is lower than
> level 0,
> + * we will denote it to S:
> + * - level S -> current actual clock freq
>* - level 0 -> min clock freq
> - * - level 1 -> current actual clock freq
> - * - level 2 -> max clock freq
> + * - level 1 -> max clock freq
>*/
> if ((single_dpm_table->dpm_levels[0].value !=
> curr_freq) &&
> - (single_dpm_table->dpm_levels[1].value !=
> curr_freq)) {
> + (single_dpm_table->dpm_levels[1].value !=
> curr_freq) &&
> + (curr_freq < SMU_13_0_0_DSCLK_THRESHOLD)) {
> + size += sysfs_emit_at(buf, size, "S: %uMhz *\n",
> + curr_freq);
> size += sysfs_emit_at(buf, size, "0: %uMhz\n",
>
> single_dpm_table->dpm_levels[0].value);
> - size += sysfs_emit_at(buf, size, "1: %uMhz *\n",
> - curr_freq);
> - size += sysfs_emit_at(buf, size, "2: %uMhz\n",
> + size += sysfs_emit_at(buf, size, "1: %uMhz\n",
>
> single_dpm_table->dpm_levels[1].value);
> + } else if ((single_dpm_table->dpm_levels[0].value !=
> curr_freq) &&
> +
> (single_dpm_table->dpm_levels[1].value != curr_freq)) {
> + size += sysfs_emit_at(buf, size, "0: %uMhz
> %s\n",
> +
> single_dpm_table->dpm_levels[0].value,
> +
> single_dpm_table->dpm_levels[0].value == curr_freq ? "*" : "");
> + size += sysfs_emit_at(buf, size, "1: %uMhz
> *\n", curr_freq);
> + size += sysfs_emit_at(buf, size, "2: %uMhz
> %s\n",
> +
> single_dpm_table->dpm_levels[1].value,
> +
> single_dpm_table->dpm_levels[1].value == curr_freq ? "*" : "");
> } else {
> size += sysfs_emit_at(buf, size, "0: %uMhz
> %s\n",
>
> single_dpm_table->dpm_levels[0].value,
'S' notation is used for any clock, not just GFXCLK. The 'else' part
here also needs modification.
Thanks,
Lijo
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
> index 0ffdb58af74e..2ecebad7a9cb 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
> @@ -85,6 +85,7 @@
> #define PP_OD_FEATURE_FAN_MINIMUM_PWM10
>
> #define LINK_SPEED_MAX 3
> +#define SMU_13_0_7_DSCLK_THRESHOLD 100
>
> static struct cmn2asic_msg_mapping
> smu_v13_0_7_message_map[SMU_MSG_MAX_COUNT] = {
> MSG_MAP(TestMessage,PPSMC_MSG_TestMessage,
>1),
> @@ -1258,20 +1259,30 @@ static int smu_v13_0_7_print_clk_levels(struct
> smu_context *sm
Re: [PATCH] drm/buddy: Fix alloc_range() error handling code
Am 07.02.24 um 18:44 schrieb Arunpravin Paneer Selvam:
Few users have observed display corruption when they boot
the machine to KDE Plasma or playing games. We have root
caused the problem that whenever alloc_range() couldn't
find the required memory blocks the function was returning
SUCCESS in some of the corner cases.
The right approach would be if the total allocated size
is less than the required size, the function should
return -ENOSPC.
Gitlab ticket link - https://gitlab.freedesktop.org/drm/amd/-/issues/3097
Fixes: 0a1844bf0b53 ("drm/buddy: Improve contiguous memory allocation")
Signed-off-by: Arunpravin Paneer Selvam
Tested-by: Mario Limonciello
Acked-by: Christian König
CC: stable.. ?
---
drivers/gpu/drm/drm_buddy.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/drm_buddy.c b/drivers/gpu/drm/drm_buddy.c
index f57e6d74fb0e..c1a99bf4dffd 100644
--- a/drivers/gpu/drm/drm_buddy.c
+++ b/drivers/gpu/drm/drm_buddy.c
@@ -539,6 +539,12 @@ static int __alloc_range(struct drm_buddy *mm,
} while (1);
list_splice_tail(&allocated, blocks);
+
+ if (total_allocated < size) {
+ err = -ENOSPC;
+ goto err_free;
+ }
+
return 0;
err_undo:
Re: [PATCH v4 3/3] drm/amd: Drop unneeded functions to check if s3/s0ix active
Am 08.02.24 um 06:52 schrieb Mario Limonciello:
amdgpu_acpi_is_s0ix_active() and amdgpu_acpi_is_s0ix_active() aren't
needed to be checked multiple times in a suspend cycle. Checking and
setting up policy one time in the prepare() callback is sufficient.
Mhm, looking at amdgpu_acpi_is_s3_active() I think we should not cache
that in a variable in the first place.
Just calling the function all the time to check the state should be
sufficient, or do we then run into any state transition problems?
Regards,
Christian.
Signed-off-by: Mario Limonciello
---
v4: New patch
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4
drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 7 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 17 ++---
3 files changed, 5 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index f6c38a974bae..53823539eba5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1545,12 +1545,8 @@ static inline int amdgpu_acpi_smart_shift_update(struct
drm_device *dev,
#endif
#if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND)
-bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev);
-bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev);
void amdgpu_choose_low_power_state(struct amdgpu_device *adev);
#else
-static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) {
return false; }
-static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) {
return false; }
static void amdgpu_choose_low_power_state(struct amdgpu_device *adev) { }
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
index cc21ed67a330..1d58728f8c3f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
@@ -1366,8 +1366,7 @@ bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device
*adev)
adev->gfx.imu.funcs) /* Not need to do mode2 reset for IMU enabled
APUs */
return false;
- if ((adev->flags & AMD_IS_APU) &&
- amdgpu_acpi_is_s3_active(adev))
+ if ((adev->flags & AMD_IS_APU) && adev->in_s3)
return false;
if (amdgpu_sriov_vf(adev))
@@ -1472,7 +1471,7 @@ void amdgpu_acpi_release(void)
*
* returns true if supported, false if not.
*/
-bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev)
+static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev)
{
return !(adev->flags & AMD_IS_APU) ||
(pm_suspend_target_state == PM_SUSPEND_MEM);
@@ -1485,7 +1484,7 @@ bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev)
*
* returns true if supported, false if not.
*/
-bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev)
+static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev)
{
if (!(adev->flags & AMD_IS_APU) ||
(pm_suspend_target_state != PM_SUSPEND_TO_IDLE))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 971acf01bea6..2bc4c5bb9b5a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -2456,13 +2456,6 @@ static int amdgpu_pmops_prepare(struct device *dev)
pm_runtime_suspended(dev))
return 1;
- /* if we will not support s3 or s2i for the device
-* then skip suspend
-*/
- if (!amdgpu_acpi_is_s0ix_active(adev) &&
- !amdgpu_acpi_is_s3_active(adev))
- return 1;
-
return amdgpu_device_prepare(drm_dev);
}
@@ -2476,10 +2469,6 @@ static int amdgpu_pmops_suspend(struct device *dev)
struct drm_device *drm_dev = dev_get_drvdata(dev);
struct amdgpu_device *adev = drm_to_adev(drm_dev);
- if (amdgpu_acpi_is_s0ix_active(adev))
- adev->in_s0ix = true;
- else if (amdgpu_acpi_is_s3_active(adev))
- adev->in_s3 = true;
if (!adev->in_s0ix && !adev->in_s3)
return 0;
return amdgpu_device_suspend(drm_dev, true);
@@ -2510,10 +2499,8 @@ static int amdgpu_pmops_resume(struct device *dev)
adev->no_hw_access = true;
r = amdgpu_device_resume(drm_dev, true);
- if (amdgpu_acpi_is_s0ix_active(adev))
- adev->in_s0ix = false;
- else
- adev->in_s3 = false;
+ adev->in_s0ix = adev->in_s3 = false;
+
return r;
}
[PATCH v4 2/3] drm/amd: Stop evicting resources on APUs in suspend
commit 5095d5418193 ("drm/amd: Evict resources during PM ops prepare()
callback") intentionally moved the eviction of resources to earlier in
the suspend process, but this introduced a subtle change that it occurs
before adev->in_s0ix or adev->in_s3 are set. This meant that APUs
actually started to evict resources at suspend time as well.
Explicitly set s0ix or s3 in the prepare() stage, and unset them if the
prepare() stage failed.
Reported-by: Jürg Billeter
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3132#note_2271038
Fixes: 5095d5418193 ("drm/amd: Evict resources during PM ops prepare()
callback")
Signed-off-by: Mario Limonciello
---
v3->v4:
* New function to set s0ix/s3 and explicitly unset in cleanup
v2->v3:
* Whitespace
v1->v2:
* Add and use new in_prepare member
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 2 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 15 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 11 +--
3 files changed, 26 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 3d8a48f46b01..f6c38a974bae 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1547,9 +1547,11 @@ static inline int amdgpu_acpi_smart_shift_update(struct
drm_device *dev,
#if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND)
bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev);
bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev);
+void amdgpu_choose_low_power_state(struct amdgpu_device *adev);
#else
static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) {
return false; }
static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) {
return false; }
+static void amdgpu_choose_low_power_state(struct amdgpu_device *adev) { }
#endif
#if defined(CONFIG_DRM_AMD_DC)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
index 2deebece810e..cc21ed67a330 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
@@ -1519,4 +1519,19 @@ bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device
*adev)
#endif /* CONFIG_AMD_PMC */
}
+/**
+ * amdgpu_choose_low_power_state
+ *
+ * @adev: amdgpu_device_pointer
+ *
+ * Choose the target low power state for the GPU
+ */
+void amdgpu_choose_low_power_state(struct amdgpu_device *adev)
+{
+ if (amdgpu_acpi_is_s0ix_active(adev))
+ adev->in_s0ix = true;
+ else if (amdgpu_acpi_is_s3_active(adev))
+ adev->in_s3 = true;
+}
+
#endif /* CONFIG_SUSPEND */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 2bc460cb993d..dab03865c827 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -4518,13 +4518,15 @@ int amdgpu_device_prepare(struct drm_device *dev)
struct amdgpu_device *adev = drm_to_adev(dev);
int i, r;
+ amdgpu_choose_low_power_state(adev);
+
if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
return 0;
/* Evict the majority of BOs before starting suspend sequence */
r = amdgpu_device_evict_resources(adev);
if (r)
- return r;
+ goto unprepare;
for (i = 0; i < adev->num_ip_blocks; i++) {
if (!adev->ip_blocks[i].status.valid)
@@ -4533,10 +4535,15 @@ int amdgpu_device_prepare(struct drm_device *dev)
continue;
r = adev->ip_blocks[i].version->funcs->prepare_suspend((void
*)adev);
if (r)
- return r;
+ goto unprepare;
}
return 0;
+
+unprepare:
+ adev->in_s0ix = adev->in_s3 = false;
+
+ return r;
}
/**
--
2.34.1
[PATCH v4 3/3] drm/amd: Drop unneeded functions to check if s3/s0ix active
amdgpu_acpi_is_s0ix_active() and amdgpu_acpi_is_s0ix_active() aren't
needed to be checked multiple times in a suspend cycle. Checking and
setting up policy one time in the prepare() callback is sufficient.
Signed-off-by: Mario Limonciello
---
v4: New patch
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4
drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 7 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 17 ++---
3 files changed, 5 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index f6c38a974bae..53823539eba5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1545,12 +1545,8 @@ static inline int amdgpu_acpi_smart_shift_update(struct
drm_device *dev,
#endif
#if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND)
-bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev);
-bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev);
void amdgpu_choose_low_power_state(struct amdgpu_device *adev);
#else
-static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) {
return false; }
-static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) {
return false; }
static void amdgpu_choose_low_power_state(struct amdgpu_device *adev) { }
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
index cc21ed67a330..1d58728f8c3f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
@@ -1366,8 +1366,7 @@ bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device
*adev)
adev->gfx.imu.funcs) /* Not need to do mode2 reset for IMU enabled
APUs */
return false;
- if ((adev->flags & AMD_IS_APU) &&
- amdgpu_acpi_is_s3_active(adev))
+ if ((adev->flags & AMD_IS_APU) && adev->in_s3)
return false;
if (amdgpu_sriov_vf(adev))
@@ -1472,7 +1471,7 @@ void amdgpu_acpi_release(void)
*
* returns true if supported, false if not.
*/
-bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev)
+static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev)
{
return !(adev->flags & AMD_IS_APU) ||
(pm_suspend_target_state == PM_SUSPEND_MEM);
@@ -1485,7 +1484,7 @@ bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev)
*
* returns true if supported, false if not.
*/
-bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev)
+static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev)
{
if (!(adev->flags & AMD_IS_APU) ||
(pm_suspend_target_state != PM_SUSPEND_TO_IDLE))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 971acf01bea6..2bc4c5bb9b5a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -2456,13 +2456,6 @@ static int amdgpu_pmops_prepare(struct device *dev)
pm_runtime_suspended(dev))
return 1;
- /* if we will not support s3 or s2i for the device
-* then skip suspend
-*/
- if (!amdgpu_acpi_is_s0ix_active(adev) &&
- !amdgpu_acpi_is_s3_active(adev))
- return 1;
-
return amdgpu_device_prepare(drm_dev);
}
@@ -2476,10 +2469,6 @@ static int amdgpu_pmops_suspend(struct device *dev)
struct drm_device *drm_dev = dev_get_drvdata(dev);
struct amdgpu_device *adev = drm_to_adev(drm_dev);
- if (amdgpu_acpi_is_s0ix_active(adev))
- adev->in_s0ix = true;
- else if (amdgpu_acpi_is_s3_active(adev))
- adev->in_s3 = true;
if (!adev->in_s0ix && !adev->in_s3)
return 0;
return amdgpu_device_suspend(drm_dev, true);
@@ -2510,10 +2499,8 @@ static int amdgpu_pmops_resume(struct device *dev)
adev->no_hw_access = true;
r = amdgpu_device_resume(drm_dev, true);
- if (amdgpu_acpi_is_s0ix_active(adev))
- adev->in_s0ix = false;
- else
- adev->in_s3 = false;
+ adev->in_s0ix = adev->in_s3 = false;
+
return r;
}
--
2.34.1
[PATCH v4 1/3] Revert "drm/amd: flush any delayed gfxoff on suspend entry"
commit ab4750332dbe ("drm/amdgpu/sdma5.2: add begin/end_use ring
callbacks") caused GFXOFF control to be used more heavily and the
codepath that was removed from commit 0dee72639533 ("drm/amd: flush any
delayed gfxoff on suspend entry") now can be exercised at suspend again.
Users report that by using GNOME to suspend the lockscreen trigger will
cause SDMA traffic and the system can deadlock.
This reverts commit 0dee726395333fea833eaaf838bc80962df886c8.
Acked-by: Alex Deucher
Fixes: ab4750332dbe ("drm/amdgpu/sdma5.2: add begin/end_use ring callbacks")
Signed-off-by: Mario Limonciello
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 -
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c| 9 -
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 670ecb789d59..2bc460cb993d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -4573,7 +4573,6 @@ int amdgpu_device_suspend(struct drm_device *dev, bool
fbcon)
drm_fb_helper_set_suspend_unlocked(adev_to_drm(adev)->fb_helper, true);
cancel_delayed_work_sync(&adev->delayed_init_work);
- flush_delayed_work(&adev->gfx.gfx_off_delay_work);
amdgpu_ras_suspend(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index aa8e1d29d10a..9831dd854532 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -727,8 +727,15 @@ void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool
enable)
if (adev->gfx.gfx_off_req_count == 0 &&
!adev->gfx.gfx_off_state) {
- schedule_delayed_work(&adev->gfx.gfx_off_delay_work,
+ /* If going to s2idle, no need to wait */
+ if (adev->in_s0ix) {
+ if (!amdgpu_dpm_set_powergating_by_smu(adev,
+ AMD_IP_BLOCK_TYPE_GFX, true))
+ adev->gfx.gfx_off_state = true;
+ } else {
+
schedule_delayed_work(&adev->gfx.gfx_off_delay_work,
delay);
+ }
}
} else {
if (adev->gfx.gfx_off_req_count == 0) {
--
2.34.1
[PATCH] drm/amd/pm: denote S to the deep sleep clock
denote S to the deep sleep clock for the clock output on smu
v13.0.0/v13.0.7/v13.0.10
Signed-off-by: Kenneth Feng
---
.../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 27 +--
.../drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 27 +--
2 files changed, 38 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index 2e7518f4ae1a..fd33646970a4 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -109,6 +109,7 @@
#define PP_OD_FEATURE_FAN_MINIMUM_PWM 10
#define LINK_SPEED_MAX 3
+#define SMU_13_0_0_DSCLK_THRESHOLD 100
static struct cmn2asic_msg_mapping smu_v13_0_0_message_map[SMU_MSG_MAX_COUNT]
= {
MSG_MAP(TestMessage,PPSMC_MSG_TestMessage,
1),
@@ -1269,20 +1270,30 @@ static int smu_v13_0_0_print_clk_levels(struct
smu_context *smu,
* - level 0 -> min clock freq
* - level 1 -> max clock freq
* And the current clock frequency can be any value
between them.
-* So, if the current clock frequency is not at level 0
or level 1,
-* we will fake it as three dpm levels:
+* So, if the current clock frequency is lower than
level 0,
+* we will denote it to S:
+* - level S -> current actual clock freq
* - level 0 -> min clock freq
-* - level 1 -> current actual clock freq
-* - level 2 -> max clock freq
+* - level 1 -> max clock freq
*/
if ((single_dpm_table->dpm_levels[0].value !=
curr_freq) &&
-(single_dpm_table->dpm_levels[1].value !=
curr_freq)) {
+(single_dpm_table->dpm_levels[1].value !=
curr_freq) &&
+(curr_freq < SMU_13_0_0_DSCLK_THRESHOLD)) {
+ size += sysfs_emit_at(buf, size, "S: %uMhz *\n",
+ curr_freq);
size += sysfs_emit_at(buf, size, "0: %uMhz\n",
single_dpm_table->dpm_levels[0].value);
- size += sysfs_emit_at(buf, size, "1: %uMhz *\n",
- curr_freq);
- size += sysfs_emit_at(buf, size, "2: %uMhz\n",
+ size += sysfs_emit_at(buf, size, "1: %uMhz\n",
single_dpm_table->dpm_levels[1].value);
+ } else if ((single_dpm_table->dpm_levels[0].value !=
curr_freq) &&
+
(single_dpm_table->dpm_levels[1].value != curr_freq)) {
+ size += sysfs_emit_at(buf, size, "0: %uMhz
%s\n",
+
single_dpm_table->dpm_levels[0].value,
+
single_dpm_table->dpm_levels[0].value == curr_freq ? "*" : "");
+ size += sysfs_emit_at(buf, size, "1: %uMhz
*\n", curr_freq);
+ size += sysfs_emit_at(buf, size, "2: %uMhz
%s\n",
+
single_dpm_table->dpm_levels[1].value,
+
single_dpm_table->dpm_levels[1].value == curr_freq ? "*" : "");
} else {
size += sysfs_emit_at(buf, size, "0: %uMhz
%s\n",
single_dpm_table->dpm_levels[0].value,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
index 0ffdb58af74e..2ecebad7a9cb 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
@@ -85,6 +85,7 @@
#define PP_OD_FEATURE_FAN_MINIMUM_PWM 10
#define LINK_SPEED_MAX 3
+#define SMU_13_0_7_DSCLK_THRESHOLD 100
static struct cmn2asic_msg_mapping smu_v13_0_7_message_map[SMU_MSG_MAX_COUNT]
= {
MSG_MAP(TestMessage,PPSMC_MSG_TestMessage,
1),
@@ -1258,20 +1259,30 @@ static int smu_v13_0_7_print_clk_levels(struct
smu_context *smu,
* - level 0 -> min clock freq
* - level 1 -> max clock freq
* And the current clock frequency can be any value
between them.
-* So, if the current clock frequency is not at level 0
or level 1,
-
[Patch v2] drm/amdkfd: update SIMD distribution algo for GFXIP 9.4.2 onwards
In certain cooperative group dispatch scenarios the default SPI resource
allocation may cause reduced per-CU workgroup occupancy. Set
COMPUTE_RESOURCE_LIMITS.FORCE_SIMD_DIST=1 to mitigate soft hang
scenarions.
Suggested-by: Joseph Greathouse
Signed-off-by: Rajneesh Bhardwaj
---
* Found a bug in the previous reviewed version
https://lists.freedesktop.org/archives/amd-gfx/2024-February/104101.html
since the q->is_gws is unset for keeping the count.
* updated pqm_set_gws to pass minfo holding gws state for the active
queues and use that to apply the FORCE_SIMD_DIST_MASK.
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c| 4
drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 1 +
drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 4 +++-
3 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
index 42d881809dc7..0b71db4c96b5 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
@@ -303,6 +303,10 @@ static void update_mqd(struct mqd_manager *mm, void *mqd,
update_cu_mask(mm, mqd, minfo, 0);
set_priority(m, q);
+ if (minfo && KFD_GC_VERSION(mm->dev) >= IP_VERSION(9, 4, 2))
+ m->compute_resource_limits = minfo->gws ?
+ COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK : 0;
+
q->is_active = QUEUE_IS_ACTIVE(*q);
}
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
index 677281c0793e..f4b327a2d4a8 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
@@ -542,6 +542,7 @@ struct mqd_update_info {
} cu_mask;
};
enum mqd_update_flag update_flag;
+ bool gws;
};
/**
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
index 43eff221eae5..5416a110ced9 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
@@ -95,6 +95,7 @@ void kfd_process_dequeue_from_device(struct
kfd_process_device *pdd)
int pqm_set_gws(struct process_queue_manager *pqm, unsigned int qid,
void *gws)
{
+ struct mqd_update_info minfo = {0};
struct kfd_node *dev = NULL;
struct process_queue_node *pqn;
struct kfd_process_device *pdd;
@@ -146,9 +147,10 @@ int pqm_set_gws(struct process_queue_manager *pqm,
unsigned int qid,
}
pdd->qpd.num_gws = gws ? dev->adev->gds.gws_size : 0;
+ minfo.gws = !!gws;
return pqn->q->device->dqm->ops.update_queue(pqn->q->device->dqm,
- pqn->q, NULL);
+ pqn->q, &minfo);
}
void kfd_process_dequeue_from_all_devices(struct kfd_process *p)
--
2.34.1
[PATCH v4 3/3] drm: Drop unneeded selects in DRM drivers
All of the selects on ACPI_VIDEO are unnecessary when DRM does the select for ACPI_VIDEO as it provides a helper for acpi based EDID. Reviewed-by: Pranjal Ramajor Asha Kanojiya Signed-off-by: Mario Limonciello --- drivers/gpu/drm/amd/amdgpu/Kconfig | 7 --- drivers/gpu/drm/gma500/Kconfig | 6 -- drivers/gpu/drm/i915/Kconfig | 7 --- drivers/gpu/drm/nouveau/Kconfig| 4 drivers/gpu/drm/radeon/Kconfig | 7 --- drivers/gpu/drm/xe/Kconfig | 6 -- 6 files changed, 37 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/Kconfig b/drivers/gpu/drm/amd/amdgpu/Kconfig index 22d88f8ef527..b2178a5a947c 100644 --- a/drivers/gpu/drm/amd/amdgpu/Kconfig +++ b/drivers/gpu/drm/amd/amdgpu/Kconfig @@ -22,13 +22,6 @@ config DRM_AMDGPU select DRM_BUDDY select DRM_SUBALLOC_HELPER select DRM_EXEC - # amdgpu depends on ACPI_VIDEO when ACPI is enabled, for select to work - # ACPI_VIDEO's dependencies must also be selected. - select INPUT if ACPI - select ACPI_VIDEO if ACPI - # On x86 ACPI_VIDEO also needs ACPI_WMI - select X86_PLATFORM_DEVICES if ACPI && X86 - select ACPI_WMI if ACPI && X86 help Choose this option if you have a recent AMD Radeon graphics card. diff --git a/drivers/gpu/drm/gma500/Kconfig b/drivers/gpu/drm/gma500/Kconfig index efb4a2dd2f80..6921ef67b256 100644 --- a/drivers/gpu/drm/gma500/Kconfig +++ b/drivers/gpu/drm/gma500/Kconfig @@ -6,12 +6,6 @@ config DRM_GMA500 select FB_IOMEM_HELPERS if DRM_FBDEV_EMULATION select I2C select I2C_ALGOBIT - # GMA500 depends on ACPI_VIDEO when ACPI is enabled, just like i915 - select ACPI_VIDEO if ACPI - select BACKLIGHT_CLASS_DEVICE if ACPI - select INPUT if ACPI - select X86_PLATFORM_DEVICES if ACPI - select ACPI_WMI if ACPI help Say yes for an experimental 2D KMS framebuffer driver for the Intel GMA500 (Poulsbo), Intel GMA600 (Moorestown/Oak Trail) and diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig index b5d6e3352071..476da09433bb 100644 --- a/drivers/gpu/drm/i915/Kconfig +++ b/drivers/gpu/drm/i915/Kconfig @@ -22,13 +22,6 @@ config DRM_I915 select I2C select I2C_ALGOBIT select IRQ_WORK - # i915 depends on ACPI_VIDEO when ACPI is enabled - # but for select to work, need to select ACPI_VIDEO's dependencies, ick - select BACKLIGHT_CLASS_DEVICE if ACPI - select INPUT if ACPI - select X86_PLATFORM_DEVICES if ACPI - select ACPI_WMI if ACPI - select ACPI_VIDEO if ACPI select ACPI_BUTTON if ACPI select SYNC_FILE select IOSF_MBI if X86 diff --git a/drivers/gpu/drm/nouveau/Kconfig b/drivers/gpu/drm/nouveau/Kconfig index 1e6aaf95ff7c..61f531abd3e3 100644 --- a/drivers/gpu/drm/nouveau/Kconfig +++ b/drivers/gpu/drm/nouveau/Kconfig @@ -20,11 +20,7 @@ config DRM_NOUVEAU select ACPI_WMI if ACPI && X86 select MXM_WMI if ACPI && X86 select POWER_SUPPLY - # Similar to i915, we need to select ACPI_VIDEO and it's dependencies - select BACKLIGHT_CLASS_DEVICE if ACPI && X86 - select INPUT if ACPI && X86 select THERMAL if ACPI && X86 - select ACPI_VIDEO if ACPI && X86 select SND_HDA_COMPONENT if SND_HDA_CORE help Choose this option for open-source NVIDIA support. diff --git a/drivers/gpu/drm/radeon/Kconfig b/drivers/gpu/drm/radeon/Kconfig index f98356be0af2..12149d594100 100644 --- a/drivers/gpu/drm/radeon/Kconfig +++ b/drivers/gpu/drm/radeon/Kconfig @@ -19,13 +19,6 @@ config DRM_RADEON select INTERVAL_TREE select I2C select I2C_ALGOBIT - # radeon depends on ACPI_VIDEO when ACPI is enabled, for select to work - # ACPI_VIDEO's dependencies must also be selected. - select INPUT if ACPI - select ACPI_VIDEO if ACPI - # On x86 ACPI_VIDEO also needs ACPI_WMI - select X86_PLATFORM_DEVICES if ACPI && X86 - select ACPI_WMI if ACPI && X86 help Choose this option if you have an ATI Radeon graphics card. There are both PCI and AGP versions. You don't need to choose this to diff --git a/drivers/gpu/drm/xe/Kconfig b/drivers/gpu/drm/xe/Kconfig index e36ae1f0d885..cf60bdcafb0c 100644 --- a/drivers/gpu/drm/xe/Kconfig +++ b/drivers/gpu/drm/xe/Kconfig @@ -19,13 +19,7 @@ config DRM_XE select DRM_MIPI_DSI select RELAY select IRQ_WORK - # xe depends on ACPI_VIDEO when ACPI is enabled - # but for select to work, need to select ACPI_VIDEO's dependencies, ick - select BACKLIGHT_CLASS_DEVICE if ACPI - select INPUT if ACPI - select ACPI_VIDEO if X86 && ACPI select ACPI_BUTTON if ACPI - select ACPI_WMI if X86 && ACPI select SYNC_FILE select IOSF_MBI select CRC32 -- 2.34.1
[PATCH v4 1/3] drm: Add drm_get_acpi_edid() helper
Some manufacturers have intentionally put an EDID that differs from
the EDID on the internal panel on laptops. Drivers can call this
helper to attempt to fetch the EDID from the BIOS's ACPI _DDC method.
Signed-off-by: Mario Limonciello
---
drivers/gpu/drm/Kconfig| 5 +++
drivers/gpu/drm/drm_edid.c | 77 ++
include/drm/drm_edid.h | 1 +
3 files changed, 83 insertions(+)
diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index 6ec33d36f3a4..ec2bb71e8b36 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -21,6 +21,11 @@ menuconfig DRM
select KCMP
select VIDEO_CMDLINE
select VIDEO_NOMODESET
+ select ACPI_VIDEO if ACPI
+ select BACKLIGHT_CLASS_DEVICE if ACPI
+ select INPUT if ACPI
+ select X86_PLATFORM_DEVICES if ACPI && X86
+ select ACPI_WMI if ACPI && X86
help
Kernel-level support for the Direct Rendering Infrastructure (DRI)
introduced in XFree86 4.0. If you say Y here, you need to select
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 923c4423151c..c649b4f9fd8e 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -28,6 +28,7 @@
* DEALINGS IN THE SOFTWARE.
*/
+#include
#include
#include
#include
@@ -2188,6 +2189,49 @@ drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int
block, size_t len)
return ret == xfers ? 0 : -1;
}
+/**
+ * drm_do_probe_acpi_edid() - get EDID information via ACPI _DDC
+ * @data: struct drm_device
+ * @buf: EDID data buffer to be filled
+ * @block: 128 byte EDID block to start fetching from
+ * @len: EDID data buffer length to fetch
+ *
+ * Try to fetch EDID information by calling acpi_video_get_edid() function.
+ *
+ * Return: 0 on success or error code on failure.
+ */
+static int
+drm_do_probe_acpi_edid(void *data, u8 *buf, unsigned int block, size_t len)
+{
+ struct drm_device *ddev = data;
+ struct acpi_device *acpidev = ACPI_COMPANION(ddev->dev);
+ unsigned char start = block * EDID_LENGTH;
+ void *edid;
+ int r;
+
+ if (!acpidev)
+ return -ENODEV;
+
+ /* fetch the entire edid from BIOS */
+ r = acpi_video_get_edid(acpidev, ACPI_VIDEO_DISPLAY_LCD, -1, &edid);
+ if (r < 0) {
+ DRM_DEBUG_KMS("Failed to get EDID from ACPI: %d\n", r);
+ return -EINVAL;
+ }
+ if (len > r || start > r || start + len > r) {
+ r = -EINVAL;
+ goto cleanup;
+ }
+
+ memcpy(buf, edid + start, len);
+ r = 0;
+
+cleanup:
+ kfree(edid);
+
+ return r;
+}
+
static void connector_bad_edid(struct drm_connector *connector,
const struct edid *edid, int num_blocks)
{
@@ -2643,6 +2687,39 @@ struct edid *drm_get_edid(struct drm_connector
*connector,
}
EXPORT_SYMBOL(drm_get_edid);
+/**
+ * drm_get_acpi_edid - get EDID data, if available
+ * @connector: connector we're probing
+ *
+ * Use the BIOS to attempt to grab EDID data if possible.
+ *
+ * The returned pointer must be freed using drm_edid_free().
+ *
+ * Return: Pointer to valid EDID or NULL if we couldn't find any.
+ */
+const struct drm_edid *drm_get_acpi_edid(struct drm_connector *connector)
+{
+ const struct drm_edid *drm_edid;
+
+ switch (connector->connector_type) {
+ case DRM_MODE_CONNECTOR_LVDS:
+ case DRM_MODE_CONNECTOR_eDP:
+ break;
+ default:
+ return NULL;
+ }
+
+ if (connector->force == DRM_FORCE_OFF)
+ return NULL;
+
+ drm_edid = drm_edid_read_custom(connector, drm_do_probe_acpi_edid,
connector->dev);
+
+ /* Note: Do *not* call connector updates here. */
+
+ return drm_edid;
+}
+EXPORT_SYMBOL(drm_get_acpi_edid);
+
/**
* drm_edid_read_custom - Read EDID data using given EDID block read function
* @connector: Connector to use
diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h
index 7923bc00dc7a..ca41be289fc6 100644
--- a/include/drm/drm_edid.h
+++ b/include/drm/drm_edid.h
@@ -410,6 +410,7 @@ struct edid *drm_do_get_edid(struct drm_connector
*connector,
void *data);
struct edid *drm_get_edid(struct drm_connector *connector,
struct i2c_adapter *adapter);
+const struct drm_edid *drm_get_acpi_edid(struct drm_connector *connector);
u32 drm_edid_get_panel_id(struct i2c_adapter *adapter);
struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
struct i2c_adapter *adapter);
--
2.34.1
[PATCH v4 2/3] drm/nouveau: Use drm_get_acpi_edid() helper
Rather than inventing a wrapper to acpi_video_get_edid() use the
one provided by drm. This fixes two problems:
1. A memory leak that the memory provided by the ACPI call was
never freed.
2. Validation of the BIOS provided blob.
Convert the usage in nouveau_connector_detect_lvds() to use
struct drm_edid at the same time.
Signed-off-by: Mario Limonciello
---
drivers/gpu/drm/nouveau/nouveau_acpi.c | 27 -
drivers/gpu/drm/nouveau/nouveau_acpi.h | 2 --
drivers/gpu/drm/nouveau/nouveau_connector.c | 20 +++
3 files changed, 9 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/nouveau_acpi.c
b/drivers/gpu/drm/nouveau/nouveau_acpi.c
index 8f0c69aad248..de9daafb3fbb 100644
--- a/drivers/gpu/drm/nouveau/nouveau_acpi.c
+++ b/drivers/gpu/drm/nouveau/nouveau_acpi.c
@@ -360,33 +360,6 @@ void nouveau_unregister_dsm_handler(void) {}
void nouveau_switcheroo_optimus_dsm(void) {}
#endif
-void *
-nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector)
-{
- struct acpi_device *acpidev;
- int type, ret;
- void *edid;
-
- switch (connector->connector_type) {
- case DRM_MODE_CONNECTOR_LVDS:
- case DRM_MODE_CONNECTOR_eDP:
- type = ACPI_VIDEO_DISPLAY_LCD;
- break;
- default:
- return NULL;
- }
-
- acpidev = ACPI_COMPANION(dev->dev);
- if (!acpidev)
- return NULL;
-
- ret = acpi_video_get_edid(acpidev, type, -1, &edid);
- if (ret < 0)
- return NULL;
-
- return kmemdup(edid, EDID_LENGTH, GFP_KERNEL);
-}
-
bool nouveau_acpi_video_backlight_use_native(void)
{
return acpi_video_backlight_use_native();
diff --git a/drivers/gpu/drm/nouveau/nouveau_acpi.h
b/drivers/gpu/drm/nouveau/nouveau_acpi.h
index e39dd8b94b8b..6a3def8e6cca 100644
--- a/drivers/gpu/drm/nouveau/nouveau_acpi.h
+++ b/drivers/gpu/drm/nouveau/nouveau_acpi.h
@@ -10,7 +10,6 @@ bool nouveau_is_v1_dsm(void);
void nouveau_register_dsm_handler(void);
void nouveau_unregister_dsm_handler(void);
void nouveau_switcheroo_optimus_dsm(void);
-void *nouveau_acpi_edid(struct drm_device *, struct drm_connector *);
bool nouveau_acpi_video_backlight_use_native(void);
void nouveau_acpi_video_register_backlight(void);
#else
@@ -19,7 +18,6 @@ static inline bool nouveau_is_v1_dsm(void) { return false; };
static inline void nouveau_register_dsm_handler(void) {}
static inline void nouveau_unregister_dsm_handler(void) {}
static inline void nouveau_switcheroo_optimus_dsm(void) {}
-static inline void *nouveau_acpi_edid(struct drm_device *dev, struct
drm_connector *connector) { return NULL; }
static inline bool nouveau_acpi_video_backlight_use_native(void) { return
true; }
static inline void nouveau_acpi_video_register_backlight(void) {}
#endif
diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c
b/drivers/gpu/drm/nouveau/nouveau_connector.c
index 856b3ef5edb8..4c47d231c65e 100644
--- a/drivers/gpu/drm/nouveau/nouveau_connector.c
+++ b/drivers/gpu/drm/nouveau/nouveau_connector.c
@@ -687,7 +687,7 @@ nouveau_connector_detect_lvds(struct drm_connector
*connector, bool force)
struct nouveau_drm *drm = nouveau_drm(dev);
struct nouveau_connector *nv_connector = nouveau_connector(connector);
struct nouveau_encoder *nv_encoder = NULL;
- struct edid *edid = NULL;
+ const struct drm_edid *drm_edid = NULL;
enum drm_connector_status status = connector_status_disconnected;
nv_encoder = find_encoder(connector, DCB_OUTPUT_LVDS);
@@ -698,7 +698,7 @@ nouveau_connector_detect_lvds(struct drm_connector
*connector, bool force)
if (!drm->vbios.fp_no_ddc) {
status = nouveau_connector_detect(connector, force);
if (status == connector_status_connected) {
- edid = nv_connector->edid;
+ drm_edid = drm_edid_alloc(nv_connector->edid,
EDID_LENGTH);
goto out;
}
}
@@ -713,8 +713,8 @@ nouveau_connector_detect_lvds(struct drm_connector
*connector, bool force)
* valid - it's not (rh#613284)
*/
if (nv_encoder->dcb->lvdsconf.use_acpi_for_edid) {
- edid = nouveau_acpi_edid(dev, connector);
- if (edid) {
+ drm_edid = drm_get_acpi_edid(connector);
+ if (drm_edid) {
status = connector_status_connected;
goto out;
}
@@ -734,12 +734,9 @@ nouveau_connector_detect_lvds(struct drm_connector
*connector, bool force)
* stored for the panel stored in them.
*/
if (!drm->vbios.fp_no_ddc) {
- edid = (struct edid *)nouveau_bios_embedded_edid(dev);
- if (edid) {
- edid = kmemdup(edid, EDID_LENGTH, GFP_KERNEL);
- if (edid)
- status = c
[PATCH v4 0/3] Add drm_get_acpi_edid() helper
The drm_get_acpi_edid() helper is for drivers that would prefer to get the EDID from ACPI instead of from the panel. Earlier versions of this series were aimed at using this in amdgpu and nouveau. This version does NOT update amdgpu as the change will require a larger overhaul to use struct drm_edid. There will be a follow up patch to amdgpu after Melissa Wen finishes that effort [2]. https://lore.kernel.org/dri-devel/20240201221119.42564-1-mario.limoncie...@amd.com/ [1] https://lore.kernel.org/amd-gfx/20240126163429.56714-1-m...@igalia.com/ [2] Mario Limonciello (3): drm: Add drm_get_acpi_edid() helper drm/nouveau: Use drm_get_acpi_edid() helper drm: Drop unneeded selects in DRM drivers drivers/gpu/drm/Kconfig | 5 ++ drivers/gpu/drm/amd/amdgpu/Kconfig | 7 -- drivers/gpu/drm/drm_edid.c | 77 + drivers/gpu/drm/gma500/Kconfig | 6 -- drivers/gpu/drm/i915/Kconfig| 7 -- drivers/gpu/drm/nouveau/Kconfig | 4 -- drivers/gpu/drm/nouveau/nouveau_acpi.c | 27 drivers/gpu/drm/nouveau/nouveau_acpi.h | 2 - drivers/gpu/drm/nouveau/nouveau_connector.c | 20 +++--- drivers/gpu/drm/radeon/Kconfig | 7 -- drivers/gpu/drm/xe/Kconfig | 6 -- include/drm/drm_edid.h | 1 + 12 files changed, 92 insertions(+), 77 deletions(-) -- 2.34.1
Re: [PATCH v2 2/2] drm/amd: Stop evicting resources on APUs in suspend
On Wed, Feb 7, 2024 at 5:36 PM Mario Limonciello
wrote:
>
> On 2/7/2024 16:34, Alex Deucher wrote:
> > On Wed, Feb 7, 2024 at 3:48 PM Mario Limonciello
> > wrote:
> >>
> >> commit 5095d5418193 ("drm/amd: Evict resources during PM ops prepare()
> >> callback")
> >> intentionally moved the eviction of resources to earlier in the suspend
> >> process, but this introduced a subtle change that it occurs before
> >> adev->in_s0ix
> >> or adev->in_s3 are set. This meant that APUs actually started to evict
> >> resources at suspend time as well.
> >>
> >> Add a new `in_prepare` flag that is set for the life of the prepare()
> >> callback
> >> to return the old code flow. Drop the existing call to return 1 in this
> >> case because
> >> the suspend() callback looks for the flags too.
> >>
> >> Also, introduce a new amdgpu_device_freeze() function to call at S4 and
> >> evict
> >> resources in this callback so that APUs will still get resources evicted.
> >>
> >> Reported-by: Jürg Billeter
> >> Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3132#note_2271038
> >> Fixes: 5095d5418193 ("drm/amd: Evict resources during PM ops prepare()
> >> callback")
> >> Signed-off-by: Mario Limonciello
> >> ---
> >> v1->v2:
> >> * Add and use new in_prepare member
> >> ---
> >> drivers/gpu/drm/amd/amdgpu/amdgpu.h| 4 +-
> >> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 46 --
> >> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c| 21 ++
> >> 3 files changed, 48 insertions(+), 23 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> >> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> >> index 5d5be3e20687..f9db09a9017a 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> >> @@ -1075,7 +1075,8 @@ struct amdgpu_device {
> >> u8
> >> reset_magic[AMDGPU_RESET_MAGIC_NUM];
> >>
> >> /* s3/s4 mask */
> >> - boolin_suspend;
> >> + boolin_prepare;
> >> + boolin_suspend;
> >> boolin_s3;
> >> boolin_s4;
> >> boolin_s0ix;
> >> @@ -1462,6 +1463,7 @@ int amdgpu_device_ip_suspend(struct amdgpu_device
> >> *adev);
> >> int amdgpu_device_prepare(struct drm_device *dev);
> >> int amdgpu_device_suspend(struct drm_device *dev, bool fbcon);
> >> int amdgpu_device_resume(struct drm_device *dev, bool fbcon);
> >> +int amdgpu_device_freeze(struct drm_device *drm_dev);
> >> u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc);
> >> int amdgpu_enable_vblank_kms(struct drm_crtc *crtc);
> >> void amdgpu_disable_vblank_kms(struct drm_crtc *crtc);
> >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> >> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> >> index 2bc460cb993d..0a337fcd89b4 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> >> @@ -4492,7 +4492,7 @@ static int amdgpu_device_evict_resources(struct
> >> amdgpu_device *adev)
> >> int ret;
> >>
> >> /* No need to evict vram on APUs for suspend to ram or s2idle */
> >> - if ((adev->in_s3 || adev->in_s0ix) && (adev->flags & AMD_IS_APU))
> >> + if ((adev->in_prepare) && (adev->flags & AMD_IS_APU))
> >
> > Could probably simplify this to:
> > if ((!adev->in_s4) && (adev->flags & AMD_IS_APU))
> >
> > Then you could drop the in_prepare variable.
> >
> >> return 0;
> >>
> >> ret = amdgpu_ttm_evict_resources(adev, TTM_PL_VRAM);
> >> @@ -4521,10 +4521,12 @@ int amdgpu_device_prepare(struct drm_device *dev)
> >> if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
> >> return 0;
> >>
> >> + adev->in_prepare = true;
> >> +
> >> /* Evict the majority of BOs before starting suspend sequence */
> >> r = amdgpu_device_evict_resources(adev);
> >> if (r)
> >> - return r;
> >> + goto unprepare;
> >>
> >> for (i = 0; i < adev->num_ip_blocks; i++) {
> >> if (!adev->ip_blocks[i].status.valid)
> >> @@ -4533,10 +4535,46 @@ int amdgpu_device_prepare(struct drm_device *dev)
> >> continue;
> >> r =
> >> adev->ip_blocks[i].version->funcs->prepare_suspend((void *)adev);
> >> if (r)
> >> - return r;
> >> + goto unprepare;
> >> }
> >>
> >> - return 0;
> >> +unprepare:
> >> + adev->in_prepare = FALSE;
> >> +
> >> + return r;
> >> +}
> >> +
> >> +/**
> >> + * amdgpu_device_freeze - run S4 sequence
> >> + *
> >> + * @dev: drm dev pointer
> >> + *
> >> + * Prepare to put the hw in the S4 state (all asics).
> >> + * Returns 0 for success or an error on failure.
> >> + * Called at d
Re: [PATCH v2 1/2] Revert "drm/amd: flush any delayed gfxoff on suspend entry"
On Wed, Feb 7, 2024 at 4:18 PM Mario Limonciello
wrote:
>
> commit ab4750332dbe ("drm/amdgpu/sdma5.2: add begin/end_use ring callbacks")
> caused GFXOFF control to be used more heavily and the codepath that was
> removed from commit 0dee72639533 ("drm/amd: flush any delayed gfxoff on
> suspend entry") now can be exercised at suspend again.
>
> Users report that by using GNOME to suspend the lockscreen trigger will
> cause SDMA traffic and the system can deadlock.
>
> This reverts commit 0dee726395333fea833eaaf838bc80962df886c8.
>
> Fixes: ab4750332dbe ("drm/amdgpu/sdma5.2: add begin/end_use ring callbacks")
> Signed-off-by: Mario Limonciello
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 -
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c| 9 -
> 2 files changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 670ecb789d59..2bc460cb993d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -4573,7 +4573,6 @@ int amdgpu_device_suspend(struct drm_device *dev, bool
> fbcon)
>
> drm_fb_helper_set_suspend_unlocked(adev_to_drm(adev)->fb_helper, true);
>
> cancel_delayed_work_sync(&adev->delayed_init_work);
> - flush_delayed_work(&adev->gfx.gfx_off_delay_work);
>
> amdgpu_ras_suspend(adev);
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> index aa8e1d29d10a..9831dd854532 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> @@ -727,8 +727,15 @@ void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev,
> bool enable)
>
> if (adev->gfx.gfx_off_req_count == 0 &&
> !adev->gfx.gfx_off_state) {
> - schedule_delayed_work(&adev->gfx.gfx_off_delay_work,
> + /* If going to s2idle, no need to wait */
> + if (adev->in_s0ix) {
> + if (!amdgpu_dpm_set_powergating_by_smu(adev,
> + AMD_IP_BLOCK_TYPE_GFX, true))
> + adev->gfx.gfx_off_state = true;
> + } else {
> +
> schedule_delayed_work(&adev->gfx.gfx_off_delay_work,
> delay);
> + }
> }
> } else {
> if (adev->gfx.gfx_off_req_count == 0) {
> --
> 2.34.1
>
Re: [PATCH v2 2/2] drm/amd: Stop evicting resources on APUs in suspend
On 2/7/2024 16:34, Alex Deucher wrote:
On Wed, Feb 7, 2024 at 3:48 PM Mario Limonciello
wrote:
commit 5095d5418193 ("drm/amd: Evict resources during PM ops prepare()
callback")
intentionally moved the eviction of resources to earlier in the suspend
process, but this introduced a subtle change that it occurs before adev->in_s0ix
or adev->in_s3 are set. This meant that APUs actually started to evict
resources at suspend time as well.
Add a new `in_prepare` flag that is set for the life of the prepare() callback
to return the old code flow. Drop the existing call to return 1 in this case
because
the suspend() callback looks for the flags too.
Also, introduce a new amdgpu_device_freeze() function to call at S4 and evict
resources in this callback so that APUs will still get resources evicted.
Reported-by: Jürg Billeter
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3132#note_2271038
Fixes: 5095d5418193 ("drm/amd: Evict resources during PM ops prepare()
callback")
Signed-off-by: Mario Limonciello
---
v1->v2:
* Add and use new in_prepare member
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 4 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 46 --
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c| 21 ++
3 files changed, 48 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 5d5be3e20687..f9db09a9017a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1075,7 +1075,8 @@ struct amdgpu_device {
u8 reset_magic[AMDGPU_RESET_MAGIC_NUM];
/* s3/s4 mask */
- boolin_suspend;
+ boolin_prepare;
+ boolin_suspend;
boolin_s3;
boolin_s4;
boolin_s0ix;
@@ -1462,6 +1463,7 @@ int amdgpu_device_ip_suspend(struct amdgpu_device *adev);
int amdgpu_device_prepare(struct drm_device *dev);
int amdgpu_device_suspend(struct drm_device *dev, bool fbcon);
int amdgpu_device_resume(struct drm_device *dev, bool fbcon);
+int amdgpu_device_freeze(struct drm_device *drm_dev);
u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc);
int amdgpu_enable_vblank_kms(struct drm_crtc *crtc);
void amdgpu_disable_vblank_kms(struct drm_crtc *crtc);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 2bc460cb993d..0a337fcd89b4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -4492,7 +4492,7 @@ static int amdgpu_device_evict_resources(struct
amdgpu_device *adev)
int ret;
/* No need to evict vram on APUs for suspend to ram or s2idle */
- if ((adev->in_s3 || adev->in_s0ix) && (adev->flags & AMD_IS_APU))
+ if ((adev->in_prepare) && (adev->flags & AMD_IS_APU))
Could probably simplify this to:
if ((!adev->in_s4) && (adev->flags & AMD_IS_APU))
Then you could drop the in_prepare variable.
return 0;
ret = amdgpu_ttm_evict_resources(adev, TTM_PL_VRAM);
@@ -4521,10 +4521,12 @@ int amdgpu_device_prepare(struct drm_device *dev)
if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
return 0;
+ adev->in_prepare = true;
+
/* Evict the majority of BOs before starting suspend sequence */
r = amdgpu_device_evict_resources(adev);
if (r)
- return r;
+ goto unprepare;
for (i = 0; i < adev->num_ip_blocks; i++) {
if (!adev->ip_blocks[i].status.valid)
@@ -4533,10 +4535,46 @@ int amdgpu_device_prepare(struct drm_device *dev)
continue;
r = adev->ip_blocks[i].version->funcs->prepare_suspend((void
*)adev);
if (r)
- return r;
+ goto unprepare;
}
- return 0;
+unprepare:
+ adev->in_prepare = FALSE;
+
+ return r;
+}
+
+/**
+ * amdgpu_device_freeze - run S4 sequence
+ *
+ * @dev: drm dev pointer
+ *
+ * Prepare to put the hw in the S4 state (all asics).
+ * Returns 0 for success or an error on failure.
+ * Called at driver freeze.
+ */
+int amdgpu_device_freeze(struct drm_device *drm_dev)
+{
+ struct amdgpu_device *adev = drm_to_adev(drm_dev);
+ int r;
+
+ adev->in_s4 = true;
+
+ r = amdgpu_device_evict_resources(adev);
Won't this be too late to allocate memory? Doesn't this need to
happen in prepare() even for S4?
Hmm; possibly. I'll swap it back with your other suggestion.
Thanks
Alex
+ if (r)
+ goto cleanup;
+
+ r = amdgpu_device_suspend(drm_dev, true);
+ if (r)
+ goto cleanup;
+
+ if (amdgpu_acpi_should_gpu_reset(adev))
+ r = amdgpu_asi
Re: [PATCH v2 2/2] drm/amd: Stop evicting resources on APUs in suspend
On Wed, Feb 7, 2024 at 3:48 PM Mario Limonciello
wrote:
>
> commit 5095d5418193 ("drm/amd: Evict resources during PM ops prepare()
> callback")
> intentionally moved the eviction of resources to earlier in the suspend
> process, but this introduced a subtle change that it occurs before
> adev->in_s0ix
> or adev->in_s3 are set. This meant that APUs actually started to evict
> resources at suspend time as well.
>
> Add a new `in_prepare` flag that is set for the life of the prepare() callback
> to return the old code flow. Drop the existing call to return 1 in this case
> because
> the suspend() callback looks for the flags too.
>
> Also, introduce a new amdgpu_device_freeze() function to call at S4 and evict
> resources in this callback so that APUs will still get resources evicted.
>
> Reported-by: Jürg Billeter
> Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3132#note_2271038
> Fixes: 5095d5418193 ("drm/amd: Evict resources during PM ops prepare()
> callback")
> Signed-off-by: Mario Limonciello
> ---
> v1->v2:
> * Add and use new in_prepare member
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h| 4 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 46 --
> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c| 21 ++
> 3 files changed, 48 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 5d5be3e20687..f9db09a9017a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -1075,7 +1075,8 @@ struct amdgpu_device {
> u8 reset_magic[AMDGPU_RESET_MAGIC_NUM];
>
> /* s3/s4 mask */
> - boolin_suspend;
> + boolin_prepare;
> + boolin_suspend;
> boolin_s3;
> boolin_s4;
> boolin_s0ix;
> @@ -1462,6 +1463,7 @@ int amdgpu_device_ip_suspend(struct amdgpu_device
> *adev);
> int amdgpu_device_prepare(struct drm_device *dev);
> int amdgpu_device_suspend(struct drm_device *dev, bool fbcon);
> int amdgpu_device_resume(struct drm_device *dev, bool fbcon);
> +int amdgpu_device_freeze(struct drm_device *drm_dev);
> u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc);
> int amdgpu_enable_vblank_kms(struct drm_crtc *crtc);
> void amdgpu_disable_vblank_kms(struct drm_crtc *crtc);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 2bc460cb993d..0a337fcd89b4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -4492,7 +4492,7 @@ static int amdgpu_device_evict_resources(struct
> amdgpu_device *adev)
> int ret;
>
> /* No need to evict vram on APUs for suspend to ram or s2idle */
> - if ((adev->in_s3 || adev->in_s0ix) && (adev->flags & AMD_IS_APU))
> + if ((adev->in_prepare) && (adev->flags & AMD_IS_APU))
Could probably simplify this to:
if ((!adev->in_s4) && (adev->flags & AMD_IS_APU))
Then you could drop the in_prepare variable.
> return 0;
>
> ret = amdgpu_ttm_evict_resources(adev, TTM_PL_VRAM);
> @@ -4521,10 +4521,12 @@ int amdgpu_device_prepare(struct drm_device *dev)
> if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
> return 0;
>
> + adev->in_prepare = true;
> +
> /* Evict the majority of BOs before starting suspend sequence */
> r = amdgpu_device_evict_resources(adev);
> if (r)
> - return r;
> + goto unprepare;
>
> for (i = 0; i < adev->num_ip_blocks; i++) {
> if (!adev->ip_blocks[i].status.valid)
> @@ -4533,10 +4535,46 @@ int amdgpu_device_prepare(struct drm_device *dev)
> continue;
> r = adev->ip_blocks[i].version->funcs->prepare_suspend((void
> *)adev);
> if (r)
> - return r;
> + goto unprepare;
> }
>
> - return 0;
> +unprepare:
> + adev->in_prepare = FALSE;
> +
> + return r;
> +}
> +
> +/**
> + * amdgpu_device_freeze - run S4 sequence
> + *
> + * @dev: drm dev pointer
> + *
> + * Prepare to put the hw in the S4 state (all asics).
> + * Returns 0 for success or an error on failure.
> + * Called at driver freeze.
> + */
> +int amdgpu_device_freeze(struct drm_device *drm_dev)
> +{
> + struct amdgpu_device *adev = drm_to_adev(drm_dev);
> + int r;
> +
> + adev->in_s4 = true;
> +
> + r = amdgpu_device_evict_resources(adev);
Won't this be too late to allocate memory? Doesn't this need to
happen in prepare() even for S4?
Alex
> + if (r)
> + goto cleanup;
> +
> + r = amdgpu_device_suspend(drm_dev, true);
> + if (r)
> + goto cl
[PATCH AUTOSEL 6.1 16/29] drm/amd/display: increased min_dcfclk_mhz and min_fclk_mhz
From: Sohaib Nadeem
[ Upstream commit 2ff33c759a4247c84ec0b7815f1f223e155ba82a ]
[why]
Originally, PMFW said min FCLK is 300Mhz, but min DCFCLK can be increased
to 400Mhz because min FCLK is now 600Mhz so FCLK >= 1.5 * DCFCLK hardware
requirement will still be satisfied. Increasing min DCFCLK addresses
underflow issues (underflow occurs when phantom pipe is turned on for some
Sub-Viewport configs).
[how]
Increasing DCFCLK by raising the min_dcfclk_mhz
Reviewed-by: Chaitanya Dhere
Reviewed-by: Alvin Lee
Acked-by: Tom Chung
Signed-off-by: Sohaib Nadeem
Tested-by: Daniel Wheeler
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index 85e0d1c2a908..baecc0ffe758 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -2123,7 +2123,7 @@ static int build_synthetic_soc_states(struct
clk_bw_params *bw_params,
unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz =
0,
max_phyclk_mhz = 0, max_dtbclk_mhz = 0, max_fclk_mhz =
0, max_uclk_mhz = 0;
- unsigned int min_dcfclk_mhz = 199, min_fclk_mhz = 299;
+ unsigned int min_dcfclk_mhz = 399, min_fclk_mhz = 599;
static const unsigned int num_dcfclk_stas = 5;
unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906,
1324, 1564};
--
2.43.0
[PATCH AUTOSEL 6.6 23/38] drm/amd/display: increased min_dcfclk_mhz and min_fclk_mhz
From: Sohaib Nadeem
[ Upstream commit 2ff33c759a4247c84ec0b7815f1f223e155ba82a ]
[why]
Originally, PMFW said min FCLK is 300Mhz, but min DCFCLK can be increased
to 400Mhz because min FCLK is now 600Mhz so FCLK >= 1.5 * DCFCLK hardware
requirement will still be satisfied. Increasing min DCFCLK addresses
underflow issues (underflow occurs when phantom pipe is turned on for some
Sub-Viewport configs).
[how]
Increasing DCFCLK by raising the min_dcfclk_mhz
Reviewed-by: Chaitanya Dhere
Reviewed-by: Alvin Lee
Acked-by: Tom Chung
Signed-off-by: Sohaib Nadeem
Tested-by: Daniel Wheeler
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index cf3b400c8619..ec09d5a8876b 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -2452,7 +2452,7 @@ static int build_synthetic_soc_states(bool
disable_dc_mode_overwrite, struct clk
struct _vcs_dpi_voltage_scaling_st entry = {0};
struct clk_limit_table_entry max_clk_data = {0};
- unsigned int min_dcfclk_mhz = 199, min_fclk_mhz = 299;
+ unsigned int min_dcfclk_mhz = 399, min_fclk_mhz = 599;
static const unsigned int num_dcfclk_stas = 5;
unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906,
1324, 1564};
--
2.43.0
[PATCH AUTOSEL 6.6 22/38] drm/amdkfd: Use correct drm device for cgroup permission check
From: Mukul Joshi
[ Upstream commit 4119734e06a7f30e7e8eb92a58b85dca0269 ]
On GFX 9.4.3, for a given KFD node, fetch the correct drm device from
XCP manager when checking for cgroup permissions.
Signed-off-by: Mukul Joshi
Reviewed-by: Harish Kasiviswanathan
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
index 3287a3961395..12ee273e87e1 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
@@ -1482,10 +1482,15 @@ void kfd_dec_compute_active(struct kfd_node *dev);
/* Cgroup Support */
/* Check with device cgroup if @kfd device is accessible */
-static inline int kfd_devcgroup_check_permission(struct kfd_node *kfd)
+static inline int kfd_devcgroup_check_permission(struct kfd_node *node)
{
#if defined(CONFIG_CGROUP_DEVICE) || defined(CONFIG_CGROUP_BPF)
- struct drm_device *ddev = adev_to_drm(kfd->adev);
+ struct drm_device *ddev;
+
+ if (node->xcp)
+ ddev = node->xcp->ddev;
+ else
+ ddev = adev_to_drm(node->adev);
return devcgroup_check_permission(DEVCG_DEV_CHAR, DRM_MAJOR,
ddev->render->index,
--
2.43.0
[PATCH AUTOSEL 6.7 27/44] drm/amd/display: Fix DPSTREAM CLK on and off sequence
From: Dmytro Laktyushkin
[ Upstream commit 31c2bf25eaf51c2d45f092284a28e97f43b54c15 ]
[Why]
Secondary DP2 display fails to light up in some instances
[How]
Clock needs to be on when DPSTREAMCLK*_EN =1. This change
moves dtbclk_p enable/disable point to make sure this is
the case
Reviewed-by: Charlene Liu
Reviewed-by: Dmytro Laktyushkin
Acked-by: Tom Chung
Signed-off-by: Daniel Miess
Signed-off-by: Dmytro Laktyushkin
Tested-by: Daniel Wheeler
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
.../gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c | 2 +-
.../gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 11 +--
2 files changed, 6 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
index 9b8299d97e40..390d7ebfd8db 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
@@ -1182,9 +1182,9 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx)
dto_params.timing = &pipe_ctx->stream->timing;
dp_hpo_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst;
if (dccg) {
- dccg->funcs->set_dtbclk_dto(dccg, &dto_params);
dccg->funcs->disable_symclk32_se(dccg, dp_hpo_inst);
dccg->funcs->set_dpstreamclk(dccg, REFCLK, tg->inst,
dp_hpo_inst);
+ dccg->funcs->set_dtbclk_dto(dccg, &dto_params);
}
} else if (dccg && dccg->funcs->disable_symclk_se) {
dccg->funcs->disable_symclk_se(dccg,
stream_enc->stream_enc_inst,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
index 608221b0dd5d..780b94592992 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
@@ -2755,18 +2755,17 @@ void dcn20_enable_stream(struct pipe_ctx *pipe_ctx)
}
if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
- dp_hpo_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst;
- dccg->funcs->set_dpstreamclk(dccg, DTBCLK0, tg->inst,
dp_hpo_inst);
-
- phyd32clk = get_phyd32clk_src(link);
- dccg->funcs->enable_symclk32_se(dccg, dp_hpo_inst, phyd32clk);
-
dto_params.otg_inst = tg->inst;
dto_params.pixclk_khz = pipe_ctx->stream->timing.pix_clk_100hz
/ 10;
dto_params.num_odm_segments = get_odm_segment_count(pipe_ctx);
dto_params.timing = &pipe_ctx->stream->timing;
dto_params.ref_dtbclk_khz =
dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(dc->clk_mgr);
dccg->funcs->set_dtbclk_dto(dccg, &dto_params);
+ dp_hpo_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst;
+ dccg->funcs->set_dpstreamclk(dccg, DTBCLK0, tg->inst,
dp_hpo_inst);
+
+ phyd32clk = get_phyd32clk_src(link);
+ dccg->funcs->enable_symclk32_se(dccg, dp_hpo_inst, phyd32clk);
} else {
if (dccg->funcs->enable_symclk_se)
dccg->funcs->enable_symclk_se(dccg,
stream_enc->stream_enc_inst,
--
2.43.0
[PATCH AUTOSEL 6.7 24/44] drm/amdkfd: Use correct drm device for cgroup permission check
From: Mukul Joshi
[ Upstream commit 4119734e06a7f30e7e8eb92a58b85dca0269 ]
On GFX 9.4.3, for a given KFD node, fetch the correct drm device from
XCP manager when checking for cgroup permissions.
Signed-off-by: Mukul Joshi
Reviewed-by: Harish Kasiviswanathan
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
index 28162bfbe1b3..71445ab63b5e 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
@@ -1482,10 +1482,15 @@ void kfd_dec_compute_active(struct kfd_node *dev);
/* Cgroup Support */
/* Check with device cgroup if @kfd device is accessible */
-static inline int kfd_devcgroup_check_permission(struct kfd_node *kfd)
+static inline int kfd_devcgroup_check_permission(struct kfd_node *node)
{
#if defined(CONFIG_CGROUP_DEVICE) || defined(CONFIG_CGROUP_BPF)
- struct drm_device *ddev = adev_to_drm(kfd->adev);
+ struct drm_device *ddev;
+
+ if (node->xcp)
+ ddev = node->xcp->ddev;
+ else
+ ddev = adev_to_drm(node->adev);
return devcgroup_check_permission(DEVCG_DEV_CHAR, DRM_MAJOR,
ddev->render->index,
--
2.43.0
[PATCH AUTOSEL 6.7 25/44] drm/amd/display: increased min_dcfclk_mhz and min_fclk_mhz
From: Sohaib Nadeem
[ Upstream commit 2ff33c759a4247c84ec0b7815f1f223e155ba82a ]
[why]
Originally, PMFW said min FCLK is 300Mhz, but min DCFCLK can be increased
to 400Mhz because min FCLK is now 600Mhz so FCLK >= 1.5 * DCFCLK hardware
requirement will still be satisfied. Increasing min DCFCLK addresses
underflow issues (underflow occurs when phantom pipe is turned on for some
Sub-Viewport configs).
[how]
Increasing DCFCLK by raising the min_dcfclk_mhz
Reviewed-by: Chaitanya Dhere
Reviewed-by: Alvin Lee
Acked-by: Tom Chung
Signed-off-by: Sohaib Nadeem
Tested-by: Daniel Wheeler
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index 92e2ddc9ab7e..67497d7d66d2 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -2719,7 +2719,7 @@ static int build_synthetic_soc_states(bool
disable_dc_mode_overwrite, struct clk
struct _vcs_dpi_voltage_scaling_st entry = {0};
struct clk_limit_table_entry max_clk_data = {0};
- unsigned int min_dcfclk_mhz = 199, min_fclk_mhz = 299;
+ unsigned int min_dcfclk_mhz = 399, min_fclk_mhz = 599;
static const unsigned int num_dcfclk_stas = 5;
unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906,
1324, 1564};
--
2.43.0
[PATCH AUTOSEL 6.7 26/44] drm/amd/display: fix USB-C flag update after enc10 feature init
From: Charlene Liu [ Upstream commit b5abd7f983e14054593dc91d6df2aa5f8cc67652 ] [why] BIOS's integration info table not following the original order which is phy instance is ext_displaypath's array index. [how] Move them to follow the original order. Reviewed-by: Muhammad Ahmed Acked-by: Tom Chung Signed-off-by: Charlene Liu Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin --- drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.c | 4 ++-- drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_link_encoder.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.c index 501388014855..d761b0df2878 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.c @@ -203,12 +203,12 @@ void dcn32_link_encoder_construct( enc10->base.hpd_source = init_data->hpd_source; enc10->base.connector = init_data->connector; - if (enc10->base.connector.id == CONNECTOR_ID_USBC) - enc10->base.features.flags.bits.DP_IS_USB_C = 1; enc10->base.preferred_engine = ENGINE_ID_UNKNOWN; enc10->base.features = *enc_features; + if (enc10->base.connector.id == CONNECTOR_ID_USBC) + enc10->base.features.flags.bits.DP_IS_USB_C = 1; enc10->base.transmitter = init_data->transmitter; diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_link_encoder.c index f91e08895275..3fca3dca61f0 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_link_encoder.c @@ -184,8 +184,6 @@ void dcn35_link_encoder_construct( enc10->base.hpd_source = init_data->hpd_source; enc10->base.connector = init_data->connector; - if (enc10->base.connector.id == CONNECTOR_ID_USBC) - enc10->base.features.flags.bits.DP_IS_USB_C = 1; enc10->base.preferred_engine = ENGINE_ID_UNKNOWN; @@ -240,6 +238,8 @@ void dcn35_link_encoder_construct( } enc10->base.features.flags.bits.HDMI_6GB_EN = 1; + if (enc10->base.connector.id == CONNECTOR_ID_USBC) + enc10->base.features.flags.bits.DP_IS_USB_C = 1; if (bp_funcs->get_connector_speed_cap_info) result = bp_funcs->get_connector_speed_cap_info(enc10->base.ctx->dc_bios, -- 2.43.0
[PATCH 13/15] drm/amd/display: Increase ips2_eval delay for DCN35
From: Nicholas Kazlauskas
[Why]
New worst-case measurement observed at 1897us.
[How]
Increase to 2000us to cover the new worst case + margin.
Reviewed-by: Ovidiu Bunea
Acked-by: Aurabindo Pillai
Signed-off-by: Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
index 28266b9a148a..5d52853cac96 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
@@ -781,7 +781,7 @@ static const struct dc_debug_options debug_defaults_drv = {
.disable_z10 = false,
.ignore_pg = true,
.psp_disabled_wa = true,
- .ips2_eval_delay_us = 1650,
+ .ips2_eval_delay_us = 2000,
.ips2_entry_delay_us = 800,
.disable_dmub_reallow_idle = true,
.static_screen_wait_frames = 2,
--
2.43.0
[PATCH 15/15] drm/amd/display: 3.2.272
From: Aric Cyr Summary: * Revert some changes related to pixel encoding and clocks that cause corruption * IPS hang fix and FGCG enable by default for DCN35 * PSR-SU/Replay fixes * Plane clip size change treated as medium update * Fix for checking link alignment done during link training. * HDMI compliance test fixes and other improvements Acked-by: Aurabindo Pillai Signed-off-by: Aric Cyr --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 181144541657..9b42f6fc8c69 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -51,7 +51,7 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.271" +#define DC_VER "3.2.272" #define MAX_SURFACES 3 #define MAX_PLANES 6 -- 2.43.0
[PATCH 10/15] drm/amd/display: Add shared firmware state for DMUB IPS handshake
From: Nicholas Kazlauskas
[Why]
Read modify write hazards can occur when using a single shared scratch
register between driver and firmware leading to driver accessing DCN
in IPS2 and a system hang.
[How]
Add infrastructure for using REGION6 as a shared firmware state between
driver and firmware. This region is uncachable.
Replace the existing get/set idle calls with reads/writes to the
(volatile) shared firmware state blocks that a separated by at least
a cache line between firmware and driver.
Remove the workarounds that required rewriting/checking read modify
write hazards.
Reviewed-by: Charlene Liu
Acked-by: Aurabindo Pillai
Signed-off-by: Nicholas Kazlauskas
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +-
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 83 +++--
drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 6 +-
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 115 ++
.../gpu/drm/amd/display/dmub/src/dmub_dcn20.c | 3 +-
.../gpu/drm/amd/display/dmub/src/dmub_dcn20.h | 3 +-
.../gpu/drm/amd/display/dmub/src/dmub_dcn30.c | 3 +-
.../gpu/drm/amd/display/dmub/src/dmub_dcn30.h | 3 +-
.../gpu/drm/amd/display/dmub/src/dmub_dcn31.c | 3 +-
.../gpu/drm/amd/display/dmub/src/dmub_dcn31.h | 3 +-
.../gpu/drm/amd/display/dmub/src/dmub_dcn32.c | 3 +-
.../gpu/drm/amd/display/dmub/src/dmub_dcn32.h | 3 +-
.../gpu/drm/amd/display/dmub/src/dmub_dcn35.c | 12 +-
.../gpu/drm/amd/display/dmub/src/dmub_dcn35.h | 8 +-
.../gpu/drm/amd/display/dmub/src/dmub_srv.c | 13 +-
15 files changed, 212 insertions(+), 52 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index fccc87ad401f..4cf4db0e5b08 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -2129,7 +2129,8 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev)
DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_4_MAILBOX
DMUB_WINDOW_MEMORY_TYPE_FB,
//DMUB_WINDOW_5_TRACEBUFF
DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_6_FW_STATE
- DMUB_WINDOW_MEMORY_TYPE_FB
//DMUB_WINDOW_7_SCRATCH_MEM
+ DMUB_WINDOW_MEMORY_TYPE_FB,
//DMUB_WINDOW_7_SCRATCH_MEM
+ DMUB_WINDOW_MEMORY_TYPE_FB,
//DMUB_WINDOW_SHARED_STATE
};
int r;
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
index a1477906fe4f..0bc32537e2eb 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
@@ -1198,6 +1198,7 @@ bool dc_dmub_srv_is_hw_pwr_up(struct dc_dmub_srv
*dc_dmub_srv, bool wait)
static void dc_dmub_srv_notify_idle(const struct dc *dc, bool allow_idle)
{
+ struct dc_dmub_srv *dc_dmub_srv;
union dmub_rb_cmd cmd = {0};
if (dc->debug.dmcub_emulation)
@@ -1206,6 +1207,8 @@ static void dc_dmub_srv_notify_idle(const struct dc *dc,
bool allow_idle)
if (!dc->ctx->dmub_srv || !dc->ctx->dmub_srv->dmub)
return;
+ dc_dmub_srv = dc->ctx->dmub_srv;
+
memset(&cmd, 0, sizeof(cmd));
cmd.idle_opt_notify_idle.header.type = DMUB_CMD__IDLE_OPT;
cmd.idle_opt_notify_idle.header.sub_type =
DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE;
@@ -1216,10 +1219,32 @@ static void dc_dmub_srv_notify_idle(const struct dc
*dc, bool allow_idle)
cmd.idle_opt_notify_idle.cntl_data.driver_idle = allow_idle;
if (allow_idle) {
+ volatile struct dmub_shared_state_ips_driver *ips_driver =
+
&dc_dmub_srv->dmub->shared_state[DMUB_SHARED_SHARE_FEATURE__IPS_DRIVER].data.ips_driver;
+ union dmub_shared_state_ips_driver_signals new_signals;
+
dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);
- if (dc->hwss.set_idle_state)
- dc->hwss.set_idle_state(dc, true);
+ memset(&new_signals, 0, sizeof(new_signals));
+
+ if (dc->config.disable_ips == DMUB_IPS_ENABLE ||
+ dc->config.disable_ips == DMUB_IPS_DISABLE_DYNAMIC) {
+ new_signals.bits.allow_pg = 1;
+ new_signals.bits.allow_ips1 = 1;
+ new_signals.bits.allow_ips2 = 1;
+ new_signals.bits.allow_z10 = 1;
+ } else if (dc->config.disable_ips == DMUB_IPS_DISABLE_IPS1) {
+ new_signals.bits.allow_ips1 = 1;
+ } else if (dc->config.disable_ips == DMUB_IPS_DISABLE_IPS2) {
+ new_signals.bits.allow_pg = 1;
+ new_signals.bits.allow_ips1 = 1;
+ } else if (dc->config.disable_ips == DMUB_IPS_DISABLE_IPS2_Z10)
{
+ new_signals.bits.allow_pg = 1;
+ new_signals.bits.all
[PATCH 11/15] drm/amd/display: allow psr-su/replay for z8
From: Charlene Liu
[why]
allow psr-su/replay for z8
Reviewed-by: Muhammad Ahmed
Reviewed-by: Sung joon Kim
Acked-by: Aurabindo Pillai
Signed-off-by: Charlene Liu
---
.../gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c | 12 ++--
drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c | 8 ++--
2 files changed, 12 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
index a07f7e685d28..9e588c56c570 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
@@ -361,32 +361,32 @@ void dcn35_smu_set_zstate_support(struct clk_mgr_internal
*clk_mgr, enum dcn_zst
case DCN_ZSTATE_SUPPORT_ALLOW:
msg_id = VBIOSSMC_MSG_AllowZstatesEntry;
param = (1 << 10) | (1 << 9) | (1 << 8);
- smu_print("%s: SMC_MSG_AllowZstatesEntry msg = ALLOW, param =
%d\n", __func__, param);
+ smu_print("%s: SMC_MSG_AllowZstatesEntry msg = ALLOW, param =
0x%x\n", __func__, param);
break;
case DCN_ZSTATE_SUPPORT_DISALLOW:
msg_id = VBIOSSMC_MSG_AllowZstatesEntry;
param = 0;
- smu_print("%s: SMC_MSG_AllowZstatesEntry msg_id = DISALLOW,
param = %d\n", __func__, param);
+ smu_print("%s: SMC_MSG_AllowZstatesEntry msg_id = DISALLOW,
param = 0x%x\n", __func__, param);
break;
case DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY:
msg_id = VBIOSSMC_MSG_AllowZstatesEntry;
param = (1 << 10);
- smu_print("%s: SMC_MSG_AllowZstatesEntry msg = ALLOW_Z10_ONLY,
param = %d\n", __func__, param);
+ smu_print("%s: SMC_MSG_AllowZstatesEntry msg = ALLOW_Z10_ONLY,
param = 0x%x\n", __func__, param);
break;
case DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY:
msg_id = VBIOSSMC_MSG_AllowZstatesEntry;
param = (1 << 10) | (1 << 8);
- smu_print("%s: SMC_MSG_AllowZstatesEntry msg =
ALLOW_Z8_Z10_ONLY, param = %d\n", __func__, param);
+ smu_print("%s: SMC_MSG_AllowZstatesEntry msg =
ALLOW_Z8_Z10_ONLY, param = 0x%x\n", __func__, param);
break;
case DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY:
msg_id = VBIOSSMC_MSG_AllowZstatesEntry;
param = (1 << 8);
- smu_print("%s: SMC_MSG_AllowZstatesEntry msg = ALLOW_Z8_ONLY,
param = %d\n", __func__, param);
+ smu_print("%s: SMC_MSG_AllowZstatesEntry msg = ALLOW_Z8_ONLY,
param = 0x%x\n", __func__, param);
break;
default: //DCN_ZSTATE_SUPPORT_UNKNOWN
@@ -400,7 +400,7 @@ void dcn35_smu_set_zstate_support(struct clk_mgr_internal
*clk_mgr, enum dcn_zst
clk_mgr,
msg_id,
param);
- smu_print("%s: msg_id = %d, param = 0x%x, return = %d\n", __func__,
msg_id, param, retv);
+ smu_print("%s: msg_id = %d, param = 0x%x, return = 0x%x\n", __func__,
msg_id, param, retv);
}
int dcn35_smu_get_dprefclk(struct clk_mgr_internal *clk_mgr)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
index 912256006d75..80bebfc268db 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
@@ -588,7 +588,9 @@ void dcn35_decide_zstate_support(struct dc *dc, struct
dc_state *context)
} else if (context->stream_count == 1 && context->streams[0]->signal ==
SIGNAL_TYPE_EDP) {
struct dc_link *link = context->streams[0]->sink->link;
bool is_pwrseq0 = link && link->link_index == 0;
- bool is_psr1 = link && link->psr_settings.psr_version ==
DC_PSR_VERSION_1 && !link->panel_config.psr.disable_psr;
+ bool is_psr = (link && (link->psr_settings.psr_version ==
DC_PSR_VERSION_1 ||
+
link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) &&
!link->panel_config.psr.disable_psr);
+ bool is_replay = link &&
link->replay_settings.replay_feature_enabled;
int minmum_z8_residency =
dc->debug.minimum_z8_residency_time > 0 ?
dc->debug.minimum_z8_residency_time : 1000;
bool allow_z8 = context->bw_ctx.dml.vba.StutterPeriod >
(double)minmum_z8_residency;
@@ -596,12 +598,14 @@ void dcn35_decide_zstate_support(struct dc *dc, struct
dc_state *context)
dc->debug.minimum_z10_residency_time > 0 ?
dc->debug.minimum_z10_residency_time : 5000;
bool allow_z10 = context->bw_ctx.dml.vba.StutterPeriod >
(double)minmum_z10_residency;
+ /*for psr1/psr-su, we allow z8 and z10 based on latency, for
replay with IPS enabled, it will enter ips2*/
[PATCH 06/15] drm/amd/display: enable fgcg by default
From: Charlene Liu [why] sw has most of the fgcg enabled which is the same as HW default. but driver disabled some due to enable flag not initialized. comparing HW state, we still need to enable dpp and dio. Reviewed-by: Muhammad Ahmed Acked-by: Aurabindo Pillai Signed-off-by: Charlene Liu --- drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c index e534e87cc85b..28266b9a148a 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c @@ -1907,7 +1907,8 @@ static bool dcn35_resource_construct( if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) dc->debug = debug_defaults_drv; - + /*HW default is to have all the FGCG enabled, SW no need to program them*/ + dc->debug.enable_fine_grain_clock_gating.u32All = 0x; // Init the vm_helper if (dc->vm_helper) vm_helper_init(dc->vm_helper, 16); -- 2.43.0
[PATCH 14/15] Revert "drm/amd/display: Add left edge pixel for YCbCr422/420 + ODM pipe split"
From: George Shen
[Why/How]
A regression was identified with the change to add left edge pixel for
YCbCr422/420 + ODM combine cases.
This reverts commit 8d09500a33f6a0e0df9cf17822fe51520d0df002
Reviewed-by: Martin Leung
Acked-by: Aurabindo Pillai
Signed-off-by: George Shen
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 4 --
.../gpu/drm/amd/display/dc/core/dc_resource.c | 37 ---
.../amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 7 +---
.../gpu/drm/amd/display/dc/inc/core_types.h | 2 -
drivers/gpu/drm/amd/display/dc/inc/resource.h | 4 --
5 files changed, 1 insertion(+), 53 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 1d0fd69cc7bd..4d5194293dbd 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -3098,10 +3098,6 @@ static bool update_planes_and_stream_state(struct dc *dc,
if (otg_master && otg_master->stream->test_pattern.type
!= DP_TEST_PATTERN_VIDEO_MODE)
resource_build_test_pattern_params(&context->res_ctx, otg_master);
-
- if (otg_master &&
(otg_master->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422 ||
-
otg_master->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420))
-
resource_build_subsampling_params(&context->res_ctx, otg_master);
}
}
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 96ea283bd169..1b7765bc5e5e 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -822,16 +822,6 @@ static struct rect
calculate_odm_slice_in_timing_active(struct pipe_ctx *pipe_ct
stream->timing.v_border_bottom +
stream->timing.v_border_top;
- /* Recout for ODM slices after the first slice need one extra left edge
pixel
-* for 3-tap chroma subsampling.
-*/
- if (odm_slice_idx > 0 &&
- (pipe_ctx->stream->timing.pixel_encoding ==
PIXEL_ENCODING_YCBCR422 ||
- pipe_ctx->stream->timing.pixel_encoding ==
PIXEL_ENCODING_YCBCR420)) {
- odm_rec.x -= 1;
- odm_rec.width += 1;
- }
-
return odm_rec;
}
@@ -1448,7 +1438,6 @@ void resource_build_test_pattern_params(struct
resource_context *res_ctx,
enum controller_dp_test_pattern controller_test_pattern;
enum controller_dp_color_space controller_color_space;
enum dc_color_depth color_depth =
otg_master->stream->timing.display_color_depth;
- enum dc_pixel_encoding pixel_encoding =
otg_master->stream->timing.pixel_encoding;
int h_active = otg_master->stream->timing.h_addressable +
otg_master->stream->timing.h_border_left +
otg_master->stream->timing.h_border_right;
@@ -1480,36 +1469,10 @@ void resource_build_test_pattern_params(struct
resource_context *res_ctx,
else
params->width = last_odm_slice_width;
- /* Extra left edge pixel is required for 3-tap chroma
subsampling. */
- if (i != 0 && (pixel_encoding == PIXEL_ENCODING_YCBCR422 ||
- pixel_encoding == PIXEL_ENCODING_YCBCR420)) {
- params->offset -= 1;
- params->width += 1;
- }
-
offset += odm_slice_width;
}
}
-void resource_build_subsampling_params(struct resource_context *res_ctx,
- struct pipe_ctx *otg_master)
-{
- struct pipe_ctx *opp_heads[MAX_PIPES];
- int odm_cnt = 1;
- int i;
-
- odm_cnt = resource_get_opp_heads_for_otg_master(otg_master, res_ctx,
opp_heads);
-
- /* For ODM slices after the first slice, extra left edge pixel is
required
-* for 3-tap chroma subsampling.
-*/
- if (otg_master->stream->timing.pixel_encoding ==
PIXEL_ENCODING_YCBCR422 ||
- otg_master->stream->timing.pixel_encoding ==
PIXEL_ENCODING_YCBCR420) {
- for (i = 0; i < odm_cnt; i++)
- opp_heads[i]->stream_res.left_edge_extra_pixel = (i ==
0) ? false : true;
- }
-}
-
bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
{
const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
index f15ba7335336..c55d5155ecb9 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
@@ -1573,8 +1573,7 @@ static void dcn20_detect_pipe_changes(struct dc_state
*old_state,
* makes this assumption at the
[PATCH 08/15] drm/amd/display: Fix array-index-out-of-bounds in dcn35_clkmgr
From: Roman Li
[Why]
There is a potential memory access violation while
iterating through array of dcn35 clks.
[How]
Limit iteration per array size.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Aurabindo Pillai
Signed-off-by: Roman Li
---
.../amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
index 36e5bb611fb1..c378b879c76d 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
@@ -658,10 +658,13 @@ static void
dcn35_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk
struct clk_limit_table_entry def_max =
bw_params->clk_table.entries[bw_params->clk_table.num_entries - 1];
uint32_t max_fclk = 0, min_pstate = 0, max_dispclk = 0, max_dppclk = 0;
uint32_t max_pstate = 0, max_dram_speed_mts = 0, min_dram_speed_mts = 0;
+ uint32_t num_memps, num_fclk, num_dcfclk;
int i;
/* Determine min/max p-state values. */
- for (i = 0; i < clock_table->NumMemPstatesEnabled; i++) {
+ num_memps = (clock_table->NumMemPstatesEnabled > NUM_MEM_PSTATE_LEVELS)
? NUM_MEM_PSTATE_LEVELS :
+ clock_table->NumMemPstatesEnabled;
+ for (i = 0; i < num_memps; i++) {
uint32_t dram_speed_mts =
calc_dram_speed_mts(&clock_table->MemPstateTable[i]);
if (is_valid_clock_value(dram_speed_mts) && dram_speed_mts >
max_dram_speed_mts) {
@@ -673,7 +676,7 @@ static void dcn35_clk_mgr_helper_populate_bw_params(struct
clk_mgr_internal *clk
min_dram_speed_mts = max_dram_speed_mts;
min_pstate = max_pstate;
- for (i = 0; i < clock_table->NumMemPstatesEnabled; i++) {
+ for (i = 0; i < num_memps; i++) {
uint32_t dram_speed_mts =
calc_dram_speed_mts(&clock_table->MemPstateTable[i]);
if (is_valid_clock_value(dram_speed_mts) && dram_speed_mts <
min_dram_speed_mts) {
@@ -702,9 +705,13 @@ static void dcn35_clk_mgr_helper_populate_bw_params(struct
clk_mgr_internal *clk
/* Base the clock table on dcfclk, need at least one entry regardless
of pmfw table */
ASSERT(clock_table->NumDcfClkLevelsEnabled > 0);
- max_fclk = find_max_clk_value(clock_table->FclkClocks_Freq,
clock_table->NumFclkLevelsEnabled);
+ num_fclk = (clock_table->NumFclkLevelsEnabled > NUM_FCLK_DPM_LEVELS) ?
NUM_FCLK_DPM_LEVELS :
+ clock_table->NumFclkLevelsEnabled;
+ max_fclk = find_max_clk_value(clock_table->FclkClocks_Freq, num_fclk);
- for (i = 0; i < clock_table->NumDcfClkLevelsEnabled; i++) {
+ num_dcfclk = (clock_table->NumFclkLevelsEnabled >
NUM_DCFCLK_DPM_LEVELS) ? NUM_DCFCLK_DPM_LEVELS :
+ clock_table->NumDcfClkLevelsEnabled;
+ for (i = 0; i < num_dcfclk; i++) {
int j;
/* First search defaults for the clocks we don't read using
closest lower or equal default dcfclk */
--
2.43.0
[PATCH 12/15] drm/amd/display: should support dmub hw lock on Replay
From: Martin Tsai
[Why]
Without acquiring DMCUB hw lock, a race condition is caused with
Panel Replay feature, which will trigger a hang. Indicate that a
lock is necessary to prevent this when replay feature is enabled.
[How]
To allow dmub hw lock on Replay.
Reviewed-by: Robin Chen
Acked-by: Aurabindo Pillai
Signed-off-by: Martin Tsai
---
drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c
b/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c
index ba1fec3016d5..bf636b28e3e1 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c
@@ -65,5 +65,9 @@ bool should_use_dmub_lock(struct dc_link *link)
{
if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1)
return true;
+
+ if (link->replay_settings.replay_feature_enabled)
+ return true;
+
return false;
}
--
2.43.0
[PATCH 09/15] drm/amd/display: fixed integer types and null check locations
From: Sohaib Nadeem
[why]:
issues fixed:
- comparison with wider integer type in loop condition which can cause
infinite loops
- pointer dereference before null check
Reviewed-by: Josip Pavic
Acked-by: Aurabindo Pillai
Signed-off-by: Sohaib Nadeem
---
.../gpu/drm/amd/display/dc/bios/bios_parser2.c | 16 ++--
.../drm/amd/display/dc/link/link_validation.c| 2 +-
2 files changed, 11 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
index 960c4b4f6ddf..05f392501c0a 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
@@ -1850,19 +1850,21 @@ static enum bp_result get_firmware_info_v3_2(
/* Vega12 */
smu_info_v3_2 = GET_IMAGE(struct atom_smu_info_v3_2,
DATA_TABLES(smu_info));
- DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent):
%d\n", smu_info_v3_2->gpuclk_ss_percentage);
if (!smu_info_v3_2)
return BP_RESULT_BADBIOSTABLE;
+ DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent):
%d\n", smu_info_v3_2->gpuclk_ss_percentage);
+
info->default_engine_clk = smu_info_v3_2->bootup_dcefclk_10khz
* 10;
} else if (revision.minor == 3) {
/* Vega20 */
smu_info_v3_3 = GET_IMAGE(struct atom_smu_info_v3_3,
DATA_TABLES(smu_info));
- DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent):
%d\n", smu_info_v3_3->gpuclk_ss_percentage);
if (!smu_info_v3_3)
return BP_RESULT_BADBIOSTABLE;
+ DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent):
%d\n", smu_info_v3_3->gpuclk_ss_percentage);
+
info->default_engine_clk = smu_info_v3_3->bootup_dcefclk_10khz
* 10;
}
@@ -2422,10 +2424,11 @@ static enum bp_result get_integrated_info_v11(
info_v11 = GET_IMAGE(struct atom_integrated_system_info_v1_11,
DATA_TABLES(integratedsysteminfo));
- DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n",
info_v11->gpuclk_ss_percentage);
if (info_v11 == NULL)
return BP_RESULT_BADBIOSTABLE;
+ DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n",
info_v11->gpuclk_ss_percentage);
+
info->gpu_cap_info =
le32_to_cpu(info_v11->gpucapinfo);
/*
@@ -2637,11 +2640,12 @@ static enum bp_result get_integrated_info_v2_1(
info_v2_1 = GET_IMAGE(struct atom_integrated_system_info_v2_1,
DATA_TABLES(integratedsysteminfo));
- DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n",
info_v2_1->gpuclk_ss_percentage);
if (info_v2_1 == NULL)
return BP_RESULT_BADBIOSTABLE;
+ DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n",
info_v2_1->gpuclk_ss_percentage);
+
info->gpu_cap_info =
le32_to_cpu(info_v2_1->gpucapinfo);
/*
@@ -2799,11 +2803,11 @@ static enum bp_result get_integrated_info_v2_2(
info_v2_2 = GET_IMAGE(struct atom_integrated_system_info_v2_2,
DATA_TABLES(integratedsysteminfo));
- DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n",
info_v2_2->gpuclk_ss_percentage);
-
if (info_v2_2 == NULL)
return BP_RESULT_BADBIOSTABLE;
+ DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n",
info_v2_2->gpuclk_ss_percentage);
+
info->gpu_cap_info =
le32_to_cpu(info_v2_2->gpucapinfo);
/*
diff --git a/drivers/gpu/drm/amd/display/dc/link/link_validation.c
b/drivers/gpu/drm/amd/display/dc/link/link_validation.c
index 1c038e2a527b..1aed55b0ab6a 100644
--- a/drivers/gpu/drm/amd/display/dc/link/link_validation.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_validation.c
@@ -359,7 +359,7 @@ bool link_validate_dpia_bandwidth(const struct
dc_stream_state *stream, const un
struct dc_link *dpia_link[MAX_DPIA_NUM] = {0};
int num_dpias = 0;
- for (uint8_t i = 0; i < num_streams; ++i) {
+ for (unsigned int i = 0; i < num_streams; ++i) {
if (stream[i].signal == SIGNAL_TYPE_DISPLAY_PORT) {
/* new dpia sst stream, check whether it exceeds max
dpia */
if (num_dpias >= MAX_DPIA_NUM)
--
2.43.0
[PATCH 04/15] Revert "drm/amd/display: Send DTBCLK disable message on first commit"
From: Gabe Teeger This reverts commit 3fda240dc2f6a4a9a3965b80cfb83d0ddfbf489c. System hang observed, this commit is thought to be the regression point. Reviewed-by: Ovidiu Bunea Acked-by: Aurabindo Pillai Signed-off-by: Gabe Teeger --- drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c index 06edca50a8fa..36e5bb611fb1 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c @@ -414,7 +414,6 @@ static void init_clk_states(struct clk_mgr *clk_mgr) uint32_t ref_dtbclk = clk_mgr->clks.ref_dtbclk_khz; memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks)); - clk_mgr->clks.dtbclk_en = true; clk_mgr->clks.ref_dtbclk_khz = ref_dtbclk; // restore ref_dtbclk clk_mgr->clks.p_state_change_support = true; clk_mgr->clks.prev_p_state_change_support = true; -- 2.43.0
[PATCH 07/15] drm/amd/display: Update FIXED_VS Retimer HWSS Test Pattern Sequences
From: Michael Strauss
[WHY]
Need to fix some broken logic and sequencing in initial commit
[HOW]
Fix logic handling override deprogramming when exiting SQ128.
Don't exit early from dp_set_hw_lane_settings for DP2/FIXED_VS case.
Move LTTPR 128b/132b check out of requires_hwss and check during
runtime, as LTTPR caps are not populated on initial call.
Add pending_test_pattern to link state to allow HWSS to set FFE overrides
on retimer TX and/or skip setting APU TX FFE depending on requested pattern.
Use updated clock source for SQ128 override sequence.
Skip HW FFE preset programming when performing test pattern overrides.
Reviewed-by: Wenjing Liu
Acked-by: Aurabindo Pillai
Signed-off-by: Michael Strauss
---
drivers/gpu/drm/amd/display/dc/dc.h | 12 +
.../display/dc/link/accessories/link_dp_cts.c | 27 +++---
.../hwss/link_hwss_dio_fixed_vs_pe_retimer.c | 16 +++---
.../link_hwss_hpo_fixed_vs_pe_retimer_dp.c| 51 +--
.../display/dc/link/protocols/link_dp_phy.c | 6 ++-
.../amd/display/include/link_service_types.h | 9
6 files changed, 65 insertions(+), 56 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index f2c27964ec1c..181144541657 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -1572,7 +1572,19 @@ struct dc_link {
enum engine_id dpia_preferred_eng_id;
bool test_pattern_enabled;
+ /* Pending/Current test pattern are only used to perform and track
+* FIXED_VS retimer test pattern/lane adjustment override state.
+* Pending allows link HWSS to differentiate PHY vs non-PHY pattern,
+* to perform specific lane adjust overrides before setting certain
+* PHY test patterns. In cases when lane adjust and set test pattern
+* calls are not performed atomically (i.e. performing link training),
+* pending_test_pattern will be invalid or contain a non-PHY test
pattern
+* and current_test_pattern will contain required context for any future
+* set pattern/set lane adjust to transition between override state(s).
+* */
enum dp_test_pattern current_test_pattern;
+ enum dp_test_pattern pending_test_pattern;
+
union compliance_test_state compliance_test_state;
void *priv;
diff --git a/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c
b/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c
index 2d152b68a501..22b24749c9d2 100644
--- a/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c
+++ b/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c
@@ -61,22 +61,6 @@ static enum dc_link_rate
get_link_rate_from_test_link_rate(uint8_t test_rate)
}
}
-static bool is_dp_phy_sqaure_pattern(enum dp_test_pattern test_pattern)
-{
- return (DP_TEST_PATTERN_SQUARE_BEGIN <= test_pattern &&
- test_pattern <= DP_TEST_PATTERN_SQUARE_END);
-}
-
-static bool is_dp_phy_pattern(enum dp_test_pattern test_pattern)
-{
- if ((DP_TEST_PATTERN_PHY_PATTERN_BEGIN <= test_pattern &&
- test_pattern <= DP_TEST_PATTERN_PHY_PATTERN_END) ||
- test_pattern == DP_TEST_PATTERN_VIDEO_MODE)
- return true;
- else
- return false;
-}
-
static void dp_retrain_link_dp_test(struct dc_link *link,
struct dc_link_settings *link_setting,
bool skip_video_pattern)
@@ -361,7 +345,7 @@ static void dp_test_send_phy_test_pattern(struct dc_link
*link)
test_pattern_size);
}
- if (is_dp_phy_sqaure_pattern(test_pattern)) {
+ if (IS_DP_PHY_SQUARE_PATTERN(test_pattern)) {
test_pattern_size = 1; // Square pattern data is 1 byte (DP
spec)
core_link_read_dpcd(
link,
@@ -623,6 +607,8 @@ bool dp_set_test_pattern(
if (pipe_ctx == NULL)
return false;
+ link->pending_test_pattern = test_pattern;
+
/* Reset CRTC Test Pattern if it is currently running and request is
VideoMode */
if (link->test_pattern_enabled && test_pattern ==
DP_TEST_PATTERN_VIDEO_MODE) {
@@ -643,12 +629,13 @@ bool dp_set_test_pattern(
/* Reset Test Pattern state */
link->test_pattern_enabled = false;
link->current_test_pattern = test_pattern;
+ link->pending_test_pattern = DP_TEST_PATTERN_UNSUPPORTED;
return true;
}
/* Check for PHY Test Patterns */
- if (is_dp_phy_pattern(test_pattern)) {
+ if (IS_DP_PHY_PATTERN(test_pattern)) {
/* Set DPCD Lane Settings before running test pattern */
if (p_link_settings != NULL) {
if ((link->chip_caps &
EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &&
@
[PATCH 03/15] drm/amd/display: Preserve original aspect ratio in create stream
From: Tom Chung
[Why]
The original picture aspect ratio in mode struct may have chance be
overwritten with wrong aspect ratio data in create_stream_for_sink().
It will create a different VIC output and cause HDMI compliance test
failed.
[How]
Preserve the original picture aspect ratio data during create the
stream.
Reviewed-by: Aurabindo Pillai
Acked-by: Aurabindo Pillai
Signed-off-by: Tom Chung
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index b3a5e730be24..fccc87ad401f 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -6228,7 +6228,9 @@ create_stream_for_sink(struct drm_connector *connector,
if (recalculate_timing) {
freesync_mode =
get_highest_refresh_rate_mode(aconnector, false);
drm_mode_copy(&saved_mode, &mode);
+ saved_mode.picture_aspect_ratio =
mode.picture_aspect_ratio;
drm_mode_copy(&mode, freesync_mode);
+ mode.picture_aspect_ratio =
saved_mode.picture_aspect_ratio;
} else {
decide_crtc_timing_for_drm_display_mode(
&mode, preferred_mode, scale);
--
2.43.0
[PATCH 05/15] drm/amd/display: treat plane clip size change as MED update type
From: Wenjing Liu
[why]
When clip size is changed recout and viewport size would require an
update. When the update is clip size only current driver fails to
program the update into hardware.
[how]
Set a new clip_size_change flag when it is detected and set MED update
type and reprogram scaling params in next program pipe.
Reviewed-by: Aric Cyr
Acked-by: Aurabindo Pillai
Signed-off-by: Wenjing Liu
---
drivers/gpu/drm/amd/display/dc/core/dc.c| 7 ++-
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 2 ++
3 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 72512903f88f..1d0fd69cc7bd 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2454,6 +2454,10 @@ static enum surface_update_type
get_scaling_info_update_type(
/* Changing clip size of a large surface may result in MPC
slice count change */
update_flags->bits.bandwidth_change = 1;
+ if (u->scaling_info->clip_rect.width != u->surface->clip_rect.width ||
+ u->scaling_info->clip_rect.height !=
u->surface->clip_rect.height)
+ update_flags->bits.clip_size_change = 1;
+
if (u->scaling_info->src_rect.x != u->surface->src_rect.x
|| u->scaling_info->src_rect.y != u->surface->src_rect.y
|| u->scaling_info->clip_rect.x !=
u->surface->clip_rect.x
@@ -2467,7 +2471,8 @@ static enum surface_update_type
get_scaling_info_update_type(
|| update_flags->bits.scaling_change)
return UPDATE_TYPE_FULL;
- if (update_flags->bits.position_change)
+ if (update_flags->bits.position_change ||
+ update_flags->bits.clip_size_change)
return UPDATE_TYPE_MED;
return UPDATE_TYPE_FAST;
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index c789cc2e216d..f2c27964ec1c 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -1252,6 +1252,7 @@ union surface_update_flags {
uint32_t rotation_change:1;
uint32_t swizzle_change:1;
uint32_t scaling_change:1;
+ uint32_t clip_size_change: 1;
uint32_t position_change:1;
uint32_t in_transfer_func_change:1;
uint32_t input_csc_change:1;
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
index bc0a21957e33..f15ba7335336 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
@@ -1740,6 +1740,7 @@ static void dcn20_update_dchubp_dpp(
if (pipe_ctx->update_flags.bits.scaler ||
plane_state->update_flags.bits.scaling_change ||
plane_state->update_flags.bits.position_change ||
+ plane_state->update_flags.bits.clip_size_change ||
plane_state->update_flags.bits.per_pixel_alpha_change ||
pipe_ctx->stream->update_flags.bits.scaling) {
pipe_ctx->plane_res.scl_data.lb_params.alpha_en =
pipe_ctx->plane_state->per_pixel_alpha;
@@ -1752,6 +1753,7 @@ static void dcn20_update_dchubp_dpp(
if (pipe_ctx->update_flags.bits.viewport ||
(context == dc->current_state &&
plane_state->update_flags.bits.position_change) ||
(context == dc->current_state &&
plane_state->update_flags.bits.scaling_change) ||
+ (context == dc->current_state &&
plane_state->update_flags.bits.clip_size_change) ||
(context == dc->current_state &&
pipe_ctx->stream->update_flags.bits.scaling)) {
hubp->funcs->mem_program_viewport(
--
2.43.0
[PATCH 02/15] Revert "drm/amd/display: increased min_dcfclk_mhz and min_fclk_mhz"
From: Sohaib Nadeem
[why]:
This reverts commit 5abbfa320b88da6034fd4121fa68c2b0e15e97ac.
The commit caused corruption when running some applications in fullscreen
Reviewed-by: Alvin Lee
Acked-by: Aurabindo Pillai
Signed-off-by: Sohaib Nadeem
---
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index ba76dd4a2ce2..a0a65e099104 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -2760,7 +2760,7 @@ static int build_synthetic_soc_states(bool
disable_dc_mode_overwrite, struct clk
struct _vcs_dpi_voltage_scaling_st entry = {0};
struct clk_limit_table_entry max_clk_data = {0};
- unsigned int min_dcfclk_mhz = 399, min_fclk_mhz = 599;
+ unsigned int min_dcfclk_mhz = 199, min_fclk_mhz = 299;
static const unsigned int num_dcfclk_stas = 5;
unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906,
1324, 1564};
--
2.43.0
[PATCH 01/15] drm/amd/display: Add align done check
From: Zhikai Zhai
[WHY]
We Double-check link status if training successful,
but miss the lane align status.
[HOW]
Add the lane align status check
Reviewed-by: Wenjing Liu
Acked-by: Aurabindo Pillai
Signed-off-by: Zhikai Zhai
---
.../gpu/drm/amd/display/dc/link/protocols/link_dp_training.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c
b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c
index e06d3c2d8910..e538c67d3ed9 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c
@@ -517,6 +517,7 @@ enum link_training_result dp_check_link_loss_status(
{
enum link_training_result status = LINK_TRAINING_SUCCESS;
union lane_status lane_status;
+ union lane_align_status_updated dpcd_lane_status_updated;
uint8_t dpcd_buf[6] = {0};
uint32_t lane;
@@ -532,10 +533,12 @@ enum link_training_result dp_check_link_loss_status(
* check lanes status
*/
lane_status.raw = dp_get_nibble_at_index(&dpcd_buf[2], lane);
+ dpcd_lane_status_updated.raw = dpcd_buf[4];
if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||
!lane_status.bits.CR_DONE_0 ||
- !lane_status.bits.SYMBOL_LOCKED_0) {
+ !lane_status.bits.SYMBOL_LOCKED_0 ||
+ !dp_is_interlane_aligned(dpcd_lane_status_updated)) {
/* if one of the channel equalization, clock
* recovery or symbol lock is dropped
* consider it as (link has been
--
2.43.0
[PATCH 00/15] DC Patches for 12 Feb 2024
Summary: * Revert some changes related to pixel encoding and clocks that cause corruption * IPS hang fix and FGCG enable by default for DCN35 * PSR-SU/Replay fixes * Plane clip size change treated as medium update * Fix for checking link alignment done during link training. * HDMI compliance test fixes and other improvements Cc: Daniel Wheeler Aric Cyr (1): drm/amd/display: 3.2.272 Charlene Liu (2): drm/amd/display: enable fgcg by default drm/amd/display: allow psr-su/replay for z8 Gabe Teeger (1): Revert "drm/amd/display: Send DTBCLK disable message on first commit" George Shen (1): Revert "drm/amd/display: Add left edge pixel for YCbCr422/420 + ODM pipe split" Martin Tsai (1): drm/amd/display: should support dmub hw lock on Replay Michael Strauss (1): drm/amd/display: Update FIXED_VS Retimer HWSS Test Pattern Sequences Nicholas Kazlauskas (2): drm/amd/display: Add shared firmware state for DMUB IPS handshake drm/amd/display: Increase ips2_eval delay for DCN35 Roman Li (1): drm/amd/display: Fix array-index-out-of-bounds in dcn35_clkmgr Sohaib Nadeem (2): Revert "drm/amd/display: increased min_dcfclk_mhz and min_fclk_mhz" drm/amd/display: fixed integer types and null check locations Tom Chung (1): drm/amd/display: Preserve original aspect ratio in create stream Wenjing Liu (1): drm/amd/display: treat plane clip size change as MED update type Zhikai Zhai (1): drm/amd/display: Add align done check .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 +- .../drm/amd/display/dc/bios/bios_parser2.c| 16 ++- .../display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c | 16 ++- .../amd/display/dc/clk_mgr/dcn35/dcn35_smu.c | 12 +- drivers/gpu/drm/amd/display/dc/core/dc.c | 11 +- .../gpu/drm/amd/display/dc/core/dc_resource.c | 37 -- drivers/gpu/drm/amd/display/dc/dc.h | 15 ++- drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 83 +++-- .../drm/amd/display/dc/dce/dmub_hw_lock_mgr.c | 4 + .../drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 2 +- .../drm/amd/display/dc/dml/dcn35/dcn35_fpu.c | 8 +- .../amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 9 +- .../gpu/drm/amd/display/dc/inc/core_types.h | 2 - drivers/gpu/drm/amd/display/dc/inc/resource.h | 4 - .../display/dc/link/accessories/link_dp_cts.c | 27 ++-- .../hwss/link_hwss_dio_fixed_vs_pe_retimer.c | 16 +-- .../link_hwss_hpo_fixed_vs_pe_retimer_dp.c| 51 .../drm/amd/display/dc/link/link_validation.c | 2 +- .../display/dc/link/protocols/link_dp_phy.c | 6 +- .../dc/link/protocols/link_dp_training.c | 5 +- .../dc/resource/dcn35/dcn35_resource.c| 5 +- drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 6 +- .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 115 ++ .../gpu/drm/amd/display/dmub/src/dmub_dcn20.c | 3 +- .../gpu/drm/amd/display/dmub/src/dmub_dcn20.h | 3 +- .../gpu/drm/amd/display/dmub/src/dmub_dcn30.c | 3 +- .../gpu/drm/amd/display/dmub/src/dmub_dcn30.h | 3 +- .../gpu/drm/amd/display/dmub/src/dmub_dcn31.c | 3 +- .../gpu/drm/amd/display/dmub/src/dmub_dcn31.h | 3 +- .../gpu/drm/amd/display/dmub/src/dmub_dcn32.c | 3 +- .../gpu/drm/amd/display/dmub/src/dmub_dcn32.h | 3 +- .../gpu/drm/amd/display/dmub/src/dmub_dcn35.c | 12 +- .../gpu/drm/amd/display/dmub/src/dmub_dcn35.h | 8 +- .../gpu/drm/amd/display/dmub/src/dmub_srv.c | 13 +- .../amd/display/include/link_service_types.h | 9 ++ 35 files changed, 336 insertions(+), 187 deletions(-) -- 2.43.0
[PATCH v2 2/2] drm/amd: Stop evicting resources on APUs in suspend
commit 5095d5418193 ("drm/amd: Evict resources during PM ops prepare()
callback")
intentionally moved the eviction of resources to earlier in the suspend
process, but this introduced a subtle change that it occurs before adev->in_s0ix
or adev->in_s3 are set. This meant that APUs actually started to evict
resources at suspend time as well.
Add a new `in_prepare` flag that is set for the life of the prepare() callback
to return the old code flow. Drop the existing call to return 1 in this case
because
the suspend() callback looks for the flags too.
Also, introduce a new amdgpu_device_freeze() function to call at S4 and evict
resources in this callback so that APUs will still get resources evicted.
Reported-by: Jürg Billeter
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3132#note_2271038
Fixes: 5095d5418193 ("drm/amd: Evict resources during PM ops prepare()
callback")
Signed-off-by: Mario Limonciello
---
v1->v2:
* Add and use new in_prepare member
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 4 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 46 --
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c| 21 ++
3 files changed, 48 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 5d5be3e20687..f9db09a9017a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1075,7 +1075,8 @@ struct amdgpu_device {
u8 reset_magic[AMDGPU_RESET_MAGIC_NUM];
/* s3/s4 mask */
- boolin_suspend;
+ boolin_prepare;
+ boolin_suspend;
boolin_s3;
boolin_s4;
boolin_s0ix;
@@ -1462,6 +1463,7 @@ int amdgpu_device_ip_suspend(struct amdgpu_device *adev);
int amdgpu_device_prepare(struct drm_device *dev);
int amdgpu_device_suspend(struct drm_device *dev, bool fbcon);
int amdgpu_device_resume(struct drm_device *dev, bool fbcon);
+int amdgpu_device_freeze(struct drm_device *drm_dev);
u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc);
int amdgpu_enable_vblank_kms(struct drm_crtc *crtc);
void amdgpu_disable_vblank_kms(struct drm_crtc *crtc);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 2bc460cb993d..0a337fcd89b4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -4492,7 +4492,7 @@ static int amdgpu_device_evict_resources(struct
amdgpu_device *adev)
int ret;
/* No need to evict vram on APUs for suspend to ram or s2idle */
- if ((adev->in_s3 || adev->in_s0ix) && (adev->flags & AMD_IS_APU))
+ if ((adev->in_prepare) && (adev->flags & AMD_IS_APU))
return 0;
ret = amdgpu_ttm_evict_resources(adev, TTM_PL_VRAM);
@@ -4521,10 +4521,12 @@ int amdgpu_device_prepare(struct drm_device *dev)
if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
return 0;
+ adev->in_prepare = true;
+
/* Evict the majority of BOs before starting suspend sequence */
r = amdgpu_device_evict_resources(adev);
if (r)
- return r;
+ goto unprepare;
for (i = 0; i < adev->num_ip_blocks; i++) {
if (!adev->ip_blocks[i].status.valid)
@@ -4533,10 +4535,46 @@ int amdgpu_device_prepare(struct drm_device *dev)
continue;
r = adev->ip_blocks[i].version->funcs->prepare_suspend((void
*)adev);
if (r)
- return r;
+ goto unprepare;
}
- return 0;
+unprepare:
+ adev->in_prepare = FALSE;
+
+ return r;
+}
+
+/**
+ * amdgpu_device_freeze - run S4 sequence
+ *
+ * @dev: drm dev pointer
+ *
+ * Prepare to put the hw in the S4 state (all asics).
+ * Returns 0 for success or an error on failure.
+ * Called at driver freeze.
+ */
+int amdgpu_device_freeze(struct drm_device *drm_dev)
+{
+ struct amdgpu_device *adev = drm_to_adev(drm_dev);
+ int r;
+
+ adev->in_s4 = true;
+
+ r = amdgpu_device_evict_resources(adev);
+ if (r)
+ goto cleanup;
+
+ r = amdgpu_device_suspend(drm_dev, true);
+ if (r)
+ goto cleanup;
+
+ if (amdgpu_acpi_should_gpu_reset(adev))
+ r = amdgpu_asic_reset(adev);
+
+cleanup:
+ adev->in_s4 = false;
+
+ return r;
}
/**
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index b74f68a15802..fc9caa14c9d6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -2456,6 +2456,7 @@ static int amdgpu_pmops_prepare(struct device *dev)
{
struct drm_device *drm_dev = dev_get_drv
[PATCH v2 1/2] Revert "drm/amd: flush any delayed gfxoff on suspend entry"
commit ab4750332dbe ("drm/amdgpu/sdma5.2: add begin/end_use ring callbacks")
caused GFXOFF control to be used more heavily and the codepath that was
removed from commit 0dee72639533 ("drm/amd: flush any delayed gfxoff on
suspend entry") now can be exercised at suspend again.
Users report that by using GNOME to suspend the lockscreen trigger will
cause SDMA traffic and the system can deadlock.
This reverts commit 0dee726395333fea833eaaf838bc80962df886c8.
Fixes: ab4750332dbe ("drm/amdgpu/sdma5.2: add begin/end_use ring callbacks")
Signed-off-by: Mario Limonciello
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 -
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c| 9 -
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 670ecb789d59..2bc460cb993d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -4573,7 +4573,6 @@ int amdgpu_device_suspend(struct drm_device *dev, bool
fbcon)
drm_fb_helper_set_suspend_unlocked(adev_to_drm(adev)->fb_helper, true);
cancel_delayed_work_sync(&adev->delayed_init_work);
- flush_delayed_work(&adev->gfx.gfx_off_delay_work);
amdgpu_ras_suspend(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index aa8e1d29d10a..9831dd854532 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -727,8 +727,15 @@ void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool
enable)
if (adev->gfx.gfx_off_req_count == 0 &&
!adev->gfx.gfx_off_state) {
- schedule_delayed_work(&adev->gfx.gfx_off_delay_work,
+ /* If going to s2idle, no need to wait */
+ if (adev->in_s0ix) {
+ if (!amdgpu_dpm_set_powergating_by_smu(adev,
+ AMD_IP_BLOCK_TYPE_GFX, true))
+ adev->gfx.gfx_off_state = true;
+ } else {
+
schedule_delayed_work(&adev->gfx.gfx_off_delay_work,
delay);
+ }
}
} else {
if (adev->gfx.gfx_off_req_count == 0) {
--
2.34.1
[PATCH] drm/buddy: Fix alloc_range() error handling code
Few users have observed display corruption when they boot
the machine to KDE Plasma or playing games. We have root
caused the problem that whenever alloc_range() couldn't
find the required memory blocks the function was returning
SUCCESS in some of the corner cases.
The right approach would be if the total allocated size
is less than the required size, the function should
return -ENOSPC.
Gitlab ticket link - https://gitlab.freedesktop.org/drm/amd/-/issues/3097
Fixes: 0a1844bf0b53 ("drm/buddy: Improve contiguous memory allocation")
Signed-off-by: Arunpravin Paneer Selvam
Tested-by: Mario Limonciello
---
drivers/gpu/drm/drm_buddy.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/drm_buddy.c b/drivers/gpu/drm/drm_buddy.c
index f57e6d74fb0e..c1a99bf4dffd 100644
--- a/drivers/gpu/drm/drm_buddy.c
+++ b/drivers/gpu/drm/drm_buddy.c
@@ -539,6 +539,12 @@ static int __alloc_range(struct drm_buddy *mm,
} while (1);
list_splice_tail(&allocated, blocks);
+
+ if (total_allocated < size) {
+ err = -ENOSPC;
+ goto err_free;
+ }
+
return 0;
err_undo:
--
2.25.1
RE: [PATCH v2] drm/amdkfd: Fix L2 cache size reporting in GFX9.4.3
[AMD Official Use Only - General]
Reviewed-by: Mukul Joshi
> -Original Message-
> From: Russell, Kent
> Sent: Tuesday, February 6, 2024 4:32 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Joshi, Mukul ; Russell, Kent
>
> Subject: [PATCH v2] drm/amdkfd: Fix L2 cache size reporting in GFX9.4.3
>
> Its currently incorrectly multiplied by number of XCCs in the partition
>
> Fixes: 6b537864925e ("drm/amdkfd: Update cache info for GFX 9.4.3")
> Signed-off-by: Kent Russell
> ---
> drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 10 --
> 1 file changed, 4 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
> b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
> index 3df2a8ad86fb..533b8292b136 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
> @@ -1640,12 +1640,10 @@ static int fill_in_l2_l3_pcache(struct
> kfd_cache_properties **props_ext,
> else
> mode = UNKNOWN_MEMORY_PARTITION_MODE;
>
> - if (pcache->cache_level == 2)
> - pcache->cache_size =
> pcache_info[cache_type].cache_size * num_xcc;
> - else if (mode)
> - pcache->cache_size =
> pcache_info[cache_type].cache_size / mode;
> - else
> - pcache->cache_size =
> pcache_info[cache_type].cache_size;
> + pcache->cache_size = pcache_info[cache_type].cache_size;
> + /* Partition mode only affects L3 cache size */
> + if (mode && pcache->cache_level == 3)
> + pcache->cache_size /= mode;
>
> if (pcache_info[cache_type].flags &
> CRAT_CACHE_FLAGS_DATA_CACHE)
> pcache->cache_type |= HSA_CACHE_TYPE_DATA;
> --
> 2.34.1
Re: [PATCH 1/2] drm/amdgpu: Unmap only clear the page table leaves
Am 01.02.24 um 17:50 schrieb Philip Yang:
SVM migration unmap pages from GPU and then update mapping to GPU to
recover page fault. Currently unmap clears the PDE entry for range
length >= huge page and free PTB bo, update mapping to alloc new PT bo.
There is race bug that the freed entry bo maybe still on the pt_free
list, reused when updating mapping and then freed, leave invalid PDE
entry and cause GPU page fault.
Well that race here is not clear to me. Can you explain more what's
going on and why we should change the VM code to avoid this situation?
By setting the update to clear only one PDE entry or clear PTB, to
avoid unmap to free PTE bo. This fixes the race bug and improve the
unmap and map to GPU performance. Update mapping to huge page will
still free the PTB bo.
I would only do this if we don't have any other way to clean this up
since that is a really ugly workaround for this issue.
Regards,
Christian.
With this change, the vm->pt_freed list and work is not needed. Add
WARN_ON(unlocked) in amdgpu_vm_pt_free_dfs to catch if unmap to free the
PTB.
Signed-off-by: Philip Yang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c| 4 ---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h| 4 ---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c | 43 ++-
3 files changed, 10 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 82e5fd66a10d..3bde77dfc63f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -2256,8 +2256,6 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct
amdgpu_vm *vm,
spin_lock_init(&vm->status_lock);
INIT_LIST_HEAD(&vm->freed);
INIT_LIST_HEAD(&vm->done);
- INIT_LIST_HEAD(&vm->pt_freed);
- INIT_WORK(&vm->pt_free_work, amdgpu_vm_pt_free_work);
INIT_KFIFO(vm->faults);
r = amdgpu_vm_init_entities(adev, vm);
@@ -2446,8 +2444,6 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct
amdgpu_vm *vm)
amdgpu_amdkfd_gpuvm_destroy_cb(adev, vm);
- flush_work(&vm->pt_free_work);
-
root = amdgpu_bo_ref(vm->root.bo);
amdgpu_bo_reserve(root, true);
amdgpu_vm_set_pasid(adev, vm, 0);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index cdb61f1e7c35..74fe211b9ecd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -316,10 +316,6 @@ struct amdgpu_vm {
/* BOs which are invalidated, has been updated in the PTs */
struct list_headdone;
- /* PT BOs scheduled to free and fill with zero if vm_resv is not hold */
- struct list_headpt_freed;
- struct work_struct pt_free_work;
-
/* contains the page directory */
struct amdgpu_vm_bo_base root;
struct dma_fence*last_update;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
index a160265ddc07..a3d609655ce3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
@@ -657,27 +657,6 @@ static void amdgpu_vm_pt_free(struct amdgpu_vm_bo_base
*entry)
amdgpu_bo_unref(&entry->bo);
}
-void amdgpu_vm_pt_free_work(struct work_struct *work)
-{
- struct amdgpu_vm_bo_base *entry, *next;
- struct amdgpu_vm *vm;
- LIST_HEAD(pt_freed);
-
- vm = container_of(work, struct amdgpu_vm, pt_free_work);
-
- spin_lock(&vm->status_lock);
- list_splice_init(&vm->pt_freed, &pt_freed);
- spin_unlock(&vm->status_lock);
-
- /* flush_work in amdgpu_vm_fini ensure vm->root.bo is valid. */
- amdgpu_bo_reserve(vm->root.bo, true);
-
- list_for_each_entry_safe(entry, next, &pt_freed, vm_status)
- amdgpu_vm_pt_free(entry);
-
- amdgpu_bo_unreserve(vm->root.bo);
-}
-
/**
* amdgpu_vm_pt_free_dfs - free PD/PT levels
*
@@ -696,17 +675,7 @@ static void amdgpu_vm_pt_free_dfs(struct amdgpu_device
*adev,
struct amdgpu_vm_pt_cursor cursor;
struct amdgpu_vm_bo_base *entry;
- if (unlocked) {
- spin_lock(&vm->status_lock);
- for_each_amdgpu_vm_pt_dfs_safe(adev, vm, start, cursor, entry)
- list_move(&entry->vm_status, &vm->pt_freed);
-
- if (start)
- list_move(&start->entry->vm_status, &vm->pt_freed);
- spin_unlock(&vm->status_lock);
- schedule_work(&vm->pt_free_work);
- return;
- }
+ WARN_ON(unlocked);
for_each_amdgpu_vm_pt_dfs_safe(adev, vm, start, cursor, entry)
amdgpu_vm_pt_free(entry);
@@ -1009,7 +978,15 @@ int amdgpu_vm_ptes_update(struct amdgpu_vm_update_params
*params,
incr = (uint64_t)AMDGPU_GPU_PAGE_SIZE << shift;
mask = amdgpu_vm_pt_entries_mask(adev, cursor.level);
RE: [PATCH] drm/amdgpu/soc21: update VCN 4 max HEVC encoding resolution
[AMD Official Use Only - General]
Reviewed-by: Ruijing Dong
Thanks,
Ruijing
-Original Message-
From: amd-gfx On Behalf Of Thong
Sent: Tuesday, February 6, 2024 6:28 PM
To: amd-gfx@lists.freedesktop.org
Cc: Thai, Thong
Subject: [PATCH] drm/amdgpu/soc21: update VCN 4 max HEVC encoding resolution
Update the maximum resolution reported for HEVC encoding on VCN 4 devices to
reflect its 8K encoding capability.
Signed-off-by: Thong
---
drivers/gpu/drm/amd/amdgpu/soc21.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c
b/drivers/gpu/drm/amd/amdgpu/soc21.c
index 48c6efcdeac9..4d7188912edf 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc21.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
@@ -50,13 +50,13 @@ static const struct amd_ip_funcs soc21_common_ip_funcs;
/* SOC21 */
static const struct amdgpu_video_codec_info
vcn_4_0_0_video_codecs_encode_array_vcn0[] = {
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096,
2304, 0)},
- {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304,
0)},
+ {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352,
+0)},
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352,
0)}, };
static const struct amdgpu_video_codec_info
vcn_4_0_0_video_codecs_encode_array_vcn1[] = {
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096,
2304, 0)},
- {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304,
0)},
+ {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352,
+0)},
};
static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode_vcn0 = {
--
2.34.1
2024 X.Org Foundation Membership deadline for voting in the election
The 2024 X.Org Foundation elections are rapidly approaching. We will be forwarding the election schedule and nominating process to the membership shortly. Please note that only current members can vote in the upcoming election, and that the deadline for new memberships or renewals to vote in the upcoming election is 26 February 2024 at 23:59 UTC. If you are interested in joining the X.Org Foundation or in renewing your membership, please visit the membership system site at: https://members.x.org/ Christopher Michael, on behalf of the X.Org elections committee
RE: [PATCH v2 1/2] drm/amdgpu: implement smu send rma reason for smu v13.0.6
[AMD Official Use Only - General]
Thanks , I will correct it before submitting.
Best Regards,
Kevin
-Original Message-
From: Zhang, Hawking
Sent: Wednesday, February 7, 2024 10:00 PM
To: Wang, Yang(Kevin) ; amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao ; Lazar, Lijo
Subject: RE: [PATCH v2 1/2] drm/amdgpu: implement smu send rma reason for smu
v13.0.6
[AMD Official Use Only - General]
With a nitpick below, the series is
Reviewed-by: Hawking Zhang
+ MSG_MAP(BadPageThreshold,
PPSMC_MSG_RmaDueToBadPageThreshold,0),
Might be better name it to RmaDueToBadPageThreshold/SMU_MSG_
RmaDueToBadPageThreshold
Regards,
Hawking
-Original Message-
From: Wang, Yang(Kevin)
Sent: Wednesday, February 7, 2024 21:54
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Zhou1, Tao ;
Lazar, Lijo ; Wang, Yang(Kevin)
Subject: [PATCH v2 1/2] drm/amdgpu: implement smu send rma reason for smu
v13.0.6
implement smu send rma reason function for smu v13.0.6
Signed-off-by: Yang Wang
Reviewed-by: Tao Zhou
---
drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 15 ++
drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h | 1 +
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 10 ++
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 6 ++
.../pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h | 3 ++-
drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h | 3 ++-
.../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 20 +++
7 files changed, 56 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
index 6627ee07d52d..f84bfed50681 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
@@ -693,6 +693,21 @@ int amdgpu_dpm_send_hbm_bad_channel_flag(struct
amdgpu_device *adev, uint32_t si
return ret;
}
+int amdgpu_dpm_send_rma_reason(struct amdgpu_device *adev) {
+ struct smu_context *smu = adev->powerplay.pp_handle;
+ int ret;
+
+ if (!is_support_sw_smu(adev))
+ return -EOPNOTSUPP;
+
+ mutex_lock(&adev->pm.mutex);
+ ret = smu_send_rma_reason(smu);
+ mutex_unlock(&adev->pm.mutex);
+
+ return ret;
+}
+
int amdgpu_dpm_get_dpm_freq_range(struct amdgpu_device *adev,
enum pp_clock_type type,
uint32_t *min, diff --git
a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
index 3047ffe7f244..621200e0823f 100644
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
@@ -450,6 +450,7 @@ int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev,
uint32_t *smu_versio int amdgpu_dpm_handle_passthrough_sbr(struct
amdgpu_device *adev, bool enable); int
amdgpu_dpm_send_hbm_bad_pages_num(struct amdgpu_device *adev, uint32_t size);
int amdgpu_dpm_send_hbm_bad_channel_flag(struct amdgpu_device *adev, uint32_t
size);
+int amdgpu_dpm_send_rma_reason(struct amdgpu_device *adev);
int amdgpu_dpm_get_dpm_freq_range(struct amdgpu_device *adev,
enum pp_clock_type type,
uint32_t *min, diff --git
a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 0ad947df777a..138dcb8724b6 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -3669,3 +3669,13 @@ int smu_send_hbm_bad_channel_flag(struct smu_context
*smu, uint32_t size)
return ret;
}
+
+int smu_send_rma_reason(struct smu_context *smu) {
+ int ret = 0;
+
+ if (smu->ppt_funcs && smu->ppt_funcs->send_rma_reason)
+ ret = smu->ppt_funcs->send_rma_reason(smu);
+
+ return ret;
+}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
index 66e84defd0b6..a870bdd49a4e 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
@@ -1341,6 +1341,11 @@ struct pptable_funcs {
*/
int (*send_hbm_bad_pages_num)(struct smu_context *smu, uint32_t size);
+ /**
+* @send_rma_reason: message rma reason event to SMU.
+*/
+ int (*send_rma_reason)(struct smu_context *smu);
+
/**
* @get_ecc_table: message SMU to get ECC INFO table.
*/
@@ -1588,5 +1593,6 @@ int smu_stb_collect_info(struct smu_context *smu, void
*buff, uint32_t size); void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device
*adev); int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t
size); int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t
size);
+int smu_send_rma_reason(struct smu_context *smu);
#endif
#endif
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h
b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h
index 509e3cd483fb..86758051
RE: [PATCH v2 1/2] drm/amdgpu: implement smu send rma reason for smu v13.0.6
[AMD Official Use Only - General]
With a nitpick below, the series is
Reviewed-by: Hawking Zhang
+ MSG_MAP(BadPageThreshold,
PPSMC_MSG_RmaDueToBadPageThreshold,0),
Might be better name it to RmaDueToBadPageThreshold/SMU_MSG_
RmaDueToBadPageThreshold
Regards,
Hawking
-Original Message-
From: Wang, Yang(Kevin)
Sent: Wednesday, February 7, 2024 21:54
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Zhou1, Tao ;
Lazar, Lijo ; Wang, Yang(Kevin)
Subject: [PATCH v2 1/2] drm/amdgpu: implement smu send rma reason for smu
v13.0.6
implement smu send rma reason function for smu v13.0.6
Signed-off-by: Yang Wang
Reviewed-by: Tao Zhou
---
drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 15 ++
drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h | 1 +
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 10 ++
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 6 ++
.../pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h | 3 ++-
drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h | 3 ++-
.../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 20 +++
7 files changed, 56 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
index 6627ee07d52d..f84bfed50681 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
@@ -693,6 +693,21 @@ int amdgpu_dpm_send_hbm_bad_channel_flag(struct
amdgpu_device *adev, uint32_t si
return ret;
}
+int amdgpu_dpm_send_rma_reason(struct amdgpu_device *adev) {
+ struct smu_context *smu = adev->powerplay.pp_handle;
+ int ret;
+
+ if (!is_support_sw_smu(adev))
+ return -EOPNOTSUPP;
+
+ mutex_lock(&adev->pm.mutex);
+ ret = smu_send_rma_reason(smu);
+ mutex_unlock(&adev->pm.mutex);
+
+ return ret;
+}
+
int amdgpu_dpm_get_dpm_freq_range(struct amdgpu_device *adev,
enum pp_clock_type type,
uint32_t *min,
diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
index 3047ffe7f244..621200e0823f 100644
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
@@ -450,6 +450,7 @@ int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev,
uint32_t *smu_versio int amdgpu_dpm_handle_passthrough_sbr(struct
amdgpu_device *adev, bool enable); int
amdgpu_dpm_send_hbm_bad_pages_num(struct amdgpu_device *adev, uint32_t size);
int amdgpu_dpm_send_hbm_bad_channel_flag(struct amdgpu_device *adev, uint32_t
size);
+int amdgpu_dpm_send_rma_reason(struct amdgpu_device *adev);
int amdgpu_dpm_get_dpm_freq_range(struct amdgpu_device *adev,
enum pp_clock_type type,
uint32_t *min,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 0ad947df777a..138dcb8724b6 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -3669,3 +3669,13 @@ int smu_send_hbm_bad_channel_flag(struct smu_context
*smu, uint32_t size)
return ret;
}
+
+int smu_send_rma_reason(struct smu_context *smu) {
+ int ret = 0;
+
+ if (smu->ppt_funcs && smu->ppt_funcs->send_rma_reason)
+ ret = smu->ppt_funcs->send_rma_reason(smu);
+
+ return ret;
+}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
index 66e84defd0b6..a870bdd49a4e 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
@@ -1341,6 +1341,11 @@ struct pptable_funcs {
*/
int (*send_hbm_bad_pages_num)(struct smu_context *smu, uint32_t size);
+ /**
+* @send_rma_reason: message rma reason event to SMU.
+*/
+ int (*send_rma_reason)(struct smu_context *smu);
+
/**
* @get_ecc_table: message SMU to get ECC INFO table.
*/
@@ -1588,5 +1593,6 @@ int smu_stb_collect_info(struct smu_context *smu, void
*buff, uint32_t size); void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device
*adev); int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t
size); int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t
size);
+int smu_send_rma_reason(struct smu_context *smu);
#endif
#endif
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h
b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h
index 509e3cd483fb..86758051cb93 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h
@@ -91,7 +91,8 @@
#define PPSMC_MSG_QueryValidMcaCeCount 0x3A
#define PPSMC_MSG_McaBankCeDumpDW 0x3B
#define PPSMC_MSG_SelectPLPDMode0x40
-#define PPSMC_Message_Count
[PATCH v2 2/2] drm/amdgpu: send smu rma reason event in ras eeprom driver
send smu rma reason event to smu in ras eeprom driver. Signed-off-by: Yang Wang --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c index 2fde93b00cab..b12808c0c331 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c @@ -735,6 +735,9 @@ amdgpu_ras_eeprom_update_header(struct amdgpu_ras_eeprom_control *control) control->tbl_rai.rma_status = GPU_RETIRED__ECC_REACH_THRESHOLD; control->tbl_rai.health_percent = 0; } + + /* ignore the -ENOTSUPP return value */ + amdgpu_dpm_send_rma_reason(adev); } if (control->tbl_hdr.version == RAS_TABLE_VER_V2_1) -- 2.34.1
[PATCH v2 1/2] drm/amdgpu: implement smu send rma reason for smu v13.0.6
implement smu send rma reason function for smu v13.0.6
Signed-off-by: Yang Wang
Reviewed-by: Tao Zhou
---
drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 15 ++
drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h | 1 +
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 10 ++
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 6 ++
.../pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h | 3 ++-
drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h | 3 ++-
.../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 20 +++
7 files changed, 56 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
index 6627ee07d52d..f84bfed50681 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
@@ -693,6 +693,21 @@ int amdgpu_dpm_send_hbm_bad_channel_flag(struct
amdgpu_device *adev, uint32_t si
return ret;
}
+int amdgpu_dpm_send_rma_reason(struct amdgpu_device *adev)
+{
+ struct smu_context *smu = adev->powerplay.pp_handle;
+ int ret;
+
+ if (!is_support_sw_smu(adev))
+ return -EOPNOTSUPP;
+
+ mutex_lock(&adev->pm.mutex);
+ ret = smu_send_rma_reason(smu);
+ mutex_unlock(&adev->pm.mutex);
+
+ return ret;
+}
+
int amdgpu_dpm_get_dpm_freq_range(struct amdgpu_device *adev,
enum pp_clock_type type,
uint32_t *min,
diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
index 3047ffe7f244..621200e0823f 100644
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
@@ -450,6 +450,7 @@ int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev,
uint32_t *smu_versio
int amdgpu_dpm_handle_passthrough_sbr(struct amdgpu_device *adev, bool enable);
int amdgpu_dpm_send_hbm_bad_pages_num(struct amdgpu_device *adev, uint32_t
size);
int amdgpu_dpm_send_hbm_bad_channel_flag(struct amdgpu_device *adev, uint32_t
size);
+int amdgpu_dpm_send_rma_reason(struct amdgpu_device *adev);
int amdgpu_dpm_get_dpm_freq_range(struct amdgpu_device *adev,
enum pp_clock_type type,
uint32_t *min,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 0ad947df777a..138dcb8724b6 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -3669,3 +3669,13 @@ int smu_send_hbm_bad_channel_flag(struct smu_context
*smu, uint32_t size)
return ret;
}
+
+int smu_send_rma_reason(struct smu_context *smu)
+{
+ int ret = 0;
+
+ if (smu->ppt_funcs && smu->ppt_funcs->send_rma_reason)
+ ret = smu->ppt_funcs->send_rma_reason(smu);
+
+ return ret;
+}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
index 66e84defd0b6..a870bdd49a4e 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
@@ -1341,6 +1341,11 @@ struct pptable_funcs {
*/
int (*send_hbm_bad_pages_num)(struct smu_context *smu, uint32_t size);
+ /**
+* @send_rma_reason: message rma reason event to SMU.
+*/
+ int (*send_rma_reason)(struct smu_context *smu);
+
/**
* @get_ecc_table: message SMU to get ECC INFO table.
*/
@@ -1588,5 +1593,6 @@ int smu_stb_collect_info(struct smu_context *smu, void
*buff, uint32_t size);
void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev);
int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size);
int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size);
+int smu_send_rma_reason(struct smu_context *smu);
#endif
#endif
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h
b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h
index 509e3cd483fb..86758051cb93 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h
@@ -91,7 +91,8 @@
#define PPSMC_MSG_QueryValidMcaCeCount 0x3A
#define PPSMC_MSG_McaBankCeDumpDW 0x3B
#define PPSMC_MSG_SelectPLPDMode0x40
-#define PPSMC_Message_Count 0x41
+#define PPSMC_MSG_RmaDueToBadPageThreshold 0x43
+#define PPSMC_Message_Count 0x44
//PPSMC Reset Types for driver msg argument
#define PPSMC_RESET_TYPE_DRIVER_MODE_1_RESET0x1
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
index 953a767613b1..efd97408b667 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
@@ -261,7 +261,8 @@
__SMU_DUMMY_MAP(SetSoftMaxVpe), \
__SMU_DUMMY_MAP(SetSoftMi
Re: [PATCH] drm/amd/pm: denote S to the actual clock
On 2/7/2024 2:03 PM, Kenneth Feng wrote:
> denote S to the actual clock in smu v13.0.0/v13.0.7/v13.0.10
>
> Signed-off-by: Kenneth Feng
> ---
> drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 12 ++--
> drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 12 ++--
> 2 files changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
> index 2e7518f4ae1a..63a930c4da01 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
> @@ -1270,18 +1270,18 @@ static int smu_v13_0_0_print_clk_levels(struct
> smu_context *smu,
>* - level 1 -> max clock freq
>* And the current clock frequency can be any value
> between them.
>* So, if the current clock frequency is not at level 0
> or level 1,
> - * we will fake it as three dpm levels:
> + * we will denote it to S:
> + * - level S -> current actual clock freq
S is not used to indicate actual clock always.
'S' is only used to indicate the "deep sleep state" of the clock. If the
clock is at deep sleep frequency ex: 95MHz, it's indicated by special
level S.
S:95Mhz*
0:500Mhz
1:1900Mhz
If the clock is active and operating as normal ex:1120MHz, the level is
not indicated by S. Sample values at that state will be
0:500Mhz
1:1120Mhz*
2:1900Mhz
Thanks,
Lijo
>* - level 0 -> min clock freq
> - * - level 1 -> current actual clock freq
> - * - level 2 -> max clock freq
> + * - level 1 -> max clock freq
>*/
> if ((single_dpm_table->dpm_levels[0].value !=
> curr_freq) &&
>(single_dpm_table->dpm_levels[1].value !=
> curr_freq)) {
> + size += sysfs_emit_at(buf, size, "S: %uMhz *\n",
> + curr_freq);
> size += sysfs_emit_at(buf, size, "0: %uMhz\n",
>
> single_dpm_table->dpm_levels[0].value);
> - size += sysfs_emit_at(buf, size, "1: %uMhz *\n",
> - curr_freq);
> - size += sysfs_emit_at(buf, size, "2: %uMhz\n",
> + size += sysfs_emit_at(buf, size, "1: %uMhz\n",
>
> single_dpm_table->dpm_levels[1].value);
> } else {
> size += sysfs_emit_at(buf, size, "0: %uMhz
> %s\n",
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
> index 0ffdb58af74e..dbdb50173de7 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
> @@ -1259,18 +1259,18 @@ static int smu_v13_0_7_print_clk_levels(struct
> smu_context *smu,
>* - level 1 -> max clock freq
>* And the current clock frequency can be any value
> between them.
>* So, if the current clock frequency is not at level 0
> or level 1,
> - * we will fake it as three dpm levels:
> + * we will denote it to S:
> + * - level S -> current actual clock freq
>* - level 0 -> min clock freq
> - * - level 1 -> current actual clock freq
> - * - level 2 -> max clock freq
> + * - level 1 -> max clock freq
>*/
> if ((single_dpm_table->dpm_levels[0].value !=
> curr_freq) &&
>(single_dpm_table->dpm_levels[1].value !=
> curr_freq)) {
> + size += sysfs_emit_at(buf, size, "S: %uMhz *\n",
> + curr_freq);
> size += sysfs_emit_at(buf, size, "0: %uMhz\n",
>
> single_dpm_table->dpm_levels[0].value);
> - size += sysfs_emit_at(buf, size, "1: %uMhz *\n",
> - curr_freq);
> - size += sysfs_emit_at(buf, size, "2: %uMhz\n",
> + size += sysfs_emit_at(buf, size, "1: %uMhz\n",
>
> single_dpm_table->dpm_levels[1].value);
> } else {
> size += sysfs_emit_at(buf, size, "0: %uMhz
> %s\n",
[PATCH] drm/amd/pm: denote S to the actual clock
denote S to the actual clock in smu v13.0.0/v13.0.7/v13.0.10
Signed-off-by: Kenneth Feng
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 12 ++--
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 12 ++--
2 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index 2e7518f4ae1a..63a930c4da01 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -1270,18 +1270,18 @@ static int smu_v13_0_0_print_clk_levels(struct
smu_context *smu,
* - level 1 -> max clock freq
* And the current clock frequency can be any value
between them.
* So, if the current clock frequency is not at level 0
or level 1,
-* we will fake it as three dpm levels:
+* we will denote it to S:
+* - level S -> current actual clock freq
* - level 0 -> min clock freq
-* - level 1 -> current actual clock freq
-* - level 2 -> max clock freq
+* - level 1 -> max clock freq
*/
if ((single_dpm_table->dpm_levels[0].value !=
curr_freq) &&
(single_dpm_table->dpm_levels[1].value !=
curr_freq)) {
+ size += sysfs_emit_at(buf, size, "S: %uMhz *\n",
+ curr_freq);
size += sysfs_emit_at(buf, size, "0: %uMhz\n",
single_dpm_table->dpm_levels[0].value);
- size += sysfs_emit_at(buf, size, "1: %uMhz *\n",
- curr_freq);
- size += sysfs_emit_at(buf, size, "2: %uMhz\n",
+ size += sysfs_emit_at(buf, size, "1: %uMhz\n",
single_dpm_table->dpm_levels[1].value);
} else {
size += sysfs_emit_at(buf, size, "0: %uMhz
%s\n",
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
index 0ffdb58af74e..dbdb50173de7 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
@@ -1259,18 +1259,18 @@ static int smu_v13_0_7_print_clk_levels(struct
smu_context *smu,
* - level 1 -> max clock freq
* And the current clock frequency can be any value
between them.
* So, if the current clock frequency is not at level 0
or level 1,
-* we will fake it as three dpm levels:
+* we will denote it to S:
+* - level S -> current actual clock freq
* - level 0 -> min clock freq
-* - level 1 -> current actual clock freq
-* - level 2 -> max clock freq
+* - level 1 -> max clock freq
*/
if ((single_dpm_table->dpm_levels[0].value !=
curr_freq) &&
(single_dpm_table->dpm_levels[1].value !=
curr_freq)) {
+ size += sysfs_emit_at(buf, size, "S: %uMhz *\n",
+ curr_freq);
size += sysfs_emit_at(buf, size, "0: %uMhz\n",
single_dpm_table->dpm_levels[0].value);
- size += sysfs_emit_at(buf, size, "1: %uMhz *\n",
- curr_freq);
- size += sysfs_emit_at(buf, size, "2: %uMhz\n",
+ size += sysfs_emit_at(buf, size, "1: %uMhz\n",
single_dpm_table->dpm_levels[1].value);
} else {
size += sysfs_emit_at(buf, size, "0: %uMhz
%s\n",
--
2.34.1
Re: drm/amdkfd: Relocate TBA/TMA to opposite side of VM hole (v2)
Hi Alexander, 在 2024/2/6 1:12, Deucher, Alexander 写道: Are you only seeing the problem with this patch applied or in general? If you are seeing it in general, it likely related to a firmware issue that was recently fixed that will be resolved with an update CP firmware image. Driver side changes: https://gitlab.freedesktop.org/agd5f/linux/-/commit/0eb6c664b780dd1b4080e047ad51b100cd7840a3 https://gitlab.freedesktop.org/agd5f/linux/-/commit/40970e60070ed3d1390ec65e38e819f6d81b8f0c Alex This problem is not affected by this patch, so possible the firmware issue. Where can I get the newest firmware image? Or is it already pushed to linux-firmware repo? Best regards, Shengyu OpenPGP_0xE3520CC91929C8E7.asc Description: OpenPGP public key OpenPGP_signature.asc Description: OpenPGP digital signature
[PATCH] drm/amd/display: fix NULL checks for adev->dm.dc in amdgpu_dm_fini()
Since 'adev->dm.dc' in amdgpu_dm_fini() might turn out to be NULL
before the call to dc_enable_dmub_notifications(), check
beforehand to ensure there will not be a possible NULL-ptr-deref
there.
Also, since commit 1e88eb1b2c25 ("drm/amd/display: Drop
CONFIG_DRM_AMD_DC_HDCP") there are two separate checks for NULL in
'adev->dm.dc' before dc_deinit_callbacks() and dc_dmub_srv_destroy().
Clean up by combining them all under one 'if'.
Found by Linux Verification Center (linuxtesting.org) with static
analysis tool SVACE.
Fixes: 81927e2808be ("drm/amd/display: Support for DMUB AUX")
Signed-off-by: Nikita Zhandarovich
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c| 16 +++-
1 file changed, 7 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index d292f290cd6e..46ac3e6f42bb 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1938,17 +1938,15 @@ static void amdgpu_dm_fini(struct amdgpu_device *adev)
adev->dm.hdcp_workqueue = NULL;
}
- if (adev->dm.dc)
+ if (adev->dm.dc) {
dc_deinit_callbacks(adev->dm.dc);
-
- if (adev->dm.dc)
dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);
-
- if (dc_enable_dmub_notifications(adev->dm.dc)) {
- kfree(adev->dm.dmub_notify);
- adev->dm.dmub_notify = NULL;
- destroy_workqueue(adev->dm.delayed_hpd_wq);
- adev->dm.delayed_hpd_wq = NULL;
+ if (dc_enable_dmub_notifications(adev->dm.dc)) {
+ kfree(adev->dm.dmub_notify);
+ adev->dm.dmub_notify = NULL;
+ destroy_workqueue(adev->dm.delayed_hpd_wq);
+ adev->dm.delayed_hpd_wq = NULL;
+ }
}
if (adev->dm.dmub_bo)
--
2.25.1
[PATCH] drm/radeon/ni: Fix wrong firmware size logging in ni_init_microcode()
Clean up a typo in pr_err() erroneously printing NI MC 'rdev->mc_fw->size'
during SMC firmware load. Log 'rdev->smc_fw->size' instead.
Found by Linux Verification Center (linuxtesting.org) with static
analysis tool SVACE.
Fixes: 6596afd48af4 ("drm/radeon/kms: add dpm support for btc (v3)")
Signed-off-by: Nikita Zhandarovich
---
drivers/gpu/drm/radeon/ni.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index 927e5f42e97d..3e48cbb522a1 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -813,7 +813,7 @@ int ni_init_microcode(struct radeon_device *rdev)
err = 0;
} else if (rdev->smc_fw->size != smc_req_size) {
pr_err("ni_mc: Bogus length %zu in firmware \"%s\"\n",
- rdev->mc_fw->size, fw_name);
+ rdev->smc_fw->size, fw_name);
err = -EINVAL;
}
}
--
2.25.1
