[PATCH 7/7] drm/amd/swsmu: support smu block discovery for smu v14
From: Kenneth Feng Support for smu ip block add for SMU v14. Signed-off-by: Kenneth Feng Reviewed-by: Likun Gao Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index 07c5fca061780..31964db7159fd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -1906,6 +1906,8 @@ static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev) break; case IP_VERSION(14, 0, 0): case IP_VERSION(14, 0, 1): + case IP_VERSION(14, 0, 2): + case IP_VERSION(14, 0, 3): amdgpu_device_ip_block_add(adev, _v14_0_ip_block); break; default: -- 2.44.0
[PATCH 4/7] drm/amd/swsmu: add pptable header for smu v14_0_2
From: Likun Gao
Add pptable header for smu v14_0_2.
Signed-off-by: Likun Gao
Reviewed-by: Kenneth Feng
Signed-off-by: Alex Deucher
---
.../amd/pm/swsmu/inc/smu_v14_0_2_pptable.h| 164 ++
1 file changed, 164 insertions(+)
create mode 100644 drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0_2_pptable.h
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0_2_pptable.h
b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0_2_pptable.h
new file mode 100644
index 0..4a3fde89aed73
--- /dev/null
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0_2_pptable.h
@@ -0,0 +1,164 @@
+/*
+ * Copyright 2023 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef SMU_14_0_2_PPTABLE_H
+#define SMU_14_0_2_PPTABLE_H
+
+
+#pragma pack(push, 1)
+
+#define SMU_14_0_2_TABLE_FORMAT_REVISION 3
+
+// POWERPLAYTABLE::ulPlatformCaps
+#define SMU_14_0_2_PP_PLATFORM_CAP_POWERPLAY0x1 // This cap
indicates whether CCC need to show Powerplay page.
+#define SMU_14_0_2_PP_PLATFORM_CAP_SBIOSPOWERSOURCE 0x2 // This cap
indicates whether power source notificaiton is done by SBIOS instead of OS.
+#define SMU_14_0_2_PP_PLATFORM_CAP_HARDWAREDC 0x4 // This cap
indicates whether DC mode notificaiton is done by GPIO pin directly.
+#define SMU_14_0_2_PP_PLATFORM_CAP_BACO 0x8 // This cap
indicates whether board supports the BACO circuitry.
+#define SMU_14_0_2_PP_PLATFORM_CAP_MACO 0x10// This cap
indicates whether board supports the MACO circuitry.
+#define SMU_14_0_2_PP_PLATFORM_CAP_SHADOWPSTATE 0x20// This cap
indicates whether board supports the Shadow Pstate.
+#define SMU_14_0_2_PP_PLATFORM_CAP_LEDSUPPORTED 0x40// This cap
indicates whether board supports the LED.
+#define SMU_14_0_2_PP_PLATFORM_CAP_MOBILEOVERDRIVE 0x80// This cap
indicates whether board supports the Mobile Overdrive.
+
+// SMU_14_0_2_PP_THERMALCONTROLLER - Thermal Controller Type
+#define SMU_14_0_2_PP_THERMALCONTROLLER_NONE0
+
+#define SMU_14_0_2_PP_OVERDRIVE_VERSION 0x1 // TODO: FIX
OverDrive Version TBD
+#define SMU_14_0_2_PP_POWERSAVINGCLOCK_VERSION 0x01// Power Saving
Clock Table Version 1.00
+
+enum SMU_14_0_2_OD_SW_FEATURE_CAP
+{
+SMU_14_0_2_ODCAP_AUTO_FAN_ACOUSTIC_LIMIT= 0,
+SMU_14_0_2_ODCAP_POWER_MODE = 1,
+SMU_14_0_2_ODCAP_AUTO_UV_ENGINE = 2,
+SMU_14_0_2_ODCAP_AUTO_OC_ENGINE = 3,
+SMU_14_0_2_ODCAP_AUTO_OC_MEMORY = 4,
+SMU_14_0_2_ODCAP_MEMORY_TIMING_TUNE = 5,
+SMU_14_0_2_ODCAP_MANUAL_AC_TIMING = 6,
+SMU_14_0_2_ODCAP_AUTO_VF_CURVE_OPTIMIZER= 7,
+SMU_14_0_2_ODCAP_AUTO_SOC_UV= 8,
+SMU_14_0_2_ODCAP_COUNT = 9,
+};
+
+enum SMU_14_0_2_OD_SW_FEATURE_ID
+{
+SMU_14_0_2_ODFEATURE_AUTO_FAN_ACOUSTIC_LIMIT = 1 <<
SMU_14_0_2_ODCAP_AUTO_FAN_ACOUSTIC_LIMIT, // Auto Fan Acoustic RPM
+SMU_14_0_2_ODFEATURE_POWER_MODE = 1 <<
SMU_14_0_2_ODCAP_POWER_MODE, // Optimized GPU Power Mode
+SMU_14_0_2_ODFEATURE_AUTO_UV_ENGINE = 1 <<
SMU_14_0_2_ODCAP_AUTO_UV_ENGINE, // Auto Under Volt GFXCLK
+SMU_14_0_2_ODFEATURE_AUTO_OC_ENGINE = 1 <<
SMU_14_0_2_ODCAP_AUTO_OC_ENGINE, // Auto Over Clock GFXCLK
+SMU_14_0_2_ODFEATURE_AUTO_OC_MEMORY = 1 <<
SMU_14_0_2_ODCAP_AUTO_OC_MEMORY, // Auto Over Clock MCLK
+SMU_14_0_2_ODFEATURE_MEMORY_TIMING_TUNE = 1 <<
SMU_14_0_2_ODCAP_MEMORY_TIMING_TUNE, // Auto AC Timing Tuning
+SMU_14_0_2_ODFEATURE_MANUAL_AC_TIMING = 1 <<
SMU_14_0_2_ODCAP_MANUAL_AC_TIMING, // Manual fine grain AC Timing
tuning
+SMU_14_0_2_ODFEATURE_AUTO_VF_CURVE_OPTIMIZER = 1 <<
[PATCH 2/7] drm/amd/swsmu: add smu14 driver if file
From: Kenneth Feng Add initial smu14 driver if file v2: squash in updates (Alex) v3: squash in updates (Alex) v4: squash in updates (Alex) Signed-off-by: Kenneth Feng Reviewed-by: Likun Gao Signed-off-by: Alex Deucher --- .../swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h | 1836 + 1 file changed, 1836 insertions(+) create mode 100644 drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h new file mode 100644 index 0..97a29b80fb133 --- /dev/null +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h @@ -0,0 +1,1836 @@ +/* + * Copyright 2023 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef SMU14_DRIVER_IF_V14_0_H +#define SMU14_DRIVER_IF_V14_0_H + +//Increment this version if SkuTable_t or BoardTable_t change +#define PPTABLE_VERSION 0x18 + +#define NUM_GFXCLK_DPM_LEVELS16 +#define NUM_SOCCLK_DPM_LEVELS8 +#define NUM_MP0CLK_DPM_LEVELS2 +#define NUM_DCLK_DPM_LEVELS 8 +#define NUM_VCLK_DPM_LEVELS 8 +#define NUM_DISPCLK_DPM_LEVELS 8 +#define NUM_DPPCLK_DPM_LEVELS8 +#define NUM_DPREFCLK_DPM_LEVELS 8 +#define NUM_DCFCLK_DPM_LEVELS8 +#define NUM_DTBCLK_DPM_LEVELS8 +#define NUM_UCLK_DPM_LEVELS 6 +#define NUM_LINK_LEVELS 3 +#define NUM_FCLK_DPM_LEVELS 8 +#define NUM_OD_FAN_MAX_POINTS6 + +// Feature Control Defines +#define FEATURE_FW_DATA_READ_BIT 0 +#define FEATURE_DPM_GFXCLK_BIT1 +#define FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT 2 +#define FEATURE_DPM_UCLK_BIT 3 +#define FEATURE_DPM_FCLK_BIT 4 +#define FEATURE_DPM_SOCCLK_BIT5 +#define FEATURE_DPM_LINK_BIT 6 +#define FEATURE_DPM_DCN_BIT 7 +#define FEATURE_VMEMP_SCALING_BIT 8 +#define FEATURE_VDDIO_MEM_SCALING_BIT 9 +#define FEATURE_DS_GFXCLK_BIT 10 +#define FEATURE_DS_SOCCLK_BIT 11 +#define FEATURE_DS_FCLK_BIT 12 +#define FEATURE_DS_LCLK_BIT 13 +#define FEATURE_DS_DCFCLK_BIT 14 +#define FEATURE_DS_UCLK_BIT 15 +#define FEATURE_GFX_ULV_BIT 16 +#define FEATURE_FW_DSTATE_BIT 17 +#define FEATURE_GFXOFF_BIT18 +#define FEATURE_BACO_BIT 19 +#define FEATURE_MM_DPM_BIT20 +#define FEATURE_SOC_MPCLK_DS_BIT 21 +#define FEATURE_BACO_MPCLK_DS_BIT 22 +#define FEATURE_THROTTLERS_BIT23 +#define FEATURE_SMARTSHIFT_BIT24 +#define FEATURE_GTHR_BIT 25 +#define FEATURE_ACDC_BIT 26 +#define FEATURE_VR0HOT_BIT27 +#define FEATURE_FW_CTF_BIT28 +#define FEATURE_FAN_CONTROL_BIT 29 +#define FEATURE_GFX_DCS_BIT 30 +#define FEATURE_GFX_READ_MARGIN_BIT 31 +#define FEATURE_LED_DISPLAY_BIT 32 +#define FEATURE_GFXCLK_SPREAD_SPECTRUM_BIT33 +#define FEATURE_OUT_OF_BAND_MONITOR_BIT 34 +#define FEATURE_OPTIMIZED_VMIN_BIT35 +#define FEATURE_GFX_IMU_BIT 36 +#define FEATURE_BOOT_TIME_CAL_BIT 37 +#define FEATURE_GFX_PCC_DFLL_BIT 38 +#define FEATURE_SOC_CG_BIT39 +#define FEATURE_DF_CSTATE_BIT 40 +#define FEATURE_GFX_EDC_BIT 41 +#define FEATURE_BOOT_POWER_OPT_BIT42 +#define FEATURE_CLOCK_POWER_DOWN_BYPASS_BIT 43 +#define FEATURE_DS_VCN_BIT44 +#define FEATURE_BACO_CG_BIT 45 +#define FEATURE_MEM_TEMP_READ_BIT 46 +#define FEATURE_ATHUB_MMHUB_PG_BIT47 +#define
[PATCH 5/7] drm/amd/swsmu: add smu v14_0_2 support
From: Likun Gao
Add initial support for smu v14_0_2.
v2: fix warnings (Alex)
v3: squash in various fixes (Alex)
v4: squash in various fixes (Alex)
v5: remove hardcoded pptable id (Alex)
v6: update fw version (Alex)
v7: squash in more updates (Alex)
v8: rebase, squash in pptable override updates,
combo table updates, SW CTF support (Alex)
Signed-off-by: Kenneth Feng
Signed-off-by: Likun Gao
Reviewed-by: Likun Gao
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h |2 +-
drivers/gpu/drm/amd/pm/swsmu/smu14/Makefile |2 +-
.../gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c| 40 +-
.../drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c | 1796 +
.../drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.h | 28 +
5 files changed, 1864 insertions(+), 4 deletions(-)
create mode 100644 drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
create mode 100644 drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.h
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h
b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h
index be5b24d3dabdb..1fc4557e6fb44 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h
@@ -28,7 +28,7 @@
#define SMU14_DRIVER_IF_VERSION_INV 0x
#define SMU14_DRIVER_IF_VERSION_SMU_V14_0_0 0x7
#define SMU14_DRIVER_IF_VERSION_SMU_V14_0_1 0x6
-#define SMU14_DRIVER_IF_VERSION_SMU_V14_0_2 0x1
+#define SMU14_DRIVER_IF_VERSION_SMU_V14_0_2 0x25
#define FEATURE_MASK(feature) (1ULL << feature)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/Makefile
b/drivers/gpu/drm/amd/pm/swsmu/smu14/Makefile
index ddbac5c655f76..4593e29e8ff80 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu14/Makefile
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/Makefile
@@ -23,7 +23,7 @@
# Makefile for the 'smu manager' sub-component of powerplay.
# It provides the smu management services for the driver.
-SMU14_MGR = smu_v14_0.o smu_v14_0_0_ppt.o
+SMU14_MGR = smu_v14_0.o smu_v14_0_0_ppt.o smu_v14_0_2_ppt.o
AMD_SWSMU_SMU14MGR = $(addprefix $(AMD_SWSMU_PATH)/smu14/,$(SMU14_MGR))
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
index 33fc0331fac2d..3bc9662fbd283 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
@@ -172,6 +172,10 @@ int smu_v14_0_init_pptable_microcode(struct smu_context
*smu)
if (!adev->scpm_enabled)
return 0;
+ if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 2)) ||
+ (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 3)))
+ return 0;
+
/* override pptable_id from driver parameter */
if (amdgpu_smu_pptable_id >= 0) {
pptable_id = amdgpu_smu_pptable_id;
@@ -245,6 +249,7 @@ int smu_v14_0_check_fw_version(struct smu_context *smu)
smu->smc_driver_if_version =
SMU14_DRIVER_IF_VERSION_SMU_V14_0_1;
break;
case IP_VERSION(14, 0, 2):
+ case IP_VERSION(14, 0, 3):
smu->smc_driver_if_version =
SMU14_DRIVER_IF_VERSION_SMU_V14_0_2;
break;
default:
@@ -895,11 +900,32 @@ static int smu_v14_0_set_irq_state(struct amdgpu_device
*adev,
return 0;
}
+#define THM_11_0__SRCID__THM_DIG_THERM_L2H 0 /*
ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH */
+#define THM_11_0__SRCID__THM_DIG_THERM_H2L 1 /*
ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL */
+
static int smu_v14_0_irq_process(struct amdgpu_device *adev,
struct amdgpu_irq_src *source,
struct amdgpu_iv_entry *entry)
{
- // TODO
+ struct smu_context *smu = adev->powerplay.pp_handle;
+ uint32_t client_id = entry->client_id;
+ uint32_t src_id = entry->src_id;
+
+ if (client_id == SOC15_IH_CLIENTID_THM) {
+ switch (src_id) {
+ case THM_11_0__SRCID__THM_DIG_THERM_L2H:
+ schedule_delayed_work(>swctf_delayed_work,
+
msecs_to_jiffies(AMDGPU_SWCTF_EXTRA_DELAY));
+ break;
+ case THM_11_0__SRCID__THM_DIG_THERM_H2L:
+ dev_emerg(adev->dev, "ERROR: GPU under temperature
range detected\n");
+ break;
+ default:
+ dev_emerg(adev->dev, "ERROR: GPU under temperature
range unknown src id (%d)\n",
+ src_id);
+ break;
+ }
+ }
return 0;
}
@@ -921,7 +947,17 @@ int smu_v14_0_register_irq_handler(struct smu_context *smu)
irq_src->num_types = 1;
irq_src->funcs = _v14_0_irq_funcs;
- // TODO: THM related
+ ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
+
[PATCH 6/7] drm/amd/swsmu: support SMU_14_0_2 ppt_funcs
From: Likun Gao Add smu v14_0_2 ppt fucs support. v2: squash in updates (Alex) Signed-off-by: Likun Gao Reviewed-by: Kenneth Feng Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index dc2a864b0f512..7789b313285c4 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -45,6 +45,7 @@ #include "smu_v13_0_6_ppt.h" #include "smu_v13_0_7_ppt.h" #include "smu_v14_0_0_ppt.h" +#include "smu_v14_0_2_ppt.h" #include "amd_pcie.h" /* @@ -715,6 +716,10 @@ static int smu_set_funcs(struct amdgpu_device *adev) case IP_VERSION(14, 0, 1): smu_v14_0_0_set_ppt_funcs(smu); break; + case IP_VERSION(14, 0, 2): + case IP_VERSION(14, 0, 3): + smu_v14_0_2_set_ppt_funcs(smu); + break; default: return -EINVAL; } -- 2.44.0
[PATCH 3/7] drm/amd/swsmu: add smu v14_0_2 ppsmc file
From: Kenneth Feng Add initial smu v14_0_2 ppsmc file v2: Squash in updates (Alex) v3: Squash in updates (Alex) Signed-off-by: Kenneth Feng Reviewed-by: Likun Gao Signed-off-by: Alex Deucher --- .../pm/swsmu/inc/pmfw_if/smu_v14_0_2_ppsmc.h | 140 ++ 1 file changed, 140 insertions(+) create mode 100644 drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_2_ppsmc.h diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_2_ppsmc.h b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_2_ppsmc.h new file mode 100644 index 0..de2e442281ffe --- /dev/null +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_2_ppsmc.h @@ -0,0 +1,140 @@ +/* + * Copyright 2023 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef SMU_V14_0_2_PPSMC_H +#define SMU_V14_0_2_PPSMC_H + +#define PPSMC_VERSION 0x1 + +// SMU Response Codes: +#define PPSMC_Result_OK0x1 +#define PPSMC_Result_Failed0xFF +#define PPSMC_Result_UnknownCmd0xFE +#define PPSMC_Result_CmdRejectedPrereq 0xFD +#define PPSMC_Result_CmdRejectedBusy 0xFC + +// Message Definitions: +// BASIC +#define PPSMC_MSG_TestMessage0x1 +#define PPSMC_MSG_GetSmuVersion 0x2 +#define PPSMC_MSG_GetDriverIfVersion 0x3 +#define PPSMC_MSG_SetAllowedFeaturesMaskLow 0x4 +#define PPSMC_MSG_SetAllowedFeaturesMaskHigh 0x5 +#define PPSMC_MSG_EnableAllSmuFeatures 0x6 +#define PPSMC_MSG_DisableAllSmuFeatures 0x7 +#define PPSMC_MSG_EnableSmuFeaturesLow 0x8 +#define PPSMC_MSG_EnableSmuFeaturesHigh 0x9 +#define PPSMC_MSG_DisableSmuFeaturesLow 0xA +#define PPSMC_MSG_DisableSmuFeaturesHigh 0xB +#define PPSMC_MSG_GetRunningSmuFeaturesLow 0xC +#define PPSMC_MSG_GetRunningSmuFeaturesHigh 0xD +#define PPSMC_MSG_SetDriverDramAddrHigh 0xE +#define PPSMC_MSG_SetDriverDramAddrLow 0xF +#define PPSMC_MSG_SetToolsDramAddrHigh 0x10 +#define PPSMC_MSG_SetToolsDramAddrLow0x11 +#define PPSMC_MSG_TransferTableSmu2Dram 0x12 +#define PPSMC_MSG_TransferTableDram2Smu 0x13 +#define PPSMC_MSG_UseDefaultPPTable 0x14 + +//BACO/BAMACO/BOMACO +#define PPSMC_MSG_EnterBaco 0x15 +#define PPSMC_MSG_ExitBaco 0x16 +#define PPSMC_MSG_ArmD3 0x17 +#define PPSMC_MSG_BacoAudioD3PME 0x18 + +//DPM +#define PPSMC_MSG_SetSoftMinByFreq 0x19 +#define PPSMC_MSG_SetSoftMaxByFreq 0x1A +#define PPSMC_MSG_SetHardMinByFreq 0x1B +#define PPSMC_MSG_SetHardMaxByFreq 0x1C +#define PPSMC_MSG_GetMinDpmFreq 0x1D +#define PPSMC_MSG_GetMaxDpmFreq 0x1E +#define PPSMC_MSG_GetDpmFreqByIndex 0x1F +#define PPSMC_MSG_OverridePcieParameters 0x20 + +//DramLog Set DramAddr +#define PPSMC_MSG_DramLogSetDramAddrHigh 0x21 +#define PPSMC_MSG_DramLogSetDramAddrLow 0x22 +#define PPSMC_MSG_DramLogSetDramSize 0x23 +#define PPSMC_MSG_SetWorkloadMask0x24 + +#define PPSMC_MSG_GetVoltageByDpm0x25 // Can be removed +#define PPSMC_MSG_SetVideoFps0x26 // Can be removed +#define PPSMC_MSG_GetDcModeMaxDpmFreq0x27 + +//Power Gating +#define PPSMC_MSG_AllowGfxOff0x28 +#define PPSMC_MSG_DisallowGfxOff 0x29 +#define PPSMC_MSG_PowerUpVcn 0x2A +#define PPSMC_MSG_PowerDownVcn 0x2B +#define PPSMC_MSG_PowerUpJpeg0x2C +#define PPSMC_MSG_PowerDownJpeg 0x2D + +//Resets +#define PPSMC_MSG_PrepareMp1ForUnload0x2E +#define PPSMC_MSG_Mode1Reset 0x2F + +//Set SystemVirtual DramAddrHigh +#define
[PATCH 1/7] drm/amd/swsmu: add smu14 ip support
From: Kenneth Feng
Add initial swSMU support for smu 14 series ASIC.
v2: rebase (Alex)
Signed-off-by: Kenneth Feng
Signed-off-by: Likun Gao
Reviewed-by: Likun Gao
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h | 3 +-
.../gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c| 77 +--
2 files changed, 54 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h
b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h
index 6cdfee5052d9a..be5b24d3dabdb 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h
@@ -39,7 +39,8 @@
#define MP1_SRAM 0x03c4
/* address block */
-#define smnMP1_FIRMWARE_FLAGS 0x3010028
+#define smnMP1_FIRMWARE_FLAGS_14_0_0 0x3010028
+#define smnMP1_FIRMWARE_FLAGS 0x3010024
#define smnMP1_PUB_CTRL0x3010d10
#define MAX_DPM_LEVELS 16
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
index 2c3517397b141..33fc0331fac2d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
@@ -38,8 +38,13 @@
#include "amdgpu_ras.h"
#include "smu_cmn.h"
-#include "asic_reg/mp/mp_14_0_0_offset.h"
-#include "asic_reg/mp/mp_14_0_0_sh_mask.h"
+#include "asic_reg/mp/mp_14_0_2_offset.h"
+#include "asic_reg/mp/mp_14_0_2_sh_mask.h"
+
+#define regMP1_SMN_IH_SW_INT_mp1_14_0_00x0341
+#define regMP1_SMN_IH_SW_INT_mp1_14_0_0_BASE_IDX0
+#define regMP1_SMN_IH_SW_INT_CTRL_mp1_14_0_00x0342
+#define regMP1_SMN_IH_SW_INT_CTRL_mp1_14_0_0_BASE_IDX 0
/*
* DO NOT use these for err/warn/info/debug messages.
@@ -52,6 +57,7 @@
#undef pr_debug
MODULE_FIRMWARE("amdgpu/smu_14_0_2.bin");
+MODULE_FIRMWARE("amdgpu/smu_14_0_3.bin");
#define ENABLE_IMU_ARG_GFXOFF_ENABLE 1
@@ -59,7 +65,7 @@ int smu_v14_0_init_microcode(struct smu_context *smu)
{
struct amdgpu_device *adev = smu->adev;
char fw_name[30];
- char ucode_prefix[15];
+ char ucode_prefix[30];
int err = 0;
const struct smc_firmware_header_v1_0 *hdr;
const struct common_firmware_header *header;
@@ -106,7 +112,6 @@ void smu_v14_0_fini_microcode(struct smu_context *smu)
int smu_v14_0_load_microcode(struct smu_context *smu)
{
-#if 0
struct amdgpu_device *adev = smu->adev;
const uint32_t *src;
const struct smc_firmware_header_v1_0 *hdr;
@@ -131,8 +136,12 @@ int smu_v14_0_load_microcode(struct smu_context *smu)
1 & ~MP1_SMN_PUB_CTRL__LX3_RESET_MASK);
for (i = 0; i < adev->usec_timeout; i++) {
- mp1_fw_flags = RREG32_PCIE(MP1_Public |
- (smnMP1_FIRMWARE_FLAGS &
0x));
+ if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0,
0))
+ mp1_fw_flags = RREG32_PCIE(MP1_Public |
+
(smnMP1_FIRMWARE_FLAGS_14_0_0 & 0x));
+ else
+ mp1_fw_flags = RREG32_PCIE(MP1_Public |
+ (smnMP1_FIRMWARE_FLAGS &
0x));
if ((mp1_fw_flags &
MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
break;
@@ -142,9 +151,7 @@ int smu_v14_0_load_microcode(struct smu_context *smu)
if (i == adev->usec_timeout)
return -ETIME;
-#endif
return 0;
-
}
int smu_v14_0_init_pptable_microcode(struct smu_context *smu)
@@ -198,7 +205,11 @@ int smu_v14_0_check_fw_status(struct smu_context *smu)
struct amdgpu_device *adev = smu->adev;
uint32_t mp1_fw_flags;
- mp1_fw_flags = RREG32_PCIE(MP1_Public |
+ if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0))
+ mp1_fw_flags = RREG32_PCIE(MP1_Public |
+ (smnMP1_FIRMWARE_FLAGS_14_0_0 &
0x));
+ else
+ mp1_fw_flags = RREG32_PCIE(MP1_Public |
(smnMP1_FIRMWARE_FLAGS &
0x));
if ((mp1_fw_flags &
MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
@@ -227,16 +238,15 @@ int smu_v14_0_check_fw_version(struct smu_context *smu)
adev->pm.fw_version = smu_version;
switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
- case IP_VERSION(14, 0, 2):
- smu->smc_driver_if_version =
SMU14_DRIVER_IF_VERSION_SMU_V14_0_2;
- break;
case IP_VERSION(14, 0, 0):
smu->smc_driver_if_version =
SMU14_DRIVER_IF_VERSION_SMU_V14_0_0;
break;
case IP_VERSION(14, 0, 1):
smu->smc_driver_if_version =
[PATCH 1/2] drm/amdgpu: Load ipkeymgr drv for psp v14
From: Hawking Zhang
while DBG_DRV is renamed to HAD_DRV for psp v14,
part of its APIs/functionality is moved to a new
component named Ipkeymgr_Drv.
Signed-off-by: Hawking Zhang
Reviewed-by: Likun Gao
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 15 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 8 +++-
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 1 +
drivers/gpu/drm/amd/amdgpu/psp_v14_0.c| 5 +
4 files changed, 28 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index edae581059af0..4bd4602d11b1e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -2265,6 +2265,15 @@ static int psp_hw_start(struct psp_context *psp)
}
}
+ if ((is_psp_fw_valid(psp->ipkeymgr_drv)) &&
+ (psp->funcs->bootloader_load_ipkeymgr_drv != NULL)) {
+ ret = psp_bootloader_load_ipkeymgr_drv(psp);
+ if (ret) {
+ dev_err(adev->dev, "PSP load ipkeymgr_drv
failed!\n");
+ return ret;
+ }
+ }
+
if ((is_psp_fw_valid(psp->sos)) &&
(psp->funcs->bootloader_load_sos != NULL)) {
ret = psp_bootloader_load_sos(psp);
@@ -3280,6 +3289,12 @@ static int parse_sos_bin_descriptor(struct psp_context
*psp,
psp->ras_drv.size_bytes = le32_to_cpu(desc->size_bytes);
psp->ras_drv.start_addr = ucode_start_addr;
break;
+ case PSP_FW_TYPE_PSP_IPKEYMGR_DRV:
+ psp->ipkeymgr_drv.fw_version =
le32_to_cpu(desc->fw_version);
+ psp->ipkeymgr_drv.feature_version=
le32_to_cpu(desc->fw_version);
+ psp->ipkeymgr_drv.size_bytes =
le32_to_cpu(desc->size_bytes);
+ psp->ipkeymgr_drv.start_addr = ucode_start_addr;
+ break;
default:
dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n",
desc->fw_type);
break;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index ee16f134ae920..66b3f88fbecdd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -74,7 +74,8 @@ enum psp_bootloader_cmd {
PSP_BL__LOAD_SOCDRV = 0xB,
PSP_BL__LOAD_DBGDRV = 0xC,
PSP_BL__LOAD_INTFDRV= 0xD,
- PSP_BL__LOAD_RASDRV = 0xE,
+ PSP_BL__LOAD_RASDRV = 0xE,
+ PSP_BL__LOAD_IPKEYMGRDRV= 0xF,
PSP_BL__DRAM_LONG_TRAIN = 0x10,
PSP_BL__DRAM_SHORT_TRAIN= 0x20,
PSP_BL__LOAD_TOS_SPL_TABLE = 0x1000,
@@ -117,6 +118,7 @@ struct psp_funcs {
int (*bootloader_load_intf_drv)(struct psp_context *psp);
int (*bootloader_load_dbg_drv)(struct psp_context *psp);
int (*bootloader_load_ras_drv)(struct psp_context *psp);
+ int (*bootloader_load_ipkeymgr_drv)(struct psp_context *psp);
int (*bootloader_load_sos)(struct psp_context *psp);
int (*ring_create)(struct psp_context *psp,
enum psp_ring_type ring_type);
@@ -336,6 +338,7 @@ struct psp_context {
struct psp_bin_desc intf_drv;
struct psp_bin_desc dbg_drv;
struct psp_bin_desc ras_drv;
+ struct psp_bin_desc ipkeymgr_drv;
/* tmr buffer */
struct amdgpu_bo*tmr_bo;
@@ -424,6 +427,9 @@ struct amdgpu_psp_funcs {
#define psp_bootloader_load_ras_drv(psp) \
((psp)->funcs->bootloader_load_ras_drv ? \
(psp)->funcs->bootloader_load_ras_drv((psp)) : 0)
+#define psp_bootloader_load_ipkeymgr_drv(psp) \
+ ((psp)->funcs->bootloader_load_ipkeymgr_drv ? \
+(psp)->funcs->bootloader_load_ipkeymgr_drv((psp)) : 0)
#define psp_bootloader_load_sos(psp) \
((psp)->funcs->bootloader_load_sos ?
(psp)->funcs->bootloader_load_sos((psp)) : 0)
#define psp_smu_reload_quirk(psp) \
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
index 6194457600372..105d4de0613af 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
@@ -125,6 +125,7 @@ enum psp_fw_type {
PSP_FW_TYPE_PSP_INTF_DRV,
PSP_FW_TYPE_PSP_DBG_DRV,
PSP_FW_TYPE_PSP_RAS_DRV,
+ PSP_FW_TYPE_PSP_IPKEYMGR_DRV,
PSP_FW_TYPE_MAX_INDEX,
};
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v14_0.c
b/drivers/gpu/drm/amd/amdgpu/psp_v14_0.c
index 78a95f8f370be..241d5ff2ef3cd 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v14_0.c
+++
[PATCH 2/2] drm/amdgpu: rename DBG_DRV to HAD_DRV for psp v14
From: Hawking Zhang
Add a psp bl command enum for HAD_DRV.
Signed-off-by: Hawking Zhang
Reviewed-by: Likun Gao
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 1 +
drivers/gpu/drm/amd/amdgpu/psp_v14_0.c | 3 ++-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index 66b3f88fbecdd..3635303e65484 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -73,6 +73,7 @@ enum psp_bootloader_cmd {
PSP_BL__LOAD_KEY_DATABASE = 0x8,
PSP_BL__LOAD_SOCDRV = 0xB,
PSP_BL__LOAD_DBGDRV = 0xC,
+ PSP_BL__LOAD_HADDRV = PSP_BL__LOAD_DBGDRV,
PSP_BL__LOAD_INTFDRV= 0xD,
PSP_BL__LOAD_RASDRV = 0xE,
PSP_BL__LOAD_IPKEYMGRDRV= 0xF,
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v14_0.c
b/drivers/gpu/drm/amd/amdgpu/psp_v14_0.c
index 241d5ff2ef3cd..f08a32c186946 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v14_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v14_0.c
@@ -169,7 +169,8 @@ static int psp_v14_0_bootloader_load_intf_drv(struct
psp_context *psp)
static int psp_v14_0_bootloader_load_dbg_drv(struct psp_context *psp)
{
- return psp_v14_0_bootloader_load_component(psp, >dbg_drv,
PSP_BL__LOAD_DBGDRV);
+ /* dbg_drv was renamed to had_drv in psp v14 */
+ return psp_v14_0_bootloader_load_component(psp, >dbg_drv,
PSP_BL__LOAD_HADDRV);
}
static int psp_v14_0_bootloader_load_ras_drv(struct psp_context *psp)
--
2.44.0
Re: [PATCH] drm/amdgpu: replace tmz flag into buffer flag
On Fri, Apr 12, 2024 at 8:17 AM Min, Frank wrote:
>
> [AMD Official Use Only - General]
>
> From: Frank Min
>
> Replace tmz flag into buffer flag to make it easier to understand and extend
>
> Signed-off-by: Likun Gao
> Signed-off-by: Frank Min
Before you push this to amd-staging-drm-next, can you squash in the
si_dma.c fix and update the kerneldoc above each function to reflect
the new parameter?
Alex
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_object.c| 2 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h | 4 ++--
> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 18 +++---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 4 +++-
> drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c| 2 +-
> drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c| 2 +-
> drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c| 4 ++--
> drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c| 4 ++--
> drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c| 4 ++--
> drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c| 4 ++--
> drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c| 5 +++--
> drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 4 ++--
> 15 files changed, 36 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
> index edc6377ec5ff..199693369c7c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
> @@ -39,7 +39,7 @@ static int amdgpu_benchmark_do_move(struct amdgpu_device
> *adev, unsigned size,
> for (i = 0; i < n; i++) {
> struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
> r = amdgpu_copy_buffer(ring, saddr, daddr, size, NULL, ,
> - false, false, false);
> + false, false, 0);
> if (r)
> goto exit_do_move;
> r = dma_fence_wait(fence, false);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> index 38742ff0ff49..abb1505c82ec 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> @@ -791,7 +791,7 @@ int amdgpu_bo_restore_shadow(struct amdgpu_bo *shadow,
> struct dma_fence **fence)
>
> return amdgpu_copy_buffer(ring, shadow_addr, parent_addr,
> amdgpu_bo_size(shadow), NULL, fence,
> - true, false, false);
> + true, false, 0);
> }
>
> /**
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
> index a22c6446817b..b5bde6652838 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
> @@ -136,7 +136,7 @@ struct amdgpu_buffer_funcs {
> uint64_t dst_offset,
> /* number of byte to transfer */
> uint32_t byte_count,
> -bool tmz);
> +uint32_t copy_flags);
>
> /* maximum bytes in a single operation */
> uint32_tfill_max_bytes;
> @@ -154,7 +154,7 @@ struct amdgpu_buffer_funcs {
> uint32_t byte_count);
> };
>
> -#define amdgpu_emit_copy_buffer(adev, ib, s, d, b, t)
> (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b), (t))
> +#define amdgpu_emit_copy_buffer(adev, ib, s, d, b, f)
> +(adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b), (f))
> #define amdgpu_emit_fill_buffer(adev, ib, s, d, b)
> (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
>
> struct amdgpu_sdma_instance *
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index f0fffbf2bdd5..d58ab879e125 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -267,7 +267,7 @@ static int amdgpu_ttm_map_buffer(struct ttm_buffer_object
> *bo,
> dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
> dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
> amdgpu_emit_copy_buffer(adev, >ibs[0], src_addr,
> - dst_addr, num_bytes, false);
> + dst_addr, num_bytes, 0);
>
> amdgpu_ring_pad_ib(ring, >ibs[0]);
> WARN_ON(job->ibs[0].length_dw > num_dw); @@ -327,6 +327,8 @@ int
> amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
> struct dma_fence *fence = NULL;
> int r = 0;
>
> + uint32_t copy_flags = 0;
> +
> if (!adev->mman.buffer_funcs_enabled) {
> DRM_ERROR("Trying to move
[pull] amdgpu, amdkfd, radeon drm-next-6.10
Hi Dave, Sima, New stuff for 6.10. The following changes since commit bc55c344b06f7e6f99eb92d393ff0a84c1532514: drm/amdgpu/pm: Don't use OD table on Arcturus (2024-03-20 13:36:29 -0400) are available in the Git repository at: https://gitlab.freedesktop.org/agd5f/linux.git tags/amd-drm-next-6.10-2024-04-13 for you to fetch changes up to ab956ed95b8bc4a65c913d7057075866d5fc3724: drm/amd/display: Add a function for checking tmds mode (2024-04-12 00:36:47 -0400) amd-drm-next-6.10-2024-04-13: amdgpu: - HDCP fixes - ODM fixes - RAS fixes - Devcoredump improvements - Misc code cleanups - Expose VCN activity via sysfs - SMY 13.0.x updates - Enable fast updates on DCN 3.1.4 - Add dclk and vclk reporting on additional devices - Add ACA RAS infrastructure - Implement TLB flush fence - EEPROM handling fixes - SMUIO 14.0.2 support - SMU 14.0.1 Updates - Sync page table freeing with TLB flushes - DML2 refactor - DC debug improvements - SR-IOV fixes - Suspend and Resume fixes - DCN 3.5.x Updates - Z8 fixes - UMSCH fixes - GPU reset fixes - HDP fix for second GFX pipe on GC 10.x - Enable secondary GFX pipe on GC 10.3 - Refactor and clean up BACO/BOCO/BAMACO handling - VCN partitioning fix - DC DWB fixes - VSC SDP fixes - DCN 3.1.6 fix - GC 11.5 fixes - Remove invalid TTM resource start check - DCN 1.0 fixes amdkfd: - MQD handling cleanup - Preemption handling fixes for XCDs - TLB flush fix for GC 9.4.2 - Properly clean up workqueue during module unload - Fix memory leak process create failure - Range check CP bad op exception targets to avoid reporting invalid exceptions to userspace radeon: - Misc code cleanups Alex Deucher (2): drm/amdgpu: always force full reset for SOC21 Documentation: add a page on amdgpu debugging Alex Hung (4): drm/amd/display: Delete duplicated function prototypes drm/amd/display: Correct indentations and spaces drm/amd/display: Skip on writeback when it's not applicable drm/amd/display: Return max resolution supported by DWB Allen Pan (1): drm/amd/display: expand the non standard link rate for testing Alvin Lee (5): drm/amd/display: Backup and restore only on full updates drm/amd/display: Allow idle opts for no flip case on PSR panel drm/amd/display: Remove plane and stream pointers from dc scratch drm/amd/display: Add extra logging for HUBP and OTG drm/amd/display: Add extra DMUB logging to track message timeout Anthony Koo (5): drm/amd/display: Add entry and exit counters drm/amd/display: Update DMUB flags and definitions drm/amd/display: [FW Promotion] Release 0.0.208.0 drm/amd/display: [FW Promotion] Release 0.0.210.0 drm/amd/display: [FW Promotion] Release 0.0.212.0 Aric Cyr (8): drm/amd/display: 3.2.274 drm/amd/display: 3.2.275 drm/amd/display: 3.2.276 drm/amd/display: 3.2.277 drm/amd/display: 3.2.278 drm/amd/display: Fix compiler warnings on high compiler warning levels drm/amd/display: 3.2.279 drm/amd/display: 3.2.280 Arunpravin Paneer Selvam (1): drm/amd/amdgpu: add pipe1 hardware support Asad Kamal (4): drm/amd/pm: Update SMUv13.0.6 PMFW headers drm/amd/pm: Use metric table for pcie speed/width drm/amd/pm: Report uclk/sclk current limits drm/amd/pm: Update uclk/sclk limit report format Aurabindo Pillai (2): drm/amd/display: Add some forward declarations drm/amd/display: Add DML2 folder to include path Bhawanpreet Lakha (2): drm/amd/display: Allow Z8 when stutter threshold is not met drm/amd/display: Allow Z8 when stutter threshold is not met for dcn35 Candice Li (1): drm/amdgpu: Update setting EEPROM table version Chaitanya Dhere (1): drm/amd/display: Add TB_BORROWED_MAX definition Charlene Liu (3): drm/amd/display: fix debug key not working on dml2 drm/amd/display: change aux_init to apu version drm/amd/display: add dwb support to dml2 Chris Park (2): drm/amd/display: Prevent crash when disable stream drm/amd/display: Add a function for checking tmds mode Christian Koenig (1): drm/amdgpu: implement TLB flush fence Christian König (1): drm/amdgpu: remove invalid resource->start check v2 Daniel Miess (2): drm/amd/display: Toggle additional RCO options in DCN35 drm/amd/display: Enable RCO for HDMISTREAMCLK in DCN35 Danijel Slivka (1): drm/amdgpu: use vm_update_mode=0 as default in sriov for gfx10.3 onwards Dillon Varone (9): drm/amd/display: add stream clock source to DP DTO params drm/amd/display: Program pixclk according to dcn revision drm/amd/display: Power on VPG memory unconditionally if off drm/amd/display: Expand DML2 callbacks drm/amd/display: Refactor DML2 interfaces drm/amd/display: Modify DHCUB waterwark
Re: [PATCH v2 2/2] drm/amdgpu: Add support of gfx10 register dump
On Sat, Apr 13, 2024 at 12:35 AM Khatri, Sunil wrote:
>
> [AMD Official Use Only - General]
>
> -Original Message-
> From: Alex Deucher
> Sent: Saturday, April 13, 2024 1:56 AM
> To: Khatri, Sunil
> Cc: Khatri, Sunil ; Deucher, Alexander
> ; Koenig, Christian ;
> amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH v2 2/2] drm/amdgpu: Add support of gfx10 register dump
>
> On Fri, Apr 12, 2024 at 1:31 PM Khatri, Sunil wrote:
> >
> >
> > On 4/12/2024 10:42 PM, Alex Deucher wrote:
> >
> > On Fri, Apr 12, 2024 at 1:05 PM Khatri, Sunil wrote:
> >
> > On 4/12/2024 8:50 PM, Alex Deucher wrote:
> >
> > On Fri, Apr 12, 2024 at 10:00 AM Sunil Khatri wrote:
> >
> > Adding initial set of registers for ipdump during devcoredump starting
> > with gfx10 gc registers.
> >
> > ip dump is triggered when gpu reset happens via devcoredump and the
> > memory is allocated by each ip and is freed once the dump is complete
> > by devcoredump.
> >
> > Signed-off-by: Sunil Khatri
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu.h | 16 +++
> > .../gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c | 22 +++
> >
> > I would split this into two patches, one to add the core
> > infrastructure in devcoredump and one to add gfx10 support. The core
> > support could be squashed into patch 1 as well.
> >
> > Sure
> >
> > drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c| 127 +-
> > .../include/asic_reg/gc/gc_10_1_0_offset.h| 12 ++
> > 4 files changed, 176 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > index 65c17c59c152..e173ad86a241 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > @@ -139,6 +139,18 @@ enum amdgpu_ss {
> > AMDGPU_SS_DRV_UNLOAD
> > };
> >
> > +struct hwip_reg_entry {
> > + u32 hwip;
> > + u32 inst;
> > + u32 seg;
> > + u32 reg_offset;
> > +};
> > +
> > +struct reg_pair {
> > + u32 offset;
> > + u32 value;
> > +};
> > +
> > struct amdgpu_watchdog_timer {
> > bool timeout_fatal_disable;
> > uint32_t period; /* maxCycles = (1 << period), the number of
> > cycles before a timeout */ @@ -1152,6 +1164,10 @@ struct amdgpu_device {
> > booldebug_largebar;
> > booldebug_disable_soft_recovery;
> > booldebug_use_vram_fw_buf;
> > +
> > + /* IP register dump */
> > + struct reg_pair *ip_dump;
> > + uint32_tnum_regs;
> > };
> >
> > static inline uint32_t amdgpu_ip_version(const struct amdgpu_device
> > *adev, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c
> > index 1129e5e5fb42..2079f67c9fac 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c
> > @@ -261,6 +261,18 @@ amdgpu_devcoredump_read(char *buffer, loff_t offset,
> > size_t count,
> > drm_printf(, "Faulty page starting at address: 0x%016llx\n",
> > fault_info->addr);
> > drm_printf(, "Protection fault status register: 0x%x\n\n",
> > fault_info->status);
> >
> > + /* Add IP dump for each ip */
> > + if (coredump->adev->ip_dump != NULL) {
> > + struct reg_pair *pair;
> > +
> > + pair = (struct reg_pair *)coredump->adev->ip_dump;
> > + drm_printf(, "IP register dump\n");
> > + drm_printf(, "Offset \t Value\n");
> > + for (int i = 0; i < coredump->adev->num_regs; i++)
> > + drm_printf(, "0x%04x \t 0x%08x\n",
> > pair[i].offset, pair[i].value);
> > + drm_printf(, "\n");
> > + }
> > +
> > /* Add ring buffer information */
> > drm_printf(, "Ring buffer information\n");
> > for (int i = 0; i < coredump->adev->num_rings; i++) { @@
> > -299,6 +311,11 @@ amdgpu_devcoredump_read(char *buffer, loff_t offset,
> > size_t count,
> >
> > static void amdgpu_devcoredump_free(void *data)
> > {
> > + struct amdgpu_coredump_info *temp = data;
> > +
> > + kfree(temp->adev->ip_dump);
> > + temp->adev->ip_dump = NULL;
> > + temp->adev->num_regs = 0;
> > kfree(data);
> > }
> >
> > @@ -337,6 +354,11 @@ void amdgpu_coredump(struct amdgpu_device *adev,
> > bool vram_lost,
> >
> > coredump->adev = adev;
> >
> > + /* Trigger ip dump here to capture the value of registers */
> > + for (int i = 0; i < adev->num_ip_blocks; i++)
> > + if (adev->ip_blocks[i].version->funcs->dump_ip_state)
> > +
> > + adev->ip_blocks[i].version->funcs->dump_ip_state((void *)adev);
> > +
> >
> > This seems too complicated. I think it would be easier to
> >
> > This is how all other per IP functions are called.
[PATCH] drm/amdkfd: fix NULL pointer dereference
From: Vitaly Prosyak
[ +0.006038] BUG: kernel NULL pointer dereference, address: 0028
[ +0.006969] #PF: supervisor read access in kernel mode
[ +0.005139] #PF: error_code(0x) - not-present page
[ +0.005139] PGD 0 P4D 0
[ +0.002530] Oops: [#1] PREEMPT SMP NOPTI
[ +0.004356] CPU: 11 PID: 12625 Comm: kworker/11:0 Tainted: GW
6.7.0+ #2
[ +0.008097] Hardware name: ASUS System Product Name/Pro WS WRX80E-SAGE SE
WIFI II, BIOS 1302 12/08/2023
[ +0.009398] Workqueue: events evict_process_worker [amdgpu]
[ +0.005750] RIP: 0010:evict_process_worker+0x2f/0x460 [amdgpu]
[ +0.005991] Code: 55 48 89 e5 41 57 41 56 4c 8d b7 a8 fc ff ff 41 55 41 54 53
48 89 fb 48 83 ec 10 0f 1f 44 00 00 48 8b 43 f8 8b 93 b0 00 00 00 <48> 3b 50 28
0f 85 50 03 00 00 48 8d 7b 58 e8 ee be cb bf 48 8b 05
[ +0.018791] RSP: 0018:c90009a2be10 EFLAGS: 00010282
[ +0.005226] RAX: RBX: 888197ffc358 RCX:
[ +0.007140] RDX: 0a1b RSI: RDI: 888197ffc358
[ +0.007139] RBP: c90009a2be48 R08: R09:
[ +0.007139] R10: R11: R12: 888197ffc358
[ +0.007139] R13: 888100153a00 R14: 888197ffc000 R15: 888100153a05
[ +0.007137] FS: () GS:889facac()
knlGS:
[ +0.008094] CS: 0010 DS: ES: CR0: 80050033
[ +0.005747] CR2: 0028 CR3: 00010d1fc001 CR4: 00770ef0
[ +0.007138] PKRU: 5554
[ +0.002702] Call Trace:
[ +0.002443]
[ +0.002096] ? show_regs+0x72/0x90
[ +0.003402] ? __die+0x25/0x80
[ +0.003052] ? page_fault_oops+0x154/0x4c0
[ +0.004099] ? do_user_addr_fault+0x30e/0x6e0
[ +0.004357] ? psi_group_change+0x237/0x520
[ +0.004185] ? exc_page_fault+0x84/0x1b0
[ +0.003926] ? asm_exc_page_fault+0x27/0x30
[ +0.004187] ? evict_process_worker+0x2f/0x460 [amdgpu]
[ +0.005377] process_one_work+0x17b/0x360
[ +0.004011] ? __pfx_worker_thread+0x10/0x10
[ +0.004269] worker_thread+0x307/0x430
[ +0.003748] ? __pfx_worker_thread+0x10/0x10
[ +0.004268] kthread+0xf7/0x130
[ +0.003142] ? __pfx_kthread+0x10/0x10
[ +0.003749] ret_from_fork+0x46/0x70
[ +0.003573] ? __pfx_kthread+0x10/0x10
[ +0.003747] ret_from_fork_asm+0x1b/0x30
[ +0.003924]
When we run stressful tests, the eviction fence could be zero and not match
to last_eviction_seqno.
Avoid calling dma_fence_signal and dma_fence_put with zero fences to rely
on checking parameters in DMA API.
Cc: Alex Deucher
Cc: Christian Koenig
Cc: Xiaogang Chen
Cc: Felix Kuehling
Signed-off-by: Vitaly Prosyak
---
drivers/gpu/drm/amd/amdkfd/kfd_process.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
index eb380296017d..a15fae1c398a 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
@@ -2118,7 +2118,7 @@ static void evict_process_worker(struct work_struct *work)
*/
p = container_of(dwork, struct kfd_process, eviction_work);
trace_kfd_evict_process_worker_start(p);
- WARN_ONCE(p->last_eviction_seqno != p->ef->seqno,
+ WARN_ONCE(p->ef && p->last_eviction_seqno != p->ef->seqno,
"Eviction fence mismatch\n");
/* Narrow window of overlap between restore and evict work
@@ -2134,9 +2134,11 @@ static void evict_process_worker(struct work_struct
*work)
pr_debug("Started evicting pasid 0x%x\n", p->pasid);
ret = kfd_process_evict_queues(p, false,
KFD_QUEUE_EVICTION_TRIGGER_TTM);
if (!ret) {
- dma_fence_signal(p->ef);
- dma_fence_put(p->ef);
- p->ef = NULL;
+ if (p->ef) {
+ dma_fence_signal(p->ef);
+ dma_fence_put(p->ef);
+ p->ef = NULL;
+ }
if (!kfd_process_unmap_doorbells_if_idle(p))
kfd_process_schedule_restore(p);
--
2.25.1
Re: [PATCH] drm/amd: Only allow one entity to control ABM
Hi> > ABM will reduce the backlight and compensate by adjusting brightness and > contrast of the image. It has 5 levels: 0, 1, 2, 3, 4. 0 means off. 4 means > maximum backlight reduction. IMO, 1 and 2 look okay. 3 and 4 can be quite > impactful, both to power and visual fidelity. I tried this with 6.9 and it looks weird with an OLED panel used with dark UI settings. The dark is no longer dark, everything is brighter. I turned this feature off with amdgpu.abmlevel=0. Best regards, Gergo
Re: [PATCH 0/2] drm/amdgpu/display: Make multi-plane configurations more flexible
On Fri, 12 Apr 2024 10:28:52 -0400 Leo Li wrote: > On 2024-04-12 04:03, Pekka Paalanen wrote: > > On Thu, 11 Apr 2024 16:33:57 -0400 > > Leo Li wrote: > > ... > >> That begs the question of what can be nailed down and what can left to > >> independent implementation. I guess things like which plane should be > >> enabled > >> first (PRIMARY), and how zpos should be interpreted (overlay, underlay, > >> mixed) > >> can be defined. How to handle atomic test failures could be as well. > > > > What room is there for the interpretation of zpos values? > > > > I thought they are unambiguous already: only the relative numerical > > order matters, and that uniquely defines the KMS plane ordering. > > The zpos value of the PRIMARY plane relative to OVERLAYS, for example, as a > way > for vendors to communicate overlay, underlay, or mixed-arrangement support. I > don't think allowing OVERLAYs to be placed under the PRIMARY is currently > documented as a way to support underlay. I always thought it's obvious that the zpos numbers dictate the plane order without any other rules. After all, we have the universal planes concept, where the plane type is only informational to aid heuristics rather than defining anything. Only if the zpos property does not exist, the plane types would come into play. Of course, if there actually exists userspace that fails if zpos allows an overlay type plane to be placed below primary, or fails if primary zpos is not zero, then DRM needs a new client cap. > libliftoff for example, assumes that the PRIMARY has the lowest zpos. So > underlay arrangements will use an OVERLAY for the scanout plane, and the > PRIMARY > for the underlay view. That's totally ok. It works, right? Plane type does not matter if the KMS driver accepts the configuration. What is a "scanout plane"? Aren't all KMS planes by definition scanout planes? IOW, if the KMS client understands zpos and can do a proper KMS configuration search, and all planes have zpos property, then there is no need to look at the plane type at all. That is the goal of the universal planes feature. Thanks, pq pgphqMhxrsF6k.pgp Description: OpenPGP digital signature
Re: [PATCH 0/2] drm/amdgpu/display: Make multi-plane configurations more flexible
On Thu, 11 Apr 2024 16:33:57 -0400 Leo Li wrote: > On 2024-04-04 10:22, Marius Vlad wrote: > > On Thu, Apr 04, 2024 at 09:59:03AM -0400, Harry Wentland wrote: > >> > > Hi all, > >> > >> On 2024-04-04 06:24, Pekka Paalanen wrote: > >>> On Wed, 3 Apr 2024 17:32:46 -0400 > >>> Leo Li wrote: > >>> > On 2024-03-28 10:33, Pekka Paalanen wrote: > > On Fri, 15 Mar 2024 13:09:56 -0400 > > wrote: > > > >> From: Leo Li > >> > >> These patches aim to make the amdgpgu KMS driver play nicer with > >> compositors > >> when building multi-plane scanout configurations. They do so by: > >> > >> 1. Making cursor behavior more sensible. > >> 2. Allowing placement of DRM OVERLAY planes underneath the PRIMARY > >> plane for > >> 'underlay' configurations (perhaps more of a RFC, see below). > >> > >> Please see the commit messages for details. > >> > >> > >> For #2, the simplest way to accomplish this was to increase the value > >> of the > >> immutable zpos property for the PRIMARY plane. This allowed OVERLAY > >> planes with > >> a mutable zpos range of (0-254) to be positioned underneath the > >> PRIMARY for an > >> underlay scanout configuration. > >> > >> Technically speaking, DCN hardware does not have a concept of primary > >> or overlay > >> planes - there are simply 4 general purpose hardware pipes that can be > >> maped in > >> any configuration. So the immutable zpos restriction on the PRIMARY > >> plane is > >> kind of arbitrary; it can have a mutable range of (0-254) just like the > >> OVERLAYs. The distinction between PRIMARY and OVERLAY planes is also > >> somewhat > >> arbitrary. We can interpret PRIMARY as the first plane that should be > >> enabled on > >> a CRTC, but beyond that, it doesn't mean much for amdgpu. > >> > >> Therefore, I'm curious about how compositors devs understand KMS > >> planes and > >> their zpos properties, and how we would like to use them. It isn't > >> clear to me > >> how compositors wish to interpret and use the DRM zpos property, or > >> differentiate between OVERLAY and PRIMARY planes, when it comes to > >> setting up > >> multi-plane scanout. > > > > You already quoted me on the Weston link, so I don't think I have > > anything to add. Sounds fine to me, and we don't have a standard plane > > arrangement algorithm that the kernel could optimize zpos ranges > > against, yet. > > > >> Ultimately, what I'd like to answer is "What can we do on the KMS > >> driver and DRM > >> plane API side, that can make building multi-plane scanout > >> configurations easier > >> for compositors?" I'm hoping we can converge on something, whether > >> that be > >> updating the existing documentation to better define the usage, or > >> update the > >> API to provide support for something that is lacking. > > > > I think there probably should be a standardised plane arrangement > > algorithm in userspace, because the search space suffers from > > permutational explosion. Either there needs to be very few planes (max > > 4 or 5 at-all-possible per CRTC, including shareable ones) for an > > exhaustive search to be feasible, or all planes should be more or less > > equal in capabilities and userspace employs some simplified or > > heuristic search. > > > > If the search algorithm is fixed, then drivers could optimize zpos > > ranges to have the algorithm find a solution faster. > > > > My worry is that userspace already has heuristic search algorithms that > > may start failing if drivers later change their zpos ranges to be more > > optimal for another algorithm. > > > > OTOH, as long as exhaustive search is feasible, then it does not matter > > how DRM drivers set up the zpos ranges. > > > > In any case, the zpos ranges should try to allow all possible plane > > arrangements while minimizing the number of arrangements that won't > > work. The absolute values of zpos are pretty much irrelevant, so I > > think setting one plane to have an immutable zpos is a good idea, even > > if it's not necessary by the driver. That is one less moving part, and > > only the relative ordering between the planes matters. > > > > > > Thanks, > > pq > > Right, thanks for your thoughts! I agree that there should be a common > plane > arrangement algorithm. I think libliftoff is the most obvious candidate > here. It > only handles overlay arrangements currently, but mixed-mode arrangements > is > something I've been trying to look at. > > Taking the driver's reported zpos into account could narrow down the > search > space for mixed arrangements.
