Re: [PATCH v2 1/6] drm/ci: uprev mesa version
Hi Dmitry,
On 23/05/24 15:29, Dmitry Baryshkov wrote:
On Thu, 23 May 2024 at 09:07, Vignesh Raman wrote:
Hi Dmitry,
On 20/05/24 16:13, Dmitry Baryshkov wrote:
On Fri, May 17, 2024 at 02:54:57PM +0530, Vignesh Raman wrote:
zlib.net is not allowing tarball download anymore and results
in below error in kernel+rootfs_arm32 container build,
urllib.error.HTTPError: HTTP Error 403: Forbidden
urllib.error.HTTPError: HTTP Error 415: Unsupported Media Type
Uprev mesa to latest version which includes a fix for this issue.
https://gitlab.freedesktop.org/mesa/mesa/-/commit/908f444e
Use id_tokens for JWT authentication. Since s3 bucket is migrated to
mesa-rootfs, update the variables accordingly. Also copy helper scripts
to install, so that the ci jobs can use these scripts for logging.
Signed-off-by: Vignesh Raman
---
v2:
- Uprev to recent version and use id_tokens for JWT authentication
---
drivers/gpu/drm/ci/build-igt.sh | 2 +-
drivers/gpu/drm/ci/build.sh | 6 +++--
drivers/gpu/drm/ci/container.yml | 12 +++--
drivers/gpu/drm/ci/gitlab-ci.yml | 44 +--
drivers/gpu/drm/ci/image-tags.yml | 2 +-
drivers/gpu/drm/ci/lava-submit.sh | 4 +--
drivers/gpu/drm/ci/test.yml | 2 ++
7 files changed, 44 insertions(+), 28 deletions(-)
[skipped]
diff --git a/drivers/gpu/drm/ci/test.yml b/drivers/gpu/drm/ci/test.yml
index 8bc63912fddb..612c9ede3507 100644
--- a/drivers/gpu/drm/ci/test.yml
+++ b/drivers/gpu/drm/ci/test.yml
@@ -150,6 +150,8 @@ msm:sdm845:
BM_KERNEL: https://${PIPELINE_ARTIFACTS_BASE}/arm64/cheza-kernel
GPU_VERSION: sdm845
RUNNER_TAG: google-freedreno-cheza
+DEVICE_TYPE: sdm845-cheza-r3
+FARM: google
I see that this is the only user of the FARM: tag. Is it correct?
No, we need to add FARM variable for other jobs as well.
Why? Even if we have to, we don't have them now and the change doesn't
seem to be related to the uprev'ing of mesa. So this probably should
go to a separate commit.
I will move them to separate commit.
Regards,
Vignesh
Also we miss DEVICE_TYPE for several other boards. Should we be adding
them?
Yes, device type needs to be added for msm:apq8016, msm:apq8096, virtio_gpu.
I will add this. Thanks.
I'd guess, separate commit too.
Regards,
Vignesh
script:
- ./install/bare-metal/cros-servo.sh
--
2.40.1
RE: [PATCH] drm/amdkfd: simplify APU VRAM handling
[Public]
Hi Alex,
3 places are missed.
--- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
@@ -1023,7 +1023,7 @@ int kgd2kfd_init_zone_device(struct amdgpu_device *adev)
if (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(9, 0, 1))
return -EINVAL;
- if (adev->gmc.is_app_apu)
+ if (adev->gmc.is_app_apu || adev->flags & AMD_IS_APU)
return 0;
pgmap = &kfddev->pgmap;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
index 91175b1bd9ac..4885d1b2cc29 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
@@ -2631,7 +2631,8 @@ svm_range_best_restore_location(struct svm_range *prange,
return -1;
}
- if (node->adev->gmc.is_app_apu)
+ if (node->adev->gmc.is_app_apu ||
+ node->adev->flags & AMD_IS_APU)
return 0;
if (prange->preferred_loc == gpuid ||
@@ -3349,7 +3350,8 @@ svm_range_best_prefetch_location(struct svm_range *prange)
goto out;
}
- if (bo_node->adev->gmc.is_app_apu) {
+ if (bo_node->adev->gmc.is_app_apu ||
+ bo_node->adev->flags & AMD_IS_APU) {
best_loc = 0;
goto out;
}
Regards,
Lang
>-Original Message-
>From: amd-gfx On Behalf Of Alex
>Deucher
>Sent: Friday, May 24, 2024 2:39 AM
>To: amd-gfx@lists.freedesktop.org
>Cc: Deucher, Alexander
>Subject: [PATCH] drm/amdkfd: simplify APU VRAM handling
>
>With commit 89773b85599a
>("drm/amdkfd: Let VRAM allocations go to GTT domain on small APUs") big
>and small APU "VRAM" handling in KFD was unified. Since AMD_IS_APU is
>set for both big and small APUs, we can simplify the checks in the code.
>
>Signed-off-by: Alex Deucher
>---
> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 16 ---
>-
> drivers/gpu/drm/amd/amdkfd/kfd_svm.h | 1 -
> 2 files changed, 8 insertions(+), 9 deletions(-)
>
>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
>b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
>index 336eb51c4839..3af00b57cd8a 100644
>--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
>+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
>@@ -196,7 +196,7 @@ int amdgpu_amdkfd_reserve_mem_limit(struct
>amdgpu_device *adev,
> return -EINVAL;
>
> vram_size = KFD_XCP_MEMORY_SIZE(adev, xcp_id);
>- if (adev->gmc.is_app_apu || adev->flags & AMD_IS_APU) {
>+ if (adev->flags & AMD_IS_APU) {
> system_mem_needed = size;
> ttm_mem_needed = size;
> }
>@@ -233,7 +233,7 @@ int amdgpu_amdkfd_reserve_mem_limit(struct
>amdgpu_device *adev,
> if (adev && xcp_id >= 0) {
> adev->kfd.vram_used[xcp_id] += vram_needed;
> adev->kfd.vram_used_aligned[xcp_id] +=
>- (adev->gmc.is_app_apu || adev->flags &
>AMD_IS_APU) ?
>+ (adev->flags & AMD_IS_APU) ?
> vram_needed :
> ALIGN(vram_needed,
>VRAM_AVAILABLITY_ALIGN);
> }
>@@ -261,7 +261,7 @@ void amdgpu_amdkfd_unreserve_mem_limit(struct
>amdgpu_device *adev,
>
> if (adev) {
> adev->kfd.vram_used[xcp_id] -= size;
>- if (adev->gmc.is_app_apu || adev->flags &
>AMD_IS_APU) {
>+ if (adev->flags & AMD_IS_APU) {
> adev->kfd.vram_used_aligned[xcp_id] -= size;
> kfd_mem_limit.system_mem_used -= size;
> kfd_mem_limit.ttm_mem_used -= size; @@ -
>894,7 +894,7 @@ static int kfd_mem_attach(struct amdgpu_device *adev,
>struct kgd_mem *mem,
>* if peer device has large BAR. In contrast, access over xGMI is
>* allowed for both small and large BAR configurations of peer device
>*/
>- if ((adev != bo_adev && !(adev->gmc.is_app_apu || adev->flags &
>AMD_IS_APU)) &&
>+ if ((adev != bo_adev && !(adev->flags & AMD_IS_APU)) &&
> ((mem->domain == AMDGPU_GEM_DOMAIN_VRAM) ||
>(mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) ||
>(mem->alloc_flags &
>KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP))) { @@ -1682,7 +1682,7 @@
>size_t amdgpu_amdkfd_get_available_memory(struct amdgpu_device *adev,
> - atomic64_read(&adev->vram_pin_size)
> - reserved_for_pt;
>
>- if (adev->gmc.is_app_apu || adev->flags & AMD_IS_APU) {
>+ if (adev->flags & AMD_IS_APU) {
> system_mem_available = no_system_mem_limit ?
>
> kfd_mem_limit.max_system_mem_limit :
>
> kfd_mem_limit.max_system_mem_limit - @@ -1730,7 +1730,7 @@
>int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
> if (flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
> domain = alloc_domain
RE: [PATCH] drm/amdgpu: drop MES 10.1 support v3
[AMD Official Use Only - AMD Internal Distribution Only]
I had one more comment. With that fixed this patch is Reviewed-by: Harish
Kasiviswanathan
static gfx_v10_0_ring_invalidate_tlbs() function can be removed since it is no
longer used.
Best Regards,
Harish
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: Thursday, May 23, 2024 3:48 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH] drm/amdgpu: drop MES 10.1 support v3
It was an enablement vehicle for MES 11 and was never
productized. Remove it.
v2: drop additional checks in the GFX10 code.
v3: drop mes_api_def.h
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/Makefile |1 -
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 20 -
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c| 281 +---
drivers/gpu/drm/amd/amdgpu/mes_v10_1.c| 1190 -
drivers/gpu/drm/amd/amdgpu/mes_v10_1.h| 29 -
drivers/gpu/drm/amd/amdgpu/nv.c |1 -
.../drm/amd/amdkfd/kfd_device_queue_manager.c |2 +-
drivers/gpu/drm/amd/include/mes_api_def.h | 570
8 files changed, 72 insertions(+), 2022 deletions(-)
delete mode 100644 drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
delete mode 100644 drivers/gpu/drm/amd/amdgpu/mes_v10_1.h
delete mode 100644 drivers/gpu/drm/amd/include/mes_api_def.h
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
b/drivers/gpu/drm/amd/amdgpu/Makefile
index 6e3d7f51616f..eddbb69a179f 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -187,7 +187,6 @@ amdgpu-y += \
# add MES block
amdgpu-y += \
amdgpu_mes.o \
- mes_v10_1.o \
mes_v11_0.o \
mes_v12_0.o
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index c5f23e1a1362..510916e28d37 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -94,7 +94,6 @@
#include "vcn_v4_0_5.h"
#include "jpeg_v4_0_5.h"
#include "amdgpu_vkms.h"
-#include "mes_v10_1.h"
#include "mes_v11_0.h"
#include "mes_v12_0.h"
#include "smuio_v11_0.h"
@@ -2319,25 +2318,6 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct
amdgpu_device *adev)
static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev)
{
switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
- case IP_VERSION(10, 1, 10):
- case IP_VERSION(10, 1, 1):
- case IP_VERSION(10, 1, 2):
- case IP_VERSION(10, 1, 3):
- case IP_VERSION(10, 1, 4):
- case IP_VERSION(10, 3, 0):
- case IP_VERSION(10, 3, 1):
- case IP_VERSION(10, 3, 2):
- case IP_VERSION(10, 3, 3):
- case IP_VERSION(10, 3, 4):
- case IP_VERSION(10, 3, 5):
- case IP_VERSION(10, 3, 6):
- if (amdgpu_mes) {
- amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
- adev->enable_mes = true;
- if (amdgpu_mes_kiq)
- adev->enable_mes_kiq = true;
- }
- break;
case IP_VERSION(11, 0, 0):
case IP_VERSION(11, 0, 1):
case IP_VERSION(11, 0, 2):
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 8ceb26a5575a..2a808029a47c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -3734,14 +3734,8 @@ static void gfx10_kiq_unmap_queues(struct amdgpu_ring
*kiq_ring,
enum amdgpu_unmap_queues_action action,
u64 gpu_addr, u64 seq)
{
- struct amdgpu_device *adev = kiq_ring->adev;
uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
- if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) {
- amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr,
seq);
- return;
- }
-
amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
PACKET3_UNMAP_QUEUES_ACTION(action) |
@@ -3999,33 +3993,18 @@ static int gfx_v10_0_ring_test_ib(struct amdgpu_ring
*ring, long timeout)
memset(&ib, 0, sizeof(ib));
- if (ring->is_mes_queue) {
- uint32_t padding, offset;
-
- offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS);
- padding = amdgpu_mes_ctx_get_offs(ring,
- AMDGPU_MES_CTX_PADDING_OFFS);
-
- ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
- ib.ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
-
- gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, padding);
- cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, padding);
- *cpu_p
Re: [PATCH 3/3] drm/amdkfd: gfx12 context save/restore trap handler fixes
On 23/05/2024 20:31, Jay Cornwall wrote: On 5/23/2024 13:37, Lancelot SIX wrote: @@ -622,8 +638,15 @@ L_SAVE_HWREG: #if ASIC_FAMILY >= CHIP_GFX12 // Ensure no further changes to barrier or LDS state. + // STATE_PRIV.BARRIER_COMPLETE may change up to this point. s_barrier_signal -2 s_barrier_wait -2 + + // Re-read final state of BARRIER_COMPLETE field for save. + s_getreg_b32 s_save_tmp, hwreg(S_STATUS_HWREG) + s_and_b32 s_save_tmp, s_save_tmp, SQ_WAVE_STATE_PRIV_BARRIER_COMPLETE_MASK + s_andn2_b32 s_save_status, s_save_status, SQ_WAVE_STATE_PRIV_BARRIER_COMPLETE_MASK Even if BARRIER_COMPLETE can be asserted while we are in the trap hadler, I do not think it can be cleared. That being said, it might be easier to just replace the bit, making it clearer. Yes, I chose to structure it this way to make the intent clearer. We don't gain much from dropping the s_andn2. Most of the time spent in the save handler is stalled on memory instructions. @@ -1351,7 +1369,17 @@ L_SKIP_BARRIER_RESTORE: s_setreg_b32 hwreg(HW_REG_SHADER_XNACK_MASK), s_restore_xnack_mask #endif +#if ASIC_FAMILY < CHIP_GFX12 s_setreg_b32 hwreg(S_TRAPSTS_HWREG), s_restore_trapsts Wouldn't other gfx1x architectures have a similar issue when writing TRAPSTS here? That is if TRAPSTS.SAVECTX is set while we are restoring, wouldn't we loose it? And for gfx11, there is TRAPSTS.HOST_TRAP that could have the same issue to some degree (not sure if we would loose the host trap completly, or re-enter with trap ID + HT bit set in ttmp1). Prior to gfx12 context save and host trap exceptions are not delivered to a wave until STATUS.PRIV=0, i.e. it leaves the trap handler. The changes needed for gfx12 are due to a design change in this area. Exceptions are now flagged immediately and cause re-entry to the trap if any are non-zero. Thanks for the clarifications. The patch looks good to me. Reviewed-by: Lancelot Six Best, Lancelot.
Re: [PATCH 4/4] drm: enable -Wformat-truncation across the subsystem
Hi Jani,
On Thu, May 23, 2024 at 06:51:09PM +0300, Jani Nikula wrote:
> With the -Wformat-truncation warnings fixed, finish the job started in
> commit a61ddb4393ad ("drm: enable (most) W=1 warnings by default across
> the subsystem"), and enable that warning too.
>
> Signed-off-by: Jani Nikula
When it is enabled for all of drm then the explicit assignments here
could be dropped I think:
drivers/gpu/drm/i915/Makefile:subdir-ccflags-y += $(call cc-option,
-Wformat-truncation)
drivers/gpu/drm/xe/Makefile:subdir-ccflags-y += $(call cc-option,
-Wformat-truncation)
Just a drive-by comment, I know this patch was mostly for the bots.
Sam
>
> ---
>
> Gut feeling says there are more issues, and my configs just don't catch
> them all, but let's see what the build bots have to say. ;)
> ---
> drivers/gpu/drm/Makefile | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
> index 68cc9258ffc4..644613dbedda 100644
> --- a/drivers/gpu/drm/Makefile
> +++ b/drivers/gpu/drm/Makefile
> @@ -16,8 +16,7 @@ subdir-ccflags-y += $(call cc-option,
> -Wunused-but-set-variable)
> subdir-ccflags-y += $(call cc-option, -Wunused-const-variable)
> subdir-ccflags-y += $(call cc-option, -Wpacked-not-aligned)
> subdir-ccflags-y += $(call cc-option, -Wformat-overflow)
> -# FIXME: fix -Wformat-truncation warnings and uncomment
> -#subdir-ccflags-y += $(call cc-option, -Wformat-truncation)
> +subdir-ccflags-y += $(call cc-option, -Wformat-truncation)
> subdir-ccflags-y += $(call cc-option, -Wstringop-truncation)
> # The following turn off the warnings enabled by -Wextra
> ifeq ($(findstring 2, $(KBUILD_EXTRA_WARN)),)
> --
> 2.39.2
[PATCH] drm/amdgpu: drop MES 10.1 support v3
It was an enablement vehicle for MES 11 and was never
productized. Remove it.
v2: drop additional checks in the GFX10 code.
v3: drop mes_api_def.h
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/Makefile |1 -
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 20 -
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c| 281 +---
drivers/gpu/drm/amd/amdgpu/mes_v10_1.c| 1190 -
drivers/gpu/drm/amd/amdgpu/mes_v10_1.h| 29 -
drivers/gpu/drm/amd/amdgpu/nv.c |1 -
.../drm/amd/amdkfd/kfd_device_queue_manager.c |2 +-
drivers/gpu/drm/amd/include/mes_api_def.h | 570
8 files changed, 72 insertions(+), 2022 deletions(-)
delete mode 100644 drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
delete mode 100644 drivers/gpu/drm/amd/amdgpu/mes_v10_1.h
delete mode 100644 drivers/gpu/drm/amd/include/mes_api_def.h
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
b/drivers/gpu/drm/amd/amdgpu/Makefile
index 6e3d7f51616f..eddbb69a179f 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -187,7 +187,6 @@ amdgpu-y += \
# add MES block
amdgpu-y += \
amdgpu_mes.o \
- mes_v10_1.o \
mes_v11_0.o \
mes_v12_0.o
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index c5f23e1a1362..510916e28d37 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -94,7 +94,6 @@
#include "vcn_v4_0_5.h"
#include "jpeg_v4_0_5.h"
#include "amdgpu_vkms.h"
-#include "mes_v10_1.h"
#include "mes_v11_0.h"
#include "mes_v12_0.h"
#include "smuio_v11_0.h"
@@ -2319,25 +2318,6 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct
amdgpu_device *adev)
static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev)
{
switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
- case IP_VERSION(10, 1, 10):
- case IP_VERSION(10, 1, 1):
- case IP_VERSION(10, 1, 2):
- case IP_VERSION(10, 1, 3):
- case IP_VERSION(10, 1, 4):
- case IP_VERSION(10, 3, 0):
- case IP_VERSION(10, 3, 1):
- case IP_VERSION(10, 3, 2):
- case IP_VERSION(10, 3, 3):
- case IP_VERSION(10, 3, 4):
- case IP_VERSION(10, 3, 5):
- case IP_VERSION(10, 3, 6):
- if (amdgpu_mes) {
- amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
- adev->enable_mes = true;
- if (amdgpu_mes_kiq)
- adev->enable_mes_kiq = true;
- }
- break;
case IP_VERSION(11, 0, 0):
case IP_VERSION(11, 0, 1):
case IP_VERSION(11, 0, 2):
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 8ceb26a5575a..2a808029a47c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -3734,14 +3734,8 @@ static void gfx10_kiq_unmap_queues(struct amdgpu_ring
*kiq_ring,
enum amdgpu_unmap_queues_action action,
u64 gpu_addr, u64 seq)
{
- struct amdgpu_device *adev = kiq_ring->adev;
uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
- if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) {
- amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr,
seq);
- return;
- }
-
amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
PACKET3_UNMAP_QUEUES_ACTION(action) |
@@ -3999,33 +3993,18 @@ static int gfx_v10_0_ring_test_ib(struct amdgpu_ring
*ring, long timeout)
memset(&ib, 0, sizeof(ib));
- if (ring->is_mes_queue) {
- uint32_t padding, offset;
-
- offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS);
- padding = amdgpu_mes_ctx_get_offs(ring,
- AMDGPU_MES_CTX_PADDING_OFFS);
-
- ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
- ib.ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
-
- gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, padding);
- cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, padding);
- *cpu_ptr = cpu_to_le32(0xCAFEDEAD);
- } else {
- r = amdgpu_device_wb_get(adev, &index);
- if (r)
- return r;
+ r = amdgpu_device_wb_get(adev, &index);
+ if (r)
+ return r;
- gpu_addr = adev->wb.gpu_addr + (index * 4);
- adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
- cpu_ptr = &adev->wb.wb[index];
+ gpu_addr = adev->wb.gpu_addr + (index * 4);
+ ad
Re: [PATCH] drm/amdgpu: drop MES 10.1 support v2
On Thu, May 23, 2024 at 3:38 PM Kasiviswanathan, Harish
wrote:
>
> [AMD Official Use Only - AMD Internal Distribution Only]
>
> File mes_api_def.h can also be removed. This is defined for gfx10.
> One minor comment inline.
>
>
> -Original Message-
> From: amd-gfx On Behalf Of Alex
> Deucher
> Sent: Thursday, May 23, 2024 2:46 PM
> To: Deucher, Alexander
> Cc: amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH] drm/amdgpu: drop MES 10.1 support v2
>
> Ping?
>
> On Fri, May 10, 2024 at 7:37 PM Alex Deucher
> wrote:
> >
> > It was an enablement vehicle for MES 11 and was never
> > productized. Remove it.
done.
> >
> > v2: drop additional checks in the GFX10 code.
> >
> > Signed-off-by: Alex Deucher
> > ---
> > drivers/gpu/drm/amd/amdgpu/Makefile |1 -
> > drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 20 -
> > drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c| 281 +---
> > drivers/gpu/drm/amd/amdgpu/mes_v10_1.c| 1190 -
> > drivers/gpu/drm/amd/amdgpu/mes_v10_1.h| 29 -
> > drivers/gpu/drm/amd/amdgpu/nv.c |1 -
> > 6 files changed, 71 insertions(+), 1451 deletions(-)
> > delete mode 100644 drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
> > delete mode 100644 drivers/gpu/drm/amd/amdgpu/mes_v10_1.h
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
> > b/drivers/gpu/drm/amd/amdgpu/Makefile
> > index de7b76327f5ba..6e1237a97a91e 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/Makefile
> > +++ b/drivers/gpu/drm/amd/amdgpu/Makefile
> > @@ -187,7 +187,6 @@ amdgpu-y += \
> > # add MES block
> > amdgpu-y += \
> > amdgpu_mes.o \
> > - mes_v10_1.o \
> > mes_v11_0.o \
> > mes_v12_0.o
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> > index 824dd5b57d0d3..47e45e1700326 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> > @@ -94,7 +94,6 @@
> > #include "vcn_v4_0_5.h"
> > #include "jpeg_v4_0_5.h"
> > #include "amdgpu_vkms.h"
> > -#include "mes_v10_1.h"
> > #include "mes_v11_0.h"
> > #include "mes_v12_0.h"
> > #include "smuio_v11_0.h"
> > @@ -2215,25 +2214,6 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct
> > amdgpu_device *adev)
> > static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev)
> > {
> > switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
> > - case IP_VERSION(10, 1, 10):
> > - case IP_VERSION(10, 1, 1):
> > - case IP_VERSION(10, 1, 2):
> > - case IP_VERSION(10, 1, 3):
> > - case IP_VERSION(10, 1, 4):
> > - case IP_VERSION(10, 3, 0):
> > - case IP_VERSION(10, 3, 1):
> > - case IP_VERSION(10, 3, 2):
> > - case IP_VERSION(10, 3, 3):
> > - case IP_VERSION(10, 3, 4):
> > - case IP_VERSION(10, 3, 5):
> > - case IP_VERSION(10, 3, 6):
> > - if (amdgpu_mes) {
> > - amdgpu_device_ip_block_add(adev,
> > &mes_v10_1_ip_block);
> > - adev->enable_mes = true;
> > - if (amdgpu_mes_kiq)
> > - adev->enable_mes_kiq = true;
> > - }
> > - break;
> > case IP_VERSION(11, 0, 0):
> > case IP_VERSION(11, 0, 1):
> > case IP_VERSION(11, 0, 2):
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > index fcb0fbd1a1122..21208bbcd70ef 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > @@ -3664,14 +3664,8 @@ static void gfx10_kiq_unmap_queues(struct
> > amdgpu_ring *kiq_ring,
> >enum amdgpu_unmap_queues_action action,
> >u64 gpu_addr, u64 seq)
> > {
> > - struct amdgpu_device *adev = kiq_ring->adev;
> > uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 :
> > 0;
> >
> > - if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) {
> > - amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr,
> > seq);
> > - return;
> > - }
> > -
> > amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
> > amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q:
> > 1 */
> > PACKET3_UNMAP_QUEUES_ACTION(action) |
> > @@ -3929,33 +3923,18 @@ static int gfx_v10_0_ring_test_ib(struct
> > amdgpu_ring *ring, long timeout)
> >
> > memset(&ib, 0, sizeof(ib));
> >
> > - if (ring->is_mes_queue) {
> > - uint32_t padding, offset;
> > -
> > - offset = amdgpu_mes_ctx_get_offs(ring,
> > AMDGPU_MES_CTX_IB_OFFS);
> > - padding = amdgpu_mes_ctx_get_offs(ring,
> > -
> > AMDGPU_MES_CTX_PADDING_OFFS);
> > -
> > - ib.gpu_addr
RE: [PATCH] drm/amdgpu: drop MES 10.1 support v2
[AMD Official Use Only - AMD Internal Distribution Only]
File mes_api_def.h can also be removed. This is defined for gfx10.
One minor comment inline.
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: Thursday, May 23, 2024 2:46 PM
To: Deucher, Alexander
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu: drop MES 10.1 support v2
Ping?
On Fri, May 10, 2024 at 7:37 PM Alex Deucher wrote:
>
> It was an enablement vehicle for MES 11 and was never
> productized. Remove it.
>
> v2: drop additional checks in the GFX10 code.
>
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/Makefile |1 -
> drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 20 -
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c| 281 +---
> drivers/gpu/drm/amd/amdgpu/mes_v10_1.c| 1190 -
> drivers/gpu/drm/amd/amdgpu/mes_v10_1.h| 29 -
> drivers/gpu/drm/amd/amdgpu/nv.c |1 -
> 6 files changed, 71 insertions(+), 1451 deletions(-)
> delete mode 100644 drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
> delete mode 100644 drivers/gpu/drm/amd/amdgpu/mes_v10_1.h
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
> b/drivers/gpu/drm/amd/amdgpu/Makefile
> index de7b76327f5ba..6e1237a97a91e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/Makefile
> +++ b/drivers/gpu/drm/amd/amdgpu/Makefile
> @@ -187,7 +187,6 @@ amdgpu-y += \
> # add MES block
> amdgpu-y += \
> amdgpu_mes.o \
> - mes_v10_1.o \
> mes_v11_0.o \
> mes_v12_0.o
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> index 824dd5b57d0d3..47e45e1700326 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> @@ -94,7 +94,6 @@
> #include "vcn_v4_0_5.h"
> #include "jpeg_v4_0_5.h"
> #include "amdgpu_vkms.h"
> -#include "mes_v10_1.h"
> #include "mes_v11_0.h"
> #include "mes_v12_0.h"
> #include "smuio_v11_0.h"
> @@ -2215,25 +2214,6 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct
> amdgpu_device *adev)
> static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev)
> {
> switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
> - case IP_VERSION(10, 1, 10):
> - case IP_VERSION(10, 1, 1):
> - case IP_VERSION(10, 1, 2):
> - case IP_VERSION(10, 1, 3):
> - case IP_VERSION(10, 1, 4):
> - case IP_VERSION(10, 3, 0):
> - case IP_VERSION(10, 3, 1):
> - case IP_VERSION(10, 3, 2):
> - case IP_VERSION(10, 3, 3):
> - case IP_VERSION(10, 3, 4):
> - case IP_VERSION(10, 3, 5):
> - case IP_VERSION(10, 3, 6):
> - if (amdgpu_mes) {
> - amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
> - adev->enable_mes = true;
> - if (amdgpu_mes_kiq)
> - adev->enable_mes_kiq = true;
> - }
> - break;
> case IP_VERSION(11, 0, 0):
> case IP_VERSION(11, 0, 1):
> case IP_VERSION(11, 0, 2):
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index fcb0fbd1a1122..21208bbcd70ef 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -3664,14 +3664,8 @@ static void gfx10_kiq_unmap_queues(struct amdgpu_ring
> *kiq_ring,
>enum amdgpu_unmap_queues_action action,
>u64 gpu_addr, u64 seq)
> {
> - struct amdgpu_device *adev = kiq_ring->adev;
> uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
>
> - if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) {
> - amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr,
> seq);
> - return;
> - }
> -
> amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
> amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1
> */
> PACKET3_UNMAP_QUEUES_ACTION(action) |
> @@ -3929,33 +3923,18 @@ static int gfx_v10_0_ring_test_ib(struct amdgpu_ring
> *ring, long timeout)
>
> memset(&ib, 0, sizeof(ib));
>
> - if (ring->is_mes_queue) {
> - uint32_t padding, offset;
> -
> - offset = amdgpu_mes_ctx_get_offs(ring,
> AMDGPU_MES_CTX_IB_OFFS);
> - padding = amdgpu_mes_ctx_get_offs(ring,
> -
> AMDGPU_MES_CTX_PADDING_OFFS);
> -
> - ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
> - ib.ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
> -
> - gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, padding);
> - cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, padding);
> - *cpu_ptr = cpu_to_le32(0xCAFEDEA
Re: [PATCH 3/3] drm/amdkfd: gfx12 context save/restore trap handler fixes
On 5/23/2024 13:37, Lancelot SIX wrote: @@ -622,8 +638,15 @@ L_SAVE_HWREG: #if ASIC_FAMILY >= CHIP_GFX12 // Ensure no further changes to barrier or LDS state. + // STATE_PRIV.BARRIER_COMPLETE may change up to this point. s_barrier_signal -2 s_barrier_wait -2 + + // Re-read final state of BARRIER_COMPLETE field for save. + s_getreg_b32 s_save_tmp, hwreg(S_STATUS_HWREG) + s_and_b32 s_save_tmp, s_save_tmp, SQ_WAVE_STATE_PRIV_BARRIER_COMPLETE_MASK + s_andn2_b32 s_save_status, s_save_status, SQ_WAVE_STATE_PRIV_BARRIER_COMPLETE_MASK Even if BARRIER_COMPLETE can be asserted while we are in the trap hadler, I do not think it can be cleared. That being said, it might be easier to just replace the bit, making it clearer. Yes, I chose to structure it this way to make the intent clearer. We don't gain much from dropping the s_andn2. Most of the time spent in the save handler is stalled on memory instructions. @@ -1351,7 +1369,17 @@ L_SKIP_BARRIER_RESTORE: s_setreg_b32 hwreg(HW_REG_SHADER_XNACK_MASK), s_restore_xnack_mask #endif +#if ASIC_FAMILY < CHIP_GFX12 s_setreg_b32 hwreg(S_TRAPSTS_HWREG), s_restore_trapsts Wouldn't other gfx1x architectures have a similar issue when writing TRAPSTS here? That is if TRAPSTS.SAVECTX is set while we are restoring, wouldn't we loose it? And for gfx11, there is TRAPSTS.HOST_TRAP that could have the same issue to some degree (not sure if we would loose the host trap completly, or re-enter with trap ID + HT bit set in ttmp1). Prior to gfx12 context save and host trap exceptions are not delivered to a wave until STATUS.PRIV=0, i.e. it leaves the trap handler. The changes needed for gfx12 are due to a design change in this area. Exceptions are now flagged immediately and cause re-entry to the trap if any are non-zero.
[PATCH 10/13] drm/amd/display: Add missing registers for DCN401
From: Rodrigo Siqueira Signed-off-by: Rodrigo Siqueira --- .../include/asic_reg/dcn/dcn_4_1_0_offset.h | 51 ++- 1 file changed, 50 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_1_0_offset.h index cd9d01fc12af..5dabf0abccce 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_1_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_1_0_offset.h @@ -258,6 +258,17 @@ #define regHDMISTREAMCLK0_DTO_PARAM 0x005b #define regHDMISTREAMCLK0_DTO_PARAM_BASE_IDX 2 +// base address: 0x0 + + +// base address: 0x30 + + +// addressBlock: dcn_dcec_dmu_fgsec_dispdec +// base address: 0x0 +#define regDMCUB_RBBMIF_SEC_CNTL 0x017a +#define regDMCUB_RBBMIF_SEC_CNTL_BASE_IDX 2 + // addressBlock: dcn_dcec_dmu_rbbmif_dispdec // base address: 0x0 #define regRBBMIF_TIMEOUT 0x017f @@ -861,6 +872,10 @@ #define regDWB_OVERFLOW_COUNTER_BASE_IDX 2 #define regDWB_SOFT_RESET 0x323b #define regDWB_SOFT_RESET_BASE_IDX 2 +#define regDWB_DEBUG_CTRL 0x323c +#define regDWB_DEBUG_CTRL_BASE_IDX 2 +#define regDWB_DEBUG 0x323d +#define regDWB_DEBUG_BASE_IDX 2 // addressBlock: dcn_dcec_wb0_dispdec_dwbcp_dispdec @@ -1073,6 +1088,10 @@ #define regMCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2 #define regMCIF_WB_SCLK_CHANGE 0x027f #define regMCIF_WB_SCLK_CHANGE_BASE_IDX 2 +#define regMCIF_WB_TEST_DEBUG_INDEX 0x0280 +#define regMCIF_WB_TEST_DEBUG_INDEX_BASE_IDX 2 +#define regMCIF_WB_TEST_DEBUG_DATA 0x0281 +#define regMCIF_WB_TEST_DEBUG_DATA_BASE_IDX 2 #define regMCIF_WB_BUF_1_ADDR_Y 0x0282 #define regMCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2 #define regMCIF_WB_BUF_1_ADDR_C 0x0284 @@ -7706,7 +7725,10 @@ #define regMPC_OUT3_CSC_C31_C32_B_BASE_IDX 3 #define regMPC_OUT3_CSC_C33_C34_B 0x033e #define regMPC_OUT3_CSC_C33_C34_B_BASE_IDX 3 - +#define regMPC_OCSC_TEST_DEBUG_INDEX 0x035b +#define regMPC_OCSC_TEST_DEBUG_INDEX_BASE_IDX 3 +#define regMPC_OCSC_TEST_DEBUG_DATA 0x035c +#define regMPC_OCSC_TEST_DEBUG_DATA_BASE_IDX 3 // addressBlock: dcn_dcec_opp_abm0_dispdec // base address: 0x0 @@ -12857,6 +12879,8 @@ #define regHDMI_TB_ENC_CRC_CNTL_BASE_IDX 3 #define regHDMI_TB_ENC_CRC_RESULT_0 0x0904 #define regHDMI_TB_ENC_CRC_RESULT_0_BASE_IDX 3 +#define regHDMI_TB_ENC_ENCRYPTION_CONTROL 0x0907 +#define regHDMI_TB_ENC_ENCRYPTION_CONTROL_BASE_IDX 3 #define regHDMI_TB_ENC_MODE 0x0908 #define regHDMI_TB_ENC_MODE_BASE_IDX 3 #define regHDMI_TB_ENC_INPUT_FIFO_STATUS
[PATCH 11/13] drm/amd/display: Move some init routines to dm_sw_init()
Move creation of CGS device node and the DAL allocation list from
amdgpu_dm_init() to dm_sw_init() which runs before dmub's sw init hook.
This is required for communicating with the VBIOS DMUB image from the
VBIOS that was loaded for early pre-os boot.
Signed-off-by: Aurabindo Pillai
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 20 ++-
1 file changed, 11 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 1e263b357c13..bb4573603479 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1662,13 +1662,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
init_data.driver = adev;
- adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
-
- if (!adev->dm.cgs_device) {
- DRM_ERROR("amdgpu: failed to create cgs device.\n");
- goto error;
- }
-
+ /* cgs_device was created in dm_sw_init() */
init_data.cgs_device = adev->dm.cgs_device;
init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
@@ -1752,8 +1746,6 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 0, 0))
init_data.num_virtual_links = 1;
- INIT_LIST_HEAD(&adev->dm.da_list);
-
retrieve_dmi_info(&adev->dm);
/* Display Core create. */
@@ -2321,6 +2313,16 @@ static int dm_sw_init(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
int r;
+ adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
+
+ if (!adev->dm.cgs_device) {
+ DRM_ERROR("amdgpu: failed to create cgs device.\n");
+ return -EINVAL;
+ }
+
+ /* Moved from dm init since we need to use allocations for storing
bounding box data */
+ INIT_LIST_HEAD(&adev->dm.da_list);
+
r = dm_dmub_sw_init(adev);
if (r)
return r;
--
2.39.2
[PATCH 13/13] drm/amd/display: Enable copying of bounding box data from VBIOS DMUB
Allocate some memory, send the address in chunks to dmub, and finally
ask it to copy the bounding box data into the newly allocated memory.
Signed-off-by: Aurabindo Pillai
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 121 ++
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 10 ++
.../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 24 +---
drivers/gpu/drm/amd/display/dc/core/dc.c | 5 +
drivers/gpu/drm/amd/display/dc/dc.h | 3 +
.../dc/dml2/dml21/dml21_translation_helper.c | 6 +-
.../drm/amd/display/dc/dml2/dml2_wrapper.h| 1 +
7 files changed, 146 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index bb4573603479..74accbcaae28 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1627,6 +1627,117 @@ static void retrieve_dmi_info(struct
amdgpu_display_manager *dm)
}
}
+void*
+dm_allocate_gpu_mem(
+ struct amdgpu_device *adev,
+ enum dc_gpu_mem_alloc_type type,
+ size_t size,
+ long long *addr)
+{
+ struct dal_allocation *da;
+ u32 domain = (type == DC_MEM_ALLOC_TYPE_GART) ?
+ AMDGPU_GEM_DOMAIN_GTT : AMDGPU_GEM_DOMAIN_VRAM;
+ int ret;
+
+ da = kzalloc(sizeof(struct dal_allocation), GFP_KERNEL);
+ if (!da)
+ return NULL;
+
+ ret = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE,
+ domain, &da->bo,
+ &da->gpu_addr, &da->cpu_ptr);
+
+ *addr = da->gpu_addr;
+
+ if (ret) {
+ kfree(da);
+ return NULL;
+ }
+
+ /* add da to list in dm */
+ list_add(&da->list, &adev->dm.da_list);
+
+ return da->cpu_ptr;
+}
+
+static enum dmub_status
+dm_dmub_send_vbios_gpint_command(struct amdgpu_device *adev,
+enum dmub_gpint_command command_code,
+uint16_t param,
+uint32_t timeout_us)
+{
+ union dmub_gpint_data_register reg, test;
+ uint32_t i;
+
+ /* Assume that VBIOS DMUB is ready to take commands */
+
+ reg.bits.status = 1;
+ reg.bits.command_code = command_code;
+ reg.bits.param = param;
+
+ cgs_write_register(adev->dm.cgs_device, 0x34c0 + 0x01f8, reg.all);
+
+ for (i = 0; i < timeout_us; ++i) {
+ udelay(1);
+
+ /* Check if our GPINT got acked */
+ reg.bits.status = 0;
+ test = (union dmub_gpint_data_register)
+ cgs_read_register(adev->dm.cgs_device, 0x34c0 + 0x01f8);
+
+ if (test.all == reg.all)
+ return DMUB_STATUS_OK;
+ }
+
+ return DMUB_STATUS_TIMEOUT;
+}
+
+static struct dml2_soc_bb *dm_dmub_get_vbios_bounding_box(struct amdgpu_device
*adev)
+{
+ struct dml2_soc_bb *bb;
+ long long addr;
+ int i = 0;
+ uint16_t chunk;
+ enum dmub_gpint_command send_addrs[] = {
+ DMUB_GPINT__SET_BB_ADDR_WORD0,
+ DMUB_GPINT__SET_BB_ADDR_WORD1,
+ DMUB_GPINT__SET_BB_ADDR_WORD2,
+ DMUB_GPINT__SET_BB_ADDR_WORD3,
+ };
+ enum dmub_status ret;
+
+ switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
+ case IP_VERSION(4, 0, 1):
+ break;
+ default:
+ return NULL;
+ }
+
+ bb = dm_allocate_gpu_mem(adev,
+ DC_MEM_ALLOC_TYPE_GART,
+ sizeof(struct dml2_soc_bb),
+ &addr);
+ if (!bb)
+ return NULL;
+
+ for (i = 0; i < 4; i++) {
+ /* Extract 16-bit chunk */
+ chunk = ((uint64_t) addr >> (i * 16)) & 0x;
+ /* Send the chunk */
+ ret = dm_dmub_send_vbios_gpint_command(adev, send_addrs[i],
chunk, 3);
+ if (ret != DMUB_STATUS_OK)
+ /* No need to free bb here since it shall be done
unconditionally */
+ return NULL;
+ }
+
+ /* Now ask DMUB to copy the bb */
+ ret = dm_dmub_send_vbios_gpint_command(adev, DMUB_GPINT__BB_COPY, 1,
20);
+ if (ret != DMUB_STATUS_OK)
+ return NULL;
+
+ return bb;
+}
+
static int amdgpu_dm_init(struct amdgpu_device *adev)
{
struct dc_init_data init_data;
@@ -1748,6 +1859,11 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
retrieve_dmi_info(&adev->dm);
+ if (adev->dm.bb_from_dmub)
+ init_data.bb_from_dmub = adev->dm.bb_from_dmub;
+ else
+ init_data.bb_from_dmub = NULL;
+
/* Display Core create. */
adev->dm.dc = dc_create(&init_data);
@@ -2305,6 +2421,8 @@ static int dm_d
[PATCH 12/13] drm/amd/display: Add new GPINT command definitions
New commands for enabling copy of DC bounding box values from VBIOS DMUB
Signed-off-by: Aurabindo Pillai
---
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 31 +++
1 file changed, 31 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index abf248d46b1c..f52716c54180 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -952,6 +952,37 @@ enum dmub_gpint_command {
*/
DMUB_GPINT__REPLAY_RESIDENCY = 14,
+ /**
+* DESC: Copy bounding box to the host.
+* ARGS: Version of bounding box to copy
+* RETURN: Result of copying bounding box
+*/
+ DMUB_GPINT__BB_COPY = 96,
+
+ /**
+* DESC: Updates the host addresses bit48~bit63 for bounding box.
+* ARGS: The word3 for the 64 bit address
+*/
+ DMUB_GPINT__SET_BB_ADDR_WORD3 = 97,
+
+ /**
+* DESC: Updates the host addresses bit32~bit47 for bounding box.
+* ARGS: The word2 for the 64 bit address
+*/
+ DMUB_GPINT__SET_BB_ADDR_WORD2 = 98,
+
+ /**
+* DESC: Updates the host addresses bit16~bit31 for bounding box.
+* ARGS: The word1 for the 64 bit address
+*/
+ DMUB_GPINT__SET_BB_ADDR_WORD1 = 99,
+
+ /**
+* DESC: Updates the host addresses bit0~bit15 for bounding box.
+* ARGS: The word0 for the 64 bit address
+*/
+ DMUB_GPINT__SET_BB_ADDR_WORD0 = 100,
+
/**
* DESC: Updates the trace buffer lower 32-bit mask.
* ARGS: The new mask
--
2.39.2
[PATCH 08/13] drm/amd/display: Remove incorrect FP context start
All the DC_FP_START/END should be used before call anything from DML2,
for this reason, the use of those guards inside DML it is not correct.
This commit removes two unnecessary DC_FP_START/END from a dml2
function.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c
b/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c
index 22f6a59d8ed2..5fe1110c4816 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c
@@ -759,7 +759,6 @@ static void dml2_init(const struct dc *in_dc, const struct
dml2_configuration_op
bool dml2_create(const struct dc *in_dc, const struct
dml2_configuration_options *config, struct dml2_context **dml2)
{
- DC_FP_START();
// TODO : Temporarily add DCN_VERSION_3_2 for N-1 validation. Remove
DCN_VERSION_3_2 after N-1 validation phase is complete.
if ((in_dc->debug.using_dml21) && (in_dc->ctx->dce_version ==
DCN_VERSION_4_01 || in_dc->ctx->dce_version == DCN_VERSION_3_2)) {
return dml21_create(in_dc, dml2, config);
@@ -773,7 +772,6 @@ bool dml2_create(const struct dc *in_dc, const struct
dml2_configuration_options
dml2_init(in_dc, config, dml2);
- DC_FP_END();
return true;
}
--
2.39.2
[PATCH 09/13] drm/amd/display: Fix null pointer dereference for dcn401
When ODM slice happens on DCN401, there is a null pointer exception caused by that. This commit address this issue by checking if the required data structures are initialized. Reviewed-by: Rodrigo Siqueira Signed-off-by: Aurabindo Pillai --- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 8 +--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index ce1991e06049..beca40f8694f 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -2083,8 +2083,10 @@ int resource_get_odm_slice_dst_width(struct pipe_ctx *otg_master, timing->h_border_left + timing->h_border_right; int width = h_active / count; - bool two_pixel_alignment_required = - otg_master->stream_res.tg->funcs->is_two_pixels_per_container(timing); + bool two_pixel_alignment_required = false; + + if (otg_master && otg_master->stream_res.tg && otg_master->stream) + two_pixel_alignment_required = otg_master->stream_res.tg->funcs->is_two_pixels_per_container(timing); if ((width % 2) && two_pixel_alignment_required) width++; @@ -2124,7 +2126,7 @@ struct rect resource_get_odm_slice_src_rect(struct pipe_ctx *pipe_ctx) odm_slice_dst = resource_get_odm_slice_dst_rect(opp_head); odm_slice_src = odm_slice_dst; - if (opp->funcs->opp_get_left_edge_extra_pixel_count) + if (opp && opp->funcs->opp_get_left_edge_extra_pixel_count) left_edge_extra_pixel_count = opp->funcs->opp_get_left_edge_extra_pixel_count( opp, pipe_ctx->stream->timing.pixel_encoding, -- 2.39.2
[PATCH 07/13] drm/amd/display: Use DCN 410 includes for DCN401
DCN401 is using DCN 320 headers, which does not have all the right registers for DCN401. This commit just replace DCN320 includes with the one from DCN410. Reviewed-by: Rodrigo Siqueira Signed-off-by: Aurabindo Pillai --- .../gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c| 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c b/drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c index 859d19360e9a..b43c9524b0de 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c +++ b/drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c @@ -6,8 +6,8 @@ #include "include/logger_interface.h" #include "../dce110/irq_service_dce110.h" -#include "dcn/dcn_3_2_0_offset.h" -#include "dcn/dcn_3_2_0_sh_mask.h" +#include "dcn/dcn_4_1_0_offset.h" +#include "dcn/dcn_4_1_0_sh_mask.h" #include "irq_service_dcn401.h" -- 2.39.2
[PATCH 06/13] drm/amd/display: Remove unnecessary HPD entry for DCN401
Drop the extra HPD irq entry for DCN401.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c
b/drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c
index 0b3d4616b774..859d19360e9a 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c
@@ -301,12 +301,10 @@ irq_source_info_dcn401[DAL_IRQ_SOURCES_NUMBER] = {
hpd_int_entry(1),
hpd_int_entry(2),
hpd_int_entry(3),
- hpd_int_entry(4),
hpd_rx_int_entry(0),
hpd_rx_int_entry(1),
hpd_rx_int_entry(2),
hpd_rx_int_entry(3),
- hpd_rx_int_entry(4),
i2c_int_entry(1),
i2c_int_entry(2),
i2c_int_entry(3),
--
2.39.2
[PATCH 04/13] drm/amd/display: Refactor HUBP into component folder.
From: Pinninti
[why]
cleaning up the code refactor requires hubp to be in its own component.
[how]
move all files under newly created hubp folder and fixing the makefiles.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Pinninti
---
drivers/gpu/drm/amd/display/dc/dcn401/Makefile | 1 -
drivers/gpu/drm/amd/display/dc/hubp/Makefile | 9 +++--
.../drm/amd/display/dc/{ => hubp}/dcn401/dcn401_hubp.c | 0
.../drm/amd/display/dc/{ => hubp}/dcn401/dcn401_hubp.h | 0
4 files changed, 7 insertions(+), 3 deletions(-)
rename drivers/gpu/drm/amd/display/dc/{ => hubp}/dcn401/dcn401_hubp.c (100%)
rename drivers/gpu/drm/amd/display/dc/{ => hubp}/dcn401/dcn401_hubp.h (100%)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn401/Makefile
b/drivers/gpu/drm/amd/display/dc/dcn401/Makefile
index f3fdfa1fba37..2989e706bccf 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn401/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dcn401/Makefile
@@ -4,7 +4,6 @@
DCN401 += dcn401_dio_link_encoder.o
DCN401 += dcn401_dio_stream_encoder.o
-DCN401 += dcn401_hubp.o
DCN401 += dcn401_mpc.o
AMD_DAL_DCN401 = $(addprefix $(AMDDALPATH)/dc/dcn401/,$(DCN401))
diff --git a/drivers/gpu/drm/amd/display/dc/hubp/Makefile
b/drivers/gpu/drm/amd/display/dc/hubp/Makefile
index a25a8b216e15..a2d1128de7a1 100644
--- a/drivers/gpu/drm/amd/display/dc/hubp/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/hubp/Makefile
@@ -88,5 +88,10 @@ AMD_DISPLAY_FILES += $(AMD_DAL_HUBP_DCN35)
###
-###
-endif
\ No newline at end of file
+HUBP_DCN401 = dcn401_hubp.o
+
+AMD_DAL_HUBP_DCN401 = $(addprefix $(AMDDALPATH)/dc/hubp/dcn401/,$(HUBP_DCN401))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_HUBP_DCN401)
+
+endif
diff --git a/drivers/gpu/drm/amd/display/dc/dcn401/dcn401_hubp.c
b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
similarity index 100%
rename from drivers/gpu/drm/amd/display/dc/dcn401/dcn401_hubp.c
rename to drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
diff --git a/drivers/gpu/drm/amd/display/dc/dcn401/dcn401_hubp.h
b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
similarity index 100%
rename from drivers/gpu/drm/amd/display/dc/dcn401/dcn401_hubp.h
rename to drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
--
2.39.2
[PATCH 03/13] drm/amd/display: Remove unused code
From: Rodrigo Siqueira
This commit removes some unused code with the required adjustments.
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 -
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h | 2 +-
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 5 -
.../gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c| 6 +-
4 files changed, 2 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 1055970d3888..31e3371b1b2e 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -1587,7 +1587,6 @@ struct dc_plane_state *dc_get_surface_for_mpcc(struct dc
*dc,
uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane);
void dc_set_disable_128b_132b_stream_overhead(bool disable);
-bool dc_get_disable_128b_132b_stream_overhead(void);
/* The function returns minimum bandwidth required to drive a given timing
* return - minimum required timing bandwidth in kbps.
diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
index 1aaae7a5bd41..4bc85aaf17da 100644
--- a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
@@ -726,4 +726,4 @@ void dpp401_set_cursor_matrix(
enum dc_color_space color_space,
struct dc_csc_transform cursor_csc_color_matrix);
-#endif
+#endif /* __DCN401_DPP_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
index b9d10e95ef7a..a1727e5bf024 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
@@ -1261,11 +1261,6 @@ void dc_set_disable_128b_132b_stream_overhead(bool
disable)
disable_128b_132b_stream_overhead = disable;
}
-bool dc_get_disable_128b_132b_stream_overhead(void)
-{
- return disable_128b_132b_stream_overhead;
-}
-
void dc_dsc_get_default_config_option(const struct dc *dc, struct
dc_dsc_config_options *options)
{
options->dsc_min_slice_height_override =
dc->debug.dsc_min_slice_height_override;
diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
b/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
index 597817b51228..054607c944a3 100644
--- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
@@ -880,12 +880,8 @@ static void dcn401_program_compbuf_segments(struct hubbub
*hubbub, unsigned comp
+ hubbub2->det3_size + compbuf_size_seg <=
hubbub2->crb_size_segs);
REG_UPDATE(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE,
compbuf_size_seg);
hubbub2->compbuf_size_segments = compbuf_size_seg;
-#ifdef DIAGS_BUILD
- REG_GET(DCHUBBUB_COMPBUF_CTRL, CONFIG_ERROR,
&cur_compbuf_size_seg);
- ASSERT(!cur_compbuf_size_seg);
-#else
+
ASSERT(REG_GET(DCHUBBUB_COMPBUF_CTRL, CONFIG_ERROR,
&cur_compbuf_size_seg) && !cur_compbuf_size_seg);
-#endif
}
}
--
2.39.2
[PATCH 02/13] drm/amd/display: Enable ISHARP support for DCN401
From: Samson Tam
[Why]
Enable sharpener support for DCN401
[How]
- Removed memcmp check that was preventing ISHARP from being enabled.
- Add missing ISHARP register defines, masks, and writes.
- Add programming of Blur and Scale coefficients.
- Program FMT_MODE and NLDELTA registers based on LLS_PREF and pixel
- format
- Only enable ISHARP for YUV420
- Add disabling of ISHARP
- Add debug flags and registry keys for debugging ISHARP.
- Set default to medium level
Acked-by: Rodrigo Siqueira
Signed-off-by: Samson Tam
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
.../gpu/drm/amd/display/dc/dc_spl_translate.c | 29 ++--
.../display/dc/dpp/dcn401/dcn401_dpp_dscl.c | 149 ++
.../dc/resource/dcn401/dcn401_resource.h | 13 ++
drivers/gpu/drm/amd/display/dc/spl/dc_spl.c | 81 --
.../display/dc/spl/dc_spl_isharp_filters.c| 8 +-
.../display/dc/spl/dc_spl_isharp_filters.h| 4 +-
.../gpu/drm/amd/display/dc/spl/dc_spl_types.h | 3 +
8 files changed, 223 insertions(+), 65 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index a711e3fd6f1b..1055970d3888 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -1040,6 +1040,7 @@ struct dc_debug_options {
unsigned int force_cositing;
unsigned int disable_spl;
unsigned int force_easf;
+ unsigned int force_sharpness;
unsigned int force_lls;
};
diff --git a/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c
b/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c
index 6e37b166802b..bc760448a378 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c
@@ -134,16 +134,25 @@ void translate_SPL_in_params_from_pipe_ctx(struct
pipe_ctx *pipe_ctx, struct spl
spl_in->prefer_easf = false;
else if (pipe_ctx->stream->ctx->dc->debug.force_easf == 2)
spl_in->disable_easf = true;
- // Translate adaptive sharpening preference
- spl_in->adaptive_sharpness.enable = plane_state->adaptive_sharpness_en;
- if (plane_state->sharpnessX1000 == 0) {
- spl_in->adaptive_sharpness.enable = false;
- } else if (plane_state->sharpnessX1000 < 999) {
- spl_in->adaptive_sharpness.sharpness = SHARPNESS_LOW;
- } else if (plane_state->sharpnessX1000 < 1999) {
- spl_in->adaptive_sharpness.sharpness = SHARPNESS_MID;
- } else { // Any other value is high sharpness
- spl_in->adaptive_sharpness.sharpness = SHARPNESS_HIGH;
+ /* Translate adaptive sharpening preference */
+ if (pipe_ctx->stream->ctx->dc->debug.force_sharpness > 0) {
+ spl_in->adaptive_sharpness.enable =
(pipe_ctx->stream->ctx->dc->debug.force_sharpness > 1) ? true : false;
+ if (pipe_ctx->stream->ctx->dc->debug.force_sharpness == 2)
+ spl_in->adaptive_sharpness.sharpness = SHARPNESS_LOW;
+ else if (pipe_ctx->stream->ctx->dc->debug.force_sharpness == 3)
+ spl_in->adaptive_sharpness.sharpness = SHARPNESS_MID;
+ else if (pipe_ctx->stream->ctx->dc->debug.force_sharpness >= 4)
+ spl_in->adaptive_sharpness.sharpness = SHARPNESS_HIGH;
+ } else {
+ spl_in->adaptive_sharpness.enable =
plane_state->adaptive_sharpness_en;
+ if (plane_state->sharpnessX1000 == 0)
+ spl_in->adaptive_sharpness.enable = false;
+ else if (plane_state->sharpnessX1000 < 999)
+ spl_in->adaptive_sharpness.sharpness = SHARPNESS_LOW;
+ else if (plane_state->sharpnessX1000 < 1999)
+ spl_in->adaptive_sharpness.sharpness = SHARPNESS_MID;
+ else // Any other value is high sharpness
+ spl_in->adaptive_sharpness.sharpness = SHARPNESS_HIGH;
}
// Translate linear light scaling preference
if (pipe_ctx->stream->ctx->dc->debug.force_lls > 0)
diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
index 4b1e52803c7a..6cb3fa4b585c 100644
--- a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
+++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
@@ -949,6 +949,9 @@ static void dpp401_dscl_set_isharp_filter(
{
int level;
uint32_t filter_data;
+ if (filter == NULL)
+ return;
+
REG_UPDATE(ISHARP_DELTA_CTRL,
ISHARP_DELTA_LUT_HOST_SELECT, 0);
for (level = 0; level < NUM_LEVELS; level++){
@@ -972,41 +975,121 @@ static void dpp401_dscl_program_isharp(struct dpp
*dpp_base,
const struct scaler_data *scl_data)
{
struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);
- const struct dscl_prog_data *data;
[PATCH 01/13] drm/amd/display: Fix incorrect cursor position for dcn401
From: "Arvindekar, Sridevi"
[Why]
Incorrect cursor position calculation in some scenarios. Also for
mirror and rotation cases.
[How]
Fix for incorrect cursor position. Added new test scenarios for diags
cursor test. Updated CRC for few of the diags cursor test scenarios.
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Sridevi
---
.../amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c | 18 +++
.../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 30 +--
2 files changed, 34 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c
b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c
index a54b9089f15d..aef73bd1221a 100644
--- a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c
+++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c
@@ -185,15 +185,23 @@ void dpp401_set_cursor_position(
rec_y_offset = y_pos - (cursor_height - y_hotspot);
}
- if (rec_x_offset >= (int)param->recout.width)
- cur_en = 0; /* not visible beyond right edge*/
+ if (param->rotation == ROTATION_ANGLE_0 && !param->mirror) {
+ if (rec_x_offset >= (int)param->recout.width)
+ cur_en = 0; /* not visible beyond right edge*/
+
+ if (rec_y_offset >= (int)param->recout.height)
+ cur_en = 0; /* not visible beyond bottom edge*/
+ } else {
+ if (rec_x_offset > (int)param->recout.width)
+ cur_en = 0; /* not visible beyond right edge*/
+
+ if (rec_y_offset > (int)param->recout.height)
+ cur_en = 0; /* not visible beyond bottom edge*/
+ }
if (rec_x_offset + cursor_width <= 0)
cur_en = 0; /* not visible beyond left edge*/
- if (rec_y_offset >= (int)param->recout.height)
- cur_en = 0; /* not visible beyond bottom edge*/
-
if (rec_y_offset + cursor_height <= 0)
cur_en = 0; /* not visible beyond top edge*/
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
index f5333a095adb..407a45a3ae2c 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
@@ -1126,14 +1126,14 @@ void dcn401_set_cursor_position(struct pipe_ctx
*pipe_ctx)
*/
if (param.rotation == ROTATION_ANGLE_90 || param.rotation ==
ROTATION_ANGLE_270) {
- x_pos = x_pos * pipe_ctx->stream->dst.width /
+ x_pos = pipe_ctx->stream->dst.x + x_pos *
pipe_ctx->stream->dst.width /
pipe_ctx->stream->src.height;
- y_pos = y_pos * pipe_ctx->stream->dst.height /
+ y_pos = pipe_ctx->stream->dst.y + y_pos *
pipe_ctx->stream->dst.height /
pipe_ctx->stream->src.width;
} else {
- x_pos = x_pos * pipe_ctx->stream->dst.width /
+ x_pos = pipe_ctx->stream->dst.x + x_pos *
pipe_ctx->stream->dst.width /
pipe_ctx->stream->src.width;
- y_pos = y_pos * pipe_ctx->stream->dst.height /
+ y_pos = pipe_ctx->stream->dst.y + y_pos *
pipe_ctx->stream->dst.height /
pipe_ctx->stream->src.height;
}
@@ -1225,10 +1225,15 @@ void dcn401_set_cursor_position(struct pipe_ctx
*pipe_ctx)
}
}
} else if (param.rotation == ROTATION_ANGLE_90) {
- uint32_t temp_y = pos_cpy.y;
+ if (!param.mirror) {
+ uint32_t temp_y = pos_cpy.y;
+
+ pos_cpy.y = pipe_ctx->plane_res.scl_data.recout.height
- pos_cpy.x;
+ pos_cpy.x = temp_y - prev_odm_width;
+ } else {
+ swap(pos_cpy.x, pos_cpy.y);
+ }
- pos_cpy.y = pipe_ctx->plane_res.scl_data.recout.height -
pos_cpy.x;
- pos_cpy.x = temp_y - prev_odm_width;
} else if (param.rotation == ROTATION_ANGLE_270) {
// Swap axis and mirror vertically
uint32_t temp_x = pos_cpy.x;
@@ -1279,8 +1284,15 @@ void dcn401_set_cursor_position(struct pipe_ctx
*pipe_ctx)
pos_cpy.y = temp_x;
}
} else {
- pos_cpy.x = pipe_ctx->plane_res.scl_data.recout.width -
pos_cpy.y;
- pos_cpy.y = temp_x;
+ if (param.mirror) {
+ swap(pos_cpy.x, pos_cpy.y);
+
+ pos_cpy.x =
pipe_ctx->plane_res.scl_data.recout.width - pos_cpy.x + 2 *
pipe_ctx->plane_res.scl_data.recout.x;
+ pos_cpy.y = (2 *
pipe_ctx->plane_res.scl_data.recout.y) +
pipe_ctx->plane_res.scl_data.recout.height - pos_cpy.y;
+
Re: [PATCH] drm/amdgpu: drop MES 10.1 support v2
Ping?
On Fri, May 10, 2024 at 7:37 PM Alex Deucher wrote:
>
> It was an enablement vehicle for MES 11 and was never
> productized. Remove it.
>
> v2: drop additional checks in the GFX10 code.
>
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/Makefile |1 -
> drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 20 -
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c| 281 +---
> drivers/gpu/drm/amd/amdgpu/mes_v10_1.c| 1190 -
> drivers/gpu/drm/amd/amdgpu/mes_v10_1.h| 29 -
> drivers/gpu/drm/amd/amdgpu/nv.c |1 -
> 6 files changed, 71 insertions(+), 1451 deletions(-)
> delete mode 100644 drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
> delete mode 100644 drivers/gpu/drm/amd/amdgpu/mes_v10_1.h
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
> b/drivers/gpu/drm/amd/amdgpu/Makefile
> index de7b76327f5ba..6e1237a97a91e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/Makefile
> +++ b/drivers/gpu/drm/amd/amdgpu/Makefile
> @@ -187,7 +187,6 @@ amdgpu-y += \
> # add MES block
> amdgpu-y += \
> amdgpu_mes.o \
> - mes_v10_1.o \
> mes_v11_0.o \
> mes_v12_0.o
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> index 824dd5b57d0d3..47e45e1700326 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> @@ -94,7 +94,6 @@
> #include "vcn_v4_0_5.h"
> #include "jpeg_v4_0_5.h"
> #include "amdgpu_vkms.h"
> -#include "mes_v10_1.h"
> #include "mes_v11_0.h"
> #include "mes_v12_0.h"
> #include "smuio_v11_0.h"
> @@ -2215,25 +2214,6 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct
> amdgpu_device *adev)
> static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev)
> {
> switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
> - case IP_VERSION(10, 1, 10):
> - case IP_VERSION(10, 1, 1):
> - case IP_VERSION(10, 1, 2):
> - case IP_VERSION(10, 1, 3):
> - case IP_VERSION(10, 1, 4):
> - case IP_VERSION(10, 3, 0):
> - case IP_VERSION(10, 3, 1):
> - case IP_VERSION(10, 3, 2):
> - case IP_VERSION(10, 3, 3):
> - case IP_VERSION(10, 3, 4):
> - case IP_VERSION(10, 3, 5):
> - case IP_VERSION(10, 3, 6):
> - if (amdgpu_mes) {
> - amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
> - adev->enable_mes = true;
> - if (amdgpu_mes_kiq)
> - adev->enable_mes_kiq = true;
> - }
> - break;
> case IP_VERSION(11, 0, 0):
> case IP_VERSION(11, 0, 1):
> case IP_VERSION(11, 0, 2):
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index fcb0fbd1a1122..21208bbcd70ef 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -3664,14 +3664,8 @@ static void gfx10_kiq_unmap_queues(struct amdgpu_ring
> *kiq_ring,
>enum amdgpu_unmap_queues_action action,
>u64 gpu_addr, u64 seq)
> {
> - struct amdgpu_device *adev = kiq_ring->adev;
> uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
>
> - if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) {
> - amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr,
> seq);
> - return;
> - }
> -
> amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
> amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1
> */
> PACKET3_UNMAP_QUEUES_ACTION(action) |
> @@ -3929,33 +3923,18 @@ static int gfx_v10_0_ring_test_ib(struct amdgpu_ring
> *ring, long timeout)
>
> memset(&ib, 0, sizeof(ib));
>
> - if (ring->is_mes_queue) {
> - uint32_t padding, offset;
> -
> - offset = amdgpu_mes_ctx_get_offs(ring,
> AMDGPU_MES_CTX_IB_OFFS);
> - padding = amdgpu_mes_ctx_get_offs(ring,
> -
> AMDGPU_MES_CTX_PADDING_OFFS);
> -
> - ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
> - ib.ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
> -
> - gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, padding);
> - cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, padding);
> - *cpu_ptr = cpu_to_le32(0xCAFEDEAD);
> - } else {
> - r = amdgpu_device_wb_get(adev, &index);
> - if (r)
> - return r;
> + r = amdgpu_device_wb_get(adev, &index);
> + if (r)
> + return r;
>
> - gpu_addr = adev->wb.gpu_addr + (index * 4);
> - adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
> -
Re: [PATCH 1/3] drm/amdgpu/gfx11: select HDP ref/mask according to gfx ring pipe
Ping on this series?
Alex
On Mon, May 13, 2024 at 4:32 PM Alex Deucher wrote:
>
> Use correct ref/mask for differnent gfx ring pipe. Ported from
> ZhenGuo's patch for gfx10.
>
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> index c87943f6c4436..c8c055ef2f3c2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> @@ -5294,7 +5294,7 @@ static void gfx_v11_0_ring_emit_hdp_flush(struct
> amdgpu_ring *ring)
> }
> reg_mem_engine = 0;
> } else {
> - ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
> + ref_and_mask = nbio_hf_reg->ref_and_mask_cp0 << ring->pipe;
> reg_mem_engine = 1; /* pfp */
> }
>
> --
> 2.45.0
>
Re: [PATCH] drm/amdgpu: silence UBSAN warning
Ping? On Thu, May 16, 2024 at 10:32 AM Alex Deucher wrote: > > Convert a variable sized array from [1] to []. > > Signed-off-by: Alex Deucher > --- > drivers/gpu/drm/amd/include/atomfirmware.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h > b/drivers/gpu/drm/amd/include/atomfirmware.h > index af3eebb4c9bcb..f732182218330 100644 > --- a/drivers/gpu/drm/amd/include/atomfirmware.h > +++ b/drivers/gpu/drm/amd/include/atomfirmware.h > @@ -3540,7 +3540,7 @@ struct atom_gpio_voltage_object_v4 > uint8_t phase_delay_us; // phase delay in unit of > micro second > uint8_t reserved; > uint32_t gpio_mask_val; // GPIO Mask value > - struct atom_voltage_gpio_map_lut voltage_gpio_lut[1]; > + struct atom_voltage_gpio_map_lut voltage_gpio_lut[] > __counted_by(gpio_entry_num); > }; > > struct atom_svid2_voltage_object_v4 > -- > 2.45.0 >
Re: [PATCH] drm/amdgpu: Adjust logic in amdgpu_device_partner_bandwidth()
Ping?
On Thu, May 16, 2024 at 11:42 AM Alex Deucher wrote:
>
> Use current speed/width on devices which don't support
> dynamic PCIe switching.
>
> Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3289
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 19 ---
> 1 file changed, 12 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index e72e774d17e6a..f0011dac589d2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -5946,13 +5946,18 @@ static void amdgpu_device_partner_bandwidth(struct
> amdgpu_device *adev,
> *speed = PCI_SPEED_UNKNOWN;
> *width = PCIE_LNK_WIDTH_UNKNOWN;
>
> - while ((parent = pci_upstream_bridge(parent))) {
> - /* skip upstream/downstream switches internal to dGPU*/
> - if (parent->vendor == PCI_VENDOR_ID_ATI)
> - continue;
> - *speed = pcie_get_speed_cap(parent);
> - *width = pcie_get_width_cap(parent);
> - break;
> + if (amdgpu_device_pcie_dynamic_switching_supported(adev)) {
> + while ((parent = pci_upstream_bridge(parent))) {
> + /* skip upstream/downstream switches internal to
> dGPU*/
> + if (parent->vendor == PCI_VENDOR_ID_ATI)
> + continue;
> + *speed = pcie_get_speed_cap(parent);
> + *width = pcie_get_width_cap(parent);
> + break;
> + }
> + } else {
> + /* use the current speeds rather than max if switching is not
> supported */
> + pcie_bandwidth_available(adev->pdev, NULL, speed, width);
> }
> }
>
> --
> 2.45.0
>
Re: [PATCH] Revert "drm/amdkfd: fix gfx_target_version for certain 11.0.3 devices"
Ping? On Mon, May 20, 2024 at 2:52 PM Alex Deucher wrote: > > This reverts commit 28ebbb4981cb1fad12e0b1227dbecc88810b1ee8. > > Revert this commit as apparently the LLVM code to take advantage of > this never landed. > > Signed-off-by: Alex Deucher > Cc: Feifei Xu > --- > drivers/gpu/drm/amd/amdkfd/kfd_device.c | 11 ++- > 1 file changed, 2 insertions(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c > b/drivers/gpu/drm/amd/amdkfd/kfd_device.c > index 6b15e55811b69..fba9b9a258a50 100644 > --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c > +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c > @@ -426,15 +426,8 @@ struct kfd_dev *kgd2kfd_probe(struct amdgpu_device > *adev, bool vf) > f2g = &gfx_v11_kfd2kgd; > break; > case IP_VERSION(11, 0, 3): > - if ((adev->pdev->device == 0x7460 && > -adev->pdev->revision == 0x00) || > - (adev->pdev->device == 0x7461 && > -adev->pdev->revision == 0x00)) > - /* Note: Compiler version is 11.0.5 while HW > version is 11.0.3 */ > - gfx_target_version = 110005; > - else > - /* Note: Compiler version is 11.0.1 while HW > version is 11.0.3 */ > - gfx_target_version = 110001; > + /* Note: Compiler version is 11.0.1 while HW version > is 11.0.3 */ > + gfx_target_version = 110001; > f2g = &gfx_v11_kfd2kgd; > break; > case IP_VERSION(11, 5, 0): > -- > 2.45.1 >
Re: [PATCH 2/3] drm/amdkfd: Replace deprecated gfx12 trap handler instructions
On 23/05/2024 15:08, Jay Cornwall wrote:
Newer assemblers reject S_WAITCNT. All instances of S_WAITCNT can be
replaced by S_WAITCNT 0 (< gfx12) or S_WAIT_IDLE (>= gfx12) since
there is no concurrency of different memory instruction classes.
Signed-off-by: Jay Cornwall
Cc: Lancelot Six
Thanks, that looks good to me.
Reviewed-by: Lancelot Six
---
.../gpu/drm/amd/amdkfd/cwsr_trap_handler.h| 140 +-
.../amd/amdkfd/cwsr_trap_handler_gfx10.asm| 52 +++
2 files changed, 97 insertions(+), 95 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
index 11d076eb770c..d61b2c3bd0ac 100644
--- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
+++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
@@ -711,12 +711,12 @@ static const uint32_t cwsr_trap_nv1x_hex[] = {
0xbf0d8f7b, 0xbf840002,
0x887bff7b, 0x,
0xf4011bbd, 0xfa10,
- 0xbf8cc07f, 0x8f6e976e,
+ 0xbf8c, 0x8f6e976e,
0x8a77ff77, 0x0080,
0x88776e77, 0xf4051bbd,
- 0xfa00, 0xbf8cc07f,
+ 0xfa00, 0xbf8c,
0xf4051ebd, 0xfa08,
- 0xbf8cc07f, 0x87ee6e6e,
+ 0xbf8c, 0x87ee6e6e,
0xbf840001, 0xbe80206e,
0x876eff6d, 0x00ff,
0xbf850008, 0x876eff6d,
@@ -1185,7 +1185,7 @@ static const uint32_t cwsr_trap_nv1x_hex[] = {
0x785d, 0xe0304080,
0x785d0100, 0xe0304100,
0x785d0200, 0xe0304180,
- 0x785d0300, 0xbf8c3f70,
+ 0x785d0300, 0xbf8c,
0x7e008500, 0x7e028501,
0x7e048502, 0x7e068503,
0x807c847c, 0x8078ff78,
@@ -1194,7 +1194,7 @@ static const uint32_t cwsr_trap_nv1x_hex[] = {
0x6e5d, 0xe0304080,
0x6e5d0100, 0xe0304100,
0x6e5d0200, 0xe0304180,
- 0x6e5d0300, 0xbf8c3f70,
+ 0x6e5d0300, 0xbf8c,
0xbf820034, 0xbef603ff,
0x0100, 0xbeee0378,
0x8078ff78, 0x0400,
@@ -1203,7 +1203,7 @@ static const uint32_t cwsr_trap_nv1x_hex[] = {
0x785d, 0xe0304100,
0x785d0100, 0xe0304200,
0x785d0200, 0xe0304300,
- 0x785d0300, 0xbf8c3f70,
+ 0x785d0300, 0xbf8c,
0x7e008500, 0x7e028501,
0x7e048502, 0x7e068503,
0x807c847c, 0x8078ff78,
@@ -1213,7 +1213,7 @@ static const uint32_t cwsr_trap_nv1x_hex[] = {
0x8f6f836f, 0x806f7c6f,
0xbefe03c1, 0xbeff0380,
0xe0304000, 0x785d,
- 0xbf8c3f70, 0x7e008500,
+ 0xbf8c, 0x7e008500,
0x807c817c, 0x8078ff78,
0x0080, 0xbf0a6f7c,
0xbf85fff7, 0xbeff03c1,
@@ -1221,7 +1221,7 @@ static const uint32_t cwsr_trap_nv1x_hex[] = {
0xe0304100, 0x6e5d0100,
0xe0304200, 0x6e5d0200,
0xe0304300, 0x6e5d0300,
- 0xbf8c3f70, 0xb9783a05,
+ 0xbf8c, 0xb9783a05,
0x80788178, 0xbf0d9972,
0xbf850002, 0x8f788978,
0xbf820001, 0x8f788a78,
@@ -1232,16 +1232,16 @@ static const uint32_t cwsr_trap_nv1x_hex[] = {
0x0100, 0xbefc03ff,
0x006c, 0x80f89078,
0xf429003a, 0xf000,
- 0xbf8cc07f, 0x80fc847c,
+ 0xbf8c, 0x80fc847c,
0xbf80, 0xbe803100,
0xbe823102, 0x80f8a078,
0xf42d003a, 0xf000,
- 0xbf8cc07f, 0x80fc887c,
+ 0xbf8c, 0x80fc887c,
0xbf80, 0xbe803100,
0xbe823102, 0xbe843104,
0xbe863106, 0x80f8c078,
0xf431003a, 0xf000,
- 0xbf8cc07f, 0x80fc907c,
+ 0xbf8c, 0x80fc907c,
0xbf80, 0xbe803100,
0xbe823102, 0xbe843104,
0xbe863106, 0xbe883108,
@@ -1271,9 +1271,9 @@ static const uint32_t cwsr_trap_nv1x_hex[] = {
0xf4211cfa, 0xf000,
0x80788478, 0xf4211bba,
0xf000, 0x80788478,
- 0xbf8cc07f, 0xb9eef814,
+ 0xbf8c, 0xb9eef814,
0xf4211bba, 0xf000,
- 0x80788478, 0xbf8cc07f,
+ 0x80788478, 0xbf8c,
0xb9eef815, 0xbefc036f,
0xbefe0370, 0xbeff0371,
0xb9f9f816, 0xb9fbf803,
@@ -1288,7 +1288,7 @@ static const uint32_t cwsr_trap_nv1x_hex[] = {
0x, 0xf4091c37,
0xfa50, 0xf4091d37,
0xfa60, 0xf4011e77,
- 0xfa74, 0xbf8cc07f,
+ 0xfa74, 0xbf8c,
0x906e8977, 0x876fff6e,
0x003f8000, 0x906e8677,
0x876eff6e, 0x0200,
@@ -2299,12 +2299,12 @@ static const uint32_t cwsr_trap_gfx10_hex[] = {
0xbf0d8f7b, 0xbf840002,
0x887bff7b, 0x,
0xf4011bbd, 0xfa10,
- 0xbf8cc07f, 0x8f6e976e,
+ 0xbf8c, 0x8f6e976e,
0x8a77ff77, 0x0080,
0x88776e77, 0xf4051bbd,
- 0xfa00, 0xbf8cc07f,
+ 0xfa00, 0xbf8c,
0xf4051ebd, 0xfa08,
- 0xbf8cc07f, 0x87ee6e6e,
+ 0xbf8c, 0x87ee6e6e,
0xbf840001, 0xbe80206e,
0x876eff6d, 0x00ff,
0xbf850008, 0x876eff6d,
@@ -2319,7 +2319,7 @@ static const uint32_
Re: [PATCH 1/3] drm/amdkfd: Sync trap handler binary with source
On 23/05/2024 15:08, Jay Cornwall wrote:
Source and binary have become mismatched during branch activity.
Signed-off-by: Jay Cornwall
Cc: Lancelot Six
Thanks for doing this.
This matches what I have when rebuilding the trap handlers.
Reviewed-by: Lancelot Six
---
.../gpu/drm/amd/amdkfd/cwsr_trap_handler.h| 57 ---
1 file changed, 24 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
index 73d3772cdb76..11d076eb770c 100644
--- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
+++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
@@ -718,12 +718,12 @@ static const uint32_t cwsr_trap_nv1x_hex[] = {
0xf4051ebd, 0xfa08,
0xbf8cc07f, 0x87ee6e6e,
0xbf840001, 0xbe80206e,
- 0x876eff6d, 0x01ff,
- 0xbf850005, 0x8878ff78,
- 0x2000, 0x80ec886c,
- 0x82ed806d, 0xbf820005,
- 0x876eff6d, 0x0100,
- 0xbf850002, 0x806c846c,
+ 0x876eff6d, 0x00ff,
+ 0xbf850008, 0x876eff6d,
+ 0x0100, 0xbf850007,
+ 0x8878ff78, 0x2000,
+ 0x80ec886c, 0x82ed806d,
+ 0xbf820002, 0x806c846c,
0x826d806d, 0x876dff6d,
0x, 0x907a8977,
0x877bff7a, 0x003f8000,
@@ -1136,7 +1136,7 @@ static const uint32_t cwsr_trap_nv1x_hex[] = {
0xe0704000, 0x705d,
0x807c817c, 0x8070ff70,
0x0080, 0xbf0a7b7c,
- 0xbf85fff8, 0xbf820144,
+ 0xbf85fff8, 0xbf82013e,
0xbef4037e, 0x8775ff7f,
0x, 0x8875ff75,
0x0004, 0xbef60380,
@@ -1276,10 +1276,7 @@ static const uint32_t cwsr_trap_nv1x_hex[] = {
0x80788478, 0xbf8cc07f,
0xb9eef815, 0xbefc036f,
0xbefe0370, 0xbeff0371,
- 0x876f7bff, 0x03ff,
- 0xb9ef4803, 0xb9f9f816,
- 0x876f7bff, 0xf800,
- 0x906f8b6f, 0xb9efa2c3,
+ 0xb9f9f816, 0xb9fbf803,
0xb9f3f801, 0xb96e3a05,
0x806e816e, 0xbf0d9972,
0xbf850002, 0x8f6e896e,
@@ -2309,12 +2306,12 @@ static const uint32_t cwsr_trap_gfx10_hex[] = {
0xf4051ebd, 0xfa08,
0xbf8cc07f, 0x87ee6e6e,
0xbf840001, 0xbe80206e,
- 0x876eff6d, 0x01ff,
- 0xbf850005, 0x8878ff78,
- 0x2000, 0x80ec886c,
- 0x82ed806d, 0xbf820005,
- 0x876eff6d, 0x0100,
- 0xbf850002, 0x806c846c,
+ 0x876eff6d, 0x00ff,
+ 0xbf850008, 0x876eff6d,
+ 0x0100, 0xbf850007,
+ 0x8878ff78, 0x2000,
+ 0x80ec886c, 0x82ed806d,
+ 0xbf820002, 0x806c846c,
0x826d806d, 0x876dff6d,
0x, 0x87fe7e7e,
0x87ea6a6a, 0xb9f8f802,
@@ -2549,7 +2546,7 @@ static const uint32_t cwsr_trap_gfx10_hex[] = {
0x705d, 0x807c817c,
0x8070ff70, 0x0080,
0xbf0a7b7c, 0xbf85fff8,
- 0xbf82013b, 0xbef4037e,
+ 0xbf820135, 0xbef4037e,
0x8775ff7f, 0x,
0x8875ff75, 0x0004,
0xbef60380, 0xbef703ff,
@@ -2688,10 +2685,7 @@ static const uint32_t cwsr_trap_gfx10_hex[] = {
0xf000, 0x80788478,
0xbf8cc07f, 0xb9eef815,
0xbefc036f, 0xbefe0370,
- 0xbeff0371, 0x876f7bff,
- 0x03ff, 0xb9ef4803,
- 0x876f7bff, 0xf800,
- 0x906f8b6f, 0xb9efa2c3,
+ 0xbeff0371, 0xb9fbf803,
0xb9f3f801, 0xb96e3a05,
0x806e816e, 0xbf0d9972,
0xbf850002, 0x8f6e896e,
@@ -2749,11 +2743,11 @@ static const uint32_t cwsr_trap_gfx11_hex[] = {
0xf808, 0xbf89fc07,
0x8bee6e6e, 0xbfa10001,
0xbe80486e, 0x8b6eff6d,
- 0x01ff, 0xbfa20005,
- 0x8c78ff78, 0x2000,
- 0x80ec886c, 0x82ed806d,
- 0xbfa5, 0x8b6eff6d,
- 0x0100, 0xbfa20002,
+ 0x00ff, 0xbfa20008,
+ 0x8b6eff6d, 0x0100,
+ 0xbfa20007, 0x8c78ff78,
+ 0x2000, 0x80ec886c,
+ 0x82ed806d, 0xbfa2,
0x806c846c, 0x826d806d,
0x8b6dff6d, 0x,
0x8bfe7e7e, 0x8bea6a6a,
@@ -2988,7 +2982,7 @@ static const uint32_t cwsr_trap_gfx11_hex[] = {
0x701d, 0x807d817d,
0x8070ff70, 0x0080,
0xbf0a7b7d, 0xbfa2fff8,
- 0xbfa00146, 0xbef4007e,
+ 0xbfa00140, 0xbef4007e,
0x8b75ff7f, 0x,
0x8c75ff75, 0x0004,
0xbef60080, 0xbef700ff,
@@ -3130,10 +3124,7 @@ static const uint32_t cwsr_trap_gfx11_hex[] = {
0xf000, 0x80788478,
0xbf89fc07, 0xb96ef815,
0xbefd006f, 0xbefe0070,
- 0xbeff0071, 0x8b6f7bff,
- 0x03ff, 0xb96f4803,
- 0x8b6f7bff, 0xf800,
- 0x856f8b6f, 0xb96fa2c3,
+ 0xbeff0071, 0xb97bf803,
0xb973f801, 0xb8ee3b05,
0x806e816e, 0xbf0d9972,
0xbfa20002, 0x846e896e,
@@ -4119,7 +4110,7 @@ static const uint32_t cwsr_trap_gfx12_hex[] = {
0x8b6dff6d, 0x,
0x8bfe7e7e, 0x8bea6a6a,
0xb97af804, 0xbe804a6c,
- 0xbfb0, 0xbf9f,
+ 0xbfb1
[PATCH] drm/amdkfd: simplify APU VRAM handling
With commit 89773b85599a
("drm/amdkfd: Let VRAM allocations go to GTT domain on small APUs")
big and small APU "VRAM" handling in KFD was unified. Since AMD_IS_APU
is set for both big and small APUs, we can simplify the checks in
the code.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 16
drivers/gpu/drm/amd/amdkfd/kfd_svm.h | 1 -
2 files changed, 8 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index 336eb51c4839..3af00b57cd8a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -196,7 +196,7 @@ int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device
*adev,
return -EINVAL;
vram_size = KFD_XCP_MEMORY_SIZE(adev, xcp_id);
- if (adev->gmc.is_app_apu || adev->flags & AMD_IS_APU) {
+ if (adev->flags & AMD_IS_APU) {
system_mem_needed = size;
ttm_mem_needed = size;
}
@@ -233,7 +233,7 @@ int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device
*adev,
if (adev && xcp_id >= 0) {
adev->kfd.vram_used[xcp_id] += vram_needed;
adev->kfd.vram_used_aligned[xcp_id] +=
- (adev->gmc.is_app_apu || adev->flags &
AMD_IS_APU) ?
+ (adev->flags & AMD_IS_APU) ?
vram_needed :
ALIGN(vram_needed, VRAM_AVAILABLITY_ALIGN);
}
@@ -261,7 +261,7 @@ void amdgpu_amdkfd_unreserve_mem_limit(struct amdgpu_device
*adev,
if (adev) {
adev->kfd.vram_used[xcp_id] -= size;
- if (adev->gmc.is_app_apu || adev->flags & AMD_IS_APU) {
+ if (adev->flags & AMD_IS_APU) {
adev->kfd.vram_used_aligned[xcp_id] -= size;
kfd_mem_limit.system_mem_used -= size;
kfd_mem_limit.ttm_mem_used -= size;
@@ -894,7 +894,7 @@ static int kfd_mem_attach(struct amdgpu_device *adev,
struct kgd_mem *mem,
* if peer device has large BAR. In contrast, access over xGMI is
* allowed for both small and large BAR configurations of peer device
*/
- if ((adev != bo_adev && !(adev->gmc.is_app_apu || adev->flags &
AMD_IS_APU)) &&
+ if ((adev != bo_adev && !(adev->flags & AMD_IS_APU)) &&
((mem->domain == AMDGPU_GEM_DOMAIN_VRAM) ||
(mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) ||
(mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP))) {
@@ -1682,7 +1682,7 @@ size_t amdgpu_amdkfd_get_available_memory(struct
amdgpu_device *adev,
- atomic64_read(&adev->vram_pin_size)
- reserved_for_pt;
- if (adev->gmc.is_app_apu || adev->flags & AMD_IS_APU) {
+ if (adev->flags & AMD_IS_APU) {
system_mem_available = no_system_mem_limit ?
kfd_mem_limit.max_system_mem_limit :
kfd_mem_limit.max_system_mem_limit -
@@ -1730,7 +1730,7 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
if (flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
domain = alloc_domain = AMDGPU_GEM_DOMAIN_VRAM;
- if (adev->gmc.is_app_apu || adev->flags & AMD_IS_APU) {
+ if (adev->flags & AMD_IS_APU) {
domain = AMDGPU_GEM_DOMAIN_GTT;
alloc_domain = AMDGPU_GEM_DOMAIN_GTT;
alloc_flags = 0;
@@ -1981,7 +1981,7 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
if (size) {
if (!is_imported &&
(mem->bo->preferred_domains == AMDGPU_GEM_DOMAIN_VRAM ||
- ((adev->gmc.is_app_apu || adev->flags & AMD_IS_APU) &&
+ ((adev->flags & AMD_IS_APU) &&
mem->bo->preferred_domains == AMDGPU_GEM_DOMAIN_GTT)))
*size = bo_size;
else
@@ -2404,7 +2404,7 @@ static int import_obj_create(struct amdgpu_device *adev,
(*mem)->bo = bo;
(*mem)->va = va;
(*mem)->domain = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) &&
-!(adev->gmc.is_app_apu || adev->flags & AMD_IS_APU) ?
+!(adev->flags & AMD_IS_APU) ?
AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT;
(*mem)->mapped_to_gpu_memory = 0;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.h
b/drivers/gpu/drm/amd/amdkfd/kfd_svm.h
index 9c37bd0567ef..70c1776611c4 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.h
@@ -201,7 +201,6 @@ void svm_range_list_lock_and_flush_work(struct
svm_range_list *svms, struct mm
Re: [PATCH 3/3] drm/amdkfd: gfx12 context save/restore trap handler fixes
Hi Jay,
I have added a couple (minor) of comments below.
On 23/05/2024 15:08, Jay Cornwall wrote:
Fix LDS size interpretation: 512 bytes (>= gfx12) vs 256 (< gfx12).
Ensure STATE_PRIV.BARRIER_COMPLETE cannot change after reading or
before writing. Other waves in the threadgroup may cause this field
to assert if they complete the barrier.
Do not overwrite EXCP_FLAG_PRIV.{SAVE_CONTEXT,HOST_TRAP} when
restoring this register. Both of these fields can assert while the
wavefront is running the trap handler.
Signed-off-by: Jay Cornwall
Cc: Lancelot Six
---
.../gpu/drm/amd/amdkfd/cwsr_trap_handler.h| 1191 +
.../amd/amdkfd/cwsr_trap_handler_gfx10.asm| 55 +-
2 files changed, 639 insertions(+), 607 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm
b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm
index 77ae25b6753c..18e012e04493 100644
--- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm
+++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm
@@ -75,17 +75,22 @@ var SQ_WAVE_STATUS_ECC_ERR_MASK =
0x2
var SQ_WAVE_STATUS_TRAP_EN_SHIFT = 6
var SQ_WAVE_IB_STS2_WAVE64_SHIFT = 11
var SQ_WAVE_IB_STS2_WAVE64_SIZE = 1
+var SQ_WAVE_LDS_ALLOC_GRANULARITY = 8
var S_STATUS_HWREG= HW_REG_STATUS
var S_STATUS_ALWAYS_CLEAR_MASK=
SQ_WAVE_STATUS_SPI_PRIO_MASK|SQ_WAVE_STATUS_ECC_ERR_MASK
var S_STATUS_HALT_MASK=
SQ_WAVE_STATUS_HALT_MASK
var S_SAVE_PC_HI_TRAP_ID_MASK = 0x00FF
var S_SAVE_PC_HI_HT_MASK = 0x0100
#else
+var SQ_WAVE_STATE_PRIV_BARRIER_COMPLETE_MASK = 0x4
+var SQ_WAVE_STATE_PRIV_SCC_SHIFT = 9
var SQ_WAVE_STATE_PRIV_SYS_PRIO_MASK = 0xC00
var SQ_WAVE_STATE_PRIV_HALT_MASK = 0x4000
var SQ_WAVE_STATE_PRIV_POISON_ERR_MASK= 0x8000
+var SQ_WAVE_STATE_PRIV_POISON_ERR_SHIFT= 15
var SQ_WAVE_STATUS_WAVE64_SHIFT = 29
var SQ_WAVE_STATUS_WAVE64_SIZE= 1
+var SQ_WAVE_LDS_ALLOC_GRANULARITY = 9
var S_STATUS_HWREG= HW_REG_WAVE_STATE_PRIV
var S_STATUS_ALWAYS_CLEAR_MASK=
SQ_WAVE_STATE_PRIV_SYS_PRIO_MASK|SQ_WAVE_STATE_PRIV_POISON_ERR_MASK
var S_STATUS_HALT_MASK=
SQ_WAVE_STATE_PRIV_HALT_MASK
@@ -149,8 +154,10 @@ var SQ_WAVE_EXCP_FLAG_PRIV_MEM_VIOL_MASK = 0x10
var SQ_WAVE_EXCP_FLAG_PRIV_SAVE_CONTEXT_SHIFT = 5
var SQ_WAVE_EXCP_FLAG_PRIV_SAVE_CONTEXT_MASK = 0x20
var SQ_WAVE_EXCP_FLAG_PRIV_ILLEGAL_INST_MASK = 0x40
+var SQ_WAVE_EXCP_FLAG_PRIV_ILLEGAL_INST_SHIFT = 6
var SQ_WAVE_EXCP_FLAG_PRIV_HOST_TRAP_MASK = 0x80
var SQ_WAVE_EXCP_FLAG_PRIV_WAVE_START_MASK= 0x100
+var SQ_WAVE_EXCP_FLAG_PRIV_WAVE_START_SHIFT= 8
var SQ_WAVE_EXCP_FLAG_PRIV_WAVE_END_MASK = 0x200
var SQ_WAVE_EXCP_FLAG_PRIV_TRAP_AFTER_INST_MASK = 0x800
var SQ_WAVE_TRAP_CTRL_ADDR_WATCH_MASK = 0x80
@@ -430,7 +437,16 @@ L_EXIT_TRAP:
// Restore SQ_WAVE_STATUS.
s_and_b64 exec, exec, exec
// Restore STATUS.EXECZ, not writable by s_setreg_b32
s_and_b64 vcc, vcc, vcc
// Restore STATUS.VCCZ, not writable by s_setreg_b32
+
+#if ASIC_FAMILY < CHIP_GFX12
s_setreg_b32hwreg(S_STATUS_HWREG), s_save_status
+#else
+ // STATE_PRIV.BARRIER_COMPLETE may have changed since we read it.
+ // Only restore fields which the trap handler changes.
+ s_lshr_b32 s_save_status, s_save_status,
SQ_WAVE_STATE_PRIV_SCC_SHIFT
+ s_setreg_b32hwreg(S_STATUS_HWREG, SQ_WAVE_STATE_PRIV_SCC_SHIFT, \
+ SQ_WAVE_STATE_PRIV_POISON_ERR_SHIFT -
SQ_WAVE_STATE_PRIV_SCC_SHIFT + 1), s_save_status
+#endif
s_rfe_b64 [ttmp0, ttmp1]
@@ -622,8 +638,15 @@ L_SAVE_HWREG:
#if ASIC_FAMILY >= CHIP_GFX12
// Ensure no further changes to barrier or LDS state.
+ // STATE_PRIV.BARRIER_COMPLETE may change up to this point.
s_barrier_signal-2
s_barrier_wait -2
+
+ // Re-read final state of BARRIER_COMPLETE field for save.
+ s_getreg_b32s_save_tmp, hwreg(S_STATUS_HWREG)
+ s_and_b32 s_save_tmp, s_save_tmp,
SQ_WAVE_STATE_PRIV_BARRIER_COMPLETE_MASK
+ s_andn2_b32 s_save_status, s_save_status,
SQ_WAVE_STATE_PRIV_BARRIER_COMPLETE_MASK
Even if BARRIER_COMPLETE can be asserted while we are in the trap
hadler, I do not think it can be cleared. That being said, it might be
easier to just replace the bit, making it clearer.
+ s_or_b32s_save_status, s_save_status, s_save_tmp
#endif
write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset)
@@ -764,8 +787,7 @@ L_SAVE_LDS_N
Re: [PATCH 1/3] drm/amdkfd: Sync trap handler binary with source
Series is:
Acked-by: Alex Deucher
On Thu, May 23, 2024 at 10:27 AM Jay Cornwall wrote:
>
> Source and binary have become mismatched during branch activity.
>
> Signed-off-by: Jay Cornwall
> Cc: Lancelot Six
> ---
> .../gpu/drm/amd/amdkfd/cwsr_trap_handler.h| 57 ---
> 1 file changed, 24 insertions(+), 33 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
> b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
> index 73d3772cdb76..11d076eb770c 100644
> --- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
> +++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
> @@ -718,12 +718,12 @@ static const uint32_t cwsr_trap_nv1x_hex[] = {
> 0xf4051ebd, 0xfa08,
> 0xbf8cc07f, 0x87ee6e6e,
> 0xbf840001, 0xbe80206e,
> - 0x876eff6d, 0x01ff,
> - 0xbf850005, 0x8878ff78,
> - 0x2000, 0x80ec886c,
> - 0x82ed806d, 0xbf820005,
> - 0x876eff6d, 0x0100,
> - 0xbf850002, 0x806c846c,
> + 0x876eff6d, 0x00ff,
> + 0xbf850008, 0x876eff6d,
> + 0x0100, 0xbf850007,
> + 0x8878ff78, 0x2000,
> + 0x80ec886c, 0x82ed806d,
> + 0xbf820002, 0x806c846c,
> 0x826d806d, 0x876dff6d,
> 0x, 0x907a8977,
> 0x877bff7a, 0x003f8000,
> @@ -1136,7 +1136,7 @@ static const uint32_t cwsr_trap_nv1x_hex[] = {
> 0xe0704000, 0x705d,
> 0x807c817c, 0x8070ff70,
> 0x0080, 0xbf0a7b7c,
> - 0xbf85fff8, 0xbf820144,
> + 0xbf85fff8, 0xbf82013e,
> 0xbef4037e, 0x8775ff7f,
> 0x, 0x8875ff75,
> 0x0004, 0xbef60380,
> @@ -1276,10 +1276,7 @@ static const uint32_t cwsr_trap_nv1x_hex[] = {
> 0x80788478, 0xbf8cc07f,
> 0xb9eef815, 0xbefc036f,
> 0xbefe0370, 0xbeff0371,
> - 0x876f7bff, 0x03ff,
> - 0xb9ef4803, 0xb9f9f816,
> - 0x876f7bff, 0xf800,
> - 0x906f8b6f, 0xb9efa2c3,
> + 0xb9f9f816, 0xb9fbf803,
> 0xb9f3f801, 0xb96e3a05,
> 0x806e816e, 0xbf0d9972,
> 0xbf850002, 0x8f6e896e,
> @@ -2309,12 +2306,12 @@ static const uint32_t cwsr_trap_gfx10_hex[] = {
> 0xf4051ebd, 0xfa08,
> 0xbf8cc07f, 0x87ee6e6e,
> 0xbf840001, 0xbe80206e,
> - 0x876eff6d, 0x01ff,
> - 0xbf850005, 0x8878ff78,
> - 0x2000, 0x80ec886c,
> - 0x82ed806d, 0xbf820005,
> - 0x876eff6d, 0x0100,
> - 0xbf850002, 0x806c846c,
> + 0x876eff6d, 0x00ff,
> + 0xbf850008, 0x876eff6d,
> + 0x0100, 0xbf850007,
> + 0x8878ff78, 0x2000,
> + 0x80ec886c, 0x82ed806d,
> + 0xbf820002, 0x806c846c,
> 0x826d806d, 0x876dff6d,
> 0x, 0x87fe7e7e,
> 0x87ea6a6a, 0xb9f8f802,
> @@ -2549,7 +2546,7 @@ static const uint32_t cwsr_trap_gfx10_hex[] = {
> 0x705d, 0x807c817c,
> 0x8070ff70, 0x0080,
> 0xbf0a7b7c, 0xbf85fff8,
> - 0xbf82013b, 0xbef4037e,
> + 0xbf820135, 0xbef4037e,
> 0x8775ff7f, 0x,
> 0x8875ff75, 0x0004,
> 0xbef60380, 0xbef703ff,
> @@ -2688,10 +2685,7 @@ static const uint32_t cwsr_trap_gfx10_hex[] = {
> 0xf000, 0x80788478,
> 0xbf8cc07f, 0xb9eef815,
> 0xbefc036f, 0xbefe0370,
> - 0xbeff0371, 0x876f7bff,
> - 0x03ff, 0xb9ef4803,
> - 0x876f7bff, 0xf800,
> - 0x906f8b6f, 0xb9efa2c3,
> + 0xbeff0371, 0xb9fbf803,
> 0xb9f3f801, 0xb96e3a05,
> 0x806e816e, 0xbf0d9972,
> 0xbf850002, 0x8f6e896e,
> @@ -2749,11 +2743,11 @@ static const uint32_t cwsr_trap_gfx11_hex[] = {
> 0xf808, 0xbf89fc07,
> 0x8bee6e6e, 0xbfa10001,
> 0xbe80486e, 0x8b6eff6d,
> - 0x01ff, 0xbfa20005,
> - 0x8c78ff78, 0x2000,
> - 0x80ec886c, 0x82ed806d,
> - 0xbfa5, 0x8b6eff6d,
> - 0x0100, 0xbfa20002,
> + 0x00ff, 0xbfa20008,
> + 0x8b6eff6d, 0x0100,
> + 0xbfa20007, 0x8c78ff78,
> + 0x2000, 0x80ec886c,
> + 0x82ed806d, 0xbfa2,
> 0x806c846c, 0x826d806d,
> 0x8b6dff6d, 0x,
> 0x8bfe7e7e, 0x8bea6a6a,
> @@ -2988,7 +2982,7 @@ static const uint32_t cwsr_trap_gfx11_hex[] = {
> 0x701d, 0x807d817d,
> 0x8070ff70, 0x0080,
> 0xbf0a7b7d, 0xbfa2fff8,
> - 0xbfa00146, 0xbef4007e,
> + 0xbfa00140, 0xbef4007e,
> 0x8b75ff7f, 0x,
> 0x8c75ff75, 0x0004,
> 0xbef60080, 0xbef700ff,
> @@ -3130,10 +3124,7 @@ static const uint32_t cwsr_trap_gfx11_hex[] = {
> 0xf000, 0x80788478,
> 0xbf89fc07, 0xb96ef815,
> 0xbefd006f, 0xbefe0070,
> - 0xbeff0071, 0x8b6f7bff,
> - 0x03ff, 0xb96f4803,
> - 0x8b6f7bff, 0xf800,
> - 0x856f8b6f, 0xb96fa2c3,
> + 0xbeff0071, 0xb97bf803,
> 0xb973f801, 0xb8ee3b05,
> 0x806e816e, 0xbf0d9972,
> 0xbfa20002, 0x846e896e,
> @@ -4119,7 +4110,7 @@ stat
Re: [PATCH 4/4] drm/amdgpu: prevent gpu access during reset recovery
On Thu, May 23, 2024 at 11:32 AM Christian König
wrote:
>
> Am 23.05.24 um 13:36 schrieb Li, Yunxiang (Teddy):
> > [AMD Official Use Only - AMD Internal Distribution Only]
> >
> >>> +void amdgpu_lock_hw_access(struct amdgpu_device *adev); void
> >>> +amdgpu_unlock_hw_access(struct amdgpu_device *adev); int
> >>> +amdgpu_begin_hw_access(struct amdgpu_device *adev); void
> >>> +amdgpu_end_hw_access(struct amdgpu_device *adev);
> >> Don't add anything to amdgpu.h. We are slowly decomposing that file.
> > Where would be a better place? I just wanted to have them next to
> > amdgpu_in_reset
>
> amdgpu_reset.h if you have time feel free to move amdgpu_in_reset() over
> there as well.
>
> >
> >>> @@ -5816,6 +5816,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device
> >>> *adev,
> >>> goto skip_hw_reset;
> >>> }
> >>>
> >>> + amdgpu_lock_hw_access(adev);
> >> That should already be locked here. So this will most likely deadlock.
> >>
> >>>retry:/* Rest of adevs pre asic reset from XGMI hive. */
> >>> list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
> >>> r = amdgpu_device_pre_asic_reset(tmp_adev, reset_context); @@
> >>> -5852,6 +5853,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device
> >>> *adev,
> >>> */
> >>> amdgpu_device_stop_pending_resets(tmp_adev);
> >>> }
> >>> + amdgpu_unlock_hw_access(adev);
> >>>
> >>>skip_hw_reset:
> >> Don't add helpers for that, especially not with that name.
> >>
> >> We don't block HW access, but just prevent concurrent resets.
> > Here is taking a different lock than the reset_domain->sem. It is a
> > seperate reset_domain->gpu_sem that is only locked when we will actuall do
> > reset, it is not taken in the skip_hw_reset path.
>
> Exactly that is what you should *not* do. Please don't add any new lock
> to the code. This is already complicated enough.
>
> If you think that adding wrappers for reset lock makes sense then we can
> probably do that, bot don't add any lock for hw access.
>
>
> >
> >>> uint32_t seq;
> >>>
> >>> - if (!adev->gmc.flush_pasid_uses_kiq || !ring->sched.ready ||
> >>> - !down_read_trylock(&adev->reset_domain->sem)) {
> >>> + /*
> >>> + * A GPU reset should flush all TLBs anyway, so no need to do
> >>> + * this while one is ongoing.
> >>> + */
> >>> + if (!amdgpu_begin_hw_access(adev))
> >>> + return 0;
> >>>
> >>> + if (!adev->gmc.flush_pasid_uses_kiq || !ring->sched.ready ||
> >>> + amdgpu_in_reset(adev)) {
> >> That check doesn't makes sense now any more.
> > same here, the two checks are for different scope, although I wasn't sure
> > if the original check is correct or not, is there a possibility that
> > !adev->gmc.flush_pasid_uses_kiq and !ring->sched.ready are false but
> > amdgpu_in_reset(adev) is true? and to we want to take this branch when that
> > happens?
>
> amdgpu_in_reset() in used incorrect in quite a lot of places. It should
> only be used inside the HW backend code to distinct between initial load
> and reset.
>
> All other use cases especially the ones in the IOCTL front end functions
> as well as here in the midlayer which isn't used by GPU reset are incorrect.
FWIW, I started to clean this up earlier this year, but never got
around to finishing up the patches:
https://lists.freedesktop.org/archives/amd-gfx/2024-February/104582.html
Alex
>
> >
> >>> @@ -684,12 +684,18 @@ int amdgpu_gmc_flush_gpu_tlb_pasid(struct
> >>> amdgpu_device *adev, uint16_t pasid,
> >>> struct amdgpu_ring *ring = &adev->gfx.kiq[inst].ring;
> >>> struct amdgpu_kiq *kiq = &adev->gfx.kiq[inst];
> >>> unsigned int ndw;
> >>> - signed long r;
> >>> + signed long r = 0;
> >> Please don't initialize local variables if it isn't necessary.
> >>
> >>> if (adev->gmc.flush_tlb_needs_extra_type_2)
> >>> adev->gmc.gmc_funcs->flush_gpu_tlb_pasid(adev, pasid,
> >>> 2, all_hub,
> >>> @@ -703,46 +709,42 @@ int amdgpu_gmc_flush_gpu_tlb_pasid(struct
> >>> amdgpu_device *adev, uint16_t pasid,
> >>> adev->gmc.gmc_funcs->flush_gpu_tlb_pasid(adev, pasid,
> >>> flush_type, all_hub,
> >>> inst);
> >>> - return 0;
> >>> - }
> >>> + } else {
> >> That the locking is missing here should be a separate bug fix independent
> >> of other changes.
> > I will split this off into a seperate patch, initializing r is needed
> > because I consolidated the return paths to drop the read lock.
>
> In that case better set r when it's not initialized in some path.
>
> Regards,
> Christian.
>
Re: [PATCH 1/4] drm/amdgpu: fix -Wformat-truncation warning in amdgpu_gfx_kiq_init_ring()
On Thu, May 23, 2024 at 11:51 AM Jani Nikula wrote: > > Enabling -Wformat-truncation yields the following warning: > > ../drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c: In function > ‘amdgpu_gfx_kiq_init_ring’: > ../drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c:332:61: error: ‘%d’ directive > output may be truncated writing between 1 and 10 bytes into a region of size > between 0 and 8 [-Werror=format-truncation=] > 332 | snprintf(ring->name, sizeof(ring->name), "kiq_%d.%d.%d.%d", > | ^~ > ../drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c:332:50: note: directive argument > in the range [0, 2147483647] > 332 | snprintf(ring->name, sizeof(ring->name), "kiq_%d.%d.%d.%d", > | ^ > ../drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c:332:9: note: ‘snprintf’ output > between 12 and 41 bytes into a destination of size 16 > 332 | snprintf(ring->name, sizeof(ring->name), "kiq_%d.%d.%d.%d", > | ^~~ > 333 | xcc_id, ring->me, ring->pipe, ring->queue); > | ~~ > > Silence the warning by checking the snprintf() return value. > Already fixed with this patch: https://patchwork.freedesktop.org/patch/594864/ Thanks, Alex > Signed-off-by: Jani Nikula > > --- > > Cc: Alex Deucher > Cc: "Christian König" > Cc: Pan Xinhui > Cc: amd-gfx@lists.freedesktop.org > Cc: dri-de...@lists.freedesktop.org > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 6 -- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c > index 1d955652f3ba..92744d0d2c10 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c > @@ -329,8 +329,10 @@ int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev, > int xcc_id) > > ring->eop_gpu_addr = kiq->eop_gpu_addr; > ring->no_scheduler = true; > - snprintf(ring->name, sizeof(ring->name), "kiq_%d.%d.%d.%d", > -xcc_id, ring->me, ring->pipe, ring->queue); > + r = snprintf(ring->name, sizeof(ring->name), "kiq_%d.%d.%d.%d", > +xcc_id, ring->me, ring->pipe, ring->queue); > + if (r >= sizeof(ring->name)) > + dev_warn(adev->dev, "kiq ring name truncated\n"); > r = amdgpu_ring_init(adev, ring, 1024, irq, AMDGPU_CP_KIQ_IRQ_DRIVER0, > AMDGPU_RING_PRIO_DEFAULT, NULL); > if (r) > -- > 2.39.2 >
Re: [PATCH 3/4] drm/imx: fix -Wformat-truncation warning in imx_ldb_probe()
On Thu, May 23, 2024 at 06:51:08PM +0300, Jani Nikula wrote:
> Enabling -Wformat-truncation yields the following warning:
>
> ../drivers/gpu/drm/imx/ipuv3/imx-ldb.c: In function ‘imx_ldb_probe’:
> ../drivers/gpu/drm/imx/ipuv3/imx-ldb.c:658:57: error: ‘_sel’ directive output
> may be truncated writing 4 bytes into a region of size between 3 and 13
> [-Werror=format-truncation=]
> 658 | snprintf(clkname, sizeof(clkname), "di%d_sel", i);
> | ^~~~
> ../drivers/gpu/drm/imx/ipuv3/imx-ldb.c:658:17: note: ‘snprintf’ output
> between 8 and 18 bytes into a destination of size 16
> 658 | snprintf(clkname, sizeof(clkname), "di%d_sel", i);
> | ^
If only the compiler could count to three...
>
> Silence the warning by checking the snprintf() return value.
>
> Signed-off-by: Jani Nikula
>
> ---
>
> Cc: Philipp Zabel
> Cc: Shawn Guo
> Cc: Sascha Hauer
> Cc: Pengutronix Kernel Team
> Cc: Fabio Estevam
> Cc: dri-de...@lists.freedesktop.org
> Cc: i...@lists.linux.dev
> ---
> drivers/gpu/drm/imx/ipuv3/imx-ldb.c | 6 +-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/imx/ipuv3/imx-ldb.c
> b/drivers/gpu/drm/imx/ipuv3/imx-ldb.c
> index 71d70194fcbd..46f779fe60ee 100644
> --- a/drivers/gpu/drm/imx/ipuv3/imx-ldb.c
> +++ b/drivers/gpu/drm/imx/ipuv3/imx-ldb.c
> @@ -654,8 +654,12 @@ static int imx_ldb_probe(struct platform_device *pdev)
>*/
> for (i = 0; i < 4; i++) {
> char clkname[16];
> + int len;
> +
> + len = snprintf(clkname, sizeof(clkname), "di%d_sel", i);
> + if (len >= sizeof(clkname))
> + dev_err(dev, "clkname truncated\n");
>
> - snprintf(clkname, sizeof(clkname), "di%d_sel", i);
> imx_ldb->clk_sel[i] = devm_clk_get(imx_ldb->dev, clkname);
> if (IS_ERR(imx_ldb->clk_sel[i])) {
> ret = PTR_ERR(imx_ldb->clk_sel[i]);
> --
> 2.39.2
--
Ville Syrjälä
Intel
Re: [PATCH] drm/amdgpu: drop some kernel messages in VCN code
[AMD Official Use Only - AMD Internal Distribution Only]
The patch is Reviewed-by: Sonny Jiang
Thanks,
Sonny
From: Dong, Ruijing
Sent: Thursday, May 23, 2024 12:58 PM
To: Wu, David ; amd-gfx@lists.freedesktop.org
; Koenig, Christian
Cc: Deucher, Alexander ; Liu, Leo ;
Jiang, Sonny
Subject: RE: [PATCH] drm/amdgpu: drop some kernel messages in VCN code
[AMD Official Use Only - AMD Internal Distribution Only]
Thanks for the response, and it looks good to me.
Ruijing
-Original Message-
From: Wu, David
Sent: Thursday, May 23, 2024 12:55 PM
To: Dong, Ruijing ; Wu, David ;
amd-gfx@lists.freedesktop.org; Koenig, Christian
Cc: Deucher, Alexander ; Liu, Leo ;
Jiang, Sonny
Subject: Re: [PATCH] drm/amdgpu: drop some kernel messages in VCN code
please see in line.
On 2024-05-23 12:02, Dong, Ruijing wrote:
> [AMD Official Use Only - AMD Internal Distribution Only]
>
> Please see my question inline below.
>
> Thanks,
> Ruijing
>
> -Original Message-
> From: Wu, David
> Sent: Thursday, May 23, 2024 11:05 AM
> To: amd-gfx@lists.freedesktop.org; Koenig, Christian
>
> Cc: Deucher, Alexander ; Liu, Leo
> ; Jiang, Sonny ; Dong, Ruijing
>
> Subject: [PATCH] drm/amdgpu: drop some kernel messages in VCN code
>
> We have messages when the VCN fails to initialize and there is no need to
> report on success.
> Also PSP loading FWs is the default for production.
>
> Signed-off-by: David (Ming Qiang) Wu
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 1 -
> drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c | 3 ---
> drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 10 +-
> 3 files changed, 1 insertion(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> index b89605b400c0..5e2b7c340724 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> @@ -1078,7 +1078,6 @@ void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev)
> IP_VERSION(4, 0, 3))
> break;
> }
> - dev_info(adev->dev, "Will use PSP to load VCN firmware\n");
> }
> }
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
> b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
> index 64c856bfe0cb..68ef29bc70e2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
> @@ -145,8 +145,6 @@ static int jpeg_v5_0_0_hw_init(void *handle)
> if (r)
> return r;
>
> - DRM_DEV_INFO(adev->dev, "JPEG decode initialized successfully.\n");
> -
> return 0;
> }
>
> @@ -549,7 +547,6 @@ static const struct amdgpu_ring_funcs
> jpeg_v5_0_0_dec_ring_vm_funcs = { static void
> jpeg_v5_0_0_set_dec_ring_funcs(struct amdgpu_device *adev) {
> adev->jpeg.inst->ring_dec->funcs = &jpeg_v5_0_0_dec_ring_vm_funcs;
> - DRM_DEV_INFO(adev->dev, "JPEG decode is enabled in VM mode\n");
> }
>
> static const struct amdgpu_irq_src_funcs jpeg_v5_0_0_irq_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
> b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
> index 36d4ca645c56..070b56610c7d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
> @@ -200,16 +200,10 @@ static int vcn_v5_0_0_hw_init(void *handle)
>
> r = amdgpu_ring_test_helper(ring);
> if (r)
> - goto done;
> + return r;
> }
> [Ruijing] Are we assuming the hw init process always be successful?
No - it could fail with errors and in this case the top level will report
error. Otherwise it will succeed(and no need to report successful message).
David
> return 0;
> -done:
> - if (!r)
> - DRM_INFO("VCN decode and encode initialized
> successfully(under %s).\n",
> - (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG
> Mode":"SPG Mode");
> -
> - return r;
> }
>
> /**
> @@ -1122,8 +1116,6 @@ static void
> vcn_v5_0_0_set_unified_ring_funcs(struct amdgpu_device *adev)
>
> adev->vcn.inst[i].ring_enc[0].funcs =
> &vcn_v5_0_0_unified_ring_vm_funcs;
> adev->vcn.inst[i].ring_enc[0].me = i;
> -
> - DRM_INFO("VCN(%d) encode/decode are enabled in VM mode\n", i);
> }
> }
>
> --
> 2.34.1
>
RE: [PATCH] drm/amdgpu: drop some kernel messages in VCN code
[AMD Official Use Only - AMD Internal Distribution Only]
Thanks for the response, and it looks good to me.
Ruijing
-Original Message-
From: Wu, David
Sent: Thursday, May 23, 2024 12:55 PM
To: Dong, Ruijing ; Wu, David ;
amd-gfx@lists.freedesktop.org; Koenig, Christian
Cc: Deucher, Alexander ; Liu, Leo ;
Jiang, Sonny
Subject: Re: [PATCH] drm/amdgpu: drop some kernel messages in VCN code
please see in line.
On 2024-05-23 12:02, Dong, Ruijing wrote:
> [AMD Official Use Only - AMD Internal Distribution Only]
>
> Please see my question inline below.
>
> Thanks,
> Ruijing
>
> -Original Message-
> From: Wu, David
> Sent: Thursday, May 23, 2024 11:05 AM
> To: amd-gfx@lists.freedesktop.org; Koenig, Christian
>
> Cc: Deucher, Alexander ; Liu, Leo
> ; Jiang, Sonny ; Dong, Ruijing
>
> Subject: [PATCH] drm/amdgpu: drop some kernel messages in VCN code
>
> We have messages when the VCN fails to initialize and there is no need to
> report on success.
> Also PSP loading FWs is the default for production.
>
> Signed-off-by: David (Ming Qiang) Wu
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 1 -
> drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c | 3 ---
> drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 10 +-
> 3 files changed, 1 insertion(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> index b89605b400c0..5e2b7c340724 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> @@ -1078,7 +1078,6 @@ void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev)
> IP_VERSION(4, 0, 3))
> break;
> }
> - dev_info(adev->dev, "Will use PSP to load VCN firmware\n");
> }
> }
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
> b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
> index 64c856bfe0cb..68ef29bc70e2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
> @@ -145,8 +145,6 @@ static int jpeg_v5_0_0_hw_init(void *handle)
> if (r)
> return r;
>
> - DRM_DEV_INFO(adev->dev, "JPEG decode initialized successfully.\n");
> -
> return 0;
> }
>
> @@ -549,7 +547,6 @@ static const struct amdgpu_ring_funcs
> jpeg_v5_0_0_dec_ring_vm_funcs = { static void
> jpeg_v5_0_0_set_dec_ring_funcs(struct amdgpu_device *adev) {
> adev->jpeg.inst->ring_dec->funcs = &jpeg_v5_0_0_dec_ring_vm_funcs;
> - DRM_DEV_INFO(adev->dev, "JPEG decode is enabled in VM mode\n");
> }
>
> static const struct amdgpu_irq_src_funcs jpeg_v5_0_0_irq_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
> b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
> index 36d4ca645c56..070b56610c7d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
> @@ -200,16 +200,10 @@ static int vcn_v5_0_0_hw_init(void *handle)
>
> r = amdgpu_ring_test_helper(ring);
> if (r)
> - goto done;
> + return r;
> }
> [Ruijing] Are we assuming the hw init process always be successful?
No - it could fail with errors and in this case the top level will report
error. Otherwise it will succeed(and no need to report successful message).
David
> return 0;
> -done:
> - if (!r)
> - DRM_INFO("VCN decode and encode initialized
> successfully(under %s).\n",
> - (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG
> Mode":"SPG Mode");
> -
> - return r;
> }
>
> /**
> @@ -1122,8 +1116,6 @@ static void
> vcn_v5_0_0_set_unified_ring_funcs(struct amdgpu_device *adev)
>
> adev->vcn.inst[i].ring_enc[0].funcs =
> &vcn_v5_0_0_unified_ring_vm_funcs;
> adev->vcn.inst[i].ring_enc[0].me = i;
> -
> - DRM_INFO("VCN(%d) encode/decode are enabled in VM mode\n", i);
> }
> }
>
> --
> 2.34.1
>
Re: [PATCH] drm/amdgpu: drop some kernel messages in VCN code
please see in line.
On 2024-05-23 12:02, Dong, Ruijing wrote:
[AMD Official Use Only - AMD Internal Distribution Only]
Please see my question inline below.
Thanks,
Ruijing
-Original Message-
From: Wu, David
Sent: Thursday, May 23, 2024 11:05 AM
To: amd-gfx@lists.freedesktop.org; Koenig, Christian
Cc: Deucher, Alexander ; Liu, Leo ; Jiang,
Sonny ; Dong, Ruijing
Subject: [PATCH] drm/amdgpu: drop some kernel messages in VCN code
We have messages when the VCN fails to initialize and there is no need to
report on success.
Also PSP loading FWs is the default for production.
Signed-off-by: David (Ming Qiang) Wu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 1 -
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c | 3 ---
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 10 +-
3 files changed, 1 insertion(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index b89605b400c0..5e2b7c340724 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -1078,7 +1078,6 @@ void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev)
IP_VERSION(4, 0, 3))
break;
}
- dev_info(adev->dev, "Will use PSP to load VCN firmware\n");
}
}
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
index 64c856bfe0cb..68ef29bc70e2 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
@@ -145,8 +145,6 @@ static int jpeg_v5_0_0_hw_init(void *handle)
if (r)
return r;
- DRM_DEV_INFO(adev->dev, "JPEG decode initialized successfully.\n");
-
return 0;
}
@@ -549,7 +547,6 @@ static const struct amdgpu_ring_funcs
jpeg_v5_0_0_dec_ring_vm_funcs = { static void
jpeg_v5_0_0_set_dec_ring_funcs(struct amdgpu_device *adev) {
adev->jpeg.inst->ring_dec->funcs = &jpeg_v5_0_0_dec_ring_vm_funcs;
- DRM_DEV_INFO(adev->dev, "JPEG decode is enabled in VM mode\n");
}
static const struct amdgpu_irq_src_funcs jpeg_v5_0_0_irq_funcs = { diff --git
a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
index 36d4ca645c56..070b56610c7d 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
@@ -200,16 +200,10 @@ static int vcn_v5_0_0_hw_init(void *handle)
r = amdgpu_ring_test_helper(ring);
if (r)
- goto done;
+ return r;
}
[Ruijing] Are we assuming the hw init process always be successful?
No - it could fail with errors and in this case the top level will
report error. Otherwise it will succeed(and no need to report successful
message).
David
return 0;
-done:
- if (!r)
- DRM_INFO("VCN decode and encode initialized successfully(under
%s).\n",
- (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG
Mode");
-
- return r;
}
/**
@@ -1122,8 +1116,6 @@ static void vcn_v5_0_0_set_unified_ring_funcs(struct
amdgpu_device *adev)
adev->vcn.inst[i].ring_enc[0].funcs =
&vcn_v5_0_0_unified_ring_vm_funcs;
adev->vcn.inst[i].ring_enc[0].me = i;
-
- DRM_INFO("VCN(%d) encode/decode are enabled in VM mode\n", i);
}
}
--
2.34.1
[PATCH 0/3] amd, i915, xe: drop redundant warnings from driver makefiles
I'm sending these together, as they're related, and almost identical, but I expect them to be merged individually to each driver. BR, Jani. Jani Nikula (3): drm/i915: drop redundant W=1 warnings from Makefile drm/xe: drop redundant W=1 warnings from Makefile drm/amdgpu: drop redundant W=1 warnings from Makefile drivers/gpu/drm/amd/amdgpu/Makefile | 18 +- drivers/gpu/drm/i915/Makefile | 25 + drivers/gpu/drm/xe/Makefile | 25 + 3 files changed, 3 insertions(+), 65 deletions(-) -- 2.39.2
[PATCH 3/3] drm/amdgpu: drop redundant W=1 warnings from Makefile
Since commit a61ddb4393ad ("drm: enable (most) W=1 warnings by default
across the subsystem"), most of the extra warnings in the driver
Makefile are redundant. Remove them.
Note that -Wmissing-declarations and -Wmissing-prototypes are always
enabled by default in scripts/Makefile.extrawarn.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/amd/amdgpu/Makefile | 18 +-
1 file changed, 1 insertion(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
b/drivers/gpu/drm/amd/amdgpu/Makefile
index 1f6b56ec99f6..9508d0b5708e 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -39,23 +39,7 @@ ccflags-y := -I$(FULL_AMD_PATH)/include/asic_reg \
-I$(FULL_AMD_DISPLAY_PATH)/amdgpu_dm \
-I$(FULL_AMD_PATH)/amdkfd
-subdir-ccflags-y := -Wextra
-subdir-ccflags-y += -Wunused
-subdir-ccflags-y += -Wmissing-prototypes
-subdir-ccflags-y += -Wmissing-declarations
-subdir-ccflags-y += -Wmissing-include-dirs
-subdir-ccflags-y += -Wold-style-definition
-subdir-ccflags-y += -Wmissing-format-attribute
-# Need this to avoid recursive variable evaluation issues
-cond-flags := $(call cc-option, -Wunused-but-set-variable) \
- $(call cc-option, -Wunused-const-variable) \
- $(call cc-option, -Wstringop-truncation) \
- $(call cc-option, -Wpacked-not-aligned)
-subdir-ccflags-y += $(cond-flags)
-subdir-ccflags-y += -Wno-unused-parameter
-subdir-ccflags-y += -Wno-type-limits
-subdir-ccflags-y += -Wno-sign-compare
-subdir-ccflags-y += -Wno-missing-field-initializers
+# Locally disable W=1 warnings enabled in drm subsystem Makefile
subdir-ccflags-y += -Wno-override-init
subdir-ccflags-$(CONFIG_DRM_AMDGPU_WERROR) += -Werror
--
2.39.2
[PATCH 2/4] drm/nouveau: fix -Wformat-truncation warning in nouveau_backlight_init()
Enabling -Wformat-truncation yields the following warning:
../drivers/gpu/drm/nouveau/nouveau_backlight.c: In function
‘nouveau_backlight_init’:
../drivers/gpu/drm/nouveau/nouveau_backlight.c:56:69: error: ‘%d’ directive
output may be truncated writing between 1 and 10 bytes into a region of size 3
[-Werror=format-truncation=]
56 | snprintf(backlight_name, BL_NAME_SIZE,
"nv_backlight%d", nb);
| ^~
In function ‘nouveau_get_backlight_name’,
inlined from ‘nouveau_backlight_init’ at
../drivers/gpu/drm/nouveau/nouveau_backlight.c:351:7:
../drivers/gpu/drm/nouveau/nouveau_backlight.c:56:56: note: directive argument
in the range [1, 2147483647]
56 | snprintf(backlight_name, BL_NAME_SIZE,
"nv_backlight%d", nb);
|^~~~
../drivers/gpu/drm/nouveau/nouveau_backlight.c:56:17: note: ‘snprintf’ output
between 14 and 23 bytes into a destination of size 15
56 | snprintf(backlight_name, BL_NAME_SIZE,
"nv_backlight%d", nb);
|
^~~~
Silence the warning by checking the snprintf() return value.
Signed-off-by: Jani Nikula
---
Cc: Karol Herbst
Cc: Lyude Paul
Cc: Danilo Krummrich
Cc: dri-de...@lists.freedesktop.org
Cc: nouv...@lists.freedesktop.org
---
drivers/gpu/drm/nouveau/nouveau_backlight.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/nouveau_backlight.c
b/drivers/gpu/drm/nouveau/nouveau_backlight.c
index d47442125fa1..1d77a5f280c5 100644
--- a/drivers/gpu/drm/nouveau/nouveau_backlight.c
+++ b/drivers/gpu/drm/nouveau/nouveau_backlight.c
@@ -49,13 +49,18 @@ nouveau_get_backlight_name(char
backlight_name[BL_NAME_SIZE],
struct nouveau_backlight *bl)
{
const int nb = ida_alloc_max(&bl_ida, 99, GFP_KERNEL);
+ int ret;
if (nb < 0)
return false;
if (nb > 0)
- snprintf(backlight_name, BL_NAME_SIZE, "nv_backlight%d", nb);
+ ret = snprintf(backlight_name, BL_NAME_SIZE, "nv_backlight%d",
nb);
else
- snprintf(backlight_name, BL_NAME_SIZE, "nv_backlight");
+ ret = snprintf(backlight_name, BL_NAME_SIZE, "nv_backlight");
+
+ if (ret >= BL_NAME_SIZE)
+ return false;
+
bl->id = nb;
return true;
}
--
2.39.2
[PATCH 0/4] drm: enable -Wformat-truncation
Jani Nikula (4): drm/amdgpu: fix -Wformat-truncation warning in amdgpu_gfx_kiq_init_ring() drm/nouveau: fix -Wformat-truncation warning in nouveau_backlight_init() drm/imx: fix -Wformat-truncation warning in imx_ldb_probe() drm: enable -Wformat-truncation across the subsystem drivers/gpu/drm/Makefile| 3 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 6 -- drivers/gpu/drm/imx/ipuv3/imx-ldb.c | 6 +- drivers/gpu/drm/nouveau/nouveau_backlight.c | 9 +++-- 4 files changed, 17 insertions(+), 7 deletions(-) -- 2.39.2
[PATCH 1/3] drm/i915: drop redundant W=1 warnings from Makefile
Since commit a61ddb4393ad ("drm: enable (most) W=1 warnings by default
across the subsystem"), most of the extra warnings in the driver
Makefile are redundant. Remove them.
Note that -Wmissing-declarations and -Wmissing-prototypes are always
enabled by default in scripts/Makefile.extrawarn.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/Makefile | 25 +
1 file changed, 1 insertion(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 7cad944b825c..a70d95a8fd7a 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -3,31 +3,8 @@
# Makefile for the drm device driver. This driver provides support for the
# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
-# Unconditionally enable W=1 warnings locally
-# --- begin copy-paste W=1 warnings from scripts/Makefile.extrawarn
-subdir-ccflags-y += -Wextra -Wunused -Wno-unused-parameter
-subdir-ccflags-y += -Wmissing-declarations
-subdir-ccflags-y += $(call cc-option, -Wrestrict)
-subdir-ccflags-y += -Wmissing-format-attribute
-subdir-ccflags-y += -Wmissing-prototypes
-subdir-ccflags-y += -Wold-style-definition
-subdir-ccflags-y += -Wmissing-include-dirs
-subdir-ccflags-y += $(call cc-option, -Wunused-but-set-variable)
-subdir-ccflags-y += $(call cc-option, -Wunused-const-variable)
-subdir-ccflags-y += $(call cc-option, -Wpacked-not-aligned)
-subdir-ccflags-y += $(call cc-option, -Wformat-overflow)
+# Enable W=1 warnings not enabled in drm subsystem Makefile
subdir-ccflags-y += $(call cc-option, -Wformat-truncation)
-subdir-ccflags-y += $(call cc-option, -Wstringop-truncation)
-# The following turn off the warnings enabled by -Wextra
-ifeq ($(findstring 2, $(KBUILD_EXTRA_WARN)),)
-subdir-ccflags-y += -Wno-missing-field-initializers
-subdir-ccflags-y += -Wno-type-limits
-subdir-ccflags-y += -Wno-shift-negative-value
-endif
-ifeq ($(findstring 3, $(KBUILD_EXTRA_WARN)),)
-subdir-ccflags-y += -Wno-sign-compare
-endif
-# --- end copy-paste
# Enable -Werror in CI and development
subdir-ccflags-$(CONFIG_DRM_I915_WERROR) += -Werror
--
2.39.2
[PATCH 4/4] drm: enable -Wformat-truncation across the subsystem
With the -Wformat-truncation warnings fixed, finish the job started in
commit a61ddb4393ad ("drm: enable (most) W=1 warnings by default across
the subsystem"), and enable that warning too.
Signed-off-by: Jani Nikula
---
Gut feeling says there are more issues, and my configs just don't catch
them all, but let's see what the build bots have to say. ;)
---
drivers/gpu/drm/Makefile | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index 68cc9258ffc4..644613dbedda 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -16,8 +16,7 @@ subdir-ccflags-y += $(call cc-option,
-Wunused-but-set-variable)
subdir-ccflags-y += $(call cc-option, -Wunused-const-variable)
subdir-ccflags-y += $(call cc-option, -Wpacked-not-aligned)
subdir-ccflags-y += $(call cc-option, -Wformat-overflow)
-# FIXME: fix -Wformat-truncation warnings and uncomment
-#subdir-ccflags-y += $(call cc-option, -Wformat-truncation)
+subdir-ccflags-y += $(call cc-option, -Wformat-truncation)
subdir-ccflags-y += $(call cc-option, -Wstringop-truncation)
# The following turn off the warnings enabled by -Wextra
ifeq ($(findstring 2, $(KBUILD_EXTRA_WARN)),)
--
2.39.2
[PATCH 1/4] drm/amdgpu: fix -Wformat-truncation warning in amdgpu_gfx_kiq_init_ring()
Enabling -Wformat-truncation yields the following warning: ../drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c: In function ‘amdgpu_gfx_kiq_init_ring’: ../drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c:332:61: error: ‘%d’ directive output may be truncated writing between 1 and 10 bytes into a region of size between 0 and 8 [-Werror=format-truncation=] 332 | snprintf(ring->name, sizeof(ring->name), "kiq_%d.%d.%d.%d", | ^~ ../drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c:332:50: note: directive argument in the range [0, 2147483647] 332 | snprintf(ring->name, sizeof(ring->name), "kiq_%d.%d.%d.%d", | ^ ../drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c:332:9: note: ‘snprintf’ output between 12 and 41 bytes into a destination of size 16 332 | snprintf(ring->name, sizeof(ring->name), "kiq_%d.%d.%d.%d", | ^~~ 333 | xcc_id, ring->me, ring->pipe, ring->queue); | ~~ Silence the warning by checking the snprintf() return value. Signed-off-by: Jani Nikula --- Cc: Alex Deucher Cc: "Christian König" Cc: Pan Xinhui Cc: amd-gfx@lists.freedesktop.org Cc: dri-de...@lists.freedesktop.org --- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c index 1d955652f3ba..92744d0d2c10 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c @@ -329,8 +329,10 @@ int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev, int xcc_id) ring->eop_gpu_addr = kiq->eop_gpu_addr; ring->no_scheduler = true; - snprintf(ring->name, sizeof(ring->name), "kiq_%d.%d.%d.%d", -xcc_id, ring->me, ring->pipe, ring->queue); + r = snprintf(ring->name, sizeof(ring->name), "kiq_%d.%d.%d.%d", +xcc_id, ring->me, ring->pipe, ring->queue); + if (r >= sizeof(ring->name)) + dev_warn(adev->dev, "kiq ring name truncated\n"); r = amdgpu_ring_init(adev, ring, 1024, irq, AMDGPU_CP_KIQ_IRQ_DRIVER0, AMDGPU_RING_PRIO_DEFAULT, NULL); if (r) -- 2.39.2
[PATCH 3/4] drm/imx: fix -Wformat-truncation warning in imx_ldb_probe()
Enabling -Wformat-truncation yields the following warning:
../drivers/gpu/drm/imx/ipuv3/imx-ldb.c: In function ‘imx_ldb_probe’:
../drivers/gpu/drm/imx/ipuv3/imx-ldb.c:658:57: error: ‘_sel’ directive output
may be truncated writing 4 bytes into a region of size between 3 and 13
[-Werror=format-truncation=]
658 | snprintf(clkname, sizeof(clkname), "di%d_sel", i);
| ^~~~
../drivers/gpu/drm/imx/ipuv3/imx-ldb.c:658:17: note: ‘snprintf’ output between
8 and 18 bytes into a destination of size 16
658 | snprintf(clkname, sizeof(clkname), "di%d_sel", i);
| ^
Silence the warning by checking the snprintf() return value.
Signed-off-by: Jani Nikula
---
Cc: Philipp Zabel
Cc: Shawn Guo
Cc: Sascha Hauer
Cc: Pengutronix Kernel Team
Cc: Fabio Estevam
Cc: dri-de...@lists.freedesktop.org
Cc: i...@lists.linux.dev
---
drivers/gpu/drm/imx/ipuv3/imx-ldb.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/imx/ipuv3/imx-ldb.c
b/drivers/gpu/drm/imx/ipuv3/imx-ldb.c
index 71d70194fcbd..46f779fe60ee 100644
--- a/drivers/gpu/drm/imx/ipuv3/imx-ldb.c
+++ b/drivers/gpu/drm/imx/ipuv3/imx-ldb.c
@@ -654,8 +654,12 @@ static int imx_ldb_probe(struct platform_device *pdev)
*/
for (i = 0; i < 4; i++) {
char clkname[16];
+ int len;
+
+ len = snprintf(clkname, sizeof(clkname), "di%d_sel", i);
+ if (len >= sizeof(clkname))
+ dev_err(dev, "clkname truncated\n");
- snprintf(clkname, sizeof(clkname), "di%d_sel", i);
imx_ldb->clk_sel[i] = devm_clk_get(imx_ldb->dev, clkname);
if (IS_ERR(imx_ldb->clk_sel[i])) {
ret = PTR_ERR(imx_ldb->clk_sel[i]);
--
2.39.2
Re: Kernel 5.15.150 black screen with AMD Raven/Picasso GPU
Am 23.05.24 um 15:13 schrieb Barry Kauler:
On Wed, May 22, 2024 at 12:58 AM Armin Wolf wrote:
Am 20.05.24 um 18:22 schrieb Alex Deucher:
On Sat, May 18, 2024 at 8:17 PM Armin Wolf wrote:
Am 17.05.24 um 03:30 schrieb Barry Kauler:
Armin, Yifan, Prike,
I will top-post, so you don't have to scroll down.
After identifying the commit that causes black screen with my gpu, I
posted the result to you guys, on May 9.
It is now May 17 and no reply.
OK, I have now created a patch that reverts Yifan's commit, compiled
5.15.158, and my gpu now works.
Note, the radeon module is not loaded, so it is not a factor.
I'm not a kernel developer. I have identified the culprit and it is up
to you guys to fix it, Yifan especially, as you are the person who has
created the regression.
I will attach my patch.
Regards,
Barry Kauler
Hi,
sorry for not responding to your findings. I normally do not work with GPU
drivers,
so i hoped one of the amdgpu developers would handle this.
I cceddri-de...@lists.freedesktop.org and amd-gfx@lists.freedesktop.org so
that other
amdgpu developers hear from this issue.
Thanks you for you persistence in finding the offending commit.
Likely this patch should not have been ported to 5.15 in the first
place. The IOMMU requirements have been dropped from the driver for
the last few kernel versions so it is no longer relevant on newer
kernels.
Alex
Barry, can you verify that the latest upstream kernel works on you device?
If yes, then the commit itself is ok and just the backporting itself was wrong.
Thanks,
Armin Wolf
Armin,
The unmodified 6.8.1 kernel works ok.
I presume that patch was applied long before 6.8.1 got released and
only got backported to 5.15.x recently.
Regards,
Barry
Great to hear, that means we only have to revert commit 56b522f46681 ("drm/amdgpu:
init iommu after amdkfd device init")
from the 5.15.y series.
I CCed the stable mailing list so that they can revert the offending commit.
Thanks,
Armin Wolf
Armin Wolf
On Thu, May 9, 2024 at 4:08 PM Barry Kauler wrote:
On Fri, May 3, 2024 at 9:03 PM Armin Wolf wrote:
...
# lspci | grep VGA
05:00.0 VGA compatible controller: Advanced Micro Devices, Inc.
[AMD/ATI] Picasso/Raven 2 [Radeon Vega Series / Radeon Vega Mobile
Series] (rev c2)
05:00.7 Non-VGA unclassified device: Advanced Micro Devices, Inc.
[AMD] Raven/Raven2/Renoir Non-Sensor Fusion Hub KMDF driver
# lspci -n -k
...
05:00.0 0300: 1002:15d8 (rev c2)
Subsystem: 1025:1456
Kernel driver in use: amdgpu
Kernel modules: amdgpu
...
thanks for informing us of this regression. Since there are four commits
affecting
amdgpu in 5.15.150, i suggest that you use "git bisect" to find the faulty
commits,
see https://docs.kernel.org/admin-guide/bug-bisect.html for details.
I think you can speed up the bisecting process by limiting yourself to the AMD
DRM
driver directory with "git bisect start -- drivers/gpu/drm/amd", take a look at
the
man page of "git bisect" for details.
Thanks,
Armin Wolf
Armin,
Thanks for the advice. I am unfamiliar with git on the commandline.
Previously only used SmartGit gui.
EasyOS requires aufs patch, and for a few days tried to figure out how
to use that with git bisect, then gave up. Changed to testing with my
"QV" distro, which is more conventional, doesn't need any kernel
patches. Managed to get it down to one commit. Here are the steps I
followed:
# git clone
git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git
# cd linux-stable
# git tag -l | grep '5\.15\.150'
v5.15.150
# git checkout -b my5.15.150 v5.15.150
Updating files: 100% (65776/65776), done.
Switched to a new branch 'my5.15.150'
Copied in my .config then...
# make menuconfig
# git bisect start -- drivers/gpu/drm/amd
# git bisect bad
# git bisect good v5.15.149
Bisecting: 1 revision left to test after this (roughly 1 step)
[b9a61ee2bb2704e42516e3da962f99dfa98f3b20] drm/amdgpu: reset gpu for
s3 suspend abort case
# make
# rm -rf /boot2
# mkdir -p /boot2/lib/modules
# make INSTALL_MOD_STRIP=1 INSTALL_MOD_PATH=/boot2 modules_install
# cp arch/x86/boot/bzImage /boot2/vmlinuz
# sync
...QV on Acer laptop, with amdgpu, works!
# git bisect good
Bisecting: 0 revisions left to test after this (roughly 0 steps)
[56b522f4668167096a50c39446d6263c96219f5f] drm/amdgpu: init iommu
after amdkfd device init
# make
# mkdir -p /boot2/lib/modules
# make INSTALL_MOD_STRIP=1 INSTALL_MOD_PATH=/boot2 modules_install
# cp arch/x86/boot/bzImage /boot2/vmlinuz
# sync
...QV on Acer laptop, black screen!
# git bisect bad
56b522f4668167096a50c39446d6263c96219f5f is the first bad commit
commit 56b522f4668167096a50c39446d6263c96219f5f
Author: Yifan Zhang
Date: Tue Sep 28 15:42:35 2021 +0800
drm/amdgpu: init iommu after amdkfd device init
[ Upstream commit 286826d7d976e7646b09149d9bc2899d74ff962b ]
This patch is to fix clinfo failure in Raven/Picasso:
Number of platforms: 1
Platform Profile: FULL_PROFILE
Platform Version: OpenC
[PATCH 2/3] drm/xe: drop redundant W=1 warnings from Makefile
Since commit a61ddb4393ad ("drm: enable (most) W=1 warnings by default
across the subsystem"), most of the extra warnings in the driver
Makefile are redundant. Remove them.
Note that -Wmissing-declarations and -Wmissing-prototypes are always
enabled by default in scripts/Makefile.extrawarn.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/xe/Makefile | 25 +
1 file changed, 1 insertion(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index c9f067b8f54d..f4366cb958be 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -3,31 +3,8 @@
# Makefile for the drm device driver. This driver provides support for the
# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
-# Unconditionally enable W=1 warnings locally
-# --- begin copy-paste W=1 warnings from scripts/Makefile.extrawarn
-subdir-ccflags-y += -Wextra -Wunused -Wno-unused-parameter
-subdir-ccflags-y += -Wmissing-declarations
-subdir-ccflags-y += $(call cc-option, -Wrestrict)
-subdir-ccflags-y += -Wmissing-format-attribute
-subdir-ccflags-y += -Wmissing-prototypes
-subdir-ccflags-y += -Wold-style-definition
-subdir-ccflags-y += -Wmissing-include-dirs
-subdir-ccflags-y += $(call cc-option, -Wunused-but-set-variable)
-subdir-ccflags-y += $(call cc-option, -Wunused-const-variable)
-subdir-ccflags-y += $(call cc-option, -Wpacked-not-aligned)
-subdir-ccflags-y += $(call cc-option, -Wformat-overflow)
+# Enable W=1 warnings not enabled in drm subsystem Makefile
subdir-ccflags-y += $(call cc-option, -Wformat-truncation)
-subdir-ccflags-y += $(call cc-option, -Wstringop-truncation)
-# The following turn off the warnings enabled by -Wextra
-ifeq ($(findstring 2, $(KBUILD_EXTRA_WARN)),)
-subdir-ccflags-y += -Wno-missing-field-initializers
-subdir-ccflags-y += -Wno-type-limits
-subdir-ccflags-y += -Wno-shift-negative-value
-endif
-ifeq ($(findstring 3, $(KBUILD_EXTRA_WARN)),)
-subdir-ccflags-y += -Wno-sign-compare
-endif
-# --- end copy-paste
# Enable -Werror in CI and development
subdir-ccflags-$(CONFIG_DRM_XE_WERROR) += -Werror
--
2.39.2
Re: Kernel 5.15.150 black screen with AMD Raven/Picasso GPU
On Wed, May 22, 2024 at 12:58 AM Armin Wolf wrote: > > Am 20.05.24 um 18:22 schrieb Alex Deucher: > > > On Sat, May 18, 2024 at 8:17 PM Armin Wolf wrote: > >> Am 17.05.24 um 03:30 schrieb Barry Kauler: > >> > >>> Armin, Yifan, Prike, > >>> I will top-post, so you don't have to scroll down. > >>> After identifying the commit that causes black screen with my gpu, I > >>> posted the result to you guys, on May 9. > >>> It is now May 17 and no reply. > >>> OK, I have now created a patch that reverts Yifan's commit, compiled > >>> 5.15.158, and my gpu now works. > >>> Note, the radeon module is not loaded, so it is not a factor. > >>> I'm not a kernel developer. I have identified the culprit and it is up > >>> to you guys to fix it, Yifan especially, as you are the person who has > >>> created the regression. > >>> I will attach my patch. > >>> Regards, > >>> Barry Kauler > >> Hi, > >> > >> sorry for not responding to your findings. I normally do not work with GPU > >> drivers, > >> so i hoped one of the amdgpu developers would handle this. > >> > >> I cceddri-de...@lists.freedesktop.org and amd-gfx@lists.freedesktop.org > >> so that other > >> amdgpu developers hear from this issue. > >> > >> Thanks you for you persistence in finding the offending commit. > > Likely this patch should not have been ported to 5.15 in the first > > place. The IOMMU requirements have been dropped from the driver for > > the last few kernel versions so it is no longer relevant on newer > > kernels. > > > > Alex > > Barry, can you verify that the latest upstream kernel works on you device? > If yes, then the commit itself is ok and just the backporting itself was > wrong. > > Thanks, > Armin Wolf Armin, The unmodified 6.8.1 kernel works ok. I presume that patch was applied long before 6.8.1 got released and only got backported to 5.15.x recently. Regards, Barry > >> Armin Wolf > >> > >>> On Thu, May 9, 2024 at 4:08 PM Barry Kauler wrote: > On Fri, May 3, 2024 at 9:03 PM Armin Wolf wrote: > >> ... > >> # lspci | grep VGA > >> 05:00.0 VGA compatible controller: Advanced Micro Devices, Inc. > >> [AMD/ATI] Picasso/Raven 2 [Radeon Vega Series / Radeon Vega Mobile > >> Series] (rev c2) > >> 05:00.7 Non-VGA unclassified device: Advanced Micro Devices, Inc. > >> [AMD] Raven/Raven2/Renoir Non-Sensor Fusion Hub KMDF driver > >> > >> # lspci -n -k > >> ... > >> 05:00.0 0300: 1002:15d8 (rev c2) > >> Subsystem: 1025:1456 > >> Kernel driver in use: amdgpu > >> Kernel modules: amdgpu > >> ... > > thanks for informing us of this regression. Since there are four > > commits affecting > > amdgpu in 5.15.150, i suggest that you use "git bisect" to find the > > faulty commits, > > see https://docs.kernel.org/admin-guide/bug-bisect.html for details. > > > > I think you can speed up the bisecting process by limiting yourself to > > the AMD DRM > > driver directory with "git bisect start -- drivers/gpu/drm/amd", take a > > look at the > > man page of "git bisect" for details. > > > > Thanks, > > Armin Wolf > Armin, > Thanks for the advice. I am unfamiliar with git on the commandline. > Previously only used SmartGit gui. > EasyOS requires aufs patch, and for a few days tried to figure out how > to use that with git bisect, then gave up. Changed to testing with my > "QV" distro, which is more conventional, doesn't need any kernel > patches. Managed to get it down to one commit. Here are the steps I > followed: > > # git clone > git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git > # cd linux-stable > # git tag -l | grep '5\.15\.150' > v5.15.150 > # git checkout -b my5.15.150 v5.15.150 > Updating files: 100% (65776/65776), done. > Switched to a new branch 'my5.15.150' > > Copied in my .config then... > > # make menuconfig > # git bisect start -- drivers/gpu/drm/amd > # git bisect bad > # git bisect good v5.15.149 > Bisecting: 1 revision left to test after this (roughly 1 step) > [b9a61ee2bb2704e42516e3da962f99dfa98f3b20] drm/amdgpu: reset gpu for > s3 suspend abort case > # make > # rm -rf /boot2 > # mkdir -p /boot2/lib/modules > # make INSTALL_MOD_STRIP=1 INSTALL_MOD_PATH=/boot2 modules_install > # cp arch/x86/boot/bzImage /boot2/vmlinuz > # sync > ...QV on Acer laptop, with amdgpu, works! > # git bisect good > Bisecting: 0 revisions left to test after this (roughly 0 steps) > [56b522f4668167096a50c39446d6263c96219f5f] drm/amdgpu: init iommu > after amdkfd device init > # make > # mkdir -p /boot2/lib/modules > # make INSTALL_MOD_STRIP=1 INSTALL_MOD_PATH=/boot2 modules_install > # cp arch/x86/boot/bzImage /boot2/vmlinuz > # sync > ...QV on Acer laptop, black screen! > > # git bis
RE: [PATCH] drm/amdgpu: drop some kernel messages in VCN code
[AMD Official Use Only - AMD Internal Distribution Only]
Please see my question inline below.
Thanks,
Ruijing
-Original Message-
From: Wu, David
Sent: Thursday, May 23, 2024 11:05 AM
To: amd-gfx@lists.freedesktop.org; Koenig, Christian
Cc: Deucher, Alexander ; Liu, Leo ;
Jiang, Sonny ; Dong, Ruijing
Subject: [PATCH] drm/amdgpu: drop some kernel messages in VCN code
We have messages when the VCN fails to initialize and there is no need to
report on success.
Also PSP loading FWs is the default for production.
Signed-off-by: David (Ming Qiang) Wu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 1 -
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c | 3 ---
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 10 +-
3 files changed, 1 insertion(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index b89605b400c0..5e2b7c340724 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -1078,7 +1078,6 @@ void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev)
IP_VERSION(4, 0, 3))
break;
}
- dev_info(adev->dev, "Will use PSP to load VCN firmware\n");
}
}
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
index 64c856bfe0cb..68ef29bc70e2 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
@@ -145,8 +145,6 @@ static int jpeg_v5_0_0_hw_init(void *handle)
if (r)
return r;
- DRM_DEV_INFO(adev->dev, "JPEG decode initialized successfully.\n");
-
return 0;
}
@@ -549,7 +547,6 @@ static const struct amdgpu_ring_funcs
jpeg_v5_0_0_dec_ring_vm_funcs = { static void
jpeg_v5_0_0_set_dec_ring_funcs(struct amdgpu_device *adev) {
adev->jpeg.inst->ring_dec->funcs = &jpeg_v5_0_0_dec_ring_vm_funcs;
- DRM_DEV_INFO(adev->dev, "JPEG decode is enabled in VM mode\n");
}
static const struct amdgpu_irq_src_funcs jpeg_v5_0_0_irq_funcs = { diff --git
a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
index 36d4ca645c56..070b56610c7d 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
@@ -200,16 +200,10 @@ static int vcn_v5_0_0_hw_init(void *handle)
r = amdgpu_ring_test_helper(ring);
if (r)
- goto done;
+ return r;
}
[Ruijing] Are we assuming the hw init process always be successful?
return 0;
-done:
- if (!r)
- DRM_INFO("VCN decode and encode initialized successfully(under
%s).\n",
- (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG
Mode":"SPG Mode");
-
- return r;
}
/**
@@ -1122,8 +1116,6 @@ static void vcn_v5_0_0_set_unified_ring_funcs(struct
amdgpu_device *adev)
adev->vcn.inst[i].ring_enc[0].funcs =
&vcn_v5_0_0_unified_ring_vm_funcs;
adev->vcn.inst[i].ring_enc[0].me = i;
-
- DRM_INFO("VCN(%d) encode/decode are enabled in VM mode\n", i);
}
}
--
2.34.1
RE: [PATCH 4/4] drm/amdgpu: prevent gpu access during reset recovery
[Public] > > Here is taking a different lock than the reset_domain->sem. It is a > > seperate reset_domain->gpu_sem that is only locked when we will actuall do > > reset, it is not taken in the skip_hw_reset path. > > Exactly that is what you should *not* do. Please don't add any new lock to > the code. This is already complicated enough. > > If you think that adding wrappers for reset lock makes sense then we can > probably do that, bot don't add any lock for hw access. The two lock protects very different things though. The first case is we need to block two resets running in parallel, this does not only cover GPU reset itself but also any teardown that happens before GPU reset. The second case is we need to ensure exclusive access to the GPU between GPU reset and GPU init, concurrent access is fine before GPU is reset. Theoretically, the second case happens within the first case, so locking the first case would protect against both. But with the current implementation this is infeasible, all the generic functions called between amdgpu_device_lock/unlock_reset_domain would need to be swapped out for special versions so the reset thread does not dead lock itself. It is much simpler to have a second, much narrower lock that only covers GPU reset<->GPU init because all the accesses there are very low level anyway. Teddy
[PATCH] drm/amdgpu: drop some kernel messages in VCN code
We have messages when the VCN fails to initialize and
there is no need to report on success.
Also PSP loading FWs is the default for production.
Signed-off-by: David (Ming Qiang) Wu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 1 -
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c | 3 ---
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 10 +-
3 files changed, 1 insertion(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index b89605b400c0..5e2b7c340724 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -1078,7 +1078,6 @@ void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev)
IP_VERSION(4, 0, 3))
break;
}
- dev_info(adev->dev, "Will use PSP to load VCN firmware\n");
}
}
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
index 64c856bfe0cb..68ef29bc70e2 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
@@ -145,8 +145,6 @@ static int jpeg_v5_0_0_hw_init(void *handle)
if (r)
return r;
- DRM_DEV_INFO(adev->dev, "JPEG decode initialized successfully.\n");
-
return 0;
}
@@ -549,7 +547,6 @@ static const struct amdgpu_ring_funcs
jpeg_v5_0_0_dec_ring_vm_funcs = {
static void jpeg_v5_0_0_set_dec_ring_funcs(struct amdgpu_device *adev)
{
adev->jpeg.inst->ring_dec->funcs = &jpeg_v5_0_0_dec_ring_vm_funcs;
- DRM_DEV_INFO(adev->dev, "JPEG decode is enabled in VM mode\n");
}
static const struct amdgpu_irq_src_funcs jpeg_v5_0_0_irq_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
index 36d4ca645c56..070b56610c7d 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
@@ -200,16 +200,10 @@ static int vcn_v5_0_0_hw_init(void *handle)
r = amdgpu_ring_test_helper(ring);
if (r)
- goto done;
+ return r;
}
return 0;
-done:
- if (!r)
- DRM_INFO("VCN decode and encode initialized successfully(under
%s).\n",
- (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG
Mode":"SPG Mode");
-
- return r;
}
/**
@@ -1122,8 +1116,6 @@ static void vcn_v5_0_0_set_unified_ring_funcs(struct
amdgpu_device *adev)
adev->vcn.inst[i].ring_enc[0].funcs =
&vcn_v5_0_0_unified_ring_vm_funcs;
adev->vcn.inst[i].ring_enc[0].me = i;
-
- DRM_INFO("VCN(%d) encode/decode are enabled in VM mode\n", i);
}
}
--
2.34.1
Re: [PATCH 4/4] drm/amdgpu: prevent gpu access during reset recovery
Am 23.05.24 um 13:36 schrieb Li, Yunxiang (Teddy):
[AMD Official Use Only - AMD Internal Distribution Only]
+void amdgpu_lock_hw_access(struct amdgpu_device *adev); void
+amdgpu_unlock_hw_access(struct amdgpu_device *adev); int
+amdgpu_begin_hw_access(struct amdgpu_device *adev); void
+amdgpu_end_hw_access(struct amdgpu_device *adev);
Don't add anything to amdgpu.h. We are slowly decomposing that file.
Where would be a better place? I just wanted to have them next to
amdgpu_in_reset
amdgpu_reset.h if you have time feel free to move amdgpu_in_reset() over
there as well.
@@ -5816,6 +5816,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
goto skip_hw_reset;
}
+ amdgpu_lock_hw_access(adev);
That should already be locked here. So this will most likely deadlock.
retry:/* Rest of adevs pre asic reset from XGMI hive. */
list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
r = amdgpu_device_pre_asic_reset(tmp_adev, reset_context); @@
-5852,6 +5853,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
*/
amdgpu_device_stop_pending_resets(tmp_adev);
}
+ amdgpu_unlock_hw_access(adev);
skip_hw_reset:
Don't add helpers for that, especially not with that name.
We don't block HW access, but just prevent concurrent resets.
Here is taking a different lock than the reset_domain->sem. It is a seperate
reset_domain->gpu_sem that is only locked when we will actuall do reset, it is not
taken in the skip_hw_reset path.
Exactly that is what you should *not* do. Please don't add any new lock
to the code. This is already complicated enough.
If you think that adding wrappers for reset lock makes sense then we can
probably do that, bot don't add any lock for hw access.
uint32_t seq;
- if (!adev->gmc.flush_pasid_uses_kiq || !ring->sched.ready ||
- !down_read_trylock(&adev->reset_domain->sem)) {
+ /*
+ * A GPU reset should flush all TLBs anyway, so no need to do
+ * this while one is ongoing.
+ */
+ if (!amdgpu_begin_hw_access(adev))
+ return 0;
+ if (!adev->gmc.flush_pasid_uses_kiq || !ring->sched.ready ||
+ amdgpu_in_reset(adev)) {
That check doesn't makes sense now any more.
same here, the two checks are for different scope, although I wasn't sure if the
original check is correct or not, is there a possibility that
!adev->gmc.flush_pasid_uses_kiq and !ring->sched.ready are false but
amdgpu_in_reset(adev) is true? and to we want to take this branch when that happens?
amdgpu_in_reset() in used incorrect in quite a lot of places. It should
only be used inside the HW backend code to distinct between initial load
and reset.
All other use cases especially the ones in the IOCTL front end functions
as well as here in the midlayer which isn't used by GPU reset are incorrect.
@@ -684,12 +684,18 @@ int amdgpu_gmc_flush_gpu_tlb_pasid(struct amdgpu_device
*adev, uint16_t pasid,
struct amdgpu_ring *ring = &adev->gfx.kiq[inst].ring;
struct amdgpu_kiq *kiq = &adev->gfx.kiq[inst];
unsigned int ndw;
- signed long r;
+ signed long r = 0;
Please don't initialize local variables if it isn't necessary.
if (adev->gmc.flush_tlb_needs_extra_type_2)
adev->gmc.gmc_funcs->flush_gpu_tlb_pasid(adev, pasid,
2, all_hub,
@@ -703,46 +709,42 @@ int amdgpu_gmc_flush_gpu_tlb_pasid(struct amdgpu_device
*adev, uint16_t pasid,
adev->gmc.gmc_funcs->flush_gpu_tlb_pasid(adev, pasid,
flush_type, all_hub,
inst);
- return 0;
- }
+ } else {
That the locking is missing here should be a separate bug fix independent of
other changes.
I will split this off into a seperate patch, initializing r is needed because I
consolidated the return paths to drop the read lock.
In that case better set r when it's not initialized in some path.
Regards,
Christian.
Re: [PATCH] drm/amdgpu/pptable: Fix UBSAN array-index-out-of-bounds
On Thu, May 23, 2024 at 9:05 AM Tasos Sahanidis wrote:
>
> Dyanmically sized arrays used [1] instead of []. Replacing the former
> with the latter resolves multiple warnings observed on boot with a
> BONAIRE card.
>
> Signed-off-by: Tasos Sahanidis
> ---
> drivers/gpu/drm/amd/include/pptable.h | 24
> 1 file changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/include/pptable.h
> b/drivers/gpu/drm/amd/include/pptable.h
> index 2e8e6c9875f6..d1dec880d2d6 100644
> --- a/drivers/gpu/drm/amd/include/pptable.h
> +++ b/drivers/gpu/drm/amd/include/pptable.h
> @@ -480,7 +480,7 @@ typedef struct _StateArray{
> //how many states we have
> UCHAR ucNumEntries;
>
> -ATOM_PPLIB_STATE_V2 states[1];
> +ATOM_PPLIB_STATE_V2 states[];
Can you add __counted_by(ucNumEntries) to the end of the line? E.g.,
ATOM_PPLIB_STATE_V2 states[] __counted_by(ucNumEntries);
Same comment for the other changes below.
Alex
> }StateArray;
>
>
> @@ -514,7 +514,7 @@ typedef struct _ATOM_PPLIB_Clock_Voltage_Dependency_Record
> typedef struct _ATOM_PPLIB_Clock_Voltage_Dependency_Table
> {
> UCHAR ucNumEntries;//
> Number of entries.
> -ATOM_PPLIB_Clock_Voltage_Dependency_Record entries[1]; //
> Dynamically allocate entries.
> +ATOM_PPLIB_Clock_Voltage_Dependency_Record entries[]; //
> Dynamically allocate entries.
> }ATOM_PPLIB_Clock_Voltage_Dependency_Table;>
> typedef struct _ATOM_PPLIB_Clock_Voltage_Limit_Record
> @@ -530,7 +530,7 @@ typedef struct _ATOM_PPLIB_Clock_Voltage_Limit_Record
> typedef struct _ATOM_PPLIB_Clock_Voltage_Limit_Table
> {
> UCHAR ucNumEntries;//
> Number of entries.
> -ATOM_PPLIB_Clock_Voltage_Limit_Record entries[1]; //
> Dynamically allocate entries.
> +ATOM_PPLIB_Clock_Voltage_Limit_Record entries[]; //
> Dynamically allocate entries.
> }ATOM_PPLIB_Clock_Voltage_Limit_Table;
>
> union _ATOM_PPLIB_CAC_Leakage_Record
> @@ -554,7 +554,7 @@ typedef union _ATOM_PPLIB_CAC_Leakage_Record
> ATOM_PPLIB_CAC_Leakage_Record;
> typedef struct _ATOM_PPLIB_CAC_Leakage_Table
> {
> UCHAR ucNumEntries; //
> Number of entries.
> -ATOM_PPLIB_CAC_Leakage_Record entries[1]; //
> Dynamically allocate entries.
> +ATOM_PPLIB_CAC_Leakage_Record entries[];//
> Dynamically allocate entries.
> }ATOM_PPLIB_CAC_Leakage_Table;
>
> typedef struct _ATOM_PPLIB_PhaseSheddingLimits_Record
> @@ -569,7 +569,7 @@ typedef struct _ATOM_PPLIB_PhaseSheddingLimits_Record
> typedef struct _ATOM_PPLIB_PhaseSheddingLimits_Table
> {
> UCHAR ucNumEntries; //
> Number of entries.
> -ATOM_PPLIB_PhaseSheddingLimits_Record entries[1]; //
> Dynamically allocate entries.
> +ATOM_PPLIB_PhaseSheddingLimits_Record entries[];//
> Dynamically allocate entries.
> }ATOM_PPLIB_PhaseSheddingLimits_Table;
>
> typedef struct _VCEClockInfo{
> @@ -581,7 +581,7 @@ typedef struct _VCEClockInfo{
>
> typedef struct _VCEClockInfoArray{
> UCHAR ucNumEntries;
> -VCEClockInfo entries[1];
> +VCEClockInfo entries[];
> }VCEClockInfoArray;
>
> typedef struct _ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record
> @@ -593,7 +593,7 @@ typedef struct _ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record
> typedef struct _ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table
> {
> UCHAR numEntries;
> -ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record entries[1];
> +ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record entries[];
> }ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table;
>
> typedef struct _ATOM_PPLIB_VCE_State_Record
> @@ -605,7 +605,7 @@ typedef struct _ATOM_PPLIB_VCE_State_Record
> typedef struct _ATOM_PPLIB_VCE_State_Table
> {
> UCHAR numEntries;
> -ATOM_PPLIB_VCE_State_Record entries[1];
> +ATOM_PPLIB_VCE_State_Record entries[];
> }ATOM_PPLIB_VCE_State_Table;
>
>
> @@ -627,7 +627,7 @@ typedef struct _UVDClockInfo{
>
> typedef struct _UVDClockInfoArray{
> UCHAR ucNumEntries;
> -UVDClockInfo entries[1];
> +UVDClockInfo entries[];
> }UVDClockInfoArray;
>
> typedef struct _ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record
> @@ -639,7 +639,7 @@ typedef struct _ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record
> typedef struct _ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table
> {
> UCHAR numEntries;
> -ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record entries[1];
> +ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record entries[];
> }ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table;
>
> typedef struct _ATOM_PPLIB_UVD_Table
> @@ -676,7 +676,7 @@ typedef struct _ATOM_PPLIB_ACPClk_Voltage_Limit_Record
>
> typedef struct _ATOM_PPLIB_ACPClk_Voltage_Limit_Table{
> UCHAR numEntries;
> -ATOM_PPLIB_ACPClk_Voltage_Limit_Record entri
[PATCH 3/3] drm/amdkfd: gfx12 context save/restore trap handler fixes
Fix LDS size interpretation: 512 bytes (>= gfx12) vs 256 (< gfx12).
Ensure STATE_PRIV.BARRIER_COMPLETE cannot change after reading or
before writing. Other waves in the threadgroup may cause this field
to assert if they complete the barrier.
Do not overwrite EXCP_FLAG_PRIV.{SAVE_CONTEXT,HOST_TRAP} when
restoring this register. Both of these fields can assert while the
wavefront is running the trap handler.
Signed-off-by: Jay Cornwall
Cc: Lancelot Six
---
.../gpu/drm/amd/amdkfd/cwsr_trap_handler.h| 1191 +
.../amd/amdkfd/cwsr_trap_handler_gfx10.asm| 55 +-
2 files changed, 639 insertions(+), 607 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
index d61b2c3bd0ac..85a41e121cce 100644
--- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
+++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
@@ -678,7 +678,7 @@ static const uint32_t cwsr_trap_gfx9_hex[] = {
};
static const uint32_t cwsr_trap_nv1x_hex[] = {
- 0xbf820001, 0xbf820394,
+ 0xbf820001, 0xbf820393,
0xb0804004, 0xb978f802,
0x8a78ff78, 0x00020006,
0xb97bf803, 0x876eff78,
@@ -932,23 +932,48 @@ static const uint32_t cwsr_trap_nv1x_hex[] = {
0xbf850002, 0xbeff0380,
0xbf820001, 0xbeff03c1,
0xb97b4306, 0x877bc17b,
- 0xbf840086, 0xbf8a,
+ 0xbf840085, 0xbf8a,
0x877aff6d, 0x8000,
- 0xbf840082, 0x8f7b867b,
- 0x8f7b827b, 0xbef6037b,
- 0xb9703a05, 0x80708170,
- 0xbf0d9973, 0xbf850002,
- 0x8f708970, 0xbf820001,
- 0x8f708a70, 0xb97a1e06,
- 0x8f7a8a7a, 0x80707a70,
- 0x8070ff70, 0x0200,
- 0x8070ff70, 0x0080,
- 0xbef603ff, 0x0100,
- 0xd765, 0x000100c1,
- 0xd766, 0x000200c1,
- 0x1684, 0x907c9973,
- 0x877c817c, 0xbf06817c,
- 0xbefc0380, 0xbf850033,
+ 0xbf840081, 0x8f7b887b,
+ 0xbef6037b, 0xb9703a05,
+ 0x80708170, 0xbf0d9973,
+ 0xbf850002, 0x8f708970,
+ 0xbf820001, 0x8f708a70,
+ 0xb97a1e06, 0x8f7a8a7a,
+ 0x80707a70, 0x8070ff70,
+ 0x0200, 0x8070ff70,
+ 0x0080, 0xbef603ff,
+ 0x0100, 0xd765,
+ 0x000100c1, 0xd766,
+ 0x000200c1, 0x1684,
+ 0x907c9973, 0x877c817c,
+ 0xbf06817c, 0xbefc0380,
+ 0xbf850033, 0xb97af803,
+ 0x8a7a7aff, 0x1000,
+ 0xbf85001d, 0xd8d8,
+ 0x0100, 0xbf8c,
+ 0xbe840380, 0xd760,
+ 0x0901, 0x80048104,
+ 0xd761, 0x0901,
+ 0x80048104, 0xd762,
+ 0x0901, 0x80048104,
+ 0xd763, 0x0901,
+ 0x80048104, 0xf469003a,
+ 0xe000, 0x80709070,
+ 0xbf06a004, 0xbf84ffef,
+ 0x807cff7c, 0x0080,
+ 0xd525, 0x0001ff00,
+ 0x0080, 0xbf0a7b7c,
+ 0xbf85ffe4, 0xbf820044,
+ 0xbe8303ff, 0x0080,
+ 0xbf80, 0xbf80,
+ 0xbf80, 0xd8d8,
+ 0x0100, 0xbf8c,
+ 0xe0704000, 0x705d0100,
+ 0x807c037c, 0x80700370,
+ 0xd525, 0x0001ff00,
+ 0x0080, 0xbf0a7b7c,
+ 0xbf85fff4, 0xbf820032,
0xb97af803, 0x8a7a7aff,
0x1000, 0xbf85001d,
0xd8d8, 0x0100,
@@ -960,24 +985,45 @@ static const uint32_t cwsr_trap_nv1x_hex[] = {
0x80048104, 0xd763,
0x0901, 0x80048104,
0xf469003a, 0xe000,
- 0x80709070, 0xbf06a004,
+ 0x80709070, 0xbf06c004,
0xbf84ffef, 0x807cff7c,
- 0x0080, 0xd525,
- 0x0001ff00, 0x0080,
+ 0x0100, 0xd525,
+ 0x0001ff00, 0x0100,
0xbf0a7b7c, 0xbf85ffe4,
- 0xbf820044, 0xbe8303ff,
- 0x0080, 0xbf80,
+ 0xbf820011, 0xbe8303ff,
+ 0x0100, 0xbf80,
0xbf80, 0xbf80,
0xd8d8, 0x0100,
0xbf8c, 0xe0704000,
0x705d0100, 0x807c037c,
0x80700370, 0xd525,
- 0x0001ff00, 0x0080,
+ 0x0001ff00, 0x0100,
0xbf0a7b7c, 0xbf85fff4,
- 0xbf820032, 0xb97af803,
- 0x8a7a7aff, 0x1000,
- 0xbf85001d, 0xd8d8,
- 0x0100, 0xbf8c,
+ 0xbefe03c1, 0x907c9973,
+ 0x877c817c, 0xbf06817c,
+ 0xbf850004, 0xbef003ff,
+ 0x0200, 0xbeff0380,
+ 0xbf820003, 0xbef003ff,
+ 0x0400, 0xbeff03c1,
+ 0xb97b3a05, 0x807b817b,
+ 0x8f7b827b, 0x907c9973,
+ 0x877c817c, 0xbf06817c,
+ 0xbf85006b, 0xbef603ff,
+ 0x0100, 0xbefc0384,
+ 0xbf0a7b7c, 0xbf8400fa,
+ 0xb97af803, 0x8a7a7aff,
+ 0x1000, 0xbf850050,
+ 0x7e008700, 0x7e028701,
+ 0x7e048702, 0x7e068703,
+ 0xbe840380, 0xd760,
+ 0x0900, 0x80048104,
+ 0xd761, 0x0900,
+ 0x80048104, 0xd762,
+ 0x0900, 0x80048104,
+ 0xd763, 0x0900,
+ 0x80048104, 0xf469003a,
+ 0xe000, 0x807090
[PATCH 2/3] drm/amdkfd: Replace deprecated gfx12 trap handler instructions
Newer assemblers reject S_WAITCNT. All instances of S_WAITCNT can be
replaced by S_WAITCNT 0 (< gfx12) or S_WAIT_IDLE (>= gfx12) since
there is no concurrency of different memory instruction classes.
Signed-off-by: Jay Cornwall
Cc: Lancelot Six
---
.../gpu/drm/amd/amdkfd/cwsr_trap_handler.h| 140 +-
.../amd/amdkfd/cwsr_trap_handler_gfx10.asm| 52 +++
2 files changed, 97 insertions(+), 95 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
index 11d076eb770c..d61b2c3bd0ac 100644
--- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
+++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
@@ -711,12 +711,12 @@ static const uint32_t cwsr_trap_nv1x_hex[] = {
0xbf0d8f7b, 0xbf840002,
0x887bff7b, 0x,
0xf4011bbd, 0xfa10,
- 0xbf8cc07f, 0x8f6e976e,
+ 0xbf8c, 0x8f6e976e,
0x8a77ff77, 0x0080,
0x88776e77, 0xf4051bbd,
- 0xfa00, 0xbf8cc07f,
+ 0xfa00, 0xbf8c,
0xf4051ebd, 0xfa08,
- 0xbf8cc07f, 0x87ee6e6e,
+ 0xbf8c, 0x87ee6e6e,
0xbf840001, 0xbe80206e,
0x876eff6d, 0x00ff,
0xbf850008, 0x876eff6d,
@@ -1185,7 +1185,7 @@ static const uint32_t cwsr_trap_nv1x_hex[] = {
0x785d, 0xe0304080,
0x785d0100, 0xe0304100,
0x785d0200, 0xe0304180,
- 0x785d0300, 0xbf8c3f70,
+ 0x785d0300, 0xbf8c,
0x7e008500, 0x7e028501,
0x7e048502, 0x7e068503,
0x807c847c, 0x8078ff78,
@@ -1194,7 +1194,7 @@ static const uint32_t cwsr_trap_nv1x_hex[] = {
0x6e5d, 0xe0304080,
0x6e5d0100, 0xe0304100,
0x6e5d0200, 0xe0304180,
- 0x6e5d0300, 0xbf8c3f70,
+ 0x6e5d0300, 0xbf8c,
0xbf820034, 0xbef603ff,
0x0100, 0xbeee0378,
0x8078ff78, 0x0400,
@@ -1203,7 +1203,7 @@ static const uint32_t cwsr_trap_nv1x_hex[] = {
0x785d, 0xe0304100,
0x785d0100, 0xe0304200,
0x785d0200, 0xe0304300,
- 0x785d0300, 0xbf8c3f70,
+ 0x785d0300, 0xbf8c,
0x7e008500, 0x7e028501,
0x7e048502, 0x7e068503,
0x807c847c, 0x8078ff78,
@@ -1213,7 +1213,7 @@ static const uint32_t cwsr_trap_nv1x_hex[] = {
0x8f6f836f, 0x806f7c6f,
0xbefe03c1, 0xbeff0380,
0xe0304000, 0x785d,
- 0xbf8c3f70, 0x7e008500,
+ 0xbf8c, 0x7e008500,
0x807c817c, 0x8078ff78,
0x0080, 0xbf0a6f7c,
0xbf85fff7, 0xbeff03c1,
@@ -1221,7 +1221,7 @@ static const uint32_t cwsr_trap_nv1x_hex[] = {
0xe0304100, 0x6e5d0100,
0xe0304200, 0x6e5d0200,
0xe0304300, 0x6e5d0300,
- 0xbf8c3f70, 0xb9783a05,
+ 0xbf8c, 0xb9783a05,
0x80788178, 0xbf0d9972,
0xbf850002, 0x8f788978,
0xbf820001, 0x8f788a78,
@@ -1232,16 +1232,16 @@ static const uint32_t cwsr_trap_nv1x_hex[] = {
0x0100, 0xbefc03ff,
0x006c, 0x80f89078,
0xf429003a, 0xf000,
- 0xbf8cc07f, 0x80fc847c,
+ 0xbf8c, 0x80fc847c,
0xbf80, 0xbe803100,
0xbe823102, 0x80f8a078,
0xf42d003a, 0xf000,
- 0xbf8cc07f, 0x80fc887c,
+ 0xbf8c, 0x80fc887c,
0xbf80, 0xbe803100,
0xbe823102, 0xbe843104,
0xbe863106, 0x80f8c078,
0xf431003a, 0xf000,
- 0xbf8cc07f, 0x80fc907c,
+ 0xbf8c, 0x80fc907c,
0xbf80, 0xbe803100,
0xbe823102, 0xbe843104,
0xbe863106, 0xbe883108,
@@ -1271,9 +1271,9 @@ static const uint32_t cwsr_trap_nv1x_hex[] = {
0xf4211cfa, 0xf000,
0x80788478, 0xf4211bba,
0xf000, 0x80788478,
- 0xbf8cc07f, 0xb9eef814,
+ 0xbf8c, 0xb9eef814,
0xf4211bba, 0xf000,
- 0x80788478, 0xbf8cc07f,
+ 0x80788478, 0xbf8c,
0xb9eef815, 0xbefc036f,
0xbefe0370, 0xbeff0371,
0xb9f9f816, 0xb9fbf803,
@@ -1288,7 +1288,7 @@ static const uint32_t cwsr_trap_nv1x_hex[] = {
0x, 0xf4091c37,
0xfa50, 0xf4091d37,
0xfa60, 0xf4011e77,
- 0xfa74, 0xbf8cc07f,
+ 0xfa74, 0xbf8c,
0x906e8977, 0x876fff6e,
0x003f8000, 0x906e8677,
0x876eff6e, 0x0200,
@@ -2299,12 +2299,12 @@ static const uint32_t cwsr_trap_gfx10_hex[] = {
0xbf0d8f7b, 0xbf840002,
0x887bff7b, 0x,
0xf4011bbd, 0xfa10,
- 0xbf8cc07f, 0x8f6e976e,
+ 0xbf8c, 0x8f6e976e,
0x8a77ff77, 0x0080,
0x88776e77, 0xf4051bbd,
- 0xfa00, 0xbf8cc07f,
+ 0xfa00, 0xbf8c,
0xf4051ebd, 0xfa08,
- 0xbf8cc07f, 0x87ee6e6e,
+ 0xbf8c, 0x87ee6e6e,
0xbf840001, 0xbe80206e,
0x876eff6d, 0x00ff,
0xbf850008, 0x876eff6d,
@@ -2319,7 +2319,7 @@ static const uint32_t cwsr_trap_gfx10_hex[] = {
0x, 0xbefa0380,
0xb9fa0283, 0xbeee037e,
0xbeef037f,
[PATCH 1/3] drm/amdkfd: Sync trap handler binary with source
Source and binary have become mismatched during branch activity.
Signed-off-by: Jay Cornwall
Cc: Lancelot Six
---
.../gpu/drm/amd/amdkfd/cwsr_trap_handler.h| 57 ---
1 file changed, 24 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
index 73d3772cdb76..11d076eb770c 100644
--- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
+++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
@@ -718,12 +718,12 @@ static const uint32_t cwsr_trap_nv1x_hex[] = {
0xf4051ebd, 0xfa08,
0xbf8cc07f, 0x87ee6e6e,
0xbf840001, 0xbe80206e,
- 0x876eff6d, 0x01ff,
- 0xbf850005, 0x8878ff78,
- 0x2000, 0x80ec886c,
- 0x82ed806d, 0xbf820005,
- 0x876eff6d, 0x0100,
- 0xbf850002, 0x806c846c,
+ 0x876eff6d, 0x00ff,
+ 0xbf850008, 0x876eff6d,
+ 0x0100, 0xbf850007,
+ 0x8878ff78, 0x2000,
+ 0x80ec886c, 0x82ed806d,
+ 0xbf820002, 0x806c846c,
0x826d806d, 0x876dff6d,
0x, 0x907a8977,
0x877bff7a, 0x003f8000,
@@ -1136,7 +1136,7 @@ static const uint32_t cwsr_trap_nv1x_hex[] = {
0xe0704000, 0x705d,
0x807c817c, 0x8070ff70,
0x0080, 0xbf0a7b7c,
- 0xbf85fff8, 0xbf820144,
+ 0xbf85fff8, 0xbf82013e,
0xbef4037e, 0x8775ff7f,
0x, 0x8875ff75,
0x0004, 0xbef60380,
@@ -1276,10 +1276,7 @@ static const uint32_t cwsr_trap_nv1x_hex[] = {
0x80788478, 0xbf8cc07f,
0xb9eef815, 0xbefc036f,
0xbefe0370, 0xbeff0371,
- 0x876f7bff, 0x03ff,
- 0xb9ef4803, 0xb9f9f816,
- 0x876f7bff, 0xf800,
- 0x906f8b6f, 0xb9efa2c3,
+ 0xb9f9f816, 0xb9fbf803,
0xb9f3f801, 0xb96e3a05,
0x806e816e, 0xbf0d9972,
0xbf850002, 0x8f6e896e,
@@ -2309,12 +2306,12 @@ static const uint32_t cwsr_trap_gfx10_hex[] = {
0xf4051ebd, 0xfa08,
0xbf8cc07f, 0x87ee6e6e,
0xbf840001, 0xbe80206e,
- 0x876eff6d, 0x01ff,
- 0xbf850005, 0x8878ff78,
- 0x2000, 0x80ec886c,
- 0x82ed806d, 0xbf820005,
- 0x876eff6d, 0x0100,
- 0xbf850002, 0x806c846c,
+ 0x876eff6d, 0x00ff,
+ 0xbf850008, 0x876eff6d,
+ 0x0100, 0xbf850007,
+ 0x8878ff78, 0x2000,
+ 0x80ec886c, 0x82ed806d,
+ 0xbf820002, 0x806c846c,
0x826d806d, 0x876dff6d,
0x, 0x87fe7e7e,
0x87ea6a6a, 0xb9f8f802,
@@ -2549,7 +2546,7 @@ static const uint32_t cwsr_trap_gfx10_hex[] = {
0x705d, 0x807c817c,
0x8070ff70, 0x0080,
0xbf0a7b7c, 0xbf85fff8,
- 0xbf82013b, 0xbef4037e,
+ 0xbf820135, 0xbef4037e,
0x8775ff7f, 0x,
0x8875ff75, 0x0004,
0xbef60380, 0xbef703ff,
@@ -2688,10 +2685,7 @@ static const uint32_t cwsr_trap_gfx10_hex[] = {
0xf000, 0x80788478,
0xbf8cc07f, 0xb9eef815,
0xbefc036f, 0xbefe0370,
- 0xbeff0371, 0x876f7bff,
- 0x03ff, 0xb9ef4803,
- 0x876f7bff, 0xf800,
- 0x906f8b6f, 0xb9efa2c3,
+ 0xbeff0371, 0xb9fbf803,
0xb9f3f801, 0xb96e3a05,
0x806e816e, 0xbf0d9972,
0xbf850002, 0x8f6e896e,
@@ -2749,11 +2743,11 @@ static const uint32_t cwsr_trap_gfx11_hex[] = {
0xf808, 0xbf89fc07,
0x8bee6e6e, 0xbfa10001,
0xbe80486e, 0x8b6eff6d,
- 0x01ff, 0xbfa20005,
- 0x8c78ff78, 0x2000,
- 0x80ec886c, 0x82ed806d,
- 0xbfa5, 0x8b6eff6d,
- 0x0100, 0xbfa20002,
+ 0x00ff, 0xbfa20008,
+ 0x8b6eff6d, 0x0100,
+ 0xbfa20007, 0x8c78ff78,
+ 0x2000, 0x80ec886c,
+ 0x82ed806d, 0xbfa2,
0x806c846c, 0x826d806d,
0x8b6dff6d, 0x,
0x8bfe7e7e, 0x8bea6a6a,
@@ -2988,7 +2982,7 @@ static const uint32_t cwsr_trap_gfx11_hex[] = {
0x701d, 0x807d817d,
0x8070ff70, 0x0080,
0xbf0a7b7d, 0xbfa2fff8,
- 0xbfa00146, 0xbef4007e,
+ 0xbfa00140, 0xbef4007e,
0x8b75ff7f, 0x,
0x8c75ff75, 0x0004,
0xbef60080, 0xbef700ff,
@@ -3130,10 +3124,7 @@ static const uint32_t cwsr_trap_gfx11_hex[] = {
0xf000, 0x80788478,
0xbf89fc07, 0xb96ef815,
0xbefd006f, 0xbefe0070,
- 0xbeff0071, 0x8b6f7bff,
- 0x03ff, 0xb96f4803,
- 0x8b6f7bff, 0xf800,
- 0x856f8b6f, 0xb96fa2c3,
+ 0xbeff0071, 0xb97bf803,
0xb973f801, 0xb8ee3b05,
0x806e816e, 0xbf0d9972,
0xbfa20002, 0x846e896e,
@@ -4119,7 +4110,7 @@ static const uint32_t cwsr_trap_gfx12_hex[] = {
0x8b6dff6d, 0x,
0x8bfe7e7e, 0x8bea6a6a,
0xb97af804, 0xbe804a6c,
- 0xbfb0, 0xbf9f,
+ 0xbfb1, 0xbf9f,
0xbf9f, 0xbf9f,
0xbf9f, 0xbf9f,
};
--
2.34.1
[linux-next:master] BUILD REGRESSION 3689b0ef08b70e4e03b82ebd37730a03a672853a
tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master branch HEAD: 3689b0ef08b70e4e03b82ebd37730a03a672853a Add linux-next specific files for 20240523 Unverified Error/Warning (likely false positive, please contact us if interested): drivers/gpu/drm/xe/xe_drm_client.c:272 show_runtime() error: uninitialized symbol 'hwe'. drivers/gpu/drm/xe/xe_drm_client.c:292 show_runtime() error: uninitialized symbol 'gpu_timestamp'. Error/Warning ids grouped by kconfigs: gcc_recent_errors |-- alpha-allyesconfig | |-- drivers-gpu-drm-imx-ipuv3-imx-ldb.c:error:_sel-directive-output-may-be-truncated-writing-bytes-into-a-region-of-size-between-and | |-- drivers-gpu-drm-nouveau-nouveau_backlight.c:error:d-directive-output-may-be-truncated-writing-between-and-bytes-into-a-region-of-size | `-- drivers-regulator-rtq2208-regulator.c:warning:rtq2208_regulator_ldo_ops-defined-but-not-used |-- arc-allmodconfig | `-- drivers-regulator-rtq2208-regulator.c:warning:rtq2208_regulator_ldo_ops-defined-but-not-used |-- arc-allyesconfig | `-- drivers-regulator-rtq2208-regulator.c:warning:rtq2208_regulator_ldo_ops-defined-but-not-used |-- arc-randconfig-002-20240523 | `-- drivers-regulator-rtq2208-regulator.c:warning:rtq2208_regulator_ldo_ops-defined-but-not-used |-- arm-allmodconfig | |-- drivers-gpu-drm-imx-ipuv3-imx-ldb.c:error:_sel-directive-output-may-be-truncated-writing-bytes-into-a-region-of-size-between-and | |-- drivers-gpu-drm-nouveau-nouveau_backlight.c:error:d-directive-output-may-be-truncated-writing-between-and-bytes-into-a-region-of-size | `-- drivers-regulator-rtq2208-regulator.c:warning:rtq2208_regulator_ldo_ops-defined-but-not-used |-- arm-allyesconfig | |-- drivers-gpu-drm-imx-ipuv3-imx-ldb.c:error:_sel-directive-output-may-be-truncated-writing-bytes-into-a-region-of-size-between-and | |-- drivers-gpu-drm-nouveau-nouveau_backlight.c:error:d-directive-output-may-be-truncated-writing-between-and-bytes-into-a-region-of-size | `-- drivers-regulator-rtq2208-regulator.c:warning:rtq2208_regulator_ldo_ops-defined-but-not-used |-- arm-randconfig-004-20240523 | `-- drivers-regulator-rtq2208-regulator.c:warning:rtq2208_regulator_ldo_ops-defined-but-not-used |-- arm64-randconfig-002-20240523 | `-- drivers-regulator-rtq2208-regulator.c:warning:rtq2208_regulator_ldo_ops-defined-but-not-used |-- arm64-randconfig-004-20240523 | `-- drivers-regulator-rtq2208-regulator.c:warning:rtq2208_regulator_ldo_ops-defined-but-not-used |-- csky-allmodconfig | |-- drivers-gpu-drm-imx-ipuv3-imx-ldb.c:error:_sel-directive-output-may-be-truncated-writing-bytes-into-a-region-of-size-between-and | |-- drivers-gpu-drm-nouveau-nouveau_backlight.c:error:d-directive-output-may-be-truncated-writing-between-and-bytes-into-a-region-of-size | `-- drivers-regulator-rtq2208-regulator.c:warning:rtq2208_regulator_ldo_ops-defined-but-not-used |-- csky-allyesconfig | |-- drivers-gpu-drm-imx-ipuv3-imx-ldb.c:error:_sel-directive-output-may-be-truncated-writing-bytes-into-a-region-of-size-between-and | |-- drivers-gpu-drm-nouveau-nouveau_backlight.c:error:d-directive-output-may-be-truncated-writing-between-and-bytes-into-a-region-of-size | `-- drivers-regulator-rtq2208-regulator.c:warning:rtq2208_regulator_ldo_ops-defined-but-not-used |-- csky-randconfig-001-20240523 | `-- drivers-regulator-rtq2208-regulator.c:warning:rtq2208_regulator_ldo_ops-defined-but-not-used |-- csky-randconfig-002-20240523 | `-- drivers-regulator-rtq2208-regulator.c:warning:rtq2208_regulator_ldo_ops-defined-but-not-used |-- i386-allmodconfig | `-- drivers-regulator-rtq2208-regulator.c:warning:rtq2208_regulator_ldo_ops-defined-but-not-used |-- i386-allyesconfig | `-- drivers-regulator-rtq2208-regulator.c:warning:rtq2208_regulator_ldo_ops-defined-but-not-used |-- i386-randconfig-011-20240523 | `-- drivers-regulator-rtq2208-regulator.c:warning:rtq2208_regulator_ldo_ops-defined-but-not-used |-- i386-randconfig-014-20240523 | `-- drivers-regulator-rtq2208-regulator.c:warning:rtq2208_regulator_ldo_ops-defined-but-not-used |-- i386-randconfig-015-20240523 | `-- drivers-regulator-rtq2208-regulator.c:warning:rtq2208_regulator_ldo_ops-defined-but-not-used |-- i386-randconfig-016-20240523 | `-- drivers-regulator-rtq2208-regulator.c:warning:rtq2208_regulator_ldo_ops-defined-but-not-used |-- i386-randconfig-053-20240523 | `-- drivers-regulator-rtq2208-regulator.c:warning:rtq2208_regulator_ldo_ops-defined-but-not-used |-- i386-randconfig-054-20240523 | `-- drivers-regulator-rtq2208-regulator.c:warning:rtq2208_regulator_ldo_ops-defined-but-not-used |-- loongarch-allmodconfig | |-- drivers-gpu-drm-imx-ipuv3-imx-ldb.c:error:_sel-directive-output-may-be-truncated-writing-bytes-into-a-region-of-size-between-and | |-- drivers-gpu-drm-nouveau-nouveau_backlight.c:error:d-directive-output-may-be-truncated-writing-between-and-bytes-into-a-region-of-size | `-
Re: [PATCH v2] drm/amd/display: Enable colorspace property for MST connectors
On 2024-05-08 17:45, Mario Limonciello wrote:
MST colorspace property support was disabled due to a series of warnings
that came up when the device was plugged in since the properties weren't
made at device creation. Create the properties in advance instead.
Suggested-by: Ville Syrjälä
Fixes: 69a959610229 ("drm/amd/display: Temporary Disable MST DP Colorspace
Property").
Reported-and-tested-by: Tyler Schneider
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3353
Signed-off-by: Mario Limonciello
Reviewed-by: Harry Wentland
Harry
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 941e96f100f4..12b036d511d0 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -613,6 +613,9 @@ dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
&connector->base,
dev->mode_config.tile_property,
0);
+ connector->colorspace_property = master->base.colorspace_property;
+ if (connector->colorspace_property)
+ drm_connector_attach_colorspace_property(connector);
drm_connector_set_path_property(connector, pathprop);
RE: [PATCH 1/2] drm/amdgpu: add RAS is_rma flag
[AMD Official Use Only - AMD Internal Distribution Only]
> -Original Message-
> From: amd-gfx On Behalf Of Tao Zhou
> Sent: Thursday, May 23, 2024 6:02 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhou1, Tao
> Subject: [PATCH 1/2] drm/amdgpu: add RAS is_rma flag
>
> Set the flag to true if bad page number reaches threshold.
>
> Signed-off-by: Tao Zhou
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c| 7 +++
> drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h| 1 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 10 ++
> drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h | 3 +--
> 4 files changed, 11 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> index ecce022c657b..934dfb2bf9e5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> @@ -2940,7 +2940,6 @@ int amdgpu_ras_recovery_init(struct amdgpu_device
> *adev)
> struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
> struct ras_err_handler_data **data;
> u32 max_eeprom_records_count = 0;
> - bool exc_err_limit = false;
> int ret;
>
> if (!con || amdgpu_sriov_vf(adev))
> @@ -2977,12 +2976,12 @@ int amdgpu_ras_recovery_init(struct
> amdgpu_device *adev)
>*/
> if (adev->gmc.xgmi.pending_reset)
> return 0;
> - ret = amdgpu_ras_eeprom_init(&con->eeprom_control, &exc_err_limit);
> + ret = amdgpu_ras_eeprom_init(&con->eeprom_control);
> /*
>* This calling fails when exc_err_limit is true or
>* ret != 0.
>*/
> - if (exc_err_limit || ret)
> + if (con->is_rma || ret)
> goto free;
>
> if (con->eeprom_control.ras_num_recs) { @@ -3033,7 +3032,7 @@ int
> amdgpu_ras_recovery_init(struct amdgpu_device *adev)
>* Except error threshold exceeding case, other failure cases in this
>* function would not fail amdgpu driver init.
>*/
> - if (!exc_err_limit)
> + if (!con->is_rma)
> ret = 0;
> else
> ret = -EINVAL;
[Stanley]: Should stop device service if device is under RMA during running?
the amdgpu_ras_recovery_init function only be called during the process of
loading driver.
Regards,
Stanley
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
> index d06c01b978cd..437c58c85639 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
> @@ -521,6 +521,7 @@ struct amdgpu_ras {
> bool update_channel_flag;
> /* Record status of smu mca debug mode */
> bool is_aca_debug_mode;
> + bool is_rma;
>
> /* Record special requirements of gpu reset caller */
> uint32_t gpu_reset_flags;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
> index 9b789dcc2bd1..eae0a555df3c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
> @@ -750,6 +750,9 @@ amdgpu_ras_eeprom_update_header(struct
> amdgpu_ras_eeprom_control *control)
> control->tbl_rai.health_percent = 0;
> }
>
> + if (amdgpu_bad_page_threshold != -1)
> + ras->is_rma = true;
> +
> /* ignore the -ENOTSUPP return value */
> amdgpu_dpm_send_rma_reason(adev);
> }
> @@ -1321,8 +1324,7 @@ static int __read_table_ras_info(struct
> amdgpu_ras_eeprom_control *control)
> return res == RAS_TABLE_V2_1_INFO_SIZE ? 0 : res; }
>
> -int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control,
> -bool *exceed_err_limit)
> +int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control)
> {
> struct amdgpu_device *adev = to_amdgpu_device(control);
> unsigned char buf[RAS_TABLE_HEADER_SIZE] = { 0 }; @@ -1330,7
> +1332,7 @@ int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control
> *control,
> struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
> int res;
>
> - *exceed_err_limit = false;
> + ras->is_rma = false;
>
> if (!__is_ras_eeprom_supported(adev))
> return 0;
> @@ -1422,7 +1424,7 @@ int amdgpu_ras_eeprom_init(struct
> amdgpu_ras_eeprom_control *control,
> dev_warn(adev->dev, "GPU will be initialized
> due to bad_page_threshold = -1.");
> res = 0;
> } else {
> - *exceed_err_limit = true;
> + ras->is_rma = true;
> dev_err(adev->dev,
> "RAS records:%d exceed threshold:%d, "
> "GPU will not be initialized. Replace
> this
> GPU or increase the threshold", diff --git
> a/drivers/gpu/drm/amd/amdgpu/amdgp
Re: [PATCH V2] drm/amdgpu: fix dereference null return value for the function amdgpu_vm_pt_parent
Am 23.05.24 um 11:16 schrieb Jesse Zhang:
The pointer parent may be NULLed by the function amdgpu_vm_pt_parent.
To make the code more robust, check the pointer parent.
Signed-off-by: Jesse Zhang
Suggested-by: Christian König
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
index 0763382d305a..e39d6e7643bf 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
@@ -706,11 +706,15 @@ int amdgpu_vm_pde_update(struct amdgpu_vm_update_params
*params,
struct amdgpu_vm_bo_base *entry)
{
struct amdgpu_vm_bo_base *parent = amdgpu_vm_pt_parent(entry);
- struct amdgpu_bo *bo = parent->bo, *pbo;
+ struct amdgpu_bo *bo, *pbo;
struct amdgpu_vm *vm = params->vm;
uint64_t pde, pt, flags;
unsigned int level;
+ if (WARN_ON(!parent))
+ return -EINVAL;
+
+ bo = parent->bo;
for (level = 0, pbo = bo->parent; pbo; ++level)
pbo = pbo->parent;
Re: [RESEND 0/6] drm, nouveau/radeon/amdpgu: edid_blob_ptr cleanups
On Mon, 13 May 2024, Alex Deucher wrote: > On Mon, May 13, 2024 at 8:20 AM Jani Nikula wrote: >> >> On Fri, 10 May 2024, Alex Deucher wrote: >> > On Fri, May 10, 2024 at 11:17 AM Jani Nikula wrote: >> > Series is: >> > Acked-by: Alex Deucher >> >> Thanks, do you want to pick these up via your tree? And do you expect a >> proper R-b before merging? > > Feel free to take them via drm-misc if you'd prefer to land the whole > set together, otherwise, I can pick up the radeon/amdgpu patches. Thanks, merged everything to drm-misc-next. BR, Jani. -- Jani Nikula, Intel
Re: [PATCH v3 2/3] drm/panel/lg-sw43408: select CONFIG_DRM_DISPLAY_DP_HELPER
On 2024-05-22 09:25:54, Dmitry Baryshkov wrote:
> This panel driver uses DSC PPS functions and as such depends on the
> DRM_DISPLAY_DP_HELPER. Select this symbol to make required functions
Here and in the title: maybe this is a remnant from v2, but you split out a
DRM_DISPLAY_DSC_HELPER and shouldn't be enabling DP for a DSI panel now.
- Marijn
> available to the driver.
>
> Reported-by: kernel test robot
> Closes:
> https://lore.kernel.org/oe-kbuild-all/202404200800.kysryyli-...@intel.com/
> Fixes: 069a6c0e94f9 ("drm: panel: Add LG sw43408 panel driver")
> Signed-off-by: Dmitry Baryshkov
> ---
> drivers/gpu/drm/panel/Kconfig | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
> index 4a2f621433ef..3e3f63479544 100644
> --- a/drivers/gpu/drm/panel/Kconfig
> +++ b/drivers/gpu/drm/panel/Kconfig
> @@ -340,6 +340,8 @@ config DRM_PANEL_LG_SW43408
> depends on OF
> depends on DRM_MIPI_DSI
> depends on BACKLIGHT_CLASS_DEVICE
> + select DRM_DISPLAY_DSC_HELPER
> + select DRM_DISPLAY_HELPER
> help
> Say Y here if you want to enable support for LG sw43408 panel.
> The panel has a 1080x2160@60Hz resolution and uses 24 bit RGB per
>
> --
> 2.39.2
>
Re: 6.10/regression/bisected commit c4cb23111103 causes sleeping function called from invalid context at kernel/locking/mutex.c:585
On Tue, May 21, 2024 at 02:39:06PM +0500, Mikhail Gavrilov wrote:
> Hi,
> Yesterday on the fresh kernel snapshot
> I spotted a new bug message with follow stacktrace:
> [4.307097] BUG: sleeping function called from invalid context at
> kernel/locking/mutex.c:585
> [4.307135] in_atomic(): 1, irqs_disabled(): 1, non_block: 0, pid:
> 1, name: swapper/0
> [4.307150] preempt_count: 3, expected: 0
> [4.307159] RCU nest depth: 0, expected: 0
> [4.307168] 4 locks held by swapper/0/1:
> [4.307176] #0: 8881080ba920 (&group->mutex){+.+.}-{3:3}, at:
> bus_iommu_probe+0xf6/0x4c0
> [4.307203] #1: 88811654c1b8 (&domain->lock){}-{2:2}, at:
> amd_iommu_attach_device+0x1ad/0x1e80
> [4.307227] #2: 888113518c18 (&dev_data->lock){}-{2:2},
> at: amd_iommu_attach_device+0x213/0x1e80
> [4.307243] #3: 888108393030 (&iommu->lock){}-{2:2}, at:
> amd_iommu_iopf_add_device+0x69/0x140
> [4.307243] irq event stamp: 1021718
> [4.307243] hardirqs last enabled at (1021717):
> [] kasan_quarantine_put+0x12e/0x250
> [4.307243] hardirqs last disabled at (1021718):
> [] _raw_spin_lock_irqsave+0x7c/0xa0
> [4.307243] softirqs last enabled at (1020154):
> [] __irq_exit_rcu+0xbb/0x1c0
> [4.307243] softirqs last disabled at (1020147):
> [] __irq_exit_rcu+0xbb/0x1c0
> [4.307243] Preemption disabled at:
> [4.307243] [<>] 0x0
> [4.307243] CPU: 0 PID: 1 Comm: swapper/0 Not tainted
> 6.10.0-0.rc0.20240520giteb6a9339efeb.9.fc41.x86_64+debug #1
> [4.307243] Hardware name: ASUS System Product Name/ROG STRIX
> B650E-I GAMING WIFI, BIOS 2611 04/07/2024
> [4.307243] Call Trace:
> [4.307243]
> [4.307243] dump_stack_lvl+0x84/0xd0
> [4.307243] __might_resched.cold+0x1f7/0x23d
> [4.307243] ? __pfx___might_resched+0x10/0x10
> [4.307243] __mutex_lock+0xf3/0x13f0
> [4.307243] ? iopf_queue_add_device+0xd2/0x5d0
> [4.307243] ? __pfx___mutex_lock+0x10/0x10
> [4.307243] ? find_held_lock+0x34/0x120
> [4.307243] ? __pfx_lock_acquired+0x10/0x10
> [4.307243] ? iopf_queue_add_device+0xd2/0x5d0
> [4.307243] iopf_queue_add_device+0xd2/0x5d0
> [4.307243] amd_iommu_iopf_add_device+0xcd/0x140
> [4.307243] amd_iommu_attach_device+0xdc8/0x1e80
> [4.307243] ? iommu_create_device_direct_mappings+0x571/0x7d0
> [4.307243] __iommu_attach_device+0x64/0x250
> [4.307243] __iommu_device_set_domain+0x122/0x1c0
> [4.307243] __iommu_group_set_domain_internal+0xfa/0x2d0
> [4.307243] iommu_setup_default_domain+0x918/0xcd0
> [4.307243] bus_iommu_probe+0x1ad/0x4c0
> [4.307243] ? __pfx_bus_iommu_probe+0x10/0x10
> [4.307243] iommu_device_register+0x184/0x230
> [4.307243] ? amd_iommu_iopf_init+0xfd/0x170
> [4.307243] iommu_go_to_state+0xf87/0x3890
> [4.307243] ? __pfx_iommu_go_to_state+0x10/0x10
> [4.307243] ? lockdep_hardirqs_on+0x7c/0x100
> [4.307243] ? _raw_spin_unlock_irqrestore+0x4f/0x80
> [4.307243] ? add_device_randomness+0xb8/0xf0
> [4.307243] ? __pfx_add_device_randomness+0x10/0x10
> [4.307243] ? __pfx_pci_iommu_init+0x10/0x10
> [4.307243] amd_iommu_init+0x21/0x60
> [4.307243] ? __pfx_pci_iommu_init+0x10/0x10
> [4.307243] pci_iommu_init+0x38/0x60
> [4.307243] do_one_initcall+0xd6/0x460
> [4.307243] ? __pfx_do_one_initcall+0x10/0x10
> [4.307243] ? kernel_init_freeable+0x4cb/0x750
> [4.307243] ? kasan_unpoison+0x44/0x70
> [4.307243] kernel_init_freeable+0x6b4/0x750
> [4.307243] ? __pfx_kernel_init_freeable+0x10/0x10
> [4.307243] ? __pfx_kernel_init+0x10/0x10
> [4.307243] ? __pfx_kernel_init+0x10/0x10
> [4.307243] kernel_init+0x1c/0x150
> [4.307243] ? __pfx_kernel_init+0x10/0x10
> [4.307243] ret_from_fork+0x31/0x70
> [4.307243] ? __pfx_kernel_init+0x10/0x10
> [4.307243] ret_from_fork_asm+0x1a/0x30
> [4.307243]
>
> [4.307243] =
> [4.307243] [ BUG: Invalid wait context ]
> [4.307243] 6.10.0-0.rc0.20240520giteb6a9339efeb.9.fc41.x86_64+debug
> #1 Tainted: GW --- ---
> [4.307243] -
> [4.307243] swapper/0/1 is trying to lock:
> [4.307243] 88810de2fa88 (&queue->lock){}-{3:3}, at:
> iopf_queue_add_device+0xd2/0x5d0
> [4.307243] other info that might help us debug this:
> [4.307243] context-{4:4}
> [4.307243] 4 locks held by swapper/0/1:
> [4.307243] #0: 8881080ba920 (&group->mutex){+.+.}-{3:3}, at:
> bus_iommu_probe+0xf6/0x4c0
> [4.307243] #1: 88811654c1b8 (&domain->lock){}-{2:2}, at:
> amd_iommu_attach_device+0x1ad/0x1e80
> [4.307243] #2: 888113518c18 (&dev_data->lock){}-{2:2},
> at: amd_iommu_attach_device+0x213/0x1e80
> [4.307243] #3: 888108393030 (&iommu->lock){}-{2:2}, at:
> amd_iommu_iopf_add_device+0x69/0x140
> [4.307243] stack backtrace:
> [4.307243] CPU: 0 PID: 1 Comm:
[PATCH] drm/amdgpu/pptable: Fix UBSAN array-index-out-of-bounds
Dyanmically sized arrays used [1] instead of []. Replacing the former
with the latter resolves multiple warnings observed on boot with a
BONAIRE card.
Signed-off-by: Tasos Sahanidis
---
drivers/gpu/drm/amd/include/pptable.h | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/include/pptable.h
b/drivers/gpu/drm/amd/include/pptable.h
index 2e8e6c9875f6..d1dec880d2d6 100644
--- a/drivers/gpu/drm/amd/include/pptable.h
+++ b/drivers/gpu/drm/amd/include/pptable.h
@@ -480,7 +480,7 @@ typedef struct _StateArray{
//how many states we have
UCHAR ucNumEntries;
-ATOM_PPLIB_STATE_V2 states[1];
+ATOM_PPLIB_STATE_V2 states[];
}StateArray;
@@ -514,7 +514,7 @@ typedef struct _ATOM_PPLIB_Clock_Voltage_Dependency_Record
typedef struct _ATOM_PPLIB_Clock_Voltage_Dependency_Table
{
UCHAR ucNumEntries;//
Number of entries.
-ATOM_PPLIB_Clock_Voltage_Dependency_Record entries[1]; //
Dynamically allocate entries.
+ATOM_PPLIB_Clock_Voltage_Dependency_Record entries[]; //
Dynamically allocate entries.
}ATOM_PPLIB_Clock_Voltage_Dependency_Table;
typedef struct _ATOM_PPLIB_Clock_Voltage_Limit_Record
@@ -530,7 +530,7 @@ typedef struct _ATOM_PPLIB_Clock_Voltage_Limit_Record
typedef struct _ATOM_PPLIB_Clock_Voltage_Limit_Table
{
UCHAR ucNumEntries;//
Number of entries.
-ATOM_PPLIB_Clock_Voltage_Limit_Record entries[1]; //
Dynamically allocate entries.
+ATOM_PPLIB_Clock_Voltage_Limit_Record entries[]; //
Dynamically allocate entries.
}ATOM_PPLIB_Clock_Voltage_Limit_Table;
union _ATOM_PPLIB_CAC_Leakage_Record
@@ -554,7 +554,7 @@ typedef union _ATOM_PPLIB_CAC_Leakage_Record
ATOM_PPLIB_CAC_Leakage_Record;
typedef struct _ATOM_PPLIB_CAC_Leakage_Table
{
UCHAR ucNumEntries; //
Number of entries.
-ATOM_PPLIB_CAC_Leakage_Record entries[1]; //
Dynamically allocate entries.
+ATOM_PPLIB_CAC_Leakage_Record entries[];//
Dynamically allocate entries.
}ATOM_PPLIB_CAC_Leakage_Table;
typedef struct _ATOM_PPLIB_PhaseSheddingLimits_Record
@@ -569,7 +569,7 @@ typedef struct _ATOM_PPLIB_PhaseSheddingLimits_Record
typedef struct _ATOM_PPLIB_PhaseSheddingLimits_Table
{
UCHAR ucNumEntries; //
Number of entries.
-ATOM_PPLIB_PhaseSheddingLimits_Record entries[1]; //
Dynamically allocate entries.
+ATOM_PPLIB_PhaseSheddingLimits_Record entries[];//
Dynamically allocate entries.
}ATOM_PPLIB_PhaseSheddingLimits_Table;
typedef struct _VCEClockInfo{
@@ -581,7 +581,7 @@ typedef struct _VCEClockInfo{
typedef struct _VCEClockInfoArray{
UCHAR ucNumEntries;
-VCEClockInfo entries[1];
+VCEClockInfo entries[];
}VCEClockInfoArray;
typedef struct _ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record
@@ -593,7 +593,7 @@ typedef struct _ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record
typedef struct _ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table
{
UCHAR numEntries;
-ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record entries[1];
+ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record entries[];
}ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table;
typedef struct _ATOM_PPLIB_VCE_State_Record
@@ -605,7 +605,7 @@ typedef struct _ATOM_PPLIB_VCE_State_Record
typedef struct _ATOM_PPLIB_VCE_State_Table
{
UCHAR numEntries;
-ATOM_PPLIB_VCE_State_Record entries[1];
+ATOM_PPLIB_VCE_State_Record entries[];
}ATOM_PPLIB_VCE_State_Table;
@@ -627,7 +627,7 @@ typedef struct _UVDClockInfo{
typedef struct _UVDClockInfoArray{
UCHAR ucNumEntries;
-UVDClockInfo entries[1];
+UVDClockInfo entries[];
}UVDClockInfoArray;
typedef struct _ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record
@@ -639,7 +639,7 @@ typedef struct _ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record
typedef struct _ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table
{
UCHAR numEntries;
-ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record entries[1];
+ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record entries[];
}ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table;
typedef struct _ATOM_PPLIB_UVD_Table
@@ -676,7 +676,7 @@ typedef struct _ATOM_PPLIB_ACPClk_Voltage_Limit_Record
typedef struct _ATOM_PPLIB_ACPClk_Voltage_Limit_Table{
UCHAR numEntries;
-ATOM_PPLIB_ACPClk_Voltage_Limit_Record entries[1];
+ATOM_PPLIB_ACPClk_Voltage_Limit_Record entries[];
}ATOM_PPLIB_ACPClk_Voltage_Limit_Table;
typedef struct _ATOM_PPLIB_ACP_Table
@@ -745,7 +745,7 @@ typedef struct ATOM_PPLIB_VQ_Budgeting_Record{
typedef struct ATOM_PPLIB_VQ_Budgeting_Table {
UCHAR revid;
UCHAR numEntries;
-ATOM_PPLIB_VQ_Budgeting_Record entries[1];
+ATOM_PPLIB_VQ_Budgeting_Record entries[];
} ATOM_PPLIB_VQ_Budgeting_Tab
Re: [PATCH v2] drm/amd/display: Add pixel encoding info to debugfs
To be perfectly honest with you, I haven't given that much though. I
used the 'bpc' and 'colorspace' property in debugfs, since I could not
find that information anywhere else. And since I also needed to verify
the pixel encoding being used, I added it where those other values
were. That made for a simple and easy addition for this property.
If you want me to do this differently, let me know. And please point
me to the standardized DRM property where I should expose the values.
Rino
On Tue, May 21, 2024 at 10:55 PM Mario Limonciello
wrote:
>
> On 5/21/2024 15:06, Rino André Johnsen wrote:
> > What is already there in debugfs is 'bpc' and 'colorspace', but not
> > the pixel encoding/format.
> > I have searched high and low for that to be able to verify that my
> > monitor and computer are using my preferred combination of all those
> > three values.
> >
> > I do think it should be available as a standard DRM CRTC property, but
> > for the time being, I figured that a simple debugfs property would be
> > sufficient for time being.
> >
>
> It's just about as much work either way to populate it though, why do it
> twice instead of just doing it right the first time?
>
> > Rino
> >
> >
> > On Tue, May 21, 2024 at 9:04 PM Christian König
> > wrote:
> >>
> >> Am 21.05.24 um 07:11 schrieb Rino Andre Johnsen:
> >>> [Why]
> >>> For debugging and testing purposes.
> >>>
> >>> [How]
> >>> Create amdgpu_current_pixelencoding debugfs entry.
> >>> Usage: cat /sys/kernel/debug/dri/1/crtc-0/amdgpu_current_pixelencoding
> >>
> >> Why isn't that available as standard DRM CRTC property in either sysfs
> >> or debugfs?
> >>
> >> I think the format specifiers should already be available somewhere there.
> >>
> >> Regards,
> >> Christian.
> >>
> >>>
> >>> Signed-off-by: Rino Andre Johnsen
> >>> ---
> >>>
> >>> Changes in v2:
> >>> 1. Do not initialize dm_crtc_state to NULL.
> >>> ---
> >>>.../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 47 +++
> >>>1 file changed, 47 insertions(+)
> >>>
> >>> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
> >>> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
> >>> index 27d5c6077630..4254d4a4b56b 100644
> >>> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
> >>> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
> >>> @@ -1160,6 +1160,51 @@ static int amdgpu_current_colorspace_show(struct
> >>> seq_file *m, void *data)
> >>>}
> >>>DEFINE_SHOW_ATTRIBUTE(amdgpu_current_colorspace);
> >>>
> >>> +/*
> >>> + * Returns the current pixelencoding for the crtc.
> >>> + * Example usage: cat
> >>> /sys/kernel/debug/dri/0/crtc-0/amdgpu_current_pixelencoding
> >>> + */
> >>> +static int amdgpu_current_pixelencoding_show(struct seq_file *m, void
> >>> *data)
> >>> +{
> >>> + struct drm_crtc *crtc = m->private;
> >>> + struct drm_device *dev = crtc->dev;
> >>> + struct dm_crtc_state *dm_crtc_state;
> >>> + int res = -ENODEV;
> >>> +
> >>> + mutex_lock(&dev->mode_config.mutex);
> >>> + drm_modeset_lock(&crtc->mutex, NULL);
> >>> + if (crtc->state == NULL)
> >>> + goto unlock;
> >>> +
> >>> + dm_crtc_state = to_dm_crtc_state(crtc->state);
> >>> + if (dm_crtc_state->stream == NULL)
> >>> + goto unlock;
> >>> +
> >>> + switch (dm_crtc_state->stream->timing.pixel_encoding) {
> >>> + case PIXEL_ENCODING_RGB:
> >>> + seq_puts(m, "RGB");
> >>> + break;
> >>> + case PIXEL_ENCODING_YCBCR422:
> >>> + seq_puts(m, "YCBCR422");
> >>> + break;
> >>> + case PIXEL_ENCODING_YCBCR444:
> >>> + seq_puts(m, "YCBCR444");
> >>> + break;
> >>> + case PIXEL_ENCODING_YCBCR420:
> >>> + seq_puts(m, "YCBCR420");
> >>> + break;
> >>> + default:
> >>> + goto unlock;
> >>> + }
> >>> + res = 0;
> >>> +
> >>> +unlock:
> >>> + drm_modeset_unlock(&crtc->mutex);
> >>> + mutex_unlock(&dev->mode_config.mutex);
> >>> +
> >>> + return res;
> >>> +}
> >>> +DEFINE_SHOW_ATTRIBUTE(amdgpu_current_pixelencoding);
> >>>
> >>>/*
> >>> * Example usage:
> >>> @@ -3688,6 +3733,8 @@ void crtc_debugfs_init(struct drm_crtc *crtc)
> >>>crtc, &amdgpu_current_bpc_fops);
> >>>debugfs_create_file("amdgpu_current_colorspace", 0644,
> >>> crtc->debugfs_entry,
> >>>crtc, &amdgpu_current_colorspace_fops);
> >>> + debugfs_create_file("amdgpu_current_pixelencoding", 0644,
> >>> crtc->debugfs_entry,
> >>> + crtc, &amdgpu_current_pixelencoding_fops);
> >>>}
> >>>
> >>>/*
> >>
>
Re: [PATCH v2] drm/amd/display: Add pixel encoding info to debugfs
Looked through the patch series from Andri Yngvason and that does exactly what I wanted in the first place. I think that the patch series should be encouraged to be merged in as fast as possible. For the patch I have submitted, it stands on its own, since the patch series from Andri Yngvason does not include anything in the debugfs. This means whenever or not the patch series gets merged, at least those with an AMD gpu can figure out which pixel encoding that is used. Rino On Wed, May 22, 2024 at 3:40 PM Simon Ser wrote: > > On Wednesday, May 22nd, 2024 at 15:36, Mario Limonciello > wrote: > > > > To be perfectly honest with you, I haven't given that much though. I > > > used the 'bpc' and 'colorspace' property in debugfs, since I could not > > > find that information anywhere else. And since I also needed to verify > > > the pixel encoding being used, I added it where those other values > > > were. That made for a simple and easy addition for this property. > > > > > > If you want me to do this differently, let me know. And please point > > > me to the standardized DRM property where I should expose the values. > > FWIW, there is a patch from Andri to add a similar (?) property: > https://lore.kernel.org/dri-devel/20240115160554.720247-1-an...@yngvason.is/ > > The patch also allows user-space to set the "pixel encoding".
RE: [PATCH 4/4] drm/amdgpu: prevent gpu access during reset recovery
[AMD Official Use Only - AMD Internal Distribution Only]
> > +void amdgpu_lock_hw_access(struct amdgpu_device *adev); void
> > +amdgpu_unlock_hw_access(struct amdgpu_device *adev); int
> > +amdgpu_begin_hw_access(struct amdgpu_device *adev); void
> > +amdgpu_end_hw_access(struct amdgpu_device *adev);
>
> Don't add anything to amdgpu.h. We are slowly decomposing that file.
Where would be a better place? I just wanted to have them next to
amdgpu_in_reset
> > @@ -5816,6 +5816,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device
> > *adev,
> > goto skip_hw_reset;
> > }
> >
> > + amdgpu_lock_hw_access(adev);
>
> That should already be locked here. So this will most likely deadlock.
>
> > retry:/* Rest of adevs pre asic reset from XGMI hive. */
> > list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
> > r = amdgpu_device_pre_asic_reset(tmp_adev, reset_context); @@
> > -5852,6 +5853,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
> > */
> > amdgpu_device_stop_pending_resets(tmp_adev);
> > }
> > + amdgpu_unlock_hw_access(adev);
> >
> > skip_hw_reset:
>
> Don't add helpers for that, especially not with that name.
>
> We don't block HW access, but just prevent concurrent resets.
Here is taking a different lock than the reset_domain->sem. It is a seperate
reset_domain->gpu_sem that is only locked when we will actuall do reset, it is
not taken in the skip_hw_reset path.
> > uint32_t seq;
> >
> > - if (!adev->gmc.flush_pasid_uses_kiq || !ring->sched.ready ||
> > - !down_read_trylock(&adev->reset_domain->sem)) {
> > + /*
> > + * A GPU reset should flush all TLBs anyway, so no need to do
> > + * this while one is ongoing.
> > + */
> > + if (!amdgpu_begin_hw_access(adev))
> > + return 0;
> >
> > + if (!adev->gmc.flush_pasid_uses_kiq || !ring->sched.ready ||
> > + amdgpu_in_reset(adev)) {
>
> That check doesn't makes sense now any more.
same here, the two checks are for different scope, although I wasn't sure if
the original check is correct or not, is there a possibility that
!adev->gmc.flush_pasid_uses_kiq and !ring->sched.ready are false but
amdgpu_in_reset(adev) is true? and to we want to take this branch when that
happens?
> >
> > @@ -684,12 +684,18 @@ int amdgpu_gmc_flush_gpu_tlb_pasid(struct
> > amdgpu_device *adev, uint16_t pasid,
> > struct amdgpu_ring *ring = &adev->gfx.kiq[inst].ring;
> > struct amdgpu_kiq *kiq = &adev->gfx.kiq[inst];
> > unsigned int ndw;
> > - signed long r;
> > + signed long r = 0;
>
> Please don't initialize local variables if it isn't necessary.
>
> > if (adev->gmc.flush_tlb_needs_extra_type_2)
> > adev->gmc.gmc_funcs->flush_gpu_tlb_pasid(adev, pasid,
> > 2, all_hub,
> > @@ -703,46 +709,42 @@ int amdgpu_gmc_flush_gpu_tlb_pasid(struct
> > amdgpu_device *adev, uint16_t pasid,
> > adev->gmc.gmc_funcs->flush_gpu_tlb_pasid(adev, pasid,
> > flush_type, all_hub,
> > inst);
> > - return 0;
> > - }
> > + } else {
>
> That the locking is missing here should be a separate bug fix independent of
> other changes.
I will split this off into a seperate patch, initializing r is needed because I
consolidated the return paths to drop the read lock.
RE: [RESEND 6/6] drm/connector: update edid_blob_ptr documentation
> -Original Message-
> From: dri-devel On Behalf Of Jani
> Nikula
> Sent: Friday, May 10, 2024 8:38 PM
> To: dri-de...@lists.freedesktop.org
> Cc: amd-gfx@lists.freedesktop.org; nouv...@lists.freedesktop.org; intel-
> g...@lists.freedesktop.org; Nikula, Jani
> Subject: [RESEND 6/6] drm/connector: update edid_blob_ptr documentation
>
> Accessing the EDID via edid_blob_ptr causes chicken-and-egg problems. Keep
> edid_blob_ptr as the userspace interface that should be accessed via dedicated
> functions.
>
> Signed-off-by: Jani Nikula
LGTM
Reviewed-by: Chaitanya Kumar Borah
> ---
> include/drm/drm_connector.h | 6 +-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
> index fe88d7fc6b8f..58ee9adf9091 100644
> --- a/include/drm/drm_connector.h
> +++ b/include/drm/drm_connector.h
> @@ -1636,8 +1636,12 @@ struct drm_connector {
>
> /**
>* @edid_blob_ptr: DRM property containing EDID if present.
> Protected by
> - * &drm_mode_config.mutex. This should be updated only by calling
> + * &drm_mode_config.mutex.
> + *
> + * This must be updated only by calling drm_edid_connector_update()
> or
>* drm_connector_update_edid_property().
> + *
> + * This must not be used by drivers directly.
>*/
> struct drm_property_blob *edid_blob_ptr;
>
> --
> 2.39.2
RE: [RESEND 5/6] drm/edid: add a helper for EDID sysfs property show
> -Original Message-
> From: dri-devel On Behalf Of Jani
> Nikula
> Sent: Friday, May 10, 2024 8:38 PM
> To: dri-de...@lists.freedesktop.org
> Cc: amd-gfx@lists.freedesktop.org; nouv...@lists.freedesktop.org; intel-
> g...@lists.freedesktop.org; Nikula, Jani
> Subject: [RESEND 5/6] drm/edid: add a helper for EDID sysfs property show
>
> Add a helper to get the EDID property for sysfs property show. This hides all
> the edid_blob_ptr usage within drm_edid.c.
>
> Signed-off-by: Jani Nikula
LGTM,
Reviewed-by: Chaitanya Kumar Borah
> ---
> drivers/gpu/drm/drm_crtc_internal.h | 2 ++
> drivers/gpu/drm/drm_edid.c | 33 +
> drivers/gpu/drm/drm_sysfs.c | 24 ++---
> 3 files changed, 37 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_crtc_internal.h
> b/drivers/gpu/drm/drm_crtc_internal.h
> index 25aaae937ceb..20e9d7b206a2 100644
> --- a/drivers/gpu/drm/drm_crtc_internal.h
> +++ b/drivers/gpu/drm/drm_crtc_internal.h
> @@ -303,6 +303,8 @@ const u8 *drm_edid_find_extension(const struct
> drm_edid *drm_edid,
> int ext_id, int *ext_index);
> void drm_edid_cta_sad_get(const struct cea_sad *cta_sad, u8 *sad); void
> drm_edid_cta_sad_set(struct cea_sad *cta_sad, const u8 *sad);
> +ssize_t drm_edid_connector_property_show(struct drm_connector
> *connector,
> + char *buf, loff_t off, size_t count);
>
> /* drm_edid_load.c */
> #ifdef CONFIG_DRM_LOAD_EDID_FIRMWARE
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index
> 4f54c91b31b2..97362dd2330b 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -6969,6 +6969,39 @@ static int
> _drm_edid_connector_property_update(struct drm_connector *connector,
> return ret;
> }
>
> +/* For sysfs edid show implementation */ ssize_t
> +drm_edid_connector_property_show(struct drm_connector *connector,
> + char *buf, loff_t off, size_t count) {
> + const void *edid;
> + size_t size;
> + ssize_t ret = 0;
> +
> + mutex_lock(&connector->dev->mode_config.mutex);
> +
> + if (!connector->edid_blob_ptr)
> + goto unlock;
> +
> + edid = connector->edid_blob_ptr->data;
> + size = connector->edid_blob_ptr->length;
> + if (!edid)
> + goto unlock;
> +
> + if (off >= size)
> + goto unlock;
> +
> + if (off + count > size)
> + count = size - off;
> +
> + memcpy(buf, edid + off, count);
> +
> + ret = count;
> +unlock:
> + mutex_unlock(&connector->dev->mode_config.mutex);
> +
> + return ret;
> +}
> +
> /**
> * drm_edid_connector_update - Update connector information from EDID
> * @connector: Connector
> diff --git a/drivers/gpu/drm/drm_sysfs.c b/drivers/gpu/drm/drm_sysfs.c
> index bd9b8ab4f82b..fb3bbb6adcd1 100644
> --- a/drivers/gpu/drm/drm_sysfs.c
> +++ b/drivers/gpu/drm/drm_sysfs.c
> @@ -266,29 +266,9 @@ static ssize_t edid_show(struct file *filp, struct
> kobject *kobj, {
> struct device *connector_dev = kobj_to_dev(kobj);
> struct drm_connector *connector =
> to_drm_connector(connector_dev);
> - unsigned char *edid;
> - size_t size;
> - ssize_t ret = 0;
> + ssize_t ret;
>
> - mutex_lock(&connector->dev->mode_config.mutex);
> - if (!connector->edid_blob_ptr)
> - goto unlock;
> -
> - edid = connector->edid_blob_ptr->data;
> - size = connector->edid_blob_ptr->length;
> - if (!edid)
> - goto unlock;
> -
> - if (off >= size)
> - goto unlock;
> -
> - if (off + count > size)
> - count = size - off;
> - memcpy(buf, edid + off, count);
> -
> - ret = count;
> -unlock:
> - mutex_unlock(&connector->dev->mode_config.mutex);
> + ret = drm_edid_connector_property_show(connector, buf, off, count);
>
> return ret;
> }
> --
> 2.39.2
[PATCH 2/2] drm/amdgpu: trigger mode1 reset for RAS RMA status
Check RMA status in bad page retirement flow.
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 16 +---
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c | 7 +++
2 files changed, 16 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index 934dfb2bf9e5..a6da44ac3fbd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -2049,8 +2049,9 @@ static void
amdgpu_ras_interrupt_poison_consumption_handler(struct ras_manager *
struct amdgpu_device *adev = obj->adev;
struct amdgpu_ras_block_object *block_obj =
amdgpu_ras_get_ras_block(adev, obj->head.block, 0);
+ struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
- if (!block_obj)
+ if (!block_obj || !con)
return;
/* both query_poison_status and handle_poison_consumption are optional,
@@ -2074,7 +2075,7 @@ static void
amdgpu_ras_interrupt_poison_consumption_handler(struct ras_manager *
poison_stat =
block_obj->hw_ops->handle_poison_consumption(adev);
/* gpu reset is fallback for failed and default cases */
- if (poison_stat) {
+ if (poison_stat || con->is_rma) {
dev_info(adev->dev, "GPU reset for %s RAS poison consumption is
issued!\n",
block_obj->ras_comm.name);
amdgpu_ras_reset_gpu(adev);
@@ -2817,6 +2818,9 @@ static void amdgpu_ras_do_page_retirement(struct
work_struct *work)
schedule_delayed_work(&con->page_retirement_dwork,
msecs_to_jiffies(AMDGPU_RAS_RETIRE_PAGE_INTERVAL));
mutex_unlock(&con->umc_ecc_log.lock);
+
+ if (err_data->err_addr_cnt && con->is_rma)
+ amdgpu_ras_reset_gpu(adev);
}
static void amdgpu_ras_poison_creation_handler(struct amdgpu_device *adev,
@@ -2867,7 +2871,7 @@ static int amdgpu_ras_poison_consumption_handler(struct
amdgpu_device *adev,
if (poison_msg->pasid_fn)
poison_msg->pasid_fn(adev, pasid, poison_msg->data);
- if (reset) {
+ if (reset && !con->is_rma) {
flush_delayed_work(&con->page_retirement_dwork);
con->gpu_reset_flags |= reset;
@@ -3983,6 +3987,12 @@ int amdgpu_ras_reset_gpu(struct amdgpu_device *adev)
{
struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
+ /* mode1 is the only selection for RMA status */
+ if (ras->is_rma) {
+ ras->gpu_reset_flags = 0;
+ ras->gpu_reset_flags |= AMDGPU_RAS_GPU_RESET_MODE1_RESET;
+ }
+
if (atomic_cmpxchg(&ras->in_recovery, 0, 1) == 0)
amdgpu_reset_domain_schedule(ras->adev->reset_domain,
&ras->recovery_work);
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
index 1dbe69eabb9a..5f3866548cb8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
@@ -195,7 +195,7 @@ static int amdgpu_umc_do_page_retirement(struct
amdgpu_device *adev,
kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
amdgpu_umc_handle_bad_pages(adev, ras_error_status);
- if (err_data->ue_count && reset) {
+ if ((err_data->ue_count && (reset || con->is_rma)) {
con->gpu_reset_flags |= reset;
amdgpu_ras_reset_gpu(adev);
}
@@ -211,6 +211,7 @@ int amdgpu_umc_bad_page_polling_timeout(struct
amdgpu_device *adev,
.block = AMDGPU_RAS_BLOCK__UMC,
};
struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head);
+ struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
uint32_t timeout = timeout_ms;
memset(&err_data, 0, sizeof(err_data));
@@ -243,9 +244,7 @@ int amdgpu_umc_bad_page_polling_timeout(struct
amdgpu_device *adev,
kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
- if (reset) {
- struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
-
+ if (reset || (err_data.err_addr_cnt && con->is_rma) {
con->gpu_reset_flags |= reset;
amdgpu_ras_reset_gpu(adev);
}
--
2.34.1
[PATCH 1/2] drm/amdgpu: add RAS is_rma flag
Set the flag to true if bad page number reaches threshold.
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c| 7 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h| 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 10 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h | 3 +--
4 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index ecce022c657b..934dfb2bf9e5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -2940,7 +2940,6 @@ int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
struct ras_err_handler_data **data;
u32 max_eeprom_records_count = 0;
- bool exc_err_limit = false;
int ret;
if (!con || amdgpu_sriov_vf(adev))
@@ -2977,12 +2976,12 @@ int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
*/
if (adev->gmc.xgmi.pending_reset)
return 0;
- ret = amdgpu_ras_eeprom_init(&con->eeprom_control, &exc_err_limit);
+ ret = amdgpu_ras_eeprom_init(&con->eeprom_control);
/*
* This calling fails when exc_err_limit is true or
* ret != 0.
*/
- if (exc_err_limit || ret)
+ if (con->is_rma || ret)
goto free;
if (con->eeprom_control.ras_num_recs) {
@@ -3033,7 +3032,7 @@ int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
* Except error threshold exceeding case, other failure cases in this
* function would not fail amdgpu driver init.
*/
- if (!exc_err_limit)
+ if (!con->is_rma)
ret = 0;
else
ret = -EINVAL;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
index d06c01b978cd..437c58c85639 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
@@ -521,6 +521,7 @@ struct amdgpu_ras {
bool update_channel_flag;
/* Record status of smu mca debug mode */
bool is_aca_debug_mode;
+ bool is_rma;
/* Record special requirements of gpu reset caller */
uint32_t gpu_reset_flags;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
index 9b789dcc2bd1..eae0a555df3c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
@@ -750,6 +750,9 @@ amdgpu_ras_eeprom_update_header(struct
amdgpu_ras_eeprom_control *control)
control->tbl_rai.health_percent = 0;
}
+ if (amdgpu_bad_page_threshold != -1)
+ ras->is_rma = true;
+
/* ignore the -ENOTSUPP return value */
amdgpu_dpm_send_rma_reason(adev);
}
@@ -1321,8 +1324,7 @@ static int __read_table_ras_info(struct
amdgpu_ras_eeprom_control *control)
return res == RAS_TABLE_V2_1_INFO_SIZE ? 0 : res;
}
-int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control,
- bool *exceed_err_limit)
+int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control)
{
struct amdgpu_device *adev = to_amdgpu_device(control);
unsigned char buf[RAS_TABLE_HEADER_SIZE] = { 0 };
@@ -1330,7 +1332,7 @@ int amdgpu_ras_eeprom_init(struct
amdgpu_ras_eeprom_control *control,
struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
int res;
- *exceed_err_limit = false;
+ ras->is_rma = false;
if (!__is_ras_eeprom_supported(adev))
return 0;
@@ -1422,7 +1424,7 @@ int amdgpu_ras_eeprom_init(struct
amdgpu_ras_eeprom_control *control,
dev_warn(adev->dev, "GPU will be initialized
due to bad_page_threshold = -1.");
res = 0;
} else {
- *exceed_err_limit = true;
+ ras->is_rma = true;
dev_err(adev->dev,
"RAS records:%d exceed threshold:%d, "
"GPU will not be initialized. Replace
this GPU or increase the threshold",
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h
index 6dfd667f3013..b9ebda577797 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h
@@ -129,8 +129,7 @@ struct eeprom_table_record {
unsigned char mcumc_id;
} __packed;
-int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control,
- bool *exceed_err_limit);
+int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control);
int amdgpu_ras_eeprom_reset_table(struct am
Re: [PATCH v2 1/6] drm/ci: uprev mesa version
On Thu, 23 May 2024 at 09:07, Vignesh Raman wrote:
>
> Hi Dmitry,
>
> On 20/05/24 16:13, Dmitry Baryshkov wrote:
> > On Fri, May 17, 2024 at 02:54:57PM +0530, Vignesh Raman wrote:
> >> zlib.net is not allowing tarball download anymore and results
> >> in below error in kernel+rootfs_arm32 container build,
> >> urllib.error.HTTPError: HTTP Error 403: Forbidden
> >> urllib.error.HTTPError: HTTP Error 415: Unsupported Media Type
> >>
> >> Uprev mesa to latest version which includes a fix for this issue.
> >> https://gitlab.freedesktop.org/mesa/mesa/-/commit/908f444e
> >>
> >> Use id_tokens for JWT authentication. Since s3 bucket is migrated to
> >> mesa-rootfs, update the variables accordingly. Also copy helper scripts
> >> to install, so that the ci jobs can use these scripts for logging.
> >>
> >> Signed-off-by: Vignesh Raman
> >> ---
> >>
> >> v2:
> >>- Uprev to recent version and use id_tokens for JWT authentication
> >>
> >> ---
> >> drivers/gpu/drm/ci/build-igt.sh | 2 +-
> >> drivers/gpu/drm/ci/build.sh | 6 +++--
> >> drivers/gpu/drm/ci/container.yml | 12 +++--
> >> drivers/gpu/drm/ci/gitlab-ci.yml | 44 +--
> >> drivers/gpu/drm/ci/image-tags.yml | 2 +-
> >> drivers/gpu/drm/ci/lava-submit.sh | 4 +--
> >> drivers/gpu/drm/ci/test.yml | 2 ++
> >> 7 files changed, 44 insertions(+), 28 deletions(-)
> >>
> >
> > [skipped]
> >
> >> diff --git a/drivers/gpu/drm/ci/test.yml b/drivers/gpu/drm/ci/test.yml
> >> index 8bc63912fddb..612c9ede3507 100644
> >> --- a/drivers/gpu/drm/ci/test.yml
> >> +++ b/drivers/gpu/drm/ci/test.yml
> >> @@ -150,6 +150,8 @@ msm:sdm845:
> >> BM_KERNEL: https://${PIPELINE_ARTIFACTS_BASE}/arm64/cheza-kernel
> >> GPU_VERSION: sdm845
> >> RUNNER_TAG: google-freedreno-cheza
> >> +DEVICE_TYPE: sdm845-cheza-r3
> >> +FARM: google
> >
> > I see that this is the only user of the FARM: tag. Is it correct?
>
> No, we need to add FARM variable for other jobs as well.
Why? Even if we have to, we don't have them now and the change doesn't
seem to be related to the uprev'ing of mesa. So this probably should
go to a separate commit.
>
> > Also we miss DEVICE_TYPE for several other boards. Should we be adding
> > them?
>
> Yes, device type needs to be added for msm:apq8016, msm:apq8096, virtio_gpu.
>
> I will add this. Thanks.
I'd guess, separate commit too.
>
> Regards,
> Vignesh
>
> >
> >> script:
> >> - ./install/bare-metal/cros-servo.sh
> >>
> >> --
> >> 2.40.1
> >>
> >
--
With best wishes
Dmitry
[RFC PATCH] drm/amdgpu: Refactor sysfs attr functions in AMDGPU for reusability
This commit refactors the sysfs attribute management functions
(`amdgpu_device_attr_create`, `amdgpu_device_attr_remove`,
`amdgpu_device_attr_create_groups`, `amdgpu_device_attr_remove_groups`)
into `amdgpu_sysfs.c`, which were originally in `amdgpu_pm.c`. This
change allows these functions to be reused by other modules like gfx,
pm, etc.
Additionally, the attribute update logic is now encapsulated in the
`pm_update_sysfs_attr` function, which is located in amdgpu_pm.c. This
function is specific to the pm module and is invoked by
amdgpu_device_attr_create for each attribute before the attribute is
created.
The `amdgpu_device_attr_create_groups` function has also been updated to
use `pm_update_syfs_attr`. This ensures that the attribute update logic
is consistently applied to all attributes.
This refactoring enhances the modularity and maintainability of the
code. It also increases the reusability of the attribute management
functions, allowing them to be used by multiple modules.
Cc: Lijo Lazar
Cc: Alex Deucher
Cc: Christian König
Suggested-by: Alex Deucher
Signed-off-by: Srinivasan Shanmugam
---
drivers/gpu/drm/amd/amdgpu/Makefile | 3 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_sysfs.c | 112
drivers/gpu/drm/amd/amdgpu/amdgpu_sysfs.h | 99 ++
drivers/gpu/drm/amd/pm/amdgpu_pm.c| 150 +++---
drivers/gpu/drm/amd/pm/inc/amdgpu_pm.h| 59 -
5 files changed, 256 insertions(+), 167 deletions(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_sysfs.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_sysfs.h
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
b/drivers/gpu/drm/amd/amdgpu/Makefile
index 1f6b56ec99f6..8c782e26dfcb 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -81,7 +81,8 @@ amdgpu-y += amdgpu_device.o amdgpu_doorbell_mgr.o
amdgpu_kms.o \
amdgpu_umc.o smu_v11_0_i2c.o amdgpu_fru_eeprom.o amdgpu_rap.o \
amdgpu_fw_attestation.o amdgpu_securedisplay.o \
amdgpu_eeprom.o amdgpu_mca.o amdgpu_psp_ta.o amdgpu_lsdma.o \
- amdgpu_ring_mux.o amdgpu_xcp.o amdgpu_seq64.o amdgpu_aca.o
amdgpu_dev_coredump.o
+ amdgpu_ring_mux.o amdgpu_xcp.o amdgpu_seq64.o amdgpu_aca.o
amdgpu_dev_coredump.o \
+ amdgpu_sysfs.o
amdgpu-$(CONFIG_PROC_FS) += amdgpu_fdinfo.o
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sysfs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_sysfs.c
new file mode 100644
index ..bbdf3e8966d5
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sysfs.c
@@ -0,0 +1,112 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "amdgpu.h"
+#include "amdgpu_dpm.h"
+#include "amdgpu_drv.h"
+#include "amdgpu_reset.h"
+#include "amdgpu_sysfs.h"
+#include "atom.h"
+#include
+#include
+#include
+#include
+#include
+#include
+
+int amdgpu_sysfs_attr_create(struct amdgpu_device *adev,
+struct amdgpu_device_attr *attr,
+u32 mask, struct list_head *attr_list)
+{
+ int ret;
+ struct amdgpu_device_attr_entry *attr_entry;
+ struct device_attribute *dev_attr;
+ const char *name;
+
+ if (!attr)
+ return -EINVAL;
+
+ dev_attr = &attr->dev_attr;
+ name = dev_attr->attr.name;
+
+ ret = device_create_file(adev->dev, dev_attr);
+ if (ret) {
+ dev_err(adev->dev, "failed to create device file %s, ret =
%d\n",
+ name, ret);
+ }
+
+ attr_entry = kmalloc(sizeof(*attr_entry), GFP_KERNEL);
+ if (!attr_entry)
+ return -ENOMEM;
+
+ attr_entry->attr = attr;
+ INIT_LIST_HEAD(&attr_entry->entry);
+
+ list_add_tail(&attr_entry->entry, attr_list);
+
+ return ret;
+}
+
+int amdgpu_sysfs_attr_create_groups(struct amdgpu_de
[PATCH V2] drm/amdgpu: fix dereference null return value for the function amdgpu_vm_pt_parent
The pointer parent may be NULLed by the function amdgpu_vm_pt_parent.
To make the code more robust, check the pointer parent.
Signed-off-by: Jesse Zhang
Suggested-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
index 0763382d305a..e39d6e7643bf 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
@@ -706,11 +706,15 @@ int amdgpu_vm_pde_update(struct amdgpu_vm_update_params
*params,
struct amdgpu_vm_bo_base *entry)
{
struct amdgpu_vm_bo_base *parent = amdgpu_vm_pt_parent(entry);
- struct amdgpu_bo *bo = parent->bo, *pbo;
+ struct amdgpu_bo *bo, *pbo;
struct amdgpu_vm *vm = params->vm;
uint64_t pde, pt, flags;
unsigned int level;
+ if (WARN_ON(!parent))
+ return -EINVAL;
+
+ bo = parent->bo;
for (level = 0, pbo = bo->parent; pbo; ++level)
pbo = pbo->parent;
--
2.25.1
Re: [PATCH V2] drm/amdgpu: fix dereference null return value for the function amdgpu_vm_pt_parent
Am 23.05.24 um 10:07 schrieb Jesse Zhang:
The pointer parent may be NULLed by the function amdgpu_vm_pt_parent.
To make the code more robust, check the pointer parent.
V2: When parent is NULL here we should
probably call BUG() instead. (Christian)
Signed-off-by: Jesse Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
index 0763382d305a..6fac8440012e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
@@ -706,11 +706,17 @@ int amdgpu_vm_pde_update(struct amdgpu_vm_update_params
*params,
struct amdgpu_vm_bo_base *entry)
{
struct amdgpu_vm_bo_base *parent = amdgpu_vm_pt_parent(entry);
- struct amdgpu_bo *bo = parent->bo, *pbo;
+ struct amdgpu_bo *bo, *pbo;
struct amdgpu_vm *vm = params->vm;
uint64_t pde, pt, flags;
unsigned int level;
+ if (!parent) {
+ BUG();
+ return -EINVAL;
+ }
+ bo = parent->bo;
+
Mhm, think more about it a BUG() isn't fully justified here.
Maybe make that:
if (WARN_ON(!parent))
return -EINVAL;
Thanks,
Christian.
for (level = 0, pbo = bo->parent; pbo; ++level)
pbo = pbo->parent;
[PATCH V2] drm/amdgpu: fix dereference null return value for the function amdgpu_vm_pt_parent
The pointer parent may be NULLed by the function amdgpu_vm_pt_parent.
To make the code more robust, check the pointer parent.
V2: When parent is NULL here we should
probably call BUG() instead. (Christian)
Signed-off-by: Jesse Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
index 0763382d305a..6fac8440012e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
@@ -706,11 +706,17 @@ int amdgpu_vm_pde_update(struct amdgpu_vm_update_params
*params,
struct amdgpu_vm_bo_base *entry)
{
struct amdgpu_vm_bo_base *parent = amdgpu_vm_pt_parent(entry);
- struct amdgpu_bo *bo = parent->bo, *pbo;
+ struct amdgpu_bo *bo, *pbo;
struct amdgpu_vm *vm = params->vm;
uint64_t pde, pt, flags;
unsigned int level;
+ if (!parent) {
+ BUG();
+ return -EINVAL;
+ }
+ bo = parent->bo;
+
for (level = 0, pbo = bo->parent; pbo; ++level)
pbo = pbo->parent;
--
2.25.1
Re: [PATCH] drm/amdgpu: fix dereference null return value for the function amdgpu_vm_pt_parent
Am 23.05.24 um 08:13 schrieb Jesse Zhang:
The pointer parent may be NULLed by the function amdgpu_vm_pt_parent.
To make the code more robust, check the pointer parent.
No that doesn't make any sense.
When parent is NULL here we should probably call BUG() instead.
Regards,
Christian.
Signed-off-by: Jesse Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
index 0763382d305a..bad8d2c31202 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
@@ -706,11 +706,15 @@ int amdgpu_vm_pde_update(struct amdgpu_vm_update_params
*params,
struct amdgpu_vm_bo_base *entry)
{
struct amdgpu_vm_bo_base *parent = amdgpu_vm_pt_parent(entry);
- struct amdgpu_bo *bo = parent->bo, *pbo;
+ struct amdgpu_bo *bo, *pbo;
struct amdgpu_vm *vm = params->vm;
uint64_t pde, pt, flags;
unsigned int level;
+ if (!parent)
+ return -EINVAL;
+ bo = parent->bo;
+
for (level = 0, pbo = bo->parent; pbo; ++level)
pbo = pbo->parent;
Re: [PATCH 4/4] drm/amdgpu: prevent gpu access during reset recovery
Am 22.05.24 um 19:27 schrieb Yunxiang Li:
Random accesses to the GPU while it is not re-initialized can lead to a
bad time. So add a rwsem to prevent such accesses. Normal accesses will
now take the read lock for shared GPU access, reset takes the write lock
for exclusive GPU access.
Care need to be taken so that the recovery thread does not take the read
lock and deadlock itself, and normal access should avoid waiting on the
reset to finish and should instead treat the hardware access as failed.
Signed-off-by: Yunxiang Li
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 5 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 22 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 74 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h | 1 +
drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c | 7 +-
drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c | 7 +-
.../drm/amd/amdkfd/kfd_device_queue_manager.c | 3 +-
.../amd/amdkfd/kfd_process_queue_manager.c| 8 +-
9 files changed, 79 insertions(+), 49 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 1f71c7b98d77..5a089e2dec2a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1632,6 +1632,11 @@ static inline bool amdgpu_is_tmz(struct amdgpu_device
*adev)
int amdgpu_in_reset(struct amdgpu_device *adev);
+void amdgpu_lock_hw_access(struct amdgpu_device *adev);
+void amdgpu_unlock_hw_access(struct amdgpu_device *adev);
+int amdgpu_begin_hw_access(struct amdgpu_device *adev);
+void amdgpu_end_hw_access(struct amdgpu_device *adev);
+
Don't add anything to amdgpu.h. We are slowly decomposing that file.
extern const struct attribute_group amdgpu_vram_mgr_attr_group;
extern const struct attribute_group amdgpu_gtt_mgr_attr_group;
extern const struct attribute_group amdgpu_flash_attr_group;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index e74789691070..057d735c7cae 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -5816,6 +5816,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
goto skip_hw_reset;
}
+ amdgpu_lock_hw_access(adev);
That should already be locked here. So this will most likely deadlock.
retry:/* Rest of adevs pre asic reset from XGMI hive. */
list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
r = amdgpu_device_pre_asic_reset(tmp_adev, reset_context);
@@ -5852,6 +5853,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
*/
amdgpu_device_stop_pending_resets(tmp_adev);
}
+ amdgpu_unlock_hw_access(adev);
skip_hw_reset:
@@ -6449,6 +6451,26 @@ int amdgpu_in_reset(struct amdgpu_device *adev)
return atomic_read(&adev->reset_domain->in_gpu_reset);
}
+void amdgpu_lock_hw_access(struct amdgpu_device *adev)
+{
+ down_write(&adev->reset_domain->gpu_sem);
+}
+
+void amdgpu_unlock_hw_access(struct amdgpu_device *adev)
+{
+ up_write(&adev->reset_domain->gpu_sem);
+}
+
+int amdgpu_begin_hw_access(struct amdgpu_device *adev)
+{
+ return down_read_trylock(&adev->reset_domain->gpu_sem);
+}
+
+void amdgpu_end_hw_access(struct amdgpu_device *adev)
+{
+ up_read(&adev->reset_domain->gpu_sem);
+}
+
Don't add helpers for that, especially not with that name.
We don't block HW access, but just prevent concurrent resets.
/**
* amdgpu_device_halt() - bring hardware to some kind of halt state
*
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index 603c0738fd03..098755db9d20 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
@@ -623,12 +623,11 @@ void amdgpu_gmc_flush_gpu_tlb(struct amdgpu_device *adev,
uint32_t vmid,
!adev->mman.buffer_funcs_enabled ||
!adev->ib_pool_ready || amdgpu_in_reset(adev) ||
!ring->sched.ready) {
-
/*
* A GPU reset should flush all TLBs anyway, so no need to do
* this while one is ongoing.
*/
- if (!down_read_trylock(&adev->reset_domain->sem))
+ if (!amdgpu_begin_hw_access(adev))
return;
if (adev->gmc.flush_tlb_needs_extra_type_2)
@@ -641,7 +640,8 @@ void amdgpu_gmc_flush_gpu_tlb(struct amdgpu_device *adev,
uint32_t vmid,
adev->gmc.gmc_funcs->flush_gpu_tlb(adev, vmid, vmhub,
flush_type);
- up_read(&adev->reset_domain->sem);
+
+ amdgpu_end_hw_access(adev);
return;
}
@@ -684,12 +684,18 @@ int amdgpu_gmc_flush_gpu_tlb_pasid(struct amdgpu_device *adev, uint16_t pasid,
