RE: High Power Consumption of AMD RX6800xt in Idle with Secondary Monitor Connected
[AMD Official Use Only - AMD Internal Distribution Only] The two high resolution panels have different timings so it's needed to be fixed to high memory clock level. @Li, Humphrey to further comment. Thanks. -Original Message- From: Jaroslav Pulchart Sent: Tuesday, July 2, 2024 12:20 PM To: Feng, Kenneth Cc: Alex Deucher ; amd-gfx@lists.freedesktop.org Subject: Re: High Power Consumption of AMD RX6800xt in Idle with Secondary Monitor Connected Caution: This message originated from an External Source. Use proper caution when opening attachments, clicking links, or responding. Hi, Yes, they are 4k monitors. Any reason for such and expected boost for them? BTW: I try to increase blanking periods for both monitors without any change. Jaroslav P. > > [AMD Official Use Only - AMD Internal Distribution Only] > > Hi Jaroslav, > Are both of your monitors 4K resolution? > Then most likely the memory clock is expected to be boosted. > Thanks. > > > -Original Message- > From: amd-gfx On Behalf Of > Alex Deucher > Sent: Monday, July 1, 2024 11:07 PM > To: Jaroslav Pulchart > Cc: amd-gfx@lists.freedesktop.org > Subject: Re: High Power Consumption of AMD RX6800xt in Idle with > Secondary Monitor Connected > > Caution: This message originated from an External Source. Use proper caution > when opening attachments, clicking links, or responding. > > > On Mon, Jul 1, 2024 at 3:25 AM Jaroslav Pulchart > wrote: > > > > Dear AMD GPU Kernel Maintainers, > > > > I am writing to report an issue with high power consumption of my > > AMD RX6800xt graphics card when a secondary monitor is connected. > > > > Upon investigation, I observed that my desktop computer generates > > more heat while idling. I determined that the high power consumption > > issue arises when I connect a secondary monitor to my AMD RX6800xt > > card, causing it to consume approximately 40W of power in idle state . > > > > I checked the "GFX Clocks and Power:" in > > /sys/kernel/debug/dri/1/amdgpu_pm_info of my RX6800xt during idle, > > and here are the findings: > > > > With the secondary monitor connected memory frequency is up and > > constantly at 1000MHz: > > 1000 MHz (MCLK) > > 3 MHz (SCLK) > > 1825 MHz (PSTATE_SCLK) > > 1000 MHz (PSTATE_MCLK) > > 856 mV (VDDGFX) > > 45.00 W (average SoC) > > > > Single monitor connected: > > 96 MHz (MCLK) > > 0 MHz (SCLK) > > 1825 MHz (PSTATE_SCLK) > > 1000 MHz (PSTATE_MCLK) > > 6 mV (VDDGFX) > > 8.00 W (average SoC) > > > > The significant difference in power consumption between the two > > states indicates a potential issue in power management that needs to > > be addressed. Your assistance in resolving this matter would be > > greatly appreciated. > > It depends on the timing of the monitors. The memory reclocking can only > occur during blanking periods on the monitors. If the reclocking is done > outside of the blanking periods, you will see flickering or artifacts on the > display when it happens. If the blanking periods are too short the driver > can only downclock memory when the displays are off. Adding more monitors > makes this harder as you have to take into account the blanking periods on > all monitors. You can try adjusting the modelines used on each display to > increase the blanking periods. > > Alex
RE: High Power Consumption of AMD RX6800xt in Idle with Secondary Monitor Connected
[AMD Official Use Only - AMD Internal Distribution Only] Hi Jaroslav, Are both of your monitors 4K resolution? Then most likely the memory clock is expected to be boosted. Thanks. -Original Message- From: amd-gfx On Behalf Of Alex Deucher Sent: Monday, July 1, 2024 11:07 PM To: Jaroslav Pulchart Cc: amd-gfx@lists.freedesktop.org Subject: Re: High Power Consumption of AMD RX6800xt in Idle with Secondary Monitor Connected Caution: This message originated from an External Source. Use proper caution when opening attachments, clicking links, or responding. On Mon, Jul 1, 2024 at 3:25 AM Jaroslav Pulchart wrote: > > Dear AMD GPU Kernel Maintainers, > > I am writing to report an issue with high power consumption of my AMD > RX6800xt graphics card when a secondary monitor is connected. > > Upon investigation, I observed that my desktop computer generates more > heat while idling. I determined that the high power consumption issue > arises when I connect a secondary monitor to my AMD RX6800xt card, > causing it to consume approximately 40W of power in idle state . > > I checked the "GFX Clocks and Power:" in > /sys/kernel/debug/dri/1/amdgpu_pm_info of my RX6800xt during idle, and > here are the findings: > > With the secondary monitor connected memory frequency is up and > constantly at 1000MHz: > 1000 MHz (MCLK) > 3 MHz (SCLK) > 1825 MHz (PSTATE_SCLK) > 1000 MHz (PSTATE_MCLK) > 856 mV (VDDGFX) > 45.00 W (average SoC) > > Single monitor connected: > 96 MHz (MCLK) > 0 MHz (SCLK) > 1825 MHz (PSTATE_SCLK) > 1000 MHz (PSTATE_MCLK) > 6 mV (VDDGFX) > 8.00 W (average SoC) > > The significant difference in power consumption between the two states > indicates a potential issue in power management that needs to be > addressed. Your assistance in resolving this matter would be greatly > appreciated. It depends on the timing of the monitors. The memory reclocking can only occur during blanking periods on the monitors. If the reclocking is done outside of the blanking periods, you will see flickering or artifacts on the display when it happens. If the blanking periods are too short the driver can only downclock memory when the displays are off. Adding more monitors makes this harder as you have to take into account the blanking periods on all monitors. You can try adjusting the modelines used on each display to increase the blanking periods. Alex
RE: [PATCH v2] drm/amd/swsmu: enable more Pstates profile levels for SMU v14.0.0 and v14.0.1
[AMD Official Use Only - AMD Internal Distribution Only] Hi Li, > -Original Message- > From: Ma, Li > Sent: Monday, July 1, 2024 9:14 PM > To: Huang, Tim ; amd-gfx@lists.freedesktop.org > Cc: Deucher, Alexander ; Zhang, Yifan > > Subject: RE: [PATCH v2] drm/amd/swsmu: enable more Pstates profile levels > for SMU v14.0.0 and v14.0.1 > > [AMD Official Use Only - AMD Internal Distribution Only] > > Hi Tim, > > > -Original Message- > > From: Huang, Tim > > Sent: Monday, July 1, 2024 7:32 PM > > To: Ma, Li ; amd-gfx@lists.freedesktop.org > > Cc: Deucher, Alexander ; Zhang, Yifan > > > > Subject: RE: [PATCH v2] drm/amd/swsmu: enable more Pstates profile > > levels for SMU v14.0.0 and v14.0.1 > > > > [AMD Official Use Only - AMD Internal Distribution Only] > > > > Hi Li, > > > > > -Original Message- > > > From: Ma, Li > > > Sent: Monday, July 1, 2024 6:44 PM > > > To: amd-gfx@lists.freedesktop.org > > > Cc: Deucher, Alexander ; Zhang, Yifan > > > ; Huang, Tim ; Ma, Li > > > > > > Subject: [PATCH v2] drm/amd/swsmu: enable more Pstates profile > > > levels for SMU v14.0.0 and v14.0.1 > > > > > > This patch enables following UMD stable Pstates profile levels for > > > power_dpm_force_performance_level interface. > > > > > > - profile_peak > > > - profile_min_mclk > > > - profile_min_sclk > > > - profile_standard > > > > > > Signed-off-by: Li Ma > > > --- > > > .../drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c | 138 > > > +- > > > 1 file changed, 131 insertions(+), 7 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c > > > b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c > > > index 3a9d58c036ea..72fca481dec1 100644 > > > --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c > > > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c > > > @@ -65,6 +65,10 @@ > > > > > > #define SMU_MALL_PG_CONFIG_DEFAULT > > > SMU_MALL_PG_CONFIG_DRIVER_CONTROL_ALWAYS_ON > > > > > > +#define SMU_14_0_0_UMD_PSTATE_GFXCLK 700 > > > +#define SMU_14_0_0_UMD_PSTATE_SOCCLK 678 > > > +#define SMU_14_0_0_UMD_PSTATE_FCLK 1800 > > > + > > > #define FEATURE_MASK(feature) (1ULL << feature) #define > > > SMC_DPM_FEATURE ( \ > > > FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \ @@ -818,9 +822,11 > @@ > > > static int smu_v14_0_1_get_dpm_ultimate_freq(struct smu_context *smu, > > > break; > > > case SMU_MCLK: > > > case SMU_UCLK: > > > - case SMU_FCLK: > > > max_dpm_level = 0; > > > break; > > > + case SMU_FCLK: > > > + max_dpm_level = > clk_table->NumFclkLevelsEnabled - 1; > > > + break; > > > case SMU_SOCCLK: > > > max_dpm_level = > clk_table->NumSocClkLevelsEnabled - 1; > > > break; > > > @@ -855,7 +861,7 @@ static int > > > smu_v14_0_1_get_dpm_ultimate_freq(struct smu_context *smu, > > > min_dpm_level = > clk_table->NumMemPstatesEnabled - 1; > > > break; > > > case SMU_FCLK: > > > - min_dpm_level = > clk_table->NumFclkLevelsEnabled - 1; > > > + min_dpm_level = 0; > > > break; > > > case SMU_SOCCLK: > > > min_dpm_level = 0; @@ -936,9 +942,11 @@ > static > > > int smu_v14_0_0_get_dpm_ultimate_freq(struct smu_context *smu, > > > break; > > > case SMU_MCLK: > > > case SMU_UCLK: > > > - case SMU_FCLK: > > > max_dpm_level = 0; > > > break; > > > + case SMU_FCLK: > > > + max_dpm_level = > clk_table->NumFclkLevelsEnabled - 1; > > > + break; > > > case SMU_SOCCLK: > > > max_dpm_level = > clk_table->NumSocClkLevelsEnabled - 1; > > > break; > > > @@ -969,7 +977,7 @@ static int > > > smu_v14_0_0_get_dpm_ultimate_freq(struct smu_context *smu, > > > min_dpm_level = > clk_table->NumMemPstatesEnabled - 1; > > > break; > > > case SMU_FCLK: > > > - min_dpm_level = > clk_table->NumFclkLevelsEnabled - 1; > > > + min_dpm_level = 0; > > > break; > > > case SMU_SOCCLK: > > > min_dpm_level = 0; @@ -1268,13 +1276,67 > @@ > > > static int smu_v14_0_0_force_clk_levels(struct > > > smu_context *smu, > > > return ret; > > > } > > > > > > -static int smu_v14_0_0_set_performance_level(struct smu_context > > > *smu, > > > +static int smu_v14_0_common_get_dpm_profile_freq(struct smu_context > > > *smu, > > > + enum amd_dpm_forced_level > level, > > > +
[PATCH] drm/amdgpu/gfx12: properly handle error ints on all pipes
Need to handle the interrupt enables for all pipes.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 130 -
1 file changed, 106 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
index af98fd0f32a7..4e761d166ef5 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
@@ -1496,26 +1496,68 @@ static void gfx_v12_0_constants_init(struct
amdgpu_device *adev)
gfx_v12_0_init_compute_vmid(adev);
}
+static u32 gfx_v12_0_get_cpg_int_cntl(struct amdgpu_device *adev,
+ int me, int pipe)
+{
+ if (me != 0)
+ return 0;
+
+ switch (pipe) {
+ case 0:
+ return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0);
+ default:
+ return 0;
+ }
+}
+
+static u32 gfx_v12_0_get_cpc_int_cntl(struct amdgpu_device *adev,
+ int me, int pipe)
+{
+ /*
+* amdgpu controls only the first MEC. That's why this function only
+* handles the setting of interrupts for this specific MEC. All other
+* pipes' interrupts are set by amdkfd.
+*/
+ if (me != 1)
+ return 0;
+
+ switch (pipe) {
+ case 0:
+ return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL);
+ case 1:
+ return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL);
+ default:
+ return 0;
+ }
+}
+
static void gfx_v12_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
- bool enable)
+ bool enable)
{
- u32 tmp;
+ u32 tmp, cp_int_cntl_reg;
+ int i, j;
if (amdgpu_sriov_vf(adev))
return;
- tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL_RING0);
-
- tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
- enable ? 1 : 0);
- tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
- enable ? 1 : 0);
- tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
- enable ? 1 : 0);
- tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
- enable ? 1 : 0);
-
- WREG32_SOC15(GC, 0, regCP_INT_CNTL_RING0, tmp);
+ for (i = 0; i < adev->gfx.me.num_me; i++) {
+ for (i = 0; i < adev->gfx.me.num_pipe_per_me; i++) {
+ cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i,
j);
+
+ if (cp_int_cntl_reg) {
+ tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
+ tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0,
CNTX_BUSY_INT_ENABLE,
+ enable ? 1 : 0);
+ tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0,
CNTX_EMPTY_INT_ENABLE,
+ enable ? 1 : 0);
+ tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0,
CMP_BUSY_INT_ENABLE,
+ enable ? 1 : 0);
+ tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0,
GFX_IDLE_INT_ENABLE,
+ enable ? 1 : 0);
+ WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp);
+ }
+ }
+ }
}
static int gfx_v12_0_init_csb(struct amdgpu_device *adev)
@@ -4584,15 +4626,42 @@ static int gfx_v12_0_eop_irq(struct amdgpu_device *adev,
static int gfx_v12_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
struct amdgpu_irq_src *source,
- unsigned type,
+ unsigned int type,
enum amdgpu_interrupt_state state)
{
+ u32 cp_int_cntl_reg, cp_int_cntl;
+ int i, j;
+
switch (state) {
case AMDGPU_IRQ_STATE_DISABLE:
case AMDGPU_IRQ_STATE_ENABLE:
- WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0,
- PRIV_REG_INT_ENABLE,
- state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
+ for (i = 0; i < adev->gfx.me.num_me; i++) {
+ for (i = 0; i < adev->gfx.me.num_pipe_per_me; i++) {
+ cp_int_cntl_reg =
gfx_v12_0_get_cpg_int_cntl(adev, i, j);
+
+ if (cp_int_cntl_reg) {
+ cp_int_cntl = RREG32_SOC15_IP(GC,
cp_int_cntl_reg);
+ cp_int_cntl =
REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
+
[PATCH 3/3] Reapply "drm/amdgpu/gfx11: enable gfx pipe1 hardware support"
This reverts commit 28ebbdd7677d84d6d25ccff40ea6e9f01c2c8c7d. Let's see if this works with the gfx pipe1 interrupts fixed. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index fcf31483ed25..91adfa1aa1f7 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -50,7 +50,7 @@ #include "nbio_v4_3.h" #include "mes_v11_0.h" -#define GFX11_NUM_GFX_RINGS1 +#define GFX11_NUM_GFX_RINGS2 #define GFX11_MEC_HPD_SIZE 2048 #define RLCG_UCODE_LOADING_START_ADDRESS 0x2000L @@ -1524,7 +1524,7 @@ static int gfx_v11_0_sw_init(void *handle) case IP_VERSION(11, 0, 2): case IP_VERSION(11, 0, 3): adev->gfx.me.num_me = 1; - adev->gfx.me.num_pipe_per_me = 1; + adev->gfx.me.num_pipe_per_me = 2; adev->gfx.me.num_queue_per_pipe = 1; adev->gfx.mec.num_mec = 2; adev->gfx.mec.num_pipe_per_mec = 4; @@ -1535,7 +1535,7 @@ static int gfx_v11_0_sw_init(void *handle) case IP_VERSION(11, 5, 0): case IP_VERSION(11, 5, 1): adev->gfx.me.num_me = 1; - adev->gfx.me.num_pipe_per_me = 1; + adev->gfx.me.num_pipe_per_me = 2; adev->gfx.me.num_queue_per_pipe = 1; adev->gfx.mec.num_mec = 1; adev->gfx.mec.num_pipe_per_mec = 4; -- 2.45.2
[PATCH 2/3] drm/amdgpu/gfx11: properly handle error ints on all pipes
Need to handle the interrupt enables for all pipes.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 134 -
1 file changed, 111 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 6d285556892b..fcf31483ed25 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -1947,26 +1947,74 @@ static void gfx_v11_0_constants_init(struct
amdgpu_device *adev)
gfx_v11_0_init_gds_vmid(adev);
}
+static u32 gfx_v11_0_get_cpg_int_cntl(struct amdgpu_device *adev,
+ int me, int pipe)
+{
+ if (me != 0)
+ return 0;
+
+ switch (pipe) {
+ case 0:
+ return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0);
+ case 1:
+ return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING1);
+ default:
+ return 0;
+ }
+}
+
+static u32 gfx_v11_0_get_cpc_int_cntl(struct amdgpu_device *adev,
+ int me, int pipe)
+{
+ /*
+* amdgpu controls only the first MEC. That's why this function only
+* handles the setting of interrupts for this specific MEC. All other
+* pipes' interrupts are set by amdkfd.
+*/
+ if (me != 1)
+ return 0;
+
+ switch (pipe) {
+ case 0:
+ return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL);
+ case 1:
+ return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL);
+ case 2:
+ return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE2_INT_CNTL);
+ case 3:
+ return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE3_INT_CNTL);
+ default:
+ return 0;
+ }
+}
+
static void gfx_v11_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
bool enable)
{
- u32 tmp;
+ u32 tmp, cp_int_cntl_reg;
+ int i, j;
if (amdgpu_sriov_vf(adev))
return;
- tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL_RING0);
-
- tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
- enable ? 1 : 0);
- tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
- enable ? 1 : 0);
- tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
- enable ? 1 : 0);
- tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
- enable ? 1 : 0);
-
- WREG32_SOC15(GC, 0, regCP_INT_CNTL_RING0, tmp);
+ for (i = 0; i < adev->gfx.me.num_me; i++) {
+ for (i = 0; i < adev->gfx.me.num_pipe_per_me; i++) {
+ cp_int_cntl_reg = gfx_v11_0_get_cpg_int_cntl(adev, i,
j);
+
+ if (cp_int_cntl_reg) {
+ tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
+ tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0,
CNTX_BUSY_INT_ENABLE,
+ enable ? 1 : 0);
+ tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0,
CNTX_EMPTY_INT_ENABLE,
+ enable ? 1 : 0);
+ tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0,
CMP_BUSY_INT_ENABLE,
+ enable ? 1 : 0);
+ tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0,
GFX_IDLE_INT_ENABLE,
+ enable ? 1 : 0);
+ WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp);
+ }
+ }
+ }
}
static int gfx_v11_0_init_csb(struct amdgpu_device *adev)
@@ -6199,15 +6247,42 @@ static int gfx_v11_0_eop_irq(struct amdgpu_device *adev,
static int gfx_v11_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
struct amdgpu_irq_src *source,
- unsigned type,
+ unsigned int type,
enum amdgpu_interrupt_state state)
{
+ u32 cp_int_cntl_reg, cp_int_cntl;
+ int i, j;
+
switch (state) {
case AMDGPU_IRQ_STATE_DISABLE:
case AMDGPU_IRQ_STATE_ENABLE:
- WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0,
- PRIV_REG_INT_ENABLE,
- state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
+ for (i = 0; i < adev->gfx.me.num_me; i++) {
+ for (i = 0; i < adev->gfx.me.num_pipe_per_me; i++) {
+ cp_int_cntl_reg =
gfx_v11_0_get_cpg_int_cntl(adev, i, j);
+
+ if (cp_int_cntl_reg) {
+
[PATCH 1/3] drm/amdgpu/gfx10: properly handle error ints on all pipes
Need to handle the interrupt enables for all pipes.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 130 +
1 file changed, 109 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 6c3fa707e20b..eb74e1975cab 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -5269,26 +5269,74 @@ static void gfx_v10_0_constants_init(struct
amdgpu_device *adev)
}
+static u32 gfx_v10_0_get_cpg_int_cntl(struct amdgpu_device *adev,
+ int me, int pipe)
+{
+ if (me != 0)
+ return 0;
+
+ switch (pipe) {
+ case 0:
+ return SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
+ case 1:
+ return SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
+ default:
+ return 0;
+ }
+}
+
+static u32 gfx_v10_0_get_cpc_int_cntl(struct amdgpu_device *adev,
+ int me, int pipe)
+{
+ /*
+* amdgpu controls only the first MEC. That's why this function only
+* handles the setting of interrupts for this specific MEC. All other
+* pipes' interrupts are set by amdkfd.
+*/
+ if (me != 1)
+ return 0;
+
+ switch (pipe) {
+ case 0:
+ return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
+ case 1:
+ return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
+ case 2:
+ return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
+ case 3:
+ return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
+ default:
+ return 0;
+ }
+}
+
static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
bool enable)
{
- u32 tmp;
+ u32 tmp, cp_int_cntl_reg;
+ int i, j;
if (amdgpu_sriov_vf(adev))
return;
- tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
-
- tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
- enable ? 1 : 0);
- tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
- enable ? 1 : 0);
- tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
- enable ? 1 : 0);
- tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
- enable ? 1 : 0);
-
- WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
+ for (i = 0; i < adev->gfx.me.num_me; i++) {
+ for (i = 0; i < adev->gfx.me.num_pipe_per_me; i++) {
+ cp_int_cntl_reg = gfx_v10_0_get_cpg_int_cntl(adev, i,
j);
+
+ if (cp_int_cntl_reg) {
+ tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
+ tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0,
CNTX_BUSY_INT_ENABLE,
+ enable ? 1 : 0);
+ tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0,
CNTX_EMPTY_INT_ENABLE,
+ enable ? 1 : 0);
+ tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0,
CMP_BUSY_INT_ENABLE,
+ enable ? 1 : 0);
+ tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0,
GFX_IDLE_INT_ENABLE,
+ enable ? 1 : 0);
+ WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp);
+ }
+ }
+ }
}
static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
@@ -9134,12 +9182,39 @@ static int gfx_v10_0_set_priv_reg_fault_state(struct
amdgpu_device *adev,
unsigned int type,
enum amdgpu_interrupt_state state)
{
+ u32 cp_int_cntl_reg, cp_int_cntl;
+ int i, j;
+
switch (state) {
case AMDGPU_IRQ_STATE_DISABLE:
case AMDGPU_IRQ_STATE_ENABLE:
- WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
- PRIV_REG_INT_ENABLE,
- state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
+ for (i = 0; i < adev->gfx.me.num_me; i++) {
+ for (i = 0; i < adev->gfx.me.num_pipe_per_me; i++) {
+ cp_int_cntl_reg =
gfx_v10_0_get_cpg_int_cntl(adev, i, j);
+
+ if (cp_int_cntl_reg) {
+ cp_int_cntl = RREG32_SOC15_IP(GC,
cp_int_cntl_reg);
+ cp_int_cntl =
REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
+
Re: [PATCH 4/4] drm/amd/display: Fix warning comparing pointer to 0
Applied the series. Thanks!
Alex
On Mon, Jul 1, 2024 at 3:15 AM Jiapeng Chong
wrote:
>
> Avoid pointer type value compared with 0 to make code clear.
>
> ./drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_factory.c:14:12-13:
> WARNING comparing pointer to 0.
>
> Reported-by: Abaci Robot
> Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=9458
> Signed-off-by: Jiapeng Chong
> ---
> .../amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_factory.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git
> a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_factory.c
> b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_factory.c
> index 1a0da8c6df5a..f56abe9ab919 100644
> ---
> a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_factory.c
> +++
> b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_factory.c
> @@ -11,7 +11,7 @@ bool dml2_core_create(enum dml2_project_id project_id,
> struct dml2_core_instance
> {
> bool result = false;
>
> - if (out == 0)
> + if (!out)
> return false;
>
> memset(out, 0, sizeof(struct dml2_core_instance));
> --
> 2.20.1.7.g153144c
>
Re: [PATCH] drm/amd/display: Fix unsigned comparison with less than zero
Applied. Thanks!
On Sun, Jun 30, 2024 at 11:10 PM Jiapeng Chong
wrote:
>
> The return value from the call to dml21_find_dc_pipes_for_plane() is int.
> However, the return value is being assigned to an unsigned int variable
> 'num_pipes', the condition if(num_pipes <= 0) is not rigorous enough,
> so making 'num_pipes' an int.
>
> ./drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c:318:6-15:
> WARNING: Unsigned expression compared with zero: num_pipes <= 0.
> ./drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c:360:6-15:
> WARNING: Unsigned expression compared with zero: num_pipes <= 0.
>
> Reported-by: Abaci Robot
> Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=9454
> Signed-off-by: Jiapeng Chong
> ---
> .../drm/amd/display/dc/dml2/dml21/dml21_wrapper.c | 15 ++-
> 1 file changed, 6 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c
> b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c
> index c310354cd5fc..9d96a31419fa 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c
> +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c
> @@ -280,7 +280,8 @@ bool dml21_validate(const struct dc *in_dc, struct
> dc_state *context, struct dml
>
> void dml21_prepare_mcache_programming(struct dc *in_dc, struct dc_state
> *context, struct dml2_context *dml_ctx)
> {
> - unsigned int num_pipes, dml_prog_idx, dml_phantom_prog_idx,
> dc_pipe_index;
> + unsigned int dml_prog_idx, dml_phantom_prog_idx, dc_pipe_index;
> + int num_pipes;
> struct pipe_ctx *dc_main_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__];
> struct pipe_ctx
> *dc_phantom_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__] = {0};
>
> @@ -314,10 +315,8 @@ void dml21_prepare_mcache_programming(struct dc *in_dc,
> struct dc_state *context
> }
>
> num_pipes = dml21_find_dc_pipes_for_plane(in_dc, context,
> dml_ctx, dc_main_pipes, dc_phantom_pipes, dml_prog_idx);
> -
> - if (num_pipes <= 0 ||
> - dc_main_pipes[0]->stream == NULL ||
> - dc_main_pipes[0]->plane_state == NULL)
> + if (num_pipes <= 0 || dc_main_pipes[0]->stream == NULL ||
> + dc_main_pipes[0]->plane_state == NULL)
> continue;
>
> /* get config for each pipe */
> @@ -356,10 +355,8 @@ void dml21_prepare_mcache_programming(struct dc *in_dc,
> struct dc_state *context
> pln_prog =
> _ctx->v21.mode_programming.programming->plane_programming[dml_prog_idx];
>
> num_pipes = dml21_find_dc_pipes_for_plane(in_dc, context,
> dml_ctx, dc_main_pipes, dc_phantom_pipes, dml_prog_idx);
> -
> - if (num_pipes <= 0 ||
> - dc_main_pipes[0]->stream == NULL ||
> - dc_main_pipes[0]->plane_state == NULL)
> + if (num_pipes <= 0 || dc_main_pipes[0]->stream == NULL ||
> + dc_main_pipes[0]->plane_state == NULL)
> continue;
>
> /* get config for each pipe */
> --
> 2.20.1.7.g153144c
>
Re: [PATCH v3 2/2] drm/amd: Add power_saving_policy drm property to eDP connectors
Am Do., 20. Juni 2024 um 22:22 Uhr schrieb Xaver Hugl : > Merging can only happen once a real world userspace application has > implemented support for it. I'll try to do that sometime next week in > KWin Here's the promised implementation: https://invent.kde.org/plasma/kwin/-/merge_requests/6028 In testing with the patches on top of kernel 6.9.6, setting the property to `Require color accuracy` makes the sysfs file correctly report "Device or resource busy" when trying to change the power saving level, but setting the property to zero doesn't really work. Once KWin sets the property to zero, changing the power saving level "works" but the screen blanks for a moment (might just be a single frame) and reading from the file returns zero again, with the visuals and backlight level unchanged as well.
Re: [PATCH] drm/amdgpu/atomfirmware: silence UBSAN warning
On Mon, 2024-07-01 at 12:55 -0400, Alex Deucher wrote:
> This is a variably sized array.
>
> Link:
> https://lists.freedesktop.org/archives/amd-gfx/2024-June/110420.html
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/include/atomfirmware.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h
> b/drivers/gpu/drm/amd/include/atomfirmware.h
> index 571691837200..09cbc3afd6d8 100644
> --- a/drivers/gpu/drm/amd/include/atomfirmware.h
> +++ b/drivers/gpu/drm/amd/include/atomfirmware.h
> @@ -734,7 +734,7 @@ struct atom_gpio_pin_lut_v2_1
> {
> struct atom_common_table_header table_header;
> /*the real number of this included in the structure is calcualted
> by using the (whole structure size - the header size)/size of
> atom_gpio_pin_lut */
> - struct atom_gpio_pin_assignment gpio_pin[8];
> + struct atom_gpio_pin_assignment gpio_pin[];
> };
>
>
Works for me:
Tested-by: Jeff Layton
Re: [PATCH v3 2/2] drm/amd: Add power_saving_policy drm property to eDP connectors
On 7/1/2024 13:47, Xaver Hugl wrote: Am Do., 20. Juni 2024 um 22:22 Uhr schrieb Xaver Hugl : Merging can only happen once a real world userspace application has implemented support for it. I'll try to do that sometime next week in KWin Here's the promised implementation: https://invent.kde.org/plasma/kwin/-/merge_requests/6028 Thanks! In testing with the patches on top of kernel 6.9.6, setting the property to `Require color accuracy` makes the sysfs file correctly report "Device or resource busy" when trying to change the power saving level, but setting the property to zero doesn't really work. Once KWin sets the property to zero, changing the power saving level "works" but the screen blanks for a moment (might just be a single frame) and reading from the file returns zero again, with the visuals and backlight level unchanged as well. Hmm I'm a bit surprised the IGT tests I did didn't catch this. Are you working on a system with two GPUs by chance (like a Framework 16)? If so; can you try the "other GPU"? As it seems your PR to span 3 projects and I've never built KDE before can you spit out some artifacts somewhere that I can have a play with to reproduce your result and find the kernel issue? Arch pkgs would be preferable for me, but some RPMs or DEBs are fine too.
Re: [PATCH] drm/amdgpu: restore dcc bo tilling configs while moving
[Public]
Reviewed-by: Alex Deucher
From: Min, Frank
Sent: Sunday, June 30, 2024 11:17 PM
To: Deucher, Alexander ; Olsak, Marek
; Koenig, Christian ; Zhang,
Hawking ; Gao, Likun ;
amd-gfx@lists.freedesktop.org
Subject: [PATCH] drm/amdgpu: restore dcc bo tilling configs while moving
[AMD Official Use Only - AMD Internal Distribution Only]
From: Frank Min
While moving buffer which as dcc tiling config, it is needed to restore its
original dcc tiling.
1. extend copy flag to cover tiling bits
2. add logic to restore original dcc tiling config
Signed-off-by: Frank Min
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 17 ++---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 11 +++
drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c | 10 --
3 files changed, 33 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 9a92dd3c9fb8..dd4aed47af1e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -308,7 +308,8 @@ int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
mutex_lock(>mman.gtt_window_lock);
while (src_mm.remaining) {
- uint64_t from, to, cur_size;
+ uint64_t from, to, cur_size, tiling_flags;
+ uint32_t num_type, data_format, max_com;
struct dma_fence *next;
/* Never copy more than 256MiB at once to avoid a timeout */ @@
-329,10 +330,20 @@ int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
abo_dst = ttm_to_amdgpu_bo(dst->bo);
if (tmz)
copy_flags |= AMDGPU_COPY_FLAGS_TMZ;
- if (abo_src->flags & AMDGPU_GEM_CREATE_GFX12_DCC)
+ if ((abo_src->flags & AMDGPU_GEM_CREATE_GFX12_DCC) &&
+ (abo_src->tbo.resource->mem_type == TTM_PL_VRAM))
copy_flags |= AMDGPU_COPY_FLAGS_READ_DECOMPRESSED;
- if (abo_dst->flags & AMDGPU_GEM_CREATE_GFX12_DCC)
+ if ((abo_dst->flags & AMDGPU_GEM_CREATE_GFX12_DCC) &&
+ (dst->mem->mem_type == TTM_PL_VRAM)) {
copy_flags |= AMDGPU_COPY_FLAGS_WRITE_COMPRESSED;
+ amdgpu_bo_get_tiling_flags(abo_dst, _flags);
+ max_com = AMDGPU_TILING_GET(tiling_flags,
GFX12_DCC_MAX_COMPRESSED_BLOCK);
+ num_type = AMDGPU_TILING_GET(tiling_flags,
GFX12_DCC_NUMBER_TYPE);
+ data_format = AMDGPU_TILING_GET(tiling_flags,
GFX12_DCC_DATA_FORMAT);
+ copy_flags |= (AMDGPU_COPY_FLAGS_SET(MAX_COMPRESSED,
max_com) |
+ AMDGPU_COPY_FLAGS_SET(NUMBER_TYPE,
num_type) |
+ AMDGPU_COPY_FLAGS_SET(DATA_FORMAT,
data_format));
+ }
r = amdgpu_copy_buffer(ring, from, to, cur_size, resv,
, false, true, copy_flags); diff
--git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
index 7c903a6c9ddb..8d34e8588dc2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
@@ -114,6 +114,17 @@ struct amdgpu_copy_mem {
#define AMDGPU_COPY_FLAGS_TMZ (1 << 0)
#define AMDGPU_COPY_FLAGS_READ_DECOMPRESSED(1 << 1)
#define AMDGPU_COPY_FLAGS_WRITE_COMPRESSED (1 << 2)
+#define AMDGPU_COPY_FLAGS_MAX_COMPRESSED_SHIFT 3
+#define AMDGPU_COPY_FLAGS_MAX_COMPRESSED_MASK 0x03
+#define AMDGPU_COPY_FLAGS_NUMBER_TYPE_SHIFT5
+#define AMDGPU_COPY_FLAGS_NUMBER_TYPE_MASK 0x07
+#define AMDGPU_COPY_FLAGS_DATA_FORMAT_SHIFT8
+#define AMDGPU_COPY_FLAGS_DATA_FORMAT_MASK 0x3f
+
+#define AMDGPU_COPY_FLAGS_SET(field, value) \
+ (((__u32)(value) & AMDGPU_COPY_FLAGS_##field##_MASK) <<
+AMDGPU_COPY_FLAGS_##field##_SHIFT)
+#define AMDGPU_COPY_FLAGS_GET(value, field) \
+ (((__u32)(value) >> AMDGPU_COPY_FLAGS_##field##_SHIFT) &
+AMDGPU_COPY_FLAGS_##field##_MASK)
int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uint64_t gtt_size); void
amdgpu_gtt_mgr_fini(struct amdgpu_device *adev); diff --git
a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
index 96514fd77e35..41b5e45697dc 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
@@ -1566,6 +1566,12 @@ static void sdma_v7_0_emit_copy_buffer(struct amdgpu_ib
*ib,
uint32_t byte_count,
uint32_t copy_flags)
{
+ uint32_t num_type, data_format, max_com;
+
+ max_com = AMDGPU_COPY_FLAGS_GET(copy_flags, MAX_COMPRESSED);
+ data_format = AMDGPU_COPY_FLAGS_GET(copy_flags, DATA_FORMAT);
+ num_type = AMDGPU_COPY_FLAGS_GET(copy_flags, NUMBER_TYPE);
+
Re: [PATCH 3/3] drm/amdgpu: add firmware for SDMA IP v6.1.2
[Public]
Series is:
Reviewed-by: Alex Deucher
From: Huang, Tim
Sent: Sunday, June 30, 2024 10:45 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Zhang, Yifan
; Huang, Tim ; Zhang, Yifan
Subject: [PATCH 3/3] drm/amdgpu: add firmware for SDMA IP v6.1.2
This patch is to add firmware for SDMA 6.1.2.
Signed-off-by: Tim Huang
Reviewed-by: Yifan Zhang
---
drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
index c833b6b8373b..dab4c2db8c9d 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
@@ -50,6 +50,7 @@ MODULE_FIRMWARE("amdgpu/sdma_6_0_2.bin");
MODULE_FIRMWARE("amdgpu/sdma_6_0_3.bin");
MODULE_FIRMWARE("amdgpu/sdma_6_1_0.bin");
MODULE_FIRMWARE("amdgpu/sdma_6_1_1.bin");
+MODULE_FIRMWARE("amdgpu/sdma_6_1_2.bin");
#define SDMA1_REG_OFFSET 0x600
#define SDMA0_HYP_DEC_REG_START 0x5880
--
2.43.0
Re: [PATCH] drm/amd/pm: avoid to load smu firmware for APUs
[Public]
Reviewed-by: Alex Deucher
From: Huang, Tim
Sent: Sunday, June 30, 2024 11:45 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Zhang, Yifan
; Huang, Tim
Subject: [PATCH] drm/amd/pm: avoid to load smu firmware for APUs
Certain call paths still load the SMU firmware for APUs,
which needs to be skipped.
Signed-off-by: Tim Huang
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 8 +++-
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 8 +++-
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 8 +++-
drivers/gpu/drm/amd/pm/amdgpu_dpm.c| 2 +-
4 files changed, 10 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 18488c02d1cf..c55518fe542c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -7324,11 +7324,9 @@ static int gfx_v10_0_hw_init(void *handle)
* loaded firstly, so in direct type, it has to load smc ucode
* here before rlc.
*/
- if (!(adev->flags & AMD_IS_APU)) {
- r = amdgpu_pm_load_smu_firmware(adev, NULL);
- if (r)
- return r;
- }
+ r = amdgpu_pm_load_smu_firmware(adev, NULL);
+ if (r)
+ return r;
gfx_v10_0_disable_gpa_mode(adev);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 38150398a31b..0ad35e96d2b8 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -4558,11 +4558,9 @@ static int gfx_v11_0_hw_init(void *handle)
* loaded firstly, so in direct type, it has to load smc ucode
* here before rlc.
*/
- if (!(adev->flags & AMD_IS_APU)) {
- r = amdgpu_pm_load_smu_firmware(adev, NULL);
- if (r)
- return r;
- }
+ r = amdgpu_pm_load_smu_firmware(adev, NULL);
+ if (r)
+ return r;
}
gfx_v11_0_constants_init(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
index ccb26f78252a..40edda2c3003 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
@@ -3306,11 +3306,9 @@ static int gfx_v12_0_hw_init(void *handle)
* loaded firstly, so in direct type, it has to load smc ucode
* here before rlc.
*/
- if (!(adev->flags & AMD_IS_APU)) {
- r = amdgpu_pm_load_smu_firmware(adev, NULL);
- if (r)
- return r;
- }
+ r = amdgpu_pm_load_smu_firmware(adev, NULL);
+ if (r)
+ return r;
}
gfx_v12_0_constants_init(adev);
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
index b3b5e7b74c85..a1b8a82d77cf 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
@@ -618,7 +618,7 @@ int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev,
uint32_t *smu_versio
const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
int r = 0;
- if (!pp_funcs || !pp_funcs->load_firmware)
+ if (!pp_funcs || !pp_funcs->load_firmware || adev->flags & AMD_IS_APU)
return 0;
mutex_lock(>pm.mutex);
--
2.43.0
Re: [PATCH 7/7] drm/amdgpu: add firmware for PSP IP v14.0.4
[AMD Official Use Only - AMD Internal Distribution Only]
Series is:
Reviewed-by: Alex Deucher
From: Huang, Tim
Sent: Sunday, June 30, 2024 10:58 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Zhang, Yifan
; Huang, Tim ; Zhang, Yifan
Subject: [PATCH 7/7] drm/amdgpu: add firmware for PSP IP v14.0.4
This patch is to add firmware for PSP 14.0.4.
Signed-off-by: Tim Huang
Reviewed-by: Yifan Zhang
---
drivers/gpu/drm/amd/amdgpu/psp_v13_0.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
index 407477b895d1..1251ee38a676 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
@@ -57,6 +57,8 @@ MODULE_FIRMWARE("amdgpu/psp_14_0_0_toc.bin");
MODULE_FIRMWARE("amdgpu/psp_14_0_0_ta.bin");
MODULE_FIRMWARE("amdgpu/psp_14_0_1_toc.bin");
MODULE_FIRMWARE("amdgpu/psp_14_0_1_ta.bin");
+MODULE_FIRMWARE("amdgpu/psp_14_0_4_toc.bin");
+MODULE_FIRMWARE("amdgpu/psp_14_0_4_ta.bin");
/* For large FW files the time to complete can be very long */
#define USBC_PD_POLLING_LIMIT_S 240
--
2.43.0
Re: [PATCH 3/3] drm/amdgpu: add firmware for VPE IP v6.1.3
[Public]
Series is:
Reviewed-by: Alex Deucher
From: Huang, Tim
Sent: Sunday, June 30, 2024 10:50 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Zhang, Yifan
; Huang, Tim ; Zhang, Yifan
Subject: [PATCH 3/3] drm/amdgpu: add firmware for VPE IP v6.1.3
This patch is to add firmware for VPE 6.1.3.
Signed-off-by: Tim Huang
Reviewed-by: Yifan Zhang
---
drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c
b/drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c
index 09315dd5a1ec..45876883bbf3 100644
--- a/drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c
@@ -34,6 +34,7 @@
MODULE_FIRMWARE("amdgpu/vpe_6_1_0.bin");
MODULE_FIRMWARE("amdgpu/vpe_6_1_1.bin");
+MODULE_FIRMWARE("amdgpu/vpe_6_1_3.bin");
#define VPE_THREAD1_UCODE_OFFSET0x8000
--
2.43.0
Re: [PATCH 2/2] drm/amdgpu: Add NBIO IP v7.11.3 support
[Public] Series is: Reviewed-by: Alex Deucher From: Huang, Tim Sent: Sunday, June 30, 2024 10:48 AM To: amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander ; Zhang, Yifan ; Huang, Tim ; Zhang, Yifan Subject: [PATCH 2/2] drm/amdgpu: Add NBIO IP v7.11.3 support Enable setting soc21 common clockgating for NBIO 7.11.3. Signed-off-by: Tim Huang Reviewed-by: Yifan Zhang --- drivers/gpu/drm/amd/amdgpu/soc21.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c index b04c763015d3..b43c50f1c7ad 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc21.c +++ b/drivers/gpu/drm/amd/amdgpu/soc21.c @@ -953,6 +953,7 @@ static int soc21_common_set_clockgating_state(void *handle, case IP_VERSION(7, 7, 1): case IP_VERSION(7, 11, 0): case IP_VERSION(7, 11, 1): + case IP_VERSION(7, 11, 3): adev->nbio.funcs->update_medium_grain_clock_gating(adev, state == AMD_CG_STATE_GATE); adev->nbio.funcs->update_medium_grain_light_sleep(adev, -- 2.43.0
Re: [PATCH 7/7] drm/amdgpu: add firmware for GC IP v11.5.2
[Public]
Series is:
Reviewed-by: Alex Deucher
From: Huang, Tim
Sent: Sunday, June 30, 2024 10:38 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Zhang, Yifan
; Huang, Tim ; Zhang, Yifan
Subject: [PATCH 7/7] drm/amdgpu: add firmware for GC IP v11.5.2
This patch is to add firmware for GC 11.5.2.
Signed-off-by: Tim Huang
Reviewed-by: Yifan Zhang
---
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 4
drivers/gpu/drm/amd/amdgpu/imu_v11_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 2 ++
3 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 9acdabd7719a..38150398a31b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -93,6 +93,10 @@ MODULE_FIRMWARE("amdgpu/gc_11_5_1_pfp.bin");
MODULE_FIRMWARE("amdgpu/gc_11_5_1_me.bin");
MODULE_FIRMWARE("amdgpu/gc_11_5_1_mec.bin");
MODULE_FIRMWARE("amdgpu/gc_11_5_1_rlc.bin");
+MODULE_FIRMWARE("amdgpu/gc_11_5_2_pfp.bin");
+MODULE_FIRMWARE("amdgpu/gc_11_5_2_me.bin");
+MODULE_FIRMWARE("amdgpu/gc_11_5_2_mec.bin");
+MODULE_FIRMWARE("amdgpu/gc_11_5_2_rlc.bin");
static const struct amdgpu_hwip_reg_entry gc_reg_list_11_0[] = {
SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS),
diff --git a/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c
index a9f5d9e4610d..6c1891889c4d 100644
--- a/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c
@@ -38,6 +38,7 @@ MODULE_FIRMWARE("amdgpu/gc_11_0_3_imu.bin");
MODULE_FIRMWARE("amdgpu/gc_11_0_4_imu.bin");
MODULE_FIRMWARE("amdgpu/gc_11_5_0_imu.bin");
MODULE_FIRMWARE("amdgpu/gc_11_5_1_imu.bin");
+MODULE_FIRMWARE("amdgpu/gc_11_5_2_imu.bin");
static int imu_v11_0_init_microcode(struct amdgpu_device *adev)
{
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
index 3b1f6ad99100..1376b6ff1b77 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
@@ -51,6 +51,8 @@ MODULE_FIRMWARE("amdgpu/gc_11_5_0_mes_2.bin");
MODULE_FIRMWARE("amdgpu/gc_11_5_0_mes1.bin");
MODULE_FIRMWARE("amdgpu/gc_11_5_1_mes_2.bin");
MODULE_FIRMWARE("amdgpu/gc_11_5_1_mes1.bin");
+MODULE_FIRMWARE("amdgpu/gc_11_5_2_mes_2.bin");
+MODULE_FIRMWARE("amdgpu/gc_11_5_2_mes1.bin");
static int mes_v11_0_hw_init(void *handle);
static int mes_v11_0_hw_fini(void *handle);
--
2.43.0
[PATCH 1/4] drm/scheduler: implement hardware time accounting
From: Christian König
Multiple drivers came up with the requirement to measure how
much runtime each entity accumulated on the HW.
A previous attempt of accounting this had to be reverted because
HW submissions can have a lifetime exceeding that of the entity
originally issuing them.
Amdgpu on the other hand solves this task by keeping track of
all the submissions and calculating how much time they have used
on demand.
Move this approach over into the scheduler to provide an easy to
use interface for all drivers.
Signed-off-by: Christian König
Signed-off-by: Lucas Stach
---
v2:
- rebase to v6.10-rc1
- fix for non-power-of-two number of HW submission
- add comment explaining the logic behind the fence tracking array
- rename some function and fix documentation
---
drivers/gpu/drm/scheduler/sched_entity.c | 82 +++-
drivers/gpu/drm/scheduler/sched_fence.c | 19 ++
include/drm/gpu_scheduler.h | 31 +
3 files changed, 131 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/scheduler/sched_entity.c
b/drivers/gpu/drm/scheduler/sched_entity.c
index 58c8161289fe..d678d0b9b29e 100644
--- a/drivers/gpu/drm/scheduler/sched_entity.c
+++ b/drivers/gpu/drm/scheduler/sched_entity.c
@@ -62,7 +62,9 @@ int drm_sched_entity_init(struct drm_sched_entity *entity,
unsigned int num_sched_list,
atomic_t *guilty)
{
- if (!(entity && sched_list && (num_sched_list == 0 || sched_list[0])))
+ unsigned int i, num_submissions = 0;
+
+ if (!entity || !sched_list)
return -EINVAL;
memset(entity, 0, sizeof(struct drm_sched_entity));
@@ -98,6 +100,11 @@ int drm_sched_entity_init(struct drm_sched_entity *entity,
(s32)
DRM_SCHED_PRIORITY_KERNEL);
}
entity->rq = sched_list[0]->sched_rq[entity->priority];
+
+ for (i = 0; i < num_sched_list; ++i) {
+ num_submissions = max(num_submissions,
+ sched_list[i]->credit_limit);
+ }
}
init_completion(>entity_idle);
@@ -110,11 +117,52 @@ int drm_sched_entity_init(struct drm_sched_entity *entity,
atomic_set(>fence_seq, 0);
entity->fence_context = dma_fence_context_alloc(2);
+ spin_lock_init(>accounting_lock);
+
+ if (!num_submissions)
+ return 0;
+
+ entity->max_hw_submissions = num_submissions;
+ entity->hw_submissions = kcalloc(num_submissions, sizeof(void *),
+GFP_KERNEL);
+ if (!entity->hw_submissions)
+ return -ENOMEM;
return 0;
}
EXPORT_SYMBOL(drm_sched_entity_init);
+/**
+ * drm_sched_entity_time_spent - Accumulated HW runtime used by this entity
+ * @entity: scheduler entity to check
+ *
+ * Get the current accumulated HW runtime used by all submissions made through
+ * this entity.
+ */
+ktime_t drm_sched_entity_time_spent(struct drm_sched_entity *entity)
+{
+ ktime_t result;
+ unsigned int i;
+
+ if (!entity->max_hw_submissions)
+ return ns_to_ktime(0);
+
+ spin_lock(>accounting_lock);
+ result = entity->hw_time_used;
+ for (i = 0; i < entity->max_hw_submissions; ++i) {
+ struct drm_sched_fence *fence = entity->hw_submissions[i];
+
+ if (!fence)
+ continue;
+
+ result = ktime_add(result, drm_sched_fence_get_runtime(fence));
+ }
+ spin_unlock(>accounting_lock);
+
+ return result;
+}
+EXPORT_SYMBOL(drm_sched_entity_time_spent);
+
/**
* drm_sched_entity_modify_sched - Modify sched of an entity
* @entity: scheduler entity to init
@@ -326,6 +374,8 @@ EXPORT_SYMBOL(drm_sched_entity_flush);
*/
void drm_sched_entity_fini(struct drm_sched_entity *entity)
{
+ unsigned int i;
+
/*
* If consumption of existing IBs wasn't completed. Forcefully remove
* them here. Also makes sure that the scheduler won't touch this entity
@@ -341,6 +391,9 @@ void drm_sched_entity_fini(struct drm_sched_entity *entity)
dma_fence_put(rcu_dereference_check(entity->last_scheduled, true));
RCU_INIT_POINTER(entity->last_scheduled, NULL);
+ for (i = 0; i < entity->max_hw_submissions; ++i)
+ dma_fence_put(>hw_submissions[i]->scheduled);
+ kfree(entity->hw_submissions);
}
EXPORT_SYMBOL(drm_sched_entity_fini);
@@ -522,6 +575,33 @@ struct drm_sched_job *drm_sched_entity_pop_job(struct
drm_sched_entity *entity)
*/
sched_job->entity = NULL;
+ if (entity->max_hw_submissions) {
+ struct drm_sched_fence *fence = sched_job->s_fence;
+ unsigned int idx = fence->scheduled.seqno;
+
+ dma_fence_get(>scheduled);
+ idx %= entity->max_hw_submissions;
+
+
[PATCH 3/4] drm/amdgpu: use new scheduler accounting
From: Christian König
Instead of implementing this ourself.
Signed-off-by: Christian König
Signed-off-by: Lucas Stach
---
v2:
- rebased to v6.10-rc1
- adapted to match new function names
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 52 -
1 file changed, 8 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index 56f2428813e8..392f51e0b2e9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -166,41 +166,6 @@ static unsigned int amdgpu_ctx_get_hw_prio(struct
amdgpu_ctx *ctx, u32 hw_ip)
return hw_prio;
}
-/* Calculate the time spend on the hw */
-static ktime_t amdgpu_ctx_fence_time(struct dma_fence *fence)
-{
- struct drm_sched_fence *s_fence;
-
- if (!fence)
- return ns_to_ktime(0);
-
- /* When the fence is not even scheduled it can't have spend time */
- s_fence = to_drm_sched_fence(fence);
- if (!test_bit(DMA_FENCE_FLAG_TIMESTAMP_BIT, _fence->scheduled.flags))
- return ns_to_ktime(0);
-
- /* When it is still running account how much already spend */
- if (!test_bit(DMA_FENCE_FLAG_TIMESTAMP_BIT, _fence->finished.flags))
- return ktime_sub(ktime_get(), s_fence->scheduled.timestamp);
-
- return ktime_sub(s_fence->finished.timestamp,
-s_fence->scheduled.timestamp);
-}
-
-static ktime_t amdgpu_ctx_entity_time(struct amdgpu_ctx *ctx,
- struct amdgpu_ctx_entity *centity)
-{
- ktime_t res = ns_to_ktime(0);
- uint32_t i;
-
- spin_lock(>ring_lock);
- for (i = 0; i < amdgpu_sched_jobs; i++) {
- res = ktime_add(res, amdgpu_ctx_fence_time(centity->fences[i]));
- }
- spin_unlock(>ring_lock);
- return res;
-}
-
static int amdgpu_ctx_init_entity(struct amdgpu_ctx *ctx, u32 hw_ip,
const u32 ring)
{
@@ -272,18 +237,17 @@ static int amdgpu_ctx_init_entity(struct amdgpu_ctx *ctx,
u32 hw_ip,
static ktime_t amdgpu_ctx_fini_entity(struct amdgpu_device *adev,
struct amdgpu_ctx_entity *entity)
{
- ktime_t res = ns_to_ktime(0);
+ ktime_t res;
int i;
if (!entity)
- return res;
+ return res = ns_to_ktime(0);
- for (i = 0; i < amdgpu_sched_jobs; ++i) {
- res = ktime_add(res, amdgpu_ctx_fence_time(entity->fences[i]));
+ for (i = 0; i < amdgpu_sched_jobs; ++i)
dma_fence_put(entity->fences[i]);
- }
amdgpu_xcp_release_sched(adev, entity);
+ res = drm_sched_entity_time_spent(>entity);
drm_sched_entity_destroy(>entity);
kfree(entity);
return res;
@@ -748,9 +712,6 @@ uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx,
centity->sequence++;
spin_unlock(>ring_lock);
- atomic64_add(ktime_to_ns(amdgpu_ctx_fence_time(other)),
->mgr->time_spend[centity->hw_ip]);
-
dma_fence_put(other);
return seq;
}
@@ -930,12 +891,15 @@ void amdgpu_ctx_mgr_usage(struct amdgpu_ctx_mgr *mgr,
for (hw_ip = 0; hw_ip < AMDGPU_HW_IP_NUM; ++hw_ip) {
for (i = 0; i < amdgpu_ctx_num_entities[hw_ip]; ++i) {
struct amdgpu_ctx_entity *centity;
+ struct drm_sched_entity *entity;
ktime_t spend;
centity = ctx->entities[hw_ip][i];
if (!centity)
continue;
- spend = amdgpu_ctx_entity_time(ctx, centity);
+
+ entity = >entity;
+ spend = drm_sched_entity_time_spent(entity);
usage[hw_ip] = ktime_add(usage[hw_ip], spend);
}
}
--
2.39.2
[PATCH 4/4] drm/etnaviv: export client GPU usage statistics via fdinfo
This exposes a accumulated GPU active time per client via the
fdinfo infrastructure.
Signed-off-by: Lucas Stach
---
v2:
- new patch
---
drivers/gpu/drm/etnaviv/etnaviv_drv.c | 32 ++-
1 file changed, 31 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_drv.c
b/drivers/gpu/drm/etnaviv/etnaviv_drv.c
index 6500f3999c5f..f42b982f9a16 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_drv.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_drv.c
@@ -24,6 +24,7 @@
#include "etnaviv_gem.h"
#include "etnaviv_mmu.h"
#include "etnaviv_perfmon.h"
+#include "common.xml.h"
/*
* DRM operations:
@@ -488,7 +489,36 @@ static const struct drm_ioctl_desc etnaviv_ioctls[] = {
ETNA_IOCTL(PM_QUERY_SIG, pm_query_sig, DRM_RENDER_ALLOW),
};
-DEFINE_DRM_GEM_FOPS(fops);
+static void etnaviv_fop_show_fdinfo(struct seq_file *m, struct file *f)
+{
+ struct drm_file *file = f->private_data;
+ struct drm_device *dev = file->minor->dev;
+ struct etnaviv_drm_private *priv = dev->dev_private;
+ struct etnaviv_file_private *ctx = file->driver_priv;
+
+ /*
+* For a description of the text output format used here, see
+* Documentation/gpu/drm-usage-stats.rst.
+*/
+ seq_printf(m, "drm-driver:\t%s\n", dev->driver->name);
+ seq_printf(m, "drm-client-id:\t%u\n", ctx->id);
+
+ for (int i = 0; i < ETNA_MAX_PIPES; i++) {
+ struct etnaviv_gpu *gpu = priv->gpu[i];
+
+ if (!gpu)
+ continue;
+
+ seq_printf(m, "drm-engine-pipe%d:\t%llu ns\n", i,
+ drm_sched_entity_time_spent(>sched_entity[i]));
+ }
+}
+
+static const struct file_operations fops = {
+ .owner = THIS_MODULE,
+ DRM_GEM_FOPS,
+ .show_fdinfo = etnaviv_fop_show_fdinfo,
+};
static const struct drm_driver etnaviv_drm_driver = {
.driver_features= DRIVER_GEM | DRIVER_RENDER,
--
2.39.2
[PATCH 2/4] drm/amdgpu: mostly revert "fix force APP kill hang(v4)"
From: Christian König
This reverts commit 8ee3a52e3f35e064a3bf82f21dc74ddaf9843648.
The new amdgpu_ctx_mgr_entity_fini() was never called, so it was pure
coincident that this patch didn't cause a crash. Since the workaround
shouldn't be needed any more just mostly revert the changes to amdgpu.
Signed-off-by: Christian König
Signed-off-by: Lucas Stach
---
v2:
- rebased to v6.10-rc1
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 59 ++---
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h | 1 -
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 +-
3 files changed, 5 insertions(+), 57 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index 5cb33ac99f70..56f2428813e8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -284,7 +284,7 @@ static ktime_t amdgpu_ctx_fini_entity(struct amdgpu_device
*adev,
}
amdgpu_xcp_release_sched(adev, entity);
-
+ drm_sched_entity_destroy(>entity);
kfree(entity);
return res;
}
@@ -503,24 +503,6 @@ static int amdgpu_ctx_alloc(struct amdgpu_device *adev,
return r;
}
-static void amdgpu_ctx_do_release(struct kref *ref)
-{
- struct amdgpu_ctx *ctx;
- u32 i, j;
-
- ctx = container_of(ref, struct amdgpu_ctx, refcount);
- for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) {
- for (j = 0; j < amdgpu_ctx_num_entities[i]; ++j) {
- if (!ctx->entities[i][j])
- continue;
-
- drm_sched_entity_destroy(>entities[i][j]->entity);
- }
- }
-
- amdgpu_ctx_fini(ref);
-}
-
static int amdgpu_ctx_free(struct amdgpu_fpriv *fpriv, uint32_t id)
{
struct amdgpu_ctx_mgr *mgr = >ctx_mgr;
@@ -529,7 +511,7 @@ static int amdgpu_ctx_free(struct amdgpu_fpriv *fpriv,
uint32_t id)
mutex_lock(>lock);
ctx = idr_remove(>ctx_handles, id);
if (ctx)
- kref_put(>refcount, amdgpu_ctx_do_release);
+ kref_put(>refcount, amdgpu_ctx_fini);
mutex_unlock(>lock);
return ctx ? 0 : -EINVAL;
}
@@ -742,7 +724,7 @@ int amdgpu_ctx_put(struct amdgpu_ctx *ctx)
if (ctx == NULL)
return -EINVAL;
- kref_put(>refcount, amdgpu_ctx_do_release);
+ kref_put(>refcount, amdgpu_ctx_fini);
return 0;
}
@@ -911,45 +893,12 @@ long amdgpu_ctx_mgr_entity_flush(struct amdgpu_ctx_mgr
*mgr, long timeout)
return timeout;
}
-void amdgpu_ctx_mgr_entity_fini(struct amdgpu_ctx_mgr *mgr)
-{
- struct amdgpu_ctx *ctx;
- struct idr *idp;
- uint32_t id, i, j;
-
- idp = >ctx_handles;
-
- idr_for_each_entry(idp, ctx, id) {
- if (kref_read(>refcount) != 1) {
- DRM_ERROR("ctx %p is still alive\n", ctx);
- continue;
- }
-
- for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) {
- for (j = 0; j < amdgpu_ctx_num_entities[i]; ++j) {
- struct drm_sched_entity *entity;
-
- if (!ctx->entities[i][j])
- continue;
-
- entity = >entities[i][j]->entity;
- drm_sched_entity_fini(entity);
- }
- }
- }
-}
-
void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr)
{
struct amdgpu_ctx *ctx;
- struct idr *idp;
uint32_t id;
- amdgpu_ctx_mgr_entity_fini(mgr);
-
- idp = >ctx_handles;
-
- idr_for_each_entry(idp, ctx, id) {
+ idr_for_each_entry(>ctx_handles, ctx, id) {
if (kref_put(>refcount, amdgpu_ctx_fini) != 1)
DRM_ERROR("ctx %p is still alive\n", ctx);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
index 85376baaa92f..090dfe86f75b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
@@ -92,7 +92,6 @@ int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx,
void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr,
struct amdgpu_device *adev);
-void amdgpu_ctx_mgr_entity_fini(struct amdgpu_ctx_mgr *mgr);
long amdgpu_ctx_mgr_entity_flush(struct amdgpu_ctx_mgr *mgr, long timeout);
void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
void amdgpu_ctx_mgr_usage(struct amdgpu_ctx_mgr *mgr,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index a0ea6fe8d060..9513cf94defb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -1401,6 +1401,7 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev,
return;
pm_runtime_get_sync(dev->dev);
+ amdgpu_ctx_mgr_fini(>ctx_mgr);
if
[PATCH] drm/amdgpu/atomfirmware: silence UBSAN warning
This is a variably sized array.
Link: https://lists.freedesktop.org/archives/amd-gfx/2024-June/110420.html
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/include/atomfirmware.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h
b/drivers/gpu/drm/amd/include/atomfirmware.h
index 571691837200..09cbc3afd6d8 100644
--- a/drivers/gpu/drm/amd/include/atomfirmware.h
+++ b/drivers/gpu/drm/amd/include/atomfirmware.h
@@ -734,7 +734,7 @@ struct atom_gpio_pin_lut_v2_1
{
struct atom_common_table_header table_header;
/*the real number of this included in the structure is calcualted by using
the (whole structure size - the header size)/size of atom_gpio_pin_lut */
- struct atom_gpio_pin_assignment gpio_pin[8];
+ struct atom_gpio_pin_assignment gpio_pin[];
};
--
2.45.2
Re: amdgpu UBSAN warnings in 6.10.0-rc5
On Sun, Jun 30, 2024 at 8:40 AM Jeff Layton wrote: > > I've been testing some vfs patches (multigrain timestamps) on my > personal desktop with a 6.10.0-rc5-ish kernel, and have hit a number of > warnings in the amdgpu driver, including a UBSAN warning that looks > like a potential array overrun: > > [8.772608] [ cut here ] > [8.772609] UBSAN: array-index-out-of-bounds in > drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser2.c:680:23 > [8.772612] index 8 is out of range for type 'atom_gpio_pin_assignment [8]' > [8.772614] CPU: 13 PID: 508 Comm: (udev-worker) Not tainted > 6.10.0-rc5-00292-gb3efd5c27332 #35 > [8.772616] Hardware name: Micro-Star International Co., Ltd. MS-7E27/PRO > B650M-P (MS-7E27), BIOS 1.A0 06/07/2024 > [8.772618] Call Trace: > [8.772620] > [8.772621] dump_stack_lvl+0x5d/0x80 > [8.772629] ubsan_epilogue+0x5/0x30 > [8.772633] __ubsan_handle_out_of_bounds.cold+0x46/0x4b > [8.772636] bios_parser_get_gpio_pin_info+0x11c/0x150 [amdgpu] > [8.773016] link_get_hpd_gpio+0x7e/0xd0 [amdgpu] > [8.773205] construct_phy+0x26d/0xd40 [amdgpu] > [8.773355] ? srso_alias_return_thunk+0x5/0xfbef5 > [8.773370] ? link_create+0x210/0x250 [amdgpu] > [8.773493] ? srso_alias_return_thunk+0x5/0xfbef5 > [8.773495] link_create+0x210/0x250 [amdgpu] > [8.773610] ? srso_alias_return_thunk+0x5/0xfbef5 > [8.773612] create_links+0x151/0x530 [amdgpu] > [8.773759] dc_create+0x401/0x7b0 [amdgpu] > [8.773883] ? srso_alias_return_thunk+0x5/0xfbef5 > [8.773886] amdgpu_dm_init.isra.0+0x32f/0x22d0 [amdgpu] > [8.774045] ? irq_work_queue+0x2d/0x50 > [8.774048] ? srso_alias_return_thunk+0x5/0xfbef5 > [8.774050] ? srso_alias_return_thunk+0x5/0xfbef5 > [8.774052] ? vprintk_emit+0x176/0x2a0 > [8.774056] ? dev_vprintk_emit+0x181/0x1b0 > [8.774063] dm_hw_init+0x12/0x30 [amdgpu] > [8.774187] amdgpu_device_init.cold+0x1c43/0x1f90 [amdgpu] > [8.774373] amdgpu_driver_load_kms+0x19/0x70 [amdgpu] > [8.774507] amdgpu_pci_probe+0x1a7/0x4b0 [amdgpu] > [8.774631] local_pci_probe+0x42/0x90 > [8.774635] pci_device_probe+0xc1/0x2a0 > [8.774638] really_probe+0xdb/0x340 > [8.774642] ? pm_runtime_barrier+0x54/0x90 > [8.774644] ? __pfx___driver_attach+0x10/0x10 > [8.774646] __driver_probe_device+0x78/0x110 > [8.774648] driver_probe_device+0x1f/0xa0 > [8.774650] __driver_attach+0xba/0x1c0 > [8.774652] bus_for_each_dev+0x8c/0xe0 > [8.774655] bus_add_driver+0x142/0x220 > [8.774657] driver_register+0x72/0xd0 > [8.774660] ? __pfx_amdgpu_init+0x10/0x10 [amdgpu] > [8.774779] do_one_initcall+0x58/0x310 > [8.774784] do_init_module+0x90/0x250 > [8.774787] init_module_from_file+0x86/0xc0 > [8.774791] idempotent_init_module+0x121/0x2b0 > [8.774794] __x64_sys_finit_module+0x5e/0xb0 > [8.774796] do_syscall_64+0x82/0x160 > [8.774799] ? __pfx_page_put_link+0x10/0x10 > [8.774804] ? srso_alias_return_thunk+0x5/0xfbef5 > [8.774806] ? do_sys_openat2+0x9c/0xe0 > [8.774809] ? srso_alias_return_thunk+0x5/0xfbef5 > [8.774810] ? syscall_exit_to_user_mode+0x72/0x220 > [8.774813] ? srso_alias_return_thunk+0x5/0xfbef5 > [8.774815] ? do_syscall_64+0x8e/0x160 > [8.774816] ? srso_alias_return_thunk+0x5/0xfbef5 > [8.774818] ? __seccomp_filter+0x303/0x520 > [8.774820] ? srso_alias_return_thunk+0x5/0xfbef5 > [8.774824] ? srso_alias_return_thunk+0x5/0xfbef5 > [8.774825] ? syscall_exit_to_user_mode+0x72/0x220 > [8.774827] ? srso_alias_return_thunk+0x5/0xfbef5 > [8.774829] ? do_syscall_64+0x8e/0x160 > [8.774830] ? do_syscall_64+0x8e/0x160 > [8.774831] ? srso_alias_return_thunk+0x5/0xfbef5 > [8.774833] ? srso_alias_return_thunk+0x5/0xfbef5 > [8.774835] entry_SYSCALL_64_after_hwframe+0x76/0x7e > [8.774837] RIP: 0033:0x7fa5f44391bd > [8.774848] Code: ff c3 66 2e 0f 1f 84 00 00 00 00 00 90 f3 0f 1e fa 48 89 > f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08 0f 05 <48> 3d > 01 f0 ff ff 73 01 c3 48 8b 0d 2b cc 0c 00 f7 d8 64 89 01 48 > [8.774850] RSP: 002b:7fff5d55a5a8 EFLAGS: 0246 ORIG_RAX: > 0139 > [8.774852] RAX: ffda RBX: 555b3bfe6a50 RCX: > 7fa5f44391bd > [8.774854] RDX: RSI: 7fa5f455507d RDI: > 002c > [8.774855] RBP: 7fff5d55a660 R08: 0001 R09: > 7fff5d55a5f0 > [8.774855] R10: 0050 R11: 0246 R12: > 7fa5f455507d > [8.774856] R13: 0002 R14: 555b3bfebb30 R15: > 555b3bff63d0 > [8.774859] > [8.774864] ---[ end trace ]--- > > > It looks like "count" probably needs to be clamped to > ARRAY_SIZE(header->gpio_pin) in bios_parser_get_gpio_pin_info ? > > dmesg is attached. There are couple of other warnings in there too > after the UBSAN
Re: High Power Consumption of AMD RX6800xt in Idle with Secondary Monitor Connected
On Mon, Jul 1, 2024 at 3:25 AM Jaroslav Pulchart wrote: > > Dear AMD GPU Kernel Maintainers, > > I am writing to report an issue with high power consumption of my AMD > RX6800xt graphics card when a secondary monitor is connected. > > Upon investigation, I observed that my desktop computer generates more > heat while idling. I determined that the high power consumption issue > arises when I connect a secondary monitor to my AMD RX6800xt card, > causing it to consume approximately 40W of power in idle state . > > I checked the "GFX Clocks and Power:" in > /sys/kernel/debug/dri/1/amdgpu_pm_info of my RX6800xt during idle, and > here are the findings: > > With the secondary monitor connected memory frequency is up and > constantly at 1000MHz: > 1000 MHz (MCLK) > 3 MHz (SCLK) > 1825 MHz (PSTATE_SCLK) > 1000 MHz (PSTATE_MCLK) > 856 mV (VDDGFX) > 45.00 W (average SoC) > > Single monitor connected: > 96 MHz (MCLK) > 0 MHz (SCLK) > 1825 MHz (PSTATE_SCLK) > 1000 MHz (PSTATE_MCLK) > 6 mV (VDDGFX) > 8.00 W (average SoC) > > The significant difference in power consumption between the two states > indicates a potential issue in power management that needs to be > addressed. Your assistance in resolving this matter would be greatly > appreciated. It depends on the timing of the monitors. The memory reclocking can only occur during blanking periods on the monitors. If the reclocking is done outside of the blanking periods, you will see flickering or artifacts on the display when it happens. If the blanking periods are too short the driver can only downclock memory when the displays are off. Adding more monitors makes this harder as you have to take into account the blanking periods on all monitors. You can try adjusting the modelines used on each display to increase the blanking periods. Alex
[PATCH 2/4] drm/amd/display: Fix warning comparing pointer to 0
Avoid pointer type value compared with 0 to make code clear.
./drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_factory.c:19:12-13:
WARNING comparing pointer to 0.
Reported-by: Abaci Robot
Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=9458
Signed-off-by: Jiapeng Chong
---
.../amd/display/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_factory.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_factory.c
b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_factory.c
index ce83c10253a2..55085b85f8ed 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_factory.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_factory.c
@@ -16,7 +16,7 @@ bool dml2_mcg_create(enum dml2_project_id project_id, struct
dml2_mcg_instance *
{
bool result = false;
- if (out == 0)
+ if (!out)
return false;
memset(out, 0, sizeof(struct dml2_mcg_instance));
--
2.20.1.7.g153144c
[PATCH 4/4] drm/amd/display: Fix warning comparing pointer to 0
Avoid pointer type value compared with 0 to make code clear.
./drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_factory.c:14:12-13:
WARNING comparing pointer to 0.
Reported-by: Abaci Robot
Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=9458
Signed-off-by: Jiapeng Chong
---
.../amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_factory.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_factory.c
b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_factory.c
index 1a0da8c6df5a..f56abe9ab919 100644
---
a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_factory.c
+++
b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_factory.c
@@ -11,7 +11,7 @@ bool dml2_core_create(enum dml2_project_id project_id, struct
dml2_core_instance
{
bool result = false;
- if (out == 0)
+ if (!out)
return false;
memset(out, 0, sizeof(struct dml2_core_instance));
--
2.20.1.7.g153144c
[PATCH 3/4] drm/amd/display: Fix warning comparing pointer to 0
Avoid pointer type value compared with 0 to make code clear.
./drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_factory.c:24:12-13:
WARNING comparing pointer to 0.
Reported-by: Abaci Robot
Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=9458
Signed-off-by: Jiapeng Chong
---
.../amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_factory.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_factory.c
b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_factory.c
index 657ec2e1b119..2c983daf2dad 100644
---
a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_factory.c
+++
b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_factory.c
@@ -21,7 +21,7 @@ bool dml2_dpmm_create(enum dml2_project_id project_id, struct
dml2_dpmm_instance
{
bool result = false;
- if (out == 0)
+ if (!out)
return false;
memset(out, 0, sizeof(struct dml2_dpmm_instance));
--
2.20.1.7.g153144c
[PATCH 1/4] drm/amd/display: Fix warning comparing pointer to 0
Avoid pointer type value compared with 0 to make code clear.
./drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_factory.c:31:12-13:
WARNING comparing pointer to 0.
Reported-by: Abaci Robot
Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=9458
Signed-off-by: Jiapeng Chong
---
.../amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_factory.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_factory.c
b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_factory.c
index a34506a78c50..e0b9ece7901d 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_factory.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_factory.c
@@ -28,7 +28,7 @@ bool dml2_pmo_create(enum dml2_project_id project_id, struct
dml2_pmo_instance *
{
bool result = false;
- if (out == 0)
+ if (!out)
return false;
memset(out, 0, sizeof(struct dml2_pmo_instance));
--
2.20.1.7.g153144c
RE: [PATCH v2] drm/amd/swsmu: enable more Pstates profile levels for SMU v14.0.0 and v14.0.1
[AMD Official Use Only - AMD Internal Distribution Only]
Hi Tim,
> -Original Message-
> From: Huang, Tim
> Sent: Monday, July 1, 2024 7:32 PM
> To: Ma, Li ; amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Zhang, Yifan
>
> Subject: RE: [PATCH v2] drm/amd/swsmu: enable more Pstates profile levels
> for SMU v14.0.0 and v14.0.1
>
> [AMD Official Use Only - AMD Internal Distribution Only]
>
> Hi Li,
>
> > -Original Message-
> > From: Ma, Li
> > Sent: Monday, July 1, 2024 6:44 PM
> > To: amd-gfx@lists.freedesktop.org
> > Cc: Deucher, Alexander ; Zhang, Yifan
> > ; Huang, Tim ; Ma, Li
> >
> > Subject: [PATCH v2] drm/amd/swsmu: enable more Pstates profile levels for
> > SMU v14.0.0 and v14.0.1
> >
> > This patch enables following UMD stable Pstates profile levels for
> > power_dpm_force_performance_level interface.
> >
> > - profile_peak
> > - profile_min_mclk
> > - profile_min_sclk
> > - profile_standard
> >
> > Signed-off-by: Li Ma
> > ---
> > .../drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c | 138
> > +-
> > 1 file changed, 131 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
> > b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
> > index 3a9d58c036ea..72fca481dec1 100644
> > --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
> > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
> > @@ -65,6 +65,10 @@
> >
> > #define SMU_MALL_PG_CONFIG_DEFAULT
> > SMU_MALL_PG_CONFIG_DRIVER_CONTROL_ALWAYS_ON
> >
> > +#define SMU_14_0_0_UMD_PSTATE_GFXCLK 700
> > +#define SMU_14_0_0_UMD_PSTATE_SOCCLK 678
> > +#define SMU_14_0_0_UMD_PSTATE_FCLK 1800
> > +
> > #define FEATURE_MASK(feature) (1ULL << feature) #define
> > SMC_DPM_FEATURE ( \
> > FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \ @@ -818,9 +822,11 @@
> > static int smu_v14_0_1_get_dpm_ultimate_freq(struct smu_context *smu,
> > break;
> > case SMU_MCLK:
> > case SMU_UCLK:
> > - case SMU_FCLK:
> > max_dpm_level = 0;
> > break;
> > + case SMU_FCLK:
> > + max_dpm_level = clk_table->NumFclkLevelsEnabled - 1;
> > + break;
> > case SMU_SOCCLK:
> > max_dpm_level = clk_table->NumSocClkLevelsEnabled - 1;
> > break;
> > @@ -855,7 +861,7 @@ static int
> > smu_v14_0_1_get_dpm_ultimate_freq(struct smu_context *smu,
> > min_dpm_level = clk_table->NumMemPstatesEnabled - 1;
> > break;
> > case SMU_FCLK:
> > - min_dpm_level = clk_table->NumFclkLevelsEnabled - 1;
> > + min_dpm_level = 0;
> > break;
> > case SMU_SOCCLK:
> > min_dpm_level = 0;
> > @@ -936,9 +942,11 @@ static int
> > smu_v14_0_0_get_dpm_ultimate_freq(struct smu_context *smu,
> > break;
> > case SMU_MCLK:
> > case SMU_UCLK:
> > - case SMU_FCLK:
> > max_dpm_level = 0;
> > break;
> > + case SMU_FCLK:
> > + max_dpm_level = clk_table->NumFclkLevelsEnabled - 1;
> > + break;
> > case SMU_SOCCLK:
> > max_dpm_level = clk_table->NumSocClkLevelsEnabled - 1;
> > break;
> > @@ -969,7 +977,7 @@ static int
> > smu_v14_0_0_get_dpm_ultimate_freq(struct smu_context *smu,
> > min_dpm_level = clk_table->NumMemPstatesEnabled - 1;
> > break;
> > case SMU_FCLK:
> > - min_dpm_level = clk_table->NumFclkLevelsEnabled - 1;
> > + min_dpm_level = 0;
> > break;
> > case SMU_SOCCLK:
> > min_dpm_level = 0;
> > @@ -1268,13 +1276,67 @@ static int smu_v14_0_0_force_clk_levels(struct
> > smu_context *smu,
> > return ret;
> > }
> >
> > -static int smu_v14_0_0_set_performance_level(struct smu_context *smu,
> > +static int smu_v14_0_common_get_dpm_profile_freq(struct smu_context
> > *smu,
> > + enum amd_dpm_forced_level level,
> > + enum smu_clk_type clk_type,
> > + uint32_t *min_clk,
> > + uint32_t *max_clk)
> > +{
> > + uint32_t clk_limit = 0;
> > + int ret = 0;
> > +
> > + switch (clk_type) {
> > + case SMU_GFXCLK:
> > + case SMU_SCLK:
> > + clk_limit = SMU_14_0_0_UMD_PSTATE_GFXCLK;
> > + if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
> > + smu_v14_0_common_get_dpm_ultimate_freq(smu,
> SMU_SCLK,
> > NULL, _limit);
> > + else if (level ==
RE: [PATCH v2] drm/amd/swsmu: enable more Pstates profile levels for SMU v14.0.0 and v14.0.1
[AMD Official Use Only - AMD Internal Distribution Only]
Hi Li,
> -Original Message-
> From: Ma, Li
> Sent: Monday, July 1, 2024 6:44 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Zhang, Yifan
> ; Huang, Tim ; Ma, Li
>
> Subject: [PATCH v2] drm/amd/swsmu: enable more Pstates profile levels for
> SMU v14.0.0 and v14.0.1
>
> This patch enables following UMD stable Pstates profile levels for
> power_dpm_force_performance_level interface.
>
> - profile_peak
> - profile_min_mclk
> - profile_min_sclk
> - profile_standard
>
> Signed-off-by: Li Ma
> ---
> .../drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c | 138
> +-
> 1 file changed, 131 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
> index 3a9d58c036ea..72fca481dec1 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
> @@ -65,6 +65,10 @@
>
> #define SMU_MALL_PG_CONFIG_DEFAULT
> SMU_MALL_PG_CONFIG_DRIVER_CONTROL_ALWAYS_ON
>
> +#define SMU_14_0_0_UMD_PSTATE_GFXCLK 700
> +#define SMU_14_0_0_UMD_PSTATE_SOCCLK 678
> +#define SMU_14_0_0_UMD_PSTATE_FCLK 1800
> +
> #define FEATURE_MASK(feature) (1ULL << feature) #define
> SMC_DPM_FEATURE ( \
> FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \ @@ -818,9 +822,11 @@
> static int smu_v14_0_1_get_dpm_ultimate_freq(struct smu_context *smu,
> break;
> case SMU_MCLK:
> case SMU_UCLK:
> - case SMU_FCLK:
> max_dpm_level = 0;
> break;
> + case SMU_FCLK:
> + max_dpm_level = clk_table->NumFclkLevelsEnabled - 1;
> + break;
> case SMU_SOCCLK:
> max_dpm_level = clk_table->NumSocClkLevelsEnabled - 1;
> break;
> @@ -855,7 +861,7 @@ static int
> smu_v14_0_1_get_dpm_ultimate_freq(struct smu_context *smu,
> min_dpm_level = clk_table->NumMemPstatesEnabled - 1;
> break;
> case SMU_FCLK:
> - min_dpm_level = clk_table->NumFclkLevelsEnabled - 1;
> + min_dpm_level = 0;
> break;
> case SMU_SOCCLK:
> min_dpm_level = 0;
> @@ -936,9 +942,11 @@ static int
> smu_v14_0_0_get_dpm_ultimate_freq(struct smu_context *smu,
> break;
> case SMU_MCLK:
> case SMU_UCLK:
> - case SMU_FCLK:
> max_dpm_level = 0;
> break;
> + case SMU_FCLK:
> + max_dpm_level = clk_table->NumFclkLevelsEnabled - 1;
> + break;
> case SMU_SOCCLK:
> max_dpm_level = clk_table->NumSocClkLevelsEnabled - 1;
> break;
> @@ -969,7 +977,7 @@ static int
> smu_v14_0_0_get_dpm_ultimate_freq(struct smu_context *smu,
> min_dpm_level = clk_table->NumMemPstatesEnabled - 1;
> break;
> case SMU_FCLK:
> - min_dpm_level = clk_table->NumFclkLevelsEnabled - 1;
> + min_dpm_level = 0;
> break;
> case SMU_SOCCLK:
> min_dpm_level = 0;
> @@ -1268,13 +1276,67 @@ static int smu_v14_0_0_force_clk_levels(struct
> smu_context *smu,
> return ret;
> }
>
> -static int smu_v14_0_0_set_performance_level(struct smu_context *smu,
> +static int smu_v14_0_common_get_dpm_profile_freq(struct smu_context
> *smu,
> + enum amd_dpm_forced_level level,
> + enum smu_clk_type clk_type,
> + uint32_t *min_clk,
> + uint32_t *max_clk)
> +{
> + uint32_t clk_limit = 0;
> + int ret = 0;
> +
> + switch (clk_type) {
> + case SMU_GFXCLK:
> + case SMU_SCLK:
> + clk_limit = SMU_14_0_0_UMD_PSTATE_GFXCLK;
> + if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
> + smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_SCLK,
> NULL, _limit);
> + else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK)
> + smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_SCLK,
> _limit, NULL);
> + break;
> + case SMU_SOCCLK:
> + clk_limit = SMU_14_0_0_UMD_PSTATE_SOCCLK;
> + if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
> + smu_v14_0_common_get_dpm_ultimate_freq(smu,
> SMU_SOCCLK, NULL, _limit);
> + break;
> + case SMU_FCLK:
> + clk_limit = SMU_14_0_0_UMD_PSTATE_FCLK;
> + if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
> +
[PATCH v2] drm/amd/swsmu: enable more Pstates profile levels for SMU v14.0.0 and v14.0.1
This patch enables following UMD stable Pstates profile
levels for power_dpm_force_performance_level interface.
- profile_peak
- profile_min_mclk
- profile_min_sclk
- profile_standard
Signed-off-by: Li Ma
---
.../drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c | 138 +-
1 file changed, 131 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
index 3a9d58c036ea..72fca481dec1 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
@@ -65,6 +65,10 @@
#define SMU_MALL_PG_CONFIG_DEFAULT SMU_MALL_PG_CONFIG_DRIVER_CONTROL_ALWAYS_ON
+#define SMU_14_0_0_UMD_PSTATE_GFXCLK 700
+#define SMU_14_0_0_UMD_PSTATE_SOCCLK 678
+#define SMU_14_0_0_UMD_PSTATE_FCLK 1800
+
#define FEATURE_MASK(feature) (1ULL << feature)
#define SMC_DPM_FEATURE ( \
FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \
@@ -818,9 +822,11 @@ static int smu_v14_0_1_get_dpm_ultimate_freq(struct
smu_context *smu,
break;
case SMU_MCLK:
case SMU_UCLK:
- case SMU_FCLK:
max_dpm_level = 0;
break;
+ case SMU_FCLK:
+ max_dpm_level = clk_table->NumFclkLevelsEnabled - 1;
+ break;
case SMU_SOCCLK:
max_dpm_level = clk_table->NumSocClkLevelsEnabled - 1;
break;
@@ -855,7 +861,7 @@ static int smu_v14_0_1_get_dpm_ultimate_freq(struct
smu_context *smu,
min_dpm_level = clk_table->NumMemPstatesEnabled - 1;
break;
case SMU_FCLK:
- min_dpm_level = clk_table->NumFclkLevelsEnabled - 1;
+ min_dpm_level = 0;
break;
case SMU_SOCCLK:
min_dpm_level = 0;
@@ -936,9 +942,11 @@ static int smu_v14_0_0_get_dpm_ultimate_freq(struct
smu_context *smu,
break;
case SMU_MCLK:
case SMU_UCLK:
- case SMU_FCLK:
max_dpm_level = 0;
break;
+ case SMU_FCLK:
+ max_dpm_level = clk_table->NumFclkLevelsEnabled - 1;
+ break;
case SMU_SOCCLK:
max_dpm_level = clk_table->NumSocClkLevelsEnabled - 1;
break;
@@ -969,7 +977,7 @@ static int smu_v14_0_0_get_dpm_ultimate_freq(struct
smu_context *smu,
min_dpm_level = clk_table->NumMemPstatesEnabled - 1;
break;
case SMU_FCLK:
- min_dpm_level = clk_table->NumFclkLevelsEnabled - 1;
+ min_dpm_level = 0;
break;
case SMU_SOCCLK:
min_dpm_level = 0;
@@ -1268,13 +1276,67 @@ static int smu_v14_0_0_force_clk_levels(struct
smu_context *smu,
return ret;
}
-static int smu_v14_0_0_set_performance_level(struct smu_context *smu,
+static int smu_v14_0_common_get_dpm_profile_freq(struct smu_context *smu,
+ enum amd_dpm_forced_level level,
+ enum smu_clk_type clk_type,
+ uint32_t *min_clk,
+ uint32_t *max_clk)
+{
+ uint32_t clk_limit = 0;
+ int ret = 0;
+
+ switch (clk_type) {
+ case SMU_GFXCLK:
+ case SMU_SCLK:
+ clk_limit = SMU_14_0_0_UMD_PSTATE_GFXCLK;
+ if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
+ smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_SCLK,
NULL, _limit);
+ else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK)
+ smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_SCLK,
_limit, NULL);
+ break;
+ case SMU_SOCCLK:
+ clk_limit = SMU_14_0_0_UMD_PSTATE_SOCCLK;
+ if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
+ smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_SOCCLK,
NULL, _limit);
+ break;
+ case SMU_FCLK:
+ clk_limit = SMU_14_0_0_UMD_PSTATE_FCLK;
+ if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
+ smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_FCLK,
NULL, _limit);
+ else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK)
+ smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_FCLK,
_limit, NULL);
+ break;
+ case SMU_VCLK:
+ smu_v14_0_common_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL,
_limit);
+ break;
+ case SMU_VCLK1:
+
Re: [PATCH] drm/amdgpu: sysfs node disable query error count during gpu reset
On 01.07.24 10:10, YiPeng Chai wrote: Sysfs node disable query error count during gpu reset. Can you elaborate a bit more? Usually the body shouldn't be a 1:1 copy of the summary phrase. Signed-off-by: YiPeng Chai --- drivers/gpu/drm/amd/amdgpu/aldebaran.c | 2 -- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 ++- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c| 3 +++ 3 files changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/aldebaran.c b/drivers/gpu/drm/amd/amdgpu/aldebaran.c index d0a8da67dc2a..b0f95a7649bf 100644 --- a/drivers/gpu/drm/amd/amdgpu/aldebaran.c +++ b/drivers/gpu/drm/amd/amdgpu/aldebaran.c @@ -316,8 +316,6 @@ static int aldebaran_mode2_restore_ip(struct amdgpu_device *adev) adev->ip_blocks[i].status.late_initialized = true; } - amdgpu_ras_set_error_query_ready(adev, true); - amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE); amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index e133a9982a77..41689aa24e67 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -3157,7 +3157,8 @@ static int amdgpu_device_ip_late_init(struct amdgpu_device *adev) return r; } - amdgpu_ras_set_error_query_ready(adev, true); + if (!amdgpu_in_reset(adev)) + amdgpu_ras_set_error_query_ready(adev, true); amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE); amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index ac7ded01dad0..e2abc04112d2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -1295,6 +1295,9 @@ ssize_t amdgpu_ras_aca_sysfs_read(struct device *dev, struct device_attribute *a .head = obj->head, }; + if (!amdgpu_ras_get_error_query_ready(obj->adev)) + return sysfs_emit(buf, "Query currently inaccessible\n"); Why not return -EBUSY instead? Best, Friedrich + if (amdgpu_ras_query_error_status(obj->adev, )) return -EINVAL;
RE: [PATCH] drm/amd/swsmu: enable more Pstates profile levels for SMU v14.0.0 and v14.0.1
[AMD Official Use Only - AMD Internal Distribution Only]
Hi Tim,
> -Original Message-
> From: Huang, Tim
> Sent: Monday, July 1, 2024 5:34 PM
> To: Ma, Li ; amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Zhang, Yifan
>
> Subject: RE: [PATCH] drm/amd/swsmu: enable more Pstates profile levels for
> SMU v14.0.0 and v14.0.1
>
> [AMD Official Use Only - AMD Internal Distribution Only]
>
> Hi Li,
>
> > -Original Message-
> > From: Ma, Li
> > Sent: Monday, July 1, 2024 4:23 PM
> > To: amd-gfx@lists.freedesktop.org
> > Cc: Deucher, Alexander ; Zhang, Yifan
> > ; Huang, Tim ; Ma, Li
> >
> > Subject: [PATCH] drm/amd/swsmu: enable more Pstates profile levels for
> SMU
> > v14.0.0 and v14.0.1
> >
> > This patch enables following UMD stable Pstates profile levels for
> > power_dpm_force_performance_level interface.
> >
> > - profile_peak
> > - profile_min_mclk
> > - profile_min_sclk
> > - profile_standard
> >
> > Signed-off-by: Li Ma
> > ---
> > .../drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c | 150
> > --
> > 1 file changed, 137 insertions(+), 13 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
> > b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
> > index 18abfbd6d059..d999e3b23173 100644
> > --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
> > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
> > @@ -65,6 +65,10 @@
> >
> > #define SMU_MALL_PG_CONFIG_DEFAULT
> > SMU_MALL_PG_CONFIG_DRIVER_CONTROL_ALWAYS_ON
> >
> > +#define SMU_14_0_0_UMD_PSTATE_GFXCLK 700
> > +#define SMU_14_0_0_UMD_PSTATE_SOCCLK 678
> > +#define SMU_14_0_0_UMD_PSTATE_FCLK 1800
> > +
> > #define FEATURE_MASK(feature) (1ULL << feature) #define
> > SMC_DPM_FEATURE ( \
> > FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \ @@ -723,10 +727,10
> @@
> > static int smu_v14_0_common_get_dpm_freq_by_index(struct
> smu_context
> > *smu,
> > uint32_t dpm_level,
> > uint32_t *freq)
> > {
> > - if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0,
> > 0))
> > - smu_v14_0_0_get_dpm_freq_by_index(smu, clk_type, dpm_level,
> > freq);
> > - else if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) ==
> IP_VERSION(14,
> > 0, 1))
> > + if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0,
> > 1))
> > smu_v14_0_1_get_dpm_freq_by_index(smu, clk_type, dpm_level,
> > freq);
> > + else
> > + smu_v14_0_0_get_dpm_freq_by_index(smu, clk_type, dpm_level,
> > freq);
> >
> > return 0;
> > }
>
> Does this conflict with the ongoing commit drm/amd/pm: smu v14.0.4 reuse
> smu v14.0.0 dpmtable ?
>
> Tim
Li: Thanks for reminder, the change in smu_v14_0_common_get_dpm_freq_by_index
and smu_v14_0_common_get_dpm_ultimate_freq are same as ongoing commit
"drm/amd/pm: smu v14.0.4 reuse smu v14.0.0 dpmtable". I will remove this change
to avoid the repetition.
>
> > @@ -818,9 +822,11 @@ static int
> > smu_v14_0_1_get_dpm_ultimate_freq(struct smu_context *smu,
> > break;
> > case SMU_MCLK:
> > case SMU_UCLK:
> > - case SMU_FCLK:
> > max_dpm_level = 0;
> > break;
> > + case SMU_FCLK:
> > + max_dpm_level = clk_table->NumFclkLevelsEnabled - 1;
> > + break;
> > case SMU_SOCCLK:
> > max_dpm_level = clk_table->NumSocClkLevelsEnabled - 1;
> > break;
> > @@ -855,7 +861,7 @@ static int
> > smu_v14_0_1_get_dpm_ultimate_freq(struct smu_context *smu,
> > min_dpm_level = clk_table->NumMemPstatesEnabled - 1;
> > break;
> > case SMU_FCLK:
> > - min_dpm_level = clk_table->NumFclkLevelsEnabled - 1;
> > + min_dpm_level = 0;
> > break;
> > case SMU_SOCCLK:
> > min_dpm_level = 0;
> > @@ -936,9 +942,11 @@ static int
> > smu_v14_0_0_get_dpm_ultimate_freq(struct smu_context *smu,
> > break;
> > case SMU_MCLK:
> > case SMU_UCLK:
> > - case SMU_FCLK:
> > max_dpm_level = 0;
> > break;
> > + case SMU_FCLK:
> > + max_dpm_level = clk_table->NumFclkLevelsEnabled - 1;
> > + break;
> > case SMU_SOCCLK:
> > max_dpm_level = clk_table->NumSocClkLevelsEnabled - 1;
> > break;
> > @@ -969,7 +977,7 @@ static int
> > smu_v14_0_0_get_dpm_ultimate_freq(struct smu_context *smu,
> > min_dpm_level = clk_table->NumMemPstatesEnabled - 1;
> > break;
> > case SMU_FCLK:
> > -
RE: [PATCH] drm/amd/swsmu: enable more Pstates profile levels for SMU v14.0.0 and v14.0.1
[AMD Official Use Only - AMD Internal Distribution Only]
Hi Li,
> -Original Message-
> From: Ma, Li
> Sent: Monday, July 1, 2024 4:23 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Zhang, Yifan
> ; Huang, Tim ; Ma, Li
>
> Subject: [PATCH] drm/amd/swsmu: enable more Pstates profile levels for SMU
> v14.0.0 and v14.0.1
>
> This patch enables following UMD stable Pstates profile levels for
> power_dpm_force_performance_level interface.
>
> - profile_peak
> - profile_min_mclk
> - profile_min_sclk
> - profile_standard
>
> Signed-off-by: Li Ma
> ---
> .../drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c | 150
> --
> 1 file changed, 137 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
> index 18abfbd6d059..d999e3b23173 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
> @@ -65,6 +65,10 @@
>
> #define SMU_MALL_PG_CONFIG_DEFAULT
> SMU_MALL_PG_CONFIG_DRIVER_CONTROL_ALWAYS_ON
>
> +#define SMU_14_0_0_UMD_PSTATE_GFXCLK 700
> +#define SMU_14_0_0_UMD_PSTATE_SOCCLK 678
> +#define SMU_14_0_0_UMD_PSTATE_FCLK 1800
> +
> #define FEATURE_MASK(feature) (1ULL << feature) #define
> SMC_DPM_FEATURE ( \
> FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \ @@ -723,10 +727,10 @@
> static int smu_v14_0_common_get_dpm_freq_by_index(struct smu_context
> *smu,
> uint32_t dpm_level,
> uint32_t *freq)
> {
> - if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0,
> 0))
> - smu_v14_0_0_get_dpm_freq_by_index(smu, clk_type, dpm_level,
> freq);
> - else if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14,
> 0, 1))
> + if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0,
> 1))
> smu_v14_0_1_get_dpm_freq_by_index(smu, clk_type, dpm_level,
> freq);
> + else
> + smu_v14_0_0_get_dpm_freq_by_index(smu, clk_type, dpm_level,
> freq);
>
> return 0;
> }
Does this conflict with the ongoing commit drm/amd/pm: smu v14.0.4 reuse smu
v14.0.0 dpmtable ?
Tim
> @@ -818,9 +822,11 @@ static int
> smu_v14_0_1_get_dpm_ultimate_freq(struct smu_context *smu,
> break;
> case SMU_MCLK:
> case SMU_UCLK:
> - case SMU_FCLK:
> max_dpm_level = 0;
> break;
> + case SMU_FCLK:
> + max_dpm_level = clk_table->NumFclkLevelsEnabled - 1;
> + break;
> case SMU_SOCCLK:
> max_dpm_level = clk_table->NumSocClkLevelsEnabled - 1;
> break;
> @@ -855,7 +861,7 @@ static int
> smu_v14_0_1_get_dpm_ultimate_freq(struct smu_context *smu,
> min_dpm_level = clk_table->NumMemPstatesEnabled - 1;
> break;
> case SMU_FCLK:
> - min_dpm_level = clk_table->NumFclkLevelsEnabled - 1;
> + min_dpm_level = 0;
> break;
> case SMU_SOCCLK:
> min_dpm_level = 0;
> @@ -936,9 +942,11 @@ static int
> smu_v14_0_0_get_dpm_ultimate_freq(struct smu_context *smu,
> break;
> case SMU_MCLK:
> case SMU_UCLK:
> - case SMU_FCLK:
> max_dpm_level = 0;
> break;
> + case SMU_FCLK:
> + max_dpm_level = clk_table->NumFclkLevelsEnabled - 1;
> + break;
> case SMU_SOCCLK:
> max_dpm_level = clk_table->NumSocClkLevelsEnabled - 1;
> break;
> @@ -969,7 +977,7 @@ static int
> smu_v14_0_0_get_dpm_ultimate_freq(struct smu_context *smu,
> min_dpm_level = clk_table->NumMemPstatesEnabled - 1;
> break;
> case SMU_FCLK:
> - min_dpm_level = clk_table->NumFclkLevelsEnabled - 1;
> + min_dpm_level = 0;
> break;
> case SMU_SOCCLK:
> min_dpm_level = 0;
> @@ -999,10 +1007,10 @@ static int
> smu_v14_0_common_get_dpm_ultimate_freq(struct smu_context *smu,
> uint32_t *min,
> uint32_t *max)
> {
> - if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0,
> 0))
> - smu_v14_0_0_get_dpm_ultimate_freq(smu, clk_type, min, max);
> - else if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14,
> 0, 1))
> + if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0,
> 1))
>
[PATCH] drm/amd/swsmu: enable more Pstates profile levels for SMU v14.0.0 and v14.0.1
This patch enables following UMD stable Pstates profile
levels for power_dpm_force_performance_level interface.
- profile_peak
- profile_min_mclk
- profile_min_sclk
- profile_standard
Signed-off-by: Li Ma
---
.../drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c | 150 --
1 file changed, 137 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
index 18abfbd6d059..d999e3b23173 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
@@ -65,6 +65,10 @@
#define SMU_MALL_PG_CONFIG_DEFAULT SMU_MALL_PG_CONFIG_DRIVER_CONTROL_ALWAYS_ON
+#define SMU_14_0_0_UMD_PSTATE_GFXCLK 700
+#define SMU_14_0_0_UMD_PSTATE_SOCCLK 678
+#define SMU_14_0_0_UMD_PSTATE_FCLK 1800
+
#define FEATURE_MASK(feature) (1ULL << feature)
#define SMC_DPM_FEATURE ( \
FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \
@@ -723,10 +727,10 @@ static int smu_v14_0_common_get_dpm_freq_by_index(struct
smu_context *smu,
uint32_t dpm_level,
uint32_t *freq)
{
- if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0))
- smu_v14_0_0_get_dpm_freq_by_index(smu, clk_type, dpm_level,
freq);
- else if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0,
1))
+ if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1))
smu_v14_0_1_get_dpm_freq_by_index(smu, clk_type, dpm_level,
freq);
+ else
+ smu_v14_0_0_get_dpm_freq_by_index(smu, clk_type, dpm_level,
freq);
return 0;
}
@@ -818,9 +822,11 @@ static int smu_v14_0_1_get_dpm_ultimate_freq(struct
smu_context *smu,
break;
case SMU_MCLK:
case SMU_UCLK:
- case SMU_FCLK:
max_dpm_level = 0;
break;
+ case SMU_FCLK:
+ max_dpm_level = clk_table->NumFclkLevelsEnabled - 1;
+ break;
case SMU_SOCCLK:
max_dpm_level = clk_table->NumSocClkLevelsEnabled - 1;
break;
@@ -855,7 +861,7 @@ static int smu_v14_0_1_get_dpm_ultimate_freq(struct
smu_context *smu,
min_dpm_level = clk_table->NumMemPstatesEnabled - 1;
break;
case SMU_FCLK:
- min_dpm_level = clk_table->NumFclkLevelsEnabled - 1;
+ min_dpm_level = 0;
break;
case SMU_SOCCLK:
min_dpm_level = 0;
@@ -936,9 +942,11 @@ static int smu_v14_0_0_get_dpm_ultimate_freq(struct
smu_context *smu,
break;
case SMU_MCLK:
case SMU_UCLK:
- case SMU_FCLK:
max_dpm_level = 0;
break;
+ case SMU_FCLK:
+ max_dpm_level = clk_table->NumFclkLevelsEnabled - 1;
+ break;
case SMU_SOCCLK:
max_dpm_level = clk_table->NumSocClkLevelsEnabled - 1;
break;
@@ -969,7 +977,7 @@ static int smu_v14_0_0_get_dpm_ultimate_freq(struct
smu_context *smu,
min_dpm_level = clk_table->NumMemPstatesEnabled - 1;
break;
case SMU_FCLK:
- min_dpm_level = clk_table->NumFclkLevelsEnabled - 1;
+ min_dpm_level = 0;
break;
case SMU_SOCCLK:
min_dpm_level = 0;
@@ -999,10 +1007,10 @@ static int smu_v14_0_common_get_dpm_ultimate_freq(struct
smu_context *smu,
uint32_t *min,
uint32_t *max)
{
- if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0))
- smu_v14_0_0_get_dpm_ultimate_freq(smu, clk_type, min, max);
- else if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0,
1))
+ if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1))
smu_v14_0_1_get_dpm_ultimate_freq(smu, clk_type, min, max);
+ else if (clk_type != SMU_VCLK1 && clk_type != SMU_DCLK1)
+ smu_v14_0_0_get_dpm_ultimate_freq(smu, clk_type, min, max);
return 0;
}
@@ -1268,13 +1276,67 @@ static int smu_v14_0_0_force_clk_levels(struct
smu_context *smu,
return ret;
}
-static int smu_v14_0_0_set_performance_level(struct smu_context *smu,
+static int smu_v14_0_common_get_dpm_profile_freq(struct smu_context *smu,
+ enum amd_dpm_forced_level level,
+
RE: [PATCH] drm/amdgpu: sysfs node disable query error count during gpu reset
[AMD Official Use Only - AMD Internal Distribution Only] Reviewed-by: Stanley.Yang Regards, Stanley > -Original Message- > From: Chai, Thomas > Sent: Monday, July 1, 2024 4:11 PM > To: amd-gfx@lists.freedesktop.org > Cc: Zhang, Hawking ; Zhou1, Tao > ; Li, Candice ; Wang, Yang(Kevin) > ; Yang, Stanley ; Chai, > Thomas > Subject: [PATCH] drm/amdgpu: sysfs node disable query error count during gpu > reset > > Sysfs node disable query error count during gpu reset. > > Signed-off-by: YiPeng Chai > --- > drivers/gpu/drm/amd/amdgpu/aldebaran.c | 2 -- > drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 ++- > drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c| 3 +++ > 3 files changed, 5 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/aldebaran.c > b/drivers/gpu/drm/amd/amdgpu/aldebaran.c > index d0a8da67dc2a..b0f95a7649bf 100644 > --- a/drivers/gpu/drm/amd/amdgpu/aldebaran.c > +++ b/drivers/gpu/drm/amd/amdgpu/aldebaran.c > @@ -316,8 +316,6 @@ static int aldebaran_mode2_restore_ip(struct > amdgpu_device *adev) > adev->ip_blocks[i].status.late_initialized = true; > } > > - amdgpu_ras_set_error_query_ready(adev, true); > - > amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE); > amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE); > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > index e133a9982a77..41689aa24e67 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > @@ -3157,7 +3157,8 @@ static int amdgpu_device_ip_late_init(struct > amdgpu_device *adev) > return r; > } > > - amdgpu_ras_set_error_query_ready(adev, true); > + if (!amdgpu_in_reset(adev)) > + amdgpu_ras_set_error_query_ready(adev, true); > > amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE); > amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE); diff --git > a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c > index ac7ded01dad0..e2abc04112d2 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c > @@ -1295,6 +1295,9 @@ ssize_t amdgpu_ras_aca_sysfs_read(struct device > *dev, struct device_attribute *a > .head = obj->head, > }; > > + if (!amdgpu_ras_get_error_query_ready(obj->adev)) > + return sysfs_emit(buf, "Query currently inaccessible\n"); > + > if (amdgpu_ras_query_error_status(obj->adev, )) > return -EINVAL; > > -- > 2.34.1
[PATCH] drm/amdgpu: sysfs node disable query error count during gpu reset
Sysfs node disable query error count during gpu reset. Signed-off-by: YiPeng Chai --- drivers/gpu/drm/amd/amdgpu/aldebaran.c | 2 -- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 ++- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c| 3 +++ 3 files changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/aldebaran.c b/drivers/gpu/drm/amd/amdgpu/aldebaran.c index d0a8da67dc2a..b0f95a7649bf 100644 --- a/drivers/gpu/drm/amd/amdgpu/aldebaran.c +++ b/drivers/gpu/drm/amd/amdgpu/aldebaran.c @@ -316,8 +316,6 @@ static int aldebaran_mode2_restore_ip(struct amdgpu_device *adev) adev->ip_blocks[i].status.late_initialized = true; } - amdgpu_ras_set_error_query_ready(adev, true); - amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE); amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index e133a9982a77..41689aa24e67 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -3157,7 +3157,8 @@ static int amdgpu_device_ip_late_init(struct amdgpu_device *adev) return r; } - amdgpu_ras_set_error_query_ready(adev, true); + if (!amdgpu_in_reset(adev)) + amdgpu_ras_set_error_query_ready(adev, true); amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE); amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index ac7ded01dad0..e2abc04112d2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -1295,6 +1295,9 @@ ssize_t amdgpu_ras_aca_sysfs_read(struct device *dev, struct device_attribute *a .head = obj->head, }; + if (!amdgpu_ras_get_error_query_ready(obj->adev)) + return sysfs_emit(buf, "Query currently inaccessible\n"); + if (amdgpu_ras_query_error_status(obj->adev, )) return -EINVAL; -- 2.34.1
RE: [PATCH V2] drm/amdgpu: sysfs node disable query error count during gpu reset
[AMD Official Use Only - AMD Internal Distribution Only]
OK
-
Best Regards,
Thomas
-Original Message-
From: Yang, Stanley
Sent: Monday, July 1, 2024 2:41 PM
To: Chai, Thomas ; amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Zhou1, Tao ; Li,
Candice ; Wang, Yang(Kevin)
Subject: RE: [PATCH V2] drm/amdgpu: sysfs node disable query error count during
gpu reset
[AMD Official Use Only - AMD Internal Distribution Only]
Hi Thomas,
I think we can optimize the amdgpu_ras_set_error_query_ready(adev, true)
function calling during GPU recovery,
amdgpu_ras_set_error_query_ready(tmp_adev, false) -> recovery start -> recovery
done -> amdgpu_ras_set_error_query_ready(tmp_adev, true), above process can
avoid access query error count during GPU recovery.
Regards,
Stanley
> -Original Message-
> From: Chai, Thomas
> Sent: Monday, July 1, 2024 11:19 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhang, Hawking ; Zhou1, Tao
> ; Li, Candice ; Wang,
> Yang(Kevin) ; Yang, Stanley
> ; Chai, Thomas
> Subject: [PATCH V2] drm/amdgpu: sysfs node disable query error count
> during gpu reset
>
> Sysfs node disable query error count during gpu reset.
>
> Signed-off-by: YiPeng Chai
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 15 +--
> 1 file changed, 13 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> index ac7ded01dad0..a65b5197b0fc 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> @@ -619,6 +619,7 @@ static const struct file_operations
> amdgpu_ras_debugfs_eeprom_ops = { static ssize_t
> amdgpu_ras_sysfs_read(struct device *dev,
> struct device_attribute *attr, char *buf) {
> + int ret;
> struct ras_manager *obj = container_of(attr, struct ras_manager,
> sysfs_attr);
> struct ras_query_if info = {
> .head = obj->head,
> @@ -627,7 +628,10 @@ static ssize_t amdgpu_ras_sysfs_read(struct
> device *dev,
> if (!amdgpu_ras_get_error_query_ready(obj->adev))
> return sysfs_emit(buf, "Query currently
> inaccessible\n");
>
> - if (amdgpu_ras_query_error_status(obj->adev, ))
> + ret = amdgpu_ras_query_error_status(obj->adev, );
> + if (ret == -EIO) /* gpu reset is ongoing */
> + return sysfs_emit(buf, "Query currently inaccessible\n");
> + else if (ret)
> return -EINVAL;
>
> if (amdgpu_ip_version(obj->adev, MP0_HWIP, 0) != IP_VERSION(11,
> 0, 2) && @@ -1290,12 +1294,19 @@ static int
> amdgpu_aca_log_ras_error_data(struct amdgpu_device *adev, enum amdgpu
> ssize_t amdgpu_ras_aca_sysfs_read(struct device *dev, struct
> device_attribute *attr,
> struct aca_handle *handle, char *buf,
> void
> *data) {
> + int ret;
> struct ras_manager *obj = container_of(handle, struct
> ras_manager, aca_handle);
> struct ras_query_if info = {
> .head = obj->head,
> };
>
> - if (amdgpu_ras_query_error_status(obj->adev, ))
> + if (!amdgpu_ras_get_error_query_ready(obj->adev))
> + return sysfs_emit(buf, "Query currently
> + inaccessible\n");
> +
> + ret = amdgpu_ras_query_error_status(obj->adev, );
> + if (ret == -EIO) /* gpu reset is ongoing */
> + return sysfs_emit(buf, "Query currently inaccessible\n");
> + else if (ret)
> return -EINVAL;
>
> return sysfs_emit(buf, "%s: %lu\n%s: %lu\n%s: %lu\n", "ue",
> info.ue_count,
> --
> 2.34.1
Re: [PATCH v2 1/3] drm: Add panel backlight quirks
On 6/23/24 01:51, Thomas Weißschuh wrote:
Panels using a PWM-controlled backlight source without an do not have a
standard way to communicate their valid PWM ranges.
On x86 the ranges are read from ACPI through driver-specific tables.
The built-in ranges are not necessarily correct, or may grow stale if an
older device can be retrofitted with newer panels.
Add a quirk infrastructure with which the valid backlight ranges can be
maintained as part of the kernel.
Signed-off-by: Thomas Weißschuh
---
...
+EXPORT_SYMBOL(drm_get_panel_backlight_quirk);
+
+MODULE_LICENSE("GPL");
Missing a MODULE_DESCRIPTION()
This will result in a make W=1 warning
Re: [PATCH v3 0/7] drm/radeon: remove load callback
Dear Thmoas, Thanks a lot for the feedback. I admit that my patch was a mess, sorry about that. I have submitted a v3 to change a lot of stuff, these patches should be able to be built now. I also improve readability, where each patch does their own stuff. Best regards, Wu On Wed, Jun 26, 2024 at 10:47 AM Thomas Zimmermann wrote: > > Hi > > Am 24.06.24 um 17:10 schrieb Wu Hoi Pok: > > Changes between v1 and v3: > > > > 1. add "ddev->dev_private = rdev;" > > 2. include a cover letter > > A cover letter should briefly say what the patchset is about. > > BTW it's not clear to me why you need to modify radeon_dev.dev for > removing the load callback. It seems it's a separate issue. > > Best regards > Thomas > > > > > > Wu Hoi Pok (7): > >drm/radeon: remove load callback > >drm/radeon: rdev->ddev to rdev_to_drm(rdev) 1 > >drm/radeon: rdev->ddev to rdev_to_drm(rdev) 2 > >drm/radeon: rdev->ddev to rdev_to_drm(rdev) 3 > >drm/radeon: rdev->ddev to rdev_to_drm(rdev) 4 > >drm/radeon: rdev->ddev to rdev_to_drm(rdev) 5 > >drm/radeon: rdev->ddev to rdev_to_drm(rdev) 6 > > > > drivers/gpu/drm/radeon/atombios_encoders.c | 2 +- > > drivers/gpu/drm/radeon/cik.c | 14 ++-- > > drivers/gpu/drm/radeon/dce6_afmt.c | 2 +- > > drivers/gpu/drm/radeon/evergreen.c | 12 ++-- > > drivers/gpu/drm/radeon/ni.c| 2 +- > > drivers/gpu/drm/radeon/r100.c | 24 +++ > > drivers/gpu/drm/radeon/r300.c | 6 +- > > drivers/gpu/drm/radeon/r420.c | 6 +- > > drivers/gpu/drm/radeon/r520.c | 2 +- > > drivers/gpu/drm/radeon/r600.c | 12 ++-- > > drivers/gpu/drm/radeon/r600_cs.c | 2 +- > > drivers/gpu/drm/radeon/r600_dpm.c | 4 +- > > drivers/gpu/drm/radeon/r600_hdmi.c | 2 +- > > drivers/gpu/drm/radeon/radeon.h| 11 +++- > > drivers/gpu/drm/radeon/radeon_acpi.c | 10 +-- > > drivers/gpu/drm/radeon/radeon_agp.c| 2 +- > > drivers/gpu/drm/radeon/radeon_atombios.c | 2 +- > > drivers/gpu/drm/radeon/radeon_audio.c | 4 +- > > drivers/gpu/drm/radeon/radeon_combios.c| 12 ++-- > > drivers/gpu/drm/radeon/radeon_device.c | 19 ++ > > drivers/gpu/drm/radeon/radeon_display.c| 74 +++--- > > drivers/gpu/drm/radeon/radeon_drv.c| 27 +--- > > drivers/gpu/drm/radeon/radeon_drv.h| 1 - > > drivers/gpu/drm/radeon/radeon_fbdev.c | 26 > > drivers/gpu/drm/radeon/radeon_fence.c | 8 +-- > > drivers/gpu/drm/radeon/radeon_gem.c| 2 +- > > drivers/gpu/drm/radeon/radeon_i2c.c| 2 +- > > drivers/gpu/drm/radeon/radeon_ib.c | 2 +- > > drivers/gpu/drm/radeon/radeon_irq_kms.c| 12 ++-- > > drivers/gpu/drm/radeon/radeon_kms.c| 18 ++ > > drivers/gpu/drm/radeon/radeon_object.c | 2 +- > > drivers/gpu/drm/radeon/radeon_pm.c | 20 +++--- > > drivers/gpu/drm/radeon/radeon_ring.c | 2 +- > > drivers/gpu/drm/radeon/radeon_ttm.c| 6 +- > > drivers/gpu/drm/radeon/rs400.c | 6 +- > > drivers/gpu/drm/radeon/rs600.c | 14 ++-- > > drivers/gpu/drm/radeon/rs690.c | 2 +- > > drivers/gpu/drm/radeon/rv515.c | 4 +- > > drivers/gpu/drm/radeon/rv770.c | 2 +- > > drivers/gpu/drm/radeon/si.c| 4 +- > > 40 files changed, 193 insertions(+), 191 deletions(-) > > > > -- > -- > Thomas Zimmermann > Graphics Driver Developer > SUSE Software Solutions Germany GmbH > Frankenstrasse 146, 90461 Nuernberg, Germany > GF: Ivo Totev, Andrew Myers, Andrew McDonald, Boudien Moerman > HRB 36809 (AG Nuernberg) >
High Power Consumption of AMD RX6800xt in Idle with Secondary Monitor Connected
Dear AMD GPU Kernel Maintainers, I am writing to report an issue with high power consumption of my AMD RX6800xt graphics card when a secondary monitor is connected. Upon investigation, I observed that my desktop computer generates more heat while idling. I determined that the high power consumption issue arises when I connect a secondary monitor to my AMD RX6800xt card, causing it to consume approximately 40W of power in idle state . I checked the "GFX Clocks and Power:" in /sys/kernel/debug/dri/1/amdgpu_pm_info of my RX6800xt during idle, and here are the findings: With the secondary monitor connected memory frequency is up and constantly at 1000MHz: 1000 MHz (MCLK) 3 MHz (SCLK) 1825 MHz (PSTATE_SCLK) 1000 MHz (PSTATE_MCLK) 856 mV (VDDGFX) 45.00 W (average SoC) Single monitor connected: 96 MHz (MCLK) 0 MHz (SCLK) 1825 MHz (PSTATE_SCLK) 1000 MHz (PSTATE_MCLK) 6 mV (VDDGFX) 8.00 W (average SoC) The significant difference in power consumption between the two states indicates a potential issue in power management that needs to be addressed. Your assistance in resolving this matter would be greatly appreciated. Thank you for your attention to this issue. Best regards, Jaroslav Pulchart
[PATCH v3 6/6] drm/radeon: change drm_dev_alloc to devm_drm_dev_alloc
"drm_dev_alloc" is deprecated, in order to use the newer "devm_drm_dev_alloc",
the "drm_device" is stored inside "radeon_device", by changing
"rdev_to_drm(rdev)"
other functions still gain access to the member "drm_device". Also,
"devm_drm_dev_alloc"
is now allocating "radeon_device", allocation inside "radeon_driver_load_kms"
has to be
removed.
In "radeon_device_init", it originally assigned "rdev->dev" etc. However it is
already
done right after "devm_drm_dev_alloc" as you can see down below. It is better
remove them.
Signed-off-by: Wu Hoi Pok
---
drivers/gpu/drm/radeon/radeon.h| 4 ++--
drivers/gpu/drm/radeon/radeon_device.c | 3 ---
drivers/gpu/drm/radeon/radeon_drv.c| 12 +---
drivers/gpu/drm/radeon/radeon_kms.c| 8 +---
4 files changed, 12 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index ae35c102a487..fd8a4513025f 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -2297,7 +2297,7 @@ typedef void (*radeon_wreg_t)(struct radeon_device*,
uint32_t, uint32_t);
struct radeon_device {
struct device *dev;
- struct drm_device *ddev;
+ struct drm_device ddev;
struct pci_dev *pdev;
#ifdef __alpha__
struct pci_controller *hose;
@@ -2478,7 +2478,7 @@ void cik_mm_wdoorbell(struct radeon_device *rdev, u32
index, u32 v);
static inline struct drm_device *rdev_to_drm(struct radeon_device *rdev)
{
- return rdev->ddev;
+ return >ddev;
}
/*
diff --git a/drivers/gpu/drm/radeon/radeon_device.c
b/drivers/gpu/drm/radeon/radeon_device.c
index 32851632643d..554b236c2328 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -1285,9 +1285,6 @@ int radeon_device_init(struct radeon_device *rdev,
bool runtime = false;
rdev->shutdown = false;
- rdev->dev = >dev;
- rdev->ddev = ddev;
- rdev->pdev = pdev;
rdev->flags = flags;
rdev->family = flags & RADEON_FAMILY_MASK;
rdev->is_atom_bios = false;
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c
b/drivers/gpu/drm/radeon/radeon_drv.c
index 7b8aa8406751..f36aa71c57c7 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -260,6 +260,7 @@ static int radeon_pci_probe(struct pci_dev *pdev,
{
unsigned long flags = 0;
struct drm_device *ddev;
+ struct radeon_device *rdev;
int ret;
if (!ent)
@@ -300,9 +301,14 @@ static int radeon_pci_probe(struct pci_dev *pdev,
if (ret)
return ret;
- ddev = drm_dev_alloc(_driver, >dev);
- if (IS_ERR(ddev))
- return PTR_ERR(ddev);
+ rdev = devm_drm_dev_alloc(>dev, _driver, typeof(*rdev), ddev);
+ if (IS_ERR(rdev))
+ return PTR_ERR(rdev);
+
+ rdev->dev = >dev;
+ rdev->pdev = pdev;
+ ddev = rdev_to_drm(rdev);
+ ddev->dev_private = rdev;
ret = pci_enable_device(pdev);
if (ret)
diff --git a/drivers/gpu/drm/radeon/radeon_kms.c
b/drivers/gpu/drm/radeon/radeon_kms.c
index a16590c6247f..645e33bf7947 100644
--- a/drivers/gpu/drm/radeon/radeon_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_kms.c
@@ -104,15 +104,9 @@ void radeon_driver_unload_kms(struct drm_device *dev)
int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
{
struct pci_dev *pdev = to_pci_dev(dev->dev);
- struct radeon_device *rdev;
+ struct radeon_device *rdev = dev->dev_private;
int r, acpi_status;
- rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
- if (rdev == NULL) {
- return -ENOMEM;
- }
- dev->dev_private = (void *)rdev;
-
#ifdef __alpha__
rdev->hose = pdev->sysdata;
#endif
--
2.45.2
[PATCH v3 5/6] drm/radeon: change rdev->ddev to rdev_to_drm(rdev)
This patch changes the way "drm_device" is accessed. It uses "rdev_to_drm(rdev)"
instead of accessing the struct member directly.
Signed-off-by: Wu Hoi Pok
---
drivers/gpu/drm/radeon/atombios_encoders.c | 2 +-
drivers/gpu/drm/radeon/cik.c | 14 ++--
drivers/gpu/drm/radeon/dce6_afmt.c | 2 +-
drivers/gpu/drm/radeon/evergreen.c | 12 ++--
drivers/gpu/drm/radeon/ni.c| 2 +-
drivers/gpu/drm/radeon/r100.c | 24 +++
drivers/gpu/drm/radeon/r300.c | 6 +-
drivers/gpu/drm/radeon/r420.c | 6 +-
drivers/gpu/drm/radeon/r520.c | 2 +-
drivers/gpu/drm/radeon/r600.c | 12 ++--
drivers/gpu/drm/radeon/r600_cs.c | 2 +-
drivers/gpu/drm/radeon/r600_dpm.c | 4 +-
drivers/gpu/drm/radeon/r600_hdmi.c | 2 +-
drivers/gpu/drm/radeon/radeon_acpi.c | 10 +--
drivers/gpu/drm/radeon/radeon_agp.c| 2 +-
drivers/gpu/drm/radeon/radeon_atombios.c | 2 +-
drivers/gpu/drm/radeon/radeon_audio.c | 4 +-
drivers/gpu/drm/radeon/radeon_combios.c| 12 ++--
drivers/gpu/drm/radeon/radeon_device.c | 10 +--
drivers/gpu/drm/radeon/radeon_display.c| 74 +++---
drivers/gpu/drm/radeon/radeon_fbdev.c | 26
drivers/gpu/drm/radeon/radeon_fence.c | 8 +--
drivers/gpu/drm/radeon/radeon_gem.c| 2 +-
drivers/gpu/drm/radeon/radeon_i2c.c| 2 +-
drivers/gpu/drm/radeon/radeon_ib.c | 2 +-
drivers/gpu/drm/radeon/radeon_irq_kms.c| 12 ++--
drivers/gpu/drm/radeon/radeon_object.c | 2 +-
drivers/gpu/drm/radeon/radeon_pm.c | 20 +++---
drivers/gpu/drm/radeon/radeon_ring.c | 2 +-
drivers/gpu/drm/radeon/radeon_ttm.c| 6 +-
drivers/gpu/drm/radeon/rs400.c | 6 +-
drivers/gpu/drm/radeon/rs600.c | 14 ++--
drivers/gpu/drm/radeon/rs690.c | 2 +-
drivers/gpu/drm/radeon/rv515.c | 4 +-
drivers/gpu/drm/radeon/rv770.c | 2 +-
drivers/gpu/drm/radeon/si.c| 4 +-
36 files changed, 159 insertions(+), 159 deletions(-)
diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c
b/drivers/gpu/drm/radeon/atombios_encoders.c
index 03e6871b3065..c82e0fbc49b4 100644
--- a/drivers/gpu/drm/radeon/atombios_encoders.c
+++ b/drivers/gpu/drm/radeon/atombios_encoders.c
@@ -2179,7 +2179,7 @@ int radeon_atom_pick_dig_encoder(struct drm_encoder
*encoder, int fe_idx)
void
radeon_atom_encoder_init(struct radeon_device *rdev)
{
- struct drm_device *dev = rdev->ddev;
+ struct drm_device *dev = rdev_to_drm(rdev);
struct drm_encoder *encoder;
list_for_each_entry(encoder, >mode_config.encoder_list, head) {
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index b5e96a8fc2c1..11a492f21157 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -7585,7 +7585,7 @@ int cik_irq_process(struct radeon_device *rdev)
DRM_DEBUG("IH: IH event w/o asserted
irq bit?\n");
if (rdev->irq.crtc_vblank_int[0]) {
- drm_handle_vblank(rdev->ddev, 0);
+ drm_handle_vblank(rdev_to_drm(rdev), 0);
rdev->pm.vblank_sync = true;
wake_up(>irq.vblank_queue);
}
@@ -7615,7 +7615,7 @@ int cik_irq_process(struct radeon_device *rdev)
DRM_DEBUG("IH: IH event w/o asserted
irq bit?\n");
if (rdev->irq.crtc_vblank_int[1]) {
- drm_handle_vblank(rdev->ddev, 1);
+ drm_handle_vblank(rdev_to_drm(rdev), 1);
rdev->pm.vblank_sync = true;
wake_up(>irq.vblank_queue);
}
@@ -7645,7 +7645,7 @@ int cik_irq_process(struct radeon_device *rdev)
DRM_DEBUG("IH: IH event w/o asserted
irq bit?\n");
if (rdev->irq.crtc_vblank_int[2]) {
- drm_handle_vblank(rdev->ddev, 2);
+ drm_handle_vblank(rdev_to_drm(rdev), 2);
rdev->pm.vblank_sync = true;
wake_up(>irq.vblank_queue);
}
@@ -7675,7 +7675,7 @@ int cik_irq_process(struct radeon_device *rdev)
DRM_DEBUG("IH: IH event w/o asserted
irq bit?\n");
if (rdev->irq.crtc_vblank_int[3]) {
- drm_handle_vblank(rdev->ddev, 3);
+ drm_handle_vblank(rdev_to_drm(rdev), 3);
[PATCH v3 1/6] drm/radeon: change variable name "dev" to "ddev" for consistency
In the probe function of amdgpu, it uses "ddev" as the name of "struct
drm_device *",
so I suggest renaming it to be consistent.
Signed-off-by: Wu Hoi Pok
---
drivers/gpu/drm/radeon/radeon_drv.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c
b/drivers/gpu/drm/radeon/radeon_drv.c
index 7bf08164140e..739bb1da9dcc 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -259,7 +259,7 @@ static int radeon_pci_probe(struct pci_dev *pdev,
const struct pci_device_id *ent)
{
unsigned long flags = 0;
- struct drm_device *dev;
+ struct drm_device *ddev;
int ret;
if (!ent)
@@ -300,28 +300,28 @@ static int radeon_pci_probe(struct pci_dev *pdev,
if (ret)
return ret;
- dev = drm_dev_alloc(_driver, >dev);
- if (IS_ERR(dev))
- return PTR_ERR(dev);
+ ddev = drm_dev_alloc(_driver, >dev);
+ if (IS_ERR(ddev))
+ return PTR_ERR(ddev);
ret = pci_enable_device(pdev);
if (ret)
goto err_free;
- pci_set_drvdata(pdev, dev);
+ pci_set_drvdata(pdev, ddev);
- ret = drm_dev_register(dev, ent->driver_data);
+ ret = drm_dev_register(ddev, ent->driver_data);
if (ret)
goto err_agp;
- radeon_fbdev_setup(dev->dev_private);
+ radeon_fbdev_setup(ddev->dev_private);
return 0;
err_agp:
pci_disable_device(pdev);
err_free:
- drm_dev_put(dev);
+ drm_dev_put(ddev);
return ret;
}
--
2.45.2
[PATCH v3 2/6] drm/radeon: remove load callback from kms_driver
The ".load" callback in "struct drm_driver" is deprecated. In order to remove
the callback, we have to manually call "radeon_driver_load_kms" instead.
Signed-off-by: Wu Hoi Pok
---
drivers/gpu/drm/radeon/radeon_drv.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c
b/drivers/gpu/drm/radeon/radeon_drv.c
index 739bb1da9dcc..88d3de2a79f8 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -310,6 +310,10 @@ static int radeon_pci_probe(struct pci_dev *pdev,
pci_set_drvdata(pdev, ddev);
+ ret = radeon_driver_load_kms(ddev, flags);
+ if (ret)
+ goto err_agp;
+
ret = drm_dev_register(ddev, ent->driver_data);
if (ret)
goto err_agp;
@@ -569,7 +573,6 @@ static const struct drm_ioctl_desc radeon_ioctls_kms[] = {
static const struct drm_driver kms_driver = {
.driver_features =
DRIVER_GEM | DRIVER_RENDER | DRIVER_MODESET,
- .load = radeon_driver_load_kms,
.open = radeon_driver_open_kms,
.postclose = radeon_driver_postclose_kms,
.unload = radeon_driver_unload_kms,
--
2.45.2
[PATCH] drm/amd/display: Fix unsigned comparison with less than zero
The return value from the call to dml21_find_dc_pipes_for_plane() is int.
However, the return value is being assigned to an unsigned int variable
'num_pipes', the condition if(num_pipes <= 0) is not rigorous enough,
so making 'num_pipes' an int.
./drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c:318:6-15: WARNING:
Unsigned expression compared with zero: num_pipes <= 0.
./drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c:360:6-15: WARNING:
Unsigned expression compared with zero: num_pipes <= 0.
Reported-by: Abaci Robot
Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=9454
Signed-off-by: Jiapeng Chong
---
.../drm/amd/display/dc/dml2/dml21/dml21_wrapper.c | 15 ++-
1 file changed, 6 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c
b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c
index c310354cd5fc..9d96a31419fa 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c
@@ -280,7 +280,8 @@ bool dml21_validate(const struct dc *in_dc, struct dc_state
*context, struct dml
void dml21_prepare_mcache_programming(struct dc *in_dc, struct dc_state
*context, struct dml2_context *dml_ctx)
{
- unsigned int num_pipes, dml_prog_idx, dml_phantom_prog_idx,
dc_pipe_index;
+ unsigned int dml_prog_idx, dml_phantom_prog_idx, dc_pipe_index;
+ int num_pipes;
struct pipe_ctx *dc_main_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__];
struct pipe_ctx *dc_phantom_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__]
= {0};
@@ -314,10 +315,8 @@ void dml21_prepare_mcache_programming(struct dc *in_dc,
struct dc_state *context
}
num_pipes = dml21_find_dc_pipes_for_plane(in_dc, context,
dml_ctx, dc_main_pipes, dc_phantom_pipes, dml_prog_idx);
-
- if (num_pipes <= 0 ||
- dc_main_pipes[0]->stream == NULL ||
- dc_main_pipes[0]->plane_state == NULL)
+ if (num_pipes <= 0 || dc_main_pipes[0]->stream == NULL ||
+ dc_main_pipes[0]->plane_state == NULL)
continue;
/* get config for each pipe */
@@ -356,10 +355,8 @@ void dml21_prepare_mcache_programming(struct dc *in_dc,
struct dc_state *context
pln_prog =
_ctx->v21.mode_programming.programming->plane_programming[dml_prog_idx];
num_pipes = dml21_find_dc_pipes_for_plane(in_dc, context,
dml_ctx, dc_main_pipes, dc_phantom_pipes, dml_prog_idx);
-
- if (num_pipes <= 0 ||
- dc_main_pipes[0]->stream == NULL ||
- dc_main_pipes[0]->plane_state == NULL)
+ if (num_pipes <= 0 || dc_main_pipes[0]->stream == NULL ||
+ dc_main_pipes[0]->plane_state == NULL)
continue;
/* get config for each pipe */
--
2.20.1.7.g153144c
[PATCH v3 0/6] drm/radeon: remove load callback & drm_dev_alloc
.load and drm_dev_alloc are deprecated. These patch series aims to remove them. v3: Both v1 and v2 sucks. v3 improves greatly on readability. Wu Hoi Pok (6): drm/radeon: change variable name "dev" to "ddev" for consistency drm/radeon: remove load callback from kms_driver drm/radeon: use variable flags as parameter drm/radeon: add helper rdev_to_drm(rdev) drm/radeon: change rdev->ddev to rdev_to_drm(rdev) drm/radeon: change drm_dev_alloc to devm_drm_dev_alloc drivers/gpu/drm/radeon/atombios_encoders.c | 2 +- drivers/gpu/drm/radeon/cik.c | 14 ++-- drivers/gpu/drm/radeon/dce6_afmt.c | 2 +- drivers/gpu/drm/radeon/evergreen.c | 12 ++-- drivers/gpu/drm/radeon/ni.c| 2 +- drivers/gpu/drm/radeon/r100.c | 24 +++ drivers/gpu/drm/radeon/r300.c | 6 +- drivers/gpu/drm/radeon/r420.c | 6 +- drivers/gpu/drm/radeon/r520.c | 2 +- drivers/gpu/drm/radeon/r600.c | 12 ++-- drivers/gpu/drm/radeon/r600_cs.c | 2 +- drivers/gpu/drm/radeon/r600_dpm.c | 4 +- drivers/gpu/drm/radeon/r600_hdmi.c | 2 +- drivers/gpu/drm/radeon/radeon.h| 7 +- drivers/gpu/drm/radeon/radeon_acpi.c | 10 +-- drivers/gpu/drm/radeon/radeon_agp.c| 2 +- drivers/gpu/drm/radeon/radeon_atombios.c | 2 +- drivers/gpu/drm/radeon/radeon_audio.c | 4 +- drivers/gpu/drm/radeon/radeon_combios.c| 12 ++-- drivers/gpu/drm/radeon/radeon_device.c | 13 ++-- drivers/gpu/drm/radeon/radeon_display.c| 74 +++--- drivers/gpu/drm/radeon/radeon_drv.c| 27 +--- drivers/gpu/drm/radeon/radeon_fbdev.c | 26 drivers/gpu/drm/radeon/radeon_fence.c | 8 +-- drivers/gpu/drm/radeon/radeon_gem.c| 2 +- drivers/gpu/drm/radeon/radeon_i2c.c| 2 +- drivers/gpu/drm/radeon/radeon_ib.c | 2 +- drivers/gpu/drm/radeon/radeon_irq_kms.c| 12 ++-- drivers/gpu/drm/radeon/radeon_kms.c| 8 +-- drivers/gpu/drm/radeon/radeon_object.c | 2 +- drivers/gpu/drm/radeon/radeon_pm.c | 20 +++--- drivers/gpu/drm/radeon/radeon_ring.c | 2 +- drivers/gpu/drm/radeon/radeon_ttm.c| 6 +- drivers/gpu/drm/radeon/rs400.c | 6 +- drivers/gpu/drm/radeon/rs600.c | 14 ++-- drivers/gpu/drm/radeon/rs690.c | 2 +- drivers/gpu/drm/radeon/rv515.c | 4 +- drivers/gpu/drm/radeon/rv770.c | 2 +- drivers/gpu/drm/radeon/si.c| 4 +- 39 files changed, 184 insertions(+), 179 deletions(-) -- 2.45.2
[PATCH v3 4/6] drm/radeon: add helper rdev_to_drm(rdev)
Add helper rdev_to_drm(rdev), similar to amdgpu, most function should
access the "drm_device" with "rdev_to_drm(rdev)" instead, where amdgpu has
"adev_to_drm(adev)". It also makes changing from "*drm_device" to "drm_device"
in "radeon_devicce" later on easier.
Signed-off-by: Wu Hoi Pok
---
drivers/gpu/drm/radeon/radeon.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 0999c8eaae94..ae35c102a487 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -2476,6 +2476,11 @@ void r100_io_wreg(struct radeon_device *rdev, u32 reg,
u32 v);
u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
+static inline struct drm_device *rdev_to_drm(struct radeon_device *rdev)
+{
+ return rdev->ddev;
+}
+
/*
* Cast helper
*/
--
2.45.2
[PATCH v3 3/6] drm/radeon: use variable flags as parameter
To be consistent with amdgpu driver, use "flags" as the parameter because it is already assigned as "ent->driver_data". Signed-off-by: Wu Hoi Pok --- drivers/gpu/drm/radeon/radeon_drv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c index 88d3de2a79f8..7b8aa8406751 100644 --- a/drivers/gpu/drm/radeon/radeon_drv.c +++ b/drivers/gpu/drm/radeon/radeon_drv.c @@ -314,7 +314,7 @@ static int radeon_pci_probe(struct pci_dev *pdev, if (ret) goto err_agp; - ret = drm_dev_register(ddev, ent->driver_data); + ret = drm_dev_register(ddev, flags); if (ret) goto err_agp; -- 2.45.2
RE: [PATCH V2] drm/amdgpu: sysfs node disable query error count during gpu reset
[AMD Official Use Only - AMD Internal Distribution Only]
Hi Thomas,
I think we can optimize the amdgpu_ras_set_error_query_ready(adev, true)
function calling during GPU recovery,
amdgpu_ras_set_error_query_ready(tmp_adev, false) -> recovery start -> recovery
done -> amdgpu_ras_set_error_query_ready(tmp_adev, true),
above process can avoid access query error count during GPU recovery.
Regards,
Stanley
> -Original Message-
> From: Chai, Thomas
> Sent: Monday, July 1, 2024 11:19 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhang, Hawking ; Zhou1, Tao
> ; Li, Candice ; Wang,
> Yang(Kevin) ; Yang, Stanley
> ; Chai, Thomas
> Subject: [PATCH V2] drm/amdgpu: sysfs node disable query error count
> during gpu reset
>
> Sysfs node disable query error count during gpu reset.
>
> Signed-off-by: YiPeng Chai
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 15 +--
> 1 file changed, 13 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> index ac7ded01dad0..a65b5197b0fc 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> @@ -619,6 +619,7 @@ static const struct file_operations
> amdgpu_ras_debugfs_eeprom_ops = { static ssize_t
> amdgpu_ras_sysfs_read(struct device *dev,
> struct device_attribute *attr, char *buf) {
> + int ret;
> struct ras_manager *obj = container_of(attr, struct ras_manager,
> sysfs_attr);
> struct ras_query_if info = {
> .head = obj->head,
> @@ -627,7 +628,10 @@ static ssize_t amdgpu_ras_sysfs_read(struct device
> *dev,
> if (!amdgpu_ras_get_error_query_ready(obj->adev))
> return sysfs_emit(buf, "Query currently inaccessible\n");
>
> - if (amdgpu_ras_query_error_status(obj->adev, ))
> + ret = amdgpu_ras_query_error_status(obj->adev, );
> + if (ret == -EIO) /* gpu reset is ongoing */
> + return sysfs_emit(buf, "Query currently inaccessible\n");
> + else if (ret)
> return -EINVAL;
>
> if (amdgpu_ip_version(obj->adev, MP0_HWIP, 0) != IP_VERSION(11,
> 0, 2) && @@ -1290,12 +1294,19 @@ static int
> amdgpu_aca_log_ras_error_data(struct amdgpu_device *adev, enum amdgpu
> ssize_t amdgpu_ras_aca_sysfs_read(struct device *dev, struct device_attribute
> *attr,
> struct aca_handle *handle, char *buf, void
> *data) {
> + int ret;
> struct ras_manager *obj = container_of(handle, struct ras_manager,
> aca_handle);
> struct ras_query_if info = {
> .head = obj->head,
> };
>
> - if (amdgpu_ras_query_error_status(obj->adev, ))
> + if (!amdgpu_ras_get_error_query_ready(obj->adev))
> + return sysfs_emit(buf, "Query currently inaccessible\n");
> +
> + ret = amdgpu_ras_query_error_status(obj->adev, );
> + if (ret == -EIO) /* gpu reset is ongoing */
> + return sysfs_emit(buf, "Query currently inaccessible\n");
> + else if (ret)
> return -EINVAL;
>
> return sysfs_emit(buf, "%s: %lu\n%s: %lu\n%s: %lu\n", "ue",
> info.ue_count,
> --
> 2.34.1
